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author | rdivacky <rdivacky@FreeBSD.org> | 2009-10-14 17:57:32 +0000 |
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committer | rdivacky <rdivacky@FreeBSD.org> | 2009-10-14 17:57:32 +0000 |
commit | cd749a9c07f1de2fb8affde90537efa4bc3e7c54 (patch) | |
tree | b21f6de4e08b89bb7931806bab798fc2a5e3a686 /lib/Target/Sparc/SparcRegisterInfo.td | |
parent | 72621d11de5b873f1695f391eb95f0b336c3d2d4 (diff) | |
download | FreeBSD-src-cd749a9c07f1de2fb8affde90537efa4bc3e7c54.zip FreeBSD-src-cd749a9c07f1de2fb8affde90537efa4bc3e7c54.tar.gz |
Update llvm to r84119.
Diffstat (limited to 'lib/Target/Sparc/SparcRegisterInfo.td')
-rw-r--r-- | lib/Target/Sparc/SparcRegisterInfo.td | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/lib/Target/Sparc/SparcRegisterInfo.td b/lib/Target/Sparc/SparcRegisterInfo.td index e3a50ca..2b05c19 100644 --- a/lib/Target/Sparc/SparcRegisterInfo.td +++ b/lib/Target/Sparc/SparcRegisterInfo.td @@ -16,6 +16,10 @@ class SparcReg<string n> : Register<n> { let Namespace = "SP"; } +class SparcCtrlReg<string n>: Register<n> { + let Namespace = "SP"; +} + // Registers are identified with 5-bit ID numbers. // Ri - 32-bit integer registers class Ri<bits<5> num, string n> : SparcReg<n> { @@ -31,6 +35,10 @@ class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> { let SubRegs = subregs; } +// Control Registers +def ICC : SparcCtrlReg<"ICC">; +def FCC : SparcCtrlReg<"FCC">; + // Integer registers def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>; def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>; @@ -46,7 +54,7 @@ def O2 : Ri<10, "O2">, DwarfRegNum<[10]>; def O3 : Ri<11, "O3">, DwarfRegNum<[11]>; def O4 : Ri<12, "O4">, DwarfRegNum<[12]>; def O5 : Ri<13, "O5">, DwarfRegNum<[13]>; -def O6 : Ri<14, "O6">, DwarfRegNum<[14]>; +def O6 : Ri<14, "SP">, DwarfRegNum<[14]>; def O7 : Ri<15, "O7">, DwarfRegNum<[15]>; def L0 : Ri<16, "L0">, DwarfRegNum<[16]>; def L1 : Ri<17, "L1">, DwarfRegNum<[17]>; @@ -62,7 +70,7 @@ def I2 : Ri<26, "I2">, DwarfRegNum<[26]>; def I3 : Ri<27, "I3">, DwarfRegNum<[27]>; def I4 : Ri<28, "I4">, DwarfRegNum<[28]>; def I5 : Ri<29, "I5">, DwarfRegNum<[29]>; -def I6 : Ri<30, "I6">, DwarfRegNum<[30]>; +def I6 : Ri<30, "FP">, DwarfRegNum<[30]>; def I7 : Ri<31, "I7">, DwarfRegNum<[31]>; // Floating-point registers |