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author | dim <dim@FreeBSD.org> | 2011-02-20 12:57:14 +0000 |
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committer | dim <dim@FreeBSD.org> | 2011-02-20 12:57:14 +0000 |
commit | cbb70ce070d220642b038ea101d9c0f9fbf860d6 (patch) | |
tree | d2b61ce94e654cb01a254d2195259db5f9cc3f3c /lib/Target/MBlaze/TODO | |
parent | 4ace901e87dac5bbbac78ed325e75462e48e386e (diff) | |
download | FreeBSD-src-cbb70ce070d220642b038ea101d9c0f9fbf860d6.zip FreeBSD-src-cbb70ce070d220642b038ea101d9c0f9fbf860d6.tar.gz |
Vendor import of llvm trunk r126079:
http://llvm.org/svn/llvm-project/llvm/trunk@126079
Diffstat (limited to 'lib/Target/MBlaze/TODO')
-rw-r--r-- | lib/Target/MBlaze/TODO | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/lib/Target/MBlaze/TODO b/lib/Target/MBlaze/TODO new file mode 100644 index 0000000..2e613eb --- /dev/null +++ b/lib/Target/MBlaze/TODO @@ -0,0 +1,26 @@ +* Writing out ELF files is close to working but the following needs to + be examined more closely: + - Relocations use 2-byte / 4-byte to terminology in reference to + the size of the immediate value being changed. The Xilinx + terminology seems to be (???) 4-byte / 8-byte in reference + to the number of bytes of instructions that are being changed. + +* Code generation seems to work relatively well now but the following + needs to be examined more closely: + - The stack layout needs to be examined to make sure it meets + the standard, especially in regards to var arg functions. + - The processor itineraries are copied from a different backend + and need to be updated to model the MicroBlaze correctly. + - Look at the MBlazeGenFastISel.inc stuff and make use of it + if appropriate. + +* A basic assembly parser is present now and seems to parse most things. + There are a few things that need to be looked at: + - There are some instructions that are not generated by the backend + and have not been tested as far as the parser is concerned. + - The assembly parser does not use any MicroBlaze specific directives. + I should investigate if there are MicroBlaze specific directive and, + if there are, add them. + - The instruction MFS and MTS use special names for some of the + special registers that can be accessed. These special register + names should be parsed by the assembly parser. |