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author | rdivacky <rdivacky@FreeBSD.org> | 2010-01-23 11:09:33 +0000 |
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committer | rdivacky <rdivacky@FreeBSD.org> | 2010-01-23 11:09:33 +0000 |
commit | 3fd58f91dd318518f7daa4ba64c0aaf31799d89b (patch) | |
tree | 74eecbae571601ec6a626a53374b1eddc7b164a5 /lib/Target/ARM/Thumb2InstrInfo.cpp | |
parent | 3fba7d16b41dfbefe3b1be6bc0ab94c017728f79 (diff) | |
download | FreeBSD-src-3fd58f91dd318518f7daa4ba64c0aaf31799d89b.zip FreeBSD-src-3fd58f91dd318518f7daa4ba64c0aaf31799d89b.tar.gz |
Update LLVM to r94309.
Diffstat (limited to 'lib/Target/ARM/Thumb2InstrInfo.cpp')
-rw-r--r-- | lib/Target/ARM/Thumb2InstrInfo.cpp | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/lib/Target/ARM/Thumb2InstrInfo.cpp b/lib/Target/ARM/Thumb2InstrInfo.cpp index f4a8c27..387edaf 100644 --- a/lib/Target/ARM/Thumb2InstrInfo.cpp +++ b/lib/Target/ARM/Thumb2InstrInfo.cpp @@ -329,12 +329,16 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Offset += MI.getOperand(FrameRegIdx+1).getImm(); bool isSP = FrameReg == ARM::SP; - if (Offset == 0) { + unsigned PredReg; + if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) { // Turn it into a move. MI.setDesc(TII.get(ARM::tMOVgpr2gpr)); MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); - MI.RemoveOperand(FrameRegIdx+1); - Offset = 0; + // Remove offset and remaining explicit predicate operands. + do MI.RemoveOperand(FrameRegIdx+1); + while (MI.getNumOperands() > FrameRegIdx+1 && + (!MI.getOperand(FrameRegIdx+1).isReg() || + !MI.getOperand(FrameRegIdx+1).isImm())); return true; } |