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| author | ed <ed@FreeBSD.org> | 2009-06-14 09:23:33 +0000 |
|---|---|---|
| committer | ed <ed@FreeBSD.org> | 2009-06-14 09:23:33 +0000 |
| commit | db89e312d968c258aba3c79c1c398f5fb19267a3 (patch) | |
| tree | 49817b316c4fdaa56d9d16ebf2555303d1a990e0 /lib/Target/ARM/ARMISelLowering.cpp | |
| parent | de000e339094f8c6e06a635dac9a803861416ec6 (diff) | |
| download | FreeBSD-src-db89e312d968c258aba3c79c1c398f5fb19267a3.zip FreeBSD-src-db89e312d968c258aba3c79c1c398f5fb19267a3.tar.gz | |
Import LLVM r73340.
Diffstat (limited to 'lib/Target/ARM/ARMISelLowering.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMISelLowering.cpp | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index c0fd9dc..ec8bd1f 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -1101,7 +1101,12 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) { else RC = ARM::GPRRegisterClass; - if (RegVT == MVT::f64) { + if (FloatABIType == FloatABI::Hard) { + if (RegVT == MVT::f32) + RC = ARM::SPRRegisterClass; + else if (RegVT == MVT::f64) + RC = ARM::DPRRegisterClass; + } else if (RegVT == MVT::f64) { // f64 is passed in pairs of GPRs and must be combined. RegVT = MVT::i32; } else if (!((RegVT == MVT::i32) || (RegVT == MVT::f32))) |
