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| author | rdivacky <rdivacky@FreeBSD.org> | 2010-03-10 17:45:15 +0000 |
|---|---|---|
| committer | rdivacky <rdivacky@FreeBSD.org> | 2010-03-10 17:45:15 +0000 |
| commit | 9e2446b38c94db61b2416c28fee415c03663c11c (patch) | |
| tree | 231646bba785a129b3a2d409badb74e7ccd1594c /lib/Target/ARM/ARMCodeEmitter.cpp | |
| parent | 9bef28eb9e224d641ce31a423e215ccf82bf1d43 (diff) | |
| download | FreeBSD-src-9e2446b38c94db61b2416c28fee415c03663c11c.zip FreeBSD-src-9e2446b38c94db61b2416c28fee415c03663c11c.tar.gz | |
Update LLVM to r98164.
Diffstat (limited to 'lib/Target/ARM/ARMCodeEmitter.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMCodeEmitter.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp index bd703f4..108a244 100644 --- a/lib/Target/ARM/ARMCodeEmitter.cpp +++ b/lib/Target/ARM/ARMCodeEmitter.cpp @@ -1138,7 +1138,7 @@ void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) { // Set the conditional execution predicate Binary |= II->getPredicate(&MI) << ARMII::CondShift; - if (TID.Opcode == ARM::BX_RET) + if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR) // The return register is LR. Binary |= ARMRegisterInfo::getRegisterNumbering(ARM::LR); else |
