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authorrdivacky <rdivacky@FreeBSD.org>2009-10-14 17:57:32 +0000
committerrdivacky <rdivacky@FreeBSD.org>2009-10-14 17:57:32 +0000
commitcd749a9c07f1de2fb8affde90537efa4bc3e7c54 (patch)
treeb21f6de4e08b89bb7931806bab798fc2a5e3a686 /lib/CodeGen/Spiller.cpp
parent72621d11de5b873f1695f391eb95f0b336c3d2d4 (diff)
downloadFreeBSD-src-cd749a9c07f1de2fb8affde90537efa4bc3e7c54.zip
FreeBSD-src-cd749a9c07f1de2fb8affde90537efa4bc3e7c54.tar.gz
Update llvm to r84119.
Diffstat (limited to 'lib/CodeGen/Spiller.cpp')
-rw-r--r--lib/CodeGen/Spiller.cpp95
1 files changed, 47 insertions, 48 deletions
diff --git a/lib/CodeGen/Spiller.cpp b/lib/CodeGen/Spiller.cpp
index 405cd80..0277d64 100644
--- a/lib/CodeGen/Spiller.cpp
+++ b/lib/CodeGen/Spiller.cpp
@@ -13,12 +13,13 @@
#include "VirtRegMap.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/LiveStackAnalysis.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
using namespace llvm;
@@ -50,13 +51,13 @@ protected:
/// Ensures there is space before the given machine instruction, returns the
/// instruction's new number.
- unsigned makeSpaceBefore(MachineInstr *mi) {
+ LiveIndex makeSpaceBefore(MachineInstr *mi) {
if (!lis->hasGapBeforeInstr(lis->getInstructionIndex(mi))) {
lis->scaleNumbering(2);
ls->scaleNumbering(2);
}
- unsigned miIdx = lis->getInstructionIndex(mi);
+ LiveIndex miIdx = lis->getInstructionIndex(mi);
assert(lis->hasGapBeforeInstr(miIdx));
@@ -65,13 +66,13 @@ protected:
/// Ensure there is space after the given machine instruction, returns the
/// instruction's new number.
- unsigned makeSpaceAfter(MachineInstr *mi) {
+ LiveIndex makeSpaceAfter(MachineInstr *mi) {
if (!lis->hasGapAfterInstr(lis->getInstructionIndex(mi))) {
lis->scaleNumbering(2);
ls->scaleNumbering(2);
}
- unsigned miIdx = lis->getInstructionIndex(mi);
+ LiveIndex miIdx = lis->getInstructionIndex(mi);
assert(lis->hasGapAfterInstr(miIdx));
@@ -82,19 +83,19 @@ protected:
/// after the given instruction. Returns the base index of the inserted
/// instruction. The caller is responsible for adding an appropriate
/// LiveInterval to the LiveIntervals analysis.
- unsigned insertStoreAfter(MachineInstr *mi, unsigned ss,
- unsigned vreg,
- const TargetRegisterClass *trc) {
+ LiveIndex insertStoreAfter(MachineInstr *mi, unsigned ss,
+ unsigned vreg,
+ const TargetRegisterClass *trc) {
MachineBasicBlock::iterator nextInstItr(next(mi));
- unsigned miIdx = makeSpaceAfter(mi);
+ LiveIndex miIdx = makeSpaceAfter(mi);
tii->storeRegToStackSlot(*mi->getParent(), nextInstItr, vreg,
true, ss, trc);
MachineBasicBlock::iterator storeInstItr(next(mi));
MachineInstr *storeInst = &*storeInstItr;
- unsigned storeInstIdx = miIdx + LiveInterval::InstrSlots::NUM;
+ LiveIndex storeInstIdx = lis->getNextIndex(miIdx);
assert(lis->getInstructionFromIndex(storeInstIdx) == 0 &&
"Store inst index already in use.");
@@ -107,15 +108,15 @@ protected:
/// Insert a store of the given vreg to the given stack slot immediately
/// before the given instructnion. Returns the base index of the inserted
/// Instruction.
- unsigned insertStoreBefore(MachineInstr *mi, unsigned ss,
- unsigned vreg,
- const TargetRegisterClass *trc) {
- unsigned miIdx = makeSpaceBefore(mi);
+ LiveIndex insertStoreBefore(MachineInstr *mi, unsigned ss,
+ unsigned vreg,
+ const TargetRegisterClass *trc) {
+ LiveIndex miIdx = makeSpaceBefore(mi);
tii->storeRegToStackSlot(*mi->getParent(), mi, vreg, true, ss, trc);
MachineBasicBlock::iterator storeInstItr(prior(mi));
MachineInstr *storeInst = &*storeInstItr;
- unsigned storeInstIdx = miIdx - LiveInterval::InstrSlots::NUM;
+ LiveIndex storeInstIdx = lis->getPrevIndex(miIdx);
assert(lis->getInstructionFromIndex(storeInstIdx) == 0 &&
"Store inst index already in use.");
@@ -130,14 +131,15 @@ protected:
unsigned vreg,
const TargetRegisterClass *trc) {
- unsigned storeInstIdx = insertStoreAfter(mi, ss, vreg, trc);
- unsigned start = lis->getDefIndex(lis->getInstructionIndex(mi)),
- end = lis->getUseIndex(storeInstIdx);
+ LiveIndex storeInstIdx = insertStoreAfter(mi, ss, vreg, trc);
+ LiveIndex start = lis->getDefIndex(lis->getInstructionIndex(mi)),
+ end = lis->getUseIndex(storeInstIdx);
VNInfo *vni =
li->getNextValue(storeInstIdx, 0, true, lis->getVNInfoAllocator());
- vni->kills.push_back(storeInstIdx);
- DOUT << " Inserting store range: [" << start << ", " << end << ")\n";
+ vni->addKill(storeInstIdx);
+ DEBUG(errs() << " Inserting store range: [" << start
+ << ", " << end << ")\n");
LiveRange lr(start, end, vni);
li->addRange(lr);
@@ -147,18 +149,18 @@ protected:
/// after the given instruction. Returns the base index of the inserted
/// instruction. The caller is responsibel for adding/removing an appropriate
/// range vreg's LiveInterval.
- unsigned insertLoadAfter(MachineInstr *mi, unsigned ss,
- unsigned vreg,
- const TargetRegisterClass *trc) {
+ LiveIndex insertLoadAfter(MachineInstr *mi, unsigned ss,
+ unsigned vreg,
+ const TargetRegisterClass *trc) {
MachineBasicBlock::iterator nextInstItr(next(mi));
- unsigned miIdx = makeSpaceAfter(mi);
+ LiveIndex miIdx = makeSpaceAfter(mi);
tii->loadRegFromStackSlot(*mi->getParent(), nextInstItr, vreg, ss, trc);
MachineBasicBlock::iterator loadInstItr(next(mi));
MachineInstr *loadInst = &*loadInstItr;
- unsigned loadInstIdx = miIdx + LiveInterval::InstrSlots::NUM;
+ LiveIndex loadInstIdx = lis->getNextIndex(miIdx);
assert(lis->getInstructionFromIndex(loadInstIdx) == 0 &&
"Store inst index already in use.");
@@ -172,15 +174,15 @@ protected:
/// before the given instruction. Returns the base index of the inserted
/// instruction. The caller is responsible for adding an appropriate
/// LiveInterval to the LiveIntervals analysis.
- unsigned insertLoadBefore(MachineInstr *mi, unsigned ss,
- unsigned vreg,
- const TargetRegisterClass *trc) {
- unsigned miIdx = makeSpaceBefore(mi);
+ LiveIndex insertLoadBefore(MachineInstr *mi, unsigned ss,
+ unsigned vreg,
+ const TargetRegisterClass *trc) {
+ LiveIndex miIdx = makeSpaceBefore(mi);
tii->loadRegFromStackSlot(*mi->getParent(), mi, vreg, ss, trc);
MachineBasicBlock::iterator loadInstItr(prior(mi));
MachineInstr *loadInst = &*loadInstItr;
- unsigned loadInstIdx = miIdx - LiveInterval::InstrSlots::NUM;
+ LiveIndex loadInstIdx = lis->getPrevIndex(miIdx);
assert(lis->getInstructionFromIndex(loadInstIdx) == 0 &&
"Load inst index already in use.");
@@ -195,14 +197,15 @@ protected:
unsigned vreg,
const TargetRegisterClass *trc) {
- unsigned loadInstIdx = insertLoadBefore(mi, ss, vreg, trc);
- unsigned start = lis->getDefIndex(loadInstIdx),
- end = lis->getUseIndex(lis->getInstructionIndex(mi));
+ LiveIndex loadInstIdx = insertLoadBefore(mi, ss, vreg, trc);
+ LiveIndex start = lis->getDefIndex(loadInstIdx),
+ end = lis->getUseIndex(lis->getInstructionIndex(mi));
VNInfo *vni =
li->getNextValue(loadInstIdx, 0, true, lis->getVNInfoAllocator());
- vni->kills.push_back(lis->getInstructionIndex(mi));
- DOUT << " Intserting load range: [" << start << ", " << end << ")\n";
+ vni->addKill(lis->getInstructionIndex(mi));
+ DEBUG(errs() << " Intserting load range: [" << start
+ << ", " << end << ")\n");
LiveRange lr(start, end, vni);
li->addRange(lr);
@@ -214,7 +217,7 @@ protected:
/// immediately before each use, and stores after each def. No folding is
/// attempted.
std::vector<LiveInterval*> trivialSpillEverywhere(LiveInterval *li) {
- DOUT << "Spilling everywhere " << *li << "\n";
+ DEBUG(errs() << "Spilling everywhere " << *li << "\n");
assert(li->weight != HUGE_VALF &&
"Attempting to spill already spilled value.");
@@ -222,7 +225,7 @@ protected:
assert(!li->isStackSlot() &&
"Trying to spill a stack slot.");
- DOUT << "Trivial spill everywhere of reg" << li->reg << "\n";
+ DEBUG(errs() << "Trivial spill everywhere of reg" << li->reg << "\n");
std::vector<LiveInterval*> added;
@@ -234,7 +237,7 @@ protected:
MachineInstr *mi = &*regItr;
- DOUT << " Processing " << *mi;
+ DEBUG(errs() << " Processing " << *mi);
do {
++regItr;
@@ -318,23 +321,21 @@ public:
vrm->assignVirt2StackSlot(li->reg, ss);
MachineInstr *mi = 0;
- unsigned storeIdx = 0;
+ LiveIndex storeIdx = LiveIndex();
if (valno->isDefAccurate()) {
// If we have an accurate def we can just grab an iterator to the instr
// after the def.
mi = lis->getInstructionFromIndex(valno->def);
- storeIdx = insertStoreAfter(mi, ss, li->reg, trc) +
- LiveInterval::InstrSlots::DEF;
+ storeIdx = lis->getDefIndex(insertStoreAfter(mi, ss, li->reg, trc));
} else {
// if we get here we have a PHI def.
mi = &lis->getMBBFromIndex(valno->def)->front();
- storeIdx = insertStoreBefore(mi, ss, li->reg, trc) +
- LiveInterval::InstrSlots::DEF;
+ storeIdx = lis->getDefIndex(insertStoreBefore(mi, ss, li->reg, trc));
}
MachineBasicBlock *defBlock = mi->getParent();
- unsigned loadIdx = 0;
+ LiveIndex loadIdx = LiveIndex();
// Now we need to find the load...
MachineBasicBlock::iterator useItr(mi);
@@ -342,13 +343,11 @@ public:
if (useItr != defBlock->end()) {
MachineInstr *loadInst = useItr;
- loadIdx = insertLoadBefore(loadInst, ss, li->reg, trc) +
- LiveInterval::InstrSlots::USE;
+ loadIdx = lis->getUseIndex(insertLoadBefore(loadInst, ss, li->reg, trc));
}
else {
MachineInstr *loadInst = &defBlock->back();
- loadIdx = insertLoadAfter(loadInst, ss, li->reg, trc) +
- LiveInterval::InstrSlots::USE;
+ loadIdx = lis->getUseIndex(insertLoadAfter(loadInst, ss, li->reg, trc));
}
li->removeRange(storeIdx, loadIdx, true);
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