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| author | dim <dim@FreeBSD.org> | 2012-05-03 16:50:55 +0000 |
|---|---|---|
| committer | dim <dim@FreeBSD.org> | 2012-05-03 16:50:55 +0000 |
| commit | 2c5e9d71aba3b1a85f07c08d2c09d40b8547264b (patch) | |
| tree | 8575c732129e272992ac5d7b4c2519238fff4735 /lib/CodeGen/SelectionDAG/TargetLowering.cpp | |
| parent | 1fc08f5e9ef733ef1ce6f363fecedc2260e78974 (diff) | |
| download | FreeBSD-src-2c5e9d71aba3b1a85f07c08d2c09d40b8547264b.zip FreeBSD-src-2c5e9d71aba3b1a85f07c08d2c09d40b8547264b.tar.gz | |
Vendor import of llvm release_31 branch r155985:
http://llvm.org/svn/llvm-project/llvm/branches/release_31@155985
Diffstat (limited to 'lib/CodeGen/SelectionDAG/TargetLowering.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/TargetLowering.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 09a2b1f..e341e15 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -1367,8 +1367,9 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, // bits on that side are also known to be set on the other side, turn this // into an AND, as we know the bits will be cleared. // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 - if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known - if ((KnownOne & KnownOne2) == KnownOne) { + // NB: it is okay if more bits are known than are requested + if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side + if (KnownOne == KnownOne2) { // set bits are the same on both sides EVT VT = Op.getValueType(); SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, |
