Vendor import of llvm release_30 branch r142614:

http://llvm.org/svn/llvm-project/llvm/branches/release_30@142614

17 files changed, 382 insertions, 1988 deletions

diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td
index 018ccbd..aa9a4f5 100644
--- a/include/llvm/Target/Target.td
+++ b/include/llvm/Target/Target.td
@@ -297,6 +297,10 @@ class Instruction {
   // from the opcode.
   int Size = 0;
 
+  // DecoderNamespace - The "namespace" in which this instruction exists, on
+  // targets like ARM which multiple ISA namespaces exist.
+  string DecoderNamespace = "";
+
   // Code size, for instruction selection.
   // FIXME: What does this actually mean?
   int CodeSize = 0;
@@ -324,6 +328,7 @@ class Instruction {
   bit isPredicable = 0;     // Is this instruction predicable?
   bit hasDelaySlot = 0;     // Does this instruction have an delay slot?
   bit usesCustomInserter = 0; // Pseudo instr needing special help.
+  bit hasPostISelHook = 0;  // To be *adjusted* after isel by target hook.
   bit hasCtrlDep   = 0;     // Does this instruction r/w ctrl-flow chains?
   bit isNotDuplicable = 0;  // Is it unsafe to duplicate this instruction?
   bit isAsCheapAsAMove = 0; // As cheap (or cheaper) than a move instruction.
@@ -581,7 +586,7 @@ class InstrInfo {
 // Standard Pseudo Instructions.
 // This list must match TargetOpcodes.h and CodeGenTarget.cpp.
 // Only these instructions are allowed in the TargetOpcode namespace.
-let isCodeGenOnly = 1, Namespace = "TargetOpcode" in {
+let isCodeGenOnly = 1, isPseudo = 1, Namespace = "TargetOpcode" in {
 def PHI : Instruction {
   let OutOperandList = (outs);
   let InOperandList = (ins variable_ops);
diff --git a/include/llvm/Target/TargetAsmBackend.h b/include/llvm/Target/TargetAsmBackend.h
deleted file mode 100644
index 2111f6b..0000000
--- a/include/llvm/Target/TargetAsmBackend.h
+++ /dev/null
@@ -1,131 +0,0 @@
-//===-- llvm/Target/TargetAsmBackend.h - Target Asm Backend -----*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_TARGETASMBACKEND_H
-#define LLVM_TARGET_TARGETASMBACKEND_H
-
-#include "llvm/MC/MCDirectives.h"
-#include "llvm/MC/MCFixup.h"
-#include "llvm/MC/MCFixupKindInfo.h"
-#include "llvm/Support/DataTypes.h"
-
-namespace llvm {
-class MCELFObjectTargetWriter;
-class MCFixup;
-class MCInst;
-class MCObjectWriter;
-class MCSection;
-template<typename T>
-class SmallVectorImpl;
-class raw_ostream;
-
-/// TargetAsmBackend - Generic interface to target specific assembler backends.
-class TargetAsmBackend {
-  TargetAsmBackend(const TargetAsmBackend &);   // DO NOT IMPLEMENT
-  void operator=(const TargetAsmBackend &);  // DO NOT IMPLEMENT
-protected: // Can only create subclasses.
-  TargetAsmBackend();
-
-  unsigned HasReliableSymbolDifference : 1;
-
-public:
-  virtual ~TargetAsmBackend();
-
-  /// createObjectWriter - Create a new MCObjectWriter instance for use by the
-  /// assembler backend to emit the final object file.
-  virtual MCObjectWriter *createObjectWriter(raw_ostream &OS) const = 0;
-
-  /// createELFObjectTargetWriter - Create a new ELFObjectTargetWriter to enable
-  /// non-standard ELFObjectWriters.
-  virtual  MCELFObjectTargetWriter *createELFObjectTargetWriter() const {
-    assert(0 && "createELFObjectTargetWriter is not supported by asm backend");
-    return 0;
-  }
-
-  /// hasReliableSymbolDifference - Check whether this target implements
-  /// accurate relocations for differences between symbols. If not, differences
-  /// between symbols will always be relocatable expressions and any references
-  /// to temporary symbols will be assumed to be in the same atom, unless they
-  /// reside in a different section.
-  ///
-  /// This should always be true (since it results in fewer relocations with no
-  /// loss of functionality), but is currently supported as a way to maintain
-  /// exact object compatibility with Darwin 'as' (on non-x86_64). It should
-  /// eventually should be eliminated.
-  bool hasReliableSymbolDifference() const {
-    return HasReliableSymbolDifference;
-  }
-
-  /// doesSectionRequireSymbols - Check whether the given section requires that
-  /// all symbols (even temporaries) have symbol table entries.
-  virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
-    return false;
-  }
-
-  /// isSectionAtomizable - Check whether the given section can be split into
-  /// atoms.
-  ///
-  /// \see MCAssembler::isSymbolLinkerVisible().
-  virtual bool isSectionAtomizable(const MCSection &Section) const {
-    return true;
-  }
-
-  /// @name Target Fixup Interfaces
-  /// @{
-
-  /// getNumFixupKinds - Get the number of target specific fixup kinds.
-  virtual unsigned getNumFixupKinds() const = 0;
-
-  /// getFixupKindInfo - Get information on a fixup kind.
-  virtual const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const;
-
-  /// @}
-
-  /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
-  /// data fragment, at the offset specified by the fixup and following the
-  /// fixup kind as appropriate.
-  virtual void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
-                          uint64_t Value) const = 0;
-
-  /// @}
-
-  /// @name Target Relaxation Interfaces
-  /// @{
-
-  /// MayNeedRelaxation - Check whether the given instruction may need
-  /// relaxation.
-  ///
-  /// \param Inst - The instruction to test.
-  virtual bool MayNeedRelaxation(const MCInst &Inst) const = 0;
-
-  /// RelaxInstruction - Relax the instruction in the given fragment to the next
-  /// wider instruction.
-  ///
-  /// \param Inst - The instruction to relax, which may be the same as the
-  /// output.
-  /// \parm Res [output] - On return, the relaxed instruction.
-  virtual void RelaxInstruction(const MCInst &Inst, MCInst &Res) const = 0;
-
-  /// @}
-
-  /// WriteNopData - Write an (optimal) nop sequence of Count bytes to the given
-  /// output. If the target cannot generate such a sequence, it should return an
-  /// error.
-  ///
-  /// \return - True on success.
-  virtual bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const = 0;
-
-  /// HandleAssemblerFlag - Handle any target-specific assembler flags.
-  /// By default, do nothing.
-  virtual void HandleAssemblerFlag(MCAssemblerFlag Flag) {}
-};
-
-} // End llvm namespace
-
-#endif
diff --git a/include/llvm/Target/TargetAsmInfo.h b/include/llvm/Target/TargetAsmInfo.h
deleted file mode 100644
index 5a526dc..0000000
--- a/include/llvm/Target/TargetAsmInfo.h
+++ /dev/null
@@ -1,103 +0,0 @@
-//===-- llvm/Target/TargetAsmInfo.h -----------------------------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// Interface to provide the information necessary for producing assembly files.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_TARGETASMINFO_H
-#define LLVM_TARGET_TARGETASMINFO_H
-
-#include "llvm/CodeGen/MachineLocation.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
-#include "llvm/Target/TargetFrameLowering.h"
-#include "llvm/Target/TargetRegisterInfo.h"
-
-namespace llvm {
-  template <typename T> class ArrayRef;
-  class MCSection;
-  class MCContext;
-  class MachineFunction;
-  class TargetMachine;
-  class TargetLoweringObjectFile;
-
-class TargetAsmInfo {
-  std::vector<MachineMove> InitialFrameState;
-  const TargetRegisterInfo *TRI;
-  const TargetFrameLowering *TFI;
-  const TargetLoweringObjectFile *TLOF;
-
-public:
-  explicit TargetAsmInfo(const TargetMachine &TM);
-
-  const MCSection *getDwarfLineSection() const {
-    return TLOF->getDwarfLineSection();
-  }
-
-  const MCSection *getEHFrameSection() const {
-    return TLOF->getEHFrameSection();
-  }
-
-  const MCSection *getCompactUnwindSection() const {
-    return TLOF->getCompactUnwindSection();
-  }
-
-  const MCSection *getDwarfFrameSection() const {
-    return TLOF->getDwarfFrameSection();
-  }
-
-  const MCSection *getWin64EHFuncTableSection(StringRef Suffix) const {
-    return TLOF->getWin64EHFuncTableSection(Suffix);
-  }
-
-  const MCSection *getWin64EHTableSection(StringRef Suffix) const {
-    return TLOF->getWin64EHTableSection(Suffix);
-  }
-
-  unsigned getFDEEncoding(bool CFI) const {
-    return TLOF->getFDEEncoding(CFI);
-  }
-
-  bool isFunctionEHFrameSymbolPrivate() const {
-    return TLOF->isFunctionEHFrameSymbolPrivate();
-  }
-
-  int getCompactUnwindEncoding(ArrayRef<MCCFIInstruction> Instrs,
-                               int DataAlignmentFactor,
-                               bool IsEH) const {
-    return TFI->getCompactUnwindEncoding(Instrs, DataAlignmentFactor, IsEH);
-  }
-
-  const unsigned *getCalleeSavedRegs(MachineFunction *MF = 0) const {
-    return TRI->getCalleeSavedRegs(MF);
-  }
-
-  unsigned getDwarfRARegNum(bool isEH) const {
-    return TRI->getDwarfRegNum(TRI->getRARegister(), isEH);
-  }
-
-  const std::vector<MachineMove> &getInitialFrameState() const {
-    return InitialFrameState;
-  }
-
-  int getDwarfRegNum(unsigned RegNum, bool isEH) const {
-    return TRI->getDwarfRegNum(RegNum, isEH);
-  }
-
-  int getLLVMRegNum(unsigned DwarfRegNum, bool isEH) const {
-    return TRI->getLLVMRegNum(DwarfRegNum, isEH);
-  }
-
-  int getSEHRegNum(unsigned RegNum) const {
-    return TRI->getSEHRegNum(RegNum);
-  }
-};
-
-}
-#endif
diff --git a/include/llvm/Target/TargetAsmLexer.h b/include/llvm/Target/TargetAsmLexer.h
deleted file mode 100644
index 9fcf449..0000000
--- a/include/llvm/Target/TargetAsmLexer.h
+++ /dev/null
@@ -1,89 +0,0 @@
-//===-- llvm/Target/TargetAsmLexer.h - Target Assembly Lexer ----*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_TARGETASMLEXER_H
-#define LLVM_TARGET_TARGETASMLEXER_H
-
-#include "llvm/MC/MCParser/MCAsmLexer.h"
-
-namespace llvm {
-class Target;
-  
-/// TargetAsmLexer - Generic interface to target specific assembly lexers.
-class TargetAsmLexer {
-  /// The current token
-  AsmToken CurTok;
-  
-  /// The location and description of the current error
-  SMLoc ErrLoc;
-  std::string Err;
-  
-  TargetAsmLexer(const TargetAsmLexer &);   // DO NOT IMPLEMENT
-  void operator=(const TargetAsmLexer &);  // DO NOT IMPLEMENT
-protected: // Can only create subclasses.
-  TargetAsmLexer(const Target &);
-  
-  virtual AsmToken LexToken() = 0;
-  
-  void SetError(const SMLoc &errLoc, const std::string &err) {
-    ErrLoc = errLoc;
-    Err = err;
-  }
-  
-  /// TheTarget - The Target that this machine was created for.
-  const Target &TheTarget;
-  MCAsmLexer *Lexer;
-  
-public:
-  virtual ~TargetAsmLexer();
-  
-  const Target &getTarget() const { return TheTarget; }
-  
-  /// InstallLexer - Set the lexer to get tokens from lower-level lexer \arg L.
-  void InstallLexer(MCAsmLexer &L) {
-    Lexer = &L;
-  }
-  
-  MCAsmLexer *getLexer() {
-    return Lexer;
-  }
-  
-  /// Lex - Consume the next token from the input stream and return it.
-  const AsmToken &Lex() {
-    return CurTok = LexToken();
-  }
-  
-  /// getTok - Get the current (last) lexed token.
-  const AsmToken &getTok() {
-    return CurTok;
-  }
-  
-  /// getErrLoc - Get the current error location
-  const SMLoc &getErrLoc() {
-    return ErrLoc;
-  }
-  
-  /// getErr - Get the current error string
-  const std::string &getErr() {
-    return Err;
-  }
-  
-  /// getKind - Get the kind of current token.
-  AsmToken::TokenKind getKind() const { return CurTok.getKind(); }
-  
-  /// is - Check if the current token has kind \arg K.
-  bool is(AsmToken::TokenKind K) const { return CurTok.is(K); }
-  
-  /// isNot - Check if the current token has kind \arg K.
-  bool isNot(AsmToken::TokenKind K) const { return CurTok.isNot(K); }
-};
-
-} // End llvm namespace
-
-#endif
diff --git a/include/llvm/Target/TargetAsmParser.h b/include/llvm/Target/TargetAsmParser.h
deleted file mode 100644
index df84231..0000000
--- a/include/llvm/Target/TargetAsmParser.h
+++ /dev/null
@@ -1,85 +0,0 @@
-//===-- llvm/Target/TargetAsmParser.h - Target Assembly Parser --*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_TARGETPARSER_H
-#define LLVM_TARGET_TARGETPARSER_H
-
-#include "llvm/MC/MCParser/MCAsmParserExtension.h"
-
-namespace llvm {
-class MCStreamer;
-class StringRef;
-class SMLoc;
-class AsmToken;
-class MCParsedAsmOperand;
-template <typename T> class SmallVectorImpl;
-
-/// TargetAsmParser - Generic interface to target specific assembly parsers.
-class TargetAsmParser : public MCAsmParserExtension {
-  TargetAsmParser(const TargetAsmParser &);   // DO NOT IMPLEMENT
-  void operator=(const TargetAsmParser &);  // DO NOT IMPLEMENT
-protected: // Can only create subclasses.
-  TargetAsmParser();
- 
-  /// AvailableFeatures - The current set of available features.
-  unsigned AvailableFeatures;
-
-public:
-  virtual ~TargetAsmParser();
-
-  unsigned getAvailableFeatures() const { return AvailableFeatures; }
-  void setAvailableFeatures(unsigned Value) { AvailableFeatures = Value; }
-
-  virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
-                             SMLoc &EndLoc) = 0;
-
-  /// ParseInstruction - Parse one assembly instruction.
-  ///
-  /// The parser is positioned following the instruction name. The target
-  /// specific instruction parser should parse the entire instruction and
-  /// construct the appropriate MCInst, or emit an error. On success, the entire
-  /// line should be parsed up to and including the end-of-statement token. On
-  /// failure, the parser is not required to read to the end of the line.
-  //
-  /// \param Name - The instruction name.
-  /// \param NameLoc - The source location of the name.
-  /// \param Operands [out] - The list of parsed operands, this returns
-  ///        ownership of them to the caller.
-  /// \return True on failure.
-  virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
-                            SmallVectorImpl<MCParsedAsmOperand*> &Operands) = 0;
-
-  /// ParseDirective - Parse a target specific assembler directive
-  ///
-  /// The parser is positioned following the directive name.  The target
-  /// specific directive parser should parse the entire directive doing or
-  /// recording any target specific work, or return true and do nothing if the
-  /// directive is not target specific. If the directive is specific for
-  /// the target, the entire line is parsed up to and including the
-  /// end-of-statement token and false is returned.
-  ///
-  /// \param DirectiveID - the identifier token of the directive.
-  virtual bool ParseDirective(AsmToken DirectiveID) = 0;
-  
-  /// MatchAndEmitInstruction - Recognize a series of operands of a parsed
-  /// instruction as an actual MCInst and emit it to the specified MCStreamer.
-  /// This returns false on success and returns true on failure to match.
-  ///
-  /// On failure, the target parser is responsible for emitting a diagnostic
-  /// explaining the match failure.
-  virtual bool 
-  MatchAndEmitInstruction(SMLoc IDLoc,
-                          SmallVectorImpl<MCParsedAsmOperand*> &Operands,
-                          MCStreamer &Out) = 0;
-  
-};
-
-} // End llvm namespace
-
-#endif
diff --git a/include/llvm/Target/TargetData.h b/include/llvm/Target/TargetData.h
index c280810..26fd187 100644
--- a/include/llvm/Target/TargetData.h
+++ b/include/llvm/Target/TargetData.h
@@ -33,6 +33,8 @@ class StructType;
 class StructLayout;
 class GlobalVariable;
 class LLVMContext;
+template<typename T>
+class ArrayRef;
 
 /// Enum used to categorize the alignment types stored by TargetAlignElem
 enum AlignTypeEnum {
@@ -42,6 +44,7 @@ enum AlignTypeEnum {
   AGGREGATE_ALIGN = 'a',             ///< Aggregate alignment
   STACK_ALIGN = 's'                  ///< Stack objects alignment
 };
+  
 /// Target alignment element.
 ///
 /// Stores the alignment data associated with a given alignment type (pointer,
@@ -62,12 +65,19 @@ struct TargetAlignElem {
   bool operator==(const TargetAlignElem &rhs) const;
 };
 
+/// TargetData - This class holds a parsed version of the target data layout
+/// string in a module and provides methods for querying it.  The target data
+/// layout string is specified *by the target* - a frontend generating LLVM IR
+/// is required to generate the right target data for the target being codegen'd
+/// to.  If some measure of portability is desired, an empty string may be
+/// specified in the module.
 class TargetData : public ImmutablePass {
 private:
   bool          LittleEndian;          ///< Defaults to false
   unsigned      PointerMemSize;        ///< Pointer size in bytes
   unsigned      PointerABIAlign;       ///< Pointer ABI alignment
   unsigned      PointerPrefAlign;      ///< Pointer preferred alignment
+  unsigned      StackNaturalAlign;     ///< Stack natural alignment
 
   SmallVector<unsigned char, 8> LegalIntWidths; ///< Legal Integers.
   
@@ -90,9 +100,9 @@ private:
   void setAlignment(AlignTypeEnum align_type, unsigned abi_align,
                     unsigned pref_align, uint32_t bit_width);
   unsigned getAlignmentInfo(AlignTypeEnum align_type, uint32_t bit_width,
-                            bool ABIAlign, const Type *Ty) const;
+                            bool ABIAlign, Type *Ty) const;
   //! Internal helper method that returns requested alignment for type.
-  unsigned getAlignment(const Type *Ty, bool abi_or_pref) const;
+  unsigned getAlignment(Type *Ty, bool abi_or_pref) const;
 
   /// Valid alignment predicate.
   ///
@@ -161,6 +171,11 @@ public:
     return !isLegalInteger(Width);
   }
 
+  /// Returns true if the given alignment exceeds the natural stack alignment.
+  bool exceedsNaturalStackAlignment(unsigned Align) const {
+    return (StackNaturalAlign != 0) && (Align > StackNaturalAlign);
+  }
+
   /// fitsInLegalInteger - This function returns true if the specified type fits
   /// in a native integer type supported by the CPU.  For example, if the CPU
   /// only supports i32 as a native integer type, then i27 fits in a legal
@@ -200,19 +215,19 @@ public:
 
   /// getTypeSizeInBits - Return the number of bits necessary to hold the
   /// specified type.  For example, returns 36 for i36 and 80 for x86_fp80.
-  uint64_t getTypeSizeInBits(const Type* Ty) const;
+  uint64_t getTypeSizeInBits(Type* Ty) const;
 
   /// getTypeStoreSize - Return the maximum number of bytes that may be
   /// overwritten by storing the specified type.  For example, returns 5
   /// for i36 and 10 for x86_fp80.
-  uint64_t getTypeStoreSize(const Type *Ty) const {
+  uint64_t getTypeStoreSize(Type *Ty) const {
     return (getTypeSizeInBits(Ty)+7)/8;
   }
 
   /// getTypeStoreSizeInBits - Return the maximum number of bits that may be
   /// overwritten by storing the specified type; always a multiple of 8.  For
   /// example, returns 40 for i36 and 80 for x86_fp80.
-  uint64_t getTypeStoreSizeInBits(const Type *Ty) const {
+  uint64_t getTypeStoreSizeInBits(Type *Ty) const {
     return 8*getTypeStoreSize(Ty);
   }
 
@@ -220,7 +235,7 @@ public:
   /// of the specified type, including alignment padding.  This is the amount
   /// that alloca reserves for this type.  For example, returns 12 or 16 for
   /// x86_fp80, depending on alignment.
-  uint64_t getTypeAllocSize(const Type* Ty) const {
+  uint64_t getTypeAllocSize(Type* Ty) const {
     // Round up to the next alignment boundary.
     return RoundUpAlignment(getTypeStoreSize(Ty), getABITypeAlignment(Ty));
   }
@@ -229,13 +244,13 @@ public:
   /// objects of the specified type, including alignment padding; always a
   /// multiple of 8.  This is the amount that alloca reserves for this type.
   /// For example, returns 96 or 128 for x86_fp80, depending on alignment.
-  uint64_t getTypeAllocSizeInBits(const Type* Ty) const {
+  uint64_t getTypeAllocSizeInBits(Type* Ty) const {
     return 8*getTypeAllocSize(Ty);
   }
 
   /// getABITypeAlignment - Return the minimum ABI-required alignment for the
   /// specified type.
-  unsigned getABITypeAlignment(const Type *Ty) const;
+  unsigned getABITypeAlignment(Type *Ty) const;
   
   /// getABIIntegerTypeAlignment - Return the minimum ABI-required alignment for
   /// an integer type of the specified bitwidth.
@@ -244,17 +259,17 @@ public:
 
   /// getCallFrameTypeAlignment - Return the minimum ABI-required alignment
   /// for the specified type when it is part of a call frame.
-  unsigned getCallFrameTypeAlignment(const Type *Ty) const;
+  unsigned getCallFrameTypeAlignment(Type *Ty) const;
 
 
   /// getPrefTypeAlignment - Return the preferred stack/global alignment for
   /// the specified type.  This is always at least as good as the ABI alignment.
-  unsigned getPrefTypeAlignment(const Type *Ty) const;
+  unsigned getPrefTypeAlignment(Type *Ty) const;
 
   /// getPreferredTypeAlignmentShift - Return the preferred alignment for the
   /// specified type, returned as log2 of the value (a shift amount).
   ///
-  unsigned getPreferredTypeAlignmentShift(const Type *Ty) const;
+  unsigned getPreferredTypeAlignmentShift(Type *Ty) const;
 
   /// getIntPtrType - Return an unsigned integer type that is the same size or
   /// greater to the host pointer size.
@@ -264,13 +279,12 @@ public:
   /// getIndexedOffset - return the offset from the beginning of the type for
   /// the specified indices.  This is used to implement getelementptr.
   ///
-  uint64_t getIndexedOffset(const Type *Ty,
-                            Value* const* Indices, unsigned NumIndices) const;
+  uint64_t getIndexedOffset(Type *Ty, ArrayRef<Value *> Indices) const;
 
   /// getStructLayout - Return a StructLayout object, indicating the alignment
   /// of the struct, its size, and the offsets of its fields.  Note that this
   /// information is lazily cached.
-  const StructLayout *getStructLayout(const StructType *Ty) const;
+  const StructLayout *getStructLayout(StructType *Ty) const;
 
   /// getPreferredAlignment - Return the preferred alignment of the specified
   /// global.  This includes an explicitly requested alignment (if the global
@@ -333,7 +347,7 @@ public:
 
 private:
   friend class TargetData;   // Only TargetData can create this class
-  StructLayout(const StructType *ST, const TargetData &TD);
+  StructLayout(StructType *ST, const TargetData &TD);
 };
 
 } // End llvm namespace
diff --git a/include/llvm/Target/TargetFrameLowering.h b/include/llvm/Target/TargetFrameLowering.h
index e3d77cf..4c759b2 100644
--- a/include/llvm/Target/TargetFrameLowering.h
+++ b/include/llvm/Target/TargetFrameLowering.h
@@ -114,6 +114,10 @@ public:
   virtual void emitEpilogue(MachineFunction &MF,
                             MachineBasicBlock &MBB) const = 0;
 
+  /// Adjust the prologue to have the function use segmented stacks. This works
+  /// by adding a check even before the "normal" function prologue.
+  virtual void adjustForSegmentedStacks(MachineFunction &MF) const { }
+
   /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
   /// saved registers and returns true if it isn't possible / profitable to do
   /// so by issuing a series of store instructions via
@@ -161,11 +165,6 @@ public:
     return hasReservedCallFrame(MF) || hasFP(MF);
   }
 
-  /// getInitialFrameState - Returns a list of machine moves that are assumed
-  /// on entry to all functions.  Note that LabelID is ignored (assumed to be
-  /// the beginning of the function.)
-  virtual void getInitialFrameState(std::vector<MachineMove> &Moves) const;
-
   /// getFrameIndexOffset - Returns the displacement from the frame register to
   /// the stack frame of the specified index.
   virtual int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
@@ -191,14 +190,6 @@ public:
   ///
   virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
   }
-
-  /// getCompactUnwindEncoding - Get the compact unwind encoding for the
-  /// function. Return 0 if the compact unwind isn't available.
-  virtual uint32_t getCompactUnwindEncoding(ArrayRef<MCCFIInstruction> Instrs,
-                                            int DataAlignmentFactor,
-                                            bool IsEH) const {
-    return 0;
-  }
 };
 
 } // End llvm namespace
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index f663566..07f614d 100644
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -49,7 +49,7 @@ public:
     : CallFrameSetupOpcode(CFSetupOpcode),
       CallFrameDestroyOpcode(CFDestroyOpcode) {
   }
-    
+
   virtual ~TargetInstrInfo();
 
   /// getRegClass - Givem a machine instruction descriptor, returns the register
@@ -386,6 +386,16 @@ public:
   assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromStackSlot!");
   }
 
+  /// expandPostRAPseudo - This function is called for all pseudo instructions
+  /// that remain after register allocation. Many pseudo instructions are
+  /// created to help register allocation. This is the place to convert them
+  /// into real instructions. The target can edit MI in place, or it can insert
+  /// new instructions and erase MI. The function should return true if
+  /// anything was changed.
+  virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
+    return false;
+  }
+
   /// emitFrameIndexDebugValue - Emit a target-dependent form of
   /// DBG_VALUE encoding the address of a frame index.  Addresses would
   /// normally be lowered the same way as other addresses on the target,
@@ -671,6 +681,43 @@ public:
   bool hasLowDefLatency(const InstrItineraryData *ItinData,
                         const MachineInstr *DefMI, unsigned DefIdx) const;
 
+  /// verifyInstruction - Perform target specific instruction verification.
+  virtual
+  bool verifyInstruction(const MachineInstr *MI, StringRef &ErrInfo) const {
+    return true;
+  }
+
+  /// getExecutionDomain - Return the current execution domain and bit mask of
+  /// possible domains for instruction.
+  ///
+  /// Some micro-architectures have multiple execution domains, and multiple
+  /// opcodes that perform the same operation in different domains.  For
+  /// example, the x86 architecture provides the por, orps, and orpd
+  /// instructions that all do the same thing.  There is a latency penalty if a
+  /// register is written in one domain and read in another.
+  ///
+  /// This function returns a pair (domain, mask) containing the execution
+  /// domain of MI, and a bit mask of possible domains.  The setExecutionDomain
+  /// function can be used to change the opcode to one of the domains in the
+  /// bit mask.  Instructions whose execution domain can't be changed should
+  /// return a 0 mask.
+  ///
+  /// The execution domain numbers don't have any special meaning except domain
+  /// 0 is used for instructions that are not associated with any interesting
+  /// execution domain.
+  ///
+  virtual std::pair<uint16_t, uint16_t>
+  getExecutionDomain(const MachineInstr *MI) const {
+    return std::make_pair(0, 0);
+  }
+
+  /// setExecutionDomain - Change the opcode of MI to execute in Domain.
+  ///
+  /// The bit (1 << Domain) must be set in the mask returned from
+  /// getExecutionDomain(MI).
+  ///
+  virtual void setExecutionDomain(MachineInstr *MI, unsigned Domain) const {}
+
 private:
   int CallFrameSetupOpcode, CallFrameDestroyOpcode;
 };
@@ -693,6 +740,12 @@ public:
                                      unsigned &SrcOpIdx2) const;
   virtual bool canFoldMemoryOperand(const MachineInstr *MI,
                                     const SmallVectorImpl<unsigned> &Ops) const;
+  virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
+                                    const MachineMemOperand *&MMO,
+                                    int &FrameIndex) const;
+  virtual bool hasStoreToStackSlot(const MachineInstr *MI,
+                                   const MachineMemOperand *&MMO,
+                                   int &FrameIndex) const;
   virtual bool PredicateInstruction(MachineInstr *MI,
                             const SmallVectorImpl<MachineOperand> &Pred) const;
   virtual void reMaterialize(MachineBasicBlock &MBB,
diff --git a/include/llvm/Target/TargetIntrinsicInfo.h b/include/llvm/Target/TargetIntrinsicInfo.h
index ad8ac92..c44b923 100644
--- a/include/llvm/Target/TargetIntrinsicInfo.h
+++ b/include/llvm/Target/TargetIntrinsicInfo.h
@@ -39,7 +39,7 @@ public:
   /// intrinsic, Tys should point to an array of numTys pointers to Type,
   /// and must provide exactly one type for each overloaded type in the
   /// intrinsic.
-  virtual std::string getName(unsigned IID, const Type **Tys = 0,
+  virtual std::string getName(unsigned IID, Type **Tys = 0,
                               unsigned numTys = 0) const = 0;
 
   /// Look up target intrinsic by name. Return intrinsic ID or 0 for unknown
@@ -55,7 +55,7 @@ public:
   /// Create or insert an LLVM Function declaration for an intrinsic,
   /// and return it. The Tys and numTys are for intrinsics with overloaded
   /// types. See above for more information.
-  virtual Function *getDeclaration(Module *M, unsigned ID, const Type **Tys = 0,
+  virtual Function *getDeclaration(Module *M, unsigned ID, Type **Tys = 0,
                                    unsigned numTys = 0) const = 0;
 };
 
diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h
index 533c3ac..013e70a 100644
--- a/include/llvm/Target/TargetLowering.h
+++ b/include/llvm/Target/TargetLowering.h
@@ -113,6 +113,22 @@ public:
     ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
   };
 
+  static ISD::NodeType getExtendForContent(BooleanContent Content) {
+    switch (Content) {
+    default:
+      assert(false && "Unknown BooleanContent!");
+    case UndefinedBooleanContent:
+      // Extend by adding rubbish bits.
+      return ISD::ANY_EXTEND;
+    case ZeroOrOneBooleanContent:
+      // Extend by adding zero bits.
+      return ISD::ZERO_EXTEND;
+    case ZeroOrNegativeOneBooleanContent:
+      // Extend by copying the sign bit.
+      return ISD::SIGN_EXTEND;
+    }
+  }
+
   /// NOTE: The constructor takes ownership of TLOF.
   explicit TargetLowering(const TargetMachine &TM,
                           const TargetLoweringObjectFile *TLOF);
@@ -148,8 +164,7 @@ public:
   /// the condition operand of SELECT and BRCOND nodes.  In the case of
   /// BRCOND the argument passed is MVT::Other since there are no other
   /// operands to get a type hint from.
-  virtual
-  MVT::SimpleValueType getSetCCResultType(EVT VT) const;
+  virtual EVT getSetCCResultType(EVT VT) const;
 
   /// getCmpLibcallReturnType - Return the ValueType for comparison
   /// libcalls. Comparions libcalls include floating point comparion calls,
@@ -162,7 +177,13 @@ public:
   /// "Boolean values" are special true/false values produced by nodes like
   /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
   /// Not to be confused with general values promoted from i1.
-  BooleanContent getBooleanContents() const { return BooleanContents;}
+  /// Some cpus distinguish between vectors of boolean and scalars; the isVec
+  /// parameter selects between the two kinds.  For example on X86 a scalar
+  /// boolean should be zero extended from i1, while the elements of a vector
+  /// of booleans should be sign extended from i1.
+  BooleanContent getBooleanContents(bool isVec) const {
+    return isVec ? BooleanVectorContents : BooleanContents;
+  }
 
   /// getSchedulingPreference - Return target scheduling preference.
   Sched::Preference getSchedulingPreference() const {
@@ -172,7 +193,7 @@ public:
   /// getSchedulingPreference - Some scheduler, e.g. hybrid, can switch to
   /// different scheduling heuristics for different nodes. This function returns
   /// the preference (or none) for the given node.
-  virtual Sched::Preference getSchedulingPreference(SDNode *N) const {
+  virtual Sched::Preference getSchedulingPreference(SDNode *) const {
     return Sched::None;
   }
 
@@ -265,9 +286,9 @@ public:
     assert(!VT.isVector());
     while (true) {
       switch (getTypeAction(Context, VT)) {
-      case Legal:
+      case TypeLegal:
         return VT;
-      case Expand:
+      case TypeExpandInteger:
         VT = getTypeToTransformTo(Context, VT);
         break;
       default:
@@ -307,15 +328,15 @@ public:
     bool         writeMem;    // writes memory?
   };
 
-  virtual bool getTgtMemIntrinsic(IntrinsicInfo &Info,
-                                  const CallInst &I, unsigned Intrinsic) const {
+  virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
+                                  unsigned /*Intrinsic*/) const {
     return false;
   }
 
   /// isFPImmLegal - Returns true if the target can instruction select the
   /// specified FP immediate natively. If false, the legalizer will materialize
   /// the FP immediate as a load from a constant pool.
-  virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const {
+  virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
     return false;
   }
 
@@ -323,8 +344,8 @@ public:
   /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
   /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values
   /// are assumed to be legal.
-  virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
-                                  EVT VT) const {
+  virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
+                                  EVT /*VT*/) const {
     return true;
   }
 
@@ -337,8 +358,8 @@ public:
   /// used by Targets can use this to indicate if there is a suitable
   /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
   /// pool entry.
-  virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
-                                      EVT VT) const {
+  virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
+                                      EVT /*VT*/) const {
     return false;
   }
 
@@ -383,9 +404,7 @@ public:
   /// isLoadExtLegal - Return true if the specified load with extension is legal
   /// on this target.
   bool isLoadExtLegal(unsigned ExtType, EVT VT) const {
-    return VT.isSimple() &&
-      (getLoadExtAction(ExtType, VT) == Legal ||
-       getLoadExtAction(ExtType, VT) == Custom);
+    return VT.isSimple() && getLoadExtAction(ExtType, VT) == Legal;
   }
 
   /// getTruncStoreAction - Return how this store with truncation should be
@@ -404,8 +423,7 @@ public:
   /// legal on this target.
   bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
     return isTypeLegal(ValVT) && MemVT.isSimple() &&
-      (getTruncStoreAction(ValVT, MemVT) == Legal ||
-       getTruncStoreAction(ValVT, MemVT) == Custom);
+           getTruncStoreAction(ValVT, MemVT) == Legal;
   }
 
   /// getIndexedLoadAction - Return how the indexed load should be treated:
@@ -501,7 +519,7 @@ public:
   /// This is fixed by the LLVM operations except for the pointer size.  If
   /// AllowUnknown is true, this will return MVT::Other for types with no EVT
   /// counterpart (e.g. structs), otherwise it will assert.
-  EVT getValueType(const Type *Ty, bool AllowUnknown = false) const {
+  EVT getValueType(Type *Ty, bool AllowUnknown = false) const {
     EVT VT = EVT::getEVT(Ty, AllowUnknown);
     return VT == MVT::iPTR ? PointerTy : VT;
   }
@@ -509,7 +527,7 @@ public:
   /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
   /// function arguments in the caller parameter area.  This is the actual
   /// alignment, not its logarithm.
-  virtual unsigned getByValTypeAlignment(const Type *Ty) const;
+  virtual unsigned getByValTypeAlignment(Type *Ty) const;
 
   /// getRegisterType - Return the type of registers that this ValueType will
   /// eventually require.
@@ -569,7 +587,7 @@ public:
   /// ShouldShrinkFPConstant - If true, then instruction selection should
   /// seek to shrink the FP constant of the specified type to a smaller type
   /// in order to save space and / or reduce runtime.
-  virtual bool ShouldShrinkFPConstant(EVT VT) const { return true; }
+  virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
 
   /// hasTargetDAGCombine - If true, the target has custom DAG combine
   /// transformations that it can perform for the specified node.
@@ -611,7 +629,7 @@ public:
   /// use helps to ensure that such replacements don't generate code that causes
   /// an alignment error  (trap) on the target machine.
   /// @brief Determine if the target supports unaligned memory accesses.
-  virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
+  virtual bool allowsUnalignedMemoryAccesses(EVT) const {
     return false;
   }
 
@@ -634,10 +652,11 @@ public:
   /// constant so it does not need to be loaded.
   /// It returns EVT::Other if the type should be determined using generic
   /// target-independent logic.
-  virtual EVT getOptimalMemOpType(uint64_t Size,
-                                  unsigned DstAlign, unsigned SrcAlign,
-                                  bool NonScalarIntSafe, bool MemcpyStrSrc,
-                                  MachineFunction &MF) const {
+  virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
+                                  unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
+                                  bool /*NonScalarIntSafe*/,
+                                  bool /*MemcpyStrSrc*/,
+                                  MachineFunction &/*MF*/) const {
     return MVT::Other;
   }
 
@@ -717,23 +736,30 @@ public:
     return ShouldFoldAtomicFences;
   }
 
+  /// getInsertFencesFor - return whether the DAG builder should automatically
+  /// insert fences and reduce ordering for atomics.
+  ///
+  bool getInsertFencesForAtomic() const {
+    return InsertFencesForAtomic;
+  }
+
   /// getPreIndexedAddressParts - returns true by value, base pointer and
   /// offset pointer and addressing mode by reference if the node's address
   /// can be legally represented as pre-indexed load / store address.
-  virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
-                                         SDValue &Offset,
-                                         ISD::MemIndexedMode &AM,
-                                         SelectionDAG &DAG) const {
+  virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
+                                         SDValue &/*Offset*/,
+                                         ISD::MemIndexedMode &/*AM*/,
+                                         SelectionDAG &/*DAG*/) const {
     return false;
   }
 
   /// getPostIndexedAddressParts - returns true by value, base pointer and
   /// offset pointer and addressing mode by reference if this node can be
   /// combined with a load / store to form a post-indexed load / store.
-  virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
-                                          SDValue &Base, SDValue &Offset,
-                                          ISD::MemIndexedMode &AM,
-                                          SelectionDAG &DAG) const {
+  virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
+                                          SDValue &/*Base*/, SDValue &/*Offset*/,
+                                          ISD::MemIndexedMode &/*AM*/,
+                                          SelectionDAG &/*DAG*/) const {
     return false;
   }
 
@@ -743,9 +769,9 @@ public:
   virtual unsigned getJumpTableEncoding() const;
 
   virtual const MCExpr *
-  LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
-                            const MachineBasicBlock *MBB, unsigned uid,
-                            MCContext &Ctx) const {
+  LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
+                            const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
+                            MCContext &/*Ctx*/) const {
     assert(0 && "Need to implement this hook if target has custom JTIs");
     return 0;
   }
@@ -771,7 +797,8 @@ public:
   /// protector cookies at a fixed offset in some non-standard address
   /// space, and populates the address space and offset as
   /// appropriate.
-  virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const {
+  virtual bool getStackCookieLocation(unsigned &/*AddressSpace*/,
+                                      unsigned &/*Offset*/) const {
     return false;
   }
 
@@ -906,7 +933,7 @@ public:
   /// the specified value type and it is 'desirable' to use the type for the
   /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
   /// instruction encodings are longer and some i16 instructions are slow.
-  virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const {
+  virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
     // By default, assume all legal types are desirable.
     return isTypeLegal(VT);
   }
@@ -914,14 +941,15 @@ public:
   /// isDesirableToPromoteOp - Return true if it is profitable for dag combiner
   /// to transform a floating point op of specified opcode to a equivalent op of
   /// an integer type. e.g. f32 load -> i32 load can be profitable on ARM.
-  virtual bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const {
+  virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
+                                                 EVT /*VT*/) const {
     return false;
   }
 
   /// IsDesirableToPromoteOp - This method query the target whether it is
   /// beneficial for dag combiner to promote the specified node. If true, it
   /// should return the desired promotion type by reference.
-  virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
+  virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
     return false;
   }
 
@@ -934,6 +962,12 @@ protected:
   /// setBooleanContents - Specify how the target extends the result of a
   /// boolean value from i1 to a wider type.  See getBooleanContents.
   void setBooleanContents(BooleanContent Ty) { BooleanContents = Ty; }
+  /// setBooleanVectorContents - Specify how the target extends the result
+  /// of a vector boolean value from a vector of i1 to a wider type.  See
+  /// getBooleanContents.
+  void setBooleanVectorContents(BooleanContent Ty) {
+    BooleanVectorContents = Ty;
+  }
 
   /// setSchedulingPreference - Specify the target scheduling preference.
   void setSchedulingPreference(Sched::Preference Pref) {
@@ -1137,6 +1171,13 @@ protected:
     ShouldFoldAtomicFences = fold;
   }
 
+  /// setInsertFencesForAtomic - Set if the the DAG builder should
+  /// automatically insert fences and reduce the order of atomic memory
+  /// operations to Monotonic.
+  void setInsertFencesForAtomic(bool fence) {
+    InsertFencesForAtomic = fence;
+  }
+
 public:
   //===--------------------------------------------------------------------===//
   // Lowering methods - These methods must be implemented by targets so that
@@ -1150,11 +1191,11 @@ public:
   /// chain value.
   ///
   virtual SDValue
-    LowerFormalArguments(SDValue Chain,
-                         CallingConv::ID CallConv, bool isVarArg,
-                         const SmallVectorImpl<ISD::InputArg> &Ins,
-                         DebugLoc dl, SelectionDAG &DAG,
-                         SmallVectorImpl<SDValue> &InVals) const {
+    LowerFormalArguments(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
+                         bool /*isVarArg*/,
+                         const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
+                         DebugLoc /*dl*/, SelectionDAG &/*DAG*/,
+                         SmallVectorImpl<SDValue> &/*InVals*/) const {
     assert(0 && "Not Implemented");
     return SDValue();    // this is here to silence compiler errors
   }
@@ -1166,7 +1207,7 @@ public:
   /// lowering.
   struct ArgListEntry {
     SDValue Node;
-    const Type* Ty;
+    Type* Ty;
     bool isSExt  : 1;
     bool isZExt  : 1;
     bool isInReg : 1;
@@ -1180,7 +1221,7 @@ public:
   };
   typedef std::vector<ArgListEntry> ArgListTy;
   std::pair<SDValue, SDValue>
-  LowerCallTo(SDValue Chain, const Type *RetTy, bool RetSExt, bool RetZExt,
+  LowerCallTo(SDValue Chain, Type *RetTy, bool RetSExt, bool RetZExt,
               bool isVarArg, bool isInreg, unsigned NumFixedArgs,
               CallingConv::ID CallConv, bool isTailCall,
               bool isReturnValueUsed, SDValue Callee, ArgListTy &Args,
@@ -1193,13 +1234,14 @@ public:
   /// InVals array with legal-type return values from the call, and return
   /// the resulting token chain value.
   virtual SDValue
-    LowerCall(SDValue Chain, SDValue Callee,
-              CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
-              const SmallVectorImpl<ISD::OutputArg> &Outs,
-              const SmallVectorImpl<SDValue> &OutVals,
-              const SmallVectorImpl<ISD::InputArg> &Ins,
-              DebugLoc dl, SelectionDAG &DAG,
-              SmallVectorImpl<SDValue> &InVals) const {
+    LowerCall(SDValue /*Chain*/, SDValue /*Callee*/,
+              CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
+              bool &/*isTailCall*/,
+              const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
+              const SmallVectorImpl<SDValue> &/*OutVals*/,
+              const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
+              DebugLoc /*dl*/, SelectionDAG &/*DAG*/,
+              SmallVectorImpl<SDValue> &/*InVals*/) const {
     assert(0 && "Not Implemented");
     return SDValue();    // this is here to silence compiler errors
   }
@@ -1211,10 +1253,10 @@ public:
   /// return values described by the Outs array can fit into the return
   /// registers.  If false is returned, an sret-demotion is performed.
   ///
-  virtual bool CanLowerReturn(CallingConv::ID CallConv,
-			      MachineFunction &MF, bool isVarArg,
-               const SmallVectorImpl<ISD::OutputArg> &Outs,
-               LLVMContext &Context) const
+  virtual bool CanLowerReturn(CallingConv::ID /*CallConv*/,
+			      MachineFunction &/*MF*/, bool /*isVarArg*/,
+               const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
+               LLVMContext &/*Context*/) const
   {
     // Return true by default to get preexisting behavior.
     return true;
@@ -1226,10 +1268,11 @@ public:
   /// value.
   ///
   virtual SDValue
-    LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
-                const SmallVectorImpl<ISD::OutputArg> &Outs,
-                const SmallVectorImpl<SDValue> &OutVals,
-                DebugLoc dl, SelectionDAG &DAG) const {
+    LowerReturn(SDValue /*Chain*/, CallingConv::ID /*CallConv*/,
+                bool /*isVarArg*/,
+                const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
+                const SmallVectorImpl<SDValue> &/*OutVals*/,
+                DebugLoc /*dl*/, SelectionDAG &/*DAG*/) const {
     assert(0 && "Not Implemented");
     return SDValue();    // this is here to silence compiler errors
   }
@@ -1237,7 +1280,7 @@ public:
   /// isUsedByReturnOnly - Return true if result of the specified node is used
   /// by a return node only. This is used to determine whether it is possible
   /// to codegen a libcall as tail call at legalization time.
-  virtual bool isUsedByReturnOnly(SDNode *N) const {
+  virtual bool isUsedByReturnOnly(SDNode *) const {
     return false;
   }
 
@@ -1245,7 +1288,7 @@ public:
   /// call instruction as a tail call. This is used by optimization passes to
   /// determine if it's profitable to duplicate return instructions to enable
   /// tailcall optimization.
-  virtual bool mayBeEmittedAsTailCall(CallInst *CI) const {
+  virtual bool mayBeEmittedAsTailCall(CallInst *) const {
     return false;
   }
 
@@ -1256,7 +1299,7 @@ public:
   /// necessary for non-C calling conventions. The frontend should handle this
   /// and include all of the necessary information.
   virtual EVT getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
-                                       ISD::NodeType ExtendKind) const {
+                                       ISD::NodeType /*ExtendKind*/) const {
     EVT MinVT = getRegisterType(Context, MVT::i32);
     return VT.bitsLT(MinVT) ? MinVT : VT;
   }
@@ -1293,8 +1336,9 @@ public:
   ///
   /// If the target has no operations that require custom lowering, it need not
   /// implement this.  The default implementation aborts.
-  virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
-                                  SelectionDAG &DAG) const {
+  virtual void ReplaceNodeResults(SDNode * /*N*/,
+                                  SmallVectorImpl<SDValue> &/*Results*/,
+                                  SelectionDAG &/*DAG*/) const {
     assert(0 && "ReplaceNodeResults not implemented for this target!");
   }
 
@@ -1304,7 +1348,7 @@ public:
 
   /// createFastISel - This method returns a target specific FastISel object,
   /// or null if the target does not support "fast" ISel.
-  virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const {
+  virtual FastISel *createFastISel(FunctionLoweringInfo &) const {
     return 0;
   }
 
@@ -1316,7 +1360,7 @@ public:
   /// call to be explicit llvm code if it wants to.  This is useful for
   /// turning simple inline asms into LLVM intrinsics, which gives the
   /// compiler more information about the behavior of the code.
-  virtual bool ExpandInlineAsm(CallInst *CI) const {
+  virtual bool ExpandInlineAsm(CallInst *) const {
     return false;
   }
 
@@ -1460,6 +1504,13 @@ public:
   virtual MachineBasicBlock *
     EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const;
 
+  /// AdjustInstrPostInstrSelection - This method should be implemented by
+  /// targets that mark instructions with the 'hasPostISelHook' flag. These
+  /// instructions must be adjusted after instruction selection by target hooks.
+  /// e.g. To fill in optional defs for ARM 's' setting instructions.
+  virtual void
+  AdjustInstrPostInstrSelection(MachineInstr *MI, SDNode *Node) const;
+
   //===--------------------------------------------------------------------===//
   // Addressing mode description hooks (used by LSR etc).
   //
@@ -1485,16 +1536,32 @@ public:
   /// The type may be VoidTy, in which case only return true if the addressing
   /// mode is legal for a load/store of any legal type.
   /// TODO: Handle pre/postinc as well.
-  virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const;
+  virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
+
+  /// isLegalICmpImmediate - Return true if the specified immediate is legal
+  /// icmp immediate, that is the target has icmp instructions which can compare
+  /// a register against the immediate without having to materialize the
+  /// immediate into a register.
+  virtual bool isLegalICmpImmediate(int64_t) const {
+    return true;
+  }
+
+  /// isLegalAddImmediate - Return true if the specified immediate is legal
+  /// add immediate, that is the target has add instructions which can add
+  /// a register with the immediate without having to materialize the
+  /// immediate into a register.
+  virtual bool isLegalAddImmediate(int64_t) const {
+    return true;
+  }
 
   /// isTruncateFree - Return true if it's free to truncate a value of
   /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
   /// register EAX to i16 by referencing its sub-register AX.
-  virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const {
+  virtual bool isTruncateFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
     return false;
   }
 
-  virtual bool isTruncateFree(EVT VT1, EVT VT2) const {
+  virtual bool isTruncateFree(EVT /*VT1*/, EVT /*VT2*/) const {
     return false;
   }
 
@@ -1506,37 +1573,21 @@ public:
   /// does not necessarily apply to truncate instructions. e.g. on x86-64,
   /// all instructions that define 32-bit values implicit zero-extend the
   /// result out to 64 bits.
-  virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const {
+  virtual bool isZExtFree(Type * /*Ty1*/, Type * /*Ty2*/) const {
     return false;
   }
 
-  virtual bool isZExtFree(EVT VT1, EVT VT2) const {
+  virtual bool isZExtFree(EVT /*VT1*/, EVT /*VT2*/) const {
     return false;
   }
 
   /// isNarrowingProfitable - Return true if it's profitable to narrow
   /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
   /// from i32 to i8 but not from i32 to i16.
-  virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const {
+  virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
     return false;
   }
 
-  /// isLegalICmpImmediate - Return true if the specified immediate is legal
-  /// icmp immediate, that is the target has icmp instructions which can compare
-  /// a register against the immediate without having to materialize the
-  /// immediate into a register.
-  virtual bool isLegalICmpImmediate(int64_t Imm) const {
-    return true;
-  }
-
-  /// isLegalAddImmediate - Return true if the specified immediate is legal
-  /// add immediate, that is the target has add instructions which can add
-  /// a register with the immediate without having to materialize the
-  /// immediate into a register.
-  virtual bool isLegalAddImmediate(int64_t Imm) const {
-    return true;
-  }
-
   //===--------------------------------------------------------------------===//
   // Div utility functions
   //
@@ -1639,6 +1690,10 @@ private:
   /// BooleanContents - Information about the contents of the high-bits in
   /// boolean values held in a type wider than i1.  See getBooleanContents.
   BooleanContent BooleanContents;
+  /// BooleanVectorContents - Information about the contents of the high-bits
+  /// in boolean vector values when the element type is wider than i1.  See
+  /// getBooleanContents.
+  BooleanContent BooleanVectorContents;
 
   /// SchedPreferenceInfo - The target scheduling preference: shortest possible
   /// total cycles or lowest register usage.
@@ -1676,6 +1731,11 @@ private:
   /// combiner.
   bool ShouldFoldAtomicFences;
 
+  /// InsertFencesForAtomic - Whether the DAG builder should automatically
+  /// insert fences and reduce ordering for atomics.  (This will be set for
+  /// for most architectures with weak memory ordering.)
+  bool InsertFencesForAtomic;
+
   /// StackPointerRegisterToSaveRestore - If set to a physical register, this
   /// specifies the register that llvm.savestack/llvm.restorestack should save
   /// and restore.
@@ -1963,7 +2023,7 @@ private:
 /// GetReturnInfo - Given an LLVM IR type and return type attributes,
 /// compute the return value EVTs and flags, and optionally also
 /// the offsets, if the return value is being lowered to memory.
-void GetReturnInfo(const Type* ReturnType, Attributes attr,
+void GetReturnInfo(Type* ReturnType, Attributes attr,
                    SmallVectorImpl<ISD::OutputArg> &Outs,
                    const TargetLowering &TLI,
                    SmallVectorImpl<uint64_t> *Offsets = 0);
diff --git a/include/llvm/Target/TargetLoweringObjectFile.h b/include/llvm/Target/TargetLoweringObjectFile.h
index 2e1d6b9..7d06cec 100644
--- a/include/llvm/Target/TargetLoweringObjectFile.h
+++ b/include/llvm/Target/TargetLoweringObjectFile.h
@@ -16,6 +16,7 @@
 #define LLVM_TARGET_TARGETLOWERINGOBJECTFILE_H
 
 #include "llvm/ADT/StringRef.h"
+#include "llvm/MC/MCObjectFileInfo.h"
 #include "llvm/MC/SectionKind.h"
 
 namespace llvm {
@@ -31,137 +32,27 @@ namespace llvm {
   class GlobalValue;
   class TargetMachine;
   
-class TargetLoweringObjectFile {
+class TargetLoweringObjectFile : public MCObjectFileInfo {
   MCContext *Ctx;
   
   TargetLoweringObjectFile(const TargetLoweringObjectFile&); // DO NOT IMPLEMENT
   void operator=(const TargetLoweringObjectFile&);           // DO NOT IMPLEMENT
-protected:
-  
-  TargetLoweringObjectFile();
-  
-  /// TextSection - Section directive for standard text.
-  ///
-  const MCSection *TextSection;
-  
-  /// DataSection - Section directive for standard data.
-  ///
-  const MCSection *DataSection;
   
-  /// BSSSection - Section that is default initialized to zero.
-  const MCSection *BSSSection;
-  
-  /// ReadOnlySection - Section that is readonly and can contain arbitrary
-  /// initialized data.  Targets are not required to have a readonly section.
-  /// If they don't, various bits of code will fall back to using the data
-  /// section for constants.
-  const MCSection *ReadOnlySection;
-  
-  /// StaticCtorSection - This section contains the static constructor pointer
-  /// list.
-  const MCSection *StaticCtorSection;
-
-  /// StaticDtorSection - This section contains the static destructor pointer
-  /// list.
-  const MCSection *StaticDtorSection;
-  
-  /// LSDASection - If exception handling is supported by the target, this is
-  /// the section the Language Specific Data Area information is emitted to.
-  const MCSection *LSDASection;
-
-  /// CompactUnwindSection - If exception handling is supported by the target
-  /// and the target can support a compact representation of the CIE and FDE,
-  /// this is the section to emit them into.
-  const MCSection *CompactUnwindSection;
-  
-  // Dwarf sections for debug info.  If a target supports debug info, these must
-  // be set.
-  const MCSection *DwarfAbbrevSection;
-  const MCSection *DwarfInfoSection;
-  const MCSection *DwarfLineSection;
-  const MCSection *DwarfFrameSection;
-  const MCSection *DwarfPubNamesSection;
-  const MCSection *DwarfPubTypesSection;
-  const MCSection *DwarfDebugInlineSection;
-  const MCSection *DwarfStrSection;
-  const MCSection *DwarfLocSection;
-  const MCSection *DwarfARangesSection;
-  const MCSection *DwarfRangesSection;
-  const MCSection *DwarfMacroInfoSection;
-  
-  // Extra TLS Variable Data section.  If the target needs to put additional
-  // information for a TLS variable, it'll go here.
-  const MCSection *TLSExtraDataSection;
-  
-  /// CommDirectiveSupportsAlignment - True if .comm supports alignment.  This
-  /// is a hack for as long as we support 10.4 Tiger, whose assembler doesn't
-  /// support alignment on comm.
-  bool CommDirectiveSupportsAlignment;
-  
-  /// SupportsWeakEmptyEHFrame - True if target object file supports a
-  /// weak_definition of constant 0 for an omitted EH frame.
-  bool SupportsWeakOmittedEHFrame;
-  
-  /// IsFunctionEHFrameSymbolPrivate - This flag is set to true if the
-  /// "EH_frame" symbol for EH information should be an assembler temporary (aka
-  /// private linkage, aka an L or .L label) or false if it should be a normal
-  /// non-.globl label.  This defaults to true.
-  bool IsFunctionEHFrameSymbolPrivate;
-
 public:
   MCContext &getContext() const { return *Ctx; }
+
+  TargetLoweringObjectFile() : MCObjectFileInfo(), Ctx(0) {}
   
   virtual ~TargetLoweringObjectFile();
   
   /// Initialize - this method must be called before any actual lowering is
   /// done.  This specifies the current context for codegen, and gives the
   /// lowering implementations a chance to set up their default sections.
-  virtual void Initialize(MCContext &ctx, const TargetMachine &TM) {
-    Ctx = &ctx;
-  }
+  virtual void Initialize(MCContext &ctx, const TargetMachine &TM);
   
-  bool isFunctionEHFrameSymbolPrivate() const {
-    return IsFunctionEHFrameSymbolPrivate;
-  }
-  bool getSupportsWeakOmittedEHFrame() const {
-    return SupportsWeakOmittedEHFrame;
-  }
-  bool getCommDirectiveSupportsAlignment() const {
-    return CommDirectiveSupportsAlignment;
-  }
-
-  const MCSection *getTextSection() const { return TextSection; }
-  const MCSection *getDataSection() const { return DataSection; }
-  const MCSection *getBSSSection() const { return BSSSection; }
-  const MCSection *getStaticCtorSection() const { return StaticCtorSection; }
-  const MCSection *getStaticDtorSection() const { return StaticDtorSection; }
-  const MCSection *getLSDASection() const { return LSDASection; }
-  const MCSection *getCompactUnwindSection() const{return CompactUnwindSection;}
-  virtual const MCSection *getEHFrameSection() const = 0;
   virtual void emitPersonalityValue(MCStreamer &Streamer,
                                     const TargetMachine &TM,
                                     const MCSymbol *Sym) const;
-  const MCSection *getDwarfAbbrevSection() const { return DwarfAbbrevSection; }
-  const MCSection *getDwarfInfoSection() const { return DwarfInfoSection; }
-  const MCSection *getDwarfLineSection() const { return DwarfLineSection; }
-  const MCSection *getDwarfFrameSection() const { return DwarfFrameSection; }
-  const MCSection *getDwarfPubNamesSection() const{return DwarfPubNamesSection;}
-  const MCSection *getDwarfPubTypesSection() const{return DwarfPubTypesSection;}
-  const MCSection *getDwarfDebugInlineSection() const {
-    return DwarfDebugInlineSection;
-  }
-  const MCSection *getDwarfStrSection() const { return DwarfStrSection; }
-  const MCSection *getDwarfLocSection() const { return DwarfLocSection; }
-  const MCSection *getDwarfARangesSection() const { return DwarfARangesSection;}
-  const MCSection *getDwarfRangesSection() const { return DwarfRangesSection; }
-  const MCSection *getDwarfMacroInfoSection() const {
-    return DwarfMacroInfoSection;
-  }
-  const MCSection *getTLSExtraDataSection() const {
-    return TLSExtraDataSection;
-  }
-  virtual const MCSection *getWin64EHFuncTableSection(StringRef suffix)const=0;
-  virtual const MCSection *getWin64EHTableSection(StringRef suffix) const = 0;
   
   /// shouldEmitUsedDirectiveFor - This hook allows targets to selectively
   /// decide not to emit the UsedDirective for some symbols in llvm.used.
@@ -231,11 +122,6 @@ public:
   getExprForDwarfReference(const MCSymbol *Sym, unsigned Encoding,
                            MCStreamer &Streamer) const;
   
-  virtual unsigned getPersonalityEncoding() const;
-  virtual unsigned getLSDAEncoding() const;
-  virtual unsigned getFDEEncoding(bool CFI) const;
-  virtual unsigned getTTypeEncoding() const;
-
 protected:
   virtual const MCSection *
   SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind,
diff --git a/include/llvm/Target/TargetMachine.h b/include/llvm/Target/TargetMachine.h
index ac41a58..8a8d142 100644
--- a/include/llvm/Target/TargetMachine.h
+++ b/include/llvm/Target/TargetMachine.h
@@ -14,6 +14,7 @@
 #ifndef LLVM_TARGET_TARGETMACHINE_H
 #define LLVM_TARGET_TARGETMACHINE_H
 
+#include "llvm/MC/MCCodeGenInfo.h"
 #include "llvm/ADT/StringRef.h"
 #include <cassert>
 #include <string>
@@ -23,6 +24,7 @@ namespace llvm {
 class InstrItineraryData;
 class JITCodeEmitter;
 class MCAsmInfo;
+class MCCodeGenInfo;
 class MCContext;
 class Pass;
 class PassManager;
@@ -41,27 +43,6 @@ class TargetSubtargetInfo;
 class formatted_raw_ostream;
 class raw_ostream;
 
-// Relocation model types.
-namespace Reloc {
-  enum Model {
-    Default,
-    Static,
-    PIC_,         // Cannot be named PIC due to collision with -DPIC
-    DynamicNoPIC
-  };
-}
-
-// Code model types.
-namespace CodeModel {
-  enum Model {
-    Default,
-    Small,
-    Kernel,
-    Medium,
-    Large
-  };
-}
-
 // Code generation optimization level.
 namespace CodeGenOpt {
   enum Level {
@@ -108,6 +89,9 @@ protected: // Can only create subclasses.
   std::string TargetCPU;
   std::string TargetFS;
 
+  /// CodeGenInfo - Low level target information such as relocation model.
+  const MCCodeGenInfo *CodeGenInfo;
+
   /// AsmInfo - Contains target specific asm information.
   ///
   const MCAsmInfo *AsmInfo;
@@ -214,19 +198,11 @@ public:
 
   /// getRelocationModel - Returns the code generation relocation model. The
   /// choices are static, PIC, and dynamic-no-pic, and target default.
-  static Reloc::Model getRelocationModel();
-
-  /// setRelocationModel - Sets the code generation relocation model.
-  ///
-  static void setRelocationModel(Reloc::Model Model);
+  Reloc::Model getRelocationModel() const;
 
   /// getCodeModel - Returns the code model. The choices are small, kernel,
   /// medium, large, and target default.
-  static CodeModel::Model getCodeModel();
-
-  /// setCodeModel - Sets the code model.
-  ///
-  static void setCodeModel(CodeModel::Model Model);
+  CodeModel::Model getCodeModel() const;
 
   /// getAsmVerbosityDefault - Returns the default value of asm verbosity.
   ///
@@ -309,7 +285,8 @@ public:
 class LLVMTargetMachine : public TargetMachine {
 protected: // Can only create subclasses.
   LLVMTargetMachine(const Target &T, StringRef TargetTriple,
-                    StringRef CPU, StringRef FS);
+                    StringRef CPU, StringRef FS,
+                    Reloc::Model RM, CodeModel::Model CM);
 
 private:
   /// addCommonCodeGenPasses - Add standard LLVM codegen passes used for
@@ -318,9 +295,6 @@ private:
   bool addCommonCodeGenPasses(PassManagerBase &, CodeGenOpt::Level,
                               bool DisableVerify, MCContext *&OutCtx);
 
-  virtual void setCodeModelForJIT();
-  virtual void setCodeModelForStatic();
-
 public:
   /// addPassesToEmitFile - Add passes to the specified pass manager to get the
   /// specified file emitted.  Typically this will involve several steps of code
diff --git a/include/llvm/Target/TargetOptions.h b/include/llvm/Target/TargetOptions.h
index 55d50d9..e07e8c1 100644
--- a/include/llvm/Target/TargetOptions.h
+++ b/include/llvm/Target/TargetOptions.h
@@ -158,6 +158,8 @@ namespace llvm {
   /// instead of an ISD::TRAP node.
   extern StringRef getTrapFunctionName();
 
+  extern bool EnableSegmentedStacks;
+
 } // End llvm namespace
 
 #endif
diff --git a/include/llvm/Target/TargetRegisterInfo.h b/include/llvm/Target/TargetRegisterInfo.h
index 8d827f1..682aa50 100644
--- a/include/llvm/Target/TargetRegisterInfo.h
+++ b/include/llvm/Target/TargetRegisterInfo.h
@@ -20,7 +20,6 @@
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/ADT/ArrayRef.h"
-#include "llvm/ADT/DenseSet.h"
 #include <cassert>
 #include <functional>
 
@@ -36,76 +35,75 @@ class TargetRegisterClass {
 public:
   typedef const unsigned* iterator;
   typedef const unsigned* const_iterator;
-
   typedef const EVT* vt_iterator;
   typedef const TargetRegisterClass* const * sc_iterator;
 private:
-  unsigned ID;
-  const char *Name;
+  const MCRegisterClass *MC;
   const vt_iterator VTs;
-  const sc_iterator SubClasses;
+  const unsigned *SubClassMask;
   const sc_iterator SuperClasses;
-  const sc_iterator SubRegClasses;
   const sc_iterator SuperRegClasses;
-  const unsigned RegSize, Alignment;    // Size & Alignment of register in bytes
-  const int CopyCost;
-  const bool Allocatable;
-  const iterator RegsBegin, RegsEnd;
-  DenseSet<unsigned> RegSet;
 public:
-  TargetRegisterClass(unsigned id,
-                      const char *name,
-                      const EVT *vts,
-                      const TargetRegisterClass * const *subcs,
+  TargetRegisterClass(const MCRegisterClass *MC, const EVT *vts,
+                      const unsigned *subcm,
                       const TargetRegisterClass * const *supcs,
-                      const TargetRegisterClass * const *subregcs,
-                      const TargetRegisterClass * const *superregcs,
-                      unsigned RS, unsigned Al, int CC, bool Allocable,
-                      iterator RB, iterator RE)
-    : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs),
-    SubRegClasses(subregcs), SuperRegClasses(superregcs),
-    RegSize(RS), Alignment(Al), CopyCost(CC), Allocatable(Allocable),
-    RegsBegin(RB), RegsEnd(RE) {
-      for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I)
-        RegSet.insert(*I);
-    }
+                      const TargetRegisterClass * const *superregcs)
+    : MC(MC), VTs(vts), SubClassMask(subcm), SuperClasses(supcs),
+      SuperRegClasses(superregcs) {}
+
   virtual ~TargetRegisterClass() {}     // Allow subclasses
 
   /// getID() - Return the register class ID number.
   ///
-  unsigned getID() const { return ID; }
+  unsigned getID() const { return MC->getID(); }
 
   /// getName() - Return the register class name for debugging.
   ///
-  const char *getName() const { return Name; }
+  const char *getName() const { return MC->getName(); }
 
   /// begin/end - Return all of the registers in this class.
   ///
-  iterator       begin() const { return RegsBegin; }
-  iterator         end() const { return RegsEnd; }
+  iterator       begin() const { return MC->begin(); }
+  iterator         end() const { return MC->end(); }
 
   /// getNumRegs - Return the number of registers in this class.
   ///
-  unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
+  unsigned getNumRegs() const { return MC->getNumRegs(); }
 
   /// getRegister - Return the specified register in the class.
   ///
   unsigned getRegister(unsigned i) const {
-    assert(i < getNumRegs() && "Register number out of range!");
-    return RegsBegin[i];
+    return MC->getRegister(i);
   }
 
   /// contains - Return true if the specified register is included in this
   /// register class.  This does not include virtual registers.
   bool contains(unsigned Reg) const {
-    return RegSet.count(Reg);
+    return MC->contains(Reg);
   }
 
   /// contains - Return true if both registers are in this class.
   bool contains(unsigned Reg1, unsigned Reg2) const {
-    return contains(Reg1) && contains(Reg2);
+    return MC->contains(Reg1, Reg2);
   }
 
+  /// getSize - Return the size of the register in bytes, which is also the size
+  /// of a stack slot allocated to hold a spilled copy of this register.
+  unsigned getSize() const { return MC->getSize(); }
+
+  /// getAlignment - Return the minimum required alignment for a register of
+  /// this class.
+  unsigned getAlignment() const { return MC->getAlignment(); }
+
+  /// getCopyCost - Return the cost of copying a value between two registers in
+  /// this class. A negative number means the register class is very expensive
+  /// to copy e.g. status flag register classes.
+  int getCopyCost() const { return MC->getCopyCost(); }
+
+  /// isAllocatable - Return true if this register class may be used to create
+  /// virtual registers.
+  bool isAllocatable() const { return MC->isAllocatable(); }
+
   /// hasType - return true if this TargetRegisterClass has the ValueType vt.
   ///
   bool hasType(EVT vt) const {
@@ -127,25 +125,6 @@ public:
     return I;
   }
 
-  /// subregclasses_begin / subregclasses_end - Loop over all of
-  /// the subreg register classes of this register class.
-  sc_iterator subregclasses_begin() const {
-    return SubRegClasses;
-  }
-
-  sc_iterator subregclasses_end() const {
-    sc_iterator I = SubRegClasses;
-    while (*I != NULL) ++I;
-    return I;
-  }
-
-  /// getSubRegisterRegClass - Return the register class of subregisters with
-  /// index SubIdx, or NULL if no such class exists.
-  const TargetRegisterClass* getSubRegisterRegClass(unsigned SubIdx) const {
-    assert(SubIdx>0 && "Invalid subregister index");
-    return SubRegClasses[SubIdx-1];
-  }
-
   /// superregclasses_begin / superregclasses_end - Loop over all of
   /// the superreg register classes of this register class.
   sc_iterator superregclasses_begin() const {
@@ -159,57 +138,42 @@ public:
   }
 
   /// hasSubClass - return true if the specified TargetRegisterClass
-  /// is a proper subset of this TargetRegisterClass.
-  bool hasSubClass(const TargetRegisterClass *cs) const {
-    for (int i = 0; SubClasses[i] != NULL; ++i)
-      if (SubClasses[i] == cs)
-        return true;
-    return false;
+  /// is a proper sub-class of this TargetRegisterClass.
+  bool hasSubClass(const TargetRegisterClass *RC) const {
+    return RC != this && hasSubClassEq(RC);
   }
 
-  /// hasSubClassEq - Returns true if RC is a subclass of or equal to this
+  /// hasSubClassEq - Returns true if RC is a sub-class of or equal to this
   /// class.
   bool hasSubClassEq(const TargetRegisterClass *RC) const {
-    return RC == this || hasSubClass(RC);
-  }
-
-  /// subclasses_begin / subclasses_end - Loop over all of the classes
-  /// that are proper subsets of this register class.
-  sc_iterator subclasses_begin() const {
-    return SubClasses;
-  }
-
-  sc_iterator subclasses_end() const {
-    sc_iterator I = SubClasses;
-    while (*I != NULL) ++I;
-    return I;
+    unsigned ID = RC->getID();
+    return (SubClassMask[ID / 32] >> (ID % 32)) & 1;
   }
 
   /// hasSuperClass - return true if the specified TargetRegisterClass is a
-  /// proper superset of this TargetRegisterClass.
-  bool hasSuperClass(const TargetRegisterClass *cs) const {
-    for (int i = 0; SuperClasses[i] != NULL; ++i)
-      if (SuperClasses[i] == cs)
-        return true;
-    return false;
+  /// proper super-class of this TargetRegisterClass.
+  bool hasSuperClass(const TargetRegisterClass *RC) const {
+    return RC->hasSubClass(this);
   }
 
-  /// hasSuperClassEq - Returns true if RC is a superclass of or equal to this
+  /// hasSuperClassEq - Returns true if RC is a super-class of or equal to this
   /// class.
   bool hasSuperClassEq(const TargetRegisterClass *RC) const {
-    return RC == this || hasSuperClass(RC);
+    return RC->hasSubClassEq(this);
   }
 
-  /// superclasses_begin / superclasses_end - Loop over all of the classes
-  /// that are proper supersets of this register class.
-  sc_iterator superclasses_begin() const {
-    return SuperClasses;
+  /// getSubClassMask - Returns a bit vector of subclasses, including this one.
+  /// The vector is indexed by class IDs, see hasSubClassEq() above for how to
+  /// use it.
+  const unsigned *getSubClassMask() const {
+    return SubClassMask;
   }
 
-  sc_iterator superclasses_end() const {
-    sc_iterator I = SuperClasses;
-    while (*I != NULL) ++I;
-    return I;
+  /// getSuperClasses - Returns a NULL terminated list of super-classes.  The
+  /// classes are ordered by ID which is also a topological ordering from large
+  /// to small classes.  The list does NOT include the current class.
+  sc_iterator getSuperClasses() const {
+    return SuperClasses;
   }
 
   /// isASubClass - return true if this TargetRegisterClass is a subset
@@ -234,25 +198,8 @@ public:
   ///
   virtual
   ArrayRef<unsigned> getRawAllocationOrder(const MachineFunction &MF) const {
-    return ArrayRef<unsigned>(begin(), getNumRegs());
+    return makeArrayRef(begin(), getNumRegs());
   }
-
-  /// getSize - Return the size of the register in bytes, which is also the size
-  /// of a stack slot allocated to hold a spilled copy of this register.
-  unsigned getSize() const { return RegSize; }
-
-  /// getAlignment - Return the minimum required alignment for a register of
-  /// this class.
-  unsigned getAlignment() const { return Alignment; }
-
-  /// getCopyCost - Return the cost of copying a value between two registers in
-  /// this class. A negative number means the register class is very expensive
-  /// to copy e.g. status flag register classes.
-  int getCopyCost() const { return CopyCost; }
-
-  /// isAllocatable - Return true if this register class may be used to create
-  /// virtual registers.
-  bool isAllocatable() const { return Allocatable; }
 };
 
 /// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about
@@ -461,6 +408,20 @@ public:
     return 0;
   }
 
+  /// getSubClassWithSubReg - Returns the largest legal sub-class of RC that
+  /// supports the sub-register index Idx.
+  /// If no such sub-class exists, return NULL.
+  /// If all registers in RC already have an Idx sub-register, return RC.
+  ///
+  /// TableGen generates a version of this function that is good enough in most
+  /// cases.  Targets can override if they have constraints that TableGen
+  /// doesn't understand.  For example, the x86 sub_8bit sub-register index is
+  /// supported by the full GR32 register class in 64-bit mode, but only by the
+  /// GR32_ABCD regiister class in 32-bit mode.
+  ///
+  virtual const TargetRegisterClass *
+  getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const =0;
+
   /// composeSubRegIndices - Return the subregister index you get from composing
   /// two subregister indices.
   ///
@@ -498,6 +459,12 @@ public:
     return RegClassBegin[i];
   }
 
+  /// getCommonSubClass - find the largest common subclass of A and B. Return
+  /// NULL if there is no common subclass.
+  const TargetRegisterClass *
+  getCommonSubClass(const TargetRegisterClass *A,
+                    const TargetRegisterClass *B) const;
+
   /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
   /// values.  If a target supports multiple different pointer register classes,
   /// kind specifies which one is indicated.
@@ -699,28 +666,10 @@ public:
   //===--------------------------------------------------------------------===//
   /// Debug information queries.
 
-  /// getDwarfRegNum - Map a target register to an equivalent dwarf register
-  /// number.  Returns -1 if there is no equivalent value.  The second
-  /// parameter allows targets to use different numberings for EH info and
-  /// debugging info.
-  virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
-
-  virtual int getLLVMRegNum(unsigned RegNum, bool isEH) const = 0;
-
   /// getFrameRegister - This method should return the register used as a base
   /// for values allocated in the current stack frame.
   virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;
 
-  /// getRARegister - This method should return the register where the return
-  /// address can be found.
-  virtual unsigned getRARegister() const = 0;
-
-  /// getSEHRegNum - Map a target register to an equivalent SEH register
-  /// number.  Returns -1 if there is no equivalent value.
-  virtual int getSEHRegNum(unsigned i) const {
-    return i;
-  }
-
   /// getCompactUnwindRegNum - This function maps the register to the number for
   /// compact unwind encoding. Return -1 if the register isn't valid.
   virtual int getCompactUnwindRegNum(unsigned, bool) const {
@@ -736,11 +685,6 @@ struct VirtReg2IndexFunctor : public std::unary_function<unsigned, unsigned> {
   }
 };
 
-/// getCommonSubClass - find the largest common subclass of A and B. Return NULL
-/// if there is no common subclass.
-const TargetRegisterClass *getCommonSubClass(const TargetRegisterClass *A,
-                                             const TargetRegisterClass *B);
-
 /// PrintReg - Helper class for printing registers on a raw_ostream.
 /// Prints virtual and physical registers with or without a TRI instance.
 ///
diff --git a/include/llvm/Target/TargetRegistry.h b/include/llvm/Target/TargetRegistry.h
deleted file mode 100644
index 7e0ce19..0000000
--- a/include/llvm/Target/TargetRegistry.h
+++ /dev/null
@@ -1,985 +0,0 @@
-//===-- Target/TargetRegistry.h - Target Registration -----------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file exposes the TargetRegistry interface, which tools can use to access
-// the appropriate target specific classes (TargetMachine, AsmPrinter, etc.)
-// which have been registered.
-//
-// Target specific class implementations should register themselves using the
-// appropriate TargetRegistry interfaces.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_TARGETREGISTRY_H
-#define LLVM_TARGET_TARGETREGISTRY_H
-
-#include "llvm/ADT/Triple.h"
-#include <string>
-#include <cassert>
-
-namespace llvm {
-  class AsmPrinter;
-  class Module;
-  class MCAssembler;
-  class MCAsmInfo;
-  class MCAsmParser;
-  class MCCodeEmitter;
-  class MCContext;
-  class MCDisassembler;
-  class MCInstPrinter;
-  class MCInstrInfo;
-  class MCRegisterInfo;
-  class MCStreamer;
-  class MCSubtargetInfo;
-  class TargetAsmBackend;
-  class TargetAsmLexer;
-  class TargetAsmParser;
-  class TargetMachine;
-  class raw_ostream;
-  class formatted_raw_ostream;
-
-  MCStreamer *createAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
-                                bool isVerboseAsm,
-                                bool useLoc, bool useCFI,
-                                MCInstPrinter *InstPrint,
-                                MCCodeEmitter *CE,
-                                TargetAsmBackend *TAB,
-                                bool ShowInst);
-
-  /// Target - Wrapper for Target specific information.
-  ///
-  /// For registration purposes, this is a POD type so that targets can be
-  /// registered without the use of static constructors.
-  ///
-  /// Targets should implement a single global instance of this class (which
-  /// will be zero initialized), and pass that instance to the TargetRegistry as
-  /// part of their initialization.
-  class Target {
-  public:
-    friend struct TargetRegistry;
-
-    typedef unsigned (*TripleMatchQualityFnTy)(const std::string &TT);
-
-    typedef MCAsmInfo *(*MCAsmInfoCtorFnTy)(const Target &T,
-                                            StringRef TT);
-    typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
-    typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(void);
-    typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT,
-                                                        StringRef CPU,
-                                                        StringRef Features);
-    typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T,
-                                                  const std::string &TT,
-                                                  const std::string &CPU,
-                                                  const std::string &Features);
-    typedef AsmPrinter *(*AsmPrinterCtorTy)(TargetMachine &TM,
-                                            MCStreamer &Streamer);
-    typedef TargetAsmBackend *(*AsmBackendCtorTy)(const Target &T,
-                                                  const std::string &TT);
-    typedef TargetAsmLexer *(*AsmLexerCtorTy)(const Target &T,
-                                              const MCAsmInfo &MAI);
-    typedef TargetAsmParser *(*AsmParserCtorTy)(MCSubtargetInfo &STI,
-                                                MCAsmParser &P);
-    typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T);
-    typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T,
-                                                  unsigned SyntaxVariant,
-                                                  const MCAsmInfo &MAI);
-    typedef MCCodeEmitter *(*CodeEmitterCtorTy)(const MCInstrInfo &II,
-                                                const MCSubtargetInfo &STI,
-                                                MCContext &Ctx);
-    typedef MCStreamer *(*ObjectStreamerCtorTy)(const Target &T,
-                                                const std::string &TT,
-                                                MCContext &Ctx,
-                                                TargetAsmBackend &TAB,
-                                                raw_ostream &_OS,
-                                                MCCodeEmitter *_Emitter,
-                                                bool RelaxAll,
-                                                bool NoExecStack);
-    typedef MCStreamer *(*AsmStreamerCtorTy)(MCContext &Ctx,
-                                             formatted_raw_ostream &OS,
-                                             bool isVerboseAsm,
-                                             bool useLoc,
-                                             bool useCFI,
-                                             MCInstPrinter *InstPrint,
-                                             MCCodeEmitter *CE,
-                                             TargetAsmBackend *TAB,
-                                             bool ShowInst);
-
-  private:
-    /// Next - The next registered target in the linked list, maintained by the
-    /// TargetRegistry.
-    Target *Next;
-
-    /// TripleMatchQualityFn - The target function for rating the match quality
-    /// of a triple.
-    TripleMatchQualityFnTy TripleMatchQualityFn;
-
-    /// Name - The target name.
-    const char *Name;
-
-    /// ShortDesc - A short description of the target.
-    const char *ShortDesc;
-
-    /// HasJIT - Whether this target supports the JIT.
-    bool HasJIT;
-
-    /// MCAsmInfoCtorFn - Constructor function for this target's MCAsmInfo, if
-    /// registered.
-    MCAsmInfoCtorFnTy MCAsmInfoCtorFn;
-
-    /// MCInstrInfoCtorFn - Constructor function for this target's MCInstrInfo,
-    /// if registered.
-    MCInstrInfoCtorFnTy MCInstrInfoCtorFn;
-
-    /// MCRegInfoCtorFn - Constructor function for this target's MCRegisterInfo,
-    /// if registered.
-    MCRegInfoCtorFnTy MCRegInfoCtorFn;
-
-    /// MCSubtargetInfoCtorFn - Constructor function for this target's
-    /// MCSubtargetInfo, if registered.
-    MCSubtargetInfoCtorFnTy MCSubtargetInfoCtorFn;
-
-    /// TargetMachineCtorFn - Construction function for this target's
-    /// TargetMachine, if registered.
-    TargetMachineCtorTy TargetMachineCtorFn;
-
-    /// AsmBackendCtorFn - Construction function for this target's
-    /// TargetAsmBackend, if registered.
-    AsmBackendCtorTy AsmBackendCtorFn;
-
-    /// AsmLexerCtorFn - Construction function for this target's TargetAsmLexer,
-    /// if registered.
-    AsmLexerCtorTy AsmLexerCtorFn;
-
-    /// AsmParserCtorFn - Construction function for this target's
-    /// TargetAsmParser, if registered.
-    AsmParserCtorTy AsmParserCtorFn;
-
-    /// AsmPrinterCtorFn - Construction function for this target's AsmPrinter,
-    /// if registered.
-    AsmPrinterCtorTy AsmPrinterCtorFn;
-
-    /// MCDisassemblerCtorFn - Construction function for this target's
-    /// MCDisassembler, if registered.
-    MCDisassemblerCtorTy MCDisassemblerCtorFn;
-
-    /// MCInstPrinterCtorFn - Construction function for this target's
-    /// MCInstPrinter, if registered.
-    MCInstPrinterCtorTy MCInstPrinterCtorFn;
-
-    /// CodeEmitterCtorFn - Construction function for this target's CodeEmitter,
-    /// if registered.
-    CodeEmitterCtorTy CodeEmitterCtorFn;
-
-    /// ObjectStreamerCtorFn - Construction function for this target's
-    /// ObjectStreamer, if registered.
-    ObjectStreamerCtorTy ObjectStreamerCtorFn;
-
-    /// AsmStreamerCtorFn - Construction function for this target's
-    /// AsmStreamer, if registered (default = llvm::createAsmStreamer).
-    AsmStreamerCtorTy AsmStreamerCtorFn;
-
-  public:
-    Target() : AsmStreamerCtorFn(llvm::createAsmStreamer) {}
-
-    /// @name Target Information
-    /// @{
-
-    // getNext - Return the next registered target.
-    const Target *getNext() const { return Next; }
-
-    /// getName - Get the target name.
-    const char *getName() const { return Name; }
-
-    /// getShortDescription - Get a short description of the target.
-    const char *getShortDescription() const { return ShortDesc; }
-
-    /// @}
-    /// @name Feature Predicates
-    /// @{
-
-    /// hasJIT - Check if this targets supports the just-in-time compilation.
-    bool hasJIT() const { return HasJIT; }
-
-    /// hasTargetMachine - Check if this target supports code generation.
-    bool hasTargetMachine() const { return TargetMachineCtorFn != 0; }
-
-    /// hasAsmBackend - Check if this target supports .o generation.
-    bool hasAsmBackend() const { return AsmBackendCtorFn != 0; }
-
-    /// hasAsmLexer - Check if this target supports .s lexing.
-    bool hasAsmLexer() const { return AsmLexerCtorFn != 0; }
-
-    /// hasAsmParser - Check if this target supports .s parsing.
-    bool hasAsmParser() const { return AsmParserCtorFn != 0; }
-
-    /// hasAsmPrinter - Check if this target supports .s printing.
-    bool hasAsmPrinter() const { return AsmPrinterCtorFn != 0; }
-
-    /// hasMCDisassembler - Check if this target has a disassembler.
-    bool hasMCDisassembler() const { return MCDisassemblerCtorFn != 0; }
-
-    /// hasMCInstPrinter - Check if this target has an instruction printer.
-    bool hasMCInstPrinter() const { return MCInstPrinterCtorFn != 0; }
-
-    /// hasCodeEmitter - Check if this target supports instruction encoding.
-    bool hasCodeEmitter() const { return CodeEmitterCtorFn != 0; }
-
-    /// hasObjectStreamer - Check if this target supports streaming to files.
-    bool hasObjectStreamer() const { return ObjectStreamerCtorFn != 0; }
-
-    /// hasAsmStreamer - Check if this target supports streaming to files.
-    bool hasAsmStreamer() const { return AsmStreamerCtorFn != 0; }
-
-    /// @}
-    /// @name Feature Constructors
-    /// @{
-
-    /// createMCAsmInfo - Create a MCAsmInfo implementation for the specified
-    /// target triple.
-    ///
-    /// \arg Triple - This argument is used to determine the target machine
-    /// feature set; it should always be provided. Generally this should be
-    /// either the target triple from the module, or the target triple of the
-    /// host if that does not exist.
-    MCAsmInfo *createMCAsmInfo(StringRef Triple) const {
-      if (!MCAsmInfoCtorFn)
-        return 0;
-      return MCAsmInfoCtorFn(*this, Triple);
-    }
-
-    /// createMCInstrInfo - Create a MCInstrInfo implementation.
-    ///
-    MCInstrInfo *createMCInstrInfo() const {
-      if (!MCInstrInfoCtorFn)
-        return 0;
-      return MCInstrInfoCtorFn();
-    }
-
-    /// createMCRegInfo - Create a MCRegisterInfo implementation.
-    ///
-    MCRegisterInfo *createMCRegInfo() const {
-      if (!MCRegInfoCtorFn)
-        return 0;
-      return MCRegInfoCtorFn();
-    }
-
-    /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
-    ///
-    /// \arg Triple - This argument is used to determine the target machine
-    /// feature set; it should always be provided. Generally this should be
-    /// either the target triple from the module, or the target triple of the
-    /// host if that does not exist.
-    /// \arg CPU - This specifies the name of the target CPU.
-    /// \arg Features - This specifies the string representation of the
-    /// additional target features.
-    MCSubtargetInfo *createMCSubtargetInfo(StringRef Triple, StringRef CPU,
-                                           StringRef Features) const {
-      if (!MCSubtargetInfoCtorFn)
-        return 0;
-      return MCSubtargetInfoCtorFn(Triple, CPU, Features);
-    }
-
-    /// createTargetMachine - Create a target specific machine implementation
-    /// for the specified \arg Triple.
-    ///
-    /// \arg Triple - This argument is used to determine the target machine
-    /// feature set; it should always be provided. Generally this should be
-    /// either the target triple from the module, or the target triple of the
-    /// host if that does not exist.
-    TargetMachine *createTargetMachine(const std::string &Triple,
-                                       const std::string &CPU,
-                                       const std::string &Features) const {
-      if (!TargetMachineCtorFn)
-        return 0;
-      return TargetMachineCtorFn(*this, Triple, CPU, Features);
-    }
-
-    /// createAsmBackend - Create a target specific assembly parser.
-    ///
-    /// \arg Triple - The target triple string.
-    /// \arg Backend - The target independent assembler object.
-    TargetAsmBackend *createAsmBackend(const std::string &Triple) const {
-      if (!AsmBackendCtorFn)
-        return 0;
-      return AsmBackendCtorFn(*this, Triple);
-    }
-
-    /// createAsmLexer - Create a target specific assembly lexer.
-    ///
-    TargetAsmLexer *createAsmLexer(const MCAsmInfo &MAI) const {
-      if (!AsmLexerCtorFn)
-        return 0;
-      return AsmLexerCtorFn(*this, MAI);
-    }
-
-    /// createAsmParser - Create a target specific assembly parser.
-    ///
-    /// \arg Parser - The target independent parser implementation to use for
-    /// parsing and lexing.
-    TargetAsmParser *createAsmParser(MCSubtargetInfo &STI,
-                                     MCAsmParser &Parser) const {
-      if (!AsmParserCtorFn)
-        return 0;
-      return AsmParserCtorFn(STI, Parser);
-    }
-
-    /// createAsmPrinter - Create a target specific assembly printer pass.  This
-    /// takes ownership of the MCStreamer object.
-    AsmPrinter *createAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) const{
-      if (!AsmPrinterCtorFn)
-        return 0;
-      return AsmPrinterCtorFn(TM, Streamer);
-    }
-
-    MCDisassembler *createMCDisassembler() const {
-      if (!MCDisassemblerCtorFn)
-        return 0;
-      return MCDisassemblerCtorFn(*this);
-    }
-
-    MCInstPrinter *createMCInstPrinter(unsigned SyntaxVariant,
-                                       const MCAsmInfo &MAI) const {
-      if (!MCInstPrinterCtorFn)
-        return 0;
-      return MCInstPrinterCtorFn(*this, SyntaxVariant, MAI);
-    }
-
-
-    /// createCodeEmitter - Create a target specific code emitter.
-    MCCodeEmitter *createCodeEmitter(const MCInstrInfo &II,
-                                     const MCSubtargetInfo &STI,
-                                     MCContext &Ctx) const {
-      if (!CodeEmitterCtorFn)
-        return 0;
-      return CodeEmitterCtorFn(II, STI, Ctx);
-    }
-
-    /// createObjectStreamer - Create a target specific MCStreamer.
-    ///
-    /// \arg TT - The target triple.
-    /// \arg Ctx - The target context.
-    /// \arg TAB - The target assembler backend object. Takes ownership.
-    /// \arg _OS - The stream object.
-    /// \arg _Emitter - The target independent assembler object.Takes ownership.
-    /// \arg RelaxAll - Relax all fixups?
-    /// \arg NoExecStack - Mark file as not needing a executable stack.
-    MCStreamer *createObjectStreamer(const std::string &TT, MCContext &Ctx,
-                                     TargetAsmBackend &TAB,
-                                     raw_ostream &_OS,
-                                     MCCodeEmitter *_Emitter,
-                                     bool RelaxAll,
-                                     bool NoExecStack) const {
-      if (!ObjectStreamerCtorFn)
-        return 0;
-      return ObjectStreamerCtorFn(*this, TT, Ctx, TAB, _OS, _Emitter, RelaxAll,
-                                  NoExecStack);
-    }
-
-    /// createAsmStreamer - Create a target specific MCStreamer.
-    MCStreamer *createAsmStreamer(MCContext &Ctx,
-                                  formatted_raw_ostream &OS,
-                                  bool isVerboseAsm,
-                                  bool useLoc,
-                                  bool useCFI,
-                                  MCInstPrinter *InstPrint,
-                                  MCCodeEmitter *CE,
-                                  TargetAsmBackend *TAB,
-                                  bool ShowInst) const {
-      // AsmStreamerCtorFn is default to llvm::createAsmStreamer
-      return AsmStreamerCtorFn(Ctx, OS, isVerboseAsm, useLoc, useCFI,
-                               InstPrint, CE, TAB, ShowInst);
-    }
-
-    /// @}
-  };
-
-  /// TargetRegistry - Generic interface to target specific features.
-  struct TargetRegistry {
-    class iterator {
-      const Target *Current;
-      explicit iterator(Target *T) : Current(T) {}
-      friend struct TargetRegistry;
-    public:
-      iterator(const iterator &I) : Current(I.Current) {}
-      iterator() : Current(0) {}
-
-      bool operator==(const iterator &x) const {
-        return Current == x.Current;
-      }
-      bool operator!=(const iterator &x) const {
-        return !operator==(x);
-      }
-
-      // Iterator traversal: forward iteration only
-      iterator &operator++() {          // Preincrement
-        assert(Current && "Cannot increment end iterator!");
-        Current = Current->getNext();
-        return *this;
-      }
-      iterator operator++(int) {        // Postincrement
-        iterator tmp = *this;
-        ++*this;
-        return tmp;
-      }
-
-      const Target &operator*() const {
-        assert(Current && "Cannot dereference end iterator!");
-        return *Current;
-      }
-
-      const Target *operator->() const {
-        return &operator*();
-      }
-    };
-
-    /// @name Registry Access
-    /// @{
-
-    static iterator begin();
-
-    static iterator end() { return iterator(); }
-
-    /// lookupTarget - Lookup a target based on a target triple.
-    ///
-    /// \param Triple - The triple to use for finding a target.
-    /// \param Error - On failure, an error string describing why no target was
-    /// found.
-    static const Target *lookupTarget(const std::string &Triple,
-                                      std::string &Error);
-
-    /// getClosestTargetForJIT - Pick the best target that is compatible with
-    /// the current host.  If no close target can be found, this returns null
-    /// and sets the Error string to a reason.
-    ///
-    /// Maintained for compatibility through 2.6.
-    static const Target *getClosestTargetForJIT(std::string &Error);
-
-    /// @}
-    /// @name Target Registration
-    /// @{
-
-    /// RegisterTarget - Register the given target. Attempts to register a
-    /// target which has already been registered will be ignored.
-    ///
-    /// Clients are responsible for ensuring that registration doesn't occur
-    /// while another thread is attempting to access the registry. Typically
-    /// this is done by initializing all targets at program startup.
-    ///
-    /// @param T - The target being registered.
-    /// @param Name - The target name. This should be a static string.
-    /// @param ShortDesc - A short target description. This should be a static
-    /// string.
-    /// @param TQualityFn - The triple match quality computation function for
-    /// this target.
-    /// @param HasJIT - Whether the target supports JIT code
-    /// generation.
-    static void RegisterTarget(Target &T,
-                               const char *Name,
-                               const char *ShortDesc,
-                               Target::TripleMatchQualityFnTy TQualityFn,
-                               bool HasJIT = false);
-
-    /// RegisterMCAsmInfo - Register a MCAsmInfo implementation for the
-    /// given target.
-    ///
-    /// Clients are responsible for ensuring that registration doesn't occur
-    /// while another thread is attempting to access the registry. Typically
-    /// this is done by initializing all targets at program startup.
-    ///
-    /// @param T - The target being registered.
-    /// @param Fn - A function to construct a MCAsmInfo for the target.
-    static void RegisterMCAsmInfo(Target &T, Target::MCAsmInfoCtorFnTy Fn) {
-      // Ignore duplicate registration.
-      if (!T.MCAsmInfoCtorFn)
-        T.MCAsmInfoCtorFn = Fn;
-    }
-
-    /// RegisterMCInstrInfo - Register a MCInstrInfo implementation for the
-    /// given target.
-    ///
-    /// Clients are responsible for ensuring that registration doesn't occur
-    /// while another thread is attempting to access the registry. Typically
-    /// this is done by initializing all targets at program startup.
-    ///
-    /// @param T - The target being registered.
-    /// @param Fn - A function to construct a MCInstrInfo for the target.
-    static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn) {
-      // Ignore duplicate registration.
-      if (!T.MCInstrInfoCtorFn)
-        T.MCInstrInfoCtorFn = Fn;
-    }
-
-    /// RegisterMCRegInfo - Register a MCRegisterInfo implementation for the
-    /// given target.
-    ///
-    /// Clients are responsible for ensuring that registration doesn't occur
-    /// while another thread is attempting to access the registry. Typically
-    /// this is done by initializing all targets at program startup.
-    ///
-    /// @param T - The target being registered.
-    /// @param Fn - A function to construct a MCRegisterInfo for the target.
-    static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn) {
-      // Ignore duplicate registration.
-      if (!T.MCRegInfoCtorFn)
-        T.MCRegInfoCtorFn = Fn;
-    }
-
-    /// RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for
-    /// the given target.
-    ///
-    /// Clients are responsible for ensuring that registration doesn't occur
-    /// while another thread is attempting to access the registry. Typically
-    /// this is done by initializing all targets at program startup.
-    ///
-    /// @param T - The target being registered.
-    /// @param Fn - A function to construct a MCSubtargetInfo for the target.
-    static void RegisterMCSubtargetInfo(Target &T,
-                                        Target::MCSubtargetInfoCtorFnTy Fn) {
-      // Ignore duplicate registration.
-      if (!T.MCSubtargetInfoCtorFn)
-        T.MCSubtargetInfoCtorFn = Fn;
-    }
-
-    /// RegisterTargetMachine - Register a TargetMachine implementation for the
-    /// given target.
-    ///
-    /// Clients are responsible for ensuring that registration doesn't occur
-    /// while another thread is attempting to access the registry. Typically
-    /// this is done by initializing all targets at program startup.
-    ///
-    /// @param T - The target being registered.
-    /// @param Fn - A function to construct a TargetMachine for the target.
-    static void RegisterTargetMachine(Target &T,
-                                      Target::TargetMachineCtorTy Fn) {
-      // Ignore duplicate registration.
-      if (!T.TargetMachineCtorFn)
-        T.TargetMachineCtorFn = Fn;
-    }
-
-    /// RegisterAsmBackend - Register a TargetAsmBackend implementation for the
-    /// given target.
-    ///
-    /// Clients are responsible for ensuring that registration doesn't occur
-    /// while another thread is attempting to access the registry. Typically
-    /// this is done by initializing all targets at program startup.
-    ///
-    /// @param T - The target being registered.
-    /// @param Fn - A function to construct an AsmBackend for the target.
-    static void RegisterAsmBackend(Target &T, Target::AsmBackendCtorTy Fn) {
-      if (!T.AsmBackendCtorFn)
-        T.AsmBackendCtorFn = Fn;
-    }
-
-    /// RegisterAsmLexer - Register a TargetAsmLexer implementation for the
-    /// given target.
-    ///
-    /// Clients are responsible for ensuring that registration doesn't occur
-    /// while another thread is attempting to access the registry. Typically
-    /// this is done by initializing all targets at program startup.
-    ///
-    /// @param T - The target being registered.
-    /// @param Fn - A function to construct an AsmLexer for the target.
-    static void RegisterAsmLexer(Target &T, Target::AsmLexerCtorTy Fn) {
-      if (!T.AsmLexerCtorFn)
-        T.AsmLexerCtorFn = Fn;
-    }
-
-    /// RegisterAsmParser - Register a TargetAsmParser implementation for the
-    /// given target.
-    ///
-    /// Clients are responsible for ensuring that registration doesn't occur
-    /// while another thread is attempting to access the registry. Typically
-    /// this is done by initializing all targets at program startup.
-    ///
-    /// @param T - The target being registered.
-    /// @param Fn - A function to construct an AsmParser for the target.
-    static void RegisterAsmParser(Target &T, Target::AsmParserCtorTy Fn) {
-      if (!T.AsmParserCtorFn)
-        T.AsmParserCtorFn = Fn;
-    }
-
-    /// RegisterAsmPrinter - Register an AsmPrinter implementation for the given
-    /// target.
-    ///
-    /// Clients are responsible for ensuring that registration doesn't occur
-    /// while another thread is attempting to access the registry. Typically
-    /// this is done by initializing all targets at program startup.
-    ///
-    /// @param T - The target being registered.
-    /// @param Fn - A function to construct an AsmPrinter for the target.
-    static void RegisterAsmPrinter(Target &T, Target::AsmPrinterCtorTy Fn) {
-      // Ignore duplicate registration.
-      if (!T.AsmPrinterCtorFn)
-        T.AsmPrinterCtorFn = Fn;
-    }
-
-    /// RegisterMCDisassembler - Register a MCDisassembler implementation for
-    /// the given target.
-    ///
-    /// Clients are responsible for ensuring that registration doesn't occur
-    /// while another thread is attempting to access the registry. Typically
-    /// this is done by initializing all targets at program startup.
-    ///
-    /// @param T - The target being registered.
-    /// @param Fn - A function to construct an MCDisassembler for the target.
-    static void RegisterMCDisassembler(Target &T,
-                                       Target::MCDisassemblerCtorTy Fn) {
-      if (!T.MCDisassemblerCtorFn)
-        T.MCDisassemblerCtorFn = Fn;
-    }
-
-    /// RegisterMCInstPrinter - Register a MCInstPrinter implementation for the
-    /// given target.
-    ///
-    /// Clients are responsible for ensuring that registration doesn't occur
-    /// while another thread is attempting to access the registry. Typically
-    /// this is done by initializing all targets at program startup.
-    ///
-    /// @param T - The target being registered.
-    /// @param Fn - A function to construct an MCInstPrinter for the target.
-    static void RegisterMCInstPrinter(Target &T,
-                                      Target::MCInstPrinterCtorTy Fn) {
-      if (!T.MCInstPrinterCtorFn)
-        T.MCInstPrinterCtorFn = Fn;
-    }
-
-    /// RegisterCodeEmitter - Register a MCCodeEmitter implementation for the
-    /// given target.
-    ///
-    /// Clients are responsible for ensuring that registration doesn't occur
-    /// while another thread is attempting to access the registry. Typically
-    /// this is done by initializing all targets at program startup.
-    ///
-    /// @param T - The target being registered.
-    /// @param Fn - A function to construct an MCCodeEmitter for the target.
-    static void RegisterCodeEmitter(Target &T, Target::CodeEmitterCtorTy Fn) {
-      if (!T.CodeEmitterCtorFn)
-        T.CodeEmitterCtorFn = Fn;
-    }
-
-    /// RegisterObjectStreamer - Register a object code MCStreamer implementation
-    /// for the given target.
-    ///
-    /// Clients are responsible for ensuring that registration doesn't occur
-    /// while another thread is attempting to access the registry. Typically
-    /// this is done by initializing all targets at program startup.
-    ///
-    /// @param T - The target being registered.
-    /// @param Fn - A function to construct an MCStreamer for the target.
-    static void RegisterObjectStreamer(Target &T, Target::ObjectStreamerCtorTy Fn) {
-      if (!T.ObjectStreamerCtorFn)
-        T.ObjectStreamerCtorFn = Fn;
-    }
-
-    /// RegisterAsmStreamer - Register an assembly MCStreamer implementation
-    /// for the given target.
-    ///
-    /// Clients are responsible for ensuring that registration doesn't occur
-    /// while another thread is attempting to access the registry. Typically
-    /// this is done by initializing all targets at program startup.
-    ///
-    /// @param T - The target being registered.
-    /// @param Fn - A function to construct an MCStreamer for the target.
-    static void RegisterAsmStreamer(Target &T, Target::AsmStreamerCtorTy Fn) {
-      if (T.AsmStreamerCtorFn == createAsmStreamer)
-        T.AsmStreamerCtorFn = Fn;
-    }
-
-    /// @}
-  };
-
-
-  //===--------------------------------------------------------------------===//
-
-  /// RegisterTarget - Helper template for registering a target, for use in the
-  /// target's initialization function. Usage:
-  ///
-  ///
-  /// Target TheFooTarget; // The global target instance.
-  ///
-  /// extern "C" void LLVMInitializeFooTargetInfo() {
-  ///   RegisterTarget<Triple::foo> X(TheFooTarget, "foo", "Foo description");
-  /// }
-  template<Triple::ArchType TargetArchType = Triple::InvalidArch,
-           bool HasJIT = false>
-  struct RegisterTarget {
-    RegisterTarget(Target &T, const char *Name, const char *Desc) {
-      TargetRegistry::RegisterTarget(T, Name, Desc,
-                                     &getTripleMatchQuality,
-                                     HasJIT);
-    }
-
-    static unsigned getTripleMatchQuality(const std::string &TT) {
-      if (Triple(TT).getArch() == TargetArchType)
-        return 20;
-      return 0;
-    }
-  };
-
-  /// RegisterMCAsmInfo - Helper template for registering a target assembly info
-  /// implementation.  This invokes the static "Create" method on the class to
-  /// actually do the construction.  Usage:
-  ///
-  /// extern "C" void LLVMInitializeFooTarget() {
-  ///   extern Target TheFooTarget;
-  ///   RegisterMCAsmInfo<FooMCAsmInfo> X(TheFooTarget);
-  /// }
-  template<class MCAsmInfoImpl>
-  struct RegisterMCAsmInfo {
-    RegisterMCAsmInfo(Target &T) {
-      TargetRegistry::RegisterMCAsmInfo(T, &Allocator);
-    }
-  private:
-    static MCAsmInfo *Allocator(const Target &T, StringRef TT) {
-      return new MCAsmInfoImpl(T, TT);
-    }
-
-  };
-
-  /// RegisterMCAsmInfoFn - Helper template for registering a target assembly info
-  /// implementation.  This invokes the specified function to do the
-  /// construction.  Usage:
-  ///
-  /// extern "C" void LLVMInitializeFooTarget() {
-  ///   extern Target TheFooTarget;
-  ///   RegisterMCAsmInfoFn X(TheFooTarget, TheFunction);
-  /// }
-  struct RegisterMCAsmInfoFn {
-    RegisterMCAsmInfoFn(Target &T, Target::MCAsmInfoCtorFnTy Fn) {
-      TargetRegistry::RegisterMCAsmInfo(T, Fn);
-    }
-  };
-
-  /// RegisterMCInstrInfo - Helper template for registering a target instruction
-  /// info implementation.  This invokes the static "Create" method on the class
-  /// to actually do the construction.  Usage:
-  ///
-  /// extern "C" void LLVMInitializeFooTarget() {
-  ///   extern Target TheFooTarget;
-  ///   RegisterMCInstrInfo<FooMCInstrInfo> X(TheFooTarget);
-  /// }
-  template<class MCInstrInfoImpl>
-  struct RegisterMCInstrInfo {
-    RegisterMCInstrInfo(Target &T) {
-      TargetRegistry::RegisterMCInstrInfo(T, &Allocator);
-    }
-  private:
-    static MCInstrInfo *Allocator() {
-      return new MCInstrInfoImpl();
-    }
-  };
-
-  /// RegisterMCInstrInfoFn - Helper template for registering a target
-  /// instruction info implementation.  This invokes the specified function to
-  /// do the construction.  Usage:
-  ///
-  /// extern "C" void LLVMInitializeFooTarget() {
-  ///   extern Target TheFooTarget;
-  ///   RegisterMCInstrInfoFn X(TheFooTarget, TheFunction);
-  /// }
-  struct RegisterMCInstrInfoFn {
-    RegisterMCInstrInfoFn(Target &T, Target::MCInstrInfoCtorFnTy Fn) {
-      TargetRegistry::RegisterMCInstrInfo(T, Fn);
-    }
-  };
-
-  /// RegisterMCRegInfo - Helper template for registering a target register info
-  /// implementation.  This invokes the static "Create" method on the class to
-  /// actually do the construction.  Usage:
-  ///
-  /// extern "C" void LLVMInitializeFooTarget() {
-  ///   extern Target TheFooTarget;
-  ///   RegisterMCRegInfo<FooMCRegInfo> X(TheFooTarget);
-  /// }
-  template<class MCRegisterInfoImpl>
-  struct RegisterMCRegInfo {
-    RegisterMCRegInfo(Target &T) {
-      TargetRegistry::RegisterMCRegInfo(T, &Allocator);
-    }
-  private:
-    static MCRegisterInfo *Allocator() {
-      return new MCRegisterInfoImpl();
-    }
-  };
-
-  /// RegisterMCRegInfoFn - Helper template for registering a target register
-  /// info implementation.  This invokes the specified function to do the
-  /// construction.  Usage:
-  ///
-  /// extern "C" void LLVMInitializeFooTarget() {
-  ///   extern Target TheFooTarget;
-  ///   RegisterMCRegInfoFn X(TheFooTarget, TheFunction);
-  /// }
-  struct RegisterMCRegInfoFn {
-    RegisterMCRegInfoFn(Target &T, Target::MCRegInfoCtorFnTy Fn) {
-      TargetRegistry::RegisterMCRegInfo(T, Fn);
-    }
-  };
-
-  /// RegisterMCSubtargetInfo - Helper template for registering a target
-  /// subtarget info implementation.  This invokes the static "Create" method
-  /// on the class to actually do the construction.  Usage:
-  ///
-  /// extern "C" void LLVMInitializeFooTarget() {
-  ///   extern Target TheFooTarget;
-  ///   RegisterMCSubtargetInfo<FooMCSubtargetInfo> X(TheFooTarget);
-  /// }
-  template<class MCSubtargetInfoImpl>
-  struct RegisterMCSubtargetInfo {
-    RegisterMCSubtargetInfo(Target &T) {
-      TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator);
-    }
-  private:
-    static MCSubtargetInfo *Allocator(StringRef TT, StringRef CPU,
-                                      StringRef FS) {
-      return new MCSubtargetInfoImpl();
-    }
-  };
-
-  /// RegisterMCSubtargetInfoFn - Helper template for registering a target
-  /// subtarget info implementation.  This invokes the specified function to
-  /// do the construction.  Usage:
-  ///
-  /// extern "C" void LLVMInitializeFooTarget() {
-  ///   extern Target TheFooTarget;
-  ///   RegisterMCSubtargetInfoFn X(TheFooTarget, TheFunction);
-  /// }
-  struct RegisterMCSubtargetInfoFn {
-    RegisterMCSubtargetInfoFn(Target &T, Target::MCSubtargetInfoCtorFnTy Fn) {
-      TargetRegistry::RegisterMCSubtargetInfo(T, Fn);
-    }
-  };
-
-  /// RegisterTargetMachine - Helper template for registering a target machine
-  /// implementation, for use in the target machine initialization
-  /// function. Usage:
-  ///
-  /// extern "C" void LLVMInitializeFooTarget() {
-  ///   extern Target TheFooTarget;
-  ///   RegisterTargetMachine<FooTargetMachine> X(TheFooTarget);
-  /// }
-  template<class TargetMachineImpl>
-  struct RegisterTargetMachine {
-    RegisterTargetMachine(Target &T) {
-      TargetRegistry::RegisterTargetMachine(T, &Allocator);
-    }
-
-  private:
-    static TargetMachine *Allocator(const Target &T, const std::string &TT,
-                                    const std::string &CPU,
-                                    const std::string &FS) {
-      return new TargetMachineImpl(T, TT, CPU, FS);
-    }
-  };
-
-  /// RegisterAsmBackend - Helper template for registering a target specific
-  /// assembler backend. Usage:
-  ///
-  /// extern "C" void LLVMInitializeFooAsmBackend() {
-  ///   extern Target TheFooTarget;
-  ///   RegisterAsmBackend<FooAsmLexer> X(TheFooTarget);
-  /// }
-  template<class AsmBackendImpl>
-  struct RegisterAsmBackend {
-    RegisterAsmBackend(Target &T) {
-      TargetRegistry::RegisterAsmBackend(T, &Allocator);
-    }
-
-  private:
-    static TargetAsmBackend *Allocator(const Target &T,
-                                       const std::string &Triple) {
-      return new AsmBackendImpl(T, Triple);
-    }
-  };
-
-  /// RegisterAsmLexer - Helper template for registering a target specific
-  /// assembly lexer, for use in the target machine initialization
-  /// function. Usage:
-  ///
-  /// extern "C" void LLVMInitializeFooAsmLexer() {
-  ///   extern Target TheFooTarget;
-  ///   RegisterAsmLexer<FooAsmLexer> X(TheFooTarget);
-  /// }
-  template<class AsmLexerImpl>
-  struct RegisterAsmLexer {
-    RegisterAsmLexer(Target &T) {
-      TargetRegistry::RegisterAsmLexer(T, &Allocator);
-    }
-
-  private:
-    static TargetAsmLexer *Allocator(const Target &T, const MCAsmInfo &MAI) {
-      return new AsmLexerImpl(T, MAI);
-    }
-  };
-
-  /// RegisterAsmParser - Helper template for registering a target specific
-  /// assembly parser, for use in the target machine initialization
-  /// function. Usage:
-  ///
-  /// extern "C" void LLVMInitializeFooAsmParser() {
-  ///   extern Target TheFooTarget;
-  ///   RegisterAsmParser<FooAsmParser> X(TheFooTarget);
-  /// }
-  template<class AsmParserImpl>
-  struct RegisterAsmParser {
-    RegisterAsmParser(Target &T) {
-      TargetRegistry::RegisterAsmParser(T, &Allocator);
-    }
-
-  private:
-    static TargetAsmParser *Allocator(MCSubtargetInfo &STI, MCAsmParser &P) {
-      return new AsmParserImpl(STI, P);
-    }
-  };
-
-  /// RegisterAsmPrinter - Helper template for registering a target specific
-  /// assembly printer, for use in the target machine initialization
-  /// function. Usage:
-  ///
-  /// extern "C" void LLVMInitializeFooAsmPrinter() {
-  ///   extern Target TheFooTarget;
-  ///   RegisterAsmPrinter<FooAsmPrinter> X(TheFooTarget);
-  /// }
-  template<class AsmPrinterImpl>
-  struct RegisterAsmPrinter {
-    RegisterAsmPrinter(Target &T) {
-      TargetRegistry::RegisterAsmPrinter(T, &Allocator);
-    }
-
-  private:
-    static AsmPrinter *Allocator(TargetMachine &TM, MCStreamer &Streamer) {
-      return new AsmPrinterImpl(TM, Streamer);
-    }
-  };
-
-  /// RegisterCodeEmitter - Helper template for registering a target specific
-  /// machine code emitter, for use in the target initialization
-  /// function. Usage:
-  ///
-  /// extern "C" void LLVMInitializeFooCodeEmitter() {
-  ///   extern Target TheFooTarget;
-  ///   RegisterCodeEmitter<FooCodeEmitter> X(TheFooTarget);
-  /// }
-  template<class CodeEmitterImpl>
-  struct RegisterCodeEmitter {
-    RegisterCodeEmitter(Target &T) {
-      TargetRegistry::RegisterCodeEmitter(T, &Allocator);
-    }
-
-  private:
-    static MCCodeEmitter *Allocator(const MCInstrInfo &II,
-                                    const MCSubtargetInfo &STI,
-                                    MCContext &Ctx) {
-      return new CodeEmitterImpl();
-    }
-  };
-
-}
-
-#endif
diff --git a/include/llvm/Target/TargetSelect.h b/include/llvm/Target/TargetSelect.h
deleted file mode 100644
index 272ee09..0000000
--- a/include/llvm/Target/TargetSelect.h
+++ /dev/null
@@ -1,184 +0,0 @@
-//===- TargetSelect.h - Target Selection & Registration ---------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file provides utilities to make sure that certain classes of targets are
-// linked into the main application executable, and initialize them as
-// appropriate.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_TARGETSELECT_H
-#define LLVM_TARGET_TARGETSELECT_H
-
-#include "llvm/Config/llvm-config.h"
-
-extern "C" {
-  // Declare all of the target-initialization functions that are available.
-#define LLVM_TARGET(TargetName) void LLVMInitialize##TargetName##TargetInfo();
-#include "llvm/Config/Targets.def"
-
-#define LLVM_TARGET(TargetName) void LLVMInitialize##TargetName##Target();
-#include "llvm/Config/Targets.def"
-  
-#define LLVM_TARGET(TargetName) \
-  void LLVMInitialize##TargetName##MCAsmInfo();
-#include "llvm/Config/Targets.def"
-
-#define LLVM_TARGET(TargetName) \
-  void LLVMInitialize##TargetName##MCInstrInfo();
-#include "llvm/Config/Targets.def"
-
-#define LLVM_TARGET(TargetName) \
-  void LLVMInitialize##TargetName##MCSubtargetInfo();
-#include "llvm/Config/Targets.def"
-
-  // Declare all of the available assembly printer initialization functions.
-#define LLVM_ASM_PRINTER(TargetName) void LLVMInitialize##TargetName##AsmPrinter();
-#include "llvm/Config/AsmPrinters.def"
-
-  // Declare all of the available assembly parser initialization functions.
-#define LLVM_ASM_PARSER(TargetName) void LLVMInitialize##TargetName##AsmParser();
-#include "llvm/Config/AsmParsers.def"
-
-  // Declare all of the available disassembler initialization functions.
-#define LLVM_DISASSEMBLER(TargetName) \
-  void LLVMInitialize##TargetName##Disassembler();
-#include "llvm/Config/Disassemblers.def"
-}
-
-namespace llvm {
-  /// InitializeAllTargetInfos - The main program should call this function if
-  /// it wants access to all available targets that LLVM is configured to
-  /// support, to make them available via the TargetRegistry.
-  ///
-  /// It is legal for a client to make multiple calls to this function.
-  inline void InitializeAllTargetInfos() {
-#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##TargetInfo();
-#include "llvm/Config/Targets.def"
-  }
-  
-  /// InitializeAllTargets - The main program should call this function if it
-  /// wants access to all available target machines that LLVM is configured to
-  /// support, to make them available via the TargetRegistry.
-  ///
-  /// It is legal for a client to make multiple calls to this function.
-  inline void InitializeAllTargets() {
-    // FIXME: Remove this, clients should do it.
-    InitializeAllTargetInfos();
-
-#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##Target();
-#include "llvm/Config/Targets.def"
-  }
-  
-  /// InitializeAllMCAsmInfos - The main program should call this function
-  /// if it wants access to all available assembly infos for targets that
-  /// LLVM is configured to support, to make them available via the
-  /// TargetRegistry.
-  ///
-  /// It is legal for a client to make multiple calls to this function.
-  inline void InitializeAllMCAsmInfos() {
-#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##MCAsmInfo();
-#include "llvm/Config/Targets.def"
-  }
-  
-  /// InitializeAllMCInstrInfos - The main program should call this function
-  /// if it wants access to all available instruction infos for targets that
-  /// LLVM is configured to support, to make them available via the
-  /// TargetRegistry.
-  ///
-  /// It is legal for a client to make multiple calls to this function.
-  inline void InitializeAllMCInstrInfos() {
-#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##MCInstrInfo();
-#include "llvm/Config/Targets.def"
-  }
-  
-  /// InitializeAllMCSubtargetInfos - The main program should call this function
-  /// if it wants access to all available subtarget infos for targets that LLVM
-  /// is configured to support, to make them available via the TargetRegistry.
-  ///
-  /// It is legal for a client to make multiple calls to this function.
-  inline void InitializeAllMCSubtargetInfos() {
-#define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##MCSubtargetInfo();
-#include "llvm/Config/Targets.def"
-  }
-  
-  /// InitializeAllAsmPrinters - The main program should call this function if
-  /// it wants all asm printers that LLVM is configured to support, to make them
-  /// available via the TargetRegistry.
-  ///
-  /// It is legal for a client to make multiple calls to this function.
-  inline void InitializeAllAsmPrinters() {
-#define LLVM_ASM_PRINTER(TargetName) LLVMInitialize##TargetName##AsmPrinter();
-#include "llvm/Config/AsmPrinters.def"
-  }
-  
-  /// InitializeAllAsmParsers - The main program should call this function if it
-  /// wants all asm parsers that LLVM is configured to support, to make them
-  /// available via the TargetRegistry.
-  ///
-  /// It is legal for a client to make multiple calls to this function.
-  inline void InitializeAllAsmParsers() {
-#define LLVM_ASM_PARSER(TargetName) LLVMInitialize##TargetName##AsmParser();
-#include "llvm/Config/AsmParsers.def"
-  }
-  
-  /// InitializeAllDisassemblers - The main program should call this function if
-  /// it wants all disassemblers that LLVM is configured to support, to make
-  /// them available via the TargetRegistry.
-  ///
-  /// It is legal for a client to make multiple calls to this function.
-  inline void InitializeAllDisassemblers() {
-#define LLVM_DISASSEMBLER(TargetName) LLVMInitialize##TargetName##Disassembler();
-#include "llvm/Config/Disassemblers.def"
-  }
-  
-  /// InitializeNativeTarget - The main program should call this function to
-  /// initialize the native target corresponding to the host.  This is useful 
-  /// for JIT applications to ensure that the target gets linked in correctly.
-  ///
-  /// It is legal for a client to make multiple calls to this function.
-  inline bool InitializeNativeTarget() {
-  // If we have a native target, initialize it to ensure it is linked in.
-#ifdef LLVM_NATIVE_TARGET
-    LLVM_NATIVE_TARGETINFO();
-    LLVM_NATIVE_TARGET();
-    LLVM_NATIVE_MCASMINFO();
-    return false;
-#else
-    return true;
-#endif
-  }  
-
-  /// InitializeNativeTargetAsmPrinter - The main program should call
-  /// this function to initialize the native target asm printer.
-  inline bool InitializeNativeTargetAsmPrinter() {
-  // If we have a native target, initialize the corresponding asm printer.
-#ifdef LLVM_NATIVE_ASMPRINTER
-    LLVM_NATIVE_ASMPRINTER();
-    return false;
-#else
-    return true;
-#endif
-  }  
-
-  /// InitializeNativeTargetAsmParser - The main program should call
-  /// this function to initialize the native target asm parser.
-  inline bool InitializeNativeTargetAsmParser() {
-  // If we have a native target, initialize the corresponding asm parser.
-#ifdef LLVM_NATIVE_ASMPARSER
-    LLVM_NATIVE_ASMPARSER();
-    return false;
-#else
-    return true;
-#endif
-  }  
-
-}
-
-#endif
diff --git a/include/llvm/Target/TargetSelectionDAG.td b/include/llvm/Target/TargetSelectionDAG.td
index 9d1ef2c..612635e 100644
--- a/include/llvm/Target/TargetSelectionDAG.td
+++ b/include/llvm/Target/TargetSelectionDAG.td
@@ -149,6 +149,10 @@ def SDTSelect : SDTypeProfile<1, 3, [       // select
   SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
 ]>;
 
+def SDTVSelect : SDTypeProfile<1, 3, [       // vselect
+  SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
+]>;
+
 def SDTSelectCC : SDTypeProfile<1, 5, [     // select_cc
   SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>, SDTCisSameAs<0, 3>,
   SDTCisVT<5, OtherVT>
@@ -205,12 +209,21 @@ def SDTMemBarrier : SDTypeProfile<0, 5, [   // memory barier
   SDTCisSameAs<0,1>,  SDTCisSameAs<0,2>,  SDTCisSameAs<0,3>, SDTCisSameAs<0,4>,
   SDTCisInt<0>
 ]>;
+def SDTAtomicFence : SDTypeProfile<0, 2, [
+  SDTCisSameAs<0,1>, SDTCisPtrTy<0>
+]>;
 def SDTAtomic3 : SDTypeProfile<1, 3, [
   SDTCisSameAs<0,2>,  SDTCisSameAs<0,3>, SDTCisInt<0>, SDTCisPtrTy<1>
 ]>;
 def SDTAtomic2 : SDTypeProfile<1, 2, [
   SDTCisSameAs<0,2>, SDTCisInt<0>, SDTCisPtrTy<1>
 ]>;
+def SDTAtomicStore : SDTypeProfile<0, 2, [
+  SDTCisPtrTy<0>, SDTCisInt<1>
+]>;
+def SDTAtomicLoad : SDTypeProfile<1, 1, [
+  SDTCisInt<0>, SDTCisPtrTy<1>
+]>;
 
 def SDTConvertOp : SDTypeProfile<1, 5, [ //cvtss, su, us, uu, ff, fs, fu, sf, su
   SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>, SDTCisPtrTy<4>, SDTCisPtrTy<5>
@@ -381,8 +394,8 @@ def f32_to_f16 : SDNode<"ISD::FP32_TO_FP16", SDTFPToIntOp>;
 
 def setcc      : SDNode<"ISD::SETCC"      , SDTSetCC>;
 def select     : SDNode<"ISD::SELECT"     , SDTSelect>;
+def vselect    : SDNode<"ISD::VSELECT"    , SDTVSelect>;
 def selectcc   : SDNode<"ISD::SELECT_CC"  , SDTSelectCC>;
-def vsetcc     : SDNode<"ISD::VSETCC"     , SDTSetCC>;
 
 def brcond     : SDNode<"ISD::BRCOND"     , SDTBrcond, [SDNPHasChain]>;
 def brind      : SDNode<"ISD::BRIND"      , SDTBrind,  [SDNPHasChain]>;
@@ -397,6 +410,9 @@ def prefetch   : SDNode<"ISD::PREFETCH"   , SDTPrefetch,
 def membarrier : SDNode<"ISD::MEMBARRIER" , SDTMemBarrier,
                         [SDNPHasChain, SDNPSideEffect]>;
 
+def atomic_fence : SDNode<"ISD::ATOMIC_FENCE" , SDTAtomicFence,
+                          [SDNPHasChain, SDNPSideEffect]>;
+
 def atomic_cmp_swap : SDNode<"ISD::ATOMIC_CMP_SWAP" , SDTAtomic3,
                     [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
 def atomic_load_add : SDNode<"ISD::ATOMIC_LOAD_ADD" , SDTAtomic2,
@@ -421,6 +437,10 @@ def atomic_load_umin : SDNode<"ISD::ATOMIC_LOAD_UMIN", SDTAtomic2,
                     [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
 def atomic_load_umax : SDNode<"ISD::ATOMIC_LOAD_UMAX", SDTAtomic2,
                     [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_load      : SDNode<"ISD::ATOMIC_LOAD", SDTAtomicLoad,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
+def atomic_store     : SDNode<"ISD::ATOMIC_STORE", SDTAtomicStore,
+                    [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>;
 
 // Do not use ld, st directly. Use load, extload, sextload, zextload, store,
 // and truncst (see below).
@@ -838,6 +858,28 @@ defm atomic_load_min  : binary_atomic_op<atomic_load_min>;
 defm atomic_load_max  : binary_atomic_op<atomic_load_max>;
 defm atomic_load_umin : binary_atomic_op<atomic_load_umin>;
 defm atomic_load_umax : binary_atomic_op<atomic_load_umax>;
+defm atomic_store     : binary_atomic_op<atomic_store>;
+
+def atomic_load_8 :
+  PatFrag<(ops node:$ptr),
+          (atomic_load node:$ptr), [{
+  return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i8;
+}]>;
+def atomic_load_16 :
+  PatFrag<(ops node:$ptr),
+          (atomic_load node:$ptr), [{
+  return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i16;
+}]>;
+def atomic_load_32 :
+  PatFrag<(ops node:$ptr),
+          (atomic_load node:$ptr), [{
+  return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i32;
+}]>;
+def atomic_load_64 :
+  PatFrag<(ops node:$ptr),
+          (atomic_load node:$ptr), [{
+  return cast<AtomicSDNode>(N)->getMemoryVT() == MVT::i64;
+}]>;
 
 //===----------------------------------------------------------------------===//
 // Selection DAG CONVERT_RNDSAT patterns