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| author | dim <dim@FreeBSD.org> | 2012-08-19 10:31:50 +0000 |
|---|---|---|
| committer | dim <dim@FreeBSD.org> | 2012-08-19 10:31:50 +0000 |
| commit | 4dc93743c9d40c29c0a3bec2aae328cac0d289e8 (patch) | |
| tree | e7da40d2f6ef824f7371860826845870e6e1dcd5 /include/llvm/Target | |
| parent | 721c201bd55ffb73cb2ba8d39e0570fa38c44e15 (diff) | |
| download | FreeBSD-src-4dc93743c9d40c29c0a3bec2aae328cac0d289e8.zip FreeBSD-src-4dc93743c9d40c29c0a3bec2aae328cac0d289e8.tar.gz | |
Vendor import of llvm trunk r162107:
http://llvm.org/svn/llvm-project/llvm/trunk@162107
Diffstat (limited to 'include/llvm/Target')
| -rw-r--r-- | include/llvm/Target/Target.td | 19 | ||||
| -rw-r--r-- | include/llvm/Target/TargetInstrInfo.h | 45 |
2 files changed, 64 insertions, 0 deletions
diff --git a/include/llvm/Target/Target.td b/include/llvm/Target/Target.td index 24be2b1..1816445 100644 --- a/include/llvm/Target/Target.td +++ b/include/llvm/Target/Target.td @@ -28,6 +28,24 @@ class SubRegIndex<list<SubRegIndex> comps = []> { // ComposedOf - A list of two SubRegIndex instances, [A, B]. // This indicates that this SubRegIndex is the result of composing A and B. list<SubRegIndex> ComposedOf = comps; + + // CoveringSubRegIndices - A list of two or more sub-register indexes that + // cover this sub-register. + // + // This field should normally be left blank as TableGen can infer it. + // + // TableGen automatically detects sub-registers that straddle the registers + // in the SubRegs field of a Register definition. For example: + // + // Q0 = dsub_0 -> D0, dsub_1 -> D1 + // Q1 = dsub_0 -> D2, dsub_1 -> D3 + // D1_D2 = dsub_0 -> D1, dsub_1 -> D2 + // QQ0 = qsub_0 -> Q0, qsub_1 -> Q1 + // + // TableGen will infer that D1_D2 is a sub-register of QQ0. It will be given + // the synthetic index dsub_1_dsub_2 unless some SubRegIndex is defined with + // CoveringSubRegIndices = [dsub_1, dsub_2]. + list<SubRegIndex> CoveringSubRegIndices = []; } // RegAltNameIndex - The alternate name set to use for register operands of @@ -321,6 +339,7 @@ class Instruction { bit isCompare = 0; // Is this instruction a comparison instruction? bit isMoveImm = 0; // Is this instruction a move immediate instruction? bit isBitcast = 0; // Is this instruction a bitcast instruction? + bit isSelect = 0; // Is this instruction a select instruction? bit isBarrier = 0; // Can control flow fall through this instruction? bit isCall = 0; // Is this instruction a call instruction? bit canFoldAsLoad = 0; // Can this be folded as a simple memory operand? diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index a18b030..da30ab8 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -413,6 +413,51 @@ public: llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!"); } + /// analyzeSelect - Analyze the given select instruction, returning true if + /// it cannot be understood. It is assumed that MI->isSelect() is true. + /// + /// When successful, return the controlling condition and the operands that + /// determine the true and false result values. + /// + /// Result = SELECT Cond, TrueOp, FalseOp + /// + /// Some targets can optimize select instructions, for example by predicating + /// the instruction defining one of the operands. Such targets should set + /// Optimizable. + /// + /// @param MI Select instruction to analyze. + /// @param Cond Condition controlling the select. + /// @param TrueOp Operand number of the value selected when Cond is true. + /// @param FalseOp Operand number of the value selected when Cond is false. + /// @param Optimizable Returned as true if MI is optimizable. + /// @returns False on success. + virtual bool analyzeSelect(const MachineInstr *MI, + SmallVectorImpl<MachineOperand> &Cond, + unsigned &TrueOp, unsigned &FalseOp, + bool &Optimizable) const { + assert(MI && MI->isSelect() && "MI must be a select instruction"); + return true; + } + + /// optimizeSelect - Given a select instruction that was understood by + /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by + /// merging it with one of its operands. Returns NULL on failure. + /// + /// When successful, returns the new select instruction. The client is + /// responsible for deleting MI. + /// + /// If both sides of the select can be optimized, PreferFalse is used to pick + /// a side. + /// + /// @param MI Optimizable select instruction. + /// @param PreferFalse Try to optimize FalseOp instead of TrueOp. + /// @returns Optimized instruction or NULL. + virtual MachineInstr *optimizeSelect(MachineInstr *MI, + bool PreferFalse = false) const { + // This function must be implemented if Optimizable is ever set. + llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!"); + } + /// copyPhysReg - Emit instructions to copy a pair of physical registers. virtual void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, DebugLoc DL, |
