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authorrdivacky <rdivacky@FreeBSD.org>2010-05-04 16:11:02 +0000
committerrdivacky <rdivacky@FreeBSD.org>2010-05-04 16:11:02 +0000
commit750ce4d809c7e2a298a389a512a17652ff5be3f2 (patch)
tree70fbd90da02177c8e6ef82adba9fa8ace285a5e3 /include/llvm/Target/TargetOpcodes.h
parent5f970ec96e421f64db6b1c6509a902ea73d98cc7 (diff)
downloadFreeBSD-src-750ce4d809c7e2a298a389a512a17652ff5be3f2.zip
FreeBSD-src-750ce4d809c7e2a298a389a512a17652ff5be3f2.tar.gz
Update LLVM to r103004.
Diffstat (limited to 'include/llvm/Target/TargetOpcodes.h')
-rw-r--r--include/llvm/Target/TargetOpcodes.h12
1 files changed, 10 insertions, 2 deletions
diff --git a/include/llvm/Target/TargetOpcodes.h b/include/llvm/Target/TargetOpcodes.h
index 48665b7..c4deaa8 100644
--- a/include/llvm/Target/TargetOpcodes.h
+++ b/include/llvm/Target/TargetOpcodes.h
@@ -62,9 +62,17 @@ namespace TargetOpcode {
/// instructions are insufficient. The actual MachineInstrs to perform
/// the copy are emitted with the TargetInstrInfo::copyRegToReg hook.
COPY_TO_REGCLASS = 10,
-
+
/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
- DBG_VALUE = 11
+ DBG_VALUE = 11,
+
+ /// REG_SEQUENCE - This variadic instruction is used to form a register that
+ /// represent a consecutive sequence of sub-registers. It's used as register
+ /// coalescing / allocation aid and must be eliminated before code emission.
+ /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
+ /// After register coalescing references of v1024 should be replace with
+ /// v1027:3, v1025 with v1027:4, etc.
+ REG_SEQUENCE = 12
};
} // end namespace TargetOpcode
} // end namespace llvm
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