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| author | dim <dim@FreeBSD.org> | 2011-07-17 15:36:56 +0000 |
|---|---|---|
| committer | dim <dim@FreeBSD.org> | 2011-07-17 15:36:56 +0000 |
| commit | 1176aa52646fe641a4243a246aa7f960c708a274 (patch) | |
| tree | c8086addb211fa670a9d2b1038d8c2e453229755 /include/llvm/Target/TargetOpcodes.h | |
| parent | ece02cd5829cea836e9365b0845a8ef042d17b0a (diff) | |
| download | FreeBSD-src-1176aa52646fe641a4243a246aa7f960c708a274.zip FreeBSD-src-1176aa52646fe641a4243a246aa7f960c708a274.tar.gz | |
Vendor import of llvm trunk r135360:
http://llvm.org/svn/llvm-project/llvm/trunk@135360
Diffstat (limited to 'include/llvm/Target/TargetOpcodes.h')
| -rw-r--r-- | include/llvm/Target/TargetOpcodes.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/include/llvm/Target/TargetOpcodes.h b/include/llvm/Target/TargetOpcodes.h index 01fba66..37f7b2f 100644 --- a/include/llvm/Target/TargetOpcodes.h +++ b/include/llvm/Target/TargetOpcodes.h @@ -71,6 +71,10 @@ namespace TargetOpcode { /// REG_SEQUENCE - This variadic instruction is used to form a register that /// represent a consecutive sequence of sub-registers. It's used as register /// coalescing / allocation aid and must be eliminated before code emission. + // In SDNode form, the first operand encodes the register class created by + // the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index + // pair. Once it has been lowered to a MachineInstr, the regclass operand + // is no longer present. /// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5 /// After register coalescing references of v1024 should be replace with /// v1027:3, v1025 with v1027:4, etc. |
