Vendor import of llvm release_30 branch r142614:

http://llvm.org/svn/llvm-project/llvm/branches/release_30@142614

1 files changed, 181 insertions, 3 deletions

diff --git a/include/llvm/MC/MCRegisterInfo.h b/include/llvm/MC/MCRegisterInfo.h
index caf98bb..ada5ae8 100644
--- a/include/llvm/MC/MCRegisterInfo.h
+++ b/include/llvm/MC/MCRegisterInfo.h
@@ -16,10 +16,94 @@
 #ifndef LLVM_MC_MCREGISTERINFO_H
 #define LLVM_MC_MCREGISTERINFO_H
 
+#include "llvm/ADT/DenseMap.h"
 #include <cassert>
 
 namespace llvm {
 
+/// MCRegisterClass - Base class of TargetRegisterClass.
+class MCRegisterClass {
+public:
+  typedef const unsigned* iterator;
+  typedef const unsigned* const_iterator;
+private:
+  unsigned ID;
+  const char *Name;
+  const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
+  const int CopyCost;
+  const bool Allocatable;
+  const iterator RegsBegin, RegsEnd;
+  const unsigned char *const RegSet;
+  const unsigned RegSetSize;
+public:
+  MCRegisterClass(unsigned id, const char *name,
+                  unsigned RS, unsigned Al, int CC, bool Allocable,
+                  iterator RB, iterator RE, const unsigned char *Bits,
+                  unsigned NumBytes)
+    : ID(id), Name(name), RegSize(RS), Alignment(Al), CopyCost(CC),
+      Allocatable(Allocable), RegsBegin(RB), RegsEnd(RE), RegSet(Bits),
+      RegSetSize(NumBytes) {
+    for (iterator i = RegsBegin; i != RegsEnd; ++i)
+       assert(contains(*i) && "Bit field corrupted.");
+  }
+
+  /// getID() - Return the register class ID number.
+  ///
+  unsigned getID() const { return ID; }
+
+  /// getName() - Return the register class name for debugging.
+  ///
+  const char *getName() const { return Name; }
+
+  /// begin/end - Return all of the registers in this class.
+  ///
+  iterator       begin() const { return RegsBegin; }
+  iterator         end() const { return RegsEnd; }
+
+  /// getNumRegs - Return the number of registers in this class.
+  ///
+  unsigned getNumRegs() const { return (unsigned)(RegsEnd-RegsBegin); }
+
+  /// getRegister - Return the specified register in the class.
+  ///
+  unsigned getRegister(unsigned i) const {
+    assert(i < getNumRegs() && "Register number out of range!");
+    return RegsBegin[i];
+  }
+
+  /// contains - Return true if the specified register is included in this
+  /// register class.  This does not include virtual registers.
+  bool contains(unsigned Reg) const {
+    unsigned InByte = Reg % 8;
+    unsigned Byte = Reg / 8;
+    if (Byte >= RegSetSize)
+      return false;
+    return (RegSet[Byte] & (1 << InByte)) != 0;
+  }
+
+  /// contains - Return true if both registers are in this class.
+  bool contains(unsigned Reg1, unsigned Reg2) const {
+    return contains(Reg1) && contains(Reg2);
+  }
+
+  /// getSize - Return the size of the register in bytes, which is also the size
+  /// of a stack slot allocated to hold a spilled copy of this register.
+  unsigned getSize() const { return RegSize; }
+
+  /// getAlignment - Return the minimum required alignment for a register of
+  /// this class.
+  unsigned getAlignment() const { return Alignment; }
+
+  /// getCopyCost - Return the cost of copying a value between two registers in
+  /// this class. A negative number means the register class is very expensive
+  /// to copy e.g. status flag register classes.
+  int getCopyCost() const { return CopyCost; }
+
+  /// isAllocatable - Return true if this register class may be used to create
+  /// virtual registers.
+  bool isAllocatable() const { return Allocatable; }
+};
+
 /// MCRegisterDesc - This record contains all of the information known about
 /// a particular register.  The Overlaps field contains a pointer to a zero
 /// terminated array of registers that this register aliases, starting with
@@ -50,18 +134,67 @@ struct MCRegisterDesc {
 /// virtual methods.
 ///
 class MCRegisterInfo {
+public:
+  typedef const MCRegisterClass *regclass_iterator;
 private:
-  const MCRegisterDesc *Desc;             // Pointer to the descriptor array
-  unsigned NumRegs;                       // Number of entries in the array
+  const MCRegisterDesc *Desc;                 // Pointer to the descriptor array
+  unsigned NumRegs;                           // Number of entries in the array
+  unsigned RAReg;                             // Return address register
+  const MCRegisterClass *Classes;             // Pointer to the regclass array
+  unsigned NumClasses;                        // Number of entries in the array
+  DenseMap<unsigned, int> L2DwarfRegs;        // LLVM to Dwarf regs mapping
+  DenseMap<unsigned, int> EHL2DwarfRegs;      // LLVM to Dwarf regs mapping EH
+  DenseMap<unsigned, unsigned> Dwarf2LRegs;   // Dwarf to LLVM regs mapping
+  DenseMap<unsigned, unsigned> EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
+  DenseMap<unsigned, int> L2SEHRegs;          // LLVM to SEH regs mapping
 
 public:
   /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
   /// auto-generated routines. *DO NOT USE*.
-  void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR) {
+  void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
+                          const MCRegisterClass *C, unsigned NC) {
     Desc = D;
     NumRegs = NR;
+    RAReg = RA;
+    Classes = C;
+    NumClasses = NC;
+  }
+
+  /// mapLLVMRegToDwarfReg - Used to initialize LLVM register to Dwarf
+  /// register number mapping. Called by TableGen auto-generated routines.
+  /// *DO NOT USE*.
+  void mapLLVMRegToDwarfReg(unsigned LLVMReg, int DwarfReg, bool isEH) {
+    if (isEH)
+      EHL2DwarfRegs[LLVMReg] = DwarfReg;
+    else
+      L2DwarfRegs[LLVMReg] = DwarfReg;
   }
     
+  /// mapDwarfRegToLLVMReg - Used to initialize Dwarf register to LLVM
+  /// register number mapping. Called by TableGen auto-generated routines.
+  /// *DO NOT USE*.
+  void mapDwarfRegToLLVMReg(unsigned DwarfReg, unsigned LLVMReg, bool isEH) {
+    if (isEH)
+      EHDwarf2LRegs[DwarfReg] = LLVMReg;
+    else
+      Dwarf2LRegs[DwarfReg] = LLVMReg;
+  }
+     
+  /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
+  /// number mapping. By default the SEH register number is just the same
+  /// as the LLVM register number.
+  /// FIXME: TableGen these numbers. Currently this requires target specific
+  /// initialization code.
+  void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
+    L2SEHRegs[LLVMReg] = SEHReg;
+  }
+
+  /// getRARegister - This method should return the register where the return
+  /// address can be found.
+  unsigned getRARegister() const {
+    return RAReg;
+  }
+
   const MCRegisterDesc &operator[](unsigned RegNo) const {
     assert(RegNo < NumRegs &&
            "Attempting to access record for invalid register number!");
@@ -122,6 +255,51 @@ public:
   unsigned getNumRegs() const {
     return NumRegs;
   }
+
+  /// getDwarfRegNum - Map a target register to an equivalent dwarf register
+  /// number.  Returns -1 if there is no equivalent value.  The second
+  /// parameter allows targets to use different numberings for EH info and
+  /// debugging info.
+  int getDwarfRegNum(unsigned RegNum, bool isEH) const {
+    const DenseMap<unsigned, int> &M = isEH ? EHL2DwarfRegs : L2DwarfRegs;
+    const DenseMap<unsigned, int>::const_iterator I = M.find(RegNum);
+    if (I == M.end()) return -1;
+    return I->second;
+  }
+
+  /// getLLVMRegNum - Map a dwarf register back to a target register.
+  ///
+  int getLLVMRegNum(unsigned RegNum, bool isEH) const {
+    const DenseMap<unsigned, unsigned> &M = isEH ? EHDwarf2LRegs : Dwarf2LRegs;
+    const DenseMap<unsigned, unsigned>::const_iterator I = M.find(RegNum);
+    if (I == M.end()) {
+      assert(0 && "Invalid RegNum");
+      return -1;
+    }
+    return I->second;
+  }
+
+  /// getSEHRegNum - Map a target register to an equivalent SEH register
+  /// number.  Returns LLVM register number if there is no equivalent value.
+  int getSEHRegNum(unsigned RegNum) const {
+    const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum);
+    if (I == L2SEHRegs.end()) return (int)RegNum;
+    return I->second;
+  }
+
+  regclass_iterator regclass_begin() const { return Classes; }
+  regclass_iterator regclass_end() const { return Classes+NumClasses; }
+
+  unsigned getNumRegClasses() const {
+    return (unsigned)(regclass_end()-regclass_begin());
+  }
+
+  /// getRegClass - Returns the register class associated with the enumeration
+  /// value.  See class MCOperandInfo.
+  const MCRegisterClass getRegClass(unsigned i) const {
+    assert(i < getNumRegClasses() && "Register Class ID out of range");
+    return Classes[i];
+  }
 };
  
 } // End llvm namespace