Update LLVM to 93512.

10 files changed, 62 insertions, 33 deletions

diff --git a/include/llvm/CodeGen/DAGISelHeader.h b/include/llvm/CodeGen/DAGISelHeader.h
index 7233f3f..4d50879 100644
--- a/include/llvm/CodeGen/DAGISelHeader.h
+++ b/include/llvm/CodeGen/DAGISelHeader.h
@@ -109,7 +109,7 @@ void SelectRoot(SelectionDAG &DAG) {
 #if 0
     DAG.setSubgraphColor(Node, "red");
 #endif
-    SDNode *ResNode = Select(SDValue(Node, 0));
+    SDNode *ResNode = Select(Node);
     // If node should not be replaced, continue with the next one.
     if (ResNode == Node)
       continue;
diff --git a/include/llvm/CodeGen/FastISel.h b/include/llvm/CodeGen/FastISel.h
index 806952a..9d0f0d9 100644
--- a/include/llvm/CodeGen/FastISel.h
+++ b/include/llvm/CodeGen/FastISel.h
@@ -139,7 +139,7 @@ protected:
   /// be emitted.
   virtual unsigned FastEmit_(MVT VT,
                              MVT RetVT,
-                             ISD::NodeType Opcode);
+                             unsigned Opcode);
 
   /// FastEmit_r - This method is called by target-independent code
   /// to request that an instruction with the given type, opcode, and
@@ -147,7 +147,7 @@ protected:
   ///
   virtual unsigned FastEmit_r(MVT VT,
                               MVT RetVT,
-                              ISD::NodeType Opcode, unsigned Op0);
+                              unsigned Opcode, unsigned Op0);
 
   /// FastEmit_rr - This method is called by target-independent code
   /// to request that an instruction with the given type, opcode, and
@@ -155,7 +155,7 @@ protected:
   ///
   virtual unsigned FastEmit_rr(MVT VT,
                                MVT RetVT,
-                               ISD::NodeType Opcode,
+                               unsigned Opcode,
                                unsigned Op0, unsigned Op1);
 
   /// FastEmit_ri - This method is called by target-independent code
@@ -164,7 +164,7 @@ protected:
   ///
   virtual unsigned FastEmit_ri(MVT VT,
                                MVT RetVT,
-                               ISD::NodeType Opcode,
+                               unsigned Opcode,
                                unsigned Op0, uint64_t Imm);
 
   /// FastEmit_rf - This method is called by target-independent code
@@ -173,7 +173,7 @@ protected:
   ///
   virtual unsigned FastEmit_rf(MVT VT,
                                MVT RetVT,
-                               ISD::NodeType Opcode,
+                               unsigned Opcode,
                                unsigned Op0, ConstantFP *FPImm);
 
   /// FastEmit_rri - This method is called by target-independent code
@@ -182,7 +182,7 @@ protected:
   ///
   virtual unsigned FastEmit_rri(MVT VT,
                                 MVT RetVT,
-                                ISD::NodeType Opcode,
+                                unsigned Opcode,
                                 unsigned Op0, unsigned Op1, uint64_t Imm);
 
   /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
@@ -190,7 +190,7 @@ protected:
   /// If that fails, it materializes the immediate into a register and try
   /// FastEmit_rr instead.
   unsigned FastEmit_ri_(MVT VT,
-                        ISD::NodeType Opcode,
+                        unsigned Opcode,
                         unsigned Op0, uint64_t Imm,
                         MVT ImmType);
   
@@ -199,7 +199,7 @@ protected:
   /// If that fails, it materializes the immediate into a register and try
   /// FastEmit_rr instead.
   unsigned FastEmit_rf_(MVT VT,
-                        ISD::NodeType Opcode,
+                        unsigned Opcode,
                         unsigned Op0, ConstantFP *FPImm,
                         MVT ImmType);
   
@@ -208,7 +208,7 @@ protected:
   /// immediate operand be emitted.
   virtual unsigned FastEmit_i(MVT VT,
                               MVT RetVT,
-                              ISD::NodeType Opcode,
+                              unsigned Opcode,
                               uint64_t Imm);
 
   /// FastEmit_f - This method is called by target-independent code
@@ -216,7 +216,7 @@ protected:
   /// floating-point immediate operand be emitted.
   virtual unsigned FastEmit_f(MVT VT,
                               MVT RetVT,
-                              ISD::NodeType Opcode,
+                              unsigned Opcode,
                               ConstantFP *FPImm);
 
   /// FastEmitInst_ - Emit a MachineInstr with no operands and a
@@ -298,7 +298,7 @@ protected:
   }
 
 private:
-  bool SelectBinaryOp(User *I, ISD::NodeType ISDOpcode);
+  bool SelectBinaryOp(User *I, unsigned ISDOpcode);
 
   bool SelectFNeg(User *I);
 
@@ -308,7 +308,7 @@ private:
 
   bool SelectBitCast(User *I);
   
-  bool SelectCast(User *I, ISD::NodeType Opcode);
+  bool SelectCast(User *I, unsigned Opcode);
 };
 
 }
diff --git a/include/llvm/CodeGen/MachineFunction.h b/include/llvm/CodeGen/MachineFunction.h
index f1bfa01..a12a55a 100644
--- a/include/llvm/CodeGen/MachineFunction.h
+++ b/include/llvm/CodeGen/MachineFunction.h
@@ -315,6 +315,8 @@ public:
   /// 'Orig' instruction, identical in all ways except the the instruction
   /// has no parent, prev, or next.
   ///
+  /// See also TargetInstrInfo::duplicate() for target-specific fixes to cloned
+  /// instructions.
   MachineInstr *CloneMachineInstr(const MachineInstr *Orig);
 
   /// DeleteMachineInstr - Delete the given MachineInstr.
diff --git a/include/llvm/CodeGen/MachineInstr.h b/include/llvm/CodeGen/MachineInstr.h
index 87b67d6..c2a0578 100644
--- a/include/llvm/CodeGen/MachineInstr.h
+++ b/include/llvm/CodeGen/MachineInstr.h
@@ -288,7 +288,7 @@ public:
   bool addRegisterKilled(unsigned IncomingReg,
                          const TargetRegisterInfo *RegInfo,
                          bool AddIfNotFound = false);
-  
+
   /// addRegisterDead - We have determined MI defined a register without a use.
   /// Look for the operand that defines it and mark it as IsDead. If
   /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
@@ -296,6 +296,11 @@ public:
   bool addRegisterDead(unsigned IncomingReg, const TargetRegisterInfo *RegInfo,
                        bool AddIfNotFound = false);
 
+  /// addRegisterDefined - We have determined MI defines a register. Make sure
+  /// there is an operand defining Reg.
+  void addRegisterDefined(unsigned IncomingReg,
+                          const TargetRegisterInfo *RegInfo);
+
   /// isSafeToMove - Return true if it is safe to move this instruction. If
   /// SawStore is set to true, it means that there is a store (or call) between
   /// the instruction's location and its intended destination.
diff --git a/include/llvm/CodeGen/MachineInstrBuilder.h b/include/llvm/CodeGen/MachineInstrBuilder.h
index 6ca63f0..8eb0add 100644
--- a/include/llvm/CodeGen/MachineInstrBuilder.h
+++ b/include/llvm/CodeGen/MachineInstrBuilder.h
@@ -22,6 +22,7 @@
 namespace llvm {
 
 class TargetInstrDesc;
+class MDNode;
 
 namespace RegState {
   enum {
@@ -123,6 +124,11 @@ public:
     MI->addOperand(MO);
     return *this;
   }
+
+  const MachineInstrBuilder &addMetadata(MDNode *MD) const {
+    MI->addOperand(MachineOperand::CreateMetadata(MD));
+    return *this;
+  }
 };
 
 /// BuildMI - Builder interface.  Specify how to create the initial instruction
diff --git a/include/llvm/CodeGen/MachineLoopInfo.h b/include/llvm/CodeGen/MachineLoopInfo.h
index d3df805..8459a8d 100644
--- a/include/llvm/CodeGen/MachineLoopInfo.h
+++ b/include/llvm/CodeGen/MachineLoopInfo.h
@@ -49,6 +49,8 @@ public:
   /// contiguous with the part the contains the header.
   MachineBasicBlock *getBottomBlock();
 
+  void dump() const;
+
 private:
   friend class LoopInfoBase<MachineBasicBlock, MachineLoop>;
   explicit MachineLoop(MachineBasicBlock *MBB)
diff --git a/include/llvm/CodeGen/MachineOperand.h b/include/llvm/CodeGen/MachineOperand.h
index 8748afc..907c25a 100644
--- a/include/llvm/CodeGen/MachineOperand.h
+++ b/include/llvm/CodeGen/MachineOperand.h
@@ -26,6 +26,7 @@ class GlobalValue;
 class MachineInstr;
 class TargetMachine;
 class MachineRegisterInfo;
+class MDNode;
 class raw_ostream;
   
 /// MachineOperand class - Representation of each machine instruction operand.
@@ -42,7 +43,8 @@ public:
     MO_JumpTableIndex,         ///< Address of indexed Jump Table for switch
     MO_ExternalSymbol,         ///< Name of external global symbol
     MO_GlobalAddress,          ///< Address of a global value
-    MO_BlockAddress            ///< Address of a basic block
+    MO_BlockAddress,           ///< Address of a basic block
+    MO_Metadata                ///< Metadata reference (for debug info)
   };
 
 private:
@@ -94,6 +96,7 @@ private:
     MachineBasicBlock *MBB;   // For MO_MachineBasicBlock.
     const ConstantFP *CFP;    // For MO_FPImmediate.
     int64_t ImmVal;           // For MO_Immediate.
+    MDNode *MD;               // For MO_Metadata.
 
     struct {                  // For MO_Register.
       unsigned RegNo;
@@ -158,6 +161,8 @@ public:
   bool isSymbol() const { return OpKind == MO_ExternalSymbol; }
   /// isBlockAddress - Tests if this is a MO_BlockAddress operand.
   bool isBlockAddress() const { return OpKind == MO_BlockAddress; }
+  /// isMetadata - Tests if this is a MO_Metadata operand.
+  bool isMetadata() const { return OpKind == MO_Metadata; }
 
   //===--------------------------------------------------------------------===//
   // Accessors for Register Operands
@@ -311,6 +316,11 @@ public:
     assert(isSymbol() && "Wrong MachineOperand accessor");
     return Contents.OffsetedInfo.Val.SymbolName;
   }
+
+  const MDNode *getMetadata() const {
+    assert(isMetadata() && "Wrong MachineOperand accessor");
+    return Contents.MD;
+  }
   
   //===--------------------------------------------------------------------===//
   // Mutators for various operand types.
@@ -443,6 +453,13 @@ public:
     Op.setTargetFlags(TargetFlags);
     return Op;
   }
+  static MachineOperand CreateMetadata(MDNode *Meta,
+                                       unsigned char TargetFlags = 0) {
+    MachineOperand Op(MachineOperand::MO_Metadata);
+    Op.Contents.MD = Meta;
+    Op.setTargetFlags(TargetFlags);
+    return Op;
+  }
 
   friend class MachineInstr;
   friend class MachineRegisterInfo;
diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h
index 99f8c34..2203f8c 100644
--- a/include/llvm/CodeGen/Passes.h
+++ b/include/llvm/CodeGen/Passes.h
@@ -170,6 +170,10 @@ namespace llvm {
   /// instructions.
   FunctionPass *createMachineSinkingPass();
 
+  /// createOptimizeExtsPass - This pass performs sign / zero extension
+  /// optimization by increasing uses of extended values.
+  FunctionPass *createOptimizeExtsPass();
+
   /// createStackSlotColoringPass - This pass performs stack slot coloring.
   FunctionPass *createStackSlotColoringPass(bool);
 
diff --git a/include/llvm/CodeGen/SelectionDAGISel.h b/include/llvm/CodeGen/SelectionDAGISel.h
index bfd3492..b33b21d 100644
--- a/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/include/llvm/CodeGen/SelectionDAGISel.h
@@ -111,11 +111,11 @@ protected:
                     int64_t DesiredMaskS) const;
   
   // Calls to these functions are generated by tblgen.
-  SDNode *Select_INLINEASM(SDValue N);
-  SDNode *Select_UNDEF(const SDValue &N);
-  SDNode *Select_EH_LABEL(const SDValue &N);
-  void CannotYetSelect(SDValue N);
-  void CannotYetSelectIntrinsic(SDValue N);
+  SDNode *Select_INLINEASM(SDNode *N);
+  SDNode *Select_UNDEF(SDNode *N);
+  SDNode *Select_EH_LABEL(SDNode *N);
+  void CannotYetSelect(SDNode *N);
+  void CannotYetSelectIntrinsic(SDNode *N);
 
 private:
   void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
@@ -131,6 +131,7 @@ private:
   void CodeGenAndEmitDAG();
   void LowerArguments(BasicBlock *BB);
   
+  void ShrinkDemandedOps();
   void ComputeLiveOutVRegInfo();
 
   void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB);
diff --git a/include/llvm/CodeGen/ValueTypes.h b/include/llvm/CodeGen/ValueTypes.h
index 9dc4c7b..0125190 100644
--- a/include/llvm/CodeGen/ValueTypes.h
+++ b/include/llvm/CodeGen/ValueTypes.h
@@ -149,7 +149,7 @@ namespace llvm {
               SimpleTy <= MVT::LAST_VECTOR_VALUETYPE);
     }
     
-    /// isPow2VectorType - Retuns true if the given vector is a power of 2.
+    /// isPow2VectorType - Returns true if the given vector is a power of 2.
     bool isPow2VectorType() const {
       unsigned NElts = getVectorNumElements();
       return !(NElts & (NElts - 1));
@@ -437,25 +437,17 @@ namespace llvm {
 
     /// isFloatingPoint - Return true if this is a FP, or a vector FP type.
     bool isFloatingPoint() const {
-      return isSimple() ?
-             ((V >= MVT::f32 && V <= MVT::ppcf128) ||
-              (V >= MVT::v2f32 && V <= MVT::v4f64)) : isExtendedFloatingPoint();
+      return isSimple() ? V.isFloatingPoint() : isExtendedFloatingPoint();
     }
 
     /// isInteger - Return true if this is an integer, or a vector integer type.
     bool isInteger() const {
-      return isSimple() ?
-             ((V >= MVT::FIRST_INTEGER_VALUETYPE &&
-               V <= MVT::LAST_INTEGER_VALUETYPE) ||
-              (V >= MVT::v2i8 && V <= MVT::v4i64)) : isExtendedInteger();
+      return isSimple() ? V.isInteger() : isExtendedInteger();
     }
 
     /// isVector - Return true if this is a vector value type.
     bool isVector() const {
-      return isSimple() ?
-             (V >= MVT::FIRST_VECTOR_VALUETYPE && V <= 
-                   MVT::LAST_VECTOR_VALUETYPE) :
-             isExtendedVector();
+      return isSimple() ? V.isVector() : isExtendedVector();
     }
 
     /// is64BitVector - Return true if this is a 64-bit vector type.
@@ -641,7 +633,7 @@ namespace llvm {
     static EVT getEVT(const Type *Ty, bool HandleUnknown = false);
 
     intptr_t getRawBits() {
-      if (V.SimpleTy <= MVT::LastSimpleValueType)
+      if (isSimple())
         return V.SimpleTy;
       else
         return (intptr_t)(LLVMTy);