Vendor import of llvm trunk r161861:

http://llvm.org/svn/llvm-project/llvm/trunk@161861

1 files changed, 0 insertions, 139 deletions

diff --git a/docs/CommandGuide/tblgen.pod b/docs/CommandGuide/tblgen.pod
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-
-=pod
-
-=head1 NAME
-
-tblgen - Target Description To C++ Code Generator
-
-=head1 SYNOPSIS
-
-B<tblgen> [I<options>] [I<filename>]
-
-=head1 DESCRIPTION
-
-B<tblgen> translates from target description (.td) files into C++ code that can
-be included in the definition of an LLVM target library. Most users of LLVM will
-not need to use this program. It is only for assisting with writing an LLVM
-target backend.
-
-The input and output of B<tblgen> is beyond the scope of this short
-introduction. Please see the I<CodeGeneration> page in the LLVM documentation.
-
-The F<filename> argument specifies the name of a Target Description (.td) file
-to read as input.
-
-=head1 OPTIONS
-
-=over
-
-=item B<-help>
-
-Print a summary of command line options.
-
-=item B<-o> F<filename>
-
-Specify the output file name.  If F<filename> is C<->, then B<tblgen>
-sends its output to standard output.
-
-=item B<-I> F<directory>
-
-Specify where to find other target description files for inclusion. The
-F<directory> value should be a full or partial path to a directory that contains
-target description files.
-
-=item B<-asmparsernum> F<N>
-
-Make -gen-asm-parser emit assembly writer number F<N>.
-
-=item B<-asmwriternum> F<N>
-
-Make -gen-asm-writer emit assembly writer number F<N>.
-
-=item B<-class> F<class Name>
-
-Print the enumeration list for this class.
-
-=item B<-print-records>
-
-Print all records to standard output (default).
-
-=item B<-print-enums>
-
-Print enumeration values for a class
-
-=item B<-print-sets>
-
-Print expanded sets for testing DAG exprs.
-
-=item B<-gen-emitter>
-
-Generate machine code emitter.
-
-=item B<-gen-register-info>
-
-Generate registers and register classes info.
-
-=item B<-gen-instr-info>
-
-Generate instruction descriptions.
-
-=item B<-gen-asm-writer>
-
-Generate the assembly writer.
-
-=item B<-gen-disassembler>
-
-Generate disassembler.
-
-=item B<-gen-pseudo-lowering>
-
-Generate pseudo instruction lowering.
-
-=item B<-gen-dag-isel>
-
-Generate a DAG (Directed Acycle Graph) instruction selector.
-
-=item B<-gen-asm-matcher>
-
-Generate assembly instruction matcher.
-
-=item B<-gen-dfa-packetizer>
-
-Generate DFA Packetizer for VLIW targets.
-
-=item B<-gen-fast-isel>
-
-Generate a "fast" instruction selector.
-
-=item B<-gen-subtarget>
-
-Generate subtarget enumerations.
-
-=item B<-gen-intrinsic>
-
-Generate intrinsic information.
-
-=item B<-gen-tgt-intrinsic>
-
-Generate target intrinsic information.
-
-=item B<-gen-enhanced-disassembly-info>
-
-Generate enhanced disassembly info.
-
-=item B<-version>
-
-Show the version number of this program.
-
-=back
-
-=head1 EXIT STATUS
-
-If B<tblgen> succeeds, it will exit with 0.  Otherwise, if an error
-occurs, it will exit with a non-zero value.
-
-=head1 AUTHORS
-
-Maintained by The LLVM Team (L<http://llvm.org/>).
-
-=cut