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| author | rdivacky <rdivacky@FreeBSD.org> | 2010-04-02 08:54:30 +0000 |
|---|---|---|
| committer | rdivacky <rdivacky@FreeBSD.org> | 2010-04-02 08:54:30 +0000 |
| commit | 20e856b2a58d12231aa42d5d13888b15ac03e5a4 (patch) | |
| tree | cf5763d092b81cecc168fa28032247ee495d06e2 /docs/CodeGenerator.html | |
| parent | 2f2afc1aae898651e26987a5c71f3febb19bca98 (diff) | |
| download | FreeBSD-src-20e856b2a58d12231aa42d5d13888b15ac03e5a4.zip FreeBSD-src-20e856b2a58d12231aa42d5d13888b15ac03e5a4.tar.gz | |
Update LLVM to r100181.
Diffstat (limited to 'docs/CodeGenerator.html')
| -rw-r--r-- | docs/CodeGenerator.html | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html index c8a0cd5..582e252 100644 --- a/docs/CodeGenerator.html +++ b/docs/CodeGenerator.html @@ -1090,8 +1090,8 @@ def FADDS : AForm_2<59, 21, <p>The portion of the instruction definition in bold indicates the pattern used to match the instruction. The DAG operators (like <tt>fmul</tt>/<tt>fadd</tt>) are defined in - the <tt>lib/Target/TargetSelectionDAG.td</tt> file. "<tt>F4RC</tt>" is the - register class of the input and result values.</p> + the <tt>include/llvm/Target/TargetSelectionDAG.td</tt> file. " + <tt>F4RC</tt>" is the register class of the input and result values.</p> <p>The TableGen DAG instruction selector generator reads the instruction patterns in the <tt>.td</tt> file and automatically builds parts of the @@ -2162,7 +2162,7 @@ MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory <a href="mailto:sabre@nondot.org">Chris Lattner</a><br> <a href="http://llvm.org">The LLVM Compiler Infrastructure</a><br> - Last modified: $Date: 2010-03-11 01:22:57 +0100 (Thu, 11 Mar 2010) $ + Last modified: $Date: 2010-03-25 01:03:04 +0100 (Thu, 25 Mar 2010) $ </address> </body> |
