MFC r271931:

Add a few missing llvm/clang patches, update the other ones to be able
to apply with the same patch options onto a fresh upstream llvm/clang
3.4.1 checkout, and use approximately the same header tempate for them.

6 files changed, 237 insertions, 61 deletions

diff --git a/contrib/llvm/patches/patch-r269387-clang-arm-target-cpu.diff b/contrib/llvm/patches/patch-r269387-clang-arm-target-cpu.diff
new file mode 100644
index 0000000..fea76a1
--- /dev/null
+++ b/contrib/llvm/patches/patch-r269387-clang-arm-target-cpu.diff
@@ -0,0 +1,34 @@
+Update the ARMv6 core clang targets to be an arm1176jzf-s. This brings us
+in line with gcc in base as this makes llvm generate code for the armv6k
+variant of the instruction set.
+
+Introduced here: http://svnweb.freebsd.org/changeset/base/269387
+
+Index: tools/clang/lib/Driver/ToolChain.cpp
+===================================================================
+--- tools/clang/lib/Driver/ToolChain.cpp	(revision 269386)
++++ tools/clang/lib/Driver/ToolChain.cpp	(revision 269387)
+@@ -183,7 +183,8 @@ static const char *getARMTargetCPU(const ArgList &
+     MArch = Triple.getArchName();
+   }
+ 
+-  if (Triple.getOS() == llvm::Triple::NetBSD) {
++  if (Triple.getOS() == llvm::Triple::NetBSD ||
++      Triple.getOS() == llvm::Triple::FreeBSD) {
+     if (MArch == "armv6")
+       return "arm1176jzf-s";
+   }
+Index: tools/clang/lib/Driver/Tools.cpp
+===================================================================
+--- tools/clang/lib/Driver/Tools.cpp	(revision 269386)
++++ tools/clang/lib/Driver/Tools.cpp	(revision 269387)
+@@ -499,7 +499,8 @@ static std::string getARMTargetCPU(const ArgList &
+     MArch = Triple.getArchName();
+   }
+ 
+-  if (Triple.getOS() == llvm::Triple::NetBSD) {
++  if (Triple.getOS() == llvm::Triple::NetBSD ||
++      Triple.getOS() == llvm::Triple::FreeBSD) {
+     if (MArch == "armv6")
+       return "arm1176jzf-s";
+   }
diff --git a/contrib/llvm/patches/patch-r271024-llvm-r216989-fix-movm-armv6.diff b/contrib/llvm/patches/patch-r271024-llvm-r216989-fix-movm-armv6.diff
deleted file mode 100644
index 30577e7..0000000
--- a/contrib/llvm/patches/patch-r271024-llvm-r216989-fix-movm-armv6.diff
+++ /dev/null
@@ -1,14 +0,0 @@
-Index: lib/Target/ARM/ARMInstrInfo.td
-===================================================================
---- lib/Target/ARM/ARMInstrInfo.td	(revision 271024)
-+++ lib/Target/ARM/ARMInstrInfo.td	(revision 271026)
-@@ -3248,7 +3248,8 @@
- def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
-              (SBCri   GPR:$src, so_imm_not:$imm)>;
- def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
--             (SBCrr   GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
-+             (SBCrr   GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
-+             Requires<[IsARM, HasV6T2]>;
- 
- // Note: These are implemented in C++ code, because they have to generate
- // ADD/SUBrs instructions, which use a complex pattern that a xform function
diff --git a/contrib/llvm/patches/patch-r271024-llvm-r216989-r216990-fix-movw-armv6.diff b/contrib/llvm/patches/patch-r271024-llvm-r216989-r216990-fix-movw-armv6.diff
new file mode 100644
index 0000000..f477390
--- /dev/null
+++ b/contrib/llvm/patches/patch-r271024-llvm-r216989-r216990-fix-movw-armv6.diff
@@ -0,0 +1,78 @@
+Pull in r216989 from upstream llvm trunk (by Renato Golin):
+
+  MFV:  Only emit movw on ARMv6T2+
+
+Pull in r216990 from upstream llvm trunk (by Renato Golin):
+
+  Missing test from r216989
+
+Building for the FreeBSD default target ARMv6 was emitting movw ASM on certain
+test cases (found building qmake4/5 for ARM).  Don't do that, moreover, the AS
+in base doesn't understand this instruction for this target.  One would need
+to use --integrated-as to get this to build if desired.
+
+Introduced here: http://svnweb.freebsd.org/changeset/base/271025
+
+Index: lib/Target/ARM/ARMInstrInfo.td
+===================================================================
+--- lib/Target/ARM/ARMInstrInfo.td
++++ lib/Target/ARM/ARMInstrInfo.td
+@@ -3248,7 +3248,8 @@
+ def : ARMPat<(ARMadde GPR:$src, so_imm_not:$imm, CPSR),
+              (SBCri   GPR:$src, so_imm_not:$imm)>;
+ def : ARMPat<(ARMadde GPR:$src, imm0_65535_neg:$imm, CPSR),
+-             (SBCrr   GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>;
++             (SBCrr   GPR:$src, (MOVi16 (imm_not_XFORM imm:$imm)))>,
++             Requires<[IsARM, HasV6T2]>;
+ 
+ // Note: These are implemented in C++ code, because they have to generate
+ // ADD/SUBrs instructions, which use a complex pattern that a xform function
+Index: test/CodeGen/ARM/carry.ll
+===================================================================
+--- test/CodeGen/ARM/carry.ll
++++ test/CodeGen/ARM/carry.ll
+@@ -1,4 +1,4 @@
+-; RUN: llc < %s -march=arm | FileCheck %s
++; RUN: llc < %s -mtriple=armv6t2-eabi | FileCheck %s
+ 
+ define i64 @f1(i64 %a, i64 %b) {
+ ; CHECK-LABEL: f1:
+Index: test/CodeGen/ARM/pr18364-movw.ll
+===================================================================
+--- test/CodeGen/ARM/pr18364-movw.ll
++++ test/CodeGen/ARM/pr18364-movw.ll
+@@ -0,0 +1,34 @@
++; RUN: llc < %s -mtriple=armv5te | FileCheck %s --check-prefix=V5
++; RUN: llc < %s -mtriple=armv6   | FileCheck %s --check-prefix=V6
++; RUN: llc < %s -mtriple=armv6t2 | FileCheck %s --check-prefix=V6T2
++; RUN: llc < %s -mtriple=armv7   | FileCheck %s --check-prefix=V7
++; PR18364
++
++define i64 @f() #0 {
++entry:
++; V5-NOT: movw
++; V6-NOT: movw
++; V6T2: movw
++; V7: movw
++  %y = alloca i64, align 8
++  %z = alloca i64, align 8
++  store i64 1, i64* %y, align 8
++  store i64 11579764786944, i64* %z, align 8
++  %0 = load i64* %y, align 8
++  %1 = load i64* %z, align 8
++  %sub = sub i64 %0, %1
++  ret i64 %sub
++}
++
++define i64 @g(i64 %a, i32 %b) #0 {
++entry:
++; V5-NOT: movw
++; V6-NOT: movw
++; V6T2: movw
++; V7: movw
++  %0 = mul i64 %a, 86400000
++  %mul = add i64 %0, -210866803200000
++  %conv = sext i32 %b to i64
++  %add = add nsw i64 %mul, %conv
++  ret i64 %add
++}
diff --git a/contrib/llvm/patches/patch-r271282-clang-r200797-r200798-r200805-debug-info-crash.diff b/contrib/llvm/patches/patch-r271282-clang-r200797-r200798-r200805-debug-info-crash.diff
index be4ce55..4088dbb 100644
--- a/contrib/llvm/patches/patch-r271282-clang-r200797-r200798-r200805-debug-info-crash.diff
+++ b/contrib/llvm/patches/patch-r271282-clang-r200797-r200798-r200805-debug-info-crash.diff
@@ -1,8 +1,17 @@
-diff --git a/lib/CodeGen/CGDebugInfo.cpp b/lib/CodeGen/CGDebugInfo.cpp
-index 59ba47c..dddc7e7 100644
---- a/lib/CodeGen/CGDebugInfo.cpp
-+++ b/lib/CodeGen/CGDebugInfo.cpp
-@@ -2251,9 +2251,10 @@ llvm::DICompositeType CGDebugInfo::CreateLimitedType(const RecordType *Ty) {
+Pull in r200797 from upstream clang trunk (by Adrian Prantl):
+
+  Debug info: fix a crasher when when emitting debug info for
+  not-yet-completed templated types. getTypeSize() needs a complete type.
+
+  rdar://problem/15931354
+
+Introduced here: http://svnweb.freebsd.org/changeset/base/271282
+
+Index: tools/clang/lib/CodeGen/CGDebugInfo.cpp
+===================================================================
+--- tools/clang/lib/CodeGen/CGDebugInfo.cpp
++++ tools/clang/lib/CodeGen/CGDebugInfo.cpp
+@@ -2251,9 +2251,10 @@ llvm::DICompositeType CGDebugInfo::CreateLimitedTy
    if (T && (!T.isForwardDecl() || !RD->getDefinition()))
        return T;
  
@@ -16,36 +25,44 @@ index 59ba47c..dddc7e7 100644
      return getOrCreateRecordFwdDecl(Ty, RDContext);
  
    uint64_t Size = CGM.getContext().getTypeSize(Ty);
-diff --git a/test/CodeGenCXX/debug-info-template-fwd.cpp b/test/CodeGenCXX/debug-info-template-fwd.cpp
-new file mode 100644
-index 0000000..b2b7073
---- /dev/null
-+++ b/test/CodeGenCXX/debug-info-template-fwd.cpp
-@@ -0,0 +1,27 @@
+Index: tools/clang/test/CodeGenCXX/debug-info-template-fwd.cpp
+===================================================================
+--- tools/clang/test/CodeGenCXX/debug-info-template-fwd.cpp
++++ tools/clang/test/CodeGenCXX/debug-info-template-fwd.cpp
+@@ -0,0 +1,36 @@
 +// RUN: %clang_cc1 %s -triple=x86_64-apple-darwin -g -emit-llvm -o - | FileCheck %s
-+// This test is for a crash when emitting debug info for not-yet-completed
-+// types.
++// This test is for a crash when emitting debug info for not-yet-completed types.
 +// Test that we don't actually emit a forward decl for the offending class:
-+// CHECK:  [ DW_TAG_structure_type ] [Derived<int>] {{.*}} [def]
++// CHECK:  [ DW_TAG_class_type ] [Derived<const __CFString, Foo>] {{.*}} [def]
 +// rdar://problem/15931354
-+template <class A> class Derived;
++typedef const struct __CFString * CFStringRef;
++template <class R> class Returner {};
++typedef const __CFString String;
 +
-+template <class A> class Base {
-+  static Derived<A> *create();
++template <class A, class B> class Derived;
++
++template <class A, class B>
++class Base
++{
++  static Derived<A, B>* create();
++};
++
++template <class A, class B>
++class Derived : public Base<A, B> {
++public:
++  static void foo();
 +};
 +
-+template <class A> struct Derived : Base<A> {
++class Foo
++{
++  Foo();
++  static Returner<Base<String,Foo> > all();
 +};
 +
-+Base<int> *f;
++Foo::Foo(){}
 +
-+// During the instantiation of Derived<int>, Base<int> becomes required to be
-+// complete - since the declaration has already been emitted (due to 'f',
-+// above), we immediately try to build debug info for Base<int> which then
-+// requires the (incomplete definition) of Derived<int> which is problematic.
-+//
-+// (if 'f' is not present, the point at which Base<int> becomes required to be
-+// complete during the instantiation of Derived<int> is a no-op because
-+// Base<int> was never emitted so we ignore it and carry on until we
-+// wire up the base class of Derived<int> in the debug info later on)
-+Derived<int> d;
++Returner<Base<String,Foo> > Foo::all()
++{
++  Derived<String,Foo>::foo();
++  return Foo::all();
++}
diff --git a/contrib/llvm/patches/patch-r271432-clang-r205331-debug-info-crash.diff b/contrib/llvm/patches/patch-r271432-clang-r205331-debug-info-crash.diff
index 4bbf8a1..a140206 100644
--- a/contrib/llvm/patches/patch-r271432-clang-r205331-debug-info-crash.diff
+++ b/contrib/llvm/patches/patch-r271432-clang-r205331-debug-info-crash.diff
@@ -1,18 +1,16 @@
-commit 96365aef99ec463375dfdaf6eb260823e0477b6a
-Author: Adrian Prantl <aprantl@apple.com>
-Date:   Tue Apr 1 17:52:06 2014 +0000
+Pull in r205331 from upstream clang trunk (by Adrian Prantl):
 
-    Debug info: fix a crash when emitting IndirectFieldDecls, which were
-    previously not handled at all.
-    rdar://problem/16348575
-    
-    git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@205331 91177308-0d34-0410-b5e6-96231b3b80d8
+  Debug info: fix a crash when emitting IndirectFieldDecls, which were
+  previously not handled at all.
+  rdar://problem/16348575
 
-diff --git a/lib/CodeGen/CGDebugInfo.cpp b/lib/CodeGen/CGDebugInfo.cpp
-index 82db942..2556cf9 100644
---- tools/clang/lib/CodeGen/CGDebugInfo.cpp
-+++ tools/clangb/lib/CodeGen/CGDebugInfo.cpp
-@@ -1252,7 +1252,7 @@ CollectTemplateParams(const TemplateParameterList *TPList,
+Introduced here: http://svnweb.freebsd.org/changeset/base/271432
+
+Index: tools/clang/lib/CodeGen/CGDebugInfo.cpp
+===================================================================
+--- tools/clang/lib/CodeGen/CGDebugInfo.cpp	(revision 205330)
++++ tools/clang/lib/CodeGen/CGDebugInfo.cpp	(revision 205331)
+@@ -1252,7 +1252,7 @@ CollectTemplateParams(const TemplateParameterList
          V = CGM.GetAddrOfFunction(FD);
        // Member data pointers have special handling too to compute the fixed
        // offset within the object.
@@ -21,11 +19,10 @@ index 82db942..2556cf9 100644
          // These five lines (& possibly the above member function pointer
          // handling) might be able to be refactored to use similar code in
          // CodeGenModule::getMemberPointerConstant
-diff --git a/test/CodeGenCXX/debug-info-indirect-field-decl.cpp b/test/CodeGenCXX/debug-info-indirect-field-decl.cpp
-new file mode 100644
-index 0000000..131ceba
---- /dev/null
-+++ tools/clang/test/CodeGenCXX/debug-info-indirect-field-decl.cpp
+Index: tools/clang/test/CodeGenCXX/debug-info-indirect-field-decl.cpp
+===================================================================
+--- tools/clang/test/CodeGenCXX/debug-info-indirect-field-decl.cpp	(revision 0)
++++ tools/clang/test/CodeGenCXX/debug-info-indirect-field-decl.cpp	(revision 205331)
 @@ -0,0 +1,17 @@
 +// RUN: %clang_cc1 -emit-llvm -g -triple x86_64-apple-darwin %s -o - | FileCheck %s
 +//
diff --git a/contrib/llvm/patches/patch-r271597-clang-r217410-i386-garbage-float.diff b/contrib/llvm/patches/patch-r271597-clang-r217410-i386-garbage-float.diff
new file mode 100644
index 0000000..c16279a
--- /dev/null
+++ b/contrib/llvm/patches/patch-r271597-clang-r217410-i386-garbage-float.diff
@@ -0,0 +1,64 @@
+Pull in r217410 from upstream llvm trunk (by Bob Wilson):
+
+  Set trunc store action to Expand for all X86 targets.
+
+  When compiling without SSE2, isTruncStoreLegal(F64, F32) would return
+  Legal, whereas with SSE2 it would return Expand. And since the Target
+  doesn't seem to actually handle a truncstore for double -> float, it
+  would just output a store of a full double in the space for a float
+  hence overwriting other bits on the stack.
+
+  Patch by Luqman Aden!
+
+This should fix clang -O0 on i386 assigning garbage to floats, in
+certain scenarios.
+
+Introduced here: http://svnweb.freebsd.org/changeset/base/271597
+
+Index: lib/Target/X86/X86ISelLowering.cpp
+===================================================================
+--- lib/Target/X86/X86ISelLowering.cpp	(revision 208032)
++++ lib/Target/X86/X86ISelLowering.cpp	(working copy)
+@@ -300,6 +300,8 @@ void X86TargetLowering::resetOperationActions() {
+   setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
+   setTruncStoreAction(MVT::i16, MVT::i8,  Expand);
+ 
++  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
++
+   // SETOEQ and SETUNE require checking two conditions.
+   setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand);
+   setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand);
+@@ -1011,8 +1013,6 @@ void X86TargetLowering::resetOperationActions() {
+       AddPromotedToType (ISD::SELECT, VT, MVT::v2i64);
+     }
+ 
+-    setTruncStoreAction(MVT::f64, MVT::f32, Expand);
+-
+     // Custom lower v2i64 and v2f64 selects.
+     setOperationAction(ISD::LOAD,               MVT::v2f64, Legal);
+     setOperationAction(ISD::LOAD,               MVT::v2i64, Legal);
+Index: test/CodeGen/X86/dont-trunc-store-double-to-float.ll
+===================================================================
+--- test/CodeGen/X86/dont-trunc-store-double-to-float.ll	(revision 0)
++++ test/CodeGen/X86/dont-trunc-store-double-to-float.ll	(working copy)
+@@ -0,0 +1,20 @@
++; RUN: llc -march=x86 < %s | FileCheck %s
++
++; CHECK-LABEL: @bar
++; CHECK: movl $1074339512,
++; CHECK: movl $1374389535,
++; CHECK: movl $1078523331,
++define void @bar() unnamed_addr {
++entry-block:
++  %a = alloca double
++  %b = alloca float
++
++  store double 3.140000e+00, double* %a
++  %0 = load double* %a
++
++  %1 = fptrunc double %0 to float
++
++  store float %1, float* %b
++
++  ret void
++}