Userspace library for Chelsio's Terminator 5 based iWARP RNICs (pretty

much every T5 card that does _not_ have "-SO" in its name is RDMA
capable).

This plugs into the OFED verbs framework and allows userspace RDMA
applications to work over T5 RNICs.  Tested with rping.

Obtained from:	Chelsio Communications
Relnotes:	Yes
Sponsored by:	Chelsio Communications

21 files changed, 55842 insertions, 1 deletions

diff --git a/contrib/ofed/libcxgb4/AUTHORS b/contrib/ofed/libcxgb4/AUTHORS
new file mode 100644
index 0000000..5d9d2e2
--- /dev/null
+++ b/contrib/ofed/libcxgb4/AUTHORS
@@ -0,0 +1 @@
+Chelsio Communications, Inc.
diff --git a/contrib/ofed/libcxgb4/COPYING b/contrib/ofed/libcxgb4/COPYING
new file mode 100644
index 0000000..93b666f
--- /dev/null
+++ b/contrib/ofed/libcxgb4/COPYING
@@ -0,0 +1,29 @@
+Copyright (c) 2010-2013. Chelsio Communications. All rights reserved.
+
+This software is available to you under a choice of one of two
+licenses.  You may choose to be licensed under the terms of the GNU
+General Public License (GPL) Version 2, available from the file
+COPYING in the main directory of this source tree, or the
+OpenIB.org BSD license below:
+
+    Redistribution and use in source and binary forms, with or
+    without modification, are permitted provided that the following
+    conditions are met:
+
+     - Redistributions of source code must retain the above
+       copyright notice, this list of conditions and the following
+       disclaimer.
+
+     - Redistributions in binary form must reproduce the above
+       copyright notice, this list of conditions and the following
+       disclaimer in the documentation and/or other materials
+       provided with the distribution.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
diff --git a/contrib/ofed/libcxgb4/ChangeLog b/contrib/ofed/libcxgb4/ChangeLog
new file mode 100644
index 0000000..0c83c24
--- /dev/null
+++ b/contrib/ofed/libcxgb4/ChangeLog
@@ -0,0 +1,1054 @@
+commit 6a417d903b9add7c8ab2b71ac11c85c46671e020
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu Jul 31 11:25:22 2014 -0500
+
+    Spin release 1.3.5.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 52ecbea1b908d3b449022e2d75ebe0ca3885bcf2
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu Jul 31 11:14:05 2014 -0500
+
+    libcxb4: use wc_wmb() instead of wmb().
+    
+    The user mode RDMA macro for wmb() is not sufficient to provide the
+    fencing needed.  This was causing corrupted packets when running multiple
+    WD-UDP sockperf processes.  The correct "sfence" instruction is provided
+    with the wc_wmb() macro.  See /usr/include/infiniband/arch.h.
+    
+    Note:  The kernel implementation of wmb() is sufficient.  This is a
+    libcxgb4 issue only...
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 242c29715372bf6999aa343a5aad5654da3ecf3a
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Wed Jun 18 10:17:00 2014 -0500
+
+    Spin release 1.3.4
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 2d54f4c5604cae24caac493aaf6d8b0907ac2ed2
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Wed Jun 18 10:16:52 2014 -0500
+
+    Support the query_qp() verb
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit f80159d12148774646ad65d03cd070f6d5f86eb4
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Mon Jun 9 15:20:47 2014 -0500
+
+    Account for the full qid range.
+    
+    The total qid range is should really be based on the max_cq attribute.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 5aaf5e7277a1c12964aac11a4cff94520717e805
+Author: Yann Droneaud <ydroneaud@opteya.com>
+Date:   Mon May 5 12:59:23 2014 -0500
+
+    kernel abi: adds explicit padding in struct c4iw_alloc_ucontext_resp
+    
+    i386 ABI disagree with most other ABIs regarding alignment
+    of data type larger than 4 bytes: on most ABIs a padding must
+    be added at end of the structures, while it is not
+    required on i386.
+    
+    Such ABI disagreement will make an x86_64 kernel try to write past
+    the struct c4iw_alloc_ucontext_resp buffer provided by an i386
+    userspace binary. As struct c4iw_alloc_ucontext_resp is likely
+    on stack, see function c4iw_alloc_context(), side effects are
+    expected.
+    
+    On kernel side, this structure was modified for kernel v3.15-rc1
+    by following commit:
+    
+      Commit 05eb23893c2cf9502a9cec0c32e7f1d1ed2895c8
+      Author: Steve Wise <swise@opengridcomputing.com>
+      Date:   Fri Mar 14 21:52:08 2014 +0530
+    
+          cxgb4/iw_cxgb4: Doorbell Drop Avoidance Bug Fixes
+    
+    If boundary check is implemented on kernel side, the x86_64
+    kernel will instead refuse to write past the i386 userspace
+    provided buffer and the uverbs will fail.
+    
+    To fix these issues, this patch adds an explicit padding at end
+    of structure so that i386 and others ABI share the same structure
+    layout. This patch makes c4iw_alloc_context() check for a value
+    in the padding field to detect newer kernel using the field for
+    a future purpose (only activated in debug).
+    
+    With this patch, libcxgb4 will work against older kernel and
+    newer patched kernel.
+    
+    Link: http://marc.info/?i=cover.1399216475.git.ydroneaud@opteya.com
+    Signed-off-by: Yann Droneaud <ydroneaud@opteya.com>
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 5c65bf17913949368db8802656dc7dbc291271ed
+Author: Yann Droneaud <ydroneaud@opteya.com>
+Date:   Mon May 5 12:59:23 2014 -0500
+
+    kernel abi: adds explicit padding in struct c4iw_create_cq_resp
+    
+    i386 ABI disagree with most other ABIs regarding alignment
+    of data type larger than 4 bytes: on most ABIs a padding must
+    be added at end of the structures, while it is not required
+    on i386.
+    
+    Such ABI disagreement will make an x86_64 kernel try to write past
+    the struct c4iw_create_cq_resp buffer provided by an i386
+    userspace binary. As struct c4iw_create_cq_resp is likely
+    on stack, see function c4iw_create_cq(), side effects are
+    expected.
+    
+    On kernel side, this structure was added for kernel v2.6.35-rc1
+    by following commit.
+    
+      Commit cfdda9d764362ab77b11a410bb928400e6520d57
+      Author: Steve Wise <swise@opengridcomputing.com>
+      Date:   Wed Apr 21 15:30:06 2010 -0700
+    
+          RDMA/cxgb4: Add driver for Chelsio T4 RNIC
+    
+    If boundary check is implemented on kernel side, the x86_64 kernel
+    will refuse to write past the i386 userspace provided buffer and the
+    uverbs will fail.
+    
+    To fix these issues, this patch adds an explicit padding at end
+    of structure so that i386 and others ABI share the same structure
+    layout. This patch makes c4iw_create_cq() check for a value in the
+    padding field to detect newer kernel using the field for a future
+    purpose (only activated in debug).
+    
+    With this patch, libcxgb4 will work against older kernel and
+    newer patched kernel.
+    
+    Link: http://marc.info/?i=cover.1399216475.git.ydroneaud@opteya.com
+    
+    Signed-off-by: Yann Droneaud <ydroneaud@opteya.com>
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 4f334446f63e3a34006f504f7c89075423c412b4
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Tue Mar 11 11:47:19 2014 -0500
+
+    Spin release 1.3.3.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 98cea522707232b99ff5c07dd9f57937aa8a7d91
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Tue Mar 11 11:44:16 2014 -0500
+
+    Zero the status_page_size before calling get_context.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomuting.com>
+
+commit a373e16a94524e20492301b0e97f53930133739b
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Tue Feb 18 12:07:19 2014 -0600
+
+    Spin release 1.3.2.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit a2f25730971e8b76033e283f03e79ef4c5dbc4bc
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Tue Feb 18 11:29:50 2014 -0600
+
+    Fixed compilation error with debug enabled.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit f484e0f4c5a4cb249f86a050efd659be37a51204
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Tue Feb 18 11:24:06 2014 -0600
+
+    Use V_PIDX_T5() for T5 devices in ring_db funcs.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 32b74074808da51e5918295bfc63d347548478a0
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Tue Feb 18 11:24:05 2014 -0600
+
+    Call wc_wmb() needed after DB writes.
+    
+    Need to do an sfence after botht he WC and regular PIDX DB write.
+    Otherwise the host might reorder things and cause work request corruption
+    (seen with NFSRDMA).
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit c078eed091a32b930f5bbdf0a12a3be0d0a79cf0
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Tue Feb 18 11:23:57 2014 -0600
+
+    Call rmb() after reading valid gen bit.
+    
+    Some HW platforms can reorder read operations, so we must rmb() after
+    we see a valid gen bit in a CQE but before we read any other fields
+    from the CQE.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 7b482dcdbbd187fd8372f744157ac2b323d32f45
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Tue Feb 18 11:12:06 2014 -0600
+
+    Update copyrights.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit f74316373c0b2a2bd2872ae38f7be516a10503c9
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Tue Feb 18 11:12:06 2014 -0600
+
+    Refresh t4 fw/hw reg files.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 1b8434f22deb30f700246dd2f474eaa2512e4867
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Tue Feb 18 11:12:03 2014 -0600
+
+    Add common device id table and chip types.
+    
+    This will make it easier to merge in new devices.
+
+commit 18e5bc32bbe7e19eb9ea5a34d8b2f7d1e6355105
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Tue Feb 18 10:25:33 2014 -0600
+
+    Remove dead SIM code.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit c8c793385de1d3e9c1edeb7b13cbc964049b8362
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Tue Feb 18 10:23:05 2014 -0600
+
+    Remove dead raw qp code.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 9302c092d46e4c40cbf6b2189aeda08e5ca3fea4
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Tue Feb 18 10:17:52 2014 -0600
+
+    iw_cxgb4/libcxgb4: swsq "signaled" state needs to mind sq_sig_all.
+    
+    When a qp is created, the ULP can request that all sq wrs be signaled.
+    The swsqe entries need to take this into account when marking the entry
+    as signaled.
+    
+    This bug will cause read request CQEs to be silently discarded, and can
+    cause flush problems because the swsqe entry will be mismarked for qps
+    created with sq_sig_all set in the qp init attributes.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 48c6633d4a6510a8c1832ac800f45c2099eb28b4
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Tue Feb 18 10:17:52 2014 -0600
+
+    never consume a pending wr in sq flush.
+    
+    There is a race when moving a QP from RTS->CLOSING where a SQ work
+    request could be posted after the FW receives the RDMA_RI/FINI WR.
+    The SQ work request will never get processed, and should be completed
+    with FLUSHED status.  Function c4iw_flush_sq(), however was dropping
+    the oldest SQ work request when in CLOSING or IDLE states, instead of
+    completing the pending work request. If that oldest pending work request
+    was actually complete and has a CQE in the CQ, then when that CQE is
+    proceessed in poll_cq, we'll BUG_ON() due to the inconsistent SQ/CQ state.
+    
+    This is a very small timing hole and has only been hit once so far.
+    
+    c4iw_flush_sq() MUST always flush all non-completed WRs with FLUSHED
+    status regardless of the QP state.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 1a3a3e8e8da7463e59b74d5c5396e7bd5e303cd4
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Tue Feb 18 10:11:35 2014 -0600
+
+    unmap status page when freeing the context.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 81e83780e44af2ff25c2572b15fe7e8b8cc6e134
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Tue Feb 18 10:05:54 2014 -0600
+
+    DB Drop Avoidance, Version 2.
+    
+    Add support for the device status page mapped per device that is used
+    to enable/disable user db usage.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 5830447cef866432c4d3e65f7e58c51a0c687798
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Tue Feb 18 09:40:39 2014 -0600
+
+    Fix DEBUG code in c4iw_flush_hw_cq().
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 127bc437797ca34e14b261fa653c1d0524d07272
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Tue Feb 18 09:40:38 2014 -0600
+
+    T4 onchip workaround: do the 16 4B MA writes just before DB ring.
+    
+    This is a merge of sw repo changesets 1576, 2149, and 2246.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit ac38281728d12a91725aa67e0273dc26976598fb
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Fri Jul 19 09:37:10 2013 -0500
+
+    Spin release 1.3.1.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 272fcac194318e13f563b46463726cc03ae83dbe
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Fri Jul 19 09:36:35 2013 -0500
+
+    Update copyright.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit ba3183d18168f764700ded52651033a79d2a9a86
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Mon Jun 10 14:10:02 2013 -0500
+
+    get rid of hard coded queue iqs.
+    
+    Since we now get the number of queues available from the driver,
+    we shouldn't be using the hard coded defines anymore.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 2095e0a04bc5357da1b9d346e00d52cf7c236cf6
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Mon Jun 10 14:09:35 2013 -0500
+
+    update configure.in
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit a7a4de4f37a60ffbd8addd8f9ab5505adb86c63f
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Mon Jun 10 14:09:34 2013 -0500
+
+    Mind the sq_sig_all/sq_sig_type QP attributes.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 4a485c8dc1c7c70ab85c708bb4c530eef385424d
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Mon Jun 10 14:09:34 2013 -0500
+
+    always do GTS write if cidx_inc == M_CIDXINC.
+    
+    When polling, we do a GTS update if the accumulated cidx_inc == the cq
+    depth / 16.  This works around a T4 bug.  However, if the cq is large
+    enough, cq depth / 16 exceeds the size of the field in the GTS word.
+    So we also need to update if cidx_inc hits M_CIDXINC to avoid overflowing
+    the field.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit a276f65add45933cf8b16bb09361786cf1932c4b
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Mon Jun 10 14:09:34 2013 -0500
+
+    fixed bug where sq.udb was getting overwritten.
+    
+    There was an erroneous statement in create_rc_qp() which caused the
+    sq.udb va to be overwritten with the rq.udb va only for on-chip queues.
+    This error only affected unmapping of that mapped va when destroying
+    a qp.  In the presence of multiple threads creating/destroying qps, the
+    erroneously unmapped va could have been assigned to another qp mapping.
+    This causes intermittent seg faults as libcxgb4 tries to access memory
+    that has been unmapped in error.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 1cb6249cf722e265d8e2364de0ee5b0d59a8e4cd
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Mon Jun 10 14:09:34 2013 -0500
+
+    flush problem with unsignaled wrs.
+    
+    c4iw_flush_sq() should only flush wrs that have not already been
+    flushed. Since we already track where in the sq we've flushed via
+    sq.cidx_flush, just start at that point and flush any remaining.  This bug
+    only caused a problem in the presence of unsignaled work requests.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 4132e3434d8ffc2b92055649f42c56be77111216
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Mon Jun 10 14:09:31 2013 -0500
+
+    clean up queue dump logic.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit a5e390613548f1dc62d9fe142b6a30a943fc56cf
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Tue Jun 4 12:09:21 2013 -0500
+
+    accounting for unsignled sq wrs fails to deal with wrap.
+    
+    When determining how many wrs are completed with a signaled cqe,
+    correctly deal with queue wraps.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 0c1906cec82443e2323dc69dd5c23ae4314087c0
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Tue Jun 4 12:09:19 2013 -0500
+
+    Handle qp flushes with pending sw cqes.
+    
+    The flush and out of order completion logic has a bug:  If out of order
+    completions are flushed but not yet polled by the consumer and the qp
+    is then flushed, we end up inserting duplicate completions.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 26a19bf6d020dbaab8c6cf13396b39a64f952dba
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Tue Jun 4 11:57:00 2013 -0500
+
+    fixed false uninitialized var warning.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 119e11e72d20a07a806c3385b8cfa6de93f7d114
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu Mar 28 15:15:39 2013 -0500
+
+    Spin release 1.3.0
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit a4a0d3fe768ffa33a75ab3df4bd8c678e7f7180b
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu Mar 28 15:15:38 2013 -0500
+
+    Remove aclocal.m4.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 3c22ddca7cf627d62d06b0ff374fa04192a8cc4c
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu Mar 28 15:15:37 2013 -0500
+
+    libcxgb4: unmap the correct udb/ugts address.
+    
+        The various db and gts variables holding the mapped bar2 pointer
+        get incremented at creation time as a normal part of object creation.
+        However this causes the wrong address to get unmapped when the object is
+        destroyed.  The result is a mapping leak because the munmap() fails.
+        So align them back to their proper page boundary when calling munmap().
+    
+    Singed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 9b2d3af5735e4067b83cde79e08a37142e8fb895
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu Mar 28 15:15:35 2013 -0500
+
+    Query device to get the max supported stags, qps, and cqs.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit e8a595da9129d650caf162b7103368af03e07fcc
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu Mar 28 15:15:33 2013 -0500
+
+    Add T5 support.
+    
+    This commit is composed of a series of patches to enable T5 support.  I
+    folded them into one commit for simplicity.  Plus intermittent patches
+    caused problems/regressions/etc, so its cleaner to have 1 commit to enable
+    the new device.
+    
+    Signed-off-by: Vipul Pandya <vipul@chelsio.com>
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 7cb73aba54eb47d6902c9a3f952c0e37500cac8f
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Mon Mar 4 10:28:32 2013 -0600
+
+    zero out r3 and r4 fields of fw_ri_send_wr messages.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit f61c762e82b3e6e1c27496eecaf2bf8d00f009e3
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Mon Mar 4 10:21:39 2013 -0600
+
+    Add new T4 device IDs.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit c66a627e1e964bad794e9dc40e9a39dc6977aa1e
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Mon Mar 4 10:08:59 2013 -0600
+
+    flush bug can cause application crash
+    
+    This fixes a problem in the flush logic that could occur if the
+    current position is near the end of the queue and the 'count' being
+    retired plus this position was greater than the queue size. In this
+    case the index wasn't being wrapped and the associated swcqe pointer
+    would point past the end of the CQ.
+    
+    Asserts were added to check other possible wrap-error paths.
+    
+    This bug was causing mbw to occasionally crash when flushing the qp.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit c5cdab8ad79cecc996d735011b210729fcc95ecd
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Mon Mar 4 10:08:58 2013 -0600
+
+    Silently eat unsignaled read response cqes.
+    
+    Terminator HW always generates read response cqes.  We need to silently
+    eat them vs returning them to the user.  The perftest benchmark ib_read_bw
+    relies on unsignaled work requests and will crash with this fix.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 1eefdaae19110deae2c20a08ea53cab451fc00bb
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Fri Feb 8 13:51:37 2013 -0600
+
+    Remove useless dma_addr_t define.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit c551f4632cfcd284ad82d1d9b36d1449d109a5de
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Fri Feb 8 13:51:00 2013 -0600
+
+    Disable strict aliasing warnings.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 695a5a4be21f44d49999c83e6ac0699ce90d97c7
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Wed Nov 9 09:50:32 2011 -0600
+
+    Spin release 1.2.0.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 721cfb11ca5697d017bc60167805aea9bbb13ba0
+Author: Vipul Pandya <vipul@chelsio.com>
+Date:   Mon Nov 7 15:08:45 2011 +0530
+
+    libcxgb4: Reset flush_cidx before incrementing cidx.
+    
+    Signed-off-by: Vipul Pandya <vipul@chelsio.com>
+
+commit db4fe38c7ee2b3ad9dc8c33f2b54f0c8cdf8b4d2
+Author: Vipul Pandya <vipul@chelsio.com>
+Date:   Mon Nov 7 15:06:29 2011 +0530
+
+    libcxgb4: Fix multi-flush logic path....again
+    
+    Signed-off-by: Vipul Pandya <vipul@chelsio.com>
+
+commit 19198bdc2f7feb05babcc2a544ae8b48e4943c41
+Author: Vipul Pandya <vipul@chelsio.com>
+Date:   Mon Nov 7 15:02:57 2011 +0530
+
+    libcxgb4: Reset cidx_flush if a active queue starts getting hw cqes
+    
+    Signed-off-by: Vipul Pandya <vipul@chelsio.com>
+
+commit 98545f3a8cbe1670efad080cf908db42269f76ff
+Author: Vipul Pandya <vipul@chelsio.com>
+Date:   Mon Nov 7 14:56:44 2011 +0530
+
+    libcxgb4: Support for flushing a CQ bound to multiple QPs
+    
+    Signed-off-by: Vipul Pandya <vipul@chelsio.com>
+
+commit 86ba968706b3dc8cb232a303201bb03a2d919c88
+Author: Vipul Pandya <vipul@chelsio.com>
+Date:   Mon Nov 7 13:06:43 2011 +0530
+
+    libcxgb4: Checks iw_cxgb4 ABI version to know door bell drop recovery support
+    
+    Store iw_cxgb4 ABI version in a global state. Read that global state in
+    t4_wq_db_enabled to know if iw_cxgb4 driver supports door bell drop recovery.
+    
+    Signed-off-by: Vipul Pandya <vipul@chelsio.com>
+
+commit 2b6563ed5b377dac56c218b809d387089d70312d
+Author: Vipul Pandya <vipul@chelsio.com>
+Date:   Sun Oct 23 16:50:16 2011 +0530
+
+    libcxgb4: fixed compilation warnings
+    
+    Signed-off-by: Vipul Pandya <vipul@chelsio.com>
+
+commit c5c120969c22a04d34adc566085192afc99d0db9
+Author: Vipul Pandya <vipul@chelsio.com>
+Date:   Fri Oct 21 19:05:20 2011 +0530
+
+    libcxgb4: Bug Fix#4410 - Fix 3 segfaults
+    
+    This patch fixes 3 segfaults with below signatures:
+    ----
+    1)
+    Program received signal SIGSEGV, Segmentation fault.
+    [Switching to Thread 0x7ffff7fef710 (LWP 22624)]
+    0x00007ffff75613e4 in create_read_req_cqe (wq=0x7fffe800ada0,
+    hw_cqe=0x7ffff7fc7880, read_cqe=0x7ffff7fee860) at src/cq.c:162
+    162             read_cqe->u.rdma.u.scqe.cidx = wq->sq.oldest_read->idx;
+    (gdb) bt
+    hw_cqe=0x7ffff7fc7880, read_cqe=0x7ffff7fee860) at src/cq.c:162
+    attr=0x7ffff7feeae0, attr_mask=1) at src/verbs.c:691
+    src/verbs.c:721
+    
+    2)
+    Program received signal SIGSEGV, Segmentation fault.
+    [Switching to Thread 0x7ffff6e07710 (LWP 22218)]
+    0x00007ffff71563e4 in create_read_req_cqe (wq=0x7fffe800ada0,
+    hw_cqe=0x7ffff7fc7880, read_cqe=0x7ffff6e02b70) at src/cq.c:162
+    162             read_cqe->u.rdma.u.scqe.cidx = wq->sq.oldest_read->idx;
+    (gdb) bt
+    hw_cqe=0x7ffff7fc7880, read_cqe=0x7ffff6e02b70) at src/cq.c:162
+    src/verbs.c:887
+    
+    3)
+    (gdb) bt
+    wc=0x7ffff51378d0) at src/cq.c:776
+    evd_ptr=<value optimized out>, wc_ptr=<value optimized out>)
+        at /usr/include/infiniband/verbs.h:957
+    ----
+    
+    Signed-off-by: Vipul Pandya <vipul@chelsio.com>
+
+commit 075adec1159606303b40f4b29ef3cea7ab780ac2
+Author: Vipul Pandya <vipul@chelsio.com>
+Date:   Fri Oct 21 18:59:16 2011 +0530
+
+    libcxgb4: return -ENOSYS in c4iw_resize_cq().
+    
+    I fixed a "bug" in c4iw_resize_cq() in an earlier commit which regressed
+    us.  c4iw_resize_cq() was returning 0 always even though we don't support
+    resizing the CQ.  So I change libcxgb4 to return whatever errno is
+    returned by the kernel driver.   However, because the driver didn't set
+    the uverbs capabilities for resize_cq, uverbs returned EINVAL.  The OMPI
+    code checks for -ENOSYS and handles providers that don't support it.
+    If, however, ibv_resize_cq() returns any other error, OMPI bails out.
+    So we need to return -ENOSYS.
+    
+    I didn't see this error, however, running NP192 OMPI/IMB all night long.
+    So it must only try to resize for small jobs and thus I missed the
+    regression.
+    
+    Signed-off-by: Vipul Pandya <vipul@chelsio.com>
+
+commit 320285a3a3a93a614e24a78f7a68780d7791e3c5
+Author: Vipul Pandya <vipul@chelsio.com>
+Date:   Fri Oct 21 18:53:47 2011 +0530
+
+    libcxgb4: Don't flush unsignaled WRs if the QP closed normally
+    
+    - add query_qp support in driver to query the qp state before flushing.
+    
+    - fixed flush logic (again).
+    
+    - don't flush unsignaled WRs is QP had a normal close.
+    
+    - support up to 64K QIDs.
+    
+    Signed-off-by: Vipul Pandya <vipul@chelsio.com>
+
+commit 4c98bebe97aeef1c5cda2f071eb9c1d4fa29c37e
+Author: Vipul Pandya <vipul@chelsio.com>
+Date:   Fri Oct 21 17:58:38 2011 +0530
+
+    libcxgb4: Correctly flush unsignaled WRs followed by a signaled WR.
+    
+    The cq flush logic was not accounting for unsignaled SQ WRs followed by
+    a signaled WR.  The result was too many flushed CQEs causing application
+    faults or assert() failures in libcxgb4 because the SQ state is corrupted.
+    
+    Signed-off-by: Vipul Pandya <vipul@chelsio.com>
+
+commit 8196f85bdefb1511d6d834240a92fdaf815834b8
+Author: Vipul Pandya <vipul@chelsio.com>
+Date:   Fri Oct 21 17:31:03 2011 +0530
+
+    libcxgb4: Remove auto generated ltmain.sh file.
+    
+    Signed-off-by: Vipul Pandya <vipul@chelsio.com>
+
+commit 230d12f42d143eeb53d8c4935ba27620c13e6165
+Author: Vipul Pandya <vipul@chelsio.com>
+Date:   Fri Oct 21 17:20:37 2011 +0530
+
+    libcxgb4: Add debug code to dump state on a stall condition.
+    
+    Signed-off-by: Vipul Pandya <vipul@chelsio.com>
+
+commit 2df0677b22aebb7a22d0e8ca11beb90250b363c7
+Author: Vipul Pandya <vipul@chelsio.com>
+Date:   Fri Oct 21 15:04:46 2011 +0530
+
+    libcxgb4: don't write host idx values when wq is in error.
+    
+    This fixes a regression introduced by the db recovery changes.  The host
+    idx shadow fields at the end of the wq should only be written if the wq
+    is not in error.  Otherwise, a seg fault can occur.
+    
+    Signed-off-by: Vipul Pandya <vipul@chelsio.com>
+
+commit 4eaf4b9added6ca660ef2f9363b24d754185fddf
+Author: Vipul Pandya <vipul@chelsio.com>
+Date:   Thu Oct 20 19:55:57 2011 +0530
+
+    libcxgb4: cq debug changes
+    
+        - turn on cq overflow detection by default
+    
+        - shadow cq->cidx in the cq status page
+    
+    Signed-off-by: Vipul Pandya <vipul@chelsio.com>
+
+commit b15d02248dd1029706d07fa229767d8b68d16c65
+Author: Vipul Pandya <vipul@chelsio.com>
+Date:   Thu Oct 20 19:43:07 2011 +0530
+
+    libcxgb4: DB Drop Recovery for RDMA and LLD queues.
+    
+    Signed-off-by: Vipul Pandya <vipul@chelsio.com>
+
+commit b2c7499eab73cf28cbd9cf86f6ea134e2450cdd3
+Author: Vipul Pandya <vipul@chelsio.com>
+Date:   Sun Oct 23 12:59:24 2011 +0530
+
+    libcxgb4: put queue idx values in status page for debug.
+    
+    Signed-off-by: Vipul Pandya <vipul@chelsio.com>
+
+commit 60a30673a4072b6727e7266f7782607ddcbc8de7
+Author: Vipul Pandya <vipul@chelsio.com>
+Date:   Thu Oct 20 18:07:13 2011 +0530
+
+    libcxgb4: DB Overflow Avoidance.
+    
+    - when user dbs are disabled, call into the kernel driver via modify_qp()
+    to ring the dbs.
+    
+    Signed-off-by: Vipul Pandya <vipul@chelsio.com>
+
+commit c8651d01a2d69d83caff8c01b32be0b23624d8da
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu Mar 10 09:45:00 2011 -0600
+
+    Spin release 1.1.1.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit ace467085deb7327522faeb19e20e13d691f66a2
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu Mar 10 09:34:11 2011 -0600
+
+    Flush MA FIFO for on-chip queues.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 7cb87f46c1784c791d29646104ab355ed920747d
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu Mar 10 09:27:57 2011 -0600
+
+    increase the frequency of CIDX-INC updates.
+    
+    Heavy IMB loads reveal that my current algorithm of doing CIDX-INC
+    GTS writes every 1/2 the CQ depth was not sufficient.  This patch
+    increases the frequency to 1/16.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 7652d71daadda0c3aba9b96311ea623a1e324d77
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Wed Sep 15 16:57:04 2010 -0500
+
+    Spin release 1.1.0.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit ed05d22592bc96987635b2c255a99663f286b812
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Wed Sep 15 16:56:51 2010 -0500
+
+    Support all T4 device IDs.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit b051a2ea9dc7b6ffa08f955e60b331e42fec8672
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Wed Sep 15 15:54:35 2010 -0500
+
+    Support ABI 0 and 1 versions of the iwarp driver.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 62f1363bb716e2283f9e2b885e5f02a6d5c692d1
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Wed Sep 15 14:06:17 2010 -0500
+
+    Bump the slots per SQ to 5 to allow up to 128MB fast registers.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit d51e041839254d656cc260dba3f26a7c9d73aa56
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Wed Sep 15 14:06:16 2010 -0500
+
+    Raw QP implementation
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 8f55539d0b8aea70084edf31687e590cf5a57221
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Wed Sep 15 14:03:55 2010 -0500
+
+    Add compile-time user mode rdma stats.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 2e3531bbd91d7a6f057b3503132aef5e64adb548
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Wed Sep 15 13:57:03 2010 -0500
+
+    Support on-chip SQs.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 65bb173b86c2e0a9ff5f877e4d3951cb8daa6e97
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Wed Sep 15 13:54:44 2010 -0500
+
+    Work around TERM CQE hw bug.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 6bb37d1f72652d4ed0c1972bc673f4418cc7a856
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Wed Sep 15 13:54:44 2010 -0500
+
+    Zero out padding in iSGLs.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit aad128404c494ec4779055b5e550c2d7de7d5ca9
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu Jul 22 14:58:51 2010 -0500
+
+    Spin release 1.0.4
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 07ac253a8a479fd59fe654baf5a94ffc1de13765
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu Jul 22 14:57:27 2010 -0500
+
+    Do GTS/CIDX_INC writes in the poll path to avoid drops.
+    
+    With T4 asic, we still see the CIDX_INC overflow/drops.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 3394198639f811c86ab519c43197a9b724435cb0
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu Jul 22 14:56:53 2010 -0500
+
+    Support T420 and T440 cards.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 311dd1c8ec3e38287895053dce52dfef5ed5f0b1
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Fri Jun 11 10:40:53 2010 -0500
+
+    Spin release 1.0.3.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit a62d7cf38f7b6c731486ff969ee7e3a4238ebc3f
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Fri Jun 11 10:37:17 2010 -0500
+
+    Support variable sized work requests.
+    
+    T4 EQ entries are in multiples of 64B.  Currently the RDMA SQ and RQ
+    use fixed sized entries composed of 4 EQ entries for the SQ and 2 EQ
+    entries for the RQ.  For optimial latency with small IO, we need to
+    change this so the HW only needs to DMA the EQ entries actually used by
+    a given work request.
+    
+    Implementation:
+    
+    - add wq_pidx counter to track where we are in the EQ.  cidx/pidx are
+    used for the sw sq/rq tracking and flow control.
+    
+    - the variable part of work requests is the SGL.  Add new functions to
+    build the SGL and/or immediate data directly in the EQ memory wrapping
+    when needed.
+    
+    - adjust the min burst size for the EQ contexts to 64B.
+
+commit 3be829d117a8ca7957370b09b477fe551de0cea5
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu May 20 15:52:59 2010 -0500
+
+    Spin release 1.0.2.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit dc1ea232e8ece4ba53d2496befad14bd433e2e3e
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu May 20 15:48:37 2010 -0500
+
+    only insert sq qid in lookup tables.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 00c60fd47b71dac42d864662567701e2618ff45d
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu May 20 15:47:37 2010 -0500
+
+    Update some driver limits.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit f25661e19d728a0a33a221c0646a9fce9b160f8b
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu May 20 15:46:38 2010 -0500
+
+    Fix cq arm overflow.
+    
+    - wrap cq->cqidx_inc based on cq size
+    - optimize t4_arm_cq() logic
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 8c224aca8f1acd219010e46da538ae4c9a4f9d1a
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu May 20 15:45:54 2010 -0500
+
+    Optimize cq overflow detection.
+    
+    1) save the timestamp flit in the cq when we consume a CQE
+    
+    2) always compare the saved flit with the previous entry flit when reading
+    the next CQE entry.  If the flits don't compare, then we've overflowed.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 0c0cfbdbeb32548994d94a6278c74e2a4f11d9ba
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu May 6 17:57:56 2010 -0500
+
+    Spin release 1.0.1.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 5b9ebdfbcd6df0f02375717aff20400ac33dc47f
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu May 6 17:34:07 2010 -0500
+
+    Update code with new t4fw interface.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 0116d75d8dcc2f4018d0c0074728ca7d127a5065
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu May 6 17:32:10 2010 -0500
+
+    Refresh t4fw-interface.h
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit ad7a3f8dea2873a3a600859cfe8eb10ad979ddb1
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu May 6 17:30:42 2010 -0500
+
+    Avoid CQ arm overflows.
+    
+    There are 2 limits that need to be taken into account when arming the CQ.
+    1) the GTS register limits the delta idx to <= M_CIDXINC.
+    2) T4 HW limits it to < cq size.
+    
+    Update t4_arm_cq() to account for these limits.
+
+commit 2905808680aad82b4f295850551bbe15711c2f42
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu May 6 17:30:12 2010 -0500
+
+    Poll fixes.
+    
+    - when synthesizing CQEs for the SWCQ, always use SQ QID.
+    - when flushing, ignore target side read response errors.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 7a7962e856eb606e25a1529bc7f2945e639042b7
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu May 6 17:24:07 2010 -0500
+
+    Fix CQ overflow detection.
+    
+    CQ overflow detection needs to read the gen bit and the timestamp in
+    one read operation.  Otherwise false overflows can result.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 5ca340c298c61c9019d8593ee7acdbda93fdd498
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Thu May 6 17:23:53 2010 -0500
+
+    libcxgb3: create_read_req_cqe() needs to swap read length.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit 9bd1e60d3aea10dbe7cb9920363e485b845d85a3
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Wed Apr 14 10:36:41 2010 -0500
+
+    Refresh t4fw_interface.h
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
+
+commit d6e6ae69be5edffc566178e1b7e6402d61a5a786
+Author: Steve Wise <swise@opengridcomputing.com>
+Date:   Fri Apr 2 16:01:31 2010 -0500
+
+    Add libcxgb4 files.
+    
+    Signed-off-by: Steve Wise <swise@opengridcomputing.com>
diff --git a/contrib/ofed/libcxgb4/README b/contrib/ofed/libcxgb4/README
new file mode 100644
index 0000000..5f73aef
--- /dev/null
+++ b/contrib/ofed/libcxgb4/README
@@ -0,0 +1,19 @@
+Introduction
+============
+
+libcxgb4 is a userspace driver for the Chelsio T5 iWARP RNICs.  It works
+as a plug-in module for libibverbs that allows programs to use Chelsio
+RNICs directly from userspace.  See the libibverbs package for more
+information.
+
+Using libcxgb4
+===================
+
+libcxgb4 will be loaded and used automatically by programs linked with
+libibverbs.  The iw_cxgbe kernel module must be loaded for Chelsio RNIC
+devices to be detected and used.
+
+Supported Hardware
+==================
+
+libcxgb4 supports the Chelsio T5 family of adapters.
diff --git a/contrib/ofed/libcxgb4/cxgb4.driver b/contrib/ofed/libcxgb4/cxgb4.driver
new file mode 100644
index 0000000..0ee45f1
--- /dev/null
+++ b/contrib/ofed/libcxgb4/cxgb4.driver
@@ -0,0 +1 @@
+driver cxgb4 
diff --git a/contrib/ofed/libcxgb4/src/cq.c b/contrib/ofed/libcxgb4/src/cq.c
new file mode 100644
index 0000000..f028a22
--- /dev/null
+++ b/contrib/ofed/libcxgb4/src/cq.c
@@ -0,0 +1,753 @@
+/*
+ * Copyright (c) 2006-2014 Chelsio, Inc. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#if HAVE_CONFIG_H
+#  include <config.h>
+#endif				/* HAVE_CONFIG_H */
+
+#include <stdio.h>
+#include <syslog.h>
+#include <pthread.h>
+#include <sys/errno.h>
+#include <netinet/in.h>
+#include <infiniband/opcode.h>
+#include "libcxgb4.h"
+#include "cxgb4-abi.h"
+
+static void insert_recv_cqe(struct t4_wq *wq, struct t4_cq *cq)
+{
+	struct t4_cqe cqe;
+
+	PDBG("%s wq %p cq %p sw_cidx %u sw_pidx %u\n", __func__,
+	     wq, cq, cq->sw_cidx, cq->sw_pidx);
+	memset(&cqe, 0, sizeof(cqe));
+	cqe.header = cpu_to_be32(V_CQE_STATUS(T4_ERR_SWFLUSH) |
+			         V_CQE_OPCODE(FW_RI_SEND) |
+				 V_CQE_TYPE(0) |
+				 V_CQE_SWCQE(1) |
+				 V_CQE_QPID(wq->sq.qid));
+	cqe.bits_type_ts = cpu_to_be64(V_CQE_GENBIT((u64)cq->gen));
+	cq->sw_queue[cq->sw_pidx] = cqe;
+	t4_swcq_produce(cq);
+}
+
+int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count)
+{
+	int flushed = 0;
+	int in_use = wq->rq.in_use - count;
+
+	BUG_ON(in_use < 0);
+	PDBG("%s wq %p cq %p rq.in_use %u skip count %u\n", __func__,
+	     wq, cq, wq->rq.in_use, count);
+	while (in_use--) {
+		insert_recv_cqe(wq, cq);
+		flushed++;
+	}
+	return flushed;
+}
+
+static void insert_sq_cqe(struct t4_wq *wq, struct t4_cq *cq,
+		          struct t4_swsqe *swcqe)
+{
+	struct t4_cqe cqe;
+
+	PDBG("%s wq %p cq %p sw_cidx %u sw_pidx %u\n", __func__,
+	     wq, cq, cq->sw_cidx, cq->sw_pidx);
+	memset(&cqe, 0, sizeof(cqe));
+	cqe.header = cpu_to_be32(V_CQE_STATUS(T4_ERR_SWFLUSH) |
+			         V_CQE_OPCODE(swcqe->opcode) |
+			         V_CQE_TYPE(1) |
+			         V_CQE_SWCQE(1) |
+			         V_CQE_QPID(wq->sq.qid));
+	CQE_WRID_SQ_IDX(&cqe) = swcqe->idx;
+	cqe.bits_type_ts = cpu_to_be64(V_CQE_GENBIT((u64)cq->gen));
+	cq->sw_queue[cq->sw_pidx] = cqe;
+	t4_swcq_produce(cq);
+}
+
+static void advance_oldest_read(struct t4_wq *wq);
+
+void c4iw_flush_sq(struct c4iw_qp *qhp)
+{
+	unsigned short flushed = 0;
+	struct t4_wq *wq = &qhp->wq;
+	struct c4iw_cq *chp = to_c4iw_cq(qhp->ibv_qp.send_cq);
+	struct t4_cq *cq = &chp->cq;
+	int idx;
+	struct t4_swsqe *swsqe;
+	
+	if (wq->sq.flush_cidx == -1)
+		wq->sq.flush_cidx = wq->sq.cidx;
+	idx = wq->sq.flush_cidx;
+	BUG_ON(idx >= wq->sq.size);
+	while (idx != wq->sq.pidx) {
+		swsqe = &wq->sq.sw_sq[idx];
+		BUG_ON(swsqe->flushed);
+		swsqe->flushed = 1;
+		insert_sq_cqe(wq, cq, swsqe);
+		if (wq->sq.oldest_read == swsqe) {
+			BUG_ON(swsqe->opcode != FW_RI_READ_REQ);
+			advance_oldest_read(wq);
+		}
+		flushed++;
+		if (++idx == wq->sq.size)
+			idx = 0;
+	}
+	wq->sq.flush_cidx += flushed;
+	if (wq->sq.flush_cidx >= wq->sq.size)
+		wq->sq.flush_cidx -= wq->sq.size;
+}
+
+static void flush_completed_wrs(struct t4_wq *wq, struct t4_cq *cq)
+{
+	struct t4_swsqe *swsqe;
+	unsigned short cidx;
+ 
+	if (wq->sq.flush_cidx == -1)
+		wq->sq.flush_cidx = wq->sq.cidx;
+	cidx = wq->sq.flush_cidx;
+	BUG_ON(cidx >= wq->sq.size);
+
+	while (cidx != wq->sq.pidx) {
+		swsqe = &wq->sq.sw_sq[cidx];
+		if (!swsqe->signaled) {
+			if (++cidx == wq->sq.size)
+				cidx = 0;
+		} else if (swsqe->complete) {
+
+			BUG_ON(swsqe->flushed);
+
+			/*
+			 * Insert this completed cqe into the swcq.
+			 */
+			PDBG("%s moving cqe into swcq sq idx %u cq idx %u\n",
+			     __func__, cidx, cq->sw_pidx);
+
+			swsqe->cqe.header |= htonl(V_CQE_SWCQE(1));
+			cq->sw_queue[cq->sw_pidx] = swsqe->cqe;
+			t4_swcq_produce(cq);
+			swsqe->flushed = 1;
+			if (++cidx == wq->sq.size)
+				cidx = 0;
+			wq->sq.flush_cidx = cidx;
+		} else
+			break;
+	}
+}
+
+static void create_read_req_cqe(struct t4_wq *wq, struct t4_cqe *hw_cqe,
+				struct t4_cqe *read_cqe)
+{
+	read_cqe->u.scqe.cidx = wq->sq.oldest_read->idx;
+	read_cqe->len = ntohl(wq->sq.oldest_read->read_len);
+	read_cqe->header = htonl(V_CQE_QPID(CQE_QPID(hw_cqe)) |
+				 V_CQE_SWCQE(SW_CQE(hw_cqe)) |
+				 V_CQE_OPCODE(FW_RI_READ_REQ) |
+				 V_CQE_TYPE(1));
+	read_cqe->bits_type_ts = hw_cqe->bits_type_ts;
+}
+
+static void advance_oldest_read(struct t4_wq *wq)
+{
+
+	u32 rptr = wq->sq.oldest_read - wq->sq.sw_sq + 1;
+
+	if (rptr == wq->sq.size)
+		rptr = 0;
+	while (rptr != wq->sq.pidx) {
+		wq->sq.oldest_read = &wq->sq.sw_sq[rptr];
+
+		if (wq->sq.oldest_read->opcode == FW_RI_READ_REQ)
+			return;
+		if (++rptr == wq->sq.size)
+			rptr = 0;
+	}
+	wq->sq.oldest_read = NULL;
+}
+
+/*
+ * Move all CQEs from the HWCQ into the SWCQ.
+ * Deal with out-of-order and/or completions that complete
+ * prior unsignalled WRs.
+ */
+void c4iw_flush_hw_cq(struct c4iw_cq *chp)
+{
+	struct t4_cqe *hw_cqe, *swcqe, read_cqe;
+	struct c4iw_qp *qhp;
+	struct t4_swsqe *swsqe;
+	int ret;
+
+	PDBG("%s  cqid 0x%x\n", __func__, chp->cq.cqid);
+	ret = t4_next_hw_cqe(&chp->cq, &hw_cqe);
+
+	/*
+	 * This logic is similar to poll_cq(), but not quite the same
+	 * unfortunately.  Need to move pertinent HW CQEs to the SW CQ but
+	 * also do any translation magic that poll_cq() normally does.
+	 */
+	while (!ret) {
+		qhp = get_qhp(chp->rhp, CQE_QPID(hw_cqe));
+
+		/*
+		 * drop CQEs with no associated QP
+		 */
+		if (qhp == NULL)
+			goto next_cqe;
+
+		if (CQE_OPCODE(hw_cqe) == FW_RI_TERMINATE)
+			goto next_cqe;
+
+		if (CQE_OPCODE(hw_cqe) == FW_RI_READ_RESP) {
+
+			/*
+			 * If we have reached here because of async
+			 * event or other error, and have egress error
+			 * then drop
+			 */
+			if (CQE_TYPE(hw_cqe) == 1) {
+				syslog(LOG_CRIT, "%s: got egress error in \
+					read-response, dropping!\n", __func__);
+				goto next_cqe;
+			}
+
+			/*
+			 * drop peer2peer RTR reads.
+			 */
+			if (CQE_WRID_STAG(hw_cqe) == 1)
+				goto next_cqe;
+
+			/*
+			 * Eat completions for unsignaled read WRs.
+			 */
+			if (!qhp->wq.sq.oldest_read->signaled) {
+				advance_oldest_read(&qhp->wq);
+				goto next_cqe;
+			}
+
+			/*
+			 * Don't write to the HWCQ, create a new read req CQE
+			 * in local memory and move it into the swcq.
+			 */
+			create_read_req_cqe(&qhp->wq, hw_cqe, &read_cqe);
+			hw_cqe = &read_cqe;
+			advance_oldest_read(&qhp->wq);
+		}
+
+		/* if its a SQ completion, then do the magic to move all the
+		 * unsignaled and now in-order completions into the swcq.
+		 */
+		if (SQ_TYPE(hw_cqe)) {
+			int idx = CQE_WRID_SQ_IDX(hw_cqe);
+
+			BUG_ON(idx >= qhp->wq.sq.size);
+			swsqe = &qhp->wq.sq.sw_sq[idx];
+			swsqe->cqe = *hw_cqe;
+			swsqe->complete = 1;
+			flush_completed_wrs(&qhp->wq, &chp->cq);
+		} else {
+			swcqe = &chp->cq.sw_queue[chp->cq.sw_pidx];
+			*swcqe = *hw_cqe;
+			swcqe->header |= cpu_to_be32(V_CQE_SWCQE(1));
+			t4_swcq_produce(&chp->cq);
+		}
+next_cqe:
+		t4_hwcq_consume(&chp->cq);
+		ret = t4_next_hw_cqe(&chp->cq, &hw_cqe);
+	}
+}
+
+static int cqe_completes_wr(struct t4_cqe *cqe, struct t4_wq *wq)
+{
+	if (CQE_OPCODE(cqe) == FW_RI_TERMINATE)
+		return 0;
+
+	if ((CQE_OPCODE(cqe) == FW_RI_RDMA_WRITE) && RQ_TYPE(cqe))
+		return 0;
+
+	if ((CQE_OPCODE(cqe) == FW_RI_READ_RESP) && SQ_TYPE(cqe))
+		return 0;
+
+	if (CQE_SEND_OPCODE(cqe) && RQ_TYPE(cqe) && t4_rq_empty(wq))
+		return 0;
+	return 1;
+}
+
+void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count)
+{
+	struct t4_cqe *cqe;
+	u32 ptr;
+
+	*count = 0;
+	ptr = cq->sw_cidx;
+	BUG_ON(ptr >= cq->size);
+	while (ptr != cq->sw_pidx) {
+		cqe = &cq->sw_queue[ptr];
+		if (RQ_TYPE(cqe) && (CQE_OPCODE(cqe) != FW_RI_READ_RESP) &&
+		    (CQE_QPID(cqe) == wq->sq.qid) && cqe_completes_wr(cqe, wq))
+			(*count)++;
+		if (++ptr == cq->size)
+			ptr = 0;
+	}
+	PDBG("%s cq %p count %d\n", __func__, cq, *count);
+}
+
+static void dump_cqe(void *arg)
+{
+	u64 *p = arg;
+	syslog(LOG_NOTICE, "cxgb4 err cqe %016lx %016lx %016lx %016lx\n",
+	       be64_to_cpu(p[0]),
+	       be64_to_cpu(p[1]),
+	       be64_to_cpu(p[2]),
+	       be64_to_cpu(p[3]));
+}
+
+/*
+ * poll_cq
+ *
+ * Caller must:
+ *     check the validity of the first CQE,
+ *     supply the wq assicated with the qpid.
+ *
+ * credit: cq credit to return to sge.
+ * cqe_flushed: 1 iff the CQE is flushed.
+ * cqe: copy of the polled CQE.
+ *
+ * return value:
+ *    0		    CQE returned ok.
+ *    -EAGAIN       CQE skipped, try again.
+ *    -EOVERFLOW    CQ overflow detected.
+ */
+static int poll_cq(struct t4_wq *wq, struct t4_cq *cq, struct t4_cqe *cqe,
+	           u8 *cqe_flushed, u64 *cookie, u32 *credit)
+{
+	int ret = 0;
+	struct t4_cqe *hw_cqe, read_cqe;
+
+	*cqe_flushed = 0;
+	*credit = 0;
+
+	ret = t4_next_cqe(cq, &hw_cqe);
+	if (ret)
+		return ret;
+
+	PDBG("%s CQE OVF %u qpid 0x%0x genbit %u type %u status 0x%0x"
+	     " opcode 0x%0x len 0x%0x wrid_hi_stag 0x%x wrid_low_msn 0x%x\n",
+	     __func__, CQE_OVFBIT(hw_cqe), CQE_QPID(hw_cqe),
+	     CQE_GENBIT(hw_cqe), CQE_TYPE(hw_cqe), CQE_STATUS(hw_cqe),
+	     CQE_OPCODE(hw_cqe), CQE_LEN(hw_cqe), CQE_WRID_HI(hw_cqe),
+	     CQE_WRID_LOW(hw_cqe));
+
+	/*
+	 * skip cqe's not affiliated with a QP.
+	 */
+	if (wq == NULL) {
+		ret = -EAGAIN;
+		goto skip_cqe;
+	}
+
+	/*
+	 * Gotta tweak READ completions:
+	 *	1) the cqe doesn't contain the sq_wptr from the wr.
+	 *	2) opcode not reflected from the wr.
+	 *	3) read_len not reflected from the wr.
+	 *	4) T4 HW (for now) inserts target read response failures which
+	 * 	   need to be skipped.
+	 */
+	if (CQE_OPCODE(hw_cqe) == FW_RI_READ_RESP) {
+
+		/*
+		 * If we have reached here because of async
+		 * event or other error, and have egress error
+		 * then drop
+		 */
+		if (CQE_TYPE(hw_cqe) == 1) {
+			syslog(LOG_CRIT, "%s: got egress error in \
+				read-response, dropping!\n", __func__);
+			if (CQE_STATUS(hw_cqe))
+				t4_set_wq_in_error(wq);
+			ret = -EAGAIN;
+			goto skip_cqe;
+		}
+
+		/*
+		 * If this is an unsolicited read response, then the read
+		 * was generated by the kernel driver as part of peer-2-peer
+		 * connection setup, or a target read response failure.
+		 * So skip the completion.
+		 */
+		if (CQE_WRID_STAG(hw_cqe) == 1) {
+			if (CQE_STATUS(hw_cqe))
+				t4_set_wq_in_error(wq);
+			ret = -EAGAIN;
+			goto skip_cqe;
+		}
+
+		/*
+		 * Eat completions for unsignaled read WRs.
+		 */
+		if (!wq->sq.oldest_read->signaled) {
+			advance_oldest_read(wq);
+			ret = -EAGAIN;
+			goto skip_cqe;
+		}
+
+		/*
+		 * Don't write to the HWCQ, so create a new read req CQE
+		 * in local memory.
+		 */
+		create_read_req_cqe(wq, hw_cqe, &read_cqe);
+		hw_cqe = &read_cqe;
+		advance_oldest_read(wq);
+	}
+
+	if (CQE_STATUS(hw_cqe) || t4_wq_in_error(wq)) {
+		*cqe_flushed = (CQE_STATUS(hw_cqe) == T4_ERR_SWFLUSH);
+		wq->error = 1;
+
+		if (!*cqe_flushed && CQE_STATUS(hw_cqe))
+			dump_cqe(hw_cqe);
+
+		BUG_ON((cqe_flushed == 0) && !SW_CQE(hw_cqe));
+		goto proc_cqe;
+	}
+
+	if (CQE_OPCODE(hw_cqe) == FW_RI_TERMINATE) {
+		ret = -EAGAIN;
+		goto skip_cqe;
+	}
+
+	/*
+	 * RECV completion.
+	 */
+	if (RQ_TYPE(hw_cqe)) {
+
+		/*
+		 * HW only validates 4 bits of MSN.  So we must validate that
+		 * the MSN in the SEND is the next expected MSN.  If its not,
+		 * then we complete this with T4_ERR_MSN and mark the wq in
+		 * error.
+		 */
+
+		if (t4_rq_empty(wq)) {
+			t4_set_wq_in_error(wq);
+			ret = -EAGAIN;
+			goto skip_cqe;
+		}
+		if (unlikely((CQE_WRID_MSN(hw_cqe) != (wq->rq.msn)))) {
+			t4_set_wq_in_error(wq);
+			hw_cqe->header |= htonl(V_CQE_STATUS(T4_ERR_MSN));
+			goto proc_cqe;
+		}
+		goto proc_cqe;
+	}
+
+	/*
+	 * If we get here its a send completion.
+	 *
+	 * Handle out of order completion. These get stuffed
+	 * in the SW SQ. Then the SW SQ is walked to move any
+	 * now in-order completions into the SW CQ.  This handles
+	 * 2 cases:
+	 *	1) reaping unsignaled WRs when the first subsequent
+	 *	   signaled WR is completed.
+	 *	2) out of order read completions.
+	 */
+	if (!SW_CQE(hw_cqe) && (CQE_WRID_SQ_IDX(hw_cqe) != wq->sq.cidx)) {
+		struct t4_swsqe *swsqe;
+		int idx =  CQE_WRID_SQ_IDX(hw_cqe);
+
+		PDBG("%s out of order completion going in sw_sq at idx %u\n",
+		     __func__, idx);
+		BUG_ON(idx >= wq->sq.size);
+		swsqe = &wq->sq.sw_sq[idx];
+		swsqe->cqe = *hw_cqe;
+		swsqe->complete = 1;
+		ret = -EAGAIN;
+		goto flush_wq;
+	}
+
+proc_cqe:
+	*cqe = *hw_cqe;
+
+	/*
+	 * Reap the associated WR(s) that are freed up with this
+	 * completion.
+	 */
+	if (SQ_TYPE(hw_cqe)) {
+		int idx = CQE_WRID_SQ_IDX(hw_cqe);
+		BUG_ON(idx >= wq->sq.size);
+
+		/*
+		 * Account for any unsignaled completions completed by
+		 * this signaled completion.  In this case, cidx points
+		 * to the first unsignaled one, and idx points to the
+		 * signaled one.  So adjust in_use based on this delta.
+		 * if this is not completing any unsigned wrs, then the
+		 * delta will be 0. Handle wrapping also!
+		 */
+		if (idx < wq->sq.cidx)
+			wq->sq.in_use -= wq->sq.size + idx - wq->sq.cidx;
+		else
+			wq->sq.in_use -= idx - wq->sq.cidx;
+		BUG_ON(wq->sq.in_use <= 0 || wq->sq.in_use >= wq->sq.size);
+
+		wq->sq.cidx = (u16)idx;
+		PDBG("%s completing sq idx %u\n", __func__, wq->sq.cidx);
+		*cookie = wq->sq.sw_sq[wq->sq.cidx].wr_id;
+		t4_sq_consume(wq);
+	} else {
+		PDBG("%s completing rq idx %u\n", __func__, wq->rq.cidx);
+		BUG_ON(wq->rq.cidx >= wq->rq.size);
+		*cookie = wq->rq.sw_rq[wq->rq.cidx].wr_id;
+		BUG_ON(t4_rq_empty(wq));
+		t4_rq_consume(wq);
+		goto skip_cqe;
+	}
+
+flush_wq:
+	/*
+	 * Flush any completed cqes that are now in-order.
+	 */
+	flush_completed_wrs(wq, cq);
+
+skip_cqe:
+	if (SW_CQE(hw_cqe)) {
+		PDBG("%s cq %p cqid 0x%x skip sw cqe cidx %u\n",
+		     __func__, cq, cq->cqid, cq->sw_cidx);
+		t4_swcq_consume(cq);
+	} else {
+		PDBG("%s cq %p cqid 0x%x skip hw cqe cidx %u\n",
+		     __func__, cq, cq->cqid, cq->cidx);
+		t4_hwcq_consume(cq);
+	}
+	return ret;
+}
+
+/*
+ * Get one cq entry from c4iw and map it to openib.
+ *
+ * Returns:
+ *	0			cqe returned
+ *	-ENODATA		EMPTY;
+ *	-EAGAIN			caller must try again
+ *	any other -errno	fatal error
+ */
+static int c4iw_poll_cq_one(struct c4iw_cq *chp, struct ibv_wc *wc)
+{
+	struct c4iw_qp *qhp = NULL;
+	struct t4_cqe cqe, *rd_cqe;
+	struct t4_wq *wq;
+	u32 credit = 0;
+	u8 cqe_flushed;
+	u64 cookie = 0;
+	int ret;
+
+	ret = t4_next_cqe(&chp->cq, &rd_cqe);
+
+	if (ret) {
+#ifdef STALL_DETECTION
+		if (ret == -ENODATA && stall_to && !chp->dumped) {
+			struct timeval t;
+
+			gettimeofday(&t, NULL);
+			if ((t.tv_sec - chp->time.tv_sec) > stall_to) {
+				dump_state();
+				chp->dumped = 1;
+			}
+		}
+#endif
+		return ret;
+	}
+
+#ifdef STALL_DETECTION
+	gettimeofday(&chp->time, NULL);
+#endif
+
+	qhp = get_qhp(chp->rhp, CQE_QPID(rd_cqe));
+	if (!qhp)
+		wq = NULL;
+	else {
+		pthread_spin_lock(&qhp->lock);
+		wq = &(qhp->wq);
+	}
+	ret = poll_cq(wq, &(chp->cq), &cqe, &cqe_flushed, &cookie, &credit);
+	if (ret)
+		goto out;
+
+	INC_STAT(cqe);
+	wc->wr_id = cookie;
+	wc->qp_num = qhp->wq.sq.qid;
+	wc->vendor_err = CQE_STATUS(&cqe);
+	wc->wc_flags = 0;
+
+	PDBG("%s qpid 0x%x type %d opcode %d status 0x%x wrid hi 0x%x "
+	     "lo 0x%x cookie 0x%llx\n", __func__,
+	     CQE_QPID(&cqe), CQE_TYPE(&cqe),
+	     CQE_OPCODE(&cqe), CQE_STATUS(&cqe), CQE_WRID_HI(&cqe),
+	     CQE_WRID_LOW(&cqe), (unsigned long long)cookie);
+
+	if (CQE_TYPE(&cqe) == 0) {
+		if (!CQE_STATUS(&cqe))
+			wc->byte_len = CQE_LEN(&cqe);
+		else
+			wc->byte_len = 0;
+		wc->opcode = IBV_WC_RECV;
+	} else {
+		switch (CQE_OPCODE(&cqe)) {
+		case FW_RI_RDMA_WRITE:
+			wc->opcode = IBV_WC_RDMA_WRITE;
+			break;
+		case FW_RI_READ_REQ:
+			wc->opcode = IBV_WC_RDMA_READ;
+			wc->byte_len = CQE_LEN(&cqe);
+			break;
+		case FW_RI_SEND:
+		case FW_RI_SEND_WITH_SE:
+		case FW_RI_SEND_WITH_INV:
+		case FW_RI_SEND_WITH_SE_INV:
+			wc->opcode = IBV_WC_SEND;
+			break;
+		case FW_RI_BIND_MW:
+			wc->opcode = IBV_WC_BIND_MW;
+			break;
+		default:
+			PDBG("Unexpected opcode %d "
+			     "in the CQE received for QPID=0x%0x\n",
+			     CQE_OPCODE(&cqe), CQE_QPID(&cqe));
+			ret = -EINVAL;
+			goto out;
+		}
+	}
+
+	if (cqe_flushed)
+		wc->status = IBV_WC_WR_FLUSH_ERR;
+	else {
+
+		switch (CQE_STATUS(&cqe)) {
+		case T4_ERR_SUCCESS:
+			wc->status = IBV_WC_SUCCESS;
+			break;
+		case T4_ERR_STAG:
+			wc->status = IBV_WC_LOC_ACCESS_ERR;
+			break;
+		case T4_ERR_PDID:
+			wc->status = IBV_WC_LOC_PROT_ERR;
+			break;
+		case T4_ERR_QPID:
+		case T4_ERR_ACCESS:
+			wc->status = IBV_WC_LOC_ACCESS_ERR;
+			break;
+		case T4_ERR_WRAP:
+			wc->status = IBV_WC_GENERAL_ERR;
+			break;
+		case T4_ERR_BOUND:
+			wc->status = IBV_WC_LOC_LEN_ERR;
+			break;
+		case T4_ERR_INVALIDATE_SHARED_MR:
+		case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
+			wc->status = IBV_WC_MW_BIND_ERR;
+			break;
+		case T4_ERR_CRC:
+		case T4_ERR_MARKER:
+		case T4_ERR_PDU_LEN_ERR:
+		case T4_ERR_OUT_OF_RQE:
+		case T4_ERR_DDP_VERSION:
+		case T4_ERR_RDMA_VERSION:
+		case T4_ERR_DDP_QUEUE_NUM:
+		case T4_ERR_MSN:
+		case T4_ERR_TBIT:
+		case T4_ERR_MO:
+		case T4_ERR_MSN_RANGE:
+		case T4_ERR_IRD_OVERFLOW:
+		case T4_ERR_OPCODE:
+		case T4_ERR_INTERNAL_ERR:
+			wc->status = IBV_WC_FATAL_ERR;
+			break;
+		case T4_ERR_SWFLUSH:
+			wc->status = IBV_WC_WR_FLUSH_ERR;
+			break;
+		default:
+			PDBG("Unexpected cqe_status 0x%x for QPID=0x%0x\n",
+			     CQE_STATUS(&cqe), CQE_QPID(&cqe));
+			ret = -EINVAL;
+		}
+	}
+	if (wc->status && wc->status != IBV_WC_WR_FLUSH_ERR)
+		syslog(LOG_NOTICE, "cxgb4 app err cqid %u qpid %u "
+			"type %u opcode %u status 0x%x\n",
+			chp->cq.cqid, CQE_QPID(&cqe), CQE_TYPE(&cqe),
+			CQE_OPCODE(&cqe), CQE_STATUS(&cqe));
+out:
+	if (wq)
+		pthread_spin_unlock(&qhp->lock);
+	return ret;
+}
+
+int c4iw_poll_cq(struct ibv_cq *ibcq, int num_entries, struct ibv_wc *wc)
+{
+	struct c4iw_cq *chp;
+	int npolled;
+	int err = 0;
+
+	chp = to_c4iw_cq(ibcq);
+
+	if (t4_cq_in_error(&chp->cq)) {
+		t4_reset_cq_in_error(&chp->cq);
+		c4iw_flush_qps(chp->rhp);
+	}
+
+	if (!num_entries)
+		return t4_cq_notempty(&chp->cq);
+
+	pthread_spin_lock(&chp->lock);
+	for (npolled = 0; npolled < num_entries; ++npolled) {
+		do {
+			err = c4iw_poll_cq_one(chp, wc + npolled);
+		} while (err == -EAGAIN);
+		if (err)
+			break;
+	}
+	pthread_spin_unlock(&chp->lock);
+	return !err || err == -ENODATA ? npolled : err;
+}
+
+int c4iw_arm_cq(struct ibv_cq *ibcq, int solicited)
+{
+	struct c4iw_cq *chp;
+	int ret;
+
+	INC_STAT(arm);
+	chp = to_c4iw_cq(ibcq);
+	pthread_spin_lock(&chp->lock);
+	ret = t4_arm_cq(&chp->cq, solicited);
+	pthread_spin_unlock(&chp->lock);
+	return ret;
+}
diff --git a/contrib/ofed/libcxgb4/src/cxgb4-abi.h b/contrib/ofed/libcxgb4/src/cxgb4-abi.h
new file mode 100644
index 0000000..0b9f4d9
--- /dev/null
+++ b/contrib/ofed/libcxgb4/src/cxgb4-abi.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2006-2014 Chelsio, Inc. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef IWCH_ABI_H
+#define IWCH_ABI_H
+
+#include <infiniband/kern-abi.h>
+
+struct c4iw_alloc_ucontext_resp {
+	struct ibv_get_context_resp ibv_resp;
+	__u64 status_page_key;
+	__u32 status_page_size;
+	__u32 reserved;
+};
+
+struct c4iw_alloc_pd_resp {
+	struct ibv_alloc_pd_resp ibv_resp;
+	uint32_t pdid;
+};
+
+struct c4iw_create_cq_resp {
+	struct ibv_create_cq_resp ibv_resp;
+	__u64 key;
+	__u64 gts_key;
+	__u64 memsize;
+	__u32 cqid;
+	__u32 size;
+	__u32 qid_mask;
+	__u32 reserved;
+};
+
+enum {
+	C4IW_QPF_ONCHIP = (1<<0),
+};
+
+struct c4iw_create_qp_resp_v0 {
+	struct ibv_create_qp_resp ibv_resp;
+	__u64 sq_key;
+	__u64 rq_key;
+	__u64 sq_db_gts_key;
+	__u64 rq_db_gts_key;
+	__u64 sq_memsize;
+	__u64 rq_memsize;
+	__u32 sqid;
+	__u32 rqid;
+	__u32 sq_size;
+	__u32 rq_size;
+	__u32 qid_mask;
+};
+
+struct c4iw_create_qp_resp {
+	struct ibv_create_qp_resp ibv_resp;
+	__u64 ma_sync_key;
+	__u64 sq_key;
+	__u64 rq_key;
+	__u64 sq_db_gts_key;
+	__u64 rq_db_gts_key;
+	__u64 sq_memsize;
+	__u64 rq_memsize;
+	__u32 sqid;
+	__u32 rqid;
+	__u32 sq_size;
+	__u32 rq_size;
+	__u32 qid_mask;
+	__u32 flags;
+};
+#endif				/* IWCH_ABI_H */
diff --git a/contrib/ofed/libcxgb4/src/cxgb4.map b/contrib/ofed/libcxgb4/src/cxgb4.map
new file mode 100644
index 0000000..59a8bae
--- /dev/null
+++ b/contrib/ofed/libcxgb4/src/cxgb4.map
@@ -0,0 +1,6 @@
+{
+	global:
+		ibv_driver_init;
+		openib_driver_init;
+	local: *;
+};
diff --git a/contrib/ofed/libcxgb4/src/dev.c b/contrib/ofed/libcxgb4/src/dev.c
new file mode 100644
index 0000000..322fa0c
--- /dev/null
+++ b/contrib/ofed/libcxgb4/src/dev.c
@@ -0,0 +1,558 @@
+/*
+ * Copyright (c) 2006-2014 Chelsio, Inc. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#if HAVE_CONFIG_H
+#  include <config.h>
+#endif				/* HAVE_CONFIG_H */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <errno.h>
+#include <sys/mman.h>
+#include <pthread.h>
+#include <string.h>
+#include <signal.h>
+
+#include "libcxgb4.h"
+#include "cxgb4-abi.h"
+
+#define PCI_VENDOR_ID_CHELSIO		0x1425
+
+/*
+ * Macros needed to support the PCI Device ID Table ...
+ */
+#define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
+	struct { \
+		unsigned vendor; \
+		unsigned device; \
+		unsigned chip_version; \
+	} hca_table[] = {
+
+#define CH_PCI_DEVICE_ID_FUNCTION \
+		0x4
+
+#define CH_PCI_ID_TABLE_ENTRY(__DeviceID) \
+		{ \
+			.vendor = PCI_VENDOR_ID_CHELSIO, \
+			.device = (__DeviceID), \
+			.chip_version = CHELSIO_PCI_ID_CHIP_VERSION(__DeviceID), \
+		}
+
+#define CH_PCI_DEVICE_ID_TABLE_DEFINE_END \
+	}
+
+#include "t4_chip_type.h"
+#include "t4_pci_id_tbl.h"
+
+unsigned long c4iw_page_size;
+unsigned long c4iw_page_shift;
+unsigned long c4iw_page_mask;
+int ma_wr;
+int t5_en_wc = 1;
+
+SLIST_HEAD(devices_struct, c4iw_dev) devices;
+
+static struct ibv_context_ops c4iw_ctx_ops = {
+	.query_device = c4iw_query_device,
+	.query_port = c4iw_query_port,
+	.alloc_pd = c4iw_alloc_pd,
+	.dealloc_pd = c4iw_free_pd,
+	.reg_mr = c4iw_reg_mr,
+	.dereg_mr = c4iw_dereg_mr,
+	.create_cq = c4iw_create_cq,
+	.resize_cq = c4iw_resize_cq,
+	.destroy_cq = c4iw_destroy_cq,
+	.create_srq = c4iw_create_srq,
+	.modify_srq = c4iw_modify_srq,
+	.destroy_srq = c4iw_destroy_srq,
+	.create_qp = c4iw_create_qp,
+	.modify_qp = c4iw_modify_qp,
+	.destroy_qp = c4iw_destroy_qp,
+	.query_qp = c4iw_query_qp,
+	.create_ah = c4iw_create_ah,
+	.destroy_ah = c4iw_destroy_ah,
+	.attach_mcast = c4iw_attach_mcast,
+	.detach_mcast = c4iw_detach_mcast,
+	.post_srq_recv = c4iw_post_srq_recv,
+	.req_notify_cq = c4iw_arm_cq,
+};
+
+static struct ibv_context *c4iw_alloc_context(struct ibv_device *ibdev,
+					      int cmd_fd)
+{
+	struct c4iw_context *context;
+	struct ibv_get_context cmd;
+	struct c4iw_alloc_ucontext_resp resp;
+	struct c4iw_dev *rhp = to_c4iw_dev(ibdev);
+	struct ibv_query_device qcmd;
+	uint64_t raw_fw_ver;
+	struct ibv_device_attr attr;
+
+	context = malloc(sizeof *context);
+	if (!context)
+		return NULL;
+
+	memset(context, 0, sizeof *context);
+	context->ibv_ctx.cmd_fd = cmd_fd;
+
+	resp.status_page_size = 0;
+	resp.reserved = 0;
+	if (ibv_cmd_get_context(&context->ibv_ctx, &cmd, sizeof cmd,
+				&resp.ibv_resp, sizeof resp))
+		goto err_free;
+
+	if (resp.reserved)
+		PDBG("%s c4iw_alloc_ucontext_resp reserved field modified by kernel\n",
+		     __FUNCTION__);
+
+	context->status_page_size = resp.status_page_size;
+	if (resp.status_page_size) {
+		context->status_page = mmap(NULL, resp.status_page_size,
+					    PROT_READ, MAP_SHARED, cmd_fd,
+					    resp.status_page_key);
+		if (context->status_page == MAP_FAILED)
+			goto err_free;
+	} 
+
+	context->ibv_ctx.device = ibdev;
+	context->ibv_ctx.ops = c4iw_ctx_ops;
+
+	switch (rhp->chip_version) {
+	case CHELSIO_T5:
+		PDBG("%s T5/T4 device\n", __FUNCTION__);
+	case CHELSIO_T4:
+		PDBG("%s T4 device\n", __FUNCTION__);
+		context->ibv_ctx.ops.async_event = c4iw_async_event;
+		context->ibv_ctx.ops.post_send = c4iw_post_send;
+		context->ibv_ctx.ops.post_recv = c4iw_post_receive;
+		context->ibv_ctx.ops.poll_cq = c4iw_poll_cq;
+		context->ibv_ctx.ops.req_notify_cq = c4iw_arm_cq;
+		break;
+	default:
+		PDBG("%s unknown hca type %d\n", __FUNCTION__,
+		     rhp->chip_version);
+		goto err_unmap;
+		break;
+	}
+
+	if (!rhp->mmid2ptr) {
+		int ret;
+
+		ret = ibv_cmd_query_device(&context->ibv_ctx, &attr, &raw_fw_ver, &qcmd,
+					   sizeof qcmd);
+		if (ret)
+			goto err_unmap;
+		rhp->max_mr = attr.max_mr;
+		rhp->mmid2ptr = calloc(attr.max_mr, sizeof(void *));
+		if (!rhp->mmid2ptr) {
+			goto err_unmap;
+		}
+		rhp->max_qp = T4_QID_BASE + attr.max_cq;
+		rhp->qpid2ptr = calloc(T4_QID_BASE + attr.max_cq, sizeof(void *));
+		if (!rhp->qpid2ptr) {
+			goto err_unmap;
+		}
+		rhp->max_cq = T4_QID_BASE + attr.max_cq;
+		rhp->cqid2ptr = calloc(T4_QID_BASE + attr.max_cq, sizeof(void *));
+		if (!rhp->cqid2ptr)
+			goto err_unmap;
+	}
+
+	return &context->ibv_ctx;
+
+err_unmap:
+	munmap(context->status_page, context->status_page_size);
+err_free:
+	if (rhp->cqid2ptr)
+		free(rhp->cqid2ptr);
+	if (rhp->qpid2ptr)
+		free(rhp->cqid2ptr);
+	if (rhp->mmid2ptr)
+		free(rhp->cqid2ptr);
+	free(context);
+	return NULL;
+}
+
+static void c4iw_free_context(struct ibv_context *ibctx)
+{
+	struct c4iw_context *context = to_c4iw_context(ibctx);
+
+	if (context->status_page_size)
+		munmap(context->status_page, context->status_page_size);
+	free(context);
+}
+
+static struct ibv_device_ops c4iw_dev_ops = {
+	.alloc_context = c4iw_alloc_context,
+	.free_context = c4iw_free_context
+};
+
+#ifdef STALL_DETECTION
+
+int stall_to;
+
+static void dump_cq(struct c4iw_cq *chp)
+{
+	int i;
+
+	fprintf(stderr,
+ 		"CQ: %p id %u queue %p cidx 0x%08x sw_queue %p sw_cidx %d sw_pidx %d sw_in_use %d depth %u error %u gen %d "
+		"cidx_inc %d bits_type_ts %016" PRIx64 " notempty %d\n", chp,
+                chp->cq.cqid, chp->cq.queue, chp->cq.cidx,
+	 	chp->cq.sw_queue, chp->cq.sw_cidx, chp->cq.sw_pidx, chp->cq.sw_in_use,
+                chp->cq.size, chp->cq.error, chp->cq.gen, chp->cq.cidx_inc, be64_to_cpu(chp->cq.bits_type_ts),
+		t4_cq_notempty(&chp->cq) || (chp->iq ? t4_iq_notempty(chp->iq) : 0));
+
+	for (i=0; i < chp->cq.size; i++) {
+		u64 *p = (u64 *)(chp->cq.queue + i);
+
+		fprintf(stderr, "%02x: %016" PRIx64 " %016" PRIx64, i, be64_to_cpu(p[0]), be64_to_cpu(p[1]));
+		if (i == chp->cq.cidx)
+			fprintf(stderr, " <-- cidx\n");
+		else
+			fprintf(stderr, "\n");
+		p+= 2;
+		fprintf(stderr, "%02x: %016" PRIx64 " %016" PRIx64 "\n", i, be64_to_cpu(p[0]), be64_to_cpu(p[1]));
+		p+= 2;
+		fprintf(stderr, "%02x: %016" PRIx64 " %016" PRIx64 "\n", i, be64_to_cpu(p[0]), be64_to_cpu(p[1]));
+		p+= 2;
+		fprintf(stderr, "%02x: %016" PRIx64 " %016" PRIx64 "\n", i, be64_to_cpu(p[0]), be64_to_cpu(p[1]));
+		p+= 2;
+	}
+}
+
+static void dump_qp(struct c4iw_qp *qhp)
+{
+	int i;
+	int j;
+	struct t4_swsqe *swsqe;
+	struct t4_swrqe *swrqe;
+	u16 cidx, pidx;
+	u64 *p;
+
+	fprintf(stderr,
+		"QP: %p id %u error %d flushed %d qid_mask 0x%x\n"
+		"    SQ: id %u queue %p sw_queue %p cidx %u pidx %u in_use %u wq_pidx %u depth %u flags 0x%x flush_cidx %d\n"
+		"    RQ: id %u queue %p sw_queue %p cidx %u pidx %u in_use %u depth %u\n",
+		qhp,
+		qhp->wq.sq.qid,
+		qhp->wq.error,
+		qhp->wq.flushed,
+		qhp->wq.qid_mask,
+		qhp->wq.sq.qid,
+		qhp->wq.sq.queue,
+		qhp->wq.sq.sw_sq,
+		qhp->wq.sq.cidx,
+		qhp->wq.sq.pidx,
+		qhp->wq.sq.in_use,
+		qhp->wq.sq.wq_pidx,
+		qhp->wq.sq.size,
+		qhp->wq.sq.flags,
+		qhp->wq.sq.flush_cidx,
+		qhp->wq.rq.qid,
+		qhp->wq.rq.queue,
+		qhp->wq.rq.sw_rq,
+		qhp->wq.rq.cidx,
+		qhp->wq.rq.pidx,
+		qhp->wq.rq.in_use,
+		qhp->wq.rq.size);
+	cidx = qhp->wq.sq.cidx;
+	pidx = qhp->wq.sq.pidx;
+	if (cidx != pidx)
+		fprintf(stderr, "SQ: \n");
+	while (cidx != pidx) {
+		swsqe = &qhp->wq.sq.sw_sq[cidx];
+		fprintf(stderr, "%04u: wr_id %016" PRIx64
+			" sq_wptr %08x read_len %u opcode 0x%x "
+			"complete %u signaled %u cqe %016" PRIx64 " %016" PRIx64 " %016" PRIx64 " %016" PRIx64 "\n",
+			cidx,
+			swsqe->wr_id,
+			swsqe->idx,
+			swsqe->read_len,
+			swsqe->opcode,
+			swsqe->complete,
+			swsqe->signaled,
+			cpu_to_be64(swsqe->cqe.u.flits[0]),
+			cpu_to_be64(swsqe->cqe.u.flits[1]),
+			cpu_to_be64((u64)swsqe->cqe.reserved),
+			cpu_to_be64(swsqe->cqe.bits_type_ts));
+		if (++cidx == qhp->wq.sq.size)
+			cidx = 0;
+	}
+
+	fprintf(stderr, "SQ WQ: \n");
+	p = (u64 *)qhp->wq.sq.queue;
+	for (i=0; i < qhp->wq.sq.size * T4_SQ_NUM_SLOTS; i++) {
+		for (j=0; j < T4_EQ_ENTRY_SIZE / 16; j++) {
+			fprintf(stderr, "%04u %016" PRIx64 " %016" PRIx64 " ",
+				i, ntohll(p[0]), ntohll(p[1]));
+			if (j == 0 && i == qhp->wq.sq.wq_pidx)
+				fprintf(stderr, " <-- pidx");
+			fprintf(stderr, "\n");
+			p += 2;
+		}
+	}
+	cidx = qhp->wq.rq.cidx;
+	pidx = qhp->wq.rq.pidx;
+	if (cidx != pidx)
+		fprintf(stderr, "RQ: \n");
+	while (cidx != pidx) {
+		swrqe = &qhp->wq.rq.sw_rq[cidx];
+		fprintf(stderr, "%04u: wr_id %016" PRIx64 "\n",
+			cidx,
+			swrqe->wr_id );
+		if (++cidx == qhp->wq.rq.size)
+			cidx = 0;
+	}
+
+	fprintf(stderr, "RQ WQ: \n");
+	p = (u64 *)qhp->wq.rq.queue;
+	for (i=0; i < qhp->wq.rq.size * T4_RQ_NUM_SLOTS; i++) {
+		for (j=0; j < T4_EQ_ENTRY_SIZE / 16; j++) {
+			fprintf(stderr, "%04u %016" PRIx64 " %016" PRIx64 " ",
+				i, ntohll(p[0]), ntohll(p[1]));
+			if (j == 0 && i == qhp->wq.rq.pidx)
+				fprintf(stderr, " <-- pidx");
+			if (j == 0 && i == qhp->wq.rq.cidx)
+				fprintf(stderr, " <-- cidx");
+			fprintf(stderr, "\n");
+			p+=2;
+		}
+	}
+}
+
+void dump_state()
+{
+	struct c4iw_dev *dev;
+	int i;
+
+	fprintf(stderr, "STALL DETECTED:\n");
+	SLIST_FOREACH(dev, &devices, list) {
+		//pthread_spin_lock(&dev->lock);
+		fprintf(stderr, "Device %s\n", dev->ibv_dev.name);
+		for (i=0; i < dev->max_cq; i++) {
+			if (dev->cqid2ptr[i]) {
+				struct c4iw_cq *chp = dev->cqid2ptr[i];
+				//pthread_spin_lock(&chp->lock);
+				dump_cq(chp);
+				//pthread_spin_unlock(&chp->lock);
+			}
+		}
+		for (i=0; i < dev->max_qp; i++) {
+			if (dev->qpid2ptr[i]) {
+				struct c4iw_qp *qhp = dev->qpid2ptr[i];
+				//pthread_spin_lock(&qhp->lock);
+				dump_qp(qhp);
+				//pthread_spin_unlock(&qhp->lock);
+			}
+		}
+		//pthread_spin_unlock(&dev->lock);
+	}
+	fprintf(stderr, "DUMP COMPLETE:\n");
+	fflush(stderr);
+}
+#endif /* end of STALL_DETECTION */
+
+/*
+ * c4iw_abi_version is used to store ABI for iw_cxgb4 so the user mode library
+ * can know if the driver supports the kernel mode db ringing. 
+ */
+int c4iw_abi_version = 1;
+
+static struct ibv_device *cxgb4_driver_init(const char *uverbs_sys_path,
+					    int abi_version)
+{
+	char devstr[IBV_SYSFS_PATH_MAX], ibdev[16], value[128], *cp;
+	char t5nexstr[IBV_SYSFS_PATH_MAX];
+	struct c4iw_dev *dev;
+	unsigned vendor, device, fw_maj, fw_min;
+	int i;
+	char devnum=0;
+        char ib_param[16];
+
+#ifndef __linux__
+	if (ibv_read_sysfs_file(uverbs_sys_path, "ibdev",
+				ibdev, sizeof ibdev) < 0)
+		return NULL;
+	/* 
+	 * Extract the non-numeric part of ibdev
+	 * say "t5nex0" -> devname=="t5nex", devnum=0
+	 */
+	if (strstr(ibdev,"t5nex")) {
+		devnum = atoi(ibdev+strlen("t5nex"));
+		sprintf(t5nexstr, "/dev/t5nex/%d", devnum);
+	} else
+		return NULL;
+
+	if (ibv_read_sysfs_file(t5nexstr, "\%pnpinfo",
+				value, sizeof value) < 0)
+		return NULL;
+	else {
+		if (strstr(value,"vendor=")) {
+			strncpy(ib_param, strstr(value,"vendor=")+strlen("vendor="),6);
+			sscanf(ib_param,"%i",&vendor);
+		}
+
+		if (strstr(value,"device=")) {
+			strncpy(ib_param, strstr(value,"device=")+strlen("device="),6);
+			sscanf(ib_param,"%i",&device);
+		}
+	}
+#else
+	if (ibv_read_sysfs_file(uverbs_sys_path, "device/vendor",
+				value, sizeof value) < 0)
+		return NULL;
+	sscanf(value, "%i", &vendor);
+
+	if (ibv_read_sysfs_file(uverbs_sys_path, "device/device",
+				value, sizeof value) < 0)
+		return NULL;
+	sscanf(value, "%i", &device);
+#endif
+
+	for (i = 0; i < sizeof hca_table / sizeof hca_table[0]; ++i)
+		if (vendor == hca_table[i].vendor &&
+		    device == hca_table[i].device)
+			goto found;
+
+	return NULL;
+
+found:
+	c4iw_abi_version = abi_version;	
+
+
+#ifndef __linux__
+	if (ibv_read_sysfs_file(t5nexstr, "firmware_version",
+				value, sizeof value) < 0)
+		return NULL;
+#else
+	/*
+	 * Verify that the firmware major number matches.  Major number
+	 * mismatches are fatal.  Minor number mismatches are tolerated.
+	 */
+	if (ibv_read_sysfs_file(uverbs_sys_path, "ibdev",
+				ibdev, sizeof ibdev) < 0)
+		return NULL;
+
+	memset(devstr, 0, sizeof devstr);
+	snprintf(devstr, sizeof devstr, "%s/class/infiniband/%s",
+		 ibv_get_sysfs_path(), ibdev);
+	if (ibv_read_sysfs_file(devstr, "fw_ver", value, sizeof value) < 0)
+		return NULL;
+#endif
+
+	cp = strtok(value+1, ".");
+	sscanf(cp, "%i", &fw_maj);
+	cp = strtok(NULL, ".");
+	sscanf(cp, "%i", &fw_min);
+
+	if (fw_maj < FW_MAJ) {
+		fprintf(stderr, "libcxgb4: Fatal firmware version mismatch.  "
+			"Firmware major number is %u and libcxgb4 needs %u.\n",
+			fw_maj, FW_MAJ);
+		fflush(stderr);
+		return NULL;
+	}
+
+	DBGLOG("libcxgb4");
+
+	if (fw_min < FW_MIN) {
+		PDBG("libcxgb4: non-fatal firmware version mismatch.  "
+			"Firmware minor number is %u and libcxgb4 needs %u.\n",
+			fw_maj, FW_MAJ);
+		fflush(stderr);
+	}
+
+	PDBG("%s found vendor %d device %d type %d\n",
+	     __FUNCTION__, vendor, device, hca_table[i].chip_version);
+
+	dev = calloc(1, sizeof *dev);
+	if (!dev) {
+		return NULL;
+	}
+
+	pthread_spin_init(&dev->lock, PTHREAD_PROCESS_PRIVATE);
+	dev->ibv_dev.ops = c4iw_dev_ops;
+	dev->chip_version = hca_table[i].chip_version;
+	dev->abi_version = abi_version;
+
+	PDBG("%s device claimed\n", __FUNCTION__);
+	SLIST_INSERT_HEAD(&devices, dev, list);
+#ifdef STALL_DETECTION
+{
+	char *c = getenv("CXGB4_STALL_TIMEOUT");
+	if (c) {
+		stall_to = strtol(c, NULL, 0);
+		if (errno || stall_to < 0)
+			stall_to = 0;
+	}
+}
+#endif
+{
+	char *c = getenv("CXGB4_MA_WR");
+	if (c) {
+		ma_wr = strtol(c, NULL, 0);
+		if (ma_wr != 1)
+			ma_wr = 0;
+	}
+}
+{
+	char *c = getenv("T5_ENABLE_WC");
+	if (c) {
+		t5_en_wc = strtol(c, NULL, 0);
+		if (t5_en_wc != 1)
+			t5_en_wc = 0;
+	}
+}
+
+	return &dev->ibv_dev;
+}
+
+static __attribute__((constructor)) void cxgb4_register_driver(void)
+{
+	c4iw_page_size = sysconf(_SC_PAGESIZE);
+	c4iw_page_shift = long_log2(c4iw_page_size);
+	c4iw_page_mask = ~(c4iw_page_size - 1);
+	ibv_register_driver("cxgb4", cxgb4_driver_init);
+}
+
+#ifdef STATS
+void __attribute__ ((destructor)) cs_fini(void);
+void  __attribute__ ((destructor)) cs_fini(void)
+{
+	syslog(LOG_NOTICE, "cxgb4 stats - sends %lu recv %lu read %lu "
+	       "write %lu arm %lu cqe %lu mr %lu qp %lu cq %lu\n",
+	       c4iw_stats.send, c4iw_stats.recv, c4iw_stats.read,
+	       c4iw_stats.write, c4iw_stats.arm, c4iw_stats.cqe,
+	       c4iw_stats.mr, c4iw_stats.qp, c4iw_stats.cq);
+}
+#endif
diff --git a/contrib/ofed/libcxgb4/src/libcxgb4.h b/contrib/ofed/libcxgb4/src/libcxgb4.h
new file mode 100644
index 0000000..7110aa3
--- /dev/null
+++ b/contrib/ofed/libcxgb4/src/libcxgb4.h
@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) 2006-2014 Chelsio, Inc. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *	  copyright notice, this list of conditions and the following
+ *	  disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *	  copyright notice, this list of conditions and the following
+ *	  disclaimer in the documentation and/or other materials
+ *	  provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef IWCH_H
+#define IWCH_H
+
+#include <pthread.h>
+#include <inttypes.h>
+#include <stddef.h>
+#include <string.h>
+#include <syslog.h>
+#include <sys/errno.h>
+#include <sys/time.h>
+#include <infiniband/driver.h>
+#include <infiniband/arch.h>
+#include "queue.h"
+#include "t4.h"
+
+extern unsigned long c4iw_page_size;
+extern unsigned long c4iw_page_shift;
+extern unsigned long c4iw_page_mask;
+
+struct c4iw_mr;
+
+struct c4iw_dev {
+	struct ibv_device ibv_dev;
+	unsigned chip_version;
+	int max_mr;
+	struct c4iw_mr **mmid2ptr;
+	int max_qp;
+	struct c4iw_qp **qpid2ptr;
+	int max_cq;
+	struct c4iw_cq **cqid2ptr;
+	pthread_spinlock_t lock;
+	SLIST_ENTRY(c4iw_dev) list;
+	int abi_version;
+};
+
+static inline int dev_is_t5(struct c4iw_dev *dev)
+{
+	return dev->chip_version == CHELSIO_T5;
+}
+
+struct c4iw_context {
+	struct ibv_context ibv_ctx;
+	struct t4_dev_status_page *status_page;
+	int status_page_size;
+};
+
+struct c4iw_pd {
+	struct ibv_pd ibv_pd;
+};
+
+struct c4iw_mr {
+	struct ibv_mr ibv_mr;
+	uint64_t va_fbo;
+	uint32_t len;
+};
+
+static inline u32 c4iw_mmid(u32 stag)
+{
+	return (stag >> 8);
+}
+
+struct c4iw_cq {
+	struct ibv_cq ibv_cq;
+	struct c4iw_dev *rhp;
+	struct t4_cq cq;
+	pthread_spinlock_t lock;
+#ifdef STALL_DETECTION
+	struct timeval time;
+	int dumped;
+#endif
+};
+
+struct c4iw_qp {
+	struct ibv_qp ibv_qp;
+	struct c4iw_dev *rhp;
+	struct t4_wq wq;
+	pthread_spinlock_t lock;
+	int sq_sig_all;
+};
+
+#define to_c4iw_xxx(xxx, type)						\
+	((struct c4iw_##type *)						\
+	 ((void *) ib##xxx - offsetof(struct c4iw_##type, ibv_##xxx)))
+
+static inline struct c4iw_dev *to_c4iw_dev(struct ibv_device *ibdev)
+{
+	return to_c4iw_xxx(dev, dev);
+}
+
+static inline struct c4iw_context *to_c4iw_context(struct ibv_context *ibctx)
+{
+	return to_c4iw_xxx(ctx, context);
+}
+
+static inline struct c4iw_pd *to_c4iw_pd(struct ibv_pd *ibpd)
+{
+	return to_c4iw_xxx(pd, pd);
+}
+
+static inline struct c4iw_cq *to_c4iw_cq(struct ibv_cq *ibcq)
+{
+	return to_c4iw_xxx(cq, cq);
+}
+
+static inline struct c4iw_qp *to_c4iw_qp(struct ibv_qp *ibqp)
+{
+	return to_c4iw_xxx(qp, qp);
+}
+
+static inline struct c4iw_mr *to_c4iw_mr(struct ibv_mr *ibmr)
+{
+	return to_c4iw_xxx(mr, mr);
+}
+
+static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qid)
+{
+	return rhp->qpid2ptr[qid];
+}
+
+static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 qid)
+{
+	return rhp->cqid2ptr[qid];
+}
+
+static inline unsigned long_log2(unsigned long x)
+{
+	unsigned r = 0;
+	for (x >>= 1; x > 0; x >>= 1)
+		r++;
+	return r;
+}
+
+int c4iw_query_device(struct ibv_context *context,
+			     struct ibv_device_attr *attr);
+int c4iw_query_port(struct ibv_context *context, uint8_t port,
+			   struct ibv_port_attr *attr);
+
+struct ibv_pd *c4iw_alloc_pd(struct ibv_context *context);
+int c4iw_free_pd(struct ibv_pd *pd);
+
+struct ibv_mr *c4iw_reg_mr(struct ibv_pd *pd, void *addr,
+				  size_t length, int access);
+int c4iw_dereg_mr(struct ibv_mr *mr);
+
+struct ibv_cq *c4iw_create_cq(struct ibv_context *context, int cqe,
+			      struct ibv_comp_channel *channel,
+			      int comp_vector);
+int c4iw_resize_cq(struct ibv_cq *cq, int cqe);
+int c4iw_destroy_cq(struct ibv_cq *cq);
+int c4iw_poll_cq(struct ibv_cq *cq, int ne, struct ibv_wc *wc);
+int c4iw_arm_cq(struct ibv_cq *cq, int solicited);
+void c4iw_cq_event(struct ibv_cq *cq);
+void c4iw_init_cq_buf(struct c4iw_cq *cq, int nent);
+
+struct ibv_srq *c4iw_create_srq(struct ibv_pd *pd,
+				       struct ibv_srq_init_attr *attr);
+int c4iw_modify_srq(struct ibv_srq *srq,
+			   struct ibv_srq_attr *attr,
+			   int mask);
+int c4iw_destroy_srq(struct ibv_srq *srq);
+int c4iw_post_srq_recv(struct ibv_srq *ibsrq,
+			      struct ibv_recv_wr *wr,
+			      struct ibv_recv_wr **bad_wr);
+
+struct ibv_qp *c4iw_create_qp(struct ibv_pd *pd,
+				     struct ibv_qp_init_attr *attr);
+int c4iw_modify_qp(struct ibv_qp *qp, struct ibv_qp_attr *attr,
+			  int attr_mask);
+int c4iw_destroy_qp(struct ibv_qp *qp);
+int c4iw_query_qp(struct ibv_qp *qp,
+			 struct ibv_qp_attr *attr,
+			 int attr_mask,
+			 struct ibv_qp_init_attr *init_attr);
+void c4iw_flush_qp(struct c4iw_qp *qhp);
+void c4iw_flush_qps(struct c4iw_dev *dev);
+int c4iw_post_send(struct ibv_qp *ibqp, struct ibv_send_wr *wr,
+			  struct ibv_send_wr **bad_wr);
+int c4iw_post_receive(struct ibv_qp *ibqp, struct ibv_recv_wr *wr,
+			  struct ibv_recv_wr **bad_wr);
+struct ibv_ah *c4iw_create_ah(struct ibv_pd *pd,
+			     struct ibv_ah_attr *ah_attr);
+int c4iw_destroy_ah(struct ibv_ah *ah);
+int c4iw_attach_mcast(struct ibv_qp *qp, const union ibv_gid *gid,
+			     uint16_t lid);
+int c4iw_detach_mcast(struct ibv_qp *qp, const union ibv_gid *gid,
+			     uint16_t lid);
+void c4iw_async_event(struct ibv_async_event *event);
+void c4iw_flush_hw_cq(struct c4iw_cq *chp);
+int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
+void c4iw_flush_sq(struct c4iw_qp *qhp);
+void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
+
+#define FW_MAJ 0
+#define FW_MIN 0
+
+static inline unsigned long align(unsigned long val, unsigned long align)
+{
+	return (val + align - 1) & ~(align - 1);
+}
+
+#ifdef STATS
+
+#define INC_STAT(a) { c4iw_stats.a++; }
+
+struct c4iw_stats {
+	unsigned long send;
+	unsigned long recv;
+	unsigned long read;
+	unsigned long write;
+	unsigned long arm;
+	unsigned long cqe;
+	unsigned long mr;
+	unsigned long qp;
+	unsigned long cq;
+};
+extern struct c4iw_stats c4iw_stats;
+#else
+#define INC_STAT(a)
+#endif
+
+#ifdef STALL_DETECTION
+void dump_state();
+extern int stall_to;
+#endif
+
+#endif				/* IWCH_H */
diff --git a/contrib/ofed/libcxgb4/src/qp.c b/contrib/ofed/libcxgb4/src/qp.c
new file mode 100644
index 0000000..9a86291
--- /dev/null
+++ b/contrib/ofed/libcxgb4/src/qp.c
@@ -0,0 +1,542 @@
+/*
+ * Copyright (c) 2006-2014 Chelsio, Inc. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#if HAVE_CONFIG_H
+#  include <config.h>
+#endif				/* HAVE_CONFIG_H */
+
+#include <assert.h>
+#include <stdlib.h>
+#include <pthread.h>
+#include <string.h>
+#include <stdio.h>
+#include <netinet/in.h>
+#include "libcxgb4.h"
+
+#ifdef STATS
+struct c4iw_stats c4iw_stats;
+#endif
+
+static void copy_wr_to_sq(struct t4_wq *wq, union t4_wr *wqe, u8 len16)
+{
+	u64 *src, *dst;
+
+	src = (u64 *)wqe;
+	dst = (u64 *)((u8 *)wq->sq.queue + wq->sq.wq_pidx * T4_EQ_ENTRY_SIZE);
+	if (t4_sq_onchip(wq)) {
+		len16 = align(len16, 4);
+		wc_wmb();
+	}
+	while (len16) {
+		*dst++ = *src++;
+		if (dst == (u64 *)&wq->sq.queue[wq->sq.size])
+			dst = (u64 *)wq->sq.queue;
+		*dst++ = *src++;
+		if (dst == (u64 *)&wq->sq.queue[wq->sq.size])
+			dst = (u64 *)wq->sq.queue;
+		len16--;
+	}
+}
+
+static void copy_wr_to_rq(struct t4_wq *wq, union t4_recv_wr *wqe, u8 len16)
+{
+	u64 *src, *dst;
+
+	src = (u64 *)wqe;
+	dst = (u64 *)((u8 *)wq->rq.queue + wq->rq.wq_pidx * T4_EQ_ENTRY_SIZE);
+	while (len16) {
+		*dst++ = *src++;
+		if (dst >= (u64 *)&wq->rq.queue[wq->rq.size])
+			dst = (u64 *)wq->rq.queue;
+		*dst++ = *src++;
+		if (dst >= (u64 *)&wq->rq.queue[wq->rq.size])
+			dst = (u64 *)wq->rq.queue;
+		len16--;
+	}
+}
+
+static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
+		      struct ibv_send_wr *wr, int max, u32 *plenp)
+{
+	u8 *dstp, *srcp;
+	u32 plen = 0;
+	int i;
+	int len;
+
+	dstp = (u8 *)immdp->data;
+	for (i = 0; i < wr->num_sge; i++) {
+		if ((plen + wr->sg_list[i].length) > max)
+			return -EMSGSIZE;
+		srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
+		plen += wr->sg_list[i].length;
+		len = wr->sg_list[i].length;
+		memcpy(dstp, srcp, len);
+		dstp += len;
+		srcp += len;
+	}
+	len = ROUND_UP(plen + 8, 16) - (plen + 8);
+	if (len)
+		memset(dstp, 0, len);
+	immdp->op = FW_RI_DATA_IMMD;
+	immdp->r1 = 0;
+	immdp->r2 = 0;
+	immdp->immdlen = cpu_to_be32(plen);
+	*plenp = plen;
+	return 0;
+}
+
+static int build_isgl(struct fw_ri_isgl *isglp, struct ibv_sge *sg_list,
+		      int num_sge, u32 *plenp)
+{
+	int i;
+	u32 plen = 0;
+	__be64 *flitp = (__be64 *)isglp->sge;
+
+	for (i = 0; i < num_sge; i++) {
+		if ((plen + sg_list[i].length) < plen)
+			return -EMSGSIZE;
+		plen += sg_list[i].length;
+		*flitp++ = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
+				     sg_list[i].length);
+		*flitp++ = cpu_to_be64(sg_list[i].addr);
+	}
+	*flitp = 0;
+	isglp->op = FW_RI_DATA_ISGL;
+	isglp->r1 = 0;
+	isglp->nsge = cpu_to_be16(num_sge);
+	isglp->r2 = 0;
+	if (plenp)
+		*plenp = plen;
+	return 0;
+}
+
+static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
+			   struct ibv_send_wr *wr, u8 *len16)
+{
+	u32 plen;
+	int size;
+	int ret;
+
+	if (wr->num_sge > T4_MAX_SEND_SGE)
+		return -EINVAL;
+	if (wr->send_flags & IBV_SEND_SOLICITED)
+		wqe->send.sendop_pkd = cpu_to_be32(
+			V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
+	else
+		wqe->send.sendop_pkd = cpu_to_be32(
+			V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
+	wqe->send.stag_inv = 0;
+	wqe->send.r3 = 0;
+	wqe->send.r4 = 0;
+
+	plen = 0;
+	if (wr->num_sge) {
+		if (wr->send_flags & IBV_SEND_INLINE) {
+			ret = build_immd(sq, wqe->send.u.immd_src, wr,
+					 T4_MAX_SEND_INLINE, &plen);
+			if (ret)
+				return ret;
+			size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
+			       plen;
+		} else {
+			ret = build_isgl(wqe->send.u.isgl_src,
+					 wr->sg_list, wr->num_sge, &plen);
+			if (ret)
+				return ret;
+			size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
+			       wr->num_sge * sizeof (struct fw_ri_sge);
+		}
+	} else {
+		wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
+		wqe->send.u.immd_src[0].r1 = 0;
+		wqe->send.u.immd_src[0].r2 = 0;
+		wqe->send.u.immd_src[0].immdlen = 0;
+		size = sizeof wqe->send + sizeof(struct fw_ri_immd);
+		plen = 0;
+	}
+	*len16 = DIV_ROUND_UP(size, 16);
+	wqe->send.plen = cpu_to_be32(plen);
+	return 0;
+}
+
+static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
+			    struct ibv_send_wr *wr, u8 *len16)
+{
+	u32 plen;
+	int size;
+	int ret;
+
+	if (wr->num_sge > T4_MAX_SEND_SGE)
+		return -EINVAL;
+	wqe->write.r2 = 0;
+	wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
+	wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
+	if (wr->num_sge) {
+		if (wr->send_flags & IBV_SEND_INLINE) {
+			ret = build_immd(sq, wqe->write.u.immd_src, wr,
+					 T4_MAX_WRITE_INLINE, &plen);
+			if (ret)
+				return ret;
+			size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
+			       plen;
+		} else {
+			ret = build_isgl(wqe->write.u.isgl_src,
+					 wr->sg_list, wr->num_sge, &plen);
+			if (ret)
+				return ret;
+			size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
+			       wr->num_sge * sizeof (struct fw_ri_sge);
+		}
+	} else {
+		wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
+		wqe->write.u.immd_src[0].r1 = 0;
+		wqe->write.u.immd_src[0].r2 = 0;
+		wqe->write.u.immd_src[0].immdlen = 0;
+		size = sizeof wqe->write + sizeof(struct fw_ri_immd);
+		plen = 0;
+	}
+	*len16 = DIV_ROUND_UP(size, 16);
+	wqe->write.plen = cpu_to_be32(plen);
+	return 0;
+}
+
+static int build_rdma_read(union t4_wr *wqe, struct ibv_send_wr *wr, u8 *len16)
+{
+	if (wr->num_sge > 1)
+		return -EINVAL;
+	if (wr->num_sge) {
+		wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
+		wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr >>32));
+		wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
+		wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
+		wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
+		wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr >> 32));
+		wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
+	} else {
+		wqe->read.stag_src = cpu_to_be32(2);
+		wqe->read.to_src_hi = 0;
+		wqe->read.to_src_lo = 0;
+		wqe->read.stag_sink = cpu_to_be32(2);
+		wqe->read.plen = 0;
+		wqe->read.to_sink_hi = 0;
+		wqe->read.to_sink_lo = 0;
+	}
+	wqe->read.r2 = 0;
+	wqe->read.r5 = 0;
+	*len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
+	return 0;
+}
+
+static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
+			   struct ibv_recv_wr *wr, u8 *len16)
+{
+	int ret;
+
+	ret = build_isgl(&wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
+	if (ret)
+		return ret;
+	*len16 = DIV_ROUND_UP(sizeof wqe->recv +
+			      wr->num_sge * sizeof(struct fw_ri_sge), 16);
+	return 0;
+}
+
+void dump_wqe(void *arg)
+{
+	u64 *p = arg;
+	int len16;
+
+	len16 = be64_to_cpu(*p) & 0xff;
+	while (len16--) {
+		printf("%02x: %016lx ", (u8)(unsigned long)p, be64_to_cpu(*p));
+		p++;
+		printf("%016lx\n", be64_to_cpu(*p));
+		p++;
+	}
+}
+
+static void ring_kernel_db(struct c4iw_qp *qhp, u32 qid, u16 idx)
+{
+	struct ibv_modify_qp cmd;
+	struct ibv_qp_attr attr;
+	int mask;
+	int ret;
+
+	wc_wmb();
+	if (qid == qhp->wq.sq.qid) {
+		attr.sq_psn = idx;
+		mask = IBV_QP_SQ_PSN;
+	} else  {
+		attr.rq_psn = idx;
+		mask = IBV_QP_RQ_PSN;
+	}
+	ret = ibv_cmd_modify_qp(&qhp->ibv_qp, &attr, mask, &cmd, sizeof cmd);
+	assert(!ret);
+}
+
+int c4iw_post_send(struct ibv_qp *ibqp, struct ibv_send_wr *wr,
+	           struct ibv_send_wr **bad_wr)
+{
+	int err = 0;
+	u8 len16;
+	enum fw_wr_opcodes fw_opcode;
+	enum fw_ri_wr_flags fw_flags;
+	struct c4iw_qp *qhp;
+	union t4_wr *wqe, lwqe;
+	u32 num_wrs;
+	struct t4_swsqe *swsqe;
+	u16 idx = 0;
+
+	qhp = to_c4iw_qp(ibqp);
+	pthread_spin_lock(&qhp->lock);
+	if (t4_wq_in_error(&qhp->wq)) {
+		pthread_spin_unlock(&qhp->lock);
+		return -EINVAL;
+	}
+	num_wrs = t4_sq_avail(&qhp->wq);
+	if (num_wrs == 0) {
+		pthread_spin_unlock(&qhp->lock);
+		return -ENOMEM;
+	}
+	while (wr) {
+		if (num_wrs == 0) {
+			err = -ENOMEM;
+			*bad_wr = wr;
+			break;
+		}
+
+		wqe = &lwqe;
+		fw_flags = 0;
+		if (wr->send_flags & IBV_SEND_SOLICITED)
+			fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
+		if (wr->send_flags & IBV_SEND_SIGNALED || qhp->sq_sig_all)
+			fw_flags |= FW_RI_COMPLETION_FLAG;
+		swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
+		switch (wr->opcode) {
+		case IBV_WR_SEND:
+			INC_STAT(send);
+			if (wr->send_flags & IBV_SEND_FENCE)
+				fw_flags |= FW_RI_READ_FENCE_FLAG;
+			fw_opcode = FW_RI_SEND_WR;
+			swsqe->opcode = FW_RI_SEND;
+			err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
+			break;
+		case IBV_WR_RDMA_WRITE:
+			INC_STAT(write);
+			fw_opcode = FW_RI_RDMA_WRITE_WR;
+			swsqe->opcode = FW_RI_RDMA_WRITE;
+			err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
+			break;
+		case IBV_WR_RDMA_READ:
+			INC_STAT(read);
+			fw_opcode = FW_RI_RDMA_READ_WR;
+			swsqe->opcode = FW_RI_READ_REQ;
+			fw_flags = 0;
+			err = build_rdma_read(wqe, wr, &len16);
+			if (err)
+				break;
+			swsqe->read_len = wr->sg_list[0].length;
+			if (!qhp->wq.sq.oldest_read)
+				qhp->wq.sq.oldest_read = swsqe;
+			break;
+		default:
+			PDBG("%s post of type=%d TBD!\n", __func__,
+			     wr->opcode);
+			err = -EINVAL;
+		}
+		if (err) {
+			*bad_wr = wr;
+			break;
+		}
+		swsqe->idx = qhp->wq.sq.pidx;
+		swsqe->complete = 0;
+		swsqe->signaled = (wr->send_flags & IBV_SEND_SIGNALED) ||
+				  qhp->sq_sig_all;
+		swsqe->flushed = 0;
+		swsqe->wr_id = wr->wr_id;
+
+		init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
+		PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x\n",
+		     __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
+		     swsqe->opcode);
+		wr = wr->next;
+		num_wrs--;
+		copy_wr_to_sq(&qhp->wq, wqe, len16);
+		t4_sq_produce(&qhp->wq, len16);
+		idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
+	}
+	if (t4_wq_db_enabled(&qhp->wq)) {
+		t4_ring_sq_db(&qhp->wq, idx, dev_is_t5(qhp->rhp),
+			      len16, wqe);
+	} else
+		ring_kernel_db(qhp, qhp->wq.sq.qid, idx);
+	qhp->wq.sq.queue[qhp->wq.sq.size].status.host_wq_pidx = \
+			(qhp->wq.sq.wq_pidx);
+	pthread_spin_unlock(&qhp->lock);
+	return err;
+}
+
+int c4iw_post_receive(struct ibv_qp *ibqp, struct ibv_recv_wr *wr,
+			   struct ibv_recv_wr **bad_wr)
+{
+	int err = 0;
+	struct c4iw_qp *qhp;
+	union t4_recv_wr *wqe, lwqe;
+	u32 num_wrs;
+	u8 len16 = 0;
+	u16 idx = 0;
+
+	qhp = to_c4iw_qp(ibqp);
+	pthread_spin_lock(&qhp->lock);
+	if (t4_wq_in_error(&qhp->wq)) {
+		pthread_spin_unlock(&qhp->lock);
+		return -EINVAL;
+	}
+	INC_STAT(recv);
+	num_wrs = t4_rq_avail(&qhp->wq);
+	if (num_wrs == 0) {
+		pthread_spin_unlock(&qhp->lock);
+		return -ENOMEM;
+	}
+	while (wr) {
+		if (wr->num_sge > T4_MAX_RECV_SGE) {
+			err = -EINVAL;
+			*bad_wr = wr;
+			break;
+		}
+		wqe = &lwqe;
+		if (num_wrs)
+			err = build_rdma_recv(qhp, wqe, wr, &len16);
+		else
+			err = -ENOMEM;
+		if (err) {
+			*bad_wr = wr;
+			break;
+		}
+
+		qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
+
+		wqe->recv.opcode = FW_RI_RECV_WR;
+		wqe->recv.r1 = 0;
+		wqe->recv.wrid = qhp->wq.rq.pidx;
+		wqe->recv.r2[0] = 0;
+		wqe->recv.r2[1] = 0;
+		wqe->recv.r2[2] = 0;
+		wqe->recv.len16 = len16;
+		PDBG("%s cookie 0x%llx pidx %u\n", __func__,
+		     (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
+		copy_wr_to_rq(&qhp->wq, wqe, len16);
+		t4_rq_produce(&qhp->wq, len16);
+		idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
+		wr = wr->next;
+		num_wrs--;
+	}
+	if (t4_wq_db_enabled(&qhp->wq))
+		t4_ring_rq_db(&qhp->wq, idx, dev_is_t5(qhp->rhp),
+			      len16, wqe);
+	else
+		ring_kernel_db(qhp, qhp->wq.rq.qid, idx);
+	qhp->wq.rq.queue[qhp->wq.rq.size].status.host_wq_pidx = \
+			(qhp->wq.rq.wq_pidx);
+	pthread_spin_unlock(&qhp->lock);
+	return err;
+}
+
+static void update_qp_state(struct c4iw_qp *qhp)
+{
+	struct ibv_query_qp cmd;
+	struct ibv_qp_attr attr;
+	struct ibv_qp_init_attr iattr;
+	int ret;
+
+	ret = ibv_cmd_query_qp(&qhp->ibv_qp, &attr, IBV_QP_STATE, &iattr,
+			       &cmd, sizeof cmd);
+	assert(!ret);
+	if (!ret)
+		qhp->ibv_qp.state = attr.qp_state;
+}
+
+/*
+ * Assumes qhp lock is held.
+ */
+void c4iw_flush_qp(struct c4iw_qp *qhp)
+{
+	struct c4iw_cq *rchp, *schp;
+	int count;
+
+	if (qhp->wq.flushed)
+		return;
+
+	update_qp_state(qhp);
+
+	rchp = to_c4iw_cq(qhp->ibv_qp.recv_cq);
+	schp = to_c4iw_cq(qhp->ibv_qp.send_cq);
+
+	PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
+	qhp->wq.flushed = 1;
+	pthread_spin_unlock(&qhp->lock);
+
+	/* locking heirarchy: cq lock first, then qp lock. */
+	pthread_spin_lock(&rchp->lock);
+	pthread_spin_lock(&qhp->lock);
+	c4iw_flush_hw_cq(rchp);
+	c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
+	c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
+	pthread_spin_unlock(&qhp->lock);
+	pthread_spin_unlock(&rchp->lock);
+
+	/* locking heirarchy: cq lock first, then qp lock. */
+	pthread_spin_lock(&schp->lock);
+	pthread_spin_lock(&qhp->lock);
+	if (schp != rchp)
+		c4iw_flush_hw_cq(schp);
+	c4iw_flush_sq(qhp);
+	pthread_spin_unlock(&qhp->lock);
+	pthread_spin_unlock(&schp->lock);
+	pthread_spin_lock(&qhp->lock);
+}
+
+void c4iw_flush_qps(struct c4iw_dev *dev)
+{
+	int i;
+
+	pthread_spin_lock(&dev->lock);
+	for (i=0; i < dev->max_qp; i++) {
+		struct c4iw_qp *qhp = dev->qpid2ptr[i];
+		if (qhp) {
+			if (!qhp->wq.flushed && t4_wq_in_error(&qhp->wq)) {
+				pthread_spin_lock(&qhp->lock);
+				c4iw_flush_qp(qhp);
+				pthread_spin_unlock(&qhp->lock);
+			}
+		}
+	}
+	pthread_spin_unlock(&dev->lock);
+}
diff --git a/contrib/ofed/libcxgb4/src/queue.h b/contrib/ofed/libcxgb4/src/queue.h
new file mode 100644
index 0000000..c97b6f4
--- /dev/null
+++ b/contrib/ofed/libcxgb4/src/queue.h
@@ -0,0 +1,650 @@
+/*
+ * Copyright (c) 2014 Chelsio, Inc. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/*-
+ * Copyright (c) 1991, 1993
+ *	The Regents of the University of California.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 4. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)queue.h	8.5 (Berkeley) 8/20/94
+ * $FreeBSD$
+ */
+
+#ifndef _SYS_QUEUE_H_
+#define	_SYS_QUEUE_H_
+
+#include <sys/cdefs.h>
+
+/*
+ * This file defines four types of data structures: singly-linked lists,
+ * singly-linked tail queues, lists and tail queues.
+ *
+ * A singly-linked list is headed by a single forward pointer. The elements
+ * are singly linked for minimum space and pointer manipulation overhead at
+ * the expense of O(n) removal for arbitrary elements. New elements can be
+ * added to the list after an existing element or at the head of the list.
+ * Elements being removed from the head of the list should use the explicit
+ * macro for this purpose for optimum efficiency. A singly-linked list may
+ * only be traversed in the forward direction.  Singly-linked lists are ideal
+ * for applications with large datasets and few or no removals or for
+ * implementing a LIFO queue.
+ *
+ * A singly-linked tail queue is headed by a pair of pointers, one to the
+ * head of the list and the other to the tail of the list. The elements are
+ * singly linked for minimum space and pointer manipulation overhead at the
+ * expense of O(n) removal for arbitrary elements. New elements can be added
+ * to the list after an existing element, at the head of the list, or at the
+ * end of the list. Elements being removed from the head of the tail queue
+ * should use the explicit macro for this purpose for optimum efficiency.
+ * A singly-linked tail queue may only be traversed in the forward direction.
+ * Singly-linked tail queues are ideal for applications with large datasets
+ * and few or no removals or for implementing a FIFO queue.
+ *
+ * A list is headed by a single forward pointer (or an array of forward
+ * pointers for a hash table header). The elements are doubly linked
+ * so that an arbitrary element can be removed without a need to
+ * traverse the list. New elements can be added to the list before
+ * or after an existing element or at the head of the list. A list
+ * may only be traversed in the forward direction.
+ *
+ * A tail queue is headed by a pair of pointers, one to the head of the
+ * list and the other to the tail of the list. The elements are doubly
+ * linked so that an arbitrary element can be removed without a need to
+ * traverse the list. New elements can be added to the list before or
+ * after an existing element, at the head of the list, or at the end of
+ * the list. A tail queue may be traversed in either direction.
+ *
+ * For details on the use of these macros, see the queue(3) manual page.
+ *
+ *
+ *				SLIST	LIST	STAILQ	TAILQ
+ * _HEAD			+	+	+	+
+ * _HEAD_INITIALIZER		+	+	+	+
+ * _ENTRY			+	+	+	+
+ * _INIT			+	+	+	+
+ * _EMPTY			+	+	+	+
+ * _FIRST			+	+	+	+
+ * _NEXT			+	+	+	+
+ * _PREV			-	-	-	+
+ * _LAST			-	-	+	+
+ * _FOREACH			+	+	+	+
+ * _FOREACH_SAFE		+	+	+	+
+ * _FOREACH_REVERSE		-	-	-	+
+ * _FOREACH_REVERSE_SAFE	-	-	-	+
+ * _INSERT_HEAD			+	+	+	+
+ * _INSERT_BEFORE		-	+	-	+
+ * _INSERT_AFTER		+	+	+	+
+ * _INSERT_TAIL			-	-	+	+
+ * _CONCAT			-	-	+	+
+ * _REMOVE_HEAD			+	-	+	-
+ * _REMOVE			+	+	+	+
+ *
+ */
+#ifdef QUEUE_MACRO_DEBUG
+/* Store the last 2 places the queue element or head was altered */
+struct qm_trace {
+	char * lastfile;
+	int lastline;
+	char * prevfile;
+	int prevline;
+};
+
+#define	TRACEBUF	struct qm_trace trace;
+#define	TRASHIT(x)	do {(x) = (void *)-1;} while (0)
+
+#define	QMD_TRACE_HEAD(head) do {					\
+	(head)->trace.prevline = (head)->trace.lastline;		\
+	(head)->trace.prevfile = (head)->trace.lastfile;		\
+	(head)->trace.lastline = __LINE__;				\
+	(head)->trace.lastfile = __FILE__;				\
+} while (0)
+
+#define	QMD_TRACE_ELEM(elem) do {					\
+	(elem)->trace.prevline = (elem)->trace.lastline;		\
+	(elem)->trace.prevfile = (elem)->trace.lastfile;		\
+	(elem)->trace.lastline = __LINE__;				\
+	(elem)->trace.lastfile = __FILE__;				\
+} while (0)
+
+#else
+#define	QMD_TRACE_ELEM(elem)
+#define	QMD_TRACE_HEAD(head)
+#define	TRACEBUF
+#define	TRASHIT(x)
+#endif	/* QUEUE_MACRO_DEBUG */
+
+/*
+ * Singly-linked List declarations.
+ */
+#define	SLIST_HEAD(name, type)						\
+struct name {								\
+	struct type *slh_first;	/* first element */			\
+}
+
+#define	SLIST_HEAD_INITIALIZER(head)					\
+	{ NULL }
+
+#define	SLIST_ENTRY(type)						\
+struct {								\
+	struct type *sle_next;	/* next element */			\
+}
+
+/*
+ * Singly-linked List functions.
+ */
+#define	SLIST_EMPTY(head)	((head)->slh_first == NULL)
+
+#define	SLIST_FIRST(head)	((head)->slh_first)
+
+#define	SLIST_FOREACH(var, head, field)					\
+	for ((var) = SLIST_FIRST((head));				\
+	    (var);							\
+	    (var) = SLIST_NEXT((var), field))
+
+#define	SLIST_FOREACH_SAFE(var, head, field, tvar)			\
+	for ((var) = SLIST_FIRST((head));				\
+	    (var) && ((tvar) = SLIST_NEXT((var), field), 1);		\
+	    (var) = (tvar))
+
+#define	SLIST_FOREACH_PREVPTR(var, varp, head, field)			\
+	for ((varp) = &SLIST_FIRST((head));				\
+	    ((var) = *(varp)) != NULL;					\
+	    (varp) = &SLIST_NEXT((var), field))
+
+#define	SLIST_INIT(head) do {						\
+	SLIST_FIRST((head)) = NULL;					\
+} while (0)
+
+#define	SLIST_INSERT_AFTER(slistelm, elm, field) do {			\
+	SLIST_NEXT((elm), field) = SLIST_NEXT((slistelm), field);	\
+	SLIST_NEXT((slistelm), field) = (elm);				\
+} while (0)
+
+#define	SLIST_INSERT_HEAD(head, elm, field) do {			\
+	SLIST_NEXT((elm), field) = SLIST_FIRST((head));			\
+	SLIST_FIRST((head)) = (elm);					\
+} while (0)
+
+#define	SLIST_NEXT(elm, field)	((elm)->field.sle_next)
+
+#define	SLIST_REMOVE(head, elm, type, field) do {			\
+	if (SLIST_FIRST((head)) == (elm)) {				\
+		SLIST_REMOVE_HEAD((head), field);			\
+	}								\
+	else {								\
+		struct type *curelm = SLIST_FIRST((head));		\
+		while (SLIST_NEXT(curelm, field) != (elm))		\
+			curelm = SLIST_NEXT(curelm, field);		\
+		SLIST_NEXT(curelm, field) =				\
+		    SLIST_NEXT(SLIST_NEXT(curelm, field), field);	\
+	}								\
+	TRASHIT((elm)->field.sle_next);					\
+} while (0)
+
+#define	SLIST_REMOVE_HEAD(head, field) do {				\
+	SLIST_FIRST((head)) = SLIST_NEXT(SLIST_FIRST((head)), field);	\
+} while (0)
+
+/*
+ * Singly-linked Tail queue declarations.
+ */
+#define	STAILQ_HEAD(name, type)						\
+struct name {								\
+	struct type *stqh_first;/* first element */			\
+	struct type **stqh_last;/* addr of last next element */		\
+}
+
+#define	STAILQ_HEAD_INITIALIZER(head)					\
+	{ NULL, &(head).stqh_first }
+
+#define	STAILQ_ENTRY(type)						\
+struct {								\
+	struct type *stqe_next;	/* next element */			\
+}
+
+/*
+ * Singly-linked Tail queue functions.
+ */
+#define	STAILQ_CONCAT(head1, head2) do {				\
+	if (!STAILQ_EMPTY((head2))) {					\
+		*(head1)->stqh_last = (head2)->stqh_first;		\
+		(head1)->stqh_last = (head2)->stqh_last;		\
+		STAILQ_INIT((head2));					\
+	}								\
+} while (0)
+
+#define	STAILQ_EMPTY(head)	((head)->stqh_first == NULL)
+
+#define	STAILQ_FIRST(head)	((head)->stqh_first)
+
+#define	STAILQ_FOREACH(var, head, field)				\
+	for((var) = STAILQ_FIRST((head));				\
+	   (var);							\
+	   (var) = STAILQ_NEXT((var), field))
+
+
+#define	STAILQ_FOREACH_SAFE(var, head, field, tvar)			\
+	for ((var) = STAILQ_FIRST((head));				\
+	    (var) && ((tvar) = STAILQ_NEXT((var), field), 1);		\
+	    (var) = (tvar))
+
+#define	STAILQ_INIT(head) do {						\
+	STAILQ_FIRST((head)) = NULL;					\
+	(head)->stqh_last = &STAILQ_FIRST((head));			\
+} while (0)
+
+#define	STAILQ_INSERT_AFTER(head, tqelm, elm, field) do {		\
+	if ((STAILQ_NEXT((elm), field) = STAILQ_NEXT((tqelm), field)) == NULL)\
+		(head)->stqh_last = &STAILQ_NEXT((elm), field);		\
+	STAILQ_NEXT((tqelm), field) = (elm);				\
+} while (0)
+
+#define	STAILQ_INSERT_HEAD(head, elm, field) do {			\
+	if ((STAILQ_NEXT((elm), field) = STAILQ_FIRST((head))) == NULL)	\
+		(head)->stqh_last = &STAILQ_NEXT((elm), field);		\
+	STAILQ_FIRST((head)) = (elm);					\
+} while (0)
+
+#define	STAILQ_INSERT_TAIL(head, elm, field) do {			\
+	STAILQ_NEXT((elm), field) = NULL;				\
+	*(head)->stqh_last = (elm);					\
+	(head)->stqh_last = &STAILQ_NEXT((elm), field);			\
+} while (0)
+
+#define	STAILQ_LAST(head, type, field)					\
+	(STAILQ_EMPTY((head)) ?						\
+		NULL :							\
+	        ((struct type *)(void *)				\
+		((char *)((head)->stqh_last) - __offsetof(struct type, field))))
+
+#define	STAILQ_NEXT(elm, field)	((elm)->field.stqe_next)
+
+#define	STAILQ_REMOVE(head, elm, type, field) do {			\
+	if (STAILQ_FIRST((head)) == (elm)) {				\
+		STAILQ_REMOVE_HEAD((head), field);			\
+	}								\
+	else {								\
+		struct type *curelm = STAILQ_FIRST((head));		\
+		while (STAILQ_NEXT(curelm, field) != (elm))		\
+			curelm = STAILQ_NEXT(curelm, field);		\
+		if ((STAILQ_NEXT(curelm, field) =			\
+		     STAILQ_NEXT(STAILQ_NEXT(curelm, field), field)) == NULL)\
+			(head)->stqh_last = &STAILQ_NEXT((curelm), field);\
+	}								\
+	TRASHIT((elm)->field.stqe_next);				\
+} while (0)
+
+#define	STAILQ_REMOVE_HEAD(head, field) do {				\
+	if ((STAILQ_FIRST((head)) =					\
+	     STAILQ_NEXT(STAILQ_FIRST((head)), field)) == NULL)		\
+		(head)->stqh_last = &STAILQ_FIRST((head));		\
+} while (0)
+
+/*
+ * List declarations.
+ */
+#define	LIST_HEAD(name, type)						\
+struct name {								\
+	struct type *lh_first;	/* first element */			\
+}
+
+#define	LIST_HEAD_INITIALIZER(head)					\
+	{ NULL }
+
+#define	LIST_ENTRY(type)						\
+struct {								\
+	struct type *le_next;	/* next element */			\
+	struct type **le_prev;	/* address of previous next element */	\
+}
+
+/*
+ * List functions.
+ */
+
+#if (defined(_KERNEL) && defined(INVARIANTS))
+#define	QMD_LIST_CHECK_HEAD(head, field) do {				\
+	if (LIST_FIRST((head)) != NULL &&				\
+	    LIST_FIRST((head))->field.le_prev !=			\
+	     &LIST_FIRST((head)))					\
+		panic("Bad list head %p first->prev != head", (head));	\
+} while (0)
+
+#define	QMD_LIST_CHECK_NEXT(elm, field) do {				\
+	if (LIST_NEXT((elm), field) != NULL &&				\
+	    LIST_NEXT((elm), field)->field.le_prev !=			\
+	     &((elm)->field.le_next))					\
+		panic("Bad link elm %p next->prev != elm", (elm));	\
+} while (0)
+
+#define	QMD_LIST_CHECK_PREV(elm, field) do {				\
+	if (*(elm)->field.le_prev != (elm))				\
+		panic("Bad link elm %p prev->next != elm", (elm));	\
+} while (0)
+#else
+#define	QMD_LIST_CHECK_HEAD(head, field)
+#define	QMD_LIST_CHECK_NEXT(elm, field)
+#define	QMD_LIST_CHECK_PREV(elm, field)
+#endif /* (_KERNEL && INVARIANTS) */
+
+#define	LIST_EMPTY(head)	((head)->lh_first == NULL)
+
+#define	LIST_FIRST(head)	((head)->lh_first)
+
+#define	LIST_FOREACH(var, head, field)					\
+	for ((var) = LIST_FIRST((head));				\
+	    (var);							\
+	    (var) = LIST_NEXT((var), field))
+
+#define	LIST_FOREACH_SAFE(var, head, field, tvar)			\
+	for ((var) = LIST_FIRST((head));				\
+	    (var) && ((tvar) = LIST_NEXT((var), field), 1);		\
+	    (var) = (tvar))
+
+#define	LIST_INIT(head) do {						\
+	LIST_FIRST((head)) = NULL;					\
+} while (0)
+
+#define	LIST_INSERT_AFTER(listelm, elm, field) do {			\
+	QMD_LIST_CHECK_NEXT(listelm, field);				\
+	if ((LIST_NEXT((elm), field) = LIST_NEXT((listelm), field)) != NULL)\
+		LIST_NEXT((listelm), field)->field.le_prev =		\
+		    &LIST_NEXT((elm), field);				\
+	LIST_NEXT((listelm), field) = (elm);				\
+	(elm)->field.le_prev = &LIST_NEXT((listelm), field);		\
+} while (0)
+
+#define	LIST_INSERT_BEFORE(listelm, elm, field) do {			\
+	QMD_LIST_CHECK_PREV(listelm, field);				\
+	(elm)->field.le_prev = (listelm)->field.le_prev;		\
+	LIST_NEXT((elm), field) = (listelm);				\
+	*(listelm)->field.le_prev = (elm);				\
+	(listelm)->field.le_prev = &LIST_NEXT((elm), field);		\
+} while (0)
+
+#define	LIST_INSERT_HEAD(head, elm, field) do {				\
+	QMD_LIST_CHECK_HEAD((head), field);				\
+	if ((LIST_NEXT((elm), field) = LIST_FIRST((head))) != NULL)	\
+		LIST_FIRST((head))->field.le_prev = &LIST_NEXT((elm), field);\
+	LIST_FIRST((head)) = (elm);					\
+	(elm)->field.le_prev = &LIST_FIRST((head));			\
+} while (0)
+
+#define	LIST_NEXT(elm, field)	((elm)->field.le_next)
+
+#define	LIST_REMOVE(elm, field) do {					\
+	QMD_LIST_CHECK_NEXT(elm, field);				\
+	QMD_LIST_CHECK_PREV(elm, field);				\
+	if (LIST_NEXT((elm), field) != NULL)				\
+		LIST_NEXT((elm), field)->field.le_prev = 		\
+		    (elm)->field.le_prev;				\
+	*(elm)->field.le_prev = LIST_NEXT((elm), field);		\
+	TRASHIT((elm)->field.le_next);					\
+	TRASHIT((elm)->field.le_prev);					\
+} while (0)
+
+/*
+ * Tail queue declarations.
+ */
+#define	TAILQ_HEAD(name, type)						\
+struct name {								\
+	struct type *tqh_first;	/* first element */			\
+	struct type **tqh_last;	/* addr of last next element */		\
+	TRACEBUF							\
+}
+
+#define	TAILQ_HEAD_INITIALIZER(head)					\
+	{ NULL, &(head).tqh_first }
+
+#define	TAILQ_ENTRY(type)						\
+struct {								\
+	struct type *tqe_next;	/* next element */			\
+	struct type **tqe_prev;	/* address of previous next element */	\
+	TRACEBUF							\
+}
+
+/*
+ * Tail queue functions.
+ */
+#if (defined(_KERNEL) && defined(INVARIANTS))
+#define	QMD_TAILQ_CHECK_HEAD(head, field) do {				\
+	if (!TAILQ_EMPTY(head) &&					\
+	    TAILQ_FIRST((head))->field.tqe_prev !=			\
+	     &TAILQ_FIRST((head)))					\
+		panic("Bad tailq head %p first->prev != head", (head));	\
+} while (0)
+
+#define	QMD_TAILQ_CHECK_TAIL(head, field) do {				\
+	if (*(head)->tqh_last != NULL)					\
+		panic("Bad tailq NEXT(%p->tqh_last) != NULL", (head)); 	\
+} while (0)
+
+#define	QMD_TAILQ_CHECK_NEXT(elm, field) do {				\
+	if (TAILQ_NEXT((elm), field) != NULL &&				\
+	    TAILQ_NEXT((elm), field)->field.tqe_prev !=			\
+	     &((elm)->field.tqe_next))					\
+		panic("Bad link elm %p next->prev != elm", (elm));	\
+} while (0)
+
+#define	QMD_TAILQ_CHECK_PREV(elm, field) do {				\
+	if (*(elm)->field.tqe_prev != (elm))				\
+		panic("Bad link elm %p prev->next != elm", (elm));	\
+} while (0)
+#else
+#define	QMD_TAILQ_CHECK_HEAD(head, field)
+#define	QMD_TAILQ_CHECK_TAIL(head, headname)
+#define	QMD_TAILQ_CHECK_NEXT(elm, field)
+#define	QMD_TAILQ_CHECK_PREV(elm, field)
+#endif /* (_KERNEL && INVARIANTS) */
+
+#define	TAILQ_CONCAT(head1, head2, field) do {				\
+	if (!TAILQ_EMPTY(head2)) {					\
+		*(head1)->tqh_last = (head2)->tqh_first;		\
+		(head2)->tqh_first->field.tqe_prev = (head1)->tqh_last;	\
+		(head1)->tqh_last = (head2)->tqh_last;			\
+		TAILQ_INIT((head2));					\
+		QMD_TRACE_HEAD(head1);					\
+		QMD_TRACE_HEAD(head2);					\
+	}								\
+} while (0)
+
+#define	TAILQ_EMPTY(head)	((head)->tqh_first == NULL)
+
+#define	TAILQ_FIRST(head)	((head)->tqh_first)
+
+#define	TAILQ_FOREACH(var, head, field)					\
+	for ((var) = TAILQ_FIRST((head));				\
+	    (var);							\
+	    (var) = TAILQ_NEXT((var), field))
+
+#define	TAILQ_FOREACH_SAFE(var, head, field, tvar)			\
+	for ((var) = TAILQ_FIRST((head));				\
+	    (var) && ((tvar) = TAILQ_NEXT((var), field), 1);		\
+	    (var) = (tvar))
+
+#define	TAILQ_FOREACH_REVERSE(var, head, headname, field)		\
+	for ((var) = TAILQ_LAST((head), headname);			\
+	    (var);							\
+	    (var) = TAILQ_PREV((var), headname, field))
+
+#define	TAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, tvar)	\
+	for ((var) = TAILQ_LAST((head), headname);			\
+	    (var) && ((tvar) = TAILQ_PREV((var), headname, field), 1);	\
+	    (var) = (tvar))
+
+#define	TAILQ_INIT(head) do {						\
+	TAILQ_FIRST((head)) = NULL;					\
+	(head)->tqh_last = &TAILQ_FIRST((head));			\
+	QMD_TRACE_HEAD(head);						\
+} while (0)
+
+#define	TAILQ_INSERT_AFTER(head, listelm, elm, field) do {		\
+	QMD_TAILQ_CHECK_NEXT(listelm, field);				\
+	if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\
+		TAILQ_NEXT((elm), field)->field.tqe_prev = 		\
+		    &TAILQ_NEXT((elm), field);				\
+	else {								\
+		(head)->tqh_last = &TAILQ_NEXT((elm), field);		\
+		QMD_TRACE_HEAD(head);					\
+	}								\
+	TAILQ_NEXT((listelm), field) = (elm);				\
+	(elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field);		\
+	QMD_TRACE_ELEM(&(elm)->field);					\
+	QMD_TRACE_ELEM(&listelm->field);				\
+} while (0)
+
+#define	TAILQ_INSERT_BEFORE(listelm, elm, field) do {			\
+	QMD_TAILQ_CHECK_PREV(listelm, field);				\
+	(elm)->field.tqe_prev = (listelm)->field.tqe_prev;		\
+	TAILQ_NEXT((elm), field) = (listelm);				\
+	*(listelm)->field.tqe_prev = (elm);				\
+	(listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field);		\
+	QMD_TRACE_ELEM(&(elm)->field);					\
+	QMD_TRACE_ELEM(&listelm->field);				\
+} while (0)
+
+#define	TAILQ_INSERT_HEAD(head, elm, field) do {			\
+	QMD_TAILQ_CHECK_HEAD(head, field);				\
+	if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL)	\
+		TAILQ_FIRST((head))->field.tqe_prev =			\
+		    &TAILQ_NEXT((elm), field);				\
+	else								\
+		(head)->tqh_last = &TAILQ_NEXT((elm), field);		\
+	TAILQ_FIRST((head)) = (elm);					\
+	(elm)->field.tqe_prev = &TAILQ_FIRST((head));			\
+	QMD_TRACE_HEAD(head);						\
+	QMD_TRACE_ELEM(&(elm)->field);					\
+} while (0)
+
+#define	TAILQ_INSERT_TAIL(head, elm, field) do {			\
+	QMD_TAILQ_CHECK_TAIL(head, field);				\
+	TAILQ_NEXT((elm), field) = NULL;				\
+	(elm)->field.tqe_prev = (head)->tqh_last;			\
+	*(head)->tqh_last = (elm);					\
+	(head)->tqh_last = &TAILQ_NEXT((elm), field);			\
+	QMD_TRACE_HEAD(head);						\
+	QMD_TRACE_ELEM(&(elm)->field);					\
+} while (0)
+
+#define	TAILQ_LAST(head, headname)					\
+	(*(((struct headname *)((head)->tqh_last))->tqh_last))
+
+#define	TAILQ_NEXT(elm, field) ((elm)->field.tqe_next)
+
+#define	TAILQ_PREV(elm, headname, field)				\
+	(*(((struct headname *)((elm)->field.tqe_prev))->tqh_last))
+
+#define	TAILQ_REMOVE(head, elm, field) do {				\
+	QMD_TAILQ_CHECK_NEXT(elm, field);				\
+	QMD_TAILQ_CHECK_PREV(elm, field);				\
+	if ((TAILQ_NEXT((elm), field)) != NULL)				\
+		TAILQ_NEXT((elm), field)->field.tqe_prev = 		\
+		    (elm)->field.tqe_prev;				\
+	else {								\
+		(head)->tqh_last = (elm)->field.tqe_prev;		\
+		QMD_TRACE_HEAD(head);					\
+	}								\
+	*(elm)->field.tqe_prev = TAILQ_NEXT((elm), field);		\
+	TRASHIT((elm)->field.tqe_next);					\
+	TRASHIT((elm)->field.tqe_prev);					\
+	QMD_TRACE_ELEM(&(elm)->field);					\
+} while (0)
+
+
+#ifdef _KERNEL
+
+/*
+ * XXX insque() and remque() are an old way of handling certain queues.
+ * They bogusly assumes that all queue heads look alike.
+ */
+
+struct quehead {
+	struct quehead *qh_link;
+	struct quehead *qh_rlink;
+};
+
+#ifdef __CC_SUPPORTS___INLINE
+
+static __inline void
+insque(void *a, void *b)
+{
+	struct quehead *element = (struct quehead *)a,
+		 *head = (struct quehead *)b;
+
+	element->qh_link = head->qh_link;
+	element->qh_rlink = head;
+	head->qh_link = element;
+	element->qh_link->qh_rlink = element;
+}
+
+static __inline void
+remque(void *a)
+{
+	struct quehead *element = (struct quehead *)a;
+
+	element->qh_link->qh_rlink = element->qh_rlink;
+	element->qh_rlink->qh_link = element->qh_link;
+	element->qh_rlink = 0;
+}
+
+#else /* !__CC_SUPPORTS___INLINE */
+
+void	insque(void *a, void *b);
+void	remque(void *a);
+
+#endif /* __CC_SUPPORTS___INLINE */
+
+#endif /* _KERNEL */
+
+#endif /* !_SYS_QUEUE_H_ */
diff --git a/contrib/ofed/libcxgb4/src/t4.h b/contrib/ofed/libcxgb4/src/t4.h
new file mode 100644
index 0000000..ce48244
--- /dev/null
+++ b/contrib/ofed/libcxgb4/src/t4.h
@@ -0,0 +1,715 @@
+/*
+ * Copyright (c) 2006-2014 Chelsio, Inc. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#ifndef __T4_H__
+#define __T4_H__
+
+#include <stdint.h>
+#include <assert.h>
+#include <syslog.h>
+
+#define ENODATA 95
+#undef  ELAST
+#define ELAST ENODATA
+
+/*
+ * Try and minimize the changes from the kernel code that is pull in
+ * here for kernel bypass ops.
+ */
+#define __u8 uint8_t
+#define u8 uint8_t
+#define __u16 uint16_t
+#define __be16 uint16_t
+#define u16 uint16_t
+#define __u32 uint32_t
+#define __be32 uint32_t
+#define u32 uint32_t
+#define __u64 uint64_t
+#define __be64 uint64_t
+#define u64 uint64_t
+#define DECLARE_PCI_UNMAP_ADDR(a)
+#define __iomem
+#define cpu_to_be16 htons
+#define cpu_to_be32 htonl
+#define cpu_to_be64 htonll
+#define be16_to_cpu ntohs
+#define be32_to_cpu ntohl
+#define be64_to_cpu ntohll
+#define BUG_ON(c) assert(!(c))
+#define unlikely
+#define ROUND_UP(x, n) (((x) + (n) - 1u) & ~((n) - 1u))
+#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+#  define cpu_to_pci32(val) ((val))
+#elif __BYTE_ORDER == __BIG_ENDIAN
+#  define cpu_to_pci32(val) (__bswap_32((val)))
+#else
+#  error __BYTE_ORDER not defined
+#endif
+
+#define writel(v, a) do { *((volatile u32 *)(a)) = cpu_to_pci32(v); } while (0)
+
+#include <arpa/inet.h> 			/* For htonl() and friends */
+#include "t4_regs.h"
+#include "t4_chip_type.h"
+#include "t4fw_interface.h"
+
+#ifdef DEBUG
+#define DBGLOG(s)
+#define PDBG(fmt, args...) do {syslog(LOG_DEBUG, fmt, ##args); } while (0)
+#else
+#define DBGLOG(s)
+#define PDBG(fmt, args...) do {} while (0)
+#endif
+
+#define T4_MAX_READ_DEPTH 16
+#define T4_QID_BASE 1024
+#define T4_MAX_QIDS 256
+#define T4_MAX_NUM_PD 65536
+#define T4_EQ_STATUS_ENTRIES (L1_CACHE_BYTES > 64 ? 2 : 1)
+#define T4_MAX_EQ_SIZE (65520 - T4_EQ_STATUS_ENTRIES)
+#define T4_MAX_IQ_SIZE (65520 - 1)
+#define T4_MAX_RQ_SIZE (8192 - T4_EQ_STATUS_ENTRIES)
+#define T4_MAX_SQ_SIZE (T4_MAX_EQ_SIZE - 1)
+#define T4_MAX_QP_DEPTH (T4_MAX_RQ_SIZE - 1)
+#define T4_MAX_CQ_DEPTH (T4_MAX_IQ_SIZE - 1)
+#define T4_MAX_NUM_STAG (1<<15)
+#define T4_MAX_MR_SIZE (~0ULL - 1)
+#define T4_PAGESIZE_MASK 0xffff000  /* 4KB-128MB */
+#define T4_STAG_UNSET 0xffffffff
+#define T4_FW_MAJ 0
+
+struct t4_status_page {
+	__be32 rsvd1;	/* flit 0 - hw owns */
+	__be16 rsvd2;
+	__be16 qid;
+	__be16 cidx;
+	__be16 pidx;
+	u8 qp_err;	/* flit 1 - sw owns */
+	u8 db_off;
+	u8 pad;
+	u16 host_wq_pidx;
+	u16 host_cidx;
+	u16 host_pidx;
+};
+
+#define T4_EQ_ENTRY_SIZE 64
+
+#define T4_SQ_NUM_SLOTS 5
+#define T4_SQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_SQ_NUM_SLOTS)
+#define T4_MAX_SEND_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - sizeof(struct fw_ri_isgl)) / sizeof (struct fw_ri_sge))
+#define T4_MAX_SEND_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_send_wr) - sizeof(struct fw_ri_immd)))
+#define T4_MAX_WRITE_INLINE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_rdma_write_wr) - sizeof(struct fw_ri_immd)))
+#define T4_MAX_WRITE_SGE ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_rdma_write_wr) - sizeof(struct fw_ri_isgl)) / sizeof (struct fw_ri_sge))
+#define T4_MAX_FR_IMMD ((T4_SQ_NUM_BYTES - sizeof(struct fw_ri_fr_nsmr_wr) - sizeof(struct fw_ri_immd)))
+#define T4_MAX_FR_DEPTH 255
+
+#define T4_RQ_NUM_SLOTS 2
+#define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS)
+#define T4_MAX_RECV_SGE 4
+
+union t4_wr {
+	struct fw_ri_res_wr res;
+	struct fw_ri_wr init;
+	struct fw_ri_rdma_write_wr write;
+	struct fw_ri_send_wr send;
+	struct fw_ri_rdma_read_wr read;
+	struct fw_ri_bind_mw_wr bind;
+	struct fw_ri_fr_nsmr_wr fr;
+	struct fw_ri_inv_lstag_wr inv;
+	struct t4_status_page status;
+	__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_SQ_NUM_SLOTS];
+};
+
+union t4_recv_wr {
+	struct fw_ri_recv_wr recv;
+	struct t4_status_page status;
+	__be64 flits[T4_EQ_ENTRY_SIZE / sizeof(__be64) * T4_RQ_NUM_SLOTS];
+};
+
+static inline void init_wr_hdr(union t4_wr *wqe, u16 wrid,
+			       enum fw_wr_opcodes opcode, u8 flags, u8 len16)
+{
+	wqe->send.opcode = (u8)opcode;
+	wqe->send.flags = flags;
+	wqe->send.wrid = wrid;
+	wqe->send.r1[0] = 0;
+	wqe->send.r1[1] = 0;
+	wqe->send.r1[2] = 0;
+	wqe->send.len16 = len16;
+}
+
+/* CQE/AE status codes */
+#define T4_ERR_SUCCESS                     0x0
+#define T4_ERR_STAG                        0x1	/* STAG invalid: either the */
+						/* STAG is offlimt, being 0, */
+						/* or STAG_key mismatch */
+#define T4_ERR_PDID                        0x2	/* PDID mismatch */
+#define T4_ERR_QPID                        0x3	/* QPID mismatch */
+#define T4_ERR_ACCESS                      0x4	/* Invalid access right */
+#define T4_ERR_WRAP                        0x5	/* Wrap error */
+#define T4_ERR_BOUND                       0x6	/* base and bounds voilation */
+#define T4_ERR_INVALIDATE_SHARED_MR        0x7	/* attempt to invalidate a  */
+						/* shared memory region */
+#define T4_ERR_INVALIDATE_MR_WITH_MW_BOUND 0x8	/* attempt to invalidate a  */
+						/* shared memory region */
+#define T4_ERR_ECC                         0x9	/* ECC error detected */
+#define T4_ERR_ECC_PSTAG                   0xA	/* ECC error detected when  */
+						/* reading PSTAG for a MW  */
+						/* Invalidate */
+#define T4_ERR_PBL_ADDR_BOUND              0xB	/* pbl addr out of bounds:  */
+						/* software error */
+#define T4_ERR_SWFLUSH			   0xC	/* SW FLUSHED */
+#define T4_ERR_CRC                         0x10 /* CRC error */
+#define T4_ERR_MARKER                      0x11 /* Marker error */
+#define T4_ERR_PDU_LEN_ERR                 0x12 /* invalid PDU length */
+#define T4_ERR_OUT_OF_RQE                  0x13 /* out of RQE */
+#define T4_ERR_DDP_VERSION                 0x14 /* wrong DDP version */
+#define T4_ERR_RDMA_VERSION                0x15 /* wrong RDMA version */
+#define T4_ERR_OPCODE                      0x16 /* invalid rdma opcode */
+#define T4_ERR_DDP_QUEUE_NUM               0x17 /* invalid ddp queue number */
+#define T4_ERR_MSN                         0x18 /* MSN error */
+#define T4_ERR_TBIT                        0x19 /* tag bit not set correctly */
+#define T4_ERR_MO                          0x1A /* MO not 0 for TERMINATE  */
+						/* or READ_REQ */
+#define T4_ERR_MSN_GAP                     0x1B
+#define T4_ERR_MSN_RANGE                   0x1C
+#define T4_ERR_IRD_OVERFLOW                0x1D
+#define T4_ERR_RQE_ADDR_BOUND              0x1E /* RQE addr out of bounds:  */
+						/* software error */
+#define T4_ERR_INTERNAL_ERR                0x1F /* internal error (opcode  */
+						/* mismatch) */
+/*
+ * CQE defs
+ */
+struct t4_cqe {
+	__be32 header;
+	__be32 len;
+	union {
+		struct {
+			__be32 stag;
+			__be32 msn;
+		} rcqe;
+		struct {
+			u32 nada1;
+			u16 nada2;
+			u16 cidx;
+		} scqe;
+		struct {
+			__be32 wrid_hi;
+			__be32 wrid_low;
+		} gen;
+	} u;
+	__be64 reserved;
+	__be64 bits_type_ts;
+};
+
+/* macros for flit 0 of the cqe */
+
+#define S_CQE_QPID        12
+#define M_CQE_QPID        0xFFFFF
+#define G_CQE_QPID(x)     ((((x) >> S_CQE_QPID)) & M_CQE_QPID)
+#define V_CQE_QPID(x)	  ((x)<<S_CQE_QPID)
+
+#define S_CQE_SWCQE       11
+#define M_CQE_SWCQE       0x1
+#define G_CQE_SWCQE(x)    ((((x) >> S_CQE_SWCQE)) & M_CQE_SWCQE)
+#define V_CQE_SWCQE(x)	  ((x)<<S_CQE_SWCQE)
+
+#define S_CQE_STATUS      5
+#define M_CQE_STATUS      0x1F
+#define G_CQE_STATUS(x)   ((((x) >> S_CQE_STATUS)) & M_CQE_STATUS)
+#define V_CQE_STATUS(x)   ((x)<<S_CQE_STATUS)
+
+#define S_CQE_TYPE        4
+#define M_CQE_TYPE        0x1
+#define G_CQE_TYPE(x)     ((((x) >> S_CQE_TYPE)) & M_CQE_TYPE)
+#define V_CQE_TYPE(x)     ((x)<<S_CQE_TYPE)
+
+#define S_CQE_OPCODE      0
+#define M_CQE_OPCODE      0xF
+#define G_CQE_OPCODE(x)   ((((x) >> S_CQE_OPCODE)) & M_CQE_OPCODE)
+#define V_CQE_OPCODE(x)   ((x)<<S_CQE_OPCODE)
+
+#define SW_CQE(x)         (G_CQE_SWCQE(be32_to_cpu((x)->header)))
+#define CQE_QPID(x)       (G_CQE_QPID(be32_to_cpu((x)->header)))
+#define CQE_TYPE(x)       (G_CQE_TYPE(be32_to_cpu((x)->header)))
+#define SQ_TYPE(x)	  (CQE_TYPE((x)))
+#define RQ_TYPE(x)	  (!CQE_TYPE((x)))
+#define CQE_STATUS(x)     (G_CQE_STATUS(be32_to_cpu((x)->header)))
+#define CQE_OPCODE(x)     (G_CQE_OPCODE(be32_to_cpu((x)->header)))
+
+#define CQE_SEND_OPCODE(x)( \
+	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND) || \
+	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE) || \
+	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_INV) || \
+	(G_CQE_OPCODE(be32_to_cpu((x)->header)) == FW_RI_SEND_WITH_SE_INV))
+
+#define CQE_LEN(x)        (be32_to_cpu((x)->len))
+
+/* used for RQ completion processing */
+#define CQE_WRID_STAG(x)  (be32_to_cpu((x)->u.rcqe.stag))
+#define CQE_WRID_MSN(x)   (be32_to_cpu((x)->u.rcqe.msn))
+
+/* used for SQ completion processing */
+#define CQE_WRID_SQ_IDX(x)	(x)->u.scqe.cidx
+
+/* generic accessor macros */
+#define CQE_WRID_HI(x)		((x)->u.gen.wrid_hi)
+#define CQE_WRID_LOW(x)		((x)->u.gen.wrid_low)
+
+/* macros for flit 3 of the cqe */
+#define S_CQE_GENBIT	63
+#define M_CQE_GENBIT	0x1
+#define G_CQE_GENBIT(x)	(((x) >> S_CQE_GENBIT) & M_CQE_GENBIT)
+#define V_CQE_GENBIT(x) ((x)<<S_CQE_GENBIT)
+
+#define S_CQE_OVFBIT	62
+#define M_CQE_OVFBIT	0x1
+#define G_CQE_OVFBIT(x)	((((x) >> S_CQE_OVFBIT)) & M_CQE_OVFBIT)
+
+#define S_CQE_IQTYPE	60
+#define M_CQE_IQTYPE	0x3
+#define G_CQE_IQTYPE(x)	((((x) >> S_CQE_IQTYPE)) & M_CQE_IQTYPE)
+
+#define M_CQE_TS	0x0fffffffffffffffULL
+#define G_CQE_TS(x)	((x) & M_CQE_TS)
+
+#define CQE_OVFBIT(x)	((unsigned)G_CQE_OVFBIT(be64_to_cpu((x)->bits_type_ts)))
+#define CQE_GENBIT(x)	((unsigned)G_CQE_GENBIT(be64_to_cpu((x)->bits_type_ts)))
+#define CQE_TS(x)	(G_CQE_TS(be64_to_cpu((x)->bits_type_ts)))
+
+struct t4_swsqe {
+	u64			wr_id;
+	struct t4_cqe		cqe;
+	__be32			read_len;
+	int			opcode;
+	int			complete;
+	int			signaled;
+	u16			idx;
+	int			flushed;
+};
+
+enum {
+	T4_SQ_ONCHIP = (1<<0),
+};
+
+struct t4_sq {
+	union t4_wr *queue;
+	struct t4_swsqe *sw_sq;
+	struct t4_swsqe *oldest_read;
+	volatile u32 *udb;
+	size_t memsize;
+	u32 qid;
+	void *ma_sync;
+	u16 in_use;
+	u16 size;
+	u16 cidx;
+	u16 pidx;
+	u16 wq_pidx;
+	u16 flags;
+	short flush_cidx;
+};
+
+struct t4_swrqe {
+	u64 wr_id;
+};
+
+struct t4_rq {
+	union  t4_recv_wr *queue;
+	struct t4_swrqe *sw_rq;
+	volatile u32 *udb;
+	size_t memsize;
+	u32 qid;
+	u32 msn;
+	u32 rqt_hwaddr;
+	u16 rqt_size;
+	u16 in_use;
+	u16 size;
+	u16 cidx;
+	u16 pidx;
+	u16 wq_pidx;
+};
+
+struct t4_wq {
+	struct t4_sq sq;
+	struct t4_rq rq;
+	struct c4iw_rdev *rdev;
+	u32 qid_mask;
+	int error;
+	int flushed;
+	u8 *db_offp;
+};
+
+static inline void t4_ma_sync(struct t4_wq *wq, int page_size)
+{
+	wc_wmb();
+	*((volatile u32 *)wq->sq.ma_sync) = 1;
+}
+
+static inline int t4_rqes_posted(struct t4_wq *wq)
+{
+	return wq->rq.in_use;
+}
+
+static inline int t4_rq_empty(struct t4_wq *wq)
+{
+	return wq->rq.in_use == 0;
+}
+
+static inline int t4_rq_full(struct t4_wq *wq)
+{
+	return wq->rq.in_use == (wq->rq.size - 1);
+}
+
+static inline u32 t4_rq_avail(struct t4_wq *wq)
+{
+	return wq->rq.size - 1 - wq->rq.in_use;
+}
+
+static inline void t4_rq_produce(struct t4_wq *wq, u8 len16)
+{
+	wq->rq.in_use++;
+	if (++wq->rq.pidx == wq->rq.size)
+		wq->rq.pidx = 0;
+	wq->rq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
+	if (wq->rq.wq_pidx >= wq->rq.size * T4_RQ_NUM_SLOTS)
+		wq->rq.wq_pidx %= wq->rq.size * T4_RQ_NUM_SLOTS;
+	if (!wq->error)
+		wq->rq.queue[wq->rq.size].status.host_pidx = wq->rq.pidx;
+}
+
+static inline void t4_rq_consume(struct t4_wq *wq)
+{
+	wq->rq.in_use--;
+	wq->rq.msn++;
+	if (++wq->rq.cidx == wq->rq.size)
+		wq->rq.cidx = 0;
+	assert((wq->rq.cidx != wq->rq.pidx) || wq->rq.in_use == 0);
+	if (!wq->error)
+		wq->rq.queue[wq->rq.size].status.host_cidx = wq->rq.cidx;
+}
+
+static inline int t4_sq_empty(struct t4_wq *wq)
+{
+	return wq->sq.in_use == 0;
+}
+
+static inline int t4_sq_full(struct t4_wq *wq)
+{
+	return wq->sq.in_use == (wq->sq.size - 1);
+}
+
+static inline u32 t4_sq_avail(struct t4_wq *wq)
+{
+	return wq->sq.size - 1 - wq->sq.in_use;
+}
+
+static inline int t4_sq_onchip(struct t4_wq *wq)
+{
+	return wq->sq.flags & T4_SQ_ONCHIP;
+}
+
+static inline void t4_sq_produce(struct t4_wq *wq, u8 len16)
+{
+	wq->sq.in_use++;
+	if (++wq->sq.pidx == wq->sq.size)
+		wq->sq.pidx = 0;
+	wq->sq.wq_pidx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
+	if (wq->sq.wq_pidx >= wq->sq.size * T4_SQ_NUM_SLOTS)
+		wq->sq.wq_pidx %= wq->sq.size * T4_SQ_NUM_SLOTS;
+	if (!wq->error)
+		wq->sq.queue[wq->sq.size].status.host_pidx = (wq->sq.pidx);
+}
+
+static inline void t4_sq_consume(struct t4_wq *wq)
+{
+	assert(wq->sq.in_use >= 1);
+	if (wq->sq.cidx == wq->sq.flush_cidx)
+                wq->sq.flush_cidx = -1;
+	wq->sq.in_use--;
+	if (++wq->sq.cidx == wq->sq.size)
+		wq->sq.cidx = 0;
+	assert((wq->sq.cidx != wq->sq.pidx) || wq->sq.in_use == 0);
+	if (!wq->error)
+		wq->sq.queue[wq->sq.size].status.host_cidx = wq->sq.cidx;
+}
+
+static void copy_wqe_to_udb(volatile u32 *udb_offset, void *wqe)
+{
+	u64 *src, *dst;
+	int len16 = 4;
+
+	src = (u64 *)wqe;
+	dst = (u64 *)udb_offset;
+
+	while (len16) {
+		*dst++ = *src++;
+		*dst++ = *src++;
+		len16--;
+	}
+}
+
+extern int ma_wr;
+extern int t5_en_wc;
+
+static inline void t4_ring_sq_db(struct t4_wq *wq, u16 inc, u8 t5, u8 len16,
+				 union t4_wr *wqe)
+{
+	wc_wmb();
+	if (t5) {
+		if (t5_en_wc && inc == 1) {
+			PDBG("%s: WC wq->sq.pidx = %d; len16=%d\n",
+			     __func__, wq->sq.pidx, len16);
+			copy_wqe_to_udb(wq->sq.udb + 14, wqe);
+		} else {
+			PDBG("%s: DB wq->sq.pidx = %d; len16=%d\n",
+			     __func__, wq->sq.pidx, len16);
+			writel(V_PIDX_T5(inc), wq->sq.udb);
+		}
+		wc_wmb();
+		return;
+	}
+	if (ma_wr) {
+		if (t4_sq_onchip(wq)) {
+			int i;
+			for (i = 0; i < 16; i++)
+				*(volatile u32 *)&wq->sq.queue[wq->sq.size].flits[2+i] = i;
+		}
+	} else {
+		if (t4_sq_onchip(wq)) {
+			int i;
+			for (i = 0; i < 16; i++)
+				*(u32 *)&wq->sq.queue[wq->sq.size].flits[2] = i;
+		}
+	}
+	writel(V_QID(wq->sq.qid & wq->qid_mask) | V_PIDX(inc), wq->sq.udb);
+}
+
+static inline void t4_ring_rq_db(struct t4_wq *wq, u16 inc, u8 t5, u8 len16,
+				 union t4_recv_wr *wqe)
+{
+	wc_wmb();
+	if (t5) {
+		if (t5_en_wc && inc == 1) {
+			PDBG("%s: WC wq->rq.pidx = %d; len16=%d\n",
+			     __func__, wq->rq.pidx, len16);
+			copy_wqe_to_udb(wq->rq.udb + 14, wqe);
+		} else {
+			PDBG("%s: DB wq->rq.pidx = %d; len16=%d\n",
+			     __func__, wq->rq.pidx, len16);
+			writel(V_PIDX_T5(inc), wq->rq.udb);
+		}
+		wc_wmb();
+		return;
+	}
+	writel(V_QID(wq->rq.qid & wq->qid_mask) | V_PIDX(inc), wq->rq.udb);
+}
+
+static inline int t4_wq_in_error(struct t4_wq *wq)
+{
+	return wq->error || wq->rq.queue[wq->rq.size].status.qp_err;
+}
+
+static inline void t4_set_wq_in_error(struct t4_wq *wq)
+{
+	wq->rq.queue[wq->rq.size].status.qp_err = 1;
+}
+
+extern int c4iw_abi_version;
+
+static inline int t4_wq_db_enabled(struct t4_wq *wq)
+{
+	/*
+	 * If iw_cxgb4 driver supports door bell drop recovery then its
+	 * c4iw_abi_version would be greater than or equal to 2. In such
+	 * case return the status of db_off flag to ring the kernel mode
+	 * DB from user mode library.
+	 */
+	if ( c4iw_abi_version >= 2 )
+		return ! *wq->db_offp;
+	else
+		return 1;
+}
+
+struct t4_cq {
+	struct t4_cqe *queue;
+	struct t4_cqe *sw_queue;
+	struct c4iw_rdev *rdev;
+	volatile u32 *ugts;
+	size_t memsize;
+	u64 bits_type_ts;
+	u32 cqid;
+	u32 qid_mask;
+	u16 size; /* including status page */
+	u16 cidx;
+	u16 sw_pidx;
+	u16 sw_cidx;
+	u16 sw_in_use;
+	u16 cidx_inc;
+	u8 gen;
+	u8 error;
+};
+
+static inline int t4_arm_cq(struct t4_cq *cq, int se)
+{
+	u32 val;
+
+	while (cq->cidx_inc > M_CIDXINC) {
+		val = V_SEINTARM(0) | V_CIDXINC(M_CIDXINC) | V_TIMERREG(7) |
+		      V_INGRESSQID(cq->cqid & cq->qid_mask);
+		writel(val, cq->ugts);
+		cq->cidx_inc -= M_CIDXINC;
+	}
+	val = V_SEINTARM(se) | V_CIDXINC(cq->cidx_inc) | V_TIMERREG(6) |
+	      V_INGRESSQID(cq->cqid & cq->qid_mask);
+	writel(val, cq->ugts);
+	cq->cidx_inc = 0;
+	return 0;
+}
+
+static inline void t4_swcq_produce(struct t4_cq *cq)
+{
+	cq->sw_in_use++;
+	if (cq->sw_in_use == cq->size) {
+		syslog(LOG_NOTICE, "cxgb4 sw cq overflow cqid %u\n", cq->cqid);
+		cq->error = 1;
+		assert(0);
+	}
+	if (++cq->sw_pidx == cq->size)
+		cq->sw_pidx = 0;
+}
+
+static inline void t4_swcq_consume(struct t4_cq *cq)
+{
+	assert(cq->sw_in_use >= 1);
+	cq->sw_in_use--;
+	if (++cq->sw_cidx == cq->size)
+		cq->sw_cidx = 0;
+}
+
+static inline void t4_hwcq_consume(struct t4_cq *cq)
+{
+	cq->bits_type_ts = cq->queue[cq->cidx].bits_type_ts;
+	if (++cq->cidx_inc == (cq->size >> 4) || cq->cidx_inc == M_CIDXINC) {
+		uint32_t val;
+
+		val = V_SEINTARM(0) | V_CIDXINC(cq->cidx_inc) | V_TIMERREG(7) |
+			V_INGRESSQID(cq->cqid & cq->qid_mask);
+		writel(val, cq->ugts);
+		cq->cidx_inc = 0;
+	}
+	if (++cq->cidx == cq->size) {
+		cq->cidx = 0;
+		cq->gen ^= 1;
+	}
+	((struct t4_status_page *)&cq->queue[cq->size])->host_cidx = cq->cidx;
+}
+
+static inline int t4_valid_cqe(struct t4_cq *cq, struct t4_cqe *cqe)
+{
+	return (CQE_GENBIT(cqe) == cq->gen);
+}
+
+static inline int t4_next_hw_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
+{
+	int ret;
+	u16 prev_cidx;
+
+	if (cq->cidx == 0)
+		prev_cidx = cq->size - 1;
+	else
+		prev_cidx = cq->cidx - 1;
+
+	if (cq->queue[prev_cidx].bits_type_ts != cq->bits_type_ts) {
+		ret = -EOVERFLOW;
+		syslog(LOG_NOTICE, "cxgb4 cq overflow cqid %u\n", cq->cqid);
+		cq->error = 1;
+		assert(0);
+	} else if (t4_valid_cqe(cq, &cq->queue[cq->cidx])) {
+		rmb();
+		*cqe = &cq->queue[cq->cidx];
+		ret = 0;
+	} else
+		ret = -ENODATA;
+	return ret;
+}
+
+static inline struct t4_cqe *t4_next_sw_cqe(struct t4_cq *cq)
+{
+	if (cq->sw_in_use == cq->size) {
+		syslog(LOG_NOTICE, "cxgb4 sw cq overflow cqid %u\n", cq->cqid);
+		cq->error = 1;
+		assert(0);
+		return NULL;
+	}
+	if (cq->sw_in_use)
+		return &cq->sw_queue[cq->sw_cidx];
+	return NULL;
+}
+
+static inline int t4_cq_notempty(struct t4_cq *cq)
+{
+	return cq->sw_in_use || t4_valid_cqe(cq, &cq->queue[cq->cidx]);
+}
+
+static inline int t4_next_cqe(struct t4_cq *cq, struct t4_cqe **cqe)
+{
+	int ret = 0;
+
+	if (cq->error)
+		ret = -ENODATA;
+	else if (cq->sw_in_use)
+		*cqe = &cq->sw_queue[cq->sw_cidx];
+	else ret = t4_next_hw_cqe(cq, cqe);
+	return ret;
+}
+
+static inline int t4_cq_in_error(struct t4_cq *cq)
+{
+	return ((struct t4_status_page *)&cq->queue[cq->size])->qp_err;
+}
+
+static inline void t4_set_cq_in_error(struct t4_cq *cq)
+{
+	((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 1;
+}
+
+static inline void t4_reset_cq_in_error(struct t4_cq *cq)
+{
+	((struct t4_status_page *)&cq->queue[cq->size])->qp_err = 0;
+}
+
+struct t4_dev_status_page 
+{
+	u8 db_off;
+};
+
+#endif
diff --git a/contrib/ofed/libcxgb4/src/t4_chip_type.h b/contrib/ofed/libcxgb4/src/t4_chip_type.h
new file mode 100644
index 0000000..b4f164c
--- /dev/null
+++ b/contrib/ofed/libcxgb4/src/t4_chip_type.h
@@ -0,0 +1,96 @@
+/*
+ * This file is part of the Chelsio T4 Ethernet driver.
+ *
+ * Copyright (C) 2003-2014 Chelsio Communications.  All rights reserved.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the LICENSE file included in this
+ * release for licensing terms and conditions.
+ */
+#ifndef __T4_CHIP_TYPE_H__
+#define __T4_CHIP_TYPE_H__
+
+/*
+ * All T4 and later chips have their PCI-E Device IDs encoded as 0xVFPP where:
+ *
+ *   V  = "4" for T4; "5" for T5, etc. or
+ *      = "a" for T4 FPGA; "b" for T4 FPGA, etc.
+ *   F  = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs
+ *   PP = adapter product designation
+ *
+ * We use the "version" (V) of the adpater to code the Chip Version above
+ * but separate out the FPGA as a separate boolean as per above.
+ */
+#define CHELSIO_PCI_ID_VER(__DeviceID)	((__DeviceID) >> 12)
+#define CHELSIO_PCI_ID_FUNC(__DeviceID)	(((__DeviceID) >> 8) & 0xf)
+#define CHELSIO_PCI_ID_PROD(__DeviceID)	((__DeviceID) & 0xff)
+
+#define CHELSIO_T4		0x4
+#define CHELSIO_T4_FPGA		0xa
+#define CHELSIO_T5		0x5
+#define CHELSIO_T5_FPGA		0xb
+
+/*
+ * Translate a PCI Device ID to a base Chelsio Chip Version -- CHELSIO_T4,
+ * CHELSIO_T5, etc.  If it weren't for the screwed up numbering of the FPGAs
+ * we could do this simply as DeviceID >> 12 (because we know the real
+ * encoding oc CHELSIO_Tx identifiers).  However, the FPGAs _do_ have weird
+ * Device IDs so we need to do this translation here.  Note that only constant
+ * arithmetic and comparisons can be done here since this is being used to
+ * initialize static tables, etc.
+ *
+ * Finally: This will of course need to be expanded as future chips are
+ * developed.
+ */
+#define CHELSIO_PCI_ID_CHIP_VERSION(__DeviceID) \
+	(CHELSIO_PCI_ID_VER(__DeviceID) == CHELSIO_T4 || \
+	 CHELSIO_PCI_ID_VER(__DeviceID) == CHELSIO_T4_FPGA \
+	 ? CHELSIO_T4 \
+	 : CHELSIO_T5)
+
+/*
+ * Internally we code the Chelsio T4 Family "Chip Code" as a tuple:
+ *
+ *     (Is FPGA, Chip Version, Chip Revision)
+ *
+ * where:
+ *
+ *     Is FPGA: is 0/1 indicating whether we're working with an FPGA
+ *     Chip Version: is T4, T5, etc.
+ *     Chip Revision: is the FAB "spin" of the Chip Version.
+ */
+#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
+#define CHELSIO_CHIP_FPGA          0x100
+#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
+#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
+
+enum chip_type {
+	T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
+	T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
+	T4_FIRST_REV	= T4_A1,
+	T4_LAST_REV	= T4_A2,
+
+	T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
+	T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
+	T5_FIRST_REV	= T5_A0,
+	T5_LAST_REV	= T5_A1,
+};
+
+static inline int is_t4(enum chip_type chip)
+{
+	return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4);
+}
+
+static inline int is_t5(enum chip_type chip)
+{
+
+	return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5);
+}
+
+static inline int is_fpga(enum chip_type chip)
+{
+	 return chip & CHELSIO_CHIP_FPGA;
+}
+
+#endif /* __T4_CHIP_TYPE_H__ */
diff --git a/contrib/ofed/libcxgb4/src/t4_pci_id_tbl.h b/contrib/ofed/libcxgb4/src/t4_pci_id_tbl.h
new file mode 100644
index 0000000..fbc2fd4
--- /dev/null
+++ b/contrib/ofed/libcxgb4/src/t4_pci_id_tbl.h
@@ -0,0 +1,175 @@
+/*
+ * This file is part of the Chelsio T4 Ethernet driver.
+ *
+ * Copyright (C) 2003-2014 Chelsio Communications.  All rights reserved.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the LICENSE file included in this
+ * release for licensing terms and conditions.
+ */
+#ifndef __T4_PCI_ID_TBL_H__
+#define __T4_PCI_ID_TBL_H__
+
+/*
+ * The Os-Dependent code can defined cpp macros for creating a PCI Device ID
+ * Table.  This is useful because it allows the PCI ID Table to be maintained
+ * in a single place and all supporting OSes to get new PCI Device IDs
+ * automatically.
+ *
+ * The macros are:
+ *
+ * CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN
+ *   -- Used to start the definition of the PCI ID Table.
+ *
+ * CH_PCI_DEVICE_ID_FUNCTION
+ *   -- The PCI Function Number to use in the PCI Device ID Table.  "0"
+ *   -- for drivers attaching to PF0-3, "4" for drivers attaching to PF4,
+ *   -- "8" for drivers attaching to SR-IOV Virtual Functions, etc.
+ *
+ * CH_PCI_DEVICE_ID_FUNCTION2 [optional]
+ *   -- If defined, create a PCI Device ID Table with both
+ *   -- CH_PCI_DEVICE_ID_FUNCTION and CH_PCI_DEVICE_ID_FUNCTION2 populated.
+ *
+ * CH_PCI_ID_TABLE_ENTRY(DeviceID)
+ *   -- Used for the individual PCI Device ID entries.  Note that we will
+ *   -- be adding a trailing comma (",") after all of the entries (and
+ *   -- between the pairs of entries if CH_PCI_DEVICE_ID_FUNCTION2 is defined).
+ *
+ * CH_PCI_DEVICE_ID_TABLE_DEFINE_END
+ *   -- Used to finish the definition of the PCI ID Table.  Note that we
+ *   -- will be adding a trailing semi-colon (";") here.
+ *
+ * CH_PCI_DEVICE_ID_BYPASS_SUPPORTED [optional]
+ *   -- If defined, indicates that the OS Driver has support for Bypass
+ *   -- Adapters.
+ */
+#ifdef CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN
+
+/*
+ * Some sanity checks ...
+ */
+#ifndef CH_PCI_DEVICE_ID_FUNCTION
+#error CH_PCI_DEVICE_ID_FUNCTION not defined!
+#endif
+#ifndef CH_PCI_ID_TABLE_ENTRY
+#error CH_PCI_ID_TABLE_ENTRY not defined!
+#endif
+#ifndef CH_PCI_DEVICE_ID_TABLE_DEFINE_END
+#error CH_PCI_DEVICE_ID_TABLE_DEFINE_END not defined!
+#endif
+
+/*
+ * T4 and later ASICs use a PCI Device ID scheme of 0xVFPP where:
+ *
+ *   V  = "4" for T4; "5" for T5, etc.
+ *   F  = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs
+ *   PP = adapter product designation
+ *
+ * We use this consistency in order to create the proper PCI Device IDs
+ * for the specified CH_PCI_DEVICE_ID_FUNCTION.
+ */
+#ifndef CH_PCI_DEVICE_ID_FUNCTION2
+#define CH_PCI_ID_TABLE_FENTRY(__DeviceID) \
+	CH_PCI_ID_TABLE_ENTRY((__DeviceID) | \
+			      ((CH_PCI_DEVICE_ID_FUNCTION) << 8))
+#else
+#define CH_PCI_ID_TABLE_FENTRY(__DeviceID) \
+	CH_PCI_ID_TABLE_ENTRY((__DeviceID) | \
+			      ((CH_PCI_DEVICE_ID_FUNCTION) << 8)), \
+	CH_PCI_ID_TABLE_ENTRY((__DeviceID) | \
+			      ((CH_PCI_DEVICE_ID_FUNCTION2) << 8))
+#endif
+
+/* Note : The comments against each entry are used by the scripts in the vmware drivers
+ * to correctly generate the pciid xml file, do not change the format currently used.
+ */
+
+CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN
+	/*
+	 * FPGAs:
+	 *
+	 * Unfortunately the FPGA PCI Device IDs don't follow the ASIC PCI
+	 * Device ID numbering convetions for the Physical Functions.
+	 */
+#if CH_PCI_DEVICE_ID_FUNCTION != 8
+	CH_PCI_ID_TABLE_ENTRY(0xa000),	/* PE10K FPGA */
+	CH_PCI_ID_TABLE_ENTRY(0xb000),	/* PF0 T5 PE10K5 FPGA */
+	CH_PCI_ID_TABLE_ENTRY(0xb001),	/* PF0 T5 PE10K FPGA */
+#else
+	CH_PCI_ID_TABLE_FENTRY(0xa000),	/* PE10K FPGA */
+	CH_PCI_ID_TABLE_FENTRY(0xb000),	/* PF0 T5 PE10K5 FPGA */
+	CH_PCI_ID_TABLE_FENTRY(0xb001),	/* PF0 T5 PE10K FPGA */
+#endif
+
+	/*
+	 *  These FPGAs seem to be used only by the csiostor driver
+	 */
+#if ((CH_PCI_DEVICE_ID_FUNCTION == 5) || (CH_PCI_DEVICE_ID_FUNCTION == 6))
+	CH_PCI_ID_TABLE_ENTRY(0xa001),	/* PF1 PE10K FPGA FCOE */
+	CH_PCI_ID_TABLE_ENTRY(0xa002),	/* PE10K FPGA iSCSI */
+#endif
+
+	/*
+	 * T4 adapters:
+	 */
+	CH_PCI_ID_TABLE_FENTRY(0x4000),	/* T440-dbg */
+	CH_PCI_ID_TABLE_FENTRY(0x4001),	/* T420-cr */
+	CH_PCI_ID_TABLE_FENTRY(0x4002),	/* T422-cr */
+	CH_PCI_ID_TABLE_FENTRY(0x4003),	/* T440-cr */
+	CH_PCI_ID_TABLE_FENTRY(0x4004),	/* T420-bch */
+	CH_PCI_ID_TABLE_FENTRY(0x4005),	/* T440-bch */
+	CH_PCI_ID_TABLE_FENTRY(0x4006),	/* T440-ch */
+	CH_PCI_ID_TABLE_FENTRY(0x4007),	/* T420-so */
+	CH_PCI_ID_TABLE_FENTRY(0x4008),	/* T420-cx */
+	CH_PCI_ID_TABLE_FENTRY(0x4009),	/* T420-bt */
+	CH_PCI_ID_TABLE_FENTRY(0x400a),	/* T404-bt */
+#ifdef CH_PCI_DEVICE_ID_BYPASS_SUPPORTED
+	CH_PCI_ID_TABLE_FENTRY(0x400b),	/* B420-sr */
+	CH_PCI_ID_TABLE_FENTRY(0x400c),	/* B404-bt */
+#endif
+	CH_PCI_ID_TABLE_FENTRY(0x400d),	/* T480-cr */
+	CH_PCI_ID_TABLE_FENTRY(0x400e),	/* T440-LP-cr */
+	CH_PCI_ID_TABLE_FENTRY(0x4080),	/* Custom T480-cr */
+	CH_PCI_ID_TABLE_FENTRY(0x4081),	/* Custom T440-cr */
+	CH_PCI_ID_TABLE_FENTRY(0x4082),	/* Custom T420-cr */
+	CH_PCI_ID_TABLE_FENTRY(0x4083),	/* Custom T420-xaui */
+	CH_PCI_ID_TABLE_FENTRY(0x4084),	/* Custom T440-cr */
+	CH_PCI_ID_TABLE_FENTRY(0x4085),	/* Custom T420-cr */
+	CH_PCI_ID_TABLE_FENTRY(0x4086),	/* Custom T440-bt */
+	CH_PCI_ID_TABLE_FENTRY(0x4087),	/* Custom T440-cr */
+	CH_PCI_ID_TABLE_FENTRY(0x4088),	/* Custom T440 2-xaui, 2-xfi */
+
+	/*
+	 * T5 adapters:
+	 */
+	CH_PCI_ID_TABLE_FENTRY(0x5000),	/* T580-dbg */
+	CH_PCI_ID_TABLE_FENTRY(0x5001),	/* T520-cr */
+	CH_PCI_ID_TABLE_FENTRY(0x5002),	/* T522-cr */
+	CH_PCI_ID_TABLE_FENTRY(0x5003),	/* T540-cr */
+	CH_PCI_ID_TABLE_FENTRY(0x5004),	/* T520-bch */
+	CH_PCI_ID_TABLE_FENTRY(0x5005),	/* T540-bch */
+	CH_PCI_ID_TABLE_FENTRY(0x5006),	/* T540-ch */
+	CH_PCI_ID_TABLE_FENTRY(0x5007),	/* T520-so */
+	CH_PCI_ID_TABLE_FENTRY(0x5008),	/* T520-cx */
+	CH_PCI_ID_TABLE_FENTRY(0x5009),	/* T520-bt */
+	CH_PCI_ID_TABLE_FENTRY(0x500a),	/* T504-bt */
+#ifdef CH_PCI_DEVICE_ID_BYPASS_SUPPORTED
+	CH_PCI_ID_TABLE_FENTRY(0x500b),	/* B520-sr */
+	CH_PCI_ID_TABLE_FENTRY(0x500c),	/* B504-bt */
+#endif
+	CH_PCI_ID_TABLE_FENTRY(0x500d),	/* T580-cr */
+	CH_PCI_ID_TABLE_FENTRY(0x500e),	/* T540-LP-cr */
+	CH_PCI_ID_TABLE_FENTRY(0x5010),	/* T580-LP-cr */
+	CH_PCI_ID_TABLE_FENTRY(0x5011),	/* T520-LL-cr */
+	CH_PCI_ID_TABLE_FENTRY(0x5012),	/* T560-cr */
+	CH_PCI_ID_TABLE_FENTRY(0x5013),	/* T580-chr */
+	CH_PCI_ID_TABLE_FENTRY(0x5014),	/* T580-so */
+	CH_PCI_ID_TABLE_FENTRY(0x5015),	/* T502-bt */
+	CH_PCI_ID_TABLE_FENTRY(0x5080),	/* Custom T540-cr */
+	CH_PCI_ID_TABLE_FENTRY(0x5081),	/* Custom T540-LL-cr */
+CH_PCI_DEVICE_ID_TABLE_DEFINE_END;
+
+#endif /* CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN */
+
+#endif /* __T4_PCI_ID_TBL_H__ */
diff --git a/contrib/ofed/libcxgb4/src/t4_regs.h b/contrib/ofed/libcxgb4/src/t4_regs.h
new file mode 100644
index 0000000..266f773
--- /dev/null
+++ b/contrib/ofed/libcxgb4/src/t4_regs.h
@@ -0,0 +1,42349 @@
+/* This file is automatically generated --- changes will be lost */
+
+#define MYPF_BASE 0x1b000
+#define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
+
+#define PF0_BASE 0x1e000
+#define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
+
+#define PF1_BASE 0x1e400
+#define PF1_REG(reg_addr) (PF1_BASE + (reg_addr))
+
+#define PF2_BASE 0x1e800
+#define PF2_REG(reg_addr) (PF2_BASE + (reg_addr))
+
+#define PF3_BASE 0x1ec00
+#define PF3_REG(reg_addr) (PF3_BASE + (reg_addr))
+
+#define PF4_BASE 0x1f000
+#define PF4_REG(reg_addr) (PF4_BASE + (reg_addr))
+
+#define PF5_BASE 0x1f400
+#define PF5_REG(reg_addr) (PF5_BASE + (reg_addr))
+
+#define PF6_BASE 0x1f800
+#define PF6_REG(reg_addr) (PF6_BASE + (reg_addr))
+
+#define PF7_BASE 0x1fc00
+#define PF7_REG(reg_addr) (PF7_BASE + (reg_addr))
+
+#define PF_STRIDE 0x400
+#define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
+#define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
+
+#define VF_SGE_BASE 0x0
+#define VF_SGE_REG(reg_addr) (VF_SGE_BASE + (reg_addr))
+
+#define VF_MPS_BASE 0x100
+#define VF_MPS_REG(reg_addr) (VF_MPS_BASE + (reg_addr))
+
+#define VF_PL_BASE 0x200
+#define VF_PL_REG(reg_addr) (VF_PL_BASE + (reg_addr))
+
+#define VF_MBDATA_BASE 0x240
+#define VF_MBDATA_REG(reg_addr) (VF_MBDATA_BASE + (reg_addr))
+
+#define VF_CIM_BASE 0x300
+#define VF_CIM_REG(reg_addr) (VF_CIM_BASE + (reg_addr))
+
+#define MYPORT_BASE 0x1c000
+#define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
+
+#define PORT0_BASE 0x20000
+#define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
+
+#define PORT1_BASE 0x22000
+#define PORT1_REG(reg_addr) (PORT1_BASE + (reg_addr))
+
+#define PORT2_BASE 0x24000
+#define PORT2_REG(reg_addr) (PORT2_BASE + (reg_addr))
+
+#define PORT3_BASE 0x26000
+#define PORT3_REG(reg_addr) (PORT3_BASE + (reg_addr))
+
+#define PORT_STRIDE 0x2000
+#define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
+#define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
+
+#define SGE_QUEUE_BASE_MAP_HIGH(idx) (A_SGE_QUEUE_BASE_MAP_HIGH + (idx) * 8)
+#define NUM_SGE_QUEUE_BASE_MAP_HIGH_INSTANCES 136
+
+#define SGE_QUEUE_BASE_MAP_LOW(idx) (A_SGE_QUEUE_BASE_MAP_LOW + (idx) * 8)
+#define NUM_SGE_QUEUE_BASE_MAP_LOW_INSTANCES 136
+
+#define PCIE_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
+#define NUM_PCIE_DMA_INSTANCES 4
+
+#define PCIE_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
+#define NUM_PCIE_CMD_INSTANCES 2
+
+#define PCIE_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
+#define NUM_PCIE_HMA_INSTANCES 1
+
+#define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
+#define NUM_PCIE_MEM_ACCESS_INSTANCES 8
+
+#define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
+#define NUM_PCIE_MAILBOX_INSTANCES 1
+
+#define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_PCIE_FW_INSTANCES 8
+
+#define PCIE_FUNC_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
+#define NUM_PCIE_FUNC_INSTANCES 256
+
+#define PCIE_FID(idx) (A_PCIE_FID + (idx) * 4)
+#define NUM_PCIE_FID_INSTANCES 2048
+
+#define PCIE_DMA_BUF_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
+#define NUM_PCIE_DMA_BUF_INSTANCES 4
+
+#define MC_DDR3PHYDATX8_REG(reg_addr, idx) ((reg_addr) + (idx) * 256)
+#define NUM_MC_DDR3PHYDATX8_INSTANCES 9
+
+#define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_MC_BIST_STATUS_INSTANCES 18
+
+#define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_EDC_BIST_STATUS_INSTANCES 18
+
+#define CIM_PF_MAILBOX_DATA(idx) (A_CIM_PF_MAILBOX_DATA + (idx) * 4)
+#define NUM_CIM_PF_MAILBOX_DATA_INSTANCES 16
+
+#define MPS_TRC_FILTER_MATCH_CTL_A(idx) (A_MPS_TRC_FILTER_MATCH_CTL_A + (idx) * 4)
+#define NUM_MPS_TRC_FILTER_MATCH_CTL_A_INSTANCES 4
+
+#define MPS_TRC_FILTER_MATCH_CTL_B(idx) (A_MPS_TRC_FILTER_MATCH_CTL_B + (idx) * 4)
+#define NUM_MPS_TRC_FILTER_MATCH_CTL_B_INSTANCES 4
+
+#define MPS_TRC_FILTER_RUNT_CTL(idx) (A_MPS_TRC_FILTER_RUNT_CTL + (idx) * 4)
+#define NUM_MPS_TRC_FILTER_RUNT_CTL_INSTANCES 4
+
+#define MPS_TRC_FILTER_DROP(idx) (A_MPS_TRC_FILTER_DROP + (idx) * 4)
+#define NUM_MPS_TRC_FILTER_DROP_INSTANCES 4
+
+#define MPS_TRC_FILTER0_MATCH(idx) (A_MPS_TRC_FILTER0_MATCH + (idx) * 4)
+#define NUM_MPS_TRC_FILTER0_MATCH_INSTANCES 28
+
+#define MPS_TRC_FILTER0_DONT_CARE(idx) (A_MPS_TRC_FILTER0_DONT_CARE + (idx) * 4)
+#define NUM_MPS_TRC_FILTER0_DONT_CARE_INSTANCES 28
+
+#define MPS_TRC_FILTER1_MATCH(idx) (A_MPS_TRC_FILTER1_MATCH + (idx) * 4)
+#define NUM_MPS_TRC_FILTER1_MATCH_INSTANCES 28
+
+#define MPS_TRC_FILTER1_DONT_CARE(idx) (A_MPS_TRC_FILTER1_DONT_CARE + (idx) * 4)
+#define NUM_MPS_TRC_FILTER1_DONT_CARE_INSTANCES 28
+
+#define MPS_TRC_FILTER2_MATCH(idx) (A_MPS_TRC_FILTER2_MATCH + (idx) * 4)
+#define NUM_MPS_TRC_FILTER2_MATCH_INSTANCES 28
+
+#define MPS_TRC_FILTER2_DONT_CARE(idx) (A_MPS_TRC_FILTER2_DONT_CARE + (idx) * 4)
+#define NUM_MPS_TRC_FILTER2_DONT_CARE_INSTANCES 28
+
+#define MPS_TRC_FILTER3_MATCH(idx) (A_MPS_TRC_FILTER3_MATCH + (idx) * 4)
+#define NUM_MPS_TRC_FILTER3_MATCH_INSTANCES 28
+
+#define MPS_TRC_FILTER3_DONT_CARE(idx) (A_MPS_TRC_FILTER3_DONT_CARE + (idx) * 4)
+#define NUM_MPS_TRC_FILTER3_DONT_CARE_INSTANCES 28
+
+#define MPS_PORT_CLS_HASH_SRAM(idx) (A_MPS_PORT_CLS_HASH_SRAM + (idx) * 4)
+#define NUM_MPS_PORT_CLS_HASH_SRAM_INSTANCES 65
+
+#define MPS_CLS_VLAN_TABLE(idx) (A_MPS_CLS_VLAN_TABLE + (idx) * 4)
+#define NUM_MPS_CLS_VLAN_TABLE_INSTANCES 9
+
+#define MPS_CLS_SRAM_L(idx) (A_MPS_CLS_SRAM_L + (idx) * 8)
+#define NUM_MPS_CLS_SRAM_L_INSTANCES 336
+
+#define MPS_CLS_SRAM_H(idx) (A_MPS_CLS_SRAM_H + (idx) * 8)
+#define NUM_MPS_CLS_SRAM_H_INSTANCES 336
+
+#define MPS_CLS_TCAM_Y_L(idx) (A_MPS_CLS_TCAM_Y_L + (idx) * 16)
+#define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512
+
+#define MPS_CLS_TCAM_Y_H(idx) (A_MPS_CLS_TCAM_Y_H + (idx) * 16)
+#define NUM_MPS_CLS_TCAM_Y_H_INSTANCES 512
+
+#define MPS_CLS_TCAM_X_L(idx) (A_MPS_CLS_TCAM_X_L + (idx) * 16)
+#define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512
+
+#define MPS_CLS_TCAM_X_H(idx) (A_MPS_CLS_TCAM_X_H + (idx) * 16)
+#define NUM_MPS_CLS_TCAM_X_H_INSTANCES 512
+
+#define PL_SEMAPHORE_LOCK(idx) (A_PL_SEMAPHORE_LOCK + (idx) * 4)
+#define NUM_PL_SEMAPHORE_LOCK_INSTANCES 8
+
+#define PL_VF_SLICE_L(idx) (A_PL_VF_SLICE_L + (idx) * 8)
+#define NUM_PL_VF_SLICE_L_INSTANCES 8
+
+#define PL_VF_SLICE_H(idx) (A_PL_VF_SLICE_H + (idx) * 8)
+#define NUM_PL_VF_SLICE_H_INSTANCES 8
+
+#define PL_FLR_VF_STATUS(idx) (A_PL_FLR_VF_STATUS + (idx) * 4)
+#define NUM_PL_FLR_VF_STATUS_INSTANCES 4
+
+#define PL_VFID_MAP(idx) (A_PL_VFID_MAP + (idx) * 4)
+#define NUM_PL_VFID_MAP_INSTANCES 256
+
+#define LE_DB_MASK_IPV4(idx) (A_LE_DB_MASK_IPV4 + (idx) * 4)
+#define NUM_LE_DB_MASK_IPV4_INSTANCES 17
+
+#define LE_DB_MASK_IPV6(idx) (A_LE_DB_MASK_IPV6 + (idx) * 4)
+#define NUM_LE_DB_MASK_IPV6_INSTANCES 17
+
+#define LE_DB_DBGI_REQ_DATA(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4)
+#define NUM_LE_DB_DBGI_REQ_DATA_INSTANCES 17
+
+#define LE_DB_DBGI_REQ_MASK(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4)
+#define NUM_LE_DB_DBGI_REQ_MASK_INSTANCES 17
+
+#define LE_DB_DBGI_RSP_DATA(idx) (A_LE_DB_DBGI_RSP_DATA + (idx) * 4)
+#define NUM_LE_DB_DBGI_RSP_DATA_INSTANCES 17
+
+#define LE_DB_ACTIVE_MASK_IPV4(idx) (A_LE_DB_ACTIVE_MASK_IPV4 + (idx) * 4)
+#define NUM_LE_DB_ACTIVE_MASK_IPV4_INSTANCES 17
+
+#define LE_DB_ACTIVE_MASK_IPV6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4)
+#define NUM_LE_DB_ACTIVE_MASK_IPV6_INSTANCES 17
+
+#define LE_HASH_MASK_GEN_IPV4(idx) (A_LE_HASH_MASK_GEN_IPV4 + (idx) * 4)
+#define NUM_LE_HASH_MASK_GEN_IPV4_INSTANCES 4
+
+#define LE_HASH_MASK_GEN_IPV6(idx) (A_LE_HASH_MASK_GEN_IPV6 + (idx) * 4)
+#define NUM_LE_HASH_MASK_GEN_IPV6_INSTANCES 12
+
+#define LE_HASH_MASK_CMP_IPV4(idx) (A_LE_HASH_MASK_CMP_IPV4 + (idx) * 4)
+#define NUM_LE_HASH_MASK_CMP_IPV4_INSTANCES 4
+
+#define LE_HASH_MASK_CMP_IPV6(idx) (A_LE_HASH_MASK_CMP_IPV6 + (idx) * 4)
+#define NUM_LE_HASH_MASK_CMP_IPV6_INSTANCES 12
+
+#define UP_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
+#define NUM_UP_TSCH_CHANNEL_INSTANCES 4
+
+#define CIM_CTL_MAILBOX_VF_STATUS(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4)
+#define NUM_CIM_CTL_MAILBOX_VF_STATUS_INSTANCES 4
+
+#define CIM_CTL_MAILBOX_VFN_CTL(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 16)
+#define NUM_CIM_CTL_MAILBOX_VFN_CTL_INSTANCES 128
+
+#define CIM_CTL_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 288)
+#define NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES 4
+
+#define CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
+#define NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES 16
+
+#define T5_MYPORT_BASE 0x2c000
+#define T5_MYPORT_REG(reg_addr) (T5_MYPORT_BASE + (reg_addr))
+
+#define T5_PORT0_BASE 0x30000
+#define T5_PORT0_REG(reg_addr) (T5_PORT0_BASE + (reg_addr))
+
+#define T5_PORT1_BASE 0x34000
+#define T5_PORT1_REG(reg_addr) (T5_PORT1_BASE + (reg_addr))
+
+#define T5_PORT2_BASE 0x38000
+#define T5_PORT2_REG(reg_addr) (T5_PORT2_BASE + (reg_addr))
+
+#define T5_PORT3_BASE 0x3c000
+#define T5_PORT3_REG(reg_addr) (T5_PORT3_BASE + (reg_addr))
+
+#define T5_PORT_STRIDE 0x4000
+#define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
+#define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
+
+#define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
+#define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
+
+#define PCIE_PF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
+#define NUM_PCIE_PF_INT_INSTANCES 8
+
+#define PCIE_VF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
+#define NUM_PCIE_VF_INT_INSTANCES 128
+
+#define PCIE_FID_VFID(idx) (A_PCIE_FID_VFID + (idx) * 4)
+#define NUM_PCIE_FID_VFID_INSTANCES 2048
+
+#define PCIE_COOKIE_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_PCIE_COOKIE_INSTANCES 8
+
+#define PCIE_T5_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
+#define NUM_PCIE_T5_DMA_INSTANCES 4
+
+#define PCIE_T5_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
+#define NUM_PCIE_T5_CMD_INSTANCES 3
+
+#define PCIE_T5_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
+#define NUM_PCIE_T5_HMA_INSTANCES 1
+
+#define PCIE_PHY_PRESET_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_PCIE_PHY_PRESET_INSTANCES 11
+
+#define MPS_T5_CLS_SRAM_L(idx) (A_MPS_T5_CLS_SRAM_L + (idx) * 8)
+#define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
+
+#define MPS_T5_CLS_SRAM_H(idx) (A_MPS_T5_CLS_SRAM_H + (idx) * 8)
+#define NUM_MPS_T5_CLS_SRAM_H_INSTANCES 512
+
+#define LE_T5_DB_MASK_IPV4(idx) (A_LE_T5_DB_MASK_IPV4 + (idx) * 4)
+#define NUM_LE_T5_DB_MASK_IPV4_INSTANCES 5
+
+#define LE_T5_DB_ACTIVE_MASK_IPV4(idx) (A_LE_T5_DB_ACTIVE_MASK_IPV4 + (idx) * 4)
+#define NUM_LE_T5_DB_ACTIVE_MASK_IPV4_INSTANCES 5
+
+#define LE_HASH_MASK_GEN_IPV4T5(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4)
+#define NUM_LE_HASH_MASK_GEN_IPV4T5_INSTANCES 5
+
+#define LE_HASH_MASK_GEN_IPV6T5(idx) (A_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4)
+#define NUM_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 12
+
+#define LE_HASH_MASK_CMP_IPV4T5(idx) (A_LE_HASH_MASK_CMP_IPV4T5 + (idx) * 4)
+#define NUM_LE_HASH_MASK_CMP_IPV4T5_INSTANCES 5
+
+#define LE_HASH_MASK_CMP_IPV6T5(idx) (A_LE_HASH_MASK_CMP_IPV6T5 + (idx) * 4)
+#define NUM_LE_HASH_MASK_CMP_IPV6T5_INSTANCES 12
+
+#define LE_DB_SECOND_ACTIVE_MASK_IPV4(idx) (A_LE_DB_SECOND_ACTIVE_MASK_IPV4 + (idx) * 4)
+#define NUM_LE_DB_SECOND_ACTIVE_MASK_IPV4_INSTANCES 5
+
+#define LE_DB_SECOND_GEN_HASH_MASK_IPV4(idx) (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4)
+#define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_INSTANCES 5
+
+#define LE_DB_SECOND_CMP_HASH_MASK_IPV4(idx) (A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 + (idx) * 4)
+#define NUM_LE_DB_SECOND_CMP_HASH_MASK_IPV4_INSTANCES 5
+
+#define MC_ADR_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
+#define NUM_MC_ADR_INSTANCES 2
+
+#define MC_DDRPHY_DP18_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
+#define NUM_MC_DDRPHY_DP18_INSTANCES 5
+
+#define MC_CE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_MC_CE_ERR_DATA_INSTANCES 8
+
+#define MC_CE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_MC_CE_COR_DATA_INSTANCES 8
+
+#define MC_UE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_MC_UE_ERR_DATA_INSTANCES 8
+
+#define MC_UE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_MC_UE_COR_DATA_INSTANCES 8
+
+#define MC_P_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_MC_P_BIST_STATUS_INSTANCES 18
+
+#define EDC_H_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_EDC_H_BIST_STATUS_INSTANCES 18
+
+#define EDC_H_ECC_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
+#define NUM_EDC_H_ECC_ERR_DATA_INSTANCES 16
+
+#define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
+#define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
+
+/* registers for module SGE */
+#define SGE_BASE_ADDR 0x1000
+
+#define A_SGE_PF_KDOORBELL 0x0
+
+#define S_QID    15
+#define M_QID    0x1ffffU
+#define V_QID(x) ((x) << S_QID)
+#define G_QID(x) (((x) >> S_QID) & M_QID)
+
+#define S_DBPRIO    14
+#define V_DBPRIO(x) ((x) << S_DBPRIO)
+#define F_DBPRIO    V_DBPRIO(1U)
+
+#define S_PIDX    0
+#define M_PIDX    0x3fffU
+#define V_PIDX(x) ((x) << S_PIDX)
+#define G_PIDX(x) (((x) >> S_PIDX) & M_PIDX)
+
+#define A_SGE_VF_KDOORBELL 0x0
+
+#define S_DBTYPE    13
+#define V_DBTYPE(x) ((x) << S_DBTYPE)
+#define F_DBTYPE    V_DBTYPE(1U)
+
+#define S_PIDX_T5    0
+#define M_PIDX_T5    0x1fffU
+#define V_PIDX_T5(x) ((x) << S_PIDX_T5)
+#define G_PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5)
+
+#define A_SGE_PF_GTS 0x4
+
+#define S_INGRESSQID    16
+#define M_INGRESSQID    0xffffU
+#define V_INGRESSQID(x) ((x) << S_INGRESSQID)
+#define G_INGRESSQID(x) (((x) >> S_INGRESSQID) & M_INGRESSQID)
+
+#define S_TIMERREG    13
+#define M_TIMERREG    0x7U
+#define V_TIMERREG(x) ((x) << S_TIMERREG)
+#define G_TIMERREG(x) (((x) >> S_TIMERREG) & M_TIMERREG)
+
+#define S_SEINTARM    12
+#define V_SEINTARM(x) ((x) << S_SEINTARM)
+#define F_SEINTARM    V_SEINTARM(1U)
+
+#define S_CIDXINC    0
+#define M_CIDXINC    0xfffU
+#define V_CIDXINC(x) ((x) << S_CIDXINC)
+#define G_CIDXINC(x) (((x) >> S_CIDXINC) & M_CIDXINC)
+
+#define A_SGE_VF_GTS 0x4
+#define A_SGE_PF_KTIMESTAMP_LO 0x8
+#define A_SGE_VF_KTIMESTAMP_LO 0x8
+#define A_SGE_PF_KTIMESTAMP_HI 0xc
+
+#define S_TSTAMPVAL    0
+#define M_TSTAMPVAL    0xfffffffU
+#define V_TSTAMPVAL(x) ((x) << S_TSTAMPVAL)
+#define G_TSTAMPVAL(x) (((x) >> S_TSTAMPVAL) & M_TSTAMPVAL)
+
+#define A_SGE_VF_KTIMESTAMP_HI 0xc
+#define A_SGE_CONTROL 0x1008
+
+#define S_IGRALLCPLTOFL    31
+#define V_IGRALLCPLTOFL(x) ((x) << S_IGRALLCPLTOFL)
+#define F_IGRALLCPLTOFL    V_IGRALLCPLTOFL(1U)
+
+#define S_FLSPLITMIN    22
+#define M_FLSPLITMIN    0x1ffU
+#define V_FLSPLITMIN(x) ((x) << S_FLSPLITMIN)
+#define G_FLSPLITMIN(x) (((x) >> S_FLSPLITMIN) & M_FLSPLITMIN)
+
+#define S_FLSPLITMODE    20
+#define M_FLSPLITMODE    0x3U
+#define V_FLSPLITMODE(x) ((x) << S_FLSPLITMODE)
+#define G_FLSPLITMODE(x) (((x) >> S_FLSPLITMODE) & M_FLSPLITMODE)
+
+#define S_DCASYSTYPE    19
+#define V_DCASYSTYPE(x) ((x) << S_DCASYSTYPE)
+#define F_DCASYSTYPE    V_DCASYSTYPE(1U)
+
+#define S_RXPKTCPLMODE    18
+#define V_RXPKTCPLMODE(x) ((x) << S_RXPKTCPLMODE)
+#define F_RXPKTCPLMODE    V_RXPKTCPLMODE(1U)
+
+#define S_EGRSTATUSPAGESIZE    17
+#define V_EGRSTATUSPAGESIZE(x) ((x) << S_EGRSTATUSPAGESIZE)
+#define F_EGRSTATUSPAGESIZE    V_EGRSTATUSPAGESIZE(1U)
+
+#define S_INGHINTENABLE1    15
+#define V_INGHINTENABLE1(x) ((x) << S_INGHINTENABLE1)
+#define F_INGHINTENABLE1    V_INGHINTENABLE1(1U)
+
+#define S_INGHINTENABLE0    14
+#define V_INGHINTENABLE0(x) ((x) << S_INGHINTENABLE0)
+#define F_INGHINTENABLE0    V_INGHINTENABLE0(1U)
+
+#define S_INGINTCOMPAREIDX    13
+#define V_INGINTCOMPAREIDX(x) ((x) << S_INGINTCOMPAREIDX)
+#define F_INGINTCOMPAREIDX    V_INGINTCOMPAREIDX(1U)
+
+#define S_PKTSHIFT    10
+#define M_PKTSHIFT    0x7U
+#define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)
+#define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT)
+
+#define S_INGPCIEBOUNDARY    7
+#define M_INGPCIEBOUNDARY    0x7U
+#define V_INGPCIEBOUNDARY(x) ((x) << S_INGPCIEBOUNDARY)
+#define G_INGPCIEBOUNDARY(x) (((x) >> S_INGPCIEBOUNDARY) & M_INGPCIEBOUNDARY)
+
+#define S_INGPADBOUNDARY    4
+#define M_INGPADBOUNDARY    0x7U
+#define V_INGPADBOUNDARY(x) ((x) << S_INGPADBOUNDARY)
+#define G_INGPADBOUNDARY(x) (((x) >> S_INGPADBOUNDARY) & M_INGPADBOUNDARY)
+
+#define S_EGRPCIEBOUNDARY    1
+#define M_EGRPCIEBOUNDARY    0x7U
+#define V_EGRPCIEBOUNDARY(x) ((x) << S_EGRPCIEBOUNDARY)
+#define G_EGRPCIEBOUNDARY(x) (((x) >> S_EGRPCIEBOUNDARY) & M_EGRPCIEBOUNDARY)
+
+#define S_GLOBALENABLE    0
+#define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE)
+#define F_GLOBALENABLE    V_GLOBALENABLE(1U)
+
+#define A_SGE_HOST_PAGE_SIZE 0x100c
+
+#define S_HOSTPAGESIZEPF7    28
+#define M_HOSTPAGESIZEPF7    0xfU
+#define V_HOSTPAGESIZEPF7(x) ((x) << S_HOSTPAGESIZEPF7)
+#define G_HOSTPAGESIZEPF7(x) (((x) >> S_HOSTPAGESIZEPF7) & M_HOSTPAGESIZEPF7)
+
+#define S_HOSTPAGESIZEPF6    24
+#define M_HOSTPAGESIZEPF6    0xfU
+#define V_HOSTPAGESIZEPF6(x) ((x) << S_HOSTPAGESIZEPF6)
+#define G_HOSTPAGESIZEPF6(x) (((x) >> S_HOSTPAGESIZEPF6) & M_HOSTPAGESIZEPF6)
+
+#define S_HOSTPAGESIZEPF5    20
+#define M_HOSTPAGESIZEPF5    0xfU
+#define V_HOSTPAGESIZEPF5(x) ((x) << S_HOSTPAGESIZEPF5)
+#define G_HOSTPAGESIZEPF5(x) (((x) >> S_HOSTPAGESIZEPF5) & M_HOSTPAGESIZEPF5)
+
+#define S_HOSTPAGESIZEPF4    16
+#define M_HOSTPAGESIZEPF4    0xfU
+#define V_HOSTPAGESIZEPF4(x) ((x) << S_HOSTPAGESIZEPF4)
+#define G_HOSTPAGESIZEPF4(x) (((x) >> S_HOSTPAGESIZEPF4) & M_HOSTPAGESIZEPF4)
+
+#define S_HOSTPAGESIZEPF3    12
+#define M_HOSTPAGESIZEPF3    0xfU
+#define V_HOSTPAGESIZEPF3(x) ((x) << S_HOSTPAGESIZEPF3)
+#define G_HOSTPAGESIZEPF3(x) (((x) >> S_HOSTPAGESIZEPF3) & M_HOSTPAGESIZEPF3)
+
+#define S_HOSTPAGESIZEPF2    8
+#define M_HOSTPAGESIZEPF2    0xfU
+#define V_HOSTPAGESIZEPF2(x) ((x) << S_HOSTPAGESIZEPF2)
+#define G_HOSTPAGESIZEPF2(x) (((x) >> S_HOSTPAGESIZEPF2) & M_HOSTPAGESIZEPF2)
+
+#define S_HOSTPAGESIZEPF1    4
+#define M_HOSTPAGESIZEPF1    0xfU
+#define V_HOSTPAGESIZEPF1(x) ((x) << S_HOSTPAGESIZEPF1)
+#define G_HOSTPAGESIZEPF1(x) (((x) >> S_HOSTPAGESIZEPF1) & M_HOSTPAGESIZEPF1)
+
+#define S_HOSTPAGESIZEPF0    0
+#define M_HOSTPAGESIZEPF0    0xfU
+#define V_HOSTPAGESIZEPF0(x) ((x) << S_HOSTPAGESIZEPF0)
+#define G_HOSTPAGESIZEPF0(x) (((x) >> S_HOSTPAGESIZEPF0) & M_HOSTPAGESIZEPF0)
+
+#define A_SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010
+
+#define S_QUEUESPERPAGEPF7    28
+#define M_QUEUESPERPAGEPF7    0xfU
+#define V_QUEUESPERPAGEPF7(x) ((x) << S_QUEUESPERPAGEPF7)
+#define G_QUEUESPERPAGEPF7(x) (((x) >> S_QUEUESPERPAGEPF7) & M_QUEUESPERPAGEPF7)
+
+#define S_QUEUESPERPAGEPF6    24
+#define M_QUEUESPERPAGEPF6    0xfU
+#define V_QUEUESPERPAGEPF6(x) ((x) << S_QUEUESPERPAGEPF6)
+#define G_QUEUESPERPAGEPF6(x) (((x) >> S_QUEUESPERPAGEPF6) & M_QUEUESPERPAGEPF6)
+
+#define S_QUEUESPERPAGEPF5    20
+#define M_QUEUESPERPAGEPF5    0xfU
+#define V_QUEUESPERPAGEPF5(x) ((x) << S_QUEUESPERPAGEPF5)
+#define G_QUEUESPERPAGEPF5(x) (((x) >> S_QUEUESPERPAGEPF5) & M_QUEUESPERPAGEPF5)
+
+#define S_QUEUESPERPAGEPF4    16
+#define M_QUEUESPERPAGEPF4    0xfU
+#define V_QUEUESPERPAGEPF4(x) ((x) << S_QUEUESPERPAGEPF4)
+#define G_QUEUESPERPAGEPF4(x) (((x) >> S_QUEUESPERPAGEPF4) & M_QUEUESPERPAGEPF4)
+
+#define S_QUEUESPERPAGEPF3    12
+#define M_QUEUESPERPAGEPF3    0xfU
+#define V_QUEUESPERPAGEPF3(x) ((x) << S_QUEUESPERPAGEPF3)
+#define G_QUEUESPERPAGEPF3(x) (((x) >> S_QUEUESPERPAGEPF3) & M_QUEUESPERPAGEPF3)
+
+#define S_QUEUESPERPAGEPF2    8
+#define M_QUEUESPERPAGEPF2    0xfU
+#define V_QUEUESPERPAGEPF2(x) ((x) << S_QUEUESPERPAGEPF2)
+#define G_QUEUESPERPAGEPF2(x) (((x) >> S_QUEUESPERPAGEPF2) & M_QUEUESPERPAGEPF2)
+
+#define S_QUEUESPERPAGEPF1    4
+#define M_QUEUESPERPAGEPF1    0xfU
+#define V_QUEUESPERPAGEPF1(x) ((x) << S_QUEUESPERPAGEPF1)
+#define G_QUEUESPERPAGEPF1(x) (((x) >> S_QUEUESPERPAGEPF1) & M_QUEUESPERPAGEPF1)
+
+#define S_QUEUESPERPAGEPF0    0
+#define M_QUEUESPERPAGEPF0    0xfU
+#define V_QUEUESPERPAGEPF0(x) ((x) << S_QUEUESPERPAGEPF0)
+#define G_QUEUESPERPAGEPF0(x) (((x) >> S_QUEUESPERPAGEPF0) & M_QUEUESPERPAGEPF0)
+
+#define A_SGE_EGRESS_QUEUES_PER_PAGE_VF 0x1014
+
+#define S_QUEUESPERPAGEVFPF7    28
+#define M_QUEUESPERPAGEVFPF7    0xfU
+#define V_QUEUESPERPAGEVFPF7(x) ((x) << S_QUEUESPERPAGEVFPF7)
+#define G_QUEUESPERPAGEVFPF7(x) (((x) >> S_QUEUESPERPAGEVFPF7) & M_QUEUESPERPAGEVFPF7)
+
+#define S_QUEUESPERPAGEVFPF6    24
+#define M_QUEUESPERPAGEVFPF6    0xfU
+#define V_QUEUESPERPAGEVFPF6(x) ((x) << S_QUEUESPERPAGEVFPF6)
+#define G_QUEUESPERPAGEVFPF6(x) (((x) >> S_QUEUESPERPAGEVFPF6) & M_QUEUESPERPAGEVFPF6)
+
+#define S_QUEUESPERPAGEVFPF5    20
+#define M_QUEUESPERPAGEVFPF5    0xfU
+#define V_QUEUESPERPAGEVFPF5(x) ((x) << S_QUEUESPERPAGEVFPF5)
+#define G_QUEUESPERPAGEVFPF5(x) (((x) >> S_QUEUESPERPAGEVFPF5) & M_QUEUESPERPAGEVFPF5)
+
+#define S_QUEUESPERPAGEVFPF4    16
+#define M_QUEUESPERPAGEVFPF4    0xfU
+#define V_QUEUESPERPAGEVFPF4(x) ((x) << S_QUEUESPERPAGEVFPF4)
+#define G_QUEUESPERPAGEVFPF4(x) (((x) >> S_QUEUESPERPAGEVFPF4) & M_QUEUESPERPAGEVFPF4)
+
+#define S_QUEUESPERPAGEVFPF3    12
+#define M_QUEUESPERPAGEVFPF3    0xfU
+#define V_QUEUESPERPAGEVFPF3(x) ((x) << S_QUEUESPERPAGEVFPF3)
+#define G_QUEUESPERPAGEVFPF3(x) (((x) >> S_QUEUESPERPAGEVFPF3) & M_QUEUESPERPAGEVFPF3)
+
+#define S_QUEUESPERPAGEVFPF2    8
+#define M_QUEUESPERPAGEVFPF2    0xfU
+#define V_QUEUESPERPAGEVFPF2(x) ((x) << S_QUEUESPERPAGEVFPF2)
+#define G_QUEUESPERPAGEVFPF2(x) (((x) >> S_QUEUESPERPAGEVFPF2) & M_QUEUESPERPAGEVFPF2)
+
+#define S_QUEUESPERPAGEVFPF1    4
+#define M_QUEUESPERPAGEVFPF1    0xfU
+#define V_QUEUESPERPAGEVFPF1(x) ((x) << S_QUEUESPERPAGEVFPF1)
+#define G_QUEUESPERPAGEVFPF1(x) (((x) >> S_QUEUESPERPAGEVFPF1) & M_QUEUESPERPAGEVFPF1)
+
+#define S_QUEUESPERPAGEVFPF0    0
+#define M_QUEUESPERPAGEVFPF0    0xfU
+#define V_QUEUESPERPAGEVFPF0(x) ((x) << S_QUEUESPERPAGEVFPF0)
+#define G_QUEUESPERPAGEVFPF0(x) (((x) >> S_QUEUESPERPAGEVFPF0) & M_QUEUESPERPAGEVFPF0)
+
+#define A_SGE_USER_MODE_LIMITS 0x1018
+
+#define S_OPCODE_MIN    24
+#define M_OPCODE_MIN    0xffU
+#define V_OPCODE_MIN(x) ((x) << S_OPCODE_MIN)
+#define G_OPCODE_MIN(x) (((x) >> S_OPCODE_MIN) & M_OPCODE_MIN)
+
+#define S_OPCODE_MAX    16
+#define M_OPCODE_MAX    0xffU
+#define V_OPCODE_MAX(x) ((x) << S_OPCODE_MAX)
+#define G_OPCODE_MAX(x) (((x) >> S_OPCODE_MAX) & M_OPCODE_MAX)
+
+#define S_LENGTH_MIN    8
+#define M_LENGTH_MIN    0xffU
+#define V_LENGTH_MIN(x) ((x) << S_LENGTH_MIN)
+#define G_LENGTH_MIN(x) (((x) >> S_LENGTH_MIN) & M_LENGTH_MIN)
+
+#define S_LENGTH_MAX    0
+#define M_LENGTH_MAX    0xffU
+#define V_LENGTH_MAX(x) ((x) << S_LENGTH_MAX)
+#define G_LENGTH_MAX(x) (((x) >> S_LENGTH_MAX) & M_LENGTH_MAX)
+
+#define A_SGE_WR_ERROR 0x101c
+
+#define S_WR_ERROR_OPCODE    0
+#define M_WR_ERROR_OPCODE    0xffU
+#define V_WR_ERROR_OPCODE(x) ((x) << S_WR_ERROR_OPCODE)
+#define G_WR_ERROR_OPCODE(x) (((x) >> S_WR_ERROR_OPCODE) & M_WR_ERROR_OPCODE)
+
+#define A_SGE_PERR_INJECT 0x1020
+
+#define S_MEMSEL    1
+#define M_MEMSEL    0x1fU
+#define V_MEMSEL(x) ((x) << S_MEMSEL)
+#define G_MEMSEL(x) (((x) >> S_MEMSEL) & M_MEMSEL)
+
+#define S_INJECTDATAERR    0
+#define V_INJECTDATAERR(x) ((x) << S_INJECTDATAERR)
+#define F_INJECTDATAERR    V_INJECTDATAERR(1U)
+
+#define A_SGE_INT_CAUSE1 0x1024
+
+#define S_PERR_FLM_CREDITFIFO    30
+#define V_PERR_FLM_CREDITFIFO(x) ((x) << S_PERR_FLM_CREDITFIFO)
+#define F_PERR_FLM_CREDITFIFO    V_PERR_FLM_CREDITFIFO(1U)
+
+#define S_PERR_IMSG_HINT_FIFO    29
+#define V_PERR_IMSG_HINT_FIFO(x) ((x) << S_PERR_IMSG_HINT_FIFO)
+#define F_PERR_IMSG_HINT_FIFO    V_PERR_IMSG_HINT_FIFO(1U)
+
+#define S_PERR_MC_PC    28
+#define V_PERR_MC_PC(x) ((x) << S_PERR_MC_PC)
+#define F_PERR_MC_PC    V_PERR_MC_PC(1U)
+
+#define S_PERR_MC_IGR_CTXT    27
+#define V_PERR_MC_IGR_CTXT(x) ((x) << S_PERR_MC_IGR_CTXT)
+#define F_PERR_MC_IGR_CTXT    V_PERR_MC_IGR_CTXT(1U)
+
+#define S_PERR_MC_EGR_CTXT    26
+#define V_PERR_MC_EGR_CTXT(x) ((x) << S_PERR_MC_EGR_CTXT)
+#define F_PERR_MC_EGR_CTXT    V_PERR_MC_EGR_CTXT(1U)
+
+#define S_PERR_MC_FLM    25
+#define V_PERR_MC_FLM(x) ((x) << S_PERR_MC_FLM)
+#define F_PERR_MC_FLM    V_PERR_MC_FLM(1U)
+
+#define S_PERR_PC_MCTAG    24
+#define V_PERR_PC_MCTAG(x) ((x) << S_PERR_PC_MCTAG)
+#define F_PERR_PC_MCTAG    V_PERR_PC_MCTAG(1U)
+
+#define S_PERR_PC_CHPI_RSP1    23
+#define V_PERR_PC_CHPI_RSP1(x) ((x) << S_PERR_PC_CHPI_RSP1)
+#define F_PERR_PC_CHPI_RSP1    V_PERR_PC_CHPI_RSP1(1U)
+
+#define S_PERR_PC_CHPI_RSP0    22
+#define V_PERR_PC_CHPI_RSP0(x) ((x) << S_PERR_PC_CHPI_RSP0)
+#define F_PERR_PC_CHPI_RSP0    V_PERR_PC_CHPI_RSP0(1U)
+
+#define S_PERR_DBP_PC_RSP_FIFO3    21
+#define V_PERR_DBP_PC_RSP_FIFO3(x) ((x) << S_PERR_DBP_PC_RSP_FIFO3)
+#define F_PERR_DBP_PC_RSP_FIFO3    V_PERR_DBP_PC_RSP_FIFO3(1U)
+
+#define S_PERR_DBP_PC_RSP_FIFO2    20
+#define V_PERR_DBP_PC_RSP_FIFO2(x) ((x) << S_PERR_DBP_PC_RSP_FIFO2)
+#define F_PERR_DBP_PC_RSP_FIFO2    V_PERR_DBP_PC_RSP_FIFO2(1U)
+
+#define S_PERR_DBP_PC_RSP_FIFO1    19
+#define V_PERR_DBP_PC_RSP_FIFO1(x) ((x) << S_PERR_DBP_PC_RSP_FIFO1)
+#define F_PERR_DBP_PC_RSP_FIFO1    V_PERR_DBP_PC_RSP_FIFO1(1U)
+
+#define S_PERR_DBP_PC_RSP_FIFO0    18
+#define V_PERR_DBP_PC_RSP_FIFO0(x) ((x) << S_PERR_DBP_PC_RSP_FIFO0)
+#define F_PERR_DBP_PC_RSP_FIFO0    V_PERR_DBP_PC_RSP_FIFO0(1U)
+
+#define S_PERR_DMARBT    17
+#define V_PERR_DMARBT(x) ((x) << S_PERR_DMARBT)
+#define F_PERR_DMARBT    V_PERR_DMARBT(1U)
+
+#define S_PERR_FLM_DBPFIFO    16
+#define V_PERR_FLM_DBPFIFO(x) ((x) << S_PERR_FLM_DBPFIFO)
+#define F_PERR_FLM_DBPFIFO    V_PERR_FLM_DBPFIFO(1U)
+
+#define S_PERR_FLM_MCREQ_FIFO    15
+#define V_PERR_FLM_MCREQ_FIFO(x) ((x) << S_PERR_FLM_MCREQ_FIFO)
+#define F_PERR_FLM_MCREQ_FIFO    V_PERR_FLM_MCREQ_FIFO(1U)
+
+#define S_PERR_FLM_HINTFIFO    14
+#define V_PERR_FLM_HINTFIFO(x) ((x) << S_PERR_FLM_HINTFIFO)
+#define F_PERR_FLM_HINTFIFO    V_PERR_FLM_HINTFIFO(1U)
+
+#define S_PERR_ALIGN_CTL_FIFO3    13
+#define V_PERR_ALIGN_CTL_FIFO3(x) ((x) << S_PERR_ALIGN_CTL_FIFO3)
+#define F_PERR_ALIGN_CTL_FIFO3    V_PERR_ALIGN_CTL_FIFO3(1U)
+
+#define S_PERR_ALIGN_CTL_FIFO2    12
+#define V_PERR_ALIGN_CTL_FIFO2(x) ((x) << S_PERR_ALIGN_CTL_FIFO2)
+#define F_PERR_ALIGN_CTL_FIFO2    V_PERR_ALIGN_CTL_FIFO2(1U)
+
+#define S_PERR_ALIGN_CTL_FIFO1    11
+#define V_PERR_ALIGN_CTL_FIFO1(x) ((x) << S_PERR_ALIGN_CTL_FIFO1)
+#define F_PERR_ALIGN_CTL_FIFO1    V_PERR_ALIGN_CTL_FIFO1(1U)
+
+#define S_PERR_ALIGN_CTL_FIFO0    10
+#define V_PERR_ALIGN_CTL_FIFO0(x) ((x) << S_PERR_ALIGN_CTL_FIFO0)
+#define F_PERR_ALIGN_CTL_FIFO0    V_PERR_ALIGN_CTL_FIFO0(1U)
+
+#define S_PERR_EDMA_FIFO3    9
+#define V_PERR_EDMA_FIFO3(x) ((x) << S_PERR_EDMA_FIFO3)
+#define F_PERR_EDMA_FIFO3    V_PERR_EDMA_FIFO3(1U)
+
+#define S_PERR_EDMA_FIFO2    8
+#define V_PERR_EDMA_FIFO2(x) ((x) << S_PERR_EDMA_FIFO2)
+#define F_PERR_EDMA_FIFO2    V_PERR_EDMA_FIFO2(1U)
+
+#define S_PERR_EDMA_FIFO1    7
+#define V_PERR_EDMA_FIFO1(x) ((x) << S_PERR_EDMA_FIFO1)
+#define F_PERR_EDMA_FIFO1    V_PERR_EDMA_FIFO1(1U)
+
+#define S_PERR_EDMA_FIFO0    6
+#define V_PERR_EDMA_FIFO0(x) ((x) << S_PERR_EDMA_FIFO0)
+#define F_PERR_EDMA_FIFO0    V_PERR_EDMA_FIFO0(1U)
+
+#define S_PERR_PD_FIFO3    5
+#define V_PERR_PD_FIFO3(x) ((x) << S_PERR_PD_FIFO3)
+#define F_PERR_PD_FIFO3    V_PERR_PD_FIFO3(1U)
+
+#define S_PERR_PD_FIFO2    4
+#define V_PERR_PD_FIFO2(x) ((x) << S_PERR_PD_FIFO2)
+#define F_PERR_PD_FIFO2    V_PERR_PD_FIFO2(1U)
+
+#define S_PERR_PD_FIFO1    3
+#define V_PERR_PD_FIFO1(x) ((x) << S_PERR_PD_FIFO1)
+#define F_PERR_PD_FIFO1    V_PERR_PD_FIFO1(1U)
+
+#define S_PERR_PD_FIFO0    2
+#define V_PERR_PD_FIFO0(x) ((x) << S_PERR_PD_FIFO0)
+#define F_PERR_PD_FIFO0    V_PERR_PD_FIFO0(1U)
+
+#define S_PERR_ING_CTXT_MIFRSP    1
+#define V_PERR_ING_CTXT_MIFRSP(x) ((x) << S_PERR_ING_CTXT_MIFRSP)
+#define F_PERR_ING_CTXT_MIFRSP    V_PERR_ING_CTXT_MIFRSP(1U)
+
+#define S_PERR_EGR_CTXT_MIFRSP    0
+#define V_PERR_EGR_CTXT_MIFRSP(x) ((x) << S_PERR_EGR_CTXT_MIFRSP)
+#define F_PERR_EGR_CTXT_MIFRSP    V_PERR_EGR_CTXT_MIFRSP(1U)
+
+#define S_PERR_PC_CHPI_RSP2    31
+#define V_PERR_PC_CHPI_RSP2(x) ((x) << S_PERR_PC_CHPI_RSP2)
+#define F_PERR_PC_CHPI_RSP2    V_PERR_PC_CHPI_RSP2(1U)
+
+#define A_SGE_INT_ENABLE1 0x1028
+#define A_SGE_PERR_ENABLE1 0x102c
+#define A_SGE_INT_CAUSE2 0x1030
+
+#define S_PERR_HINT_DELAY_FIFO1    30
+#define V_PERR_HINT_DELAY_FIFO1(x) ((x) << S_PERR_HINT_DELAY_FIFO1)
+#define F_PERR_HINT_DELAY_FIFO1    V_PERR_HINT_DELAY_FIFO1(1U)
+
+#define S_PERR_HINT_DELAY_FIFO0    29
+#define V_PERR_HINT_DELAY_FIFO0(x) ((x) << S_PERR_HINT_DELAY_FIFO0)
+#define F_PERR_HINT_DELAY_FIFO0    V_PERR_HINT_DELAY_FIFO0(1U)
+
+#define S_PERR_IMSG_PD_FIFO    28
+#define V_PERR_IMSG_PD_FIFO(x) ((x) << S_PERR_IMSG_PD_FIFO)
+#define F_PERR_IMSG_PD_FIFO    V_PERR_IMSG_PD_FIFO(1U)
+
+#define S_PERR_ULPTX_FIFO1    27
+#define V_PERR_ULPTX_FIFO1(x) ((x) << S_PERR_ULPTX_FIFO1)
+#define F_PERR_ULPTX_FIFO1    V_PERR_ULPTX_FIFO1(1U)
+
+#define S_PERR_ULPTX_FIFO0    26
+#define V_PERR_ULPTX_FIFO0(x) ((x) << S_PERR_ULPTX_FIFO0)
+#define F_PERR_ULPTX_FIFO0    V_PERR_ULPTX_FIFO0(1U)
+
+#define S_PERR_IDMA2IMSG_FIFO1    25
+#define V_PERR_IDMA2IMSG_FIFO1(x) ((x) << S_PERR_IDMA2IMSG_FIFO1)
+#define F_PERR_IDMA2IMSG_FIFO1    V_PERR_IDMA2IMSG_FIFO1(1U)
+
+#define S_PERR_IDMA2IMSG_FIFO0    24
+#define V_PERR_IDMA2IMSG_FIFO0(x) ((x) << S_PERR_IDMA2IMSG_FIFO0)
+#define F_PERR_IDMA2IMSG_FIFO0    V_PERR_IDMA2IMSG_FIFO0(1U)
+
+#define S_PERR_HEADERSPLIT_FIFO1    23
+#define V_PERR_HEADERSPLIT_FIFO1(x) ((x) << S_PERR_HEADERSPLIT_FIFO1)
+#define F_PERR_HEADERSPLIT_FIFO1    V_PERR_HEADERSPLIT_FIFO1(1U)
+
+#define S_PERR_HEADERSPLIT_FIFO0    22
+#define V_PERR_HEADERSPLIT_FIFO0(x) ((x) << S_PERR_HEADERSPLIT_FIFO0)
+#define F_PERR_HEADERSPLIT_FIFO0    V_PERR_HEADERSPLIT_FIFO0(1U)
+
+#define S_PERR_ESWITCH_FIFO3    21
+#define V_PERR_ESWITCH_FIFO3(x) ((x) << S_PERR_ESWITCH_FIFO3)
+#define F_PERR_ESWITCH_FIFO3    V_PERR_ESWITCH_FIFO3(1U)
+
+#define S_PERR_ESWITCH_FIFO2    20
+#define V_PERR_ESWITCH_FIFO2(x) ((x) << S_PERR_ESWITCH_FIFO2)
+#define F_PERR_ESWITCH_FIFO2    V_PERR_ESWITCH_FIFO2(1U)
+
+#define S_PERR_ESWITCH_FIFO1    19
+#define V_PERR_ESWITCH_FIFO1(x) ((x) << S_PERR_ESWITCH_FIFO1)
+#define F_PERR_ESWITCH_FIFO1    V_PERR_ESWITCH_FIFO1(1U)
+
+#define S_PERR_ESWITCH_FIFO0    18
+#define V_PERR_ESWITCH_FIFO0(x) ((x) << S_PERR_ESWITCH_FIFO0)
+#define F_PERR_ESWITCH_FIFO0    V_PERR_ESWITCH_FIFO0(1U)
+
+#define S_PERR_PC_DBP1    17
+#define V_PERR_PC_DBP1(x) ((x) << S_PERR_PC_DBP1)
+#define F_PERR_PC_DBP1    V_PERR_PC_DBP1(1U)
+
+#define S_PERR_PC_DBP0    16
+#define V_PERR_PC_DBP0(x) ((x) << S_PERR_PC_DBP0)
+#define F_PERR_PC_DBP0    V_PERR_PC_DBP0(1U)
+
+#define S_PERR_IMSG_OB_FIFO    15
+#define V_PERR_IMSG_OB_FIFO(x) ((x) << S_PERR_IMSG_OB_FIFO)
+#define F_PERR_IMSG_OB_FIFO    V_PERR_IMSG_OB_FIFO(1U)
+
+#define S_PERR_CONM_SRAM    14
+#define V_PERR_CONM_SRAM(x) ((x) << S_PERR_CONM_SRAM)
+#define F_PERR_CONM_SRAM    V_PERR_CONM_SRAM(1U)
+
+#define S_PERR_PC_MC_RSP    13
+#define V_PERR_PC_MC_RSP(x) ((x) << S_PERR_PC_MC_RSP)
+#define F_PERR_PC_MC_RSP    V_PERR_PC_MC_RSP(1U)
+
+#define S_PERR_ISW_IDMA0_FIFO    12
+#define V_PERR_ISW_IDMA0_FIFO(x) ((x) << S_PERR_ISW_IDMA0_FIFO)
+#define F_PERR_ISW_IDMA0_FIFO    V_PERR_ISW_IDMA0_FIFO(1U)
+
+#define S_PERR_ISW_IDMA1_FIFO    11
+#define V_PERR_ISW_IDMA1_FIFO(x) ((x) << S_PERR_ISW_IDMA1_FIFO)
+#define F_PERR_ISW_IDMA1_FIFO    V_PERR_ISW_IDMA1_FIFO(1U)
+
+#define S_PERR_ISW_DBP_FIFO    10
+#define V_PERR_ISW_DBP_FIFO(x) ((x) << S_PERR_ISW_DBP_FIFO)
+#define F_PERR_ISW_DBP_FIFO    V_PERR_ISW_DBP_FIFO(1U)
+
+#define S_PERR_ISW_GTS_FIFO    9
+#define V_PERR_ISW_GTS_FIFO(x) ((x) << S_PERR_ISW_GTS_FIFO)
+#define F_PERR_ISW_GTS_FIFO    V_PERR_ISW_GTS_FIFO(1U)
+
+#define S_PERR_ITP_EVR    8
+#define V_PERR_ITP_EVR(x) ((x) << S_PERR_ITP_EVR)
+#define F_PERR_ITP_EVR    V_PERR_ITP_EVR(1U)
+
+#define S_PERR_FLM_CNTXMEM    7
+#define V_PERR_FLM_CNTXMEM(x) ((x) << S_PERR_FLM_CNTXMEM)
+#define F_PERR_FLM_CNTXMEM    V_PERR_FLM_CNTXMEM(1U)
+
+#define S_PERR_FLM_L1CACHE    6
+#define V_PERR_FLM_L1CACHE(x) ((x) << S_PERR_FLM_L1CACHE)
+#define F_PERR_FLM_L1CACHE    V_PERR_FLM_L1CACHE(1U)
+
+#define S_PERR_DBP_HINT_FIFO    5
+#define V_PERR_DBP_HINT_FIFO(x) ((x) << S_PERR_DBP_HINT_FIFO)
+#define F_PERR_DBP_HINT_FIFO    V_PERR_DBP_HINT_FIFO(1U)
+
+#define S_PERR_DBP_HP_FIFO    4
+#define V_PERR_DBP_HP_FIFO(x) ((x) << S_PERR_DBP_HP_FIFO)
+#define F_PERR_DBP_HP_FIFO    V_PERR_DBP_HP_FIFO(1U)
+
+#define S_PERR_DBP_LP_FIFO    3
+#define V_PERR_DBP_LP_FIFO(x) ((x) << S_PERR_DBP_LP_FIFO)
+#define F_PERR_DBP_LP_FIFO    V_PERR_DBP_LP_FIFO(1U)
+
+#define S_PERR_ING_CTXT_CACHE    2
+#define V_PERR_ING_CTXT_CACHE(x) ((x) << S_PERR_ING_CTXT_CACHE)
+#define F_PERR_ING_CTXT_CACHE    V_PERR_ING_CTXT_CACHE(1U)
+
+#define S_PERR_EGR_CTXT_CACHE    1
+#define V_PERR_EGR_CTXT_CACHE(x) ((x) << S_PERR_EGR_CTXT_CACHE)
+#define F_PERR_EGR_CTXT_CACHE    V_PERR_EGR_CTXT_CACHE(1U)
+
+#define S_PERR_BASE_SIZE    0
+#define V_PERR_BASE_SIZE(x) ((x) << S_PERR_BASE_SIZE)
+#define F_PERR_BASE_SIZE    V_PERR_BASE_SIZE(1U)
+
+#define S_PERR_DBP_HINT_FL_FIFO    24
+#define V_PERR_DBP_HINT_FL_FIFO(x) ((x) << S_PERR_DBP_HINT_FL_FIFO)
+#define F_PERR_DBP_HINT_FL_FIFO    V_PERR_DBP_HINT_FL_FIFO(1U)
+
+#define S_PERR_EGR_DBP_TX_COAL    23
+#define V_PERR_EGR_DBP_TX_COAL(x) ((x) << S_PERR_EGR_DBP_TX_COAL)
+#define F_PERR_EGR_DBP_TX_COAL    V_PERR_EGR_DBP_TX_COAL(1U)
+
+#define S_PERR_DBP_FL_FIFO    22
+#define V_PERR_DBP_FL_FIFO(x) ((x) << S_PERR_DBP_FL_FIFO)
+#define F_PERR_DBP_FL_FIFO    V_PERR_DBP_FL_FIFO(1U)
+
+#define S_PERR_PC_DBP2    15
+#define V_PERR_PC_DBP2(x) ((x) << S_PERR_PC_DBP2)
+#define F_PERR_PC_DBP2    V_PERR_PC_DBP2(1U)
+
+#define A_SGE_INT_ENABLE2 0x1034
+#define A_SGE_PERR_ENABLE2 0x1038
+#define A_SGE_INT_CAUSE3 0x103c
+
+#define S_ERR_FLM_DBP    31
+#define V_ERR_FLM_DBP(x) ((x) << S_ERR_FLM_DBP)
+#define F_ERR_FLM_DBP    V_ERR_FLM_DBP(1U)
+
+#define S_ERR_FLM_IDMA1    30
+#define V_ERR_FLM_IDMA1(x) ((x) << S_ERR_FLM_IDMA1)
+#define F_ERR_FLM_IDMA1    V_ERR_FLM_IDMA1(1U)
+
+#define S_ERR_FLM_IDMA0    29
+#define V_ERR_FLM_IDMA0(x) ((x) << S_ERR_FLM_IDMA0)
+#define F_ERR_FLM_IDMA0    V_ERR_FLM_IDMA0(1U)
+
+#define S_ERR_FLM_HINT    28
+#define V_ERR_FLM_HINT(x) ((x) << S_ERR_FLM_HINT)
+#define F_ERR_FLM_HINT    V_ERR_FLM_HINT(1U)
+
+#define S_ERR_PCIE_ERROR3    27
+#define V_ERR_PCIE_ERROR3(x) ((x) << S_ERR_PCIE_ERROR3)
+#define F_ERR_PCIE_ERROR3    V_ERR_PCIE_ERROR3(1U)
+
+#define S_ERR_PCIE_ERROR2    26
+#define V_ERR_PCIE_ERROR2(x) ((x) << S_ERR_PCIE_ERROR2)
+#define F_ERR_PCIE_ERROR2    V_ERR_PCIE_ERROR2(1U)
+
+#define S_ERR_PCIE_ERROR1    25
+#define V_ERR_PCIE_ERROR1(x) ((x) << S_ERR_PCIE_ERROR1)
+#define F_ERR_PCIE_ERROR1    V_ERR_PCIE_ERROR1(1U)
+
+#define S_ERR_PCIE_ERROR0    24
+#define V_ERR_PCIE_ERROR0(x) ((x) << S_ERR_PCIE_ERROR0)
+#define F_ERR_PCIE_ERROR0    V_ERR_PCIE_ERROR0(1U)
+
+#define S_ERR_TIMER_ABOVE_MAX_QID    23
+#define V_ERR_TIMER_ABOVE_MAX_QID(x) ((x) << S_ERR_TIMER_ABOVE_MAX_QID)
+#define F_ERR_TIMER_ABOVE_MAX_QID    V_ERR_TIMER_ABOVE_MAX_QID(1U)
+
+#define S_ERR_CPL_EXCEED_IQE_SIZE    22
+#define V_ERR_CPL_EXCEED_IQE_SIZE(x) ((x) << S_ERR_CPL_EXCEED_IQE_SIZE)
+#define F_ERR_CPL_EXCEED_IQE_SIZE    V_ERR_CPL_EXCEED_IQE_SIZE(1U)
+
+#define S_ERR_INVALID_CIDX_INC    21
+#define V_ERR_INVALID_CIDX_INC(x) ((x) << S_ERR_INVALID_CIDX_INC)
+#define F_ERR_INVALID_CIDX_INC    V_ERR_INVALID_CIDX_INC(1U)
+
+#define S_ERR_ITP_TIME_PAUSED    20
+#define V_ERR_ITP_TIME_PAUSED(x) ((x) << S_ERR_ITP_TIME_PAUSED)
+#define F_ERR_ITP_TIME_PAUSED    V_ERR_ITP_TIME_PAUSED(1U)
+
+#define S_ERR_CPL_OPCODE_0    19
+#define V_ERR_CPL_OPCODE_0(x) ((x) << S_ERR_CPL_OPCODE_0)
+#define F_ERR_CPL_OPCODE_0    V_ERR_CPL_OPCODE_0(1U)
+
+#define S_ERR_DROPPED_DB    18
+#define V_ERR_DROPPED_DB(x) ((x) << S_ERR_DROPPED_DB)
+#define F_ERR_DROPPED_DB    V_ERR_DROPPED_DB(1U)
+
+#define S_ERR_DATA_CPL_ON_HIGH_QID1    17
+#define V_ERR_DATA_CPL_ON_HIGH_QID1(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID1)
+#define F_ERR_DATA_CPL_ON_HIGH_QID1    V_ERR_DATA_CPL_ON_HIGH_QID1(1U)
+
+#define S_ERR_DATA_CPL_ON_HIGH_QID0    16
+#define V_ERR_DATA_CPL_ON_HIGH_QID0(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID0)
+#define F_ERR_DATA_CPL_ON_HIGH_QID0    V_ERR_DATA_CPL_ON_HIGH_QID0(1U)
+
+#define S_ERR_BAD_DB_PIDX3    15
+#define V_ERR_BAD_DB_PIDX3(x) ((x) << S_ERR_BAD_DB_PIDX3)
+#define F_ERR_BAD_DB_PIDX3    V_ERR_BAD_DB_PIDX3(1U)
+
+#define S_ERR_BAD_DB_PIDX2    14
+#define V_ERR_BAD_DB_PIDX2(x) ((x) << S_ERR_BAD_DB_PIDX2)
+#define F_ERR_BAD_DB_PIDX2    V_ERR_BAD_DB_PIDX2(1U)
+
+#define S_ERR_BAD_DB_PIDX1    13
+#define V_ERR_BAD_DB_PIDX1(x) ((x) << S_ERR_BAD_DB_PIDX1)
+#define F_ERR_BAD_DB_PIDX1    V_ERR_BAD_DB_PIDX1(1U)
+
+#define S_ERR_BAD_DB_PIDX0    12
+#define V_ERR_BAD_DB_PIDX0(x) ((x) << S_ERR_BAD_DB_PIDX0)
+#define F_ERR_BAD_DB_PIDX0    V_ERR_BAD_DB_PIDX0(1U)
+
+#define S_ERR_ING_PCIE_CHAN    11
+#define V_ERR_ING_PCIE_CHAN(x) ((x) << S_ERR_ING_PCIE_CHAN)
+#define F_ERR_ING_PCIE_CHAN    V_ERR_ING_PCIE_CHAN(1U)
+
+#define S_ERR_ING_CTXT_PRIO    10
+#define V_ERR_ING_CTXT_PRIO(x) ((x) << S_ERR_ING_CTXT_PRIO)
+#define F_ERR_ING_CTXT_PRIO    V_ERR_ING_CTXT_PRIO(1U)
+
+#define S_ERR_EGR_CTXT_PRIO    9
+#define V_ERR_EGR_CTXT_PRIO(x) ((x) << S_ERR_EGR_CTXT_PRIO)
+#define F_ERR_EGR_CTXT_PRIO    V_ERR_EGR_CTXT_PRIO(1U)
+
+#define S_DBFIFO_HP_INT    8
+#define V_DBFIFO_HP_INT(x) ((x) << S_DBFIFO_HP_INT)
+#define F_DBFIFO_HP_INT    V_DBFIFO_HP_INT(1U)
+
+#define S_DBFIFO_LP_INT    7
+#define V_DBFIFO_LP_INT(x) ((x) << S_DBFIFO_LP_INT)
+#define F_DBFIFO_LP_INT    V_DBFIFO_LP_INT(1U)
+
+#define S_REG_ADDRESS_ERR    6
+#define V_REG_ADDRESS_ERR(x) ((x) << S_REG_ADDRESS_ERR)
+#define F_REG_ADDRESS_ERR    V_REG_ADDRESS_ERR(1U)
+
+#define S_INGRESS_SIZE_ERR    5
+#define V_INGRESS_SIZE_ERR(x) ((x) << S_INGRESS_SIZE_ERR)
+#define F_INGRESS_SIZE_ERR    V_INGRESS_SIZE_ERR(1U)
+
+#define S_EGRESS_SIZE_ERR    4
+#define V_EGRESS_SIZE_ERR(x) ((x) << S_EGRESS_SIZE_ERR)
+#define F_EGRESS_SIZE_ERR    V_EGRESS_SIZE_ERR(1U)
+
+#define S_ERR_INV_CTXT3    3
+#define V_ERR_INV_CTXT3(x) ((x) << S_ERR_INV_CTXT3)
+#define F_ERR_INV_CTXT3    V_ERR_INV_CTXT3(1U)
+
+#define S_ERR_INV_CTXT2    2
+#define V_ERR_INV_CTXT2(x) ((x) << S_ERR_INV_CTXT2)
+#define F_ERR_INV_CTXT2    V_ERR_INV_CTXT2(1U)
+
+#define S_ERR_INV_CTXT1    1
+#define V_ERR_INV_CTXT1(x) ((x) << S_ERR_INV_CTXT1)
+#define F_ERR_INV_CTXT1    V_ERR_INV_CTXT1(1U)
+
+#define S_ERR_INV_CTXT0    0
+#define V_ERR_INV_CTXT0(x) ((x) << S_ERR_INV_CTXT0)
+#define F_ERR_INV_CTXT0    V_ERR_INV_CTXT0(1U)
+
+#define A_SGE_INT_ENABLE3 0x1040
+#define A_SGE_FL_BUFFER_SIZE0 0x1044
+
+#define S_SIZE    4
+#define M_SIZE    0xfffffffU
+#define V_SIZE(x) ((x) << S_SIZE)
+#define G_SIZE(x) (((x) >> S_SIZE) & M_SIZE)
+
+#define A_SGE_FL_BUFFER_SIZE1 0x1048
+#define A_SGE_FL_BUFFER_SIZE2 0x104c
+#define A_SGE_FL_BUFFER_SIZE3 0x1050
+#define A_SGE_FL_BUFFER_SIZE4 0x1054
+#define A_SGE_FL_BUFFER_SIZE5 0x1058
+#define A_SGE_FL_BUFFER_SIZE6 0x105c
+#define A_SGE_FL_BUFFER_SIZE7 0x1060
+#define A_SGE_FL_BUFFER_SIZE8 0x1064
+#define A_SGE_FL_BUFFER_SIZE9 0x1068
+#define A_SGE_FL_BUFFER_SIZE10 0x106c
+#define A_SGE_FL_BUFFER_SIZE11 0x1070
+#define A_SGE_FL_BUFFER_SIZE12 0x1074
+#define A_SGE_FL_BUFFER_SIZE13 0x1078
+#define A_SGE_FL_BUFFER_SIZE14 0x107c
+#define A_SGE_FL_BUFFER_SIZE15 0x1080
+#define A_SGE_DBQ_CTXT_BADDR 0x1084
+
+#define S_BASEADDR    3
+#define M_BASEADDR    0x1fffffffU
+#define V_BASEADDR(x) ((x) << S_BASEADDR)
+#define G_BASEADDR(x) (((x) >> S_BASEADDR) & M_BASEADDR)
+
+#define A_SGE_IMSG_CTXT_BADDR 0x1088
+#define A_SGE_FLM_CACHE_BADDR 0x108c
+#define A_SGE_FLM_CFG 0x1090
+
+#define S_OPMODE    26
+#define M_OPMODE    0x3fU
+#define V_OPMODE(x) ((x) << S_OPMODE)
+#define G_OPMODE(x) (((x) >> S_OPMODE) & M_OPMODE)
+
+#define S_NOHDR    18
+#define V_NOHDR(x) ((x) << S_NOHDR)
+#define F_NOHDR    V_NOHDR(1U)
+
+#define S_CACHEPTRCNT    16
+#define M_CACHEPTRCNT    0x3U
+#define V_CACHEPTRCNT(x) ((x) << S_CACHEPTRCNT)
+#define G_CACHEPTRCNT(x) (((x) >> S_CACHEPTRCNT) & M_CACHEPTRCNT)
+
+#define S_EDRAMPTRCNT    14
+#define M_EDRAMPTRCNT    0x3U
+#define V_EDRAMPTRCNT(x) ((x) << S_EDRAMPTRCNT)
+#define G_EDRAMPTRCNT(x) (((x) >> S_EDRAMPTRCNT) & M_EDRAMPTRCNT)
+
+#define S_HDRSTARTFLQ    11
+#define M_HDRSTARTFLQ    0x7U
+#define V_HDRSTARTFLQ(x) ((x) << S_HDRSTARTFLQ)
+#define G_HDRSTARTFLQ(x) (((x) >> S_HDRSTARTFLQ) & M_HDRSTARTFLQ)
+
+#define S_FETCHTHRESH    6
+#define M_FETCHTHRESH    0x1fU
+#define V_FETCHTHRESH(x) ((x) << S_FETCHTHRESH)
+#define G_FETCHTHRESH(x) (((x) >> S_FETCHTHRESH) & M_FETCHTHRESH)
+
+#define S_CREDITCNT    4
+#define M_CREDITCNT    0x3U
+#define V_CREDITCNT(x) ((x) << S_CREDITCNT)
+#define G_CREDITCNT(x) (((x) >> S_CREDITCNT) & M_CREDITCNT)
+
+#define S_NOEDRAM    0
+#define V_NOEDRAM(x) ((x) << S_NOEDRAM)
+#define F_NOEDRAM    V_NOEDRAM(1U)
+
+#define S_CREDITCNTPACKING    2
+#define M_CREDITCNTPACKING    0x3U
+#define V_CREDITCNTPACKING(x) ((x) << S_CREDITCNTPACKING)
+#define G_CREDITCNTPACKING(x) (((x) >> S_CREDITCNTPACKING) & M_CREDITCNTPACKING)
+
+#define A_SGE_CONM_CTRL 0x1094
+
+#define S_EGRTHRESHOLD    8
+#define M_EGRTHRESHOLD    0x3fU
+#define V_EGRTHRESHOLD(x) ((x) << S_EGRTHRESHOLD)
+#define G_EGRTHRESHOLD(x) (((x) >> S_EGRTHRESHOLD) & M_EGRTHRESHOLD)
+
+#define S_INGTHRESHOLD    2
+#define M_INGTHRESHOLD    0x3fU
+#define V_INGTHRESHOLD(x) ((x) << S_INGTHRESHOLD)
+#define G_INGTHRESHOLD(x) (((x) >> S_INGTHRESHOLD) & M_INGTHRESHOLD)
+
+#define S_MPS_ENABLE    1
+#define V_MPS_ENABLE(x) ((x) << S_MPS_ENABLE)
+#define F_MPS_ENABLE    V_MPS_ENABLE(1U)
+
+#define S_TP_ENABLE    0
+#define V_TP_ENABLE(x) ((x) << S_TP_ENABLE)
+#define F_TP_ENABLE    V_TP_ENABLE(1U)
+
+#define S_EGRTHRESHOLDPACKING    14
+#define M_EGRTHRESHOLDPACKING    0x3fU
+#define V_EGRTHRESHOLDPACKING(x) ((x) << S_EGRTHRESHOLDPACKING)
+#define G_EGRTHRESHOLDPACKING(x) (((x) >> S_EGRTHRESHOLDPACKING) & M_EGRTHRESHOLDPACKING)
+
+#define A_SGE_TIMESTAMP_LO 0x1098
+#define A_SGE_TIMESTAMP_HI 0x109c
+
+#define S_TSOP    28
+#define M_TSOP    0x3U
+#define V_TSOP(x) ((x) << S_TSOP)
+#define G_TSOP(x) (((x) >> S_TSOP) & M_TSOP)
+
+#define S_TSVAL    0
+#define M_TSVAL    0xfffffffU
+#define V_TSVAL(x) ((x) << S_TSVAL)
+#define G_TSVAL(x) (((x) >> S_TSVAL) & M_TSVAL)
+
+#define A_SGE_INGRESS_RX_THRESHOLD 0x10a0
+
+#define S_THRESHOLD_0    24
+#define M_THRESHOLD_0    0x3fU
+#define V_THRESHOLD_0(x) ((x) << S_THRESHOLD_0)
+#define G_THRESHOLD_0(x) (((x) >> S_THRESHOLD_0) & M_THRESHOLD_0)
+
+#define S_THRESHOLD_1    16
+#define M_THRESHOLD_1    0x3fU
+#define V_THRESHOLD_1(x) ((x) << S_THRESHOLD_1)
+#define G_THRESHOLD_1(x) (((x) >> S_THRESHOLD_1) & M_THRESHOLD_1)
+
+#define S_THRESHOLD_2    8
+#define M_THRESHOLD_2    0x3fU
+#define V_THRESHOLD_2(x) ((x) << S_THRESHOLD_2)
+#define G_THRESHOLD_2(x) (((x) >> S_THRESHOLD_2) & M_THRESHOLD_2)
+
+#define S_THRESHOLD_3    0
+#define M_THRESHOLD_3    0x3fU
+#define V_THRESHOLD_3(x) ((x) << S_THRESHOLD_3)
+#define G_THRESHOLD_3(x) (((x) >> S_THRESHOLD_3) & M_THRESHOLD_3)
+
+#define A_SGE_DBFIFO_STATUS 0x10a4
+
+#define S_HP_INT_THRESH    28
+#define M_HP_INT_THRESH    0xfU
+#define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH)
+#define G_HP_INT_THRESH(x) (((x) >> S_HP_INT_THRESH) & M_HP_INT_THRESH)
+
+#define S_HP_COUNT    16
+#define M_HP_COUNT    0x7ffU
+#define V_HP_COUNT(x) ((x) << S_HP_COUNT)
+#define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT)
+
+#define S_LP_INT_THRESH    12
+#define M_LP_INT_THRESH    0xfU
+#define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH)
+#define G_LP_INT_THRESH(x) (((x) >> S_LP_INT_THRESH) & M_LP_INT_THRESH)
+
+#define S_LP_COUNT    0
+#define M_LP_COUNT    0x7ffU
+#define V_LP_COUNT(x) ((x) << S_LP_COUNT)
+#define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT)
+
+#define S_BAR2VALID    31
+#define V_BAR2VALID(x) ((x) << S_BAR2VALID)
+#define F_BAR2VALID    V_BAR2VALID(1U)
+
+#define S_BAR2FULL    30
+#define V_BAR2FULL(x) ((x) << S_BAR2FULL)
+#define F_BAR2FULL    V_BAR2FULL(1U)
+
+#define S_LP_INT_THRESH_T5    18
+#define M_LP_INT_THRESH_T5    0xfffU
+#define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5)
+#define G_LP_INT_THRESH_T5(x) (((x) >> S_LP_INT_THRESH_T5) & M_LP_INT_THRESH_T5)
+
+#define S_LP_COUNT_T5    0
+#define M_LP_COUNT_T5    0x3ffffU
+#define V_LP_COUNT_T5(x) ((x) << S_LP_COUNT_T5)
+#define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT_T5) & M_LP_COUNT_T5)
+
+#define A_SGE_DOORBELL_CONTROL 0x10a8
+
+#define S_HINTDEPTHCTL    27
+#define M_HINTDEPTHCTL    0x1fU
+#define V_HINTDEPTHCTL(x) ((x) << S_HINTDEPTHCTL)
+#define G_HINTDEPTHCTL(x) (((x) >> S_HINTDEPTHCTL) & M_HINTDEPTHCTL)
+
+#define S_NOCOALESCE    26
+#define V_NOCOALESCE(x) ((x) << S_NOCOALESCE)
+#define F_NOCOALESCE    V_NOCOALESCE(1U)
+
+#define S_HP_WEIGHT    24
+#define M_HP_WEIGHT    0x3U
+#define V_HP_WEIGHT(x) ((x) << S_HP_WEIGHT)
+#define G_HP_WEIGHT(x) (((x) >> S_HP_WEIGHT) & M_HP_WEIGHT)
+
+#define S_HP_DISABLE    23
+#define V_HP_DISABLE(x) ((x) << S_HP_DISABLE)
+#define F_HP_DISABLE    V_HP_DISABLE(1U)
+
+#define S_FORCEUSERDBTOLP    22
+#define V_FORCEUSERDBTOLP(x) ((x) << S_FORCEUSERDBTOLP)
+#define F_FORCEUSERDBTOLP    V_FORCEUSERDBTOLP(1U)
+
+#define S_FORCEVFPF0DBTOLP    21
+#define V_FORCEVFPF0DBTOLP(x) ((x) << S_FORCEVFPF0DBTOLP)
+#define F_FORCEVFPF0DBTOLP    V_FORCEVFPF0DBTOLP(1U)
+
+#define S_FORCEVFPF1DBTOLP    20
+#define V_FORCEVFPF1DBTOLP(x) ((x) << S_FORCEVFPF1DBTOLP)
+#define F_FORCEVFPF1DBTOLP    V_FORCEVFPF1DBTOLP(1U)
+
+#define S_FORCEVFPF2DBTOLP    19
+#define V_FORCEVFPF2DBTOLP(x) ((x) << S_FORCEVFPF2DBTOLP)
+#define F_FORCEVFPF2DBTOLP    V_FORCEVFPF2DBTOLP(1U)
+
+#define S_FORCEVFPF3DBTOLP    18
+#define V_FORCEVFPF3DBTOLP(x) ((x) << S_FORCEVFPF3DBTOLP)
+#define F_FORCEVFPF3DBTOLP    V_FORCEVFPF3DBTOLP(1U)
+
+#define S_FORCEVFPF4DBTOLP    17
+#define V_FORCEVFPF4DBTOLP(x) ((x) << S_FORCEVFPF4DBTOLP)
+#define F_FORCEVFPF4DBTOLP    V_FORCEVFPF4DBTOLP(1U)
+
+#define S_FORCEVFPF5DBTOLP    16
+#define V_FORCEVFPF5DBTOLP(x) ((x) << S_FORCEVFPF5DBTOLP)
+#define F_FORCEVFPF5DBTOLP    V_FORCEVFPF5DBTOLP(1U)
+
+#define S_FORCEVFPF6DBTOLP    15
+#define V_FORCEVFPF6DBTOLP(x) ((x) << S_FORCEVFPF6DBTOLP)
+#define F_FORCEVFPF6DBTOLP    V_FORCEVFPF6DBTOLP(1U)
+
+#define S_FORCEVFPF7DBTOLP    14
+#define V_FORCEVFPF7DBTOLP(x) ((x) << S_FORCEVFPF7DBTOLP)
+#define F_FORCEVFPF7DBTOLP    V_FORCEVFPF7DBTOLP(1U)
+
+#define S_ENABLE_DROP    13
+#define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP)
+#define F_ENABLE_DROP    V_ENABLE_DROP(1U)
+
+#define S_DROP_TIMEOUT    1
+#define M_DROP_TIMEOUT    0xfffU
+#define V_DROP_TIMEOUT(x) ((x) << S_DROP_TIMEOUT)
+#define G_DROP_TIMEOUT(x) (((x) >> S_DROP_TIMEOUT) & M_DROP_TIMEOUT)
+
+#define S_DROPPED_DB    0
+#define V_DROPPED_DB(x) ((x) << S_DROPPED_DB)
+#define F_DROPPED_DB    V_DROPPED_DB(1U)
+
+#define A_SGE_DROPPED_DOORBELL 0x10ac
+#define A_SGE_DOORBELL_THROTTLE_CONTROL 0x10b0
+
+#define S_THROTTLE_COUNT    1
+#define M_THROTTLE_COUNT    0xfffU
+#define V_THROTTLE_COUNT(x) ((x) << S_THROTTLE_COUNT)
+#define G_THROTTLE_COUNT(x) (((x) >> S_THROTTLE_COUNT) & M_THROTTLE_COUNT)
+
+#define S_THROTTLE_ENABLE    0
+#define V_THROTTLE_ENABLE(x) ((x) << S_THROTTLE_ENABLE)
+#define F_THROTTLE_ENABLE    V_THROTTLE_ENABLE(1U)
+
+#define S_BAR2THROTTLECOUNT    16
+#define M_BAR2THROTTLECOUNT    0xffU
+#define V_BAR2THROTTLECOUNT(x) ((x) << S_BAR2THROTTLECOUNT)
+#define G_BAR2THROTTLECOUNT(x) (((x) >> S_BAR2THROTTLECOUNT) & M_BAR2THROTTLECOUNT)
+
+#define S_CLRCOALESCEDISABLE    15
+#define V_CLRCOALESCEDISABLE(x) ((x) << S_CLRCOALESCEDISABLE)
+#define F_CLRCOALESCEDISABLE    V_CLRCOALESCEDISABLE(1U)
+
+#define S_OPENBAR2GATEONCE    14
+#define V_OPENBAR2GATEONCE(x) ((x) << S_OPENBAR2GATEONCE)
+#define F_OPENBAR2GATEONCE    V_OPENBAR2GATEONCE(1U)
+
+#define S_FORCEOPENBAR2GATE    13
+#define V_FORCEOPENBAR2GATE(x) ((x) << S_FORCEOPENBAR2GATE)
+#define F_FORCEOPENBAR2GATE    V_FORCEOPENBAR2GATE(1U)
+
+#define A_SGE_ITP_CONTROL 0x10b4
+
+#define S_CRITICAL_TIME    10
+#define M_CRITICAL_TIME    0x7fffU
+#define V_CRITICAL_TIME(x) ((x) << S_CRITICAL_TIME)
+#define G_CRITICAL_TIME(x) (((x) >> S_CRITICAL_TIME) & M_CRITICAL_TIME)
+
+#define S_LL_EMPTY    4
+#define M_LL_EMPTY    0x3fU
+#define V_LL_EMPTY(x) ((x) << S_LL_EMPTY)
+#define G_LL_EMPTY(x) (((x) >> S_LL_EMPTY) & M_LL_EMPTY)
+
+#define S_LL_READ_WAIT_DISABLE    0
+#define V_LL_READ_WAIT_DISABLE(x) ((x) << S_LL_READ_WAIT_DISABLE)
+#define F_LL_READ_WAIT_DISABLE    V_LL_READ_WAIT_DISABLE(1U)
+
+#define A_SGE_TIMER_VALUE_0_AND_1 0x10b8
+
+#define S_TIMERVALUE0    16
+#define M_TIMERVALUE0    0xffffU
+#define V_TIMERVALUE0(x) ((x) << S_TIMERVALUE0)
+#define G_TIMERVALUE0(x) (((x) >> S_TIMERVALUE0) & M_TIMERVALUE0)
+
+#define S_TIMERVALUE1    0
+#define M_TIMERVALUE1    0xffffU
+#define V_TIMERVALUE1(x) ((x) << S_TIMERVALUE1)
+#define G_TIMERVALUE1(x) (((x) >> S_TIMERVALUE1) & M_TIMERVALUE1)
+
+#define A_SGE_TIMER_VALUE_2_AND_3 0x10bc
+
+#define S_TIMERVALUE2    16
+#define M_TIMERVALUE2    0xffffU
+#define V_TIMERVALUE2(x) ((x) << S_TIMERVALUE2)
+#define G_TIMERVALUE2(x) (((x) >> S_TIMERVALUE2) & M_TIMERVALUE2)
+
+#define S_TIMERVALUE3    0
+#define M_TIMERVALUE3    0xffffU
+#define V_TIMERVALUE3(x) ((x) << S_TIMERVALUE3)
+#define G_TIMERVALUE3(x) (((x) >> S_TIMERVALUE3) & M_TIMERVALUE3)
+
+#define A_SGE_TIMER_VALUE_4_AND_5 0x10c0
+
+#define S_TIMERVALUE4    16
+#define M_TIMERVALUE4    0xffffU
+#define V_TIMERVALUE4(x) ((x) << S_TIMERVALUE4)
+#define G_TIMERVALUE4(x) (((x) >> S_TIMERVALUE4) & M_TIMERVALUE4)
+
+#define S_TIMERVALUE5    0
+#define M_TIMERVALUE5    0xffffU
+#define V_TIMERVALUE5(x) ((x) << S_TIMERVALUE5)
+#define G_TIMERVALUE5(x) (((x) >> S_TIMERVALUE5) & M_TIMERVALUE5)
+
+#define A_SGE_PD_RSP_CREDIT01 0x10c4
+
+#define S_RSPCREDITEN0    31
+#define V_RSPCREDITEN0(x) ((x) << S_RSPCREDITEN0)
+#define F_RSPCREDITEN0    V_RSPCREDITEN0(1U)
+
+#define S_MAXTAG0    24
+#define M_MAXTAG0    0x7fU
+#define V_MAXTAG0(x) ((x) << S_MAXTAG0)
+#define G_MAXTAG0(x) (((x) >> S_MAXTAG0) & M_MAXTAG0)
+
+#define S_MAXRSPCNT0    16
+#define M_MAXRSPCNT0    0xffU
+#define V_MAXRSPCNT0(x) ((x) << S_MAXRSPCNT0)
+#define G_MAXRSPCNT0(x) (((x) >> S_MAXRSPCNT0) & M_MAXRSPCNT0)
+
+#define S_RSPCREDITEN1    15
+#define V_RSPCREDITEN1(x) ((x) << S_RSPCREDITEN1)
+#define F_RSPCREDITEN1    V_RSPCREDITEN1(1U)
+
+#define S_MAXTAG1    8
+#define M_MAXTAG1    0x7fU
+#define V_MAXTAG1(x) ((x) << S_MAXTAG1)
+#define G_MAXTAG1(x) (((x) >> S_MAXTAG1) & M_MAXTAG1)
+
+#define S_MAXRSPCNT1    0
+#define M_MAXRSPCNT1    0xffU
+#define V_MAXRSPCNT1(x) ((x) << S_MAXRSPCNT1)
+#define G_MAXRSPCNT1(x) (((x) >> S_MAXRSPCNT1) & M_MAXRSPCNT1)
+
+#define A_SGE_PD_RSP_CREDIT23 0x10c8
+
+#define S_RSPCREDITEN2    31
+#define V_RSPCREDITEN2(x) ((x) << S_RSPCREDITEN2)
+#define F_RSPCREDITEN2    V_RSPCREDITEN2(1U)
+
+#define S_MAXTAG2    24
+#define M_MAXTAG2    0x7fU
+#define V_MAXTAG2(x) ((x) << S_MAXTAG2)
+#define G_MAXTAG2(x) (((x) >> S_MAXTAG2) & M_MAXTAG2)
+
+#define S_MAXRSPCNT2    16
+#define M_MAXRSPCNT2    0xffU
+#define V_MAXRSPCNT2(x) ((x) << S_MAXRSPCNT2)
+#define G_MAXRSPCNT2(x) (((x) >> S_MAXRSPCNT2) & M_MAXRSPCNT2)
+
+#define S_RSPCREDITEN3    15
+#define V_RSPCREDITEN3(x) ((x) << S_RSPCREDITEN3)
+#define F_RSPCREDITEN3    V_RSPCREDITEN3(1U)
+
+#define S_MAXTAG3    8
+#define M_MAXTAG3    0x7fU
+#define V_MAXTAG3(x) ((x) << S_MAXTAG3)
+#define G_MAXTAG3(x) (((x) >> S_MAXTAG3) & M_MAXTAG3)
+
+#define S_MAXRSPCNT3    0
+#define M_MAXRSPCNT3    0xffU
+#define V_MAXRSPCNT3(x) ((x) << S_MAXRSPCNT3)
+#define G_MAXRSPCNT3(x) (((x) >> S_MAXRSPCNT3) & M_MAXRSPCNT3)
+
+#define A_SGE_DEBUG_INDEX 0x10cc
+#define A_SGE_DEBUG_DATA_HIGH 0x10d0
+#define A_SGE_DEBUG_DATA_LOW 0x10d4
+#define A_SGE_REVISION 0x10d8
+#define A_SGE_INT_CAUSE4 0x10dc
+
+#define S_ERR_BAD_UPFL_INC_CREDIT3    8
+#define V_ERR_BAD_UPFL_INC_CREDIT3(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT3)
+#define F_ERR_BAD_UPFL_INC_CREDIT3    V_ERR_BAD_UPFL_INC_CREDIT3(1U)
+
+#define S_ERR_BAD_UPFL_INC_CREDIT2    7
+#define V_ERR_BAD_UPFL_INC_CREDIT2(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT2)
+#define F_ERR_BAD_UPFL_INC_CREDIT2    V_ERR_BAD_UPFL_INC_CREDIT2(1U)
+
+#define S_ERR_BAD_UPFL_INC_CREDIT1    6
+#define V_ERR_BAD_UPFL_INC_CREDIT1(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT1)
+#define F_ERR_BAD_UPFL_INC_CREDIT1    V_ERR_BAD_UPFL_INC_CREDIT1(1U)
+
+#define S_ERR_BAD_UPFL_INC_CREDIT0    5
+#define V_ERR_BAD_UPFL_INC_CREDIT0(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT0)
+#define F_ERR_BAD_UPFL_INC_CREDIT0    V_ERR_BAD_UPFL_INC_CREDIT0(1U)
+
+#define S_ERR_PHYSADDR_LEN0_IDMA1    4
+#define V_ERR_PHYSADDR_LEN0_IDMA1(x) ((x) << S_ERR_PHYSADDR_LEN0_IDMA1)
+#define F_ERR_PHYSADDR_LEN0_IDMA1    V_ERR_PHYSADDR_LEN0_IDMA1(1U)
+
+#define S_ERR_PHYSADDR_LEN0_IDMA0    3
+#define V_ERR_PHYSADDR_LEN0_IDMA0(x) ((x) << S_ERR_PHYSADDR_LEN0_IDMA0)
+#define F_ERR_PHYSADDR_LEN0_IDMA0    V_ERR_PHYSADDR_LEN0_IDMA0(1U)
+
+#define S_ERR_FLM_INVALID_PKT_DROP1    2
+#define V_ERR_FLM_INVALID_PKT_DROP1(x) ((x) << S_ERR_FLM_INVALID_PKT_DROP1)
+#define F_ERR_FLM_INVALID_PKT_DROP1    V_ERR_FLM_INVALID_PKT_DROP1(1U)
+
+#define S_ERR_FLM_INVALID_PKT_DROP0    1
+#define V_ERR_FLM_INVALID_PKT_DROP0(x) ((x) << S_ERR_FLM_INVALID_PKT_DROP0)
+#define F_ERR_FLM_INVALID_PKT_DROP0    V_ERR_FLM_INVALID_PKT_DROP0(1U)
+
+#define S_ERR_UNEXPECTED_TIMER    0
+#define V_ERR_UNEXPECTED_TIMER(x) ((x) << S_ERR_UNEXPECTED_TIMER)
+#define F_ERR_UNEXPECTED_TIMER    V_ERR_UNEXPECTED_TIMER(1U)
+
+#define S_BAR2_EGRESS_LEN_OR_ADDR_ERR    29
+#define V_BAR2_EGRESS_LEN_OR_ADDR_ERR(x) ((x) << S_BAR2_EGRESS_LEN_OR_ADDR_ERR)
+#define F_BAR2_EGRESS_LEN_OR_ADDR_ERR    V_BAR2_EGRESS_LEN_OR_ADDR_ERR(1U)
+
+#define S_ERR_CPL_EXCEED_MAX_IQE_SIZE1    28
+#define V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE1)
+#define F_ERR_CPL_EXCEED_MAX_IQE_SIZE1    V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(1U)
+
+#define S_ERR_CPL_EXCEED_MAX_IQE_SIZE0    27
+#define V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE0)
+#define F_ERR_CPL_EXCEED_MAX_IQE_SIZE0    V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(1U)
+
+#define S_ERR_WR_LEN_TOO_LARGE3    26
+#define V_ERR_WR_LEN_TOO_LARGE3(x) ((x) << S_ERR_WR_LEN_TOO_LARGE3)
+#define F_ERR_WR_LEN_TOO_LARGE3    V_ERR_WR_LEN_TOO_LARGE3(1U)
+
+#define S_ERR_WR_LEN_TOO_LARGE2    25
+#define V_ERR_WR_LEN_TOO_LARGE2(x) ((x) << S_ERR_WR_LEN_TOO_LARGE2)
+#define F_ERR_WR_LEN_TOO_LARGE2    V_ERR_WR_LEN_TOO_LARGE2(1U)
+
+#define S_ERR_WR_LEN_TOO_LARGE1    24
+#define V_ERR_WR_LEN_TOO_LARGE1(x) ((x) << S_ERR_WR_LEN_TOO_LARGE1)
+#define F_ERR_WR_LEN_TOO_LARGE1    V_ERR_WR_LEN_TOO_LARGE1(1U)
+
+#define S_ERR_WR_LEN_TOO_LARGE0    23
+#define V_ERR_WR_LEN_TOO_LARGE0(x) ((x) << S_ERR_WR_LEN_TOO_LARGE0)
+#define F_ERR_WR_LEN_TOO_LARGE0    V_ERR_WR_LEN_TOO_LARGE0(1U)
+
+#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL3    22
+#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL3)
+#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL3    V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(1U)
+
+#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL2    21
+#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL2)
+#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL2    V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(1U)
+
+#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL1    20
+#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL1)
+#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL1    V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(1U)
+
+#define S_ERR_LARGE_MINFETCH_WITH_TXCOAL0    19
+#define V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL0)
+#define F_ERR_LARGE_MINFETCH_WITH_TXCOAL0    V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(1U)
+
+#define S_COAL_WITH_HP_DISABLE_ERR    18
+#define V_COAL_WITH_HP_DISABLE_ERR(x) ((x) << S_COAL_WITH_HP_DISABLE_ERR)
+#define F_COAL_WITH_HP_DISABLE_ERR    V_COAL_WITH_HP_DISABLE_ERR(1U)
+
+#define S_BAR2_EGRESS_COAL0_ERR    17
+#define V_BAR2_EGRESS_COAL0_ERR(x) ((x) << S_BAR2_EGRESS_COAL0_ERR)
+#define F_BAR2_EGRESS_COAL0_ERR    V_BAR2_EGRESS_COAL0_ERR(1U)
+
+#define S_BAR2_EGRESS_SIZE_ERR    16
+#define V_BAR2_EGRESS_SIZE_ERR(x) ((x) << S_BAR2_EGRESS_SIZE_ERR)
+#define F_BAR2_EGRESS_SIZE_ERR    V_BAR2_EGRESS_SIZE_ERR(1U)
+
+#define S_FLM_PC_RSP_ERR    15
+#define V_FLM_PC_RSP_ERR(x) ((x) << S_FLM_PC_RSP_ERR)
+#define F_FLM_PC_RSP_ERR    V_FLM_PC_RSP_ERR(1U)
+
+#define S_DBFIFO_HP_INT_LOW    14
+#define V_DBFIFO_HP_INT_LOW(x) ((x) << S_DBFIFO_HP_INT_LOW)
+#define F_DBFIFO_HP_INT_LOW    V_DBFIFO_HP_INT_LOW(1U)
+
+#define S_DBFIFO_LP_INT_LOW    13
+#define V_DBFIFO_LP_INT_LOW(x) ((x) << S_DBFIFO_LP_INT_LOW)
+#define F_DBFIFO_LP_INT_LOW    V_DBFIFO_LP_INT_LOW(1U)
+
+#define S_DBFIFO_FL_INT_LOW    12
+#define V_DBFIFO_FL_INT_LOW(x) ((x) << S_DBFIFO_FL_INT_LOW)
+#define F_DBFIFO_FL_INT_LOW    V_DBFIFO_FL_INT_LOW(1U)
+
+#define S_DBFIFO_FL_INT    11
+#define V_DBFIFO_FL_INT(x) ((x) << S_DBFIFO_FL_INT)
+#define F_DBFIFO_FL_INT    V_DBFIFO_FL_INT(1U)
+
+#define S_ERR_RX_CPL_PACKET_SIZE1    10
+#define V_ERR_RX_CPL_PACKET_SIZE1(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE1)
+#define F_ERR_RX_CPL_PACKET_SIZE1    V_ERR_RX_CPL_PACKET_SIZE1(1U)
+
+#define S_ERR_RX_CPL_PACKET_SIZE0    9
+#define V_ERR_RX_CPL_PACKET_SIZE0(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE0)
+#define F_ERR_RX_CPL_PACKET_SIZE0    V_ERR_RX_CPL_PACKET_SIZE0(1U)
+
+#define A_SGE_INT_ENABLE4 0x10e0
+#define A_SGE_STAT_TOTAL 0x10e4
+#define A_SGE_STAT_MATCH 0x10e8
+#define A_SGE_STAT_CFG 0x10ec
+
+#define S_ITPOPMODE    8
+#define V_ITPOPMODE(x) ((x) << S_ITPOPMODE)
+#define F_ITPOPMODE    V_ITPOPMODE(1U)
+
+#define S_EGRCTXTOPMODE    6
+#define M_EGRCTXTOPMODE    0x3U
+#define V_EGRCTXTOPMODE(x) ((x) << S_EGRCTXTOPMODE)
+#define G_EGRCTXTOPMODE(x) (((x) >> S_EGRCTXTOPMODE) & M_EGRCTXTOPMODE)
+
+#define S_INGCTXTOPMODE    4
+#define M_INGCTXTOPMODE    0x3U
+#define V_INGCTXTOPMODE(x) ((x) << S_INGCTXTOPMODE)
+#define G_INGCTXTOPMODE(x) (((x) >> S_INGCTXTOPMODE) & M_INGCTXTOPMODE)
+
+#define S_STATMODE    2
+#define M_STATMODE    0x3U
+#define V_STATMODE(x) ((x) << S_STATMODE)
+#define G_STATMODE(x) (((x) >> S_STATMODE) & M_STATMODE)
+
+#define S_STATSOURCE    0
+#define M_STATSOURCE    0x3U
+#define V_STATSOURCE(x) ((x) << S_STATSOURCE)
+#define G_STATSOURCE(x) (((x) >> S_STATSOURCE) & M_STATSOURCE)
+
+#define S_STATSOURCE_T5    9
+#define M_STATSOURCE_T5    0xfU
+#define V_STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
+#define G_STATSOURCE_T5(x) (((x) >> S_STATSOURCE_T5) & M_STATSOURCE_T5)
+
+#define A_SGE_HINT_CFG 0x10f0
+
+#define S_HINTSALLOWEDNOHDR    6
+#define M_HINTSALLOWEDNOHDR    0x3fU
+#define V_HINTSALLOWEDNOHDR(x) ((x) << S_HINTSALLOWEDNOHDR)
+#define G_HINTSALLOWEDNOHDR(x) (((x) >> S_HINTSALLOWEDNOHDR) & M_HINTSALLOWEDNOHDR)
+
+#define S_HINTSALLOWEDHDR    0
+#define M_HINTSALLOWEDHDR    0x3fU
+#define V_HINTSALLOWEDHDR(x) ((x) << S_HINTSALLOWEDHDR)
+#define G_HINTSALLOWEDHDR(x) (((x) >> S_HINTSALLOWEDHDR) & M_HINTSALLOWEDHDR)
+
+#define S_UPCUTOFFTHRESHLP    12
+#define M_UPCUTOFFTHRESHLP    0x7ffU
+#define V_UPCUTOFFTHRESHLP(x) ((x) << S_UPCUTOFFTHRESHLP)
+#define G_UPCUTOFFTHRESHLP(x) (((x) >> S_UPCUTOFFTHRESHLP) & M_UPCUTOFFTHRESHLP)
+
+#define A_SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
+#define A_SGE_INGRESS_QUEUES_PER_PAGE_VF 0x10f8
+#define A_SGE_PD_WRR_CONFIG 0x10fc
+
+#define S_EDMA_WEIGHT    0
+#define M_EDMA_WEIGHT    0x3fU
+#define V_EDMA_WEIGHT(x) ((x) << S_EDMA_WEIGHT)
+#define G_EDMA_WEIGHT(x) (((x) >> S_EDMA_WEIGHT) & M_EDMA_WEIGHT)
+
+#define A_SGE_ERROR_STATS 0x1100
+
+#define S_UNCAPTURED_ERROR    18
+#define V_UNCAPTURED_ERROR(x) ((x) << S_UNCAPTURED_ERROR)
+#define F_UNCAPTURED_ERROR    V_UNCAPTURED_ERROR(1U)
+
+#define S_ERROR_QID_VALID    17
+#define V_ERROR_QID_VALID(x) ((x) << S_ERROR_QID_VALID)
+#define F_ERROR_QID_VALID    V_ERROR_QID_VALID(1U)
+
+#define S_ERROR_QID    0
+#define M_ERROR_QID    0x1ffffU
+#define V_ERROR_QID(x) ((x) << S_ERROR_QID)
+#define G_ERROR_QID(x) (((x) >> S_ERROR_QID) & M_ERROR_QID)
+
+#define S_CAUSE_REGISTER    24
+#define M_CAUSE_REGISTER    0x7U
+#define V_CAUSE_REGISTER(x) ((x) << S_CAUSE_REGISTER)
+#define G_CAUSE_REGISTER(x) (((x) >> S_CAUSE_REGISTER) & M_CAUSE_REGISTER)
+
+#define S_CAUSE_BIT    19
+#define M_CAUSE_BIT    0x1fU
+#define V_CAUSE_BIT(x) ((x) << S_CAUSE_BIT)
+#define G_CAUSE_BIT(x) (((x) >> S_CAUSE_BIT) & M_CAUSE_BIT)
+
+#define A_SGE_SHARED_TAG_CHAN_CFG 0x1104
+
+#define S_MINTAG3    24
+#define M_MINTAG3    0xffU
+#define V_MINTAG3(x) ((x) << S_MINTAG3)
+#define G_MINTAG3(x) (((x) >> S_MINTAG3) & M_MINTAG3)
+
+#define S_MINTAG2    16
+#define M_MINTAG2    0xffU
+#define V_MINTAG2(x) ((x) << S_MINTAG2)
+#define G_MINTAG2(x) (((x) >> S_MINTAG2) & M_MINTAG2)
+
+#define S_MINTAG1    8
+#define M_MINTAG1    0xffU
+#define V_MINTAG1(x) ((x) << S_MINTAG1)
+#define G_MINTAG1(x) (((x) >> S_MINTAG1) & M_MINTAG1)
+
+#define S_MINTAG0    0
+#define M_MINTAG0    0xffU
+#define V_MINTAG0(x) ((x) << S_MINTAG0)
+#define G_MINTAG0(x) (((x) >> S_MINTAG0) & M_MINTAG0)
+
+#define A_SGE_SHARED_TAG_POOL_CFG 0x1108
+
+#define S_TAGPOOLTOTAL    0
+#define M_TAGPOOLTOTAL    0xffU
+#define V_TAGPOOLTOTAL(x) ((x) << S_TAGPOOLTOTAL)
+#define G_TAGPOOLTOTAL(x) (((x) >> S_TAGPOOLTOTAL) & M_TAGPOOLTOTAL)
+
+#define A_SGE_INT_CAUSE5 0x110c
+
+#define S_ERR_T_RXCRC    31
+#define V_ERR_T_RXCRC(x) ((x) << S_ERR_T_RXCRC)
+#define F_ERR_T_RXCRC    V_ERR_T_RXCRC(1U)
+
+#define S_PERR_MC_RSPDATA    30
+#define V_PERR_MC_RSPDATA(x) ((x) << S_PERR_MC_RSPDATA)
+#define F_PERR_MC_RSPDATA    V_PERR_MC_RSPDATA(1U)
+
+#define S_PERR_PC_RSPDATA    29
+#define V_PERR_PC_RSPDATA(x) ((x) << S_PERR_PC_RSPDATA)
+#define F_PERR_PC_RSPDATA    V_PERR_PC_RSPDATA(1U)
+
+#define S_PERR_PD_RDRSPDATA    28
+#define V_PERR_PD_RDRSPDATA(x) ((x) << S_PERR_PD_RDRSPDATA)
+#define F_PERR_PD_RDRSPDATA    V_PERR_PD_RDRSPDATA(1U)
+
+#define S_PERR_U_RXDATA    27
+#define V_PERR_U_RXDATA(x) ((x) << S_PERR_U_RXDATA)
+#define F_PERR_U_RXDATA    V_PERR_U_RXDATA(1U)
+
+#define S_PERR_UD_RXDATA    26
+#define V_PERR_UD_RXDATA(x) ((x) << S_PERR_UD_RXDATA)
+#define F_PERR_UD_RXDATA    V_PERR_UD_RXDATA(1U)
+
+#define S_PERR_UP_DATA    25
+#define V_PERR_UP_DATA(x) ((x) << S_PERR_UP_DATA)
+#define F_PERR_UP_DATA    V_PERR_UP_DATA(1U)
+
+#define S_PERR_CIM2SGE_RXDATA    24
+#define V_PERR_CIM2SGE_RXDATA(x) ((x) << S_PERR_CIM2SGE_RXDATA)
+#define F_PERR_CIM2SGE_RXDATA    V_PERR_CIM2SGE_RXDATA(1U)
+
+#define S_PERR_HINT_DELAY_FIFO1_T5    23
+#define V_PERR_HINT_DELAY_FIFO1_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO1_T5)
+#define F_PERR_HINT_DELAY_FIFO1_T5    V_PERR_HINT_DELAY_FIFO1_T5(1U)
+
+#define S_PERR_HINT_DELAY_FIFO0_T5    22
+#define V_PERR_HINT_DELAY_FIFO0_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO0_T5)
+#define F_PERR_HINT_DELAY_FIFO0_T5    V_PERR_HINT_DELAY_FIFO0_T5(1U)
+
+#define S_PERR_IMSG_PD_FIFO_T5    21
+#define V_PERR_IMSG_PD_FIFO_T5(x) ((x) << S_PERR_IMSG_PD_FIFO_T5)
+#define F_PERR_IMSG_PD_FIFO_T5    V_PERR_IMSG_PD_FIFO_T5(1U)
+
+#define S_PERR_ULPTX_FIFO1_T5    20
+#define V_PERR_ULPTX_FIFO1_T5(x) ((x) << S_PERR_ULPTX_FIFO1_T5)
+#define F_PERR_ULPTX_FIFO1_T5    V_PERR_ULPTX_FIFO1_T5(1U)
+
+#define S_PERR_ULPTX_FIFO0_T5    19
+#define V_PERR_ULPTX_FIFO0_T5(x) ((x) << S_PERR_ULPTX_FIFO0_T5)
+#define F_PERR_ULPTX_FIFO0_T5    V_PERR_ULPTX_FIFO0_T5(1U)
+
+#define S_PERR_IDMA2IMSG_FIFO1_T5    18
+#define V_PERR_IDMA2IMSG_FIFO1_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO1_T5)
+#define F_PERR_IDMA2IMSG_FIFO1_T5    V_PERR_IDMA2IMSG_FIFO1_T5(1U)
+
+#define S_PERR_IDMA2IMSG_FIFO0_T5    17
+#define V_PERR_IDMA2IMSG_FIFO0_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO0_T5)
+#define F_PERR_IDMA2IMSG_FIFO0_T5    V_PERR_IDMA2IMSG_FIFO0_T5(1U)
+
+#define S_PERR_POINTER_DATA_FIFO0    16
+#define V_PERR_POINTER_DATA_FIFO0(x) ((x) << S_PERR_POINTER_DATA_FIFO0)
+#define F_PERR_POINTER_DATA_FIFO0    V_PERR_POINTER_DATA_FIFO0(1U)
+
+#define S_PERR_POINTER_DATA_FIFO1    15
+#define V_PERR_POINTER_DATA_FIFO1(x) ((x) << S_PERR_POINTER_DATA_FIFO1)
+#define F_PERR_POINTER_DATA_FIFO1    V_PERR_POINTER_DATA_FIFO1(1U)
+
+#define S_PERR_POINTER_HDR_FIFO0    14
+#define V_PERR_POINTER_HDR_FIFO0(x) ((x) << S_PERR_POINTER_HDR_FIFO0)
+#define F_PERR_POINTER_HDR_FIFO0    V_PERR_POINTER_HDR_FIFO0(1U)
+
+#define S_PERR_POINTER_HDR_FIFO1    13
+#define V_PERR_POINTER_HDR_FIFO1(x) ((x) << S_PERR_POINTER_HDR_FIFO1)
+#define F_PERR_POINTER_HDR_FIFO1    V_PERR_POINTER_HDR_FIFO1(1U)
+
+#define S_PERR_PAYLOAD_FIFO0    12
+#define V_PERR_PAYLOAD_FIFO0(x) ((x) << S_PERR_PAYLOAD_FIFO0)
+#define F_PERR_PAYLOAD_FIFO0    V_PERR_PAYLOAD_FIFO0(1U)
+
+#define S_PERR_PAYLOAD_FIFO1    11
+#define V_PERR_PAYLOAD_FIFO1(x) ((x) << S_PERR_PAYLOAD_FIFO1)
+#define F_PERR_PAYLOAD_FIFO1    V_PERR_PAYLOAD_FIFO1(1U)
+
+#define S_PERR_EDMA_INPUT_FIFO3    10
+#define V_PERR_EDMA_INPUT_FIFO3(x) ((x) << S_PERR_EDMA_INPUT_FIFO3)
+#define F_PERR_EDMA_INPUT_FIFO3    V_PERR_EDMA_INPUT_FIFO3(1U)
+
+#define S_PERR_EDMA_INPUT_FIFO2    9
+#define V_PERR_EDMA_INPUT_FIFO2(x) ((x) << S_PERR_EDMA_INPUT_FIFO2)
+#define F_PERR_EDMA_INPUT_FIFO2    V_PERR_EDMA_INPUT_FIFO2(1U)
+
+#define S_PERR_EDMA_INPUT_FIFO1    8
+#define V_PERR_EDMA_INPUT_FIFO1(x) ((x) << S_PERR_EDMA_INPUT_FIFO1)
+#define F_PERR_EDMA_INPUT_FIFO1    V_PERR_EDMA_INPUT_FIFO1(1U)
+
+#define S_PERR_EDMA_INPUT_FIFO0    7
+#define V_PERR_EDMA_INPUT_FIFO0(x) ((x) << S_PERR_EDMA_INPUT_FIFO0)
+#define F_PERR_EDMA_INPUT_FIFO0    V_PERR_EDMA_INPUT_FIFO0(1U)
+
+#define S_PERR_MGT_BAR2_FIFO    6
+#define V_PERR_MGT_BAR2_FIFO(x) ((x) << S_PERR_MGT_BAR2_FIFO)
+#define F_PERR_MGT_BAR2_FIFO    V_PERR_MGT_BAR2_FIFO(1U)
+
+#define S_PERR_HEADERSPLIT_FIFO1_T5    5
+#define V_PERR_HEADERSPLIT_FIFO1_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO1_T5)
+#define F_PERR_HEADERSPLIT_FIFO1_T5    V_PERR_HEADERSPLIT_FIFO1_T5(1U)
+
+#define S_PERR_HEADERSPLIT_FIFO0_T5    4
+#define V_PERR_HEADERSPLIT_FIFO0_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO0_T5)
+#define F_PERR_HEADERSPLIT_FIFO0_T5    V_PERR_HEADERSPLIT_FIFO0_T5(1U)
+
+#define S_PERR_CIM_FIFO1    3
+#define V_PERR_CIM_FIFO1(x) ((x) << S_PERR_CIM_FIFO1)
+#define F_PERR_CIM_FIFO1    V_PERR_CIM_FIFO1(1U)
+
+#define S_PERR_CIM_FIFO0    2
+#define V_PERR_CIM_FIFO0(x) ((x) << S_PERR_CIM_FIFO0)
+#define F_PERR_CIM_FIFO0    V_PERR_CIM_FIFO0(1U)
+
+#define S_PERR_IDMA_SWITCH_OUTPUT_FIFO1    1
+#define V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO1)
+#define F_PERR_IDMA_SWITCH_OUTPUT_FIFO1    V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(1U)
+
+#define S_PERR_IDMA_SWITCH_OUTPUT_FIFO0    0
+#define V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO0)
+#define F_PERR_IDMA_SWITCH_OUTPUT_FIFO0    V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(1U)
+
+#define A_SGE_INT_ENABLE5 0x1110
+#define A_SGE_PERR_ENABLE5 0x1114
+#define A_SGE_DBFIFO_STATUS2 0x1118
+
+#define S_FL_INT_THRESH    24
+#define M_FL_INT_THRESH    0xfU
+#define V_FL_INT_THRESH(x) ((x) << S_FL_INT_THRESH)
+#define G_FL_INT_THRESH(x) (((x) >> S_FL_INT_THRESH) & M_FL_INT_THRESH)
+
+#define S_FL_COUNT    14
+#define M_FL_COUNT    0x3ffU
+#define V_FL_COUNT(x) ((x) << S_FL_COUNT)
+#define G_FL_COUNT(x) (((x) >> S_FL_COUNT) & M_FL_COUNT)
+
+#define S_HP_INT_THRESH_T5    10
+#define M_HP_INT_THRESH_T5    0xfU
+#define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5)
+#define G_HP_INT_THRESH_T5(x) (((x) >> S_HP_INT_THRESH_T5) & M_HP_INT_THRESH_T5)
+
+#define S_HP_COUNT_T5    0
+#define M_HP_COUNT_T5    0x3ffU
+#define V_HP_COUNT_T5(x) ((x) << S_HP_COUNT_T5)
+#define G_HP_COUNT_T5(x) (((x) >> S_HP_COUNT_T5) & M_HP_COUNT_T5)
+
+#define A_SGE_FETCH_BURST_MAX_0_AND_1 0x111c
+
+#define S_FETCHBURSTMAX0    16
+#define M_FETCHBURSTMAX0    0x3ffU
+#define V_FETCHBURSTMAX0(x) ((x) << S_FETCHBURSTMAX0)
+#define G_FETCHBURSTMAX0(x) (((x) >> S_FETCHBURSTMAX0) & M_FETCHBURSTMAX0)
+
+#define S_FETCHBURSTMAX1    0
+#define M_FETCHBURSTMAX1    0x3ffU
+#define V_FETCHBURSTMAX1(x) ((x) << S_FETCHBURSTMAX1)
+#define G_FETCHBURSTMAX1(x) (((x) >> S_FETCHBURSTMAX1) & M_FETCHBURSTMAX1)
+
+#define A_SGE_FETCH_BURST_MAX_2_AND_3 0x1120
+
+#define S_FETCHBURSTMAX2    16
+#define M_FETCHBURSTMAX2    0x3ffU
+#define V_FETCHBURSTMAX2(x) ((x) << S_FETCHBURSTMAX2)
+#define G_FETCHBURSTMAX2(x) (((x) >> S_FETCHBURSTMAX2) & M_FETCHBURSTMAX2)
+
+#define S_FETCHBURSTMAX3    0
+#define M_FETCHBURSTMAX3    0x3ffU
+#define V_FETCHBURSTMAX3(x) ((x) << S_FETCHBURSTMAX3)
+#define G_FETCHBURSTMAX3(x) (((x) >> S_FETCHBURSTMAX3) & M_FETCHBURSTMAX3)
+
+#define A_SGE_CONTROL2 0x1124
+
+#define S_UPFLCUTOFFDIS    21
+#define V_UPFLCUTOFFDIS(x) ((x) << S_UPFLCUTOFFDIS)
+#define F_UPFLCUTOFFDIS    V_UPFLCUTOFFDIS(1U)
+
+#define S_RXCPLSIZEAUTOCORRECT    20
+#define V_RXCPLSIZEAUTOCORRECT(x) ((x) << S_RXCPLSIZEAUTOCORRECT)
+#define F_RXCPLSIZEAUTOCORRECT    V_RXCPLSIZEAUTOCORRECT(1U)
+
+#define S_IDMAARBROUNDROBIN    19
+#define V_IDMAARBROUNDROBIN(x) ((x) << S_IDMAARBROUNDROBIN)
+#define F_IDMAARBROUNDROBIN    V_IDMAARBROUNDROBIN(1U)
+
+#define S_INGPACKBOUNDARY    16
+#define M_INGPACKBOUNDARY    0x7U
+#define V_INGPACKBOUNDARY(x) ((x) << S_INGPACKBOUNDARY)
+#define G_INGPACKBOUNDARY(x) (((x) >> S_INGPACKBOUNDARY) & M_INGPACKBOUNDARY)
+
+#define S_CGEN_EGRESS_CONTEXT    15
+#define V_CGEN_EGRESS_CONTEXT(x) ((x) << S_CGEN_EGRESS_CONTEXT)
+#define F_CGEN_EGRESS_CONTEXT    V_CGEN_EGRESS_CONTEXT(1U)
+
+#define S_CGEN_INGRESS_CONTEXT    14
+#define V_CGEN_INGRESS_CONTEXT(x) ((x) << S_CGEN_INGRESS_CONTEXT)
+#define F_CGEN_INGRESS_CONTEXT    V_CGEN_INGRESS_CONTEXT(1U)
+
+#define S_CGEN_IDMA    13
+#define V_CGEN_IDMA(x) ((x) << S_CGEN_IDMA)
+#define F_CGEN_IDMA    V_CGEN_IDMA(1U)
+
+#define S_CGEN_DBP    12
+#define V_CGEN_DBP(x) ((x) << S_CGEN_DBP)
+#define F_CGEN_DBP    V_CGEN_DBP(1U)
+
+#define S_CGEN_EDMA    11
+#define V_CGEN_EDMA(x) ((x) << S_CGEN_EDMA)
+#define F_CGEN_EDMA    V_CGEN_EDMA(1U)
+
+#define S_VFIFO_ENABLE    10
+#define V_VFIFO_ENABLE(x) ((x) << S_VFIFO_ENABLE)
+#define F_VFIFO_ENABLE    V_VFIFO_ENABLE(1U)
+
+#define S_FLM_RESCHEDULE_MODE    9
+#define V_FLM_RESCHEDULE_MODE(x) ((x) << S_FLM_RESCHEDULE_MODE)
+#define F_FLM_RESCHEDULE_MODE    V_FLM_RESCHEDULE_MODE(1U)
+
+#define S_HINTDEPTHCTLFL    4
+#define M_HINTDEPTHCTLFL    0x1fU
+#define V_HINTDEPTHCTLFL(x) ((x) << S_HINTDEPTHCTLFL)
+#define G_HINTDEPTHCTLFL(x) (((x) >> S_HINTDEPTHCTLFL) & M_HINTDEPTHCTLFL)
+
+#define S_FORCE_ORDERING    3
+#define V_FORCE_ORDERING(x) ((x) << S_FORCE_ORDERING)
+#define F_FORCE_ORDERING    V_FORCE_ORDERING(1U)
+
+#define S_TX_COALESCE_SIZE    2
+#define V_TX_COALESCE_SIZE(x) ((x) << S_TX_COALESCE_SIZE)
+#define F_TX_COALESCE_SIZE    V_TX_COALESCE_SIZE(1U)
+
+#define S_COAL_STRICT_CIM_PRI    1
+#define V_COAL_STRICT_CIM_PRI(x) ((x) << S_COAL_STRICT_CIM_PRI)
+#define F_COAL_STRICT_CIM_PRI    V_COAL_STRICT_CIM_PRI(1U)
+
+#define S_TX_COALESCE_PRI    0
+#define V_TX_COALESCE_PRI(x) ((x) << S_TX_COALESCE_PRI)
+#define F_TX_COALESCE_PRI    V_TX_COALESCE_PRI(1U)
+
+#define A_SGE_DEEP_SLEEP 0x1128
+
+#define S_IDMA1_SLEEP_STATUS    11
+#define V_IDMA1_SLEEP_STATUS(x) ((x) << S_IDMA1_SLEEP_STATUS)
+#define F_IDMA1_SLEEP_STATUS    V_IDMA1_SLEEP_STATUS(1U)
+
+#define S_IDMA0_SLEEP_STATUS    10
+#define V_IDMA0_SLEEP_STATUS(x) ((x) << S_IDMA0_SLEEP_STATUS)
+#define F_IDMA0_SLEEP_STATUS    V_IDMA0_SLEEP_STATUS(1U)
+
+#define S_IDMA1_SLEEP_REQ    9
+#define V_IDMA1_SLEEP_REQ(x) ((x) << S_IDMA1_SLEEP_REQ)
+#define F_IDMA1_SLEEP_REQ    V_IDMA1_SLEEP_REQ(1U)
+
+#define S_IDMA0_SLEEP_REQ    8
+#define V_IDMA0_SLEEP_REQ(x) ((x) << S_IDMA0_SLEEP_REQ)
+#define F_IDMA0_SLEEP_REQ    V_IDMA0_SLEEP_REQ(1U)
+
+#define S_EDMA3_SLEEP_STATUS    7
+#define V_EDMA3_SLEEP_STATUS(x) ((x) << S_EDMA3_SLEEP_STATUS)
+#define F_EDMA3_SLEEP_STATUS    V_EDMA3_SLEEP_STATUS(1U)
+
+#define S_EDMA2_SLEEP_STATUS    6
+#define V_EDMA2_SLEEP_STATUS(x) ((x) << S_EDMA2_SLEEP_STATUS)
+#define F_EDMA2_SLEEP_STATUS    V_EDMA2_SLEEP_STATUS(1U)
+
+#define S_EDMA1_SLEEP_STATUS    5
+#define V_EDMA1_SLEEP_STATUS(x) ((x) << S_EDMA1_SLEEP_STATUS)
+#define F_EDMA1_SLEEP_STATUS    V_EDMA1_SLEEP_STATUS(1U)
+
+#define S_EDMA0_SLEEP_STATUS    4
+#define V_EDMA0_SLEEP_STATUS(x) ((x) << S_EDMA0_SLEEP_STATUS)
+#define F_EDMA0_SLEEP_STATUS    V_EDMA0_SLEEP_STATUS(1U)
+
+#define S_EDMA3_SLEEP_REQ    3
+#define V_EDMA3_SLEEP_REQ(x) ((x) << S_EDMA3_SLEEP_REQ)
+#define F_EDMA3_SLEEP_REQ    V_EDMA3_SLEEP_REQ(1U)
+
+#define S_EDMA2_SLEEP_REQ    2
+#define V_EDMA2_SLEEP_REQ(x) ((x) << S_EDMA2_SLEEP_REQ)
+#define F_EDMA2_SLEEP_REQ    V_EDMA2_SLEEP_REQ(1U)
+
+#define S_EDMA1_SLEEP_REQ    1
+#define V_EDMA1_SLEEP_REQ(x) ((x) << S_EDMA1_SLEEP_REQ)
+#define F_EDMA1_SLEEP_REQ    V_EDMA1_SLEEP_REQ(1U)
+
+#define S_EDMA0_SLEEP_REQ    0
+#define V_EDMA0_SLEEP_REQ(x) ((x) << S_EDMA0_SLEEP_REQ)
+#define F_EDMA0_SLEEP_REQ    V_EDMA0_SLEEP_REQ(1U)
+
+#define A_SGE_DOORBELL_THROTTLE_THRESHOLD 0x112c
+
+#define S_THROTTLE_THRESHOLD_FL    16
+#define M_THROTTLE_THRESHOLD_FL    0xfU
+#define V_THROTTLE_THRESHOLD_FL(x) ((x) << S_THROTTLE_THRESHOLD_FL)
+#define G_THROTTLE_THRESHOLD_FL(x) (((x) >> S_THROTTLE_THRESHOLD_FL) & M_THROTTLE_THRESHOLD_FL)
+
+#define S_THROTTLE_THRESHOLD_HP    12
+#define M_THROTTLE_THRESHOLD_HP    0xfU
+#define V_THROTTLE_THRESHOLD_HP(x) ((x) << S_THROTTLE_THRESHOLD_HP)
+#define G_THROTTLE_THRESHOLD_HP(x) (((x) >> S_THROTTLE_THRESHOLD_HP) & M_THROTTLE_THRESHOLD_HP)
+
+#define S_THROTTLE_THRESHOLD_LP    0
+#define M_THROTTLE_THRESHOLD_LP    0xfffU
+#define V_THROTTLE_THRESHOLD_LP(x) ((x) << S_THROTTLE_THRESHOLD_LP)
+#define G_THROTTLE_THRESHOLD_LP(x) (((x) >> S_THROTTLE_THRESHOLD_LP) & M_THROTTLE_THRESHOLD_LP)
+
+#define A_SGE_DBP_FETCH_THRESHOLD 0x1130
+
+#define S_DBP_FETCH_THRESHOLD_FL    21
+#define M_DBP_FETCH_THRESHOLD_FL    0xfU
+#define V_DBP_FETCH_THRESHOLD_FL(x) ((x) << S_DBP_FETCH_THRESHOLD_FL)
+#define G_DBP_FETCH_THRESHOLD_FL(x) (((x) >> S_DBP_FETCH_THRESHOLD_FL) & M_DBP_FETCH_THRESHOLD_FL)
+
+#define S_DBP_FETCH_THRESHOLD_HP    17
+#define M_DBP_FETCH_THRESHOLD_HP    0xfU
+#define V_DBP_FETCH_THRESHOLD_HP(x) ((x) << S_DBP_FETCH_THRESHOLD_HP)
+#define G_DBP_FETCH_THRESHOLD_HP(x) (((x) >> S_DBP_FETCH_THRESHOLD_HP) & M_DBP_FETCH_THRESHOLD_HP)
+
+#define S_DBP_FETCH_THRESHOLD_LP    5
+#define M_DBP_FETCH_THRESHOLD_LP    0xfffU
+#define V_DBP_FETCH_THRESHOLD_LP(x) ((x) << S_DBP_FETCH_THRESHOLD_LP)
+#define G_DBP_FETCH_THRESHOLD_LP(x) (((x) >> S_DBP_FETCH_THRESHOLD_LP) & M_DBP_FETCH_THRESHOLD_LP)
+
+#define S_DBP_FETCH_THRESHOLD_MODE    4
+#define V_DBP_FETCH_THRESHOLD_MODE(x) ((x) << S_DBP_FETCH_THRESHOLD_MODE)
+#define F_DBP_FETCH_THRESHOLD_MODE    V_DBP_FETCH_THRESHOLD_MODE(1U)
+
+#define S_DBP_FETCH_THRESHOLD_EN3    3
+#define V_DBP_FETCH_THRESHOLD_EN3(x) ((x) << S_DBP_FETCH_THRESHOLD_EN3)
+#define F_DBP_FETCH_THRESHOLD_EN3    V_DBP_FETCH_THRESHOLD_EN3(1U)
+
+#define S_DBP_FETCH_THRESHOLD_EN2    2
+#define V_DBP_FETCH_THRESHOLD_EN2(x) ((x) << S_DBP_FETCH_THRESHOLD_EN2)
+#define F_DBP_FETCH_THRESHOLD_EN2    V_DBP_FETCH_THRESHOLD_EN2(1U)
+
+#define S_DBP_FETCH_THRESHOLD_EN1    1
+#define V_DBP_FETCH_THRESHOLD_EN1(x) ((x) << S_DBP_FETCH_THRESHOLD_EN1)
+#define F_DBP_FETCH_THRESHOLD_EN1    V_DBP_FETCH_THRESHOLD_EN1(1U)
+
+#define S_DBP_FETCH_THRESHOLD_EN0    0
+#define V_DBP_FETCH_THRESHOLD_EN0(x) ((x) << S_DBP_FETCH_THRESHOLD_EN0)
+#define F_DBP_FETCH_THRESHOLD_EN0    V_DBP_FETCH_THRESHOLD_EN0(1U)
+
+#define A_SGE_DBP_FETCH_THRESHOLD_QUEUE 0x1134
+
+#define S_DBP_FETCH_THRESHOLD_IQ1    16
+#define M_DBP_FETCH_THRESHOLD_IQ1    0xffffU
+#define V_DBP_FETCH_THRESHOLD_IQ1(x) ((x) << S_DBP_FETCH_THRESHOLD_IQ1)
+#define G_DBP_FETCH_THRESHOLD_IQ1(x) (((x) >> S_DBP_FETCH_THRESHOLD_IQ1) & M_DBP_FETCH_THRESHOLD_IQ1)
+
+#define S_DBP_FETCH_THRESHOLD_IQ0    0
+#define M_DBP_FETCH_THRESHOLD_IQ0    0xffffU
+#define V_DBP_FETCH_THRESHOLD_IQ0(x) ((x) << S_DBP_FETCH_THRESHOLD_IQ0)
+#define G_DBP_FETCH_THRESHOLD_IQ0(x) (((x) >> S_DBP_FETCH_THRESHOLD_IQ0) & M_DBP_FETCH_THRESHOLD_IQ0)
+
+#define A_SGE_DBVFIFO_BADDR 0x1138
+#define A_SGE_DBVFIFO_SIZE 0x113c
+
+#define S_DBVFIFO_SIZE    6
+#define M_DBVFIFO_SIZE    0xfffU
+#define V_DBVFIFO_SIZE(x) ((x) << S_DBVFIFO_SIZE)
+#define G_DBVFIFO_SIZE(x) (((x) >> S_DBVFIFO_SIZE) & M_DBVFIFO_SIZE)
+
+#define A_SGE_DBFIFO_STATUS3 0x1140
+
+#define S_LP_PTRS_EQUAL    21
+#define V_LP_PTRS_EQUAL(x) ((x) << S_LP_PTRS_EQUAL)
+#define F_LP_PTRS_EQUAL    V_LP_PTRS_EQUAL(1U)
+
+#define S_LP_SNAPHOT    20
+#define V_LP_SNAPHOT(x) ((x) << S_LP_SNAPHOT)
+#define F_LP_SNAPHOT    V_LP_SNAPHOT(1U)
+
+#define S_FL_INT_THRESH_LOW    16
+#define M_FL_INT_THRESH_LOW    0xfU
+#define V_FL_INT_THRESH_LOW(x) ((x) << S_FL_INT_THRESH_LOW)
+#define G_FL_INT_THRESH_LOW(x) (((x) >> S_FL_INT_THRESH_LOW) & M_FL_INT_THRESH_LOW)
+
+#define S_HP_INT_THRESH_LOW    12
+#define M_HP_INT_THRESH_LOW    0xfU
+#define V_HP_INT_THRESH_LOW(x) ((x) << S_HP_INT_THRESH_LOW)
+#define G_HP_INT_THRESH_LOW(x) (((x) >> S_HP_INT_THRESH_LOW) & M_HP_INT_THRESH_LOW)
+
+#define S_LP_INT_THRESH_LOW    0
+#define M_LP_INT_THRESH_LOW    0xfffU
+#define V_LP_INT_THRESH_LOW(x) ((x) << S_LP_INT_THRESH_LOW)
+#define G_LP_INT_THRESH_LOW(x) (((x) >> S_LP_INT_THRESH_LOW) & M_LP_INT_THRESH_LOW)
+
+#define A_SGE_CHANGESET 0x1144
+#define A_SGE_PC_RSP_ERROR 0x1148
+#define A_SGE_PC0_REQ_BIST_CMD 0x1180
+#define A_SGE_PC0_REQ_BIST_ERROR_CNT 0x1184
+#define A_SGE_PC1_REQ_BIST_CMD 0x1190
+#define A_SGE_PC1_REQ_BIST_ERROR_CNT 0x1194
+#define A_SGE_PC0_RSP_BIST_CMD 0x11a0
+#define A_SGE_PC0_RSP_BIST_ERROR_CNT 0x11a4
+#define A_SGE_PC1_RSP_BIST_CMD 0x11b0
+#define A_SGE_PC1_RSP_BIST_ERROR_CNT 0x11b4
+#define A_SGE_CTXT_CMD 0x11fc
+
+#define S_BUSY    31
+#define V_BUSY(x) ((x) << S_BUSY)
+#define F_BUSY    V_BUSY(1U)
+
+#define S_CTXTOP    28
+#define M_CTXTOP    0x3U
+#define V_CTXTOP(x) ((x) << S_CTXTOP)
+#define G_CTXTOP(x) (((x) >> S_CTXTOP) & M_CTXTOP)
+
+#define S_CTXTTYPE    24
+#define M_CTXTTYPE    0x3U
+#define V_CTXTTYPE(x) ((x) << S_CTXTTYPE)
+#define G_CTXTTYPE(x) (((x) >> S_CTXTTYPE) & M_CTXTTYPE)
+
+#define S_CTXTQID    0
+#define M_CTXTQID    0x1ffffU
+#define V_CTXTQID(x) ((x) << S_CTXTQID)
+#define G_CTXTQID(x) (((x) >> S_CTXTQID) & M_CTXTQID)
+
+#define A_SGE_CTXT_DATA0 0x1200
+#define A_SGE_CTXT_DATA1 0x1204
+#define A_SGE_CTXT_DATA2 0x1208
+#define A_SGE_CTXT_DATA3 0x120c
+#define A_SGE_CTXT_DATA4 0x1210
+#define A_SGE_CTXT_DATA5 0x1214
+#define A_SGE_CTXT_DATA6 0x1218
+#define A_SGE_CTXT_DATA7 0x121c
+#define A_SGE_CTXT_MASK0 0x1220
+#define A_SGE_CTXT_MASK1 0x1224
+#define A_SGE_CTXT_MASK2 0x1228
+#define A_SGE_CTXT_MASK3 0x122c
+#define A_SGE_CTXT_MASK4 0x1230
+#define A_SGE_CTXT_MASK5 0x1234
+#define A_SGE_CTXT_MASK6 0x1238
+#define A_SGE_CTXT_MASK7 0x123c
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_0 0x1280
+
+#define S_CIM_WM    24
+#define M_CIM_WM    0x3U
+#define V_CIM_WM(x) ((x) << S_CIM_WM)
+#define G_CIM_WM(x) (((x) >> S_CIM_WM) & M_CIM_WM)
+
+#define S_DEBUG_UP_SOP_CNT    20
+#define M_DEBUG_UP_SOP_CNT    0xfU
+#define V_DEBUG_UP_SOP_CNT(x) ((x) << S_DEBUG_UP_SOP_CNT)
+#define G_DEBUG_UP_SOP_CNT(x) (((x) >> S_DEBUG_UP_SOP_CNT) & M_DEBUG_UP_SOP_CNT)
+
+#define S_DEBUG_UP_EOP_CNT    16
+#define M_DEBUG_UP_EOP_CNT    0xfU
+#define V_DEBUG_UP_EOP_CNT(x) ((x) << S_DEBUG_UP_EOP_CNT)
+#define G_DEBUG_UP_EOP_CNT(x) (((x) >> S_DEBUG_UP_EOP_CNT) & M_DEBUG_UP_EOP_CNT)
+
+#define S_DEBUG_CIM_SOP1_CNT    12
+#define M_DEBUG_CIM_SOP1_CNT    0xfU
+#define V_DEBUG_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CIM_SOP1_CNT)
+#define G_DEBUG_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CIM_SOP1_CNT) & M_DEBUG_CIM_SOP1_CNT)
+
+#define S_DEBUG_CIM_EOP1_CNT    8
+#define M_DEBUG_CIM_EOP1_CNT    0xfU
+#define V_DEBUG_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CIM_EOP1_CNT)
+#define G_DEBUG_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CIM_EOP1_CNT) & M_DEBUG_CIM_EOP1_CNT)
+
+#define S_DEBUG_CIM_SOP0_CNT    4
+#define M_DEBUG_CIM_SOP0_CNT    0xfU
+#define V_DEBUG_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CIM_SOP0_CNT)
+#define G_DEBUG_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CIM_SOP0_CNT) & M_DEBUG_CIM_SOP0_CNT)
+
+#define S_DEBUG_CIM_EOP0_CNT    0
+#define M_DEBUG_CIM_EOP0_CNT    0xfU
+#define V_DEBUG_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CIM_EOP0_CNT)
+#define G_DEBUG_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CIM_EOP0_CNT) & M_DEBUG_CIM_EOP0_CNT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_1 0x1284
+
+#define S_DEBUG_T_RX_SOP1_CNT    28
+#define M_DEBUG_T_RX_SOP1_CNT    0xfU
+#define V_DEBUG_T_RX_SOP1_CNT(x) ((x) << S_DEBUG_T_RX_SOP1_CNT)
+#define G_DEBUG_T_RX_SOP1_CNT(x) (((x) >> S_DEBUG_T_RX_SOP1_CNT) & M_DEBUG_T_RX_SOP1_CNT)
+
+#define S_DEBUG_T_RX_EOP1_CNT    24
+#define M_DEBUG_T_RX_EOP1_CNT    0xfU
+#define V_DEBUG_T_RX_EOP1_CNT(x) ((x) << S_DEBUG_T_RX_EOP1_CNT)
+#define G_DEBUG_T_RX_EOP1_CNT(x) (((x) >> S_DEBUG_T_RX_EOP1_CNT) & M_DEBUG_T_RX_EOP1_CNT)
+
+#define S_DEBUG_T_RX_SOP0_CNT    20
+#define M_DEBUG_T_RX_SOP0_CNT    0xfU
+#define V_DEBUG_T_RX_SOP0_CNT(x) ((x) << S_DEBUG_T_RX_SOP0_CNT)
+#define G_DEBUG_T_RX_SOP0_CNT(x) (((x) >> S_DEBUG_T_RX_SOP0_CNT) & M_DEBUG_T_RX_SOP0_CNT)
+
+#define S_DEBUG_T_RX_EOP0_CNT    16
+#define M_DEBUG_T_RX_EOP0_CNT    0xfU
+#define V_DEBUG_T_RX_EOP0_CNT(x) ((x) << S_DEBUG_T_RX_EOP0_CNT)
+#define G_DEBUG_T_RX_EOP0_CNT(x) (((x) >> S_DEBUG_T_RX_EOP0_CNT) & M_DEBUG_T_RX_EOP0_CNT)
+
+#define S_DEBUG_U_RX_SOP1_CNT    12
+#define M_DEBUG_U_RX_SOP1_CNT    0xfU
+#define V_DEBUG_U_RX_SOP1_CNT(x) ((x) << S_DEBUG_U_RX_SOP1_CNT)
+#define G_DEBUG_U_RX_SOP1_CNT(x) (((x) >> S_DEBUG_U_RX_SOP1_CNT) & M_DEBUG_U_RX_SOP1_CNT)
+
+#define S_DEBUG_U_RX_EOP1_CNT    8
+#define M_DEBUG_U_RX_EOP1_CNT    0xfU
+#define V_DEBUG_U_RX_EOP1_CNT(x) ((x) << S_DEBUG_U_RX_EOP1_CNT)
+#define G_DEBUG_U_RX_EOP1_CNT(x) (((x) >> S_DEBUG_U_RX_EOP1_CNT) & M_DEBUG_U_RX_EOP1_CNT)
+
+#define S_DEBUG_U_RX_SOP0_CNT    4
+#define M_DEBUG_U_RX_SOP0_CNT    0xfU
+#define V_DEBUG_U_RX_SOP0_CNT(x) ((x) << S_DEBUG_U_RX_SOP0_CNT)
+#define G_DEBUG_U_RX_SOP0_CNT(x) (((x) >> S_DEBUG_U_RX_SOP0_CNT) & M_DEBUG_U_RX_SOP0_CNT)
+
+#define S_DEBUG_U_RX_EOP0_CNT    0
+#define M_DEBUG_U_RX_EOP0_CNT    0xfU
+#define V_DEBUG_U_RX_EOP0_CNT(x) ((x) << S_DEBUG_U_RX_EOP0_CNT)
+#define G_DEBUG_U_RX_EOP0_CNT(x) (((x) >> S_DEBUG_U_RX_EOP0_CNT) & M_DEBUG_U_RX_EOP0_CNT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_2 0x1288
+
+#define S_DEBUG_UD_RX_SOP3_CNT    28
+#define M_DEBUG_UD_RX_SOP3_CNT    0xfU
+#define V_DEBUG_UD_RX_SOP3_CNT(x) ((x) << S_DEBUG_UD_RX_SOP3_CNT)
+#define G_DEBUG_UD_RX_SOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP3_CNT) & M_DEBUG_UD_RX_SOP3_CNT)
+
+#define S_DEBUG_UD_RX_EOP3_CNT    24
+#define M_DEBUG_UD_RX_EOP3_CNT    0xfU
+#define V_DEBUG_UD_RX_EOP3_CNT(x) ((x) << S_DEBUG_UD_RX_EOP3_CNT)
+#define G_DEBUG_UD_RX_EOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP3_CNT) & M_DEBUG_UD_RX_EOP3_CNT)
+
+#define S_DEBUG_UD_RX_SOP2_CNT    20
+#define M_DEBUG_UD_RX_SOP2_CNT    0xfU
+#define V_DEBUG_UD_RX_SOP2_CNT(x) ((x) << S_DEBUG_UD_RX_SOP2_CNT)
+#define G_DEBUG_UD_RX_SOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP2_CNT) & M_DEBUG_UD_RX_SOP2_CNT)
+
+#define S_DEBUG_UD_RX_EOP2_CNT    16
+#define M_DEBUG_UD_RX_EOP2_CNT    0xfU
+#define V_DEBUG_UD_RX_EOP2_CNT(x) ((x) << S_DEBUG_UD_RX_EOP2_CNT)
+#define G_DEBUG_UD_RX_EOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP2_CNT) & M_DEBUG_UD_RX_EOP2_CNT)
+
+#define S_DEBUG_UD_RX_SOP1_CNT    12
+#define M_DEBUG_UD_RX_SOP1_CNT    0xfU
+#define V_DEBUG_UD_RX_SOP1_CNT(x) ((x) << S_DEBUG_UD_RX_SOP1_CNT)
+#define G_DEBUG_UD_RX_SOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP1_CNT) & M_DEBUG_UD_RX_SOP1_CNT)
+
+#define S_DEBUG_UD_RX_EOP1_CNT    8
+#define M_DEBUG_UD_RX_EOP1_CNT    0xfU
+#define V_DEBUG_UD_RX_EOP1_CNT(x) ((x) << S_DEBUG_UD_RX_EOP1_CNT)
+#define G_DEBUG_UD_RX_EOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP1_CNT) & M_DEBUG_UD_RX_EOP1_CNT)
+
+#define S_DEBUG_UD_RX_SOP0_CNT    4
+#define M_DEBUG_UD_RX_SOP0_CNT    0xfU
+#define V_DEBUG_UD_RX_SOP0_CNT(x) ((x) << S_DEBUG_UD_RX_SOP0_CNT)
+#define G_DEBUG_UD_RX_SOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP0_CNT) & M_DEBUG_UD_RX_SOP0_CNT)
+
+#define S_DEBUG_UD_RX_EOP0_CNT    0
+#define M_DEBUG_UD_RX_EOP0_CNT    0xfU
+#define V_DEBUG_UD_RX_EOP0_CNT(x) ((x) << S_DEBUG_UD_RX_EOP0_CNT)
+#define G_DEBUG_UD_RX_EOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP0_CNT) & M_DEBUG_UD_RX_EOP0_CNT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_3 0x128c
+
+#define S_DEBUG_U_TX_SOP3_CNT    28
+#define M_DEBUG_U_TX_SOP3_CNT    0xfU
+#define V_DEBUG_U_TX_SOP3_CNT(x) ((x) << S_DEBUG_U_TX_SOP3_CNT)
+#define G_DEBUG_U_TX_SOP3_CNT(x) (((x) >> S_DEBUG_U_TX_SOP3_CNT) & M_DEBUG_U_TX_SOP3_CNT)
+
+#define S_DEBUG_U_TX_EOP3_CNT    24
+#define M_DEBUG_U_TX_EOP3_CNT    0xfU
+#define V_DEBUG_U_TX_EOP3_CNT(x) ((x) << S_DEBUG_U_TX_EOP3_CNT)
+#define G_DEBUG_U_TX_EOP3_CNT(x) (((x) >> S_DEBUG_U_TX_EOP3_CNT) & M_DEBUG_U_TX_EOP3_CNT)
+
+#define S_DEBUG_U_TX_SOP2_CNT    20
+#define M_DEBUG_U_TX_SOP2_CNT    0xfU
+#define V_DEBUG_U_TX_SOP2_CNT(x) ((x) << S_DEBUG_U_TX_SOP2_CNT)
+#define G_DEBUG_U_TX_SOP2_CNT(x) (((x) >> S_DEBUG_U_TX_SOP2_CNT) & M_DEBUG_U_TX_SOP2_CNT)
+
+#define S_DEBUG_U_TX_EOP2_CNT    16
+#define M_DEBUG_U_TX_EOP2_CNT    0xfU
+#define V_DEBUG_U_TX_EOP2_CNT(x) ((x) << S_DEBUG_U_TX_EOP2_CNT)
+#define G_DEBUG_U_TX_EOP2_CNT(x) (((x) >> S_DEBUG_U_TX_EOP2_CNT) & M_DEBUG_U_TX_EOP2_CNT)
+
+#define S_DEBUG_U_TX_SOP1_CNT    12
+#define M_DEBUG_U_TX_SOP1_CNT    0xfU
+#define V_DEBUG_U_TX_SOP1_CNT(x) ((x) << S_DEBUG_U_TX_SOP1_CNT)
+#define G_DEBUG_U_TX_SOP1_CNT(x) (((x) >> S_DEBUG_U_TX_SOP1_CNT) & M_DEBUG_U_TX_SOP1_CNT)
+
+#define S_DEBUG_U_TX_EOP1_CNT    8
+#define M_DEBUG_U_TX_EOP1_CNT    0xfU
+#define V_DEBUG_U_TX_EOP1_CNT(x) ((x) << S_DEBUG_U_TX_EOP1_CNT)
+#define G_DEBUG_U_TX_EOP1_CNT(x) (((x) >> S_DEBUG_U_TX_EOP1_CNT) & M_DEBUG_U_TX_EOP1_CNT)
+
+#define S_DEBUG_U_TX_SOP0_CNT    4
+#define M_DEBUG_U_TX_SOP0_CNT    0xfU
+#define V_DEBUG_U_TX_SOP0_CNT(x) ((x) << S_DEBUG_U_TX_SOP0_CNT)
+#define G_DEBUG_U_TX_SOP0_CNT(x) (((x) >> S_DEBUG_U_TX_SOP0_CNT) & M_DEBUG_U_TX_SOP0_CNT)
+
+#define S_DEBUG_U_TX_EOP0_CNT    0
+#define M_DEBUG_U_TX_EOP0_CNT    0xfU
+#define V_DEBUG_U_TX_EOP0_CNT(x) ((x) << S_DEBUG_U_TX_EOP0_CNT)
+#define G_DEBUG_U_TX_EOP0_CNT(x) (((x) >> S_DEBUG_U_TX_EOP0_CNT) & M_DEBUG_U_TX_EOP0_CNT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_4 0x1290
+
+#define S_DEBUG_PC_RSP_SOP1_CNT    28
+#define M_DEBUG_PC_RSP_SOP1_CNT    0xfU
+#define V_DEBUG_PC_RSP_SOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP1_CNT)
+#define G_DEBUG_PC_RSP_SOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP1_CNT) & M_DEBUG_PC_RSP_SOP1_CNT)
+
+#define S_DEBUG_PC_RSP_EOP1_CNT    24
+#define M_DEBUG_PC_RSP_EOP1_CNT    0xfU
+#define V_DEBUG_PC_RSP_EOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP1_CNT)
+#define G_DEBUG_PC_RSP_EOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP1_CNT) & M_DEBUG_PC_RSP_EOP1_CNT)
+
+#define S_DEBUG_PC_RSP_SOP0_CNT    20
+#define M_DEBUG_PC_RSP_SOP0_CNT    0xfU
+#define V_DEBUG_PC_RSP_SOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP0_CNT)
+#define G_DEBUG_PC_RSP_SOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP0_CNT) & M_DEBUG_PC_RSP_SOP0_CNT)
+
+#define S_DEBUG_PC_RSP_EOP0_CNT    16
+#define M_DEBUG_PC_RSP_EOP0_CNT    0xfU
+#define V_DEBUG_PC_RSP_EOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP0_CNT)
+#define G_DEBUG_PC_RSP_EOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP0_CNT) & M_DEBUG_PC_RSP_EOP0_CNT)
+
+#define S_DEBUG_PC_REQ_SOP1_CNT    12
+#define M_DEBUG_PC_REQ_SOP1_CNT    0xfU
+#define V_DEBUG_PC_REQ_SOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP1_CNT)
+#define G_DEBUG_PC_REQ_SOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP1_CNT) & M_DEBUG_PC_REQ_SOP1_CNT)
+
+#define S_DEBUG_PC_REQ_EOP1_CNT    8
+#define M_DEBUG_PC_REQ_EOP1_CNT    0xfU
+#define V_DEBUG_PC_REQ_EOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP1_CNT)
+#define G_DEBUG_PC_REQ_EOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP1_CNT) & M_DEBUG_PC_REQ_EOP1_CNT)
+
+#define S_DEBUG_PC_REQ_SOP0_CNT    4
+#define M_DEBUG_PC_REQ_SOP0_CNT    0xfU
+#define V_DEBUG_PC_REQ_SOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP0_CNT)
+#define G_DEBUG_PC_REQ_SOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP0_CNT) & M_DEBUG_PC_REQ_SOP0_CNT)
+
+#define S_DEBUG_PC_REQ_EOP0_CNT    0
+#define M_DEBUG_PC_REQ_EOP0_CNT    0xfU
+#define V_DEBUG_PC_REQ_EOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP0_CNT)
+#define G_DEBUG_PC_REQ_EOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP0_CNT) & M_DEBUG_PC_REQ_EOP0_CNT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_5 0x1294
+
+#define S_DEBUG_PD_RDREQ_SOP3_CNT    28
+#define M_DEBUG_PD_RDREQ_SOP3_CNT    0xfU
+#define V_DEBUG_PD_RDREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP3_CNT)
+#define G_DEBUG_PD_RDREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP3_CNT) & M_DEBUG_PD_RDREQ_SOP3_CNT)
+
+#define S_DEBUG_PD_RDREQ_EOP3_CNT    24
+#define M_DEBUG_PD_RDREQ_EOP3_CNT    0xfU
+#define V_DEBUG_PD_RDREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP3_CNT)
+#define G_DEBUG_PD_RDREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP3_CNT) & M_DEBUG_PD_RDREQ_EOP3_CNT)
+
+#define S_DEBUG_PD_RDREQ_SOP2_CNT    20
+#define M_DEBUG_PD_RDREQ_SOP2_CNT    0xfU
+#define V_DEBUG_PD_RDREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP2_CNT)
+#define G_DEBUG_PD_RDREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP2_CNT) & M_DEBUG_PD_RDREQ_SOP2_CNT)
+
+#define S_DEBUG_PD_RDREQ_EOP2_CNT    16
+#define M_DEBUG_PD_RDREQ_EOP2_CNT    0xfU
+#define V_DEBUG_PD_RDREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP2_CNT)
+#define G_DEBUG_PD_RDREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP2_CNT) & M_DEBUG_PD_RDREQ_EOP2_CNT)
+
+#define S_DEBUG_PD_RDREQ_SOP1_CNT    12
+#define M_DEBUG_PD_RDREQ_SOP1_CNT    0xfU
+#define V_DEBUG_PD_RDREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP1_CNT)
+#define G_DEBUG_PD_RDREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP1_CNT) & M_DEBUG_PD_RDREQ_SOP1_CNT)
+
+#define S_DEBUG_PD_RDREQ_EOP1_CNT    8
+#define M_DEBUG_PD_RDREQ_EOP1_CNT    0xfU
+#define V_DEBUG_PD_RDREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP1_CNT)
+#define G_DEBUG_PD_RDREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP1_CNT) & M_DEBUG_PD_RDREQ_EOP1_CNT)
+
+#define S_DEBUG_PD_RDREQ_SOP0_CNT    4
+#define M_DEBUG_PD_RDREQ_SOP0_CNT    0xfU
+#define V_DEBUG_PD_RDREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP0_CNT)
+#define G_DEBUG_PD_RDREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP0_CNT) & M_DEBUG_PD_RDREQ_SOP0_CNT)
+
+#define S_DEBUG_PD_RDREQ_EOP0_CNT    0
+#define M_DEBUG_PD_RDREQ_EOP0_CNT    0xfU
+#define V_DEBUG_PD_RDREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP0_CNT)
+#define G_DEBUG_PD_RDREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP0_CNT) & M_DEBUG_PD_RDREQ_EOP0_CNT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_6 0x1298
+
+#define S_DEBUG_PD_RDRSP_SOP3_CNT    28
+#define M_DEBUG_PD_RDRSP_SOP3_CNT    0xfU
+#define V_DEBUG_PD_RDRSP_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP3_CNT)
+#define G_DEBUG_PD_RDRSP_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP3_CNT) & M_DEBUG_PD_RDRSP_SOP3_CNT)
+
+#define S_DEBUG_PD_RDRSP_EOP3_CNT    24
+#define M_DEBUG_PD_RDRSP_EOP3_CNT    0xfU
+#define V_DEBUG_PD_RDRSP_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP3_CNT)
+#define G_DEBUG_PD_RDRSP_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP3_CNT) & M_DEBUG_PD_RDRSP_EOP3_CNT)
+
+#define S_DEBUG_PD_RDRSP_SOP2_CNT    20
+#define M_DEBUG_PD_RDRSP_SOP2_CNT    0xfU
+#define V_DEBUG_PD_RDRSP_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP2_CNT)
+#define G_DEBUG_PD_RDRSP_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP2_CNT) & M_DEBUG_PD_RDRSP_SOP2_CNT)
+
+#define S_DEBUG_PD_RDRSP_EOP2_CNT    16
+#define M_DEBUG_PD_RDRSP_EOP2_CNT    0xfU
+#define V_DEBUG_PD_RDRSP_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP2_CNT)
+#define G_DEBUG_PD_RDRSP_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP2_CNT) & M_DEBUG_PD_RDRSP_EOP2_CNT)
+
+#define S_DEBUG_PD_RDRSP_SOP1_CNT    12
+#define M_DEBUG_PD_RDRSP_SOP1_CNT    0xfU
+#define V_DEBUG_PD_RDRSP_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP1_CNT)
+#define G_DEBUG_PD_RDRSP_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP1_CNT) & M_DEBUG_PD_RDRSP_SOP1_CNT)
+
+#define S_DEBUG_PD_RDRSP_EOP1_CNT    8
+#define M_DEBUG_PD_RDRSP_EOP1_CNT    0xfU
+#define V_DEBUG_PD_RDRSP_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP1_CNT)
+#define G_DEBUG_PD_RDRSP_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP1_CNT) & M_DEBUG_PD_RDRSP_EOP1_CNT)
+
+#define S_DEBUG_PD_RDRSP_SOP0_CNT    4
+#define M_DEBUG_PD_RDRSP_SOP0_CNT    0xfU
+#define V_DEBUG_PD_RDRSP_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP0_CNT)
+#define G_DEBUG_PD_RDRSP_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP0_CNT) & M_DEBUG_PD_RDRSP_SOP0_CNT)
+
+#define S_DEBUG_PD_RDRSP_EOP0_CNT    0
+#define M_DEBUG_PD_RDRSP_EOP0_CNT    0xfU
+#define V_DEBUG_PD_RDRSP_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP0_CNT)
+#define G_DEBUG_PD_RDRSP_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP0_CNT) & M_DEBUG_PD_RDRSP_EOP0_CNT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_7 0x129c
+
+#define S_DEBUG_PD_WRREQ_SOP3_CNT    28
+#define M_DEBUG_PD_WRREQ_SOP3_CNT    0xfU
+#define V_DEBUG_PD_WRREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP3_CNT)
+#define G_DEBUG_PD_WRREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP3_CNT) & M_DEBUG_PD_WRREQ_SOP3_CNT)
+
+#define S_DEBUG_PD_WRREQ_EOP3_CNT    24
+#define M_DEBUG_PD_WRREQ_EOP3_CNT    0xfU
+#define V_DEBUG_PD_WRREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP3_CNT)
+#define G_DEBUG_PD_WRREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP3_CNT) & M_DEBUG_PD_WRREQ_EOP3_CNT)
+
+#define S_DEBUG_PD_WRREQ_SOP2_CNT    20
+#define M_DEBUG_PD_WRREQ_SOP2_CNT    0xfU
+#define V_DEBUG_PD_WRREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP2_CNT)
+#define G_DEBUG_PD_WRREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP2_CNT) & M_DEBUG_PD_WRREQ_SOP2_CNT)
+
+#define S_DEBUG_PD_WRREQ_EOP2_CNT    16
+#define M_DEBUG_PD_WRREQ_EOP2_CNT    0xfU
+#define V_DEBUG_PD_WRREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP2_CNT)
+#define G_DEBUG_PD_WRREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP2_CNT) & M_DEBUG_PD_WRREQ_EOP2_CNT)
+
+#define S_DEBUG_PD_WRREQ_SOP1_CNT    12
+#define M_DEBUG_PD_WRREQ_SOP1_CNT    0xfU
+#define V_DEBUG_PD_WRREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP1_CNT)
+#define G_DEBUG_PD_WRREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP1_CNT) & M_DEBUG_PD_WRREQ_SOP1_CNT)
+
+#define S_DEBUG_PD_WRREQ_EOP1_CNT    8
+#define M_DEBUG_PD_WRREQ_EOP1_CNT    0xfU
+#define V_DEBUG_PD_WRREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP1_CNT)
+#define G_DEBUG_PD_WRREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP1_CNT) & M_DEBUG_PD_WRREQ_EOP1_CNT)
+
+#define S_DEBUG_PD_WRREQ_SOP0_CNT    4
+#define M_DEBUG_PD_WRREQ_SOP0_CNT    0xfU
+#define V_DEBUG_PD_WRREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP0_CNT)
+#define G_DEBUG_PD_WRREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP0_CNT) & M_DEBUG_PD_WRREQ_SOP0_CNT)
+
+#define S_DEBUG_PD_WRREQ_EOP0_CNT    0
+#define M_DEBUG_PD_WRREQ_EOP0_CNT    0xfU
+#define V_DEBUG_PD_WRREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP0_CNT)
+#define G_DEBUG_PD_WRREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP0_CNT) & M_DEBUG_PD_WRREQ_EOP0_CNT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_8 0x12a0
+
+#define S_GLOBALENABLE_OFF    29
+#define V_GLOBALENABLE_OFF(x) ((x) << S_GLOBALENABLE_OFF)
+#define F_GLOBALENABLE_OFF    V_GLOBALENABLE_OFF(1U)
+
+#define S_DEBUG_CIM2SGE_RXAFULL_D    27
+#define M_DEBUG_CIM2SGE_RXAFULL_D    0x3U
+#define V_DEBUG_CIM2SGE_RXAFULL_D(x) ((x) << S_DEBUG_CIM2SGE_RXAFULL_D)
+#define G_DEBUG_CIM2SGE_RXAFULL_D(x) (((x) >> S_DEBUG_CIM2SGE_RXAFULL_D) & M_DEBUG_CIM2SGE_RXAFULL_D)
+
+#define S_DEBUG_CPLSW_CIM_TXAFULL_D    25
+#define M_DEBUG_CPLSW_CIM_TXAFULL_D    0x3U
+#define V_DEBUG_CPLSW_CIM_TXAFULL_D(x) ((x) << S_DEBUG_CPLSW_CIM_TXAFULL_D)
+#define G_DEBUG_CPLSW_CIM_TXAFULL_D(x) (((x) >> S_DEBUG_CPLSW_CIM_TXAFULL_D) & M_DEBUG_CPLSW_CIM_TXAFULL_D)
+
+#define S_DEBUG_UP_FULL    24
+#define V_DEBUG_UP_FULL(x) ((x) << S_DEBUG_UP_FULL)
+#define F_DEBUG_UP_FULL    V_DEBUG_UP_FULL(1U)
+
+#define S_DEBUG_M_RD_REQ_OUTSTANDING_PC    23
+#define V_DEBUG_M_RD_REQ_OUTSTANDING_PC(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_PC)
+#define F_DEBUG_M_RD_REQ_OUTSTANDING_PC    V_DEBUG_M_RD_REQ_OUTSTANDING_PC(1U)
+
+#define S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO    22
+#define V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO)
+#define F_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO    V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(1U)
+
+#define S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG    21
+#define V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG)
+#define F_DEBUG_M_RD_REQ_OUTSTANDING_IMSG    V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(1U)
+
+#define S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB    20
+#define V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB)
+#define F_DEBUG_M_RD_REQ_OUTSTANDING_CMARB    V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(1U)
+
+#define S_DEBUG_M_RD_REQ_OUTSTANDING_FLM    19
+#define V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_FLM)
+#define F_DEBUG_M_RD_REQ_OUTSTANDING_FLM    V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(1U)
+
+#define S_DEBUG_M_REQVLD    18
+#define V_DEBUG_M_REQVLD(x) ((x) << S_DEBUG_M_REQVLD)
+#define F_DEBUG_M_REQVLD    V_DEBUG_M_REQVLD(1U)
+
+#define S_DEBUG_M_REQRDY    17
+#define V_DEBUG_M_REQRDY(x) ((x) << S_DEBUG_M_REQRDY)
+#define F_DEBUG_M_REQRDY    V_DEBUG_M_REQRDY(1U)
+
+#define S_DEBUG_M_RSPVLD    16
+#define V_DEBUG_M_RSPVLD(x) ((x) << S_DEBUG_M_RSPVLD)
+#define F_DEBUG_M_RSPVLD    V_DEBUG_M_RSPVLD(1U)
+
+#define S_DEBUG_PD_WRREQ_INT3_CNT    12
+#define M_DEBUG_PD_WRREQ_INT3_CNT    0xfU
+#define V_DEBUG_PD_WRREQ_INT3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT3_CNT)
+#define G_DEBUG_PD_WRREQ_INT3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT3_CNT) & M_DEBUG_PD_WRREQ_INT3_CNT)
+
+#define S_DEBUG_PD_WRREQ_INT2_CNT    8
+#define M_DEBUG_PD_WRREQ_INT2_CNT    0xfU
+#define V_DEBUG_PD_WRREQ_INT2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT2_CNT)
+#define G_DEBUG_PD_WRREQ_INT2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT2_CNT) & M_DEBUG_PD_WRREQ_INT2_CNT)
+
+#define S_DEBUG_PD_WRREQ_INT1_CNT    4
+#define M_DEBUG_PD_WRREQ_INT1_CNT    0xfU
+#define V_DEBUG_PD_WRREQ_INT1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT1_CNT)
+#define G_DEBUG_PD_WRREQ_INT1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT1_CNT) & M_DEBUG_PD_WRREQ_INT1_CNT)
+
+#define S_DEBUG_PD_WRREQ_INT0_CNT    0
+#define M_DEBUG_PD_WRREQ_INT0_CNT    0xfU
+#define V_DEBUG_PD_WRREQ_INT0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT0_CNT)
+#define G_DEBUG_PD_WRREQ_INT0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT0_CNT) & M_DEBUG_PD_WRREQ_INT0_CNT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_9 0x12a4
+
+#define S_DEBUG_CPLSW_TP_RX_SOP1_CNT    28
+#define M_DEBUG_CPLSW_TP_RX_SOP1_CNT    0xfU
+#define V_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP1_CNT)
+#define G_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP1_CNT) & M_DEBUG_CPLSW_TP_RX_SOP1_CNT)
+
+#define S_DEBUG_CPLSW_TP_RX_EOP1_CNT    24
+#define M_DEBUG_CPLSW_TP_RX_EOP1_CNT    0xfU
+#define V_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP1_CNT)
+#define G_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP1_CNT) & M_DEBUG_CPLSW_TP_RX_EOP1_CNT)
+
+#define S_DEBUG_CPLSW_TP_RX_SOP0_CNT    20
+#define M_DEBUG_CPLSW_TP_RX_SOP0_CNT    0xfU
+#define V_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP0_CNT)
+#define G_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP0_CNT) & M_DEBUG_CPLSW_TP_RX_SOP0_CNT)
+
+#define S_DEBUG_CPLSW_TP_RX_EOP0_CNT    16
+#define M_DEBUG_CPLSW_TP_RX_EOP0_CNT    0xfU
+#define V_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP0_CNT)
+#define G_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP0_CNT) & M_DEBUG_CPLSW_TP_RX_EOP0_CNT)
+
+#define S_DEBUG_CPLSW_CIM_SOP1_CNT    12
+#define M_DEBUG_CPLSW_CIM_SOP1_CNT    0xfU
+#define V_DEBUG_CPLSW_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP1_CNT)
+#define G_DEBUG_CPLSW_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP1_CNT) & M_DEBUG_CPLSW_CIM_SOP1_CNT)
+
+#define S_DEBUG_CPLSW_CIM_EOP1_CNT    8
+#define M_DEBUG_CPLSW_CIM_EOP1_CNT    0xfU
+#define V_DEBUG_CPLSW_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP1_CNT)
+#define G_DEBUG_CPLSW_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP1_CNT) & M_DEBUG_CPLSW_CIM_EOP1_CNT)
+
+#define S_DEBUG_CPLSW_CIM_SOP0_CNT    4
+#define M_DEBUG_CPLSW_CIM_SOP0_CNT    0xfU
+#define V_DEBUG_CPLSW_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP0_CNT)
+#define G_DEBUG_CPLSW_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP0_CNT) & M_DEBUG_CPLSW_CIM_SOP0_CNT)
+
+#define S_DEBUG_CPLSW_CIM_EOP0_CNT    0
+#define M_DEBUG_CPLSW_CIM_EOP0_CNT    0xfU
+#define V_DEBUG_CPLSW_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP0_CNT)
+#define G_DEBUG_CPLSW_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP0_CNT) & M_DEBUG_CPLSW_CIM_EOP0_CNT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8
+
+#define S_DEBUG_T_RXAFULL_D    30
+#define M_DEBUG_T_RXAFULL_D    0x3U
+#define V_DEBUG_T_RXAFULL_D(x) ((x) << S_DEBUG_T_RXAFULL_D)
+#define G_DEBUG_T_RXAFULL_D(x) (((x) >> S_DEBUG_T_RXAFULL_D) & M_DEBUG_T_RXAFULL_D)
+
+#define S_DEBUG_PD_RDRSPAFULL_D    26
+#define M_DEBUG_PD_RDRSPAFULL_D    0xfU
+#define V_DEBUG_PD_RDRSPAFULL_D(x) ((x) << S_DEBUG_PD_RDRSPAFULL_D)
+#define G_DEBUG_PD_RDRSPAFULL_D(x) (((x) >> S_DEBUG_PD_RDRSPAFULL_D) & M_DEBUG_PD_RDRSPAFULL_D)
+
+#define S_DEBUG_PD_RDREQAFULL_D    22
+#define M_DEBUG_PD_RDREQAFULL_D    0xfU
+#define V_DEBUG_PD_RDREQAFULL_D(x) ((x) << S_DEBUG_PD_RDREQAFULL_D)
+#define G_DEBUG_PD_RDREQAFULL_D(x) (((x) >> S_DEBUG_PD_RDREQAFULL_D) & M_DEBUG_PD_RDREQAFULL_D)
+
+#define S_DEBUG_PD_WRREQAFULL_D    18
+#define M_DEBUG_PD_WRREQAFULL_D    0xfU
+#define V_DEBUG_PD_WRREQAFULL_D(x) ((x) << S_DEBUG_PD_WRREQAFULL_D)
+#define G_DEBUG_PD_WRREQAFULL_D(x) (((x) >> S_DEBUG_PD_WRREQAFULL_D) & M_DEBUG_PD_WRREQAFULL_D)
+
+#define S_DEBUG_PC_RSPAFULL_D    15
+#define M_DEBUG_PC_RSPAFULL_D    0x7U
+#define V_DEBUG_PC_RSPAFULL_D(x) ((x) << S_DEBUG_PC_RSPAFULL_D)
+#define G_DEBUG_PC_RSPAFULL_D(x) (((x) >> S_DEBUG_PC_RSPAFULL_D) & M_DEBUG_PC_RSPAFULL_D)
+
+#define S_DEBUG_PC_REQAFULL_D    12
+#define M_DEBUG_PC_REQAFULL_D    0x7U
+#define V_DEBUG_PC_REQAFULL_D(x) ((x) << S_DEBUG_PC_REQAFULL_D)
+#define G_DEBUG_PC_REQAFULL_D(x) (((x) >> S_DEBUG_PC_REQAFULL_D) & M_DEBUG_PC_REQAFULL_D)
+
+#define S_DEBUG_U_TXAFULL_D    8
+#define M_DEBUG_U_TXAFULL_D    0xfU
+#define V_DEBUG_U_TXAFULL_D(x) ((x) << S_DEBUG_U_TXAFULL_D)
+#define G_DEBUG_U_TXAFULL_D(x) (((x) >> S_DEBUG_U_TXAFULL_D) & M_DEBUG_U_TXAFULL_D)
+
+#define S_DEBUG_UD_RXAFULL_D    4
+#define M_DEBUG_UD_RXAFULL_D    0xfU
+#define V_DEBUG_UD_RXAFULL_D(x) ((x) << S_DEBUG_UD_RXAFULL_D)
+#define G_DEBUG_UD_RXAFULL_D(x) (((x) >> S_DEBUG_UD_RXAFULL_D) & M_DEBUG_UD_RXAFULL_D)
+
+#define S_DEBUG_U_RXAFULL_D    2
+#define M_DEBUG_U_RXAFULL_D    0x3U
+#define V_DEBUG_U_RXAFULL_D(x) ((x) << S_DEBUG_U_RXAFULL_D)
+#define G_DEBUG_U_RXAFULL_D(x) (((x) >> S_DEBUG_U_RXAFULL_D) & M_DEBUG_U_RXAFULL_D)
+
+#define S_DEBUG_CIM_AFULL_D    0
+#define M_DEBUG_CIM_AFULL_D    0x3U
+#define V_DEBUG_CIM_AFULL_D(x) ((x) << S_DEBUG_CIM_AFULL_D)
+#define G_DEBUG_CIM_AFULL_D(x) (((x) >> S_DEBUG_CIM_AFULL_D) & M_DEBUG_CIM_AFULL_D)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_11 0x12ac
+
+#define S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE    24
+#define V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE)
+#define F_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE    V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(1U)
+
+#define S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE    23
+#define V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE)
+#define F_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE    V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(1U)
+
+#define S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE    22
+#define V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE)
+#define F_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE    V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(1U)
+
+#define S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE    21
+#define V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE)
+#define F_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE    V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(1U)
+
+#define S_DEBUG_ST_FLM_IDMA1_CACHE    19
+#define M_DEBUG_ST_FLM_IDMA1_CACHE    0x3U
+#define V_DEBUG_ST_FLM_IDMA1_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CACHE)
+#define G_DEBUG_ST_FLM_IDMA1_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CACHE) & M_DEBUG_ST_FLM_IDMA1_CACHE)
+
+#define S_DEBUG_ST_FLM_IDMA1_CTXT    16
+#define M_DEBUG_ST_FLM_IDMA1_CTXT    0x7U
+#define V_DEBUG_ST_FLM_IDMA1_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CTXT)
+#define G_DEBUG_ST_FLM_IDMA1_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CTXT) & M_DEBUG_ST_FLM_IDMA1_CTXT)
+
+#define S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE    8
+#define V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE)
+#define F_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE    V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(1U)
+
+#define S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE    7
+#define V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE)
+#define F_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE    V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(1U)
+
+#define S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE    6
+#define V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE)
+#define F_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE    V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(1U)
+
+#define S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE    5
+#define V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE)
+#define F_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE    V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(1U)
+
+#define S_DEBUG_ST_FLM_IDMA0_CACHE    3
+#define M_DEBUG_ST_FLM_IDMA0_CACHE    0x3U
+#define V_DEBUG_ST_FLM_IDMA0_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CACHE)
+#define G_DEBUG_ST_FLM_IDMA0_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CACHE) & M_DEBUG_ST_FLM_IDMA0_CACHE)
+
+#define S_DEBUG_ST_FLM_IDMA0_CTXT    0
+#define M_DEBUG_ST_FLM_IDMA0_CTXT    0x7U
+#define V_DEBUG_ST_FLM_IDMA0_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CTXT)
+#define G_DEBUG_ST_FLM_IDMA0_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CTXT) & M_DEBUG_ST_FLM_IDMA0_CTXT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_12 0x12b0
+
+#define S_DEBUG_CPLSW_SOP1_CNT    28
+#define M_DEBUG_CPLSW_SOP1_CNT    0xfU
+#define V_DEBUG_CPLSW_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_SOP1_CNT)
+#define G_DEBUG_CPLSW_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP1_CNT) & M_DEBUG_CPLSW_SOP1_CNT)
+
+#define S_DEBUG_CPLSW_EOP1_CNT    24
+#define M_DEBUG_CPLSW_EOP1_CNT    0xfU
+#define V_DEBUG_CPLSW_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_EOP1_CNT)
+#define G_DEBUG_CPLSW_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP1_CNT) & M_DEBUG_CPLSW_EOP1_CNT)
+
+#define S_DEBUG_CPLSW_SOP0_CNT    20
+#define M_DEBUG_CPLSW_SOP0_CNT    0xfU
+#define V_DEBUG_CPLSW_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_SOP0_CNT)
+#define G_DEBUG_CPLSW_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP0_CNT) & M_DEBUG_CPLSW_SOP0_CNT)
+
+#define S_DEBUG_CPLSW_EOP0_CNT    16
+#define M_DEBUG_CPLSW_EOP0_CNT    0xfU
+#define V_DEBUG_CPLSW_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_EOP0_CNT)
+#define G_DEBUG_CPLSW_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP0_CNT) & M_DEBUG_CPLSW_EOP0_CNT)
+
+#define S_DEBUG_PC_RSP_SOP2_CNT    12
+#define M_DEBUG_PC_RSP_SOP2_CNT    0xfU
+#define V_DEBUG_PC_RSP_SOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP2_CNT)
+#define G_DEBUG_PC_RSP_SOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP2_CNT) & M_DEBUG_PC_RSP_SOP2_CNT)
+
+#define S_DEBUG_PC_RSP_EOP2_CNT    8
+#define M_DEBUG_PC_RSP_EOP2_CNT    0xfU
+#define V_DEBUG_PC_RSP_EOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP2_CNT)
+#define G_DEBUG_PC_RSP_EOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP2_CNT) & M_DEBUG_PC_RSP_EOP2_CNT)
+
+#define S_DEBUG_PC_REQ_SOP2_CNT    4
+#define M_DEBUG_PC_REQ_SOP2_CNT    0xfU
+#define V_DEBUG_PC_REQ_SOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP2_CNT)
+#define G_DEBUG_PC_REQ_SOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP2_CNT) & M_DEBUG_PC_REQ_SOP2_CNT)
+
+#define S_DEBUG_PC_REQ_EOP2_CNT    0
+#define M_DEBUG_PC_REQ_EOP2_CNT    0xfU
+#define V_DEBUG_PC_REQ_EOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP2_CNT)
+#define G_DEBUG_PC_REQ_EOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP2_CNT) & M_DEBUG_PC_REQ_EOP2_CNT)
+
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_13 0x12b4
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_14 0x12b8
+#define A_SGE_DEBUG_DATA_HIGH_INDEX_15 0x12bc
+#define A_SGE_DEBUG_DATA_LOW_INDEX_0 0x12c0
+
+#define S_DEBUG_ST_IDMA1_FLM_REQ    29
+#define M_DEBUG_ST_IDMA1_FLM_REQ    0x7U
+#define V_DEBUG_ST_IDMA1_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA1_FLM_REQ)
+#define G_DEBUG_ST_IDMA1_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA1_FLM_REQ) & M_DEBUG_ST_IDMA1_FLM_REQ)
+
+#define S_DEBUG_ST_IDMA0_FLM_REQ    26
+#define M_DEBUG_ST_IDMA0_FLM_REQ    0x7U
+#define V_DEBUG_ST_IDMA0_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA0_FLM_REQ)
+#define G_DEBUG_ST_IDMA0_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA0_FLM_REQ) & M_DEBUG_ST_IDMA0_FLM_REQ)
+
+#define S_DEBUG_ST_IMSG_CTXT    23
+#define M_DEBUG_ST_IMSG_CTXT    0x7U
+#define V_DEBUG_ST_IMSG_CTXT(x) ((x) << S_DEBUG_ST_IMSG_CTXT)
+#define G_DEBUG_ST_IMSG_CTXT(x) (((x) >> S_DEBUG_ST_IMSG_CTXT) & M_DEBUG_ST_IMSG_CTXT)
+
+#define S_DEBUG_ST_IMSG    18
+#define M_DEBUG_ST_IMSG    0x1fU
+#define V_DEBUG_ST_IMSG(x) ((x) << S_DEBUG_ST_IMSG)
+#define G_DEBUG_ST_IMSG(x) (((x) >> S_DEBUG_ST_IMSG) & M_DEBUG_ST_IMSG)
+
+#define S_DEBUG_ST_IDMA1_IALN    16
+#define M_DEBUG_ST_IDMA1_IALN    0x3U
+#define V_DEBUG_ST_IDMA1_IALN(x) ((x) << S_DEBUG_ST_IDMA1_IALN)
+#define G_DEBUG_ST_IDMA1_IALN(x) (((x) >> S_DEBUG_ST_IDMA1_IALN) & M_DEBUG_ST_IDMA1_IALN)
+
+#define S_DEBUG_ST_IDMA1_IDMA_SM    9
+#define M_DEBUG_ST_IDMA1_IDMA_SM    0x3fU
+#define V_DEBUG_ST_IDMA1_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA1_IDMA_SM)
+#define G_DEBUG_ST_IDMA1_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA1_IDMA_SM) & M_DEBUG_ST_IDMA1_IDMA_SM)
+
+#define S_DEBUG_ST_IDMA0_IALN    7
+#define M_DEBUG_ST_IDMA0_IALN    0x3U
+#define V_DEBUG_ST_IDMA0_IALN(x) ((x) << S_DEBUG_ST_IDMA0_IALN)
+#define G_DEBUG_ST_IDMA0_IALN(x) (((x) >> S_DEBUG_ST_IDMA0_IALN) & M_DEBUG_ST_IDMA0_IALN)
+
+#define S_DEBUG_ST_IDMA0_IDMA_SM    0
+#define M_DEBUG_ST_IDMA0_IDMA_SM    0x3fU
+#define V_DEBUG_ST_IDMA0_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA0_IDMA_SM)
+#define G_DEBUG_ST_IDMA0_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA0_IDMA_SM) & M_DEBUG_ST_IDMA0_IDMA_SM)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_1 0x12c4
+
+#define S_DEBUG_ITP_EMPTY    12
+#define M_DEBUG_ITP_EMPTY    0x3fU
+#define V_DEBUG_ITP_EMPTY(x) ((x) << S_DEBUG_ITP_EMPTY)
+#define G_DEBUG_ITP_EMPTY(x) (((x) >> S_DEBUG_ITP_EMPTY) & M_DEBUG_ITP_EMPTY)
+
+#define S_DEBUG_ITP_EXPIRED    6
+#define M_DEBUG_ITP_EXPIRED    0x3fU
+#define V_DEBUG_ITP_EXPIRED(x) ((x) << S_DEBUG_ITP_EXPIRED)
+#define G_DEBUG_ITP_EXPIRED(x) (((x) >> S_DEBUG_ITP_EXPIRED) & M_DEBUG_ITP_EXPIRED)
+
+#define S_DEBUG_ITP_PAUSE    5
+#define V_DEBUG_ITP_PAUSE(x) ((x) << S_DEBUG_ITP_PAUSE)
+#define F_DEBUG_ITP_PAUSE    V_DEBUG_ITP_PAUSE(1U)
+
+#define S_DEBUG_ITP_DEL_DONE    4
+#define V_DEBUG_ITP_DEL_DONE(x) ((x) << S_DEBUG_ITP_DEL_DONE)
+#define F_DEBUG_ITP_DEL_DONE    V_DEBUG_ITP_DEL_DONE(1U)
+
+#define S_DEBUG_ITP_ADD_DONE    3
+#define V_DEBUG_ITP_ADD_DONE(x) ((x) << S_DEBUG_ITP_ADD_DONE)
+#define F_DEBUG_ITP_ADD_DONE    V_DEBUG_ITP_ADD_DONE(1U)
+
+#define S_DEBUG_ITP_EVR_STATE    0
+#define M_DEBUG_ITP_EVR_STATE    0x7U
+#define V_DEBUG_ITP_EVR_STATE(x) ((x) << S_DEBUG_ITP_EVR_STATE)
+#define G_DEBUG_ITP_EVR_STATE(x) (((x) >> S_DEBUG_ITP_EVR_STATE) & M_DEBUG_ITP_EVR_STATE)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8
+
+#define S_DEBUG_ST_DBP_THREAD2_CIMFL    25
+#define M_DEBUG_ST_DBP_THREAD2_CIMFL    0x1fU
+#define V_DEBUG_ST_DBP_THREAD2_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD2_CIMFL)
+#define G_DEBUG_ST_DBP_THREAD2_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_CIMFL) & M_DEBUG_ST_DBP_THREAD2_CIMFL)
+
+#define S_DEBUG_ST_DBP_THREAD2_MAIN    20
+#define M_DEBUG_ST_DBP_THREAD2_MAIN    0x1fU
+#define V_DEBUG_ST_DBP_THREAD2_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD2_MAIN)
+#define G_DEBUG_ST_DBP_THREAD2_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_MAIN) & M_DEBUG_ST_DBP_THREAD2_MAIN)
+
+#define S_DEBUG_ST_DBP_THREAD1_CIMFL    15
+#define M_DEBUG_ST_DBP_THREAD1_CIMFL    0x1fU
+#define V_DEBUG_ST_DBP_THREAD1_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD1_CIMFL)
+#define G_DEBUG_ST_DBP_THREAD1_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_CIMFL) & M_DEBUG_ST_DBP_THREAD1_CIMFL)
+
+#define S_DEBUG_ST_DBP_THREAD1_MAIN    10
+#define M_DEBUG_ST_DBP_THREAD1_MAIN    0x1fU
+#define V_DEBUG_ST_DBP_THREAD1_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD1_MAIN)
+#define G_DEBUG_ST_DBP_THREAD1_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_MAIN) & M_DEBUG_ST_DBP_THREAD1_MAIN)
+
+#define S_DEBUG_ST_DBP_THREAD0_CIMFL    5
+#define M_DEBUG_ST_DBP_THREAD0_CIMFL    0x1fU
+#define V_DEBUG_ST_DBP_THREAD0_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD0_CIMFL)
+#define G_DEBUG_ST_DBP_THREAD0_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_CIMFL) & M_DEBUG_ST_DBP_THREAD0_CIMFL)
+
+#define S_DEBUG_ST_DBP_THREAD0_MAIN    0
+#define M_DEBUG_ST_DBP_THREAD0_MAIN    0x1fU
+#define V_DEBUG_ST_DBP_THREAD0_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD0_MAIN)
+#define G_DEBUG_ST_DBP_THREAD0_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_MAIN) & M_DEBUG_ST_DBP_THREAD0_MAIN)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc
+
+#define S_DEBUG_ST_DBP_UPCP_MAIN    14
+#define M_DEBUG_ST_DBP_UPCP_MAIN    0x1fU
+#define V_DEBUG_ST_DBP_UPCP_MAIN(x) ((x) << S_DEBUG_ST_DBP_UPCP_MAIN)
+#define G_DEBUG_ST_DBP_UPCP_MAIN(x) (((x) >> S_DEBUG_ST_DBP_UPCP_MAIN) & M_DEBUG_ST_DBP_UPCP_MAIN)
+
+#define S_DEBUG_ST_DBP_DBFIFO_MAIN    13
+#define V_DEBUG_ST_DBP_DBFIFO_MAIN(x) ((x) << S_DEBUG_ST_DBP_DBFIFO_MAIN)
+#define F_DEBUG_ST_DBP_DBFIFO_MAIN    V_DEBUG_ST_DBP_DBFIFO_MAIN(1U)
+
+#define S_DEBUG_ST_DBP_CTXT    10
+#define M_DEBUG_ST_DBP_CTXT    0x7U
+#define V_DEBUG_ST_DBP_CTXT(x) ((x) << S_DEBUG_ST_DBP_CTXT)
+#define G_DEBUG_ST_DBP_CTXT(x) (((x) >> S_DEBUG_ST_DBP_CTXT) & M_DEBUG_ST_DBP_CTXT)
+
+#define S_DEBUG_ST_DBP_THREAD3_CIMFL    5
+#define M_DEBUG_ST_DBP_THREAD3_CIMFL    0x1fU
+#define V_DEBUG_ST_DBP_THREAD3_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD3_CIMFL)
+#define G_DEBUG_ST_DBP_THREAD3_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_CIMFL) & M_DEBUG_ST_DBP_THREAD3_CIMFL)
+
+#define S_DEBUG_ST_DBP_THREAD3_MAIN    0
+#define M_DEBUG_ST_DBP_THREAD3_MAIN    0x1fU
+#define V_DEBUG_ST_DBP_THREAD3_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD3_MAIN)
+#define G_DEBUG_ST_DBP_THREAD3_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_MAIN) & M_DEBUG_ST_DBP_THREAD3_MAIN)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_4 0x12d0
+
+#define S_DEBUG_ST_EDMA3_ALIGN_SUB    29
+#define M_DEBUG_ST_EDMA3_ALIGN_SUB    0x7U
+#define V_DEBUG_ST_EDMA3_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN_SUB)
+#define G_DEBUG_ST_EDMA3_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN_SUB) & M_DEBUG_ST_EDMA3_ALIGN_SUB)
+
+#define S_DEBUG_ST_EDMA3_ALIGN    27
+#define M_DEBUG_ST_EDMA3_ALIGN    0x3U
+#define V_DEBUG_ST_EDMA3_ALIGN(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN)
+#define G_DEBUG_ST_EDMA3_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN) & M_DEBUG_ST_EDMA3_ALIGN)
+
+#define S_DEBUG_ST_EDMA3_REQ    24
+#define M_DEBUG_ST_EDMA3_REQ    0x7U
+#define V_DEBUG_ST_EDMA3_REQ(x) ((x) << S_DEBUG_ST_EDMA3_REQ)
+#define G_DEBUG_ST_EDMA3_REQ(x) (((x) >> S_DEBUG_ST_EDMA3_REQ) & M_DEBUG_ST_EDMA3_REQ)
+
+#define S_DEBUG_ST_EDMA2_ALIGN_SUB    21
+#define M_DEBUG_ST_EDMA2_ALIGN_SUB    0x7U
+#define V_DEBUG_ST_EDMA2_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN_SUB)
+#define G_DEBUG_ST_EDMA2_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN_SUB) & M_DEBUG_ST_EDMA2_ALIGN_SUB)
+
+#define S_DEBUG_ST_EDMA2_ALIGN    19
+#define M_DEBUG_ST_EDMA2_ALIGN    0x3U
+#define V_DEBUG_ST_EDMA2_ALIGN(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN)
+#define G_DEBUG_ST_EDMA2_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN) & M_DEBUG_ST_EDMA2_ALIGN)
+
+#define S_DEBUG_ST_EDMA2_REQ    16
+#define M_DEBUG_ST_EDMA2_REQ    0x7U
+#define V_DEBUG_ST_EDMA2_REQ(x) ((x) << S_DEBUG_ST_EDMA2_REQ)
+#define G_DEBUG_ST_EDMA2_REQ(x) (((x) >> S_DEBUG_ST_EDMA2_REQ) & M_DEBUG_ST_EDMA2_REQ)
+
+#define S_DEBUG_ST_EDMA1_ALIGN_SUB    13
+#define M_DEBUG_ST_EDMA1_ALIGN_SUB    0x7U
+#define V_DEBUG_ST_EDMA1_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN_SUB)
+#define G_DEBUG_ST_EDMA1_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN_SUB) & M_DEBUG_ST_EDMA1_ALIGN_SUB)
+
+#define S_DEBUG_ST_EDMA1_ALIGN    11
+#define M_DEBUG_ST_EDMA1_ALIGN    0x3U
+#define V_DEBUG_ST_EDMA1_ALIGN(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN)
+#define G_DEBUG_ST_EDMA1_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN) & M_DEBUG_ST_EDMA1_ALIGN)
+
+#define S_DEBUG_ST_EDMA1_REQ    8
+#define M_DEBUG_ST_EDMA1_REQ    0x7U
+#define V_DEBUG_ST_EDMA1_REQ(x) ((x) << S_DEBUG_ST_EDMA1_REQ)
+#define G_DEBUG_ST_EDMA1_REQ(x) (((x) >> S_DEBUG_ST_EDMA1_REQ) & M_DEBUG_ST_EDMA1_REQ)
+
+#define S_DEBUG_ST_EDMA0_ALIGN_SUB    5
+#define M_DEBUG_ST_EDMA0_ALIGN_SUB    0x7U
+#define V_DEBUG_ST_EDMA0_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN_SUB)
+#define G_DEBUG_ST_EDMA0_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN_SUB) & M_DEBUG_ST_EDMA0_ALIGN_SUB)
+
+#define S_DEBUG_ST_EDMA0_ALIGN    3
+#define M_DEBUG_ST_EDMA0_ALIGN    0x3U
+#define V_DEBUG_ST_EDMA0_ALIGN(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN)
+#define G_DEBUG_ST_EDMA0_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN) & M_DEBUG_ST_EDMA0_ALIGN)
+
+#define S_DEBUG_ST_EDMA0_REQ    0
+#define M_DEBUG_ST_EDMA0_REQ    0x7U
+#define V_DEBUG_ST_EDMA0_REQ(x) ((x) << S_DEBUG_ST_EDMA0_REQ)
+#define G_DEBUG_ST_EDMA0_REQ(x) (((x) >> S_DEBUG_ST_EDMA0_REQ) & M_DEBUG_ST_EDMA0_REQ)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_5 0x12d4
+
+#define S_DEBUG_ST_FLM_DBPTR    30
+#define M_DEBUG_ST_FLM_DBPTR    0x3U
+#define V_DEBUG_ST_FLM_DBPTR(x) ((x) << S_DEBUG_ST_FLM_DBPTR)
+#define G_DEBUG_ST_FLM_DBPTR(x) (((x) >> S_DEBUG_ST_FLM_DBPTR) & M_DEBUG_ST_FLM_DBPTR)
+
+#define S_DEBUG_FLM_CACHE_LOCKED_COUNT    23
+#define M_DEBUG_FLM_CACHE_LOCKED_COUNT    0x7fU
+#define V_DEBUG_FLM_CACHE_LOCKED_COUNT(x) ((x) << S_DEBUG_FLM_CACHE_LOCKED_COUNT)
+#define G_DEBUG_FLM_CACHE_LOCKED_COUNT(x) (((x) >> S_DEBUG_FLM_CACHE_LOCKED_COUNT) & M_DEBUG_FLM_CACHE_LOCKED_COUNT)
+
+#define S_DEBUG_FLM_CACHE_AGENT    20
+#define M_DEBUG_FLM_CACHE_AGENT    0x7U
+#define V_DEBUG_FLM_CACHE_AGENT(x) ((x) << S_DEBUG_FLM_CACHE_AGENT)
+#define G_DEBUG_FLM_CACHE_AGENT(x) (((x) >> S_DEBUG_FLM_CACHE_AGENT) & M_DEBUG_FLM_CACHE_AGENT)
+
+#define S_DEBUG_ST_FLM_CACHE    16
+#define M_DEBUG_ST_FLM_CACHE    0xfU
+#define V_DEBUG_ST_FLM_CACHE(x) ((x) << S_DEBUG_ST_FLM_CACHE)
+#define G_DEBUG_ST_FLM_CACHE(x) (((x) >> S_DEBUG_ST_FLM_CACHE) & M_DEBUG_ST_FLM_CACHE)
+
+#define S_DEBUG_FLM_DBPTR_CIDX_STALL    12
+#define V_DEBUG_FLM_DBPTR_CIDX_STALL(x) ((x) << S_DEBUG_FLM_DBPTR_CIDX_STALL)
+#define F_DEBUG_FLM_DBPTR_CIDX_STALL    V_DEBUG_FLM_DBPTR_CIDX_STALL(1U)
+
+#define S_DEBUG_FLM_DBPTR_QID    0
+#define M_DEBUG_FLM_DBPTR_QID    0xfffU
+#define V_DEBUG_FLM_DBPTR_QID(x) ((x) << S_DEBUG_FLM_DBPTR_QID)
+#define G_DEBUG_FLM_DBPTR_QID(x) (((x) >> S_DEBUG_FLM_DBPTR_QID) & M_DEBUG_FLM_DBPTR_QID)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_6 0x12d8
+
+#define S_DEBUG_DBP_THREAD0_QID    0
+#define M_DEBUG_DBP_THREAD0_QID    0x1ffffU
+#define V_DEBUG_DBP_THREAD0_QID(x) ((x) << S_DEBUG_DBP_THREAD0_QID)
+#define G_DEBUG_DBP_THREAD0_QID(x) (((x) >> S_DEBUG_DBP_THREAD0_QID) & M_DEBUG_DBP_THREAD0_QID)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_7 0x12dc
+
+#define S_DEBUG_DBP_THREAD1_QID    0
+#define M_DEBUG_DBP_THREAD1_QID    0x1ffffU
+#define V_DEBUG_DBP_THREAD1_QID(x) ((x) << S_DEBUG_DBP_THREAD1_QID)
+#define G_DEBUG_DBP_THREAD1_QID(x) (((x) >> S_DEBUG_DBP_THREAD1_QID) & M_DEBUG_DBP_THREAD1_QID)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_8 0x12e0
+
+#define S_DEBUG_DBP_THREAD2_QID    0
+#define M_DEBUG_DBP_THREAD2_QID    0x1ffffU
+#define V_DEBUG_DBP_THREAD2_QID(x) ((x) << S_DEBUG_DBP_THREAD2_QID)
+#define G_DEBUG_DBP_THREAD2_QID(x) (((x) >> S_DEBUG_DBP_THREAD2_QID) & M_DEBUG_DBP_THREAD2_QID)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_9 0x12e4
+
+#define S_DEBUG_DBP_THREAD3_QID    0
+#define M_DEBUG_DBP_THREAD3_QID    0x1ffffU
+#define V_DEBUG_DBP_THREAD3_QID(x) ((x) << S_DEBUG_DBP_THREAD3_QID)
+#define G_DEBUG_DBP_THREAD3_QID(x) (((x) >> S_DEBUG_DBP_THREAD3_QID) & M_DEBUG_DBP_THREAD3_QID)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_10 0x12e8
+
+#define S_DEBUG_IMSG_CPL    16
+#define M_DEBUG_IMSG_CPL    0xffU
+#define V_DEBUG_IMSG_CPL(x) ((x) << S_DEBUG_IMSG_CPL)
+#define G_DEBUG_IMSG_CPL(x) (((x) >> S_DEBUG_IMSG_CPL) & M_DEBUG_IMSG_CPL)
+
+#define S_DEBUG_IMSG_QID    0
+#define M_DEBUG_IMSG_QID    0xffffU
+#define V_DEBUG_IMSG_QID(x) ((x) << S_DEBUG_IMSG_QID)
+#define G_DEBUG_IMSG_QID(x) (((x) >> S_DEBUG_IMSG_QID) & M_DEBUG_IMSG_QID)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_11 0x12ec
+
+#define S_DEBUG_IDMA1_QID    16
+#define M_DEBUG_IDMA1_QID    0xffffU
+#define V_DEBUG_IDMA1_QID(x) ((x) << S_DEBUG_IDMA1_QID)
+#define G_DEBUG_IDMA1_QID(x) (((x) >> S_DEBUG_IDMA1_QID) & M_DEBUG_IDMA1_QID)
+
+#define S_DEBUG_IDMA0_QID    0
+#define M_DEBUG_IDMA0_QID    0xffffU
+#define V_DEBUG_IDMA0_QID(x) ((x) << S_DEBUG_IDMA0_QID)
+#define G_DEBUG_IDMA0_QID(x) (((x) >> S_DEBUG_IDMA0_QID) & M_DEBUG_IDMA0_QID)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_12 0x12f0
+
+#define S_DEBUG_IDMA1_FLM_REQ_QID    16
+#define M_DEBUG_IDMA1_FLM_REQ_QID    0xffffU
+#define V_DEBUG_IDMA1_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA1_FLM_REQ_QID)
+#define G_DEBUG_IDMA1_FLM_REQ_QID(x) (((x) >> S_DEBUG_IDMA1_FLM_REQ_QID) & M_DEBUG_IDMA1_FLM_REQ_QID)
+
+#define S_DEBUG_IDMA0_FLM_REQ_QID    0
+#define M_DEBUG_IDMA0_FLM_REQ_QID    0xffffU
+#define V_DEBUG_IDMA0_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA0_FLM_REQ_QID)
+#define G_DEBUG_IDMA0_FLM_REQ_QID(x) (((x) >> S_DEBUG_IDMA0_FLM_REQ_QID) & M_DEBUG_IDMA0_FLM_REQ_QID)
+
+#define A_SGE_DEBUG_DATA_LOW_INDEX_13 0x12f4
+#define A_SGE_DEBUG_DATA_LOW_INDEX_14 0x12f8
+#define A_SGE_DEBUG_DATA_LOW_INDEX_15 0x12fc
+#define A_SGE_QUEUE_BASE_MAP_HIGH 0x1300
+
+#define S_EGRESS_LOG2SIZE    27
+#define M_EGRESS_LOG2SIZE    0x1fU
+#define V_EGRESS_LOG2SIZE(x) ((x) << S_EGRESS_LOG2SIZE)
+#define G_EGRESS_LOG2SIZE(x) (((x) >> S_EGRESS_LOG2SIZE) & M_EGRESS_LOG2SIZE)
+
+#define S_EGRESS_BASE    10
+#define M_EGRESS_BASE    0x1ffffU
+#define V_EGRESS_BASE(x) ((x) << S_EGRESS_BASE)
+#define G_EGRESS_BASE(x) (((x) >> S_EGRESS_BASE) & M_EGRESS_BASE)
+
+#define S_INGRESS2_LOG2SIZE    5
+#define M_INGRESS2_LOG2SIZE    0x1fU
+#define V_INGRESS2_LOG2SIZE(x) ((x) << S_INGRESS2_LOG2SIZE)
+#define G_INGRESS2_LOG2SIZE(x) (((x) >> S_INGRESS2_LOG2SIZE) & M_INGRESS2_LOG2SIZE)
+
+#define S_INGRESS1_LOG2SIZE    0
+#define M_INGRESS1_LOG2SIZE    0x1fU
+#define V_INGRESS1_LOG2SIZE(x) ((x) << S_INGRESS1_LOG2SIZE)
+#define G_INGRESS1_LOG2SIZE(x) (((x) >> S_INGRESS1_LOG2SIZE) & M_INGRESS1_LOG2SIZE)
+
+#define S_EGRESS_SIZE    27
+#define M_EGRESS_SIZE    0x1fU
+#define V_EGRESS_SIZE(x) ((x) << S_EGRESS_SIZE)
+#define G_EGRESS_SIZE(x) (((x) >> S_EGRESS_SIZE) & M_EGRESS_SIZE)
+
+#define S_INGRESS2_SIZE    5
+#define M_INGRESS2_SIZE    0x1fU
+#define V_INGRESS2_SIZE(x) ((x) << S_INGRESS2_SIZE)
+#define G_INGRESS2_SIZE(x) (((x) >> S_INGRESS2_SIZE) & M_INGRESS2_SIZE)
+
+#define S_INGRESS1_SIZE    0
+#define M_INGRESS1_SIZE    0x1fU
+#define V_INGRESS1_SIZE(x) ((x) << S_INGRESS1_SIZE)
+#define G_INGRESS1_SIZE(x) (((x) >> S_INGRESS1_SIZE) & M_INGRESS1_SIZE)
+
+#define A_SGE_QUEUE_BASE_MAP_LOW 0x1304
+
+#define S_INGRESS2_BASE    16
+#define M_INGRESS2_BASE    0xffffU
+#define V_INGRESS2_BASE(x) ((x) << S_INGRESS2_BASE)
+#define G_INGRESS2_BASE(x) (((x) >> S_INGRESS2_BASE) & M_INGRESS2_BASE)
+
+#define S_INGRESS1_BASE    0
+#define M_INGRESS1_BASE    0xffffU
+#define V_INGRESS1_BASE(x) ((x) << S_INGRESS1_BASE)
+#define G_INGRESS1_BASE(x) (((x) >> S_INGRESS1_BASE) & M_INGRESS1_BASE)
+
+#define A_SGE_LA_RDPTR_0 0x1800
+#define A_SGE_LA_RDDATA_0 0x1804
+#define A_SGE_LA_WRPTR_0 0x1808
+#define A_SGE_LA_RESERVED_0 0x180c
+#define A_SGE_LA_RDPTR_1 0x1810
+#define A_SGE_LA_RDDATA_1 0x1814
+#define A_SGE_LA_WRPTR_1 0x1818
+#define A_SGE_LA_RESERVED_1 0x181c
+#define A_SGE_LA_RDPTR_2 0x1820
+#define A_SGE_LA_RDDATA_2 0x1824
+#define A_SGE_LA_WRPTR_2 0x1828
+#define A_SGE_LA_RESERVED_2 0x182c
+#define A_SGE_LA_RDPTR_3 0x1830
+#define A_SGE_LA_RDDATA_3 0x1834
+#define A_SGE_LA_WRPTR_3 0x1838
+#define A_SGE_LA_RESERVED_3 0x183c
+#define A_SGE_LA_RDPTR_4 0x1840
+#define A_SGE_LA_RDDATA_4 0x1844
+#define A_SGE_LA_WRPTR_4 0x1848
+#define A_SGE_LA_RESERVED_4 0x184c
+#define A_SGE_LA_RDPTR_5 0x1850
+#define A_SGE_LA_RDDATA_5 0x1854
+#define A_SGE_LA_WRPTR_5 0x1858
+#define A_SGE_LA_RESERVED_5 0x185c
+#define A_SGE_LA_RDPTR_6 0x1860
+#define A_SGE_LA_RDDATA_6 0x1864
+#define A_SGE_LA_WRPTR_6 0x1868
+#define A_SGE_LA_RESERVED_6 0x186c
+#define A_SGE_LA_RDPTR_7 0x1870
+#define A_SGE_LA_RDDATA_7 0x1874
+#define A_SGE_LA_WRPTR_7 0x1878
+#define A_SGE_LA_RESERVED_7 0x187c
+#define A_SGE_LA_RDPTR_8 0x1880
+#define A_SGE_LA_RDDATA_8 0x1884
+#define A_SGE_LA_WRPTR_8 0x1888
+#define A_SGE_LA_RESERVED_8 0x188c
+#define A_SGE_LA_RDPTR_9 0x1890
+#define A_SGE_LA_RDDATA_9 0x1894
+#define A_SGE_LA_WRPTR_9 0x1898
+#define A_SGE_LA_RESERVED_9 0x189c
+#define A_SGE_LA_RDPTR_10 0x18a0
+#define A_SGE_LA_RDDATA_10 0x18a4
+#define A_SGE_LA_WRPTR_10 0x18a8
+#define A_SGE_LA_RESERVED_10 0x18ac
+#define A_SGE_LA_RDPTR_11 0x18b0
+#define A_SGE_LA_RDDATA_11 0x18b4
+#define A_SGE_LA_WRPTR_11 0x18b8
+#define A_SGE_LA_RESERVED_11 0x18bc
+#define A_SGE_LA_RDPTR_12 0x18c0
+#define A_SGE_LA_RDDATA_12 0x18c4
+#define A_SGE_LA_WRPTR_12 0x18c8
+#define A_SGE_LA_RESERVED_12 0x18cc
+#define A_SGE_LA_RDPTR_13 0x18d0
+#define A_SGE_LA_RDDATA_13 0x18d4
+#define A_SGE_LA_WRPTR_13 0x18d8
+#define A_SGE_LA_RESERVED_13 0x18dc
+#define A_SGE_LA_RDPTR_14 0x18e0
+#define A_SGE_LA_RDDATA_14 0x18e4
+#define A_SGE_LA_WRPTR_14 0x18e8
+#define A_SGE_LA_RESERVED_14 0x18ec
+#define A_SGE_LA_RDPTR_15 0x18f0
+#define A_SGE_LA_RDDATA_15 0x18f4
+#define A_SGE_LA_WRPTR_15 0x18f8
+#define A_SGE_LA_RESERVED_15 0x18fc
+
+/* registers for module PCIE */
+#define PCIE_BASE_ADDR 0x3000
+
+#define A_PCIE_PF_CFG 0x40
+
+#define S_INTXSTAT    16
+#define V_INTXSTAT(x) ((x) << S_INTXSTAT)
+#define F_INTXSTAT    V_INTXSTAT(1U)
+
+#define S_AUXPWRPMEN    15
+#define V_AUXPWRPMEN(x) ((x) << S_AUXPWRPMEN)
+#define F_AUXPWRPMEN    V_AUXPWRPMEN(1U)
+
+#define S_NOSOFTRESET    14
+#define V_NOSOFTRESET(x) ((x) << S_NOSOFTRESET)
+#define F_NOSOFTRESET    V_NOSOFTRESET(1U)
+
+#define S_AIVEC    4
+#define M_AIVEC    0x3ffU
+#define V_AIVEC(x) ((x) << S_AIVEC)
+#define G_AIVEC(x) (((x) >> S_AIVEC) & M_AIVEC)
+
+#define S_INTXTYPE    2
+#define M_INTXTYPE    0x3U
+#define V_INTXTYPE(x) ((x) << S_INTXTYPE)
+#define G_INTXTYPE(x) (((x) >> S_INTXTYPE) & M_INTXTYPE)
+
+#define S_D3HOTEN    1
+#define V_D3HOTEN(x) ((x) << S_D3HOTEN)
+#define F_D3HOTEN    V_D3HOTEN(1U)
+
+#define S_CLIDECEN    0
+#define V_CLIDECEN(x) ((x) << S_CLIDECEN)
+#define F_CLIDECEN    V_CLIDECEN(1U)
+
+#define A_PCIE_PF_CLI 0x44
+#define A_PCIE_PF_GEN_MSG 0x48
+
+#define S_MSGTYPE    0
+#define M_MSGTYPE    0xffU
+#define V_MSGTYPE(x) ((x) << S_MSGTYPE)
+#define G_MSGTYPE(x) (((x) >> S_MSGTYPE) & M_MSGTYPE)
+
+#define A_PCIE_PF_EXPROM_OFST 0x4c
+
+#define S_OFFSET    10
+#define M_OFFSET    0x3fffU
+#define V_OFFSET(x) ((x) << S_OFFSET)
+#define G_OFFSET(x) (((x) >> S_OFFSET) & M_OFFSET)
+
+#define A_PCIE_INT_ENABLE 0x3000
+
+#define S_NONFATALERR    30
+#define V_NONFATALERR(x) ((x) << S_NONFATALERR)
+#define F_NONFATALERR    V_NONFATALERR(1U)
+
+#define S_UNXSPLCPLERR    29
+#define V_UNXSPLCPLERR(x) ((x) << S_UNXSPLCPLERR)
+#define F_UNXSPLCPLERR    V_UNXSPLCPLERR(1U)
+
+#define S_PCIEPINT    28
+#define V_PCIEPINT(x) ((x) << S_PCIEPINT)
+#define F_PCIEPINT    V_PCIEPINT(1U)
+
+#define S_PCIESINT    27
+#define V_PCIESINT(x) ((x) << S_PCIESINT)
+#define F_PCIESINT    V_PCIESINT(1U)
+
+#define S_RPLPERR    26
+#define V_RPLPERR(x) ((x) << S_RPLPERR)
+#define F_RPLPERR    V_RPLPERR(1U)
+
+#define S_RXWRPERR    25
+#define V_RXWRPERR(x) ((x) << S_RXWRPERR)
+#define F_RXWRPERR    V_RXWRPERR(1U)
+
+#define S_RXCPLPERR    24
+#define V_RXCPLPERR(x) ((x) << S_RXCPLPERR)
+#define F_RXCPLPERR    V_RXCPLPERR(1U)
+
+#define S_PIOTAGPERR    23
+#define V_PIOTAGPERR(x) ((x) << S_PIOTAGPERR)
+#define F_PIOTAGPERR    V_PIOTAGPERR(1U)
+
+#define S_MATAGPERR    22
+#define V_MATAGPERR(x) ((x) << S_MATAGPERR)
+#define F_MATAGPERR    V_MATAGPERR(1U)
+
+#define S_INTXCLRPERR    21
+#define V_INTXCLRPERR(x) ((x) << S_INTXCLRPERR)
+#define F_INTXCLRPERR    V_INTXCLRPERR(1U)
+
+#define S_FIDPERR    20
+#define V_FIDPERR(x) ((x) << S_FIDPERR)
+#define F_FIDPERR    V_FIDPERR(1U)
+
+#define S_CFGSNPPERR    19
+#define V_CFGSNPPERR(x) ((x) << S_CFGSNPPERR)
+#define F_CFGSNPPERR    V_CFGSNPPERR(1U)
+
+#define S_HRSPPERR    18
+#define V_HRSPPERR(x) ((x) << S_HRSPPERR)
+#define F_HRSPPERR    V_HRSPPERR(1U)
+
+#define S_HREQPERR    17
+#define V_HREQPERR(x) ((x) << S_HREQPERR)
+#define F_HREQPERR    V_HREQPERR(1U)
+
+#define S_HCNTPERR    16
+#define V_HCNTPERR(x) ((x) << S_HCNTPERR)
+#define F_HCNTPERR    V_HCNTPERR(1U)
+
+#define S_DRSPPERR    15
+#define V_DRSPPERR(x) ((x) << S_DRSPPERR)
+#define F_DRSPPERR    V_DRSPPERR(1U)
+
+#define S_DREQPERR    14
+#define V_DREQPERR(x) ((x) << S_DREQPERR)
+#define F_DREQPERR    V_DREQPERR(1U)
+
+#define S_DCNTPERR    13
+#define V_DCNTPERR(x) ((x) << S_DCNTPERR)
+#define F_DCNTPERR    V_DCNTPERR(1U)
+
+#define S_CRSPPERR    12
+#define V_CRSPPERR(x) ((x) << S_CRSPPERR)
+#define F_CRSPPERR    V_CRSPPERR(1U)
+
+#define S_CREQPERR    11
+#define V_CREQPERR(x) ((x) << S_CREQPERR)
+#define F_CREQPERR    V_CREQPERR(1U)
+
+#define S_CCNTPERR    10
+#define V_CCNTPERR(x) ((x) << S_CCNTPERR)
+#define F_CCNTPERR    V_CCNTPERR(1U)
+
+#define S_TARTAGPERR    9
+#define V_TARTAGPERR(x) ((x) << S_TARTAGPERR)
+#define F_TARTAGPERR    V_TARTAGPERR(1U)
+
+#define S_PIOREQPERR    8
+#define V_PIOREQPERR(x) ((x) << S_PIOREQPERR)
+#define F_PIOREQPERR    V_PIOREQPERR(1U)
+
+#define S_PIOCPLPERR    7
+#define V_PIOCPLPERR(x) ((x) << S_PIOCPLPERR)
+#define F_PIOCPLPERR    V_PIOCPLPERR(1U)
+
+#define S_MSIXDIPERR    6
+#define V_MSIXDIPERR(x) ((x) << S_MSIXDIPERR)
+#define F_MSIXDIPERR    V_MSIXDIPERR(1U)
+
+#define S_MSIXDATAPERR    5
+#define V_MSIXDATAPERR(x) ((x) << S_MSIXDATAPERR)
+#define F_MSIXDATAPERR    V_MSIXDATAPERR(1U)
+
+#define S_MSIXADDRHPERR    4
+#define V_MSIXADDRHPERR(x) ((x) << S_MSIXADDRHPERR)
+#define F_MSIXADDRHPERR    V_MSIXADDRHPERR(1U)
+
+#define S_MSIXADDRLPERR    3
+#define V_MSIXADDRLPERR(x) ((x) << S_MSIXADDRLPERR)
+#define F_MSIXADDRLPERR    V_MSIXADDRLPERR(1U)
+
+#define S_MSIDATAPERR    2
+#define V_MSIDATAPERR(x) ((x) << S_MSIDATAPERR)
+#define F_MSIDATAPERR    V_MSIDATAPERR(1U)
+
+#define S_MSIADDRHPERR    1
+#define V_MSIADDRHPERR(x) ((x) << S_MSIADDRHPERR)
+#define F_MSIADDRHPERR    V_MSIADDRHPERR(1U)
+
+#define S_MSIADDRLPERR    0
+#define V_MSIADDRLPERR(x) ((x) << S_MSIADDRLPERR)
+#define F_MSIADDRLPERR    V_MSIADDRLPERR(1U)
+
+#define S_IPGRPPERR    31
+#define V_IPGRPPERR(x) ((x) << S_IPGRPPERR)
+#define F_IPGRPPERR    V_IPGRPPERR(1U)
+
+#define S_READRSPERR    29
+#define V_READRSPERR(x) ((x) << S_READRSPERR)
+#define F_READRSPERR    V_READRSPERR(1U)
+
+#define S_TRGT1GRPPERR    28
+#define V_TRGT1GRPPERR(x) ((x) << S_TRGT1GRPPERR)
+#define F_TRGT1GRPPERR    V_TRGT1GRPPERR(1U)
+
+#define S_IPSOTPERR    27
+#define V_IPSOTPERR(x) ((x) << S_IPSOTPERR)
+#define F_IPSOTPERR    V_IPSOTPERR(1U)
+
+#define S_IPRETRYPERR    26
+#define V_IPRETRYPERR(x) ((x) << S_IPRETRYPERR)
+#define F_IPRETRYPERR    V_IPRETRYPERR(1U)
+
+#define S_IPRXDATAGRPPERR    25
+#define V_IPRXDATAGRPPERR(x) ((x) << S_IPRXDATAGRPPERR)
+#define F_IPRXDATAGRPPERR    V_IPRXDATAGRPPERR(1U)
+
+#define S_IPRXHDRGRPPERR    24
+#define V_IPRXHDRGRPPERR(x) ((x) << S_IPRXHDRGRPPERR)
+#define F_IPRXHDRGRPPERR    V_IPRXHDRGRPPERR(1U)
+
+#define S_PIOTAGQPERR    23
+#define V_PIOTAGQPERR(x) ((x) << S_PIOTAGQPERR)
+#define F_PIOTAGQPERR    V_PIOTAGQPERR(1U)
+
+#define S_MAGRPPERR    22
+#define V_MAGRPPERR(x) ((x) << S_MAGRPPERR)
+#define F_MAGRPPERR    V_MAGRPPERR(1U)
+
+#define S_VFIDPERR    21
+#define V_VFIDPERR(x) ((x) << S_VFIDPERR)
+#define F_VFIDPERR    V_VFIDPERR(1U)
+
+#define S_HREQRDPERR    17
+#define V_HREQRDPERR(x) ((x) << S_HREQRDPERR)
+#define F_HREQRDPERR    V_HREQRDPERR(1U)
+
+#define S_HREQWRPERR    16
+#define V_HREQWRPERR(x) ((x) << S_HREQWRPERR)
+#define F_HREQWRPERR    V_HREQWRPERR(1U)
+
+#define S_DREQRDPERR    14
+#define V_DREQRDPERR(x) ((x) << S_DREQRDPERR)
+#define F_DREQRDPERR    V_DREQRDPERR(1U)
+
+#define S_DREQWRPERR    13
+#define V_DREQWRPERR(x) ((x) << S_DREQWRPERR)
+#define F_DREQWRPERR    V_DREQWRPERR(1U)
+
+#define S_CREQRDPERR    11
+#define V_CREQRDPERR(x) ((x) << S_CREQRDPERR)
+#define F_CREQRDPERR    V_CREQRDPERR(1U)
+
+#define S_MSTTAGQPERR    10
+#define V_MSTTAGQPERR(x) ((x) << S_MSTTAGQPERR)
+#define F_MSTTAGQPERR    V_MSTTAGQPERR(1U)
+
+#define S_TGTTAGQPERR    9
+#define V_TGTTAGQPERR(x) ((x) << S_TGTTAGQPERR)
+#define F_TGTTAGQPERR    V_TGTTAGQPERR(1U)
+
+#define S_PIOREQGRPPERR    8
+#define V_PIOREQGRPPERR(x) ((x) << S_PIOREQGRPPERR)
+#define F_PIOREQGRPPERR    V_PIOREQGRPPERR(1U)
+
+#define S_PIOCPLGRPPERR    7
+#define V_PIOCPLGRPPERR(x) ((x) << S_PIOCPLGRPPERR)
+#define F_PIOCPLGRPPERR    V_PIOCPLGRPPERR(1U)
+
+#define S_MSIXSTIPERR    2
+#define V_MSIXSTIPERR(x) ((x) << S_MSIXSTIPERR)
+#define F_MSIXSTIPERR    V_MSIXSTIPERR(1U)
+
+#define S_MSTTIMEOUTPERR    1
+#define V_MSTTIMEOUTPERR(x) ((x) << S_MSTTIMEOUTPERR)
+#define F_MSTTIMEOUTPERR    V_MSTTIMEOUTPERR(1U)
+
+#define S_MSTGRPPERR    0
+#define V_MSTGRPPERR(x) ((x) << S_MSTGRPPERR)
+#define F_MSTGRPPERR    V_MSTGRPPERR(1U)
+
+#define A_PCIE_INT_CAUSE 0x3004
+#define A_PCIE_PERR_ENABLE 0x3008
+#define A_PCIE_PERR_INJECT 0x300c
+
+#define S_IDE    0
+#define V_IDE(x) ((x) << S_IDE)
+#define F_IDE    V_IDE(1U)
+
+#define A_PCIE_NONFAT_ERR 0x3010
+
+#define S_RDRSPERR    9
+#define V_RDRSPERR(x) ((x) << S_RDRSPERR)
+#define F_RDRSPERR    V_RDRSPERR(1U)
+
+#define S_VPDRSPERR    8
+#define V_VPDRSPERR(x) ((x) << S_VPDRSPERR)
+#define F_VPDRSPERR    V_VPDRSPERR(1U)
+
+#define S_POPD    7
+#define V_POPD(x) ((x) << S_POPD)
+#define F_POPD    V_POPD(1U)
+
+#define S_POPH    6
+#define V_POPH(x) ((x) << S_POPH)
+#define F_POPH    V_POPH(1U)
+
+#define S_POPC    5
+#define V_POPC(x) ((x) << S_POPC)
+#define F_POPC    V_POPC(1U)
+
+#define S_MEMREQ    4
+#define V_MEMREQ(x) ((x) << S_MEMREQ)
+#define F_MEMREQ    V_MEMREQ(1U)
+
+#define S_PIOREQ    3
+#define V_PIOREQ(x) ((x) << S_PIOREQ)
+#define F_PIOREQ    V_PIOREQ(1U)
+
+#define S_TAGDROP    2
+#define V_TAGDROP(x) ((x) << S_TAGDROP)
+#define F_TAGDROP    V_TAGDROP(1U)
+
+#define S_TAGCPL    1
+#define V_TAGCPL(x) ((x) << S_TAGCPL)
+#define F_TAGCPL    V_TAGCPL(1U)
+
+#define S_CFGSNP    0
+#define V_CFGSNP(x) ((x) << S_CFGSNP)
+#define F_CFGSNP    V_CFGSNP(1U)
+
+#define S_MAREQTIMEOUT    29
+#define V_MAREQTIMEOUT(x) ((x) << S_MAREQTIMEOUT)
+#define F_MAREQTIMEOUT    V_MAREQTIMEOUT(1U)
+
+#define S_TRGT1BARTYPEERR    28
+#define V_TRGT1BARTYPEERR(x) ((x) << S_TRGT1BARTYPEERR)
+#define F_TRGT1BARTYPEERR    V_TRGT1BARTYPEERR(1U)
+
+#define S_MAEXTRARSPERR    27
+#define V_MAEXTRARSPERR(x) ((x) << S_MAEXTRARSPERR)
+#define F_MAEXTRARSPERR    V_MAEXTRARSPERR(1U)
+
+#define S_MARSPTIMEOUT    26
+#define V_MARSPTIMEOUT(x) ((x) << S_MARSPTIMEOUT)
+#define F_MARSPTIMEOUT    V_MARSPTIMEOUT(1U)
+
+#define S_INTVFALLMSIDISERR    25
+#define V_INTVFALLMSIDISERR(x) ((x) << S_INTVFALLMSIDISERR)
+#define F_INTVFALLMSIDISERR    V_INTVFALLMSIDISERR(1U)
+
+#define S_INTVFRANGEERR    24
+#define V_INTVFRANGEERR(x) ((x) << S_INTVFRANGEERR)
+#define F_INTVFRANGEERR    V_INTVFRANGEERR(1U)
+
+#define S_INTPLIRSPERR    23
+#define V_INTPLIRSPERR(x) ((x) << S_INTPLIRSPERR)
+#define F_INTPLIRSPERR    V_INTPLIRSPERR(1U)
+
+#define S_MEMREQRDTAGERR    22
+#define V_MEMREQRDTAGERR(x) ((x) << S_MEMREQRDTAGERR)
+#define F_MEMREQRDTAGERR    V_MEMREQRDTAGERR(1U)
+
+#define S_CFGINITDONEERR    21
+#define V_CFGINITDONEERR(x) ((x) << S_CFGINITDONEERR)
+#define F_CFGINITDONEERR    V_CFGINITDONEERR(1U)
+
+#define S_BAR2TIMEOUT    20
+#define V_BAR2TIMEOUT(x) ((x) << S_BAR2TIMEOUT)
+#define F_BAR2TIMEOUT    V_BAR2TIMEOUT(1U)
+
+#define S_VPDTIMEOUT    19
+#define V_VPDTIMEOUT(x) ((x) << S_VPDTIMEOUT)
+#define F_VPDTIMEOUT    V_VPDTIMEOUT(1U)
+
+#define S_MEMRSPRDTAGERR    18
+#define V_MEMRSPRDTAGERR(x) ((x) << S_MEMRSPRDTAGERR)
+#define F_MEMRSPRDTAGERR    V_MEMRSPRDTAGERR(1U)
+
+#define S_MEMRSPWRTAGERR    17
+#define V_MEMRSPWRTAGERR(x) ((x) << S_MEMRSPWRTAGERR)
+#define F_MEMRSPWRTAGERR    V_MEMRSPWRTAGERR(1U)
+
+#define S_PIORSPRDTAGERR    16
+#define V_PIORSPRDTAGERR(x) ((x) << S_PIORSPRDTAGERR)
+#define F_PIORSPRDTAGERR    V_PIORSPRDTAGERR(1U)
+
+#define S_PIORSPWRTAGERR    15
+#define V_PIORSPWRTAGERR(x) ((x) << S_PIORSPWRTAGERR)
+#define F_PIORSPWRTAGERR    V_PIORSPWRTAGERR(1U)
+
+#define S_DBITIMEOUT    14
+#define V_DBITIMEOUT(x) ((x) << S_DBITIMEOUT)
+#define F_DBITIMEOUT    V_DBITIMEOUT(1U)
+
+#define S_PIOUNALINDWR    13
+#define V_PIOUNALINDWR(x) ((x) << S_PIOUNALINDWR)
+#define F_PIOUNALINDWR    V_PIOUNALINDWR(1U)
+
+#define S_BAR2RDERR    12
+#define V_BAR2RDERR(x) ((x) << S_BAR2RDERR)
+#define F_BAR2RDERR    V_BAR2RDERR(1U)
+
+#define S_MAWREOPERR    11
+#define V_MAWREOPERR(x) ((x) << S_MAWREOPERR)
+#define F_MAWREOPERR    V_MAWREOPERR(1U)
+
+#define S_MARDEOPERR    10
+#define V_MARDEOPERR(x) ((x) << S_MARDEOPERR)
+#define F_MARDEOPERR    V_MARDEOPERR(1U)
+
+#define S_BAR2REQ    2
+#define V_BAR2REQ(x) ((x) << S_BAR2REQ)
+#define F_BAR2REQ    V_BAR2REQ(1U)
+
+#define A_PCIE_CFG 0x3014
+
+#define S_CFGDMAXPYLDSZRX    26
+#define M_CFGDMAXPYLDSZRX    0x7U
+#define V_CFGDMAXPYLDSZRX(x) ((x) << S_CFGDMAXPYLDSZRX)
+#define G_CFGDMAXPYLDSZRX(x) (((x) >> S_CFGDMAXPYLDSZRX) & M_CFGDMAXPYLDSZRX)
+
+#define S_CFGDMAXPYLDSZTX    23
+#define M_CFGDMAXPYLDSZTX    0x7U
+#define V_CFGDMAXPYLDSZTX(x) ((x) << S_CFGDMAXPYLDSZTX)
+#define G_CFGDMAXPYLDSZTX(x) (((x) >> S_CFGDMAXPYLDSZTX) & M_CFGDMAXPYLDSZTX)
+
+#define S_CFGDMAXRDREQSZ    20
+#define M_CFGDMAXRDREQSZ    0x7U
+#define V_CFGDMAXRDREQSZ(x) ((x) << S_CFGDMAXRDREQSZ)
+#define G_CFGDMAXRDREQSZ(x) (((x) >> S_CFGDMAXRDREQSZ) & M_CFGDMAXRDREQSZ)
+
+#define S_MASYNCEN    19
+#define V_MASYNCEN(x) ((x) << S_MASYNCEN)
+#define F_MASYNCEN    V_MASYNCEN(1U)
+
+#define S_DCAENDMA    18
+#define V_DCAENDMA(x) ((x) << S_DCAENDMA)
+#define F_DCAENDMA    V_DCAENDMA(1U)
+
+#define S_DCAENCMD    17
+#define V_DCAENCMD(x) ((x) << S_DCAENCMD)
+#define F_DCAENCMD    V_DCAENCMD(1U)
+
+#define S_VFMSIPNDEN    16
+#define V_VFMSIPNDEN(x) ((x) << S_VFMSIPNDEN)
+#define F_VFMSIPNDEN    V_VFMSIPNDEN(1U)
+
+#define S_FORCETXERROR    15
+#define V_FORCETXERROR(x) ((x) << S_FORCETXERROR)
+#define F_FORCETXERROR    V_FORCETXERROR(1U)
+
+#define S_VPDREQPROTECT    14
+#define V_VPDREQPROTECT(x) ((x) << S_VPDREQPROTECT)
+#define F_VPDREQPROTECT    V_VPDREQPROTECT(1U)
+
+#define S_FIDTABLEINVALID    13
+#define V_FIDTABLEINVALID(x) ((x) << S_FIDTABLEINVALID)
+#define F_FIDTABLEINVALID    V_FIDTABLEINVALID(1U)
+
+#define S_BYPASSMSIXCACHE    12
+#define V_BYPASSMSIXCACHE(x) ((x) << S_BYPASSMSIXCACHE)
+#define F_BYPASSMSIXCACHE    V_BYPASSMSIXCACHE(1U)
+
+#define S_BYPASSMSICACHE    11
+#define V_BYPASSMSICACHE(x) ((x) << S_BYPASSMSICACHE)
+#define F_BYPASSMSICACHE    V_BYPASSMSICACHE(1U)
+
+#define S_SIMSPEED    10
+#define V_SIMSPEED(x) ((x) << S_SIMSPEED)
+#define F_SIMSPEED    V_SIMSPEED(1U)
+
+#define S_TC0_STAMP    9
+#define V_TC0_STAMP(x) ((x) << S_TC0_STAMP)
+#define F_TC0_STAMP    V_TC0_STAMP(1U)
+
+#define S_AI_TCVAL    6
+#define M_AI_TCVAL    0x7U
+#define V_AI_TCVAL(x) ((x) << S_AI_TCVAL)
+#define G_AI_TCVAL(x) (((x) >> S_AI_TCVAL) & M_AI_TCVAL)
+
+#define S_DMASTOPEN    5
+#define V_DMASTOPEN(x) ((x) << S_DMASTOPEN)
+#define F_DMASTOPEN    V_DMASTOPEN(1U)
+
+#define S_DEVSTATERSTMODE    4
+#define V_DEVSTATERSTMODE(x) ((x) << S_DEVSTATERSTMODE)
+#define F_DEVSTATERSTMODE    V_DEVSTATERSTMODE(1U)
+
+#define S_HOTRSTPCIECRSTMODE    3
+#define V_HOTRSTPCIECRSTMODE(x) ((x) << S_HOTRSTPCIECRSTMODE)
+#define F_HOTRSTPCIECRSTMODE    V_HOTRSTPCIECRSTMODE(1U)
+
+#define S_DLDNPCIECRSTMODE    2
+#define V_DLDNPCIECRSTMODE(x) ((x) << S_DLDNPCIECRSTMODE)
+#define F_DLDNPCIECRSTMODE    V_DLDNPCIECRSTMODE(1U)
+
+#define S_DLDNPCIEPRECRSTMODE    1
+#define V_DLDNPCIEPRECRSTMODE(x) ((x) << S_DLDNPCIEPRECRSTMODE)
+#define F_DLDNPCIEPRECRSTMODE    V_DLDNPCIEPRECRSTMODE(1U)
+
+#define S_LINKDNRSTEN    0
+#define V_LINKDNRSTEN(x) ((x) << S_LINKDNRSTEN)
+#define F_LINKDNRSTEN    V_LINKDNRSTEN(1U)
+
+#define S_DIAGCTRLBUS    28
+#define M_DIAGCTRLBUS    0x7U
+#define V_DIAGCTRLBUS(x) ((x) << S_DIAGCTRLBUS)
+#define G_DIAGCTRLBUS(x) (((x) >> S_DIAGCTRLBUS) & M_DIAGCTRLBUS)
+
+#define S_IPPERREN    27
+#define V_IPPERREN(x) ((x) << S_IPPERREN)
+#define F_IPPERREN    V_IPPERREN(1U)
+
+#define S_CFGDEXTTAGEN    26
+#define V_CFGDEXTTAGEN(x) ((x) << S_CFGDEXTTAGEN)
+#define F_CFGDEXTTAGEN    V_CFGDEXTTAGEN(1U)
+
+#define S_CFGDMAXPYLDSZ    23
+#define M_CFGDMAXPYLDSZ    0x7U
+#define V_CFGDMAXPYLDSZ(x) ((x) << S_CFGDMAXPYLDSZ)
+#define G_CFGDMAXPYLDSZ(x) (((x) >> S_CFGDMAXPYLDSZ) & M_CFGDMAXPYLDSZ)
+
+#define S_DCAEN    17
+#define V_DCAEN(x) ((x) << S_DCAEN)
+#define F_DCAEN    V_DCAEN(1U)
+
+#define S_T5CMDREQPRIORITY    16
+#define V_T5CMDREQPRIORITY(x) ((x) << S_T5CMDREQPRIORITY)
+#define F_T5CMDREQPRIORITY    V_T5CMDREQPRIORITY(1U)
+
+#define S_T5VPDREQPROTECT    14
+#define M_T5VPDREQPROTECT    0x3U
+#define V_T5VPDREQPROTECT(x) ((x) << S_T5VPDREQPROTECT)
+#define G_T5VPDREQPROTECT(x) (((x) >> S_T5VPDREQPROTECT) & M_T5VPDREQPROTECT)
+
+#define S_DROPPEDRDRSPDATA    12
+#define V_DROPPEDRDRSPDATA(x) ((x) << S_DROPPEDRDRSPDATA)
+#define F_DROPPEDRDRSPDATA    V_DROPPEDRDRSPDATA(1U)
+
+#define S_AI_INTX_REASSERTEN    11
+#define V_AI_INTX_REASSERTEN(x) ((x) << S_AI_INTX_REASSERTEN)
+#define F_AI_INTX_REASSERTEN    V_AI_INTX_REASSERTEN(1U)
+
+#define S_AUTOTXNDISABLE    10
+#define V_AUTOTXNDISABLE(x) ((x) << S_AUTOTXNDISABLE)
+#define F_AUTOTXNDISABLE    V_AUTOTXNDISABLE(1U)
+
+#define S_LINKREQRSTPCIECRSTMODE    3
+#define V_LINKREQRSTPCIECRSTMODE(x) ((x) << S_LINKREQRSTPCIECRSTMODE)
+#define F_LINKREQRSTPCIECRSTMODE    V_LINKREQRSTPCIECRSTMODE(1U)
+
+#define A_PCIE_DMA_CTRL 0x3018
+
+#define S_LITTLEENDIAN    7
+#define V_LITTLEENDIAN(x) ((x) << S_LITTLEENDIAN)
+#define F_LITTLEENDIAN    V_LITTLEENDIAN(1U)
+
+#define A_PCIE_CFG2 0x3018
+
+#define S_VPDTIMER    16
+#define M_VPDTIMER    0xffffU
+#define V_VPDTIMER(x) ((x) << S_VPDTIMER)
+#define G_VPDTIMER(x) (((x) >> S_VPDTIMER) & M_VPDTIMER)
+
+#define S_BAR2TIMER    4
+#define M_BAR2TIMER    0xfffU
+#define V_BAR2TIMER(x) ((x) << S_BAR2TIMER)
+#define G_BAR2TIMER(x) (((x) >> S_BAR2TIMER) & M_BAR2TIMER)
+
+#define S_MSTREQRDRRASIMPLE    3
+#define V_MSTREQRDRRASIMPLE(x) ((x) << S_MSTREQRDRRASIMPLE)
+#define F_MSTREQRDRRASIMPLE    V_MSTREQRDRRASIMPLE(1U)
+
+#define S_TOTMAXTAG    0
+#define M_TOTMAXTAG    0x3U
+#define V_TOTMAXTAG(x) ((x) << S_TOTMAXTAG)
+#define G_TOTMAXTAG(x) (((x) >> S_TOTMAXTAG) & M_TOTMAXTAG)
+
+#define A_PCIE_DMA_CFG 0x301c
+
+#define S_MAXPYLDSIZE    28
+#define M_MAXPYLDSIZE    0x7U
+#define V_MAXPYLDSIZE(x) ((x) << S_MAXPYLDSIZE)
+#define G_MAXPYLDSIZE(x) (((x) >> S_MAXPYLDSIZE) & M_MAXPYLDSIZE)
+
+#define S_MAXRDREQSIZE    25
+#define M_MAXRDREQSIZE    0x7U
+#define V_MAXRDREQSIZE(x) ((x) << S_MAXRDREQSIZE)
+#define G_MAXRDREQSIZE(x) (((x) >> S_MAXRDREQSIZE) & M_MAXRDREQSIZE)
+
+#define S_DMA_MAXRSPCNT    16
+#define M_DMA_MAXRSPCNT    0x1ffU
+#define V_DMA_MAXRSPCNT(x) ((x) << S_DMA_MAXRSPCNT)
+#define G_DMA_MAXRSPCNT(x) (((x) >> S_DMA_MAXRSPCNT) & M_DMA_MAXRSPCNT)
+
+#define S_DMA_MAXREQCNT    8
+#define M_DMA_MAXREQCNT    0xffU
+#define V_DMA_MAXREQCNT(x) ((x) << S_DMA_MAXREQCNT)
+#define G_DMA_MAXREQCNT(x) (((x) >> S_DMA_MAXREQCNT) & M_DMA_MAXREQCNT)
+
+#define S_MAXTAG    0
+#define M_MAXTAG    0x7fU
+#define V_MAXTAG(x) ((x) << S_MAXTAG)
+#define G_MAXTAG(x) (((x) >> S_MAXTAG) & M_MAXTAG)
+
+#define A_PCIE_CFG3 0x301c
+
+#define S_AUTOPIOCOOKIEMATCH    6
+#define V_AUTOPIOCOOKIEMATCH(x) ((x) << S_AUTOPIOCOOKIEMATCH)
+#define F_AUTOPIOCOOKIEMATCH    V_AUTOPIOCOOKIEMATCH(1U)
+
+#define S_FLRPNDCPLMODE    4
+#define M_FLRPNDCPLMODE    0x3U
+#define V_FLRPNDCPLMODE(x) ((x) << S_FLRPNDCPLMODE)
+#define G_FLRPNDCPLMODE(x) (((x) >> S_FLRPNDCPLMODE) & M_FLRPNDCPLMODE)
+
+#define S_HMADCASTFIRSTONLY    2
+#define V_HMADCASTFIRSTONLY(x) ((x) << S_HMADCASTFIRSTONLY)
+#define F_HMADCASTFIRSTONLY    V_HMADCASTFIRSTONLY(1U)
+
+#define S_CMDDCASTFIRSTONLY    1
+#define V_CMDDCASTFIRSTONLY(x) ((x) << S_CMDDCASTFIRSTONLY)
+#define F_CMDDCASTFIRSTONLY    V_CMDDCASTFIRSTONLY(1U)
+
+#define S_DMADCASTFIRSTONLY    0
+#define V_DMADCASTFIRSTONLY(x) ((x) << S_DMADCASTFIRSTONLY)
+#define F_DMADCASTFIRSTONLY    V_DMADCASTFIRSTONLY(1U)
+
+#define A_PCIE_DMA_STAT 0x3020
+
+#define S_STATEREQ    28
+#define M_STATEREQ    0xfU
+#define V_STATEREQ(x) ((x) << S_STATEREQ)
+#define G_STATEREQ(x) (((x) >> S_STATEREQ) & M_STATEREQ)
+
+#define S_DMA_RSPCNT    16
+#define M_DMA_RSPCNT    0xfffU
+#define V_DMA_RSPCNT(x) ((x) << S_DMA_RSPCNT)
+#define G_DMA_RSPCNT(x) (((x) >> S_DMA_RSPCNT) & M_DMA_RSPCNT)
+
+#define S_STATEAREQ    13
+#define M_STATEAREQ    0x7U
+#define V_STATEAREQ(x) ((x) << S_STATEAREQ)
+#define G_STATEAREQ(x) (((x) >> S_STATEAREQ) & M_STATEAREQ)
+
+#define S_TAGFREE    12
+#define V_TAGFREE(x) ((x) << S_TAGFREE)
+#define F_TAGFREE    V_TAGFREE(1U)
+
+#define S_DMA_REQCNT    0
+#define M_DMA_REQCNT    0x7ffU
+#define V_DMA_REQCNT(x) ((x) << S_DMA_REQCNT)
+#define G_DMA_REQCNT(x) (((x) >> S_DMA_REQCNT) & M_DMA_REQCNT)
+
+#define A_PCIE_CFG4 0x3020
+
+#define S_L1CLKREMOVALEN    17
+#define V_L1CLKREMOVALEN(x) ((x) << S_L1CLKREMOVALEN)
+#define F_L1CLKREMOVALEN    V_L1CLKREMOVALEN(1U)
+
+#define S_READYENTERL23    16
+#define V_READYENTERL23(x) ((x) << S_READYENTERL23)
+#define F_READYENTERL23    V_READYENTERL23(1U)
+
+#define S_EXITL1    12
+#define V_EXITL1(x) ((x) << S_EXITL1)
+#define F_EXITL1    V_EXITL1(1U)
+
+#define S_ENTERL1    8
+#define V_ENTERL1(x) ((x) << S_ENTERL1)
+#define F_ENTERL1    V_ENTERL1(1U)
+
+#define S_GENPME    0
+#define M_GENPME    0xffU
+#define V_GENPME(x) ((x) << S_GENPME)
+#define G_GENPME(x) (((x) >> S_GENPME) & M_GENPME)
+
+#define A_PCIE_CFG5 0x3024
+
+#define S_ENABLESKPPARITYFIX    2
+#define V_ENABLESKPPARITYFIX(x) ((x) << S_ENABLESKPPARITYFIX)
+#define F_ENABLESKPPARITYFIX    V_ENABLESKPPARITYFIX(1U)
+
+#define S_ENABLEL2ENTRYINL1    1
+#define V_ENABLEL2ENTRYINL1(x) ((x) << S_ENABLEL2ENTRYINL1)
+#define F_ENABLEL2ENTRYINL1    V_ENABLEL2ENTRYINL1(1U)
+
+#define S_HOLDCPLENTERINGL1    0
+#define V_HOLDCPLENTERINGL1(x) ((x) << S_HOLDCPLENTERINGL1)
+#define F_HOLDCPLENTERINGL1    V_HOLDCPLENTERINGL1(1U)
+
+#define A_PCIE_CFG6 0x3028
+
+#define S_PERSTTIMERCOUNT    12
+#define M_PERSTTIMERCOUNT    0x3fffU
+#define V_PERSTTIMERCOUNT(x) ((x) << S_PERSTTIMERCOUNT)
+#define G_PERSTTIMERCOUNT(x) (((x) >> S_PERSTTIMERCOUNT) & M_PERSTTIMERCOUNT)
+
+#define S_PERSTTIMEOUT    8
+#define V_PERSTTIMEOUT(x) ((x) << S_PERSTTIMEOUT)
+#define F_PERSTTIMEOUT    V_PERSTTIMEOUT(1U)
+
+#define S_PERSTTIMER    0
+#define M_PERSTTIMER    0xfU
+#define V_PERSTTIMER(x) ((x) << S_PERSTTIMER)
+#define G_PERSTTIMER(x) (((x) >> S_PERSTTIMER) & M_PERSTTIMER)
+
+#define A_PCIE_CMD_CTRL 0x303c
+#define A_PCIE_CMD_CFG 0x3040
+
+#define S_MAXRSPCNT    16
+#define M_MAXRSPCNT    0xfU
+#define V_MAXRSPCNT(x) ((x) << S_MAXRSPCNT)
+#define G_MAXRSPCNT(x) (((x) >> S_MAXRSPCNT) & M_MAXRSPCNT)
+
+#define S_MAXREQCNT    8
+#define M_MAXREQCNT    0x1fU
+#define V_MAXREQCNT(x) ((x) << S_MAXREQCNT)
+#define G_MAXREQCNT(x) (((x) >> S_MAXREQCNT) & M_MAXREQCNT)
+
+#define A_PCIE_CMD_STAT 0x3044
+
+#define S_RSPCNT    16
+#define M_RSPCNT    0x7fU
+#define V_RSPCNT(x) ((x) << S_RSPCNT)
+#define G_RSPCNT(x) (((x) >> S_RSPCNT) & M_RSPCNT)
+
+#define S_REQCNT    0
+#define M_REQCNT    0xffU
+#define V_REQCNT(x) ((x) << S_REQCNT)
+#define G_REQCNT(x) (((x) >> S_REQCNT) & M_REQCNT)
+
+#define A_PCIE_HMA_CTRL 0x3050
+
+#define S_IPLTSSM    12
+#define M_IPLTSSM    0xfU
+#define V_IPLTSSM(x) ((x) << S_IPLTSSM)
+#define G_IPLTSSM(x) (((x) >> S_IPLTSSM) & M_IPLTSSM)
+
+#define S_IPCONFIGDOWN    8
+#define M_IPCONFIGDOWN    0x7U
+#define V_IPCONFIGDOWN(x) ((x) << S_IPCONFIGDOWN)
+#define G_IPCONFIGDOWN(x) (((x) >> S_IPCONFIGDOWN) & M_IPCONFIGDOWN)
+
+#define A_PCIE_HMA_CFG 0x3054
+
+#define S_HMA_MAXRSPCNT    16
+#define M_HMA_MAXRSPCNT    0x1fU
+#define V_HMA_MAXRSPCNT(x) ((x) << S_HMA_MAXRSPCNT)
+#define G_HMA_MAXRSPCNT(x) (((x) >> S_HMA_MAXRSPCNT) & M_HMA_MAXRSPCNT)
+
+#define A_PCIE_HMA_STAT 0x3058
+
+#define S_HMA_RSPCNT    16
+#define M_HMA_RSPCNT    0xffU
+#define V_HMA_RSPCNT(x) ((x) << S_HMA_RSPCNT)
+#define G_HMA_RSPCNT(x) (((x) >> S_HMA_RSPCNT) & M_HMA_RSPCNT)
+
+#define A_PCIE_PIO_FIFO_CFG 0x305c
+
+#define S_CPLCONFIG    16
+#define M_CPLCONFIG    0xffffU
+#define V_CPLCONFIG(x) ((x) << S_CPLCONFIG)
+#define G_CPLCONFIG(x) (((x) >> S_CPLCONFIG) & M_CPLCONFIG)
+
+#define S_PIOSTOPEN    12
+#define V_PIOSTOPEN(x) ((x) << S_PIOSTOPEN)
+#define F_PIOSTOPEN    V_PIOSTOPEN(1U)
+
+#define S_IPLANESWAP    11
+#define V_IPLANESWAP(x) ((x) << S_IPLANESWAP)
+#define F_IPLANESWAP    V_IPLANESWAP(1U)
+
+#define S_FORCESTRICTTS1    10
+#define V_FORCESTRICTTS1(x) ((x) << S_FORCESTRICTTS1)
+#define F_FORCESTRICTTS1    V_FORCESTRICTTS1(1U)
+
+#define S_FORCEPROGRESSCNT    0
+#define M_FORCEPROGRESSCNT    0x3ffU
+#define V_FORCEPROGRESSCNT(x) ((x) << S_FORCEPROGRESSCNT)
+#define G_FORCEPROGRESSCNT(x) (((x) >> S_FORCEPROGRESSCNT) & M_FORCEPROGRESSCNT)
+
+#define A_PCIE_CFG_SPACE_REQ 0x3060
+
+#define S_ENABLE    30
+#define V_ENABLE(x) ((x) << S_ENABLE)
+#define F_ENABLE    V_ENABLE(1U)
+
+#define S_AI    29
+#define V_AI(x) ((x) << S_AI)
+#define F_AI    V_AI(1U)
+
+#define S_LOCALCFG    28
+#define V_LOCALCFG(x) ((x) << S_LOCALCFG)
+#define F_LOCALCFG    V_LOCALCFG(1U)
+
+#define S_BUS    20
+#define M_BUS    0xffU
+#define V_BUS(x) ((x) << S_BUS)
+#define G_BUS(x) (((x) >> S_BUS) & M_BUS)
+
+#define S_DEVICE    15
+#define M_DEVICE    0x1fU
+#define V_DEVICE(x) ((x) << S_DEVICE)
+#define G_DEVICE(x) (((x) >> S_DEVICE) & M_DEVICE)
+
+#define S_FUNCTION    12
+#define M_FUNCTION    0x7U
+#define V_FUNCTION(x) ((x) << S_FUNCTION)
+#define G_FUNCTION(x) (((x) >> S_FUNCTION) & M_FUNCTION)
+
+#define S_EXTREGISTER    8
+#define M_EXTREGISTER    0xfU
+#define V_EXTREGISTER(x) ((x) << S_EXTREGISTER)
+#define G_EXTREGISTER(x) (((x) >> S_EXTREGISTER) & M_EXTREGISTER)
+
+#define S_REGISTER    0
+#define M_REGISTER    0xffU
+#define V_REGISTER(x) ((x) << S_REGISTER)
+#define G_REGISTER(x) (((x) >> S_REGISTER) & M_REGISTER)
+
+#define S_CS2    28
+#define V_CS2(x) ((x) << S_CS2)
+#define F_CS2    V_CS2(1U)
+
+#define S_WRBE    24
+#define M_WRBE    0xfU
+#define V_WRBE(x) ((x) << S_WRBE)
+#define G_WRBE(x) (((x) >> S_WRBE) & M_WRBE)
+
+#define S_CFG_SPACE_VFVLD    23
+#define V_CFG_SPACE_VFVLD(x) ((x) << S_CFG_SPACE_VFVLD)
+#define F_CFG_SPACE_VFVLD    V_CFG_SPACE_VFVLD(1U)
+
+#define S_CFG_SPACE_RVF    16
+#define M_CFG_SPACE_RVF    0x7fU
+#define V_CFG_SPACE_RVF(x) ((x) << S_CFG_SPACE_RVF)
+#define G_CFG_SPACE_RVF(x) (((x) >> S_CFG_SPACE_RVF) & M_CFG_SPACE_RVF)
+
+#define S_CFG_SPACE_PF    12
+#define M_CFG_SPACE_PF    0x7U
+#define V_CFG_SPACE_PF(x) ((x) << S_CFG_SPACE_PF)
+#define G_CFG_SPACE_PF(x) (((x) >> S_CFG_SPACE_PF) & M_CFG_SPACE_PF)
+
+#define A_PCIE_CFG_SPACE_DATA 0x3064
+#define A_PCIE_MEM_ACCESS_BASE_WIN 0x3068
+
+#define S_PCIEOFST    10
+#define M_PCIEOFST    0x3fffffU
+#define V_PCIEOFST(x) ((x) << S_PCIEOFST)
+#define G_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST)
+
+#define S_BIR    8
+#define M_BIR    0x3U
+#define V_BIR(x) ((x) << S_BIR)
+#define G_BIR(x) (((x) >> S_BIR) & M_BIR)
+
+#define S_WINDOW    0
+#define M_WINDOW    0xffU
+#define V_WINDOW(x) ((x) << S_WINDOW)
+#define G_WINDOW(x) (((x) >> S_WINDOW) & M_WINDOW)
+
+#define A_PCIE_MEM_ACCESS_OFFSET 0x306c
+
+#define S_MEMOFST    7
+#define M_MEMOFST    0x1ffffffU
+#define V_MEMOFST(x) ((x) << S_MEMOFST)
+#define G_MEMOFST(x) (((x) >> S_MEMOFST) & M_MEMOFST)
+
+#define A_PCIE_MAILBOX_BASE_WIN 0x30a8
+
+#define S_MBOXPCIEOFST    6
+#define M_MBOXPCIEOFST    0x3ffffffU
+#define V_MBOXPCIEOFST(x) ((x) << S_MBOXPCIEOFST)
+#define G_MBOXPCIEOFST(x) (((x) >> S_MBOXPCIEOFST) & M_MBOXPCIEOFST)
+
+#define S_MBOXBIR    4
+#define M_MBOXBIR    0x3U
+#define V_MBOXBIR(x) ((x) << S_MBOXBIR)
+#define G_MBOXBIR(x) (((x) >> S_MBOXBIR) & M_MBOXBIR)
+
+#define S_MBOXWIN    0
+#define M_MBOXWIN    0x3U
+#define V_MBOXWIN(x) ((x) << S_MBOXWIN)
+#define G_MBOXWIN(x) (((x) >> S_MBOXWIN) & M_MBOXWIN)
+
+#define A_PCIE_MAILBOX_OFFSET 0x30ac
+#define A_PCIE_MA_CTRL 0x30b0
+
+#define S_MA_TAGFREE    29
+#define V_MA_TAGFREE(x) ((x) << S_MA_TAGFREE)
+#define F_MA_TAGFREE    V_MA_TAGFREE(1U)
+
+#define S_MA_MAXRSPCNT    24
+#define M_MA_MAXRSPCNT    0x1fU
+#define V_MA_MAXRSPCNT(x) ((x) << S_MA_MAXRSPCNT)
+#define G_MA_MAXRSPCNT(x) (((x) >> S_MA_MAXRSPCNT) & M_MA_MAXRSPCNT)
+
+#define S_MA_MAXREQCNT    16
+#define M_MA_MAXREQCNT    0x1fU
+#define V_MA_MAXREQCNT(x) ((x) << S_MA_MAXREQCNT)
+#define G_MA_MAXREQCNT(x) (((x) >> S_MA_MAXREQCNT) & M_MA_MAXREQCNT)
+
+#define S_MA_LE    15
+#define V_MA_LE(x) ((x) << S_MA_LE)
+#define F_MA_LE    V_MA_LE(1U)
+
+#define S_MA_MAXPYLDSIZE    12
+#define M_MA_MAXPYLDSIZE    0x7U
+#define V_MA_MAXPYLDSIZE(x) ((x) << S_MA_MAXPYLDSIZE)
+#define G_MA_MAXPYLDSIZE(x) (((x) >> S_MA_MAXPYLDSIZE) & M_MA_MAXPYLDSIZE)
+
+#define S_MA_MAXRDREQSIZE    8
+#define M_MA_MAXRDREQSIZE    0x7U
+#define V_MA_MAXRDREQSIZE(x) ((x) << S_MA_MAXRDREQSIZE)
+#define G_MA_MAXRDREQSIZE(x) (((x) >> S_MA_MAXRDREQSIZE) & M_MA_MAXRDREQSIZE)
+
+#define S_MA_MAXTAG    0
+#define M_MA_MAXTAG    0x1fU
+#define V_MA_MAXTAG(x) ((x) << S_MA_MAXTAG)
+#define G_MA_MAXTAG(x) (((x) >> S_MA_MAXTAG) & M_MA_MAXTAG)
+
+#define S_T5_MA_MAXREQCNT    16
+#define M_T5_MA_MAXREQCNT    0x7fU
+#define V_T5_MA_MAXREQCNT(x) ((x) << S_T5_MA_MAXREQCNT)
+#define G_T5_MA_MAXREQCNT(x) (((x) >> S_T5_MA_MAXREQCNT) & M_T5_MA_MAXREQCNT)
+
+#define S_MA_MAXREQSIZE    8
+#define M_MA_MAXREQSIZE    0x7U
+#define V_MA_MAXREQSIZE(x) ((x) << S_MA_MAXREQSIZE)
+#define G_MA_MAXREQSIZE(x) (((x) >> S_MA_MAXREQSIZE) & M_MA_MAXREQSIZE)
+
+#define A_PCIE_MA_SYNC 0x30b4
+#define A_PCIE_FW 0x30b8
+#define A_PCIE_FW_PF 0x30bc
+#define A_PCIE_PIO_PAUSE 0x30dc
+
+#define S_PIOPAUSEDONE    31
+#define V_PIOPAUSEDONE(x) ((x) << S_PIOPAUSEDONE)
+#define F_PIOPAUSEDONE    V_PIOPAUSEDONE(1U)
+
+#define S_PIOPAUSETIME    4
+#define M_PIOPAUSETIME    0xffffffU
+#define V_PIOPAUSETIME(x) ((x) << S_PIOPAUSETIME)
+#define G_PIOPAUSETIME(x) (((x) >> S_PIOPAUSETIME) & M_PIOPAUSETIME)
+
+#define S_PIOPAUSE    0
+#define V_PIOPAUSE(x) ((x) << S_PIOPAUSE)
+#define F_PIOPAUSE    V_PIOPAUSE(1U)
+
+#define S_MSTPAUSEDONE    30
+#define V_MSTPAUSEDONE(x) ((x) << S_MSTPAUSEDONE)
+#define F_MSTPAUSEDONE    V_MSTPAUSEDONE(1U)
+
+#define S_MSTPAUSE    1
+#define V_MSTPAUSE(x) ((x) << S_MSTPAUSE)
+#define F_MSTPAUSE    V_MSTPAUSE(1U)
+
+#define A_PCIE_SYS_CFG_READY 0x30e0
+#define A_PCIE_MA_STAT 0x30e0
+#define A_PCIE_STATIC_CFG1 0x30e4
+
+#define S_LINKDOWN_RESET_EN    26
+#define V_LINKDOWN_RESET_EN(x) ((x) << S_LINKDOWN_RESET_EN)
+#define F_LINKDOWN_RESET_EN    V_LINKDOWN_RESET_EN(1U)
+
+#define S_IN_WR_DISCONTIG    25
+#define V_IN_WR_DISCONTIG(x) ((x) << S_IN_WR_DISCONTIG)
+#define F_IN_WR_DISCONTIG    V_IN_WR_DISCONTIG(1U)
+
+#define S_IN_RD_CPLSIZE    22
+#define M_IN_RD_CPLSIZE    0x7U
+#define V_IN_RD_CPLSIZE(x) ((x) << S_IN_RD_CPLSIZE)
+#define G_IN_RD_CPLSIZE(x) (((x) >> S_IN_RD_CPLSIZE) & M_IN_RD_CPLSIZE)
+
+#define S_IN_RD_BUFMODE    20
+#define M_IN_RD_BUFMODE    0x3U
+#define V_IN_RD_BUFMODE(x) ((x) << S_IN_RD_BUFMODE)
+#define G_IN_RD_BUFMODE(x) (((x) >> S_IN_RD_BUFMODE) & M_IN_RD_BUFMODE)
+
+#define S_GBIF_NPTRANS_TOT    18
+#define M_GBIF_NPTRANS_TOT    0x3U
+#define V_GBIF_NPTRANS_TOT(x) ((x) << S_GBIF_NPTRANS_TOT)
+#define G_GBIF_NPTRANS_TOT(x) (((x) >> S_GBIF_NPTRANS_TOT) & M_GBIF_NPTRANS_TOT)
+
+#define S_IN_PDAT_TOT    15
+#define M_IN_PDAT_TOT    0x7U
+#define V_IN_PDAT_TOT(x) ((x) << S_IN_PDAT_TOT)
+#define G_IN_PDAT_TOT(x) (((x) >> S_IN_PDAT_TOT) & M_IN_PDAT_TOT)
+
+#define S_PCIE_NPTRANS_TOT    12
+#define M_PCIE_NPTRANS_TOT    0x7U
+#define V_PCIE_NPTRANS_TOT(x) ((x) << S_PCIE_NPTRANS_TOT)
+#define G_PCIE_NPTRANS_TOT(x) (((x) >> S_PCIE_NPTRANS_TOT) & M_PCIE_NPTRANS_TOT)
+
+#define S_OUT_PDAT_TOT    9
+#define M_OUT_PDAT_TOT    0x7U
+#define V_OUT_PDAT_TOT(x) ((x) << S_OUT_PDAT_TOT)
+#define G_OUT_PDAT_TOT(x) (((x) >> S_OUT_PDAT_TOT) & M_OUT_PDAT_TOT)
+
+#define S_GBIF_MAX_WRSIZE    6
+#define M_GBIF_MAX_WRSIZE    0x7U
+#define V_GBIF_MAX_WRSIZE(x) ((x) << S_GBIF_MAX_WRSIZE)
+#define G_GBIF_MAX_WRSIZE(x) (((x) >> S_GBIF_MAX_WRSIZE) & M_GBIF_MAX_WRSIZE)
+
+#define S_GBIF_MAX_RDSIZE    3
+#define M_GBIF_MAX_RDSIZE    0x7U
+#define V_GBIF_MAX_RDSIZE(x) ((x) << S_GBIF_MAX_RDSIZE)
+#define G_GBIF_MAX_RDSIZE(x) (((x) >> S_GBIF_MAX_RDSIZE) & M_GBIF_MAX_RDSIZE)
+
+#define S_PCIE_MAX_RDSIZE    0
+#define M_PCIE_MAX_RDSIZE    0x7U
+#define V_PCIE_MAX_RDSIZE(x) ((x) << S_PCIE_MAX_RDSIZE)
+#define G_PCIE_MAX_RDSIZE(x) (((x) >> S_PCIE_MAX_RDSIZE) & M_PCIE_MAX_RDSIZE)
+
+#define S_AUXPOWER_DETECTED    27
+#define V_AUXPOWER_DETECTED(x) ((x) << S_AUXPOWER_DETECTED)
+#define F_AUXPOWER_DETECTED    V_AUXPOWER_DETECTED(1U)
+
+#define A_PCIE_STATIC_CFG2 0x30e8
+
+#define S_PL_CONTROL    16
+#define M_PL_CONTROL    0xffffU
+#define V_PL_CONTROL(x) ((x) << S_PL_CONTROL)
+#define G_PL_CONTROL(x) (((x) >> S_PL_CONTROL) & M_PL_CONTROL)
+
+#define S_STATIC_SPARE3    0
+#define M_STATIC_SPARE3    0x3fffU
+#define V_STATIC_SPARE3(x) ((x) << S_STATIC_SPARE3)
+#define G_STATIC_SPARE3(x) (((x) >> S_STATIC_SPARE3) & M_STATIC_SPARE3)
+
+#define A_PCIE_DBG_INDIR_REQ 0x30ec
+
+#define S_DBGENABLE    31
+#define V_DBGENABLE(x) ((x) << S_DBGENABLE)
+#define F_DBGENABLE    V_DBGENABLE(1U)
+
+#define S_DBGAUTOINC    30
+#define V_DBGAUTOINC(x) ((x) << S_DBGAUTOINC)
+#define F_DBGAUTOINC    V_DBGAUTOINC(1U)
+
+#define S_POINTER    8
+#define M_POINTER    0xffffU
+#define V_POINTER(x) ((x) << S_POINTER)
+#define G_POINTER(x) (((x) >> S_POINTER) & M_POINTER)
+
+#define S_SELECT    0
+#define M_SELECT    0xfU
+#define V_SELECT(x) ((x) << S_SELECT)
+#define G_SELECT(x) (((x) >> S_SELECT) & M_SELECT)
+
+#define A_PCIE_DBG_INDIR_DATA_0 0x30f0
+#define A_PCIE_DBG_INDIR_DATA_1 0x30f4
+#define A_PCIE_DBG_INDIR_DATA_2 0x30f8
+#define A_PCIE_DBG_INDIR_DATA_3 0x30fc
+#define A_PCIE_FUNC_INT_CFG 0x3100
+
+#define S_PBAOFST    28
+#define M_PBAOFST    0xfU
+#define V_PBAOFST(x) ((x) << S_PBAOFST)
+#define G_PBAOFST(x) (((x) >> S_PBAOFST) & M_PBAOFST)
+
+#define S_TABOFST    24
+#define M_TABOFST    0xfU
+#define V_TABOFST(x) ((x) << S_TABOFST)
+#define G_TABOFST(x) (((x) >> S_TABOFST) & M_TABOFST)
+
+#define S_VECNUM    12
+#define M_VECNUM    0x3ffU
+#define V_VECNUM(x) ((x) << S_VECNUM)
+#define G_VECNUM(x) (((x) >> S_VECNUM) & M_VECNUM)
+
+#define S_VECBASE    0
+#define M_VECBASE    0x7ffU
+#define V_VECBASE(x) ((x) << S_VECBASE)
+#define G_VECBASE(x) (((x) >> S_VECBASE) & M_VECBASE)
+
+#define A_PCIE_FUNC_CTL_STAT 0x3104
+
+#define S_SENDFLRRSP    31
+#define V_SENDFLRRSP(x) ((x) << S_SENDFLRRSP)
+#define F_SENDFLRRSP    V_SENDFLRRSP(1U)
+
+#define S_IMMFLRRSP    24
+#define V_IMMFLRRSP(x) ((x) << S_IMMFLRRSP)
+#define F_IMMFLRRSP    V_IMMFLRRSP(1U)
+
+#define S_TXNDISABLE    20
+#define V_TXNDISABLE(x) ((x) << S_TXNDISABLE)
+#define F_TXNDISABLE    V_TXNDISABLE(1U)
+
+#define S_PNDTXNS    8
+#define M_PNDTXNS    0x3ffU
+#define V_PNDTXNS(x) ((x) << S_PNDTXNS)
+#define G_PNDTXNS(x) (((x) >> S_PNDTXNS) & M_PNDTXNS)
+
+#define S_VFVLD    3
+#define V_VFVLD(x) ((x) << S_VFVLD)
+#define F_VFVLD    V_VFVLD(1U)
+
+#define S_PFNUM    0
+#define M_PFNUM    0x7U
+#define V_PFNUM(x) ((x) << S_PFNUM)
+#define G_PFNUM(x) (((x) >> S_PFNUM) & M_PFNUM)
+
+#define A_PCIE_PF_INT_CFG 0x3140
+#define A_PCIE_PF_INT_CFG2 0x3144
+#define A_PCIE_VF_INT_CFG 0x3180
+#define A_PCIE_VF_INT_CFG2 0x3184
+#define A_PCIE_PF_MSI_EN 0x35a8
+
+#define S_PFMSIEN_7_0    0
+#define M_PFMSIEN_7_0    0xffU
+#define V_PFMSIEN_7_0(x) ((x) << S_PFMSIEN_7_0)
+#define G_PFMSIEN_7_0(x) (((x) >> S_PFMSIEN_7_0) & M_PFMSIEN_7_0)
+
+#define A_PCIE_VF_MSI_EN_0 0x35ac
+#define A_PCIE_VF_MSI_EN_1 0x35b0
+#define A_PCIE_VF_MSI_EN_2 0x35b4
+#define A_PCIE_VF_MSI_EN_3 0x35b8
+#define A_PCIE_PF_MSIX_EN 0x35bc
+
+#define S_PFMSIXEN_7_0    0
+#define M_PFMSIXEN_7_0    0xffU
+#define V_PFMSIXEN_7_0(x) ((x) << S_PFMSIXEN_7_0)
+#define G_PFMSIXEN_7_0(x) (((x) >> S_PFMSIXEN_7_0) & M_PFMSIXEN_7_0)
+
+#define A_PCIE_VF_MSIX_EN_0 0x35c0
+#define A_PCIE_VF_MSIX_EN_1 0x35c4
+#define A_PCIE_VF_MSIX_EN_2 0x35c8
+#define A_PCIE_VF_MSIX_EN_3 0x35cc
+#define A_PCIE_FID_VFID_SEL 0x35ec
+
+#define S_FID_VFID_SEL_SELECT    0
+#define M_FID_VFID_SEL_SELECT    0x3U
+#define V_FID_VFID_SEL_SELECT(x) ((x) << S_FID_VFID_SEL_SELECT)
+#define G_FID_VFID_SEL_SELECT(x) (((x) >> S_FID_VFID_SEL_SELECT) & M_FID_VFID_SEL_SELECT)
+
+#define A_PCIE_FID_VFID 0x3600
+
+#define S_FID_VFID_SELECT    30
+#define M_FID_VFID_SELECT    0x3U
+#define V_FID_VFID_SELECT(x) ((x) << S_FID_VFID_SELECT)
+#define G_FID_VFID_SELECT(x) (((x) >> S_FID_VFID_SELECT) & M_FID_VFID_SELECT)
+
+#define S_IDO    24
+#define V_IDO(x) ((x) << S_IDO)
+#define F_IDO    V_IDO(1U)
+
+#define S_FID_VFID_VFID    16
+#define M_FID_VFID_VFID    0xffU
+#define V_FID_VFID_VFID(x) ((x) << S_FID_VFID_VFID)
+#define G_FID_VFID_VFID(x) (((x) >> S_FID_VFID_VFID) & M_FID_VFID_VFID)
+
+#define S_FID_VFID_TC    11
+#define M_FID_VFID_TC    0x7U
+#define V_FID_VFID_TC(x) ((x) << S_FID_VFID_TC)
+#define G_FID_VFID_TC(x) (((x) >> S_FID_VFID_TC) & M_FID_VFID_TC)
+
+#define S_FID_VFID_VFVLD    10
+#define V_FID_VFID_VFVLD(x) ((x) << S_FID_VFID_VFVLD)
+#define F_FID_VFID_VFVLD    V_FID_VFID_VFVLD(1U)
+
+#define S_FID_VFID_PF    7
+#define M_FID_VFID_PF    0x7U
+#define V_FID_VFID_PF(x) ((x) << S_FID_VFID_PF)
+#define G_FID_VFID_PF(x) (((x) >> S_FID_VFID_PF) & M_FID_VFID_PF)
+
+#define S_FID_VFID_RVF    0
+#define M_FID_VFID_RVF    0x7fU
+#define V_FID_VFID_RVF(x) ((x) << S_FID_VFID_RVF)
+#define G_FID_VFID_RVF(x) (((x) >> S_FID_VFID_RVF) & M_FID_VFID_RVF)
+
+#define A_PCIE_FID 0x3900
+
+#define S_PAD    11
+#define V_PAD(x) ((x) << S_PAD)
+#define F_PAD    V_PAD(1U)
+
+#define S_TC    8
+#define M_TC    0x7U
+#define V_TC(x) ((x) << S_TC)
+#define G_TC(x) (((x) >> S_TC) & M_TC)
+
+#define S_FUNC    0
+#define M_FUNC    0xffU
+#define V_FUNC(x) ((x) << S_FUNC)
+#define G_FUNC(x) (((x) >> S_FUNC) & M_FUNC)
+
+#define A_PCIE_COOKIE_STAT 0x5600
+
+#define S_COOKIEB    16
+#define M_COOKIEB    0x3ffU
+#define V_COOKIEB(x) ((x) << S_COOKIEB)
+#define G_COOKIEB(x) (((x) >> S_COOKIEB) & M_COOKIEB)
+
+#define S_COOKIEA    0
+#define M_COOKIEA    0x3ffU
+#define V_COOKIEA(x) ((x) << S_COOKIEA)
+#define G_COOKIEA(x) (((x) >> S_COOKIEA) & M_COOKIEA)
+
+#define A_PCIE_FLR_PIO 0x5620
+
+#define S_RCVDBAR2COOKIE    24
+#define M_RCVDBAR2COOKIE    0xffU
+#define V_RCVDBAR2COOKIE(x) ((x) << S_RCVDBAR2COOKIE)
+#define G_RCVDBAR2COOKIE(x) (((x) >> S_RCVDBAR2COOKIE) & M_RCVDBAR2COOKIE)
+
+#define S_RCVDMARSPCOOKIE    16
+#define M_RCVDMARSPCOOKIE    0xffU
+#define V_RCVDMARSPCOOKIE(x) ((x) << S_RCVDMARSPCOOKIE)
+#define G_RCVDMARSPCOOKIE(x) (((x) >> S_RCVDMARSPCOOKIE) & M_RCVDMARSPCOOKIE)
+
+#define S_RCVDPIORSPCOOKIE    8
+#define M_RCVDPIORSPCOOKIE    0xffU
+#define V_RCVDPIORSPCOOKIE(x) ((x) << S_RCVDPIORSPCOOKIE)
+#define G_RCVDPIORSPCOOKIE(x) (((x) >> S_RCVDPIORSPCOOKIE) & M_RCVDPIORSPCOOKIE)
+
+#define S_EXPDCOOKIE    0
+#define M_EXPDCOOKIE    0xffU
+#define V_EXPDCOOKIE(x) ((x) << S_EXPDCOOKIE)
+#define G_EXPDCOOKIE(x) (((x) >> S_EXPDCOOKIE) & M_EXPDCOOKIE)
+
+#define A_PCIE_FLR_PIO2 0x5624
+
+#define S_RCVDMAREQCOOKIE    16
+#define M_RCVDMAREQCOOKIE    0xffU
+#define V_RCVDMAREQCOOKIE(x) ((x) << S_RCVDMAREQCOOKIE)
+#define G_RCVDMAREQCOOKIE(x) (((x) >> S_RCVDMAREQCOOKIE) & M_RCVDMAREQCOOKIE)
+
+#define S_RCVDPIOREQCOOKIE    8
+#define M_RCVDPIOREQCOOKIE    0xffU
+#define V_RCVDPIOREQCOOKIE(x) ((x) << S_RCVDPIOREQCOOKIE)
+#define G_RCVDPIOREQCOOKIE(x) (((x) >> S_RCVDPIOREQCOOKIE) & M_RCVDPIOREQCOOKIE)
+
+#define A_PCIE_VC0_CDTS0 0x56cc
+
+#define S_CPLD0    20
+#define M_CPLD0    0xfffU
+#define V_CPLD0(x) ((x) << S_CPLD0)
+#define G_CPLD0(x) (((x) >> S_CPLD0) & M_CPLD0)
+
+#define S_PH0    12
+#define M_PH0    0xffU
+#define V_PH0(x) ((x) << S_PH0)
+#define G_PH0(x) (((x) >> S_PH0) & M_PH0)
+
+#define S_PD0    0
+#define M_PD0    0xfffU
+#define V_PD0(x) ((x) << S_PD0)
+#define G_PD0(x) (((x) >> S_PD0) & M_PD0)
+
+#define A_PCIE_VC0_CDTS1 0x56d0
+
+#define S_CPLH0    20
+#define M_CPLH0    0xffU
+#define V_CPLH0(x) ((x) << S_CPLH0)
+#define G_CPLH0(x) (((x) >> S_CPLH0) & M_CPLH0)
+
+#define S_NPH0    12
+#define M_NPH0    0xffU
+#define V_NPH0(x) ((x) << S_NPH0)
+#define G_NPH0(x) (((x) >> S_NPH0) & M_NPH0)
+
+#define S_NPD0    0
+#define M_NPD0    0xfffU
+#define V_NPD0(x) ((x) << S_NPD0)
+#define G_NPD0(x) (((x) >> S_NPD0) & M_NPD0)
+
+#define A_PCIE_VC1_CDTS0 0x56d4
+
+#define S_CPLD1    20
+#define M_CPLD1    0xfffU
+#define V_CPLD1(x) ((x) << S_CPLD1)
+#define G_CPLD1(x) (((x) >> S_CPLD1) & M_CPLD1)
+
+#define S_PH1    12
+#define M_PH1    0xffU
+#define V_PH1(x) ((x) << S_PH1)
+#define G_PH1(x) (((x) >> S_PH1) & M_PH1)
+
+#define S_PD1    0
+#define M_PD1    0xfffU
+#define V_PD1(x) ((x) << S_PD1)
+#define G_PD1(x) (((x) >> S_PD1) & M_PD1)
+
+#define A_PCIE_VC1_CDTS1 0x56d8
+
+#define S_CPLH1    20
+#define M_CPLH1    0xffU
+#define V_CPLH1(x) ((x) << S_CPLH1)
+#define G_CPLH1(x) (((x) >> S_CPLH1) & M_CPLH1)
+
+#define S_NPH1    12
+#define M_NPH1    0xffU
+#define V_NPH1(x) ((x) << S_NPH1)
+#define G_NPH1(x) (((x) >> S_NPH1) & M_NPH1)
+
+#define S_NPD1    0
+#define M_NPD1    0xfffU
+#define V_NPD1(x) ((x) << S_NPD1)
+#define G_NPD1(x) (((x) >> S_NPD1) & M_NPD1)
+
+#define A_PCIE_FLR_PF_STATUS 0x56dc
+#define A_PCIE_FLR_VF0_STATUS 0x56e0
+#define A_PCIE_FLR_VF1_STATUS 0x56e4
+#define A_PCIE_FLR_VF2_STATUS 0x56e8
+#define A_PCIE_FLR_VF3_STATUS 0x56ec
+#define A_PCIE_STAT 0x56f4
+
+#define S_PM_STATUS    24
+#define M_PM_STATUS    0xffU
+#define V_PM_STATUS(x) ((x) << S_PM_STATUS)
+#define G_PM_STATUS(x) (((x) >> S_PM_STATUS) & M_PM_STATUS)
+
+#define S_PM_CURRENTSTATE    20
+#define M_PM_CURRENTSTATE    0x7U
+#define V_PM_CURRENTSTATE(x) ((x) << S_PM_CURRENTSTATE)
+#define G_PM_CURRENTSTATE(x) (((x) >> S_PM_CURRENTSTATE) & M_PM_CURRENTSTATE)
+
+#define S_LTSSMENABLE    12
+#define V_LTSSMENABLE(x) ((x) << S_LTSSMENABLE)
+#define F_LTSSMENABLE    V_LTSSMENABLE(1U)
+
+#define S_STATECFGINITF    4
+#define M_STATECFGINITF    0x7fU
+#define V_STATECFGINITF(x) ((x) << S_STATECFGINITF)
+#define G_STATECFGINITF(x) (((x) >> S_STATECFGINITF) & M_STATECFGINITF)
+
+#define S_STATECFGINIT    0
+#define M_STATECFGINIT    0xfU
+#define V_STATECFGINIT(x) ((x) << S_STATECFGINIT)
+#define G_STATECFGINIT(x) (((x) >> S_STATECFGINIT) & M_STATECFGINIT)
+
+#define A_PCIE_CRS 0x56f8
+
+#define S_CRS_ENABLE    0
+#define V_CRS_ENABLE(x) ((x) << S_CRS_ENABLE)
+#define F_CRS_ENABLE    V_CRS_ENABLE(1U)
+
+#define A_PCIE_LTSSM 0x56fc
+
+#define S_LTSSM_ENABLE    0
+#define V_LTSSM_ENABLE(x) ((x) << S_LTSSM_ENABLE)
+#define F_LTSSM_ENABLE    V_LTSSM_ENABLE(1U)
+
+#define A_PCIE_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER 0x5700
+
+#define S_REPLAY_TIME_LIMIT    16
+#define M_REPLAY_TIME_LIMIT    0xffffU
+#define V_REPLAY_TIME_LIMIT(x) ((x) << S_REPLAY_TIME_LIMIT)
+#define G_REPLAY_TIME_LIMIT(x) (((x) >> S_REPLAY_TIME_LIMIT) & M_REPLAY_TIME_LIMIT)
+
+#define S_ACK_LATENCY_TIMER_LIMIT    0
+#define M_ACK_LATENCY_TIMER_LIMIT    0xffffU
+#define V_ACK_LATENCY_TIMER_LIMIT(x) ((x) << S_ACK_LATENCY_TIMER_LIMIT)
+#define G_ACK_LATENCY_TIMER_LIMIT(x) (((x) >> S_ACK_LATENCY_TIMER_LIMIT) & M_ACK_LATENCY_TIMER_LIMIT)
+
+#define A_PCIE_CORE_VENDOR_SPECIFIC_DLLP 0x5704
+#define A_PCIE_CORE_PORT_FORCE_LINK 0x5708
+
+#define S_LOW_POWER_ENTRANCE_COUNT    24
+#define M_LOW_POWER_ENTRANCE_COUNT    0xffU
+#define V_LOW_POWER_ENTRANCE_COUNT(x) ((x) << S_LOW_POWER_ENTRANCE_COUNT)
+#define G_LOW_POWER_ENTRANCE_COUNT(x) (((x) >> S_LOW_POWER_ENTRANCE_COUNT) & M_LOW_POWER_ENTRANCE_COUNT)
+
+#define S_LINK_STATE    16
+#define M_LINK_STATE    0x3fU
+#define V_LINK_STATE(x) ((x) << S_LINK_STATE)
+#define G_LINK_STATE(x) (((x) >> S_LINK_STATE) & M_LINK_STATE)
+
+#define S_FORCE_LINK    15
+#define V_FORCE_LINK(x) ((x) << S_FORCE_LINK)
+#define F_FORCE_LINK    V_FORCE_LINK(1U)
+
+#define S_LINK_NUMBER    0
+#define M_LINK_NUMBER    0xffU
+#define V_LINK_NUMBER(x) ((x) << S_LINK_NUMBER)
+#define G_LINK_NUMBER(x) (((x) >> S_LINK_NUMBER) & M_LINK_NUMBER)
+
+#define A_PCIE_CORE_ACK_FREQUENCY_L0L1_ASPM_CONTROL 0x570c
+
+#define S_ENTER_ASPM_L1_WO_L0S    30
+#define V_ENTER_ASPM_L1_WO_L0S(x) ((x) << S_ENTER_ASPM_L1_WO_L0S)
+#define F_ENTER_ASPM_L1_WO_L0S    V_ENTER_ASPM_L1_WO_L0S(1U)
+
+#define S_L1_ENTRANCE_LATENCY    27
+#define M_L1_ENTRANCE_LATENCY    0x7U
+#define V_L1_ENTRANCE_LATENCY(x) ((x) << S_L1_ENTRANCE_LATENCY)
+#define G_L1_ENTRANCE_LATENCY(x) (((x) >> S_L1_ENTRANCE_LATENCY) & M_L1_ENTRANCE_LATENCY)
+
+#define S_L0S_ENTRANCE_LATENCY    24
+#define M_L0S_ENTRANCE_LATENCY    0x7U
+#define V_L0S_ENTRANCE_LATENCY(x) ((x) << S_L0S_ENTRANCE_LATENCY)
+#define G_L0S_ENTRANCE_LATENCY(x) (((x) >> S_L0S_ENTRANCE_LATENCY) & M_L0S_ENTRANCE_LATENCY)
+
+#define S_COMMON_CLOCK_N_FTS    16
+#define M_COMMON_CLOCK_N_FTS    0xffU
+#define V_COMMON_CLOCK_N_FTS(x) ((x) << S_COMMON_CLOCK_N_FTS)
+#define G_COMMON_CLOCK_N_FTS(x) (((x) >> S_COMMON_CLOCK_N_FTS) & M_COMMON_CLOCK_N_FTS)
+
+#define S_N_FTS    8
+#define M_N_FTS    0xffU
+#define V_N_FTS(x) ((x) << S_N_FTS)
+#define G_N_FTS(x) (((x) >> S_N_FTS) & M_N_FTS)
+
+#define S_ACK_FREQUENCY    0
+#define M_ACK_FREQUENCY    0xffU
+#define V_ACK_FREQUENCY(x) ((x) << S_ACK_FREQUENCY)
+#define G_ACK_FREQUENCY(x) (((x) >> S_ACK_FREQUENCY) & M_ACK_FREQUENCY)
+
+#define A_PCIE_CORE_PORT_LINK_CONTROL 0x5710
+
+#define S_CROSSLINK_ACTIVE    23
+#define V_CROSSLINK_ACTIVE(x) ((x) << S_CROSSLINK_ACTIVE)
+#define F_CROSSLINK_ACTIVE    V_CROSSLINK_ACTIVE(1U)
+
+#define S_CROSSLINK_ENABLE    22
+#define V_CROSSLINK_ENABLE(x) ((x) << S_CROSSLINK_ENABLE)
+#define F_CROSSLINK_ENABLE    V_CROSSLINK_ENABLE(1U)
+
+#define S_LINK_MODE_ENABLE    16
+#define M_LINK_MODE_ENABLE    0x3fU
+#define V_LINK_MODE_ENABLE(x) ((x) << S_LINK_MODE_ENABLE)
+#define G_LINK_MODE_ENABLE(x) (((x) >> S_LINK_MODE_ENABLE) & M_LINK_MODE_ENABLE)
+
+#define S_FAST_LINK_MODE    7
+#define V_FAST_LINK_MODE(x) ((x) << S_FAST_LINK_MODE)
+#define F_FAST_LINK_MODE    V_FAST_LINK_MODE(1U)
+
+#define S_DLL_LINK_ENABLE    5
+#define V_DLL_LINK_ENABLE(x) ((x) << S_DLL_LINK_ENABLE)
+#define F_DLL_LINK_ENABLE    V_DLL_LINK_ENABLE(1U)
+
+#define S_RESET_ASSERT    3
+#define V_RESET_ASSERT(x) ((x) << S_RESET_ASSERT)
+#define F_RESET_ASSERT    V_RESET_ASSERT(1U)
+
+#define S_LOOPBACK_ENABLE    2
+#define V_LOOPBACK_ENABLE(x) ((x) << S_LOOPBACK_ENABLE)
+#define F_LOOPBACK_ENABLE    V_LOOPBACK_ENABLE(1U)
+
+#define S_SCRAMBLE_DISABLE    1
+#define V_SCRAMBLE_DISABLE(x) ((x) << S_SCRAMBLE_DISABLE)
+#define F_SCRAMBLE_DISABLE    V_SCRAMBLE_DISABLE(1U)
+
+#define S_VENDOR_SPECIFIC_DLLP_REQUEST    0
+#define V_VENDOR_SPECIFIC_DLLP_REQUEST(x) ((x) << S_VENDOR_SPECIFIC_DLLP_REQUEST)
+#define F_VENDOR_SPECIFIC_DLLP_REQUEST    V_VENDOR_SPECIFIC_DLLP_REQUEST(1U)
+
+#define A_PCIE_CORE_LANE_SKEW 0x5714
+
+#define S_DISABLE_DESKEW    31
+#define V_DISABLE_DESKEW(x) ((x) << S_DISABLE_DESKEW)
+#define F_DISABLE_DESKEW    V_DISABLE_DESKEW(1U)
+
+#define S_ACK_NAK_DISABLE    25
+#define V_ACK_NAK_DISABLE(x) ((x) << S_ACK_NAK_DISABLE)
+#define F_ACK_NAK_DISABLE    V_ACK_NAK_DISABLE(1U)
+
+#define S_FLOW_CONTROL_DISABLE    24
+#define V_FLOW_CONTROL_DISABLE(x) ((x) << S_FLOW_CONTROL_DISABLE)
+#define F_FLOW_CONTROL_DISABLE    V_FLOW_CONTROL_DISABLE(1U)
+
+#define S_INSERT_TXSKEW    0
+#define M_INSERT_TXSKEW    0xffffffU
+#define V_INSERT_TXSKEW(x) ((x) << S_INSERT_TXSKEW)
+#define G_INSERT_TXSKEW(x) (((x) >> S_INSERT_TXSKEW) & M_INSERT_TXSKEW)
+
+#define A_PCIE_CORE_SYMBOL_NUMBER 0x5718
+
+#define S_FLOW_CONTROL_TIMER_MODIFIER    24
+#define M_FLOW_CONTROL_TIMER_MODIFIER    0x1fU
+#define V_FLOW_CONTROL_TIMER_MODIFIER(x) ((x) << S_FLOW_CONTROL_TIMER_MODIFIER)
+#define G_FLOW_CONTROL_TIMER_MODIFIER(x) (((x) >> S_FLOW_CONTROL_TIMER_MODIFIER) & M_FLOW_CONTROL_TIMER_MODIFIER)
+
+#define S_ACK_NAK_TIMER_MODIFIER    19
+#define M_ACK_NAK_TIMER_MODIFIER    0x1fU
+#define V_ACK_NAK_TIMER_MODIFIER(x) ((x) << S_ACK_NAK_TIMER_MODIFIER)
+#define G_ACK_NAK_TIMER_MODIFIER(x) (((x) >> S_ACK_NAK_TIMER_MODIFIER) & M_ACK_NAK_TIMER_MODIFIER)
+
+#define S_REPLAY_TIMER_MODIFIER    14
+#define M_REPLAY_TIMER_MODIFIER    0x1fU
+#define V_REPLAY_TIMER_MODIFIER(x) ((x) << S_REPLAY_TIMER_MODIFIER)
+#define G_REPLAY_TIMER_MODIFIER(x) (((x) >> S_REPLAY_TIMER_MODIFIER) & M_REPLAY_TIMER_MODIFIER)
+
+#define S_MAXFUNC    0
+#define M_MAXFUNC    0x7U
+#define V_MAXFUNC(x) ((x) << S_MAXFUNC)
+#define G_MAXFUNC(x) (((x) >> S_MAXFUNC) & M_MAXFUNC)
+
+#define A_PCIE_CORE_SYMBOL_TIMER_FILTER_MASK1 0x571c
+
+#define S_MASK_RADM_FILTER    16
+#define M_MASK_RADM_FILTER    0xffffU
+#define V_MASK_RADM_FILTER(x) ((x) << S_MASK_RADM_FILTER)
+#define G_MASK_RADM_FILTER(x) (((x) >> S_MASK_RADM_FILTER) & M_MASK_RADM_FILTER)
+
+#define S_DISABLE_FC_WATCHDOG    15
+#define V_DISABLE_FC_WATCHDOG(x) ((x) << S_DISABLE_FC_WATCHDOG)
+#define F_DISABLE_FC_WATCHDOG    V_DISABLE_FC_WATCHDOG(1U)
+
+#define S_SKP_INTERVAL    0
+#define M_SKP_INTERVAL    0x7ffU
+#define V_SKP_INTERVAL(x) ((x) << S_SKP_INTERVAL)
+#define G_SKP_INTERVAL(x) (((x) >> S_SKP_INTERVAL) & M_SKP_INTERVAL)
+
+#define A_PCIE_CORE_FILTER_MASK2 0x5720
+#define A_PCIE_CORE_DEBUG_0 0x5728
+#define A_PCIE_CORE_DEBUG_1 0x572c
+#define A_PCIE_CORE_TRANSMIT_POSTED_FC_CREDIT_STATUS 0x5730
+
+#define S_TXPH_FC    12
+#define M_TXPH_FC    0xffU
+#define V_TXPH_FC(x) ((x) << S_TXPH_FC)
+#define G_TXPH_FC(x) (((x) >> S_TXPH_FC) & M_TXPH_FC)
+
+#define S_TXPD_FC    0
+#define M_TXPD_FC    0xfffU
+#define V_TXPD_FC(x) ((x) << S_TXPD_FC)
+#define G_TXPD_FC(x) (((x) >> S_TXPD_FC) & M_TXPD_FC)
+
+#define A_PCIE_CORE_TRANSMIT_NONPOSTED_FC_CREDIT_STATUS 0x5734
+
+#define S_TXNPH_FC    12
+#define M_TXNPH_FC    0xffU
+#define V_TXNPH_FC(x) ((x) << S_TXNPH_FC)
+#define G_TXNPH_FC(x) (((x) >> S_TXNPH_FC) & M_TXNPH_FC)
+
+#define S_TXNPD_FC    0
+#define M_TXNPD_FC    0xfffU
+#define V_TXNPD_FC(x) ((x) << S_TXNPD_FC)
+#define G_TXNPD_FC(x) (((x) >> S_TXNPD_FC) & M_TXNPD_FC)
+
+#define A_PCIE_CORE_TRANSMIT_COMPLETION_FC_CREDIT_STATUS 0x5738
+
+#define S_TXCPLH_FC    12
+#define M_TXCPLH_FC    0xffU
+#define V_TXCPLH_FC(x) ((x) << S_TXCPLH_FC)
+#define G_TXCPLH_FC(x) (((x) >> S_TXCPLH_FC) & M_TXCPLH_FC)
+
+#define S_TXCPLD_FC    0
+#define M_TXCPLD_FC    0xfffU
+#define V_TXCPLD_FC(x) ((x) << S_TXCPLD_FC)
+#define G_TXCPLD_FC(x) (((x) >> S_TXCPLD_FC) & M_TXCPLD_FC)
+
+#define A_PCIE_CORE_QUEUE_STATUS 0x573c
+
+#define S_RXQUEUE_NOT_EMPTY    2
+#define V_RXQUEUE_NOT_EMPTY(x) ((x) << S_RXQUEUE_NOT_EMPTY)
+#define F_RXQUEUE_NOT_EMPTY    V_RXQUEUE_NOT_EMPTY(1U)
+
+#define S_TXRETRYBUF_NOT_EMPTY    1
+#define V_TXRETRYBUF_NOT_EMPTY(x) ((x) << S_TXRETRYBUF_NOT_EMPTY)
+#define F_TXRETRYBUF_NOT_EMPTY    V_TXRETRYBUF_NOT_EMPTY(1U)
+
+#define S_RXTLP_FC_NOT_RETURNED    0
+#define V_RXTLP_FC_NOT_RETURNED(x) ((x) << S_RXTLP_FC_NOT_RETURNED)
+#define F_RXTLP_FC_NOT_RETURNED    V_RXTLP_FC_NOT_RETURNED(1U)
+
+#define A_PCIE_CORE_VC_TRANSMIT_ARBITRATION_1 0x5740
+
+#define S_VC3_WRR    24
+#define M_VC3_WRR    0xffU
+#define V_VC3_WRR(x) ((x) << S_VC3_WRR)
+#define G_VC3_WRR(x) (((x) >> S_VC3_WRR) & M_VC3_WRR)
+
+#define S_VC2_WRR    16
+#define M_VC2_WRR    0xffU
+#define V_VC2_WRR(x) ((x) << S_VC2_WRR)
+#define G_VC2_WRR(x) (((x) >> S_VC2_WRR) & M_VC2_WRR)
+
+#define S_VC1_WRR    8
+#define M_VC1_WRR    0xffU
+#define V_VC1_WRR(x) ((x) << S_VC1_WRR)
+#define G_VC1_WRR(x) (((x) >> S_VC1_WRR) & M_VC1_WRR)
+
+#define S_VC0_WRR    0
+#define M_VC0_WRR    0xffU
+#define V_VC0_WRR(x) ((x) << S_VC0_WRR)
+#define G_VC0_WRR(x) (((x) >> S_VC0_WRR) & M_VC0_WRR)
+
+#define A_PCIE_CORE_VC_TRANSMIT_ARBITRATION_2 0x5744
+
+#define S_VC7_WRR    24
+#define M_VC7_WRR    0xffU
+#define V_VC7_WRR(x) ((x) << S_VC7_WRR)
+#define G_VC7_WRR(x) (((x) >> S_VC7_WRR) & M_VC7_WRR)
+
+#define S_VC6_WRR    16
+#define M_VC6_WRR    0xffU
+#define V_VC6_WRR(x) ((x) << S_VC6_WRR)
+#define G_VC6_WRR(x) (((x) >> S_VC6_WRR) & M_VC6_WRR)
+
+#define S_VC5_WRR    8
+#define M_VC5_WRR    0xffU
+#define V_VC5_WRR(x) ((x) << S_VC5_WRR)
+#define G_VC5_WRR(x) (((x) >> S_VC5_WRR) & M_VC5_WRR)
+
+#define S_VC4_WRR    0
+#define M_VC4_WRR    0xffU
+#define V_VC4_WRR(x) ((x) << S_VC4_WRR)
+#define G_VC4_WRR(x) (((x) >> S_VC4_WRR) & M_VC4_WRR)
+
+#define A_PCIE_CORE_VC0_POSTED_RECEIVE_QUEUE_CONTROL 0x5748
+
+#define S_VC0_RX_ORDERING    31
+#define V_VC0_RX_ORDERING(x) ((x) << S_VC0_RX_ORDERING)
+#define F_VC0_RX_ORDERING    V_VC0_RX_ORDERING(1U)
+
+#define S_VC0_TLP_ORDERING    30
+#define V_VC0_TLP_ORDERING(x) ((x) << S_VC0_TLP_ORDERING)
+#define F_VC0_TLP_ORDERING    V_VC0_TLP_ORDERING(1U)
+
+#define S_VC0_PTLP_QUEUE_MODE    21
+#define M_VC0_PTLP_QUEUE_MODE    0x7U
+#define V_VC0_PTLP_QUEUE_MODE(x) ((x) << S_VC0_PTLP_QUEUE_MODE)
+#define G_VC0_PTLP_QUEUE_MODE(x) (((x) >> S_VC0_PTLP_QUEUE_MODE) & M_VC0_PTLP_QUEUE_MODE)
+
+#define S_VC0_PH_CREDITS    12
+#define M_VC0_PH_CREDITS    0xffU
+#define V_VC0_PH_CREDITS(x) ((x) << S_VC0_PH_CREDITS)
+#define G_VC0_PH_CREDITS(x) (((x) >> S_VC0_PH_CREDITS) & M_VC0_PH_CREDITS)
+
+#define S_VC0_PD_CREDITS    0
+#define M_VC0_PD_CREDITS    0xfffU
+#define V_VC0_PD_CREDITS(x) ((x) << S_VC0_PD_CREDITS)
+#define G_VC0_PD_CREDITS(x) (((x) >> S_VC0_PD_CREDITS) & M_VC0_PD_CREDITS)
+
+#define A_PCIE_CORE_VC0_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x574c
+
+#define S_VC0_NPTLP_QUEUE_MODE    21
+#define M_VC0_NPTLP_QUEUE_MODE    0x7U
+#define V_VC0_NPTLP_QUEUE_MODE(x) ((x) << S_VC0_NPTLP_QUEUE_MODE)
+#define G_VC0_NPTLP_QUEUE_MODE(x) (((x) >> S_VC0_NPTLP_QUEUE_MODE) & M_VC0_NPTLP_QUEUE_MODE)
+
+#define S_VC0_NPH_CREDITS    12
+#define M_VC0_NPH_CREDITS    0xffU
+#define V_VC0_NPH_CREDITS(x) ((x) << S_VC0_NPH_CREDITS)
+#define G_VC0_NPH_CREDITS(x) (((x) >> S_VC0_NPH_CREDITS) & M_VC0_NPH_CREDITS)
+
+#define S_VC0_NPD_CREDITS    0
+#define M_VC0_NPD_CREDITS    0xfffU
+#define V_VC0_NPD_CREDITS(x) ((x) << S_VC0_NPD_CREDITS)
+#define G_VC0_NPD_CREDITS(x) (((x) >> S_VC0_NPD_CREDITS) & M_VC0_NPD_CREDITS)
+
+#define A_PCIE_CORE_VC0_COMPLETION_RECEIVE_QUEUE_CONTROL 0x5750
+
+#define S_VC0_CPLTLP_QUEUE_MODE    21
+#define M_VC0_CPLTLP_QUEUE_MODE    0x7U
+#define V_VC0_CPLTLP_QUEUE_MODE(x) ((x) << S_VC0_CPLTLP_QUEUE_MODE)
+#define G_VC0_CPLTLP_QUEUE_MODE(x) (((x) >> S_VC0_CPLTLP_QUEUE_MODE) & M_VC0_CPLTLP_QUEUE_MODE)
+
+#define S_VC0_CPLH_CREDITS    12
+#define M_VC0_CPLH_CREDITS    0xffU
+#define V_VC0_CPLH_CREDITS(x) ((x) << S_VC0_CPLH_CREDITS)
+#define G_VC0_CPLH_CREDITS(x) (((x) >> S_VC0_CPLH_CREDITS) & M_VC0_CPLH_CREDITS)
+
+#define S_VC0_CPLD_CREDITS    0
+#define M_VC0_CPLD_CREDITS    0xfffU
+#define V_VC0_CPLD_CREDITS(x) ((x) << S_VC0_CPLD_CREDITS)
+#define G_VC0_CPLD_CREDITS(x) (((x) >> S_VC0_CPLD_CREDITS) & M_VC0_CPLD_CREDITS)
+
+#define A_PCIE_CORE_VC1_POSTED_RECEIVE_QUEUE_CONTROL 0x5754
+
+#define S_VC1_TLP_ORDERING    30
+#define V_VC1_TLP_ORDERING(x) ((x) << S_VC1_TLP_ORDERING)
+#define F_VC1_TLP_ORDERING    V_VC1_TLP_ORDERING(1U)
+
+#define S_VC1_PTLP_QUEUE_MODE    21
+#define M_VC1_PTLP_QUEUE_MODE    0x7U
+#define V_VC1_PTLP_QUEUE_MODE(x) ((x) << S_VC1_PTLP_QUEUE_MODE)
+#define G_VC1_PTLP_QUEUE_MODE(x) (((x) >> S_VC1_PTLP_QUEUE_MODE) & M_VC1_PTLP_QUEUE_MODE)
+
+#define S_VC1_PH_CREDITS    12
+#define M_VC1_PH_CREDITS    0xffU
+#define V_VC1_PH_CREDITS(x) ((x) << S_VC1_PH_CREDITS)
+#define G_VC1_PH_CREDITS(x) (((x) >> S_VC1_PH_CREDITS) & M_VC1_PH_CREDITS)
+
+#define S_VC1_PD_CREDITS    0
+#define M_VC1_PD_CREDITS    0xfffU
+#define V_VC1_PD_CREDITS(x) ((x) << S_VC1_PD_CREDITS)
+#define G_VC1_PD_CREDITS(x) (((x) >> S_VC1_PD_CREDITS) & M_VC1_PD_CREDITS)
+
+#define A_PCIE_CORE_VC1_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x5758
+
+#define S_VC1_NPTLP_QUEUE_MODE    21
+#define M_VC1_NPTLP_QUEUE_MODE    0x7U
+#define V_VC1_NPTLP_QUEUE_MODE(x) ((x) << S_VC1_NPTLP_QUEUE_MODE)
+#define G_VC1_NPTLP_QUEUE_MODE(x) (((x) >> S_VC1_NPTLP_QUEUE_MODE) & M_VC1_NPTLP_QUEUE_MODE)
+
+#define S_VC1_NPH_CREDITS    12
+#define M_VC1_NPH_CREDITS    0xffU
+#define V_VC1_NPH_CREDITS(x) ((x) << S_VC1_NPH_CREDITS)
+#define G_VC1_NPH_CREDITS(x) (((x) >> S_VC1_NPH_CREDITS) & M_VC1_NPH_CREDITS)
+
+#define S_VC1_NPD_CREDITS    0
+#define M_VC1_NPD_CREDITS    0xfffU
+#define V_VC1_NPD_CREDITS(x) ((x) << S_VC1_NPD_CREDITS)
+#define G_VC1_NPD_CREDITS(x) (((x) >> S_VC1_NPD_CREDITS) & M_VC1_NPD_CREDITS)
+
+#define A_PCIE_CORE_VC1_COMPLETION_RECEIVE_QUEUE_CONTROL 0x575c
+
+#define S_VC1_CPLTLP_QUEUE_MODE    21
+#define M_VC1_CPLTLP_QUEUE_MODE    0x7U
+#define V_VC1_CPLTLP_QUEUE_MODE(x) ((x) << S_VC1_CPLTLP_QUEUE_MODE)
+#define G_VC1_CPLTLP_QUEUE_MODE(x) (((x) >> S_VC1_CPLTLP_QUEUE_MODE) & M_VC1_CPLTLP_QUEUE_MODE)
+
+#define S_VC1_CPLH_CREDITS    12
+#define M_VC1_CPLH_CREDITS    0xffU
+#define V_VC1_CPLH_CREDITS(x) ((x) << S_VC1_CPLH_CREDITS)
+#define G_VC1_CPLH_CREDITS(x) (((x) >> S_VC1_CPLH_CREDITS) & M_VC1_CPLH_CREDITS)
+
+#define S_VC1_CPLD_CREDITS    0
+#define M_VC1_CPLD_CREDITS    0xfffU
+#define V_VC1_CPLD_CREDITS(x) ((x) << S_VC1_CPLD_CREDITS)
+#define G_VC1_CPLD_CREDITS(x) (((x) >> S_VC1_CPLD_CREDITS) & M_VC1_CPLD_CREDITS)
+
+#define A_PCIE_CORE_LINK_WIDTH_SPEED_CHANGE 0x580c
+
+#define S_SEL_DEEMPHASIS    20
+#define V_SEL_DEEMPHASIS(x) ((x) << S_SEL_DEEMPHASIS)
+#define F_SEL_DEEMPHASIS    V_SEL_DEEMPHASIS(1U)
+
+#define S_TXCMPLRCV    19
+#define V_TXCMPLRCV(x) ((x) << S_TXCMPLRCV)
+#define F_TXCMPLRCV    V_TXCMPLRCV(1U)
+
+#define S_PHYTXSWING    18
+#define V_PHYTXSWING(x) ((x) << S_PHYTXSWING)
+#define F_PHYTXSWING    V_PHYTXSWING(1U)
+
+#define S_DIRSPDCHANGE    17
+#define V_DIRSPDCHANGE(x) ((x) << S_DIRSPDCHANGE)
+#define F_DIRSPDCHANGE    V_DIRSPDCHANGE(1U)
+
+#define S_NUM_LANES    8
+#define M_NUM_LANES    0x1ffU
+#define V_NUM_LANES(x) ((x) << S_NUM_LANES)
+#define G_NUM_LANES(x) (((x) >> S_NUM_LANES) & M_NUM_LANES)
+
+#define S_NFTS_GEN2_3    0
+#define M_NFTS_GEN2_3    0xffU
+#define V_NFTS_GEN2_3(x) ((x) << S_NFTS_GEN2_3)
+#define G_NFTS_GEN2_3(x) (((x) >> S_NFTS_GEN2_3) & M_NFTS_GEN2_3)
+
+#define A_PCIE_CORE_PHY_STATUS 0x5810
+#define A_PCIE_CORE_PHY_CONTROL 0x5814
+#define A_PCIE_CORE_GEN3_CONTROL 0x5890
+
+#define S_DC_BALANCE_DISABLE    18
+#define V_DC_BALANCE_DISABLE(x) ((x) << S_DC_BALANCE_DISABLE)
+#define F_DC_BALANCE_DISABLE    V_DC_BALANCE_DISABLE(1U)
+
+#define S_DLLP_DELAY_DISABLE    17
+#define V_DLLP_DELAY_DISABLE(x) ((x) << S_DLLP_DELAY_DISABLE)
+#define F_DLLP_DELAY_DISABLE    V_DLLP_DELAY_DISABLE(1U)
+
+#define S_EQL_DISABLE    16
+#define V_EQL_DISABLE(x) ((x) << S_EQL_DISABLE)
+#define F_EQL_DISABLE    V_EQL_DISABLE(1U)
+
+#define S_EQL_REDO_DISABLE    11
+#define V_EQL_REDO_DISABLE(x) ((x) << S_EQL_REDO_DISABLE)
+#define F_EQL_REDO_DISABLE    V_EQL_REDO_DISABLE(1U)
+
+#define S_EQL_EIEOS_CNTRST_DISABLE    10
+#define V_EQL_EIEOS_CNTRST_DISABLE(x) ((x) << S_EQL_EIEOS_CNTRST_DISABLE)
+#define F_EQL_EIEOS_CNTRST_DISABLE    V_EQL_EIEOS_CNTRST_DISABLE(1U)
+
+#define S_EQL_PH2_PH3_DISABLE    9
+#define V_EQL_PH2_PH3_DISABLE(x) ((x) << S_EQL_PH2_PH3_DISABLE)
+#define F_EQL_PH2_PH3_DISABLE    V_EQL_PH2_PH3_DISABLE(1U)
+
+#define S_DISABLE_SCRAMBLER    8
+#define V_DISABLE_SCRAMBLER(x) ((x) << S_DISABLE_SCRAMBLER)
+#define F_DISABLE_SCRAMBLER    V_DISABLE_SCRAMBLER(1U)
+
+#define A_PCIE_CORE_GEN3_EQ_FS_LF 0x5894
+
+#define S_FULL_SWING    6
+#define M_FULL_SWING    0x3fU
+#define V_FULL_SWING(x) ((x) << S_FULL_SWING)
+#define G_FULL_SWING(x) (((x) >> S_FULL_SWING) & M_FULL_SWING)
+
+#define S_LOW_FREQUENCY    0
+#define M_LOW_FREQUENCY    0x3fU
+#define V_LOW_FREQUENCY(x) ((x) << S_LOW_FREQUENCY)
+#define G_LOW_FREQUENCY(x) (((x) >> S_LOW_FREQUENCY) & M_LOW_FREQUENCY)
+
+#define A_PCIE_CORE_GEN3_EQ_PRESET_COEFF 0x5898
+
+#define S_POSTCURSOR    12
+#define M_POSTCURSOR    0x3fU
+#define V_POSTCURSOR(x) ((x) << S_POSTCURSOR)
+#define G_POSTCURSOR(x) (((x) >> S_POSTCURSOR) & M_POSTCURSOR)
+
+#define S_CURSOR    6
+#define M_CURSOR    0x3fU
+#define V_CURSOR(x) ((x) << S_CURSOR)
+#define G_CURSOR(x) (((x) >> S_CURSOR) & M_CURSOR)
+
+#define S_PRECURSOR    0
+#define M_PRECURSOR    0x3fU
+#define V_PRECURSOR(x) ((x) << S_PRECURSOR)
+#define G_PRECURSOR(x) (((x) >> S_PRECURSOR) & M_PRECURSOR)
+
+#define A_PCIE_CORE_GEN3_EQ_PRESET_INDEX 0x589c
+
+#define S_INDEX    0
+#define M_INDEX    0xfU
+#define V_INDEX(x) ((x) << S_INDEX)
+#define G_INDEX(x) (((x) >> S_INDEX) & M_INDEX)
+
+#define A_PCIE_CORE_GEN3_EQ_STATUS 0x58a4
+
+#define S_LEGALITY_STATUS    0
+#define V_LEGALITY_STATUS(x) ((x) << S_LEGALITY_STATUS)
+#define F_LEGALITY_STATUS    V_LEGALITY_STATUS(1U)
+
+#define A_PCIE_CORE_GEN3_EQ_CONTROL 0x58a8
+
+#define S_INCLUDE_INITIAL_FOM    24
+#define V_INCLUDE_INITIAL_FOM(x) ((x) << S_INCLUDE_INITIAL_FOM)
+#define F_INCLUDE_INITIAL_FOM    V_INCLUDE_INITIAL_FOM(1U)
+
+#define S_PRESET_REQUEST_VECTOR    8
+#define M_PRESET_REQUEST_VECTOR    0xffffU
+#define V_PRESET_REQUEST_VECTOR(x) ((x) << S_PRESET_REQUEST_VECTOR)
+#define G_PRESET_REQUEST_VECTOR(x) (((x) >> S_PRESET_REQUEST_VECTOR) & M_PRESET_REQUEST_VECTOR)
+
+#define S_PHASE23_2MS_TIMEOUT_DISABLE    5
+#define V_PHASE23_2MS_TIMEOUT_DISABLE(x) ((x) << S_PHASE23_2MS_TIMEOUT_DISABLE)
+#define F_PHASE23_2MS_TIMEOUT_DISABLE    V_PHASE23_2MS_TIMEOUT_DISABLE(1U)
+
+#define S_AFTER24MS    4
+#define V_AFTER24MS(x) ((x) << S_AFTER24MS)
+#define F_AFTER24MS    V_AFTER24MS(1U)
+
+#define S_FEEDBACK_MODE    0
+#define M_FEEDBACK_MODE    0xfU
+#define V_FEEDBACK_MODE(x) ((x) << S_FEEDBACK_MODE)
+#define G_FEEDBACK_MODE(x) (((x) >> S_FEEDBACK_MODE) & M_FEEDBACK_MODE)
+
+#define A_PCIE_CORE_GEN3_EQ_DIRCHANGE_FEEDBACK 0x58ac
+
+#define S_WINAPERTURE_CPLUS1    14
+#define M_WINAPERTURE_CPLUS1    0xfU
+#define V_WINAPERTURE_CPLUS1(x) ((x) << S_WINAPERTURE_CPLUS1)
+#define G_WINAPERTURE_CPLUS1(x) (((x) >> S_WINAPERTURE_CPLUS1) & M_WINAPERTURE_CPLUS1)
+
+#define S_WINAPERTURE_CMINS1    10
+#define M_WINAPERTURE_CMINS1    0xfU
+#define V_WINAPERTURE_CMINS1(x) ((x) << S_WINAPERTURE_CMINS1)
+#define G_WINAPERTURE_CMINS1(x) (((x) >> S_WINAPERTURE_CMINS1) & M_WINAPERTURE_CMINS1)
+
+#define S_CONVERGENCE_WINDEPTH    5
+#define M_CONVERGENCE_WINDEPTH    0x1fU
+#define V_CONVERGENCE_WINDEPTH(x) ((x) << S_CONVERGENCE_WINDEPTH)
+#define G_CONVERGENCE_WINDEPTH(x) (((x) >> S_CONVERGENCE_WINDEPTH) & M_CONVERGENCE_WINDEPTH)
+
+#define S_EQMASTERPHASE_MINTIME    0
+#define M_EQMASTERPHASE_MINTIME    0x1fU
+#define V_EQMASTERPHASE_MINTIME(x) ((x) << S_EQMASTERPHASE_MINTIME)
+#define G_EQMASTERPHASE_MINTIME(x) (((x) >> S_EQMASTERPHASE_MINTIME) & M_EQMASTERPHASE_MINTIME)
+
+#define A_PCIE_CORE_PIPE_CONTROL 0x58b8
+
+#define S_PIPE_LOOPBACK_EN    0
+#define V_PIPE_LOOPBACK_EN(x) ((x) << S_PIPE_LOOPBACK_EN)
+#define F_PIPE_LOOPBACK_EN    V_PIPE_LOOPBACK_EN(1U)
+
+#define A_PCIE_CORE_DBI_RO_WE 0x58bc
+
+#define S_READONLY_WRITEEN    0
+#define V_READONLY_WRITEEN(x) ((x) << S_READONLY_WRITEEN)
+#define F_READONLY_WRITEEN    V_READONLY_WRITEEN(1U)
+
+#define A_PCIE_CORE_UTL_SYSTEM_BUS_CONTROL 0x5900
+
+#define S_SMTD    27
+#define V_SMTD(x) ((x) << S_SMTD)
+#define F_SMTD    V_SMTD(1U)
+
+#define S_SSTD    26
+#define V_SSTD(x) ((x) << S_SSTD)
+#define F_SSTD    V_SSTD(1U)
+
+#define S_SWD0    23
+#define V_SWD0(x) ((x) << S_SWD0)
+#define F_SWD0    V_SWD0(1U)
+
+#define S_SWD1    22
+#define V_SWD1(x) ((x) << S_SWD1)
+#define F_SWD1    V_SWD1(1U)
+
+#define S_SWD2    21
+#define V_SWD2(x) ((x) << S_SWD2)
+#define F_SWD2    V_SWD2(1U)
+
+#define S_SWD3    20
+#define V_SWD3(x) ((x) << S_SWD3)
+#define F_SWD3    V_SWD3(1U)
+
+#define S_SWD4    19
+#define V_SWD4(x) ((x) << S_SWD4)
+#define F_SWD4    V_SWD4(1U)
+
+#define S_SWD5    18
+#define V_SWD5(x) ((x) << S_SWD5)
+#define F_SWD5    V_SWD5(1U)
+
+#define S_SWD6    17
+#define V_SWD6(x) ((x) << S_SWD6)
+#define F_SWD6    V_SWD6(1U)
+
+#define S_SWD7    16
+#define V_SWD7(x) ((x) << S_SWD7)
+#define F_SWD7    V_SWD7(1U)
+
+#define S_SWD8    15
+#define V_SWD8(x) ((x) << S_SWD8)
+#define F_SWD8    V_SWD8(1U)
+
+#define S_SRD0    13
+#define V_SRD0(x) ((x) << S_SRD0)
+#define F_SRD0    V_SRD0(1U)
+
+#define S_SRD1    12
+#define V_SRD1(x) ((x) << S_SRD1)
+#define F_SRD1    V_SRD1(1U)
+
+#define S_SRD2    11
+#define V_SRD2(x) ((x) << S_SRD2)
+#define F_SRD2    V_SRD2(1U)
+
+#define S_SRD3    10
+#define V_SRD3(x) ((x) << S_SRD3)
+#define F_SRD3    V_SRD3(1U)
+
+#define S_SRD4    9
+#define V_SRD4(x) ((x) << S_SRD4)
+#define F_SRD4    V_SRD4(1U)
+
+#define S_SRD5    8
+#define V_SRD5(x) ((x) << S_SRD5)
+#define F_SRD5    V_SRD5(1U)
+
+#define S_SRD6    7
+#define V_SRD6(x) ((x) << S_SRD6)
+#define F_SRD6    V_SRD6(1U)
+
+#define S_SRD7    6
+#define V_SRD7(x) ((x) << S_SRD7)
+#define F_SRD7    V_SRD7(1U)
+
+#define S_SRD8    5
+#define V_SRD8(x) ((x) << S_SRD8)
+#define F_SRD8    V_SRD8(1U)
+
+#define S_CRRE    3
+#define V_CRRE(x) ((x) << S_CRRE)
+#define F_CRRE    V_CRRE(1U)
+
+#define S_CRMC    0
+#define M_CRMC    0x7U
+#define V_CRMC(x) ((x) << S_CRMC)
+#define G_CRMC(x) (((x) >> S_CRMC) & M_CRMC)
+
+#define A_PCIE_CORE_UTL_STATUS 0x5904
+
+#define S_USBP    31
+#define V_USBP(x) ((x) << S_USBP)
+#define F_USBP    V_USBP(1U)
+
+#define S_UPEP    30
+#define V_UPEP(x) ((x) << S_UPEP)
+#define F_UPEP    V_UPEP(1U)
+
+#define S_RCEP    29
+#define V_RCEP(x) ((x) << S_RCEP)
+#define F_RCEP    V_RCEP(1U)
+
+#define S_EPEP    28
+#define V_EPEP(x) ((x) << S_EPEP)
+#define F_EPEP    V_EPEP(1U)
+
+#define S_USBS    27
+#define V_USBS(x) ((x) << S_USBS)
+#define F_USBS    V_USBS(1U)
+
+#define S_UPES    26
+#define V_UPES(x) ((x) << S_UPES)
+#define F_UPES    V_UPES(1U)
+
+#define S_RCES    25
+#define V_RCES(x) ((x) << S_RCES)
+#define F_RCES    V_RCES(1U)
+
+#define S_EPES    24
+#define V_EPES(x) ((x) << S_EPES)
+#define F_EPES    V_EPES(1U)
+
+#define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908
+
+#define S_RNPP    31
+#define V_RNPP(x) ((x) << S_RNPP)
+#define F_RNPP    V_RNPP(1U)
+
+#define S_RPCP    29
+#define V_RPCP(x) ((x) << S_RPCP)
+#define F_RPCP    V_RPCP(1U)
+
+#define S_RCIP    27
+#define V_RCIP(x) ((x) << S_RCIP)
+#define F_RCIP    V_RCIP(1U)
+
+#define S_RCCP    26
+#define V_RCCP(x) ((x) << S_RCCP)
+#define F_RCCP    V_RCCP(1U)
+
+#define S_RFTP    23
+#define V_RFTP(x) ((x) << S_RFTP)
+#define F_RFTP    V_RFTP(1U)
+
+#define S_PTRP    20
+#define V_PTRP(x) ((x) << S_PTRP)
+#define F_PTRP    V_PTRP(1U)
+
+#define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_ERROR_SEVERITY 0x590c
+
+#define S_RNPS    31
+#define V_RNPS(x) ((x) << S_RNPS)
+#define F_RNPS    V_RNPS(1U)
+
+#define S_RPCS    29
+#define V_RPCS(x) ((x) << S_RPCS)
+#define F_RPCS    V_RPCS(1U)
+
+#define S_RCIS    27
+#define V_RCIS(x) ((x) << S_RCIS)
+#define F_RCIS    V_RCIS(1U)
+
+#define S_RCCS    26
+#define V_RCCS(x) ((x) << S_RCCS)
+#define F_RCCS    V_RCCS(1U)
+
+#define S_RFTS    23
+#define V_RFTS(x) ((x) << S_RFTS)
+#define F_RFTS    V_RFTS(1U)
+
+#define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE 0x5910
+
+#define S_RNPI    31
+#define V_RNPI(x) ((x) << S_RNPI)
+#define F_RNPI    V_RNPI(1U)
+
+#define S_RPCI    29
+#define V_RPCI(x) ((x) << S_RPCI)
+#define F_RPCI    V_RPCI(1U)
+
+#define S_RCII    27
+#define V_RCII(x) ((x) << S_RCII)
+#define F_RCII    V_RCII(1U)
+
+#define S_RCCI    26
+#define V_RCCI(x) ((x) << S_RCCI)
+#define F_RCCI    V_RCCI(1U)
+
+#define S_RFTI    23
+#define V_RFTI(x) ((x) << S_RFTI)
+#define F_RFTI    V_RFTI(1U)
+
+#define A_PCIE_CORE_SYSTEM_BUS_BURST_SIZE_CONFIGURATION 0x5920
+
+#define S_SBRS    28
+#define M_SBRS    0x7U
+#define V_SBRS(x) ((x) << S_SBRS)
+#define G_SBRS(x) (((x) >> S_SBRS) & M_SBRS)
+
+#define S_OTWS    20
+#define M_OTWS    0x7U
+#define V_OTWS(x) ((x) << S_OTWS)
+#define G_OTWS(x) (((x) >> S_OTWS) & M_OTWS)
+
+#define A_PCIE_CORE_REVISION_ID 0x5924
+
+#define S_RVID    20
+#define M_RVID    0xfffU
+#define V_RVID(x) ((x) << S_RVID)
+#define G_RVID(x) (((x) >> S_RVID) & M_RVID)
+
+#define S_BRVN    12
+#define M_BRVN    0xffU
+#define V_BRVN(x) ((x) << S_BRVN)
+#define G_BRVN(x) (((x) >> S_BRVN) & M_BRVN)
+
+#define A_PCIE_T5_DMA_CFG 0x5940
+
+#define S_T5_DMA_MAXREQCNT    20
+#define M_T5_DMA_MAXREQCNT    0xffU
+#define V_T5_DMA_MAXREQCNT(x) ((x) << S_T5_DMA_MAXREQCNT)
+#define G_T5_DMA_MAXREQCNT(x) (((x) >> S_T5_DMA_MAXREQCNT) & M_T5_DMA_MAXREQCNT)
+
+#define S_T5_DMA_MAXRDREQSIZE    17
+#define M_T5_DMA_MAXRDREQSIZE    0x7U
+#define V_T5_DMA_MAXRDREQSIZE(x) ((x) << S_T5_DMA_MAXRDREQSIZE)
+#define G_T5_DMA_MAXRDREQSIZE(x) (((x) >> S_T5_DMA_MAXRDREQSIZE) & M_T5_DMA_MAXRDREQSIZE)
+
+#define S_T5_DMA_MAXRSPCNT    8
+#define M_T5_DMA_MAXRSPCNT    0x1ffU
+#define V_T5_DMA_MAXRSPCNT(x) ((x) << S_T5_DMA_MAXRSPCNT)
+#define G_T5_DMA_MAXRSPCNT(x) (((x) >> S_T5_DMA_MAXRSPCNT) & M_T5_DMA_MAXRSPCNT)
+
+#define S_SEQCHKDIS    7
+#define V_SEQCHKDIS(x) ((x) << S_SEQCHKDIS)
+#define F_SEQCHKDIS    V_SEQCHKDIS(1U)
+
+#define S_MINTAG    0
+#define M_MINTAG    0x7fU
+#define V_MINTAG(x) ((x) << S_MINTAG)
+#define G_MINTAG(x) (((x) >> S_MINTAG) & M_MINTAG)
+
+#define A_PCIE_T5_DMA_STAT 0x5944
+
+#define S_DMA_RESPCNT    20
+#define M_DMA_RESPCNT    0xfffU
+#define V_DMA_RESPCNT(x) ((x) << S_DMA_RESPCNT)
+#define G_DMA_RESPCNT(x) (((x) >> S_DMA_RESPCNT) & M_DMA_RESPCNT)
+
+#define S_DMA_RDREQCNT    12
+#define M_DMA_RDREQCNT    0xffU
+#define V_DMA_RDREQCNT(x) ((x) << S_DMA_RDREQCNT)
+#define G_DMA_RDREQCNT(x) (((x) >> S_DMA_RDREQCNT) & M_DMA_RDREQCNT)
+
+#define S_DMA_WRREQCNT    0
+#define M_DMA_WRREQCNT    0x7ffU
+#define V_DMA_WRREQCNT(x) ((x) << S_DMA_WRREQCNT)
+#define G_DMA_WRREQCNT(x) (((x) >> S_DMA_WRREQCNT) & M_DMA_WRREQCNT)
+
+#define A_PCIE_T5_DMA_STAT2 0x5948
+
+#define S_COOKIECNT    24
+#define M_COOKIECNT    0xfU
+#define V_COOKIECNT(x) ((x) << S_COOKIECNT)
+#define G_COOKIECNT(x) (((x) >> S_COOKIECNT) & M_COOKIECNT)
+
+#define S_RDSEQNUMUPDCNT    20
+#define M_RDSEQNUMUPDCNT    0xfU
+#define V_RDSEQNUMUPDCNT(x) ((x) << S_RDSEQNUMUPDCNT)
+#define G_RDSEQNUMUPDCNT(x) (((x) >> S_RDSEQNUMUPDCNT) & M_RDSEQNUMUPDCNT)
+
+#define S_SIREQCNT    16
+#define M_SIREQCNT    0xfU
+#define V_SIREQCNT(x) ((x) << S_SIREQCNT)
+#define G_SIREQCNT(x) (((x) >> S_SIREQCNT) & M_SIREQCNT)
+
+#define S_WREOPMATCHSOP    12
+#define V_WREOPMATCHSOP(x) ((x) << S_WREOPMATCHSOP)
+#define F_WREOPMATCHSOP    V_WREOPMATCHSOP(1U)
+
+#define S_WRSOPCNT    8
+#define M_WRSOPCNT    0xfU
+#define V_WRSOPCNT(x) ((x) << S_WRSOPCNT)
+#define G_WRSOPCNT(x) (((x) >> S_WRSOPCNT) & M_WRSOPCNT)
+
+#define S_RDSOPCNT    0
+#define M_RDSOPCNT    0xffU
+#define V_RDSOPCNT(x) ((x) << S_RDSOPCNT)
+#define G_RDSOPCNT(x) (((x) >> S_RDSOPCNT) & M_RDSOPCNT)
+
+#define A_PCIE_T5_DMA_STAT3 0x594c
+
+#define S_ATMREQSOPCNT    24
+#define M_ATMREQSOPCNT    0xffU
+#define V_ATMREQSOPCNT(x) ((x) << S_ATMREQSOPCNT)
+#define G_ATMREQSOPCNT(x) (((x) >> S_ATMREQSOPCNT) & M_ATMREQSOPCNT)
+
+#define S_ATMEOPMATCHSOP    17
+#define V_ATMEOPMATCHSOP(x) ((x) << S_ATMEOPMATCHSOP)
+#define F_ATMEOPMATCHSOP    V_ATMEOPMATCHSOP(1U)
+
+#define S_RSPEOPMATCHSOP    16
+#define V_RSPEOPMATCHSOP(x) ((x) << S_RSPEOPMATCHSOP)
+#define F_RSPEOPMATCHSOP    V_RSPEOPMATCHSOP(1U)
+
+#define S_RSPERRCNT    8
+#define M_RSPERRCNT    0xffU
+#define V_RSPERRCNT(x) ((x) << S_RSPERRCNT)
+#define G_RSPERRCNT(x) (((x) >> S_RSPERRCNT) & M_RSPERRCNT)
+
+#define S_RSPSOPCNT    0
+#define M_RSPSOPCNT    0xffU
+#define V_RSPSOPCNT(x) ((x) << S_RSPSOPCNT)
+#define G_RSPSOPCNT(x) (((x) >> S_RSPSOPCNT) & M_RSPSOPCNT)
+
+#define A_PCIE_CORE_OUTBOUND_POSTED_HEADER_BUFFER_ALLOCATION 0x5960
+
+#define S_OP0H    24
+#define M_OP0H    0xfU
+#define V_OP0H(x) ((x) << S_OP0H)
+#define G_OP0H(x) (((x) >> S_OP0H) & M_OP0H)
+
+#define S_OP1H    16
+#define M_OP1H    0xfU
+#define V_OP1H(x) ((x) << S_OP1H)
+#define G_OP1H(x) (((x) >> S_OP1H) & M_OP1H)
+
+#define S_OP2H    8
+#define M_OP2H    0xfU
+#define V_OP2H(x) ((x) << S_OP2H)
+#define G_OP2H(x) (((x) >> S_OP2H) & M_OP2H)
+
+#define S_OP3H    0
+#define M_OP3H    0xfU
+#define V_OP3H(x) ((x) << S_OP3H)
+#define G_OP3H(x) (((x) >> S_OP3H) & M_OP3H)
+
+#define A_PCIE_CORE_OUTBOUND_POSTED_DATA_BUFFER_ALLOCATION 0x5968
+
+#define S_OP0D    24
+#define M_OP0D    0x7fU
+#define V_OP0D(x) ((x) << S_OP0D)
+#define G_OP0D(x) (((x) >> S_OP0D) & M_OP0D)
+
+#define S_OP1D    16
+#define M_OP1D    0x7fU
+#define V_OP1D(x) ((x) << S_OP1D)
+#define G_OP1D(x) (((x) >> S_OP1D) & M_OP1D)
+
+#define S_OP2D    8
+#define M_OP2D    0x7fU
+#define V_OP2D(x) ((x) << S_OP2D)
+#define G_OP2D(x) (((x) >> S_OP2D) & M_OP2D)
+
+#define S_OP3D    0
+#define M_OP3D    0x7fU
+#define V_OP3D(x) ((x) << S_OP3D)
+#define G_OP3D(x) (((x) >> S_OP3D) & M_OP3D)
+
+#define A_PCIE_CORE_INBOUND_POSTED_HEADER_BUFFER_ALLOCATION 0x5970
+
+#define S_IP0H    24
+#define M_IP0H    0x3fU
+#define V_IP0H(x) ((x) << S_IP0H)
+#define G_IP0H(x) (((x) >> S_IP0H) & M_IP0H)
+
+#define S_IP1H    16
+#define M_IP1H    0x3fU
+#define V_IP1H(x) ((x) << S_IP1H)
+#define G_IP1H(x) (((x) >> S_IP1H) & M_IP1H)
+
+#define S_IP2H    8
+#define M_IP2H    0x3fU
+#define V_IP2H(x) ((x) << S_IP2H)
+#define G_IP2H(x) (((x) >> S_IP2H) & M_IP2H)
+
+#define S_IP3H    0
+#define M_IP3H    0x3fU
+#define V_IP3H(x) ((x) << S_IP3H)
+#define G_IP3H(x) (((x) >> S_IP3H) & M_IP3H)
+
+#define A_PCIE_CORE_INBOUND_POSTED_DATA_BUFFER_ALLOCATION 0x5978
+
+#define S_IP0D    24
+#define M_IP0D    0xffU
+#define V_IP0D(x) ((x) << S_IP0D)
+#define G_IP0D(x) (((x) >> S_IP0D) & M_IP0D)
+
+#define S_IP1D    16
+#define M_IP1D    0xffU
+#define V_IP1D(x) ((x) << S_IP1D)
+#define G_IP1D(x) (((x) >> S_IP1D) & M_IP1D)
+
+#define S_IP2D    8
+#define M_IP2D    0xffU
+#define V_IP2D(x) ((x) << S_IP2D)
+#define G_IP2D(x) (((x) >> S_IP2D) & M_IP2D)
+
+#define S_IP3D    0
+#define M_IP3D    0xffU
+#define V_IP3D(x) ((x) << S_IP3D)
+#define G_IP3D(x) (((x) >> S_IP3D) & M_IP3D)
+
+#define A_PCIE_CORE_OUTBOUND_NON_POSTED_BUFFER_ALLOCATION 0x5980
+
+#define S_ON0H    24
+#define M_ON0H    0xfU
+#define V_ON0H(x) ((x) << S_ON0H)
+#define G_ON0H(x) (((x) >> S_ON0H) & M_ON0H)
+
+#define S_ON1H    16
+#define M_ON1H    0xfU
+#define V_ON1H(x) ((x) << S_ON1H)
+#define G_ON1H(x) (((x) >> S_ON1H) & M_ON1H)
+
+#define S_ON2H    8
+#define M_ON2H    0xfU
+#define V_ON2H(x) ((x) << S_ON2H)
+#define G_ON2H(x) (((x) >> S_ON2H) & M_ON2H)
+
+#define S_ON3H    0
+#define M_ON3H    0xfU
+#define V_ON3H(x) ((x) << S_ON3H)
+#define G_ON3H(x) (((x) >> S_ON3H) & M_ON3H)
+
+#define A_PCIE_T5_CMD_CFG 0x5980
+
+#define S_T5_CMD_MAXRDREQSIZE    17
+#define M_T5_CMD_MAXRDREQSIZE    0x7U
+#define V_T5_CMD_MAXRDREQSIZE(x) ((x) << S_T5_CMD_MAXRDREQSIZE)
+#define G_T5_CMD_MAXRDREQSIZE(x) (((x) >> S_T5_CMD_MAXRDREQSIZE) & M_T5_CMD_MAXRDREQSIZE)
+
+#define S_T5_CMD_MAXRSPCNT    8
+#define M_T5_CMD_MAXRSPCNT    0xffU
+#define V_T5_CMD_MAXRSPCNT(x) ((x) << S_T5_CMD_MAXRSPCNT)
+#define G_T5_CMD_MAXRSPCNT(x) (((x) >> S_T5_CMD_MAXRSPCNT) & M_T5_CMD_MAXRSPCNT)
+
+#define S_USECMDPOOL    7
+#define V_USECMDPOOL(x) ((x) << S_USECMDPOOL)
+#define F_USECMDPOOL    V_USECMDPOOL(1U)
+
+#define A_PCIE_T5_CMD_STAT 0x5984
+
+#define S_T5_STAT_RSPCNT    20
+#define M_T5_STAT_RSPCNT    0x7ffU
+#define V_T5_STAT_RSPCNT(x) ((x) << S_T5_STAT_RSPCNT)
+#define G_T5_STAT_RSPCNT(x) (((x) >> S_T5_STAT_RSPCNT) & M_T5_STAT_RSPCNT)
+
+#define S_RDREQCNT    12
+#define M_RDREQCNT    0x1fU
+#define V_RDREQCNT(x) ((x) << S_RDREQCNT)
+#define G_RDREQCNT(x) (((x) >> S_RDREQCNT) & M_RDREQCNT)
+
+#define A_PCIE_CORE_INBOUND_NON_POSTED_REQUESTS_BUFFER_ALLOCATION 0x5988
+
+#define S_IN0H    24
+#define M_IN0H    0x3fU
+#define V_IN0H(x) ((x) << S_IN0H)
+#define G_IN0H(x) (((x) >> S_IN0H) & M_IN0H)
+
+#define S_IN1H    16
+#define M_IN1H    0x3fU
+#define V_IN1H(x) ((x) << S_IN1H)
+#define G_IN1H(x) (((x) >> S_IN1H) & M_IN1H)
+
+#define S_IN2H    8
+#define M_IN2H    0x3fU
+#define V_IN2H(x) ((x) << S_IN2H)
+#define G_IN2H(x) (((x) >> S_IN2H) & M_IN2H)
+
+#define S_IN3H    0
+#define M_IN3H    0x3fU
+#define V_IN3H(x) ((x) << S_IN3H)
+#define G_IN3H(x) (((x) >> S_IN3H) & M_IN3H)
+
+#define A_PCIE_T5_CMD_STAT2 0x5988
+#define A_PCIE_T5_CMD_STAT3 0x598c
+#define A_PCIE_CORE_PCI_EXPRESS_TAGS_ALLOCATION 0x5990
+
+#define S_OC0T    24
+#define M_OC0T    0xffU
+#define V_OC0T(x) ((x) << S_OC0T)
+#define G_OC0T(x) (((x) >> S_OC0T) & M_OC0T)
+
+#define S_OC1T    16
+#define M_OC1T    0xffU
+#define V_OC1T(x) ((x) << S_OC1T)
+#define G_OC1T(x) (((x) >> S_OC1T) & M_OC1T)
+
+#define S_OC2T    8
+#define M_OC2T    0xffU
+#define V_OC2T(x) ((x) << S_OC2T)
+#define G_OC2T(x) (((x) >> S_OC2T) & M_OC2T)
+
+#define S_OC3T    0
+#define M_OC3T    0xffU
+#define V_OC3T(x) ((x) << S_OC3T)
+#define G_OC3T(x) (((x) >> S_OC3T) & M_OC3T)
+
+#define A_PCIE_CORE_GBIF_READ_TAGS_ALLOCATION 0x5998
+
+#define S_IC0T    24
+#define M_IC0T    0x3fU
+#define V_IC0T(x) ((x) << S_IC0T)
+#define G_IC0T(x) (((x) >> S_IC0T) & M_IC0T)
+
+#define S_IC1T    16
+#define M_IC1T    0x3fU
+#define V_IC1T(x) ((x) << S_IC1T)
+#define G_IC1T(x) (((x) >> S_IC1T) & M_IC1T)
+
+#define S_IC2T    8
+#define M_IC2T    0x3fU
+#define V_IC2T(x) ((x) << S_IC2T)
+#define G_IC2T(x) (((x) >> S_IC2T) & M_IC2T)
+
+#define S_IC3T    0
+#define M_IC3T    0x3fU
+#define V_IC3T(x) ((x) << S_IC3T)
+#define G_IC3T(x) (((x) >> S_IC3T) & M_IC3T)
+
+#define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_CONTROL 0x59a0
+
+#define S_VRB0    31
+#define V_VRB0(x) ((x) << S_VRB0)
+#define F_VRB0    V_VRB0(1U)
+
+#define S_VRB1    30
+#define V_VRB1(x) ((x) << S_VRB1)
+#define F_VRB1    V_VRB1(1U)
+
+#define S_VRB2    29
+#define V_VRB2(x) ((x) << S_VRB2)
+#define F_VRB2    V_VRB2(1U)
+
+#define S_VRB3    28
+#define V_VRB3(x) ((x) << S_VRB3)
+#define F_VRB3    V_VRB3(1U)
+
+#define S_PSFE    26
+#define V_PSFE(x) ((x) << S_PSFE)
+#define F_PSFE    V_PSFE(1U)
+
+#define S_RVDE    25
+#define V_RVDE(x) ((x) << S_RVDE)
+#define F_RVDE    V_RVDE(1U)
+
+#define S_TXE0    23
+#define V_TXE0(x) ((x) << S_TXE0)
+#define F_TXE0    V_TXE0(1U)
+
+#define S_TXE1    22
+#define V_TXE1(x) ((x) << S_TXE1)
+#define F_TXE1    V_TXE1(1U)
+
+#define S_TXE2    21
+#define V_TXE2(x) ((x) << S_TXE2)
+#define F_TXE2    V_TXE2(1U)
+
+#define S_TXE3    20
+#define V_TXE3(x) ((x) << S_TXE3)
+#define F_TXE3    V_TXE3(1U)
+
+#define S_RPAM    13
+#define V_RPAM(x) ((x) << S_RPAM)
+#define F_RPAM    V_RPAM(1U)
+
+#define S_RTOS    4
+#define M_RTOS    0xfU
+#define V_RTOS(x) ((x) << S_RTOS)
+#define G_RTOS(x) (((x) >> S_RTOS) & M_RTOS)
+
+#define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4
+
+#define S_TPCP    30
+#define V_TPCP(x) ((x) << S_TPCP)
+#define F_TPCP    V_TPCP(1U)
+
+#define S_TNPP    29
+#define V_TNPP(x) ((x) << S_TNPP)
+#define F_TNPP    V_TNPP(1U)
+
+#define S_TFTP    28
+#define V_TFTP(x) ((x) << S_TFTP)
+#define F_TFTP    V_TFTP(1U)
+
+#define S_TCAP    27
+#define V_TCAP(x) ((x) << S_TCAP)
+#define F_TCAP    V_TCAP(1U)
+
+#define S_TCIP    26
+#define V_TCIP(x) ((x) << S_TCIP)
+#define F_TCIP    V_TCIP(1U)
+
+#define S_RCAP    25
+#define V_RCAP(x) ((x) << S_RCAP)
+#define F_RCAP    V_RCAP(1U)
+
+#define S_PLUP    23
+#define V_PLUP(x) ((x) << S_PLUP)
+#define F_PLUP    V_PLUP(1U)
+
+#define S_PLDN    22
+#define V_PLDN(x) ((x) << S_PLDN)
+#define F_PLDN    V_PLDN(1U)
+
+#define S_OTDD    21
+#define V_OTDD(x) ((x) << S_OTDD)
+#define F_OTDD    V_OTDD(1U)
+
+#define S_GTRP    20
+#define V_GTRP(x) ((x) << S_GTRP)
+#define F_GTRP    V_GTRP(1U)
+
+#define S_RDPE    18
+#define V_RDPE(x) ((x) << S_RDPE)
+#define F_RDPE    V_RDPE(1U)
+
+#define S_TDCE    17
+#define V_TDCE(x) ((x) << S_TDCE)
+#define F_TDCE    V_TDCE(1U)
+
+#define S_TDUE    16
+#define V_TDUE(x) ((x) << S_TDUE)
+#define F_TDUE    V_TDUE(1U)
+
+#define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_ERROR_SEVERITY 0x59a8
+
+#define S_TPCS    30
+#define V_TPCS(x) ((x) << S_TPCS)
+#define F_TPCS    V_TPCS(1U)
+
+#define S_TNPS    29
+#define V_TNPS(x) ((x) << S_TNPS)
+#define F_TNPS    V_TNPS(1U)
+
+#define S_TFTS    28
+#define V_TFTS(x) ((x) << S_TFTS)
+#define F_TFTS    V_TFTS(1U)
+
+#define S_TCAS    27
+#define V_TCAS(x) ((x) << S_TCAS)
+#define F_TCAS    V_TCAS(1U)
+
+#define S_TCIS    26
+#define V_TCIS(x) ((x) << S_TCIS)
+#define F_TCIS    V_TCIS(1U)
+
+#define S_RCAS    25
+#define V_RCAS(x) ((x) << S_RCAS)
+#define F_RCAS    V_RCAS(1U)
+
+#define S_PLUS    23
+#define V_PLUS(x) ((x) << S_PLUS)
+#define F_PLUS    V_PLUS(1U)
+
+#define S_PLDS    22
+#define V_PLDS(x) ((x) << S_PLDS)
+#define F_PLDS    V_PLDS(1U)
+
+#define S_OTDS    21
+#define V_OTDS(x) ((x) << S_OTDS)
+#define F_OTDS    V_OTDS(1U)
+
+#define S_RDPS    18
+#define V_RDPS(x) ((x) << S_RDPS)
+#define F_RDPS    V_RDPS(1U)
+
+#define S_TDCS    17
+#define V_TDCS(x) ((x) << S_TDCS)
+#define F_TDCS    V_TDCS(1U)
+
+#define S_TDUS    16
+#define V_TDUS(x) ((x) << S_TDUS)
+#define F_TDUS    V_TDUS(1U)
+
+#define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE 0x59ac
+
+#define S_TPCI    30
+#define V_TPCI(x) ((x) << S_TPCI)
+#define F_TPCI    V_TPCI(1U)
+
+#define S_TNPI    29
+#define V_TNPI(x) ((x) << S_TNPI)
+#define F_TNPI    V_TNPI(1U)
+
+#define S_TFTI    28
+#define V_TFTI(x) ((x) << S_TFTI)
+#define F_TFTI    V_TFTI(1U)
+
+#define S_TCAI    27
+#define V_TCAI(x) ((x) << S_TCAI)
+#define F_TCAI    V_TCAI(1U)
+
+#define S_TCII    26
+#define V_TCII(x) ((x) << S_TCII)
+#define F_TCII    V_TCII(1U)
+
+#define S_RCAI    25
+#define V_RCAI(x) ((x) << S_RCAI)
+#define F_RCAI    V_RCAI(1U)
+
+#define S_PLUI    23
+#define V_PLUI(x) ((x) << S_PLUI)
+#define F_PLUI    V_PLUI(1U)
+
+#define S_PLDI    22
+#define V_PLDI(x) ((x) << S_PLDI)
+#define F_PLDI    V_PLDI(1U)
+
+#define S_OTDI    21
+#define V_OTDI(x) ((x) << S_OTDI)
+#define F_OTDI    V_OTDI(1U)
+
+#define A_PCIE_CORE_ROOT_COMPLEX_STATUS 0x59b0
+
+#define S_RLCE    31
+#define V_RLCE(x) ((x) << S_RLCE)
+#define F_RLCE    V_RLCE(1U)
+
+#define S_RLNE    30
+#define V_RLNE(x) ((x) << S_RLNE)
+#define F_RLNE    V_RLNE(1U)
+
+#define S_RLFE    29
+#define V_RLFE(x) ((x) << S_RLFE)
+#define F_RLFE    V_RLFE(1U)
+
+#define S_RCPE    25
+#define V_RCPE(x) ((x) << S_RCPE)
+#define F_RCPE    V_RCPE(1U)
+
+#define S_RCTO    24
+#define V_RCTO(x) ((x) << S_RCTO)
+#define F_RCTO    V_RCTO(1U)
+
+#define S_PINA    23
+#define V_PINA(x) ((x) << S_PINA)
+#define F_PINA    V_PINA(1U)
+
+#define S_PINB    22
+#define V_PINB(x) ((x) << S_PINB)
+#define F_PINB    V_PINB(1U)
+
+#define S_PINC    21
+#define V_PINC(x) ((x) << S_PINC)
+#define F_PINC    V_PINC(1U)
+
+#define S_PIND    20
+#define V_PIND(x) ((x) << S_PIND)
+#define F_PIND    V_PIND(1U)
+
+#define S_ALER    19
+#define V_ALER(x) ((x) << S_ALER)
+#define F_ALER    V_ALER(1U)
+
+#define S_CRSE    18
+#define V_CRSE(x) ((x) << S_CRSE)
+#define F_CRSE    V_CRSE(1U)
+
+#define A_PCIE_T5_HMA_CFG 0x59b0
+
+#define S_HMA_MAXREQCNT    20
+#define M_HMA_MAXREQCNT    0x1fU
+#define V_HMA_MAXREQCNT(x) ((x) << S_HMA_MAXREQCNT)
+#define G_HMA_MAXREQCNT(x) (((x) >> S_HMA_MAXREQCNT) & M_HMA_MAXREQCNT)
+
+#define S_T5_HMA_MAXRDREQSIZE    17
+#define M_T5_HMA_MAXRDREQSIZE    0x7U
+#define V_T5_HMA_MAXRDREQSIZE(x) ((x) << S_T5_HMA_MAXRDREQSIZE)
+#define G_T5_HMA_MAXRDREQSIZE(x) (((x) >> S_T5_HMA_MAXRDREQSIZE) & M_T5_HMA_MAXRDREQSIZE)
+
+#define S_T5_HMA_MAXRSPCNT    8
+#define M_T5_HMA_MAXRSPCNT    0x1fU
+#define V_T5_HMA_MAXRSPCNT(x) ((x) << S_T5_HMA_MAXRSPCNT)
+#define G_T5_HMA_MAXRSPCNT(x) (((x) >> S_T5_HMA_MAXRSPCNT) & M_T5_HMA_MAXRSPCNT)
+
+#define A_PCIE_CORE_ROOT_COMPLEX_ERROR_SEVERITY 0x59b4
+
+#define S_RLCS    31
+#define V_RLCS(x) ((x) << S_RLCS)
+#define F_RLCS    V_RLCS(1U)
+
+#define S_RLNS    30
+#define V_RLNS(x) ((x) << S_RLNS)
+#define F_RLNS    V_RLNS(1U)
+
+#define S_RLFS    29
+#define V_RLFS(x) ((x) << S_RLFS)
+#define F_RLFS    V_RLFS(1U)
+
+#define S_RCPS    25
+#define V_RCPS(x) ((x) << S_RCPS)
+#define F_RCPS    V_RCPS(1U)
+
+#define S_RCTS    24
+#define V_RCTS(x) ((x) << S_RCTS)
+#define F_RCTS    V_RCTS(1U)
+
+#define S_PAAS    23
+#define V_PAAS(x) ((x) << S_PAAS)
+#define F_PAAS    V_PAAS(1U)
+
+#define S_PABS    22
+#define V_PABS(x) ((x) << S_PABS)
+#define F_PABS    V_PABS(1U)
+
+#define S_PACS    21
+#define V_PACS(x) ((x) << S_PACS)
+#define F_PACS    V_PACS(1U)
+
+#define S_PADS    20
+#define V_PADS(x) ((x) << S_PADS)
+#define F_PADS    V_PADS(1U)
+
+#define S_ALES    19
+#define V_ALES(x) ((x) << S_ALES)
+#define F_ALES    V_ALES(1U)
+
+#define S_CRSS    18
+#define V_CRSS(x) ((x) << S_CRSS)
+#define F_CRSS    V_CRSS(1U)
+
+#define A_PCIE_T5_HMA_STAT 0x59b4
+
+#define S_HMA_RESPCNT    20
+#define M_HMA_RESPCNT    0x1ffU
+#define V_HMA_RESPCNT(x) ((x) << S_HMA_RESPCNT)
+#define G_HMA_RESPCNT(x) (((x) >> S_HMA_RESPCNT) & M_HMA_RESPCNT)
+
+#define S_HMA_RDREQCNT    12
+#define M_HMA_RDREQCNT    0x3fU
+#define V_HMA_RDREQCNT(x) ((x) << S_HMA_RDREQCNT)
+#define G_HMA_RDREQCNT(x) (((x) >> S_HMA_RDREQCNT) & M_HMA_RDREQCNT)
+
+#define S_HMA_WRREQCNT    0
+#define M_HMA_WRREQCNT    0x1ffU
+#define V_HMA_WRREQCNT(x) ((x) << S_HMA_WRREQCNT)
+#define G_HMA_WRREQCNT(x) (((x) >> S_HMA_WRREQCNT) & M_HMA_WRREQCNT)
+
+#define A_PCIE_CORE_ROOT_COMPLEX_INTERRUPT_ENABLE 0x59b8
+
+#define S_RLCI    31
+#define V_RLCI(x) ((x) << S_RLCI)
+#define F_RLCI    V_RLCI(1U)
+
+#define S_RLNI    30
+#define V_RLNI(x) ((x) << S_RLNI)
+#define F_RLNI    V_RLNI(1U)
+
+#define S_RLFI    29
+#define V_RLFI(x) ((x) << S_RLFI)
+#define F_RLFI    V_RLFI(1U)
+
+#define S_RCPI    25
+#define V_RCPI(x) ((x) << S_RCPI)
+#define F_RCPI    V_RCPI(1U)
+
+#define S_RCTI    24
+#define V_RCTI(x) ((x) << S_RCTI)
+#define F_RCTI    V_RCTI(1U)
+
+#define S_PAAI    23
+#define V_PAAI(x) ((x) << S_PAAI)
+#define F_PAAI    V_PAAI(1U)
+
+#define S_PABI    22
+#define V_PABI(x) ((x) << S_PABI)
+#define F_PABI    V_PABI(1U)
+
+#define S_PACI    21
+#define V_PACI(x) ((x) << S_PACI)
+#define F_PACI    V_PACI(1U)
+
+#define S_PADI    20
+#define V_PADI(x) ((x) << S_PADI)
+#define F_PADI    V_PADI(1U)
+
+#define S_ALEI    19
+#define V_ALEI(x) ((x) << S_ALEI)
+#define F_ALEI    V_ALEI(1U)
+
+#define S_CRSI    18
+#define V_CRSI(x) ((x) << S_CRSI)
+#define F_CRSI    V_CRSI(1U)
+
+#define A_PCIE_T5_HMA_STAT2 0x59b8
+#define A_PCIE_CORE_ENDPOINT_STATUS 0x59bc
+
+#define S_PTOM    31
+#define V_PTOM(x) ((x) << S_PTOM)
+#define F_PTOM    V_PTOM(1U)
+
+#define S_ALEA    29
+#define V_ALEA(x) ((x) << S_ALEA)
+#define F_ALEA    V_ALEA(1U)
+
+#define S_PMC0    23
+#define V_PMC0(x) ((x) << S_PMC0)
+#define F_PMC0    V_PMC0(1U)
+
+#define S_PMC1    22
+#define V_PMC1(x) ((x) << S_PMC1)
+#define F_PMC1    V_PMC1(1U)
+
+#define S_PMC2    21
+#define V_PMC2(x) ((x) << S_PMC2)
+#define F_PMC2    V_PMC2(1U)
+
+#define S_PMC3    20
+#define V_PMC3(x) ((x) << S_PMC3)
+#define F_PMC3    V_PMC3(1U)
+
+#define S_PMC4    19
+#define V_PMC4(x) ((x) << S_PMC4)
+#define F_PMC4    V_PMC4(1U)
+
+#define S_PMC5    18
+#define V_PMC5(x) ((x) << S_PMC5)
+#define F_PMC5    V_PMC5(1U)
+
+#define S_PMC6    17
+#define V_PMC6(x) ((x) << S_PMC6)
+#define F_PMC6    V_PMC6(1U)
+
+#define S_PMC7    16
+#define V_PMC7(x) ((x) << S_PMC7)
+#define F_PMC7    V_PMC7(1U)
+
+#define A_PCIE_T5_HMA_STAT3 0x59bc
+#define A_PCIE_CORE_ENDPOINT_ERROR_SEVERITY 0x59c0
+
+#define S_PTOS    31
+#define V_PTOS(x) ((x) << S_PTOS)
+#define F_PTOS    V_PTOS(1U)
+
+#define S_AENS    29
+#define V_AENS(x) ((x) << S_AENS)
+#define F_AENS    V_AENS(1U)
+
+#define S_PC0S    23
+#define V_PC0S(x) ((x) << S_PC0S)
+#define F_PC0S    V_PC0S(1U)
+
+#define S_PC1S    22
+#define V_PC1S(x) ((x) << S_PC1S)
+#define F_PC1S    V_PC1S(1U)
+
+#define S_PC2S    21
+#define V_PC2S(x) ((x) << S_PC2S)
+#define F_PC2S    V_PC2S(1U)
+
+#define S_PC3S    20
+#define V_PC3S(x) ((x) << S_PC3S)
+#define F_PC3S    V_PC3S(1U)
+
+#define S_PC4S    19
+#define V_PC4S(x) ((x) << S_PC4S)
+#define F_PC4S    V_PC4S(1U)
+
+#define S_PC5S    18
+#define V_PC5S(x) ((x) << S_PC5S)
+#define F_PC5S    V_PC5S(1U)
+
+#define S_PC6S    17
+#define V_PC6S(x) ((x) << S_PC6S)
+#define F_PC6S    V_PC6S(1U)
+
+#define S_PC7S    16
+#define V_PC7S(x) ((x) << S_PC7S)
+#define F_PC7S    V_PC7S(1U)
+
+#define S_PME0    15
+#define V_PME0(x) ((x) << S_PME0)
+#define F_PME0    V_PME0(1U)
+
+#define S_PME1    14
+#define V_PME1(x) ((x) << S_PME1)
+#define F_PME1    V_PME1(1U)
+
+#define S_PME2    13
+#define V_PME2(x) ((x) << S_PME2)
+#define F_PME2    V_PME2(1U)
+
+#define S_PME3    12
+#define V_PME3(x) ((x) << S_PME3)
+#define F_PME3    V_PME3(1U)
+
+#define S_PME4    11
+#define V_PME4(x) ((x) << S_PME4)
+#define F_PME4    V_PME4(1U)
+
+#define S_PME5    10
+#define V_PME5(x) ((x) << S_PME5)
+#define F_PME5    V_PME5(1U)
+
+#define S_PME6    9
+#define V_PME6(x) ((x) << S_PME6)
+#define F_PME6    V_PME6(1U)
+
+#define S_PME7    8
+#define V_PME7(x) ((x) << S_PME7)
+#define F_PME7    V_PME7(1U)
+
+#define A_PCIE_CGEN 0x59c0
+
+#define S_VPD_DYNAMIC_CGEN    26
+#define V_VPD_DYNAMIC_CGEN(x) ((x) << S_VPD_DYNAMIC_CGEN)
+#define F_VPD_DYNAMIC_CGEN    V_VPD_DYNAMIC_CGEN(1U)
+
+#define S_MA_DYNAMIC_CGEN    25
+#define V_MA_DYNAMIC_CGEN(x) ((x) << S_MA_DYNAMIC_CGEN)
+#define F_MA_DYNAMIC_CGEN    V_MA_DYNAMIC_CGEN(1U)
+
+#define S_TAGQ_DYNAMIC_CGEN    24
+#define V_TAGQ_DYNAMIC_CGEN(x) ((x) << S_TAGQ_DYNAMIC_CGEN)
+#define F_TAGQ_DYNAMIC_CGEN    V_TAGQ_DYNAMIC_CGEN(1U)
+
+#define S_REQCTL_DYNAMIC_CGEN    23
+#define V_REQCTL_DYNAMIC_CGEN(x) ((x) << S_REQCTL_DYNAMIC_CGEN)
+#define F_REQCTL_DYNAMIC_CGEN    V_REQCTL_DYNAMIC_CGEN(1U)
+
+#define S_RSPDATAPROC_DYNAMIC_CGEN    22
+#define V_RSPDATAPROC_DYNAMIC_CGEN(x) ((x) << S_RSPDATAPROC_DYNAMIC_CGEN)
+#define F_RSPDATAPROC_DYNAMIC_CGEN    V_RSPDATAPROC_DYNAMIC_CGEN(1U)
+
+#define S_RSPRDQ_DYNAMIC_CGEN    21
+#define V_RSPRDQ_DYNAMIC_CGEN(x) ((x) << S_RSPRDQ_DYNAMIC_CGEN)
+#define F_RSPRDQ_DYNAMIC_CGEN    V_RSPRDQ_DYNAMIC_CGEN(1U)
+
+#define S_RSPIPIF_DYNAMIC_CGEN    20
+#define V_RSPIPIF_DYNAMIC_CGEN(x) ((x) << S_RSPIPIF_DYNAMIC_CGEN)
+#define F_RSPIPIF_DYNAMIC_CGEN    V_RSPIPIF_DYNAMIC_CGEN(1U)
+
+#define S_HMA_STATIC_CGEN    19
+#define V_HMA_STATIC_CGEN(x) ((x) << S_HMA_STATIC_CGEN)
+#define F_HMA_STATIC_CGEN    V_HMA_STATIC_CGEN(1U)
+
+#define S_HMA_DYNAMIC_CGEN    18
+#define V_HMA_DYNAMIC_CGEN(x) ((x) << S_HMA_DYNAMIC_CGEN)
+#define F_HMA_DYNAMIC_CGEN    V_HMA_DYNAMIC_CGEN(1U)
+
+#define S_CMD_STATIC_CGEN    16
+#define V_CMD_STATIC_CGEN(x) ((x) << S_CMD_STATIC_CGEN)
+#define F_CMD_STATIC_CGEN    V_CMD_STATIC_CGEN(1U)
+
+#define S_CMD_DYNAMIC_CGEN    15
+#define V_CMD_DYNAMIC_CGEN(x) ((x) << S_CMD_DYNAMIC_CGEN)
+#define F_CMD_DYNAMIC_CGEN    V_CMD_DYNAMIC_CGEN(1U)
+
+#define S_DMA_STATIC_CGEN    13
+#define V_DMA_STATIC_CGEN(x) ((x) << S_DMA_STATIC_CGEN)
+#define F_DMA_STATIC_CGEN    V_DMA_STATIC_CGEN(1U)
+
+#define S_DMA_DYNAMIC_CGEN    12
+#define V_DMA_DYNAMIC_CGEN(x) ((x) << S_DMA_DYNAMIC_CGEN)
+#define F_DMA_DYNAMIC_CGEN    V_DMA_DYNAMIC_CGEN(1U)
+
+#define S_VFID_SLEEPSTATUS    10
+#define V_VFID_SLEEPSTATUS(x) ((x) << S_VFID_SLEEPSTATUS)
+#define F_VFID_SLEEPSTATUS    V_VFID_SLEEPSTATUS(1U)
+
+#define S_VC1_SLEEPSTATUS    9
+#define V_VC1_SLEEPSTATUS(x) ((x) << S_VC1_SLEEPSTATUS)
+#define F_VC1_SLEEPSTATUS    V_VC1_SLEEPSTATUS(1U)
+
+#define S_STI_SLEEPSTATUS    8
+#define V_STI_SLEEPSTATUS(x) ((x) << S_STI_SLEEPSTATUS)
+#define F_STI_SLEEPSTATUS    V_STI_SLEEPSTATUS(1U)
+
+#define S_VFID_SLEEPREQ    2
+#define V_VFID_SLEEPREQ(x) ((x) << S_VFID_SLEEPREQ)
+#define F_VFID_SLEEPREQ    V_VFID_SLEEPREQ(1U)
+
+#define S_VC1_SLEEPREQ    1
+#define V_VC1_SLEEPREQ(x) ((x) << S_VC1_SLEEPREQ)
+#define F_VC1_SLEEPREQ    V_VC1_SLEEPREQ(1U)
+
+#define S_STI_SLEEPREQ    0
+#define V_STI_SLEEPREQ(x) ((x) << S_STI_SLEEPREQ)
+#define F_STI_SLEEPREQ    V_STI_SLEEPREQ(1U)
+
+#define A_PCIE_CORE_ENDPOINT_INTERRUPT_ENABLE 0x59c4
+
+#define S_PTOI    31
+#define V_PTOI(x) ((x) << S_PTOI)
+#define F_PTOI    V_PTOI(1U)
+
+#define S_AENI    29
+#define V_AENI(x) ((x) << S_AENI)
+#define F_AENI    V_AENI(1U)
+
+#define S_PC0I    23
+#define V_PC0I(x) ((x) << S_PC0I)
+#define F_PC0I    V_PC0I(1U)
+
+#define S_PC1I    22
+#define V_PC1I(x) ((x) << S_PC1I)
+#define F_PC1I    V_PC1I(1U)
+
+#define S_PC2I    21
+#define V_PC2I(x) ((x) << S_PC2I)
+#define F_PC2I    V_PC2I(1U)
+
+#define S_PC3I    20
+#define V_PC3I(x) ((x) << S_PC3I)
+#define F_PC3I    V_PC3I(1U)
+
+#define S_PC4I    19
+#define V_PC4I(x) ((x) << S_PC4I)
+#define F_PC4I    V_PC4I(1U)
+
+#define S_PC5I    18
+#define V_PC5I(x) ((x) << S_PC5I)
+#define F_PC5I    V_PC5I(1U)
+
+#define S_PC6I    17
+#define V_PC6I(x) ((x) << S_PC6I)
+#define F_PC6I    V_PC6I(1U)
+
+#define S_PC7I    16
+#define V_PC7I(x) ((x) << S_PC7I)
+#define F_PC7I    V_PC7I(1U)
+
+#define A_PCIE_MA_RSP 0x59c4
+
+#define S_TIMERVALUE    8
+#define M_TIMERVALUE    0xffffffU
+#define V_TIMERVALUE(x) ((x) << S_TIMERVALUE)
+#define G_TIMERVALUE(x) (((x) >> S_TIMERVALUE) & M_TIMERVALUE)
+
+#define S_MAREQTIMEREN    1
+#define V_MAREQTIMEREN(x) ((x) << S_MAREQTIMEREN)
+#define F_MAREQTIMEREN    V_MAREQTIMEREN(1U)
+
+#define S_MARSPTIMEREN    0
+#define V_MARSPTIMEREN(x) ((x) << S_MARSPTIMEREN)
+#define F_MARSPTIMEREN    V_MARSPTIMEREN(1U)
+
+#define A_PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_1 0x59c8
+
+#define S_TOAK    31
+#define V_TOAK(x) ((x) << S_TOAK)
+#define F_TOAK    V_TOAK(1U)
+
+#define S_L1RS    23
+#define V_L1RS(x) ((x) << S_L1RS)
+#define F_L1RS    V_L1RS(1U)
+
+#define S_L23S    22
+#define V_L23S(x) ((x) << S_L23S)
+#define F_L23S    V_L23S(1U)
+
+#define S_AL1S    21
+#define V_AL1S(x) ((x) << S_AL1S)
+#define F_AL1S    V_AL1S(1U)
+
+#define S_ALET    19
+#define V_ALET(x) ((x) << S_ALET)
+#define F_ALET    V_ALET(1U)
+
+#define A_PCIE_HPRD 0x59c8
+
+#define S_NPH_CREDITSAVAILVC0    19
+#define M_NPH_CREDITSAVAILVC0    0x3U
+#define V_NPH_CREDITSAVAILVC0(x) ((x) << S_NPH_CREDITSAVAILVC0)
+#define G_NPH_CREDITSAVAILVC0(x) (((x) >> S_NPH_CREDITSAVAILVC0) & M_NPH_CREDITSAVAILVC0)
+
+#define S_NPD_CREDITSAVAILVC0    17
+#define M_NPD_CREDITSAVAILVC0    0x3U
+#define V_NPD_CREDITSAVAILVC0(x) ((x) << S_NPD_CREDITSAVAILVC0)
+#define G_NPD_CREDITSAVAILVC0(x) (((x) >> S_NPD_CREDITSAVAILVC0) & M_NPD_CREDITSAVAILVC0)
+
+#define S_NPH_CREDITSAVAILVC1    15
+#define M_NPH_CREDITSAVAILVC1    0x3U
+#define V_NPH_CREDITSAVAILVC1(x) ((x) << S_NPH_CREDITSAVAILVC1)
+#define G_NPH_CREDITSAVAILVC1(x) (((x) >> S_NPH_CREDITSAVAILVC1) & M_NPH_CREDITSAVAILVC1)
+
+#define S_NPD_CREDITSAVAILVC1    13
+#define M_NPD_CREDITSAVAILVC1    0x3U
+#define V_NPD_CREDITSAVAILVC1(x) ((x) << S_NPD_CREDITSAVAILVC1)
+#define G_NPD_CREDITSAVAILVC1(x) (((x) >> S_NPD_CREDITSAVAILVC1) & M_NPD_CREDITSAVAILVC1)
+
+#define S_NPH_CREDITSREQUIRED    11
+#define M_NPH_CREDITSREQUIRED    0x3U
+#define V_NPH_CREDITSREQUIRED(x) ((x) << S_NPH_CREDITSREQUIRED)
+#define G_NPH_CREDITSREQUIRED(x) (((x) >> S_NPH_CREDITSREQUIRED) & M_NPH_CREDITSREQUIRED)
+
+#define S_NPD_CREDITSREQUIRED    9
+#define M_NPD_CREDITSREQUIRED    0x3U
+#define V_NPD_CREDITSREQUIRED(x) ((x) << S_NPD_CREDITSREQUIRED)
+#define G_NPD_CREDITSREQUIRED(x) (((x) >> S_NPD_CREDITSREQUIRED) & M_NPD_CREDITSREQUIRED)
+
+#define S_REQBURSTCOUNT    5
+#define M_REQBURSTCOUNT    0xfU
+#define V_REQBURSTCOUNT(x) ((x) << S_REQBURSTCOUNT)
+#define G_REQBURSTCOUNT(x) (((x) >> S_REQBURSTCOUNT) & M_REQBURSTCOUNT)
+
+#define S_REQBURSTFREQUENCY    1
+#define M_REQBURSTFREQUENCY    0xfU
+#define V_REQBURSTFREQUENCY(x) ((x) << S_REQBURSTFREQUENCY)
+#define G_REQBURSTFREQUENCY(x) (((x) >> S_REQBURSTFREQUENCY) & M_REQBURSTFREQUENCY)
+
+#define S_ENABLEVC1    0
+#define V_ENABLEVC1(x) ((x) << S_ENABLEVC1)
+#define F_ENABLEVC1    V_ENABLEVC1(1U)
+
+#define A_PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_2 0x59cc
+
+#define S_CPM0    30
+#define M_CPM0    0x3U
+#define V_CPM0(x) ((x) << S_CPM0)
+#define G_CPM0(x) (((x) >> S_CPM0) & M_CPM0)
+
+#define S_CPM1    28
+#define M_CPM1    0x3U
+#define V_CPM1(x) ((x) << S_CPM1)
+#define G_CPM1(x) (((x) >> S_CPM1) & M_CPM1)
+
+#define S_CPM2    26
+#define M_CPM2    0x3U
+#define V_CPM2(x) ((x) << S_CPM2)
+#define G_CPM2(x) (((x) >> S_CPM2) & M_CPM2)
+
+#define S_CPM3    24
+#define M_CPM3    0x3U
+#define V_CPM3(x) ((x) << S_CPM3)
+#define G_CPM3(x) (((x) >> S_CPM3) & M_CPM3)
+
+#define S_CPM4    22
+#define M_CPM4    0x3U
+#define V_CPM4(x) ((x) << S_CPM4)
+#define G_CPM4(x) (((x) >> S_CPM4) & M_CPM4)
+
+#define S_CPM5    20
+#define M_CPM5    0x3U
+#define V_CPM5(x) ((x) << S_CPM5)
+#define G_CPM5(x) (((x) >> S_CPM5) & M_CPM5)
+
+#define S_CPM6    18
+#define M_CPM6    0x3U
+#define V_CPM6(x) ((x) << S_CPM6)
+#define G_CPM6(x) (((x) >> S_CPM6) & M_CPM6)
+
+#define S_CPM7    16
+#define M_CPM7    0x3U
+#define V_CPM7(x) ((x) << S_CPM7)
+#define G_CPM7(x) (((x) >> S_CPM7) & M_CPM7)
+
+#define S_OPM0    14
+#define M_OPM0    0x3U
+#define V_OPM0(x) ((x) << S_OPM0)
+#define G_OPM0(x) (((x) >> S_OPM0) & M_OPM0)
+
+#define S_OPM1    12
+#define M_OPM1    0x3U
+#define V_OPM1(x) ((x) << S_OPM1)
+#define G_OPM1(x) (((x) >> S_OPM1) & M_OPM1)
+
+#define S_OPM2    10
+#define M_OPM2    0x3U
+#define V_OPM2(x) ((x) << S_OPM2)
+#define G_OPM2(x) (((x) >> S_OPM2) & M_OPM2)
+
+#define S_OPM3    8
+#define M_OPM3    0x3U
+#define V_OPM3(x) ((x) << S_OPM3)
+#define G_OPM3(x) (((x) >> S_OPM3) & M_OPM3)
+
+#define S_OPM4    6
+#define M_OPM4    0x3U
+#define V_OPM4(x) ((x) << S_OPM4)
+#define G_OPM4(x) (((x) >> S_OPM4) & M_OPM4)
+
+#define S_OPM5    4
+#define M_OPM5    0x3U
+#define V_OPM5(x) ((x) << S_OPM5)
+#define G_OPM5(x) (((x) >> S_OPM5) & M_OPM5)
+
+#define S_OPM6    2
+#define M_OPM6    0x3U
+#define V_OPM6(x) ((x) << S_OPM6)
+#define G_OPM6(x) (((x) >> S_OPM6) & M_OPM6)
+
+#define S_OPM7    0
+#define M_OPM7    0x3U
+#define V_OPM7(x) ((x) << S_OPM7)
+#define G_OPM7(x) (((x) >> S_OPM7) & M_OPM7)
+
+#define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_1 0x59d0
+#define A_PCIE_PERR_GROUP 0x59d0
+
+#define S_MST_DATAPATHPERR    25
+#define V_MST_DATAPATHPERR(x) ((x) << S_MST_DATAPATHPERR)
+#define F_MST_DATAPATHPERR    V_MST_DATAPATHPERR(1U)
+
+#define S_MST_RSPRDQPERR    24
+#define V_MST_RSPRDQPERR(x) ((x) << S_MST_RSPRDQPERR)
+#define F_MST_RSPRDQPERR    V_MST_RSPRDQPERR(1U)
+
+#define S_IP_RXPERR    23
+#define V_IP_RXPERR(x) ((x) << S_IP_RXPERR)
+#define F_IP_RXPERR    V_IP_RXPERR(1U)
+
+#define S_IP_BACKTXPERR    22
+#define V_IP_BACKTXPERR(x) ((x) << S_IP_BACKTXPERR)
+#define F_IP_BACKTXPERR    V_IP_BACKTXPERR(1U)
+
+#define S_IP_FRONTTXPERR    21
+#define V_IP_FRONTTXPERR(x) ((x) << S_IP_FRONTTXPERR)
+#define F_IP_FRONTTXPERR    V_IP_FRONTTXPERR(1U)
+
+#define S_TRGT1_FIDLKUPHDRPERR    20
+#define V_TRGT1_FIDLKUPHDRPERR(x) ((x) << S_TRGT1_FIDLKUPHDRPERR)
+#define F_TRGT1_FIDLKUPHDRPERR    V_TRGT1_FIDLKUPHDRPERR(1U)
+
+#define S_TRGT1_ALINDDATAPERR    19
+#define V_TRGT1_ALINDDATAPERR(x) ((x) << S_TRGT1_ALINDDATAPERR)
+#define F_TRGT1_ALINDDATAPERR    V_TRGT1_ALINDDATAPERR(1U)
+
+#define S_TRGT1_UNALINDATAPERR    18
+#define V_TRGT1_UNALINDATAPERR(x) ((x) << S_TRGT1_UNALINDATAPERR)
+#define F_TRGT1_UNALINDATAPERR    V_TRGT1_UNALINDATAPERR(1U)
+
+#define S_TRGT1_REQDATAPERR    17
+#define V_TRGT1_REQDATAPERR(x) ((x) << S_TRGT1_REQDATAPERR)
+#define F_TRGT1_REQDATAPERR    V_TRGT1_REQDATAPERR(1U)
+
+#define S_TRGT1_REQHDRPERR    16
+#define V_TRGT1_REQHDRPERR(x) ((x) << S_TRGT1_REQHDRPERR)
+#define F_TRGT1_REQHDRPERR    V_TRGT1_REQHDRPERR(1U)
+
+#define S_IPRXDATA_VC1PERR    15
+#define V_IPRXDATA_VC1PERR(x) ((x) << S_IPRXDATA_VC1PERR)
+#define F_IPRXDATA_VC1PERR    V_IPRXDATA_VC1PERR(1U)
+
+#define S_IPRXDATA_VC0PERR    14
+#define V_IPRXDATA_VC0PERR(x) ((x) << S_IPRXDATA_VC0PERR)
+#define F_IPRXDATA_VC0PERR    V_IPRXDATA_VC0PERR(1U)
+
+#define S_IPRXHDR_VC1PERR    13
+#define V_IPRXHDR_VC1PERR(x) ((x) << S_IPRXHDR_VC1PERR)
+#define F_IPRXHDR_VC1PERR    V_IPRXHDR_VC1PERR(1U)
+
+#define S_IPRXHDR_VC0PERR    12
+#define V_IPRXHDR_VC0PERR(x) ((x) << S_IPRXHDR_VC0PERR)
+#define F_IPRXHDR_VC0PERR    V_IPRXHDR_VC0PERR(1U)
+
+#define S_MA_RSPDATAPERR    11
+#define V_MA_RSPDATAPERR(x) ((x) << S_MA_RSPDATAPERR)
+#define F_MA_RSPDATAPERR    V_MA_RSPDATAPERR(1U)
+
+#define S_MA_CPLTAGQPERR    10
+#define V_MA_CPLTAGQPERR(x) ((x) << S_MA_CPLTAGQPERR)
+#define F_MA_CPLTAGQPERR    V_MA_CPLTAGQPERR(1U)
+
+#define S_MA_REQTAGQPERR    9
+#define V_MA_REQTAGQPERR(x) ((x) << S_MA_REQTAGQPERR)
+#define F_MA_REQTAGQPERR    V_MA_REQTAGQPERR(1U)
+
+#define S_PIOREQ_BAR2CTLPERR    8
+#define V_PIOREQ_BAR2CTLPERR(x) ((x) << S_PIOREQ_BAR2CTLPERR)
+#define F_PIOREQ_BAR2CTLPERR    V_PIOREQ_BAR2CTLPERR(1U)
+
+#define S_PIOREQ_MEMCTLPERR    7
+#define V_PIOREQ_MEMCTLPERR(x) ((x) << S_PIOREQ_MEMCTLPERR)
+#define F_PIOREQ_MEMCTLPERR    V_PIOREQ_MEMCTLPERR(1U)
+
+#define S_PIOREQ_PLMCTLPERR    6
+#define V_PIOREQ_PLMCTLPERR(x) ((x) << S_PIOREQ_PLMCTLPERR)
+#define F_PIOREQ_PLMCTLPERR    V_PIOREQ_PLMCTLPERR(1U)
+
+#define S_PIOREQ_BAR2DATAPERR    5
+#define V_PIOREQ_BAR2DATAPERR(x) ((x) << S_PIOREQ_BAR2DATAPERR)
+#define F_PIOREQ_BAR2DATAPERR    V_PIOREQ_BAR2DATAPERR(1U)
+
+#define S_PIOREQ_MEMDATAPERR    4
+#define V_PIOREQ_MEMDATAPERR(x) ((x) << S_PIOREQ_MEMDATAPERR)
+#define F_PIOREQ_MEMDATAPERR    V_PIOREQ_MEMDATAPERR(1U)
+
+#define S_PIOREQ_PLMDATAPERR    3
+#define V_PIOREQ_PLMDATAPERR(x) ((x) << S_PIOREQ_PLMDATAPERR)
+#define F_PIOREQ_PLMDATAPERR    V_PIOREQ_PLMDATAPERR(1U)
+
+#define S_PIOCPL_CTLPERR    2
+#define V_PIOCPL_CTLPERR(x) ((x) << S_PIOCPL_CTLPERR)
+#define F_PIOCPL_CTLPERR    V_PIOCPL_CTLPERR(1U)
+
+#define S_PIOCPL_DATAPERR    1
+#define V_PIOCPL_DATAPERR(x) ((x) << S_PIOCPL_DATAPERR)
+#define F_PIOCPL_DATAPERR    V_PIOCPL_DATAPERR(1U)
+
+#define S_PIOCPL_PLMRSPPERR    0
+#define V_PIOCPL_PLMRSPPERR(x) ((x) << S_PIOCPL_PLMRSPPERR)
+#define F_PIOCPL_PLMRSPPERR    V_PIOCPL_PLMRSPPERR(1U)
+
+#define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_2 0x59d4
+#define A_PCIE_RSP_ERR_INT_LOG_EN 0x59d4
+
+#define S_CPLSTATUSINTEN    12
+#define V_CPLSTATUSINTEN(x) ((x) << S_CPLSTATUSINTEN)
+#define F_CPLSTATUSINTEN    V_CPLSTATUSINTEN(1U)
+
+#define S_REQTIMEOUTINTEN    11
+#define V_REQTIMEOUTINTEN(x) ((x) << S_REQTIMEOUTINTEN)
+#define F_REQTIMEOUTINTEN    V_REQTIMEOUTINTEN(1U)
+
+#define S_DISABLEDINTEN    10
+#define V_DISABLEDINTEN(x) ((x) << S_DISABLEDINTEN)
+#define F_DISABLEDINTEN    V_DISABLEDINTEN(1U)
+
+#define S_RSPDROPFLRINTEN    9
+#define V_RSPDROPFLRINTEN(x) ((x) << S_RSPDROPFLRINTEN)
+#define F_RSPDROPFLRINTEN    V_RSPDROPFLRINTEN(1U)
+
+#define S_REQUNDERFLRINTEN    8
+#define V_REQUNDERFLRINTEN(x) ((x) << S_REQUNDERFLRINTEN)
+#define F_REQUNDERFLRINTEN    V_REQUNDERFLRINTEN(1U)
+
+#define S_CPLSTATUSLOGEN    4
+#define V_CPLSTATUSLOGEN(x) ((x) << S_CPLSTATUSLOGEN)
+#define F_CPLSTATUSLOGEN    V_CPLSTATUSLOGEN(1U)
+
+#define S_TIMEOUTLOGEN    3
+#define V_TIMEOUTLOGEN(x) ((x) << S_TIMEOUTLOGEN)
+#define F_TIMEOUTLOGEN    V_TIMEOUTLOGEN(1U)
+
+#define S_DISABLEDLOGEN    2
+#define V_DISABLEDLOGEN(x) ((x) << S_DISABLEDLOGEN)
+#define F_DISABLEDLOGEN    V_DISABLEDLOGEN(1U)
+
+#define S_RSPDROPFLRLOGEN    1
+#define V_RSPDROPFLRLOGEN(x) ((x) << S_RSPDROPFLRLOGEN)
+#define F_RSPDROPFLRLOGEN    V_RSPDROPFLRLOGEN(1U)
+
+#define S_REQUNDERFLRLOGEN    0
+#define V_REQUNDERFLRLOGEN(x) ((x) << S_REQUNDERFLRLOGEN)
+#define F_REQUNDERFLRLOGEN    V_REQUNDERFLRLOGEN(1U)
+
+#define A_PCIE_RSP_ERR_LOG1 0x59d8
+
+#define S_REQTAG    25
+#define M_REQTAG    0x7fU
+#define V_REQTAG(x) ((x) << S_REQTAG)
+#define G_REQTAG(x) (((x) >> S_REQTAG) & M_REQTAG)
+
+#define S_CID    22
+#define M_CID    0x7U
+#define V_CID(x) ((x) << S_CID)
+#define G_CID(x) (((x) >> S_CID) & M_CID)
+
+#define S_CHNUM    19
+#define M_CHNUM    0x7U
+#define V_CHNUM(x) ((x) << S_CHNUM)
+#define G_CHNUM(x) (((x) >> S_CHNUM) & M_CHNUM)
+
+#define S_BYTELEN    6
+#define M_BYTELEN    0x1fffU
+#define V_BYTELEN(x) ((x) << S_BYTELEN)
+#define G_BYTELEN(x) (((x) >> S_BYTELEN) & M_BYTELEN)
+
+#define S_REASON    3
+#define M_REASON    0x7U
+#define V_REASON(x) ((x) << S_REASON)
+#define G_REASON(x) (((x) >> S_REASON) & M_REASON)
+
+#define S_CPLSTATUS    0
+#define M_CPLSTATUS    0x7U
+#define V_CPLSTATUS(x) ((x) << S_CPLSTATUS)
+#define G_CPLSTATUS(x) (((x) >> S_CPLSTATUS) & M_CPLSTATUS)
+
+#define A_PCIE_RSP_ERR_LOG2 0x59dc
+
+#define S_LOGVALID    31
+#define V_LOGVALID(x) ((x) << S_LOGVALID)
+#define F_LOGVALID    V_LOGVALID(1U)
+
+#define S_ADDR10B    8
+#define M_ADDR10B    0x3ffU
+#define V_ADDR10B(x) ((x) << S_ADDR10B)
+#define G_ADDR10B(x) (((x) >> S_ADDR10B) & M_ADDR10B)
+
+#define S_REQVFID    0
+#define M_REQVFID    0xffU
+#define V_REQVFID(x) ((x) << S_REQVFID)
+#define G_REQVFID(x) (((x) >> S_REQVFID) & M_REQVFID)
+
+#define A_PCIE_CHANGESET 0x59fc
+#define A_PCIE_REVISION 0x5a00
+#define A_PCIE_PDEBUG_INDEX 0x5a04
+
+#define S_PDEBUGSELH    16
+#define M_PDEBUGSELH    0x3fU
+#define V_PDEBUGSELH(x) ((x) << S_PDEBUGSELH)
+#define G_PDEBUGSELH(x) (((x) >> S_PDEBUGSELH) & M_PDEBUGSELH)
+
+#define S_PDEBUGSELL    0
+#define M_PDEBUGSELL    0x3fU
+#define V_PDEBUGSELL(x) ((x) << S_PDEBUGSELL)
+#define G_PDEBUGSELL(x) (((x) >> S_PDEBUGSELL) & M_PDEBUGSELL)
+
+#define A_PCIE_PDEBUG_DATA_HIGH 0x5a08
+#define A_PCIE_PDEBUG_DATA_LOW 0x5a0c
+#define A_PCIE_CDEBUG_INDEX 0x5a10
+
+#define S_CDEBUGSELH    16
+#define M_CDEBUGSELH    0xffU
+#define V_CDEBUGSELH(x) ((x) << S_CDEBUGSELH)
+#define G_CDEBUGSELH(x) (((x) >> S_CDEBUGSELH) & M_CDEBUGSELH)
+
+#define S_CDEBUGSELL    0
+#define M_CDEBUGSELL    0xffU
+#define V_CDEBUGSELL(x) ((x) << S_CDEBUGSELL)
+#define G_CDEBUGSELL(x) (((x) >> S_CDEBUGSELL) & M_CDEBUGSELL)
+
+#define A_PCIE_CDEBUG_DATA_HIGH 0x5a14
+#define A_PCIE_CDEBUG_DATA_LOW 0x5a18
+#define A_PCIE_DMAW_SOP_CNT 0x5a1c
+
+#define S_CH3    24
+#define M_CH3    0xffU
+#define V_CH3(x) ((x) << S_CH3)
+#define G_CH3(x) (((x) >> S_CH3) & M_CH3)
+
+#define S_CH2    16
+#define M_CH2    0xffU
+#define V_CH2(x) ((x) << S_CH2)
+#define G_CH2(x) (((x) >> S_CH2) & M_CH2)
+
+#define S_CH1    8
+#define M_CH1    0xffU
+#define V_CH1(x) ((x) << S_CH1)
+#define G_CH1(x) (((x) >> S_CH1) & M_CH1)
+
+#define S_CH0    0
+#define M_CH0    0xffU
+#define V_CH0(x) ((x) << S_CH0)
+#define G_CH0(x) (((x) >> S_CH0) & M_CH0)
+
+#define A_PCIE_DMAW_EOP_CNT 0x5a20
+#define A_PCIE_DMAR_REQ_CNT 0x5a24
+#define A_PCIE_DMAR_RSP_SOP_CNT 0x5a28
+#define A_PCIE_DMAR_RSP_EOP_CNT 0x5a2c
+#define A_PCIE_DMAR_RSP_ERR_CNT 0x5a30
+#define A_PCIE_DMAI_CNT 0x5a34
+#define A_PCIE_CMDW_CNT 0x5a38
+
+#define S_CH1_EOP    24
+#define M_CH1_EOP    0xffU
+#define V_CH1_EOP(x) ((x) << S_CH1_EOP)
+#define G_CH1_EOP(x) (((x) >> S_CH1_EOP) & M_CH1_EOP)
+
+#define S_CH1_SOP    16
+#define M_CH1_SOP    0xffU
+#define V_CH1_SOP(x) ((x) << S_CH1_SOP)
+#define G_CH1_SOP(x) (((x) >> S_CH1_SOP) & M_CH1_SOP)
+
+#define S_CH0_EOP    8
+#define M_CH0_EOP    0xffU
+#define V_CH0_EOP(x) ((x) << S_CH0_EOP)
+#define G_CH0_EOP(x) (((x) >> S_CH0_EOP) & M_CH0_EOP)
+
+#define S_CH0_SOP    0
+#define M_CH0_SOP    0xffU
+#define V_CH0_SOP(x) ((x) << S_CH0_SOP)
+#define G_CH0_SOP(x) (((x) >> S_CH0_SOP) & M_CH0_SOP)
+
+#define A_PCIE_CMDR_REQ_CNT 0x5a3c
+#define A_PCIE_CMDR_RSP_CNT 0x5a40
+#define A_PCIE_CMDR_RSP_ERR_CNT 0x5a44
+#define A_PCIE_HMA_REQ_CNT 0x5a48
+
+#define S_CH0_READ    16
+#define M_CH0_READ    0xffU
+#define V_CH0_READ(x) ((x) << S_CH0_READ)
+#define G_CH0_READ(x) (((x) >> S_CH0_READ) & M_CH0_READ)
+
+#define S_CH0_WEOP    8
+#define M_CH0_WEOP    0xffU
+#define V_CH0_WEOP(x) ((x) << S_CH0_WEOP)
+#define G_CH0_WEOP(x) (((x) >> S_CH0_WEOP) & M_CH0_WEOP)
+
+#define S_CH0_WSOP    0
+#define M_CH0_WSOP    0xffU
+#define V_CH0_WSOP(x) ((x) << S_CH0_WSOP)
+#define G_CH0_WSOP(x) (((x) >> S_CH0_WSOP) & M_CH0_WSOP)
+
+#define A_PCIE_HMA_RSP_CNT 0x5a4c
+#define A_PCIE_DMA10_RSP_FREE 0x5a50
+
+#define S_CH1_RSP_FREE    16
+#define M_CH1_RSP_FREE    0xfffU
+#define V_CH1_RSP_FREE(x) ((x) << S_CH1_RSP_FREE)
+#define G_CH1_RSP_FREE(x) (((x) >> S_CH1_RSP_FREE) & M_CH1_RSP_FREE)
+
+#define S_CH0_RSP_FREE    0
+#define M_CH0_RSP_FREE    0xfffU
+#define V_CH0_RSP_FREE(x) ((x) << S_CH0_RSP_FREE)
+#define G_CH0_RSP_FREE(x) (((x) >> S_CH0_RSP_FREE) & M_CH0_RSP_FREE)
+
+#define A_PCIE_DMA32_RSP_FREE 0x5a54
+
+#define S_CH3_RSP_FREE    16
+#define M_CH3_RSP_FREE    0xfffU
+#define V_CH3_RSP_FREE(x) ((x) << S_CH3_RSP_FREE)
+#define G_CH3_RSP_FREE(x) (((x) >> S_CH3_RSP_FREE) & M_CH3_RSP_FREE)
+
+#define S_CH2_RSP_FREE    0
+#define M_CH2_RSP_FREE    0xfffU
+#define V_CH2_RSP_FREE(x) ((x) << S_CH2_RSP_FREE)
+#define G_CH2_RSP_FREE(x) (((x) >> S_CH2_RSP_FREE) & M_CH2_RSP_FREE)
+
+#define A_PCIE_CMD_RSP_FREE 0x5a58
+
+#define S_CMD_CH1_RSP_FREE    16
+#define M_CMD_CH1_RSP_FREE    0x7fU
+#define V_CMD_CH1_RSP_FREE(x) ((x) << S_CMD_CH1_RSP_FREE)
+#define G_CMD_CH1_RSP_FREE(x) (((x) >> S_CMD_CH1_RSP_FREE) & M_CMD_CH1_RSP_FREE)
+
+#define S_CMD_CH0_RSP_FREE    0
+#define M_CMD_CH0_RSP_FREE    0x7fU
+#define V_CMD_CH0_RSP_FREE(x) ((x) << S_CMD_CH0_RSP_FREE)
+#define G_CMD_CH0_RSP_FREE(x) (((x) >> S_CMD_CH0_RSP_FREE) & M_CMD_CH0_RSP_FREE)
+
+#define A_PCIE_HMA_RSP_FREE 0x5a5c
+#define A_PCIE_BUS_MST_STAT_0 0x5a60
+#define A_PCIE_BUS_MST_STAT_1 0x5a64
+#define A_PCIE_BUS_MST_STAT_2 0x5a68
+#define A_PCIE_BUS_MST_STAT_3 0x5a6c
+#define A_PCIE_BUS_MST_STAT_4 0x5a70
+
+#define S_BUSMST_135_128    0
+#define M_BUSMST_135_128    0xffU
+#define V_BUSMST_135_128(x) ((x) << S_BUSMST_135_128)
+#define G_BUSMST_135_128(x) (((x) >> S_BUSMST_135_128) & M_BUSMST_135_128)
+
+#define A_PCIE_BUS_MST_STAT_5 0x5a74
+#define A_PCIE_BUS_MST_STAT_6 0x5a78
+#define A_PCIE_BUS_MST_STAT_7 0x5a7c
+#define A_PCIE_RSP_ERR_STAT_0 0x5a80
+#define A_PCIE_RSP_ERR_STAT_1 0x5a84
+#define A_PCIE_RSP_ERR_STAT_2 0x5a88
+#define A_PCIE_RSP_ERR_STAT_3 0x5a8c
+#define A_PCIE_RSP_ERR_STAT_4 0x5a90
+
+#define S_RSPERR_135_128    0
+#define M_RSPERR_135_128    0xffU
+#define V_RSPERR_135_128(x) ((x) << S_RSPERR_135_128)
+#define G_RSPERR_135_128(x) (((x) >> S_RSPERR_135_128) & M_RSPERR_135_128)
+
+#define A_PCIE_RSP_ERR_STAT_5 0x5a94
+#define A_PCIE_DBI_TIMEOUT_CTL 0x5a94
+
+#define S_DBI_TIMER    0
+#define M_DBI_TIMER    0xffffU
+#define V_DBI_TIMER(x) ((x) << S_DBI_TIMER)
+#define G_DBI_TIMER(x) (((x) >> S_DBI_TIMER) & M_DBI_TIMER)
+
+#define A_PCIE_RSP_ERR_STAT_6 0x5a98
+#define A_PCIE_DBI_TIMEOUT_STATUS0 0x5a98
+#define A_PCIE_RSP_ERR_STAT_7 0x5a9c
+#define A_PCIE_DBI_TIMEOUT_STATUS1 0x5a9c
+
+#define S_SOURCE    16
+#define M_SOURCE    0x3U
+#define V_SOURCE(x) ((x) << S_SOURCE)
+#define G_SOURCE(x) (((x) >> S_SOURCE) & M_SOURCE)
+
+#define S_DBI_WRITE    12
+#define M_DBI_WRITE    0xfU
+#define V_DBI_WRITE(x) ((x) << S_DBI_WRITE)
+#define G_DBI_WRITE(x) (((x) >> S_DBI_WRITE) & M_DBI_WRITE)
+
+#define S_DBI_CS2    11
+#define V_DBI_CS2(x) ((x) << S_DBI_CS2)
+#define F_DBI_CS2    V_DBI_CS2(1U)
+
+#define S_DBI_PF    8
+#define M_DBI_PF    0x7U
+#define V_DBI_PF(x) ((x) << S_DBI_PF)
+#define G_DBI_PF(x) (((x) >> S_DBI_PF) & M_DBI_PF)
+
+#define S_PL_TOVFVLD    7
+#define V_PL_TOVFVLD(x) ((x) << S_PL_TOVFVLD)
+#define F_PL_TOVFVLD    V_PL_TOVFVLD(1U)
+
+#define S_PL_TOVF    0
+#define M_PL_TOVF    0x7fU
+#define V_PL_TOVF(x) ((x) << S_PL_TOVF)
+#define G_PL_TOVF(x) (((x) >> S_PL_TOVF) & M_PL_TOVF)
+
+#define A_PCIE_MSI_EN_0 0x5aa0
+#define A_PCIE_MSI_EN_1 0x5aa4
+#define A_PCIE_MSI_EN_2 0x5aa8
+#define A_PCIE_MSI_EN_3 0x5aac
+#define A_PCIE_MSI_EN_4 0x5ab0
+#define A_PCIE_MSI_EN_5 0x5ab4
+#define A_PCIE_MSI_EN_6 0x5ab8
+#define A_PCIE_MSI_EN_7 0x5abc
+#define A_PCIE_MSIX_EN_0 0x5ac0
+#define A_PCIE_MSIX_EN_1 0x5ac4
+#define A_PCIE_MSIX_EN_2 0x5ac8
+#define A_PCIE_MSIX_EN_3 0x5acc
+#define A_PCIE_MSIX_EN_4 0x5ad0
+#define A_PCIE_MSIX_EN_5 0x5ad4
+#define A_PCIE_MSIX_EN_6 0x5ad8
+#define A_PCIE_MSIX_EN_7 0x5adc
+#define A_PCIE_DMA_BUF_CTL 0x5ae0
+
+#define S_BUFRDCNT    18
+#define M_BUFRDCNT    0x3fffU
+#define V_BUFRDCNT(x) ((x) << S_BUFRDCNT)
+#define G_BUFRDCNT(x) (((x) >> S_BUFRDCNT) & M_BUFRDCNT)
+
+#define S_BUFWRCNT    9
+#define M_BUFWRCNT    0x1ffU
+#define V_BUFWRCNT(x) ((x) << S_BUFWRCNT)
+#define G_BUFWRCNT(x) (((x) >> S_BUFWRCNT) & M_BUFWRCNT)
+
+#define S_MAXBUFWRREQ    0
+#define M_MAXBUFWRREQ    0x1ffU
+#define V_MAXBUFWRREQ(x) ((x) << S_MAXBUFWRREQ)
+#define G_MAXBUFWRREQ(x) (((x) >> S_MAXBUFWRREQ) & M_MAXBUFWRREQ)
+
+#define A_PCIE_PB_CTL 0x5b94
+
+#define S_PB_SEL    16
+#define M_PB_SEL    0xffU
+#define V_PB_SEL(x) ((x) << S_PB_SEL)
+#define G_PB_SEL(x) (((x) >> S_PB_SEL) & M_PB_SEL)
+
+#define S_PB_SELREG    8
+#define M_PB_SELREG    0xffU
+#define V_PB_SELREG(x) ((x) << S_PB_SELREG)
+#define G_PB_SELREG(x) (((x) >> S_PB_SELREG) & M_PB_SELREG)
+
+#define S_PB_FUNC    0
+#define M_PB_FUNC    0x7U
+#define V_PB_FUNC(x) ((x) << S_PB_FUNC)
+#define G_PB_FUNC(x) (((x) >> S_PB_FUNC) & M_PB_FUNC)
+
+#define A_PCIE_PB_DATA 0x5b98
+#define A_PCIE_CUR_LINK 0x5b9c
+
+#define S_CFGINITCOEFFDONESEEN    22
+#define V_CFGINITCOEFFDONESEEN(x) ((x) << S_CFGINITCOEFFDONESEEN)
+#define F_CFGINITCOEFFDONESEEN    V_CFGINITCOEFFDONESEEN(1U)
+
+#define S_CFGINITCOEFFDONE    21
+#define V_CFGINITCOEFFDONE(x) ((x) << S_CFGINITCOEFFDONE)
+#define F_CFGINITCOEFFDONE    V_CFGINITCOEFFDONE(1U)
+
+#define S_XMLH_LINK_UP    20
+#define V_XMLH_LINK_UP(x) ((x) << S_XMLH_LINK_UP)
+#define F_XMLH_LINK_UP    V_XMLH_LINK_UP(1U)
+
+#define S_PM_LINKST_IN_L0S    19
+#define V_PM_LINKST_IN_L0S(x) ((x) << S_PM_LINKST_IN_L0S)
+#define F_PM_LINKST_IN_L0S    V_PM_LINKST_IN_L0S(1U)
+
+#define S_PM_LINKST_IN_L1    18
+#define V_PM_LINKST_IN_L1(x) ((x) << S_PM_LINKST_IN_L1)
+#define F_PM_LINKST_IN_L1    V_PM_LINKST_IN_L1(1U)
+
+#define S_PM_LINKST_IN_L2    17
+#define V_PM_LINKST_IN_L2(x) ((x) << S_PM_LINKST_IN_L2)
+#define F_PM_LINKST_IN_L2    V_PM_LINKST_IN_L2(1U)
+
+#define S_PM_LINKST_L2_EXIT    16
+#define V_PM_LINKST_L2_EXIT(x) ((x) << S_PM_LINKST_L2_EXIT)
+#define F_PM_LINKST_L2_EXIT    V_PM_LINKST_L2_EXIT(1U)
+
+#define S_XMLH_IN_RL0S    15
+#define V_XMLH_IN_RL0S(x) ((x) << S_XMLH_IN_RL0S)
+#define F_XMLH_IN_RL0S    V_XMLH_IN_RL0S(1U)
+
+#define S_XMLH_LTSSM_STATE_RCVRY_EQ    14
+#define V_XMLH_LTSSM_STATE_RCVRY_EQ(x) ((x) << S_XMLH_LTSSM_STATE_RCVRY_EQ)
+#define F_XMLH_LTSSM_STATE_RCVRY_EQ    V_XMLH_LTSSM_STATE_RCVRY_EQ(1U)
+
+#define S_NEGOTIATEDWIDTH    8
+#define M_NEGOTIATEDWIDTH    0x3fU
+#define V_NEGOTIATEDWIDTH(x) ((x) << S_NEGOTIATEDWIDTH)
+#define G_NEGOTIATEDWIDTH(x) (((x) >> S_NEGOTIATEDWIDTH) & M_NEGOTIATEDWIDTH)
+
+#define S_ACTIVELANES    0
+#define M_ACTIVELANES    0xffU
+#define V_ACTIVELANES(x) ((x) << S_ACTIVELANES)
+#define G_ACTIVELANES(x) (((x) >> S_ACTIVELANES) & M_ACTIVELANES)
+
+#define A_PCIE_PHY_REQRXPWR 0x5ba0
+
+#define S_LNH_RXSTATEDONE    31
+#define V_LNH_RXSTATEDONE(x) ((x) << S_LNH_RXSTATEDONE)
+#define F_LNH_RXSTATEDONE    V_LNH_RXSTATEDONE(1U)
+
+#define S_LNH_RXSTATEREQ    30
+#define V_LNH_RXSTATEREQ(x) ((x) << S_LNH_RXSTATEREQ)
+#define F_LNH_RXSTATEREQ    V_LNH_RXSTATEREQ(1U)
+
+#define S_LNH_RXPWRSTATE    28
+#define M_LNH_RXPWRSTATE    0x3U
+#define V_LNH_RXPWRSTATE(x) ((x) << S_LNH_RXPWRSTATE)
+#define G_LNH_RXPWRSTATE(x) (((x) >> S_LNH_RXPWRSTATE) & M_LNH_RXPWRSTATE)
+
+#define S_LNG_RXSTATEDONE    27
+#define V_LNG_RXSTATEDONE(x) ((x) << S_LNG_RXSTATEDONE)
+#define F_LNG_RXSTATEDONE    V_LNG_RXSTATEDONE(1U)
+
+#define S_LNG_RXSTATEREQ    26
+#define V_LNG_RXSTATEREQ(x) ((x) << S_LNG_RXSTATEREQ)
+#define F_LNG_RXSTATEREQ    V_LNG_RXSTATEREQ(1U)
+
+#define S_LNG_RXPWRSTATE    24
+#define M_LNG_RXPWRSTATE    0x3U
+#define V_LNG_RXPWRSTATE(x) ((x) << S_LNG_RXPWRSTATE)
+#define G_LNG_RXPWRSTATE(x) (((x) >> S_LNG_RXPWRSTATE) & M_LNG_RXPWRSTATE)
+
+#define S_LNF_RXSTATEDONE    23
+#define V_LNF_RXSTATEDONE(x) ((x) << S_LNF_RXSTATEDONE)
+#define F_LNF_RXSTATEDONE    V_LNF_RXSTATEDONE(1U)
+
+#define S_LNF_RXSTATEREQ    22
+#define V_LNF_RXSTATEREQ(x) ((x) << S_LNF_RXSTATEREQ)
+#define F_LNF_RXSTATEREQ    V_LNF_RXSTATEREQ(1U)
+
+#define S_LNF_RXPWRSTATE    20
+#define M_LNF_RXPWRSTATE    0x3U
+#define V_LNF_RXPWRSTATE(x) ((x) << S_LNF_RXPWRSTATE)
+#define G_LNF_RXPWRSTATE(x) (((x) >> S_LNF_RXPWRSTATE) & M_LNF_RXPWRSTATE)
+
+#define S_LNE_RXSTATEDONE    19
+#define V_LNE_RXSTATEDONE(x) ((x) << S_LNE_RXSTATEDONE)
+#define F_LNE_RXSTATEDONE    V_LNE_RXSTATEDONE(1U)
+
+#define S_LNE_RXSTATEREQ    18
+#define V_LNE_RXSTATEREQ(x) ((x) << S_LNE_RXSTATEREQ)
+#define F_LNE_RXSTATEREQ    V_LNE_RXSTATEREQ(1U)
+
+#define S_LNE_RXPWRSTATE    16
+#define M_LNE_RXPWRSTATE    0x3U
+#define V_LNE_RXPWRSTATE(x) ((x) << S_LNE_RXPWRSTATE)
+#define G_LNE_RXPWRSTATE(x) (((x) >> S_LNE_RXPWRSTATE) & M_LNE_RXPWRSTATE)
+
+#define S_LND_RXSTATEDONE    15
+#define V_LND_RXSTATEDONE(x) ((x) << S_LND_RXSTATEDONE)
+#define F_LND_RXSTATEDONE    V_LND_RXSTATEDONE(1U)
+
+#define S_LND_RXSTATEREQ    14
+#define V_LND_RXSTATEREQ(x) ((x) << S_LND_RXSTATEREQ)
+#define F_LND_RXSTATEREQ    V_LND_RXSTATEREQ(1U)
+
+#define S_LND_RXPWRSTATE    12
+#define M_LND_RXPWRSTATE    0x3U
+#define V_LND_RXPWRSTATE(x) ((x) << S_LND_RXPWRSTATE)
+#define G_LND_RXPWRSTATE(x) (((x) >> S_LND_RXPWRSTATE) & M_LND_RXPWRSTATE)
+
+#define S_LNC_RXSTATEDONE    11
+#define V_LNC_RXSTATEDONE(x) ((x) << S_LNC_RXSTATEDONE)
+#define F_LNC_RXSTATEDONE    V_LNC_RXSTATEDONE(1U)
+
+#define S_LNC_RXSTATEREQ    10
+#define V_LNC_RXSTATEREQ(x) ((x) << S_LNC_RXSTATEREQ)
+#define F_LNC_RXSTATEREQ    V_LNC_RXSTATEREQ(1U)
+
+#define S_LNC_RXPWRSTATE    8
+#define M_LNC_RXPWRSTATE    0x3U
+#define V_LNC_RXPWRSTATE(x) ((x) << S_LNC_RXPWRSTATE)
+#define G_LNC_RXPWRSTATE(x) (((x) >> S_LNC_RXPWRSTATE) & M_LNC_RXPWRSTATE)
+
+#define S_LNB_RXSTATEDONE    7
+#define V_LNB_RXSTATEDONE(x) ((x) << S_LNB_RXSTATEDONE)
+#define F_LNB_RXSTATEDONE    V_LNB_RXSTATEDONE(1U)
+
+#define S_LNB_RXSTATEREQ    6
+#define V_LNB_RXSTATEREQ(x) ((x) << S_LNB_RXSTATEREQ)
+#define F_LNB_RXSTATEREQ    V_LNB_RXSTATEREQ(1U)
+
+#define S_LNB_RXPWRSTATE    4
+#define M_LNB_RXPWRSTATE    0x3U
+#define V_LNB_RXPWRSTATE(x) ((x) << S_LNB_RXPWRSTATE)
+#define G_LNB_RXPWRSTATE(x) (((x) >> S_LNB_RXPWRSTATE) & M_LNB_RXPWRSTATE)
+
+#define S_LNA_RXSTATEDONE    3
+#define V_LNA_RXSTATEDONE(x) ((x) << S_LNA_RXSTATEDONE)
+#define F_LNA_RXSTATEDONE    V_LNA_RXSTATEDONE(1U)
+
+#define S_LNA_RXSTATEREQ    2
+#define V_LNA_RXSTATEREQ(x) ((x) << S_LNA_RXSTATEREQ)
+#define F_LNA_RXSTATEREQ    V_LNA_RXSTATEREQ(1U)
+
+#define S_LNA_RXPWRSTATE    0
+#define M_LNA_RXPWRSTATE    0x3U
+#define V_LNA_RXPWRSTATE(x) ((x) << S_LNA_RXPWRSTATE)
+#define G_LNA_RXPWRSTATE(x) (((x) >> S_LNA_RXPWRSTATE) & M_LNA_RXPWRSTATE)
+
+#define A_PCIE_PHY_CURRXPWR 0x5ba4
+#define A_PCIE_PHY_GEN3_AE0 0x5ba8
+
+#define S_LND_STAT    28
+#define M_LND_STAT    0x7U
+#define V_LND_STAT(x) ((x) << S_LND_STAT)
+#define G_LND_STAT(x) (((x) >> S_LND_STAT) & M_LND_STAT)
+
+#define S_LND_CMD    24
+#define M_LND_CMD    0x7U
+#define V_LND_CMD(x) ((x) << S_LND_CMD)
+#define G_LND_CMD(x) (((x) >> S_LND_CMD) & M_LND_CMD)
+
+#define S_LNC_STAT    20
+#define M_LNC_STAT    0x7U
+#define V_LNC_STAT(x) ((x) << S_LNC_STAT)
+#define G_LNC_STAT(x) (((x) >> S_LNC_STAT) & M_LNC_STAT)
+
+#define S_LNC_CMD    16
+#define M_LNC_CMD    0x7U
+#define V_LNC_CMD(x) ((x) << S_LNC_CMD)
+#define G_LNC_CMD(x) (((x) >> S_LNC_CMD) & M_LNC_CMD)
+
+#define S_LNB_STAT    12
+#define M_LNB_STAT    0x7U
+#define V_LNB_STAT(x) ((x) << S_LNB_STAT)
+#define G_LNB_STAT(x) (((x) >> S_LNB_STAT) & M_LNB_STAT)
+
+#define S_LNB_CMD    8
+#define M_LNB_CMD    0x7U
+#define V_LNB_CMD(x) ((x) << S_LNB_CMD)
+#define G_LNB_CMD(x) (((x) >> S_LNB_CMD) & M_LNB_CMD)
+
+#define S_LNA_STAT    4
+#define M_LNA_STAT    0x7U
+#define V_LNA_STAT(x) ((x) << S_LNA_STAT)
+#define G_LNA_STAT(x) (((x) >> S_LNA_STAT) & M_LNA_STAT)
+
+#define S_LNA_CMD    0
+#define M_LNA_CMD    0x7U
+#define V_LNA_CMD(x) ((x) << S_LNA_CMD)
+#define G_LNA_CMD(x) (((x) >> S_LNA_CMD) & M_LNA_CMD)
+
+#define A_PCIE_PHY_GEN3_AE1 0x5bac
+
+#define S_LNH_STAT    28
+#define M_LNH_STAT    0x7U
+#define V_LNH_STAT(x) ((x) << S_LNH_STAT)
+#define G_LNH_STAT(x) (((x) >> S_LNH_STAT) & M_LNH_STAT)
+
+#define S_LNH_CMD    24
+#define M_LNH_CMD    0x7U
+#define V_LNH_CMD(x) ((x) << S_LNH_CMD)
+#define G_LNH_CMD(x) (((x) >> S_LNH_CMD) & M_LNH_CMD)
+
+#define S_LNG_STAT    20
+#define M_LNG_STAT    0x7U
+#define V_LNG_STAT(x) ((x) << S_LNG_STAT)
+#define G_LNG_STAT(x) (((x) >> S_LNG_STAT) & M_LNG_STAT)
+
+#define S_LNG_CMD    16
+#define M_LNG_CMD    0x7U
+#define V_LNG_CMD(x) ((x) << S_LNG_CMD)
+#define G_LNG_CMD(x) (((x) >> S_LNG_CMD) & M_LNG_CMD)
+
+#define S_LNF_STAT    12
+#define M_LNF_STAT    0x7U
+#define V_LNF_STAT(x) ((x) << S_LNF_STAT)
+#define G_LNF_STAT(x) (((x) >> S_LNF_STAT) & M_LNF_STAT)
+
+#define S_LNF_CMD    8
+#define M_LNF_CMD    0x7U
+#define V_LNF_CMD(x) ((x) << S_LNF_CMD)
+#define G_LNF_CMD(x) (((x) >> S_LNF_CMD) & M_LNF_CMD)
+
+#define S_LNE_STAT    4
+#define M_LNE_STAT    0x7U
+#define V_LNE_STAT(x) ((x) << S_LNE_STAT)
+#define G_LNE_STAT(x) (((x) >> S_LNE_STAT) & M_LNE_STAT)
+
+#define S_LNE_CMD    0
+#define M_LNE_CMD    0x7U
+#define V_LNE_CMD(x) ((x) << S_LNE_CMD)
+#define G_LNE_CMD(x) (((x) >> S_LNE_CMD) & M_LNE_CMD)
+
+#define A_PCIE_PHY_FS_LF0 0x5bb0
+
+#define S_LANE1LF    24
+#define M_LANE1LF    0x3fU
+#define V_LANE1LF(x) ((x) << S_LANE1LF)
+#define G_LANE1LF(x) (((x) >> S_LANE1LF) & M_LANE1LF)
+
+#define S_LANE1FS    16
+#define M_LANE1FS    0x3fU
+#define V_LANE1FS(x) ((x) << S_LANE1FS)
+#define G_LANE1FS(x) (((x) >> S_LANE1FS) & M_LANE1FS)
+
+#define S_LANE0LF    8
+#define M_LANE0LF    0x3fU
+#define V_LANE0LF(x) ((x) << S_LANE0LF)
+#define G_LANE0LF(x) (((x) >> S_LANE0LF) & M_LANE0LF)
+
+#define S_LANE0FS    0
+#define M_LANE0FS    0x3fU
+#define V_LANE0FS(x) ((x) << S_LANE0FS)
+#define G_LANE0FS(x) (((x) >> S_LANE0FS) & M_LANE0FS)
+
+#define A_PCIE_PHY_FS_LF1 0x5bb4
+
+#define S_LANE3LF    24
+#define M_LANE3LF    0x3fU
+#define V_LANE3LF(x) ((x) << S_LANE3LF)
+#define G_LANE3LF(x) (((x) >> S_LANE3LF) & M_LANE3LF)
+
+#define S_LANE3FS    16
+#define M_LANE3FS    0x3fU
+#define V_LANE3FS(x) ((x) << S_LANE3FS)
+#define G_LANE3FS(x) (((x) >> S_LANE3FS) & M_LANE3FS)
+
+#define S_LANE2LF    8
+#define M_LANE2LF    0x3fU
+#define V_LANE2LF(x) ((x) << S_LANE2LF)
+#define G_LANE2LF(x) (((x) >> S_LANE2LF) & M_LANE2LF)
+
+#define S_LANE2FS    0
+#define M_LANE2FS    0x3fU
+#define V_LANE2FS(x) ((x) << S_LANE2FS)
+#define G_LANE2FS(x) (((x) >> S_LANE2FS) & M_LANE2FS)
+
+#define A_PCIE_PHY_FS_LF2 0x5bb8
+
+#define S_LANE5LF    24
+#define M_LANE5LF    0x3fU
+#define V_LANE5LF(x) ((x) << S_LANE5LF)
+#define G_LANE5LF(x) (((x) >> S_LANE5LF) & M_LANE5LF)
+
+#define S_LANE5FS    16
+#define M_LANE5FS    0x3fU
+#define V_LANE5FS(x) ((x) << S_LANE5FS)
+#define G_LANE5FS(x) (((x) >> S_LANE5FS) & M_LANE5FS)
+
+#define S_LANE4LF    8
+#define M_LANE4LF    0x3fU
+#define V_LANE4LF(x) ((x) << S_LANE4LF)
+#define G_LANE4LF(x) (((x) >> S_LANE4LF) & M_LANE4LF)
+
+#define S_LANE4FS    0
+#define M_LANE4FS    0x3fU
+#define V_LANE4FS(x) ((x) << S_LANE4FS)
+#define G_LANE4FS(x) (((x) >> S_LANE4FS) & M_LANE4FS)
+
+#define A_PCIE_PHY_FS_LF3 0x5bbc
+
+#define S_LANE7LF    24
+#define M_LANE7LF    0x3fU
+#define V_LANE7LF(x) ((x) << S_LANE7LF)
+#define G_LANE7LF(x) (((x) >> S_LANE7LF) & M_LANE7LF)
+
+#define S_LANE7FS    16
+#define M_LANE7FS    0x3fU
+#define V_LANE7FS(x) ((x) << S_LANE7FS)
+#define G_LANE7FS(x) (((x) >> S_LANE7FS) & M_LANE7FS)
+
+#define S_LANE6LF    8
+#define M_LANE6LF    0x3fU
+#define V_LANE6LF(x) ((x) << S_LANE6LF)
+#define G_LANE6LF(x) (((x) >> S_LANE6LF) & M_LANE6LF)
+
+#define S_LANE6FS    0
+#define M_LANE6FS    0x3fU
+#define V_LANE6FS(x) ((x) << S_LANE6FS)
+#define G_LANE6FS(x) (((x) >> S_LANE6FS) & M_LANE6FS)
+
+#define A_PCIE_PHY_PRESET_REQ 0x5bc0
+
+#define S_COEFFDONE    16
+#define V_COEFFDONE(x) ((x) << S_COEFFDONE)
+#define F_COEFFDONE    V_COEFFDONE(1U)
+
+#define S_COEFFLANE    8
+#define M_COEFFLANE    0x7U
+#define V_COEFFLANE(x) ((x) << S_COEFFLANE)
+#define G_COEFFLANE(x) (((x) >> S_COEFFLANE) & M_COEFFLANE)
+
+#define S_COEFFSTART    0
+#define V_COEFFSTART(x) ((x) << S_COEFFSTART)
+#define F_COEFFSTART    V_COEFFSTART(1U)
+
+#define A_PCIE_PHY_PRESET_COEFF 0x5bc4
+
+#define S_COEFF    0
+#define M_COEFF    0x3ffffU
+#define V_COEFF(x) ((x) << S_COEFF)
+#define G_COEFF(x) (((x) >> S_COEFF) & M_COEFF)
+
+#define A_PCIE_PHY_INDIR_REQ 0x5bf0
+
+#define S_PHYENABLE    31
+#define V_PHYENABLE(x) ((x) << S_PHYENABLE)
+#define F_PHYENABLE    V_PHYENABLE(1U)
+
+#define S_PCIE_PHY_REGADDR    0
+#define M_PCIE_PHY_REGADDR    0xffffU
+#define V_PCIE_PHY_REGADDR(x) ((x) << S_PCIE_PHY_REGADDR)
+#define G_PCIE_PHY_REGADDR(x) (((x) >> S_PCIE_PHY_REGADDR) & M_PCIE_PHY_REGADDR)
+
+#define A_PCIE_PHY_INDIR_DATA 0x5bf4
+#define A_PCIE_STATIC_SPARE1 0x5bf8
+#define A_PCIE_STATIC_SPARE2 0x5bfc
+
+/* registers for module DBG */
+#define DBG_BASE_ADDR 0x6000
+
+#define A_DBG_DBG0_CFG 0x6000
+
+#define S_MODULESELECT    12
+#define M_MODULESELECT    0xffU
+#define V_MODULESELECT(x) ((x) << S_MODULESELECT)
+#define G_MODULESELECT(x) (((x) >> S_MODULESELECT) & M_MODULESELECT)
+
+#define S_REGSELECT    4
+#define M_REGSELECT    0xffU
+#define V_REGSELECT(x) ((x) << S_REGSELECT)
+#define G_REGSELECT(x) (((x) >> S_REGSELECT) & M_REGSELECT)
+
+#define S_CLKSELECT    0
+#define M_CLKSELECT    0xfU
+#define V_CLKSELECT(x) ((x) << S_CLKSELECT)
+#define G_CLKSELECT(x) (((x) >> S_CLKSELECT) & M_CLKSELECT)
+
+#define A_DBG_DBG0_EN 0x6004
+
+#define S_PORTEN_PONR    16
+#define V_PORTEN_PONR(x) ((x) << S_PORTEN_PONR)
+#define F_PORTEN_PONR    V_PORTEN_PONR(1U)
+
+#define S_PORTEN_POND    12
+#define V_PORTEN_POND(x) ((x) << S_PORTEN_POND)
+#define F_PORTEN_POND    V_PORTEN_POND(1U)
+
+#define S_SDRHALFWORD0    8
+#define V_SDRHALFWORD0(x) ((x) << S_SDRHALFWORD0)
+#define F_SDRHALFWORD0    V_SDRHALFWORD0(1U)
+
+#define S_DDREN    4
+#define V_DDREN(x) ((x) << S_DDREN)
+#define F_DDREN    V_DDREN(1U)
+
+#define S_DBG_PORTEN    0
+#define V_DBG_PORTEN(x) ((x) << S_DBG_PORTEN)
+#define F_DBG_PORTEN    V_DBG_PORTEN(1U)
+
+#define A_DBG_DBG1_CFG 0x6008
+#define A_DBG_DBG1_EN 0x600c
+
+#define S_CLK_EN_ON_DBG1    20
+#define V_CLK_EN_ON_DBG1(x) ((x) << S_CLK_EN_ON_DBG1)
+#define F_CLK_EN_ON_DBG1    V_CLK_EN_ON_DBG1(1U)
+
+#define A_DBG_GPIO_EN 0x6010
+
+#define S_GPIO15_OEN    31
+#define V_GPIO15_OEN(x) ((x) << S_GPIO15_OEN)
+#define F_GPIO15_OEN    V_GPIO15_OEN(1U)
+
+#define S_GPIO14_OEN    30
+#define V_GPIO14_OEN(x) ((x) << S_GPIO14_OEN)
+#define F_GPIO14_OEN    V_GPIO14_OEN(1U)
+
+#define S_GPIO13_OEN    29
+#define V_GPIO13_OEN(x) ((x) << S_GPIO13_OEN)
+#define F_GPIO13_OEN    V_GPIO13_OEN(1U)
+
+#define S_GPIO12_OEN    28
+#define V_GPIO12_OEN(x) ((x) << S_GPIO12_OEN)
+#define F_GPIO12_OEN    V_GPIO12_OEN(1U)
+
+#define S_GPIO11_OEN    27
+#define V_GPIO11_OEN(x) ((x) << S_GPIO11_OEN)
+#define F_GPIO11_OEN    V_GPIO11_OEN(1U)
+
+#define S_GPIO10_OEN    26
+#define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN)
+#define F_GPIO10_OEN    V_GPIO10_OEN(1U)
+
+#define S_GPIO9_OEN    25
+#define V_GPIO9_OEN(x) ((x) << S_GPIO9_OEN)
+#define F_GPIO9_OEN    V_GPIO9_OEN(1U)
+
+#define S_GPIO8_OEN    24
+#define V_GPIO8_OEN(x) ((x) << S_GPIO8_OEN)
+#define F_GPIO8_OEN    V_GPIO8_OEN(1U)
+
+#define S_GPIO7_OEN    23
+#define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN)
+#define F_GPIO7_OEN    V_GPIO7_OEN(1U)
+
+#define S_GPIO6_OEN    22
+#define V_GPIO6_OEN(x) ((x) << S_GPIO6_OEN)
+#define F_GPIO6_OEN    V_GPIO6_OEN(1U)
+
+#define S_GPIO5_OEN    21
+#define V_GPIO5_OEN(x) ((x) << S_GPIO5_OEN)
+#define F_GPIO5_OEN    V_GPIO5_OEN(1U)
+
+#define S_GPIO4_OEN    20
+#define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN)
+#define F_GPIO4_OEN    V_GPIO4_OEN(1U)
+
+#define S_GPIO3_OEN    19
+#define V_GPIO3_OEN(x) ((x) << S_GPIO3_OEN)
+#define F_GPIO3_OEN    V_GPIO3_OEN(1U)
+
+#define S_GPIO2_OEN    18
+#define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN)
+#define F_GPIO2_OEN    V_GPIO2_OEN(1U)
+
+#define S_GPIO1_OEN    17
+#define V_GPIO1_OEN(x) ((x) << S_GPIO1_OEN)
+#define F_GPIO1_OEN    V_GPIO1_OEN(1U)
+
+#define S_GPIO0_OEN    16
+#define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN)
+#define F_GPIO0_OEN    V_GPIO0_OEN(1U)
+
+#define S_GPIO15_OUT_VAL    15
+#define V_GPIO15_OUT_VAL(x) ((x) << S_GPIO15_OUT_VAL)
+#define F_GPIO15_OUT_VAL    V_GPIO15_OUT_VAL(1U)
+
+#define S_GPIO14_OUT_VAL    14
+#define V_GPIO14_OUT_VAL(x) ((x) << S_GPIO14_OUT_VAL)
+#define F_GPIO14_OUT_VAL    V_GPIO14_OUT_VAL(1U)
+
+#define S_GPIO13_OUT_VAL    13
+#define V_GPIO13_OUT_VAL(x) ((x) << S_GPIO13_OUT_VAL)
+#define F_GPIO13_OUT_VAL    V_GPIO13_OUT_VAL(1U)
+
+#define S_GPIO12_OUT_VAL    12
+#define V_GPIO12_OUT_VAL(x) ((x) << S_GPIO12_OUT_VAL)
+#define F_GPIO12_OUT_VAL    V_GPIO12_OUT_VAL(1U)
+
+#define S_GPIO11_OUT_VAL    11
+#define V_GPIO11_OUT_VAL(x) ((x) << S_GPIO11_OUT_VAL)
+#define F_GPIO11_OUT_VAL    V_GPIO11_OUT_VAL(1U)
+
+#define S_GPIO10_OUT_VAL    10
+#define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL)
+#define F_GPIO10_OUT_VAL    V_GPIO10_OUT_VAL(1U)
+
+#define S_GPIO9_OUT_VAL    9
+#define V_GPIO9_OUT_VAL(x) ((x) << S_GPIO9_OUT_VAL)
+#define F_GPIO9_OUT_VAL    V_GPIO9_OUT_VAL(1U)
+
+#define S_GPIO8_OUT_VAL    8
+#define V_GPIO8_OUT_VAL(x) ((x) << S_GPIO8_OUT_VAL)
+#define F_GPIO8_OUT_VAL    V_GPIO8_OUT_VAL(1U)
+
+#define S_GPIO7_OUT_VAL    7
+#define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL)
+#define F_GPIO7_OUT_VAL    V_GPIO7_OUT_VAL(1U)
+
+#define S_GPIO6_OUT_VAL    6
+#define V_GPIO6_OUT_VAL(x) ((x) << S_GPIO6_OUT_VAL)
+#define F_GPIO6_OUT_VAL    V_GPIO6_OUT_VAL(1U)
+
+#define S_GPIO5_OUT_VAL    5
+#define V_GPIO5_OUT_VAL(x) ((x) << S_GPIO5_OUT_VAL)
+#define F_GPIO5_OUT_VAL    V_GPIO5_OUT_VAL(1U)
+
+#define S_GPIO4_OUT_VAL    4
+#define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL)
+#define F_GPIO4_OUT_VAL    V_GPIO4_OUT_VAL(1U)
+
+#define S_GPIO3_OUT_VAL    3
+#define V_GPIO3_OUT_VAL(x) ((x) << S_GPIO3_OUT_VAL)
+#define F_GPIO3_OUT_VAL    V_GPIO3_OUT_VAL(1U)
+
+#define S_GPIO2_OUT_VAL    2
+#define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL)
+#define F_GPIO2_OUT_VAL    V_GPIO2_OUT_VAL(1U)
+
+#define S_GPIO1_OUT_VAL    1
+#define V_GPIO1_OUT_VAL(x) ((x) << S_GPIO1_OUT_VAL)
+#define F_GPIO1_OUT_VAL    V_GPIO1_OUT_VAL(1U)
+
+#define S_GPIO0_OUT_VAL    0
+#define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL)
+#define F_GPIO0_OUT_VAL    V_GPIO0_OUT_VAL(1U)
+
+#define A_DBG_GPIO_IN 0x6014
+
+#define S_GPIO15_CHG_DET    31
+#define V_GPIO15_CHG_DET(x) ((x) << S_GPIO15_CHG_DET)
+#define F_GPIO15_CHG_DET    V_GPIO15_CHG_DET(1U)
+
+#define S_GPIO14_CHG_DET    30
+#define V_GPIO14_CHG_DET(x) ((x) << S_GPIO14_CHG_DET)
+#define F_GPIO14_CHG_DET    V_GPIO14_CHG_DET(1U)
+
+#define S_GPIO13_CHG_DET    29
+#define V_GPIO13_CHG_DET(x) ((x) << S_GPIO13_CHG_DET)
+#define F_GPIO13_CHG_DET    V_GPIO13_CHG_DET(1U)
+
+#define S_GPIO12_CHG_DET    28
+#define V_GPIO12_CHG_DET(x) ((x) << S_GPIO12_CHG_DET)
+#define F_GPIO12_CHG_DET    V_GPIO12_CHG_DET(1U)
+
+#define S_GPIO11_CHG_DET    27
+#define V_GPIO11_CHG_DET(x) ((x) << S_GPIO11_CHG_DET)
+#define F_GPIO11_CHG_DET    V_GPIO11_CHG_DET(1U)
+
+#define S_GPIO10_CHG_DET    26
+#define V_GPIO10_CHG_DET(x) ((x) << S_GPIO10_CHG_DET)
+#define F_GPIO10_CHG_DET    V_GPIO10_CHG_DET(1U)
+
+#define S_GPIO9_CHG_DET    25
+#define V_GPIO9_CHG_DET(x) ((x) << S_GPIO9_CHG_DET)
+#define F_GPIO9_CHG_DET    V_GPIO9_CHG_DET(1U)
+
+#define S_GPIO8_CHG_DET    24
+#define V_GPIO8_CHG_DET(x) ((x) << S_GPIO8_CHG_DET)
+#define F_GPIO8_CHG_DET    V_GPIO8_CHG_DET(1U)
+
+#define S_GPIO7_CHG_DET    23
+#define V_GPIO7_CHG_DET(x) ((x) << S_GPIO7_CHG_DET)
+#define F_GPIO7_CHG_DET    V_GPIO7_CHG_DET(1U)
+
+#define S_GPIO6_CHG_DET    22
+#define V_GPIO6_CHG_DET(x) ((x) << S_GPIO6_CHG_DET)
+#define F_GPIO6_CHG_DET    V_GPIO6_CHG_DET(1U)
+
+#define S_GPIO5_CHG_DET    21
+#define V_GPIO5_CHG_DET(x) ((x) << S_GPIO5_CHG_DET)
+#define F_GPIO5_CHG_DET    V_GPIO5_CHG_DET(1U)
+
+#define S_GPIO4_CHG_DET    20
+#define V_GPIO4_CHG_DET(x) ((x) << S_GPIO4_CHG_DET)
+#define F_GPIO4_CHG_DET    V_GPIO4_CHG_DET(1U)
+
+#define S_GPIO3_CHG_DET    19
+#define V_GPIO3_CHG_DET(x) ((x) << S_GPIO3_CHG_DET)
+#define F_GPIO3_CHG_DET    V_GPIO3_CHG_DET(1U)
+
+#define S_GPIO2_CHG_DET    18
+#define V_GPIO2_CHG_DET(x) ((x) << S_GPIO2_CHG_DET)
+#define F_GPIO2_CHG_DET    V_GPIO2_CHG_DET(1U)
+
+#define S_GPIO1_CHG_DET    17
+#define V_GPIO1_CHG_DET(x) ((x) << S_GPIO1_CHG_DET)
+#define F_GPIO1_CHG_DET    V_GPIO1_CHG_DET(1U)
+
+#define S_GPIO0_CHG_DET    16
+#define V_GPIO0_CHG_DET(x) ((x) << S_GPIO0_CHG_DET)
+#define F_GPIO0_CHG_DET    V_GPIO0_CHG_DET(1U)
+
+#define S_GPIO15_IN    15
+#define V_GPIO15_IN(x) ((x) << S_GPIO15_IN)
+#define F_GPIO15_IN    V_GPIO15_IN(1U)
+
+#define S_GPIO14_IN    14
+#define V_GPIO14_IN(x) ((x) << S_GPIO14_IN)
+#define F_GPIO14_IN    V_GPIO14_IN(1U)
+
+#define S_GPIO13_IN    13
+#define V_GPIO13_IN(x) ((x) << S_GPIO13_IN)
+#define F_GPIO13_IN    V_GPIO13_IN(1U)
+
+#define S_GPIO12_IN    12
+#define V_GPIO12_IN(x) ((x) << S_GPIO12_IN)
+#define F_GPIO12_IN    V_GPIO12_IN(1U)
+
+#define S_GPIO11_IN    11
+#define V_GPIO11_IN(x) ((x) << S_GPIO11_IN)
+#define F_GPIO11_IN    V_GPIO11_IN(1U)
+
+#define S_GPIO10_IN    10
+#define V_GPIO10_IN(x) ((x) << S_GPIO10_IN)
+#define F_GPIO10_IN    V_GPIO10_IN(1U)
+
+#define S_GPIO9_IN    9
+#define V_GPIO9_IN(x) ((x) << S_GPIO9_IN)
+#define F_GPIO9_IN    V_GPIO9_IN(1U)
+
+#define S_GPIO8_IN    8
+#define V_GPIO8_IN(x) ((x) << S_GPIO8_IN)
+#define F_GPIO8_IN    V_GPIO8_IN(1U)
+
+#define S_GPIO7_IN    7
+#define V_GPIO7_IN(x) ((x) << S_GPIO7_IN)
+#define F_GPIO7_IN    V_GPIO7_IN(1U)
+
+#define S_GPIO6_IN    6
+#define V_GPIO6_IN(x) ((x) << S_GPIO6_IN)
+#define F_GPIO6_IN    V_GPIO6_IN(1U)
+
+#define S_GPIO5_IN    5
+#define V_GPIO5_IN(x) ((x) << S_GPIO5_IN)
+#define F_GPIO5_IN    V_GPIO5_IN(1U)
+
+#define S_GPIO4_IN    4
+#define V_GPIO4_IN(x) ((x) << S_GPIO4_IN)
+#define F_GPIO4_IN    V_GPIO4_IN(1U)
+
+#define S_GPIO3_IN    3
+#define V_GPIO3_IN(x) ((x) << S_GPIO3_IN)
+#define F_GPIO3_IN    V_GPIO3_IN(1U)
+
+#define S_GPIO2_IN    2
+#define V_GPIO2_IN(x) ((x) << S_GPIO2_IN)
+#define F_GPIO2_IN    V_GPIO2_IN(1U)
+
+#define S_GPIO1_IN    1
+#define V_GPIO1_IN(x) ((x) << S_GPIO1_IN)
+#define F_GPIO1_IN    V_GPIO1_IN(1U)
+
+#define S_GPIO0_IN    0
+#define V_GPIO0_IN(x) ((x) << S_GPIO0_IN)
+#define F_GPIO0_IN    V_GPIO0_IN(1U)
+
+#define A_DBG_INT_ENABLE 0x6018
+
+#define S_IBM_FDL_FAIL_INT_ENBL    25
+#define V_IBM_FDL_FAIL_INT_ENBL(x) ((x) << S_IBM_FDL_FAIL_INT_ENBL)
+#define F_IBM_FDL_FAIL_INT_ENBL    V_IBM_FDL_FAIL_INT_ENBL(1U)
+
+#define S_ARM_FAIL_INT_ENBL    24
+#define V_ARM_FAIL_INT_ENBL(x) ((x) << S_ARM_FAIL_INT_ENBL)
+#define F_ARM_FAIL_INT_ENBL    V_ARM_FAIL_INT_ENBL(1U)
+
+#define S_ARM_ERROR_OUT_INT_ENBL    23
+#define V_ARM_ERROR_OUT_INT_ENBL(x) ((x) << S_ARM_ERROR_OUT_INT_ENBL)
+#define F_ARM_ERROR_OUT_INT_ENBL    V_ARM_ERROR_OUT_INT_ENBL(1U)
+
+#define S_PLL_LOCK_LOST_INT_ENBL    22
+#define V_PLL_LOCK_LOST_INT_ENBL(x) ((x) << S_PLL_LOCK_LOST_INT_ENBL)
+#define F_PLL_LOCK_LOST_INT_ENBL    V_PLL_LOCK_LOST_INT_ENBL(1U)
+
+#define S_C_LOCK    21
+#define V_C_LOCK(x) ((x) << S_C_LOCK)
+#define F_C_LOCK    V_C_LOCK(1U)
+
+#define S_M_LOCK    20
+#define V_M_LOCK(x) ((x) << S_M_LOCK)
+#define F_M_LOCK    V_M_LOCK(1U)
+
+#define S_U_LOCK    19
+#define V_U_LOCK(x) ((x) << S_U_LOCK)
+#define F_U_LOCK    V_U_LOCK(1U)
+
+#define S_PCIE_LOCK    18
+#define V_PCIE_LOCK(x) ((x) << S_PCIE_LOCK)
+#define F_PCIE_LOCK    V_PCIE_LOCK(1U)
+
+#define S_KX_LOCK    17
+#define V_KX_LOCK(x) ((x) << S_KX_LOCK)
+#define F_KX_LOCK    V_KX_LOCK(1U)
+
+#define S_KR_LOCK    16
+#define V_KR_LOCK(x) ((x) << S_KR_LOCK)
+#define F_KR_LOCK    V_KR_LOCK(1U)
+
+#define S_GPIO15    15
+#define V_GPIO15(x) ((x) << S_GPIO15)
+#define F_GPIO15    V_GPIO15(1U)
+
+#define S_GPIO14    14
+#define V_GPIO14(x) ((x) << S_GPIO14)
+#define F_GPIO14    V_GPIO14(1U)
+
+#define S_GPIO13    13
+#define V_GPIO13(x) ((x) << S_GPIO13)
+#define F_GPIO13    V_GPIO13(1U)
+
+#define S_GPIO12    12
+#define V_GPIO12(x) ((x) << S_GPIO12)
+#define F_GPIO12    V_GPIO12(1U)
+
+#define S_GPIO11    11
+#define V_GPIO11(x) ((x) << S_GPIO11)
+#define F_GPIO11    V_GPIO11(1U)
+
+#define S_GPIO10    10
+#define V_GPIO10(x) ((x) << S_GPIO10)
+#define F_GPIO10    V_GPIO10(1U)
+
+#define S_GPIO9    9
+#define V_GPIO9(x) ((x) << S_GPIO9)
+#define F_GPIO9    V_GPIO9(1U)
+
+#define S_GPIO8    8
+#define V_GPIO8(x) ((x) << S_GPIO8)
+#define F_GPIO8    V_GPIO8(1U)
+
+#define S_GPIO7    7
+#define V_GPIO7(x) ((x) << S_GPIO7)
+#define F_GPIO7    V_GPIO7(1U)
+
+#define S_GPIO6    6
+#define V_GPIO6(x) ((x) << S_GPIO6)
+#define F_GPIO6    V_GPIO6(1U)
+
+#define S_GPIO5    5
+#define V_GPIO5(x) ((x) << S_GPIO5)
+#define F_GPIO5    V_GPIO5(1U)
+
+#define S_GPIO4    4
+#define V_GPIO4(x) ((x) << S_GPIO4)
+#define F_GPIO4    V_GPIO4(1U)
+
+#define S_GPIO3    3
+#define V_GPIO3(x) ((x) << S_GPIO3)
+#define F_GPIO3    V_GPIO3(1U)
+
+#define S_GPIO2    2
+#define V_GPIO2(x) ((x) << S_GPIO2)
+#define F_GPIO2    V_GPIO2(1U)
+
+#define S_GPIO1    1
+#define V_GPIO1(x) ((x) << S_GPIO1)
+#define F_GPIO1    V_GPIO1(1U)
+
+#define S_GPIO0    0
+#define V_GPIO0(x) ((x) << S_GPIO0)
+#define F_GPIO0    V_GPIO0(1U)
+
+#define S_GPIO19    29
+#define V_GPIO19(x) ((x) << S_GPIO19)
+#define F_GPIO19    V_GPIO19(1U)
+
+#define S_GPIO18    28
+#define V_GPIO18(x) ((x) << S_GPIO18)
+#define F_GPIO18    V_GPIO18(1U)
+
+#define S_GPIO17    27
+#define V_GPIO17(x) ((x) << S_GPIO17)
+#define F_GPIO17    V_GPIO17(1U)
+
+#define S_GPIO16    26
+#define V_GPIO16(x) ((x) << S_GPIO16)
+#define F_GPIO16    V_GPIO16(1U)
+
+#define A_DBG_INT_CAUSE 0x601c
+
+#define S_IBM_FDL_FAIL_INT_CAUSE    25
+#define V_IBM_FDL_FAIL_INT_CAUSE(x) ((x) << S_IBM_FDL_FAIL_INT_CAUSE)
+#define F_IBM_FDL_FAIL_INT_CAUSE    V_IBM_FDL_FAIL_INT_CAUSE(1U)
+
+#define S_ARM_FAIL_INT_CAUSE    24
+#define V_ARM_FAIL_INT_CAUSE(x) ((x) << S_ARM_FAIL_INT_CAUSE)
+#define F_ARM_FAIL_INT_CAUSE    V_ARM_FAIL_INT_CAUSE(1U)
+
+#define S_ARM_ERROR_OUT_INT_CAUSE    23
+#define V_ARM_ERROR_OUT_INT_CAUSE(x) ((x) << S_ARM_ERROR_OUT_INT_CAUSE)
+#define F_ARM_ERROR_OUT_INT_CAUSE    V_ARM_ERROR_OUT_INT_CAUSE(1U)
+
+#define S_PLL_LOCK_LOST_INT_CAUSE    22
+#define V_PLL_LOCK_LOST_INT_CAUSE(x) ((x) << S_PLL_LOCK_LOST_INT_CAUSE)
+#define F_PLL_LOCK_LOST_INT_CAUSE    V_PLL_LOCK_LOST_INT_CAUSE(1U)
+
+#define A_DBG_DBG0_RST_VALUE 0x6020
+
+#define S_DEBUGDATA    0
+#define M_DEBUGDATA    0xffffU
+#define V_DEBUGDATA(x) ((x) << S_DEBUGDATA)
+#define G_DEBUGDATA(x) (((x) >> S_DEBUGDATA) & M_DEBUGDATA)
+
+#define A_DBG_OVERWRSERCFG_EN 0x6024
+
+#define S_OVERWRSERCFG_EN    0
+#define V_OVERWRSERCFG_EN(x) ((x) << S_OVERWRSERCFG_EN)
+#define F_OVERWRSERCFG_EN    V_OVERWRSERCFG_EN(1U)
+
+#define A_DBG_PLL_OCLK_PAD_EN 0x6028
+
+#define S_PCIE_OCLK_EN    20
+#define V_PCIE_OCLK_EN(x) ((x) << S_PCIE_OCLK_EN)
+#define F_PCIE_OCLK_EN    V_PCIE_OCLK_EN(1U)
+
+#define S_KX_OCLK_EN    16
+#define V_KX_OCLK_EN(x) ((x) << S_KX_OCLK_EN)
+#define F_KX_OCLK_EN    V_KX_OCLK_EN(1U)
+
+#define S_U_OCLK_EN    12
+#define V_U_OCLK_EN(x) ((x) << S_U_OCLK_EN)
+#define F_U_OCLK_EN    V_U_OCLK_EN(1U)
+
+#define S_KR_OCLK_EN    8
+#define V_KR_OCLK_EN(x) ((x) << S_KR_OCLK_EN)
+#define F_KR_OCLK_EN    V_KR_OCLK_EN(1U)
+
+#define S_M_OCLK_EN    4
+#define V_M_OCLK_EN(x) ((x) << S_M_OCLK_EN)
+#define F_M_OCLK_EN    V_M_OCLK_EN(1U)
+
+#define S_C_OCLK_EN    0
+#define V_C_OCLK_EN(x) ((x) << S_C_OCLK_EN)
+#define F_C_OCLK_EN    V_C_OCLK_EN(1U)
+
+#define A_DBG_PLL_LOCK 0x602c
+
+#define S_PLL_P_LOCK    20
+#define V_PLL_P_LOCK(x) ((x) << S_PLL_P_LOCK)
+#define F_PLL_P_LOCK    V_PLL_P_LOCK(1U)
+
+#define S_PLL_KX_LOCK    16
+#define V_PLL_KX_LOCK(x) ((x) << S_PLL_KX_LOCK)
+#define F_PLL_KX_LOCK    V_PLL_KX_LOCK(1U)
+
+#define S_PLL_U_LOCK    12
+#define V_PLL_U_LOCK(x) ((x) << S_PLL_U_LOCK)
+#define F_PLL_U_LOCK    V_PLL_U_LOCK(1U)
+
+#define S_PLL_KR_LOCK    8
+#define V_PLL_KR_LOCK(x) ((x) << S_PLL_KR_LOCK)
+#define F_PLL_KR_LOCK    V_PLL_KR_LOCK(1U)
+
+#define S_PLL_M_LOCK    4
+#define V_PLL_M_LOCK(x) ((x) << S_PLL_M_LOCK)
+#define F_PLL_M_LOCK    V_PLL_M_LOCK(1U)
+
+#define S_PLL_C_LOCK    0
+#define V_PLL_C_LOCK(x) ((x) << S_PLL_C_LOCK)
+#define F_PLL_C_LOCK    V_PLL_C_LOCK(1U)
+
+#define A_DBG_GPIO_ACT_LOW 0x6030
+
+#define S_P_LOCK_ACT_LOW    21
+#define V_P_LOCK_ACT_LOW(x) ((x) << S_P_LOCK_ACT_LOW)
+#define F_P_LOCK_ACT_LOW    V_P_LOCK_ACT_LOW(1U)
+
+#define S_C_LOCK_ACT_LOW    20
+#define V_C_LOCK_ACT_LOW(x) ((x) << S_C_LOCK_ACT_LOW)
+#define F_C_LOCK_ACT_LOW    V_C_LOCK_ACT_LOW(1U)
+
+#define S_M_LOCK_ACT_LOW    19
+#define V_M_LOCK_ACT_LOW(x) ((x) << S_M_LOCK_ACT_LOW)
+#define F_M_LOCK_ACT_LOW    V_M_LOCK_ACT_LOW(1U)
+
+#define S_U_LOCK_ACT_LOW    18
+#define V_U_LOCK_ACT_LOW(x) ((x) << S_U_LOCK_ACT_LOW)
+#define F_U_LOCK_ACT_LOW    V_U_LOCK_ACT_LOW(1U)
+
+#define S_KR_LOCK_ACT_LOW    17
+#define V_KR_LOCK_ACT_LOW(x) ((x) << S_KR_LOCK_ACT_LOW)
+#define F_KR_LOCK_ACT_LOW    V_KR_LOCK_ACT_LOW(1U)
+
+#define S_KX_LOCK_ACT_LOW    16
+#define V_KX_LOCK_ACT_LOW(x) ((x) << S_KX_LOCK_ACT_LOW)
+#define F_KX_LOCK_ACT_LOW    V_KX_LOCK_ACT_LOW(1U)
+
+#define S_GPIO15_ACT_LOW    15
+#define V_GPIO15_ACT_LOW(x) ((x) << S_GPIO15_ACT_LOW)
+#define F_GPIO15_ACT_LOW    V_GPIO15_ACT_LOW(1U)
+
+#define S_GPIO14_ACT_LOW    14
+#define V_GPIO14_ACT_LOW(x) ((x) << S_GPIO14_ACT_LOW)
+#define F_GPIO14_ACT_LOW    V_GPIO14_ACT_LOW(1U)
+
+#define S_GPIO13_ACT_LOW    13
+#define V_GPIO13_ACT_LOW(x) ((x) << S_GPIO13_ACT_LOW)
+#define F_GPIO13_ACT_LOW    V_GPIO13_ACT_LOW(1U)
+
+#define S_GPIO12_ACT_LOW    12
+#define V_GPIO12_ACT_LOW(x) ((x) << S_GPIO12_ACT_LOW)
+#define F_GPIO12_ACT_LOW    V_GPIO12_ACT_LOW(1U)
+
+#define S_GPIO11_ACT_LOW    11
+#define V_GPIO11_ACT_LOW(x) ((x) << S_GPIO11_ACT_LOW)
+#define F_GPIO11_ACT_LOW    V_GPIO11_ACT_LOW(1U)
+
+#define S_GPIO10_ACT_LOW    10
+#define V_GPIO10_ACT_LOW(x) ((x) << S_GPIO10_ACT_LOW)
+#define F_GPIO10_ACT_LOW    V_GPIO10_ACT_LOW(1U)
+
+#define S_GPIO9_ACT_LOW    9
+#define V_GPIO9_ACT_LOW(x) ((x) << S_GPIO9_ACT_LOW)
+#define F_GPIO9_ACT_LOW    V_GPIO9_ACT_LOW(1U)
+
+#define S_GPIO8_ACT_LOW    8
+#define V_GPIO8_ACT_LOW(x) ((x) << S_GPIO8_ACT_LOW)
+#define F_GPIO8_ACT_LOW    V_GPIO8_ACT_LOW(1U)
+
+#define S_GPIO7_ACT_LOW    7
+#define V_GPIO7_ACT_LOW(x) ((x) << S_GPIO7_ACT_LOW)
+#define F_GPIO7_ACT_LOW    V_GPIO7_ACT_LOW(1U)
+
+#define S_GPIO6_ACT_LOW    6
+#define V_GPIO6_ACT_LOW(x) ((x) << S_GPIO6_ACT_LOW)
+#define F_GPIO6_ACT_LOW    V_GPIO6_ACT_LOW(1U)
+
+#define S_GPIO5_ACT_LOW    5
+#define V_GPIO5_ACT_LOW(x) ((x) << S_GPIO5_ACT_LOW)
+#define F_GPIO5_ACT_LOW    V_GPIO5_ACT_LOW(1U)
+
+#define S_GPIO4_ACT_LOW    4
+#define V_GPIO4_ACT_LOW(x) ((x) << S_GPIO4_ACT_LOW)
+#define F_GPIO4_ACT_LOW    V_GPIO4_ACT_LOW(1U)
+
+#define S_GPIO3_ACT_LOW    3
+#define V_GPIO3_ACT_LOW(x) ((x) << S_GPIO3_ACT_LOW)
+#define F_GPIO3_ACT_LOW    V_GPIO3_ACT_LOW(1U)
+
+#define S_GPIO2_ACT_LOW    2
+#define V_GPIO2_ACT_LOW(x) ((x) << S_GPIO2_ACT_LOW)
+#define F_GPIO2_ACT_LOW    V_GPIO2_ACT_LOW(1U)
+
+#define S_GPIO1_ACT_LOW    1
+#define V_GPIO1_ACT_LOW(x) ((x) << S_GPIO1_ACT_LOW)
+#define F_GPIO1_ACT_LOW    V_GPIO1_ACT_LOW(1U)
+
+#define S_GPIO0_ACT_LOW    0
+#define V_GPIO0_ACT_LOW(x) ((x) << S_GPIO0_ACT_LOW)
+#define F_GPIO0_ACT_LOW    V_GPIO0_ACT_LOW(1U)
+
+#define S_GPIO19_ACT_LOW    25
+#define V_GPIO19_ACT_LOW(x) ((x) << S_GPIO19_ACT_LOW)
+#define F_GPIO19_ACT_LOW    V_GPIO19_ACT_LOW(1U)
+
+#define S_GPIO18_ACT_LOW    24
+#define V_GPIO18_ACT_LOW(x) ((x) << S_GPIO18_ACT_LOW)
+#define F_GPIO18_ACT_LOW    V_GPIO18_ACT_LOW(1U)
+
+#define S_GPIO17_ACT_LOW    23
+#define V_GPIO17_ACT_LOW(x) ((x) << S_GPIO17_ACT_LOW)
+#define F_GPIO17_ACT_LOW    V_GPIO17_ACT_LOW(1U)
+
+#define S_GPIO16_ACT_LOW    22
+#define V_GPIO16_ACT_LOW(x) ((x) << S_GPIO16_ACT_LOW)
+#define F_GPIO16_ACT_LOW    V_GPIO16_ACT_LOW(1U)
+
+#define A_DBG_EFUSE_BYTE0_3 0x6034
+#define A_DBG_EFUSE_BYTE4_7 0x6038
+#define A_DBG_EFUSE_BYTE8_11 0x603c
+#define A_DBG_EFUSE_BYTE12_15 0x6040
+#define A_DBG_STATIC_U_PLL_CONF 0x6044
+
+#define S_STATIC_U_PLL_MULT    23
+#define M_STATIC_U_PLL_MULT    0x1ffU
+#define V_STATIC_U_PLL_MULT(x) ((x) << S_STATIC_U_PLL_MULT)
+#define G_STATIC_U_PLL_MULT(x) (((x) >> S_STATIC_U_PLL_MULT) & M_STATIC_U_PLL_MULT)
+
+#define S_STATIC_U_PLL_PREDIV    18
+#define M_STATIC_U_PLL_PREDIV    0x1fU
+#define V_STATIC_U_PLL_PREDIV(x) ((x) << S_STATIC_U_PLL_PREDIV)
+#define G_STATIC_U_PLL_PREDIV(x) (((x) >> S_STATIC_U_PLL_PREDIV) & M_STATIC_U_PLL_PREDIV)
+
+#define S_STATIC_U_PLL_RANGEA    14
+#define M_STATIC_U_PLL_RANGEA    0xfU
+#define V_STATIC_U_PLL_RANGEA(x) ((x) << S_STATIC_U_PLL_RANGEA)
+#define G_STATIC_U_PLL_RANGEA(x) (((x) >> S_STATIC_U_PLL_RANGEA) & M_STATIC_U_PLL_RANGEA)
+
+#define S_STATIC_U_PLL_RANGEB    10
+#define M_STATIC_U_PLL_RANGEB    0xfU
+#define V_STATIC_U_PLL_RANGEB(x) ((x) << S_STATIC_U_PLL_RANGEB)
+#define G_STATIC_U_PLL_RANGEB(x) (((x) >> S_STATIC_U_PLL_RANGEB) & M_STATIC_U_PLL_RANGEB)
+
+#define S_STATIC_U_PLL_TUNE    0
+#define M_STATIC_U_PLL_TUNE    0x3ffU
+#define V_STATIC_U_PLL_TUNE(x) ((x) << S_STATIC_U_PLL_TUNE)
+#define G_STATIC_U_PLL_TUNE(x) (((x) >> S_STATIC_U_PLL_TUNE) & M_STATIC_U_PLL_TUNE)
+
+#define A_DBG_STATIC_C_PLL_CONF 0x6048
+
+#define S_STATIC_C_PLL_MULT    23
+#define M_STATIC_C_PLL_MULT    0x1ffU
+#define V_STATIC_C_PLL_MULT(x) ((x) << S_STATIC_C_PLL_MULT)
+#define G_STATIC_C_PLL_MULT(x) (((x) >> S_STATIC_C_PLL_MULT) & M_STATIC_C_PLL_MULT)
+
+#define S_STATIC_C_PLL_PREDIV    18
+#define M_STATIC_C_PLL_PREDIV    0x1fU
+#define V_STATIC_C_PLL_PREDIV(x) ((x) << S_STATIC_C_PLL_PREDIV)
+#define G_STATIC_C_PLL_PREDIV(x) (((x) >> S_STATIC_C_PLL_PREDIV) & M_STATIC_C_PLL_PREDIV)
+
+#define S_STATIC_C_PLL_RANGEA    14
+#define M_STATIC_C_PLL_RANGEA    0xfU
+#define V_STATIC_C_PLL_RANGEA(x) ((x) << S_STATIC_C_PLL_RANGEA)
+#define G_STATIC_C_PLL_RANGEA(x) (((x) >> S_STATIC_C_PLL_RANGEA) & M_STATIC_C_PLL_RANGEA)
+
+#define S_STATIC_C_PLL_RANGEB    10
+#define M_STATIC_C_PLL_RANGEB    0xfU
+#define V_STATIC_C_PLL_RANGEB(x) ((x) << S_STATIC_C_PLL_RANGEB)
+#define G_STATIC_C_PLL_RANGEB(x) (((x) >> S_STATIC_C_PLL_RANGEB) & M_STATIC_C_PLL_RANGEB)
+
+#define S_STATIC_C_PLL_TUNE    0
+#define M_STATIC_C_PLL_TUNE    0x3ffU
+#define V_STATIC_C_PLL_TUNE(x) ((x) << S_STATIC_C_PLL_TUNE)
+#define G_STATIC_C_PLL_TUNE(x) (((x) >> S_STATIC_C_PLL_TUNE) & M_STATIC_C_PLL_TUNE)
+
+#define A_DBG_STATIC_M_PLL_CONF 0x604c
+
+#define S_STATIC_M_PLL_MULT    23
+#define M_STATIC_M_PLL_MULT    0x1ffU
+#define V_STATIC_M_PLL_MULT(x) ((x) << S_STATIC_M_PLL_MULT)
+#define G_STATIC_M_PLL_MULT(x) (((x) >> S_STATIC_M_PLL_MULT) & M_STATIC_M_PLL_MULT)
+
+#define S_STATIC_M_PLL_PREDIV    18
+#define M_STATIC_M_PLL_PREDIV    0x1fU
+#define V_STATIC_M_PLL_PREDIV(x) ((x) << S_STATIC_M_PLL_PREDIV)
+#define G_STATIC_M_PLL_PREDIV(x) (((x) >> S_STATIC_M_PLL_PREDIV) & M_STATIC_M_PLL_PREDIV)
+
+#define S_STATIC_M_PLL_RANGEA    14
+#define M_STATIC_M_PLL_RANGEA    0xfU
+#define V_STATIC_M_PLL_RANGEA(x) ((x) << S_STATIC_M_PLL_RANGEA)
+#define G_STATIC_M_PLL_RANGEA(x) (((x) >> S_STATIC_M_PLL_RANGEA) & M_STATIC_M_PLL_RANGEA)
+
+#define S_STATIC_M_PLL_RANGEB    10
+#define M_STATIC_M_PLL_RANGEB    0xfU
+#define V_STATIC_M_PLL_RANGEB(x) ((x) << S_STATIC_M_PLL_RANGEB)
+#define G_STATIC_M_PLL_RANGEB(x) (((x) >> S_STATIC_M_PLL_RANGEB) & M_STATIC_M_PLL_RANGEB)
+
+#define S_STATIC_M_PLL_TUNE    0
+#define M_STATIC_M_PLL_TUNE    0x3ffU
+#define V_STATIC_M_PLL_TUNE(x) ((x) << S_STATIC_M_PLL_TUNE)
+#define G_STATIC_M_PLL_TUNE(x) (((x) >> S_STATIC_M_PLL_TUNE) & M_STATIC_M_PLL_TUNE)
+
+#define A_DBG_STATIC_KX_PLL_CONF 0x6050
+
+#define S_STATIC_KX_PLL_C    21
+#define M_STATIC_KX_PLL_C    0xffU
+#define V_STATIC_KX_PLL_C(x) ((x) << S_STATIC_KX_PLL_C)
+#define G_STATIC_KX_PLL_C(x) (((x) >> S_STATIC_KX_PLL_C) & M_STATIC_KX_PLL_C)
+
+#define S_STATIC_KX_PLL_M    15
+#define M_STATIC_KX_PLL_M    0x3fU
+#define V_STATIC_KX_PLL_M(x) ((x) << S_STATIC_KX_PLL_M)
+#define G_STATIC_KX_PLL_M(x) (((x) >> S_STATIC_KX_PLL_M) & M_STATIC_KX_PLL_M)
+
+#define S_STATIC_KX_PLL_N1    11
+#define M_STATIC_KX_PLL_N1    0xfU
+#define V_STATIC_KX_PLL_N1(x) ((x) << S_STATIC_KX_PLL_N1)
+#define G_STATIC_KX_PLL_N1(x) (((x) >> S_STATIC_KX_PLL_N1) & M_STATIC_KX_PLL_N1)
+
+#define S_STATIC_KX_PLL_N2    7
+#define M_STATIC_KX_PLL_N2    0xfU
+#define V_STATIC_KX_PLL_N2(x) ((x) << S_STATIC_KX_PLL_N2)
+#define G_STATIC_KX_PLL_N2(x) (((x) >> S_STATIC_KX_PLL_N2) & M_STATIC_KX_PLL_N2)
+
+#define S_STATIC_KX_PLL_N3    3
+#define M_STATIC_KX_PLL_N3    0xfU
+#define V_STATIC_KX_PLL_N3(x) ((x) << S_STATIC_KX_PLL_N3)
+#define G_STATIC_KX_PLL_N3(x) (((x) >> S_STATIC_KX_PLL_N3) & M_STATIC_KX_PLL_N3)
+
+#define S_STATIC_KX_PLL_P    0
+#define M_STATIC_KX_PLL_P    0x7U
+#define V_STATIC_KX_PLL_P(x) ((x) << S_STATIC_KX_PLL_P)
+#define G_STATIC_KX_PLL_P(x) (((x) >> S_STATIC_KX_PLL_P) & M_STATIC_KX_PLL_P)
+
+#define A_DBG_STATIC_KR_PLL_CONF 0x6054
+
+#define S_STATIC_KR_PLL_C    21
+#define M_STATIC_KR_PLL_C    0xffU
+#define V_STATIC_KR_PLL_C(x) ((x) << S_STATIC_KR_PLL_C)
+#define G_STATIC_KR_PLL_C(x) (((x) >> S_STATIC_KR_PLL_C) & M_STATIC_KR_PLL_C)
+
+#define S_STATIC_KR_PLL_M    15
+#define M_STATIC_KR_PLL_M    0x3fU
+#define V_STATIC_KR_PLL_M(x) ((x) << S_STATIC_KR_PLL_M)
+#define G_STATIC_KR_PLL_M(x) (((x) >> S_STATIC_KR_PLL_M) & M_STATIC_KR_PLL_M)
+
+#define S_STATIC_KR_PLL_N1    11
+#define M_STATIC_KR_PLL_N1    0xfU
+#define V_STATIC_KR_PLL_N1(x) ((x) << S_STATIC_KR_PLL_N1)
+#define G_STATIC_KR_PLL_N1(x) (((x) >> S_STATIC_KR_PLL_N1) & M_STATIC_KR_PLL_N1)
+
+#define S_STATIC_KR_PLL_N2    7
+#define M_STATIC_KR_PLL_N2    0xfU
+#define V_STATIC_KR_PLL_N2(x) ((x) << S_STATIC_KR_PLL_N2)
+#define G_STATIC_KR_PLL_N2(x) (((x) >> S_STATIC_KR_PLL_N2) & M_STATIC_KR_PLL_N2)
+
+#define S_STATIC_KR_PLL_N3    3
+#define M_STATIC_KR_PLL_N3    0xfU
+#define V_STATIC_KR_PLL_N3(x) ((x) << S_STATIC_KR_PLL_N3)
+#define G_STATIC_KR_PLL_N3(x) (((x) >> S_STATIC_KR_PLL_N3) & M_STATIC_KR_PLL_N3)
+
+#define S_STATIC_KR_PLL_P    0
+#define M_STATIC_KR_PLL_P    0x7U
+#define V_STATIC_KR_PLL_P(x) ((x) << S_STATIC_KR_PLL_P)
+#define G_STATIC_KR_PLL_P(x) (((x) >> S_STATIC_KR_PLL_P) & M_STATIC_KR_PLL_P)
+
+#define A_DBG_EXTRA_STATIC_BITS_CONF 0x6058
+
+#define S_STATIC_M_PLL_RESET    30
+#define V_STATIC_M_PLL_RESET(x) ((x) << S_STATIC_M_PLL_RESET)
+#define F_STATIC_M_PLL_RESET    V_STATIC_M_PLL_RESET(1U)
+
+#define S_STATIC_M_PLL_SLEEP    29
+#define V_STATIC_M_PLL_SLEEP(x) ((x) << S_STATIC_M_PLL_SLEEP)
+#define F_STATIC_M_PLL_SLEEP    V_STATIC_M_PLL_SLEEP(1U)
+
+#define S_STATIC_M_PLL_BYPASS    28
+#define V_STATIC_M_PLL_BYPASS(x) ((x) << S_STATIC_M_PLL_BYPASS)
+#define F_STATIC_M_PLL_BYPASS    V_STATIC_M_PLL_BYPASS(1U)
+
+#define S_STATIC_MPLL_CLK_SEL    27
+#define V_STATIC_MPLL_CLK_SEL(x) ((x) << S_STATIC_MPLL_CLK_SEL)
+#define F_STATIC_MPLL_CLK_SEL    V_STATIC_MPLL_CLK_SEL(1U)
+
+#define S_STATIC_U_PLL_SLEEP    26
+#define V_STATIC_U_PLL_SLEEP(x) ((x) << S_STATIC_U_PLL_SLEEP)
+#define F_STATIC_U_PLL_SLEEP    V_STATIC_U_PLL_SLEEP(1U)
+
+#define S_STATIC_C_PLL_SLEEP    25
+#define V_STATIC_C_PLL_SLEEP(x) ((x) << S_STATIC_C_PLL_SLEEP)
+#define F_STATIC_C_PLL_SLEEP    V_STATIC_C_PLL_SLEEP(1U)
+
+#define S_STATIC_LVDS_CLKOUT_SEL    23
+#define M_STATIC_LVDS_CLKOUT_SEL    0x3U
+#define V_STATIC_LVDS_CLKOUT_SEL(x) ((x) << S_STATIC_LVDS_CLKOUT_SEL)
+#define G_STATIC_LVDS_CLKOUT_SEL(x) (((x) >> S_STATIC_LVDS_CLKOUT_SEL) & M_STATIC_LVDS_CLKOUT_SEL)
+
+#define S_STATIC_LVDS_CLKOUT_EN    22
+#define V_STATIC_LVDS_CLKOUT_EN(x) ((x) << S_STATIC_LVDS_CLKOUT_EN)
+#define F_STATIC_LVDS_CLKOUT_EN    V_STATIC_LVDS_CLKOUT_EN(1U)
+
+#define S_STATIC_CCLK_FREQ_SEL    20
+#define M_STATIC_CCLK_FREQ_SEL    0x3U
+#define V_STATIC_CCLK_FREQ_SEL(x) ((x) << S_STATIC_CCLK_FREQ_SEL)
+#define G_STATIC_CCLK_FREQ_SEL(x) (((x) >> S_STATIC_CCLK_FREQ_SEL) & M_STATIC_CCLK_FREQ_SEL)
+
+#define S_STATIC_UCLK_FREQ_SEL    18
+#define M_STATIC_UCLK_FREQ_SEL    0x3U
+#define V_STATIC_UCLK_FREQ_SEL(x) ((x) << S_STATIC_UCLK_FREQ_SEL)
+#define G_STATIC_UCLK_FREQ_SEL(x) (((x) >> S_STATIC_UCLK_FREQ_SEL) & M_STATIC_UCLK_FREQ_SEL)
+
+#define S_EXPHYCLK_SEL_EN    17
+#define V_EXPHYCLK_SEL_EN(x) ((x) << S_EXPHYCLK_SEL_EN)
+#define F_EXPHYCLK_SEL_EN    V_EXPHYCLK_SEL_EN(1U)
+
+#define S_EXPHYCLK_SEL    15
+#define M_EXPHYCLK_SEL    0x3U
+#define V_EXPHYCLK_SEL(x) ((x) << S_EXPHYCLK_SEL)
+#define G_EXPHYCLK_SEL(x) (((x) >> S_EXPHYCLK_SEL) & M_EXPHYCLK_SEL)
+
+#define S_STATIC_U_PLL_BYPASS    14
+#define V_STATIC_U_PLL_BYPASS(x) ((x) << S_STATIC_U_PLL_BYPASS)
+#define F_STATIC_U_PLL_BYPASS    V_STATIC_U_PLL_BYPASS(1U)
+
+#define S_STATIC_C_PLL_BYPASS    13
+#define V_STATIC_C_PLL_BYPASS(x) ((x) << S_STATIC_C_PLL_BYPASS)
+#define F_STATIC_C_PLL_BYPASS    V_STATIC_C_PLL_BYPASS(1U)
+
+#define S_STATIC_KR_PLL_BYPASS    12
+#define V_STATIC_KR_PLL_BYPASS(x) ((x) << S_STATIC_KR_PLL_BYPASS)
+#define F_STATIC_KR_PLL_BYPASS    V_STATIC_KR_PLL_BYPASS(1U)
+
+#define S_STATIC_KX_PLL_BYPASS    11
+#define V_STATIC_KX_PLL_BYPASS(x) ((x) << S_STATIC_KX_PLL_BYPASS)
+#define F_STATIC_KX_PLL_BYPASS    V_STATIC_KX_PLL_BYPASS(1U)
+
+#define S_STATIC_KX_PLL_V    7
+#define M_STATIC_KX_PLL_V    0xfU
+#define V_STATIC_KX_PLL_V(x) ((x) << S_STATIC_KX_PLL_V)
+#define G_STATIC_KX_PLL_V(x) (((x) >> S_STATIC_KX_PLL_V) & M_STATIC_KX_PLL_V)
+
+#define S_STATIC_KR_PLL_V    3
+#define M_STATIC_KR_PLL_V    0xfU
+#define V_STATIC_KR_PLL_V(x) ((x) << S_STATIC_KR_PLL_V)
+#define G_STATIC_KR_PLL_V(x) (((x) >> S_STATIC_KR_PLL_V) & M_STATIC_KR_PLL_V)
+
+#define S_PSRO_SEL    0
+#define M_PSRO_SEL    0x7U
+#define V_PSRO_SEL(x) ((x) << S_PSRO_SEL)
+#define G_PSRO_SEL(x) (((x) >> S_PSRO_SEL) & M_PSRO_SEL)
+
+#define A_DBG_STATIC_OCLK_MUXSEL_CONF 0x605c
+
+#define S_M_OCLK_MUXSEL    12
+#define V_M_OCLK_MUXSEL(x) ((x) << S_M_OCLK_MUXSEL)
+#define F_M_OCLK_MUXSEL    V_M_OCLK_MUXSEL(1U)
+
+#define S_C_OCLK_MUXSEL    10
+#define M_C_OCLK_MUXSEL    0x3U
+#define V_C_OCLK_MUXSEL(x) ((x) << S_C_OCLK_MUXSEL)
+#define G_C_OCLK_MUXSEL(x) (((x) >> S_C_OCLK_MUXSEL) & M_C_OCLK_MUXSEL)
+
+#define S_U_OCLK_MUXSEL    8
+#define M_U_OCLK_MUXSEL    0x3U
+#define V_U_OCLK_MUXSEL(x) ((x) << S_U_OCLK_MUXSEL)
+#define G_U_OCLK_MUXSEL(x) (((x) >> S_U_OCLK_MUXSEL) & M_U_OCLK_MUXSEL)
+
+#define S_P_OCLK_MUXSEL    6
+#define M_P_OCLK_MUXSEL    0x3U
+#define V_P_OCLK_MUXSEL(x) ((x) << S_P_OCLK_MUXSEL)
+#define G_P_OCLK_MUXSEL(x) (((x) >> S_P_OCLK_MUXSEL) & M_P_OCLK_MUXSEL)
+
+#define S_KX_OCLK_MUXSEL    3
+#define M_KX_OCLK_MUXSEL    0x7U
+#define V_KX_OCLK_MUXSEL(x) ((x) << S_KX_OCLK_MUXSEL)
+#define G_KX_OCLK_MUXSEL(x) (((x) >> S_KX_OCLK_MUXSEL) & M_KX_OCLK_MUXSEL)
+
+#define S_KR_OCLK_MUXSEL    0
+#define M_KR_OCLK_MUXSEL    0x7U
+#define V_KR_OCLK_MUXSEL(x) ((x) << S_KR_OCLK_MUXSEL)
+#define G_KR_OCLK_MUXSEL(x) (((x) >> S_KR_OCLK_MUXSEL) & M_KR_OCLK_MUXSEL)
+
+#define S_T5_P_OCLK_MUXSEL    13
+#define M_T5_P_OCLK_MUXSEL    0xfU
+#define V_T5_P_OCLK_MUXSEL(x) ((x) << S_T5_P_OCLK_MUXSEL)
+#define G_T5_P_OCLK_MUXSEL(x) (((x) >> S_T5_P_OCLK_MUXSEL) & M_T5_P_OCLK_MUXSEL)
+
+#define A_DBG_TRACE0_CONF_COMPREG0 0x6060
+#define A_DBG_TRACE0_CONF_COMPREG1 0x6064
+#define A_DBG_TRACE1_CONF_COMPREG0 0x6068
+#define A_DBG_TRACE1_CONF_COMPREG1 0x606c
+#define A_DBG_TRACE0_CONF_MASKREG0 0x6070
+#define A_DBG_TRACE0_CONF_MASKREG1 0x6074
+#define A_DBG_TRACE1_CONF_MASKREG0 0x6078
+#define A_DBG_TRACE1_CONF_MASKREG1 0x607c
+#define A_DBG_TRACE_COUNTER 0x6080
+
+#define S_COUNTER1    16
+#define M_COUNTER1    0xffffU
+#define V_COUNTER1(x) ((x) << S_COUNTER1)
+#define G_COUNTER1(x) (((x) >> S_COUNTER1) & M_COUNTER1)
+
+#define S_COUNTER0    0
+#define M_COUNTER0    0xffffU
+#define V_COUNTER0(x) ((x) << S_COUNTER0)
+#define G_COUNTER0(x) (((x) >> S_COUNTER0) & M_COUNTER0)
+
+#define A_DBG_STATIC_REFCLK_PERIOD 0x6084
+
+#define S_STATIC_REFCLK_PERIOD    0
+#define M_STATIC_REFCLK_PERIOD    0xffffU
+#define V_STATIC_REFCLK_PERIOD(x) ((x) << S_STATIC_REFCLK_PERIOD)
+#define G_STATIC_REFCLK_PERIOD(x) (((x) >> S_STATIC_REFCLK_PERIOD) & M_STATIC_REFCLK_PERIOD)
+
+#define A_DBG_TRACE_CONF 0x6088
+
+#define S_DBG_TRACE_OPERATE_WITH_TRG    5
+#define V_DBG_TRACE_OPERATE_WITH_TRG(x) ((x) << S_DBG_TRACE_OPERATE_WITH_TRG)
+#define F_DBG_TRACE_OPERATE_WITH_TRG    V_DBG_TRACE_OPERATE_WITH_TRG(1U)
+
+#define S_DBG_TRACE_OPERATE_EN    4
+#define V_DBG_TRACE_OPERATE_EN(x) ((x) << S_DBG_TRACE_OPERATE_EN)
+#define F_DBG_TRACE_OPERATE_EN    V_DBG_TRACE_OPERATE_EN(1U)
+
+#define S_DBG_OPERATE_INDV_COMBINED    3
+#define V_DBG_OPERATE_INDV_COMBINED(x) ((x) << S_DBG_OPERATE_INDV_COMBINED)
+#define F_DBG_OPERATE_INDV_COMBINED    V_DBG_OPERATE_INDV_COMBINED(1U)
+
+#define S_DBG_OPERATE_ORDER_OF_TRIGGER    2
+#define V_DBG_OPERATE_ORDER_OF_TRIGGER(x) ((x) << S_DBG_OPERATE_ORDER_OF_TRIGGER)
+#define F_DBG_OPERATE_ORDER_OF_TRIGGER    V_DBG_OPERATE_ORDER_OF_TRIGGER(1U)
+
+#define S_DBG_OPERATE_SGL_DBL_TRIGGER    1
+#define V_DBG_OPERATE_SGL_DBL_TRIGGER(x) ((x) << S_DBG_OPERATE_SGL_DBL_TRIGGER)
+#define F_DBG_OPERATE_SGL_DBL_TRIGGER    V_DBG_OPERATE_SGL_DBL_TRIGGER(1U)
+
+#define S_DBG_OPERATE0_OR_1    0
+#define V_DBG_OPERATE0_OR_1(x) ((x) << S_DBG_OPERATE0_OR_1)
+#define F_DBG_OPERATE0_OR_1    V_DBG_OPERATE0_OR_1(1U)
+
+#define A_DBG_TRACE_RDEN 0x608c
+
+#define S_RD_ADDR1    10
+#define M_RD_ADDR1    0xffU
+#define V_RD_ADDR1(x) ((x) << S_RD_ADDR1)
+#define G_RD_ADDR1(x) (((x) >> S_RD_ADDR1) & M_RD_ADDR1)
+
+#define S_RD_ADDR0    2
+#define M_RD_ADDR0    0xffU
+#define V_RD_ADDR0(x) ((x) << S_RD_ADDR0)
+#define G_RD_ADDR0(x) (((x) >> S_RD_ADDR0) & M_RD_ADDR0)
+
+#define S_RD_EN1    1
+#define V_RD_EN1(x) ((x) << S_RD_EN1)
+#define F_RD_EN1    V_RD_EN1(1U)
+
+#define S_RD_EN0    0
+#define V_RD_EN0(x) ((x) << S_RD_EN0)
+#define F_RD_EN0    V_RD_EN0(1U)
+
+#define A_DBG_TRACE_WRADDR 0x6090
+
+#define S_WR_POINTER_ADDR1    16
+#define M_WR_POINTER_ADDR1    0xffU
+#define V_WR_POINTER_ADDR1(x) ((x) << S_WR_POINTER_ADDR1)
+#define G_WR_POINTER_ADDR1(x) (((x) >> S_WR_POINTER_ADDR1) & M_WR_POINTER_ADDR1)
+
+#define S_WR_POINTER_ADDR0    0
+#define M_WR_POINTER_ADDR0    0xffU
+#define V_WR_POINTER_ADDR0(x) ((x) << S_WR_POINTER_ADDR0)
+#define G_WR_POINTER_ADDR0(x) (((x) >> S_WR_POINTER_ADDR0) & M_WR_POINTER_ADDR0)
+
+#define A_DBG_TRACE0_DATA_OUT 0x6094
+#define A_DBG_TRACE1_DATA_OUT 0x6098
+#define A_DBG_FUSE_SENSE_DONE 0x609c
+
+#define S_STATIC_JTAG_VERSIONNR    5
+#define M_STATIC_JTAG_VERSIONNR    0xfU
+#define V_STATIC_JTAG_VERSIONNR(x) ((x) << S_STATIC_JTAG_VERSIONNR)
+#define G_STATIC_JTAG_VERSIONNR(x) (((x) >> S_STATIC_JTAG_VERSIONNR) & M_STATIC_JTAG_VERSIONNR)
+
+#define S_UNQ0    1
+#define M_UNQ0    0xfU
+#define V_UNQ0(x) ((x) << S_UNQ0)
+#define G_UNQ0(x) (((x) >> S_UNQ0) & M_UNQ0)
+
+#define S_FUSE_DONE_SENSE    0
+#define V_FUSE_DONE_SENSE(x) ((x) << S_FUSE_DONE_SENSE)
+#define F_FUSE_DONE_SENSE    V_FUSE_DONE_SENSE(1U)
+
+#define A_DBG_TVSENSE_EN 0x60a8
+
+#define S_MCIMPED1_OUT    29
+#define V_MCIMPED1_OUT(x) ((x) << S_MCIMPED1_OUT)
+#define F_MCIMPED1_OUT    V_MCIMPED1_OUT(1U)
+
+#define S_MCIMPED2_OUT    28
+#define V_MCIMPED2_OUT(x) ((x) << S_MCIMPED2_OUT)
+#define F_MCIMPED2_OUT    V_MCIMPED2_OUT(1U)
+
+#define S_TVSENSE_SNSOUT    17
+#define M_TVSENSE_SNSOUT    0x1ffU
+#define V_TVSENSE_SNSOUT(x) ((x) << S_TVSENSE_SNSOUT)
+#define G_TVSENSE_SNSOUT(x) (((x) >> S_TVSENSE_SNSOUT) & M_TVSENSE_SNSOUT)
+
+#define S_TVSENSE_OUTPUTVALID    16
+#define V_TVSENSE_OUTPUTVALID(x) ((x) << S_TVSENSE_OUTPUTVALID)
+#define F_TVSENSE_OUTPUTVALID    V_TVSENSE_OUTPUTVALID(1U)
+
+#define S_TVSENSE_SLEEP    10
+#define V_TVSENSE_SLEEP(x) ((x) << S_TVSENSE_SLEEP)
+#define F_TVSENSE_SLEEP    V_TVSENSE_SLEEP(1U)
+
+#define S_TVSENSE_SENSV    9
+#define V_TVSENSE_SENSV(x) ((x) << S_TVSENSE_SENSV)
+#define F_TVSENSE_SENSV    V_TVSENSE_SENSV(1U)
+
+#define S_TVSENSE_RST    8
+#define V_TVSENSE_RST(x) ((x) << S_TVSENSE_RST)
+#define F_TVSENSE_RST    V_TVSENSE_RST(1U)
+
+#define S_TVSENSE_RATIO    0
+#define M_TVSENSE_RATIO    0xffU
+#define V_TVSENSE_RATIO(x) ((x) << S_TVSENSE_RATIO)
+#define G_TVSENSE_RATIO(x) (((x) >> S_TVSENSE_RATIO) & M_TVSENSE_RATIO)
+
+#define A_DBG_CUST_EFUSE_OUT_EN 0x60ac
+#define A_DBG_CUST_EFUSE_SEL1_EN 0x60b0
+#define A_DBG_CUST_EFUSE_SEL2_EN 0x60b4
+
+#define S_DBG_FEENABLE    29
+#define V_DBG_FEENABLE(x) ((x) << S_DBG_FEENABLE)
+#define F_DBG_FEENABLE    V_DBG_FEENABLE(1U)
+
+#define S_DBG_FEF    23
+#define M_DBG_FEF    0x3fU
+#define V_DBG_FEF(x) ((x) << S_DBG_FEF)
+#define G_DBG_FEF(x) (((x) >> S_DBG_FEF) & M_DBG_FEF)
+
+#define S_DBG_FEMIMICN    22
+#define V_DBG_FEMIMICN(x) ((x) << S_DBG_FEMIMICN)
+#define F_DBG_FEMIMICN    V_DBG_FEMIMICN(1U)
+
+#define S_DBG_FEGATEC    21
+#define V_DBG_FEGATEC(x) ((x) << S_DBG_FEGATEC)
+#define F_DBG_FEGATEC    V_DBG_FEGATEC(1U)
+
+#define S_DBG_FEPROGP    20
+#define V_DBG_FEPROGP(x) ((x) << S_DBG_FEPROGP)
+#define F_DBG_FEPROGP    V_DBG_FEPROGP(1U)
+
+#define S_DBG_FEREADCLK    19
+#define V_DBG_FEREADCLK(x) ((x) << S_DBG_FEREADCLK)
+#define F_DBG_FEREADCLK    V_DBG_FEREADCLK(1U)
+
+#define S_DBG_FERSEL    3
+#define M_DBG_FERSEL    0xffffU
+#define V_DBG_FERSEL(x) ((x) << S_DBG_FERSEL)
+#define G_DBG_FERSEL(x) (((x) >> S_DBG_FERSEL) & M_DBG_FERSEL)
+
+#define S_DBG_FETIME    0
+#define M_DBG_FETIME    0x7U
+#define V_DBG_FETIME(x) ((x) << S_DBG_FETIME)
+#define G_DBG_FETIME(x) (((x) >> S_DBG_FETIME) & M_DBG_FETIME)
+
+#define A_DBG_T5_STATIC_M_PLL_CONF1 0x60b8
+
+#define S_T5_STATIC_M_PLL_MULTFRAC    8
+#define M_T5_STATIC_M_PLL_MULTFRAC    0xffffffU
+#define V_T5_STATIC_M_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_M_PLL_MULTFRAC)
+#define G_T5_STATIC_M_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_M_PLL_MULTFRAC) & M_T5_STATIC_M_PLL_MULTFRAC)
+
+#define S_T5_STATIC_M_PLL_FFSLEWRATE    0
+#define M_T5_STATIC_M_PLL_FFSLEWRATE    0xffU
+#define V_T5_STATIC_M_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_M_PLL_FFSLEWRATE)
+#define G_T5_STATIC_M_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_M_PLL_FFSLEWRATE) & M_T5_STATIC_M_PLL_FFSLEWRATE)
+
+#define A_DBG_T5_STATIC_M_PLL_CONF2 0x60bc
+
+#define S_T5_STATIC_M_PLL_DCO_BYPASS    23
+#define V_T5_STATIC_M_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_M_PLL_DCO_BYPASS)
+#define F_T5_STATIC_M_PLL_DCO_BYPASS    V_T5_STATIC_M_PLL_DCO_BYPASS(1U)
+
+#define S_T5_STATIC_M_PLL_SDORDER    21
+#define M_T5_STATIC_M_PLL_SDORDER    0x3U
+#define V_T5_STATIC_M_PLL_SDORDER(x) ((x) << S_T5_STATIC_M_PLL_SDORDER)
+#define G_T5_STATIC_M_PLL_SDORDER(x) (((x) >> S_T5_STATIC_M_PLL_SDORDER) & M_T5_STATIC_M_PLL_SDORDER)
+
+#define S_T5_STATIC_M_PLL_FFENABLE    20
+#define V_T5_STATIC_M_PLL_FFENABLE(x) ((x) << S_T5_STATIC_M_PLL_FFENABLE)
+#define F_T5_STATIC_M_PLL_FFENABLE    V_T5_STATIC_M_PLL_FFENABLE(1U)
+
+#define S_T5_STATIC_M_PLL_STOPCLKB    19
+#define V_T5_STATIC_M_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_M_PLL_STOPCLKB)
+#define F_T5_STATIC_M_PLL_STOPCLKB    V_T5_STATIC_M_PLL_STOPCLKB(1U)
+
+#define S_T5_STATIC_M_PLL_STOPCLKA    18
+#define V_T5_STATIC_M_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_M_PLL_STOPCLKA)
+#define F_T5_STATIC_M_PLL_STOPCLKA    V_T5_STATIC_M_PLL_STOPCLKA(1U)
+
+#define S_T5_STATIC_M_PLL_SLEEP    17
+#define V_T5_STATIC_M_PLL_SLEEP(x) ((x) << S_T5_STATIC_M_PLL_SLEEP)
+#define F_T5_STATIC_M_PLL_SLEEP    V_T5_STATIC_M_PLL_SLEEP(1U)
+
+#define S_T5_STATIC_M_PLL_BYPASS    16
+#define V_T5_STATIC_M_PLL_BYPASS(x) ((x) << S_T5_STATIC_M_PLL_BYPASS)
+#define F_T5_STATIC_M_PLL_BYPASS    V_T5_STATIC_M_PLL_BYPASS(1U)
+
+#define S_T5_STATIC_M_PLL_LOCKTUNE    0
+#define M_T5_STATIC_M_PLL_LOCKTUNE    0xffffU
+#define V_T5_STATIC_M_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_M_PLL_LOCKTUNE)
+#define G_T5_STATIC_M_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_M_PLL_LOCKTUNE) & M_T5_STATIC_M_PLL_LOCKTUNE)
+
+#define A_DBG_T5_STATIC_M_PLL_CONF3 0x60c0
+
+#define S_T5_STATIC_M_PLL_MULTPRE    30
+#define M_T5_STATIC_M_PLL_MULTPRE    0x3U
+#define V_T5_STATIC_M_PLL_MULTPRE(x) ((x) << S_T5_STATIC_M_PLL_MULTPRE)
+#define G_T5_STATIC_M_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_M_PLL_MULTPRE) & M_T5_STATIC_M_PLL_MULTPRE)
+
+#define S_T5_STATIC_M_PLL_LOCKSEL    28
+#define M_T5_STATIC_M_PLL_LOCKSEL    0x3U
+#define V_T5_STATIC_M_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_M_PLL_LOCKSEL)
+#define G_T5_STATIC_M_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_M_PLL_LOCKSEL) & M_T5_STATIC_M_PLL_LOCKSEL)
+
+#define S_T5_STATIC_M_PLL_FFTUNE    12
+#define M_T5_STATIC_M_PLL_FFTUNE    0xffffU
+#define V_T5_STATIC_M_PLL_FFTUNE(x) ((x) << S_T5_STATIC_M_PLL_FFTUNE)
+#define G_T5_STATIC_M_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_M_PLL_FFTUNE) & M_T5_STATIC_M_PLL_FFTUNE)
+
+#define S_T5_STATIC_M_PLL_RANGEPRE    10
+#define M_T5_STATIC_M_PLL_RANGEPRE    0x3U
+#define V_T5_STATIC_M_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_M_PLL_RANGEPRE)
+#define G_T5_STATIC_M_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_M_PLL_RANGEPRE) & M_T5_STATIC_M_PLL_RANGEPRE)
+
+#define S_T5_STATIC_M_PLL_RANGEB    5
+#define M_T5_STATIC_M_PLL_RANGEB    0x1fU
+#define V_T5_STATIC_M_PLL_RANGEB(x) ((x) << S_T5_STATIC_M_PLL_RANGEB)
+#define G_T5_STATIC_M_PLL_RANGEB(x) (((x) >> S_T5_STATIC_M_PLL_RANGEB) & M_T5_STATIC_M_PLL_RANGEB)
+
+#define S_T5_STATIC_M_PLL_RANGEA    0
+#define M_T5_STATIC_M_PLL_RANGEA    0x1fU
+#define V_T5_STATIC_M_PLL_RANGEA(x) ((x) << S_T5_STATIC_M_PLL_RANGEA)
+#define G_T5_STATIC_M_PLL_RANGEA(x) (((x) >> S_T5_STATIC_M_PLL_RANGEA) & M_T5_STATIC_M_PLL_RANGEA)
+
+#define A_DBG_T5_STATIC_M_PLL_CONF4 0x60c4
+#define A_DBG_T5_STATIC_M_PLL_CONF5 0x60c8
+
+#define S_T5_STATIC_M_PLL_VCVTUNE    24
+#define M_T5_STATIC_M_PLL_VCVTUNE    0x7U
+#define V_T5_STATIC_M_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_M_PLL_VCVTUNE)
+#define G_T5_STATIC_M_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_M_PLL_VCVTUNE) & M_T5_STATIC_M_PLL_VCVTUNE)
+
+#define S_T5_STATIC_M_PLL_RESET    23
+#define V_T5_STATIC_M_PLL_RESET(x) ((x) << S_T5_STATIC_M_PLL_RESET)
+#define F_T5_STATIC_M_PLL_RESET    V_T5_STATIC_M_PLL_RESET(1U)
+
+#define S_T5_STATIC_MPLL_REFCLK_SEL    22
+#define V_T5_STATIC_MPLL_REFCLK_SEL(x) ((x) << S_T5_STATIC_MPLL_REFCLK_SEL)
+#define F_T5_STATIC_MPLL_REFCLK_SEL    V_T5_STATIC_MPLL_REFCLK_SEL(1U)
+
+#define S_T5_STATIC_M_PLL_LFTUNE_32_40    13
+#define M_T5_STATIC_M_PLL_LFTUNE_32_40    0x1ffU
+#define V_T5_STATIC_M_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_M_PLL_LFTUNE_32_40)
+#define G_T5_STATIC_M_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_M_PLL_LFTUNE_32_40) & M_T5_STATIC_M_PLL_LFTUNE_32_40)
+
+#define S_T5_STATIC_M_PLL_PREDIV    8
+#define M_T5_STATIC_M_PLL_PREDIV    0x1fU
+#define V_T5_STATIC_M_PLL_PREDIV(x) ((x) << S_T5_STATIC_M_PLL_PREDIV)
+#define G_T5_STATIC_M_PLL_PREDIV(x) (((x) >> S_T5_STATIC_M_PLL_PREDIV) & M_T5_STATIC_M_PLL_PREDIV)
+
+#define S_T5_STATIC_M_PLL_MULT    0
+#define M_T5_STATIC_M_PLL_MULT    0xffU
+#define V_T5_STATIC_M_PLL_MULT(x) ((x) << S_T5_STATIC_M_PLL_MULT)
+#define G_T5_STATIC_M_PLL_MULT(x) (((x) >> S_T5_STATIC_M_PLL_MULT) & M_T5_STATIC_M_PLL_MULT)
+
+#define A_DBG_T5_STATIC_M_PLL_CONF6 0x60cc
+
+#define S_T5_STATIC_PHY0RECRST_    5
+#define V_T5_STATIC_PHY0RECRST_(x) ((x) << S_T5_STATIC_PHY0RECRST_)
+#define F_T5_STATIC_PHY0RECRST_    V_T5_STATIC_PHY0RECRST_(1U)
+
+#define S_T5_STATIC_PHY1RECRST_    4
+#define V_T5_STATIC_PHY1RECRST_(x) ((x) << S_T5_STATIC_PHY1RECRST_)
+#define F_T5_STATIC_PHY1RECRST_    V_T5_STATIC_PHY1RECRST_(1U)
+
+#define S_T5_STATIC_SWMC0RST_    3
+#define V_T5_STATIC_SWMC0RST_(x) ((x) << S_T5_STATIC_SWMC0RST_)
+#define F_T5_STATIC_SWMC0RST_    V_T5_STATIC_SWMC0RST_(1U)
+
+#define S_T5_STATIC_SWMC0CFGRST_    2
+#define V_T5_STATIC_SWMC0CFGRST_(x) ((x) << S_T5_STATIC_SWMC0CFGRST_)
+#define F_T5_STATIC_SWMC0CFGRST_    V_T5_STATIC_SWMC0CFGRST_(1U)
+
+#define S_T5_STATIC_SWMC1RST_    1
+#define V_T5_STATIC_SWMC1RST_(x) ((x) << S_T5_STATIC_SWMC1RST_)
+#define F_T5_STATIC_SWMC1RST_    V_T5_STATIC_SWMC1RST_(1U)
+
+#define S_T5_STATIC_SWMC1CFGRST_    0
+#define V_T5_STATIC_SWMC1CFGRST_(x) ((x) << S_T5_STATIC_SWMC1CFGRST_)
+#define F_T5_STATIC_SWMC1CFGRST_    V_T5_STATIC_SWMC1CFGRST_(1U)
+
+#define A_DBG_T5_STATIC_C_PLL_CONF1 0x60d0
+
+#define S_T5_STATIC_C_PLL_MULTFRAC    8
+#define M_T5_STATIC_C_PLL_MULTFRAC    0xffffffU
+#define V_T5_STATIC_C_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_C_PLL_MULTFRAC)
+#define G_T5_STATIC_C_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_C_PLL_MULTFRAC) & M_T5_STATIC_C_PLL_MULTFRAC)
+
+#define S_T5_STATIC_C_PLL_FFSLEWRATE    0
+#define M_T5_STATIC_C_PLL_FFSLEWRATE    0xffU
+#define V_T5_STATIC_C_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_C_PLL_FFSLEWRATE)
+#define G_T5_STATIC_C_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_C_PLL_FFSLEWRATE) & M_T5_STATIC_C_PLL_FFSLEWRATE)
+
+#define A_DBG_T5_STATIC_C_PLL_CONF2 0x60d4
+
+#define S_T5_STATIC_C_PLL_DCO_BYPASS    23
+#define V_T5_STATIC_C_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_C_PLL_DCO_BYPASS)
+#define F_T5_STATIC_C_PLL_DCO_BYPASS    V_T5_STATIC_C_PLL_DCO_BYPASS(1U)
+
+#define S_T5_STATIC_C_PLL_SDORDER    21
+#define M_T5_STATIC_C_PLL_SDORDER    0x3U
+#define V_T5_STATIC_C_PLL_SDORDER(x) ((x) << S_T5_STATIC_C_PLL_SDORDER)
+#define G_T5_STATIC_C_PLL_SDORDER(x) (((x) >> S_T5_STATIC_C_PLL_SDORDER) & M_T5_STATIC_C_PLL_SDORDER)
+
+#define S_T5_STATIC_C_PLL_FFENABLE    20
+#define V_T5_STATIC_C_PLL_FFENABLE(x) ((x) << S_T5_STATIC_C_PLL_FFENABLE)
+#define F_T5_STATIC_C_PLL_FFENABLE    V_T5_STATIC_C_PLL_FFENABLE(1U)
+
+#define S_T5_STATIC_C_PLL_STOPCLKB    19
+#define V_T5_STATIC_C_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_C_PLL_STOPCLKB)
+#define F_T5_STATIC_C_PLL_STOPCLKB    V_T5_STATIC_C_PLL_STOPCLKB(1U)
+
+#define S_T5_STATIC_C_PLL_STOPCLKA    18
+#define V_T5_STATIC_C_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_C_PLL_STOPCLKA)
+#define F_T5_STATIC_C_PLL_STOPCLKA    V_T5_STATIC_C_PLL_STOPCLKA(1U)
+
+#define S_T5_STATIC_C_PLL_SLEEP    17
+#define V_T5_STATIC_C_PLL_SLEEP(x) ((x) << S_T5_STATIC_C_PLL_SLEEP)
+#define F_T5_STATIC_C_PLL_SLEEP    V_T5_STATIC_C_PLL_SLEEP(1U)
+
+#define S_T5_STATIC_C_PLL_BYPASS    16
+#define V_T5_STATIC_C_PLL_BYPASS(x) ((x) << S_T5_STATIC_C_PLL_BYPASS)
+#define F_T5_STATIC_C_PLL_BYPASS    V_T5_STATIC_C_PLL_BYPASS(1U)
+
+#define S_T5_STATIC_C_PLL_LOCKTUNE    0
+#define M_T5_STATIC_C_PLL_LOCKTUNE    0xffffU
+#define V_T5_STATIC_C_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_C_PLL_LOCKTUNE)
+#define G_T5_STATIC_C_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_C_PLL_LOCKTUNE) & M_T5_STATIC_C_PLL_LOCKTUNE)
+
+#define A_DBG_T5_STATIC_C_PLL_CONF3 0x60d8
+
+#define S_T5_STATIC_C_PLL_MULTPRE    30
+#define M_T5_STATIC_C_PLL_MULTPRE    0x3U
+#define V_T5_STATIC_C_PLL_MULTPRE(x) ((x) << S_T5_STATIC_C_PLL_MULTPRE)
+#define G_T5_STATIC_C_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_C_PLL_MULTPRE) & M_T5_STATIC_C_PLL_MULTPRE)
+
+#define S_T5_STATIC_C_PLL_LOCKSEL    28
+#define M_T5_STATIC_C_PLL_LOCKSEL    0x3U
+#define V_T5_STATIC_C_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_C_PLL_LOCKSEL)
+#define G_T5_STATIC_C_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_C_PLL_LOCKSEL) & M_T5_STATIC_C_PLL_LOCKSEL)
+
+#define S_T5_STATIC_C_PLL_FFTUNE    12
+#define M_T5_STATIC_C_PLL_FFTUNE    0xffffU
+#define V_T5_STATIC_C_PLL_FFTUNE(x) ((x) << S_T5_STATIC_C_PLL_FFTUNE)
+#define G_T5_STATIC_C_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_C_PLL_FFTUNE) & M_T5_STATIC_C_PLL_FFTUNE)
+
+#define S_T5_STATIC_C_PLL_RANGEPRE    10
+#define M_T5_STATIC_C_PLL_RANGEPRE    0x3U
+#define V_T5_STATIC_C_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_C_PLL_RANGEPRE)
+#define G_T5_STATIC_C_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_C_PLL_RANGEPRE) & M_T5_STATIC_C_PLL_RANGEPRE)
+
+#define S_T5_STATIC_C_PLL_RANGEB    5
+#define M_T5_STATIC_C_PLL_RANGEB    0x1fU
+#define V_T5_STATIC_C_PLL_RANGEB(x) ((x) << S_T5_STATIC_C_PLL_RANGEB)
+#define G_T5_STATIC_C_PLL_RANGEB(x) (((x) >> S_T5_STATIC_C_PLL_RANGEB) & M_T5_STATIC_C_PLL_RANGEB)
+
+#define S_T5_STATIC_C_PLL_RANGEA    0
+#define M_T5_STATIC_C_PLL_RANGEA    0x1fU
+#define V_T5_STATIC_C_PLL_RANGEA(x) ((x) << S_T5_STATIC_C_PLL_RANGEA)
+#define G_T5_STATIC_C_PLL_RANGEA(x) (((x) >> S_T5_STATIC_C_PLL_RANGEA) & M_T5_STATIC_C_PLL_RANGEA)
+
+#define A_DBG_T5_STATIC_C_PLL_CONF4 0x60dc
+#define A_DBG_T5_STATIC_C_PLL_CONF5 0x60e0
+
+#define S_T5_STATIC_C_PLL_VCVTUNE    22
+#define M_T5_STATIC_C_PLL_VCVTUNE    0x7U
+#define V_T5_STATIC_C_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_C_PLL_VCVTUNE)
+#define G_T5_STATIC_C_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_C_PLL_VCVTUNE) & M_T5_STATIC_C_PLL_VCVTUNE)
+
+#define S_T5_STATIC_C_PLL_LFTUNE_32_40    13
+#define M_T5_STATIC_C_PLL_LFTUNE_32_40    0x1ffU
+#define V_T5_STATIC_C_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_C_PLL_LFTUNE_32_40)
+#define G_T5_STATIC_C_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_C_PLL_LFTUNE_32_40) & M_T5_STATIC_C_PLL_LFTUNE_32_40)
+
+#define S_T5_STATIC_C_PLL_PREDIV    8
+#define M_T5_STATIC_C_PLL_PREDIV    0x1fU
+#define V_T5_STATIC_C_PLL_PREDIV(x) ((x) << S_T5_STATIC_C_PLL_PREDIV)
+#define G_T5_STATIC_C_PLL_PREDIV(x) (((x) >> S_T5_STATIC_C_PLL_PREDIV) & M_T5_STATIC_C_PLL_PREDIV)
+
+#define S_T5_STATIC_C_PLL_MULT    0
+#define M_T5_STATIC_C_PLL_MULT    0xffU
+#define V_T5_STATIC_C_PLL_MULT(x) ((x) << S_T5_STATIC_C_PLL_MULT)
+#define G_T5_STATIC_C_PLL_MULT(x) (((x) >> S_T5_STATIC_C_PLL_MULT) & M_T5_STATIC_C_PLL_MULT)
+
+#define A_DBG_T5_STATIC_U_PLL_CONF1 0x60e4
+
+#define S_T5_STATIC_U_PLL_MULTFRAC    8
+#define M_T5_STATIC_U_PLL_MULTFRAC    0xffffffU
+#define V_T5_STATIC_U_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_U_PLL_MULTFRAC)
+#define G_T5_STATIC_U_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_U_PLL_MULTFRAC) & M_T5_STATIC_U_PLL_MULTFRAC)
+
+#define S_T5_STATIC_U_PLL_FFSLEWRATE    0
+#define M_T5_STATIC_U_PLL_FFSLEWRATE    0xffU
+#define V_T5_STATIC_U_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_U_PLL_FFSLEWRATE)
+#define G_T5_STATIC_U_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_U_PLL_FFSLEWRATE) & M_T5_STATIC_U_PLL_FFSLEWRATE)
+
+#define A_DBG_T5_STATIC_U_PLL_CONF2 0x60e8
+
+#define S_T5_STATIC_U_PLL_DCO_BYPASS    23
+#define V_T5_STATIC_U_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_U_PLL_DCO_BYPASS)
+#define F_T5_STATIC_U_PLL_DCO_BYPASS    V_T5_STATIC_U_PLL_DCO_BYPASS(1U)
+
+#define S_T5_STATIC_U_PLL_SDORDER    21
+#define M_T5_STATIC_U_PLL_SDORDER    0x3U
+#define V_T5_STATIC_U_PLL_SDORDER(x) ((x) << S_T5_STATIC_U_PLL_SDORDER)
+#define G_T5_STATIC_U_PLL_SDORDER(x) (((x) >> S_T5_STATIC_U_PLL_SDORDER) & M_T5_STATIC_U_PLL_SDORDER)
+
+#define S_T5_STATIC_U_PLL_FFENABLE    20
+#define V_T5_STATIC_U_PLL_FFENABLE(x) ((x) << S_T5_STATIC_U_PLL_FFENABLE)
+#define F_T5_STATIC_U_PLL_FFENABLE    V_T5_STATIC_U_PLL_FFENABLE(1U)
+
+#define S_T5_STATIC_U_PLL_STOPCLKB    19
+#define V_T5_STATIC_U_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_U_PLL_STOPCLKB)
+#define F_T5_STATIC_U_PLL_STOPCLKB    V_T5_STATIC_U_PLL_STOPCLKB(1U)
+
+#define S_T5_STATIC_U_PLL_STOPCLKA    18
+#define V_T5_STATIC_U_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_U_PLL_STOPCLKA)
+#define F_T5_STATIC_U_PLL_STOPCLKA    V_T5_STATIC_U_PLL_STOPCLKA(1U)
+
+#define S_T5_STATIC_U_PLL_SLEEP    17
+#define V_T5_STATIC_U_PLL_SLEEP(x) ((x) << S_T5_STATIC_U_PLL_SLEEP)
+#define F_T5_STATIC_U_PLL_SLEEP    V_T5_STATIC_U_PLL_SLEEP(1U)
+
+#define S_T5_STATIC_U_PLL_BYPASS    16
+#define V_T5_STATIC_U_PLL_BYPASS(x) ((x) << S_T5_STATIC_U_PLL_BYPASS)
+#define F_T5_STATIC_U_PLL_BYPASS    V_T5_STATIC_U_PLL_BYPASS(1U)
+
+#define S_T5_STATIC_U_PLL_LOCKTUNE    0
+#define M_T5_STATIC_U_PLL_LOCKTUNE    0xffffU
+#define V_T5_STATIC_U_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_U_PLL_LOCKTUNE)
+#define G_T5_STATIC_U_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_U_PLL_LOCKTUNE) & M_T5_STATIC_U_PLL_LOCKTUNE)
+
+#define A_DBG_T5_STATIC_U_PLL_CONF3 0x60ec
+
+#define S_T5_STATIC_U_PLL_MULTPRE    30
+#define M_T5_STATIC_U_PLL_MULTPRE    0x3U
+#define V_T5_STATIC_U_PLL_MULTPRE(x) ((x) << S_T5_STATIC_U_PLL_MULTPRE)
+#define G_T5_STATIC_U_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_U_PLL_MULTPRE) & M_T5_STATIC_U_PLL_MULTPRE)
+
+#define S_T5_STATIC_U_PLL_LOCKSEL    28
+#define M_T5_STATIC_U_PLL_LOCKSEL    0x3U
+#define V_T5_STATIC_U_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_U_PLL_LOCKSEL)
+#define G_T5_STATIC_U_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_U_PLL_LOCKSEL) & M_T5_STATIC_U_PLL_LOCKSEL)
+
+#define S_T5_STATIC_U_PLL_FFTUNE    12
+#define M_T5_STATIC_U_PLL_FFTUNE    0xffffU
+#define V_T5_STATIC_U_PLL_FFTUNE(x) ((x) << S_T5_STATIC_U_PLL_FFTUNE)
+#define G_T5_STATIC_U_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_U_PLL_FFTUNE) & M_T5_STATIC_U_PLL_FFTUNE)
+
+#define S_T5_STATIC_U_PLL_RANGEPRE    10
+#define M_T5_STATIC_U_PLL_RANGEPRE    0x3U
+#define V_T5_STATIC_U_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_U_PLL_RANGEPRE)
+#define G_T5_STATIC_U_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_U_PLL_RANGEPRE) & M_T5_STATIC_U_PLL_RANGEPRE)
+
+#define S_T5_STATIC_U_PLL_RANGEB    5
+#define M_T5_STATIC_U_PLL_RANGEB    0x1fU
+#define V_T5_STATIC_U_PLL_RANGEB(x) ((x) << S_T5_STATIC_U_PLL_RANGEB)
+#define G_T5_STATIC_U_PLL_RANGEB(x) (((x) >> S_T5_STATIC_U_PLL_RANGEB) & M_T5_STATIC_U_PLL_RANGEB)
+
+#define S_T5_STATIC_U_PLL_RANGEA    0
+#define M_T5_STATIC_U_PLL_RANGEA    0x1fU
+#define V_T5_STATIC_U_PLL_RANGEA(x) ((x) << S_T5_STATIC_U_PLL_RANGEA)
+#define G_T5_STATIC_U_PLL_RANGEA(x) (((x) >> S_T5_STATIC_U_PLL_RANGEA) & M_T5_STATIC_U_PLL_RANGEA)
+
+#define A_DBG_T5_STATIC_U_PLL_CONF4 0x60f0
+#define A_DBG_T5_STATIC_U_PLL_CONF5 0x60f4
+
+#define S_T5_STATIC_U_PLL_VCVTUNE    22
+#define M_T5_STATIC_U_PLL_VCVTUNE    0x7U
+#define V_T5_STATIC_U_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_U_PLL_VCVTUNE)
+#define G_T5_STATIC_U_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_U_PLL_VCVTUNE) & M_T5_STATIC_U_PLL_VCVTUNE)
+
+#define S_T5_STATIC_U_PLL_LFTUNE_32_40    13
+#define M_T5_STATIC_U_PLL_LFTUNE_32_40    0x1ffU
+#define V_T5_STATIC_U_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_U_PLL_LFTUNE_32_40)
+#define G_T5_STATIC_U_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_U_PLL_LFTUNE_32_40) & M_T5_STATIC_U_PLL_LFTUNE_32_40)
+
+#define S_T5_STATIC_U_PLL_PREDIV    8
+#define M_T5_STATIC_U_PLL_PREDIV    0x1fU
+#define V_T5_STATIC_U_PLL_PREDIV(x) ((x) << S_T5_STATIC_U_PLL_PREDIV)
+#define G_T5_STATIC_U_PLL_PREDIV(x) (((x) >> S_T5_STATIC_U_PLL_PREDIV) & M_T5_STATIC_U_PLL_PREDIV)
+
+#define S_T5_STATIC_U_PLL_MULT    0
+#define M_T5_STATIC_U_PLL_MULT    0xffU
+#define V_T5_STATIC_U_PLL_MULT(x) ((x) << S_T5_STATIC_U_PLL_MULT)
+#define G_T5_STATIC_U_PLL_MULT(x) (((x) >> S_T5_STATIC_U_PLL_MULT) & M_T5_STATIC_U_PLL_MULT)
+
+#define A_DBG_T5_STATIC_KR_PLL_CONF1 0x60f8
+
+#define S_T5_STATIC_KR_PLL_BYPASS    30
+#define V_T5_STATIC_KR_PLL_BYPASS(x) ((x) << S_T5_STATIC_KR_PLL_BYPASS)
+#define F_T5_STATIC_KR_PLL_BYPASS    V_T5_STATIC_KR_PLL_BYPASS(1U)
+
+#define S_T5_STATIC_KR_PLL_VBOOSTDIV    27
+#define M_T5_STATIC_KR_PLL_VBOOSTDIV    0x7U
+#define V_T5_STATIC_KR_PLL_VBOOSTDIV(x) ((x) << S_T5_STATIC_KR_PLL_VBOOSTDIV)
+#define G_T5_STATIC_KR_PLL_VBOOSTDIV(x) (((x) >> S_T5_STATIC_KR_PLL_VBOOSTDIV) & M_T5_STATIC_KR_PLL_VBOOSTDIV)
+
+#define S_T5_STATIC_KR_PLL_CPISEL    24
+#define M_T5_STATIC_KR_PLL_CPISEL    0x7U
+#define V_T5_STATIC_KR_PLL_CPISEL(x) ((x) << S_T5_STATIC_KR_PLL_CPISEL)
+#define G_T5_STATIC_KR_PLL_CPISEL(x) (((x) >> S_T5_STATIC_KR_PLL_CPISEL) & M_T5_STATIC_KR_PLL_CPISEL)
+
+#define S_T5_STATIC_KR_PLL_CCALMETHOD    23
+#define V_T5_STATIC_KR_PLL_CCALMETHOD(x) ((x) << S_T5_STATIC_KR_PLL_CCALMETHOD)
+#define F_T5_STATIC_KR_PLL_CCALMETHOD    V_T5_STATIC_KR_PLL_CCALMETHOD(1U)
+
+#define S_T5_STATIC_KR_PLL_CCALLOAD    22
+#define V_T5_STATIC_KR_PLL_CCALLOAD(x) ((x) << S_T5_STATIC_KR_PLL_CCALLOAD)
+#define F_T5_STATIC_KR_PLL_CCALLOAD    V_T5_STATIC_KR_PLL_CCALLOAD(1U)
+
+#define S_T5_STATIC_KR_PLL_CCALFMIN    21
+#define V_T5_STATIC_KR_PLL_CCALFMIN(x) ((x) << S_T5_STATIC_KR_PLL_CCALFMIN)
+#define F_T5_STATIC_KR_PLL_CCALFMIN    V_T5_STATIC_KR_PLL_CCALFMIN(1U)
+
+#define S_T5_STATIC_KR_PLL_CCALFMAX    20
+#define V_T5_STATIC_KR_PLL_CCALFMAX(x) ((x) << S_T5_STATIC_KR_PLL_CCALFMAX)
+#define F_T5_STATIC_KR_PLL_CCALFMAX    V_T5_STATIC_KR_PLL_CCALFMAX(1U)
+
+#define S_T5_STATIC_KR_PLL_CCALCVHOLD    19
+#define V_T5_STATIC_KR_PLL_CCALCVHOLD(x) ((x) << S_T5_STATIC_KR_PLL_CCALCVHOLD)
+#define F_T5_STATIC_KR_PLL_CCALCVHOLD    V_T5_STATIC_KR_PLL_CCALCVHOLD(1U)
+
+#define S_T5_STATIC_KR_PLL_CCALBANDSEL    15
+#define M_T5_STATIC_KR_PLL_CCALBANDSEL    0xfU
+#define V_T5_STATIC_KR_PLL_CCALBANDSEL(x) ((x) << S_T5_STATIC_KR_PLL_CCALBANDSEL)
+#define G_T5_STATIC_KR_PLL_CCALBANDSEL(x) (((x) >> S_T5_STATIC_KR_PLL_CCALBANDSEL) & M_T5_STATIC_KR_PLL_CCALBANDSEL)
+
+#define S_T5_STATIC_KR_PLL_BGOFFSET    11
+#define M_T5_STATIC_KR_PLL_BGOFFSET    0xfU
+#define V_T5_STATIC_KR_PLL_BGOFFSET(x) ((x) << S_T5_STATIC_KR_PLL_BGOFFSET)
+#define G_T5_STATIC_KR_PLL_BGOFFSET(x) (((x) >> S_T5_STATIC_KR_PLL_BGOFFSET) & M_T5_STATIC_KR_PLL_BGOFFSET)
+
+#define S_T5_STATIC_KR_PLL_P    8
+#define M_T5_STATIC_KR_PLL_P    0x7U
+#define V_T5_STATIC_KR_PLL_P(x) ((x) << S_T5_STATIC_KR_PLL_P)
+#define G_T5_STATIC_KR_PLL_P(x) (((x) >> S_T5_STATIC_KR_PLL_P) & M_T5_STATIC_KR_PLL_P)
+
+#define S_T5_STATIC_KR_PLL_N2    4
+#define M_T5_STATIC_KR_PLL_N2    0xfU
+#define V_T5_STATIC_KR_PLL_N2(x) ((x) << S_T5_STATIC_KR_PLL_N2)
+#define G_T5_STATIC_KR_PLL_N2(x) (((x) >> S_T5_STATIC_KR_PLL_N2) & M_T5_STATIC_KR_PLL_N2)
+
+#define S_T5_STATIC_KR_PLL_N1    0
+#define M_T5_STATIC_KR_PLL_N1    0xfU
+#define V_T5_STATIC_KR_PLL_N1(x) ((x) << S_T5_STATIC_KR_PLL_N1)
+#define G_T5_STATIC_KR_PLL_N1(x) (((x) >> S_T5_STATIC_KR_PLL_N1) & M_T5_STATIC_KR_PLL_N1)
+
+#define A_DBG_T5_STATIC_KR_PLL_CONF2 0x60fc
+
+#define S_T5_STATIC_KR_PLL_M    11
+#define M_T5_STATIC_KR_PLL_M    0x1ffU
+#define V_T5_STATIC_KR_PLL_M(x) ((x) << S_T5_STATIC_KR_PLL_M)
+#define G_T5_STATIC_KR_PLL_M(x) (((x) >> S_T5_STATIC_KR_PLL_M) & M_T5_STATIC_KR_PLL_M)
+
+#define S_T5_STATIC_KR_PLL_ANALOGTUNE    0
+#define M_T5_STATIC_KR_PLL_ANALOGTUNE    0x7ffU
+#define V_T5_STATIC_KR_PLL_ANALOGTUNE(x) ((x) << S_T5_STATIC_KR_PLL_ANALOGTUNE)
+#define G_T5_STATIC_KR_PLL_ANALOGTUNE(x) (((x) >> S_T5_STATIC_KR_PLL_ANALOGTUNE) & M_T5_STATIC_KR_PLL_ANALOGTUNE)
+
+#define A_DBG_PVT_REG_CALIBRATE_CTL 0x6100
+
+#define S_HALT_CALIBRATE    1
+#define V_HALT_CALIBRATE(x) ((x) << S_HALT_CALIBRATE)
+#define F_HALT_CALIBRATE    V_HALT_CALIBRATE(1U)
+
+#define S_RESET_CALIBRATE    0
+#define V_RESET_CALIBRATE(x) ((x) << S_RESET_CALIBRATE)
+#define F_RESET_CALIBRATE    V_RESET_CALIBRATE(1U)
+
+#define A_DBG_GPIO_EN_NEW 0x6100
+
+#define S_GPIO16_OEN    7
+#define V_GPIO16_OEN(x) ((x) << S_GPIO16_OEN)
+#define F_GPIO16_OEN    V_GPIO16_OEN(1U)
+
+#define S_GPIO17_OEN    6
+#define V_GPIO17_OEN(x) ((x) << S_GPIO17_OEN)
+#define F_GPIO17_OEN    V_GPIO17_OEN(1U)
+
+#define S_GPIO18_OEN    5
+#define V_GPIO18_OEN(x) ((x) << S_GPIO18_OEN)
+#define F_GPIO18_OEN    V_GPIO18_OEN(1U)
+
+#define S_GPIO19_OEN    4
+#define V_GPIO19_OEN(x) ((x) << S_GPIO19_OEN)
+#define F_GPIO19_OEN    V_GPIO19_OEN(1U)
+
+#define S_GPIO16_OUT_VAL    3
+#define V_GPIO16_OUT_VAL(x) ((x) << S_GPIO16_OUT_VAL)
+#define F_GPIO16_OUT_VAL    V_GPIO16_OUT_VAL(1U)
+
+#define S_GPIO17_OUT_VAL    2
+#define V_GPIO17_OUT_VAL(x) ((x) << S_GPIO17_OUT_VAL)
+#define F_GPIO17_OUT_VAL    V_GPIO17_OUT_VAL(1U)
+
+#define S_GPIO18_OUT_VAL    1
+#define V_GPIO18_OUT_VAL(x) ((x) << S_GPIO18_OUT_VAL)
+#define F_GPIO18_OUT_VAL    V_GPIO18_OUT_VAL(1U)
+
+#define S_GPIO19_OUT_VAL    0
+#define V_GPIO19_OUT_VAL(x) ((x) << S_GPIO19_OUT_VAL)
+#define F_GPIO19_OUT_VAL    V_GPIO19_OUT_VAL(1U)
+
+#define A_DBG_PVT_REG_UPDATE_CTL 0x6104
+
+#define S_FAST_UPDATE    8
+#define V_FAST_UPDATE(x) ((x) << S_FAST_UPDATE)
+#define F_FAST_UPDATE    V_FAST_UPDATE(1U)
+
+#define S_FORCE_REG_IN_VALUE    2
+#define V_FORCE_REG_IN_VALUE(x) ((x) << S_FORCE_REG_IN_VALUE)
+#define F_FORCE_REG_IN_VALUE    V_FORCE_REG_IN_VALUE(1U)
+
+#define S_HALT_UPDATE    1
+#define V_HALT_UPDATE(x) ((x) << S_HALT_UPDATE)
+#define F_HALT_UPDATE    V_HALT_UPDATE(1U)
+
+#define A_DBG_GPIO_IN_NEW 0x6104
+
+#define S_GPIO16_CHG_DET    7
+#define V_GPIO16_CHG_DET(x) ((x) << S_GPIO16_CHG_DET)
+#define F_GPIO16_CHG_DET    V_GPIO16_CHG_DET(1U)
+
+#define S_GPIO17_CHG_DET    6
+#define V_GPIO17_CHG_DET(x) ((x) << S_GPIO17_CHG_DET)
+#define F_GPIO17_CHG_DET    V_GPIO17_CHG_DET(1U)
+
+#define S_GPIO18_CHG_DET    5
+#define V_GPIO18_CHG_DET(x) ((x) << S_GPIO18_CHG_DET)
+#define F_GPIO18_CHG_DET    V_GPIO18_CHG_DET(1U)
+
+#define S_GPIO19_CHG_DET    4
+#define V_GPIO19_CHG_DET(x) ((x) << S_GPIO19_CHG_DET)
+#define F_GPIO19_CHG_DET    V_GPIO19_CHG_DET(1U)
+
+#define S_GPIO16_IN    3
+#define V_GPIO16_IN(x) ((x) << S_GPIO16_IN)
+#define F_GPIO16_IN    V_GPIO16_IN(1U)
+
+#define S_GPIO17_IN    2
+#define V_GPIO17_IN(x) ((x) << S_GPIO17_IN)
+#define F_GPIO17_IN    V_GPIO17_IN(1U)
+
+#define S_GPIO18_IN    1
+#define V_GPIO18_IN(x) ((x) << S_GPIO18_IN)
+#define F_GPIO18_IN    V_GPIO18_IN(1U)
+
+#define S_GPIO19_IN    0
+#define V_GPIO19_IN(x) ((x) << S_GPIO19_IN)
+#define F_GPIO19_IN    V_GPIO19_IN(1U)
+
+#define A_DBG_PVT_REG_LAST_MEASUREMENT 0x6108
+
+#define S_LAST_MEASUREMENT_SELECT    8
+#define M_LAST_MEASUREMENT_SELECT    0x3U
+#define V_LAST_MEASUREMENT_SELECT(x) ((x) << S_LAST_MEASUREMENT_SELECT)
+#define G_LAST_MEASUREMENT_SELECT(x) (((x) >> S_LAST_MEASUREMENT_SELECT) & M_LAST_MEASUREMENT_SELECT)
+
+#define S_LAST_MEASUREMENT_RESULT_BANK_B    4
+#define M_LAST_MEASUREMENT_RESULT_BANK_B    0xfU
+#define V_LAST_MEASUREMENT_RESULT_BANK_B(x) ((x) << S_LAST_MEASUREMENT_RESULT_BANK_B)
+#define G_LAST_MEASUREMENT_RESULT_BANK_B(x) (((x) >> S_LAST_MEASUREMENT_RESULT_BANK_B) & M_LAST_MEASUREMENT_RESULT_BANK_B)
+
+#define S_LAST_MEASUREMENT_RESULT_BANK_A    0
+#define M_LAST_MEASUREMENT_RESULT_BANK_A    0xfU
+#define V_LAST_MEASUREMENT_RESULT_BANK_A(x) ((x) << S_LAST_MEASUREMENT_RESULT_BANK_A)
+#define G_LAST_MEASUREMENT_RESULT_BANK_A(x) (((x) >> S_LAST_MEASUREMENT_RESULT_BANK_A) & M_LAST_MEASUREMENT_RESULT_BANK_A)
+
+#define A_DBG_T5_STATIC_KX_PLL_CONF1 0x6108
+
+#define S_T5_STATIC_KX_PLL_BYPASS    30
+#define V_T5_STATIC_KX_PLL_BYPASS(x) ((x) << S_T5_STATIC_KX_PLL_BYPASS)
+#define F_T5_STATIC_KX_PLL_BYPASS    V_T5_STATIC_KX_PLL_BYPASS(1U)
+
+#define S_T5_STATIC_KX_PLL_VBOOSTDIV    27
+#define M_T5_STATIC_KX_PLL_VBOOSTDIV    0x7U
+#define V_T5_STATIC_KX_PLL_VBOOSTDIV(x) ((x) << S_T5_STATIC_KX_PLL_VBOOSTDIV)
+#define G_T5_STATIC_KX_PLL_VBOOSTDIV(x) (((x) >> S_T5_STATIC_KX_PLL_VBOOSTDIV) & M_T5_STATIC_KX_PLL_VBOOSTDIV)
+
+#define S_T5_STATIC_KX_PLL_CPISEL    24
+#define M_T5_STATIC_KX_PLL_CPISEL    0x7U
+#define V_T5_STATIC_KX_PLL_CPISEL(x) ((x) << S_T5_STATIC_KX_PLL_CPISEL)
+#define G_T5_STATIC_KX_PLL_CPISEL(x) (((x) >> S_T5_STATIC_KX_PLL_CPISEL) & M_T5_STATIC_KX_PLL_CPISEL)
+
+#define S_T5_STATIC_KX_PLL_CCALMETHOD    23
+#define V_T5_STATIC_KX_PLL_CCALMETHOD(x) ((x) << S_T5_STATIC_KX_PLL_CCALMETHOD)
+#define F_T5_STATIC_KX_PLL_CCALMETHOD    V_T5_STATIC_KX_PLL_CCALMETHOD(1U)
+
+#define S_T5_STATIC_KX_PLL_CCALLOAD    22
+#define V_T5_STATIC_KX_PLL_CCALLOAD(x) ((x) << S_T5_STATIC_KX_PLL_CCALLOAD)
+#define F_T5_STATIC_KX_PLL_CCALLOAD    V_T5_STATIC_KX_PLL_CCALLOAD(1U)
+
+#define S_T5_STATIC_KX_PLL_CCALFMIN    21
+#define V_T5_STATIC_KX_PLL_CCALFMIN(x) ((x) << S_T5_STATIC_KX_PLL_CCALFMIN)
+#define F_T5_STATIC_KX_PLL_CCALFMIN    V_T5_STATIC_KX_PLL_CCALFMIN(1U)
+
+#define S_T5_STATIC_KX_PLL_CCALFMAX    20
+#define V_T5_STATIC_KX_PLL_CCALFMAX(x) ((x) << S_T5_STATIC_KX_PLL_CCALFMAX)
+#define F_T5_STATIC_KX_PLL_CCALFMAX    V_T5_STATIC_KX_PLL_CCALFMAX(1U)
+
+#define S_T5_STATIC_KX_PLL_CCALCVHOLD    19
+#define V_T5_STATIC_KX_PLL_CCALCVHOLD(x) ((x) << S_T5_STATIC_KX_PLL_CCALCVHOLD)
+#define F_T5_STATIC_KX_PLL_CCALCVHOLD    V_T5_STATIC_KX_PLL_CCALCVHOLD(1U)
+
+#define S_T5_STATIC_KX_PLL_CCALBANDSEL    15
+#define M_T5_STATIC_KX_PLL_CCALBANDSEL    0xfU
+#define V_T5_STATIC_KX_PLL_CCALBANDSEL(x) ((x) << S_T5_STATIC_KX_PLL_CCALBANDSEL)
+#define G_T5_STATIC_KX_PLL_CCALBANDSEL(x) (((x) >> S_T5_STATIC_KX_PLL_CCALBANDSEL) & M_T5_STATIC_KX_PLL_CCALBANDSEL)
+
+#define S_T5_STATIC_KX_PLL_BGOFFSET    11
+#define M_T5_STATIC_KX_PLL_BGOFFSET    0xfU
+#define V_T5_STATIC_KX_PLL_BGOFFSET(x) ((x) << S_T5_STATIC_KX_PLL_BGOFFSET)
+#define G_T5_STATIC_KX_PLL_BGOFFSET(x) (((x) >> S_T5_STATIC_KX_PLL_BGOFFSET) & M_T5_STATIC_KX_PLL_BGOFFSET)
+
+#define S_T5_STATIC_KX_PLL_P    8
+#define M_T5_STATIC_KX_PLL_P    0x7U
+#define V_T5_STATIC_KX_PLL_P(x) ((x) << S_T5_STATIC_KX_PLL_P)
+#define G_T5_STATIC_KX_PLL_P(x) (((x) >> S_T5_STATIC_KX_PLL_P) & M_T5_STATIC_KX_PLL_P)
+
+#define S_T5_STATIC_KX_PLL_N2    4
+#define M_T5_STATIC_KX_PLL_N2    0xfU
+#define V_T5_STATIC_KX_PLL_N2(x) ((x) << S_T5_STATIC_KX_PLL_N2)
+#define G_T5_STATIC_KX_PLL_N2(x) (((x) >> S_T5_STATIC_KX_PLL_N2) & M_T5_STATIC_KX_PLL_N2)
+
+#define S_T5_STATIC_KX_PLL_N1    0
+#define M_T5_STATIC_KX_PLL_N1    0xfU
+#define V_T5_STATIC_KX_PLL_N1(x) ((x) << S_T5_STATIC_KX_PLL_N1)
+#define G_T5_STATIC_KX_PLL_N1(x) (((x) >> S_T5_STATIC_KX_PLL_N1) & M_T5_STATIC_KX_PLL_N1)
+
+#define A_DBG_PVT_REG_DRVN 0x610c
+
+#define S_PVT_REG_DRVN_EN    8
+#define V_PVT_REG_DRVN_EN(x) ((x) << S_PVT_REG_DRVN_EN)
+#define F_PVT_REG_DRVN_EN    V_PVT_REG_DRVN_EN(1U)
+
+#define S_PVT_REG_DRVN_B    4
+#define M_PVT_REG_DRVN_B    0xfU
+#define V_PVT_REG_DRVN_B(x) ((x) << S_PVT_REG_DRVN_B)
+#define G_PVT_REG_DRVN_B(x) (((x) >> S_PVT_REG_DRVN_B) & M_PVT_REG_DRVN_B)
+
+#define S_PVT_REG_DRVN_A    0
+#define M_PVT_REG_DRVN_A    0xfU
+#define V_PVT_REG_DRVN_A(x) ((x) << S_PVT_REG_DRVN_A)
+#define G_PVT_REG_DRVN_A(x) (((x) >> S_PVT_REG_DRVN_A) & M_PVT_REG_DRVN_A)
+
+#define A_DBG_T5_STATIC_KX_PLL_CONF2 0x610c
+
+#define S_T5_STATIC_KX_PLL_M    11
+#define M_T5_STATIC_KX_PLL_M    0x1ffU
+#define V_T5_STATIC_KX_PLL_M(x) ((x) << S_T5_STATIC_KX_PLL_M)
+#define G_T5_STATIC_KX_PLL_M(x) (((x) >> S_T5_STATIC_KX_PLL_M) & M_T5_STATIC_KX_PLL_M)
+
+#define S_T5_STATIC_KX_PLL_ANALOGTUNE    0
+#define M_T5_STATIC_KX_PLL_ANALOGTUNE    0x7ffU
+#define V_T5_STATIC_KX_PLL_ANALOGTUNE(x) ((x) << S_T5_STATIC_KX_PLL_ANALOGTUNE)
+#define G_T5_STATIC_KX_PLL_ANALOGTUNE(x) (((x) >> S_T5_STATIC_KX_PLL_ANALOGTUNE) & M_T5_STATIC_KX_PLL_ANALOGTUNE)
+
+#define A_DBG_PVT_REG_DRVP 0x6110
+
+#define S_PVT_REG_DRVP_EN    8
+#define V_PVT_REG_DRVP_EN(x) ((x) << S_PVT_REG_DRVP_EN)
+#define F_PVT_REG_DRVP_EN    V_PVT_REG_DRVP_EN(1U)
+
+#define S_PVT_REG_DRVP_B    4
+#define M_PVT_REG_DRVP_B    0xfU
+#define V_PVT_REG_DRVP_B(x) ((x) << S_PVT_REG_DRVP_B)
+#define G_PVT_REG_DRVP_B(x) (((x) >> S_PVT_REG_DRVP_B) & M_PVT_REG_DRVP_B)
+
+#define S_PVT_REG_DRVP_A    0
+#define M_PVT_REG_DRVP_A    0xfU
+#define V_PVT_REG_DRVP_A(x) ((x) << S_PVT_REG_DRVP_A)
+#define G_PVT_REG_DRVP_A(x) (((x) >> S_PVT_REG_DRVP_A) & M_PVT_REG_DRVP_A)
+
+#define A_DBG_T5_STATIC_C_DFS_CONF 0x6110
+
+#define S_STATIC_C_DFS_RANGEA    8
+#define M_STATIC_C_DFS_RANGEA    0x1fU
+#define V_STATIC_C_DFS_RANGEA(x) ((x) << S_STATIC_C_DFS_RANGEA)
+#define G_STATIC_C_DFS_RANGEA(x) (((x) >> S_STATIC_C_DFS_RANGEA) & M_STATIC_C_DFS_RANGEA)
+
+#define S_STATIC_C_DFS_RANGEB    3
+#define M_STATIC_C_DFS_RANGEB    0x1fU
+#define V_STATIC_C_DFS_RANGEB(x) ((x) << S_STATIC_C_DFS_RANGEB)
+#define G_STATIC_C_DFS_RANGEB(x) (((x) >> S_STATIC_C_DFS_RANGEB) & M_STATIC_C_DFS_RANGEB)
+
+#define S_STATIC_C_DFS_FFTUNE4    2
+#define V_STATIC_C_DFS_FFTUNE4(x) ((x) << S_STATIC_C_DFS_FFTUNE4)
+#define F_STATIC_C_DFS_FFTUNE4    V_STATIC_C_DFS_FFTUNE4(1U)
+
+#define S_STATIC_C_DFS_FFTUNE5    1
+#define V_STATIC_C_DFS_FFTUNE5(x) ((x) << S_STATIC_C_DFS_FFTUNE5)
+#define F_STATIC_C_DFS_FFTUNE5    V_STATIC_C_DFS_FFTUNE5(1U)
+
+#define S_STATIC_C_DFS_ENABLE    0
+#define V_STATIC_C_DFS_ENABLE(x) ((x) << S_STATIC_C_DFS_ENABLE)
+#define F_STATIC_C_DFS_ENABLE    V_STATIC_C_DFS_ENABLE(1U)
+
+#define A_DBG_PVT_REG_TERMN 0x6114
+
+#define S_PVT_REG_TERMN_EN    8
+#define V_PVT_REG_TERMN_EN(x) ((x) << S_PVT_REG_TERMN_EN)
+#define F_PVT_REG_TERMN_EN    V_PVT_REG_TERMN_EN(1U)
+
+#define S_PVT_REG_TERMN_B    4
+#define M_PVT_REG_TERMN_B    0xfU
+#define V_PVT_REG_TERMN_B(x) ((x) << S_PVT_REG_TERMN_B)
+#define G_PVT_REG_TERMN_B(x) (((x) >> S_PVT_REG_TERMN_B) & M_PVT_REG_TERMN_B)
+
+#define S_PVT_REG_TERMN_A    0
+#define M_PVT_REG_TERMN_A    0xfU
+#define V_PVT_REG_TERMN_A(x) ((x) << S_PVT_REG_TERMN_A)
+#define G_PVT_REG_TERMN_A(x) (((x) >> S_PVT_REG_TERMN_A) & M_PVT_REG_TERMN_A)
+
+#define A_DBG_T5_STATIC_U_DFS_CONF 0x6114
+
+#define S_STATIC_U_DFS_RANGEA    8
+#define M_STATIC_U_DFS_RANGEA    0x1fU
+#define V_STATIC_U_DFS_RANGEA(x) ((x) << S_STATIC_U_DFS_RANGEA)
+#define G_STATIC_U_DFS_RANGEA(x) (((x) >> S_STATIC_U_DFS_RANGEA) & M_STATIC_U_DFS_RANGEA)
+
+#define S_STATIC_U_DFS_RANGEB    3
+#define M_STATIC_U_DFS_RANGEB    0x1fU
+#define V_STATIC_U_DFS_RANGEB(x) ((x) << S_STATIC_U_DFS_RANGEB)
+#define G_STATIC_U_DFS_RANGEB(x) (((x) >> S_STATIC_U_DFS_RANGEB) & M_STATIC_U_DFS_RANGEB)
+
+#define S_STATIC_U_DFS_FFTUNE4    2
+#define V_STATIC_U_DFS_FFTUNE4(x) ((x) << S_STATIC_U_DFS_FFTUNE4)
+#define F_STATIC_U_DFS_FFTUNE4    V_STATIC_U_DFS_FFTUNE4(1U)
+
+#define S_STATIC_U_DFS_FFTUNE5    1
+#define V_STATIC_U_DFS_FFTUNE5(x) ((x) << S_STATIC_U_DFS_FFTUNE5)
+#define F_STATIC_U_DFS_FFTUNE5    V_STATIC_U_DFS_FFTUNE5(1U)
+
+#define S_STATIC_U_DFS_ENABLE    0
+#define V_STATIC_U_DFS_ENABLE(x) ((x) << S_STATIC_U_DFS_ENABLE)
+#define F_STATIC_U_DFS_ENABLE    V_STATIC_U_DFS_ENABLE(1U)
+
+#define A_DBG_PVT_REG_TERMP 0x6118
+
+#define S_PVT_REG_TERMP_EN    8
+#define V_PVT_REG_TERMP_EN(x) ((x) << S_PVT_REG_TERMP_EN)
+#define F_PVT_REG_TERMP_EN    V_PVT_REG_TERMP_EN(1U)
+
+#define S_PVT_REG_TERMP_B    4
+#define M_PVT_REG_TERMP_B    0xfU
+#define V_PVT_REG_TERMP_B(x) ((x) << S_PVT_REG_TERMP_B)
+#define G_PVT_REG_TERMP_B(x) (((x) >> S_PVT_REG_TERMP_B) & M_PVT_REG_TERMP_B)
+
+#define S_PVT_REG_TERMP_A    0
+#define M_PVT_REG_TERMP_A    0xfU
+#define V_PVT_REG_TERMP_A(x) ((x) << S_PVT_REG_TERMP_A)
+#define G_PVT_REG_TERMP_A(x) (((x) >> S_PVT_REG_TERMP_A) & M_PVT_REG_TERMP_A)
+
+#define A_DBG_GPIO_PE_EN 0x6118
+
+#define S_GPIO19_PE_EN    19
+#define V_GPIO19_PE_EN(x) ((x) << S_GPIO19_PE_EN)
+#define F_GPIO19_PE_EN    V_GPIO19_PE_EN(1U)
+
+#define S_GPIO18_PE_EN    18
+#define V_GPIO18_PE_EN(x) ((x) << S_GPIO18_PE_EN)
+#define F_GPIO18_PE_EN    V_GPIO18_PE_EN(1U)
+
+#define S_GPIO17_PE_EN    17
+#define V_GPIO17_PE_EN(x) ((x) << S_GPIO17_PE_EN)
+#define F_GPIO17_PE_EN    V_GPIO17_PE_EN(1U)
+
+#define S_GPIO16_PE_EN    16
+#define V_GPIO16_PE_EN(x) ((x) << S_GPIO16_PE_EN)
+#define F_GPIO16_PE_EN    V_GPIO16_PE_EN(1U)
+
+#define S_GPIO15_PE_EN    15
+#define V_GPIO15_PE_EN(x) ((x) << S_GPIO15_PE_EN)
+#define F_GPIO15_PE_EN    V_GPIO15_PE_EN(1U)
+
+#define S_GPIO14_PE_EN    14
+#define V_GPIO14_PE_EN(x) ((x) << S_GPIO14_PE_EN)
+#define F_GPIO14_PE_EN    V_GPIO14_PE_EN(1U)
+
+#define S_GPIO13_PE_EN    13
+#define V_GPIO13_PE_EN(x) ((x) << S_GPIO13_PE_EN)
+#define F_GPIO13_PE_EN    V_GPIO13_PE_EN(1U)
+
+#define S_GPIO12_PE_EN    12
+#define V_GPIO12_PE_EN(x) ((x) << S_GPIO12_PE_EN)
+#define F_GPIO12_PE_EN    V_GPIO12_PE_EN(1U)
+
+#define S_GPIO11_PE_EN    11
+#define V_GPIO11_PE_EN(x) ((x) << S_GPIO11_PE_EN)
+#define F_GPIO11_PE_EN    V_GPIO11_PE_EN(1U)
+
+#define S_GPIO10_PE_EN    10
+#define V_GPIO10_PE_EN(x) ((x) << S_GPIO10_PE_EN)
+#define F_GPIO10_PE_EN    V_GPIO10_PE_EN(1U)
+
+#define S_GPIO9_PE_EN    9
+#define V_GPIO9_PE_EN(x) ((x) << S_GPIO9_PE_EN)
+#define F_GPIO9_PE_EN    V_GPIO9_PE_EN(1U)
+
+#define S_GPIO8_PE_EN    8
+#define V_GPIO8_PE_EN(x) ((x) << S_GPIO8_PE_EN)
+#define F_GPIO8_PE_EN    V_GPIO8_PE_EN(1U)
+
+#define S_GPIO7_PE_EN    7
+#define V_GPIO7_PE_EN(x) ((x) << S_GPIO7_PE_EN)
+#define F_GPIO7_PE_EN    V_GPIO7_PE_EN(1U)
+
+#define S_GPIO6_PE_EN    6
+#define V_GPIO6_PE_EN(x) ((x) << S_GPIO6_PE_EN)
+#define F_GPIO6_PE_EN    V_GPIO6_PE_EN(1U)
+
+#define S_GPIO5_PE_EN    5
+#define V_GPIO5_PE_EN(x) ((x) << S_GPIO5_PE_EN)
+#define F_GPIO5_PE_EN    V_GPIO5_PE_EN(1U)
+
+#define S_GPIO4_PE_EN    4
+#define V_GPIO4_PE_EN(x) ((x) << S_GPIO4_PE_EN)
+#define F_GPIO4_PE_EN    V_GPIO4_PE_EN(1U)
+
+#define S_GPIO3_PE_EN    3
+#define V_GPIO3_PE_EN(x) ((x) << S_GPIO3_PE_EN)
+#define F_GPIO3_PE_EN    V_GPIO3_PE_EN(1U)
+
+#define S_GPIO2_PE_EN    2
+#define V_GPIO2_PE_EN(x) ((x) << S_GPIO2_PE_EN)
+#define F_GPIO2_PE_EN    V_GPIO2_PE_EN(1U)
+
+#define S_GPIO1_PE_EN    1
+#define V_GPIO1_PE_EN(x) ((x) << S_GPIO1_PE_EN)
+#define F_GPIO1_PE_EN    V_GPIO1_PE_EN(1U)
+
+#define S_GPIO0_PE_EN    0
+#define V_GPIO0_PE_EN(x) ((x) << S_GPIO0_PE_EN)
+#define F_GPIO0_PE_EN    V_GPIO0_PE_EN(1U)
+
+#define A_DBG_PVT_REG_THRESHOLD 0x611c
+
+#define S_PVT_CALIBRATION_DONE    8
+#define V_PVT_CALIBRATION_DONE(x) ((x) << S_PVT_CALIBRATION_DONE)
+#define F_PVT_CALIBRATION_DONE    V_PVT_CALIBRATION_DONE(1U)
+
+#define S_THRESHOLD_TERMP_MAX_SYNC    7
+#define V_THRESHOLD_TERMP_MAX_SYNC(x) ((x) << S_THRESHOLD_TERMP_MAX_SYNC)
+#define F_THRESHOLD_TERMP_MAX_SYNC    V_THRESHOLD_TERMP_MAX_SYNC(1U)
+
+#define S_THRESHOLD_TERMP_MIN_SYNC    6
+#define V_THRESHOLD_TERMP_MIN_SYNC(x) ((x) << S_THRESHOLD_TERMP_MIN_SYNC)
+#define F_THRESHOLD_TERMP_MIN_SYNC    V_THRESHOLD_TERMP_MIN_SYNC(1U)
+
+#define S_THRESHOLD_TERMN_MAX_SYNC    5
+#define V_THRESHOLD_TERMN_MAX_SYNC(x) ((x) << S_THRESHOLD_TERMN_MAX_SYNC)
+#define F_THRESHOLD_TERMN_MAX_SYNC    V_THRESHOLD_TERMN_MAX_SYNC(1U)
+
+#define S_THRESHOLD_TERMN_MIN_SYNC    4
+#define V_THRESHOLD_TERMN_MIN_SYNC(x) ((x) << S_THRESHOLD_TERMN_MIN_SYNC)
+#define F_THRESHOLD_TERMN_MIN_SYNC    V_THRESHOLD_TERMN_MIN_SYNC(1U)
+
+#define S_THRESHOLD_DRVP_MAX_SYNC    3
+#define V_THRESHOLD_DRVP_MAX_SYNC(x) ((x) << S_THRESHOLD_DRVP_MAX_SYNC)
+#define F_THRESHOLD_DRVP_MAX_SYNC    V_THRESHOLD_DRVP_MAX_SYNC(1U)
+
+#define S_THRESHOLD_DRVP_MIN_SYNC    2
+#define V_THRESHOLD_DRVP_MIN_SYNC(x) ((x) << S_THRESHOLD_DRVP_MIN_SYNC)
+#define F_THRESHOLD_DRVP_MIN_SYNC    V_THRESHOLD_DRVP_MIN_SYNC(1U)
+
+#define S_THRESHOLD_DRVN_MAX_SYNC    1
+#define V_THRESHOLD_DRVN_MAX_SYNC(x) ((x) << S_THRESHOLD_DRVN_MAX_SYNC)
+#define F_THRESHOLD_DRVN_MAX_SYNC    V_THRESHOLD_DRVN_MAX_SYNC(1U)
+
+#define S_THRESHOLD_DRVN_MIN_SYNC    0
+#define V_THRESHOLD_DRVN_MIN_SYNC(x) ((x) << S_THRESHOLD_DRVN_MIN_SYNC)
+#define F_THRESHOLD_DRVN_MIN_SYNC    V_THRESHOLD_DRVN_MIN_SYNC(1U)
+
+#define A_DBG_GPIO_PS_EN 0x611c
+
+#define S_GPIO19_PS_EN    19
+#define V_GPIO19_PS_EN(x) ((x) << S_GPIO19_PS_EN)
+#define F_GPIO19_PS_EN    V_GPIO19_PS_EN(1U)
+
+#define S_GPIO18_PS_EN    18
+#define V_GPIO18_PS_EN(x) ((x) << S_GPIO18_PS_EN)
+#define F_GPIO18_PS_EN    V_GPIO18_PS_EN(1U)
+
+#define S_GPIO17_PS_EN    17
+#define V_GPIO17_PS_EN(x) ((x) << S_GPIO17_PS_EN)
+#define F_GPIO17_PS_EN    V_GPIO17_PS_EN(1U)
+
+#define S_GPIO16_PS_EN    16
+#define V_GPIO16_PS_EN(x) ((x) << S_GPIO16_PS_EN)
+#define F_GPIO16_PS_EN    V_GPIO16_PS_EN(1U)
+
+#define S_GPIO15_PS_EN    15
+#define V_GPIO15_PS_EN(x) ((x) << S_GPIO15_PS_EN)
+#define F_GPIO15_PS_EN    V_GPIO15_PS_EN(1U)
+
+#define S_GPIO14_PS_EN    14
+#define V_GPIO14_PS_EN(x) ((x) << S_GPIO14_PS_EN)
+#define F_GPIO14_PS_EN    V_GPIO14_PS_EN(1U)
+
+#define S_GPIO13_PS_EN    13
+#define V_GPIO13_PS_EN(x) ((x) << S_GPIO13_PS_EN)
+#define F_GPIO13_PS_EN    V_GPIO13_PS_EN(1U)
+
+#define S_GPIO12_PS_EN    12
+#define V_GPIO12_PS_EN(x) ((x) << S_GPIO12_PS_EN)
+#define F_GPIO12_PS_EN    V_GPIO12_PS_EN(1U)
+
+#define S_GPIO11_PS_EN    11
+#define V_GPIO11_PS_EN(x) ((x) << S_GPIO11_PS_EN)
+#define F_GPIO11_PS_EN    V_GPIO11_PS_EN(1U)
+
+#define S_GPIO10_PS_EN    10
+#define V_GPIO10_PS_EN(x) ((x) << S_GPIO10_PS_EN)
+#define F_GPIO10_PS_EN    V_GPIO10_PS_EN(1U)
+
+#define S_GPIO9_PS_EN    9
+#define V_GPIO9_PS_EN(x) ((x) << S_GPIO9_PS_EN)
+#define F_GPIO9_PS_EN    V_GPIO9_PS_EN(1U)
+
+#define S_GPIO8_PS_EN    8
+#define V_GPIO8_PS_EN(x) ((x) << S_GPIO8_PS_EN)
+#define F_GPIO8_PS_EN    V_GPIO8_PS_EN(1U)
+
+#define S_GPIO7_PS_EN    7
+#define V_GPIO7_PS_EN(x) ((x) << S_GPIO7_PS_EN)
+#define F_GPIO7_PS_EN    V_GPIO7_PS_EN(1U)
+
+#define S_GPIO6_PS_EN    6
+#define V_GPIO6_PS_EN(x) ((x) << S_GPIO6_PS_EN)
+#define F_GPIO6_PS_EN    V_GPIO6_PS_EN(1U)
+
+#define S_GPIO5_PS_EN    5
+#define V_GPIO5_PS_EN(x) ((x) << S_GPIO5_PS_EN)
+#define F_GPIO5_PS_EN    V_GPIO5_PS_EN(1U)
+
+#define S_GPIO4_PS_EN    4
+#define V_GPIO4_PS_EN(x) ((x) << S_GPIO4_PS_EN)
+#define F_GPIO4_PS_EN    V_GPIO4_PS_EN(1U)
+
+#define S_GPIO3_PS_EN    3
+#define V_GPIO3_PS_EN(x) ((x) << S_GPIO3_PS_EN)
+#define F_GPIO3_PS_EN    V_GPIO3_PS_EN(1U)
+
+#define S_GPIO2_PS_EN    2
+#define V_GPIO2_PS_EN(x) ((x) << S_GPIO2_PS_EN)
+#define F_GPIO2_PS_EN    V_GPIO2_PS_EN(1U)
+
+#define S_GPIO1_PS_EN    1
+#define V_GPIO1_PS_EN(x) ((x) << S_GPIO1_PS_EN)
+#define F_GPIO1_PS_EN    V_GPIO1_PS_EN(1U)
+
+#define S_GPIO0_PS_EN    0
+#define V_GPIO0_PS_EN(x) ((x) << S_GPIO0_PS_EN)
+#define F_GPIO0_PS_EN    V_GPIO0_PS_EN(1U)
+
+#define A_DBG_PVT_REG_IN_TERMP 0x6120
+
+#define S_REG_IN_TERMP_B    4
+#define M_REG_IN_TERMP_B    0xfU
+#define V_REG_IN_TERMP_B(x) ((x) << S_REG_IN_TERMP_B)
+#define G_REG_IN_TERMP_B(x) (((x) >> S_REG_IN_TERMP_B) & M_REG_IN_TERMP_B)
+
+#define S_REG_IN_TERMP_A    0
+#define M_REG_IN_TERMP_A    0xfU
+#define V_REG_IN_TERMP_A(x) ((x) << S_REG_IN_TERMP_A)
+#define G_REG_IN_TERMP_A(x) (((x) >> S_REG_IN_TERMP_A) & M_REG_IN_TERMP_A)
+
+#define A_DBG_EFUSE_BYTE16_19 0x6120
+#define A_DBG_PVT_REG_IN_TERMN 0x6124
+
+#define S_REG_IN_TERMN_B    4
+#define M_REG_IN_TERMN_B    0xfU
+#define V_REG_IN_TERMN_B(x) ((x) << S_REG_IN_TERMN_B)
+#define G_REG_IN_TERMN_B(x) (((x) >> S_REG_IN_TERMN_B) & M_REG_IN_TERMN_B)
+
+#define S_REG_IN_TERMN_A    0
+#define M_REG_IN_TERMN_A    0xfU
+#define V_REG_IN_TERMN_A(x) ((x) << S_REG_IN_TERMN_A)
+#define G_REG_IN_TERMN_A(x) (((x) >> S_REG_IN_TERMN_A) & M_REG_IN_TERMN_A)
+
+#define A_DBG_EFUSE_BYTE20_23 0x6124
+#define A_DBG_PVT_REG_IN_DRVP 0x6128
+
+#define S_REG_IN_DRVP_B    4
+#define M_REG_IN_DRVP_B    0xfU
+#define V_REG_IN_DRVP_B(x) ((x) << S_REG_IN_DRVP_B)
+#define G_REG_IN_DRVP_B(x) (((x) >> S_REG_IN_DRVP_B) & M_REG_IN_DRVP_B)
+
+#define S_REG_IN_DRVP_A    0
+#define M_REG_IN_DRVP_A    0xfU
+#define V_REG_IN_DRVP_A(x) ((x) << S_REG_IN_DRVP_A)
+#define G_REG_IN_DRVP_A(x) (((x) >> S_REG_IN_DRVP_A) & M_REG_IN_DRVP_A)
+
+#define A_DBG_EFUSE_BYTE24_27 0x6128
+#define A_DBG_PVT_REG_IN_DRVN 0x612c
+
+#define S_REG_IN_DRVN_B    4
+#define M_REG_IN_DRVN_B    0xfU
+#define V_REG_IN_DRVN_B(x) ((x) << S_REG_IN_DRVN_B)
+#define G_REG_IN_DRVN_B(x) (((x) >> S_REG_IN_DRVN_B) & M_REG_IN_DRVN_B)
+
+#define S_REG_IN_DRVN_A    0
+#define M_REG_IN_DRVN_A    0xfU
+#define V_REG_IN_DRVN_A(x) ((x) << S_REG_IN_DRVN_A)
+#define G_REG_IN_DRVN_A(x) (((x) >> S_REG_IN_DRVN_A) & M_REG_IN_DRVN_A)
+
+#define A_DBG_EFUSE_BYTE28_31 0x612c
+#define A_DBG_PVT_REG_OUT_TERMP 0x6130
+
+#define S_REG_OUT_TERMP_B    4
+#define M_REG_OUT_TERMP_B    0xfU
+#define V_REG_OUT_TERMP_B(x) ((x) << S_REG_OUT_TERMP_B)
+#define G_REG_OUT_TERMP_B(x) (((x) >> S_REG_OUT_TERMP_B) & M_REG_OUT_TERMP_B)
+
+#define S_REG_OUT_TERMP_A    0
+#define M_REG_OUT_TERMP_A    0xfU
+#define V_REG_OUT_TERMP_A(x) ((x) << S_REG_OUT_TERMP_A)
+#define G_REG_OUT_TERMP_A(x) (((x) >> S_REG_OUT_TERMP_A) & M_REG_OUT_TERMP_A)
+
+#define A_DBG_EFUSE_BYTE32_35 0x6130
+#define A_DBG_PVT_REG_OUT_TERMN 0x6134
+
+#define S_REG_OUT_TERMN_B    4
+#define M_REG_OUT_TERMN_B    0xfU
+#define V_REG_OUT_TERMN_B(x) ((x) << S_REG_OUT_TERMN_B)
+#define G_REG_OUT_TERMN_B(x) (((x) >> S_REG_OUT_TERMN_B) & M_REG_OUT_TERMN_B)
+
+#define S_REG_OUT_TERMN_A    0
+#define M_REG_OUT_TERMN_A    0xfU
+#define V_REG_OUT_TERMN_A(x) ((x) << S_REG_OUT_TERMN_A)
+#define G_REG_OUT_TERMN_A(x) (((x) >> S_REG_OUT_TERMN_A) & M_REG_OUT_TERMN_A)
+
+#define A_DBG_EFUSE_BYTE36_39 0x6134
+#define A_DBG_PVT_REG_OUT_DRVP 0x6138
+
+#define S_REG_OUT_DRVP_B    4
+#define M_REG_OUT_DRVP_B    0xfU
+#define V_REG_OUT_DRVP_B(x) ((x) << S_REG_OUT_DRVP_B)
+#define G_REG_OUT_DRVP_B(x) (((x) >> S_REG_OUT_DRVP_B) & M_REG_OUT_DRVP_B)
+
+#define S_REG_OUT_DRVP_A    0
+#define M_REG_OUT_DRVP_A    0xfU
+#define V_REG_OUT_DRVP_A(x) ((x) << S_REG_OUT_DRVP_A)
+#define G_REG_OUT_DRVP_A(x) (((x) >> S_REG_OUT_DRVP_A) & M_REG_OUT_DRVP_A)
+
+#define A_DBG_EFUSE_BYTE40_43 0x6138
+#define A_DBG_PVT_REG_OUT_DRVN 0x613c
+
+#define S_REG_OUT_DRVN_B    4
+#define M_REG_OUT_DRVN_B    0xfU
+#define V_REG_OUT_DRVN_B(x) ((x) << S_REG_OUT_DRVN_B)
+#define G_REG_OUT_DRVN_B(x) (((x) >> S_REG_OUT_DRVN_B) & M_REG_OUT_DRVN_B)
+
+#define S_REG_OUT_DRVN_A    0
+#define M_REG_OUT_DRVN_A    0xfU
+#define V_REG_OUT_DRVN_A(x) ((x) << S_REG_OUT_DRVN_A)
+#define G_REG_OUT_DRVN_A(x) (((x) >> S_REG_OUT_DRVN_A) & M_REG_OUT_DRVN_A)
+
+#define A_DBG_EFUSE_BYTE44_47 0x613c
+#define A_DBG_PVT_REG_HISTORY_TERMP 0x6140
+
+#define S_TERMP_B_HISTORY    4
+#define M_TERMP_B_HISTORY    0xfU
+#define V_TERMP_B_HISTORY(x) ((x) << S_TERMP_B_HISTORY)
+#define G_TERMP_B_HISTORY(x) (((x) >> S_TERMP_B_HISTORY) & M_TERMP_B_HISTORY)
+
+#define S_TERMP_A_HISTORY    0
+#define M_TERMP_A_HISTORY    0xfU
+#define V_TERMP_A_HISTORY(x) ((x) << S_TERMP_A_HISTORY)
+#define G_TERMP_A_HISTORY(x) (((x) >> S_TERMP_A_HISTORY) & M_TERMP_A_HISTORY)
+
+#define A_DBG_EFUSE_BYTE48_51 0x6140
+#define A_DBG_PVT_REG_HISTORY_TERMN 0x6144
+
+#define S_TERMN_B_HISTORY    4
+#define M_TERMN_B_HISTORY    0xfU
+#define V_TERMN_B_HISTORY(x) ((x) << S_TERMN_B_HISTORY)
+#define G_TERMN_B_HISTORY(x) (((x) >> S_TERMN_B_HISTORY) & M_TERMN_B_HISTORY)
+
+#define S_TERMN_A_HISTORY    0
+#define M_TERMN_A_HISTORY    0xfU
+#define V_TERMN_A_HISTORY(x) ((x) << S_TERMN_A_HISTORY)
+#define G_TERMN_A_HISTORY(x) (((x) >> S_TERMN_A_HISTORY) & M_TERMN_A_HISTORY)
+
+#define A_DBG_EFUSE_BYTE52_55 0x6144
+#define A_DBG_PVT_REG_HISTORY_DRVP 0x6148
+
+#define S_DRVP_B_HISTORY    4
+#define M_DRVP_B_HISTORY    0xfU
+#define V_DRVP_B_HISTORY(x) ((x) << S_DRVP_B_HISTORY)
+#define G_DRVP_B_HISTORY(x) (((x) >> S_DRVP_B_HISTORY) & M_DRVP_B_HISTORY)
+
+#define S_DRVP_A_HISTORY    0
+#define M_DRVP_A_HISTORY    0xfU
+#define V_DRVP_A_HISTORY(x) ((x) << S_DRVP_A_HISTORY)
+#define G_DRVP_A_HISTORY(x) (((x) >> S_DRVP_A_HISTORY) & M_DRVP_A_HISTORY)
+
+#define A_DBG_EFUSE_BYTE56_59 0x6148
+#define A_DBG_PVT_REG_HISTORY_DRVN 0x614c
+
+#define S_DRVN_B_HISTORY    4
+#define M_DRVN_B_HISTORY    0xfU
+#define V_DRVN_B_HISTORY(x) ((x) << S_DRVN_B_HISTORY)
+#define G_DRVN_B_HISTORY(x) (((x) >> S_DRVN_B_HISTORY) & M_DRVN_B_HISTORY)
+
+#define S_DRVN_A_HISTORY    0
+#define M_DRVN_A_HISTORY    0xfU
+#define V_DRVN_A_HISTORY(x) ((x) << S_DRVN_A_HISTORY)
+#define G_DRVN_A_HISTORY(x) (((x) >> S_DRVN_A_HISTORY) & M_DRVN_A_HISTORY)
+
+#define A_DBG_EFUSE_BYTE60_63 0x614c
+#define A_DBG_PVT_REG_SAMPLE_WAIT_CLKS 0x6150
+
+#define S_SAMPLE_WAIT_CLKS    0
+#define M_SAMPLE_WAIT_CLKS    0x1fU
+#define V_SAMPLE_WAIT_CLKS(x) ((x) << S_SAMPLE_WAIT_CLKS)
+#define G_SAMPLE_WAIT_CLKS(x) (((x) >> S_SAMPLE_WAIT_CLKS) & M_SAMPLE_WAIT_CLKS)
+
+/* registers for module MC */
+#define MC_BASE_ADDR 0x6200
+
+#define A_MC_PCTL_SCFG 0x6200
+
+#define S_RKINF_EN    5
+#define V_RKINF_EN(x) ((x) << S_RKINF_EN)
+#define F_RKINF_EN    V_RKINF_EN(1U)
+
+#define S_DUAL_PCTL_EN    4
+#define V_DUAL_PCTL_EN(x) ((x) << S_DUAL_PCTL_EN)
+#define F_DUAL_PCTL_EN    V_DUAL_PCTL_EN(1U)
+
+#define S_SLAVE_MODE    3
+#define V_SLAVE_MODE(x) ((x) << S_SLAVE_MODE)
+#define F_SLAVE_MODE    V_SLAVE_MODE(1U)
+
+#define S_LOOPBACK_EN    1
+#define V_LOOPBACK_EN(x) ((x) << S_LOOPBACK_EN)
+#define F_LOOPBACK_EN    V_LOOPBACK_EN(1U)
+
+#define S_HW_LOW_POWER_EN    0
+#define V_HW_LOW_POWER_EN(x) ((x) << S_HW_LOW_POWER_EN)
+#define F_HW_LOW_POWER_EN    V_HW_LOW_POWER_EN(1U)
+
+#define A_MC_PCTL_SCTL 0x6204
+
+#define S_STATE_CMD    0
+#define M_STATE_CMD    0x7U
+#define V_STATE_CMD(x) ((x) << S_STATE_CMD)
+#define G_STATE_CMD(x) (((x) >> S_STATE_CMD) & M_STATE_CMD)
+
+#define A_MC_PCTL_STAT 0x6208
+
+#define S_CTL_STAT    0
+#define M_CTL_STAT    0x7U
+#define V_CTL_STAT(x) ((x) << S_CTL_STAT)
+#define G_CTL_STAT(x) (((x) >> S_CTL_STAT) & M_CTL_STAT)
+
+#define A_MC_PCTL_MCMD 0x6240
+
+#define S_START_CMD    31
+#define V_START_CMD(x) ((x) << S_START_CMD)
+#define F_START_CMD    V_START_CMD(1U)
+
+#define S_CMD_ADD_DEL    24
+#define M_CMD_ADD_DEL    0xfU
+#define V_CMD_ADD_DEL(x) ((x) << S_CMD_ADD_DEL)
+#define G_CMD_ADD_DEL(x) (((x) >> S_CMD_ADD_DEL) & M_CMD_ADD_DEL)
+
+#define S_RANK_SEL    20
+#define M_RANK_SEL    0xfU
+#define V_RANK_SEL(x) ((x) << S_RANK_SEL)
+#define G_RANK_SEL(x) (((x) >> S_RANK_SEL) & M_RANK_SEL)
+
+#define S_BANK_ADDR    17
+#define M_BANK_ADDR    0x7U
+#define V_BANK_ADDR(x) ((x) << S_BANK_ADDR)
+#define G_BANK_ADDR(x) (((x) >> S_BANK_ADDR) & M_BANK_ADDR)
+
+#define S_CMD_ADDR    4
+#define M_CMD_ADDR    0x1fffU
+#define V_CMD_ADDR(x) ((x) << S_CMD_ADDR)
+#define G_CMD_ADDR(x) (((x) >> S_CMD_ADDR) & M_CMD_ADDR)
+
+#define S_CMD_OPCODE    0
+#define M_CMD_OPCODE    0x7U
+#define V_CMD_OPCODE(x) ((x) << S_CMD_OPCODE)
+#define G_CMD_OPCODE(x) (((x) >> S_CMD_OPCODE) & M_CMD_OPCODE)
+
+#define A_MC_PCTL_POWCTL 0x6244
+
+#define S_POWER_UP_START    0
+#define V_POWER_UP_START(x) ((x) << S_POWER_UP_START)
+#define F_POWER_UP_START    V_POWER_UP_START(1U)
+
+#define A_MC_PCTL_POWSTAT 0x6248
+
+#define S_PHY_CALIBDONE    1
+#define V_PHY_CALIBDONE(x) ((x) << S_PHY_CALIBDONE)
+#define F_PHY_CALIBDONE    V_PHY_CALIBDONE(1U)
+
+#define S_POWER_UP_DONE    0
+#define V_POWER_UP_DONE(x) ((x) << S_POWER_UP_DONE)
+#define F_POWER_UP_DONE    V_POWER_UP_DONE(1U)
+
+#define A_MC_PCTL_MCFG 0x6280
+
+#define S_TFAW_CFG    18
+#define M_TFAW_CFG    0x3U
+#define V_TFAW_CFG(x) ((x) << S_TFAW_CFG)
+#define G_TFAW_CFG(x) (((x) >> S_TFAW_CFG) & M_TFAW_CFG)
+
+#define S_PD_EXIT_MODE    17
+#define V_PD_EXIT_MODE(x) ((x) << S_PD_EXIT_MODE)
+#define F_PD_EXIT_MODE    V_PD_EXIT_MODE(1U)
+
+#define S_PD_TYPE    16
+#define V_PD_TYPE(x) ((x) << S_PD_TYPE)
+#define F_PD_TYPE    V_PD_TYPE(1U)
+
+#define S_PD_IDLE    8
+#define M_PD_IDLE    0xffU
+#define V_PD_IDLE(x) ((x) << S_PD_IDLE)
+#define G_PD_IDLE(x) (((x) >> S_PD_IDLE) & M_PD_IDLE)
+
+#define S_PAGE_POLICY    6
+#define M_PAGE_POLICY    0x3U
+#define V_PAGE_POLICY(x) ((x) << S_PAGE_POLICY)
+#define G_PAGE_POLICY(x) (((x) >> S_PAGE_POLICY) & M_PAGE_POLICY)
+
+#define S_DDR3_EN    5
+#define V_DDR3_EN(x) ((x) << S_DDR3_EN)
+#define F_DDR3_EN    V_DDR3_EN(1U)
+
+#define S_TWO_T_EN    3
+#define V_TWO_T_EN(x) ((x) << S_TWO_T_EN)
+#define F_TWO_T_EN    V_TWO_T_EN(1U)
+
+#define S_BL8INT_EN    2
+#define V_BL8INT_EN(x) ((x) << S_BL8INT_EN)
+#define F_BL8INT_EN    V_BL8INT_EN(1U)
+
+#define S_MEM_BL    0
+#define V_MEM_BL(x) ((x) << S_MEM_BL)
+#define F_MEM_BL    V_MEM_BL(1U)
+
+#define A_MC_PCTL_PPCFG 0x6284
+
+#define S_RPMEM_DIS    1
+#define M_RPMEM_DIS    0xffU
+#define V_RPMEM_DIS(x) ((x) << S_RPMEM_DIS)
+#define G_RPMEM_DIS(x) (((x) >> S_RPMEM_DIS) & M_RPMEM_DIS)
+
+#define S_PPMEM_EN    0
+#define V_PPMEM_EN(x) ((x) << S_PPMEM_EN)
+#define F_PPMEM_EN    V_PPMEM_EN(1U)
+
+#define A_MC_PCTL_MSTAT 0x6288
+
+#define S_POWER_DOWN    0
+#define V_POWER_DOWN(x) ((x) << S_POWER_DOWN)
+#define F_POWER_DOWN    V_POWER_DOWN(1U)
+
+#define A_MC_PCTL_ODTCFG 0x628c
+
+#define S_RANK3_ODT_DEFAULT    28
+#define V_RANK3_ODT_DEFAULT(x) ((x) << S_RANK3_ODT_DEFAULT)
+#define F_RANK3_ODT_DEFAULT    V_RANK3_ODT_DEFAULT(1U)
+
+#define S_RANK3_ODT_WRITE_SEL    27
+#define V_RANK3_ODT_WRITE_SEL(x) ((x) << S_RANK3_ODT_WRITE_SEL)
+#define F_RANK3_ODT_WRITE_SEL    V_RANK3_ODT_WRITE_SEL(1U)
+
+#define S_RANK3_ODT_WRITE_NSE    26
+#define V_RANK3_ODT_WRITE_NSE(x) ((x) << S_RANK3_ODT_WRITE_NSE)
+#define F_RANK3_ODT_WRITE_NSE    V_RANK3_ODT_WRITE_NSE(1U)
+
+#define S_RANK3_ODT_READ_SEL    25
+#define V_RANK3_ODT_READ_SEL(x) ((x) << S_RANK3_ODT_READ_SEL)
+#define F_RANK3_ODT_READ_SEL    V_RANK3_ODT_READ_SEL(1U)
+
+#define S_RANK3_ODT_READ_NSEL    24
+#define V_RANK3_ODT_READ_NSEL(x) ((x) << S_RANK3_ODT_READ_NSEL)
+#define F_RANK3_ODT_READ_NSEL    V_RANK3_ODT_READ_NSEL(1U)
+
+#define S_RANK2_ODT_DEFAULT    20
+#define V_RANK2_ODT_DEFAULT(x) ((x) << S_RANK2_ODT_DEFAULT)
+#define F_RANK2_ODT_DEFAULT    V_RANK2_ODT_DEFAULT(1U)
+
+#define S_RANK2_ODT_WRITE_SEL    19
+#define V_RANK2_ODT_WRITE_SEL(x) ((x) << S_RANK2_ODT_WRITE_SEL)
+#define F_RANK2_ODT_WRITE_SEL    V_RANK2_ODT_WRITE_SEL(1U)
+
+#define S_RANK2_ODT_WRITE_NSEL    18
+#define V_RANK2_ODT_WRITE_NSEL(x) ((x) << S_RANK2_ODT_WRITE_NSEL)
+#define F_RANK2_ODT_WRITE_NSEL    V_RANK2_ODT_WRITE_NSEL(1U)
+
+#define S_RANK2_ODT_READ_SEL    17
+#define V_RANK2_ODT_READ_SEL(x) ((x) << S_RANK2_ODT_READ_SEL)
+#define F_RANK2_ODT_READ_SEL    V_RANK2_ODT_READ_SEL(1U)
+
+#define S_RANK2_ODT_READ_NSEL    16
+#define V_RANK2_ODT_READ_NSEL(x) ((x) << S_RANK2_ODT_READ_NSEL)
+#define F_RANK2_ODT_READ_NSEL    V_RANK2_ODT_READ_NSEL(1U)
+
+#define S_RANK1_ODT_DEFAULT    12
+#define V_RANK1_ODT_DEFAULT(x) ((x) << S_RANK1_ODT_DEFAULT)
+#define F_RANK1_ODT_DEFAULT    V_RANK1_ODT_DEFAULT(1U)
+
+#define S_RANK1_ODT_WRITE_SEL    11
+#define V_RANK1_ODT_WRITE_SEL(x) ((x) << S_RANK1_ODT_WRITE_SEL)
+#define F_RANK1_ODT_WRITE_SEL    V_RANK1_ODT_WRITE_SEL(1U)
+
+#define S_RANK1_ODT_WRITE_NSEL    10
+#define V_RANK1_ODT_WRITE_NSEL(x) ((x) << S_RANK1_ODT_WRITE_NSEL)
+#define F_RANK1_ODT_WRITE_NSEL    V_RANK1_ODT_WRITE_NSEL(1U)
+
+#define S_RANK1_ODT_READ_SEL    9
+#define V_RANK1_ODT_READ_SEL(x) ((x) << S_RANK1_ODT_READ_SEL)
+#define F_RANK1_ODT_READ_SEL    V_RANK1_ODT_READ_SEL(1U)
+
+#define S_RANK1_ODT_READ_NSEL    8
+#define V_RANK1_ODT_READ_NSEL(x) ((x) << S_RANK1_ODT_READ_NSEL)
+#define F_RANK1_ODT_READ_NSEL    V_RANK1_ODT_READ_NSEL(1U)
+
+#define S_RANK0_ODT_DEFAULT    4
+#define V_RANK0_ODT_DEFAULT(x) ((x) << S_RANK0_ODT_DEFAULT)
+#define F_RANK0_ODT_DEFAULT    V_RANK0_ODT_DEFAULT(1U)
+
+#define S_RANK0_ODT_WRITE_SEL    3
+#define V_RANK0_ODT_WRITE_SEL(x) ((x) << S_RANK0_ODT_WRITE_SEL)
+#define F_RANK0_ODT_WRITE_SEL    V_RANK0_ODT_WRITE_SEL(1U)
+
+#define S_RANK0_ODT_WRITE_NSEL    2
+#define V_RANK0_ODT_WRITE_NSEL(x) ((x) << S_RANK0_ODT_WRITE_NSEL)
+#define F_RANK0_ODT_WRITE_NSEL    V_RANK0_ODT_WRITE_NSEL(1U)
+
+#define S_RANK0_ODT_READ_SEL    1
+#define V_RANK0_ODT_READ_SEL(x) ((x) << S_RANK0_ODT_READ_SEL)
+#define F_RANK0_ODT_READ_SEL    V_RANK0_ODT_READ_SEL(1U)
+
+#define S_RANK0_ODT_READ_NSEL    0
+#define V_RANK0_ODT_READ_NSEL(x) ((x) << S_RANK0_ODT_READ_NSEL)
+#define F_RANK0_ODT_READ_NSEL    V_RANK0_ODT_READ_NSEL(1U)
+
+#define A_MC_PCTL_DQSECFG 0x6290
+
+#define S_DV_ALAT    20
+#define M_DV_ALAT    0xfU
+#define V_DV_ALAT(x) ((x) << S_DV_ALAT)
+#define G_DV_ALAT(x) (((x) >> S_DV_ALAT) & M_DV_ALAT)
+
+#define S_DV_ALEN    16
+#define M_DV_ALEN    0x3U
+#define V_DV_ALEN(x) ((x) << S_DV_ALEN)
+#define G_DV_ALEN(x) (((x) >> S_DV_ALEN) & M_DV_ALEN)
+
+#define S_DSE_ALAT    12
+#define M_DSE_ALAT    0xfU
+#define V_DSE_ALAT(x) ((x) << S_DSE_ALAT)
+#define G_DSE_ALAT(x) (((x) >> S_DSE_ALAT) & M_DSE_ALAT)
+
+#define S_DSE_ALEN    8
+#define M_DSE_ALEN    0x3U
+#define V_DSE_ALEN(x) ((x) << S_DSE_ALEN)
+#define G_DSE_ALEN(x) (((x) >> S_DSE_ALEN) & M_DSE_ALEN)
+
+#define S_QSE_ALAT    4
+#define M_QSE_ALAT    0xfU
+#define V_QSE_ALAT(x) ((x) << S_QSE_ALAT)
+#define G_QSE_ALAT(x) (((x) >> S_QSE_ALAT) & M_QSE_ALAT)
+
+#define S_QSE_ALEN    0
+#define M_QSE_ALEN    0x3U
+#define V_QSE_ALEN(x) ((x) << S_QSE_ALEN)
+#define G_QSE_ALEN(x) (((x) >> S_QSE_ALEN) & M_QSE_ALEN)
+
+#define A_MC_PCTL_DTUPDES 0x6294
+
+#define S_DTU_RD_MISSING    13
+#define V_DTU_RD_MISSING(x) ((x) << S_DTU_RD_MISSING)
+#define F_DTU_RD_MISSING    V_DTU_RD_MISSING(1U)
+
+#define S_DTU_EAFFL    9
+#define M_DTU_EAFFL    0xfU
+#define V_DTU_EAFFL(x) ((x) << S_DTU_EAFFL)
+#define G_DTU_EAFFL(x) (((x) >> S_DTU_EAFFL) & M_DTU_EAFFL)
+
+#define S_DTU_RANDOM_ERROR    8
+#define V_DTU_RANDOM_ERROR(x) ((x) << S_DTU_RANDOM_ERROR)
+#define F_DTU_RANDOM_ERROR    V_DTU_RANDOM_ERROR(1U)
+
+#define S_DTU_ERROR_B7    7
+#define V_DTU_ERROR_B7(x) ((x) << S_DTU_ERROR_B7)
+#define F_DTU_ERROR_B7    V_DTU_ERROR_B7(1U)
+
+#define S_DTU_ERR_B6    6
+#define V_DTU_ERR_B6(x) ((x) << S_DTU_ERR_B6)
+#define F_DTU_ERR_B6    V_DTU_ERR_B6(1U)
+
+#define S_DTU_ERR_B5    5
+#define V_DTU_ERR_B5(x) ((x) << S_DTU_ERR_B5)
+#define F_DTU_ERR_B5    V_DTU_ERR_B5(1U)
+
+#define S_DTU_ERR_B4    4
+#define V_DTU_ERR_B4(x) ((x) << S_DTU_ERR_B4)
+#define F_DTU_ERR_B4    V_DTU_ERR_B4(1U)
+
+#define S_DTU_ERR_B3    3
+#define V_DTU_ERR_B3(x) ((x) << S_DTU_ERR_B3)
+#define F_DTU_ERR_B3    V_DTU_ERR_B3(1U)
+
+#define S_DTU_ERR_B2    2
+#define V_DTU_ERR_B2(x) ((x) << S_DTU_ERR_B2)
+#define F_DTU_ERR_B2    V_DTU_ERR_B2(1U)
+
+#define S_DTU_ERR_B1    1
+#define V_DTU_ERR_B1(x) ((x) << S_DTU_ERR_B1)
+#define F_DTU_ERR_B1    V_DTU_ERR_B1(1U)
+
+#define S_DTU_ERR_B0    0
+#define V_DTU_ERR_B0(x) ((x) << S_DTU_ERR_B0)
+#define F_DTU_ERR_B0    V_DTU_ERR_B0(1U)
+
+#define A_MC_PCTL_DTUNA 0x6298
+#define A_MC_PCTL_DTUNE 0x629c
+#define A_MC_PCTL_DTUPRDO 0x62a0
+
+#define S_DTU_ALLBITS_1    16
+#define M_DTU_ALLBITS_1    0xffffU
+#define V_DTU_ALLBITS_1(x) ((x) << S_DTU_ALLBITS_1)
+#define G_DTU_ALLBITS_1(x) (((x) >> S_DTU_ALLBITS_1) & M_DTU_ALLBITS_1)
+
+#define S_DTU_ALLBITS_0    0
+#define M_DTU_ALLBITS_0    0xffffU
+#define V_DTU_ALLBITS_0(x) ((x) << S_DTU_ALLBITS_0)
+#define G_DTU_ALLBITS_0(x) (((x) >> S_DTU_ALLBITS_0) & M_DTU_ALLBITS_0)
+
+#define A_MC_PCTL_DTUPRD1 0x62a4
+
+#define S_DTU_ALLBITS_3    16
+#define M_DTU_ALLBITS_3    0xffffU
+#define V_DTU_ALLBITS_3(x) ((x) << S_DTU_ALLBITS_3)
+#define G_DTU_ALLBITS_3(x) (((x) >> S_DTU_ALLBITS_3) & M_DTU_ALLBITS_3)
+
+#define S_DTU_ALLBITS_2    0
+#define M_DTU_ALLBITS_2    0xffffU
+#define V_DTU_ALLBITS_2(x) ((x) << S_DTU_ALLBITS_2)
+#define G_DTU_ALLBITS_2(x) (((x) >> S_DTU_ALLBITS_2) & M_DTU_ALLBITS_2)
+
+#define A_MC_PCTL_DTUPRD2 0x62a8
+
+#define S_DTU_ALLBITS_5    16
+#define M_DTU_ALLBITS_5    0xffffU
+#define V_DTU_ALLBITS_5(x) ((x) << S_DTU_ALLBITS_5)
+#define G_DTU_ALLBITS_5(x) (((x) >> S_DTU_ALLBITS_5) & M_DTU_ALLBITS_5)
+
+#define S_DTU_ALLBITS_4    0
+#define M_DTU_ALLBITS_4    0xffffU
+#define V_DTU_ALLBITS_4(x) ((x) << S_DTU_ALLBITS_4)
+#define G_DTU_ALLBITS_4(x) (((x) >> S_DTU_ALLBITS_4) & M_DTU_ALLBITS_4)
+
+#define A_MC_PCTL_DTUPRD3 0x62ac
+
+#define S_DTU_ALLBITS_7    16
+#define M_DTU_ALLBITS_7    0xffffU
+#define V_DTU_ALLBITS_7(x) ((x) << S_DTU_ALLBITS_7)
+#define G_DTU_ALLBITS_7(x) (((x) >> S_DTU_ALLBITS_7) & M_DTU_ALLBITS_7)
+
+#define S_DTU_ALLBITS_6    0
+#define M_DTU_ALLBITS_6    0xffffU
+#define V_DTU_ALLBITS_6(x) ((x) << S_DTU_ALLBITS_6)
+#define G_DTU_ALLBITS_6(x) (((x) >> S_DTU_ALLBITS_6) & M_DTU_ALLBITS_6)
+
+#define A_MC_PCTL_DTUAWDT 0x62b0
+
+#define S_NUMBER_RANKS    9
+#define M_NUMBER_RANKS    0x3U
+#define V_NUMBER_RANKS(x) ((x) << S_NUMBER_RANKS)
+#define G_NUMBER_RANKS(x) (((x) >> S_NUMBER_RANKS) & M_NUMBER_RANKS)
+
+#define S_ROW_ADDR_WIDTH    6
+#define M_ROW_ADDR_WIDTH    0x3U
+#define V_ROW_ADDR_WIDTH(x) ((x) << S_ROW_ADDR_WIDTH)
+#define G_ROW_ADDR_WIDTH(x) (((x) >> S_ROW_ADDR_WIDTH) & M_ROW_ADDR_WIDTH)
+
+#define S_BANK_ADDR_WIDTH    3
+#define M_BANK_ADDR_WIDTH    0x3U
+#define V_BANK_ADDR_WIDTH(x) ((x) << S_BANK_ADDR_WIDTH)
+#define G_BANK_ADDR_WIDTH(x) (((x) >> S_BANK_ADDR_WIDTH) & M_BANK_ADDR_WIDTH)
+
+#define S_COLUMN_ADDR_WIDTH    0
+#define M_COLUMN_ADDR_WIDTH    0x3U
+#define V_COLUMN_ADDR_WIDTH(x) ((x) << S_COLUMN_ADDR_WIDTH)
+#define G_COLUMN_ADDR_WIDTH(x) (((x) >> S_COLUMN_ADDR_WIDTH) & M_COLUMN_ADDR_WIDTH)
+
+#define A_MC_PCTL_TOGCNT1U 0x62c0
+
+#define S_TOGGLE_COUNTER_1U    0
+#define M_TOGGLE_COUNTER_1U    0x3ffU
+#define V_TOGGLE_COUNTER_1U(x) ((x) << S_TOGGLE_COUNTER_1U)
+#define G_TOGGLE_COUNTER_1U(x) (((x) >> S_TOGGLE_COUNTER_1U) & M_TOGGLE_COUNTER_1U)
+
+#define A_MC_PCTL_TINIT 0x62c4
+
+#define S_T_INIT    0
+#define M_T_INIT    0x1ffU
+#define V_T_INIT(x) ((x) << S_T_INIT)
+#define G_T_INIT(x) (((x) >> S_T_INIT) & M_T_INIT)
+
+#define A_MC_PCTL_TRSTH 0x62c8
+
+#define S_T_RSTH    0
+#define M_T_RSTH    0x3ffU
+#define V_T_RSTH(x) ((x) << S_T_RSTH)
+#define G_T_RSTH(x) (((x) >> S_T_RSTH) & M_T_RSTH)
+
+#define A_MC_PCTL_TOGCNT100N 0x62cc
+
+#define S_TOGGLE_COUNTER_100N    0
+#define M_TOGGLE_COUNTER_100N    0x7fU
+#define V_TOGGLE_COUNTER_100N(x) ((x) << S_TOGGLE_COUNTER_100N)
+#define G_TOGGLE_COUNTER_100N(x) (((x) >> S_TOGGLE_COUNTER_100N) & M_TOGGLE_COUNTER_100N)
+
+#define A_MC_PCTL_TREFI 0x62d0
+
+#define S_T_REFI    0
+#define M_T_REFI    0xffU
+#define V_T_REFI(x) ((x) << S_T_REFI)
+#define G_T_REFI(x) (((x) >> S_T_REFI) & M_T_REFI)
+
+#define A_MC_PCTL_TMRD 0x62d4
+
+#define S_T_MRD    0
+#define M_T_MRD    0x7U
+#define V_T_MRD(x) ((x) << S_T_MRD)
+#define G_T_MRD(x) (((x) >> S_T_MRD) & M_T_MRD)
+
+#define A_MC_PCTL_TRFC 0x62d8
+
+#define S_T_RFC    0
+#define M_T_RFC    0xffU
+#define V_T_RFC(x) ((x) << S_T_RFC)
+#define G_T_RFC(x) (((x) >> S_T_RFC) & M_T_RFC)
+
+#define A_MC_PCTL_TRP 0x62dc
+
+#define S_T_RP    0
+#define M_T_RP    0xfU
+#define V_T_RP(x) ((x) << S_T_RP)
+#define G_T_RP(x) (((x) >> S_T_RP) & M_T_RP)
+
+#define A_MC_PCTL_TRTW 0x62e0
+
+#define S_T_RTW    0
+#define M_T_RTW    0x7U
+#define V_T_RTW(x) ((x) << S_T_RTW)
+#define G_T_RTW(x) (((x) >> S_T_RTW) & M_T_RTW)
+
+#define A_MC_PCTL_TAL 0x62e4
+
+#define S_T_AL    0
+#define M_T_AL    0xfU
+#define V_T_AL(x) ((x) << S_T_AL)
+#define G_T_AL(x) (((x) >> S_T_AL) & M_T_AL)
+
+#define A_MC_PCTL_TCL 0x62e8
+
+#define S_T_CL    0
+#define M_T_CL    0xfU
+#define V_T_CL(x) ((x) << S_T_CL)
+#define G_T_CL(x) (((x) >> S_T_CL) & M_T_CL)
+
+#define A_MC_PCTL_TCWL 0x62ec
+
+#define S_T_CWL    0
+#define M_T_CWL    0xfU
+#define V_T_CWL(x) ((x) << S_T_CWL)
+#define G_T_CWL(x) (((x) >> S_T_CWL) & M_T_CWL)
+
+#define A_MC_PCTL_TRAS 0x62f0
+
+#define S_T_RAS    0
+#define M_T_RAS    0x3fU
+#define V_T_RAS(x) ((x) << S_T_RAS)
+#define G_T_RAS(x) (((x) >> S_T_RAS) & M_T_RAS)
+
+#define A_MC_PCTL_TRC 0x62f4
+
+#define S_T_RC    0
+#define M_T_RC    0x3fU
+#define V_T_RC(x) ((x) << S_T_RC)
+#define G_T_RC(x) (((x) >> S_T_RC) & M_T_RC)
+
+#define A_MC_PCTL_TRCD 0x62f8
+
+#define S_T_RCD    0
+#define M_T_RCD    0xfU
+#define V_T_RCD(x) ((x) << S_T_RCD)
+#define G_T_RCD(x) (((x) >> S_T_RCD) & M_T_RCD)
+
+#define A_MC_PCTL_TRRD 0x62fc
+
+#define S_T_RRD    0
+#define M_T_RRD    0xfU
+#define V_T_RRD(x) ((x) << S_T_RRD)
+#define G_T_RRD(x) (((x) >> S_T_RRD) & M_T_RRD)
+
+#define A_MC_PCTL_TRTP 0x6300
+
+#define S_T_RTP    0
+#define M_T_RTP    0x7U
+#define V_T_RTP(x) ((x) << S_T_RTP)
+#define G_T_RTP(x) (((x) >> S_T_RTP) & M_T_RTP)
+
+#define A_MC_PCTL_TWR 0x6304
+
+#define S_T_WR    0
+#define M_T_WR    0x7U
+#define V_T_WR(x) ((x) << S_T_WR)
+#define G_T_WR(x) (((x) >> S_T_WR) & M_T_WR)
+
+#define A_MC_PCTL_TWTR 0x6308
+
+#define S_T_WTR    0
+#define M_T_WTR    0x7U
+#define V_T_WTR(x) ((x) << S_T_WTR)
+#define G_T_WTR(x) (((x) >> S_T_WTR) & M_T_WTR)
+
+#define A_MC_PCTL_TEXSR 0x630c
+
+#define S_T_EXSR    0
+#define M_T_EXSR    0x3ffU
+#define V_T_EXSR(x) ((x) << S_T_EXSR)
+#define G_T_EXSR(x) (((x) >> S_T_EXSR) & M_T_EXSR)
+
+#define A_MC_PCTL_TXP 0x6310
+
+#define S_T_XP    0
+#define M_T_XP    0x7U
+#define V_T_XP(x) ((x) << S_T_XP)
+#define G_T_XP(x) (((x) >> S_T_XP) & M_T_XP)
+
+#define A_MC_PCTL_TXPDLL 0x6314
+
+#define S_T_XPDLL    0
+#define M_T_XPDLL    0x3fU
+#define V_T_XPDLL(x) ((x) << S_T_XPDLL)
+#define G_T_XPDLL(x) (((x) >> S_T_XPDLL) & M_T_XPDLL)
+
+#define A_MC_PCTL_TZQCS 0x6318
+
+#define S_T_ZQCS    0
+#define M_T_ZQCS    0x7fU
+#define V_T_ZQCS(x) ((x) << S_T_ZQCS)
+#define G_T_ZQCS(x) (((x) >> S_T_ZQCS) & M_T_ZQCS)
+
+#define A_MC_PCTL_TZQCSI 0x631c
+
+#define S_T_ZQCSI    0
+#define M_T_ZQCSI    0xfffU
+#define V_T_ZQCSI(x) ((x) << S_T_ZQCSI)
+#define G_T_ZQCSI(x) (((x) >> S_T_ZQCSI) & M_T_ZQCSI)
+
+#define A_MC_PCTL_TDQS 0x6320
+
+#define S_T_DQS    0
+#define M_T_DQS    0x7U
+#define V_T_DQS(x) ((x) << S_T_DQS)
+#define G_T_DQS(x) (((x) >> S_T_DQS) & M_T_DQS)
+
+#define A_MC_PCTL_TCKSRE 0x6324
+
+#define S_T_CKSRE    0
+#define M_T_CKSRE    0xfU
+#define V_T_CKSRE(x) ((x) << S_T_CKSRE)
+#define G_T_CKSRE(x) (((x) >> S_T_CKSRE) & M_T_CKSRE)
+
+#define A_MC_PCTL_TCKSRX 0x6328
+
+#define S_T_CKSRX    0
+#define M_T_CKSRX    0xfU
+#define V_T_CKSRX(x) ((x) << S_T_CKSRX)
+#define G_T_CKSRX(x) (((x) >> S_T_CKSRX) & M_T_CKSRX)
+
+#define A_MC_PCTL_TCKE 0x632c
+
+#define S_T_CKE    0
+#define M_T_CKE    0x7U
+#define V_T_CKE(x) ((x) << S_T_CKE)
+#define G_T_CKE(x) (((x) >> S_T_CKE) & M_T_CKE)
+
+#define A_MC_PCTL_TMOD 0x6330
+
+#define S_T_MOD    0
+#define M_T_MOD    0xfU
+#define V_T_MOD(x) ((x) << S_T_MOD)
+#define G_T_MOD(x) (((x) >> S_T_MOD) & M_T_MOD)
+
+#define A_MC_PCTL_TRSTL 0x6334
+
+#define S_RSTHOLD    0
+#define M_RSTHOLD    0x7fU
+#define V_RSTHOLD(x) ((x) << S_RSTHOLD)
+#define G_RSTHOLD(x) (((x) >> S_RSTHOLD) & M_RSTHOLD)
+
+#define A_MC_PCTL_TZQCL 0x6338
+
+#define S_T_ZQCL    0
+#define M_T_ZQCL    0x3ffU
+#define V_T_ZQCL(x) ((x) << S_T_ZQCL)
+#define G_T_ZQCL(x) (((x) >> S_T_ZQCL) & M_T_ZQCL)
+
+#define A_MC_PCTL_DWLCFG0 0x6370
+
+#define S_T_ADWL_VEC    0
+#define M_T_ADWL_VEC    0x1ffU
+#define V_T_ADWL_VEC(x) ((x) << S_T_ADWL_VEC)
+#define G_T_ADWL_VEC(x) (((x) >> S_T_ADWL_VEC) & M_T_ADWL_VEC)
+
+#define A_MC_PCTL_DWLCFG1 0x6374
+#define A_MC_PCTL_DWLCFG2 0x6378
+#define A_MC_PCTL_DWLCFG3 0x637c
+#define A_MC_PCTL_ECCCFG 0x6380
+
+#define S_INLINE_SYN_EN    4
+#define V_INLINE_SYN_EN(x) ((x) << S_INLINE_SYN_EN)
+#define F_INLINE_SYN_EN    V_INLINE_SYN_EN(1U)
+
+#define S_ECC_EN    3
+#define V_ECC_EN(x) ((x) << S_ECC_EN)
+#define F_ECC_EN    V_ECC_EN(1U)
+
+#define S_ECC_INTR_EN    2
+#define V_ECC_INTR_EN(x) ((x) << S_ECC_INTR_EN)
+#define F_ECC_INTR_EN    V_ECC_INTR_EN(1U)
+
+#define A_MC_PCTL_ECCTST 0x6384
+
+#define S_ECC_TEST_MASK    0
+#define M_ECC_TEST_MASK    0xffU
+#define V_ECC_TEST_MASK(x) ((x) << S_ECC_TEST_MASK)
+#define G_ECC_TEST_MASK(x) (((x) >> S_ECC_TEST_MASK) & M_ECC_TEST_MASK)
+
+#define A_MC_PCTL_ECCCLR 0x6388
+
+#define S_CLR_ECC_LOG    1
+#define V_CLR_ECC_LOG(x) ((x) << S_CLR_ECC_LOG)
+#define F_CLR_ECC_LOG    V_CLR_ECC_LOG(1U)
+
+#define S_CLR_ECC_INTR    0
+#define V_CLR_ECC_INTR(x) ((x) << S_CLR_ECC_INTR)
+#define F_CLR_ECC_INTR    V_CLR_ECC_INTR(1U)
+
+#define A_MC_PCTL_ECCLOG 0x638c
+#define A_MC_PCTL_DTUWACTL 0x6400
+
+#define S_DTU_WR_RANK    30
+#define M_DTU_WR_RANK    0x3U
+#define V_DTU_WR_RANK(x) ((x) << S_DTU_WR_RANK)
+#define G_DTU_WR_RANK(x) (((x) >> S_DTU_WR_RANK) & M_DTU_WR_RANK)
+
+#define S_DTU_WR_ROW    13
+#define M_DTU_WR_ROW    0x1ffffU
+#define V_DTU_WR_ROW(x) ((x) << S_DTU_WR_ROW)
+#define G_DTU_WR_ROW(x) (((x) >> S_DTU_WR_ROW) & M_DTU_WR_ROW)
+
+#define S_DTU_WR_BANK    10
+#define M_DTU_WR_BANK    0x7U
+#define V_DTU_WR_BANK(x) ((x) << S_DTU_WR_BANK)
+#define G_DTU_WR_BANK(x) (((x) >> S_DTU_WR_BANK) & M_DTU_WR_BANK)
+
+#define S_DTU_WR_COL    0
+#define M_DTU_WR_COL    0x3ffU
+#define V_DTU_WR_COL(x) ((x) << S_DTU_WR_COL)
+#define G_DTU_WR_COL(x) (((x) >> S_DTU_WR_COL) & M_DTU_WR_COL)
+
+#define A_MC_PCTL_DTURACTL 0x6404
+
+#define S_DTU_RD_RANK    30
+#define M_DTU_RD_RANK    0x3U
+#define V_DTU_RD_RANK(x) ((x) << S_DTU_RD_RANK)
+#define G_DTU_RD_RANK(x) (((x) >> S_DTU_RD_RANK) & M_DTU_RD_RANK)
+
+#define S_DTU_RD_ROW    13
+#define M_DTU_RD_ROW    0x1ffffU
+#define V_DTU_RD_ROW(x) ((x) << S_DTU_RD_ROW)
+#define G_DTU_RD_ROW(x) (((x) >> S_DTU_RD_ROW) & M_DTU_RD_ROW)
+
+#define S_DTU_RD_BANK    10
+#define M_DTU_RD_BANK    0x7U
+#define V_DTU_RD_BANK(x) ((x) << S_DTU_RD_BANK)
+#define G_DTU_RD_BANK(x) (((x) >> S_DTU_RD_BANK) & M_DTU_RD_BANK)
+
+#define S_DTU_RD_COL    0
+#define M_DTU_RD_COL    0x3ffU
+#define V_DTU_RD_COL(x) ((x) << S_DTU_RD_COL)
+#define G_DTU_RD_COL(x) (((x) >> S_DTU_RD_COL) & M_DTU_RD_COL)
+
+#define A_MC_PCTL_DTUCFG 0x6408
+
+#define S_DTU_ROW_INCREMENTS    16
+#define M_DTU_ROW_INCREMENTS    0x7fU
+#define V_DTU_ROW_INCREMENTS(x) ((x) << S_DTU_ROW_INCREMENTS)
+#define G_DTU_ROW_INCREMENTS(x) (((x) >> S_DTU_ROW_INCREMENTS) & M_DTU_ROW_INCREMENTS)
+
+#define S_DTU_WR_MULTI_RD    15
+#define V_DTU_WR_MULTI_RD(x) ((x) << S_DTU_WR_MULTI_RD)
+#define F_DTU_WR_MULTI_RD    V_DTU_WR_MULTI_RD(1U)
+
+#define S_DTU_DATA_MASK_EN    14
+#define V_DTU_DATA_MASK_EN(x) ((x) << S_DTU_DATA_MASK_EN)
+#define F_DTU_DATA_MASK_EN    V_DTU_DATA_MASK_EN(1U)
+
+#define S_DTU_TARGET_LANE    10
+#define M_DTU_TARGET_LANE    0xfU
+#define V_DTU_TARGET_LANE(x) ((x) << S_DTU_TARGET_LANE)
+#define G_DTU_TARGET_LANE(x) (((x) >> S_DTU_TARGET_LANE) & M_DTU_TARGET_LANE)
+
+#define S_DTU_GENERATE_RANDOM    9
+#define V_DTU_GENERATE_RANDOM(x) ((x) << S_DTU_GENERATE_RANDOM)
+#define F_DTU_GENERATE_RANDOM    V_DTU_GENERATE_RANDOM(1U)
+
+#define S_DTU_INCR_BANKS    8
+#define V_DTU_INCR_BANKS(x) ((x) << S_DTU_INCR_BANKS)
+#define F_DTU_INCR_BANKS    V_DTU_INCR_BANKS(1U)
+
+#define S_DTU_INCR_COLS    7
+#define V_DTU_INCR_COLS(x) ((x) << S_DTU_INCR_COLS)
+#define F_DTU_INCR_COLS    V_DTU_INCR_COLS(1U)
+
+#define S_DTU_NALEN    1
+#define M_DTU_NALEN    0x3fU
+#define V_DTU_NALEN(x) ((x) << S_DTU_NALEN)
+#define G_DTU_NALEN(x) (((x) >> S_DTU_NALEN) & M_DTU_NALEN)
+
+#define S_DTU_ENABLE    0
+#define V_DTU_ENABLE(x) ((x) << S_DTU_ENABLE)
+#define F_DTU_ENABLE    V_DTU_ENABLE(1U)
+
+#define A_MC_PCTL_DTUECTL 0x640c
+
+#define S_WR_MULTI_RD_RST    2
+#define V_WR_MULTI_RD_RST(x) ((x) << S_WR_MULTI_RD_RST)
+#define F_WR_MULTI_RD_RST    V_WR_MULTI_RD_RST(1U)
+
+#define S_RUN_ERROR_REPORTS    1
+#define V_RUN_ERROR_REPORTS(x) ((x) << S_RUN_ERROR_REPORTS)
+#define F_RUN_ERROR_REPORTS    V_RUN_ERROR_REPORTS(1U)
+
+#define S_RUN_DTU    0
+#define V_RUN_DTU(x) ((x) << S_RUN_DTU)
+#define F_RUN_DTU    V_RUN_DTU(1U)
+
+#define A_MC_PCTL_DTUWD0 0x6410
+
+#define S_DTU_WR_BYTE3    24
+#define M_DTU_WR_BYTE3    0xffU
+#define V_DTU_WR_BYTE3(x) ((x) << S_DTU_WR_BYTE3)
+#define G_DTU_WR_BYTE3(x) (((x) >> S_DTU_WR_BYTE3) & M_DTU_WR_BYTE3)
+
+#define S_DTU_WR_BYTE2    16
+#define M_DTU_WR_BYTE2    0xffU
+#define V_DTU_WR_BYTE2(x) ((x) << S_DTU_WR_BYTE2)
+#define G_DTU_WR_BYTE2(x) (((x) >> S_DTU_WR_BYTE2) & M_DTU_WR_BYTE2)
+
+#define S_DTU_WR_BYTE1    8
+#define M_DTU_WR_BYTE1    0xffU
+#define V_DTU_WR_BYTE1(x) ((x) << S_DTU_WR_BYTE1)
+#define G_DTU_WR_BYTE1(x) (((x) >> S_DTU_WR_BYTE1) & M_DTU_WR_BYTE1)
+
+#define S_DTU_WR_BYTE0    0
+#define M_DTU_WR_BYTE0    0xffU
+#define V_DTU_WR_BYTE0(x) ((x) << S_DTU_WR_BYTE0)
+#define G_DTU_WR_BYTE0(x) (((x) >> S_DTU_WR_BYTE0) & M_DTU_WR_BYTE0)
+
+#define A_MC_PCTL_DTUWD1 0x6414
+
+#define S_DTU_WR_BYTE7    24
+#define M_DTU_WR_BYTE7    0xffU
+#define V_DTU_WR_BYTE7(x) ((x) << S_DTU_WR_BYTE7)
+#define G_DTU_WR_BYTE7(x) (((x) >> S_DTU_WR_BYTE7) & M_DTU_WR_BYTE7)
+
+#define S_DTU_WR_BYTE6    16
+#define M_DTU_WR_BYTE6    0xffU
+#define V_DTU_WR_BYTE6(x) ((x) << S_DTU_WR_BYTE6)
+#define G_DTU_WR_BYTE6(x) (((x) >> S_DTU_WR_BYTE6) & M_DTU_WR_BYTE6)
+
+#define S_DTU_WR_BYTE5    8
+#define M_DTU_WR_BYTE5    0xffU
+#define V_DTU_WR_BYTE5(x) ((x) << S_DTU_WR_BYTE5)
+#define G_DTU_WR_BYTE5(x) (((x) >> S_DTU_WR_BYTE5) & M_DTU_WR_BYTE5)
+
+#define S_DTU_WR_BYTE4    0
+#define M_DTU_WR_BYTE4    0xffU
+#define V_DTU_WR_BYTE4(x) ((x) << S_DTU_WR_BYTE4)
+#define G_DTU_WR_BYTE4(x) (((x) >> S_DTU_WR_BYTE4) & M_DTU_WR_BYTE4)
+
+#define A_MC_PCTL_DTUWD2 0x6418
+
+#define S_DTU_WR_BYTE11    24
+#define M_DTU_WR_BYTE11    0xffU
+#define V_DTU_WR_BYTE11(x) ((x) << S_DTU_WR_BYTE11)
+#define G_DTU_WR_BYTE11(x) (((x) >> S_DTU_WR_BYTE11) & M_DTU_WR_BYTE11)
+
+#define S_DTU_WR_BYTE10    16
+#define M_DTU_WR_BYTE10    0xffU
+#define V_DTU_WR_BYTE10(x) ((x) << S_DTU_WR_BYTE10)
+#define G_DTU_WR_BYTE10(x) (((x) >> S_DTU_WR_BYTE10) & M_DTU_WR_BYTE10)
+
+#define S_DTU_WR_BYTE9    8
+#define M_DTU_WR_BYTE9    0xffU
+#define V_DTU_WR_BYTE9(x) ((x) << S_DTU_WR_BYTE9)
+#define G_DTU_WR_BYTE9(x) (((x) >> S_DTU_WR_BYTE9) & M_DTU_WR_BYTE9)
+
+#define S_DTU_WR_BYTE8    0
+#define M_DTU_WR_BYTE8    0xffU
+#define V_DTU_WR_BYTE8(x) ((x) << S_DTU_WR_BYTE8)
+#define G_DTU_WR_BYTE8(x) (((x) >> S_DTU_WR_BYTE8) & M_DTU_WR_BYTE8)
+
+#define A_MC_PCTL_DTUWD3 0x641c
+
+#define S_DTU_WR_BYTE15    24
+#define M_DTU_WR_BYTE15    0xffU
+#define V_DTU_WR_BYTE15(x) ((x) << S_DTU_WR_BYTE15)
+#define G_DTU_WR_BYTE15(x) (((x) >> S_DTU_WR_BYTE15) & M_DTU_WR_BYTE15)
+
+#define S_DTU_WR_BYTE14    16
+#define M_DTU_WR_BYTE14    0xffU
+#define V_DTU_WR_BYTE14(x) ((x) << S_DTU_WR_BYTE14)
+#define G_DTU_WR_BYTE14(x) (((x) >> S_DTU_WR_BYTE14) & M_DTU_WR_BYTE14)
+
+#define S_DTU_WR_BYTE13    8
+#define M_DTU_WR_BYTE13    0xffU
+#define V_DTU_WR_BYTE13(x) ((x) << S_DTU_WR_BYTE13)
+#define G_DTU_WR_BYTE13(x) (((x) >> S_DTU_WR_BYTE13) & M_DTU_WR_BYTE13)
+
+#define S_DTU_WR_BYTE12    0
+#define M_DTU_WR_BYTE12    0xffU
+#define V_DTU_WR_BYTE12(x) ((x) << S_DTU_WR_BYTE12)
+#define G_DTU_WR_BYTE12(x) (((x) >> S_DTU_WR_BYTE12) & M_DTU_WR_BYTE12)
+
+#define A_MC_PCTL_DTUWDM 0x6420
+
+#define S_DM_WR_BYTE0    0
+#define M_DM_WR_BYTE0    0xffffU
+#define V_DM_WR_BYTE0(x) ((x) << S_DM_WR_BYTE0)
+#define G_DM_WR_BYTE0(x) (((x) >> S_DM_WR_BYTE0) & M_DM_WR_BYTE0)
+
+#define A_MC_PCTL_DTURD0 0x6424
+
+#define S_DTU_RD_BYTE3    24
+#define M_DTU_RD_BYTE3    0xffU
+#define V_DTU_RD_BYTE3(x) ((x) << S_DTU_RD_BYTE3)
+#define G_DTU_RD_BYTE3(x) (((x) >> S_DTU_RD_BYTE3) & M_DTU_RD_BYTE3)
+
+#define S_DTU_RD_BYTE2    16
+#define M_DTU_RD_BYTE2    0xffU
+#define V_DTU_RD_BYTE2(x) ((x) << S_DTU_RD_BYTE2)
+#define G_DTU_RD_BYTE2(x) (((x) >> S_DTU_RD_BYTE2) & M_DTU_RD_BYTE2)
+
+#define S_DTU_RD_BYTE1    8
+#define M_DTU_RD_BYTE1    0xffU
+#define V_DTU_RD_BYTE1(x) ((x) << S_DTU_RD_BYTE1)
+#define G_DTU_RD_BYTE1(x) (((x) >> S_DTU_RD_BYTE1) & M_DTU_RD_BYTE1)
+
+#define S_DTU_RD_BYTE0    0
+#define M_DTU_RD_BYTE0    0xffU
+#define V_DTU_RD_BYTE0(x) ((x) << S_DTU_RD_BYTE0)
+#define G_DTU_RD_BYTE0(x) (((x) >> S_DTU_RD_BYTE0) & M_DTU_RD_BYTE0)
+
+#define A_MC_PCTL_DTURD1 0x6428
+
+#define S_DTU_RD_BYTE7    24
+#define M_DTU_RD_BYTE7    0xffU
+#define V_DTU_RD_BYTE7(x) ((x) << S_DTU_RD_BYTE7)
+#define G_DTU_RD_BYTE7(x) (((x) >> S_DTU_RD_BYTE7) & M_DTU_RD_BYTE7)
+
+#define S_DTU_RD_BYTE6    16
+#define M_DTU_RD_BYTE6    0xffU
+#define V_DTU_RD_BYTE6(x) ((x) << S_DTU_RD_BYTE6)
+#define G_DTU_RD_BYTE6(x) (((x) >> S_DTU_RD_BYTE6) & M_DTU_RD_BYTE6)
+
+#define S_DTU_RD_BYTE5    8
+#define M_DTU_RD_BYTE5    0xffU
+#define V_DTU_RD_BYTE5(x) ((x) << S_DTU_RD_BYTE5)
+#define G_DTU_RD_BYTE5(x) (((x) >> S_DTU_RD_BYTE5) & M_DTU_RD_BYTE5)
+
+#define S_DTU_RD_BYTE4    0
+#define M_DTU_RD_BYTE4    0xffU
+#define V_DTU_RD_BYTE4(x) ((x) << S_DTU_RD_BYTE4)
+#define G_DTU_RD_BYTE4(x) (((x) >> S_DTU_RD_BYTE4) & M_DTU_RD_BYTE4)
+
+#define A_MC_PCTL_DTURD2 0x642c
+
+#define S_DTU_RD_BYTE11    24
+#define M_DTU_RD_BYTE11    0xffU
+#define V_DTU_RD_BYTE11(x) ((x) << S_DTU_RD_BYTE11)
+#define G_DTU_RD_BYTE11(x) (((x) >> S_DTU_RD_BYTE11) & M_DTU_RD_BYTE11)
+
+#define S_DTU_RD_BYTE10    16
+#define M_DTU_RD_BYTE10    0xffU
+#define V_DTU_RD_BYTE10(x) ((x) << S_DTU_RD_BYTE10)
+#define G_DTU_RD_BYTE10(x) (((x) >> S_DTU_RD_BYTE10) & M_DTU_RD_BYTE10)
+
+#define S_DTU_RD_BYTE9    8
+#define M_DTU_RD_BYTE9    0xffU
+#define V_DTU_RD_BYTE9(x) ((x) << S_DTU_RD_BYTE9)
+#define G_DTU_RD_BYTE9(x) (((x) >> S_DTU_RD_BYTE9) & M_DTU_RD_BYTE9)
+
+#define S_DTU_RD_BYTE8    0
+#define M_DTU_RD_BYTE8    0xffU
+#define V_DTU_RD_BYTE8(x) ((x) << S_DTU_RD_BYTE8)
+#define G_DTU_RD_BYTE8(x) (((x) >> S_DTU_RD_BYTE8) & M_DTU_RD_BYTE8)
+
+#define A_MC_PCTL_DTURD3 0x6430
+
+#define S_DTU_RD_BYTE15    24
+#define M_DTU_RD_BYTE15    0xffU
+#define V_DTU_RD_BYTE15(x) ((x) << S_DTU_RD_BYTE15)
+#define G_DTU_RD_BYTE15(x) (((x) >> S_DTU_RD_BYTE15) & M_DTU_RD_BYTE15)
+
+#define S_DTU_RD_BYTE14    16
+#define M_DTU_RD_BYTE14    0xffU
+#define V_DTU_RD_BYTE14(x) ((x) << S_DTU_RD_BYTE14)
+#define G_DTU_RD_BYTE14(x) (((x) >> S_DTU_RD_BYTE14) & M_DTU_RD_BYTE14)
+
+#define S_DTU_RD_BYTE13    8
+#define M_DTU_RD_BYTE13    0xffU
+#define V_DTU_RD_BYTE13(x) ((x) << S_DTU_RD_BYTE13)
+#define G_DTU_RD_BYTE13(x) (((x) >> S_DTU_RD_BYTE13) & M_DTU_RD_BYTE13)
+
+#define S_DTU_RD_BYTE12    0
+#define M_DTU_RD_BYTE12    0xffU
+#define V_DTU_RD_BYTE12(x) ((x) << S_DTU_RD_BYTE12)
+#define G_DTU_RD_BYTE12(x) (((x) >> S_DTU_RD_BYTE12) & M_DTU_RD_BYTE12)
+
+#define A_MC_DTULFSRWD 0x6434
+#define A_MC_PCTL_DTULFSRRD 0x6438
+#define A_MC_PCTL_DTUEAF 0x643c
+
+#define S_EA_RANK    30
+#define M_EA_RANK    0x3U
+#define V_EA_RANK(x) ((x) << S_EA_RANK)
+#define G_EA_RANK(x) (((x) >> S_EA_RANK) & M_EA_RANK)
+
+#define S_EA_ROW    13
+#define M_EA_ROW    0x1ffffU
+#define V_EA_ROW(x) ((x) << S_EA_ROW)
+#define G_EA_ROW(x) (((x) >> S_EA_ROW) & M_EA_ROW)
+
+#define S_EA_BANK    10
+#define M_EA_BANK    0x7U
+#define V_EA_BANK(x) ((x) << S_EA_BANK)
+#define G_EA_BANK(x) (((x) >> S_EA_BANK) & M_EA_BANK)
+
+#define S_EA_COLUMN    0
+#define M_EA_COLUMN    0x3ffU
+#define V_EA_COLUMN(x) ((x) << S_EA_COLUMN)
+#define G_EA_COLUMN(x) (((x) >> S_EA_COLUMN) & M_EA_COLUMN)
+
+#define A_MC_PCTL_PHYPVTCFG 0x6500
+
+#define S_PVT_UPD_REQ_EN    15
+#define V_PVT_UPD_REQ_EN(x) ((x) << S_PVT_UPD_REQ_EN)
+#define F_PVT_UPD_REQ_EN    V_PVT_UPD_REQ_EN(1U)
+
+#define S_PVT_UPD_TRIG_POL    14
+#define V_PVT_UPD_TRIG_POL(x) ((x) << S_PVT_UPD_TRIG_POL)
+#define F_PVT_UPD_TRIG_POL    V_PVT_UPD_TRIG_POL(1U)
+
+#define S_PVT_UPD_TRIG_TYPE    12
+#define V_PVT_UPD_TRIG_TYPE(x) ((x) << S_PVT_UPD_TRIG_TYPE)
+#define F_PVT_UPD_TRIG_TYPE    V_PVT_UPD_TRIG_TYPE(1U)
+
+#define S_PVT_UPD_DONE_POL    10
+#define V_PVT_UPD_DONE_POL(x) ((x) << S_PVT_UPD_DONE_POL)
+#define F_PVT_UPD_DONE_POL    V_PVT_UPD_DONE_POL(1U)
+
+#define S_PVT_UPD_DONE_TYPE    8
+#define M_PVT_UPD_DONE_TYPE    0x3U
+#define V_PVT_UPD_DONE_TYPE(x) ((x) << S_PVT_UPD_DONE_TYPE)
+#define G_PVT_UPD_DONE_TYPE(x) (((x) >> S_PVT_UPD_DONE_TYPE) & M_PVT_UPD_DONE_TYPE)
+
+#define S_PHY_UPD_REQ_EN    7
+#define V_PHY_UPD_REQ_EN(x) ((x) << S_PHY_UPD_REQ_EN)
+#define F_PHY_UPD_REQ_EN    V_PHY_UPD_REQ_EN(1U)
+
+#define S_PHY_UPD_TRIG_POL    6
+#define V_PHY_UPD_TRIG_POL(x) ((x) << S_PHY_UPD_TRIG_POL)
+#define F_PHY_UPD_TRIG_POL    V_PHY_UPD_TRIG_POL(1U)
+
+#define S_PHY_UPD_TRIG_TYPE    4
+#define V_PHY_UPD_TRIG_TYPE(x) ((x) << S_PHY_UPD_TRIG_TYPE)
+#define F_PHY_UPD_TRIG_TYPE    V_PHY_UPD_TRIG_TYPE(1U)
+
+#define S_PHY_UPD_DONE_POL    2
+#define V_PHY_UPD_DONE_POL(x) ((x) << S_PHY_UPD_DONE_POL)
+#define F_PHY_UPD_DONE_POL    V_PHY_UPD_DONE_POL(1U)
+
+#define S_PHY_UPD_DONE_TYPE    0
+#define M_PHY_UPD_DONE_TYPE    0x3U
+#define V_PHY_UPD_DONE_TYPE(x) ((x) << S_PHY_UPD_DONE_TYPE)
+#define G_PHY_UPD_DONE_TYPE(x) (((x) >> S_PHY_UPD_DONE_TYPE) & M_PHY_UPD_DONE_TYPE)
+
+#define A_MC_PCTL_PHYPVTSTAT 0x6504
+
+#define S_I_PVT_UPD_TRIG    5
+#define V_I_PVT_UPD_TRIG(x) ((x) << S_I_PVT_UPD_TRIG)
+#define F_I_PVT_UPD_TRIG    V_I_PVT_UPD_TRIG(1U)
+
+#define S_I_PVT_UPD_DONE    4
+#define V_I_PVT_UPD_DONE(x) ((x) << S_I_PVT_UPD_DONE)
+#define F_I_PVT_UPD_DONE    V_I_PVT_UPD_DONE(1U)
+
+#define S_I_PHY_UPD_TRIG    1
+#define V_I_PHY_UPD_TRIG(x) ((x) << S_I_PHY_UPD_TRIG)
+#define F_I_PHY_UPD_TRIG    V_I_PHY_UPD_TRIG(1U)
+
+#define S_I_PHY_UPD_DONE    0
+#define V_I_PHY_UPD_DONE(x) ((x) << S_I_PHY_UPD_DONE)
+#define F_I_PHY_UPD_DONE    V_I_PHY_UPD_DONE(1U)
+
+#define A_MC_PCTL_PHYTUPDON 0x6508
+
+#define S_PHY_T_UPDON    0
+#define M_PHY_T_UPDON    0xffU
+#define V_PHY_T_UPDON(x) ((x) << S_PHY_T_UPDON)
+#define G_PHY_T_UPDON(x) (((x) >> S_PHY_T_UPDON) & M_PHY_T_UPDON)
+
+#define A_MC_PCTL_PHYTUPDDLY 0x650c
+
+#define S_PHY_T_UPDDLY    0
+#define M_PHY_T_UPDDLY    0xfU
+#define V_PHY_T_UPDDLY(x) ((x) << S_PHY_T_UPDDLY)
+#define G_PHY_T_UPDDLY(x) (((x) >> S_PHY_T_UPDDLY) & M_PHY_T_UPDDLY)
+
+#define A_MC_PCTL_PVTTUPON 0x6510
+
+#define S_PVT_T_UPDON    0
+#define M_PVT_T_UPDON    0xffU
+#define V_PVT_T_UPDON(x) ((x) << S_PVT_T_UPDON)
+#define G_PVT_T_UPDON(x) (((x) >> S_PVT_T_UPDON) & M_PVT_T_UPDON)
+
+#define A_MC_PCTL_PVTTUPDDLY 0x6514
+
+#define S_PVT_T_UPDDLY    0
+#define M_PVT_T_UPDDLY    0xfU
+#define V_PVT_T_UPDDLY(x) ((x) << S_PVT_T_UPDDLY)
+#define G_PVT_T_UPDDLY(x) (((x) >> S_PVT_T_UPDDLY) & M_PVT_T_UPDDLY)
+
+#define A_MC_PCTL_PHYPVTUPDI 0x6518
+
+#define S_PHYPVT_T_UPDI    0
+#define M_PHYPVT_T_UPDI    0xffU
+#define V_PHYPVT_T_UPDI(x) ((x) << S_PHYPVT_T_UPDI)
+#define G_PHYPVT_T_UPDI(x) (((x) >> S_PHYPVT_T_UPDI) & M_PHYPVT_T_UPDI)
+
+#define A_MC_PCTL_PHYIOCRV1 0x651c
+
+#define S_BYTE_OE_CTL    16
+#define M_BYTE_OE_CTL    0x3U
+#define V_BYTE_OE_CTL(x) ((x) << S_BYTE_OE_CTL)
+#define G_BYTE_OE_CTL(x) (((x) >> S_BYTE_OE_CTL) & M_BYTE_OE_CTL)
+
+#define S_DYN_SOC_ODT_ALAT    12
+#define M_DYN_SOC_ODT_ALAT    0xfU
+#define V_DYN_SOC_ODT_ALAT(x) ((x) << S_DYN_SOC_ODT_ALAT)
+#define G_DYN_SOC_ODT_ALAT(x) (((x) >> S_DYN_SOC_ODT_ALAT) & M_DYN_SOC_ODT_ALAT)
+
+#define S_DYN_SOC_ODT_ATEN    8
+#define M_DYN_SOC_ODT_ATEN    0x3U
+#define V_DYN_SOC_ODT_ATEN(x) ((x) << S_DYN_SOC_ODT_ATEN)
+#define G_DYN_SOC_ODT_ATEN(x) (((x) >> S_DYN_SOC_ODT_ATEN) & M_DYN_SOC_ODT_ATEN)
+
+#define S_DYN_SOC_ODT    2
+#define V_DYN_SOC_ODT(x) ((x) << S_DYN_SOC_ODT)
+#define F_DYN_SOC_ODT    V_DYN_SOC_ODT(1U)
+
+#define S_SOC_ODT_EN    0
+#define V_SOC_ODT_EN(x) ((x) << S_SOC_ODT_EN)
+#define F_SOC_ODT_EN    V_SOC_ODT_EN(1U)
+
+#define A_MC_PCTL_PHYTUPDWAIT 0x6520
+
+#define S_PHY_T_UPDWAIT    0
+#define M_PHY_T_UPDWAIT    0x3fU
+#define V_PHY_T_UPDWAIT(x) ((x) << S_PHY_T_UPDWAIT)
+#define G_PHY_T_UPDWAIT(x) (((x) >> S_PHY_T_UPDWAIT) & M_PHY_T_UPDWAIT)
+
+#define A_MC_PCTL_PVTTUPDWAIT 0x6524
+
+#define S_PVT_T_UPDWAIT    0
+#define M_PVT_T_UPDWAIT    0x3fU
+#define V_PVT_T_UPDWAIT(x) ((x) << S_PVT_T_UPDWAIT)
+#define G_PVT_T_UPDWAIT(x) (((x) >> S_PVT_T_UPDWAIT) & M_PVT_T_UPDWAIT)
+
+#define A_MC_DDR3PHYAC_GCR 0x6a00
+
+#define S_WLRANK    8
+#define M_WLRANK    0x3U
+#define V_WLRANK(x) ((x) << S_WLRANK)
+#define G_WLRANK(x) (((x) >> S_WLRANK) & M_WLRANK)
+
+#define S_FDEPTH    6
+#define M_FDEPTH    0x3U
+#define V_FDEPTH(x) ((x) << S_FDEPTH)
+#define G_FDEPTH(x) (((x) >> S_FDEPTH) & M_FDEPTH)
+
+#define S_LPFDEPTH    4
+#define M_LPFDEPTH    0x3U
+#define V_LPFDEPTH(x) ((x) << S_LPFDEPTH)
+#define G_LPFDEPTH(x) (((x) >> S_LPFDEPTH) & M_LPFDEPTH)
+
+#define S_LPFEN    3
+#define V_LPFEN(x) ((x) << S_LPFEN)
+#define F_LPFEN    V_LPFEN(1U)
+
+#define S_WL    2
+#define V_WL(x) ((x) << S_WL)
+#define F_WL    V_WL(1U)
+
+#define S_CAL    1
+#define V_CAL(x) ((x) << S_CAL)
+#define F_CAL    V_CAL(1U)
+
+#define S_MDLEN    0
+#define V_MDLEN(x) ((x) << S_MDLEN)
+#define F_MDLEN    V_MDLEN(1U)
+
+#define A_MC_DDR3PHYAC_RCR0 0x6a04
+
+#define S_OCPONR    8
+#define V_OCPONR(x) ((x) << S_OCPONR)
+#define F_OCPONR    V_OCPONR(1U)
+
+#define S_OCPOND    7
+#define V_OCPOND(x) ((x) << S_OCPOND)
+#define F_OCPOND    V_OCPOND(1U)
+
+#define S_OCOEN    6
+#define V_OCOEN(x) ((x) << S_OCOEN)
+#define F_OCOEN    V_OCOEN(1U)
+
+#define S_CKEPONR    5
+#define V_CKEPONR(x) ((x) << S_CKEPONR)
+#define F_CKEPONR    V_CKEPONR(1U)
+
+#define S_CKEPOND    4
+#define V_CKEPOND(x) ((x) << S_CKEPOND)
+#define F_CKEPOND    V_CKEPOND(1U)
+
+#define S_CKEOEN    3
+#define V_CKEOEN(x) ((x) << S_CKEOEN)
+#define F_CKEOEN    V_CKEOEN(1U)
+
+#define S_CKPONR    2
+#define V_CKPONR(x) ((x) << S_CKPONR)
+#define F_CKPONR    V_CKPONR(1U)
+
+#define S_CKPOND    1
+#define V_CKPOND(x) ((x) << S_CKPOND)
+#define F_CKPOND    V_CKPOND(1U)
+
+#define S_CKOEN    0
+#define V_CKOEN(x) ((x) << S_CKOEN)
+#define F_CKOEN    V_CKOEN(1U)
+
+#define A_MC_DDR3PHYAC_ACCR 0x6a14
+
+#define S_ACPONR    8
+#define V_ACPONR(x) ((x) << S_ACPONR)
+#define F_ACPONR    V_ACPONR(1U)
+
+#define S_ACPOND    7
+#define V_ACPOND(x) ((x) << S_ACPOND)
+#define F_ACPOND    V_ACPOND(1U)
+
+#define S_ACOEN    6
+#define V_ACOEN(x) ((x) << S_ACOEN)
+#define F_ACOEN    V_ACOEN(1U)
+
+#define S_CK5PONR    5
+#define V_CK5PONR(x) ((x) << S_CK5PONR)
+#define F_CK5PONR    V_CK5PONR(1U)
+
+#define S_CK5POND    4
+#define V_CK5POND(x) ((x) << S_CK5POND)
+#define F_CK5POND    V_CK5POND(1U)
+
+#define S_CK5OEN    3
+#define V_CK5OEN(x) ((x) << S_CK5OEN)
+#define F_CK5OEN    V_CK5OEN(1U)
+
+#define S_CK4PONR    2
+#define V_CK4PONR(x) ((x) << S_CK4PONR)
+#define F_CK4PONR    V_CK4PONR(1U)
+
+#define S_CK4POND    1
+#define V_CK4POND(x) ((x) << S_CK4POND)
+#define F_CK4POND    V_CK4POND(1U)
+
+#define S_CK4OEN    0
+#define V_CK4OEN(x) ((x) << S_CK4OEN)
+#define F_CK4OEN    V_CK4OEN(1U)
+
+#define A_MC_DDR3PHYAC_GSR 0x6a18
+
+#define S_WLERR    4
+#define V_WLERR(x) ((x) << S_WLERR)
+#define F_WLERR    V_WLERR(1U)
+
+#define S_INIT    3
+#define V_INIT(x) ((x) << S_INIT)
+#define F_INIT    V_INIT(1U)
+
+#define S_ACCAL    0
+#define V_ACCAL(x) ((x) << S_ACCAL)
+#define F_ACCAL    V_ACCAL(1U)
+
+#define A_MC_DDR3PHYAC_ECSR 0x6a1c
+
+#define S_WLDEC    1
+#define V_WLDEC(x) ((x) << S_WLDEC)
+#define F_WLDEC    V_WLDEC(1U)
+
+#define S_WLINC    0
+#define V_WLINC(x) ((x) << S_WLINC)
+#define F_WLINC    V_WLINC(1U)
+
+#define A_MC_DDR3PHYAC_OCSR 0x6a20
+#define A_MC_DDR3PHYAC_MDIPR 0x6a24
+
+#define S_PRD    0
+#define M_PRD    0x3ffU
+#define V_PRD(x) ((x) << S_PRD)
+#define G_PRD(x) (((x) >> S_PRD) & M_PRD)
+
+#define A_MC_DDR3PHYAC_MDTPR 0x6a28
+#define A_MC_DDR3PHYAC_MDPPR0 0x6a2c
+#define A_MC_DDR3PHYAC_MDPPR1 0x6a30
+#define A_MC_DDR3PHYAC_PMBDR0 0x6a34
+
+#define S_DFLTDLY    0
+#define M_DFLTDLY    0x7fU
+#define V_DFLTDLY(x) ((x) << S_DFLTDLY)
+#define G_DFLTDLY(x) (((x) >> S_DFLTDLY) & M_DFLTDLY)
+
+#define A_MC_DDR3PHYAC_PMBDR1 0x6a38
+#define A_MC_DDR3PHYAC_ACR 0x6a60
+
+#define S_TSEL    9
+#define V_TSEL(x) ((x) << S_TSEL)
+#define F_TSEL    V_TSEL(1U)
+
+#define S_ISEL    7
+#define M_ISEL    0x3U
+#define V_ISEL(x) ((x) << S_ISEL)
+#define G_ISEL(x) (((x) >> S_ISEL) & M_ISEL)
+
+#define S_CALBYP    2
+#define V_CALBYP(x) ((x) << S_CALBYP)
+#define F_CALBYP    V_CALBYP(1U)
+
+#define S_SDRSELINV    1
+#define V_SDRSELINV(x) ((x) << S_SDRSELINV)
+#define F_SDRSELINV    V_SDRSELINV(1U)
+
+#define S_CKINV    0
+#define V_CKINV(x) ((x) << S_CKINV)
+#define F_CKINV    V_CKINV(1U)
+
+#define A_MC_DDR3PHYAC_PSCR 0x6a64
+
+#define S_PSCALE    0
+#define M_PSCALE    0x3ffU
+#define V_PSCALE(x) ((x) << S_PSCALE)
+#define G_PSCALE(x) (((x) >> S_PSCALE) & M_PSCALE)
+
+#define A_MC_DDR3PHYAC_PRCR 0x6a68
+
+#define S_PHYINIT    9
+#define V_PHYINIT(x) ((x) << S_PHYINIT)
+#define F_PHYINIT    V_PHYINIT(1U)
+
+#define S_PHYHRST    7
+#define V_PHYHRST(x) ((x) << S_PHYHRST)
+#define F_PHYHRST    V_PHYHRST(1U)
+
+#define S_RSTCLKS    3
+#define M_RSTCLKS    0xfU
+#define V_RSTCLKS(x) ((x) << S_RSTCLKS)
+#define G_RSTCLKS(x) (((x) >> S_RSTCLKS) & M_RSTCLKS)
+
+#define S_PLLPD    2
+#define V_PLLPD(x) ((x) << S_PLLPD)
+#define F_PLLPD    V_PLLPD(1U)
+
+#define S_PLLRST    1
+#define V_PLLRST(x) ((x) << S_PLLRST)
+#define F_PLLRST    V_PLLRST(1U)
+
+#define S_PHYRST    0
+#define V_PHYRST(x) ((x) << S_PHYRST)
+#define F_PHYRST    V_PHYRST(1U)
+
+#define A_MC_DDR3PHYAC_PLLCR0 0x6a6c
+
+#define S_RSTCXKS    4
+#define M_RSTCXKS    0x1fU
+#define V_RSTCXKS(x) ((x) << S_RSTCXKS)
+#define G_RSTCXKS(x) (((x) >> S_RSTCXKS) & M_RSTCXKS)
+
+#define S_ICPSEL    3
+#define V_ICPSEL(x) ((x) << S_ICPSEL)
+#define F_ICPSEL    V_ICPSEL(1U)
+
+#define S_TESTA    0
+#define M_TESTA    0x7U
+#define V_TESTA(x) ((x) << S_TESTA)
+#define G_TESTA(x) (((x) >> S_TESTA) & M_TESTA)
+
+#define A_MC_DDR3PHYAC_PLLCR1 0x6a70
+
+#define S_BYPASS    9
+#define V_BYPASS(x) ((x) << S_BYPASS)
+#define F_BYPASS    V_BYPASS(1U)
+
+#define S_BDIV    3
+#define M_BDIV    0x3U
+#define V_BDIV(x) ((x) << S_BDIV)
+#define G_BDIV(x) (((x) >> S_BDIV) & M_BDIV)
+
+#define S_TESTD    0
+#define M_TESTD    0x7U
+#define V_TESTD(x) ((x) << S_TESTD)
+#define G_TESTD(x) (((x) >> S_TESTD) & M_TESTD)
+
+#define A_MC_DDR3PHYAC_CLKENR 0x6a78
+
+#define S_CKCLKEN    3
+#define M_CKCLKEN    0x3fU
+#define V_CKCLKEN(x) ((x) << S_CKCLKEN)
+#define G_CKCLKEN(x) (((x) >> S_CKCLKEN) & M_CKCLKEN)
+
+#define S_HDRCLKEN    2
+#define V_HDRCLKEN(x) ((x) << S_HDRCLKEN)
+#define F_HDRCLKEN    V_HDRCLKEN(1U)
+
+#define S_SDRCLKEN    1
+#define V_SDRCLKEN(x) ((x) << S_SDRCLKEN)
+#define F_SDRCLKEN    V_SDRCLKEN(1U)
+
+#define S_DDRCLKEN    0
+#define V_DDRCLKEN(x) ((x) << S_DDRCLKEN)
+#define F_DDRCLKEN    V_DDRCLKEN(1U)
+
+#define A_MC_DDR3PHYDATX8_GCR 0x6b00
+
+#define S_PONR    6
+#define V_PONR(x) ((x) << S_PONR)
+#define F_PONR    V_PONR(1U)
+
+#define S_POND    5
+#define V_POND(x) ((x) << S_POND)
+#define F_POND    V_POND(1U)
+
+#define S_RDBDVT    4
+#define V_RDBDVT(x) ((x) << S_RDBDVT)
+#define F_RDBDVT    V_RDBDVT(1U)
+
+#define S_WDBDVT    3
+#define V_WDBDVT(x) ((x) << S_WDBDVT)
+#define F_WDBDVT    V_WDBDVT(1U)
+
+#define S_RDSDVT    2
+#define V_RDSDVT(x) ((x) << S_RDSDVT)
+#define F_RDSDVT    V_RDSDVT(1U)
+
+#define S_WDSDVT    1
+#define V_WDSDVT(x) ((x) << S_WDSDVT)
+#define F_WDSDVT    V_WDSDVT(1U)
+
+#define S_WLSDVT    0
+#define V_WLSDVT(x) ((x) << S_WLSDVT)
+#define F_WLSDVT    V_WLSDVT(1U)
+
+#define A_MC_DDR3PHYDATX8_WDSDR 0x6b04
+
+#define S_WDSDR_DLY    0
+#define M_WDSDR_DLY    0x3ffU
+#define V_WDSDR_DLY(x) ((x) << S_WDSDR_DLY)
+#define G_WDSDR_DLY(x) (((x) >> S_WDSDR_DLY) & M_WDSDR_DLY)
+
+#define A_MC_DDR3PHYDATX8_WLDPR 0x6b08
+#define A_MC_DDR3PHYDATX8_WLDR 0x6b0c
+
+#define S_WL_DLY    0
+#define M_WL_DLY    0x3ffU
+#define V_WL_DLY(x) ((x) << S_WL_DLY)
+#define G_WL_DLY(x) (((x) >> S_WL_DLY) & M_WL_DLY)
+
+#define A_MC_DDR3PHYDATX8_WDBDR0 0x6b1c
+
+#define S_DLY    0
+#define M_DLY    0x7fU
+#define V_DLY(x) ((x) << S_DLY)
+#define G_DLY(x) (((x) >> S_DLY) & M_DLY)
+
+#define A_MC_DDR3PHYDATX8_WDBDR1 0x6b20
+#define A_MC_DDR3PHYDATX8_WDBDR2 0x6b24
+#define A_MC_DDR3PHYDATX8_WDBDR3 0x6b28
+#define A_MC_DDR3PHYDATX8_WDBDR4 0x6b2c
+#define A_MC_DDR3PHYDATX8_WDBDR5 0x6b30
+#define A_MC_DDR3PHYDATX8_WDBDR6 0x6b34
+#define A_MC_DDR3PHYDATX8_WDBDR7 0x6b38
+#define A_MC_DDR3PHYDATX8_WDBDR8 0x6b3c
+#define A_MC_DDR3PHYDATX8_WDBDMR 0x6b40
+
+#define S_MAXDLY    0
+#define M_MAXDLY    0x7fU
+#define V_MAXDLY(x) ((x) << S_MAXDLY)
+#define G_MAXDLY(x) (((x) >> S_MAXDLY) & M_MAXDLY)
+
+#define A_MC_DDR3PHYDATX8_RDSDR 0x6b44
+
+#define S_RDSDR_DLY    0
+#define M_RDSDR_DLY    0x3ffU
+#define V_RDSDR_DLY(x) ((x) << S_RDSDR_DLY)
+#define G_RDSDR_DLY(x) (((x) >> S_RDSDR_DLY) & M_RDSDR_DLY)
+
+#define A_MC_DDR3PHYDATX8_RDBDR0 0x6b48
+#define A_MC_DDR3PHYDATX8_RDBDR1 0x6b4c
+#define A_MC_DDR3PHYDATX8_RDBDR2 0x6b50
+#define A_MC_DDR3PHYDATX8_RDBDR3 0x6b54
+#define A_MC_DDR3PHYDATX8_RDBDR4 0x6b58
+#define A_MC_DDR3PHYDATX8_RDBDR5 0x6b5c
+#define A_MC_DDR3PHYDATX8_RDBDR6 0x6b60
+#define A_MC_DDR3PHYDATX8_RDBDR7 0x6b64
+#define A_MC_DDR3PHYDATX8_RDBDMR 0x6b68
+#define A_MC_DDR3PHYDATX8_PMBDR0 0x6b6c
+#define A_MC_DDR3PHYDATX8_PMBDR1 0x6b70
+#define A_MC_DDR3PHYDATX8_PMBDR2 0x6b74
+#define A_MC_DDR3PHYDATX8_PMBDR3 0x6b78
+#define A_MC_DDR3PHYDATX8_WDBDPR 0x6b7c
+
+#define S_DP_DLY    0
+#define M_DP_DLY    0x1ffU
+#define V_DP_DLY(x) ((x) << S_DP_DLY)
+#define G_DP_DLY(x) (((x) >> S_DP_DLY) & M_DP_DLY)
+
+#define A_MC_DDR3PHYDATX8_RDBDPR 0x6b80
+#define A_MC_DDR3PHYDATX8_GSR 0x6b84
+
+#define S_WLDONE    3
+#define V_WLDONE(x) ((x) << S_WLDONE)
+#define F_WLDONE    V_WLDONE(1U)
+
+#define S_WLCAL    2
+#define V_WLCAL(x) ((x) << S_WLCAL)
+#define F_WLCAL    V_WLCAL(1U)
+
+#define S_READ    1
+#define V_READ(x) ((x) << S_READ)
+#define F_READ    V_READ(1U)
+
+#define S_RDQSCAL    0
+#define V_RDQSCAL(x) ((x) << S_RDQSCAL)
+#define F_RDQSCAL    V_RDQSCAL(1U)
+
+#define A_MC_DDR3PHYDATX8_ACR 0x6bf0
+
+#define S_PHYHSRST    9
+#define V_PHYHSRST(x) ((x) << S_PHYHSRST)
+#define F_PHYHSRST    V_PHYHSRST(1U)
+
+#define S_WLSTEP    8
+#define V_WLSTEP(x) ((x) << S_WLSTEP)
+#define F_WLSTEP    V_WLSTEP(1U)
+
+#define S_SDR_SEL_INV    2
+#define V_SDR_SEL_INV(x) ((x) << S_SDR_SEL_INV)
+#define F_SDR_SEL_INV    V_SDR_SEL_INV(1U)
+
+#define S_DDRSELINV    1
+#define V_DDRSELINV(x) ((x) << S_DDRSELINV)
+#define F_DDRSELINV    V_DDRSELINV(1U)
+
+#define S_DSINV    0
+#define V_DSINV(x) ((x) << S_DSINV)
+#define F_DSINV    V_DSINV(1U)
+
+#define A_MC_DDR3PHYDATX8_RSR 0x6bf4
+
+#define S_WLRANKSEL    9
+#define V_WLRANKSEL(x) ((x) << S_WLRANKSEL)
+#define F_WLRANKSEL    V_WLRANKSEL(1U)
+
+#define S_RANK    0
+#define M_RANK    0x3U
+#define V_RANK(x) ((x) << S_RANK)
+#define G_RANK(x) (((x) >> S_RANK) & M_RANK)
+
+#define A_MC_DDR3PHYDATX8_CLKENR 0x6bf8
+
+#define S_DTOSEL    8
+#define M_DTOSEL    0x3U
+#define V_DTOSEL(x) ((x) << S_DTOSEL)
+#define G_DTOSEL(x) (((x) >> S_DTOSEL) & M_DTOSEL)
+
+#define A_MC_PVT_REG_CALIBRATE_CTL 0x7400
+#define A_MC_PVT_REG_UPDATE_CTL 0x7404
+#define A_MC_PVT_REG_LAST_MEASUREMENT 0x7408
+#define A_MC_PVT_REG_DRVN 0x740c
+#define A_MC_PVT_REG_DRVP 0x7410
+#define A_MC_PVT_REG_TERMN 0x7414
+#define A_MC_PVT_REG_TERMP 0x7418
+#define A_MC_PVT_REG_THRESHOLD 0x741c
+#define A_MC_PVT_REG_IN_TERMP 0x7420
+#define A_MC_PVT_REG_IN_TERMN 0x7424
+#define A_MC_PVT_REG_IN_DRVP 0x7428
+#define A_MC_PVT_REG_IN_DRVN 0x742c
+#define A_MC_PVT_REG_OUT_TERMP 0x7430
+#define A_MC_PVT_REG_OUT_TERMN 0x7434
+#define A_MC_PVT_REG_OUT_DRVP 0x7438
+#define A_MC_PVT_REG_OUT_DRVN 0x743c
+#define A_MC_PVT_REG_HISTORY_TERMP 0x7440
+#define A_MC_PVT_REG_HISTORY_TERMN 0x7444
+#define A_MC_PVT_REG_HISTORY_DRVP 0x7448
+#define A_MC_PVT_REG_HISTORY_DRVN 0x744c
+#define A_MC_PVT_REG_SAMPLE_WAIT_CLKS 0x7450
+#define A_MC_DDRPHY_RST_CTRL 0x7500
+
+#define S_DDRIO_ENABLE    1
+#define V_DDRIO_ENABLE(x) ((x) << S_DDRIO_ENABLE)
+#define F_DDRIO_ENABLE    V_DDRIO_ENABLE(1U)
+
+#define S_PHY_RST_N    0
+#define V_PHY_RST_N(x) ((x) << S_PHY_RST_N)
+#define F_PHY_RST_N    V_PHY_RST_N(1U)
+
+#define A_MC_PERFORMANCE_CTRL 0x7504
+
+#define S_STALL_CHK_BIT    2
+#define V_STALL_CHK_BIT(x) ((x) << S_STALL_CHK_BIT)
+#define F_STALL_CHK_BIT    V_STALL_CHK_BIT(1U)
+
+#define S_DDR3_BRC_MODE    1
+#define V_DDR3_BRC_MODE(x) ((x) << S_DDR3_BRC_MODE)
+#define F_DDR3_BRC_MODE    V_DDR3_BRC_MODE(1U)
+
+#define S_RMW_PERF_CTRL    0
+#define V_RMW_PERF_CTRL(x) ((x) << S_RMW_PERF_CTRL)
+#define F_RMW_PERF_CTRL    V_RMW_PERF_CTRL(1U)
+
+#define A_MC_ECC_CTRL 0x7508
+
+#define S_ECC_BYPASS_BIST    1
+#define V_ECC_BYPASS_BIST(x) ((x) << S_ECC_BYPASS_BIST)
+#define F_ECC_BYPASS_BIST    V_ECC_BYPASS_BIST(1U)
+
+#define S_ECC_DISABLE    0
+#define V_ECC_DISABLE(x) ((x) << S_ECC_DISABLE)
+#define F_ECC_DISABLE    V_ECC_DISABLE(1U)
+
+#define A_MC_PAR_ENABLE 0x750c
+
+#define S_ECC_UE_PAR_ENABLE    3
+#define V_ECC_UE_PAR_ENABLE(x) ((x) << S_ECC_UE_PAR_ENABLE)
+#define F_ECC_UE_PAR_ENABLE    V_ECC_UE_PAR_ENABLE(1U)
+
+#define S_ECC_CE_PAR_ENABLE    2
+#define V_ECC_CE_PAR_ENABLE(x) ((x) << S_ECC_CE_PAR_ENABLE)
+#define F_ECC_CE_PAR_ENABLE    V_ECC_CE_PAR_ENABLE(1U)
+
+#define S_PERR_REG_INT_ENABLE    1
+#define V_PERR_REG_INT_ENABLE(x) ((x) << S_PERR_REG_INT_ENABLE)
+#define F_PERR_REG_INT_ENABLE    V_PERR_REG_INT_ENABLE(1U)
+
+#define S_PERR_BLK_INT_ENABLE    0
+#define V_PERR_BLK_INT_ENABLE(x) ((x) << S_PERR_BLK_INT_ENABLE)
+#define F_PERR_BLK_INT_ENABLE    V_PERR_BLK_INT_ENABLE(1U)
+
+#define A_MC_PAR_CAUSE 0x7510
+
+#define S_ECC_UE_PAR_CAUSE    3
+#define V_ECC_UE_PAR_CAUSE(x) ((x) << S_ECC_UE_PAR_CAUSE)
+#define F_ECC_UE_PAR_CAUSE    V_ECC_UE_PAR_CAUSE(1U)
+
+#define S_ECC_CE_PAR_CAUSE    2
+#define V_ECC_CE_PAR_CAUSE(x) ((x) << S_ECC_CE_PAR_CAUSE)
+#define F_ECC_CE_PAR_CAUSE    V_ECC_CE_PAR_CAUSE(1U)
+
+#define S_FIFOR_PAR_CAUSE    1
+#define V_FIFOR_PAR_CAUSE(x) ((x) << S_FIFOR_PAR_CAUSE)
+#define F_FIFOR_PAR_CAUSE    V_FIFOR_PAR_CAUSE(1U)
+
+#define S_RDATA_FIFOR_PAR_CAUSE    0
+#define V_RDATA_FIFOR_PAR_CAUSE(x) ((x) << S_RDATA_FIFOR_PAR_CAUSE)
+#define F_RDATA_FIFOR_PAR_CAUSE    V_RDATA_FIFOR_PAR_CAUSE(1U)
+
+#define A_MC_INT_ENABLE 0x7514
+
+#define S_ECC_UE_INT_ENABLE    2
+#define V_ECC_UE_INT_ENABLE(x) ((x) << S_ECC_UE_INT_ENABLE)
+#define F_ECC_UE_INT_ENABLE    V_ECC_UE_INT_ENABLE(1U)
+
+#define S_ECC_CE_INT_ENABLE    1
+#define V_ECC_CE_INT_ENABLE(x) ((x) << S_ECC_CE_INT_ENABLE)
+#define F_ECC_CE_INT_ENABLE    V_ECC_CE_INT_ENABLE(1U)
+
+#define S_PERR_INT_ENABLE    0
+#define V_PERR_INT_ENABLE(x) ((x) << S_PERR_INT_ENABLE)
+#define F_PERR_INT_ENABLE    V_PERR_INT_ENABLE(1U)
+
+#define A_MC_INT_CAUSE 0x7518
+
+#define S_ECC_UE_INT_CAUSE    2
+#define V_ECC_UE_INT_CAUSE(x) ((x) << S_ECC_UE_INT_CAUSE)
+#define F_ECC_UE_INT_CAUSE    V_ECC_UE_INT_CAUSE(1U)
+
+#define S_ECC_CE_INT_CAUSE    1
+#define V_ECC_CE_INT_CAUSE(x) ((x) << S_ECC_CE_INT_CAUSE)
+#define F_ECC_CE_INT_CAUSE    V_ECC_CE_INT_CAUSE(1U)
+
+#define S_PERR_INT_CAUSE    0
+#define V_PERR_INT_CAUSE(x) ((x) << S_PERR_INT_CAUSE)
+#define F_PERR_INT_CAUSE    V_PERR_INT_CAUSE(1U)
+
+#define A_MC_ECC_STATUS 0x751c
+
+#define S_ECC_CECNT    16
+#define M_ECC_CECNT    0xffffU
+#define V_ECC_CECNT(x) ((x) << S_ECC_CECNT)
+#define G_ECC_CECNT(x) (((x) >> S_ECC_CECNT) & M_ECC_CECNT)
+
+#define S_ECC_UECNT    0
+#define M_ECC_UECNT    0xffffU
+#define V_ECC_UECNT(x) ((x) << S_ECC_UECNT)
+#define G_ECC_UECNT(x) (((x) >> S_ECC_UECNT) & M_ECC_UECNT)
+
+#define A_MC_PHY_CTRL 0x7520
+
+#define S_CTLPHYRR    0
+#define V_CTLPHYRR(x) ((x) << S_CTLPHYRR)
+#define F_CTLPHYRR    V_CTLPHYRR(1U)
+
+#define A_MC_STATIC_CFG_STATUS 0x7524
+
+#define S_STATIC_MODE    9
+#define V_STATIC_MODE(x) ((x) << S_STATIC_MODE)
+#define F_STATIC_MODE    V_STATIC_MODE(1U)
+
+#define S_STATIC_DEN    6
+#define M_STATIC_DEN    0x7U
+#define V_STATIC_DEN(x) ((x) << S_STATIC_DEN)
+#define G_STATIC_DEN(x) (((x) >> S_STATIC_DEN) & M_STATIC_DEN)
+
+#define S_STATIC_ORG    5
+#define V_STATIC_ORG(x) ((x) << S_STATIC_ORG)
+#define F_STATIC_ORG    V_STATIC_ORG(1U)
+
+#define S_STATIC_RKS    4
+#define V_STATIC_RKS(x) ((x) << S_STATIC_RKS)
+#define F_STATIC_RKS    V_STATIC_RKS(1U)
+
+#define S_STATIC_WIDTH    1
+#define M_STATIC_WIDTH    0x7U
+#define V_STATIC_WIDTH(x) ((x) << S_STATIC_WIDTH)
+#define G_STATIC_WIDTH(x) (((x) >> S_STATIC_WIDTH) & M_STATIC_WIDTH)
+
+#define S_STATIC_SLOW    0
+#define V_STATIC_SLOW(x) ((x) << S_STATIC_SLOW)
+#define F_STATIC_SLOW    V_STATIC_SLOW(1U)
+
+#define A_MC_CORE_PCTL_STAT 0x7528
+
+#define S_PCTL_ACCESS_STAT    0
+#define M_PCTL_ACCESS_STAT    0x7U
+#define V_PCTL_ACCESS_STAT(x) ((x) << S_PCTL_ACCESS_STAT)
+#define G_PCTL_ACCESS_STAT(x) (((x) >> S_PCTL_ACCESS_STAT) & M_PCTL_ACCESS_STAT)
+
+#define A_MC_DEBUG_CNT 0x752c
+
+#define S_WDATA_OCNT    8
+#define M_WDATA_OCNT    0x1fU
+#define V_WDATA_OCNT(x) ((x) << S_WDATA_OCNT)
+#define G_WDATA_OCNT(x) (((x) >> S_WDATA_OCNT) & M_WDATA_OCNT)
+
+#define S_RDATA_OCNT    0
+#define M_RDATA_OCNT    0x1fU
+#define V_RDATA_OCNT(x) ((x) << S_RDATA_OCNT)
+#define G_RDATA_OCNT(x) (((x) >> S_RDATA_OCNT) & M_RDATA_OCNT)
+
+#define A_MC_BONUS 0x7530
+#define A_MC_BIST_CMD 0x7600
+
+#define S_START_BIST    31
+#define V_START_BIST(x) ((x) << S_START_BIST)
+#define F_START_BIST    V_START_BIST(1U)
+
+#define S_BIST_CMD_GAP    8
+#define M_BIST_CMD_GAP    0xffU
+#define V_BIST_CMD_GAP(x) ((x) << S_BIST_CMD_GAP)
+#define G_BIST_CMD_GAP(x) (((x) >> S_BIST_CMD_GAP) & M_BIST_CMD_GAP)
+
+#define S_BIST_OPCODE    0
+#define M_BIST_OPCODE    0x3U
+#define V_BIST_OPCODE(x) ((x) << S_BIST_OPCODE)
+#define G_BIST_OPCODE(x) (((x) >> S_BIST_OPCODE) & M_BIST_OPCODE)
+
+#define A_MC_BIST_CMD_ADDR 0x7604
+#define A_MC_BIST_CMD_LEN 0x7608
+#define A_MC_BIST_DATA_PATTERN 0x760c
+
+#define S_BIST_DATA_TYPE    0
+#define M_BIST_DATA_TYPE    0xfU
+#define V_BIST_DATA_TYPE(x) ((x) << S_BIST_DATA_TYPE)
+#define G_BIST_DATA_TYPE(x) (((x) >> S_BIST_DATA_TYPE) & M_BIST_DATA_TYPE)
+
+#define A_MC_BIST_USER_WDATA0 0x7614
+#define A_MC_BIST_USER_WDATA1 0x7618
+#define A_MC_BIST_USER_WDATA2 0x761c
+
+#define S_USER_DATA2    0
+#define M_USER_DATA2    0xffU
+#define V_USER_DATA2(x) ((x) << S_USER_DATA2)
+#define G_USER_DATA2(x) (((x) >> S_USER_DATA2) & M_USER_DATA2)
+
+#define A_MC_BIST_NUM_ERR 0x7680
+#define A_MC_BIST_ERR_FIRST_ADDR 0x7684
+#define A_MC_BIST_STATUS_RDATA 0x7688
+
+/* registers for module MA */
+#define MA_BASE_ADDR 0x7700
+
+#define A_MA_CLIENT0_RD_LATENCY_THRESHOLD 0x7700
+
+#define S_THRESHOLD1    17
+#define M_THRESHOLD1    0x7fffU
+#define V_THRESHOLD1(x) ((x) << S_THRESHOLD1)
+#define G_THRESHOLD1(x) (((x) >> S_THRESHOLD1) & M_THRESHOLD1)
+
+#define S_THRESHOLD1_EN    16
+#define V_THRESHOLD1_EN(x) ((x) << S_THRESHOLD1_EN)
+#define F_THRESHOLD1_EN    V_THRESHOLD1_EN(1U)
+
+#define S_THRESHOLD0    1
+#define M_THRESHOLD0    0x7fffU
+#define V_THRESHOLD0(x) ((x) << S_THRESHOLD0)
+#define G_THRESHOLD0(x) (((x) >> S_THRESHOLD0) & M_THRESHOLD0)
+
+#define S_THRESHOLD0_EN    0
+#define V_THRESHOLD0_EN(x) ((x) << S_THRESHOLD0_EN)
+#define F_THRESHOLD0_EN    V_THRESHOLD0_EN(1U)
+
+#define A_MA_CLIENT0_WR_LATENCY_THRESHOLD 0x7704
+#define A_MA_CLIENT1_RD_LATENCY_THRESHOLD 0x7708
+#define A_MA_CLIENT1_WR_LATENCY_THRESHOLD 0x770c
+#define A_MA_CLIENT2_RD_LATENCY_THRESHOLD 0x7710
+#define A_MA_CLIENT2_WR_LATENCY_THRESHOLD 0x7714
+#define A_MA_CLIENT3_RD_LATENCY_THRESHOLD 0x7718
+#define A_MA_CLIENT3_WR_LATENCY_THRESHOLD 0x771c
+#define A_MA_CLIENT4_RD_LATENCY_THRESHOLD 0x7720
+#define A_MA_CLIENT4_WR_LATENCY_THRESHOLD 0x7724
+#define A_MA_CLIENT5_RD_LATENCY_THRESHOLD 0x7728
+#define A_MA_CLIENT5_WR_LATENCY_THRESHOLD 0x772c
+#define A_MA_CLIENT6_RD_LATENCY_THRESHOLD 0x7730
+#define A_MA_CLIENT6_WR_LATENCY_THRESHOLD 0x7734
+#define A_MA_CLIENT7_RD_LATENCY_THRESHOLD 0x7738
+#define A_MA_CLIENT7_WR_LATENCY_THRESHOLD 0x773c
+#define A_MA_CLIENT8_RD_LATENCY_THRESHOLD 0x7740
+#define A_MA_CLIENT8_WR_LATENCY_THRESHOLD 0x7744
+#define A_MA_CLIENT9_RD_LATENCY_THRESHOLD 0x7748
+#define A_MA_CLIENT9_WR_LATENCY_THRESHOLD 0x774c
+#define A_MA_CLIENT10_RD_LATENCY_THRESHOLD 0x7750
+#define A_MA_CLIENT10_WR_LATENCY_THRESHOLD 0x7754
+#define A_MA_CLIENT11_RD_LATENCY_THRESHOLD 0x7758
+#define A_MA_CLIENT11_WR_LATENCY_THRESHOLD 0x775c
+#define A_MA_CLIENT12_RD_LATENCY_THRESHOLD 0x7760
+#define A_MA_CLIENT12_WR_LATENCY_THRESHOLD 0x7764
+#define A_MA_SGE_TH0_DEBUG_CNT 0x7768
+
+#define S_DBG_READ_DATA_CNT    24
+#define M_DBG_READ_DATA_CNT    0xffU
+#define V_DBG_READ_DATA_CNT(x) ((x) << S_DBG_READ_DATA_CNT)
+#define G_DBG_READ_DATA_CNT(x) (((x) >> S_DBG_READ_DATA_CNT) & M_DBG_READ_DATA_CNT)
+
+#define S_DBG_READ_REQ_CNT    16
+#define M_DBG_READ_REQ_CNT    0xffU
+#define V_DBG_READ_REQ_CNT(x) ((x) << S_DBG_READ_REQ_CNT)
+#define G_DBG_READ_REQ_CNT(x) (((x) >> S_DBG_READ_REQ_CNT) & M_DBG_READ_REQ_CNT)
+
+#define S_DBG_WRITE_DATA_CNT    8
+#define M_DBG_WRITE_DATA_CNT    0xffU
+#define V_DBG_WRITE_DATA_CNT(x) ((x) << S_DBG_WRITE_DATA_CNT)
+#define G_DBG_WRITE_DATA_CNT(x) (((x) >> S_DBG_WRITE_DATA_CNT) & M_DBG_WRITE_DATA_CNT)
+
+#define S_DBG_WRITE_REQ_CNT    0
+#define M_DBG_WRITE_REQ_CNT    0xffU
+#define V_DBG_WRITE_REQ_CNT(x) ((x) << S_DBG_WRITE_REQ_CNT)
+#define G_DBG_WRITE_REQ_CNT(x) (((x) >> S_DBG_WRITE_REQ_CNT) & M_DBG_WRITE_REQ_CNT)
+
+#define A_MA_SGE_TH1_DEBUG_CNT 0x776c
+#define A_MA_ULPTX_DEBUG_CNT 0x7770
+#define A_MA_ULPRX_DEBUG_CNT 0x7774
+#define A_MA_ULPTXRX_DEBUG_CNT 0x7778
+#define A_MA_TP_TH0_DEBUG_CNT 0x777c
+#define A_MA_TP_TH1_DEBUG_CNT 0x7780
+#define A_MA_LE_DEBUG_CNT 0x7784
+#define A_MA_CIM_DEBUG_CNT 0x7788
+#define A_MA_PCIE_DEBUG_CNT 0x778c
+#define A_MA_PMTX_DEBUG_CNT 0x7790
+#define A_MA_PMRX_DEBUG_CNT 0x7794
+#define A_MA_HMA_DEBUG_CNT 0x7798
+#define A_MA_EDRAM0_BAR 0x77c0
+
+#define S_EDRAM0_BASE    16
+#define M_EDRAM0_BASE    0xfffU
+#define V_EDRAM0_BASE(x) ((x) << S_EDRAM0_BASE)
+#define G_EDRAM0_BASE(x) (((x) >> S_EDRAM0_BASE) & M_EDRAM0_BASE)
+
+#define S_EDRAM0_SIZE    0
+#define M_EDRAM0_SIZE    0xfffU
+#define V_EDRAM0_SIZE(x) ((x) << S_EDRAM0_SIZE)
+#define G_EDRAM0_SIZE(x) (((x) >> S_EDRAM0_SIZE) & M_EDRAM0_SIZE)
+
+#define A_MA_EDRAM1_BAR 0x77c4
+
+#define S_EDRAM1_BASE    16
+#define M_EDRAM1_BASE    0xfffU
+#define V_EDRAM1_BASE(x) ((x) << S_EDRAM1_BASE)
+#define G_EDRAM1_BASE(x) (((x) >> S_EDRAM1_BASE) & M_EDRAM1_BASE)
+
+#define S_EDRAM1_SIZE    0
+#define M_EDRAM1_SIZE    0xfffU
+#define V_EDRAM1_SIZE(x) ((x) << S_EDRAM1_SIZE)
+#define G_EDRAM1_SIZE(x) (((x) >> S_EDRAM1_SIZE) & M_EDRAM1_SIZE)
+
+#define A_MA_EXT_MEMORY_BAR 0x77c8
+
+#define S_EXT_MEM_BASE    16
+#define M_EXT_MEM_BASE    0xfffU
+#define V_EXT_MEM_BASE(x) ((x) << S_EXT_MEM_BASE)
+#define G_EXT_MEM_BASE(x) (((x) >> S_EXT_MEM_BASE) & M_EXT_MEM_BASE)
+
+#define S_EXT_MEM_SIZE    0
+#define M_EXT_MEM_SIZE    0xfffU
+#define V_EXT_MEM_SIZE(x) ((x) << S_EXT_MEM_SIZE)
+#define G_EXT_MEM_SIZE(x) (((x) >> S_EXT_MEM_SIZE) & M_EXT_MEM_SIZE)
+
+#define A_MA_EXT_MEMORY0_BAR 0x77c8
+
+#define S_EXT_MEM0_BASE    16
+#define M_EXT_MEM0_BASE    0xfffU
+#define V_EXT_MEM0_BASE(x) ((x) << S_EXT_MEM0_BASE)
+#define G_EXT_MEM0_BASE(x) (((x) >> S_EXT_MEM0_BASE) & M_EXT_MEM0_BASE)
+
+#define S_EXT_MEM0_SIZE    0
+#define M_EXT_MEM0_SIZE    0xfffU
+#define V_EXT_MEM0_SIZE(x) ((x) << S_EXT_MEM0_SIZE)
+#define G_EXT_MEM0_SIZE(x) (((x) >> S_EXT_MEM0_SIZE) & M_EXT_MEM0_SIZE)
+
+#define A_MA_HOST_MEMORY_BAR 0x77cc
+
+#define S_HMA_BASE    16
+#define M_HMA_BASE    0xfffU
+#define V_HMA_BASE(x) ((x) << S_HMA_BASE)
+#define G_HMA_BASE(x) (((x) >> S_HMA_BASE) & M_HMA_BASE)
+
+#define S_HMA_SIZE    0
+#define M_HMA_SIZE    0xfffU
+#define V_HMA_SIZE(x) ((x) << S_HMA_SIZE)
+#define G_HMA_SIZE(x) (((x) >> S_HMA_SIZE) & M_HMA_SIZE)
+
+#define A_MA_EXT_MEM_PAGE_SIZE 0x77d0
+
+#define S_BRC_MODE    2
+#define V_BRC_MODE(x) ((x) << S_BRC_MODE)
+#define F_BRC_MODE    V_BRC_MODE(1U)
+
+#define S_EXT_MEM_PAGE_SIZE    0
+#define M_EXT_MEM_PAGE_SIZE    0x3U
+#define V_EXT_MEM_PAGE_SIZE(x) ((x) << S_EXT_MEM_PAGE_SIZE)
+#define G_EXT_MEM_PAGE_SIZE(x) (((x) >> S_EXT_MEM_PAGE_SIZE) & M_EXT_MEM_PAGE_SIZE)
+
+#define S_BRC_MODE1    6
+#define V_BRC_MODE1(x) ((x) << S_BRC_MODE1)
+#define F_BRC_MODE1    V_BRC_MODE1(1U)
+
+#define S_EXT_MEM_PAGE_SIZE1    4
+#define M_EXT_MEM_PAGE_SIZE1    0x3U
+#define V_EXT_MEM_PAGE_SIZE1(x) ((x) << S_EXT_MEM_PAGE_SIZE1)
+#define G_EXT_MEM_PAGE_SIZE1(x) (((x) >> S_EXT_MEM_PAGE_SIZE1) & M_EXT_MEM_PAGE_SIZE1)
+
+#define A_MA_ARB_CTRL 0x77d4
+
+#define S_DIS_PAGE_HINT    1
+#define V_DIS_PAGE_HINT(x) ((x) << S_DIS_PAGE_HINT)
+#define F_DIS_PAGE_HINT    V_DIS_PAGE_HINT(1U)
+
+#define S_DIS_ADV_ARB    0
+#define V_DIS_ADV_ARB(x) ((x) << S_DIS_ADV_ARB)
+#define F_DIS_ADV_ARB    V_DIS_ADV_ARB(1U)
+
+#define S_DIS_BANK_FAIR    2
+#define V_DIS_BANK_FAIR(x) ((x) << S_DIS_BANK_FAIR)
+#define F_DIS_BANK_FAIR    V_DIS_BANK_FAIR(1U)
+
+#define A_MA_TARGET_MEM_ENABLE 0x77d8
+
+#define S_HMA_ENABLE    3
+#define V_HMA_ENABLE(x) ((x) << S_HMA_ENABLE)
+#define F_HMA_ENABLE    V_HMA_ENABLE(1U)
+
+#define S_EXT_MEM_ENABLE    2
+#define V_EXT_MEM_ENABLE(x) ((x) << S_EXT_MEM_ENABLE)
+#define F_EXT_MEM_ENABLE    V_EXT_MEM_ENABLE(1U)
+
+#define S_EDRAM1_ENABLE    1
+#define V_EDRAM1_ENABLE(x) ((x) << S_EDRAM1_ENABLE)
+#define F_EDRAM1_ENABLE    V_EDRAM1_ENABLE(1U)
+
+#define S_EDRAM0_ENABLE    0
+#define V_EDRAM0_ENABLE(x) ((x) << S_EDRAM0_ENABLE)
+#define F_EDRAM0_ENABLE    V_EDRAM0_ENABLE(1U)
+
+#define S_HMA_MUX    5
+#define V_HMA_MUX(x) ((x) << S_HMA_MUX)
+#define F_HMA_MUX    V_HMA_MUX(1U)
+
+#define S_EXT_MEM1_ENABLE    4
+#define V_EXT_MEM1_ENABLE(x) ((x) << S_EXT_MEM1_ENABLE)
+#define F_EXT_MEM1_ENABLE    V_EXT_MEM1_ENABLE(1U)
+
+#define S_EXT_MEM0_ENABLE    2
+#define V_EXT_MEM0_ENABLE(x) ((x) << S_EXT_MEM0_ENABLE)
+#define F_EXT_MEM0_ENABLE    V_EXT_MEM0_ENABLE(1U)
+
+#define A_MA_INT_ENABLE 0x77dc
+
+#define S_MEM_PERR_INT_ENABLE    1
+#define V_MEM_PERR_INT_ENABLE(x) ((x) << S_MEM_PERR_INT_ENABLE)
+#define F_MEM_PERR_INT_ENABLE    V_MEM_PERR_INT_ENABLE(1U)
+
+#define S_MEM_WRAP_INT_ENABLE    0
+#define V_MEM_WRAP_INT_ENABLE(x) ((x) << S_MEM_WRAP_INT_ENABLE)
+#define F_MEM_WRAP_INT_ENABLE    V_MEM_WRAP_INT_ENABLE(1U)
+
+#define S_MEM_TO_INT_ENABLE    2
+#define V_MEM_TO_INT_ENABLE(x) ((x) << S_MEM_TO_INT_ENABLE)
+#define F_MEM_TO_INT_ENABLE    V_MEM_TO_INT_ENABLE(1U)
+
+#define A_MA_INT_CAUSE 0x77e0
+
+#define S_MEM_PERR_INT_CAUSE    1
+#define V_MEM_PERR_INT_CAUSE(x) ((x) << S_MEM_PERR_INT_CAUSE)
+#define F_MEM_PERR_INT_CAUSE    V_MEM_PERR_INT_CAUSE(1U)
+
+#define S_MEM_WRAP_INT_CAUSE    0
+#define V_MEM_WRAP_INT_CAUSE(x) ((x) << S_MEM_WRAP_INT_CAUSE)
+#define F_MEM_WRAP_INT_CAUSE    V_MEM_WRAP_INT_CAUSE(1U)
+
+#define S_MEM_TO_INT_CAUSE    2
+#define V_MEM_TO_INT_CAUSE(x) ((x) << S_MEM_TO_INT_CAUSE)
+#define F_MEM_TO_INT_CAUSE    V_MEM_TO_INT_CAUSE(1U)
+
+#define A_MA_INT_WRAP_STATUS 0x77e4
+
+#define S_MEM_WRAP_ADDRESS    4
+#define M_MEM_WRAP_ADDRESS    0xfffffffU
+#define V_MEM_WRAP_ADDRESS(x) ((x) << S_MEM_WRAP_ADDRESS)
+#define G_MEM_WRAP_ADDRESS(x) (((x) >> S_MEM_WRAP_ADDRESS) & M_MEM_WRAP_ADDRESS)
+
+#define S_MEM_WRAP_CLIENT_NUM    0
+#define M_MEM_WRAP_CLIENT_NUM    0xfU
+#define V_MEM_WRAP_CLIENT_NUM(x) ((x) << S_MEM_WRAP_CLIENT_NUM)
+#define G_MEM_WRAP_CLIENT_NUM(x) (((x) >> S_MEM_WRAP_CLIENT_NUM) & M_MEM_WRAP_CLIENT_NUM)
+
+#define A_MA_TP_THREAD1_MAPPER 0x77e8
+
+#define S_TP_THREAD1_EN    0
+#define M_TP_THREAD1_EN    0xffU
+#define V_TP_THREAD1_EN(x) ((x) << S_TP_THREAD1_EN)
+#define G_TP_THREAD1_EN(x) (((x) >> S_TP_THREAD1_EN) & M_TP_THREAD1_EN)
+
+#define A_MA_SGE_THREAD1_MAPPER 0x77ec
+
+#define S_SGE_THREAD1_EN    0
+#define M_SGE_THREAD1_EN    0xffU
+#define V_SGE_THREAD1_EN(x) ((x) << S_SGE_THREAD1_EN)
+#define G_SGE_THREAD1_EN(x) (((x) >> S_SGE_THREAD1_EN) & M_SGE_THREAD1_EN)
+
+#define A_MA_PARITY_ERROR_ENABLE 0x77f0
+
+#define S_TP_DMARBT_PAR_ERROR_EN    31
+#define V_TP_DMARBT_PAR_ERROR_EN(x) ((x) << S_TP_DMARBT_PAR_ERROR_EN)
+#define F_TP_DMARBT_PAR_ERROR_EN    V_TP_DMARBT_PAR_ERROR_EN(1U)
+
+#define S_LOGIC_FIFO_PAR_ERROR_EN    30
+#define V_LOGIC_FIFO_PAR_ERROR_EN(x) ((x) << S_LOGIC_FIFO_PAR_ERROR_EN)
+#define F_LOGIC_FIFO_PAR_ERROR_EN    V_LOGIC_FIFO_PAR_ERROR_EN(1U)
+
+#define S_ARB3_PAR_WRQUEUE_ERROR_EN    29
+#define V_ARB3_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB3_PAR_WRQUEUE_ERROR_EN)
+#define F_ARB3_PAR_WRQUEUE_ERROR_EN    V_ARB3_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_ARB2_PAR_WRQUEUE_ERROR_EN    28
+#define V_ARB2_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB2_PAR_WRQUEUE_ERROR_EN)
+#define F_ARB2_PAR_WRQUEUE_ERROR_EN    V_ARB2_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_ARB1_PAR_WRQUEUE_ERROR_EN    27
+#define V_ARB1_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB1_PAR_WRQUEUE_ERROR_EN)
+#define F_ARB1_PAR_WRQUEUE_ERROR_EN    V_ARB1_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_ARB0_PAR_WRQUEUE_ERROR_EN    26
+#define V_ARB0_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB0_PAR_WRQUEUE_ERROR_EN)
+#define F_ARB0_PAR_WRQUEUE_ERROR_EN    V_ARB0_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_ARB3_PAR_RDQUEUE_ERROR_EN    25
+#define V_ARB3_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB3_PAR_RDQUEUE_ERROR_EN)
+#define F_ARB3_PAR_RDQUEUE_ERROR_EN    V_ARB3_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define S_ARB2_PAR_RDQUEUE_ERROR_EN    24
+#define V_ARB2_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB2_PAR_RDQUEUE_ERROR_EN)
+#define F_ARB2_PAR_RDQUEUE_ERROR_EN    V_ARB2_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define S_ARB1_PAR_RDQUEUE_ERROR_EN    23
+#define V_ARB1_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB1_PAR_RDQUEUE_ERROR_EN)
+#define F_ARB1_PAR_RDQUEUE_ERROR_EN    V_ARB1_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define S_ARB0_PAR_RDQUEUE_ERROR_EN    22
+#define V_ARB0_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB0_PAR_RDQUEUE_ERROR_EN)
+#define F_ARB0_PAR_RDQUEUE_ERROR_EN    V_ARB0_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL10_PAR_WRQUEUE_ERROR_EN    21
+#define V_CL10_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL10_PAR_WRQUEUE_ERROR_EN)
+#define F_CL10_PAR_WRQUEUE_ERROR_EN    V_CL10_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL9_PAR_WRQUEUE_ERROR_EN    20
+#define V_CL9_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL9_PAR_WRQUEUE_ERROR_EN)
+#define F_CL9_PAR_WRQUEUE_ERROR_EN    V_CL9_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL8_PAR_WRQUEUE_ERROR_EN    19
+#define V_CL8_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL8_PAR_WRQUEUE_ERROR_EN)
+#define F_CL8_PAR_WRQUEUE_ERROR_EN    V_CL8_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL7_PAR_WRQUEUE_ERROR_EN    18
+#define V_CL7_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL7_PAR_WRQUEUE_ERROR_EN)
+#define F_CL7_PAR_WRQUEUE_ERROR_EN    V_CL7_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL6_PAR_WRQUEUE_ERROR_EN    17
+#define V_CL6_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL6_PAR_WRQUEUE_ERROR_EN)
+#define F_CL6_PAR_WRQUEUE_ERROR_EN    V_CL6_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL5_PAR_WRQUEUE_ERROR_EN    16
+#define V_CL5_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL5_PAR_WRQUEUE_ERROR_EN)
+#define F_CL5_PAR_WRQUEUE_ERROR_EN    V_CL5_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL4_PAR_WRQUEUE_ERROR_EN    15
+#define V_CL4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL4_PAR_WRQUEUE_ERROR_EN)
+#define F_CL4_PAR_WRQUEUE_ERROR_EN    V_CL4_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL3_PAR_WRQUEUE_ERROR_EN    14
+#define V_CL3_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL3_PAR_WRQUEUE_ERROR_EN)
+#define F_CL3_PAR_WRQUEUE_ERROR_EN    V_CL3_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL2_PAR_WRQUEUE_ERROR_EN    13
+#define V_CL2_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL2_PAR_WRQUEUE_ERROR_EN)
+#define F_CL2_PAR_WRQUEUE_ERROR_EN    V_CL2_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL1_PAR_WRQUEUE_ERROR_EN    12
+#define V_CL1_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL1_PAR_WRQUEUE_ERROR_EN)
+#define F_CL1_PAR_WRQUEUE_ERROR_EN    V_CL1_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL0_PAR_WRQUEUE_ERROR_EN    11
+#define V_CL0_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL0_PAR_WRQUEUE_ERROR_EN)
+#define F_CL0_PAR_WRQUEUE_ERROR_EN    V_CL0_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_CL10_PAR_RDQUEUE_ERROR_EN    10
+#define V_CL10_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL10_PAR_RDQUEUE_ERROR_EN)
+#define F_CL10_PAR_RDQUEUE_ERROR_EN    V_CL10_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL9_PAR_RDQUEUE_ERROR_EN    9
+#define V_CL9_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL9_PAR_RDQUEUE_ERROR_EN)
+#define F_CL9_PAR_RDQUEUE_ERROR_EN    V_CL9_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL8_PAR_RDQUEUE_ERROR_EN    8
+#define V_CL8_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL8_PAR_RDQUEUE_ERROR_EN)
+#define F_CL8_PAR_RDQUEUE_ERROR_EN    V_CL8_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL7_PAR_RDQUEUE_ERROR_EN    7
+#define V_CL7_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL7_PAR_RDQUEUE_ERROR_EN)
+#define F_CL7_PAR_RDQUEUE_ERROR_EN    V_CL7_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL6_PAR_RDQUEUE_ERROR_EN    6
+#define V_CL6_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL6_PAR_RDQUEUE_ERROR_EN)
+#define F_CL6_PAR_RDQUEUE_ERROR_EN    V_CL6_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL5_PAR_RDQUEUE_ERROR_EN    5
+#define V_CL5_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL5_PAR_RDQUEUE_ERROR_EN)
+#define F_CL5_PAR_RDQUEUE_ERROR_EN    V_CL5_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL4_PAR_RDQUEUE_ERROR_EN    4
+#define V_CL4_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL4_PAR_RDQUEUE_ERROR_EN)
+#define F_CL4_PAR_RDQUEUE_ERROR_EN    V_CL4_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL3_PAR_RDQUEUE_ERROR_EN    3
+#define V_CL3_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL3_PAR_RDQUEUE_ERROR_EN)
+#define F_CL3_PAR_RDQUEUE_ERROR_EN    V_CL3_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL2_PAR_RDQUEUE_ERROR_EN    2
+#define V_CL2_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL2_PAR_RDQUEUE_ERROR_EN)
+#define F_CL2_PAR_RDQUEUE_ERROR_EN    V_CL2_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL1_PAR_RDQUEUE_ERROR_EN    1
+#define V_CL1_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL1_PAR_RDQUEUE_ERROR_EN)
+#define F_CL1_PAR_RDQUEUE_ERROR_EN    V_CL1_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define S_CL0_PAR_RDQUEUE_ERROR_EN    0
+#define V_CL0_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL0_PAR_RDQUEUE_ERROR_EN)
+#define F_CL0_PAR_RDQUEUE_ERROR_EN    V_CL0_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define A_MA_PARITY_ERROR_ENABLE1 0x77f0
+#define A_MA_PARITY_ERROR_STATUS 0x77f4
+
+#define S_TP_DMARBT_PAR_ERROR    31
+#define V_TP_DMARBT_PAR_ERROR(x) ((x) << S_TP_DMARBT_PAR_ERROR)
+#define F_TP_DMARBT_PAR_ERROR    V_TP_DMARBT_PAR_ERROR(1U)
+
+#define S_LOGIC_FIFO_PAR_ERROR    30
+#define V_LOGIC_FIFO_PAR_ERROR(x) ((x) << S_LOGIC_FIFO_PAR_ERROR)
+#define F_LOGIC_FIFO_PAR_ERROR    V_LOGIC_FIFO_PAR_ERROR(1U)
+
+#define S_ARB3_PAR_WRQUEUE_ERROR    29
+#define V_ARB3_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB3_PAR_WRQUEUE_ERROR)
+#define F_ARB3_PAR_WRQUEUE_ERROR    V_ARB3_PAR_WRQUEUE_ERROR(1U)
+
+#define S_ARB2_PAR_WRQUEUE_ERROR    28
+#define V_ARB2_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB2_PAR_WRQUEUE_ERROR)
+#define F_ARB2_PAR_WRQUEUE_ERROR    V_ARB2_PAR_WRQUEUE_ERROR(1U)
+
+#define S_ARB1_PAR_WRQUEUE_ERROR    27
+#define V_ARB1_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB1_PAR_WRQUEUE_ERROR)
+#define F_ARB1_PAR_WRQUEUE_ERROR    V_ARB1_PAR_WRQUEUE_ERROR(1U)
+
+#define S_ARB0_PAR_WRQUEUE_ERROR    26
+#define V_ARB0_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB0_PAR_WRQUEUE_ERROR)
+#define F_ARB0_PAR_WRQUEUE_ERROR    V_ARB0_PAR_WRQUEUE_ERROR(1U)
+
+#define S_ARB3_PAR_RDQUEUE_ERROR    25
+#define V_ARB3_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB3_PAR_RDQUEUE_ERROR)
+#define F_ARB3_PAR_RDQUEUE_ERROR    V_ARB3_PAR_RDQUEUE_ERROR(1U)
+
+#define S_ARB2_PAR_RDQUEUE_ERROR    24
+#define V_ARB2_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB2_PAR_RDQUEUE_ERROR)
+#define F_ARB2_PAR_RDQUEUE_ERROR    V_ARB2_PAR_RDQUEUE_ERROR(1U)
+
+#define S_ARB1_PAR_RDQUEUE_ERROR    23
+#define V_ARB1_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB1_PAR_RDQUEUE_ERROR)
+#define F_ARB1_PAR_RDQUEUE_ERROR    V_ARB1_PAR_RDQUEUE_ERROR(1U)
+
+#define S_ARB0_PAR_RDQUEUE_ERROR    22
+#define V_ARB0_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB0_PAR_RDQUEUE_ERROR)
+#define F_ARB0_PAR_RDQUEUE_ERROR    V_ARB0_PAR_RDQUEUE_ERROR(1U)
+
+#define S_CL10_PAR_WRQUEUE_ERROR    21
+#define V_CL10_PAR_WRQUEUE_ERROR(x) ((x) << S_CL10_PAR_WRQUEUE_ERROR)
+#define F_CL10_PAR_WRQUEUE_ERROR    V_CL10_PAR_WRQUEUE_ERROR(1U)
+
+#define S_CL9_PAR_WRQUEUE_ERROR    20
+#define V_CL9_PAR_WRQUEUE_ERROR(x) ((x) << S_CL9_PAR_WRQUEUE_ERROR)
+#define F_CL9_PAR_WRQUEUE_ERROR    V_CL9_PAR_WRQUEUE_ERROR(1U)
+
+#define S_CL8_PAR_WRQUEUE_ERROR    19
+#define V_CL8_PAR_WRQUEUE_ERROR(x) ((x) << S_CL8_PAR_WRQUEUE_ERROR)
+#define F_CL8_PAR_WRQUEUE_ERROR    V_CL8_PAR_WRQUEUE_ERROR(1U)
+
+#define S_CL7_PAR_WRQUEUE_ERROR    18
+#define V_CL7_PAR_WRQUEUE_ERROR(x) ((x) << S_CL7_PAR_WRQUEUE_ERROR)
+#define F_CL7_PAR_WRQUEUE_ERROR    V_CL7_PAR_WRQUEUE_ERROR(1U)
+
+#define S_CL6_PAR_WRQUEUE_ERROR    17
+#define V_CL6_PAR_WRQUEUE_ERROR(x) ((x) << S_CL6_PAR_WRQUEUE_ERROR)
+#define F_CL6_PAR_WRQUEUE_ERROR    V_CL6_PAR_WRQUEUE_ERROR(1U)
+
+#define S_CL5_PAR_WRQUEUE_ERROR    16
+#define V_CL5_PAR_WRQUEUE_ERROR(x) ((x) << S_CL5_PAR_WRQUEUE_ERROR)
+#define F_CL5_PAR_WRQUEUE_ERROR    V_CL5_PAR_WRQUEUE_ERROR(1U)
+
+#define S_CL4_PAR_WRQUEUE_ERROR    15
+#define V_CL4_PAR_WRQUEUE_ERROR(x) ((x) << S_CL4_PAR_WRQUEUE_ERROR)
+#define F_CL4_PAR_WRQUEUE_ERROR    V_CL4_PAR_WRQUEUE_ERROR(1U)
+
+#define S_CL3_PAR_WRQUEUE_ERROR    14
+#define V_CL3_PAR_WRQUEUE_ERROR(x) ((x) << S_CL3_PAR_WRQUEUE_ERROR)
+#define F_CL3_PAR_WRQUEUE_ERROR    V_CL3_PAR_WRQUEUE_ERROR(1U)
+
+#define S_CL2_PAR_WRQUEUE_ERROR    13
+#define V_CL2_PAR_WRQUEUE_ERROR(x) ((x) << S_CL2_PAR_WRQUEUE_ERROR)
+#define F_CL2_PAR_WRQUEUE_ERROR    V_CL2_PAR_WRQUEUE_ERROR(1U)
+
+#define S_CL1_PAR_WRQUEUE_ERROR    12
+#define V_CL1_PAR_WRQUEUE_ERROR(x) ((x) << S_CL1_PAR_WRQUEUE_ERROR)
+#define F_CL1_PAR_WRQUEUE_ERROR    V_CL1_PAR_WRQUEUE_ERROR(1U)
+
+#define S_CL0_PAR_WRQUEUE_ERROR    11
+#define V_CL0_PAR_WRQUEUE_ERROR(x) ((x) << S_CL0_PAR_WRQUEUE_ERROR)
+#define F_CL0_PAR_WRQUEUE_ERROR    V_CL0_PAR_WRQUEUE_ERROR(1U)
+
+#define S_CL10_PAR_RDQUEUE_ERROR    10
+#define V_CL10_PAR_RDQUEUE_ERROR(x) ((x) << S_CL10_PAR_RDQUEUE_ERROR)
+#define F_CL10_PAR_RDQUEUE_ERROR    V_CL10_PAR_RDQUEUE_ERROR(1U)
+
+#define S_CL9_PAR_RDQUEUE_ERROR    9
+#define V_CL9_PAR_RDQUEUE_ERROR(x) ((x) << S_CL9_PAR_RDQUEUE_ERROR)
+#define F_CL9_PAR_RDQUEUE_ERROR    V_CL9_PAR_RDQUEUE_ERROR(1U)
+
+#define S_CL8_PAR_RDQUEUE_ERROR    8
+#define V_CL8_PAR_RDQUEUE_ERROR(x) ((x) << S_CL8_PAR_RDQUEUE_ERROR)
+#define F_CL8_PAR_RDQUEUE_ERROR    V_CL8_PAR_RDQUEUE_ERROR(1U)
+
+#define S_CL7_PAR_RDQUEUE_ERROR    7
+#define V_CL7_PAR_RDQUEUE_ERROR(x) ((x) << S_CL7_PAR_RDQUEUE_ERROR)
+#define F_CL7_PAR_RDQUEUE_ERROR    V_CL7_PAR_RDQUEUE_ERROR(1U)
+
+#define S_CL6_PAR_RDQUEUE_ERROR    6
+#define V_CL6_PAR_RDQUEUE_ERROR(x) ((x) << S_CL6_PAR_RDQUEUE_ERROR)
+#define F_CL6_PAR_RDQUEUE_ERROR    V_CL6_PAR_RDQUEUE_ERROR(1U)
+
+#define S_CL5_PAR_RDQUEUE_ERROR    5
+#define V_CL5_PAR_RDQUEUE_ERROR(x) ((x) << S_CL5_PAR_RDQUEUE_ERROR)
+#define F_CL5_PAR_RDQUEUE_ERROR    V_CL5_PAR_RDQUEUE_ERROR(1U)
+
+#define S_CL4_PAR_RDQUEUE_ERROR    4
+#define V_CL4_PAR_RDQUEUE_ERROR(x) ((x) << S_CL4_PAR_RDQUEUE_ERROR)
+#define F_CL4_PAR_RDQUEUE_ERROR    V_CL4_PAR_RDQUEUE_ERROR(1U)
+
+#define S_CL3_PAR_RDQUEUE_ERROR    3
+#define V_CL3_PAR_RDQUEUE_ERROR(x) ((x) << S_CL3_PAR_RDQUEUE_ERROR)
+#define F_CL3_PAR_RDQUEUE_ERROR    V_CL3_PAR_RDQUEUE_ERROR(1U)
+
+#define S_CL2_PAR_RDQUEUE_ERROR    2
+#define V_CL2_PAR_RDQUEUE_ERROR(x) ((x) << S_CL2_PAR_RDQUEUE_ERROR)
+#define F_CL2_PAR_RDQUEUE_ERROR    V_CL2_PAR_RDQUEUE_ERROR(1U)
+
+#define S_CL1_PAR_RDQUEUE_ERROR    1
+#define V_CL1_PAR_RDQUEUE_ERROR(x) ((x) << S_CL1_PAR_RDQUEUE_ERROR)
+#define F_CL1_PAR_RDQUEUE_ERROR    V_CL1_PAR_RDQUEUE_ERROR(1U)
+
+#define S_CL0_PAR_RDQUEUE_ERROR    0
+#define V_CL0_PAR_RDQUEUE_ERROR(x) ((x) << S_CL0_PAR_RDQUEUE_ERROR)
+#define F_CL0_PAR_RDQUEUE_ERROR    V_CL0_PAR_RDQUEUE_ERROR(1U)
+
+#define A_MA_PARITY_ERROR_STATUS1 0x77f4
+#define A_MA_SGE_PCIE_COHERANCY_CTRL 0x77f8
+
+#define S_BONUS_REG    6
+#define M_BONUS_REG    0x3ffffffU
+#define V_BONUS_REG(x) ((x) << S_BONUS_REG)
+#define G_BONUS_REG(x) (((x) >> S_BONUS_REG) & M_BONUS_REG)
+
+#define S_COHERANCY_CMD_TYPE    4
+#define M_COHERANCY_CMD_TYPE    0x3U
+#define V_COHERANCY_CMD_TYPE(x) ((x) << S_COHERANCY_CMD_TYPE)
+#define G_COHERANCY_CMD_TYPE(x) (((x) >> S_COHERANCY_CMD_TYPE) & M_COHERANCY_CMD_TYPE)
+
+#define S_COHERANCY_THREAD_NUM    1
+#define M_COHERANCY_THREAD_NUM    0x7U
+#define V_COHERANCY_THREAD_NUM(x) ((x) << S_COHERANCY_THREAD_NUM)
+#define G_COHERANCY_THREAD_NUM(x) (((x) >> S_COHERANCY_THREAD_NUM) & M_COHERANCY_THREAD_NUM)
+
+#define S_COHERANCY_ENABLE    0
+#define V_COHERANCY_ENABLE(x) ((x) << S_COHERANCY_ENABLE)
+#define F_COHERANCY_ENABLE    V_COHERANCY_ENABLE(1U)
+
+#define A_MA_ERROR_ENABLE 0x77fc
+
+#define S_UE_ENABLE    0
+#define V_UE_ENABLE(x) ((x) << S_UE_ENABLE)
+#define F_UE_ENABLE    V_UE_ENABLE(1U)
+
+#define S_FUTURE_EXPANSION    1
+#define M_FUTURE_EXPANSION    0x7fffffffU
+#define V_FUTURE_EXPANSION(x) ((x) << S_FUTURE_EXPANSION)
+#define G_FUTURE_EXPANSION(x) (((x) >> S_FUTURE_EXPANSION) & M_FUTURE_EXPANSION)
+
+#define A_MA_PARITY_ERROR_ENABLE2 0x7800
+
+#define S_ARB4_PAR_WRQUEUE_ERROR_EN    1
+#define V_ARB4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB4_PAR_WRQUEUE_ERROR_EN)
+#define F_ARB4_PAR_WRQUEUE_ERROR_EN    V_ARB4_PAR_WRQUEUE_ERROR_EN(1U)
+
+#define S_ARB4_PAR_RDQUEUE_ERROR_EN    0
+#define V_ARB4_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR_EN)
+#define F_ARB4_PAR_RDQUEUE_ERROR_EN    V_ARB4_PAR_RDQUEUE_ERROR_EN(1U)
+
+#define A_MA_PARITY_ERROR_STATUS2 0x7804
+
+#define S_ARB4_PAR_WRQUEUE_ERROR    1
+#define V_ARB4_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB4_PAR_WRQUEUE_ERROR)
+#define F_ARB4_PAR_WRQUEUE_ERROR    V_ARB4_PAR_WRQUEUE_ERROR(1U)
+
+#define S_ARB4_PAR_RDQUEUE_ERROR    0
+#define V_ARB4_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR)
+#define F_ARB4_PAR_RDQUEUE_ERROR    V_ARB4_PAR_RDQUEUE_ERROR(1U)
+
+#define A_MA_EXT_MEMORY1_BAR 0x7808
+
+#define S_EXT_MEM1_BASE    16
+#define M_EXT_MEM1_BASE    0xfffU
+#define V_EXT_MEM1_BASE(x) ((x) << S_EXT_MEM1_BASE)
+#define G_EXT_MEM1_BASE(x) (((x) >> S_EXT_MEM1_BASE) & M_EXT_MEM1_BASE)
+
+#define S_EXT_MEM1_SIZE    0
+#define M_EXT_MEM1_SIZE    0xfffU
+#define V_EXT_MEM1_SIZE(x) ((x) << S_EXT_MEM1_SIZE)
+#define G_EXT_MEM1_SIZE(x) (((x) >> S_EXT_MEM1_SIZE) & M_EXT_MEM1_SIZE)
+
+#define A_MA_PMTX_THROTTLE 0x780c
+
+#define S_FL_ENABLE    31
+#define V_FL_ENABLE(x) ((x) << S_FL_ENABLE)
+#define F_FL_ENABLE    V_FL_ENABLE(1U)
+
+#define S_FL_LIMIT    0
+#define M_FL_LIMIT    0xffU
+#define V_FL_LIMIT(x) ((x) << S_FL_LIMIT)
+#define G_FL_LIMIT(x) (((x) >> S_FL_LIMIT) & M_FL_LIMIT)
+
+#define A_MA_PMRX_THROTTLE 0x7810
+#define A_MA_SGE_TH0_WRDATA_CNT 0x7814
+#define A_MA_SGE_TH1_WRDATA_CNT 0x7818
+#define A_MA_ULPTX_WRDATA_CNT 0x781c
+#define A_MA_ULPRX_WRDATA_CNT 0x7820
+#define A_MA_ULPTXRX_WRDATA_CNT 0x7824
+#define A_MA_TP_TH0_WRDATA_CNT 0x7828
+#define A_MA_TP_TH1_WRDATA_CNT 0x782c
+#define A_MA_LE_WRDATA_CNT 0x7830
+#define A_MA_CIM_WRDATA_CNT 0x7834
+#define A_MA_PCIE_WRDATA_CNT 0x7838
+#define A_MA_PMTX_WRDATA_CNT 0x783c
+#define A_MA_PMRX_WRDATA_CNT 0x7840
+#define A_MA_HMA_WRDATA_CNT 0x7844
+#define A_MA_SGE_TH0_RDDATA_CNT 0x7848
+#define A_MA_SGE_TH1_RDDATA_CNT 0x784c
+#define A_MA_ULPTX_RDDATA_CNT 0x7850
+#define A_MA_ULPRX_RDDATA_CNT 0x7854
+#define A_MA_ULPTXRX_RDDATA_CNT 0x7858
+#define A_MA_TP_TH0_RDDATA_CNT 0x785c
+#define A_MA_TP_TH1_RDDATA_CNT 0x7860
+#define A_MA_LE_RDDATA_CNT 0x7864
+#define A_MA_CIM_RDDATA_CNT 0x7868
+#define A_MA_PCIE_RDDATA_CNT 0x786c
+#define A_MA_PMTX_RDDATA_CNT 0x7870
+#define A_MA_PMRX_RDDATA_CNT 0x7874
+#define A_MA_HMA_RDDATA_CNT 0x7878
+#define A_MA_EDRAM0_WRDATA_CNT1 0x787c
+#define A_MA_EDRAM0_WRDATA_CNT0 0x7880
+#define A_MA_EDRAM1_WRDATA_CNT1 0x7884
+#define A_MA_EDRAM1_WRDATA_CNT0 0x7888
+#define A_MA_EXT_MEMORY0_WRDATA_CNT1 0x788c
+#define A_MA_EXT_MEMORY0_WRDATA_CNT0 0x7890
+#define A_MA_HOST_MEMORY_WRDATA_CNT1 0x7894
+#define A_MA_HOST_MEMORY_WRDATA_CNT0 0x7898
+#define A_MA_EXT_MEMORY1_WRDATA_CNT1 0x789c
+#define A_MA_EXT_MEMORY1_WRDATA_CNT0 0x78a0
+#define A_MA_EDRAM0_RDDATA_CNT1 0x78a4
+#define A_MA_EDRAM0_RDDATA_CNT0 0x78a8
+#define A_MA_EDRAM1_RDDATA_CNT1 0x78ac
+#define A_MA_EDRAM1_RDDATA_CNT0 0x78b0
+#define A_MA_EXT_MEMORY0_RDDATA_CNT1 0x78b4
+#define A_MA_EXT_MEMORY0_RDDATA_CNT0 0x78b8
+#define A_MA_HOST_MEMORY_RDDATA_CNT1 0x78bc
+#define A_MA_HOST_MEMORY_RDDATA_CNT0 0x78c0
+#define A_MA_EXT_MEMORY1_RDDATA_CNT1 0x78c4
+#define A_MA_EXT_MEMORY1_RDDATA_CNT0 0x78c8
+#define A_MA_TIMEOUT_CFG 0x78cc
+
+#define S_CLR    31
+#define V_CLR(x) ((x) << S_CLR)
+#define F_CLR    V_CLR(1U)
+
+#define S_CNT_LOCK    30
+#define V_CNT_LOCK(x) ((x) << S_CNT_LOCK)
+#define F_CNT_LOCK    V_CNT_LOCK(1U)
+
+#define S_WRN    24
+#define V_WRN(x) ((x) << S_WRN)
+#define F_WRN    V_WRN(1U)
+
+#define S_DIR    23
+#define V_DIR(x) ((x) << S_DIR)
+#define F_DIR    V_DIR(1U)
+
+#define S_TO_BUS    22
+#define V_TO_BUS(x) ((x) << S_TO_BUS)
+#define F_TO_BUS    V_TO_BUS(1U)
+
+#define S_CLIENT    16
+#define M_CLIENT    0xfU
+#define V_CLIENT(x) ((x) << S_CLIENT)
+#define G_CLIENT(x) (((x) >> S_CLIENT) & M_CLIENT)
+
+#define S_DELAY    0
+#define M_DELAY    0xffffU
+#define V_DELAY(x) ((x) << S_DELAY)
+#define G_DELAY(x) (((x) >> S_DELAY) & M_DELAY)
+
+#define A_MA_TIMEOUT_CNT 0x78d0
+
+#define S_CNT_VAL    0
+#define M_CNT_VAL    0xffffU
+#define V_CNT_VAL(x) ((x) << S_CNT_VAL)
+#define G_CNT_VAL(x) (((x) >> S_CNT_VAL) & M_CNT_VAL)
+
+#define A_MA_WRITE_TIMEOUT_ERROR_ENABLE 0x78d4
+
+#define S_FUTURE_CEXPANSION    29
+#define M_FUTURE_CEXPANSION    0x7U
+#define V_FUTURE_CEXPANSION(x) ((x) << S_FUTURE_CEXPANSION)
+#define G_FUTURE_CEXPANSION(x) (((x) >> S_FUTURE_CEXPANSION) & M_FUTURE_CEXPANSION)
+
+#define S_CL12_WR_CMD_TO_EN    28
+#define V_CL12_WR_CMD_TO_EN(x) ((x) << S_CL12_WR_CMD_TO_EN)
+#define F_CL12_WR_CMD_TO_EN    V_CL12_WR_CMD_TO_EN(1U)
+
+#define S_CL11_WR_CMD_TO_EN    27
+#define V_CL11_WR_CMD_TO_EN(x) ((x) << S_CL11_WR_CMD_TO_EN)
+#define F_CL11_WR_CMD_TO_EN    V_CL11_WR_CMD_TO_EN(1U)
+
+#define S_CL10_WR_CMD_TO_EN    26
+#define V_CL10_WR_CMD_TO_EN(x) ((x) << S_CL10_WR_CMD_TO_EN)
+#define F_CL10_WR_CMD_TO_EN    V_CL10_WR_CMD_TO_EN(1U)
+
+#define S_CL9_WR_CMD_TO_EN    25
+#define V_CL9_WR_CMD_TO_EN(x) ((x) << S_CL9_WR_CMD_TO_EN)
+#define F_CL9_WR_CMD_TO_EN    V_CL9_WR_CMD_TO_EN(1U)
+
+#define S_CL8_WR_CMD_TO_EN    24
+#define V_CL8_WR_CMD_TO_EN(x) ((x) << S_CL8_WR_CMD_TO_EN)
+#define F_CL8_WR_CMD_TO_EN    V_CL8_WR_CMD_TO_EN(1U)
+
+#define S_CL7_WR_CMD_TO_EN    23
+#define V_CL7_WR_CMD_TO_EN(x) ((x) << S_CL7_WR_CMD_TO_EN)
+#define F_CL7_WR_CMD_TO_EN    V_CL7_WR_CMD_TO_EN(1U)
+
+#define S_CL6_WR_CMD_TO_EN    22
+#define V_CL6_WR_CMD_TO_EN(x) ((x) << S_CL6_WR_CMD_TO_EN)
+#define F_CL6_WR_CMD_TO_EN    V_CL6_WR_CMD_TO_EN(1U)
+
+#define S_CL5_WR_CMD_TO_EN    21
+#define V_CL5_WR_CMD_TO_EN(x) ((x) << S_CL5_WR_CMD_TO_EN)
+#define F_CL5_WR_CMD_TO_EN    V_CL5_WR_CMD_TO_EN(1U)
+
+#define S_CL4_WR_CMD_TO_EN    20
+#define V_CL4_WR_CMD_TO_EN(x) ((x) << S_CL4_WR_CMD_TO_EN)
+#define F_CL4_WR_CMD_TO_EN    V_CL4_WR_CMD_TO_EN(1U)
+
+#define S_CL3_WR_CMD_TO_EN    19
+#define V_CL3_WR_CMD_TO_EN(x) ((x) << S_CL3_WR_CMD_TO_EN)
+#define F_CL3_WR_CMD_TO_EN    V_CL3_WR_CMD_TO_EN(1U)
+
+#define S_CL2_WR_CMD_TO_EN    18
+#define V_CL2_WR_CMD_TO_EN(x) ((x) << S_CL2_WR_CMD_TO_EN)
+#define F_CL2_WR_CMD_TO_EN    V_CL2_WR_CMD_TO_EN(1U)
+
+#define S_CL1_WR_CMD_TO_EN    17
+#define V_CL1_WR_CMD_TO_EN(x) ((x) << S_CL1_WR_CMD_TO_EN)
+#define F_CL1_WR_CMD_TO_EN    V_CL1_WR_CMD_TO_EN(1U)
+
+#define S_CL0_WR_CMD_TO_EN    16
+#define V_CL0_WR_CMD_TO_EN(x) ((x) << S_CL0_WR_CMD_TO_EN)
+#define F_CL0_WR_CMD_TO_EN    V_CL0_WR_CMD_TO_EN(1U)
+
+#define S_FUTURE_DEXPANSION    13
+#define M_FUTURE_DEXPANSION    0x7U
+#define V_FUTURE_DEXPANSION(x) ((x) << S_FUTURE_DEXPANSION)
+#define G_FUTURE_DEXPANSION(x) (((x) >> S_FUTURE_DEXPANSION) & M_FUTURE_DEXPANSION)
+
+#define S_CL12_WR_DATA_TO_EN    12
+#define V_CL12_WR_DATA_TO_EN(x) ((x) << S_CL12_WR_DATA_TO_EN)
+#define F_CL12_WR_DATA_TO_EN    V_CL12_WR_DATA_TO_EN(1U)
+
+#define S_CL11_WR_DATA_TO_EN    11
+#define V_CL11_WR_DATA_TO_EN(x) ((x) << S_CL11_WR_DATA_TO_EN)
+#define F_CL11_WR_DATA_TO_EN    V_CL11_WR_DATA_TO_EN(1U)
+
+#define S_CL10_WR_DATA_TO_EN    10
+#define V_CL10_WR_DATA_TO_EN(x) ((x) << S_CL10_WR_DATA_TO_EN)
+#define F_CL10_WR_DATA_TO_EN    V_CL10_WR_DATA_TO_EN(1U)
+
+#define S_CL9_WR_DATA_TO_EN    9
+#define V_CL9_WR_DATA_TO_EN(x) ((x) << S_CL9_WR_DATA_TO_EN)
+#define F_CL9_WR_DATA_TO_EN    V_CL9_WR_DATA_TO_EN(1U)
+
+#define S_CL8_WR_DATA_TO_EN    8
+#define V_CL8_WR_DATA_TO_EN(x) ((x) << S_CL8_WR_DATA_TO_EN)
+#define F_CL8_WR_DATA_TO_EN    V_CL8_WR_DATA_TO_EN(1U)
+
+#define S_CL7_WR_DATA_TO_EN    7
+#define V_CL7_WR_DATA_TO_EN(x) ((x) << S_CL7_WR_DATA_TO_EN)
+#define F_CL7_WR_DATA_TO_EN    V_CL7_WR_DATA_TO_EN(1U)
+
+#define S_CL6_WR_DATA_TO_EN    6
+#define V_CL6_WR_DATA_TO_EN(x) ((x) << S_CL6_WR_DATA_TO_EN)
+#define F_CL6_WR_DATA_TO_EN    V_CL6_WR_DATA_TO_EN(1U)
+
+#define S_CL5_WR_DATA_TO_EN    5
+#define V_CL5_WR_DATA_TO_EN(x) ((x) << S_CL5_WR_DATA_TO_EN)
+#define F_CL5_WR_DATA_TO_EN    V_CL5_WR_DATA_TO_EN(1U)
+
+#define S_CL4_WR_DATA_TO_EN    4
+#define V_CL4_WR_DATA_TO_EN(x) ((x) << S_CL4_WR_DATA_TO_EN)
+#define F_CL4_WR_DATA_TO_EN    V_CL4_WR_DATA_TO_EN(1U)
+
+#define S_CL3_WR_DATA_TO_EN    3
+#define V_CL3_WR_DATA_TO_EN(x) ((x) << S_CL3_WR_DATA_TO_EN)
+#define F_CL3_WR_DATA_TO_EN    V_CL3_WR_DATA_TO_EN(1U)
+
+#define S_CL2_WR_DATA_TO_EN    2
+#define V_CL2_WR_DATA_TO_EN(x) ((x) << S_CL2_WR_DATA_TO_EN)
+#define F_CL2_WR_DATA_TO_EN    V_CL2_WR_DATA_TO_EN(1U)
+
+#define S_CL1_WR_DATA_TO_EN    1
+#define V_CL1_WR_DATA_TO_EN(x) ((x) << S_CL1_WR_DATA_TO_EN)
+#define F_CL1_WR_DATA_TO_EN    V_CL1_WR_DATA_TO_EN(1U)
+
+#define S_CL0_WR_DATA_TO_EN    0
+#define V_CL0_WR_DATA_TO_EN(x) ((x) << S_CL0_WR_DATA_TO_EN)
+#define F_CL0_WR_DATA_TO_EN    V_CL0_WR_DATA_TO_EN(1U)
+
+#define A_MA_WRITE_TIMEOUT_ERROR_STATUS 0x78d8
+
+#define S_CL12_WR_CMD_TO_ERROR    28
+#define V_CL12_WR_CMD_TO_ERROR(x) ((x) << S_CL12_WR_CMD_TO_ERROR)
+#define F_CL12_WR_CMD_TO_ERROR    V_CL12_WR_CMD_TO_ERROR(1U)
+
+#define S_CL11_WR_CMD_TO_ERROR    27
+#define V_CL11_WR_CMD_TO_ERROR(x) ((x) << S_CL11_WR_CMD_TO_ERROR)
+#define F_CL11_WR_CMD_TO_ERROR    V_CL11_WR_CMD_TO_ERROR(1U)
+
+#define S_CL10_WR_CMD_TO_ERROR    26
+#define V_CL10_WR_CMD_TO_ERROR(x) ((x) << S_CL10_WR_CMD_TO_ERROR)
+#define F_CL10_WR_CMD_TO_ERROR    V_CL10_WR_CMD_TO_ERROR(1U)
+
+#define S_CL9_WR_CMD_TO_ERROR    25
+#define V_CL9_WR_CMD_TO_ERROR(x) ((x) << S_CL9_WR_CMD_TO_ERROR)
+#define F_CL9_WR_CMD_TO_ERROR    V_CL9_WR_CMD_TO_ERROR(1U)
+
+#define S_CL8_WR_CMD_TO_ERROR    24
+#define V_CL8_WR_CMD_TO_ERROR(x) ((x) << S_CL8_WR_CMD_TO_ERROR)
+#define F_CL8_WR_CMD_TO_ERROR    V_CL8_WR_CMD_TO_ERROR(1U)
+
+#define S_CL7_WR_CMD_TO_ERROR    23
+#define V_CL7_WR_CMD_TO_ERROR(x) ((x) << S_CL7_WR_CMD_TO_ERROR)
+#define F_CL7_WR_CMD_TO_ERROR    V_CL7_WR_CMD_TO_ERROR(1U)
+
+#define S_CL6_WR_CMD_TO_ERROR    22
+#define V_CL6_WR_CMD_TO_ERROR(x) ((x) << S_CL6_WR_CMD_TO_ERROR)
+#define F_CL6_WR_CMD_TO_ERROR    V_CL6_WR_CMD_TO_ERROR(1U)
+
+#define S_CL5_WR_CMD_TO_ERROR    21
+#define V_CL5_WR_CMD_TO_ERROR(x) ((x) << S_CL5_WR_CMD_TO_ERROR)
+#define F_CL5_WR_CMD_TO_ERROR    V_CL5_WR_CMD_TO_ERROR(1U)
+
+#define S_CL4_WR_CMD_TO_ERROR    20
+#define V_CL4_WR_CMD_TO_ERROR(x) ((x) << S_CL4_WR_CMD_TO_ERROR)
+#define F_CL4_WR_CMD_TO_ERROR    V_CL4_WR_CMD_TO_ERROR(1U)
+
+#define S_CL3_WR_CMD_TO_ERROR    19
+#define V_CL3_WR_CMD_TO_ERROR(x) ((x) << S_CL3_WR_CMD_TO_ERROR)
+#define F_CL3_WR_CMD_TO_ERROR    V_CL3_WR_CMD_TO_ERROR(1U)
+
+#define S_CL2_WR_CMD_TO_ERROR    18
+#define V_CL2_WR_CMD_TO_ERROR(x) ((x) << S_CL2_WR_CMD_TO_ERROR)
+#define F_CL2_WR_CMD_TO_ERROR    V_CL2_WR_CMD_TO_ERROR(1U)
+
+#define S_CL1_WR_CMD_TO_ERROR    17
+#define V_CL1_WR_CMD_TO_ERROR(x) ((x) << S_CL1_WR_CMD_TO_ERROR)
+#define F_CL1_WR_CMD_TO_ERROR    V_CL1_WR_CMD_TO_ERROR(1U)
+
+#define S_CL0_WR_CMD_TO_ERROR    16
+#define V_CL0_WR_CMD_TO_ERROR(x) ((x) << S_CL0_WR_CMD_TO_ERROR)
+#define F_CL0_WR_CMD_TO_ERROR    V_CL0_WR_CMD_TO_ERROR(1U)
+
+#define S_CL12_WR_DATA_TO_ERROR    12
+#define V_CL12_WR_DATA_TO_ERROR(x) ((x) << S_CL12_WR_DATA_TO_ERROR)
+#define F_CL12_WR_DATA_TO_ERROR    V_CL12_WR_DATA_TO_ERROR(1U)
+
+#define S_CL11_WR_DATA_TO_ERROR    11
+#define V_CL11_WR_DATA_TO_ERROR(x) ((x) << S_CL11_WR_DATA_TO_ERROR)
+#define F_CL11_WR_DATA_TO_ERROR    V_CL11_WR_DATA_TO_ERROR(1U)
+
+#define S_CL10_WR_DATA_TO_ERROR    10
+#define V_CL10_WR_DATA_TO_ERROR(x) ((x) << S_CL10_WR_DATA_TO_ERROR)
+#define F_CL10_WR_DATA_TO_ERROR    V_CL10_WR_DATA_TO_ERROR(1U)
+
+#define S_CL9_WR_DATA_TO_ERROR    9
+#define V_CL9_WR_DATA_TO_ERROR(x) ((x) << S_CL9_WR_DATA_TO_ERROR)
+#define F_CL9_WR_DATA_TO_ERROR    V_CL9_WR_DATA_TO_ERROR(1U)
+
+#define S_CL8_WR_DATA_TO_ERROR    8
+#define V_CL8_WR_DATA_TO_ERROR(x) ((x) << S_CL8_WR_DATA_TO_ERROR)
+#define F_CL8_WR_DATA_TO_ERROR    V_CL8_WR_DATA_TO_ERROR(1U)
+
+#define S_CL7_WR_DATA_TO_ERROR    7
+#define V_CL7_WR_DATA_TO_ERROR(x) ((x) << S_CL7_WR_DATA_TO_ERROR)
+#define F_CL7_WR_DATA_TO_ERROR    V_CL7_WR_DATA_TO_ERROR(1U)
+
+#define S_CL6_WR_DATA_TO_ERROR    6
+#define V_CL6_WR_DATA_TO_ERROR(x) ((x) << S_CL6_WR_DATA_TO_ERROR)
+#define F_CL6_WR_DATA_TO_ERROR    V_CL6_WR_DATA_TO_ERROR(1U)
+
+#define S_CL5_WR_DATA_TO_ERROR    5
+#define V_CL5_WR_DATA_TO_ERROR(x) ((x) << S_CL5_WR_DATA_TO_ERROR)
+#define F_CL5_WR_DATA_TO_ERROR    V_CL5_WR_DATA_TO_ERROR(1U)
+
+#define S_CL4_WR_DATA_TO_ERROR    4
+#define V_CL4_WR_DATA_TO_ERROR(x) ((x) << S_CL4_WR_DATA_TO_ERROR)
+#define F_CL4_WR_DATA_TO_ERROR    V_CL4_WR_DATA_TO_ERROR(1U)
+
+#define S_CL3_WR_DATA_TO_ERROR    3
+#define V_CL3_WR_DATA_TO_ERROR(x) ((x) << S_CL3_WR_DATA_TO_ERROR)
+#define F_CL3_WR_DATA_TO_ERROR    V_CL3_WR_DATA_TO_ERROR(1U)
+
+#define S_CL2_WR_DATA_TO_ERROR    2
+#define V_CL2_WR_DATA_TO_ERROR(x) ((x) << S_CL2_WR_DATA_TO_ERROR)
+#define F_CL2_WR_DATA_TO_ERROR    V_CL2_WR_DATA_TO_ERROR(1U)
+
+#define S_CL1_WR_DATA_TO_ERROR    1
+#define V_CL1_WR_DATA_TO_ERROR(x) ((x) << S_CL1_WR_DATA_TO_ERROR)
+#define F_CL1_WR_DATA_TO_ERROR    V_CL1_WR_DATA_TO_ERROR(1U)
+
+#define S_CL0_WR_DATA_TO_ERROR    0
+#define V_CL0_WR_DATA_TO_ERROR(x) ((x) << S_CL0_WR_DATA_TO_ERROR)
+#define F_CL0_WR_DATA_TO_ERROR    V_CL0_WR_DATA_TO_ERROR(1U)
+
+#define A_MA_READ_TIMEOUT_ERROR_ENABLE 0x78dc
+
+#define S_CL12_RD_CMD_TO_EN    28
+#define V_CL12_RD_CMD_TO_EN(x) ((x) << S_CL12_RD_CMD_TO_EN)
+#define F_CL12_RD_CMD_TO_EN    V_CL12_RD_CMD_TO_EN(1U)
+
+#define S_CL11_RD_CMD_TO_EN    27
+#define V_CL11_RD_CMD_TO_EN(x) ((x) << S_CL11_RD_CMD_TO_EN)
+#define F_CL11_RD_CMD_TO_EN    V_CL11_RD_CMD_TO_EN(1U)
+
+#define S_CL10_RD_CMD_TO_EN    26
+#define V_CL10_RD_CMD_TO_EN(x) ((x) << S_CL10_RD_CMD_TO_EN)
+#define F_CL10_RD_CMD_TO_EN    V_CL10_RD_CMD_TO_EN(1U)
+
+#define S_CL9_RD_CMD_TO_EN    25
+#define V_CL9_RD_CMD_TO_EN(x) ((x) << S_CL9_RD_CMD_TO_EN)
+#define F_CL9_RD_CMD_TO_EN    V_CL9_RD_CMD_TO_EN(1U)
+
+#define S_CL8_RD_CMD_TO_EN    24
+#define V_CL8_RD_CMD_TO_EN(x) ((x) << S_CL8_RD_CMD_TO_EN)
+#define F_CL8_RD_CMD_TO_EN    V_CL8_RD_CMD_TO_EN(1U)
+
+#define S_CL7_RD_CMD_TO_EN    23
+#define V_CL7_RD_CMD_TO_EN(x) ((x) << S_CL7_RD_CMD_TO_EN)
+#define F_CL7_RD_CMD_TO_EN    V_CL7_RD_CMD_TO_EN(1U)
+
+#define S_CL6_RD_CMD_TO_EN    22
+#define V_CL6_RD_CMD_TO_EN(x) ((x) << S_CL6_RD_CMD_TO_EN)
+#define F_CL6_RD_CMD_TO_EN    V_CL6_RD_CMD_TO_EN(1U)
+
+#define S_CL5_RD_CMD_TO_EN    21
+#define V_CL5_RD_CMD_TO_EN(x) ((x) << S_CL5_RD_CMD_TO_EN)
+#define F_CL5_RD_CMD_TO_EN    V_CL5_RD_CMD_TO_EN(1U)
+
+#define S_CL4_RD_CMD_TO_EN    20
+#define V_CL4_RD_CMD_TO_EN(x) ((x) << S_CL4_RD_CMD_TO_EN)
+#define F_CL4_RD_CMD_TO_EN    V_CL4_RD_CMD_TO_EN(1U)
+
+#define S_CL3_RD_CMD_TO_EN    19
+#define V_CL3_RD_CMD_TO_EN(x) ((x) << S_CL3_RD_CMD_TO_EN)
+#define F_CL3_RD_CMD_TO_EN    V_CL3_RD_CMD_TO_EN(1U)
+
+#define S_CL2_RD_CMD_TO_EN    18
+#define V_CL2_RD_CMD_TO_EN(x) ((x) << S_CL2_RD_CMD_TO_EN)
+#define F_CL2_RD_CMD_TO_EN    V_CL2_RD_CMD_TO_EN(1U)
+
+#define S_CL1_RD_CMD_TO_EN    17
+#define V_CL1_RD_CMD_TO_EN(x) ((x) << S_CL1_RD_CMD_TO_EN)
+#define F_CL1_RD_CMD_TO_EN    V_CL1_RD_CMD_TO_EN(1U)
+
+#define S_CL0_RD_CMD_TO_EN    16
+#define V_CL0_RD_CMD_TO_EN(x) ((x) << S_CL0_RD_CMD_TO_EN)
+#define F_CL0_RD_CMD_TO_EN    V_CL0_RD_CMD_TO_EN(1U)
+
+#define S_CL12_RD_DATA_TO_EN    12
+#define V_CL12_RD_DATA_TO_EN(x) ((x) << S_CL12_RD_DATA_TO_EN)
+#define F_CL12_RD_DATA_TO_EN    V_CL12_RD_DATA_TO_EN(1U)
+
+#define S_CL11_RD_DATA_TO_EN    11
+#define V_CL11_RD_DATA_TO_EN(x) ((x) << S_CL11_RD_DATA_TO_EN)
+#define F_CL11_RD_DATA_TO_EN    V_CL11_RD_DATA_TO_EN(1U)
+
+#define S_CL10_RD_DATA_TO_EN    10
+#define V_CL10_RD_DATA_TO_EN(x) ((x) << S_CL10_RD_DATA_TO_EN)
+#define F_CL10_RD_DATA_TO_EN    V_CL10_RD_DATA_TO_EN(1U)
+
+#define S_CL9_RD_DATA_TO_EN    9
+#define V_CL9_RD_DATA_TO_EN(x) ((x) << S_CL9_RD_DATA_TO_EN)
+#define F_CL9_RD_DATA_TO_EN    V_CL9_RD_DATA_TO_EN(1U)
+
+#define S_CL8_RD_DATA_TO_EN    8
+#define V_CL8_RD_DATA_TO_EN(x) ((x) << S_CL8_RD_DATA_TO_EN)
+#define F_CL8_RD_DATA_TO_EN    V_CL8_RD_DATA_TO_EN(1U)
+
+#define S_CL7_RD_DATA_TO_EN    7
+#define V_CL7_RD_DATA_TO_EN(x) ((x) << S_CL7_RD_DATA_TO_EN)
+#define F_CL7_RD_DATA_TO_EN    V_CL7_RD_DATA_TO_EN(1U)
+
+#define S_CL6_RD_DATA_TO_EN    6
+#define V_CL6_RD_DATA_TO_EN(x) ((x) << S_CL6_RD_DATA_TO_EN)
+#define F_CL6_RD_DATA_TO_EN    V_CL6_RD_DATA_TO_EN(1U)
+
+#define S_CL5_RD_DATA_TO_EN    5
+#define V_CL5_RD_DATA_TO_EN(x) ((x) << S_CL5_RD_DATA_TO_EN)
+#define F_CL5_RD_DATA_TO_EN    V_CL5_RD_DATA_TO_EN(1U)
+
+#define S_CL4_RD_DATA_TO_EN    4
+#define V_CL4_RD_DATA_TO_EN(x) ((x) << S_CL4_RD_DATA_TO_EN)
+#define F_CL4_RD_DATA_TO_EN    V_CL4_RD_DATA_TO_EN(1U)
+
+#define S_CL3_RD_DATA_TO_EN    3
+#define V_CL3_RD_DATA_TO_EN(x) ((x) << S_CL3_RD_DATA_TO_EN)
+#define F_CL3_RD_DATA_TO_EN    V_CL3_RD_DATA_TO_EN(1U)
+
+#define S_CL2_RD_DATA_TO_EN    2
+#define V_CL2_RD_DATA_TO_EN(x) ((x) << S_CL2_RD_DATA_TO_EN)
+#define F_CL2_RD_DATA_TO_EN    V_CL2_RD_DATA_TO_EN(1U)
+
+#define S_CL1_RD_DATA_TO_EN    1
+#define V_CL1_RD_DATA_TO_EN(x) ((x) << S_CL1_RD_DATA_TO_EN)
+#define F_CL1_RD_DATA_TO_EN    V_CL1_RD_DATA_TO_EN(1U)
+
+#define S_CL0_RD_DATA_TO_EN    0
+#define V_CL0_RD_DATA_TO_EN(x) ((x) << S_CL0_RD_DATA_TO_EN)
+#define F_CL0_RD_DATA_TO_EN    V_CL0_RD_DATA_TO_EN(1U)
+
+#define A_MA_READ_TIMEOUT_ERROR_STATUS 0x78e0
+
+#define S_CL12_RD_CMD_TO_ERROR    28
+#define V_CL12_RD_CMD_TO_ERROR(x) ((x) << S_CL12_RD_CMD_TO_ERROR)
+#define F_CL12_RD_CMD_TO_ERROR    V_CL12_RD_CMD_TO_ERROR(1U)
+
+#define S_CL11_RD_CMD_TO_ERROR    27
+#define V_CL11_RD_CMD_TO_ERROR(x) ((x) << S_CL11_RD_CMD_TO_ERROR)
+#define F_CL11_RD_CMD_TO_ERROR    V_CL11_RD_CMD_TO_ERROR(1U)
+
+#define S_CL10_RD_CMD_TO_ERROR    26
+#define V_CL10_RD_CMD_TO_ERROR(x) ((x) << S_CL10_RD_CMD_TO_ERROR)
+#define F_CL10_RD_CMD_TO_ERROR    V_CL10_RD_CMD_TO_ERROR(1U)
+
+#define S_CL9_RD_CMD_TO_ERROR    25
+#define V_CL9_RD_CMD_TO_ERROR(x) ((x) << S_CL9_RD_CMD_TO_ERROR)
+#define F_CL9_RD_CMD_TO_ERROR    V_CL9_RD_CMD_TO_ERROR(1U)
+
+#define S_CL8_RD_CMD_TO_ERROR    24
+#define V_CL8_RD_CMD_TO_ERROR(x) ((x) << S_CL8_RD_CMD_TO_ERROR)
+#define F_CL8_RD_CMD_TO_ERROR    V_CL8_RD_CMD_TO_ERROR(1U)
+
+#define S_CL7_RD_CMD_TO_ERROR    23
+#define V_CL7_RD_CMD_TO_ERROR(x) ((x) << S_CL7_RD_CMD_TO_ERROR)
+#define F_CL7_RD_CMD_TO_ERROR    V_CL7_RD_CMD_TO_ERROR(1U)
+
+#define S_CL6_RD_CMD_TO_ERROR    22
+#define V_CL6_RD_CMD_TO_ERROR(x) ((x) << S_CL6_RD_CMD_TO_ERROR)
+#define F_CL6_RD_CMD_TO_ERROR    V_CL6_RD_CMD_TO_ERROR(1U)
+
+#define S_CL5_RD_CMD_TO_ERROR    21
+#define V_CL5_RD_CMD_TO_ERROR(x) ((x) << S_CL5_RD_CMD_TO_ERROR)
+#define F_CL5_RD_CMD_TO_ERROR    V_CL5_RD_CMD_TO_ERROR(1U)
+
+#define S_CL4_RD_CMD_TO_ERROR    20
+#define V_CL4_RD_CMD_TO_ERROR(x) ((x) << S_CL4_RD_CMD_TO_ERROR)
+#define F_CL4_RD_CMD_TO_ERROR    V_CL4_RD_CMD_TO_ERROR(1U)
+
+#define S_CL3_RD_CMD_TO_ERROR    19
+#define V_CL3_RD_CMD_TO_ERROR(x) ((x) << S_CL3_RD_CMD_TO_ERROR)
+#define F_CL3_RD_CMD_TO_ERROR    V_CL3_RD_CMD_TO_ERROR(1U)
+
+#define S_CL2_RD_CMD_TO_ERROR    18
+#define V_CL2_RD_CMD_TO_ERROR(x) ((x) << S_CL2_RD_CMD_TO_ERROR)
+#define F_CL2_RD_CMD_TO_ERROR    V_CL2_RD_CMD_TO_ERROR(1U)
+
+#define S_CL1_RD_CMD_TO_ERROR    17
+#define V_CL1_RD_CMD_TO_ERROR(x) ((x) << S_CL1_RD_CMD_TO_ERROR)
+#define F_CL1_RD_CMD_TO_ERROR    V_CL1_RD_CMD_TO_ERROR(1U)
+
+#define S_CL0_RD_CMD_TO_ERROR    16
+#define V_CL0_RD_CMD_TO_ERROR(x) ((x) << S_CL0_RD_CMD_TO_ERROR)
+#define F_CL0_RD_CMD_TO_ERROR    V_CL0_RD_CMD_TO_ERROR(1U)
+
+#define S_CL12_RD_DATA_TO_ERROR    12
+#define V_CL12_RD_DATA_TO_ERROR(x) ((x) << S_CL12_RD_DATA_TO_ERROR)
+#define F_CL12_RD_DATA_TO_ERROR    V_CL12_RD_DATA_TO_ERROR(1U)
+
+#define S_CL11_RD_DATA_TO_ERROR    11
+#define V_CL11_RD_DATA_TO_ERROR(x) ((x) << S_CL11_RD_DATA_TO_ERROR)
+#define F_CL11_RD_DATA_TO_ERROR    V_CL11_RD_DATA_TO_ERROR(1U)
+
+#define S_CL10_RD_DATA_TO_ERROR    10
+#define V_CL10_RD_DATA_TO_ERROR(x) ((x) << S_CL10_RD_DATA_TO_ERROR)
+#define F_CL10_RD_DATA_TO_ERROR    V_CL10_RD_DATA_TO_ERROR(1U)
+
+#define S_CL9_RD_DATA_TO_ERROR    9
+#define V_CL9_RD_DATA_TO_ERROR(x) ((x) << S_CL9_RD_DATA_TO_ERROR)
+#define F_CL9_RD_DATA_TO_ERROR    V_CL9_RD_DATA_TO_ERROR(1U)
+
+#define S_CL8_RD_DATA_TO_ERROR    8
+#define V_CL8_RD_DATA_TO_ERROR(x) ((x) << S_CL8_RD_DATA_TO_ERROR)
+#define F_CL8_RD_DATA_TO_ERROR    V_CL8_RD_DATA_TO_ERROR(1U)
+
+#define S_CL7_RD_DATA_TO_ERROR    7
+#define V_CL7_RD_DATA_TO_ERROR(x) ((x) << S_CL7_RD_DATA_TO_ERROR)
+#define F_CL7_RD_DATA_TO_ERROR    V_CL7_RD_DATA_TO_ERROR(1U)
+
+#define S_CL6_RD_DATA_TO_ERROR    6
+#define V_CL6_RD_DATA_TO_ERROR(x) ((x) << S_CL6_RD_DATA_TO_ERROR)
+#define F_CL6_RD_DATA_TO_ERROR    V_CL6_RD_DATA_TO_ERROR(1U)
+
+#define S_CL5_RD_DATA_TO_ERROR    5
+#define V_CL5_RD_DATA_TO_ERROR(x) ((x) << S_CL5_RD_DATA_TO_ERROR)
+#define F_CL5_RD_DATA_TO_ERROR    V_CL5_RD_DATA_TO_ERROR(1U)
+
+#define S_CL4_RD_DATA_TO_ERROR    4
+#define V_CL4_RD_DATA_TO_ERROR(x) ((x) << S_CL4_RD_DATA_TO_ERROR)
+#define F_CL4_RD_DATA_TO_ERROR    V_CL4_RD_DATA_TO_ERROR(1U)
+
+#define S_CL3_RD_DATA_TO_ERROR    3
+#define V_CL3_RD_DATA_TO_ERROR(x) ((x) << S_CL3_RD_DATA_TO_ERROR)
+#define F_CL3_RD_DATA_TO_ERROR    V_CL3_RD_DATA_TO_ERROR(1U)
+
+#define S_CL2_RD_DATA_TO_ERROR    2
+#define V_CL2_RD_DATA_TO_ERROR(x) ((x) << S_CL2_RD_DATA_TO_ERROR)
+#define F_CL2_RD_DATA_TO_ERROR    V_CL2_RD_DATA_TO_ERROR(1U)
+
+#define S_CL1_RD_DATA_TO_ERROR    1
+#define V_CL1_RD_DATA_TO_ERROR(x) ((x) << S_CL1_RD_DATA_TO_ERROR)
+#define F_CL1_RD_DATA_TO_ERROR    V_CL1_RD_DATA_TO_ERROR(1U)
+
+#define S_CL0_RD_DATA_TO_ERROR    0
+#define V_CL0_RD_DATA_TO_ERROR(x) ((x) << S_CL0_RD_DATA_TO_ERROR)
+#define F_CL0_RD_DATA_TO_ERROR    V_CL0_RD_DATA_TO_ERROR(1U)
+
+#define A_MA_BKP_CNT_SEL 0x78e4
+
+#define S_BKP_CNT_TYPE    30
+#define M_BKP_CNT_TYPE    0x3U
+#define V_BKP_CNT_TYPE(x) ((x) << S_BKP_CNT_TYPE)
+#define G_BKP_CNT_TYPE(x) (((x) >> S_BKP_CNT_TYPE) & M_BKP_CNT_TYPE)
+
+#define S_BKP_CLIENT    24
+#define M_BKP_CLIENT    0xfU
+#define V_BKP_CLIENT(x) ((x) << S_BKP_CLIENT)
+#define G_BKP_CLIENT(x) (((x) >> S_BKP_CLIENT) & M_BKP_CLIENT)
+
+#define A_MA_BKP_CNT 0x78e8
+#define A_MA_WRT_ARB 0x78ec
+
+#define S_WRT_EN    31
+#define V_WRT_EN(x) ((x) << S_WRT_EN)
+#define F_WRT_EN    V_WRT_EN(1U)
+
+#define S_WR_TIM    16
+#define M_WR_TIM    0xffU
+#define V_WR_TIM(x) ((x) << S_WR_TIM)
+#define G_WR_TIM(x) (((x) >> S_WR_TIM) & M_WR_TIM)
+
+#define S_RD_WIN    8
+#define M_RD_WIN    0xffU
+#define V_RD_WIN(x) ((x) << S_RD_WIN)
+#define G_RD_WIN(x) (((x) >> S_RD_WIN) & M_RD_WIN)
+
+#define S_WR_WIN    0
+#define M_WR_WIN    0xffU
+#define V_WR_WIN(x) ((x) << S_WR_WIN)
+#define G_WR_WIN(x) (((x) >> S_WR_WIN) & M_WR_WIN)
+
+#define A_MA_IF_PARITY_ERROR_ENABLE 0x78f0
+
+#define S_CL12_IF_PAR_EN    12
+#define V_CL12_IF_PAR_EN(x) ((x) << S_CL12_IF_PAR_EN)
+#define F_CL12_IF_PAR_EN    V_CL12_IF_PAR_EN(1U)
+
+#define S_CL11_IF_PAR_EN    11
+#define V_CL11_IF_PAR_EN(x) ((x) << S_CL11_IF_PAR_EN)
+#define F_CL11_IF_PAR_EN    V_CL11_IF_PAR_EN(1U)
+
+#define S_CL10_IF_PAR_EN    10
+#define V_CL10_IF_PAR_EN(x) ((x) << S_CL10_IF_PAR_EN)
+#define F_CL10_IF_PAR_EN    V_CL10_IF_PAR_EN(1U)
+
+#define S_CL9_IF_PAR_EN    9
+#define V_CL9_IF_PAR_EN(x) ((x) << S_CL9_IF_PAR_EN)
+#define F_CL9_IF_PAR_EN    V_CL9_IF_PAR_EN(1U)
+
+#define S_CL8_IF_PAR_EN    8
+#define V_CL8_IF_PAR_EN(x) ((x) << S_CL8_IF_PAR_EN)
+#define F_CL8_IF_PAR_EN    V_CL8_IF_PAR_EN(1U)
+
+#define S_CL7_IF_PAR_EN    7
+#define V_CL7_IF_PAR_EN(x) ((x) << S_CL7_IF_PAR_EN)
+#define F_CL7_IF_PAR_EN    V_CL7_IF_PAR_EN(1U)
+
+#define S_CL6_IF_PAR_EN    6
+#define V_CL6_IF_PAR_EN(x) ((x) << S_CL6_IF_PAR_EN)
+#define F_CL6_IF_PAR_EN    V_CL6_IF_PAR_EN(1U)
+
+#define S_CL5_IF_PAR_EN    5
+#define V_CL5_IF_PAR_EN(x) ((x) << S_CL5_IF_PAR_EN)
+#define F_CL5_IF_PAR_EN    V_CL5_IF_PAR_EN(1U)
+
+#define S_CL4_IF_PAR_EN    4
+#define V_CL4_IF_PAR_EN(x) ((x) << S_CL4_IF_PAR_EN)
+#define F_CL4_IF_PAR_EN    V_CL4_IF_PAR_EN(1U)
+
+#define S_CL3_IF_PAR_EN    3
+#define V_CL3_IF_PAR_EN(x) ((x) << S_CL3_IF_PAR_EN)
+#define F_CL3_IF_PAR_EN    V_CL3_IF_PAR_EN(1U)
+
+#define S_CL2_IF_PAR_EN    2
+#define V_CL2_IF_PAR_EN(x) ((x) << S_CL2_IF_PAR_EN)
+#define F_CL2_IF_PAR_EN    V_CL2_IF_PAR_EN(1U)
+
+#define S_CL1_IF_PAR_EN    1
+#define V_CL1_IF_PAR_EN(x) ((x) << S_CL1_IF_PAR_EN)
+#define F_CL1_IF_PAR_EN    V_CL1_IF_PAR_EN(1U)
+
+#define S_CL0_IF_PAR_EN    0
+#define V_CL0_IF_PAR_EN(x) ((x) << S_CL0_IF_PAR_EN)
+#define F_CL0_IF_PAR_EN    V_CL0_IF_PAR_EN(1U)
+
+#define A_MA_IF_PARITY_ERROR_STATUS 0x78f4
+
+#define S_CL12_IF_PAR_ERROR    12
+#define V_CL12_IF_PAR_ERROR(x) ((x) << S_CL12_IF_PAR_ERROR)
+#define F_CL12_IF_PAR_ERROR    V_CL12_IF_PAR_ERROR(1U)
+
+#define S_CL11_IF_PAR_ERROR    11
+#define V_CL11_IF_PAR_ERROR(x) ((x) << S_CL11_IF_PAR_ERROR)
+#define F_CL11_IF_PAR_ERROR    V_CL11_IF_PAR_ERROR(1U)
+
+#define S_CL10_IF_PAR_ERROR    10
+#define V_CL10_IF_PAR_ERROR(x) ((x) << S_CL10_IF_PAR_ERROR)
+#define F_CL10_IF_PAR_ERROR    V_CL10_IF_PAR_ERROR(1U)
+
+#define S_CL9_IF_PAR_ERROR    9
+#define V_CL9_IF_PAR_ERROR(x) ((x) << S_CL9_IF_PAR_ERROR)
+#define F_CL9_IF_PAR_ERROR    V_CL9_IF_PAR_ERROR(1U)
+
+#define S_CL8_IF_PAR_ERROR    8
+#define V_CL8_IF_PAR_ERROR(x) ((x) << S_CL8_IF_PAR_ERROR)
+#define F_CL8_IF_PAR_ERROR    V_CL8_IF_PAR_ERROR(1U)
+
+#define S_CL7_IF_PAR_ERROR    7
+#define V_CL7_IF_PAR_ERROR(x) ((x) << S_CL7_IF_PAR_ERROR)
+#define F_CL7_IF_PAR_ERROR    V_CL7_IF_PAR_ERROR(1U)
+
+#define S_CL6_IF_PAR_ERROR    6
+#define V_CL6_IF_PAR_ERROR(x) ((x) << S_CL6_IF_PAR_ERROR)
+#define F_CL6_IF_PAR_ERROR    V_CL6_IF_PAR_ERROR(1U)
+
+#define S_CL5_IF_PAR_ERROR    5
+#define V_CL5_IF_PAR_ERROR(x) ((x) << S_CL5_IF_PAR_ERROR)
+#define F_CL5_IF_PAR_ERROR    V_CL5_IF_PAR_ERROR(1U)
+
+#define S_CL4_IF_PAR_ERROR    4
+#define V_CL4_IF_PAR_ERROR(x) ((x) << S_CL4_IF_PAR_ERROR)
+#define F_CL4_IF_PAR_ERROR    V_CL4_IF_PAR_ERROR(1U)
+
+#define S_CL3_IF_PAR_ERROR    3
+#define V_CL3_IF_PAR_ERROR(x) ((x) << S_CL3_IF_PAR_ERROR)
+#define F_CL3_IF_PAR_ERROR    V_CL3_IF_PAR_ERROR(1U)
+
+#define S_CL2_IF_PAR_ERROR    2
+#define V_CL2_IF_PAR_ERROR(x) ((x) << S_CL2_IF_PAR_ERROR)
+#define F_CL2_IF_PAR_ERROR    V_CL2_IF_PAR_ERROR(1U)
+
+#define S_CL1_IF_PAR_ERROR    1
+#define V_CL1_IF_PAR_ERROR(x) ((x) << S_CL1_IF_PAR_ERROR)
+#define F_CL1_IF_PAR_ERROR    V_CL1_IF_PAR_ERROR(1U)
+
+#define S_CL0_IF_PAR_ERROR    0
+#define V_CL0_IF_PAR_ERROR(x) ((x) << S_CL0_IF_PAR_ERROR)
+#define F_CL0_IF_PAR_ERROR    V_CL0_IF_PAR_ERROR(1U)
+
+#define A_MA_LOCAL_DEBUG_CFG 0x78f8
+
+#define S_DEBUG_OR    15
+#define V_DEBUG_OR(x) ((x) << S_DEBUG_OR)
+#define F_DEBUG_OR    V_DEBUG_OR(1U)
+
+#define S_DEBUG_HI    14
+#define V_DEBUG_HI(x) ((x) << S_DEBUG_HI)
+#define F_DEBUG_HI    V_DEBUG_HI(1U)
+
+#define S_DEBUG_RPT    13
+#define V_DEBUG_RPT(x) ((x) << S_DEBUG_RPT)
+#define F_DEBUG_RPT    V_DEBUG_RPT(1U)
+
+#define S_DEBUGPAGE    10
+#define M_DEBUGPAGE    0x7U
+#define V_DEBUGPAGE(x) ((x) << S_DEBUGPAGE)
+#define G_DEBUGPAGE(x) (((x) >> S_DEBUGPAGE) & M_DEBUGPAGE)
+
+#define A_MA_LOCAL_DEBUG_RPT 0x78fc
+
+/* registers for module EDC_0 */
+#define EDC_0_BASE_ADDR 0x7900
+
+#define A_EDC_REF 0x7900
+
+#define S_EDC_INST_NUM    18
+#define V_EDC_INST_NUM(x) ((x) << S_EDC_INST_NUM)
+#define F_EDC_INST_NUM    V_EDC_INST_NUM(1U)
+
+#define S_ENABLE_PERF    17
+#define V_ENABLE_PERF(x) ((x) << S_ENABLE_PERF)
+#define F_ENABLE_PERF    V_ENABLE_PERF(1U)
+
+#define S_ECC_BYPASS    16
+#define V_ECC_BYPASS(x) ((x) << S_ECC_BYPASS)
+#define F_ECC_BYPASS    V_ECC_BYPASS(1U)
+
+#define S_REFFREQ    0
+#define M_REFFREQ    0xffffU
+#define V_REFFREQ(x) ((x) << S_REFFREQ)
+#define G_REFFREQ(x) (((x) >> S_REFFREQ) & M_REFFREQ)
+
+#define A_EDC_BIST_CMD 0x7904
+#define A_EDC_BIST_CMD_ADDR 0x7908
+#define A_EDC_BIST_CMD_LEN 0x790c
+#define A_EDC_BIST_DATA_PATTERN 0x7910
+#define A_EDC_BIST_USER_WDATA0 0x7914
+#define A_EDC_BIST_USER_WDATA1 0x7918
+#define A_EDC_BIST_USER_WDATA2 0x791c
+#define A_EDC_BIST_NUM_ERR 0x7920
+#define A_EDC_BIST_ERR_FIRST_ADDR 0x7924
+#define A_EDC_BIST_STATUS_RDATA 0x7928
+#define A_EDC_PAR_ENABLE 0x7970
+
+#define S_ECC_UE    2
+#define V_ECC_UE(x) ((x) << S_ECC_UE)
+#define F_ECC_UE    V_ECC_UE(1U)
+
+#define S_ECC_CE    1
+#define V_ECC_CE(x) ((x) << S_ECC_CE)
+#define F_ECC_CE    V_ECC_CE(1U)
+
+#define A_EDC_INT_ENABLE 0x7974
+#define A_EDC_INT_CAUSE 0x7978
+
+#define S_ECC_UE_PAR    5
+#define V_ECC_UE_PAR(x) ((x) << S_ECC_UE_PAR)
+#define F_ECC_UE_PAR    V_ECC_UE_PAR(1U)
+
+#define S_ECC_CE_PAR    4
+#define V_ECC_CE_PAR(x) ((x) << S_ECC_CE_PAR)
+#define F_ECC_CE_PAR    V_ECC_CE_PAR(1U)
+
+#define S_PERR_PAR_CAUSE    3
+#define V_PERR_PAR_CAUSE(x) ((x) << S_PERR_PAR_CAUSE)
+#define F_PERR_PAR_CAUSE    V_PERR_PAR_CAUSE(1U)
+
+#define A_EDC_ECC_STATUS 0x797c
+
+/* registers for module EDC_1 */
+#define EDC_1_BASE_ADDR 0x7980
+
+/* registers for module HMA */
+#define HMA_BASE_ADDR 0x7a00
+
+/* registers for module CIM */
+#define CIM_BASE_ADDR 0x7b00
+
+#define A_CIM_VF_EXT_MAILBOX_CTRL 0x0
+
+#define S_VFMBGENERIC    4
+#define M_VFMBGENERIC    0xfU
+#define V_VFMBGENERIC(x) ((x) << S_VFMBGENERIC)
+#define G_VFMBGENERIC(x) (((x) >> S_VFMBGENERIC) & M_VFMBGENERIC)
+
+#define A_CIM_VF_EXT_MAILBOX_STATUS 0x4
+
+#define S_MBVFREADY    0
+#define V_MBVFREADY(x) ((x) << S_MBVFREADY)
+#define F_MBVFREADY    V_MBVFREADY(1U)
+
+#define A_CIM_PF_MAILBOX_DATA 0x240
+#define A_CIM_PF_MAILBOX_CTRL 0x280
+
+#define S_MBGENERIC    4
+#define M_MBGENERIC    0xfffffffU
+#define V_MBGENERIC(x) ((x) << S_MBGENERIC)
+#define G_MBGENERIC(x) (((x) >> S_MBGENERIC) & M_MBGENERIC)
+
+#define S_MBMSGVALID    3
+#define V_MBMSGVALID(x) ((x) << S_MBMSGVALID)
+#define F_MBMSGVALID    V_MBMSGVALID(1U)
+
+#define S_MBINTREQ    2
+#define V_MBINTREQ(x) ((x) << S_MBINTREQ)
+#define F_MBINTREQ    V_MBINTREQ(1U)
+
+#define S_MBOWNER    0
+#define M_MBOWNER    0x3U
+#define V_MBOWNER(x) ((x) << S_MBOWNER)
+#define G_MBOWNER(x) (((x) >> S_MBOWNER) & M_MBOWNER)
+
+#define A_CIM_PF_MAILBOX_ACC_STATUS 0x284
+
+#define S_MBWRBUSY    31
+#define V_MBWRBUSY(x) ((x) << S_MBWRBUSY)
+#define F_MBWRBUSY    V_MBWRBUSY(1U)
+
+#define A_CIM_PF_HOST_INT_ENABLE 0x288
+
+#define S_MBMSGRDYINTEN    19
+#define V_MBMSGRDYINTEN(x) ((x) << S_MBMSGRDYINTEN)
+#define F_MBMSGRDYINTEN    V_MBMSGRDYINTEN(1U)
+
+#define A_CIM_PF_HOST_INT_CAUSE 0x28c
+
+#define S_MBMSGRDYINT    19
+#define V_MBMSGRDYINT(x) ((x) << S_MBMSGRDYINT)
+#define F_MBMSGRDYINT    V_MBMSGRDYINT(1U)
+
+#define A_CIM_PF_MAILBOX_CTRL_SHADOW_COPY 0x290
+#define A_CIM_BOOT_CFG 0x7b00
+
+#define S_BOOTADDR    8
+#define M_BOOTADDR    0xffffffU
+#define V_BOOTADDR(x) ((x) << S_BOOTADDR)
+#define G_BOOTADDR(x) (((x) >> S_BOOTADDR) & M_BOOTADDR)
+
+#define S_UPGEN    2
+#define M_UPGEN    0x3fU
+#define V_UPGEN(x) ((x) << S_UPGEN)
+#define G_UPGEN(x) (((x) >> S_UPGEN) & M_UPGEN)
+
+#define S_BOOTSDRAM    1
+#define V_BOOTSDRAM(x) ((x) << S_BOOTSDRAM)
+#define F_BOOTSDRAM    V_BOOTSDRAM(1U)
+
+#define S_UPCRST    0
+#define V_UPCRST(x) ((x) << S_UPCRST)
+#define F_UPCRST    V_UPCRST(1U)
+
+#define A_CIM_FLASH_BASE_ADDR 0x7b04
+
+#define S_FLASHBASEADDR    6
+#define M_FLASHBASEADDR    0x3ffffU
+#define V_FLASHBASEADDR(x) ((x) << S_FLASHBASEADDR)
+#define G_FLASHBASEADDR(x) (((x) >> S_FLASHBASEADDR) & M_FLASHBASEADDR)
+
+#define A_CIM_FLASH_ADDR_SIZE 0x7b08
+
+#define S_FLASHADDRSIZE    4
+#define M_FLASHADDRSIZE    0xfffffU
+#define V_FLASHADDRSIZE(x) ((x) << S_FLASHADDRSIZE)
+#define G_FLASHADDRSIZE(x) (((x) >> S_FLASHADDRSIZE) & M_FLASHADDRSIZE)
+
+#define A_CIM_EEPROM_BASE_ADDR 0x7b0c
+
+#define S_EEPROMBASEADDR    6
+#define M_EEPROMBASEADDR    0x3ffffU
+#define V_EEPROMBASEADDR(x) ((x) << S_EEPROMBASEADDR)
+#define G_EEPROMBASEADDR(x) (((x) >> S_EEPROMBASEADDR) & M_EEPROMBASEADDR)
+
+#define A_CIM_EEPROM_ADDR_SIZE 0x7b10
+
+#define S_EEPROMADDRSIZE    4
+#define M_EEPROMADDRSIZE    0xfffffU
+#define V_EEPROMADDRSIZE(x) ((x) << S_EEPROMADDRSIZE)
+#define G_EEPROMADDRSIZE(x) (((x) >> S_EEPROMADDRSIZE) & M_EEPROMADDRSIZE)
+
+#define A_CIM_SDRAM_BASE_ADDR 0x7b14
+
+#define S_SDRAMBASEADDR    6
+#define M_SDRAMBASEADDR    0x3ffffffU
+#define V_SDRAMBASEADDR(x) ((x) << S_SDRAMBASEADDR)
+#define G_SDRAMBASEADDR(x) (((x) >> S_SDRAMBASEADDR) & M_SDRAMBASEADDR)
+
+#define A_CIM_SDRAM_ADDR_SIZE 0x7b18
+
+#define S_SDRAMADDRSIZE    4
+#define M_SDRAMADDRSIZE    0xfffffffU
+#define V_SDRAMADDRSIZE(x) ((x) << S_SDRAMADDRSIZE)
+#define G_SDRAMADDRSIZE(x) (((x) >> S_SDRAMADDRSIZE) & M_SDRAMADDRSIZE)
+
+#define A_CIM_EXTMEM2_BASE_ADDR 0x7b1c
+
+#define S_EXTMEM2BASEADDR    6
+#define M_EXTMEM2BASEADDR    0x3ffffffU
+#define V_EXTMEM2BASEADDR(x) ((x) << S_EXTMEM2BASEADDR)
+#define G_EXTMEM2BASEADDR(x) (((x) >> S_EXTMEM2BASEADDR) & M_EXTMEM2BASEADDR)
+
+#define A_CIM_EXTMEM2_ADDR_SIZE 0x7b20
+
+#define S_EXTMEM2ADDRSIZE    4
+#define M_EXTMEM2ADDRSIZE    0xfffffffU
+#define V_EXTMEM2ADDRSIZE(x) ((x) << S_EXTMEM2ADDRSIZE)
+#define G_EXTMEM2ADDRSIZE(x) (((x) >> S_EXTMEM2ADDRSIZE) & M_EXTMEM2ADDRSIZE)
+
+#define A_CIM_UP_SPARE_INT 0x7b24
+
+#define S_TDEBUGINT    4
+#define V_TDEBUGINT(x) ((x) << S_TDEBUGINT)
+#define F_TDEBUGINT    V_TDEBUGINT(1U)
+
+#define S_BOOTVECSEL    3
+#define V_BOOTVECSEL(x) ((x) << S_BOOTVECSEL)
+#define F_BOOTVECSEL    V_BOOTVECSEL(1U)
+
+#define S_UPSPAREINT    0
+#define M_UPSPAREINT    0x7U
+#define V_UPSPAREINT(x) ((x) << S_UPSPAREINT)
+#define G_UPSPAREINT(x) (((x) >> S_UPSPAREINT) & M_UPSPAREINT)
+
+#define A_CIM_HOST_INT_ENABLE 0x7b28
+
+#define S_TIEQOUTPARERRINTEN    20
+#define V_TIEQOUTPARERRINTEN(x) ((x) << S_TIEQOUTPARERRINTEN)
+#define F_TIEQOUTPARERRINTEN    V_TIEQOUTPARERRINTEN(1U)
+
+#define S_TIEQINPARERRINTEN    19
+#define V_TIEQINPARERRINTEN(x) ((x) << S_TIEQINPARERRINTEN)
+#define F_TIEQINPARERRINTEN    V_TIEQINPARERRINTEN(1U)
+
+#define S_MBHOSTPARERR    18
+#define V_MBHOSTPARERR(x) ((x) << S_MBHOSTPARERR)
+#define F_MBHOSTPARERR    V_MBHOSTPARERR(1U)
+
+#define S_MBUPPARERR    17
+#define V_MBUPPARERR(x) ((x) << S_MBUPPARERR)
+#define F_MBUPPARERR    V_MBUPPARERR(1U)
+
+#define S_IBQTP0PARERR    16
+#define V_IBQTP0PARERR(x) ((x) << S_IBQTP0PARERR)
+#define F_IBQTP0PARERR    V_IBQTP0PARERR(1U)
+
+#define S_IBQTP1PARERR    15
+#define V_IBQTP1PARERR(x) ((x) << S_IBQTP1PARERR)
+#define F_IBQTP1PARERR    V_IBQTP1PARERR(1U)
+
+#define S_IBQULPPARERR    14
+#define V_IBQULPPARERR(x) ((x) << S_IBQULPPARERR)
+#define F_IBQULPPARERR    V_IBQULPPARERR(1U)
+
+#define S_IBQSGELOPARERR    13
+#define V_IBQSGELOPARERR(x) ((x) << S_IBQSGELOPARERR)
+#define F_IBQSGELOPARERR    V_IBQSGELOPARERR(1U)
+
+#define S_IBQSGEHIPARERR    12
+#define V_IBQSGEHIPARERR(x) ((x) << S_IBQSGEHIPARERR)
+#define F_IBQSGEHIPARERR    V_IBQSGEHIPARERR(1U)
+
+#define S_IBQNCSIPARERR    11
+#define V_IBQNCSIPARERR(x) ((x) << S_IBQNCSIPARERR)
+#define F_IBQNCSIPARERR    V_IBQNCSIPARERR(1U)
+
+#define S_OBQULP0PARERR    10
+#define V_OBQULP0PARERR(x) ((x) << S_OBQULP0PARERR)
+#define F_OBQULP0PARERR    V_OBQULP0PARERR(1U)
+
+#define S_OBQULP1PARERR    9
+#define V_OBQULP1PARERR(x) ((x) << S_OBQULP1PARERR)
+#define F_OBQULP1PARERR    V_OBQULP1PARERR(1U)
+
+#define S_OBQULP2PARERR    8
+#define V_OBQULP2PARERR(x) ((x) << S_OBQULP2PARERR)
+#define F_OBQULP2PARERR    V_OBQULP2PARERR(1U)
+
+#define S_OBQULP3PARERR    7
+#define V_OBQULP3PARERR(x) ((x) << S_OBQULP3PARERR)
+#define F_OBQULP3PARERR    V_OBQULP3PARERR(1U)
+
+#define S_OBQSGEPARERR    6
+#define V_OBQSGEPARERR(x) ((x) << S_OBQSGEPARERR)
+#define F_OBQSGEPARERR    V_OBQSGEPARERR(1U)
+
+#define S_OBQNCSIPARERR    5
+#define V_OBQNCSIPARERR(x) ((x) << S_OBQNCSIPARERR)
+#define F_OBQNCSIPARERR    V_OBQNCSIPARERR(1U)
+
+#define S_TIMER1INTEN    3
+#define V_TIMER1INTEN(x) ((x) << S_TIMER1INTEN)
+#define F_TIMER1INTEN    V_TIMER1INTEN(1U)
+
+#define S_TIMER0INTEN    2
+#define V_TIMER0INTEN(x) ((x) << S_TIMER0INTEN)
+#define F_TIMER0INTEN    V_TIMER0INTEN(1U)
+
+#define S_PREFDROPINTEN    1
+#define V_PREFDROPINTEN(x) ((x) << S_PREFDROPINTEN)
+#define F_PREFDROPINTEN    V_PREFDROPINTEN(1U)
+
+#define S_MA_CIM_INTFPERR    28
+#define V_MA_CIM_INTFPERR(x) ((x) << S_MA_CIM_INTFPERR)
+#define F_MA_CIM_INTFPERR    V_MA_CIM_INTFPERR(1U)
+
+#define S_PLCIM_MSTRSPDATAPARERR    27
+#define V_PLCIM_MSTRSPDATAPARERR(x) ((x) << S_PLCIM_MSTRSPDATAPARERR)
+#define F_PLCIM_MSTRSPDATAPARERR    V_PLCIM_MSTRSPDATAPARERR(1U)
+
+#define S_NCSI2CIMINTFPARERR    26
+#define V_NCSI2CIMINTFPARERR(x) ((x) << S_NCSI2CIMINTFPARERR)
+#define F_NCSI2CIMINTFPARERR    V_NCSI2CIMINTFPARERR(1U)
+
+#define S_SGE2CIMINTFPARERR    25
+#define V_SGE2CIMINTFPARERR(x) ((x) << S_SGE2CIMINTFPARERR)
+#define F_SGE2CIMINTFPARERR    V_SGE2CIMINTFPARERR(1U)
+
+#define S_ULP2CIMINTFPARERR    24
+#define V_ULP2CIMINTFPARERR(x) ((x) << S_ULP2CIMINTFPARERR)
+#define F_ULP2CIMINTFPARERR    V_ULP2CIMINTFPARERR(1U)
+
+#define S_TP2CIMINTFPARERR    23
+#define V_TP2CIMINTFPARERR(x) ((x) << S_TP2CIMINTFPARERR)
+#define F_TP2CIMINTFPARERR    V_TP2CIMINTFPARERR(1U)
+
+#define S_OBQSGERX1PARERR    22
+#define V_OBQSGERX1PARERR(x) ((x) << S_OBQSGERX1PARERR)
+#define F_OBQSGERX1PARERR    V_OBQSGERX1PARERR(1U)
+
+#define S_OBQSGERX0PARERR    21
+#define V_OBQSGERX0PARERR(x) ((x) << S_OBQSGERX0PARERR)
+#define F_OBQSGERX0PARERR    V_OBQSGERX0PARERR(1U)
+
+#define A_CIM_HOST_INT_CAUSE 0x7b2c
+
+#define S_TIEQOUTPARERRINT    20
+#define V_TIEQOUTPARERRINT(x) ((x) << S_TIEQOUTPARERRINT)
+#define F_TIEQOUTPARERRINT    V_TIEQOUTPARERRINT(1U)
+
+#define S_TIEQINPARERRINT    19
+#define V_TIEQINPARERRINT(x) ((x) << S_TIEQINPARERRINT)
+#define F_TIEQINPARERRINT    V_TIEQINPARERRINT(1U)
+
+#define S_TIMER1INT    3
+#define V_TIMER1INT(x) ((x) << S_TIMER1INT)
+#define F_TIMER1INT    V_TIMER1INT(1U)
+
+#define S_TIMER0INT    2
+#define V_TIMER0INT(x) ((x) << S_TIMER0INT)
+#define F_TIMER0INT    V_TIMER0INT(1U)
+
+#define S_PREFDROPINT    1
+#define V_PREFDROPINT(x) ((x) << S_PREFDROPINT)
+#define F_PREFDROPINT    V_PREFDROPINT(1U)
+
+#define S_UPACCNONZERO    0
+#define V_UPACCNONZERO(x) ((x) << S_UPACCNONZERO)
+#define F_UPACCNONZERO    V_UPACCNONZERO(1U)
+
+#define A_CIM_HOST_UPACC_INT_ENABLE 0x7b30
+
+#define S_EEPROMWRINTEN    30
+#define V_EEPROMWRINTEN(x) ((x) << S_EEPROMWRINTEN)
+#define F_EEPROMWRINTEN    V_EEPROMWRINTEN(1U)
+
+#define S_TIMEOUTMAINTEN    29
+#define V_TIMEOUTMAINTEN(x) ((x) << S_TIMEOUTMAINTEN)
+#define F_TIMEOUTMAINTEN    V_TIMEOUTMAINTEN(1U)
+
+#define S_TIMEOUTINTEN    28
+#define V_TIMEOUTINTEN(x) ((x) << S_TIMEOUTINTEN)
+#define F_TIMEOUTINTEN    V_TIMEOUTINTEN(1U)
+
+#define S_RSPOVRLOOKUPINTEN    27
+#define V_RSPOVRLOOKUPINTEN(x) ((x) << S_RSPOVRLOOKUPINTEN)
+#define F_RSPOVRLOOKUPINTEN    V_RSPOVRLOOKUPINTEN(1U)
+
+#define S_REQOVRLOOKUPINTEN    26
+#define V_REQOVRLOOKUPINTEN(x) ((x) << S_REQOVRLOOKUPINTEN)
+#define F_REQOVRLOOKUPINTEN    V_REQOVRLOOKUPINTEN(1U)
+
+#define S_BLKWRPLINTEN    25
+#define V_BLKWRPLINTEN(x) ((x) << S_BLKWRPLINTEN)
+#define F_BLKWRPLINTEN    V_BLKWRPLINTEN(1U)
+
+#define S_BLKRDPLINTEN    24
+#define V_BLKRDPLINTEN(x) ((x) << S_BLKRDPLINTEN)
+#define F_BLKRDPLINTEN    V_BLKRDPLINTEN(1U)
+
+#define S_SGLWRPLINTEN    23
+#define V_SGLWRPLINTEN(x) ((x) << S_SGLWRPLINTEN)
+#define F_SGLWRPLINTEN    V_SGLWRPLINTEN(1U)
+
+#define S_SGLRDPLINTEN    22
+#define V_SGLRDPLINTEN(x) ((x) << S_SGLRDPLINTEN)
+#define F_SGLRDPLINTEN    V_SGLRDPLINTEN(1U)
+
+#define S_BLKWRCTLINTEN    21
+#define V_BLKWRCTLINTEN(x) ((x) << S_BLKWRCTLINTEN)
+#define F_BLKWRCTLINTEN    V_BLKWRCTLINTEN(1U)
+
+#define S_BLKRDCTLINTEN    20
+#define V_BLKRDCTLINTEN(x) ((x) << S_BLKRDCTLINTEN)
+#define F_BLKRDCTLINTEN    V_BLKRDCTLINTEN(1U)
+
+#define S_SGLWRCTLINTEN    19
+#define V_SGLWRCTLINTEN(x) ((x) << S_SGLWRCTLINTEN)
+#define F_SGLWRCTLINTEN    V_SGLWRCTLINTEN(1U)
+
+#define S_SGLRDCTLINTEN    18
+#define V_SGLRDCTLINTEN(x) ((x) << S_SGLRDCTLINTEN)
+#define F_SGLRDCTLINTEN    V_SGLRDCTLINTEN(1U)
+
+#define S_BLKWREEPROMINTEN    17
+#define V_BLKWREEPROMINTEN(x) ((x) << S_BLKWREEPROMINTEN)
+#define F_BLKWREEPROMINTEN    V_BLKWREEPROMINTEN(1U)
+
+#define S_BLKRDEEPROMINTEN    16
+#define V_BLKRDEEPROMINTEN(x) ((x) << S_BLKRDEEPROMINTEN)
+#define F_BLKRDEEPROMINTEN    V_BLKRDEEPROMINTEN(1U)
+
+#define S_SGLWREEPROMINTEN    15
+#define V_SGLWREEPROMINTEN(x) ((x) << S_SGLWREEPROMINTEN)
+#define F_SGLWREEPROMINTEN    V_SGLWREEPROMINTEN(1U)
+
+#define S_SGLRDEEPROMINTEN    14
+#define V_SGLRDEEPROMINTEN(x) ((x) << S_SGLRDEEPROMINTEN)
+#define F_SGLRDEEPROMINTEN    V_SGLRDEEPROMINTEN(1U)
+
+#define S_BLKWRFLASHINTEN    13
+#define V_BLKWRFLASHINTEN(x) ((x) << S_BLKWRFLASHINTEN)
+#define F_BLKWRFLASHINTEN    V_BLKWRFLASHINTEN(1U)
+
+#define S_BLKRDFLASHINTEN    12
+#define V_BLKRDFLASHINTEN(x) ((x) << S_BLKRDFLASHINTEN)
+#define F_BLKRDFLASHINTEN    V_BLKRDFLASHINTEN(1U)
+
+#define S_SGLWRFLASHINTEN    11
+#define V_SGLWRFLASHINTEN(x) ((x) << S_SGLWRFLASHINTEN)
+#define F_SGLWRFLASHINTEN    V_SGLWRFLASHINTEN(1U)
+
+#define S_SGLRDFLASHINTEN    10
+#define V_SGLRDFLASHINTEN(x) ((x) << S_SGLRDFLASHINTEN)
+#define F_SGLRDFLASHINTEN    V_SGLRDFLASHINTEN(1U)
+
+#define S_BLKWRBOOTINTEN    9
+#define V_BLKWRBOOTINTEN(x) ((x) << S_BLKWRBOOTINTEN)
+#define F_BLKWRBOOTINTEN    V_BLKWRBOOTINTEN(1U)
+
+#define S_BLKRDBOOTINTEN    8
+#define V_BLKRDBOOTINTEN(x) ((x) << S_BLKRDBOOTINTEN)
+#define F_BLKRDBOOTINTEN    V_BLKRDBOOTINTEN(1U)
+
+#define S_SGLWRBOOTINTEN    7
+#define V_SGLWRBOOTINTEN(x) ((x) << S_SGLWRBOOTINTEN)
+#define F_SGLWRBOOTINTEN    V_SGLWRBOOTINTEN(1U)
+
+#define S_SGLRDBOOTINTEN    6
+#define V_SGLRDBOOTINTEN(x) ((x) << S_SGLRDBOOTINTEN)
+#define F_SGLRDBOOTINTEN    V_SGLRDBOOTINTEN(1U)
+
+#define S_ILLWRBEINTEN    5
+#define V_ILLWRBEINTEN(x) ((x) << S_ILLWRBEINTEN)
+#define F_ILLWRBEINTEN    V_ILLWRBEINTEN(1U)
+
+#define S_ILLRDBEINTEN    4
+#define V_ILLRDBEINTEN(x) ((x) << S_ILLRDBEINTEN)
+#define F_ILLRDBEINTEN    V_ILLRDBEINTEN(1U)
+
+#define S_ILLRDINTEN    3
+#define V_ILLRDINTEN(x) ((x) << S_ILLRDINTEN)
+#define F_ILLRDINTEN    V_ILLRDINTEN(1U)
+
+#define S_ILLWRINTEN    2
+#define V_ILLWRINTEN(x) ((x) << S_ILLWRINTEN)
+#define F_ILLWRINTEN    V_ILLWRINTEN(1U)
+
+#define S_ILLTRANSINTEN    1
+#define V_ILLTRANSINTEN(x) ((x) << S_ILLTRANSINTEN)
+#define F_ILLTRANSINTEN    V_ILLTRANSINTEN(1U)
+
+#define S_RSVDSPACEINTEN    0
+#define V_RSVDSPACEINTEN(x) ((x) << S_RSVDSPACEINTEN)
+#define F_RSVDSPACEINTEN    V_RSVDSPACEINTEN(1U)
+
+#define A_CIM_HOST_UPACC_INT_CAUSE 0x7b34
+
+#define S_EEPROMWRINT    30
+#define V_EEPROMWRINT(x) ((x) << S_EEPROMWRINT)
+#define F_EEPROMWRINT    V_EEPROMWRINT(1U)
+
+#define S_TIMEOUTMAINT    29
+#define V_TIMEOUTMAINT(x) ((x) << S_TIMEOUTMAINT)
+#define F_TIMEOUTMAINT    V_TIMEOUTMAINT(1U)
+
+#define S_TIMEOUTINT    28
+#define V_TIMEOUTINT(x) ((x) << S_TIMEOUTINT)
+#define F_TIMEOUTINT    V_TIMEOUTINT(1U)
+
+#define S_RSPOVRLOOKUPINT    27
+#define V_RSPOVRLOOKUPINT(x) ((x) << S_RSPOVRLOOKUPINT)
+#define F_RSPOVRLOOKUPINT    V_RSPOVRLOOKUPINT(1U)
+
+#define S_REQOVRLOOKUPINT    26
+#define V_REQOVRLOOKUPINT(x) ((x) << S_REQOVRLOOKUPINT)
+#define F_REQOVRLOOKUPINT    V_REQOVRLOOKUPINT(1U)
+
+#define S_BLKWRPLINT    25
+#define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT)
+#define F_BLKWRPLINT    V_BLKWRPLINT(1U)
+
+#define S_BLKRDPLINT    24
+#define V_BLKRDPLINT(x) ((x) << S_BLKRDPLINT)
+#define F_BLKRDPLINT    V_BLKRDPLINT(1U)
+
+#define S_SGLWRPLINT    23
+#define V_SGLWRPLINT(x) ((x) << S_SGLWRPLINT)
+#define F_SGLWRPLINT    V_SGLWRPLINT(1U)
+
+#define S_SGLRDPLINT    22
+#define V_SGLRDPLINT(x) ((x) << S_SGLRDPLINT)
+#define F_SGLRDPLINT    V_SGLRDPLINT(1U)
+
+#define S_BLKWRCTLINT    21
+#define V_BLKWRCTLINT(x) ((x) << S_BLKWRCTLINT)
+#define F_BLKWRCTLINT    V_BLKWRCTLINT(1U)
+
+#define S_BLKRDCTLINT    20
+#define V_BLKRDCTLINT(x) ((x) << S_BLKRDCTLINT)
+#define F_BLKRDCTLINT    V_BLKRDCTLINT(1U)
+
+#define S_SGLWRCTLINT    19
+#define V_SGLWRCTLINT(x) ((x) << S_SGLWRCTLINT)
+#define F_SGLWRCTLINT    V_SGLWRCTLINT(1U)
+
+#define S_SGLRDCTLINT    18
+#define V_SGLRDCTLINT(x) ((x) << S_SGLRDCTLINT)
+#define F_SGLRDCTLINT    V_SGLRDCTLINT(1U)
+
+#define S_BLKWREEPROMINT    17
+#define V_BLKWREEPROMINT(x) ((x) << S_BLKWREEPROMINT)
+#define F_BLKWREEPROMINT    V_BLKWREEPROMINT(1U)
+
+#define S_BLKRDEEPROMINT    16
+#define V_BLKRDEEPROMINT(x) ((x) << S_BLKRDEEPROMINT)
+#define F_BLKRDEEPROMINT    V_BLKRDEEPROMINT(1U)
+
+#define S_SGLWREEPROMINT    15
+#define V_SGLWREEPROMINT(x) ((x) << S_SGLWREEPROMINT)
+#define F_SGLWREEPROMINT    V_SGLWREEPROMINT(1U)
+
+#define S_SGLRDEEPROMINT    14
+#define V_SGLRDEEPROMINT(x) ((x) << S_SGLRDEEPROMINT)
+#define F_SGLRDEEPROMINT    V_SGLRDEEPROMINT(1U)
+
+#define S_BLKWRFLASHINT    13
+#define V_BLKWRFLASHINT(x) ((x) << S_BLKWRFLASHINT)
+#define F_BLKWRFLASHINT    V_BLKWRFLASHINT(1U)
+
+#define S_BLKRDFLASHINT    12
+#define V_BLKRDFLASHINT(x) ((x) << S_BLKRDFLASHINT)
+#define F_BLKRDFLASHINT    V_BLKRDFLASHINT(1U)
+
+#define S_SGLWRFLASHINT    11
+#define V_SGLWRFLASHINT(x) ((x) << S_SGLWRFLASHINT)
+#define F_SGLWRFLASHINT    V_SGLWRFLASHINT(1U)
+
+#define S_SGLRDFLASHINT    10
+#define V_SGLRDFLASHINT(x) ((x) << S_SGLRDFLASHINT)
+#define F_SGLRDFLASHINT    V_SGLRDFLASHINT(1U)
+
+#define S_BLKWRBOOTINT    9
+#define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT)
+#define F_BLKWRBOOTINT    V_BLKWRBOOTINT(1U)
+
+#define S_BLKRDBOOTINT    8
+#define V_BLKRDBOOTINT(x) ((x) << S_BLKRDBOOTINT)
+#define F_BLKRDBOOTINT    V_BLKRDBOOTINT(1U)
+
+#define S_SGLWRBOOTINT    7
+#define V_SGLWRBOOTINT(x) ((x) << S_SGLWRBOOTINT)
+#define F_SGLWRBOOTINT    V_SGLWRBOOTINT(1U)
+
+#define S_SGLRDBOOTINT    6
+#define V_SGLRDBOOTINT(x) ((x) << S_SGLRDBOOTINT)
+#define F_SGLRDBOOTINT    V_SGLRDBOOTINT(1U)
+
+#define S_ILLWRBEINT    5
+#define V_ILLWRBEINT(x) ((x) << S_ILLWRBEINT)
+#define F_ILLWRBEINT    V_ILLWRBEINT(1U)
+
+#define S_ILLRDBEINT    4
+#define V_ILLRDBEINT(x) ((x) << S_ILLRDBEINT)
+#define F_ILLRDBEINT    V_ILLRDBEINT(1U)
+
+#define S_ILLRDINT    3
+#define V_ILLRDINT(x) ((x) << S_ILLRDINT)
+#define F_ILLRDINT    V_ILLRDINT(1U)
+
+#define S_ILLWRINT    2
+#define V_ILLWRINT(x) ((x) << S_ILLWRINT)
+#define F_ILLWRINT    V_ILLWRINT(1U)
+
+#define S_ILLTRANSINT    1
+#define V_ILLTRANSINT(x) ((x) << S_ILLTRANSINT)
+#define F_ILLTRANSINT    V_ILLTRANSINT(1U)
+
+#define S_RSVDSPACEINT    0
+#define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT)
+#define F_RSVDSPACEINT    V_RSVDSPACEINT(1U)
+
+#define A_CIM_UP_INT_ENABLE 0x7b38
+
+#define S_MSTPLINTEN    4
+#define V_MSTPLINTEN(x) ((x) << S_MSTPLINTEN)
+#define F_MSTPLINTEN    V_MSTPLINTEN(1U)
+
+#define A_CIM_UP_INT_CAUSE 0x7b3c
+
+#define S_MSTPLINT    4
+#define V_MSTPLINT(x) ((x) << S_MSTPLINT)
+#define F_MSTPLINT    V_MSTPLINT(1U)
+
+#define A_CIM_UP_ACC_INT_ENABLE 0x7b40
+#define A_CIM_UP_ACC_INT_CAUSE 0x7b44
+#define A_CIM_QUEUE_CONFIG_REF 0x7b48
+
+#define S_OBQSELECT    4
+#define V_OBQSELECT(x) ((x) << S_OBQSELECT)
+#define F_OBQSELECT    V_OBQSELECT(1U)
+
+#define S_IBQSELECT    3
+#define V_IBQSELECT(x) ((x) << S_IBQSELECT)
+#define F_IBQSELECT    V_IBQSELECT(1U)
+
+#define S_QUENUMSELECT    0
+#define M_QUENUMSELECT    0x7U
+#define V_QUENUMSELECT(x) ((x) << S_QUENUMSELECT)
+#define G_QUENUMSELECT(x) (((x) >> S_QUENUMSELECT) & M_QUENUMSELECT)
+
+#define A_CIM_QUEUE_CONFIG_CTRL 0x7b4c
+
+#define S_CIMQSIZE    24
+#define M_CIMQSIZE    0x3fU
+#define V_CIMQSIZE(x) ((x) << S_CIMQSIZE)
+#define G_CIMQSIZE(x) (((x) >> S_CIMQSIZE) & M_CIMQSIZE)
+
+#define S_CIMQBASE    16
+#define M_CIMQBASE    0x3fU
+#define V_CIMQBASE(x) ((x) << S_CIMQBASE)
+#define G_CIMQBASE(x) (((x) >> S_CIMQBASE) & M_CIMQBASE)
+
+#define S_CIMQDBG8BEN    9
+#define V_CIMQDBG8BEN(x) ((x) << S_CIMQDBG8BEN)
+#define F_CIMQDBG8BEN    V_CIMQDBG8BEN(1U)
+
+#define S_QUEFULLTHRSH    0
+#define M_QUEFULLTHRSH    0x1ffU
+#define V_QUEFULLTHRSH(x) ((x) << S_QUEFULLTHRSH)
+#define G_QUEFULLTHRSH(x) (((x) >> S_QUEFULLTHRSH) & M_QUEFULLTHRSH)
+
+#define A_CIM_HOST_ACC_CTRL 0x7b50
+
+#define S_HOSTBUSY    17
+#define V_HOSTBUSY(x) ((x) << S_HOSTBUSY)
+#define F_HOSTBUSY    V_HOSTBUSY(1U)
+
+#define S_HOSTWRITE    16
+#define V_HOSTWRITE(x) ((x) << S_HOSTWRITE)
+#define F_HOSTWRITE    V_HOSTWRITE(1U)
+
+#define S_HOSTADDR    0
+#define M_HOSTADDR    0xffffU
+#define V_HOSTADDR(x) ((x) << S_HOSTADDR)
+#define G_HOSTADDR(x) (((x) >> S_HOSTADDR) & M_HOSTADDR)
+
+#define A_CIM_HOST_ACC_DATA 0x7b54
+#define A_CIM_CDEBUGDATA 0x7b58
+
+#define S_CDEBUGDATAH    16
+#define M_CDEBUGDATAH    0xffffU
+#define V_CDEBUGDATAH(x) ((x) << S_CDEBUGDATAH)
+#define G_CDEBUGDATAH(x) (((x) >> S_CDEBUGDATAH) & M_CDEBUGDATAH)
+
+#define S_CDEBUGDATAL    0
+#define M_CDEBUGDATAL    0xffffU
+#define V_CDEBUGDATAL(x) ((x) << S_CDEBUGDATAL)
+#define G_CDEBUGDATAL(x) (((x) >> S_CDEBUGDATAL) & M_CDEBUGDATAL)
+
+#define A_CIM_IBQ_DBG_CFG 0x7b60
+
+#define S_IBQDBGADDR    16
+#define M_IBQDBGADDR    0xfffU
+#define V_IBQDBGADDR(x) ((x) << S_IBQDBGADDR)
+#define G_IBQDBGADDR(x) (((x) >> S_IBQDBGADDR) & M_IBQDBGADDR)
+
+#define S_IBQDBGWR    2
+#define V_IBQDBGWR(x) ((x) << S_IBQDBGWR)
+#define F_IBQDBGWR    V_IBQDBGWR(1U)
+
+#define S_IBQDBGBUSY    1
+#define V_IBQDBGBUSY(x) ((x) << S_IBQDBGBUSY)
+#define F_IBQDBGBUSY    V_IBQDBGBUSY(1U)
+
+#define S_IBQDBGEN    0
+#define V_IBQDBGEN(x) ((x) << S_IBQDBGEN)
+#define F_IBQDBGEN    V_IBQDBGEN(1U)
+
+#define A_CIM_OBQ_DBG_CFG 0x7b64
+
+#define S_OBQDBGADDR    16
+#define M_OBQDBGADDR    0xfffU
+#define V_OBQDBGADDR(x) ((x) << S_OBQDBGADDR)
+#define G_OBQDBGADDR(x) (((x) >> S_OBQDBGADDR) & M_OBQDBGADDR)
+
+#define S_OBQDBGWR    2
+#define V_OBQDBGWR(x) ((x) << S_OBQDBGWR)
+#define F_OBQDBGWR    V_OBQDBGWR(1U)
+
+#define S_OBQDBGBUSY    1
+#define V_OBQDBGBUSY(x) ((x) << S_OBQDBGBUSY)
+#define F_OBQDBGBUSY    V_OBQDBGBUSY(1U)
+
+#define S_OBQDBGEN    0
+#define V_OBQDBGEN(x) ((x) << S_OBQDBGEN)
+#define F_OBQDBGEN    V_OBQDBGEN(1U)
+
+#define A_CIM_IBQ_DBG_DATA 0x7b68
+#define A_CIM_OBQ_DBG_DATA 0x7b6c
+#define A_CIM_DEBUGCFG 0x7b70
+
+#define S_POLADBGRDPTR    23
+#define M_POLADBGRDPTR    0x1ffU
+#define V_POLADBGRDPTR(x) ((x) << S_POLADBGRDPTR)
+#define G_POLADBGRDPTR(x) (((x) >> S_POLADBGRDPTR) & M_POLADBGRDPTR)
+
+#define S_PILADBGRDPTR    14
+#define M_PILADBGRDPTR    0x1ffU
+#define V_PILADBGRDPTR(x) ((x) << S_PILADBGRDPTR)
+#define G_PILADBGRDPTR(x) (((x) >> S_PILADBGRDPTR) & M_PILADBGRDPTR)
+
+#define S_LAMASKTRIG    13
+#define V_LAMASKTRIG(x) ((x) << S_LAMASKTRIG)
+#define F_LAMASKTRIG    V_LAMASKTRIG(1U)
+
+#define S_LADBGEN    12
+#define V_LADBGEN(x) ((x) << S_LADBGEN)
+#define F_LADBGEN    V_LADBGEN(1U)
+
+#define S_LAFILLONCE    11
+#define V_LAFILLONCE(x) ((x) << S_LAFILLONCE)
+#define F_LAFILLONCE    V_LAFILLONCE(1U)
+
+#define S_LAMASKSTOP    10
+#define V_LAMASKSTOP(x) ((x) << S_LAMASKSTOP)
+#define F_LAMASKSTOP    V_LAMASKSTOP(1U)
+
+#define S_DEBUGSELH    5
+#define M_DEBUGSELH    0x1fU
+#define V_DEBUGSELH(x) ((x) << S_DEBUGSELH)
+#define G_DEBUGSELH(x) (((x) >> S_DEBUGSELH) & M_DEBUGSELH)
+
+#define S_DEBUGSELL    0
+#define M_DEBUGSELL    0x1fU
+#define V_DEBUGSELL(x) ((x) << S_DEBUGSELL)
+#define G_DEBUGSELL(x) (((x) >> S_DEBUGSELL) & M_DEBUGSELL)
+
+#define A_CIM_DEBUGSTS 0x7b74
+
+#define S_LARESET    31
+#define V_LARESET(x) ((x) << S_LARESET)
+#define F_LARESET    V_LARESET(1U)
+
+#define S_POLADBGWRPTR    16
+#define M_POLADBGWRPTR    0x1ffU
+#define V_POLADBGWRPTR(x) ((x) << S_POLADBGWRPTR)
+#define G_POLADBGWRPTR(x) (((x) >> S_POLADBGWRPTR) & M_POLADBGWRPTR)
+
+#define S_PILADBGWRPTR    0
+#define M_PILADBGWRPTR    0x1ffU
+#define V_PILADBGWRPTR(x) ((x) << S_PILADBGWRPTR)
+#define G_PILADBGWRPTR(x) (((x) >> S_PILADBGWRPTR) & M_PILADBGWRPTR)
+
+#define A_CIM_PO_LA_DEBUGDATA 0x7b78
+#define A_CIM_PI_LA_DEBUGDATA 0x7b7c
+#define A_CIM_PO_LA_MADEBUGDATA 0x7b80
+#define A_CIM_PI_LA_MADEBUGDATA 0x7b84
+#define A_CIM_PO_LA_PIFSMDEBUGDATA 0x7b8c
+#define A_CIM_MEM_ZONE0_VA 0x7b90
+
+#define S_MEM_ZONE_VA    4
+#define M_MEM_ZONE_VA    0xfffffffU
+#define V_MEM_ZONE_VA(x) ((x) << S_MEM_ZONE_VA)
+#define G_MEM_ZONE_VA(x) (((x) >> S_MEM_ZONE_VA) & M_MEM_ZONE_VA)
+
+#define A_CIM_MEM_ZONE0_BA 0x7b94
+
+#define S_MEM_ZONE_BA    6
+#define M_MEM_ZONE_BA    0x3ffffffU
+#define V_MEM_ZONE_BA(x) ((x) << S_MEM_ZONE_BA)
+#define G_MEM_ZONE_BA(x) (((x) >> S_MEM_ZONE_BA) & M_MEM_ZONE_BA)
+
+#define S_PBT_ENABLE    5
+#define V_PBT_ENABLE(x) ((x) << S_PBT_ENABLE)
+#define F_PBT_ENABLE    V_PBT_ENABLE(1U)
+
+#define S_ZONE_DST    0
+#define M_ZONE_DST    0x3U
+#define V_ZONE_DST(x) ((x) << S_ZONE_DST)
+#define G_ZONE_DST(x) (((x) >> S_ZONE_DST) & M_ZONE_DST)
+
+#define A_CIM_MEM_ZONE0_LEN 0x7b98
+
+#define S_MEM_ZONE_LEN    4
+#define M_MEM_ZONE_LEN    0xfffffffU
+#define V_MEM_ZONE_LEN(x) ((x) << S_MEM_ZONE_LEN)
+#define G_MEM_ZONE_LEN(x) (((x) >> S_MEM_ZONE_LEN) & M_MEM_ZONE_LEN)
+
+#define A_CIM_MEM_ZONE1_VA 0x7b9c
+#define A_CIM_MEM_ZONE1_BA 0x7ba0
+#define A_CIM_MEM_ZONE1_LEN 0x7ba4
+#define A_CIM_MEM_ZONE2_VA 0x7ba8
+#define A_CIM_MEM_ZONE2_BA 0x7bac
+#define A_CIM_MEM_ZONE2_LEN 0x7bb0
+#define A_CIM_MEM_ZONE3_VA 0x7bb4
+#define A_CIM_MEM_ZONE3_BA 0x7bb8
+#define A_CIM_MEM_ZONE3_LEN 0x7bbc
+#define A_CIM_MEM_ZONE4_VA 0x7bc0
+#define A_CIM_MEM_ZONE4_BA 0x7bc4
+#define A_CIM_MEM_ZONE4_LEN 0x7bc8
+#define A_CIM_MEM_ZONE5_VA 0x7bcc
+#define A_CIM_MEM_ZONE5_BA 0x7bd0
+#define A_CIM_MEM_ZONE5_LEN 0x7bd4
+#define A_CIM_MEM_ZONE6_VA 0x7bd8
+#define A_CIM_MEM_ZONE6_BA 0x7bdc
+#define A_CIM_MEM_ZONE6_LEN 0x7be0
+#define A_CIM_MEM_ZONE7_VA 0x7be4
+#define A_CIM_MEM_ZONE7_BA 0x7be8
+#define A_CIM_MEM_ZONE7_LEN 0x7bec
+#define A_CIM_BOOT_LEN 0x7bf0
+
+#define S_BOOTLEN    4
+#define M_BOOTLEN    0xfffffffU
+#define V_BOOTLEN(x) ((x) << S_BOOTLEN)
+#define G_BOOTLEN(x) (((x) >> S_BOOTLEN) & M_BOOTLEN)
+
+#define A_CIM_GLB_TIMER_CTL 0x7bf4
+
+#define S_TIMER1EN    4
+#define V_TIMER1EN(x) ((x) << S_TIMER1EN)
+#define F_TIMER1EN    V_TIMER1EN(1U)
+
+#define S_TIMER0EN    3
+#define V_TIMER0EN(x) ((x) << S_TIMER0EN)
+#define F_TIMER0EN    V_TIMER0EN(1U)
+
+#define S_TIMEREN    1
+#define V_TIMEREN(x) ((x) << S_TIMEREN)
+#define F_TIMEREN    V_TIMEREN(1U)
+
+#define A_CIM_GLB_TIMER 0x7bf8
+#define A_CIM_GLB_TIMER_TICK 0x7bfc
+
+#define S_GLBLTTICK    0
+#define M_GLBLTTICK    0xffffU
+#define V_GLBLTTICK(x) ((x) << S_GLBLTTICK)
+#define G_GLBLTTICK(x) (((x) >> S_GLBLTTICK) & M_GLBLTTICK)
+
+#define A_CIM_TIMER0 0x7c00
+#define A_CIM_TIMER1 0x7c04
+#define A_CIM_DEBUG_ADDR_TIMEOUT 0x7c08
+
+#define S_DADDRTIMEOUT    2
+#define M_DADDRTIMEOUT    0x3fffffffU
+#define V_DADDRTIMEOUT(x) ((x) << S_DADDRTIMEOUT)
+#define G_DADDRTIMEOUT(x) (((x) >> S_DADDRTIMEOUT) & M_DADDRTIMEOUT)
+
+#define A_CIM_DEBUG_ADDR_ILLEGAL 0x7c0c
+
+#define S_DADDRILLEGAL    2
+#define M_DADDRILLEGAL    0x3fffffffU
+#define V_DADDRILLEGAL(x) ((x) << S_DADDRILLEGAL)
+#define G_DADDRILLEGAL(x) (((x) >> S_DADDRILLEGAL) & M_DADDRILLEGAL)
+
+#define A_CIM_DEBUG_PIF_CAUSE_MASK 0x7c10
+
+#define S_DPIFHOSTMASK    0
+#define M_DPIFHOSTMASK    0x1fffffU
+#define V_DPIFHOSTMASK(x) ((x) << S_DPIFHOSTMASK)
+#define G_DPIFHOSTMASK(x) (((x) >> S_DPIFHOSTMASK) & M_DPIFHOSTMASK)
+
+#define S_T5_DPIFHOSTMASK    0
+#define M_T5_DPIFHOSTMASK    0x1fffffffU
+#define V_T5_DPIFHOSTMASK(x) ((x) << S_T5_DPIFHOSTMASK)
+#define G_T5_DPIFHOSTMASK(x) (((x) >> S_T5_DPIFHOSTMASK) & M_T5_DPIFHOSTMASK)
+
+#define A_CIM_DEBUG_PIF_UPACC_CAUSE_MASK 0x7c14
+
+#define S_DPIFHUPAMASK    0
+#define M_DPIFHUPAMASK    0x7fffffffU
+#define V_DPIFHUPAMASK(x) ((x) << S_DPIFHUPAMASK)
+#define G_DPIFHUPAMASK(x) (((x) >> S_DPIFHUPAMASK) & M_DPIFHUPAMASK)
+
+#define A_CIM_DEBUG_UP_CAUSE_MASK 0x7c18
+
+#define S_DUPMASK    0
+#define M_DUPMASK    0x1fffffU
+#define V_DUPMASK(x) ((x) << S_DUPMASK)
+#define G_DUPMASK(x) (((x) >> S_DUPMASK) & M_DUPMASK)
+
+#define S_T5_DUPMASK    0
+#define M_T5_DUPMASK    0x1fffffffU
+#define V_T5_DUPMASK(x) ((x) << S_T5_DUPMASK)
+#define G_T5_DUPMASK(x) (((x) >> S_T5_DUPMASK) & M_T5_DUPMASK)
+
+#define A_CIM_DEBUG_UP_UPACC_CAUSE_MASK 0x7c1c
+
+#define S_DUPUACCMASK    0
+#define M_DUPUACCMASK    0x7fffffffU
+#define V_DUPUACCMASK(x) ((x) << S_DUPUACCMASK)
+#define G_DUPUACCMASK(x) (((x) >> S_DUPUACCMASK) & M_DUPUACCMASK)
+
+#define A_CIM_PERR_INJECT 0x7c20
+#define A_CIM_PERR_ENABLE 0x7c24
+
+#define S_PERREN    0
+#define M_PERREN    0x1fffffU
+#define V_PERREN(x) ((x) << S_PERREN)
+#define G_PERREN(x) (((x) >> S_PERREN) & M_PERREN)
+
+#define S_T5_PERREN    0
+#define M_T5_PERREN    0x1fffffffU
+#define V_T5_PERREN(x) ((x) << S_T5_PERREN)
+#define G_T5_PERREN(x) (((x) >> S_T5_PERREN) & M_T5_PERREN)
+
+#define A_CIM_EEPROM_BUSY_BIT 0x7c28
+
+#define S_EEPROMBUSY    0
+#define V_EEPROMBUSY(x) ((x) << S_EEPROMBUSY)
+#define F_EEPROMBUSY    V_EEPROMBUSY(1U)
+
+#define A_CIM_MA_TIMER_EN 0x7c2c
+
+#define S_MA_TIMER_ENABLE    0
+#define V_MA_TIMER_ENABLE(x) ((x) << S_MA_TIMER_ENABLE)
+#define F_MA_TIMER_ENABLE    V_MA_TIMER_ENABLE(1U)
+
+#define A_CIM_UP_PO_SINGLE_OUTSTANDING 0x7c30
+
+#define S_UP_PO_SINGLE_OUTSTANDING    0
+#define V_UP_PO_SINGLE_OUTSTANDING(x) ((x) << S_UP_PO_SINGLE_OUTSTANDING)
+#define F_UP_PO_SINGLE_OUTSTANDING    V_UP_PO_SINGLE_OUTSTANDING(1U)
+
+#define A_CIM_CIM_DEBUG_SPARE 0x7c34
+#define A_CIM_UP_OPERATION_FREQ 0x7c38
+#define A_CIM_CIM_IBQ_ERR_CODE 0x7c3c
+
+#define S_CIM_ULP_TX_PKT_ERR_CODE    16
+#define M_CIM_ULP_TX_PKT_ERR_CODE    0xffU
+#define V_CIM_ULP_TX_PKT_ERR_CODE(x) ((x) << S_CIM_ULP_TX_PKT_ERR_CODE)
+#define G_CIM_ULP_TX_PKT_ERR_CODE(x) (((x) >> S_CIM_ULP_TX_PKT_ERR_CODE) & M_CIM_ULP_TX_PKT_ERR_CODE)
+
+#define S_CIM_SGE1_PKT_ERR_CODE    8
+#define M_CIM_SGE1_PKT_ERR_CODE    0xffU
+#define V_CIM_SGE1_PKT_ERR_CODE(x) ((x) << S_CIM_SGE1_PKT_ERR_CODE)
+#define G_CIM_SGE1_PKT_ERR_CODE(x) (((x) >> S_CIM_SGE1_PKT_ERR_CODE) & M_CIM_SGE1_PKT_ERR_CODE)
+
+#define S_CIM_SGE0_PKT_ERR_CODE    0
+#define M_CIM_SGE0_PKT_ERR_CODE    0xffU
+#define V_CIM_SGE0_PKT_ERR_CODE(x) ((x) << S_CIM_SGE0_PKT_ERR_CODE)
+#define G_CIM_SGE0_PKT_ERR_CODE(x) (((x) >> S_CIM_SGE0_PKT_ERR_CODE) & M_CIM_SGE0_PKT_ERR_CODE)
+
+#define A_CIM_IBQ_DBG_WAIT_COUNTER 0x7c40
+#define A_CIM_PIO_UP_MST_CFG_SEL 0x7c44
+
+#define S_PIO_UP_MST_CFG_SEL    0
+#define V_PIO_UP_MST_CFG_SEL(x) ((x) << S_PIO_UP_MST_CFG_SEL)
+#define F_PIO_UP_MST_CFG_SEL    V_PIO_UP_MST_CFG_SEL(1U)
+
+#define A_CIM_CGEN 0x7c48
+
+#define S_TSCH_CGEN    0
+#define V_TSCH_CGEN(x) ((x) << S_TSCH_CGEN)
+#define F_TSCH_CGEN    V_TSCH_CGEN(1U)
+
+#define A_CIM_QUEUE_FEATURE_DISABLE 0x7c4c
+
+#define S_OBQ_THROUTTLE_ON_EOP    4
+#define V_OBQ_THROUTTLE_ON_EOP(x) ((x) << S_OBQ_THROUTTLE_ON_EOP)
+#define F_OBQ_THROUTTLE_ON_EOP    V_OBQ_THROUTTLE_ON_EOP(1U)
+
+#define S_OBQ_READ_CTL_PERF_MODE_DISABLE    3
+#define V_OBQ_READ_CTL_PERF_MODE_DISABLE(x) ((x) << S_OBQ_READ_CTL_PERF_MODE_DISABLE)
+#define F_OBQ_READ_CTL_PERF_MODE_DISABLE    V_OBQ_READ_CTL_PERF_MODE_DISABLE(1U)
+
+#define S_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE    2
+#define V_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE(x) ((x) << S_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE)
+#define F_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE    V_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE(1U)
+
+#define S_IBQ_RRA_DSBL    1
+#define V_IBQ_RRA_DSBL(x) ((x) << S_IBQ_RRA_DSBL)
+#define F_IBQ_RRA_DSBL    V_IBQ_RRA_DSBL(1U)
+
+#define S_IBQ_SKID_FIFO_EOP_FLSH_DSBL    0
+#define V_IBQ_SKID_FIFO_EOP_FLSH_DSBL(x) ((x) << S_IBQ_SKID_FIFO_EOP_FLSH_DSBL)
+#define F_IBQ_SKID_FIFO_EOP_FLSH_DSBL    V_IBQ_SKID_FIFO_EOP_FLSH_DSBL(1U)
+
+#define A_CIM_CGEN_GLOBAL 0x7c50
+
+#define S_CGEN_GLOBAL    0
+#define V_CGEN_GLOBAL(x) ((x) << S_CGEN_GLOBAL)
+#define F_CGEN_GLOBAL    V_CGEN_GLOBAL(1U)
+
+#define A_CIM_DPSLP_EN 0x7c54
+
+#define S_PIFDBGLA_DPSLP_EN    0
+#define V_PIFDBGLA_DPSLP_EN(x) ((x) << S_PIFDBGLA_DPSLP_EN)
+#define F_PIFDBGLA_DPSLP_EN    V_PIFDBGLA_DPSLP_EN(1U)
+
+/* registers for module TP */
+#define TP_BASE_ADDR 0x7d00
+
+#define A_TP_IN_CONFIG 0x7d00
+
+#define S_TCPOPTPARSERDISCH3    27
+#define V_TCPOPTPARSERDISCH3(x) ((x) << S_TCPOPTPARSERDISCH3)
+#define F_TCPOPTPARSERDISCH3    V_TCPOPTPARSERDISCH3(1U)
+
+#define S_TCPOPTPARSERDISCH2    26
+#define V_TCPOPTPARSERDISCH2(x) ((x) << S_TCPOPTPARSERDISCH2)
+#define F_TCPOPTPARSERDISCH2    V_TCPOPTPARSERDISCH2(1U)
+
+#define S_TCPOPTPARSERDISCH1    25
+#define V_TCPOPTPARSERDISCH1(x) ((x) << S_TCPOPTPARSERDISCH1)
+#define F_TCPOPTPARSERDISCH1    V_TCPOPTPARSERDISCH1(1U)
+
+#define S_TCPOPTPARSERDISCH0    24
+#define V_TCPOPTPARSERDISCH0(x) ((x) << S_TCPOPTPARSERDISCH0)
+#define F_TCPOPTPARSERDISCH0    V_TCPOPTPARSERDISCH0(1U)
+
+#define S_CRCPASSPRT3    23
+#define V_CRCPASSPRT3(x) ((x) << S_CRCPASSPRT3)
+#define F_CRCPASSPRT3    V_CRCPASSPRT3(1U)
+
+#define S_CRCPASSPRT2    22
+#define V_CRCPASSPRT2(x) ((x) << S_CRCPASSPRT2)
+#define F_CRCPASSPRT2    V_CRCPASSPRT2(1U)
+
+#define S_CRCPASSPRT1    21
+#define V_CRCPASSPRT1(x) ((x) << S_CRCPASSPRT1)
+#define F_CRCPASSPRT1    V_CRCPASSPRT1(1U)
+
+#define S_CRCPASSPRT0    20
+#define V_CRCPASSPRT0(x) ((x) << S_CRCPASSPRT0)
+#define F_CRCPASSPRT0    V_CRCPASSPRT0(1U)
+
+#define S_VEPAMODE    19
+#define V_VEPAMODE(x) ((x) << S_VEPAMODE)
+#define F_VEPAMODE    V_VEPAMODE(1U)
+
+#define S_FIPUPEN    18
+#define V_FIPUPEN(x) ((x) << S_FIPUPEN)
+#define F_FIPUPEN    V_FIPUPEN(1U)
+
+#define S_FCOEUPEN    17
+#define V_FCOEUPEN(x) ((x) << S_FCOEUPEN)
+#define F_FCOEUPEN    V_FCOEUPEN(1U)
+
+#define S_FCOEENABLE    16
+#define V_FCOEENABLE(x) ((x) << S_FCOEENABLE)
+#define F_FCOEENABLE    V_FCOEENABLE(1U)
+
+#define S_IPV6ENABLE    15
+#define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE)
+#define F_IPV6ENABLE    V_IPV6ENABLE(1U)
+
+#define S_NICMODE    14
+#define V_NICMODE(x) ((x) << S_NICMODE)
+#define F_NICMODE    V_NICMODE(1U)
+
+#define S_ECHECKSUMCHECKTCP    13
+#define V_ECHECKSUMCHECKTCP(x) ((x) << S_ECHECKSUMCHECKTCP)
+#define F_ECHECKSUMCHECKTCP    V_ECHECKSUMCHECKTCP(1U)
+
+#define S_ECHECKSUMCHECKIP    12
+#define V_ECHECKSUMCHECKIP(x) ((x) << S_ECHECKSUMCHECKIP)
+#define F_ECHECKSUMCHECKIP    V_ECHECKSUMCHECKIP(1U)
+
+#define S_EREPORTUDPHDRLEN    11
+#define V_EREPORTUDPHDRLEN(x) ((x) << S_EREPORTUDPHDRLEN)
+#define F_EREPORTUDPHDRLEN    V_EREPORTUDPHDRLEN(1U)
+
+#define S_IN_ECPL    10
+#define V_IN_ECPL(x) ((x) << S_IN_ECPL)
+#define F_IN_ECPL    V_IN_ECPL(1U)
+
+#define S_VNTAGENABLE    9
+#define V_VNTAGENABLE(x) ((x) << S_VNTAGENABLE)
+#define F_VNTAGENABLE    V_VNTAGENABLE(1U)
+
+#define S_IN_EETH    8
+#define V_IN_EETH(x) ((x) << S_IN_EETH)
+#define F_IN_EETH    V_IN_EETH(1U)
+
+#define S_CCHECKSUMCHECKTCP    6
+#define V_CCHECKSUMCHECKTCP(x) ((x) << S_CCHECKSUMCHECKTCP)
+#define F_CCHECKSUMCHECKTCP    V_CCHECKSUMCHECKTCP(1U)
+
+#define S_CCHECKSUMCHECKIP    5
+#define V_CCHECKSUMCHECKIP(x) ((x) << S_CCHECKSUMCHECKIP)
+#define F_CCHECKSUMCHECKIP    V_CCHECKSUMCHECKIP(1U)
+
+#define S_CTAG    4
+#define V_CTAG(x) ((x) << S_CTAG)
+#define F_CTAG    V_CTAG(1U)
+
+#define S_IN_CCPL    3
+#define V_IN_CCPL(x) ((x) << S_IN_CCPL)
+#define F_IN_CCPL    V_IN_CCPL(1U)
+
+#define S_IN_CETH    1
+#define V_IN_CETH(x) ((x) << S_IN_CETH)
+#define F_IN_CETH    V_IN_CETH(1U)
+
+#define S_CTUNNEL    0
+#define V_CTUNNEL(x) ((x) << S_CTUNNEL)
+#define F_CTUNNEL    V_CTUNNEL(1U)
+
+#define S_VLANEXTENPORT3    31
+#define V_VLANEXTENPORT3(x) ((x) << S_VLANEXTENPORT3)
+#define F_VLANEXTENPORT3    V_VLANEXTENPORT3(1U)
+
+#define S_VLANEXTENPORT2    30
+#define V_VLANEXTENPORT2(x) ((x) << S_VLANEXTENPORT2)
+#define F_VLANEXTENPORT2    V_VLANEXTENPORT2(1U)
+
+#define S_VLANEXTENPORT1    29
+#define V_VLANEXTENPORT1(x) ((x) << S_VLANEXTENPORT1)
+#define F_VLANEXTENPORT1    V_VLANEXTENPORT1(1U)
+
+#define S_VLANEXTENPORT0    28
+#define V_VLANEXTENPORT0(x) ((x) << S_VLANEXTENPORT0)
+#define F_VLANEXTENPORT0    V_VLANEXTENPORT0(1U)
+
+#define S_VNTAGDEFAULTVAL    13
+#define V_VNTAGDEFAULTVAL(x) ((x) << S_VNTAGDEFAULTVAL)
+#define F_VNTAGDEFAULTVAL    V_VNTAGDEFAULTVAL(1U)
+
+#define S_ECHECKUDPLEN    12
+#define V_ECHECKUDPLEN(x) ((x) << S_ECHECKUDPLEN)
+#define F_ECHECKUDPLEN    V_ECHECKUDPLEN(1U)
+
+#define S_FCOEFPMA    10
+#define V_FCOEFPMA(x) ((x) << S_FCOEFPMA)
+#define F_FCOEFPMA    V_FCOEFPMA(1U)
+
+#define S_VNTAGETHENABLE    8
+#define V_VNTAGETHENABLE(x) ((x) << S_VNTAGETHENABLE)
+#define F_VNTAGETHENABLE    V_VNTAGETHENABLE(1U)
+
+#define S_IP_CCSM    7
+#define V_IP_CCSM(x) ((x) << S_IP_CCSM)
+#define F_IP_CCSM    V_IP_CCSM(1U)
+
+#define S_CCHECKSUMCHECKUDP    6
+#define V_CCHECKSUMCHECKUDP(x) ((x) << S_CCHECKSUMCHECKUDP)
+#define F_CCHECKSUMCHECKUDP    V_CCHECKSUMCHECKUDP(1U)
+
+#define S_TCP_CCSM    5
+#define V_TCP_CCSM(x) ((x) << S_TCP_CCSM)
+#define F_TCP_CCSM    V_TCP_CCSM(1U)
+
+#define S_CDEMUX    3
+#define V_CDEMUX(x) ((x) << S_CDEMUX)
+#define F_CDEMUX    V_CDEMUX(1U)
+
+#define S_ETHUPEN    2
+#define V_ETHUPEN(x) ((x) << S_ETHUPEN)
+#define F_ETHUPEN    V_ETHUPEN(1U)
+
+#define A_TP_OUT_CONFIG 0x7d04
+
+#define S_PORTQFCEN    28
+#define M_PORTQFCEN    0xfU
+#define V_PORTQFCEN(x) ((x) << S_PORTQFCEN)
+#define G_PORTQFCEN(x) (((x) >> S_PORTQFCEN) & M_PORTQFCEN)
+
+#define S_EPKTDISTCHN3    23
+#define V_EPKTDISTCHN3(x) ((x) << S_EPKTDISTCHN3)
+#define F_EPKTDISTCHN3    V_EPKTDISTCHN3(1U)
+
+#define S_EPKTDISTCHN2    22
+#define V_EPKTDISTCHN2(x) ((x) << S_EPKTDISTCHN2)
+#define F_EPKTDISTCHN2    V_EPKTDISTCHN2(1U)
+
+#define S_EPKTDISTCHN1    21
+#define V_EPKTDISTCHN1(x) ((x) << S_EPKTDISTCHN1)
+#define F_EPKTDISTCHN1    V_EPKTDISTCHN1(1U)
+
+#define S_EPKTDISTCHN0    20
+#define V_EPKTDISTCHN0(x) ((x) << S_EPKTDISTCHN0)
+#define F_EPKTDISTCHN0    V_EPKTDISTCHN0(1U)
+
+#define S_TTLMODE    19
+#define V_TTLMODE(x) ((x) << S_TTLMODE)
+#define F_TTLMODE    V_TTLMODE(1U)
+
+#define S_EQFCDMAC    18
+#define V_EQFCDMAC(x) ((x) << S_EQFCDMAC)
+#define F_EQFCDMAC    V_EQFCDMAC(1U)
+
+#define S_ELPBKINCMPSSTAT    17
+#define V_ELPBKINCMPSSTAT(x) ((x) << S_ELPBKINCMPSSTAT)
+#define F_ELPBKINCMPSSTAT    V_ELPBKINCMPSSTAT(1U)
+
+#define S_IPIDSPLITMODE    16
+#define V_IPIDSPLITMODE(x) ((x) << S_IPIDSPLITMODE)
+#define F_IPIDSPLITMODE    V_IPIDSPLITMODE(1U)
+
+#define S_VLANEXTENABLEPORT3    15
+#define V_VLANEXTENABLEPORT3(x) ((x) << S_VLANEXTENABLEPORT3)
+#define F_VLANEXTENABLEPORT3    V_VLANEXTENABLEPORT3(1U)
+
+#define S_VLANEXTENABLEPORT2    14
+#define V_VLANEXTENABLEPORT2(x) ((x) << S_VLANEXTENABLEPORT2)
+#define F_VLANEXTENABLEPORT2    V_VLANEXTENABLEPORT2(1U)
+
+#define S_VLANEXTENABLEPORT1    13
+#define V_VLANEXTENABLEPORT1(x) ((x) << S_VLANEXTENABLEPORT1)
+#define F_VLANEXTENABLEPORT1    V_VLANEXTENABLEPORT1(1U)
+
+#define S_VLANEXTENABLEPORT0    12
+#define V_VLANEXTENABLEPORT0(x) ((x) << S_VLANEXTENABLEPORT0)
+#define F_VLANEXTENABLEPORT0    V_VLANEXTENABLEPORT0(1U)
+
+#define S_ECHECKSUMINSERTTCP    11
+#define V_ECHECKSUMINSERTTCP(x) ((x) << S_ECHECKSUMINSERTTCP)
+#define F_ECHECKSUMINSERTTCP    V_ECHECKSUMINSERTTCP(1U)
+
+#define S_ECHECKSUMINSERTIP    10
+#define V_ECHECKSUMINSERTIP(x) ((x) << S_ECHECKSUMINSERTIP)
+#define F_ECHECKSUMINSERTIP    V_ECHECKSUMINSERTIP(1U)
+
+#define S_ECPL    8
+#define V_ECPL(x) ((x) << S_ECPL)
+#define F_ECPL    V_ECPL(1U)
+
+#define S_EPRIORITY    7
+#define V_EPRIORITY(x) ((x) << S_EPRIORITY)
+#define F_EPRIORITY    V_EPRIORITY(1U)
+
+#define S_EETHERNET    6
+#define V_EETHERNET(x) ((x) << S_EETHERNET)
+#define F_EETHERNET    V_EETHERNET(1U)
+
+#define S_CCHECKSUMINSERTTCP    5
+#define V_CCHECKSUMINSERTTCP(x) ((x) << S_CCHECKSUMINSERTTCP)
+#define F_CCHECKSUMINSERTTCP    V_CCHECKSUMINSERTTCP(1U)
+
+#define S_CCHECKSUMINSERTIP    4
+#define V_CCHECKSUMINSERTIP(x) ((x) << S_CCHECKSUMINSERTIP)
+#define F_CCHECKSUMINSERTIP    V_CCHECKSUMINSERTIP(1U)
+
+#define S_CCPL    2
+#define V_CCPL(x) ((x) << S_CCPL)
+#define F_CCPL    V_CCPL(1U)
+
+#define S_CETHERNET    0
+#define V_CETHERNET(x) ((x) << S_CETHERNET)
+#define F_CETHERNET    V_CETHERNET(1U)
+
+#define S_EVNTAGEN    9
+#define V_EVNTAGEN(x) ((x) << S_EVNTAGEN)
+#define F_EVNTAGEN    V_EVNTAGEN(1U)
+
+#define A_TP_GLOBAL_CONFIG 0x7d08
+
+#define S_SYNCOOKIEPARAMS    26
+#define M_SYNCOOKIEPARAMS    0x3fU
+#define V_SYNCOOKIEPARAMS(x) ((x) << S_SYNCOOKIEPARAMS)
+#define G_SYNCOOKIEPARAMS(x) (((x) >> S_SYNCOOKIEPARAMS) & M_SYNCOOKIEPARAMS)
+
+#define S_RXFLOWCONTROLDISABLE    25
+#define V_RXFLOWCONTROLDISABLE(x) ((x) << S_RXFLOWCONTROLDISABLE)
+#define F_RXFLOWCONTROLDISABLE    V_RXFLOWCONTROLDISABLE(1U)
+
+#define S_TXPACINGENABLE    24
+#define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE)
+#define F_TXPACINGENABLE    V_TXPACINGENABLE(1U)
+
+#define S_ATTACKFILTERENABLE    23
+#define V_ATTACKFILTERENABLE(x) ((x) << S_ATTACKFILTERENABLE)
+#define F_ATTACKFILTERENABLE    V_ATTACKFILTERENABLE(1U)
+
+#define S_SYNCOOKIENOOPTIONS    22
+#define V_SYNCOOKIENOOPTIONS(x) ((x) << S_SYNCOOKIENOOPTIONS)
+#define F_SYNCOOKIENOOPTIONS    V_SYNCOOKIENOOPTIONS(1U)
+
+#define S_PROTECTEDMODE    21
+#define V_PROTECTEDMODE(x) ((x) << S_PROTECTEDMODE)
+#define F_PROTECTEDMODE    V_PROTECTEDMODE(1U)
+
+#define S_PINGDROP    20
+#define V_PINGDROP(x) ((x) << S_PINGDROP)
+#define F_PINGDROP    V_PINGDROP(1U)
+
+#define S_FRAGMENTDROP    19
+#define V_FRAGMENTDROP(x) ((x) << S_FRAGMENTDROP)
+#define F_FRAGMENTDROP    V_FRAGMENTDROP(1U)
+
+#define S_FIVETUPLELOOKUP    17
+#define M_FIVETUPLELOOKUP    0x3U
+#define V_FIVETUPLELOOKUP(x) ((x) << S_FIVETUPLELOOKUP)
+#define G_FIVETUPLELOOKUP(x) (((x) >> S_FIVETUPLELOOKUP) & M_FIVETUPLELOOKUP)
+
+#define S_OFDMPSSTATS    16
+#define V_OFDMPSSTATS(x) ((x) << S_OFDMPSSTATS)
+#define F_OFDMPSSTATS    V_OFDMPSSTATS(1U)
+
+#define S_DONTFRAGMENT    15
+#define V_DONTFRAGMENT(x) ((x) << S_DONTFRAGMENT)
+#define F_DONTFRAGMENT    V_DONTFRAGMENT(1U)
+
+#define S_IPIDENTSPLIT    14
+#define V_IPIDENTSPLIT(x) ((x) << S_IPIDENTSPLIT)
+#define F_IPIDENTSPLIT    V_IPIDENTSPLIT(1U)
+
+#define S_IPCHECKSUMOFFLOAD    13
+#define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD)
+#define F_IPCHECKSUMOFFLOAD    V_IPCHECKSUMOFFLOAD(1U)
+
+#define S_UDPCHECKSUMOFFLOAD    12
+#define V_UDPCHECKSUMOFFLOAD(x) ((x) << S_UDPCHECKSUMOFFLOAD)
+#define F_UDPCHECKSUMOFFLOAD    V_UDPCHECKSUMOFFLOAD(1U)
+
+#define S_TCPCHECKSUMOFFLOAD    11
+#define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD)
+#define F_TCPCHECKSUMOFFLOAD    V_TCPCHECKSUMOFFLOAD(1U)
+
+#define S_RSSLOOPBACKENABLE    10
+#define V_RSSLOOPBACKENABLE(x) ((x) << S_RSSLOOPBACKENABLE)
+#define F_RSSLOOPBACKENABLE    V_RSSLOOPBACKENABLE(1U)
+
+#define S_TCAMSERVERUSE    8
+#define M_TCAMSERVERUSE    0x3U
+#define V_TCAMSERVERUSE(x) ((x) << S_TCAMSERVERUSE)
+#define G_TCAMSERVERUSE(x) (((x) >> S_TCAMSERVERUSE) & M_TCAMSERVERUSE)
+
+#define S_IPTTL    0
+#define M_IPTTL    0xffU
+#define V_IPTTL(x) ((x) << S_IPTTL)
+#define G_IPTTL(x) (((x) >> S_IPTTL) & M_IPTTL)
+
+#define S_RSSSYNSTEERENABLE    12
+#define V_RSSSYNSTEERENABLE(x) ((x) << S_RSSSYNSTEERENABLE)
+#define F_RSSSYNSTEERENABLE    V_RSSSYNSTEERENABLE(1U)
+
+#define S_ISSFROMCPLENABLE    11
+#define V_ISSFROMCPLENABLE(x) ((x) << S_ISSFROMCPLENABLE)
+#define F_ISSFROMCPLENABLE    V_ISSFROMCPLENABLE(1U)
+
+#define A_TP_DB_CONFIG 0x7d0c
+
+#define S_DBMAXOPCNT    24
+#define M_DBMAXOPCNT    0xffU
+#define V_DBMAXOPCNT(x) ((x) << S_DBMAXOPCNT)
+#define G_DBMAXOPCNT(x) (((x) >> S_DBMAXOPCNT) & M_DBMAXOPCNT)
+
+#define S_CXMAXOPCNTDISABLE    23
+#define V_CXMAXOPCNTDISABLE(x) ((x) << S_CXMAXOPCNTDISABLE)
+#define F_CXMAXOPCNTDISABLE    V_CXMAXOPCNTDISABLE(1U)
+
+#define S_CXMAXOPCNT    16
+#define M_CXMAXOPCNT    0x7fU
+#define V_CXMAXOPCNT(x) ((x) << S_CXMAXOPCNT)
+#define G_CXMAXOPCNT(x) (((x) >> S_CXMAXOPCNT) & M_CXMAXOPCNT)
+
+#define S_TXMAXOPCNTDISABLE    15
+#define V_TXMAXOPCNTDISABLE(x) ((x) << S_TXMAXOPCNTDISABLE)
+#define F_TXMAXOPCNTDISABLE    V_TXMAXOPCNTDISABLE(1U)
+
+#define S_TXMAXOPCNT    8
+#define M_TXMAXOPCNT    0x7fU
+#define V_TXMAXOPCNT(x) ((x) << S_TXMAXOPCNT)
+#define G_TXMAXOPCNT(x) (((x) >> S_TXMAXOPCNT) & M_TXMAXOPCNT)
+
+#define S_RXMAXOPCNTDISABLE    7
+#define V_RXMAXOPCNTDISABLE(x) ((x) << S_RXMAXOPCNTDISABLE)
+#define F_RXMAXOPCNTDISABLE    V_RXMAXOPCNTDISABLE(1U)
+
+#define S_RXMAXOPCNT    0
+#define M_RXMAXOPCNT    0x7fU
+#define V_RXMAXOPCNT(x) ((x) << S_RXMAXOPCNT)
+#define G_RXMAXOPCNT(x) (((x) >> S_RXMAXOPCNT) & M_RXMAXOPCNT)
+
+#define A_TP_CMM_TCB_BASE 0x7d10
+#define A_TP_CMM_MM_BASE 0x7d14
+#define A_TP_CMM_TIMER_BASE 0x7d18
+#define A_TP_CMM_MM_FLST_SIZE 0x7d1c
+
+#define S_RXPOOLSIZE    16
+#define M_RXPOOLSIZE    0xffffU
+#define V_RXPOOLSIZE(x) ((x) << S_RXPOOLSIZE)
+#define G_RXPOOLSIZE(x) (((x) >> S_RXPOOLSIZE) & M_RXPOOLSIZE)
+
+#define S_TXPOOLSIZE    0
+#define M_TXPOOLSIZE    0xffffU
+#define V_TXPOOLSIZE(x) ((x) << S_TXPOOLSIZE)
+#define G_TXPOOLSIZE(x) (((x) >> S_TXPOOLSIZE) & M_TXPOOLSIZE)
+
+#define A_TP_PMM_TX_BASE 0x7d20
+#define A_TP_PMM_DEFRAG_BASE 0x7d24
+#define A_TP_PMM_RX_BASE 0x7d28
+#define A_TP_PMM_RX_PAGE_SIZE 0x7d2c
+#define A_TP_PMM_RX_MAX_PAGE 0x7d30
+
+#define S_PMRXNUMCHN    31
+#define V_PMRXNUMCHN(x) ((x) << S_PMRXNUMCHN)
+#define F_PMRXNUMCHN    V_PMRXNUMCHN(1U)
+
+#define S_PMRXMAXPAGE    0
+#define M_PMRXMAXPAGE    0x1fffffU
+#define V_PMRXMAXPAGE(x) ((x) << S_PMRXMAXPAGE)
+#define G_PMRXMAXPAGE(x) (((x) >> S_PMRXMAXPAGE) & M_PMRXMAXPAGE)
+
+#define A_TP_PMM_TX_PAGE_SIZE 0x7d34
+#define A_TP_PMM_TX_MAX_PAGE 0x7d38
+
+#define S_PMTXNUMCHN    30
+#define M_PMTXNUMCHN    0x3U
+#define V_PMTXNUMCHN(x) ((x) << S_PMTXNUMCHN)
+#define G_PMTXNUMCHN(x) (((x) >> S_PMTXNUMCHN) & M_PMTXNUMCHN)
+
+#define S_PMTXMAXPAGE    0
+#define M_PMTXMAXPAGE    0x1fffffU
+#define V_PMTXMAXPAGE(x) ((x) << S_PMTXMAXPAGE)
+#define G_PMTXMAXPAGE(x) (((x) >> S_PMTXMAXPAGE) & M_PMTXMAXPAGE)
+
+#define A_TP_TCP_OPTIONS 0x7d40
+
+#define S_MTUDEFAULT    16
+#define M_MTUDEFAULT    0xffffU
+#define V_MTUDEFAULT(x) ((x) << S_MTUDEFAULT)
+#define G_MTUDEFAULT(x) (((x) >> S_MTUDEFAULT) & M_MTUDEFAULT)
+
+#define S_MTUENABLE    10
+#define V_MTUENABLE(x) ((x) << S_MTUENABLE)
+#define F_MTUENABLE    V_MTUENABLE(1U)
+
+#define S_SACKTX    9
+#define V_SACKTX(x) ((x) << S_SACKTX)
+#define F_SACKTX    V_SACKTX(1U)
+
+#define S_SACKRX    8
+#define V_SACKRX(x) ((x) << S_SACKRX)
+#define F_SACKRX    V_SACKRX(1U)
+
+#define S_SACKMODE    4
+#define M_SACKMODE    0x3U
+#define V_SACKMODE(x) ((x) << S_SACKMODE)
+#define G_SACKMODE(x) (((x) >> S_SACKMODE) & M_SACKMODE)
+
+#define S_WINDOWSCALEMODE    2
+#define M_WINDOWSCALEMODE    0x3U
+#define V_WINDOWSCALEMODE(x) ((x) << S_WINDOWSCALEMODE)
+#define G_WINDOWSCALEMODE(x) (((x) >> S_WINDOWSCALEMODE) & M_WINDOWSCALEMODE)
+
+#define S_TIMESTAMPSMODE    0
+#define M_TIMESTAMPSMODE    0x3U
+#define V_TIMESTAMPSMODE(x) ((x) << S_TIMESTAMPSMODE)
+#define G_TIMESTAMPSMODE(x) (((x) >> S_TIMESTAMPSMODE) & M_TIMESTAMPSMODE)
+
+#define A_TP_DACK_CONFIG 0x7d44
+
+#define S_AUTOSTATE3    30
+#define M_AUTOSTATE3    0x3U
+#define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3)
+#define G_AUTOSTATE3(x) (((x) >> S_AUTOSTATE3) & M_AUTOSTATE3)
+
+#define S_AUTOSTATE2    28
+#define M_AUTOSTATE2    0x3U
+#define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2)
+#define G_AUTOSTATE2(x) (((x) >> S_AUTOSTATE2) & M_AUTOSTATE2)
+
+#define S_AUTOSTATE1    26
+#define M_AUTOSTATE1    0x3U
+#define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1)
+#define G_AUTOSTATE1(x) (((x) >> S_AUTOSTATE1) & M_AUTOSTATE1)
+
+#define S_BYTETHRESHOLD    8
+#define M_BYTETHRESHOLD    0x3ffffU
+#define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD)
+#define G_BYTETHRESHOLD(x) (((x) >> S_BYTETHRESHOLD) & M_BYTETHRESHOLD)
+
+#define S_MSSTHRESHOLD    4
+#define M_MSSTHRESHOLD    0x7U
+#define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD)
+#define G_MSSTHRESHOLD(x) (((x) >> S_MSSTHRESHOLD) & M_MSSTHRESHOLD)
+
+#define S_AUTOCAREFUL    2
+#define V_AUTOCAREFUL(x) ((x) << S_AUTOCAREFUL)
+#define F_AUTOCAREFUL    V_AUTOCAREFUL(1U)
+
+#define S_AUTOENABLE    1
+#define V_AUTOENABLE(x) ((x) << S_AUTOENABLE)
+#define F_AUTOENABLE    V_AUTOENABLE(1U)
+
+#define S_MODE    0
+#define V_MODE(x) ((x) << S_MODE)
+#define F_MODE    V_MODE(1U)
+
+#define A_TP_PC_CONFIG 0x7d48
+
+#define S_CMCACHEDISABLE    31
+#define V_CMCACHEDISABLE(x) ((x) << S_CMCACHEDISABLE)
+#define F_CMCACHEDISABLE    V_CMCACHEDISABLE(1U)
+
+#define S_ENABLEOCSPIFULL    30
+#define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL)
+#define F_ENABLEOCSPIFULL    V_ENABLEOCSPIFULL(1U)
+
+#define S_ENABLEFLMERRORDDP    29
+#define V_ENABLEFLMERRORDDP(x) ((x) << S_ENABLEFLMERRORDDP)
+#define F_ENABLEFLMERRORDDP    V_ENABLEFLMERRORDDP(1U)
+
+#define S_LOCKTID    28
+#define V_LOCKTID(x) ((x) << S_LOCKTID)
+#define F_LOCKTID    V_LOCKTID(1U)
+
+#define S_DISABLEINVPEND    27
+#define V_DISABLEINVPEND(x) ((x) << S_DISABLEINVPEND)
+#define F_DISABLEINVPEND    V_DISABLEINVPEND(1U)
+
+#define S_ENABLEFILTERCOUNT    26
+#define V_ENABLEFILTERCOUNT(x) ((x) << S_ENABLEFILTERCOUNT)
+#define F_ENABLEFILTERCOUNT    V_ENABLEFILTERCOUNT(1U)
+
+#define S_RDDPCONGEN    25
+#define V_RDDPCONGEN(x) ((x) << S_RDDPCONGEN)
+#define F_RDDPCONGEN    V_RDDPCONGEN(1U)
+
+#define S_ENABLEONFLYPDU    24
+#define V_ENABLEONFLYPDU(x) ((x) << S_ENABLEONFLYPDU)
+#define F_ENABLEONFLYPDU    V_ENABLEONFLYPDU(1U)
+
+#define S_ENABLEMINRCVWND    23
+#define V_ENABLEMINRCVWND(x) ((x) << S_ENABLEMINRCVWND)
+#define F_ENABLEMINRCVWND    V_ENABLEMINRCVWND(1U)
+
+#define S_ENABLEMAXRCVWND    22
+#define V_ENABLEMAXRCVWND(x) ((x) << S_ENABLEMAXRCVWND)
+#define F_ENABLEMAXRCVWND    V_ENABLEMAXRCVWND(1U)
+
+#define S_TXDATAACKRATEENABLE    21
+#define V_TXDATAACKRATEENABLE(x) ((x) << S_TXDATAACKRATEENABLE)
+#define F_TXDATAACKRATEENABLE    V_TXDATAACKRATEENABLE(1U)
+
+#define S_TXDEFERENABLE    20
+#define V_TXDEFERENABLE(x) ((x) << S_TXDEFERENABLE)
+#define F_TXDEFERENABLE    V_TXDEFERENABLE(1U)
+
+#define S_RXCONGESTIONMODE    19
+#define V_RXCONGESTIONMODE(x) ((x) << S_RXCONGESTIONMODE)
+#define F_RXCONGESTIONMODE    V_RXCONGESTIONMODE(1U)
+
+#define S_HEARBEATONCEDACK    18
+#define V_HEARBEATONCEDACK(x) ((x) << S_HEARBEATONCEDACK)
+#define F_HEARBEATONCEDACK    V_HEARBEATONCEDACK(1U)
+
+#define S_HEARBEATONCEHEAP    17
+#define V_HEARBEATONCEHEAP(x) ((x) << S_HEARBEATONCEHEAP)
+#define F_HEARBEATONCEHEAP    V_HEARBEATONCEHEAP(1U)
+
+#define S_HEARBEATDACK    16
+#define V_HEARBEATDACK(x) ((x) << S_HEARBEATDACK)
+#define F_HEARBEATDACK    V_HEARBEATDACK(1U)
+
+#define S_TXCONGESTIONMODE    15
+#define V_TXCONGESTIONMODE(x) ((x) << S_TXCONGESTIONMODE)
+#define F_TXCONGESTIONMODE    V_TXCONGESTIONMODE(1U)
+
+#define S_ACCEPTLATESTRCVADV    14
+#define V_ACCEPTLATESTRCVADV(x) ((x) << S_ACCEPTLATESTRCVADV)
+#define F_ACCEPTLATESTRCVADV    V_ACCEPTLATESTRCVADV(1U)
+
+#define S_DISABLESYNDATA    13
+#define V_DISABLESYNDATA(x) ((x) << S_DISABLESYNDATA)
+#define F_DISABLESYNDATA    V_DISABLESYNDATA(1U)
+
+#define S_DISABLEWINDOWPSH    12
+#define V_DISABLEWINDOWPSH(x) ((x) << S_DISABLEWINDOWPSH)
+#define F_DISABLEWINDOWPSH    V_DISABLEWINDOWPSH(1U)
+
+#define S_DISABLEFINOLDDATA    11
+#define V_DISABLEFINOLDDATA(x) ((x) << S_DISABLEFINOLDDATA)
+#define F_DISABLEFINOLDDATA    V_DISABLEFINOLDDATA(1U)
+
+#define S_ENABLEFLMERROR    10
+#define V_ENABLEFLMERROR(x) ((x) << S_ENABLEFLMERROR)
+#define F_ENABLEFLMERROR    V_ENABLEFLMERROR(1U)
+
+#define S_ENABLEOPTMTU    9
+#define V_ENABLEOPTMTU(x) ((x) << S_ENABLEOPTMTU)
+#define F_ENABLEOPTMTU    V_ENABLEOPTMTU(1U)
+
+#define S_FILTERPEERFIN    8
+#define V_FILTERPEERFIN(x) ((x) << S_FILTERPEERFIN)
+#define F_FILTERPEERFIN    V_FILTERPEERFIN(1U)
+
+#define S_ENABLEFEEDBACKSEND    7
+#define V_ENABLEFEEDBACKSEND(x) ((x) << S_ENABLEFEEDBACKSEND)
+#define F_ENABLEFEEDBACKSEND    V_ENABLEFEEDBACKSEND(1U)
+
+#define S_ENABLERDMAERROR    6
+#define V_ENABLERDMAERROR(x) ((x) << S_ENABLERDMAERROR)
+#define F_ENABLERDMAERROR    V_ENABLERDMAERROR(1U)
+
+#define S_ENABLEDDPFLOWCONTROL    5
+#define V_ENABLEDDPFLOWCONTROL(x) ((x) << S_ENABLEDDPFLOWCONTROL)
+#define F_ENABLEDDPFLOWCONTROL    V_ENABLEDDPFLOWCONTROL(1U)
+
+#define S_DISABLEHELDFIN    4
+#define V_DISABLEHELDFIN(x) ((x) << S_DISABLEHELDFIN)
+#define F_DISABLEHELDFIN    V_DISABLEHELDFIN(1U)
+
+#define S_ENABLEOFDOVLAN    3
+#define V_ENABLEOFDOVLAN(x) ((x) << S_ENABLEOFDOVLAN)
+#define F_ENABLEOFDOVLAN    V_ENABLEOFDOVLAN(1U)
+
+#define S_DISABLETIMEWAIT    2
+#define V_DISABLETIMEWAIT(x) ((x) << S_DISABLETIMEWAIT)
+#define F_DISABLETIMEWAIT    V_DISABLETIMEWAIT(1U)
+
+#define S_ENABLEVLANCHECK    1
+#define V_ENABLEVLANCHECK(x) ((x) << S_ENABLEVLANCHECK)
+#define F_ENABLEVLANCHECK    V_ENABLEVLANCHECK(1U)
+
+#define S_TXDATAACKPAGEENABLE    0
+#define V_TXDATAACKPAGEENABLE(x) ((x) << S_TXDATAACKPAGEENABLE)
+#define F_TXDATAACKPAGEENABLE    V_TXDATAACKPAGEENABLE(1U)
+
+#define S_ENABLEFILTERNAT    5
+#define V_ENABLEFILTERNAT(x) ((x) << S_ENABLEFILTERNAT)
+#define F_ENABLEFILTERNAT    V_ENABLEFILTERNAT(1U)
+
+#define A_TP_PC_CONFIG2 0x7d4c
+
+#define S_ENABLEMTUVFMODE    31
+#define V_ENABLEMTUVFMODE(x) ((x) << S_ENABLEMTUVFMODE)
+#define F_ENABLEMTUVFMODE    V_ENABLEMTUVFMODE(1U)
+
+#define S_ENABLEMIBVFMODE    30
+#define V_ENABLEMIBVFMODE(x) ((x) << S_ENABLEMIBVFMODE)
+#define F_ENABLEMIBVFMODE    V_ENABLEMIBVFMODE(1U)
+
+#define S_DISABLELBKCHECK    29
+#define V_DISABLELBKCHECK(x) ((x) << S_DISABLELBKCHECK)
+#define F_DISABLELBKCHECK    V_DISABLELBKCHECK(1U)
+
+#define S_ENABLEURGDDPOFF    28
+#define V_ENABLEURGDDPOFF(x) ((x) << S_ENABLEURGDDPOFF)
+#define F_ENABLEURGDDPOFF    V_ENABLEURGDDPOFF(1U)
+
+#define S_ENABLEFILTERLPBK    27
+#define V_ENABLEFILTERLPBK(x) ((x) << S_ENABLEFILTERLPBK)
+#define F_ENABLEFILTERLPBK    V_ENABLEFILTERLPBK(1U)
+
+#define S_DISABLETBLMMGR    26
+#define V_DISABLETBLMMGR(x) ((x) << S_DISABLETBLMMGR)
+#define F_DISABLETBLMMGR    V_DISABLETBLMMGR(1U)
+
+#define S_CNGRECSNDNXT    25
+#define V_CNGRECSNDNXT(x) ((x) << S_CNGRECSNDNXT)
+#define F_CNGRECSNDNXT    V_CNGRECSNDNXT(1U)
+
+#define S_ENABLELBKCHN    24
+#define V_ENABLELBKCHN(x) ((x) << S_ENABLELBKCHN)
+#define F_ENABLELBKCHN    V_ENABLELBKCHN(1U)
+
+#define S_ENABLELROECN    23
+#define V_ENABLELROECN(x) ((x) << S_ENABLELROECN)
+#define F_ENABLELROECN    V_ENABLELROECN(1U)
+
+#define S_ENABLEPCMDCHECK    22
+#define V_ENABLEPCMDCHECK(x) ((x) << S_ENABLEPCMDCHECK)
+#define F_ENABLEPCMDCHECK    V_ENABLEPCMDCHECK(1U)
+
+#define S_ENABLEELBKAFULL    21
+#define V_ENABLEELBKAFULL(x) ((x) << S_ENABLEELBKAFULL)
+#define F_ENABLEELBKAFULL    V_ENABLEELBKAFULL(1U)
+
+#define S_ENABLECLBKAFULL    20
+#define V_ENABLECLBKAFULL(x) ((x) << S_ENABLECLBKAFULL)
+#define F_ENABLECLBKAFULL    V_ENABLECLBKAFULL(1U)
+
+#define S_ENABLEOESPIFULL    19
+#define V_ENABLEOESPIFULL(x) ((x) << S_ENABLEOESPIFULL)
+#define F_ENABLEOESPIFULL    V_ENABLEOESPIFULL(1U)
+
+#define S_DISABLEHITCHECK    18
+#define V_DISABLEHITCHECK(x) ((x) << S_DISABLEHITCHECK)
+#define F_DISABLEHITCHECK    V_DISABLEHITCHECK(1U)
+
+#define S_ENABLERSSERRCHECK    17
+#define V_ENABLERSSERRCHECK(x) ((x) << S_ENABLERSSERRCHECK)
+#define F_ENABLERSSERRCHECK    V_ENABLERSSERRCHECK(1U)
+
+#define S_DISABLENEWPSHFLAG    16
+#define V_DISABLENEWPSHFLAG(x) ((x) << S_DISABLENEWPSHFLAG)
+#define F_DISABLENEWPSHFLAG    V_DISABLENEWPSHFLAG(1U)
+
+#define S_ENABLERDDPRCVADVCLR    15
+#define V_ENABLERDDPRCVADVCLR(x) ((x) << S_ENABLERDDPRCVADVCLR)
+#define F_ENABLERDDPRCVADVCLR    V_ENABLERDDPRCVADVCLR(1U)
+
+#define S_ENABLETXDATAARPMISS    14
+#define V_ENABLETXDATAARPMISS(x) ((x) << S_ENABLETXDATAARPMISS)
+#define F_ENABLETXDATAARPMISS    V_ENABLETXDATAARPMISS(1U)
+
+#define S_ENABLEARPMISS    13
+#define V_ENABLEARPMISS(x) ((x) << S_ENABLEARPMISS)
+#define F_ENABLEARPMISS    V_ENABLEARPMISS(1U)
+
+#define S_ENABLERSTPAWS    12
+#define V_ENABLERSTPAWS(x) ((x) << S_ENABLERSTPAWS)
+#define F_ENABLERSTPAWS    V_ENABLERSTPAWS(1U)
+
+#define S_ENABLEIPV6RSS    11
+#define V_ENABLEIPV6RSS(x) ((x) << S_ENABLEIPV6RSS)
+#define F_ENABLEIPV6RSS    V_ENABLEIPV6RSS(1U)
+
+#define S_ENABLENONOFDHYBRSS    10
+#define V_ENABLENONOFDHYBRSS(x) ((x) << S_ENABLENONOFDHYBRSS)
+#define F_ENABLENONOFDHYBRSS    V_ENABLENONOFDHYBRSS(1U)
+
+#define S_ENABLEUDP4TUPRSS    9
+#define V_ENABLEUDP4TUPRSS(x) ((x) << S_ENABLEUDP4TUPRSS)
+#define F_ENABLEUDP4TUPRSS    V_ENABLEUDP4TUPRSS(1U)
+
+#define S_ENABLERXPKTTMSTPRSS    8
+#define V_ENABLERXPKTTMSTPRSS(x) ((x) << S_ENABLERXPKTTMSTPRSS)
+#define F_ENABLERXPKTTMSTPRSS    V_ENABLERXPKTTMSTPRSS(1U)
+
+#define S_ENABLEEPCMDAFULL    7
+#define V_ENABLEEPCMDAFULL(x) ((x) << S_ENABLEEPCMDAFULL)
+#define F_ENABLEEPCMDAFULL    V_ENABLEEPCMDAFULL(1U)
+
+#define S_ENABLECPCMDAFULL    6
+#define V_ENABLECPCMDAFULL(x) ((x) << S_ENABLECPCMDAFULL)
+#define F_ENABLECPCMDAFULL    V_ENABLECPCMDAFULL(1U)
+
+#define S_ENABLEEHDRAFULL    5
+#define V_ENABLEEHDRAFULL(x) ((x) << S_ENABLEEHDRAFULL)
+#define F_ENABLEEHDRAFULL    V_ENABLEEHDRAFULL(1U)
+
+#define S_ENABLECHDRAFULL    4
+#define V_ENABLECHDRAFULL(x) ((x) << S_ENABLECHDRAFULL)
+#define F_ENABLECHDRAFULL    V_ENABLECHDRAFULL(1U)
+
+#define S_ENABLEEMACAFULL    3
+#define V_ENABLEEMACAFULL(x) ((x) << S_ENABLEEMACAFULL)
+#define F_ENABLEEMACAFULL    V_ENABLEEMACAFULL(1U)
+
+#define S_ENABLENONOFDTIDRSS    2
+#define V_ENABLENONOFDTIDRSS(x) ((x) << S_ENABLENONOFDTIDRSS)
+#define F_ENABLENONOFDTIDRSS    V_ENABLENONOFDTIDRSS(1U)
+
+#define S_ENABLENONOFDTCBRSS    1
+#define V_ENABLENONOFDTCBRSS(x) ((x) << S_ENABLENONOFDTCBRSS)
+#define F_ENABLENONOFDTCBRSS    V_ENABLENONOFDTCBRSS(1U)
+
+#define S_ENABLETNLOFDCLOSED    0
+#define V_ENABLETNLOFDCLOSED(x) ((x) << S_ENABLETNLOFDCLOSED)
+#define F_ENABLETNLOFDCLOSED    V_ENABLETNLOFDCLOSED(1U)
+
+#define S_ENABLEFINDDPOFF    14
+#define V_ENABLEFINDDPOFF(x) ((x) << S_ENABLEFINDDPOFF)
+#define F_ENABLEFINDDPOFF    V_ENABLEFINDDPOFF(1U)
+
+#define A_TP_TCP_BACKOFF_REG0 0x7d50
+
+#define S_TIMERBACKOFFINDEX3    24
+#define M_TIMERBACKOFFINDEX3    0xffU
+#define V_TIMERBACKOFFINDEX3(x) ((x) << S_TIMERBACKOFFINDEX3)
+#define G_TIMERBACKOFFINDEX3(x) (((x) >> S_TIMERBACKOFFINDEX3) & M_TIMERBACKOFFINDEX3)
+
+#define S_TIMERBACKOFFINDEX2    16
+#define M_TIMERBACKOFFINDEX2    0xffU
+#define V_TIMERBACKOFFINDEX2(x) ((x) << S_TIMERBACKOFFINDEX2)
+#define G_TIMERBACKOFFINDEX2(x) (((x) >> S_TIMERBACKOFFINDEX2) & M_TIMERBACKOFFINDEX2)
+
+#define S_TIMERBACKOFFINDEX1    8
+#define M_TIMERBACKOFFINDEX1    0xffU
+#define V_TIMERBACKOFFINDEX1(x) ((x) << S_TIMERBACKOFFINDEX1)
+#define G_TIMERBACKOFFINDEX1(x) (((x) >> S_TIMERBACKOFFINDEX1) & M_TIMERBACKOFFINDEX1)
+
+#define S_TIMERBACKOFFINDEX0    0
+#define M_TIMERBACKOFFINDEX0    0xffU
+#define V_TIMERBACKOFFINDEX0(x) ((x) << S_TIMERBACKOFFINDEX0)
+#define G_TIMERBACKOFFINDEX0(x) (((x) >> S_TIMERBACKOFFINDEX0) & M_TIMERBACKOFFINDEX0)
+
+#define A_TP_TCP_BACKOFF_REG1 0x7d54
+
+#define S_TIMERBACKOFFINDEX7    24
+#define M_TIMERBACKOFFINDEX7    0xffU
+#define V_TIMERBACKOFFINDEX7(x) ((x) << S_TIMERBACKOFFINDEX7)
+#define G_TIMERBACKOFFINDEX7(x) (((x) >> S_TIMERBACKOFFINDEX7) & M_TIMERBACKOFFINDEX7)
+
+#define S_TIMERBACKOFFINDEX6    16
+#define M_TIMERBACKOFFINDEX6    0xffU
+#define V_TIMERBACKOFFINDEX6(x) ((x) << S_TIMERBACKOFFINDEX6)
+#define G_TIMERBACKOFFINDEX6(x) (((x) >> S_TIMERBACKOFFINDEX6) & M_TIMERBACKOFFINDEX6)
+
+#define S_TIMERBACKOFFINDEX5    8
+#define M_TIMERBACKOFFINDEX5    0xffU
+#define V_TIMERBACKOFFINDEX5(x) ((x) << S_TIMERBACKOFFINDEX5)
+#define G_TIMERBACKOFFINDEX5(x) (((x) >> S_TIMERBACKOFFINDEX5) & M_TIMERBACKOFFINDEX5)
+
+#define S_TIMERBACKOFFINDEX4    0
+#define M_TIMERBACKOFFINDEX4    0xffU
+#define V_TIMERBACKOFFINDEX4(x) ((x) << S_TIMERBACKOFFINDEX4)
+#define G_TIMERBACKOFFINDEX4(x) (((x) >> S_TIMERBACKOFFINDEX4) & M_TIMERBACKOFFINDEX4)
+
+#define A_TP_TCP_BACKOFF_REG2 0x7d58
+
+#define S_TIMERBACKOFFINDEX11    24
+#define M_TIMERBACKOFFINDEX11    0xffU
+#define V_TIMERBACKOFFINDEX11(x) ((x) << S_TIMERBACKOFFINDEX11)
+#define G_TIMERBACKOFFINDEX11(x) (((x) >> S_TIMERBACKOFFINDEX11) & M_TIMERBACKOFFINDEX11)
+
+#define S_TIMERBACKOFFINDEX10    16
+#define M_TIMERBACKOFFINDEX10    0xffU
+#define V_TIMERBACKOFFINDEX10(x) ((x) << S_TIMERBACKOFFINDEX10)
+#define G_TIMERBACKOFFINDEX10(x) (((x) >> S_TIMERBACKOFFINDEX10) & M_TIMERBACKOFFINDEX10)
+
+#define S_TIMERBACKOFFINDEX9    8
+#define M_TIMERBACKOFFINDEX9    0xffU
+#define V_TIMERBACKOFFINDEX9(x) ((x) << S_TIMERBACKOFFINDEX9)
+#define G_TIMERBACKOFFINDEX9(x) (((x) >> S_TIMERBACKOFFINDEX9) & M_TIMERBACKOFFINDEX9)
+
+#define S_TIMERBACKOFFINDEX8    0
+#define M_TIMERBACKOFFINDEX8    0xffU
+#define V_TIMERBACKOFFINDEX8(x) ((x) << S_TIMERBACKOFFINDEX8)
+#define G_TIMERBACKOFFINDEX8(x) (((x) >> S_TIMERBACKOFFINDEX8) & M_TIMERBACKOFFINDEX8)
+
+#define A_TP_TCP_BACKOFF_REG3 0x7d5c
+
+#define S_TIMERBACKOFFINDEX15    24
+#define M_TIMERBACKOFFINDEX15    0xffU
+#define V_TIMERBACKOFFINDEX15(x) ((x) << S_TIMERBACKOFFINDEX15)
+#define G_TIMERBACKOFFINDEX15(x) (((x) >> S_TIMERBACKOFFINDEX15) & M_TIMERBACKOFFINDEX15)
+
+#define S_TIMERBACKOFFINDEX14    16
+#define M_TIMERBACKOFFINDEX14    0xffU
+#define V_TIMERBACKOFFINDEX14(x) ((x) << S_TIMERBACKOFFINDEX14)
+#define G_TIMERBACKOFFINDEX14(x) (((x) >> S_TIMERBACKOFFINDEX14) & M_TIMERBACKOFFINDEX14)
+
+#define S_TIMERBACKOFFINDEX13    8
+#define M_TIMERBACKOFFINDEX13    0xffU
+#define V_TIMERBACKOFFINDEX13(x) ((x) << S_TIMERBACKOFFINDEX13)
+#define G_TIMERBACKOFFINDEX13(x) (((x) >> S_TIMERBACKOFFINDEX13) & M_TIMERBACKOFFINDEX13)
+
+#define S_TIMERBACKOFFINDEX12    0
+#define M_TIMERBACKOFFINDEX12    0xffU
+#define V_TIMERBACKOFFINDEX12(x) ((x) << S_TIMERBACKOFFINDEX12)
+#define G_TIMERBACKOFFINDEX12(x) (((x) >> S_TIMERBACKOFFINDEX12) & M_TIMERBACKOFFINDEX12)
+
+#define A_TP_PARA_REG0 0x7d60
+
+#define S_INITCWNDIDLE    27
+#define V_INITCWNDIDLE(x) ((x) << S_INITCWNDIDLE)
+#define F_INITCWNDIDLE    V_INITCWNDIDLE(1U)
+
+#define S_INITCWND    24
+#define M_INITCWND    0x7U
+#define V_INITCWND(x) ((x) << S_INITCWND)
+#define G_INITCWND(x) (((x) >> S_INITCWND) & M_INITCWND)
+
+#define S_DUPACKTHRESH    20
+#define M_DUPACKTHRESH    0xfU
+#define V_DUPACKTHRESH(x) ((x) << S_DUPACKTHRESH)
+#define G_DUPACKTHRESH(x) (((x) >> S_DUPACKTHRESH) & M_DUPACKTHRESH)
+
+#define S_CPLERRENABLE    12
+#define V_CPLERRENABLE(x) ((x) << S_CPLERRENABLE)
+#define F_CPLERRENABLE    V_CPLERRENABLE(1U)
+
+#define S_FASTTNLCNT    11
+#define V_FASTTNLCNT(x) ((x) << S_FASTTNLCNT)
+#define F_FASTTNLCNT    V_FASTTNLCNT(1U)
+
+#define S_FASTTBLCNT    10
+#define V_FASTTBLCNT(x) ((x) << S_FASTTBLCNT)
+#define F_FASTTBLCNT    V_FASTTBLCNT(1U)
+
+#define S_TPTCAMKEY    9
+#define V_TPTCAMKEY(x) ((x) << S_TPTCAMKEY)
+#define F_TPTCAMKEY    V_TPTCAMKEY(1U)
+
+#define S_SWSMODE    8
+#define V_SWSMODE(x) ((x) << S_SWSMODE)
+#define F_SWSMODE    V_SWSMODE(1U)
+
+#define S_TSMPMODE    6
+#define M_TSMPMODE    0x3U
+#define V_TSMPMODE(x) ((x) << S_TSMPMODE)
+#define G_TSMPMODE(x) (((x) >> S_TSMPMODE) & M_TSMPMODE)
+
+#define S_BYTECOUNTLIMIT    4
+#define M_BYTECOUNTLIMIT    0x3U
+#define V_BYTECOUNTLIMIT(x) ((x) << S_BYTECOUNTLIMIT)
+#define G_BYTECOUNTLIMIT(x) (((x) >> S_BYTECOUNTLIMIT) & M_BYTECOUNTLIMIT)
+
+#define S_SWSSHOVE    3
+#define V_SWSSHOVE(x) ((x) << S_SWSSHOVE)
+#define F_SWSSHOVE    V_SWSSHOVE(1U)
+
+#define S_TBLTIMER    2
+#define V_TBLTIMER(x) ((x) << S_TBLTIMER)
+#define F_TBLTIMER    V_TBLTIMER(1U)
+
+#define S_RXTPACE    1
+#define V_RXTPACE(x) ((x) << S_RXTPACE)
+#define F_RXTPACE    V_RXTPACE(1U)
+
+#define S_SWSTIMER    0
+#define V_SWSTIMER(x) ((x) << S_SWSTIMER)
+#define F_SWSTIMER    V_SWSTIMER(1U)
+
+#define S_LIMTXTHRESH    28
+#define M_LIMTXTHRESH    0xfU
+#define V_LIMTXTHRESH(x) ((x) << S_LIMTXTHRESH)
+#define G_LIMTXTHRESH(x) (((x) >> S_LIMTXTHRESH) & M_LIMTXTHRESH)
+
+#define S_CHNERRENABLE    14
+#define V_CHNERRENABLE(x) ((x) << S_CHNERRENABLE)
+#define F_CHNERRENABLE    V_CHNERRENABLE(1U)
+
+#define S_SETTIMEENABLE    13
+#define V_SETTIMEENABLE(x) ((x) << S_SETTIMEENABLE)
+#define F_SETTIMEENABLE    V_SETTIMEENABLE(1U)
+
+#define A_TP_PARA_REG1 0x7d64
+
+#define S_INITRWND    16
+#define M_INITRWND    0xffffU
+#define V_INITRWND(x) ((x) << S_INITRWND)
+#define G_INITRWND(x) (((x) >> S_INITRWND) & M_INITRWND)
+
+#define S_INITIALSSTHRESH    0
+#define M_INITIALSSTHRESH    0xffffU
+#define V_INITIALSSTHRESH(x) ((x) << S_INITIALSSTHRESH)
+#define G_INITIALSSTHRESH(x) (((x) >> S_INITIALSSTHRESH) & M_INITIALSSTHRESH)
+
+#define A_TP_PARA_REG2 0x7d68
+
+#define S_MAXRXDATA    16
+#define M_MAXRXDATA    0xffffU
+#define V_MAXRXDATA(x) ((x) << S_MAXRXDATA)
+#define G_MAXRXDATA(x) (((x) >> S_MAXRXDATA) & M_MAXRXDATA)
+
+#define S_RXCOALESCESIZE    0
+#define M_RXCOALESCESIZE    0xffffU
+#define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE)
+#define G_RXCOALESCESIZE(x) (((x) >> S_RXCOALESCESIZE) & M_RXCOALESCESIZE)
+
+#define A_TP_PARA_REG3 0x7d6c
+
+#define S_ENABLETNLCNGLPBK    31
+#define V_ENABLETNLCNGLPBK(x) ((x) << S_ENABLETNLCNGLPBK)
+#define F_ENABLETNLCNGLPBK    V_ENABLETNLCNGLPBK(1U)
+
+#define S_ENABLETNLCNGFIFO    30
+#define V_ENABLETNLCNGFIFO(x) ((x) << S_ENABLETNLCNGFIFO)
+#define F_ENABLETNLCNGFIFO    V_ENABLETNLCNGFIFO(1U)
+
+#define S_ENABLETNLCNGHDR    29
+#define V_ENABLETNLCNGHDR(x) ((x) << S_ENABLETNLCNGHDR)
+#define F_ENABLETNLCNGHDR    V_ENABLETNLCNGHDR(1U)
+
+#define S_ENABLETNLCNGSGE    28
+#define V_ENABLETNLCNGSGE(x) ((x) << S_ENABLETNLCNGSGE)
+#define F_ENABLETNLCNGSGE    V_ENABLETNLCNGSGE(1U)
+
+#define S_RXMACCHECK    27
+#define V_RXMACCHECK(x) ((x) << S_RXMACCHECK)
+#define F_RXMACCHECK    V_RXMACCHECK(1U)
+
+#define S_RXSYNFILTER    26
+#define V_RXSYNFILTER(x) ((x) << S_RXSYNFILTER)
+#define F_RXSYNFILTER    V_RXSYNFILTER(1U)
+
+#define S_CNGCTRLECN    25
+#define V_CNGCTRLECN(x) ((x) << S_CNGCTRLECN)
+#define F_CNGCTRLECN    V_CNGCTRLECN(1U)
+
+#define S_RXDDPOFFINIT    24
+#define V_RXDDPOFFINIT(x) ((x) << S_RXDDPOFFINIT)
+#define F_RXDDPOFFINIT    V_RXDDPOFFINIT(1U)
+
+#define S_TUNNELCNGDROP3    23
+#define V_TUNNELCNGDROP3(x) ((x) << S_TUNNELCNGDROP3)
+#define F_TUNNELCNGDROP3    V_TUNNELCNGDROP3(1U)
+
+#define S_TUNNELCNGDROP2    22
+#define V_TUNNELCNGDROP2(x) ((x) << S_TUNNELCNGDROP2)
+#define F_TUNNELCNGDROP2    V_TUNNELCNGDROP2(1U)
+
+#define S_TUNNELCNGDROP1    21
+#define V_TUNNELCNGDROP1(x) ((x) << S_TUNNELCNGDROP1)
+#define F_TUNNELCNGDROP1    V_TUNNELCNGDROP1(1U)
+
+#define S_TUNNELCNGDROP0    20
+#define V_TUNNELCNGDROP0(x) ((x) << S_TUNNELCNGDROP0)
+#define F_TUNNELCNGDROP0    V_TUNNELCNGDROP0(1U)
+
+#define S_TXDATAACKIDX    16
+#define M_TXDATAACKIDX    0xfU
+#define V_TXDATAACKIDX(x) ((x) << S_TXDATAACKIDX)
+#define G_TXDATAACKIDX(x) (((x) >> S_TXDATAACKIDX) & M_TXDATAACKIDX)
+
+#define S_RXFRAGENABLE    12
+#define M_RXFRAGENABLE    0x7U
+#define V_RXFRAGENABLE(x) ((x) << S_RXFRAGENABLE)
+#define G_RXFRAGENABLE(x) (((x) >> S_RXFRAGENABLE) & M_RXFRAGENABLE)
+
+#define S_TXPACEFIXEDSTRICT    11
+#define V_TXPACEFIXEDSTRICT(x) ((x) << S_TXPACEFIXEDSTRICT)
+#define F_TXPACEFIXEDSTRICT    V_TXPACEFIXEDSTRICT(1U)
+
+#define S_TXPACEAUTOSTRICT    10
+#define V_TXPACEAUTOSTRICT(x) ((x) << S_TXPACEAUTOSTRICT)
+#define F_TXPACEAUTOSTRICT    V_TXPACEAUTOSTRICT(1U)
+
+#define S_TXPACEFIXED    9
+#define V_TXPACEFIXED(x) ((x) << S_TXPACEFIXED)
+#define F_TXPACEFIXED    V_TXPACEFIXED(1U)
+
+#define S_TXPACEAUTO    8
+#define V_TXPACEAUTO(x) ((x) << S_TXPACEAUTO)
+#define F_TXPACEAUTO    V_TXPACEAUTO(1U)
+
+#define S_RXCHNTUNNEL    7
+#define V_RXCHNTUNNEL(x) ((x) << S_RXCHNTUNNEL)
+#define F_RXCHNTUNNEL    V_RXCHNTUNNEL(1U)
+
+#define S_RXURGTUNNEL    6
+#define V_RXURGTUNNEL(x) ((x) << S_RXURGTUNNEL)
+#define F_RXURGTUNNEL    V_RXURGTUNNEL(1U)
+
+#define S_RXURGMODE    5
+#define V_RXURGMODE(x) ((x) << S_RXURGMODE)
+#define F_RXURGMODE    V_RXURGMODE(1U)
+
+#define S_TXURGMODE    4
+#define V_TXURGMODE(x) ((x) << S_TXURGMODE)
+#define F_TXURGMODE    V_TXURGMODE(1U)
+
+#define S_CNGCTRLMODE    2
+#define M_CNGCTRLMODE    0x3U
+#define V_CNGCTRLMODE(x) ((x) << S_CNGCTRLMODE)
+#define G_CNGCTRLMODE(x) (((x) >> S_CNGCTRLMODE) & M_CNGCTRLMODE)
+
+#define S_RXCOALESCEENABLE    1
+#define V_RXCOALESCEENABLE(x) ((x) << S_RXCOALESCEENABLE)
+#define F_RXCOALESCEENABLE    V_RXCOALESCEENABLE(1U)
+
+#define S_RXCOALESCEPSHEN    0
+#define V_RXCOALESCEPSHEN(x) ((x) << S_RXCOALESCEPSHEN)
+#define F_RXCOALESCEPSHEN    V_RXCOALESCEPSHEN(1U)
+
+#define A_TP_PARA_REG4 0x7d70
+
+#define S_HIGHSPEEDCFG    24
+#define M_HIGHSPEEDCFG    0xffU
+#define V_HIGHSPEEDCFG(x) ((x) << S_HIGHSPEEDCFG)
+#define G_HIGHSPEEDCFG(x) (((x) >> S_HIGHSPEEDCFG) & M_HIGHSPEEDCFG)
+
+#define S_NEWRENOCFG    16
+#define M_NEWRENOCFG    0xffU
+#define V_NEWRENOCFG(x) ((x) << S_NEWRENOCFG)
+#define G_NEWRENOCFG(x) (((x) >> S_NEWRENOCFG) & M_NEWRENOCFG)
+
+#define S_TAHOECFG    8
+#define M_TAHOECFG    0xffU
+#define V_TAHOECFG(x) ((x) << S_TAHOECFG)
+#define G_TAHOECFG(x) (((x) >> S_TAHOECFG) & M_TAHOECFG)
+
+#define S_RENOCFG    0
+#define M_RENOCFG    0xffU
+#define V_RENOCFG(x) ((x) << S_RENOCFG)
+#define G_RENOCFG(x) (((x) >> S_RENOCFG) & M_RENOCFG)
+
+#define S_IDLECWNDHIGHSPEED    28
+#define V_IDLECWNDHIGHSPEED(x) ((x) << S_IDLECWNDHIGHSPEED)
+#define F_IDLECWNDHIGHSPEED    V_IDLECWNDHIGHSPEED(1U)
+
+#define S_RXMTCWNDHIGHSPEED    27
+#define V_RXMTCWNDHIGHSPEED(x) ((x) << S_RXMTCWNDHIGHSPEED)
+#define F_RXMTCWNDHIGHSPEED    V_RXMTCWNDHIGHSPEED(1U)
+
+#define S_OVERDRIVEHIGHSPEED    25
+#define M_OVERDRIVEHIGHSPEED    0x3U
+#define V_OVERDRIVEHIGHSPEED(x) ((x) << S_OVERDRIVEHIGHSPEED)
+#define G_OVERDRIVEHIGHSPEED(x) (((x) >> S_OVERDRIVEHIGHSPEED) & M_OVERDRIVEHIGHSPEED)
+
+#define S_BYTECOUNTHIGHSPEED    24
+#define V_BYTECOUNTHIGHSPEED(x) ((x) << S_BYTECOUNTHIGHSPEED)
+#define F_BYTECOUNTHIGHSPEED    V_BYTECOUNTHIGHSPEED(1U)
+
+#define S_IDLECWNDNEWRENO    20
+#define V_IDLECWNDNEWRENO(x) ((x) << S_IDLECWNDNEWRENO)
+#define F_IDLECWNDNEWRENO    V_IDLECWNDNEWRENO(1U)
+
+#define S_RXMTCWNDNEWRENO    19
+#define V_RXMTCWNDNEWRENO(x) ((x) << S_RXMTCWNDNEWRENO)
+#define F_RXMTCWNDNEWRENO    V_RXMTCWNDNEWRENO(1U)
+
+#define S_OVERDRIVENEWRENO    17
+#define M_OVERDRIVENEWRENO    0x3U
+#define V_OVERDRIVENEWRENO(x) ((x) << S_OVERDRIVENEWRENO)
+#define G_OVERDRIVENEWRENO(x) (((x) >> S_OVERDRIVENEWRENO) & M_OVERDRIVENEWRENO)
+
+#define S_BYTECOUNTNEWRENO    16
+#define V_BYTECOUNTNEWRENO(x) ((x) << S_BYTECOUNTNEWRENO)
+#define F_BYTECOUNTNEWRENO    V_BYTECOUNTNEWRENO(1U)
+
+#define S_IDLECWNDTAHOE    12
+#define V_IDLECWNDTAHOE(x) ((x) << S_IDLECWNDTAHOE)
+#define F_IDLECWNDTAHOE    V_IDLECWNDTAHOE(1U)
+
+#define S_RXMTCWNDTAHOE    11
+#define V_RXMTCWNDTAHOE(x) ((x) << S_RXMTCWNDTAHOE)
+#define F_RXMTCWNDTAHOE    V_RXMTCWNDTAHOE(1U)
+
+#define S_OVERDRIVETAHOE    9
+#define M_OVERDRIVETAHOE    0x3U
+#define V_OVERDRIVETAHOE(x) ((x) << S_OVERDRIVETAHOE)
+#define G_OVERDRIVETAHOE(x) (((x) >> S_OVERDRIVETAHOE) & M_OVERDRIVETAHOE)
+
+#define S_BYTECOUNTTAHOE    8
+#define V_BYTECOUNTTAHOE(x) ((x) << S_BYTECOUNTTAHOE)
+#define F_BYTECOUNTTAHOE    V_BYTECOUNTTAHOE(1U)
+
+#define S_IDLECWNDRENO    4
+#define V_IDLECWNDRENO(x) ((x) << S_IDLECWNDRENO)
+#define F_IDLECWNDRENO    V_IDLECWNDRENO(1U)
+
+#define S_RXMTCWNDRENO    3
+#define V_RXMTCWNDRENO(x) ((x) << S_RXMTCWNDRENO)
+#define F_RXMTCWNDRENO    V_RXMTCWNDRENO(1U)
+
+#define S_OVERDRIVERENO    1
+#define M_OVERDRIVERENO    0x3U
+#define V_OVERDRIVERENO(x) ((x) << S_OVERDRIVERENO)
+#define G_OVERDRIVERENO(x) (((x) >> S_OVERDRIVERENO) & M_OVERDRIVERENO)
+
+#define S_BYTECOUNTRENO    0
+#define V_BYTECOUNTRENO(x) ((x) << S_BYTECOUNTRENO)
+#define F_BYTECOUNTRENO    V_BYTECOUNTRENO(1U)
+
+#define A_TP_PARA_REG5 0x7d74
+
+#define S_INDICATESIZE    16
+#define M_INDICATESIZE    0xffffU
+#define V_INDICATESIZE(x) ((x) << S_INDICATESIZE)
+#define G_INDICATESIZE(x) (((x) >> S_INDICATESIZE) & M_INDICATESIZE)
+
+#define S_MAXPROXYSIZE    12
+#define M_MAXPROXYSIZE    0xfU
+#define V_MAXPROXYSIZE(x) ((x) << S_MAXPROXYSIZE)
+#define G_MAXPROXYSIZE(x) (((x) >> S_MAXPROXYSIZE) & M_MAXPROXYSIZE)
+
+#define S_ENABLEREADPDU    11
+#define V_ENABLEREADPDU(x) ((x) << S_ENABLEREADPDU)
+#define F_ENABLEREADPDU    V_ENABLEREADPDU(1U)
+
+#define S_RXREADAHEAD    10
+#define V_RXREADAHEAD(x) ((x) << S_RXREADAHEAD)
+#define F_RXREADAHEAD    V_RXREADAHEAD(1U)
+
+#define S_EMPTYRQENABLE    9
+#define V_EMPTYRQENABLE(x) ((x) << S_EMPTYRQENABLE)
+#define F_EMPTYRQENABLE    V_EMPTYRQENABLE(1U)
+
+#define S_SCHDENABLE    8
+#define V_SCHDENABLE(x) ((x) << S_SCHDENABLE)
+#define F_SCHDENABLE    V_SCHDENABLE(1U)
+
+#define S_REARMDDPOFFSET    4
+#define V_REARMDDPOFFSET(x) ((x) << S_REARMDDPOFFSET)
+#define F_REARMDDPOFFSET    V_REARMDDPOFFSET(1U)
+
+#define S_RESETDDPOFFSET    3
+#define V_RESETDDPOFFSET(x) ((x) << S_RESETDDPOFFSET)
+#define F_RESETDDPOFFSET    V_RESETDDPOFFSET(1U)
+
+#define S_ONFLYDDPENABLE    2
+#define V_ONFLYDDPENABLE(x) ((x) << S_ONFLYDDPENABLE)
+#define F_ONFLYDDPENABLE    V_ONFLYDDPENABLE(1U)
+
+#define S_DACKTIMERSPIN    1
+#define V_DACKTIMERSPIN(x) ((x) << S_DACKTIMERSPIN)
+#define F_DACKTIMERSPIN    V_DACKTIMERSPIN(1U)
+
+#define S_PUSHTIMERENABLE    0
+#define V_PUSHTIMERENABLE(x) ((x) << S_PUSHTIMERENABLE)
+#define F_PUSHTIMERENABLE    V_PUSHTIMERENABLE(1U)
+
+#define S_ENABLEXOFFPDU    7
+#define V_ENABLEXOFFPDU(x) ((x) << S_ENABLEXOFFPDU)
+#define F_ENABLEXOFFPDU    V_ENABLEXOFFPDU(1U)
+
+#define S_ENABLENEWFAR    6
+#define V_ENABLENEWFAR(x) ((x) << S_ENABLENEWFAR)
+#define F_ENABLENEWFAR    V_ENABLENEWFAR(1U)
+
+#define S_ENABLEFRAGCHECK    5
+#define V_ENABLEFRAGCHECK(x) ((x) << S_ENABLEFRAGCHECK)
+#define F_ENABLEFRAGCHECK    V_ENABLEFRAGCHECK(1U)
+
+#define A_TP_PARA_REG6 0x7d78
+
+#define S_TXPDUSIZEADJ    24
+#define M_TXPDUSIZEADJ    0xffU
+#define V_TXPDUSIZEADJ(x) ((x) << S_TXPDUSIZEADJ)
+#define G_TXPDUSIZEADJ(x) (((x) >> S_TXPDUSIZEADJ) & M_TXPDUSIZEADJ)
+
+#define S_LIMITEDTRANSMIT    20
+#define M_LIMITEDTRANSMIT    0xfU
+#define V_LIMITEDTRANSMIT(x) ((x) << S_LIMITEDTRANSMIT)
+#define G_LIMITEDTRANSMIT(x) (((x) >> S_LIMITEDTRANSMIT) & M_LIMITEDTRANSMIT)
+
+#define S_ENABLECSAV    19
+#define V_ENABLECSAV(x) ((x) << S_ENABLECSAV)
+#define F_ENABLECSAV    V_ENABLECSAV(1U)
+
+#define S_ENABLEDEFERPDU    18
+#define V_ENABLEDEFERPDU(x) ((x) << S_ENABLEDEFERPDU)
+#define F_ENABLEDEFERPDU    V_ENABLEDEFERPDU(1U)
+
+#define S_ENABLEFLUSH    17
+#define V_ENABLEFLUSH(x) ((x) << S_ENABLEFLUSH)
+#define F_ENABLEFLUSH    V_ENABLEFLUSH(1U)
+
+#define S_ENABLEBYTEPERSIST    16
+#define V_ENABLEBYTEPERSIST(x) ((x) << S_ENABLEBYTEPERSIST)
+#define F_ENABLEBYTEPERSIST    V_ENABLEBYTEPERSIST(1U)
+
+#define S_DISABLETMOCNG    15
+#define V_DISABLETMOCNG(x) ((x) << S_DISABLETMOCNG)
+#define F_DISABLETMOCNG    V_DISABLETMOCNG(1U)
+
+#define S_TXREADAHEAD    14
+#define V_TXREADAHEAD(x) ((x) << S_TXREADAHEAD)
+#define F_TXREADAHEAD    V_TXREADAHEAD(1U)
+
+#define S_ALLOWEXEPTION    13
+#define V_ALLOWEXEPTION(x) ((x) << S_ALLOWEXEPTION)
+#define F_ALLOWEXEPTION    V_ALLOWEXEPTION(1U)
+
+#define S_ENABLEDEFERACK    12
+#define V_ENABLEDEFERACK(x) ((x) << S_ENABLEDEFERACK)
+#define F_ENABLEDEFERACK    V_ENABLEDEFERACK(1U)
+
+#define S_ENABLEESND    11
+#define V_ENABLEESND(x) ((x) << S_ENABLEESND)
+#define F_ENABLEESND    V_ENABLEESND(1U)
+
+#define S_ENABLECSND    10
+#define V_ENABLECSND(x) ((x) << S_ENABLECSND)
+#define F_ENABLECSND    V_ENABLECSND(1U)
+
+#define S_ENABLEPDUE    9
+#define V_ENABLEPDUE(x) ((x) << S_ENABLEPDUE)
+#define F_ENABLEPDUE    V_ENABLEPDUE(1U)
+
+#define S_ENABLEPDUC    8
+#define V_ENABLEPDUC(x) ((x) << S_ENABLEPDUC)
+#define F_ENABLEPDUC    V_ENABLEPDUC(1U)
+
+#define S_ENABLEBUFI    7
+#define V_ENABLEBUFI(x) ((x) << S_ENABLEBUFI)
+#define F_ENABLEBUFI    V_ENABLEBUFI(1U)
+
+#define S_ENABLEBUFE    6
+#define V_ENABLEBUFE(x) ((x) << S_ENABLEBUFE)
+#define F_ENABLEBUFE    V_ENABLEBUFE(1U)
+
+#define S_ENABLEDEFER    5
+#define V_ENABLEDEFER(x) ((x) << S_ENABLEDEFER)
+#define F_ENABLEDEFER    V_ENABLEDEFER(1U)
+
+#define S_ENABLECLEARRXMTOOS    4
+#define V_ENABLECLEARRXMTOOS(x) ((x) << S_ENABLECLEARRXMTOOS)
+#define F_ENABLECLEARRXMTOOS    V_ENABLECLEARRXMTOOS(1U)
+
+#define S_DISABLEPDUCNG    3
+#define V_DISABLEPDUCNG(x) ((x) << S_DISABLEPDUCNG)
+#define F_DISABLEPDUCNG    V_DISABLEPDUCNG(1U)
+
+#define S_DISABLEPDUTIMEOUT    2
+#define V_DISABLEPDUTIMEOUT(x) ((x) << S_DISABLEPDUTIMEOUT)
+#define F_DISABLEPDUTIMEOUT    V_DISABLEPDUTIMEOUT(1U)
+
+#define S_DISABLEPDURXMT    1
+#define V_DISABLEPDURXMT(x) ((x) << S_DISABLEPDURXMT)
+#define F_DISABLEPDURXMT    V_DISABLEPDURXMT(1U)
+
+#define S_DISABLEPDUXMT    0
+#define V_DISABLEPDUXMT(x) ((x) << S_DISABLEPDUXMT)
+#define F_DISABLEPDUXMT    V_DISABLEPDUXMT(1U)
+
+#define S_DISABLEPDUACK    20
+#define V_DISABLEPDUACK(x) ((x) << S_DISABLEPDUACK)
+#define F_DISABLEPDUACK    V_DISABLEPDUACK(1U)
+
+#define A_TP_PARA_REG7 0x7d7c
+
+#define S_PMMAXXFERLEN1    16
+#define M_PMMAXXFERLEN1    0xffffU
+#define V_PMMAXXFERLEN1(x) ((x) << S_PMMAXXFERLEN1)
+#define G_PMMAXXFERLEN1(x) (((x) >> S_PMMAXXFERLEN1) & M_PMMAXXFERLEN1)
+
+#define S_PMMAXXFERLEN0    0
+#define M_PMMAXXFERLEN0    0xffffU
+#define V_PMMAXXFERLEN0(x) ((x) << S_PMMAXXFERLEN0)
+#define G_PMMAXXFERLEN0(x) (((x) >> S_PMMAXXFERLEN0) & M_PMMAXXFERLEN0)
+
+#define A_TP_ENG_CONFIG 0x7d80
+
+#define S_TABLELATENCYDONE    28
+#define M_TABLELATENCYDONE    0xfU
+#define V_TABLELATENCYDONE(x) ((x) << S_TABLELATENCYDONE)
+#define G_TABLELATENCYDONE(x) (((x) >> S_TABLELATENCYDONE) & M_TABLELATENCYDONE)
+
+#define S_TABLELATENCYSTART    24
+#define M_TABLELATENCYSTART    0xfU
+#define V_TABLELATENCYSTART(x) ((x) << S_TABLELATENCYSTART)
+#define G_TABLELATENCYSTART(x) (((x) >> S_TABLELATENCYSTART) & M_TABLELATENCYSTART)
+
+#define S_ENGINELATENCYDELTA    16
+#define M_ENGINELATENCYDELTA    0xfU
+#define V_ENGINELATENCYDELTA(x) ((x) << S_ENGINELATENCYDELTA)
+#define G_ENGINELATENCYDELTA(x) (((x) >> S_ENGINELATENCYDELTA) & M_ENGINELATENCYDELTA)
+
+#define S_ENGINELATENCYMMGR    12
+#define M_ENGINELATENCYMMGR    0xfU
+#define V_ENGINELATENCYMMGR(x) ((x) << S_ENGINELATENCYMMGR)
+#define G_ENGINELATENCYMMGR(x) (((x) >> S_ENGINELATENCYMMGR) & M_ENGINELATENCYMMGR)
+
+#define S_ENGINELATENCYWIREIP6    8
+#define M_ENGINELATENCYWIREIP6    0xfU
+#define V_ENGINELATENCYWIREIP6(x) ((x) << S_ENGINELATENCYWIREIP6)
+#define G_ENGINELATENCYWIREIP6(x) (((x) >> S_ENGINELATENCYWIREIP6) & M_ENGINELATENCYWIREIP6)
+
+#define S_ENGINELATENCYWIRE    4
+#define M_ENGINELATENCYWIRE    0xfU
+#define V_ENGINELATENCYWIRE(x) ((x) << S_ENGINELATENCYWIRE)
+#define G_ENGINELATENCYWIRE(x) (((x) >> S_ENGINELATENCYWIRE) & M_ENGINELATENCYWIRE)
+
+#define S_ENGINELATENCYBASE    0
+#define M_ENGINELATENCYBASE    0xfU
+#define V_ENGINELATENCYBASE(x) ((x) << S_ENGINELATENCYBASE)
+#define G_ENGINELATENCYBASE(x) (((x) >> S_ENGINELATENCYBASE) & M_ENGINELATENCYBASE)
+
+#define A_TP_ERR_CONFIG 0x7d8c
+
+#define S_TNLERRORPING    30
+#define V_TNLERRORPING(x) ((x) << S_TNLERRORPING)
+#define F_TNLERRORPING    V_TNLERRORPING(1U)
+
+#define S_TNLERRORCSUM    29
+#define V_TNLERRORCSUM(x) ((x) << S_TNLERRORCSUM)
+#define F_TNLERRORCSUM    V_TNLERRORCSUM(1U)
+
+#define S_TNLERRORCSUMIP    28
+#define V_TNLERRORCSUMIP(x) ((x) << S_TNLERRORCSUMIP)
+#define F_TNLERRORCSUMIP    V_TNLERRORCSUMIP(1U)
+
+#define S_TNLERRORTCPOPT    25
+#define V_TNLERRORTCPOPT(x) ((x) << S_TNLERRORTCPOPT)
+#define F_TNLERRORTCPOPT    V_TNLERRORTCPOPT(1U)
+
+#define S_TNLERRORPKTLEN    24
+#define V_TNLERRORPKTLEN(x) ((x) << S_TNLERRORPKTLEN)
+#define F_TNLERRORPKTLEN    V_TNLERRORPKTLEN(1U)
+
+#define S_TNLERRORTCPHDRLEN    23
+#define V_TNLERRORTCPHDRLEN(x) ((x) << S_TNLERRORTCPHDRLEN)
+#define F_TNLERRORTCPHDRLEN    V_TNLERRORTCPHDRLEN(1U)
+
+#define S_TNLERRORIPHDRLEN    22
+#define V_TNLERRORIPHDRLEN(x) ((x) << S_TNLERRORIPHDRLEN)
+#define F_TNLERRORIPHDRLEN    V_TNLERRORIPHDRLEN(1U)
+
+#define S_TNLERRORETHHDRLEN    21
+#define V_TNLERRORETHHDRLEN(x) ((x) << S_TNLERRORETHHDRLEN)
+#define F_TNLERRORETHHDRLEN    V_TNLERRORETHHDRLEN(1U)
+
+#define S_TNLERRORATTACK    20
+#define V_TNLERRORATTACK(x) ((x) << S_TNLERRORATTACK)
+#define F_TNLERRORATTACK    V_TNLERRORATTACK(1U)
+
+#define S_TNLERRORFRAG    19
+#define V_TNLERRORFRAG(x) ((x) << S_TNLERRORFRAG)
+#define F_TNLERRORFRAG    V_TNLERRORFRAG(1U)
+
+#define S_TNLERRORIPVER    18
+#define V_TNLERRORIPVER(x) ((x) << S_TNLERRORIPVER)
+#define F_TNLERRORIPVER    V_TNLERRORIPVER(1U)
+
+#define S_TNLERRORMAC    17
+#define V_TNLERRORMAC(x) ((x) << S_TNLERRORMAC)
+#define F_TNLERRORMAC    V_TNLERRORMAC(1U)
+
+#define S_TNLERRORANY    16
+#define V_TNLERRORANY(x) ((x) << S_TNLERRORANY)
+#define F_TNLERRORANY    V_TNLERRORANY(1U)
+
+#define S_DROPERRORPING    14
+#define V_DROPERRORPING(x) ((x) << S_DROPERRORPING)
+#define F_DROPERRORPING    V_DROPERRORPING(1U)
+
+#define S_DROPERRORCSUM    13
+#define V_DROPERRORCSUM(x) ((x) << S_DROPERRORCSUM)
+#define F_DROPERRORCSUM    V_DROPERRORCSUM(1U)
+
+#define S_DROPERRORCSUMIP    12
+#define V_DROPERRORCSUMIP(x) ((x) << S_DROPERRORCSUMIP)
+#define F_DROPERRORCSUMIP    V_DROPERRORCSUMIP(1U)
+
+#define S_DROPERRORTCPOPT    9
+#define V_DROPERRORTCPOPT(x) ((x) << S_DROPERRORTCPOPT)
+#define F_DROPERRORTCPOPT    V_DROPERRORTCPOPT(1U)
+
+#define S_DROPERRORPKTLEN    8
+#define V_DROPERRORPKTLEN(x) ((x) << S_DROPERRORPKTLEN)
+#define F_DROPERRORPKTLEN    V_DROPERRORPKTLEN(1U)
+
+#define S_DROPERRORTCPHDRLEN    7
+#define V_DROPERRORTCPHDRLEN(x) ((x) << S_DROPERRORTCPHDRLEN)
+#define F_DROPERRORTCPHDRLEN    V_DROPERRORTCPHDRLEN(1U)
+
+#define S_DROPERRORIPHDRLEN    6
+#define V_DROPERRORIPHDRLEN(x) ((x) << S_DROPERRORIPHDRLEN)
+#define F_DROPERRORIPHDRLEN    V_DROPERRORIPHDRLEN(1U)
+
+#define S_DROPERRORETHHDRLEN    5
+#define V_DROPERRORETHHDRLEN(x) ((x) << S_DROPERRORETHHDRLEN)
+#define F_DROPERRORETHHDRLEN    V_DROPERRORETHHDRLEN(1U)
+
+#define S_DROPERRORATTACK    4
+#define V_DROPERRORATTACK(x) ((x) << S_DROPERRORATTACK)
+#define F_DROPERRORATTACK    V_DROPERRORATTACK(1U)
+
+#define S_DROPERRORFRAG    3
+#define V_DROPERRORFRAG(x) ((x) << S_DROPERRORFRAG)
+#define F_DROPERRORFRAG    V_DROPERRORFRAG(1U)
+
+#define S_DROPERRORIPVER    2
+#define V_DROPERRORIPVER(x) ((x) << S_DROPERRORIPVER)
+#define F_DROPERRORIPVER    V_DROPERRORIPVER(1U)
+
+#define S_DROPERRORMAC    1
+#define V_DROPERRORMAC(x) ((x) << S_DROPERRORMAC)
+#define F_DROPERRORMAC    V_DROPERRORMAC(1U)
+
+#define S_DROPERRORANY    0
+#define V_DROPERRORANY(x) ((x) << S_DROPERRORANY)
+#define F_DROPERRORANY    V_DROPERRORANY(1U)
+
+#define S_TNLERRORFPMA    31
+#define V_TNLERRORFPMA(x) ((x) << S_TNLERRORFPMA)
+#define F_TNLERRORFPMA    V_TNLERRORFPMA(1U)
+
+#define S_DROPERRORFPMA    15
+#define V_DROPERRORFPMA(x) ((x) << S_DROPERRORFPMA)
+#define F_DROPERRORFPMA    V_DROPERRORFPMA(1U)
+
+#define A_TP_TIMER_RESOLUTION 0x7d90
+
+#define S_TIMERRESOLUTION    16
+#define M_TIMERRESOLUTION    0xffU
+#define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION)
+#define G_TIMERRESOLUTION(x) (((x) >> S_TIMERRESOLUTION) & M_TIMERRESOLUTION)
+
+#define S_TIMESTAMPRESOLUTION    8
+#define M_TIMESTAMPRESOLUTION    0xffU
+#define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION)
+#define G_TIMESTAMPRESOLUTION(x) (((x) >> S_TIMESTAMPRESOLUTION) & M_TIMESTAMPRESOLUTION)
+
+#define S_DELAYEDACKRESOLUTION    0
+#define M_DELAYEDACKRESOLUTION    0xffU
+#define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)
+#define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & M_DELAYEDACKRESOLUTION)
+
+#define A_TP_MSL 0x7d94
+
+#define S_MSL    0
+#define M_MSL    0x3fffffffU
+#define V_MSL(x) ((x) << S_MSL)
+#define G_MSL(x) (((x) >> S_MSL) & M_MSL)
+
+#define A_TP_RXT_MIN 0x7d98
+
+#define S_RXTMIN    0
+#define M_RXTMIN    0x3fffffffU
+#define V_RXTMIN(x) ((x) << S_RXTMIN)
+#define G_RXTMIN(x) (((x) >> S_RXTMIN) & M_RXTMIN)
+
+#define A_TP_RXT_MAX 0x7d9c
+
+#define S_RXTMAX    0
+#define M_RXTMAX    0x3fffffffU
+#define V_RXTMAX(x) ((x) << S_RXTMAX)
+#define G_RXTMAX(x) (((x) >> S_RXTMAX) & M_RXTMAX)
+
+#define A_TP_PERS_MIN 0x7da0
+
+#define S_PERSMIN    0
+#define M_PERSMIN    0x3fffffffU
+#define V_PERSMIN(x) ((x) << S_PERSMIN)
+#define G_PERSMIN(x) (((x) >> S_PERSMIN) & M_PERSMIN)
+
+#define A_TP_PERS_MAX 0x7da4
+
+#define S_PERSMAX    0
+#define M_PERSMAX    0x3fffffffU
+#define V_PERSMAX(x) ((x) << S_PERSMAX)
+#define G_PERSMAX(x) (((x) >> S_PERSMAX) & M_PERSMAX)
+
+#define A_TP_KEEP_IDLE 0x7da8
+
+#define S_KEEPALIVEIDLE    0
+#define M_KEEPALIVEIDLE    0x3fffffffU
+#define V_KEEPALIVEIDLE(x) ((x) << S_KEEPALIVEIDLE)
+#define G_KEEPALIVEIDLE(x) (((x) >> S_KEEPALIVEIDLE) & M_KEEPALIVEIDLE)
+
+#define A_TP_KEEP_INTVL 0x7dac
+
+#define S_KEEPALIVEINTVL    0
+#define M_KEEPALIVEINTVL    0x3fffffffU
+#define V_KEEPALIVEINTVL(x) ((x) << S_KEEPALIVEINTVL)
+#define G_KEEPALIVEINTVL(x) (((x) >> S_KEEPALIVEINTVL) & M_KEEPALIVEINTVL)
+
+#define A_TP_INIT_SRTT 0x7db0
+
+#define S_MAXRTT    16
+#define M_MAXRTT    0xffffU
+#define V_MAXRTT(x) ((x) << S_MAXRTT)
+#define G_MAXRTT(x) (((x) >> S_MAXRTT) & M_MAXRTT)
+
+#define S_INITSRTT    0
+#define M_INITSRTT    0xffffU
+#define V_INITSRTT(x) ((x) << S_INITSRTT)
+#define G_INITSRTT(x) (((x) >> S_INITSRTT) & M_INITSRTT)
+
+#define A_TP_DACK_TIMER 0x7db4
+
+#define S_DACKTIME    0
+#define M_DACKTIME    0xfffU
+#define V_DACKTIME(x) ((x) << S_DACKTIME)
+#define G_DACKTIME(x) (((x) >> S_DACKTIME) & M_DACKTIME)
+
+#define A_TP_FINWAIT2_TIMER 0x7db8
+
+#define S_FINWAIT2TIME    0
+#define M_FINWAIT2TIME    0x3fffffffU
+#define V_FINWAIT2TIME(x) ((x) << S_FINWAIT2TIME)
+#define G_FINWAIT2TIME(x) (((x) >> S_FINWAIT2TIME) & M_FINWAIT2TIME)
+
+#define A_TP_FAST_FINWAIT2_TIMER 0x7dbc
+
+#define S_FASTFINWAIT2TIME    0
+#define M_FASTFINWAIT2TIME    0x3fffffffU
+#define V_FASTFINWAIT2TIME(x) ((x) << S_FASTFINWAIT2TIME)
+#define G_FASTFINWAIT2TIME(x) (((x) >> S_FASTFINWAIT2TIME) & M_FASTFINWAIT2TIME)
+
+#define A_TP_SHIFT_CNT 0x7dc0
+
+#define S_SYNSHIFTMAX    24
+#define M_SYNSHIFTMAX    0xffU
+#define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX)
+#define G_SYNSHIFTMAX(x) (((x) >> S_SYNSHIFTMAX) & M_SYNSHIFTMAX)
+
+#define S_RXTSHIFTMAXR1    20
+#define M_RXTSHIFTMAXR1    0xfU
+#define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1)
+#define G_RXTSHIFTMAXR1(x) (((x) >> S_RXTSHIFTMAXR1) & M_RXTSHIFTMAXR1)
+
+#define S_RXTSHIFTMAXR2    16
+#define M_RXTSHIFTMAXR2    0xfU
+#define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2)
+#define G_RXTSHIFTMAXR2(x) (((x) >> S_RXTSHIFTMAXR2) & M_RXTSHIFTMAXR2)
+
+#define S_PERSHIFTBACKOFFMAX    12
+#define M_PERSHIFTBACKOFFMAX    0xfU
+#define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX)
+#define G_PERSHIFTBACKOFFMAX(x) (((x) >> S_PERSHIFTBACKOFFMAX) & M_PERSHIFTBACKOFFMAX)
+
+#define S_PERSHIFTMAX    8
+#define M_PERSHIFTMAX    0xfU
+#define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX)
+#define G_PERSHIFTMAX(x) (((x) >> S_PERSHIFTMAX) & M_PERSHIFTMAX)
+
+#define S_KEEPALIVEMAXR1    4
+#define M_KEEPALIVEMAXR1    0xfU
+#define V_KEEPALIVEMAXR1(x) ((x) << S_KEEPALIVEMAXR1)
+#define G_KEEPALIVEMAXR1(x) (((x) >> S_KEEPALIVEMAXR1) & M_KEEPALIVEMAXR1)
+
+#define S_KEEPALIVEMAXR2    0
+#define M_KEEPALIVEMAXR2    0xfU
+#define V_KEEPALIVEMAXR2(x) ((x) << S_KEEPALIVEMAXR2)
+#define G_KEEPALIVEMAXR2(x) (((x) >> S_KEEPALIVEMAXR2) & M_KEEPALIVEMAXR2)
+
+#define A_TP_TM_CONFIG 0x7dc4
+
+#define S_CMTIMERMAXNUM    0
+#define M_CMTIMERMAXNUM    0x7U
+#define V_CMTIMERMAXNUM(x) ((x) << S_CMTIMERMAXNUM)
+#define G_CMTIMERMAXNUM(x) (((x) >> S_CMTIMERMAXNUM) & M_CMTIMERMAXNUM)
+
+#define A_TP_TIME_LO 0x7dc8
+#define A_TP_TIME_HI 0x7dcc
+#define A_TP_PORT_MTU_0 0x7dd0
+
+#define S_PORT1MTUVALUE    16
+#define M_PORT1MTUVALUE    0xffffU
+#define V_PORT1MTUVALUE(x) ((x) << S_PORT1MTUVALUE)
+#define G_PORT1MTUVALUE(x) (((x) >> S_PORT1MTUVALUE) & M_PORT1MTUVALUE)
+
+#define S_PORT0MTUVALUE    0
+#define M_PORT0MTUVALUE    0xffffU
+#define V_PORT0MTUVALUE(x) ((x) << S_PORT0MTUVALUE)
+#define G_PORT0MTUVALUE(x) (((x) >> S_PORT0MTUVALUE) & M_PORT0MTUVALUE)
+
+#define A_TP_PORT_MTU_1 0x7dd4
+
+#define S_PORT3MTUVALUE    16
+#define M_PORT3MTUVALUE    0xffffU
+#define V_PORT3MTUVALUE(x) ((x) << S_PORT3MTUVALUE)
+#define G_PORT3MTUVALUE(x) (((x) >> S_PORT3MTUVALUE) & M_PORT3MTUVALUE)
+
+#define S_PORT2MTUVALUE    0
+#define M_PORT2MTUVALUE    0xffffU
+#define V_PORT2MTUVALUE(x) ((x) << S_PORT2MTUVALUE)
+#define G_PORT2MTUVALUE(x) (((x) >> S_PORT2MTUVALUE) & M_PORT2MTUVALUE)
+
+#define A_TP_PACE_TABLE 0x7dd8
+#define A_TP_CCTRL_TABLE 0x7ddc
+
+#define S_ROWINDEX    16
+#define M_ROWINDEX    0xffffU
+#define V_ROWINDEX(x) ((x) << S_ROWINDEX)
+#define G_ROWINDEX(x) (((x) >> S_ROWINDEX) & M_ROWINDEX)
+
+#define S_ROWVALUE    0
+#define M_ROWVALUE    0xffffU
+#define V_ROWVALUE(x) ((x) << S_ROWVALUE)
+#define G_ROWVALUE(x) (((x) >> S_ROWVALUE) & M_ROWVALUE)
+
+#define A_TP_MTU_TABLE 0x7de4
+
+#define S_MTUINDEX    24
+#define M_MTUINDEX    0xffU
+#define V_MTUINDEX(x) ((x) << S_MTUINDEX)
+#define G_MTUINDEX(x) (((x) >> S_MTUINDEX) & M_MTUINDEX)
+
+#define S_MTUWIDTH    16
+#define M_MTUWIDTH    0xfU
+#define V_MTUWIDTH(x) ((x) << S_MTUWIDTH)
+#define G_MTUWIDTH(x) (((x) >> S_MTUWIDTH) & M_MTUWIDTH)
+
+#define S_MTUVALUE    0
+#define M_MTUVALUE    0x3fffU
+#define V_MTUVALUE(x) ((x) << S_MTUVALUE)
+#define G_MTUVALUE(x) (((x) >> S_MTUVALUE) & M_MTUVALUE)
+
+#define A_TP_ULP_TABLE 0x7de8
+
+#define S_ULPTYPE7FIELD    28
+#define M_ULPTYPE7FIELD    0xfU
+#define V_ULPTYPE7FIELD(x) ((x) << S_ULPTYPE7FIELD)
+#define G_ULPTYPE7FIELD(x) (((x) >> S_ULPTYPE7FIELD) & M_ULPTYPE7FIELD)
+
+#define S_ULPTYPE6FIELD    24
+#define M_ULPTYPE6FIELD    0xfU
+#define V_ULPTYPE6FIELD(x) ((x) << S_ULPTYPE6FIELD)
+#define G_ULPTYPE6FIELD(x) (((x) >> S_ULPTYPE6FIELD) & M_ULPTYPE6FIELD)
+
+#define S_ULPTYPE5FIELD    20
+#define M_ULPTYPE5FIELD    0xfU
+#define V_ULPTYPE5FIELD(x) ((x) << S_ULPTYPE5FIELD)
+#define G_ULPTYPE5FIELD(x) (((x) >> S_ULPTYPE5FIELD) & M_ULPTYPE5FIELD)
+
+#define S_ULPTYPE4FIELD    16
+#define M_ULPTYPE4FIELD    0xfU
+#define V_ULPTYPE4FIELD(x) ((x) << S_ULPTYPE4FIELD)
+#define G_ULPTYPE4FIELD(x) (((x) >> S_ULPTYPE4FIELD) & M_ULPTYPE4FIELD)
+
+#define S_ULPTYPE3FIELD    12
+#define M_ULPTYPE3FIELD    0xfU
+#define V_ULPTYPE3FIELD(x) ((x) << S_ULPTYPE3FIELD)
+#define G_ULPTYPE3FIELD(x) (((x) >> S_ULPTYPE3FIELD) & M_ULPTYPE3FIELD)
+
+#define S_ULPTYPE2FIELD    8
+#define M_ULPTYPE2FIELD    0xfU
+#define V_ULPTYPE2FIELD(x) ((x) << S_ULPTYPE2FIELD)
+#define G_ULPTYPE2FIELD(x) (((x) >> S_ULPTYPE2FIELD) & M_ULPTYPE2FIELD)
+
+#define S_ULPTYPE1FIELD    4
+#define M_ULPTYPE1FIELD    0xfU
+#define V_ULPTYPE1FIELD(x) ((x) << S_ULPTYPE1FIELD)
+#define G_ULPTYPE1FIELD(x) (((x) >> S_ULPTYPE1FIELD) & M_ULPTYPE1FIELD)
+
+#define S_ULPTYPE0FIELD    0
+#define M_ULPTYPE0FIELD    0xfU
+#define V_ULPTYPE0FIELD(x) ((x) << S_ULPTYPE0FIELD)
+#define G_ULPTYPE0FIELD(x) (((x) >> S_ULPTYPE0FIELD) & M_ULPTYPE0FIELD)
+
+#define A_TP_RSS_LKP_TABLE 0x7dec
+
+#define S_LKPTBLROWVLD    31
+#define V_LKPTBLROWVLD(x) ((x) << S_LKPTBLROWVLD)
+#define F_LKPTBLROWVLD    V_LKPTBLROWVLD(1U)
+
+#define S_LKPTBLROWIDX    20
+#define M_LKPTBLROWIDX    0x3ffU
+#define V_LKPTBLROWIDX(x) ((x) << S_LKPTBLROWIDX)
+#define G_LKPTBLROWIDX(x) (((x) >> S_LKPTBLROWIDX) & M_LKPTBLROWIDX)
+
+#define S_LKPTBLQUEUE1    10
+#define M_LKPTBLQUEUE1    0x3ffU
+#define V_LKPTBLQUEUE1(x) ((x) << S_LKPTBLQUEUE1)
+#define G_LKPTBLQUEUE1(x) (((x) >> S_LKPTBLQUEUE1) & M_LKPTBLQUEUE1)
+
+#define S_LKPTBLQUEUE0    0
+#define M_LKPTBLQUEUE0    0x3ffU
+#define V_LKPTBLQUEUE0(x) ((x) << S_LKPTBLQUEUE0)
+#define G_LKPTBLQUEUE0(x) (((x) >> S_LKPTBLQUEUE0) & M_LKPTBLQUEUE0)
+
+#define A_TP_RSS_CONFIG 0x7df0
+
+#define S_TNL4TUPENIPV6    31
+#define V_TNL4TUPENIPV6(x) ((x) << S_TNL4TUPENIPV6)
+#define F_TNL4TUPENIPV6    V_TNL4TUPENIPV6(1U)
+
+#define S_TNL2TUPENIPV6    30
+#define V_TNL2TUPENIPV6(x) ((x) << S_TNL2TUPENIPV6)
+#define F_TNL2TUPENIPV6    V_TNL2TUPENIPV6(1U)
+
+#define S_TNL4TUPENIPV4    29
+#define V_TNL4TUPENIPV4(x) ((x) << S_TNL4TUPENIPV4)
+#define F_TNL4TUPENIPV4    V_TNL4TUPENIPV4(1U)
+
+#define S_TNL2TUPENIPV4    28
+#define V_TNL2TUPENIPV4(x) ((x) << S_TNL2TUPENIPV4)
+#define F_TNL2TUPENIPV4    V_TNL2TUPENIPV4(1U)
+
+#define S_TNLTCPSEL    27
+#define V_TNLTCPSEL(x) ((x) << S_TNLTCPSEL)
+#define F_TNLTCPSEL    V_TNLTCPSEL(1U)
+
+#define S_TNLIP6SEL    26
+#define V_TNLIP6SEL(x) ((x) << S_TNLIP6SEL)
+#define F_TNLIP6SEL    V_TNLIP6SEL(1U)
+
+#define S_TNLVRTSEL    25
+#define V_TNLVRTSEL(x) ((x) << S_TNLVRTSEL)
+#define F_TNLVRTSEL    V_TNLVRTSEL(1U)
+
+#define S_TNLMAPEN    24
+#define V_TNLMAPEN(x) ((x) << S_TNLMAPEN)
+#define F_TNLMAPEN    V_TNLMAPEN(1U)
+
+#define S_OFDHASHSAVE    19
+#define V_OFDHASHSAVE(x) ((x) << S_OFDHASHSAVE)
+#define F_OFDHASHSAVE    V_OFDHASHSAVE(1U)
+
+#define S_OFDVRTSEL    18
+#define V_OFDVRTSEL(x) ((x) << S_OFDVRTSEL)
+#define F_OFDVRTSEL    V_OFDVRTSEL(1U)
+
+#define S_OFDMAPEN    17
+#define V_OFDMAPEN(x) ((x) << S_OFDMAPEN)
+#define F_OFDMAPEN    V_OFDMAPEN(1U)
+
+#define S_OFDLKPEN    16
+#define V_OFDLKPEN(x) ((x) << S_OFDLKPEN)
+#define F_OFDLKPEN    V_OFDLKPEN(1U)
+
+#define S_SYN4TUPENIPV6    15
+#define V_SYN4TUPENIPV6(x) ((x) << S_SYN4TUPENIPV6)
+#define F_SYN4TUPENIPV6    V_SYN4TUPENIPV6(1U)
+
+#define S_SYN2TUPENIPV6    14
+#define V_SYN2TUPENIPV6(x) ((x) << S_SYN2TUPENIPV6)
+#define F_SYN2TUPENIPV6    V_SYN2TUPENIPV6(1U)
+
+#define S_SYN4TUPENIPV4    13
+#define V_SYN4TUPENIPV4(x) ((x) << S_SYN4TUPENIPV4)
+#define F_SYN4TUPENIPV4    V_SYN4TUPENIPV4(1U)
+
+#define S_SYN2TUPENIPV4    12
+#define V_SYN2TUPENIPV4(x) ((x) << S_SYN2TUPENIPV4)
+#define F_SYN2TUPENIPV4    V_SYN2TUPENIPV4(1U)
+
+#define S_SYNIP6SEL    11
+#define V_SYNIP6SEL(x) ((x) << S_SYNIP6SEL)
+#define F_SYNIP6SEL    V_SYNIP6SEL(1U)
+
+#define S_SYNVRTSEL    10
+#define V_SYNVRTSEL(x) ((x) << S_SYNVRTSEL)
+#define F_SYNVRTSEL    V_SYNVRTSEL(1U)
+
+#define S_SYNMAPEN    9
+#define V_SYNMAPEN(x) ((x) << S_SYNMAPEN)
+#define F_SYNMAPEN    V_SYNMAPEN(1U)
+
+#define S_SYNLKPEN    8
+#define V_SYNLKPEN(x) ((x) << S_SYNLKPEN)
+#define F_SYNLKPEN    V_SYNLKPEN(1U)
+
+#define S_CHANNELENABLE    7
+#define V_CHANNELENABLE(x) ((x) << S_CHANNELENABLE)
+#define F_CHANNELENABLE    V_CHANNELENABLE(1U)
+
+#define S_PORTENABLE    6
+#define V_PORTENABLE(x) ((x) << S_PORTENABLE)
+#define F_PORTENABLE    V_PORTENABLE(1U)
+
+#define S_TNLALLLOOKUP    5
+#define V_TNLALLLOOKUP(x) ((x) << S_TNLALLLOOKUP)
+#define F_TNLALLLOOKUP    V_TNLALLLOOKUP(1U)
+
+#define S_VIRTENABLE    4
+#define V_VIRTENABLE(x) ((x) << S_VIRTENABLE)
+#define F_VIRTENABLE    V_VIRTENABLE(1U)
+
+#define S_CONGESTIONENABLE    3
+#define V_CONGESTIONENABLE(x) ((x) << S_CONGESTIONENABLE)
+#define F_CONGESTIONENABLE    V_CONGESTIONENABLE(1U)
+
+#define S_HASHTOEPLITZ    2
+#define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ)
+#define F_HASHTOEPLITZ    V_HASHTOEPLITZ(1U)
+
+#define S_UDPENABLE    1
+#define V_UDPENABLE(x) ((x) << S_UDPENABLE)
+#define F_UDPENABLE    V_UDPENABLE(1U)
+
+#define S_DISABLE    0
+#define V_DISABLE(x) ((x) << S_DISABLE)
+#define F_DISABLE    V_DISABLE(1U)
+
+#define S_TNLFCOEMODE    23
+#define V_TNLFCOEMODE(x) ((x) << S_TNLFCOEMODE)
+#define F_TNLFCOEMODE    V_TNLFCOEMODE(1U)
+
+#define S_TNLFCOEEN    21
+#define V_TNLFCOEEN(x) ((x) << S_TNLFCOEEN)
+#define F_TNLFCOEEN    V_TNLFCOEEN(1U)
+
+#define S_HASHXOR    20
+#define V_HASHXOR(x) ((x) << S_HASHXOR)
+#define F_HASHXOR    V_HASHXOR(1U)
+
+#define A_TP_RSS_CONFIG_TNL 0x7df4
+
+#define S_MASKSIZE    28
+#define M_MASKSIZE    0xfU
+#define V_MASKSIZE(x) ((x) << S_MASKSIZE)
+#define G_MASKSIZE(x) (((x) >> S_MASKSIZE) & M_MASKSIZE)
+
+#define S_MASKFILTER    16
+#define M_MASKFILTER    0x7ffU
+#define V_MASKFILTER(x) ((x) << S_MASKFILTER)
+#define G_MASKFILTER(x) (((x) >> S_MASKFILTER) & M_MASKFILTER)
+
+#define S_USEWIRECH    0
+#define V_USEWIRECH(x) ((x) << S_USEWIRECH)
+#define F_USEWIRECH    V_USEWIRECH(1U)
+
+#define A_TP_RSS_CONFIG_OFD 0x7df8
+
+#define S_RRCPLMAPEN    20
+#define V_RRCPLMAPEN(x) ((x) << S_RRCPLMAPEN)
+#define F_RRCPLMAPEN    V_RRCPLMAPEN(1U)
+
+#define S_RRCPLQUEWIDTH    16
+#define M_RRCPLQUEWIDTH    0xfU
+#define V_RRCPLQUEWIDTH(x) ((x) << S_RRCPLQUEWIDTH)
+#define G_RRCPLQUEWIDTH(x) (((x) >> S_RRCPLQUEWIDTH) & M_RRCPLQUEWIDTH)
+
+#define S_FRMWRQUEMASK    12
+#define M_FRMWRQUEMASK    0xfU
+#define V_FRMWRQUEMASK(x) ((x) << S_FRMWRQUEMASK)
+#define G_FRMWRQUEMASK(x) (((x) >> S_FRMWRQUEMASK) & M_FRMWRQUEMASK)
+
+#define A_TP_RSS_CONFIG_SYN 0x7dfc
+#define A_TP_RSS_CONFIG_VRT 0x7e00
+
+#define S_VFRDRG    25
+#define V_VFRDRG(x) ((x) << S_VFRDRG)
+#define F_VFRDRG    V_VFRDRG(1U)
+
+#define S_VFRDEN    24
+#define V_VFRDEN(x) ((x) << S_VFRDEN)
+#define F_VFRDEN    V_VFRDEN(1U)
+
+#define S_VFPERREN    23
+#define V_VFPERREN(x) ((x) << S_VFPERREN)
+#define F_VFPERREN    V_VFPERREN(1U)
+
+#define S_KEYPERREN    22
+#define V_KEYPERREN(x) ((x) << S_KEYPERREN)
+#define F_KEYPERREN    V_KEYPERREN(1U)
+
+#define S_DISABLEVLAN    21
+#define V_DISABLEVLAN(x) ((x) << S_DISABLEVLAN)
+#define F_DISABLEVLAN    V_DISABLEVLAN(1U)
+
+#define S_ENABLEUP0    20
+#define V_ENABLEUP0(x) ((x) << S_ENABLEUP0)
+#define F_ENABLEUP0    V_ENABLEUP0(1U)
+
+#define S_HASHDELAY    16
+#define M_HASHDELAY    0xfU
+#define V_HASHDELAY(x) ((x) << S_HASHDELAY)
+#define G_HASHDELAY(x) (((x) >> S_HASHDELAY) & M_HASHDELAY)
+
+#define S_VFWRADDR    8
+#define M_VFWRADDR    0x7fU
+#define V_VFWRADDR(x) ((x) << S_VFWRADDR)
+#define G_VFWRADDR(x) (((x) >> S_VFWRADDR) & M_VFWRADDR)
+
+#define S_KEYMODE    6
+#define M_KEYMODE    0x3U
+#define V_KEYMODE(x) ((x) << S_KEYMODE)
+#define G_KEYMODE(x) (((x) >> S_KEYMODE) & M_KEYMODE)
+
+#define S_VFWREN    5
+#define V_VFWREN(x) ((x) << S_VFWREN)
+#define F_VFWREN    V_VFWREN(1U)
+
+#define S_KEYWREN    4
+#define V_KEYWREN(x) ((x) << S_KEYWREN)
+#define F_KEYWREN    V_KEYWREN(1U)
+
+#define S_KEYWRADDR    0
+#define M_KEYWRADDR    0xfU
+#define V_KEYWRADDR(x) ((x) << S_KEYWRADDR)
+#define G_KEYWRADDR(x) (((x) >> S_KEYWRADDR) & M_KEYWRADDR)
+
+#define S_VFVLANEN    21
+#define V_VFVLANEN(x) ((x) << S_VFVLANEN)
+#define F_VFVLANEN    V_VFVLANEN(1U)
+
+#define S_VFFWEN    20
+#define V_VFFWEN(x) ((x) << S_VFFWEN)
+#define F_VFFWEN    V_VFFWEN(1U)
+
+#define A_TP_RSS_CONFIG_CNG 0x7e04
+
+#define S_CHNCOUNT3    31
+#define V_CHNCOUNT3(x) ((x) << S_CHNCOUNT3)
+#define F_CHNCOUNT3    V_CHNCOUNT3(1U)
+
+#define S_CHNCOUNT2    30
+#define V_CHNCOUNT2(x) ((x) << S_CHNCOUNT2)
+#define F_CHNCOUNT2    V_CHNCOUNT2(1U)
+
+#define S_CHNCOUNT1    29
+#define V_CHNCOUNT1(x) ((x) << S_CHNCOUNT1)
+#define F_CHNCOUNT1    V_CHNCOUNT1(1U)
+
+#define S_CHNCOUNT0    28
+#define V_CHNCOUNT0(x) ((x) << S_CHNCOUNT0)
+#define F_CHNCOUNT0    V_CHNCOUNT0(1U)
+
+#define S_CHNUNDFLOW3    27
+#define V_CHNUNDFLOW3(x) ((x) << S_CHNUNDFLOW3)
+#define F_CHNUNDFLOW3    V_CHNUNDFLOW3(1U)
+
+#define S_CHNUNDFLOW2    26
+#define V_CHNUNDFLOW2(x) ((x) << S_CHNUNDFLOW2)
+#define F_CHNUNDFLOW2    V_CHNUNDFLOW2(1U)
+
+#define S_CHNUNDFLOW1    25
+#define V_CHNUNDFLOW1(x) ((x) << S_CHNUNDFLOW1)
+#define F_CHNUNDFLOW1    V_CHNUNDFLOW1(1U)
+
+#define S_CHNUNDFLOW0    24
+#define V_CHNUNDFLOW0(x) ((x) << S_CHNUNDFLOW0)
+#define F_CHNUNDFLOW0    V_CHNUNDFLOW0(1U)
+
+#define S_CHNOVRFLOW3    23
+#define V_CHNOVRFLOW3(x) ((x) << S_CHNOVRFLOW3)
+#define F_CHNOVRFLOW3    V_CHNOVRFLOW3(1U)
+
+#define S_CHNOVRFLOW2    22
+#define V_CHNOVRFLOW2(x) ((x) << S_CHNOVRFLOW2)
+#define F_CHNOVRFLOW2    V_CHNOVRFLOW2(1U)
+
+#define S_CHNOVRFLOW1    21
+#define V_CHNOVRFLOW1(x) ((x) << S_CHNOVRFLOW1)
+#define F_CHNOVRFLOW1    V_CHNOVRFLOW1(1U)
+
+#define S_CHNOVRFLOW0    20
+#define V_CHNOVRFLOW0(x) ((x) << S_CHNOVRFLOW0)
+#define F_CHNOVRFLOW0    V_CHNOVRFLOW0(1U)
+
+#define S_RSTCHN3    19
+#define V_RSTCHN3(x) ((x) << S_RSTCHN3)
+#define F_RSTCHN3    V_RSTCHN3(1U)
+
+#define S_RSTCHN2    18
+#define V_RSTCHN2(x) ((x) << S_RSTCHN2)
+#define F_RSTCHN2    V_RSTCHN2(1U)
+
+#define S_RSTCHN1    17
+#define V_RSTCHN1(x) ((x) << S_RSTCHN1)
+#define F_RSTCHN1    V_RSTCHN1(1U)
+
+#define S_RSTCHN0    16
+#define V_RSTCHN0(x) ((x) << S_RSTCHN0)
+#define F_RSTCHN0    V_RSTCHN0(1U)
+
+#define S_UPDVLD    15
+#define V_UPDVLD(x) ((x) << S_UPDVLD)
+#define F_UPDVLD    V_UPDVLD(1U)
+
+#define S_XOFF    14
+#define V_XOFF(x) ((x) << S_XOFF)
+#define F_XOFF    V_XOFF(1U)
+
+#define S_UPDCHN3    13
+#define V_UPDCHN3(x) ((x) << S_UPDCHN3)
+#define F_UPDCHN3    V_UPDCHN3(1U)
+
+#define S_UPDCHN2    12
+#define V_UPDCHN2(x) ((x) << S_UPDCHN2)
+#define F_UPDCHN2    V_UPDCHN2(1U)
+
+#define S_UPDCHN1    11
+#define V_UPDCHN1(x) ((x) << S_UPDCHN1)
+#define F_UPDCHN1    V_UPDCHN1(1U)
+
+#define S_UPDCHN0    10
+#define V_UPDCHN0(x) ((x) << S_UPDCHN0)
+#define F_UPDCHN0    V_UPDCHN0(1U)
+
+#define S_QUEUE    0
+#define M_QUEUE    0x3ffU
+#define V_QUEUE(x) ((x) << S_QUEUE)
+#define G_QUEUE(x) (((x) >> S_QUEUE) & M_QUEUE)
+
+#define A_TP_LA_TABLE_0 0x7e10
+
+#define S_VIRTPORT1TABLE    16
+#define M_VIRTPORT1TABLE    0xffffU
+#define V_VIRTPORT1TABLE(x) ((x) << S_VIRTPORT1TABLE)
+#define G_VIRTPORT1TABLE(x) (((x) >> S_VIRTPORT1TABLE) & M_VIRTPORT1TABLE)
+
+#define S_VIRTPORT0TABLE    0
+#define M_VIRTPORT0TABLE    0xffffU
+#define V_VIRTPORT0TABLE(x) ((x) << S_VIRTPORT0TABLE)
+#define G_VIRTPORT0TABLE(x) (((x) >> S_VIRTPORT0TABLE) & M_VIRTPORT0TABLE)
+
+#define A_TP_LA_TABLE_1 0x7e14
+
+#define S_VIRTPORT3TABLE    16
+#define M_VIRTPORT3TABLE    0xffffU
+#define V_VIRTPORT3TABLE(x) ((x) << S_VIRTPORT3TABLE)
+#define G_VIRTPORT3TABLE(x) (((x) >> S_VIRTPORT3TABLE) & M_VIRTPORT3TABLE)
+
+#define S_VIRTPORT2TABLE    0
+#define M_VIRTPORT2TABLE    0xffffU
+#define V_VIRTPORT2TABLE(x) ((x) << S_VIRTPORT2TABLE)
+#define G_VIRTPORT2TABLE(x) (((x) >> S_VIRTPORT2TABLE) & M_VIRTPORT2TABLE)
+
+#define A_TP_TM_PIO_ADDR 0x7e18
+#define A_TP_TM_PIO_DATA 0x7e1c
+#define A_TP_MOD_CONFIG 0x7e24
+
+#define S_RXCHANNELWEIGHT1    24
+#define M_RXCHANNELWEIGHT1    0xffU
+#define V_RXCHANNELWEIGHT1(x) ((x) << S_RXCHANNELWEIGHT1)
+#define G_RXCHANNELWEIGHT1(x) (((x) >> S_RXCHANNELWEIGHT1) & M_RXCHANNELWEIGHT1)
+
+#define S_RXCHANNELWEIGHT0    16
+#define M_RXCHANNELWEIGHT0    0xffU
+#define V_RXCHANNELWEIGHT0(x) ((x) << S_RXCHANNELWEIGHT0)
+#define G_RXCHANNELWEIGHT0(x) (((x) >> S_RXCHANNELWEIGHT0) & M_RXCHANNELWEIGHT0)
+
+#define S_TIMERMODE    8
+#define M_TIMERMODE    0xffU
+#define V_TIMERMODE(x) ((x) << S_TIMERMODE)
+#define G_TIMERMODE(x) (((x) >> S_TIMERMODE) & M_TIMERMODE)
+
+#define S_TXCHANNELXOFFEN    0
+#define M_TXCHANNELXOFFEN    0xfU
+#define V_TXCHANNELXOFFEN(x) ((x) << S_TXCHANNELXOFFEN)
+#define G_TXCHANNELXOFFEN(x) (((x) >> S_TXCHANNELXOFFEN) & M_TXCHANNELXOFFEN)
+
+#define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28
+
+#define S_RX_MOD_WEIGHT    24
+#define M_RX_MOD_WEIGHT    0xffU
+#define V_RX_MOD_WEIGHT(x) ((x) << S_RX_MOD_WEIGHT)
+#define G_RX_MOD_WEIGHT(x) (((x) >> S_RX_MOD_WEIGHT) & M_RX_MOD_WEIGHT)
+
+#define S_TX_MOD_WEIGHT    16
+#define M_TX_MOD_WEIGHT    0xffU
+#define V_TX_MOD_WEIGHT(x) ((x) << S_TX_MOD_WEIGHT)
+#define G_TX_MOD_WEIGHT(x) (((x) >> S_TX_MOD_WEIGHT) & M_TX_MOD_WEIGHT)
+
+#define S_TX_MOD_QUEUE_REQ_MAP    0
+#define M_TX_MOD_QUEUE_REQ_MAP    0xffffU
+#define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
+#define G_TX_MOD_QUEUE_REQ_MAP(x) (((x) >> S_TX_MOD_QUEUE_REQ_MAP) & M_TX_MOD_QUEUE_REQ_MAP)
+
+#define A_TP_TX_MOD_QUEUE_WEIGHT1 0x7e2c
+
+#define S_TX_MODQ_WEIGHT7    24
+#define M_TX_MODQ_WEIGHT7    0xffU
+#define V_TX_MODQ_WEIGHT7(x) ((x) << S_TX_MODQ_WEIGHT7)
+#define G_TX_MODQ_WEIGHT7(x) (((x) >> S_TX_MODQ_WEIGHT7) & M_TX_MODQ_WEIGHT7)
+
+#define S_TX_MODQ_WEIGHT6    16
+#define M_TX_MODQ_WEIGHT6    0xffU
+#define V_TX_MODQ_WEIGHT6(x) ((x) << S_TX_MODQ_WEIGHT6)
+#define G_TX_MODQ_WEIGHT6(x) (((x) >> S_TX_MODQ_WEIGHT6) & M_TX_MODQ_WEIGHT6)
+
+#define S_TX_MODQ_WEIGHT5    8
+#define M_TX_MODQ_WEIGHT5    0xffU
+#define V_TX_MODQ_WEIGHT5(x) ((x) << S_TX_MODQ_WEIGHT5)
+#define G_TX_MODQ_WEIGHT5(x) (((x) >> S_TX_MODQ_WEIGHT5) & M_TX_MODQ_WEIGHT5)
+
+#define S_TX_MODQ_WEIGHT4    0
+#define M_TX_MODQ_WEIGHT4    0xffU
+#define V_TX_MODQ_WEIGHT4(x) ((x) << S_TX_MODQ_WEIGHT4)
+#define G_TX_MODQ_WEIGHT4(x) (((x) >> S_TX_MODQ_WEIGHT4) & M_TX_MODQ_WEIGHT4)
+
+#define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30
+
+#define S_TX_MODQ_WEIGHT3    24
+#define M_TX_MODQ_WEIGHT3    0xffU
+#define V_TX_MODQ_WEIGHT3(x) ((x) << S_TX_MODQ_WEIGHT3)
+#define G_TX_MODQ_WEIGHT3(x) (((x) >> S_TX_MODQ_WEIGHT3) & M_TX_MODQ_WEIGHT3)
+
+#define S_TX_MODQ_WEIGHT2    16
+#define M_TX_MODQ_WEIGHT2    0xffU
+#define V_TX_MODQ_WEIGHT2(x) ((x) << S_TX_MODQ_WEIGHT2)
+#define G_TX_MODQ_WEIGHT2(x) (((x) >> S_TX_MODQ_WEIGHT2) & M_TX_MODQ_WEIGHT2)
+
+#define S_TX_MODQ_WEIGHT1    8
+#define M_TX_MODQ_WEIGHT1    0xffU
+#define V_TX_MODQ_WEIGHT1(x) ((x) << S_TX_MODQ_WEIGHT1)
+#define G_TX_MODQ_WEIGHT1(x) (((x) >> S_TX_MODQ_WEIGHT1) & M_TX_MODQ_WEIGHT1)
+
+#define S_TX_MODQ_WEIGHT0    0
+#define M_TX_MODQ_WEIGHT0    0xffU
+#define V_TX_MODQ_WEIGHT0(x) ((x) << S_TX_MODQ_WEIGHT0)
+#define G_TX_MODQ_WEIGHT0(x) (((x) >> S_TX_MODQ_WEIGHT0) & M_TX_MODQ_WEIGHT0)
+
+#define A_TP_TX_MOD_CHANNEL_WEIGHT 0x7e34
+#define A_TP_MOD_RATE_LIMIT 0x7e38
+
+#define S_RX_MOD_RATE_LIMIT_INC    24
+#define M_RX_MOD_RATE_LIMIT_INC    0xffU
+#define V_RX_MOD_RATE_LIMIT_INC(x) ((x) << S_RX_MOD_RATE_LIMIT_INC)
+#define G_RX_MOD_RATE_LIMIT_INC(x) (((x) >> S_RX_MOD_RATE_LIMIT_INC) & M_RX_MOD_RATE_LIMIT_INC)
+
+#define S_RX_MOD_RATE_LIMIT_TICK    16
+#define M_RX_MOD_RATE_LIMIT_TICK    0xffU
+#define V_RX_MOD_RATE_LIMIT_TICK(x) ((x) << S_RX_MOD_RATE_LIMIT_TICK)
+#define G_RX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_RX_MOD_RATE_LIMIT_TICK) & M_RX_MOD_RATE_LIMIT_TICK)
+
+#define S_TX_MOD_RATE_LIMIT_INC    8
+#define M_TX_MOD_RATE_LIMIT_INC    0xffU
+#define V_TX_MOD_RATE_LIMIT_INC(x) ((x) << S_TX_MOD_RATE_LIMIT_INC)
+#define G_TX_MOD_RATE_LIMIT_INC(x) (((x) >> S_TX_MOD_RATE_LIMIT_INC) & M_TX_MOD_RATE_LIMIT_INC)
+
+#define S_TX_MOD_RATE_LIMIT_TICK    0
+#define M_TX_MOD_RATE_LIMIT_TICK    0xffU
+#define V_TX_MOD_RATE_LIMIT_TICK(x) ((x) << S_TX_MOD_RATE_LIMIT_TICK)
+#define G_TX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_TX_MOD_RATE_LIMIT_TICK) & M_TX_MOD_RATE_LIMIT_TICK)
+
+#define A_TP_PIO_ADDR 0x7e40
+#define A_TP_PIO_DATA 0x7e44
+#define A_TP_RESET 0x7e4c
+
+#define S_FLSTINITENABLE    1
+#define V_FLSTINITENABLE(x) ((x) << S_FLSTINITENABLE)
+#define F_FLSTINITENABLE    V_FLSTINITENABLE(1U)
+
+#define S_TPRESET    0
+#define V_TPRESET(x) ((x) << S_TPRESET)
+#define F_TPRESET    V_TPRESET(1U)
+
+#define A_TP_MIB_INDEX 0x7e50
+#define A_TP_MIB_DATA 0x7e54
+#define A_TP_SYNC_TIME_HI 0x7e58
+#define A_TP_SYNC_TIME_LO 0x7e5c
+#define A_TP_CMM_MM_RX_FLST_BASE 0x7e60
+#define A_TP_CMM_MM_TX_FLST_BASE 0x7e64
+#define A_TP_CMM_MM_PS_FLST_BASE 0x7e68
+#define A_TP_CMM_MM_MAX_PSTRUCT 0x7e6c
+
+#define S_CMMAXPSTRUCT    0
+#define M_CMMAXPSTRUCT    0x1fffffU
+#define V_CMMAXPSTRUCT(x) ((x) << S_CMMAXPSTRUCT)
+#define G_CMMAXPSTRUCT(x) (((x) >> S_CMMAXPSTRUCT) & M_CMMAXPSTRUCT)
+
+#define A_TP_INT_ENABLE 0x7e70
+
+#define S_FLMTXFLSTEMPTY    30
+#define V_FLMTXFLSTEMPTY(x) ((x) << S_FLMTXFLSTEMPTY)
+#define F_FLMTXFLSTEMPTY    V_FLMTXFLSTEMPTY(1U)
+
+#define S_RSSLKPPERR    29
+#define V_RSSLKPPERR(x) ((x) << S_RSSLKPPERR)
+#define F_RSSLKPPERR    V_RSSLKPPERR(1U)
+
+#define S_FLMPERRSET    28
+#define V_FLMPERRSET(x) ((x) << S_FLMPERRSET)
+#define F_FLMPERRSET    V_FLMPERRSET(1U)
+
+#define S_PROTOCOLSRAMPERR    27
+#define V_PROTOCOLSRAMPERR(x) ((x) << S_PROTOCOLSRAMPERR)
+#define F_PROTOCOLSRAMPERR    V_PROTOCOLSRAMPERR(1U)
+
+#define S_ARPLUTPERR    26
+#define V_ARPLUTPERR(x) ((x) << S_ARPLUTPERR)
+#define F_ARPLUTPERR    V_ARPLUTPERR(1U)
+
+#define S_CMRCFOPPERR    25
+#define V_CMRCFOPPERR(x) ((x) << S_CMRCFOPPERR)
+#define F_CMRCFOPPERR    V_CMRCFOPPERR(1U)
+
+#define S_CMCACHEPERR    24
+#define V_CMCACHEPERR(x) ((x) << S_CMCACHEPERR)
+#define F_CMCACHEPERR    V_CMCACHEPERR(1U)
+
+#define S_CMRCFDATAPERR    23
+#define V_CMRCFDATAPERR(x) ((x) << S_CMRCFDATAPERR)
+#define F_CMRCFDATAPERR    V_CMRCFDATAPERR(1U)
+
+#define S_DBL2TLUTPERR    22
+#define V_DBL2TLUTPERR(x) ((x) << S_DBL2TLUTPERR)
+#define F_DBL2TLUTPERR    V_DBL2TLUTPERR(1U)
+
+#define S_DBTXTIDPERR    21
+#define V_DBTXTIDPERR(x) ((x) << S_DBTXTIDPERR)
+#define F_DBTXTIDPERR    V_DBTXTIDPERR(1U)
+
+#define S_DBEXTPERR    20
+#define V_DBEXTPERR(x) ((x) << S_DBEXTPERR)
+#define F_DBEXTPERR    V_DBEXTPERR(1U)
+
+#define S_DBOPPERR    19
+#define V_DBOPPERR(x) ((x) << S_DBOPPERR)
+#define F_DBOPPERR    V_DBOPPERR(1U)
+
+#define S_TMCACHEPERR    18
+#define V_TMCACHEPERR(x) ((x) << S_TMCACHEPERR)
+#define F_TMCACHEPERR    V_TMCACHEPERR(1U)
+
+#define S_ETPOUTCPLFIFOPERR    17
+#define V_ETPOUTCPLFIFOPERR(x) ((x) << S_ETPOUTCPLFIFOPERR)
+#define F_ETPOUTCPLFIFOPERR    V_ETPOUTCPLFIFOPERR(1U)
+
+#define S_ETPOUTTCPFIFOPERR    16
+#define V_ETPOUTTCPFIFOPERR(x) ((x) << S_ETPOUTTCPFIFOPERR)
+#define F_ETPOUTTCPFIFOPERR    V_ETPOUTTCPFIFOPERR(1U)
+
+#define S_ETPOUTIPFIFOPERR    15
+#define V_ETPOUTIPFIFOPERR(x) ((x) << S_ETPOUTIPFIFOPERR)
+#define F_ETPOUTIPFIFOPERR    V_ETPOUTIPFIFOPERR(1U)
+
+#define S_ETPOUTETHFIFOPERR    14
+#define V_ETPOUTETHFIFOPERR(x) ((x) << S_ETPOUTETHFIFOPERR)
+#define F_ETPOUTETHFIFOPERR    V_ETPOUTETHFIFOPERR(1U)
+
+#define S_ETPINCPLFIFOPERR    13
+#define V_ETPINCPLFIFOPERR(x) ((x) << S_ETPINCPLFIFOPERR)
+#define F_ETPINCPLFIFOPERR    V_ETPINCPLFIFOPERR(1U)
+
+#define S_ETPINTCPOPTFIFOPERR    12
+#define V_ETPINTCPOPTFIFOPERR(x) ((x) << S_ETPINTCPOPTFIFOPERR)
+#define F_ETPINTCPOPTFIFOPERR    V_ETPINTCPOPTFIFOPERR(1U)
+
+#define S_ETPINTCPFIFOPERR    11
+#define V_ETPINTCPFIFOPERR(x) ((x) << S_ETPINTCPFIFOPERR)
+#define F_ETPINTCPFIFOPERR    V_ETPINTCPFIFOPERR(1U)
+
+#define S_ETPINIPFIFOPERR    10
+#define V_ETPINIPFIFOPERR(x) ((x) << S_ETPINIPFIFOPERR)
+#define F_ETPINIPFIFOPERR    V_ETPINIPFIFOPERR(1U)
+
+#define S_ETPINETHFIFOPERR    9
+#define V_ETPINETHFIFOPERR(x) ((x) << S_ETPINETHFIFOPERR)
+#define F_ETPINETHFIFOPERR    V_ETPINETHFIFOPERR(1U)
+
+#define S_CTPOUTCPLFIFOPERR    8
+#define V_CTPOUTCPLFIFOPERR(x) ((x) << S_CTPOUTCPLFIFOPERR)
+#define F_CTPOUTCPLFIFOPERR    V_CTPOUTCPLFIFOPERR(1U)
+
+#define S_CTPOUTTCPFIFOPERR    7
+#define V_CTPOUTTCPFIFOPERR(x) ((x) << S_CTPOUTTCPFIFOPERR)
+#define F_CTPOUTTCPFIFOPERR    V_CTPOUTTCPFIFOPERR(1U)
+
+#define S_CTPOUTIPFIFOPERR    6
+#define V_CTPOUTIPFIFOPERR(x) ((x) << S_CTPOUTIPFIFOPERR)
+#define F_CTPOUTIPFIFOPERR    V_CTPOUTIPFIFOPERR(1U)
+
+#define S_CTPOUTETHFIFOPERR    5
+#define V_CTPOUTETHFIFOPERR(x) ((x) << S_CTPOUTETHFIFOPERR)
+#define F_CTPOUTETHFIFOPERR    V_CTPOUTETHFIFOPERR(1U)
+
+#define S_CTPINCPLFIFOPERR    4
+#define V_CTPINCPLFIFOPERR(x) ((x) << S_CTPINCPLFIFOPERR)
+#define F_CTPINCPLFIFOPERR    V_CTPINCPLFIFOPERR(1U)
+
+#define S_CTPINTCPOPFIFOPERR    3
+#define V_CTPINTCPOPFIFOPERR(x) ((x) << S_CTPINTCPOPFIFOPERR)
+#define F_CTPINTCPOPFIFOPERR    V_CTPINTCPOPFIFOPERR(1U)
+
+#define S_PDUFBKFIFOPERR    2
+#define V_PDUFBKFIFOPERR(x) ((x) << S_PDUFBKFIFOPERR)
+#define F_PDUFBKFIFOPERR    V_PDUFBKFIFOPERR(1U)
+
+#define S_CMOPEXTFIFOPERR    1
+#define V_CMOPEXTFIFOPERR(x) ((x) << S_CMOPEXTFIFOPERR)
+#define F_CMOPEXTFIFOPERR    V_CMOPEXTFIFOPERR(1U)
+
+#define S_DELINVFIFOPERR    0
+#define V_DELINVFIFOPERR(x) ((x) << S_DELINVFIFOPERR)
+#define F_DELINVFIFOPERR    V_DELINVFIFOPERR(1U)
+
+#define S_CTPOUTPLDFIFOPERR    7
+#define V_CTPOUTPLDFIFOPERR(x) ((x) << S_CTPOUTPLDFIFOPERR)
+#define F_CTPOUTPLDFIFOPERR    V_CTPOUTPLDFIFOPERR(1U)
+
+#define A_TP_INT_CAUSE 0x7e74
+#define A_TP_PER_ENABLE 0x7e78
+#define A_TP_FLM_FREE_PS_CNT 0x7e80
+
+#define S_FREEPSTRUCTCOUNT    0
+#define M_FREEPSTRUCTCOUNT    0x1fffffU
+#define V_FREEPSTRUCTCOUNT(x) ((x) << S_FREEPSTRUCTCOUNT)
+#define G_FREEPSTRUCTCOUNT(x) (((x) >> S_FREEPSTRUCTCOUNT) & M_FREEPSTRUCTCOUNT)
+
+#define A_TP_FLM_FREE_RX_CNT 0x7e84
+
+#define S_FREERXPAGECHN    28
+#define V_FREERXPAGECHN(x) ((x) << S_FREERXPAGECHN)
+#define F_FREERXPAGECHN    V_FREERXPAGECHN(1U)
+
+#define S_FREERXPAGECOUNT    0
+#define M_FREERXPAGECOUNT    0x1fffffU
+#define V_FREERXPAGECOUNT(x) ((x) << S_FREERXPAGECOUNT)
+#define G_FREERXPAGECOUNT(x) (((x) >> S_FREERXPAGECOUNT) & M_FREERXPAGECOUNT)
+
+#define A_TP_FLM_FREE_TX_CNT 0x7e88
+
+#define S_FREETXPAGECHN    28
+#define M_FREETXPAGECHN    0x3U
+#define V_FREETXPAGECHN(x) ((x) << S_FREETXPAGECHN)
+#define G_FREETXPAGECHN(x) (((x) >> S_FREETXPAGECHN) & M_FREETXPAGECHN)
+
+#define S_FREETXPAGECOUNT    0
+#define M_FREETXPAGECOUNT    0x1fffffU
+#define V_FREETXPAGECOUNT(x) ((x) << S_FREETXPAGECOUNT)
+#define G_FREETXPAGECOUNT(x) (((x) >> S_FREETXPAGECOUNT) & M_FREETXPAGECOUNT)
+
+#define A_TP_TM_HEAP_PUSH_CNT 0x7e8c
+#define A_TP_TM_HEAP_POP_CNT 0x7e90
+#define A_TP_TM_DACK_PUSH_CNT 0x7e94
+#define A_TP_TM_DACK_POP_CNT 0x7e98
+#define A_TP_TM_MOD_PUSH_CNT 0x7e9c
+#define A_TP_MOD_POP_CNT 0x7ea0
+#define A_TP_TIMER_SEPARATOR 0x7ea4
+
+#define S_TIMERSEPARATOR    16
+#define M_TIMERSEPARATOR    0xffffU
+#define V_TIMERSEPARATOR(x) ((x) << S_TIMERSEPARATOR)
+#define G_TIMERSEPARATOR(x) (((x) >> S_TIMERSEPARATOR) & M_TIMERSEPARATOR)
+
+#define S_DISABLETIMEFREEZE    0
+#define V_DISABLETIMEFREEZE(x) ((x) << S_DISABLETIMEFREEZE)
+#define F_DISABLETIMEFREEZE    V_DISABLETIMEFREEZE(1U)
+
+#define A_TP_STAMP_TIME 0x7ea8
+#define A_TP_DEBUG_FLAGS 0x7eac
+
+#define S_RXTIMERDACKFIRST    26
+#define V_RXTIMERDACKFIRST(x) ((x) << S_RXTIMERDACKFIRST)
+#define F_RXTIMERDACKFIRST    V_RXTIMERDACKFIRST(1U)
+
+#define S_RXTIMERDACK    25
+#define V_RXTIMERDACK(x) ((x) << S_RXTIMERDACK)
+#define F_RXTIMERDACK    V_RXTIMERDACK(1U)
+
+#define S_RXTIMERHEARTBEAT    24
+#define V_RXTIMERHEARTBEAT(x) ((x) << S_RXTIMERHEARTBEAT)
+#define F_RXTIMERHEARTBEAT    V_RXTIMERHEARTBEAT(1U)
+
+#define S_RXPAWSDROP    23
+#define V_RXPAWSDROP(x) ((x) << S_RXPAWSDROP)
+#define F_RXPAWSDROP    V_RXPAWSDROP(1U)
+
+#define S_RXURGDATADROP    22
+#define V_RXURGDATADROP(x) ((x) << S_RXURGDATADROP)
+#define F_RXURGDATADROP    V_RXURGDATADROP(1U)
+
+#define S_RXFUTUREDATA    21
+#define V_RXFUTUREDATA(x) ((x) << S_RXFUTUREDATA)
+#define F_RXFUTUREDATA    V_RXFUTUREDATA(1U)
+
+#define S_RXRCVRXMDATA    20
+#define V_RXRCVRXMDATA(x) ((x) << S_RXRCVRXMDATA)
+#define F_RXRCVRXMDATA    V_RXRCVRXMDATA(1U)
+
+#define S_RXRCVOOODATAFIN    19
+#define V_RXRCVOOODATAFIN(x) ((x) << S_RXRCVOOODATAFIN)
+#define F_RXRCVOOODATAFIN    V_RXRCVOOODATAFIN(1U)
+
+#define S_RXRCVOOODATA    18
+#define V_RXRCVOOODATA(x) ((x) << S_RXRCVOOODATA)
+#define F_RXRCVOOODATA    V_RXRCVOOODATA(1U)
+
+#define S_RXRCVWNDZERO    17
+#define V_RXRCVWNDZERO(x) ((x) << S_RXRCVWNDZERO)
+#define F_RXRCVWNDZERO    V_RXRCVWNDZERO(1U)
+
+#define S_RXRCVWNDLTMSS    16
+#define V_RXRCVWNDLTMSS(x) ((x) << S_RXRCVWNDLTMSS)
+#define F_RXRCVWNDLTMSS    V_RXRCVWNDLTMSS(1U)
+
+#define S_TXDUPACKINC    11
+#define V_TXDUPACKINC(x) ((x) << S_TXDUPACKINC)
+#define F_TXDUPACKINC    V_TXDUPACKINC(1U)
+
+#define S_TXRXMURG    10
+#define V_TXRXMURG(x) ((x) << S_TXRXMURG)
+#define F_TXRXMURG    V_TXRXMURG(1U)
+
+#define S_TXRXMFIN    9
+#define V_TXRXMFIN(x) ((x) << S_TXRXMFIN)
+#define F_TXRXMFIN    V_TXRXMFIN(1U)
+
+#define S_TXRXMSYN    8
+#define V_TXRXMSYN(x) ((x) << S_TXRXMSYN)
+#define F_TXRXMSYN    V_TXRXMSYN(1U)
+
+#define S_TXRXMNEWRENO    7
+#define V_TXRXMNEWRENO(x) ((x) << S_TXRXMNEWRENO)
+#define F_TXRXMNEWRENO    V_TXRXMNEWRENO(1U)
+
+#define S_TXRXMFAST    6
+#define V_TXRXMFAST(x) ((x) << S_TXRXMFAST)
+#define F_TXRXMFAST    V_TXRXMFAST(1U)
+
+#define S_TXRXMTIMER    5
+#define V_TXRXMTIMER(x) ((x) << S_TXRXMTIMER)
+#define F_TXRXMTIMER    V_TXRXMTIMER(1U)
+
+#define S_TXRXMTIMERKEEPALIVE    4
+#define V_TXRXMTIMERKEEPALIVE(x) ((x) << S_TXRXMTIMERKEEPALIVE)
+#define F_TXRXMTIMERKEEPALIVE    V_TXRXMTIMERKEEPALIVE(1U)
+
+#define S_TXRXMTIMERPERSIST    3
+#define V_TXRXMTIMERPERSIST(x) ((x) << S_TXRXMTIMERPERSIST)
+#define F_TXRXMTIMERPERSIST    V_TXRXMTIMERPERSIST(1U)
+
+#define S_TXRCVADVSHRUNK    2
+#define V_TXRCVADVSHRUNK(x) ((x) << S_TXRCVADVSHRUNK)
+#define F_TXRCVADVSHRUNK    V_TXRCVADVSHRUNK(1U)
+
+#define S_TXRCVADVZERO    1
+#define V_TXRCVADVZERO(x) ((x) << S_TXRCVADVZERO)
+#define F_TXRCVADVZERO    V_TXRCVADVZERO(1U)
+
+#define S_TXRCVADVLTMSS    0
+#define V_TXRCVADVLTMSS(x) ((x) << S_TXRCVADVLTMSS)
+#define F_TXRCVADVLTMSS    V_TXRCVADVLTMSS(1U)
+
+#define S_RXTIMERCOMPBUFFER    27
+#define V_RXTIMERCOMPBUFFER(x) ((x) << S_RXTIMERCOMPBUFFER)
+#define F_RXTIMERCOMPBUFFER    V_RXTIMERCOMPBUFFER(1U)
+
+#define S_TXDFRFAST    13
+#define V_TXDFRFAST(x) ((x) << S_TXDFRFAST)
+#define F_TXDFRFAST    V_TXDFRFAST(1U)
+
+#define S_TXRXMMISC    12
+#define V_TXRXMMISC(x) ((x) << S_TXRXMMISC)
+#define F_TXRXMMISC    V_TXRXMMISC(1U)
+
+#define A_TP_RX_SCHED 0x7eb0
+
+#define S_RXCOMMITRESET1    31
+#define V_RXCOMMITRESET1(x) ((x) << S_RXCOMMITRESET1)
+#define F_RXCOMMITRESET1    V_RXCOMMITRESET1(1U)
+
+#define S_RXCOMMITRESET0    30
+#define V_RXCOMMITRESET0(x) ((x) << S_RXCOMMITRESET0)
+#define F_RXCOMMITRESET0    V_RXCOMMITRESET0(1U)
+
+#define S_RXFORCECONG1    29
+#define V_RXFORCECONG1(x) ((x) << S_RXFORCECONG1)
+#define F_RXFORCECONG1    V_RXFORCECONG1(1U)
+
+#define S_RXFORCECONG0    28
+#define V_RXFORCECONG0(x) ((x) << S_RXFORCECONG0)
+#define F_RXFORCECONG0    V_RXFORCECONG0(1U)
+
+#define S_ENABLELPBKFULL1    26
+#define M_ENABLELPBKFULL1    0x3U
+#define V_ENABLELPBKFULL1(x) ((x) << S_ENABLELPBKFULL1)
+#define G_ENABLELPBKFULL1(x) (((x) >> S_ENABLELPBKFULL1) & M_ENABLELPBKFULL1)
+
+#define S_ENABLELPBKFULL0    24
+#define M_ENABLELPBKFULL0    0x3U
+#define V_ENABLELPBKFULL0(x) ((x) << S_ENABLELPBKFULL0)
+#define G_ENABLELPBKFULL0(x) (((x) >> S_ENABLELPBKFULL0) & M_ENABLELPBKFULL0)
+
+#define S_ENABLEFIFOFULL1    22
+#define M_ENABLEFIFOFULL1    0x3U
+#define V_ENABLEFIFOFULL1(x) ((x) << S_ENABLEFIFOFULL1)
+#define G_ENABLEFIFOFULL1(x) (((x) >> S_ENABLEFIFOFULL1) & M_ENABLEFIFOFULL1)
+
+#define S_ENABLEPCMDFULL1    20
+#define M_ENABLEPCMDFULL1    0x3U
+#define V_ENABLEPCMDFULL1(x) ((x) << S_ENABLEPCMDFULL1)
+#define G_ENABLEPCMDFULL1(x) (((x) >> S_ENABLEPCMDFULL1) & M_ENABLEPCMDFULL1)
+
+#define S_ENABLEHDRFULL1    18
+#define M_ENABLEHDRFULL1    0x3U
+#define V_ENABLEHDRFULL1(x) ((x) << S_ENABLEHDRFULL1)
+#define G_ENABLEHDRFULL1(x) (((x) >> S_ENABLEHDRFULL1) & M_ENABLEHDRFULL1)
+
+#define S_ENABLEFIFOFULL0    16
+#define M_ENABLEFIFOFULL0    0x3U
+#define V_ENABLEFIFOFULL0(x) ((x) << S_ENABLEFIFOFULL0)
+#define G_ENABLEFIFOFULL0(x) (((x) >> S_ENABLEFIFOFULL0) & M_ENABLEFIFOFULL0)
+
+#define S_ENABLEPCMDFULL0    14
+#define M_ENABLEPCMDFULL0    0x3U
+#define V_ENABLEPCMDFULL0(x) ((x) << S_ENABLEPCMDFULL0)
+#define G_ENABLEPCMDFULL0(x) (((x) >> S_ENABLEPCMDFULL0) & M_ENABLEPCMDFULL0)
+
+#define S_ENABLEHDRFULL0    12
+#define M_ENABLEHDRFULL0    0x3U
+#define V_ENABLEHDRFULL0(x) ((x) << S_ENABLEHDRFULL0)
+#define G_ENABLEHDRFULL0(x) (((x) >> S_ENABLEHDRFULL0) & M_ENABLEHDRFULL0)
+
+#define S_COMMITLIMIT1    6
+#define M_COMMITLIMIT1    0x3fU
+#define V_COMMITLIMIT1(x) ((x) << S_COMMITLIMIT1)
+#define G_COMMITLIMIT1(x) (((x) >> S_COMMITLIMIT1) & M_COMMITLIMIT1)
+
+#define S_COMMITLIMIT0    0
+#define M_COMMITLIMIT0    0x3fU
+#define V_COMMITLIMIT0(x) ((x) << S_COMMITLIMIT0)
+#define G_COMMITLIMIT0(x) (((x) >> S_COMMITLIMIT0) & M_COMMITLIMIT0)
+
+#define A_TP_TX_SCHED 0x7eb4
+
+#define S_COMMITRESET3    31
+#define V_COMMITRESET3(x) ((x) << S_COMMITRESET3)
+#define F_COMMITRESET3    V_COMMITRESET3(1U)
+
+#define S_COMMITRESET2    30
+#define V_COMMITRESET2(x) ((x) << S_COMMITRESET2)
+#define F_COMMITRESET2    V_COMMITRESET2(1U)
+
+#define S_COMMITRESET1    29
+#define V_COMMITRESET1(x) ((x) << S_COMMITRESET1)
+#define F_COMMITRESET1    V_COMMITRESET1(1U)
+
+#define S_COMMITRESET0    28
+#define V_COMMITRESET0(x) ((x) << S_COMMITRESET0)
+#define F_COMMITRESET0    V_COMMITRESET0(1U)
+
+#define S_FORCECONG3    27
+#define V_FORCECONG3(x) ((x) << S_FORCECONG3)
+#define F_FORCECONG3    V_FORCECONG3(1U)
+
+#define S_FORCECONG2    26
+#define V_FORCECONG2(x) ((x) << S_FORCECONG2)
+#define F_FORCECONG2    V_FORCECONG2(1U)
+
+#define S_FORCECONG1    25
+#define V_FORCECONG1(x) ((x) << S_FORCECONG1)
+#define F_FORCECONG1    V_FORCECONG1(1U)
+
+#define S_FORCECONG0    24
+#define V_FORCECONG0(x) ((x) << S_FORCECONG0)
+#define F_FORCECONG0    V_FORCECONG0(1U)
+
+#define S_COMMITLIMIT3    18
+#define M_COMMITLIMIT3    0x3fU
+#define V_COMMITLIMIT3(x) ((x) << S_COMMITLIMIT3)
+#define G_COMMITLIMIT3(x) (((x) >> S_COMMITLIMIT3) & M_COMMITLIMIT3)
+
+#define S_COMMITLIMIT2    12
+#define M_COMMITLIMIT2    0x3fU
+#define V_COMMITLIMIT2(x) ((x) << S_COMMITLIMIT2)
+#define G_COMMITLIMIT2(x) (((x) >> S_COMMITLIMIT2) & M_COMMITLIMIT2)
+
+#define A_TP_FX_SCHED 0x7eb8
+
+#define S_TXCHNXOFF3    19
+#define V_TXCHNXOFF3(x) ((x) << S_TXCHNXOFF3)
+#define F_TXCHNXOFF3    V_TXCHNXOFF3(1U)
+
+#define S_TXCHNXOFF2    18
+#define V_TXCHNXOFF2(x) ((x) << S_TXCHNXOFF2)
+#define F_TXCHNXOFF2    V_TXCHNXOFF2(1U)
+
+#define S_TXCHNXOFF1    17
+#define V_TXCHNXOFF1(x) ((x) << S_TXCHNXOFF1)
+#define F_TXCHNXOFF1    V_TXCHNXOFF1(1U)
+
+#define S_TXCHNXOFF0    16
+#define V_TXCHNXOFF0(x) ((x) << S_TXCHNXOFF0)
+#define F_TXCHNXOFF0    V_TXCHNXOFF0(1U)
+
+#define S_TXMODXOFF7    15
+#define V_TXMODXOFF7(x) ((x) << S_TXMODXOFF7)
+#define F_TXMODXOFF7    V_TXMODXOFF7(1U)
+
+#define S_TXMODXOFF6    14
+#define V_TXMODXOFF6(x) ((x) << S_TXMODXOFF6)
+#define F_TXMODXOFF6    V_TXMODXOFF6(1U)
+
+#define S_TXMODXOFF5    13
+#define V_TXMODXOFF5(x) ((x) << S_TXMODXOFF5)
+#define F_TXMODXOFF5    V_TXMODXOFF5(1U)
+
+#define S_TXMODXOFF4    12
+#define V_TXMODXOFF4(x) ((x) << S_TXMODXOFF4)
+#define F_TXMODXOFF4    V_TXMODXOFF4(1U)
+
+#define S_TXMODXOFF3    11
+#define V_TXMODXOFF3(x) ((x) << S_TXMODXOFF3)
+#define F_TXMODXOFF3    V_TXMODXOFF3(1U)
+
+#define S_TXMODXOFF2    10
+#define V_TXMODXOFF2(x) ((x) << S_TXMODXOFF2)
+#define F_TXMODXOFF2    V_TXMODXOFF2(1U)
+
+#define S_TXMODXOFF1    9
+#define V_TXMODXOFF1(x) ((x) << S_TXMODXOFF1)
+#define F_TXMODXOFF1    V_TXMODXOFF1(1U)
+
+#define S_TXMODXOFF0    8
+#define V_TXMODXOFF0(x) ((x) << S_TXMODXOFF0)
+#define F_TXMODXOFF0    V_TXMODXOFF0(1U)
+
+#define S_RXCHNXOFF3    7
+#define V_RXCHNXOFF3(x) ((x) << S_RXCHNXOFF3)
+#define F_RXCHNXOFF3    V_RXCHNXOFF3(1U)
+
+#define S_RXCHNXOFF2    6
+#define V_RXCHNXOFF2(x) ((x) << S_RXCHNXOFF2)
+#define F_RXCHNXOFF2    V_RXCHNXOFF2(1U)
+
+#define S_RXCHNXOFF1    5
+#define V_RXCHNXOFF1(x) ((x) << S_RXCHNXOFF1)
+#define F_RXCHNXOFF1    V_RXCHNXOFF1(1U)
+
+#define S_RXCHNXOFF0    4
+#define V_RXCHNXOFF0(x) ((x) << S_RXCHNXOFF0)
+#define F_RXCHNXOFF0    V_RXCHNXOFF0(1U)
+
+#define S_RXMODXOFF1    1
+#define V_RXMODXOFF1(x) ((x) << S_RXMODXOFF1)
+#define F_RXMODXOFF1    V_RXMODXOFF1(1U)
+
+#define S_RXMODXOFF0    0
+#define V_RXMODXOFF0(x) ((x) << S_RXMODXOFF0)
+#define F_RXMODXOFF0    V_RXMODXOFF0(1U)
+
+#define A_TP_TX_ORATE 0x7ebc
+
+#define S_OFDRATE3    24
+#define M_OFDRATE3    0xffU
+#define V_OFDRATE3(x) ((x) << S_OFDRATE3)
+#define G_OFDRATE3(x) (((x) >> S_OFDRATE3) & M_OFDRATE3)
+
+#define S_OFDRATE2    16
+#define M_OFDRATE2    0xffU
+#define V_OFDRATE2(x) ((x) << S_OFDRATE2)
+#define G_OFDRATE2(x) (((x) >> S_OFDRATE2) & M_OFDRATE2)
+
+#define S_OFDRATE1    8
+#define M_OFDRATE1    0xffU
+#define V_OFDRATE1(x) ((x) << S_OFDRATE1)
+#define G_OFDRATE1(x) (((x) >> S_OFDRATE1) & M_OFDRATE1)
+
+#define S_OFDRATE0    0
+#define M_OFDRATE0    0xffU
+#define V_OFDRATE0(x) ((x) << S_OFDRATE0)
+#define G_OFDRATE0(x) (((x) >> S_OFDRATE0) & M_OFDRATE0)
+
+#define A_TP_IX_SCHED0 0x7ec0
+#define A_TP_IX_SCHED1 0x7ec4
+#define A_TP_IX_SCHED2 0x7ec8
+#define A_TP_IX_SCHED3 0x7ecc
+#define A_TP_TX_TRATE 0x7ed0
+
+#define S_TNLRATE3    24
+#define M_TNLRATE3    0xffU
+#define V_TNLRATE3(x) ((x) << S_TNLRATE3)
+#define G_TNLRATE3(x) (((x) >> S_TNLRATE3) & M_TNLRATE3)
+
+#define S_TNLRATE2    16
+#define M_TNLRATE2    0xffU
+#define V_TNLRATE2(x) ((x) << S_TNLRATE2)
+#define G_TNLRATE2(x) (((x) >> S_TNLRATE2) & M_TNLRATE2)
+
+#define S_TNLRATE1    8
+#define M_TNLRATE1    0xffU
+#define V_TNLRATE1(x) ((x) << S_TNLRATE1)
+#define G_TNLRATE1(x) (((x) >> S_TNLRATE1) & M_TNLRATE1)
+
+#define S_TNLRATE0    0
+#define M_TNLRATE0    0xffU
+#define V_TNLRATE0(x) ((x) << S_TNLRATE0)
+#define G_TNLRATE0(x) (((x) >> S_TNLRATE0) & M_TNLRATE0)
+
+#define A_TP_DBG_LA_CONFIG 0x7ed4
+
+#define S_DBGLAOPCENABLE    24
+#define M_DBGLAOPCENABLE    0xffU
+#define V_DBGLAOPCENABLE(x) ((x) << S_DBGLAOPCENABLE)
+#define G_DBGLAOPCENABLE(x) (((x) >> S_DBGLAOPCENABLE) & M_DBGLAOPCENABLE)
+
+#define S_DBGLAWHLF    23
+#define V_DBGLAWHLF(x) ((x) << S_DBGLAWHLF)
+#define F_DBGLAWHLF    V_DBGLAWHLF(1U)
+
+#define S_DBGLAWPTR    16
+#define M_DBGLAWPTR    0x7fU
+#define V_DBGLAWPTR(x) ((x) << S_DBGLAWPTR)
+#define G_DBGLAWPTR(x) (((x) >> S_DBGLAWPTR) & M_DBGLAWPTR)
+
+#define S_DBGLAMODE    14
+#define M_DBGLAMODE    0x3U
+#define V_DBGLAMODE(x) ((x) << S_DBGLAMODE)
+#define G_DBGLAMODE(x) (((x) >> S_DBGLAMODE) & M_DBGLAMODE)
+
+#define S_DBGLAFATALFREEZE    13
+#define V_DBGLAFATALFREEZE(x) ((x) << S_DBGLAFATALFREEZE)
+#define F_DBGLAFATALFREEZE    V_DBGLAFATALFREEZE(1U)
+
+#define S_DBGLAENABLE    12
+#define V_DBGLAENABLE(x) ((x) << S_DBGLAENABLE)
+#define F_DBGLAENABLE    V_DBGLAENABLE(1U)
+
+#define S_DBGLARPTR    0
+#define M_DBGLARPTR    0x7fU
+#define V_DBGLARPTR(x) ((x) << S_DBGLARPTR)
+#define G_DBGLARPTR(x) (((x) >> S_DBGLARPTR) & M_DBGLARPTR)
+
+#define A_TP_DBG_LA_DATAL 0x7ed8
+#define A_TP_DBG_LA_DATAH 0x7edc
+#define A_TP_PROTOCOL_CNTRL 0x7ee8
+
+#define S_WRITEENABLE    31
+#define V_WRITEENABLE(x) ((x) << S_WRITEENABLE)
+#define F_WRITEENABLE    V_WRITEENABLE(1U)
+
+#define S_TCAMENABLE    10
+#define V_TCAMENABLE(x) ((x) << S_TCAMENABLE)
+#define F_TCAMENABLE    V_TCAMENABLE(1U)
+
+#define S_BLOCKSELECT    8
+#define M_BLOCKSELECT    0x3U
+#define V_BLOCKSELECT(x) ((x) << S_BLOCKSELECT)
+#define G_BLOCKSELECT(x) (((x) >> S_BLOCKSELECT) & M_BLOCKSELECT)
+
+#define S_LINEADDRESS    1
+#define M_LINEADDRESS    0x7fU
+#define V_LINEADDRESS(x) ((x) << S_LINEADDRESS)
+#define G_LINEADDRESS(x) (((x) >> S_LINEADDRESS) & M_LINEADDRESS)
+
+#define S_REQUESTDONE    0
+#define V_REQUESTDONE(x) ((x) << S_REQUESTDONE)
+#define F_REQUESTDONE    V_REQUESTDONE(1U)
+
+#define A_TP_PROTOCOL_DATA0 0x7eec
+#define A_TP_PROTOCOL_DATA1 0x7ef0
+#define A_TP_PROTOCOL_DATA2 0x7ef4
+#define A_TP_PROTOCOL_DATA3 0x7ef8
+#define A_TP_PROTOCOL_DATA4 0x7efc
+
+#define S_PROTOCOLDATAFIELD    0
+#define M_PROTOCOLDATAFIELD    0xfU
+#define V_PROTOCOLDATAFIELD(x) ((x) << S_PROTOCOLDATAFIELD)
+#define G_PROTOCOLDATAFIELD(x) (((x) >> S_PROTOCOLDATAFIELD) & M_PROTOCOLDATAFIELD)
+
+#define A_TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR 0x0
+
+#define S_TXTIMERSEPQ7    16
+#define M_TXTIMERSEPQ7    0xffffU
+#define V_TXTIMERSEPQ7(x) ((x) << S_TXTIMERSEPQ7)
+#define G_TXTIMERSEPQ7(x) (((x) >> S_TXTIMERSEPQ7) & M_TXTIMERSEPQ7)
+
+#define S_TXTIMERSEPQ6    0
+#define M_TXTIMERSEPQ6    0xffffU
+#define V_TXTIMERSEPQ6(x) ((x) << S_TXTIMERSEPQ6)
+#define G_TXTIMERSEPQ6(x) (((x) >> S_TXTIMERSEPQ6) & M_TXTIMERSEPQ6)
+
+#define A_TP_TX_MOD_Q5_Q4_TIMER_SEPARATOR 0x1
+
+#define S_TXTIMERSEPQ5    16
+#define M_TXTIMERSEPQ5    0xffffU
+#define V_TXTIMERSEPQ5(x) ((x) << S_TXTIMERSEPQ5)
+#define G_TXTIMERSEPQ5(x) (((x) >> S_TXTIMERSEPQ5) & M_TXTIMERSEPQ5)
+
+#define S_TXTIMERSEPQ4    0
+#define M_TXTIMERSEPQ4    0xffffU
+#define V_TXTIMERSEPQ4(x) ((x) << S_TXTIMERSEPQ4)
+#define G_TXTIMERSEPQ4(x) (((x) >> S_TXTIMERSEPQ4) & M_TXTIMERSEPQ4)
+
+#define A_TP_TX_MOD_Q3_Q2_TIMER_SEPARATOR 0x2
+
+#define S_TXTIMERSEPQ3    16
+#define M_TXTIMERSEPQ3    0xffffU
+#define V_TXTIMERSEPQ3(x) ((x) << S_TXTIMERSEPQ3)
+#define G_TXTIMERSEPQ3(x) (((x) >> S_TXTIMERSEPQ3) & M_TXTIMERSEPQ3)
+
+#define S_TXTIMERSEPQ2    0
+#define M_TXTIMERSEPQ2    0xffffU
+#define V_TXTIMERSEPQ2(x) ((x) << S_TXTIMERSEPQ2)
+#define G_TXTIMERSEPQ2(x) (((x) >> S_TXTIMERSEPQ2) & M_TXTIMERSEPQ2)
+
+#define A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR 0x3
+
+#define S_TXTIMERSEPQ1    16
+#define M_TXTIMERSEPQ1    0xffffU
+#define V_TXTIMERSEPQ1(x) ((x) << S_TXTIMERSEPQ1)
+#define G_TXTIMERSEPQ1(x) (((x) >> S_TXTIMERSEPQ1) & M_TXTIMERSEPQ1)
+
+#define S_TXTIMERSEPQ0    0
+#define M_TXTIMERSEPQ0    0xffffU
+#define V_TXTIMERSEPQ0(x) ((x) << S_TXTIMERSEPQ0)
+#define G_TXTIMERSEPQ0(x) (((x) >> S_TXTIMERSEPQ0) & M_TXTIMERSEPQ0)
+
+#define A_TP_RX_MOD_Q1_Q0_TIMER_SEPARATOR 0x4
+
+#define S_RXTIMERSEPQ1    16
+#define M_RXTIMERSEPQ1    0xffffU
+#define V_RXTIMERSEPQ1(x) ((x) << S_RXTIMERSEPQ1)
+#define G_RXTIMERSEPQ1(x) (((x) >> S_RXTIMERSEPQ1) & M_RXTIMERSEPQ1)
+
+#define S_RXTIMERSEPQ0    0
+#define M_RXTIMERSEPQ0    0xffffU
+#define V_RXTIMERSEPQ0(x) ((x) << S_RXTIMERSEPQ0)
+#define G_RXTIMERSEPQ0(x) (((x) >> S_RXTIMERSEPQ0) & M_RXTIMERSEPQ0)
+
+#define A_TP_TX_MOD_Q7_Q6_RATE_LIMIT 0x5
+
+#define S_TXRATEINCQ7    24
+#define M_TXRATEINCQ7    0xffU
+#define V_TXRATEINCQ7(x) ((x) << S_TXRATEINCQ7)
+#define G_TXRATEINCQ7(x) (((x) >> S_TXRATEINCQ7) & M_TXRATEINCQ7)
+
+#define S_TXRATETCKQ7    16
+#define M_TXRATETCKQ7    0xffU
+#define V_TXRATETCKQ7(x) ((x) << S_TXRATETCKQ7)
+#define G_TXRATETCKQ7(x) (((x) >> S_TXRATETCKQ7) & M_TXRATETCKQ7)
+
+#define S_TXRATEINCQ6    8
+#define M_TXRATEINCQ6    0xffU
+#define V_TXRATEINCQ6(x) ((x) << S_TXRATEINCQ6)
+#define G_TXRATEINCQ6(x) (((x) >> S_TXRATEINCQ6) & M_TXRATEINCQ6)
+
+#define S_TXRATETCKQ6    0
+#define M_TXRATETCKQ6    0xffU
+#define V_TXRATETCKQ6(x) ((x) << S_TXRATETCKQ6)
+#define G_TXRATETCKQ6(x) (((x) >> S_TXRATETCKQ6) & M_TXRATETCKQ6)
+
+#define A_TP_TX_MOD_Q5_Q4_RATE_LIMIT 0x6
+
+#define S_TXRATEINCQ5    24
+#define M_TXRATEINCQ5    0xffU
+#define V_TXRATEINCQ5(x) ((x) << S_TXRATEINCQ5)
+#define G_TXRATEINCQ5(x) (((x) >> S_TXRATEINCQ5) & M_TXRATEINCQ5)
+
+#define S_TXRATETCKQ5    16
+#define M_TXRATETCKQ5    0xffU
+#define V_TXRATETCKQ5(x) ((x) << S_TXRATETCKQ5)
+#define G_TXRATETCKQ5(x) (((x) >> S_TXRATETCKQ5) & M_TXRATETCKQ5)
+
+#define S_TXRATEINCQ4    8
+#define M_TXRATEINCQ4    0xffU
+#define V_TXRATEINCQ4(x) ((x) << S_TXRATEINCQ4)
+#define G_TXRATEINCQ4(x) (((x) >> S_TXRATEINCQ4) & M_TXRATEINCQ4)
+
+#define S_TXRATETCKQ4    0
+#define M_TXRATETCKQ4    0xffU
+#define V_TXRATETCKQ4(x) ((x) << S_TXRATETCKQ4)
+#define G_TXRATETCKQ4(x) (((x) >> S_TXRATETCKQ4) & M_TXRATETCKQ4)
+
+#define A_TP_TX_MOD_Q3_Q2_RATE_LIMIT 0x7
+
+#define S_TXRATEINCQ3    24
+#define M_TXRATEINCQ3    0xffU
+#define V_TXRATEINCQ3(x) ((x) << S_TXRATEINCQ3)
+#define G_TXRATEINCQ3(x) (((x) >> S_TXRATEINCQ3) & M_TXRATEINCQ3)
+
+#define S_TXRATETCKQ3    16
+#define M_TXRATETCKQ3    0xffU
+#define V_TXRATETCKQ3(x) ((x) << S_TXRATETCKQ3)
+#define G_TXRATETCKQ3(x) (((x) >> S_TXRATETCKQ3) & M_TXRATETCKQ3)
+
+#define S_TXRATEINCQ2    8
+#define M_TXRATEINCQ2    0xffU
+#define V_TXRATEINCQ2(x) ((x) << S_TXRATEINCQ2)
+#define G_TXRATEINCQ2(x) (((x) >> S_TXRATEINCQ2) & M_TXRATEINCQ2)
+
+#define S_TXRATETCKQ2    0
+#define M_TXRATETCKQ2    0xffU
+#define V_TXRATETCKQ2(x) ((x) << S_TXRATETCKQ2)
+#define G_TXRATETCKQ2(x) (((x) >> S_TXRATETCKQ2) & M_TXRATETCKQ2)
+
+#define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8
+
+#define S_TXRATEINCQ1    24
+#define M_TXRATEINCQ1    0xffU
+#define V_TXRATEINCQ1(x) ((x) << S_TXRATEINCQ1)
+#define G_TXRATEINCQ1(x) (((x) >> S_TXRATEINCQ1) & M_TXRATEINCQ1)
+
+#define S_TXRATETCKQ1    16
+#define M_TXRATETCKQ1    0xffU
+#define V_TXRATETCKQ1(x) ((x) << S_TXRATETCKQ1)
+#define G_TXRATETCKQ1(x) (((x) >> S_TXRATETCKQ1) & M_TXRATETCKQ1)
+
+#define S_TXRATEINCQ0    8
+#define M_TXRATEINCQ0    0xffU
+#define V_TXRATEINCQ0(x) ((x) << S_TXRATEINCQ0)
+#define G_TXRATEINCQ0(x) (((x) >> S_TXRATEINCQ0) & M_TXRATEINCQ0)
+
+#define S_TXRATETCKQ0    0
+#define M_TXRATETCKQ0    0xffU
+#define V_TXRATETCKQ0(x) ((x) << S_TXRATETCKQ0)
+#define G_TXRATETCKQ0(x) (((x) >> S_TXRATETCKQ0) & M_TXRATETCKQ0)
+
+#define A_TP_RX_MOD_Q1_Q0_RATE_LIMIT 0x9
+
+#define S_RXRATEINCQ1    24
+#define M_RXRATEINCQ1    0xffU
+#define V_RXRATEINCQ1(x) ((x) << S_RXRATEINCQ1)
+#define G_RXRATEINCQ1(x) (((x) >> S_RXRATEINCQ1) & M_RXRATEINCQ1)
+
+#define S_RXRATETCKQ1    16
+#define M_RXRATETCKQ1    0xffU
+#define V_RXRATETCKQ1(x) ((x) << S_RXRATETCKQ1)
+#define G_RXRATETCKQ1(x) (((x) >> S_RXRATETCKQ1) & M_RXRATETCKQ1)
+
+#define S_RXRATEINCQ0    8
+#define M_RXRATEINCQ0    0xffU
+#define V_RXRATEINCQ0(x) ((x) << S_RXRATEINCQ0)
+#define G_RXRATEINCQ0(x) (((x) >> S_RXRATEINCQ0) & M_RXRATEINCQ0)
+
+#define S_RXRATETCKQ0    0
+#define M_RXRATETCKQ0    0xffU
+#define V_RXRATETCKQ0(x) ((x) << S_RXRATETCKQ0)
+#define G_RXRATETCKQ0(x) (((x) >> S_RXRATETCKQ0) & M_RXRATETCKQ0)
+
+#define A_TP_TX_MOD_C3_C2_RATE_LIMIT 0xa
+#define A_TP_TX_MOD_C1_C0_RATE_LIMIT 0xb
+#define A_TP_RX_SCHED_MAP 0x20
+
+#define S_RXMAPCHANNEL3    24
+#define M_RXMAPCHANNEL3    0xffU
+#define V_RXMAPCHANNEL3(x) ((x) << S_RXMAPCHANNEL3)
+#define G_RXMAPCHANNEL3(x) (((x) >> S_RXMAPCHANNEL3) & M_RXMAPCHANNEL3)
+
+#define S_RXMAPCHANNEL2    16
+#define M_RXMAPCHANNEL2    0xffU
+#define V_RXMAPCHANNEL2(x) ((x) << S_RXMAPCHANNEL2)
+#define G_RXMAPCHANNEL2(x) (((x) >> S_RXMAPCHANNEL2) & M_RXMAPCHANNEL2)
+
+#define S_RXMAPCHANNEL1    8
+#define M_RXMAPCHANNEL1    0xffU
+#define V_RXMAPCHANNEL1(x) ((x) << S_RXMAPCHANNEL1)
+#define G_RXMAPCHANNEL1(x) (((x) >> S_RXMAPCHANNEL1) & M_RXMAPCHANNEL1)
+
+#define S_RXMAPCHANNEL0    0
+#define M_RXMAPCHANNEL0    0xffU
+#define V_RXMAPCHANNEL0(x) ((x) << S_RXMAPCHANNEL0)
+#define G_RXMAPCHANNEL0(x) (((x) >> S_RXMAPCHANNEL0) & M_RXMAPCHANNEL0)
+
+#define A_TP_RX_SCHED_SGE 0x21
+
+#define S_RXSGEMOD1    12
+#define M_RXSGEMOD1    0xfU
+#define V_RXSGEMOD1(x) ((x) << S_RXSGEMOD1)
+#define G_RXSGEMOD1(x) (((x) >> S_RXSGEMOD1) & M_RXSGEMOD1)
+
+#define S_RXSGEMOD0    8
+#define M_RXSGEMOD0    0xfU
+#define V_RXSGEMOD0(x) ((x) << S_RXSGEMOD0)
+#define G_RXSGEMOD0(x) (((x) >> S_RXSGEMOD0) & M_RXSGEMOD0)
+
+#define S_RXSGECHANNEL3    3
+#define V_RXSGECHANNEL3(x) ((x) << S_RXSGECHANNEL3)
+#define F_RXSGECHANNEL3    V_RXSGECHANNEL3(1U)
+
+#define S_RXSGECHANNEL2    2
+#define V_RXSGECHANNEL2(x) ((x) << S_RXSGECHANNEL2)
+#define F_RXSGECHANNEL2    V_RXSGECHANNEL2(1U)
+
+#define S_RXSGECHANNEL1    1
+#define V_RXSGECHANNEL1(x) ((x) << S_RXSGECHANNEL1)
+#define F_RXSGECHANNEL1    V_RXSGECHANNEL1(1U)
+
+#define S_RXSGECHANNEL0    0
+#define V_RXSGECHANNEL0(x) ((x) << S_RXSGECHANNEL0)
+#define F_RXSGECHANNEL0    V_RXSGECHANNEL0(1U)
+
+#define A_TP_TX_SCHED_MAP 0x22
+
+#define S_TXMAPCHANNEL3    12
+#define M_TXMAPCHANNEL3    0xfU
+#define V_TXMAPCHANNEL3(x) ((x) << S_TXMAPCHANNEL3)
+#define G_TXMAPCHANNEL3(x) (((x) >> S_TXMAPCHANNEL3) & M_TXMAPCHANNEL3)
+
+#define S_TXMAPCHANNEL2    8
+#define M_TXMAPCHANNEL2    0xfU
+#define V_TXMAPCHANNEL2(x) ((x) << S_TXMAPCHANNEL2)
+#define G_TXMAPCHANNEL2(x) (((x) >> S_TXMAPCHANNEL2) & M_TXMAPCHANNEL2)
+
+#define S_TXMAPCHANNEL1    4
+#define M_TXMAPCHANNEL1    0xfU
+#define V_TXMAPCHANNEL1(x) ((x) << S_TXMAPCHANNEL1)
+#define G_TXMAPCHANNEL1(x) (((x) >> S_TXMAPCHANNEL1) & M_TXMAPCHANNEL1)
+
+#define S_TXMAPCHANNEL0    0
+#define M_TXMAPCHANNEL0    0xfU
+#define V_TXMAPCHANNEL0(x) ((x) << S_TXMAPCHANNEL0)
+#define G_TXMAPCHANNEL0(x) (((x) >> S_TXMAPCHANNEL0) & M_TXMAPCHANNEL0)
+
+#define A_TP_TX_SCHED_HDR 0x23
+
+#define S_TXMAPHDRCHANNEL7    28
+#define M_TXMAPHDRCHANNEL7    0xfU
+#define V_TXMAPHDRCHANNEL7(x) ((x) << S_TXMAPHDRCHANNEL7)
+#define G_TXMAPHDRCHANNEL7(x) (((x) >> S_TXMAPHDRCHANNEL7) & M_TXMAPHDRCHANNEL7)
+
+#define S_TXMAPHDRCHANNEL6    24
+#define M_TXMAPHDRCHANNEL6    0xfU
+#define V_TXMAPHDRCHANNEL6(x) ((x) << S_TXMAPHDRCHANNEL6)
+#define G_TXMAPHDRCHANNEL6(x) (((x) >> S_TXMAPHDRCHANNEL6) & M_TXMAPHDRCHANNEL6)
+
+#define S_TXMAPHDRCHANNEL5    20
+#define M_TXMAPHDRCHANNEL5    0xfU
+#define V_TXMAPHDRCHANNEL5(x) ((x) << S_TXMAPHDRCHANNEL5)
+#define G_TXMAPHDRCHANNEL5(x) (((x) >> S_TXMAPHDRCHANNEL5) & M_TXMAPHDRCHANNEL5)
+
+#define S_TXMAPHDRCHANNEL4    16
+#define M_TXMAPHDRCHANNEL4    0xfU
+#define V_TXMAPHDRCHANNEL4(x) ((x) << S_TXMAPHDRCHANNEL4)
+#define G_TXMAPHDRCHANNEL4(x) (((x) >> S_TXMAPHDRCHANNEL4) & M_TXMAPHDRCHANNEL4)
+
+#define S_TXMAPHDRCHANNEL3    12
+#define M_TXMAPHDRCHANNEL3    0xfU
+#define V_TXMAPHDRCHANNEL3(x) ((x) << S_TXMAPHDRCHANNEL3)
+#define G_TXMAPHDRCHANNEL3(x) (((x) >> S_TXMAPHDRCHANNEL3) & M_TXMAPHDRCHANNEL3)
+
+#define S_TXMAPHDRCHANNEL2    8
+#define M_TXMAPHDRCHANNEL2    0xfU
+#define V_TXMAPHDRCHANNEL2(x) ((x) << S_TXMAPHDRCHANNEL2)
+#define G_TXMAPHDRCHANNEL2(x) (((x) >> S_TXMAPHDRCHANNEL2) & M_TXMAPHDRCHANNEL2)
+
+#define S_TXMAPHDRCHANNEL1    4
+#define M_TXMAPHDRCHANNEL1    0xfU
+#define V_TXMAPHDRCHANNEL1(x) ((x) << S_TXMAPHDRCHANNEL1)
+#define G_TXMAPHDRCHANNEL1(x) (((x) >> S_TXMAPHDRCHANNEL1) & M_TXMAPHDRCHANNEL1)
+
+#define S_TXMAPHDRCHANNEL0    0
+#define M_TXMAPHDRCHANNEL0    0xfU
+#define V_TXMAPHDRCHANNEL0(x) ((x) << S_TXMAPHDRCHANNEL0)
+#define G_TXMAPHDRCHANNEL0(x) (((x) >> S_TXMAPHDRCHANNEL0) & M_TXMAPHDRCHANNEL0)
+
+#define A_TP_TX_SCHED_FIFO 0x24
+
+#define S_TXMAPFIFOCHANNEL7    28
+#define M_TXMAPFIFOCHANNEL7    0xfU
+#define V_TXMAPFIFOCHANNEL7(x) ((x) << S_TXMAPFIFOCHANNEL7)
+#define G_TXMAPFIFOCHANNEL7(x) (((x) >> S_TXMAPFIFOCHANNEL7) & M_TXMAPFIFOCHANNEL7)
+
+#define S_TXMAPFIFOCHANNEL6    24
+#define M_TXMAPFIFOCHANNEL6    0xfU
+#define V_TXMAPFIFOCHANNEL6(x) ((x) << S_TXMAPFIFOCHANNEL6)
+#define G_TXMAPFIFOCHANNEL6(x) (((x) >> S_TXMAPFIFOCHANNEL6) & M_TXMAPFIFOCHANNEL6)
+
+#define S_TXMAPFIFOCHANNEL5    20
+#define M_TXMAPFIFOCHANNEL5    0xfU
+#define V_TXMAPFIFOCHANNEL5(x) ((x) << S_TXMAPFIFOCHANNEL5)
+#define G_TXMAPFIFOCHANNEL5(x) (((x) >> S_TXMAPFIFOCHANNEL5) & M_TXMAPFIFOCHANNEL5)
+
+#define S_TXMAPFIFOCHANNEL4    16
+#define M_TXMAPFIFOCHANNEL4    0xfU
+#define V_TXMAPFIFOCHANNEL4(x) ((x) << S_TXMAPFIFOCHANNEL4)
+#define G_TXMAPFIFOCHANNEL4(x) (((x) >> S_TXMAPFIFOCHANNEL4) & M_TXMAPFIFOCHANNEL4)
+
+#define S_TXMAPFIFOCHANNEL3    12
+#define M_TXMAPFIFOCHANNEL3    0xfU
+#define V_TXMAPFIFOCHANNEL3(x) ((x) << S_TXMAPFIFOCHANNEL3)
+#define G_TXMAPFIFOCHANNEL3(x) (((x) >> S_TXMAPFIFOCHANNEL3) & M_TXMAPFIFOCHANNEL3)
+
+#define S_TXMAPFIFOCHANNEL2    8
+#define M_TXMAPFIFOCHANNEL2    0xfU
+#define V_TXMAPFIFOCHANNEL2(x) ((x) << S_TXMAPFIFOCHANNEL2)
+#define G_TXMAPFIFOCHANNEL2(x) (((x) >> S_TXMAPFIFOCHANNEL2) & M_TXMAPFIFOCHANNEL2)
+
+#define S_TXMAPFIFOCHANNEL1    4
+#define M_TXMAPFIFOCHANNEL1    0xfU
+#define V_TXMAPFIFOCHANNEL1(x) ((x) << S_TXMAPFIFOCHANNEL1)
+#define G_TXMAPFIFOCHANNEL1(x) (((x) >> S_TXMAPFIFOCHANNEL1) & M_TXMAPFIFOCHANNEL1)
+
+#define S_TXMAPFIFOCHANNEL0    0
+#define M_TXMAPFIFOCHANNEL0    0xfU
+#define V_TXMAPFIFOCHANNEL0(x) ((x) << S_TXMAPFIFOCHANNEL0)
+#define G_TXMAPFIFOCHANNEL0(x) (((x) >> S_TXMAPFIFOCHANNEL0) & M_TXMAPFIFOCHANNEL0)
+
+#define A_TP_TX_SCHED_PCMD 0x25
+
+#define S_TXMAPPCMDCHANNEL7    28
+#define M_TXMAPPCMDCHANNEL7    0xfU
+#define V_TXMAPPCMDCHANNEL7(x) ((x) << S_TXMAPPCMDCHANNEL7)
+#define G_TXMAPPCMDCHANNEL7(x) (((x) >> S_TXMAPPCMDCHANNEL7) & M_TXMAPPCMDCHANNEL7)
+
+#define S_TXMAPPCMDCHANNEL6    24
+#define M_TXMAPPCMDCHANNEL6    0xfU
+#define V_TXMAPPCMDCHANNEL6(x) ((x) << S_TXMAPPCMDCHANNEL6)
+#define G_TXMAPPCMDCHANNEL6(x) (((x) >> S_TXMAPPCMDCHANNEL6) & M_TXMAPPCMDCHANNEL6)
+
+#define S_TXMAPPCMDCHANNEL5    20
+#define M_TXMAPPCMDCHANNEL5    0xfU
+#define V_TXMAPPCMDCHANNEL5(x) ((x) << S_TXMAPPCMDCHANNEL5)
+#define G_TXMAPPCMDCHANNEL5(x) (((x) >> S_TXMAPPCMDCHANNEL5) & M_TXMAPPCMDCHANNEL5)
+
+#define S_TXMAPPCMDCHANNEL4    16
+#define M_TXMAPPCMDCHANNEL4    0xfU
+#define V_TXMAPPCMDCHANNEL4(x) ((x) << S_TXMAPPCMDCHANNEL4)
+#define G_TXMAPPCMDCHANNEL4(x) (((x) >> S_TXMAPPCMDCHANNEL4) & M_TXMAPPCMDCHANNEL4)
+
+#define S_TXMAPPCMDCHANNEL3    12
+#define M_TXMAPPCMDCHANNEL3    0xfU
+#define V_TXMAPPCMDCHANNEL3(x) ((x) << S_TXMAPPCMDCHANNEL3)
+#define G_TXMAPPCMDCHANNEL3(x) (((x) >> S_TXMAPPCMDCHANNEL3) & M_TXMAPPCMDCHANNEL3)
+
+#define S_TXMAPPCMDCHANNEL2    8
+#define M_TXMAPPCMDCHANNEL2    0xfU
+#define V_TXMAPPCMDCHANNEL2(x) ((x) << S_TXMAPPCMDCHANNEL2)
+#define G_TXMAPPCMDCHANNEL2(x) (((x) >> S_TXMAPPCMDCHANNEL2) & M_TXMAPPCMDCHANNEL2)
+
+#define S_TXMAPPCMDCHANNEL1    4
+#define M_TXMAPPCMDCHANNEL1    0xfU
+#define V_TXMAPPCMDCHANNEL1(x) ((x) << S_TXMAPPCMDCHANNEL1)
+#define G_TXMAPPCMDCHANNEL1(x) (((x) >> S_TXMAPPCMDCHANNEL1) & M_TXMAPPCMDCHANNEL1)
+
+#define S_TXMAPPCMDCHANNEL0    0
+#define M_TXMAPPCMDCHANNEL0    0xfU
+#define V_TXMAPPCMDCHANNEL0(x) ((x) << S_TXMAPPCMDCHANNEL0)
+#define G_TXMAPPCMDCHANNEL0(x) (((x) >> S_TXMAPPCMDCHANNEL0) & M_TXMAPPCMDCHANNEL0)
+
+#define A_TP_TX_SCHED_LPBK 0x26
+
+#define S_TXMAPLPBKCHANNEL7    28
+#define M_TXMAPLPBKCHANNEL7    0xfU
+#define V_TXMAPLPBKCHANNEL7(x) ((x) << S_TXMAPLPBKCHANNEL7)
+#define G_TXMAPLPBKCHANNEL7(x) (((x) >> S_TXMAPLPBKCHANNEL7) & M_TXMAPLPBKCHANNEL7)
+
+#define S_TXMAPLPBKCHANNEL6    24
+#define M_TXMAPLPBKCHANNEL6    0xfU
+#define V_TXMAPLPBKCHANNEL6(x) ((x) << S_TXMAPLPBKCHANNEL6)
+#define G_TXMAPLPBKCHANNEL6(x) (((x) >> S_TXMAPLPBKCHANNEL6) & M_TXMAPLPBKCHANNEL6)
+
+#define S_TXMAPLPBKCHANNEL5    20
+#define M_TXMAPLPBKCHANNEL5    0xfU
+#define V_TXMAPLPBKCHANNEL5(x) ((x) << S_TXMAPLPBKCHANNEL5)
+#define G_TXMAPLPBKCHANNEL5(x) (((x) >> S_TXMAPLPBKCHANNEL5) & M_TXMAPLPBKCHANNEL5)
+
+#define S_TXMAPLPBKCHANNEL4    16
+#define M_TXMAPLPBKCHANNEL4    0xfU
+#define V_TXMAPLPBKCHANNEL4(x) ((x) << S_TXMAPLPBKCHANNEL4)
+#define G_TXMAPLPBKCHANNEL4(x) (((x) >> S_TXMAPLPBKCHANNEL4) & M_TXMAPLPBKCHANNEL4)
+
+#define S_TXMAPLPBKCHANNEL3    12
+#define M_TXMAPLPBKCHANNEL3    0xfU
+#define V_TXMAPLPBKCHANNEL3(x) ((x) << S_TXMAPLPBKCHANNEL3)
+#define G_TXMAPLPBKCHANNEL3(x) (((x) >> S_TXMAPLPBKCHANNEL3) & M_TXMAPLPBKCHANNEL3)
+
+#define S_TXMAPLPBKCHANNEL2    8
+#define M_TXMAPLPBKCHANNEL2    0xfU
+#define V_TXMAPLPBKCHANNEL2(x) ((x) << S_TXMAPLPBKCHANNEL2)
+#define G_TXMAPLPBKCHANNEL2(x) (((x) >> S_TXMAPLPBKCHANNEL2) & M_TXMAPLPBKCHANNEL2)
+
+#define S_TXMAPLPBKCHANNEL1    4
+#define M_TXMAPLPBKCHANNEL1    0xfU
+#define V_TXMAPLPBKCHANNEL1(x) ((x) << S_TXMAPLPBKCHANNEL1)
+#define G_TXMAPLPBKCHANNEL1(x) (((x) >> S_TXMAPLPBKCHANNEL1) & M_TXMAPLPBKCHANNEL1)
+
+#define S_TXMAPLPBKCHANNEL0    0
+#define M_TXMAPLPBKCHANNEL0    0xfU
+#define V_TXMAPLPBKCHANNEL0(x) ((x) << S_TXMAPLPBKCHANNEL0)
+#define G_TXMAPLPBKCHANNEL0(x) (((x) >> S_TXMAPLPBKCHANNEL0) & M_TXMAPLPBKCHANNEL0)
+
+#define A_TP_CHANNEL_MAP 0x27
+
+#define S_RXMAPCHANNELELN    16
+#define M_RXMAPCHANNELELN    0xfU
+#define V_RXMAPCHANNELELN(x) ((x) << S_RXMAPCHANNELELN)
+#define G_RXMAPCHANNELELN(x) (((x) >> S_RXMAPCHANNELELN) & M_RXMAPCHANNELELN)
+
+#define S_RXMAPE2LCHANNEL3    14
+#define M_RXMAPE2LCHANNEL3    0x3U
+#define V_RXMAPE2LCHANNEL3(x) ((x) << S_RXMAPE2LCHANNEL3)
+#define G_RXMAPE2LCHANNEL3(x) (((x) >> S_RXMAPE2LCHANNEL3) & M_RXMAPE2LCHANNEL3)
+
+#define S_RXMAPE2LCHANNEL2    12
+#define M_RXMAPE2LCHANNEL2    0x3U
+#define V_RXMAPE2LCHANNEL2(x) ((x) << S_RXMAPE2LCHANNEL2)
+#define G_RXMAPE2LCHANNEL2(x) (((x) >> S_RXMAPE2LCHANNEL2) & M_RXMAPE2LCHANNEL2)
+
+#define S_RXMAPE2LCHANNEL1    10
+#define M_RXMAPE2LCHANNEL1    0x3U
+#define V_RXMAPE2LCHANNEL1(x) ((x) << S_RXMAPE2LCHANNEL1)
+#define G_RXMAPE2LCHANNEL1(x) (((x) >> S_RXMAPE2LCHANNEL1) & M_RXMAPE2LCHANNEL1)
+
+#define S_RXMAPE2LCHANNEL0    8
+#define M_RXMAPE2LCHANNEL0    0x3U
+#define V_RXMAPE2LCHANNEL0(x) ((x) << S_RXMAPE2LCHANNEL0)
+#define G_RXMAPE2LCHANNEL0(x) (((x) >> S_RXMAPE2LCHANNEL0) & M_RXMAPE2LCHANNEL0)
+
+#define S_RXMAPC2CCHANNEL3    7
+#define V_RXMAPC2CCHANNEL3(x) ((x) << S_RXMAPC2CCHANNEL3)
+#define F_RXMAPC2CCHANNEL3    V_RXMAPC2CCHANNEL3(1U)
+
+#define S_RXMAPC2CCHANNEL2    6
+#define V_RXMAPC2CCHANNEL2(x) ((x) << S_RXMAPC2CCHANNEL2)
+#define F_RXMAPC2CCHANNEL2    V_RXMAPC2CCHANNEL2(1U)
+
+#define S_RXMAPC2CCHANNEL1    5
+#define V_RXMAPC2CCHANNEL1(x) ((x) << S_RXMAPC2CCHANNEL1)
+#define F_RXMAPC2CCHANNEL1    V_RXMAPC2CCHANNEL1(1U)
+
+#define S_RXMAPC2CCHANNEL0    4
+#define V_RXMAPC2CCHANNEL0(x) ((x) << S_RXMAPC2CCHANNEL0)
+#define F_RXMAPC2CCHANNEL0    V_RXMAPC2CCHANNEL0(1U)
+
+#define S_RXMAPE2CCHANNEL3    3
+#define V_RXMAPE2CCHANNEL3(x) ((x) << S_RXMAPE2CCHANNEL3)
+#define F_RXMAPE2CCHANNEL3    V_RXMAPE2CCHANNEL3(1U)
+
+#define S_RXMAPE2CCHANNEL2    2
+#define V_RXMAPE2CCHANNEL2(x) ((x) << S_RXMAPE2CCHANNEL2)
+#define F_RXMAPE2CCHANNEL2    V_RXMAPE2CCHANNEL2(1U)
+
+#define S_RXMAPE2CCHANNEL1    1
+#define V_RXMAPE2CCHANNEL1(x) ((x) << S_RXMAPE2CCHANNEL1)
+#define F_RXMAPE2CCHANNEL1    V_RXMAPE2CCHANNEL1(1U)
+
+#define S_RXMAPE2CCHANNEL0    0
+#define V_RXMAPE2CCHANNEL0(x) ((x) << S_RXMAPE2CCHANNEL0)
+#define F_RXMAPE2CCHANNEL0    V_RXMAPE2CCHANNEL0(1U)
+
+#define A_TP_RX_LPBK 0x28
+#define A_TP_TX_LPBK 0x29
+#define A_TP_TX_SCHED_PPP 0x2a
+
+#define S_TXPPPENPORT3    24
+#define M_TXPPPENPORT3    0xffU
+#define V_TXPPPENPORT3(x) ((x) << S_TXPPPENPORT3)
+#define G_TXPPPENPORT3(x) (((x) >> S_TXPPPENPORT3) & M_TXPPPENPORT3)
+
+#define S_TXPPPENPORT2    16
+#define M_TXPPPENPORT2    0xffU
+#define V_TXPPPENPORT2(x) ((x) << S_TXPPPENPORT2)
+#define G_TXPPPENPORT2(x) (((x) >> S_TXPPPENPORT2) & M_TXPPPENPORT2)
+
+#define S_TXPPPENPORT1    8
+#define M_TXPPPENPORT1    0xffU
+#define V_TXPPPENPORT1(x) ((x) << S_TXPPPENPORT1)
+#define G_TXPPPENPORT1(x) (((x) >> S_TXPPPENPORT1) & M_TXPPPENPORT1)
+
+#define S_TXPPPENPORT0    0
+#define M_TXPPPENPORT0    0xffU
+#define V_TXPPPENPORT0(x) ((x) << S_TXPPPENPORT0)
+#define G_TXPPPENPORT0(x) (((x) >> S_TXPPPENPORT0) & M_TXPPPENPORT0)
+
+#define A_TP_RX_SCHED_FIFO 0x2b
+
+#define S_COMMITLIMIT1H    24
+#define M_COMMITLIMIT1H    0xffU
+#define V_COMMITLIMIT1H(x) ((x) << S_COMMITLIMIT1H)
+#define G_COMMITLIMIT1H(x) (((x) >> S_COMMITLIMIT1H) & M_COMMITLIMIT1H)
+
+#define S_COMMITLIMIT1L    16
+#define M_COMMITLIMIT1L    0xffU
+#define V_COMMITLIMIT1L(x) ((x) << S_COMMITLIMIT1L)
+#define G_COMMITLIMIT1L(x) (((x) >> S_COMMITLIMIT1L) & M_COMMITLIMIT1L)
+
+#define S_COMMITLIMIT0H    8
+#define M_COMMITLIMIT0H    0xffU
+#define V_COMMITLIMIT0H(x) ((x) << S_COMMITLIMIT0H)
+#define G_COMMITLIMIT0H(x) (((x) >> S_COMMITLIMIT0H) & M_COMMITLIMIT0H)
+
+#define S_COMMITLIMIT0L    0
+#define M_COMMITLIMIT0L    0xffU
+#define V_COMMITLIMIT0L(x) ((x) << S_COMMITLIMIT0L)
+#define G_COMMITLIMIT0L(x) (((x) >> S_COMMITLIMIT0L) & M_COMMITLIMIT0L)
+
+#define A_TP_IPMI_CFG1 0x2e
+
+#define S_VLANENABLE    31
+#define V_VLANENABLE(x) ((x) << S_VLANENABLE)
+#define F_VLANENABLE    V_VLANENABLE(1U)
+
+#define S_PRIMARYPORTENABLE    30
+#define V_PRIMARYPORTENABLE(x) ((x) << S_PRIMARYPORTENABLE)
+#define F_PRIMARYPORTENABLE    V_PRIMARYPORTENABLE(1U)
+
+#define S_SECUREPORTENABLE    29
+#define V_SECUREPORTENABLE(x) ((x) << S_SECUREPORTENABLE)
+#define F_SECUREPORTENABLE    V_SECUREPORTENABLE(1U)
+
+#define S_ARPENABLE    28
+#define V_ARPENABLE(x) ((x) << S_ARPENABLE)
+#define F_ARPENABLE    V_ARPENABLE(1U)
+
+#define S_IPMI_VLAN    0
+#define M_IPMI_VLAN    0xffffU
+#define V_IPMI_VLAN(x) ((x) << S_IPMI_VLAN)
+#define G_IPMI_VLAN(x) (((x) >> S_IPMI_VLAN) & M_IPMI_VLAN)
+
+#define A_TP_IPMI_CFG2 0x2f
+
+#define S_SECUREPORT    16
+#define M_SECUREPORT    0xffffU
+#define V_SECUREPORT(x) ((x) << S_SECUREPORT)
+#define G_SECUREPORT(x) (((x) >> S_SECUREPORT) & M_SECUREPORT)
+
+#define S_PRIMARYPORT    0
+#define M_PRIMARYPORT    0xffffU
+#define V_PRIMARYPORT(x) ((x) << S_PRIMARYPORT)
+#define G_PRIMARYPORT(x) (((x) >> S_PRIMARYPORT) & M_PRIMARYPORT)
+
+#define A_TP_RSS_PF0_CONFIG 0x30
+
+#define S_MAPENABLE    31
+#define V_MAPENABLE(x) ((x) << S_MAPENABLE)
+#define F_MAPENABLE    V_MAPENABLE(1U)
+
+#define S_CHNENABLE    30
+#define V_CHNENABLE(x) ((x) << S_CHNENABLE)
+#define F_CHNENABLE    V_CHNENABLE(1U)
+
+#define S_PRTENABLE    29
+#define V_PRTENABLE(x) ((x) << S_PRTENABLE)
+#define F_PRTENABLE    V_PRTENABLE(1U)
+
+#define S_UDPFOURTUPEN    28
+#define V_UDPFOURTUPEN(x) ((x) << S_UDPFOURTUPEN)
+#define F_UDPFOURTUPEN    V_UDPFOURTUPEN(1U)
+
+#define S_IP6FOURTUPEN    27
+#define V_IP6FOURTUPEN(x) ((x) << S_IP6FOURTUPEN)
+#define F_IP6FOURTUPEN    V_IP6FOURTUPEN(1U)
+
+#define S_IP6TWOTUPEN    26
+#define V_IP6TWOTUPEN(x) ((x) << S_IP6TWOTUPEN)
+#define F_IP6TWOTUPEN    V_IP6TWOTUPEN(1U)
+
+#define S_IP4FOURTUPEN    25
+#define V_IP4FOURTUPEN(x) ((x) << S_IP4FOURTUPEN)
+#define F_IP4FOURTUPEN    V_IP4FOURTUPEN(1U)
+
+#define S_IP4TWOTUPEN    24
+#define V_IP4TWOTUPEN(x) ((x) << S_IP4TWOTUPEN)
+#define F_IP4TWOTUPEN    V_IP4TWOTUPEN(1U)
+
+#define S_IVFWIDTH    20
+#define M_IVFWIDTH    0xfU
+#define V_IVFWIDTH(x) ((x) << S_IVFWIDTH)
+#define G_IVFWIDTH(x) (((x) >> S_IVFWIDTH) & M_IVFWIDTH)
+
+#define S_CH1DEFAULTQUEUE    10
+#define M_CH1DEFAULTQUEUE    0x3ffU
+#define V_CH1DEFAULTQUEUE(x) ((x) << S_CH1DEFAULTQUEUE)
+#define G_CH1DEFAULTQUEUE(x) (((x) >> S_CH1DEFAULTQUEUE) & M_CH1DEFAULTQUEUE)
+
+#define S_CH0DEFAULTQUEUE    0
+#define M_CH0DEFAULTQUEUE    0x3ffU
+#define V_CH0DEFAULTQUEUE(x) ((x) << S_CH0DEFAULTQUEUE)
+#define G_CH0DEFAULTQUEUE(x) (((x) >> S_CH0DEFAULTQUEUE) & M_CH0DEFAULTQUEUE)
+
+#define A_TP_RSS_PF1_CONFIG 0x31
+#define A_TP_RSS_PF2_CONFIG 0x32
+#define A_TP_RSS_PF3_CONFIG 0x33
+#define A_TP_RSS_PF4_CONFIG 0x34
+#define A_TP_RSS_PF5_CONFIG 0x35
+#define A_TP_RSS_PF6_CONFIG 0x36
+#define A_TP_RSS_PF7_CONFIG 0x37
+#define A_TP_RSS_PF_MAP 0x38
+
+#define S_LKPIDXSIZE    24
+#define M_LKPIDXSIZE    0x3U
+#define V_LKPIDXSIZE(x) ((x) << S_LKPIDXSIZE)
+#define G_LKPIDXSIZE(x) (((x) >> S_LKPIDXSIZE) & M_LKPIDXSIZE)
+
+#define S_PF7LKPIDX    21
+#define M_PF7LKPIDX    0x7U
+#define V_PF7LKPIDX(x) ((x) << S_PF7LKPIDX)
+#define G_PF7LKPIDX(x) (((x) >> S_PF7LKPIDX) & M_PF7LKPIDX)
+
+#define S_PF6LKPIDX    18
+#define M_PF6LKPIDX    0x7U
+#define V_PF6LKPIDX(x) ((x) << S_PF6LKPIDX)
+#define G_PF6LKPIDX(x) (((x) >> S_PF6LKPIDX) & M_PF6LKPIDX)
+
+#define S_PF5LKPIDX    15
+#define M_PF5LKPIDX    0x7U
+#define V_PF5LKPIDX(x) ((x) << S_PF5LKPIDX)
+#define G_PF5LKPIDX(x) (((x) >> S_PF5LKPIDX) & M_PF5LKPIDX)
+
+#define S_PF4LKPIDX    12
+#define M_PF4LKPIDX    0x7U
+#define V_PF4LKPIDX(x) ((x) << S_PF4LKPIDX)
+#define G_PF4LKPIDX(x) (((x) >> S_PF4LKPIDX) & M_PF4LKPIDX)
+
+#define S_PF3LKPIDX    9
+#define M_PF3LKPIDX    0x7U
+#define V_PF3LKPIDX(x) ((x) << S_PF3LKPIDX)
+#define G_PF3LKPIDX(x) (((x) >> S_PF3LKPIDX) & M_PF3LKPIDX)
+
+#define S_PF2LKPIDX    6
+#define M_PF2LKPIDX    0x7U
+#define V_PF2LKPIDX(x) ((x) << S_PF2LKPIDX)
+#define G_PF2LKPIDX(x) (((x) >> S_PF2LKPIDX) & M_PF2LKPIDX)
+
+#define S_PF1LKPIDX    3
+#define M_PF1LKPIDX    0x7U
+#define V_PF1LKPIDX(x) ((x) << S_PF1LKPIDX)
+#define G_PF1LKPIDX(x) (((x) >> S_PF1LKPIDX) & M_PF1LKPIDX)
+
+#define S_PF0LKPIDX    0
+#define M_PF0LKPIDX    0x7U
+#define V_PF0LKPIDX(x) ((x) << S_PF0LKPIDX)
+#define G_PF0LKPIDX(x) (((x) >> S_PF0LKPIDX) & M_PF0LKPIDX)
+
+#define A_TP_RSS_PF_MSK 0x39
+
+#define S_PF7MSKSIZE    28
+#define M_PF7MSKSIZE    0xfU
+#define V_PF7MSKSIZE(x) ((x) << S_PF7MSKSIZE)
+#define G_PF7MSKSIZE(x) (((x) >> S_PF7MSKSIZE) & M_PF7MSKSIZE)
+
+#define S_PF6MSKSIZE    24
+#define M_PF6MSKSIZE    0xfU
+#define V_PF6MSKSIZE(x) ((x) << S_PF6MSKSIZE)
+#define G_PF6MSKSIZE(x) (((x) >> S_PF6MSKSIZE) & M_PF6MSKSIZE)
+
+#define S_PF5MSKSIZE    20
+#define M_PF5MSKSIZE    0xfU
+#define V_PF5MSKSIZE(x) ((x) << S_PF5MSKSIZE)
+#define G_PF5MSKSIZE(x) (((x) >> S_PF5MSKSIZE) & M_PF5MSKSIZE)
+
+#define S_PF4MSKSIZE    16
+#define M_PF4MSKSIZE    0xfU
+#define V_PF4MSKSIZE(x) ((x) << S_PF4MSKSIZE)
+#define G_PF4MSKSIZE(x) (((x) >> S_PF4MSKSIZE) & M_PF4MSKSIZE)
+
+#define S_PF3MSKSIZE    12
+#define M_PF3MSKSIZE    0xfU
+#define V_PF3MSKSIZE(x) ((x) << S_PF3MSKSIZE)
+#define G_PF3MSKSIZE(x) (((x) >> S_PF3MSKSIZE) & M_PF3MSKSIZE)
+
+#define S_PF2MSKSIZE    8
+#define M_PF2MSKSIZE    0xfU
+#define V_PF2MSKSIZE(x) ((x) << S_PF2MSKSIZE)
+#define G_PF2MSKSIZE(x) (((x) >> S_PF2MSKSIZE) & M_PF2MSKSIZE)
+
+#define S_PF1MSKSIZE    4
+#define M_PF1MSKSIZE    0xfU
+#define V_PF1MSKSIZE(x) ((x) << S_PF1MSKSIZE)
+#define G_PF1MSKSIZE(x) (((x) >> S_PF1MSKSIZE) & M_PF1MSKSIZE)
+
+#define S_PF0MSKSIZE    0
+#define M_PF0MSKSIZE    0xfU
+#define V_PF0MSKSIZE(x) ((x) << S_PF0MSKSIZE)
+#define G_PF0MSKSIZE(x) (((x) >> S_PF0MSKSIZE) & M_PF0MSKSIZE)
+
+#define A_TP_RSS_VFL_CONFIG 0x3a
+#define A_TP_RSS_VFH_CONFIG 0x3b
+
+#define S_ENABLEUDPHASH    31
+#define V_ENABLEUDPHASH(x) ((x) << S_ENABLEUDPHASH)
+#define F_ENABLEUDPHASH    V_ENABLEUDPHASH(1U)
+
+#define S_VFUPEN    30
+#define V_VFUPEN(x) ((x) << S_VFUPEN)
+#define F_VFUPEN    V_VFUPEN(1U)
+
+#define S_VFVLNEX    28
+#define V_VFVLNEX(x) ((x) << S_VFVLNEX)
+#define F_VFVLNEX    V_VFVLNEX(1U)
+
+#define S_VFPRTEN    27
+#define V_VFPRTEN(x) ((x) << S_VFPRTEN)
+#define F_VFPRTEN    V_VFPRTEN(1U)
+
+#define S_VFCHNEN    26
+#define V_VFCHNEN(x) ((x) << S_VFCHNEN)
+#define F_VFCHNEN    V_VFCHNEN(1U)
+
+#define S_DEFAULTQUEUE    16
+#define M_DEFAULTQUEUE    0x3ffU
+#define V_DEFAULTQUEUE(x) ((x) << S_DEFAULTQUEUE)
+#define G_DEFAULTQUEUE(x) (((x) >> S_DEFAULTQUEUE) & M_DEFAULTQUEUE)
+
+#define S_VFLKPIDX    8
+#define M_VFLKPIDX    0xffU
+#define V_VFLKPIDX(x) ((x) << S_VFLKPIDX)
+#define G_VFLKPIDX(x) (((x) >> S_VFLKPIDX) & M_VFLKPIDX)
+
+#define S_VFIP6FOURTUPEN    7
+#define V_VFIP6FOURTUPEN(x) ((x) << S_VFIP6FOURTUPEN)
+#define F_VFIP6FOURTUPEN    V_VFIP6FOURTUPEN(1U)
+
+#define S_VFIP6TWOTUPEN    6
+#define V_VFIP6TWOTUPEN(x) ((x) << S_VFIP6TWOTUPEN)
+#define F_VFIP6TWOTUPEN    V_VFIP6TWOTUPEN(1U)
+
+#define S_VFIP4FOURTUPEN    5
+#define V_VFIP4FOURTUPEN(x) ((x) << S_VFIP4FOURTUPEN)
+#define F_VFIP4FOURTUPEN    V_VFIP4FOURTUPEN(1U)
+
+#define S_VFIP4TWOTUPEN    4
+#define V_VFIP4TWOTUPEN(x) ((x) << S_VFIP4TWOTUPEN)
+#define F_VFIP4TWOTUPEN    V_VFIP4TWOTUPEN(1U)
+
+#define S_KEYINDEX    0
+#define M_KEYINDEX    0xfU
+#define V_KEYINDEX(x) ((x) << S_KEYINDEX)
+#define G_KEYINDEX(x) (((x) >> S_KEYINDEX) & M_KEYINDEX)
+
+#define A_TP_RSS_SECRET_KEY0 0x40
+#define A_TP_RSS_SECRET_KEY1 0x41
+#define A_TP_RSS_SECRET_KEY2 0x42
+#define A_TP_RSS_SECRET_KEY3 0x43
+#define A_TP_RSS_SECRET_KEY4 0x44
+#define A_TP_RSS_SECRET_KEY5 0x45
+#define A_TP_RSS_SECRET_KEY6 0x46
+#define A_TP_RSS_SECRET_KEY7 0x47
+#define A_TP_RSS_SECRET_KEY8 0x48
+#define A_TP_RSS_SECRET_KEY9 0x49
+#define A_TP_ETHER_TYPE_VL 0x50
+
+#define S_CQFCTYPE    16
+#define M_CQFCTYPE    0xffffU
+#define V_CQFCTYPE(x) ((x) << S_CQFCTYPE)
+#define G_CQFCTYPE(x) (((x) >> S_CQFCTYPE) & M_CQFCTYPE)
+
+#define S_VLANTYPE    0
+#define M_VLANTYPE    0xffffU
+#define V_VLANTYPE(x) ((x) << S_VLANTYPE)
+#define G_VLANTYPE(x) (((x) >> S_VLANTYPE) & M_VLANTYPE)
+
+#define A_TP_ETHER_TYPE_IP 0x51
+
+#define S_IPV6TYPE    16
+#define M_IPV6TYPE    0xffffU
+#define V_IPV6TYPE(x) ((x) << S_IPV6TYPE)
+#define G_IPV6TYPE(x) (((x) >> S_IPV6TYPE) & M_IPV6TYPE)
+
+#define S_IPV4TYPE    0
+#define M_IPV4TYPE    0xffffU
+#define V_IPV4TYPE(x) ((x) << S_IPV4TYPE)
+#define G_IPV4TYPE(x) (((x) >> S_IPV4TYPE) & M_IPV4TYPE)
+
+#define A_TP_ETHER_TYPE_FW 0x52
+
+#define S_ETHTYPE1    16
+#define M_ETHTYPE1    0xffffU
+#define V_ETHTYPE1(x) ((x) << S_ETHTYPE1)
+#define G_ETHTYPE1(x) (((x) >> S_ETHTYPE1) & M_ETHTYPE1)
+
+#define S_ETHTYPE0    0
+#define M_ETHTYPE0    0xffffU
+#define V_ETHTYPE0(x) ((x) << S_ETHTYPE0)
+#define G_ETHTYPE0(x) (((x) >> S_ETHTYPE0) & M_ETHTYPE0)
+
+#define A_TP_CORE_POWER 0x54
+
+#define S_SLEEPRDYVNT    12
+#define V_SLEEPRDYVNT(x) ((x) << S_SLEEPRDYVNT)
+#define F_SLEEPRDYVNT    V_SLEEPRDYVNT(1U)
+
+#define S_SLEEPRDYTBL    11
+#define V_SLEEPRDYTBL(x) ((x) << S_SLEEPRDYTBL)
+#define F_SLEEPRDYTBL    V_SLEEPRDYTBL(1U)
+
+#define S_SLEEPRDYMIB    10
+#define V_SLEEPRDYMIB(x) ((x) << S_SLEEPRDYMIB)
+#define F_SLEEPRDYMIB    V_SLEEPRDYMIB(1U)
+
+#define S_SLEEPRDYARP    9
+#define V_SLEEPRDYARP(x) ((x) << S_SLEEPRDYARP)
+#define F_SLEEPRDYARP    V_SLEEPRDYARP(1U)
+
+#define S_SLEEPRDYRSS    8
+#define V_SLEEPRDYRSS(x) ((x) << S_SLEEPRDYRSS)
+#define F_SLEEPRDYRSS    V_SLEEPRDYRSS(1U)
+
+#define S_SLEEPREQVNT    4
+#define V_SLEEPREQVNT(x) ((x) << S_SLEEPREQVNT)
+#define F_SLEEPREQVNT    V_SLEEPREQVNT(1U)
+
+#define S_SLEEPREQTBL    3
+#define V_SLEEPREQTBL(x) ((x) << S_SLEEPREQTBL)
+#define F_SLEEPREQTBL    V_SLEEPREQTBL(1U)
+
+#define S_SLEEPREQMIB    2
+#define V_SLEEPREQMIB(x) ((x) << S_SLEEPREQMIB)
+#define F_SLEEPREQMIB    V_SLEEPREQMIB(1U)
+
+#define S_SLEEPREQARP    1
+#define V_SLEEPREQARP(x) ((x) << S_SLEEPREQARP)
+#define F_SLEEPREQARP    V_SLEEPREQARP(1U)
+
+#define S_SLEEPREQRSS    0
+#define V_SLEEPREQRSS(x) ((x) << S_SLEEPREQRSS)
+#define F_SLEEPREQRSS    V_SLEEPREQRSS(1U)
+
+#define A_TP_CORE_RDMA 0x55
+
+#define S_IMMEDIATEOP    20
+#define M_IMMEDIATEOP    0xfU
+#define V_IMMEDIATEOP(x) ((x) << S_IMMEDIATEOP)
+#define G_IMMEDIATEOP(x) (((x) >> S_IMMEDIATEOP) & M_IMMEDIATEOP)
+
+#define S_IMMEDIATESE    16
+#define M_IMMEDIATESE    0xfU
+#define V_IMMEDIATESE(x) ((x) << S_IMMEDIATESE)
+#define G_IMMEDIATESE(x) (((x) >> S_IMMEDIATESE) & M_IMMEDIATESE)
+
+#define S_ATOMICREQOP    12
+#define M_ATOMICREQOP    0xfU
+#define V_ATOMICREQOP(x) ((x) << S_ATOMICREQOP)
+#define G_ATOMICREQOP(x) (((x) >> S_ATOMICREQOP) & M_ATOMICREQOP)
+
+#define S_ATOMICRSPOP    8
+#define M_ATOMICRSPOP    0xfU
+#define V_ATOMICRSPOP(x) ((x) << S_ATOMICRSPOP)
+#define G_ATOMICRSPOP(x) (((x) >> S_ATOMICRSPOP) & M_ATOMICRSPOP)
+
+#define S_IMMEDIASEEN    1
+#define V_IMMEDIASEEN(x) ((x) << S_IMMEDIASEEN)
+#define F_IMMEDIASEEN    V_IMMEDIASEEN(1U)
+
+#define S_IMMEDIATEEN    0
+#define V_IMMEDIATEEN(x) ((x) << S_IMMEDIATEEN)
+#define F_IMMEDIATEEN    V_IMMEDIATEEN(1U)
+
+#define A_TP_DBG_CLEAR 0x60
+#define A_TP_DBG_CORE_HDR0 0x61
+
+#define S_E_TCP_OP_SRDY    16
+#define V_E_TCP_OP_SRDY(x) ((x) << S_E_TCP_OP_SRDY)
+#define F_E_TCP_OP_SRDY    V_E_TCP_OP_SRDY(1U)
+
+#define S_E_PLD_TXZEROP_SRDY    15
+#define V_E_PLD_TXZEROP_SRDY(x) ((x) << S_E_PLD_TXZEROP_SRDY)
+#define F_E_PLD_TXZEROP_SRDY    V_E_PLD_TXZEROP_SRDY(1U)
+
+#define S_E_PLD_RX_SRDY    14
+#define V_E_PLD_RX_SRDY(x) ((x) << S_E_PLD_RX_SRDY)
+#define F_E_PLD_RX_SRDY    V_E_PLD_RX_SRDY(1U)
+
+#define S_E_RX_ERROR_SRDY    13
+#define V_E_RX_ERROR_SRDY(x) ((x) << S_E_RX_ERROR_SRDY)
+#define F_E_RX_ERROR_SRDY    V_E_RX_ERROR_SRDY(1U)
+
+#define S_E_RX_ISS_SRDY    12
+#define V_E_RX_ISS_SRDY(x) ((x) << S_E_RX_ISS_SRDY)
+#define F_E_RX_ISS_SRDY    V_E_RX_ISS_SRDY(1U)
+
+#define S_C_TCP_OP_SRDY    11
+#define V_C_TCP_OP_SRDY(x) ((x) << S_C_TCP_OP_SRDY)
+#define F_C_TCP_OP_SRDY    V_C_TCP_OP_SRDY(1U)
+
+#define S_C_PLD_TXZEROP_SRDY    10
+#define V_C_PLD_TXZEROP_SRDY(x) ((x) << S_C_PLD_TXZEROP_SRDY)
+#define F_C_PLD_TXZEROP_SRDY    V_C_PLD_TXZEROP_SRDY(1U)
+
+#define S_C_PLD_RX_SRDY    9
+#define V_C_PLD_RX_SRDY(x) ((x) << S_C_PLD_RX_SRDY)
+#define F_C_PLD_RX_SRDY    V_C_PLD_RX_SRDY(1U)
+
+#define S_C_RX_ERROR_SRDY    8
+#define V_C_RX_ERROR_SRDY(x) ((x) << S_C_RX_ERROR_SRDY)
+#define F_C_RX_ERROR_SRDY    V_C_RX_ERROR_SRDY(1U)
+
+#define S_C_RX_ISS_SRDY    7
+#define V_C_RX_ISS_SRDY(x) ((x) << S_C_RX_ISS_SRDY)
+#define F_C_RX_ISS_SRDY    V_C_RX_ISS_SRDY(1U)
+
+#define S_E_CPL5_TXVALID    6
+#define V_E_CPL5_TXVALID(x) ((x) << S_E_CPL5_TXVALID)
+#define F_E_CPL5_TXVALID    V_E_CPL5_TXVALID(1U)
+
+#define S_E_ETH_TXVALID    5
+#define V_E_ETH_TXVALID(x) ((x) << S_E_ETH_TXVALID)
+#define F_E_ETH_TXVALID    V_E_ETH_TXVALID(1U)
+
+#define S_E_IP_TXVALID    4
+#define V_E_IP_TXVALID(x) ((x) << S_E_IP_TXVALID)
+#define F_E_IP_TXVALID    V_E_IP_TXVALID(1U)
+
+#define S_E_TCP_TXVALID    3
+#define V_E_TCP_TXVALID(x) ((x) << S_E_TCP_TXVALID)
+#define F_E_TCP_TXVALID    V_E_TCP_TXVALID(1U)
+
+#define S_C_CPL5_RXVALID    2
+#define V_C_CPL5_RXVALID(x) ((x) << S_C_CPL5_RXVALID)
+#define F_C_CPL5_RXVALID    V_C_CPL5_RXVALID(1U)
+
+#define S_C_CPL5_TXVALID    1
+#define V_C_CPL5_TXVALID(x) ((x) << S_C_CPL5_TXVALID)
+#define F_C_CPL5_TXVALID    V_C_CPL5_TXVALID(1U)
+
+#define S_E_TCP_OPT_RXVALID    0
+#define V_E_TCP_OPT_RXVALID(x) ((x) << S_E_TCP_OPT_RXVALID)
+#define F_E_TCP_OPT_RXVALID    V_E_TCP_OPT_RXVALID(1U)
+
+#define A_TP_DBG_CORE_HDR1 0x62
+
+#define S_E_CPL5_TXFULL    6
+#define V_E_CPL5_TXFULL(x) ((x) << S_E_CPL5_TXFULL)
+#define F_E_CPL5_TXFULL    V_E_CPL5_TXFULL(1U)
+
+#define S_E_ETH_TXFULL    5
+#define V_E_ETH_TXFULL(x) ((x) << S_E_ETH_TXFULL)
+#define F_E_ETH_TXFULL    V_E_ETH_TXFULL(1U)
+
+#define S_E_IP_TXFULL    4
+#define V_E_IP_TXFULL(x) ((x) << S_E_IP_TXFULL)
+#define F_E_IP_TXFULL    V_E_IP_TXFULL(1U)
+
+#define S_E_TCP_TXFULL    3
+#define V_E_TCP_TXFULL(x) ((x) << S_E_TCP_TXFULL)
+#define F_E_TCP_TXFULL    V_E_TCP_TXFULL(1U)
+
+#define S_C_CPL5_RXFULL    2
+#define V_C_CPL5_RXFULL(x) ((x) << S_C_CPL5_RXFULL)
+#define F_C_CPL5_RXFULL    V_C_CPL5_RXFULL(1U)
+
+#define S_C_CPL5_TXFULL    1
+#define V_C_CPL5_TXFULL(x) ((x) << S_C_CPL5_TXFULL)
+#define F_C_CPL5_TXFULL    V_C_CPL5_TXFULL(1U)
+
+#define S_E_TCP_OPT_RXFULL    0
+#define V_E_TCP_OPT_RXFULL(x) ((x) << S_E_TCP_OPT_RXFULL)
+#define F_E_TCP_OPT_RXFULL    V_E_TCP_OPT_RXFULL(1U)
+
+#define A_TP_DBG_CORE_FATAL 0x63
+
+#define S_EMSGFATAL    31
+#define V_EMSGFATAL(x) ((x) << S_EMSGFATAL)
+#define F_EMSGFATAL    V_EMSGFATAL(1U)
+
+#define S_CMSGFATAL    30
+#define V_CMSGFATAL(x) ((x) << S_CMSGFATAL)
+#define F_CMSGFATAL    V_CMSGFATAL(1U)
+
+#define S_PAWSFATAL    29
+#define V_PAWSFATAL(x) ((x) << S_PAWSFATAL)
+#define F_PAWSFATAL    V_PAWSFATAL(1U)
+
+#define S_SRAMFATAL    28
+#define V_SRAMFATAL(x) ((x) << S_SRAMFATAL)
+#define F_SRAMFATAL    V_SRAMFATAL(1U)
+
+#define S_CPCMDCONG    24
+#define M_CPCMDCONG    0xfU
+#define V_CPCMDCONG(x) ((x) << S_CPCMDCONG)
+#define G_CPCMDCONG(x) (((x) >> S_CPCMDCONG) & M_CPCMDCONG)
+
+#define S_EPCMDCONG    22
+#define M_EPCMDCONG    0x3U
+#define V_EPCMDCONG(x) ((x) << S_EPCMDCONG)
+#define G_EPCMDCONG(x) (((x) >> S_EPCMDCONG) & M_EPCMDCONG)
+
+#define S_CPCMDLENFATAL    21
+#define V_CPCMDLENFATAL(x) ((x) << S_CPCMDLENFATAL)
+#define F_CPCMDLENFATAL    V_CPCMDLENFATAL(1U)
+
+#define S_EPCMDLENFATAL    20
+#define V_EPCMDLENFATAL(x) ((x) << S_EPCMDLENFATAL)
+#define F_EPCMDLENFATAL    V_EPCMDLENFATAL(1U)
+
+#define S_CPCMDVALID    16
+#define M_CPCMDVALID    0xfU
+#define V_CPCMDVALID(x) ((x) << S_CPCMDVALID)
+#define G_CPCMDVALID(x) (((x) >> S_CPCMDVALID) & M_CPCMDVALID)
+
+#define S_CPCMDAFULL    12
+#define M_CPCMDAFULL    0xfU
+#define V_CPCMDAFULL(x) ((x) << S_CPCMDAFULL)
+#define G_CPCMDAFULL(x) (((x) >> S_CPCMDAFULL) & M_CPCMDAFULL)
+
+#define S_EPCMDVALID    10
+#define M_EPCMDVALID    0x3U
+#define V_EPCMDVALID(x) ((x) << S_EPCMDVALID)
+#define G_EPCMDVALID(x) (((x) >> S_EPCMDVALID) & M_EPCMDVALID)
+
+#define S_EPCMDAFULL    8
+#define M_EPCMDAFULL    0x3U
+#define V_EPCMDAFULL(x) ((x) << S_EPCMDAFULL)
+#define G_EPCMDAFULL(x) (((x) >> S_EPCMDAFULL) & M_EPCMDAFULL)
+
+#define S_CPCMDEOIFATAL    7
+#define V_CPCMDEOIFATAL(x) ((x) << S_CPCMDEOIFATAL)
+#define F_CPCMDEOIFATAL    V_CPCMDEOIFATAL(1U)
+
+#define S_CMDBRQFATAL    4
+#define V_CMDBRQFATAL(x) ((x) << S_CMDBRQFATAL)
+#define F_CMDBRQFATAL    V_CMDBRQFATAL(1U)
+
+#define S_CNONZEROPPOPCNT    2
+#define M_CNONZEROPPOPCNT    0x3U
+#define V_CNONZEROPPOPCNT(x) ((x) << S_CNONZEROPPOPCNT)
+#define G_CNONZEROPPOPCNT(x) (((x) >> S_CNONZEROPPOPCNT) & M_CNONZEROPPOPCNT)
+
+#define S_CPCMDEOICNT    0
+#define M_CPCMDEOICNT    0x3U
+#define V_CPCMDEOICNT(x) ((x) << S_CPCMDEOICNT)
+#define G_CPCMDEOICNT(x) (((x) >> S_CPCMDEOICNT) & M_CPCMDEOICNT)
+
+#define S_CPCMDTTLFATAL    6
+#define V_CPCMDTTLFATAL(x) ((x) << S_CPCMDTTLFATAL)
+#define F_CPCMDTTLFATAL    V_CPCMDTTLFATAL(1U)
+
+#define S_CDATACHNFATAL    5
+#define V_CDATACHNFATAL(x) ((x) << S_CDATACHNFATAL)
+#define F_CDATACHNFATAL    V_CDATACHNFATAL(1U)
+
+#define A_TP_DBG_CORE_OUT 0x64
+
+#define S_CCPLENC    26
+#define V_CCPLENC(x) ((x) << S_CCPLENC)
+#define F_CCPLENC    V_CCPLENC(1U)
+
+#define S_CWRCPLPKT    25
+#define V_CWRCPLPKT(x) ((x) << S_CWRCPLPKT)
+#define F_CWRCPLPKT    V_CWRCPLPKT(1U)
+
+#define S_CWRETHPKT    24
+#define V_CWRETHPKT(x) ((x) << S_CWRETHPKT)
+#define F_CWRETHPKT    V_CWRETHPKT(1U)
+
+#define S_CWRIPPKT    23
+#define V_CWRIPPKT(x) ((x) << S_CWRIPPKT)
+#define F_CWRIPPKT    V_CWRIPPKT(1U)
+
+#define S_CWRTCPPKT    22
+#define V_CWRTCPPKT(x) ((x) << S_CWRTCPPKT)
+#define F_CWRTCPPKT    V_CWRTCPPKT(1U)
+
+#define S_CWRZEROP    21
+#define V_CWRZEROP(x) ((x) << S_CWRZEROP)
+#define F_CWRZEROP    V_CWRZEROP(1U)
+
+#define S_CCPLTXFULL    20
+#define V_CCPLTXFULL(x) ((x) << S_CCPLTXFULL)
+#define F_CCPLTXFULL    V_CCPLTXFULL(1U)
+
+#define S_CETHTXFULL    19
+#define V_CETHTXFULL(x) ((x) << S_CETHTXFULL)
+#define F_CETHTXFULL    V_CETHTXFULL(1U)
+
+#define S_CIPTXFULL    18
+#define V_CIPTXFULL(x) ((x) << S_CIPTXFULL)
+#define F_CIPTXFULL    V_CIPTXFULL(1U)
+
+#define S_CTCPTXFULL    17
+#define V_CTCPTXFULL(x) ((x) << S_CTCPTXFULL)
+#define F_CTCPTXFULL    V_CTCPTXFULL(1U)
+
+#define S_CPLDTXZEROPDRDY    16
+#define V_CPLDTXZEROPDRDY(x) ((x) << S_CPLDTXZEROPDRDY)
+#define F_CPLDTXZEROPDRDY    V_CPLDTXZEROPDRDY(1U)
+
+#define S_ECPLENC    10
+#define V_ECPLENC(x) ((x) << S_ECPLENC)
+#define F_ECPLENC    V_ECPLENC(1U)
+
+#define S_EWRCPLPKT    9
+#define V_EWRCPLPKT(x) ((x) << S_EWRCPLPKT)
+#define F_EWRCPLPKT    V_EWRCPLPKT(1U)
+
+#define S_EWRETHPKT    8
+#define V_EWRETHPKT(x) ((x) << S_EWRETHPKT)
+#define F_EWRETHPKT    V_EWRETHPKT(1U)
+
+#define S_EWRIPPKT    7
+#define V_EWRIPPKT(x) ((x) << S_EWRIPPKT)
+#define F_EWRIPPKT    V_EWRIPPKT(1U)
+
+#define S_EWRTCPPKT    6
+#define V_EWRTCPPKT(x) ((x) << S_EWRTCPPKT)
+#define F_EWRTCPPKT    V_EWRTCPPKT(1U)
+
+#define S_EWRZEROP    5
+#define V_EWRZEROP(x) ((x) << S_EWRZEROP)
+#define F_EWRZEROP    V_EWRZEROP(1U)
+
+#define S_ECPLTXFULL    4
+#define V_ECPLTXFULL(x) ((x) << S_ECPLTXFULL)
+#define F_ECPLTXFULL    V_ECPLTXFULL(1U)
+
+#define S_EETHTXFULL    3
+#define V_EETHTXFULL(x) ((x) << S_EETHTXFULL)
+#define F_EETHTXFULL    V_EETHTXFULL(1U)
+
+#define S_EIPTXFULL    2
+#define V_EIPTXFULL(x) ((x) << S_EIPTXFULL)
+#define F_EIPTXFULL    V_EIPTXFULL(1U)
+
+#define S_ETCPTXFULL    1
+#define V_ETCPTXFULL(x) ((x) << S_ETCPTXFULL)
+#define F_ETCPTXFULL    V_ETCPTXFULL(1U)
+
+#define S_EPLDTXZEROPDRDY    0
+#define V_EPLDTXZEROPDRDY(x) ((x) << S_EPLDTXZEROPDRDY)
+#define F_EPLDTXZEROPDRDY    V_EPLDTXZEROPDRDY(1U)
+
+#define S_CRXBUSYOUT    31
+#define V_CRXBUSYOUT(x) ((x) << S_CRXBUSYOUT)
+#define F_CRXBUSYOUT    V_CRXBUSYOUT(1U)
+
+#define S_CTXBUSYOUT    30
+#define V_CTXBUSYOUT(x) ((x) << S_CTXBUSYOUT)
+#define F_CTXBUSYOUT    V_CTXBUSYOUT(1U)
+
+#define S_CRDCPLPKT    29
+#define V_CRDCPLPKT(x) ((x) << S_CRDCPLPKT)
+#define F_CRDCPLPKT    V_CRDCPLPKT(1U)
+
+#define S_CRDTCPPKT    28
+#define V_CRDTCPPKT(x) ((x) << S_CRDTCPPKT)
+#define F_CRDTCPPKT    V_CRDTCPPKT(1U)
+
+#define S_CNEWMSG    27
+#define V_CNEWMSG(x) ((x) << S_CNEWMSG)
+#define F_CNEWMSG    V_CNEWMSG(1U)
+
+#define S_ERXBUSYOUT    15
+#define V_ERXBUSYOUT(x) ((x) << S_ERXBUSYOUT)
+#define F_ERXBUSYOUT    V_ERXBUSYOUT(1U)
+
+#define S_ETXBUSYOUT    14
+#define V_ETXBUSYOUT(x) ((x) << S_ETXBUSYOUT)
+#define F_ETXBUSYOUT    V_ETXBUSYOUT(1U)
+
+#define S_ERDCPLPKT    13
+#define V_ERDCPLPKT(x) ((x) << S_ERDCPLPKT)
+#define F_ERDCPLPKT    V_ERDCPLPKT(1U)
+
+#define S_ERDTCPPKT    12
+#define V_ERDTCPPKT(x) ((x) << S_ERDTCPPKT)
+#define F_ERDTCPPKT    V_ERDTCPPKT(1U)
+
+#define S_ENEWMSG    11
+#define V_ENEWMSG(x) ((x) << S_ENEWMSG)
+#define F_ENEWMSG    V_ENEWMSG(1U)
+
+#define A_TP_DBG_CORE_TID 0x65
+
+#define S_LINENUMBER    24
+#define M_LINENUMBER    0x7fU
+#define V_LINENUMBER(x) ((x) << S_LINENUMBER)
+#define G_LINENUMBER(x) (((x) >> S_LINENUMBER) & M_LINENUMBER)
+
+#define S_SPURIOUSMSG    23
+#define V_SPURIOUSMSG(x) ((x) << S_SPURIOUSMSG)
+#define F_SPURIOUSMSG    V_SPURIOUSMSG(1U)
+
+#define S_SYNLEARNED    20
+#define V_SYNLEARNED(x) ((x) << S_SYNLEARNED)
+#define F_SYNLEARNED    V_SYNLEARNED(1U)
+
+#define S_TIDVALUE    0
+#define M_TIDVALUE    0xfffffU
+#define V_TIDVALUE(x) ((x) << S_TIDVALUE)
+#define G_TIDVALUE(x) (((x) >> S_TIDVALUE) & M_TIDVALUE)
+
+#define S_SRC    21
+#define M_SRC    0x3U
+#define V_SRC(x) ((x) << S_SRC)
+#define G_SRC(x) (((x) >> S_SRC) & M_SRC)
+
+#define A_TP_DBG_ENG_RES0 0x66
+
+#define S_RESOURCESREADY    31
+#define V_RESOURCESREADY(x) ((x) << S_RESOURCESREADY)
+#define F_RESOURCESREADY    V_RESOURCESREADY(1U)
+
+#define S_RCFOPCODEOUTSRDY    30
+#define V_RCFOPCODEOUTSRDY(x) ((x) << S_RCFOPCODEOUTSRDY)
+#define F_RCFOPCODEOUTSRDY    V_RCFOPCODEOUTSRDY(1U)
+
+#define S_RCFDATAOUTSRDY    29
+#define V_RCFDATAOUTSRDY(x) ((x) << S_RCFDATAOUTSRDY)
+#define F_RCFDATAOUTSRDY    V_RCFDATAOUTSRDY(1U)
+
+#define S_FLUSHINPUTMSG    28
+#define V_FLUSHINPUTMSG(x) ((x) << S_FLUSHINPUTMSG)
+#define F_FLUSHINPUTMSG    V_FLUSHINPUTMSG(1U)
+
+#define S_RCFOPSRCOUT    26
+#define M_RCFOPSRCOUT    0x3U
+#define V_RCFOPSRCOUT(x) ((x) << S_RCFOPSRCOUT)
+#define G_RCFOPSRCOUT(x) (((x) >> S_RCFOPSRCOUT) & M_RCFOPSRCOUT)
+
+#define S_C_MSG    25
+#define V_C_MSG(x) ((x) << S_C_MSG)
+#define F_C_MSG    V_C_MSG(1U)
+
+#define S_E_MSG    24
+#define V_E_MSG(x) ((x) << S_E_MSG)
+#define F_E_MSG    V_E_MSG(1U)
+
+#define S_RCFOPCODEOUT    20
+#define M_RCFOPCODEOUT    0xfU
+#define V_RCFOPCODEOUT(x) ((x) << S_RCFOPCODEOUT)
+#define G_RCFOPCODEOUT(x) (((x) >> S_RCFOPCODEOUT) & M_RCFOPCODEOUT)
+
+#define S_EFFRCFOPCODEOUT    16
+#define M_EFFRCFOPCODEOUT    0xfU
+#define V_EFFRCFOPCODEOUT(x) ((x) << S_EFFRCFOPCODEOUT)
+#define G_EFFRCFOPCODEOUT(x) (((x) >> S_EFFRCFOPCODEOUT) & M_EFFRCFOPCODEOUT)
+
+#define S_SEENRESOURCESREADY    15
+#define V_SEENRESOURCESREADY(x) ((x) << S_SEENRESOURCESREADY)
+#define F_SEENRESOURCESREADY    V_SEENRESOURCESREADY(1U)
+
+#define S_RESOURCESREADYCOPY    14
+#define V_RESOURCESREADYCOPY(x) ((x) << S_RESOURCESREADYCOPY)
+#define F_RESOURCESREADYCOPY    V_RESOURCESREADYCOPY(1U)
+
+#define S_OPCODEWAITSFORDATA    13
+#define V_OPCODEWAITSFORDATA(x) ((x) << S_OPCODEWAITSFORDATA)
+#define F_OPCODEWAITSFORDATA    V_OPCODEWAITSFORDATA(1U)
+
+#define S_CPLDRXSRDY    12
+#define V_CPLDRXSRDY(x) ((x) << S_CPLDRXSRDY)
+#define F_CPLDRXSRDY    V_CPLDRXSRDY(1U)
+
+#define S_CPLDRXZEROPSRDY    11
+#define V_CPLDRXZEROPSRDY(x) ((x) << S_CPLDRXZEROPSRDY)
+#define F_CPLDRXZEROPSRDY    V_CPLDRXZEROPSRDY(1U)
+
+#define S_EPLDRXZEROPSRDY    10
+#define V_EPLDRXZEROPSRDY(x) ((x) << S_EPLDRXZEROPSRDY)
+#define F_EPLDRXZEROPSRDY    V_EPLDRXZEROPSRDY(1U)
+
+#define S_ERXERRORSRDY    9
+#define V_ERXERRORSRDY(x) ((x) << S_ERXERRORSRDY)
+#define F_ERXERRORSRDY    V_ERXERRORSRDY(1U)
+
+#define S_EPLDRXSRDY    8
+#define V_EPLDRXSRDY(x) ((x) << S_EPLDRXSRDY)
+#define F_EPLDRXSRDY    V_EPLDRXSRDY(1U)
+
+#define S_CRXBUSY    7
+#define V_CRXBUSY(x) ((x) << S_CRXBUSY)
+#define F_CRXBUSY    V_CRXBUSY(1U)
+
+#define S_ERXBUSY    6
+#define V_ERXBUSY(x) ((x) << S_ERXBUSY)
+#define F_ERXBUSY    V_ERXBUSY(1U)
+
+#define S_TIMERINSERTBUSY    5
+#define V_TIMERINSERTBUSY(x) ((x) << S_TIMERINSERTBUSY)
+#define F_TIMERINSERTBUSY    V_TIMERINSERTBUSY(1U)
+
+#define S_WCFBUSY    4
+#define V_WCFBUSY(x) ((x) << S_WCFBUSY)
+#define F_WCFBUSY    V_WCFBUSY(1U)
+
+#define S_CTXBUSY    3
+#define V_CTXBUSY(x) ((x) << S_CTXBUSY)
+#define F_CTXBUSY    V_CTXBUSY(1U)
+
+#define S_CPCMDBUSY    2
+#define V_CPCMDBUSY(x) ((x) << S_CPCMDBUSY)
+#define F_CPCMDBUSY    V_CPCMDBUSY(1U)
+
+#define S_EPCMDBUSY    1
+#define V_EPCMDBUSY(x) ((x) << S_EPCMDBUSY)
+#define F_EPCMDBUSY    V_EPCMDBUSY(1U)
+
+#define S_ETXBUSY    0
+#define V_ETXBUSY(x) ((x) << S_ETXBUSY)
+#define F_ETXBUSY    V_ETXBUSY(1U)
+
+#define S_EFFOPCODEOUT    16
+#define M_EFFOPCODEOUT    0xfU
+#define V_EFFOPCODEOUT(x) ((x) << S_EFFOPCODEOUT)
+#define G_EFFOPCODEOUT(x) (((x) >> S_EFFOPCODEOUT) & M_EFFOPCODEOUT)
+
+#define S_DELDRDY    14
+#define V_DELDRDY(x) ((x) << S_DELDRDY)
+#define F_DELDRDY    V_DELDRDY(1U)
+
+#define A_TP_DBG_ENG_RES1 0x67
+
+#define S_RXCPLSRDY    31
+#define V_RXCPLSRDY(x) ((x) << S_RXCPLSRDY)
+#define F_RXCPLSRDY    V_RXCPLSRDY(1U)
+
+#define S_RXOPTSRDY    30
+#define V_RXOPTSRDY(x) ((x) << S_RXOPTSRDY)
+#define F_RXOPTSRDY    V_RXOPTSRDY(1U)
+
+#define S_RXPLDLENSRDY    29
+#define V_RXPLDLENSRDY(x) ((x) << S_RXPLDLENSRDY)
+#define F_RXPLDLENSRDY    V_RXPLDLENSRDY(1U)
+
+#define S_RXNOTBUSY    28
+#define V_RXNOTBUSY(x) ((x) << S_RXNOTBUSY)
+#define F_RXNOTBUSY    V_RXNOTBUSY(1U)
+
+#define S_CPLCMDIN    20
+#define M_CPLCMDIN    0xffU
+#define V_CPLCMDIN(x) ((x) << S_CPLCMDIN)
+#define G_CPLCMDIN(x) (((x) >> S_CPLCMDIN) & M_CPLCMDIN)
+
+#define S_RCFPTIDSRDY    19
+#define V_RCFPTIDSRDY(x) ((x) << S_RCFPTIDSRDY)
+#define F_RCFPTIDSRDY    V_RCFPTIDSRDY(1U)
+
+#define S_EPDUHDRSRDY    18
+#define V_EPDUHDRSRDY(x) ((x) << S_EPDUHDRSRDY)
+#define F_EPDUHDRSRDY    V_EPDUHDRSRDY(1U)
+
+#define S_TUNNELPKTREG    17
+#define V_TUNNELPKTREG(x) ((x) << S_TUNNELPKTREG)
+#define F_TUNNELPKTREG    V_TUNNELPKTREG(1U)
+
+#define S_TXPKTCSUMSRDY    16
+#define V_TXPKTCSUMSRDY(x) ((x) << S_TXPKTCSUMSRDY)
+#define F_TXPKTCSUMSRDY    V_TXPKTCSUMSRDY(1U)
+
+#define S_TABLEACCESSLATENCY    12
+#define M_TABLEACCESSLATENCY    0xfU
+#define V_TABLEACCESSLATENCY(x) ((x) << S_TABLEACCESSLATENCY)
+#define G_TABLEACCESSLATENCY(x) (((x) >> S_TABLEACCESSLATENCY) & M_TABLEACCESSLATENCY)
+
+#define S_MMGRDONE    11
+#define V_MMGRDONE(x) ((x) << S_MMGRDONE)
+#define F_MMGRDONE    V_MMGRDONE(1U)
+
+#define S_SEENMMGRDONE    10
+#define V_SEENMMGRDONE(x) ((x) << S_SEENMMGRDONE)
+#define F_SEENMMGRDONE    V_SEENMMGRDONE(1U)
+
+#define S_RXERRORSRDY    9
+#define V_RXERRORSRDY(x) ((x) << S_RXERRORSRDY)
+#define F_RXERRORSRDY    V_RXERRORSRDY(1U)
+
+#define S_RCFOPTIONSTCPSRDY    8
+#define V_RCFOPTIONSTCPSRDY(x) ((x) << S_RCFOPTIONSTCPSRDY)
+#define F_RCFOPTIONSTCPSRDY    V_RCFOPTIONSTCPSRDY(1U)
+
+#define S_ENGINESTATE    6
+#define M_ENGINESTATE    0x3U
+#define V_ENGINESTATE(x) ((x) << S_ENGINESTATE)
+#define G_ENGINESTATE(x) (((x) >> S_ENGINESTATE) & M_ENGINESTATE)
+
+#define S_TABLEACCESINCREMENT    5
+#define V_TABLEACCESINCREMENT(x) ((x) << S_TABLEACCESINCREMENT)
+#define F_TABLEACCESINCREMENT    V_TABLEACCESINCREMENT(1U)
+
+#define S_TABLEACCESCOMPLETE    4
+#define V_TABLEACCESCOMPLETE(x) ((x) << S_TABLEACCESCOMPLETE)
+#define F_TABLEACCESCOMPLETE    V_TABLEACCESCOMPLETE(1U)
+
+#define S_RCFOPCODEOUTUSABLE    3
+#define V_RCFOPCODEOUTUSABLE(x) ((x) << S_RCFOPCODEOUTUSABLE)
+#define F_RCFOPCODEOUTUSABLE    V_RCFOPCODEOUTUSABLE(1U)
+
+#define S_RCFDATAOUTUSABLE    2
+#define V_RCFDATAOUTUSABLE(x) ((x) << S_RCFDATAOUTUSABLE)
+#define F_RCFDATAOUTUSABLE    V_RCFDATAOUTUSABLE(1U)
+
+#define S_RCFDATAWAITAFTERRD    1
+#define V_RCFDATAWAITAFTERRD(x) ((x) << S_RCFDATAWAITAFTERRD)
+#define F_RCFDATAWAITAFTERRD    V_RCFDATAWAITAFTERRD(1U)
+
+#define S_RCFDATACMRDY    0
+#define V_RCFDATACMRDY(x) ((x) << S_RCFDATACMRDY)
+#define F_RCFDATACMRDY    V_RCFDATACMRDY(1U)
+
+#define A_TP_DBG_ENG_RES2 0x68
+
+#define S_CPLCMDRAW    24
+#define M_CPLCMDRAW    0xffU
+#define V_CPLCMDRAW(x) ((x) << S_CPLCMDRAW)
+#define G_CPLCMDRAW(x) (((x) >> S_CPLCMDRAW) & M_CPLCMDRAW)
+
+#define S_RXMACPORT    20
+#define M_RXMACPORT    0xfU
+#define V_RXMACPORT(x) ((x) << S_RXMACPORT)
+#define G_RXMACPORT(x) (((x) >> S_RXMACPORT) & M_RXMACPORT)
+
+#define S_TXECHANNEL    18
+#define M_TXECHANNEL    0x3U
+#define V_TXECHANNEL(x) ((x) << S_TXECHANNEL)
+#define G_TXECHANNEL(x) (((x) >> S_TXECHANNEL) & M_TXECHANNEL)
+
+#define S_RXECHANNEL    16
+#define M_RXECHANNEL    0x3U
+#define V_RXECHANNEL(x) ((x) << S_RXECHANNEL)
+#define G_RXECHANNEL(x) (((x) >> S_RXECHANNEL) & M_RXECHANNEL)
+
+#define S_CDATAOUT    15
+#define V_CDATAOUT(x) ((x) << S_CDATAOUT)
+#define F_CDATAOUT    V_CDATAOUT(1U)
+
+#define S_CREADPDU    14
+#define V_CREADPDU(x) ((x) << S_CREADPDU)
+#define F_CREADPDU    V_CREADPDU(1U)
+
+#define S_EDATAOUT    13
+#define V_EDATAOUT(x) ((x) << S_EDATAOUT)
+#define F_EDATAOUT    V_EDATAOUT(1U)
+
+#define S_EREADPDU    12
+#define V_EREADPDU(x) ((x) << S_EREADPDU)
+#define F_EREADPDU    V_EREADPDU(1U)
+
+#define S_ETCPOPSRDY    11
+#define V_ETCPOPSRDY(x) ((x) << S_ETCPOPSRDY)
+#define F_ETCPOPSRDY    V_ETCPOPSRDY(1U)
+
+#define S_CTCPOPSRDY    10
+#define V_CTCPOPSRDY(x) ((x) << S_CTCPOPSRDY)
+#define F_CTCPOPSRDY    V_CTCPOPSRDY(1U)
+
+#define S_CPKTOUT    9
+#define V_CPKTOUT(x) ((x) << S_CPKTOUT)
+#define F_CPKTOUT    V_CPKTOUT(1U)
+
+#define S_CMDBRSPSRDY    8
+#define V_CMDBRSPSRDY(x) ((x) << S_CMDBRSPSRDY)
+#define F_CMDBRSPSRDY    V_CMDBRSPSRDY(1U)
+
+#define S_RXPSTRUCTSFULL    6
+#define M_RXPSTRUCTSFULL    0x3U
+#define V_RXPSTRUCTSFULL(x) ((x) << S_RXPSTRUCTSFULL)
+#define G_RXPSTRUCTSFULL(x) (((x) >> S_RXPSTRUCTSFULL) & M_RXPSTRUCTSFULL)
+
+#define S_RXPAGEPOOLFULL    4
+#define M_RXPAGEPOOLFULL    0x3U
+#define V_RXPAGEPOOLFULL(x) ((x) << S_RXPAGEPOOLFULL)
+#define G_RXPAGEPOOLFULL(x) (((x) >> S_RXPAGEPOOLFULL) & M_RXPAGEPOOLFULL)
+
+#define S_RCFREASONOUT    0
+#define M_RCFREASONOUT    0xfU
+#define V_RCFREASONOUT(x) ((x) << S_RCFREASONOUT)
+#define G_RCFREASONOUT(x) (((x) >> S_RCFREASONOUT) & M_RCFREASONOUT)
+
+#define A_TP_DBG_CORE_PCMD 0x69
+
+#define S_CPCMDEOPCNT    30
+#define M_CPCMDEOPCNT    0x3U
+#define V_CPCMDEOPCNT(x) ((x) << S_CPCMDEOPCNT)
+#define G_CPCMDEOPCNT(x) (((x) >> S_CPCMDEOPCNT) & M_CPCMDEOPCNT)
+
+#define S_CPCMDLENSAVE    16
+#define M_CPCMDLENSAVE    0x3fffU
+#define V_CPCMDLENSAVE(x) ((x) << S_CPCMDLENSAVE)
+#define G_CPCMDLENSAVE(x) (((x) >> S_CPCMDLENSAVE) & M_CPCMDLENSAVE)
+
+#define S_EPCMDEOPCNT    14
+#define M_EPCMDEOPCNT    0x3U
+#define V_EPCMDEOPCNT(x) ((x) << S_EPCMDEOPCNT)
+#define G_EPCMDEOPCNT(x) (((x) >> S_EPCMDEOPCNT) & M_EPCMDEOPCNT)
+
+#define S_EPCMDLENSAVE    0
+#define M_EPCMDLENSAVE    0x3fffU
+#define V_EPCMDLENSAVE(x) ((x) << S_EPCMDLENSAVE)
+#define G_EPCMDLENSAVE(x) (((x) >> S_EPCMDLENSAVE) & M_EPCMDLENSAVE)
+
+#define A_TP_DBG_SCHED_TX 0x6a
+
+#define S_TXCHNXOFF    28
+#define M_TXCHNXOFF    0xfU
+#define V_TXCHNXOFF(x) ((x) << S_TXCHNXOFF)
+#define G_TXCHNXOFF(x) (((x) >> S_TXCHNXOFF) & M_TXCHNXOFF)
+
+#define S_TXFIFOCNG    24
+#define M_TXFIFOCNG    0xfU
+#define V_TXFIFOCNG(x) ((x) << S_TXFIFOCNG)
+#define G_TXFIFOCNG(x) (((x) >> S_TXFIFOCNG) & M_TXFIFOCNG)
+
+#define S_TXPCMDCNG    20
+#define M_TXPCMDCNG    0xfU
+#define V_TXPCMDCNG(x) ((x) << S_TXPCMDCNG)
+#define G_TXPCMDCNG(x) (((x) >> S_TXPCMDCNG) & M_TXPCMDCNG)
+
+#define S_TXLPBKCNG    16
+#define M_TXLPBKCNG    0xfU
+#define V_TXLPBKCNG(x) ((x) << S_TXLPBKCNG)
+#define G_TXLPBKCNG(x) (((x) >> S_TXLPBKCNG) & M_TXLPBKCNG)
+
+#define S_TXHDRCNG    8
+#define M_TXHDRCNG    0xffU
+#define V_TXHDRCNG(x) ((x) << S_TXHDRCNG)
+#define G_TXHDRCNG(x) (((x) >> S_TXHDRCNG) & M_TXHDRCNG)
+
+#define S_TXMODXOFF    0
+#define M_TXMODXOFF    0xffU
+#define V_TXMODXOFF(x) ((x) << S_TXMODXOFF)
+#define G_TXMODXOFF(x) (((x) >> S_TXMODXOFF) & M_TXMODXOFF)
+
+#define A_TP_DBG_SCHED_RX 0x6b
+
+#define S_RXCHNXOFF    28
+#define M_RXCHNXOFF    0xfU
+#define V_RXCHNXOFF(x) ((x) << S_RXCHNXOFF)
+#define G_RXCHNXOFF(x) (((x) >> S_RXCHNXOFF) & M_RXCHNXOFF)
+
+#define S_RXSGECNG    24
+#define M_RXSGECNG    0xfU
+#define V_RXSGECNG(x) ((x) << S_RXSGECNG)
+#define G_RXSGECNG(x) (((x) >> S_RXSGECNG) & M_RXSGECNG)
+
+#define S_RXFIFOCNG    22
+#define M_RXFIFOCNG    0x3U
+#define V_RXFIFOCNG(x) ((x) << S_RXFIFOCNG)
+#define G_RXFIFOCNG(x) (((x) >> S_RXFIFOCNG) & M_RXFIFOCNG)
+
+#define S_RXPCMDCNG    20
+#define M_RXPCMDCNG    0x3U
+#define V_RXPCMDCNG(x) ((x) << S_RXPCMDCNG)
+#define G_RXPCMDCNG(x) (((x) >> S_RXPCMDCNG) & M_RXPCMDCNG)
+
+#define S_RXLPBKCNG    16
+#define M_RXLPBKCNG    0xfU
+#define V_RXLPBKCNG(x) ((x) << S_RXLPBKCNG)
+#define G_RXLPBKCNG(x) (((x) >> S_RXLPBKCNG) & M_RXLPBKCNG)
+
+#define S_RXHDRCNG    8
+#define M_RXHDRCNG    0xfU
+#define V_RXHDRCNG(x) ((x) << S_RXHDRCNG)
+#define G_RXHDRCNG(x) (((x) >> S_RXHDRCNG) & M_RXHDRCNG)
+
+#define S_RXMODXOFF    0
+#define M_RXMODXOFF    0x3U
+#define V_RXMODXOFF(x) ((x) << S_RXMODXOFF)
+#define G_RXMODXOFF(x) (((x) >> S_RXMODXOFF) & M_RXMODXOFF)
+
+#define A_TP_DBG_ERROR_CNT 0x6c
+#define A_TP_MIB_DEBUG 0x6f
+
+#define S_SRC3    31
+#define V_SRC3(x) ((x) << S_SRC3)
+#define F_SRC3    V_SRC3(1U)
+
+#define S_LINENUM3    24
+#define M_LINENUM3    0x7fU
+#define V_LINENUM3(x) ((x) << S_LINENUM3)
+#define G_LINENUM3(x) (((x) >> S_LINENUM3) & M_LINENUM3)
+
+#define S_SRC2    23
+#define V_SRC2(x) ((x) << S_SRC2)
+#define F_SRC2    V_SRC2(1U)
+
+#define S_LINENUM2    16
+#define M_LINENUM2    0x7fU
+#define V_LINENUM2(x) ((x) << S_LINENUM2)
+#define G_LINENUM2(x) (((x) >> S_LINENUM2) & M_LINENUM2)
+
+#define S_SRC1    15
+#define V_SRC1(x) ((x) << S_SRC1)
+#define F_SRC1    V_SRC1(1U)
+
+#define S_LINENUM1    8
+#define M_LINENUM1    0x7fU
+#define V_LINENUM1(x) ((x) << S_LINENUM1)
+#define G_LINENUM1(x) (((x) >> S_LINENUM1) & M_LINENUM1)
+
+#define S_SRC0    7
+#define V_SRC0(x) ((x) << S_SRC0)
+#define F_SRC0    V_SRC0(1U)
+
+#define S_LINENUM0    0
+#define M_LINENUM0    0x7fU
+#define V_LINENUM0(x) ((x) << S_LINENUM0)
+#define G_LINENUM0(x) (((x) >> S_LINENUM0) & M_LINENUM0)
+
+#define A_TP_T5_TX_DROP_CNT_CH0 0x120
+#define A_TP_T5_TX_DROP_CNT_CH1 0x121
+#define A_TP_TX_DROP_CNT_CH2 0x122
+#define A_TP_TX_DROP_CNT_CH3 0x123
+#define A_TP_TX_DROP_CFG_CH0 0x12b
+
+#define S_TIMERENABLED    31
+#define V_TIMERENABLED(x) ((x) << S_TIMERENABLED)
+#define F_TIMERENABLED    V_TIMERENABLED(1U)
+
+#define S_TIMERERRORENABLE    30
+#define V_TIMERERRORENABLE(x) ((x) << S_TIMERERRORENABLE)
+#define F_TIMERERRORENABLE    V_TIMERERRORENABLE(1U)
+
+#define S_TIMERTHRESHOLD    4
+#define M_TIMERTHRESHOLD    0x3ffffffU
+#define V_TIMERTHRESHOLD(x) ((x) << S_TIMERTHRESHOLD)
+#define G_TIMERTHRESHOLD(x) (((x) >> S_TIMERTHRESHOLD) & M_TIMERTHRESHOLD)
+
+#define S_PACKETDROPS    0
+#define M_PACKETDROPS    0xfU
+#define V_PACKETDROPS(x) ((x) << S_PACKETDROPS)
+#define G_PACKETDROPS(x) (((x) >> S_PACKETDROPS) & M_PACKETDROPS)
+
+#define A_TP_TX_DROP_CFG_CH1 0x12c
+#define A_TP_TX_DROP_CNT_CH0 0x12d
+
+#define S_TXDROPCNTCH0SENT    16
+#define M_TXDROPCNTCH0SENT    0xffffU
+#define V_TXDROPCNTCH0SENT(x) ((x) << S_TXDROPCNTCH0SENT)
+#define G_TXDROPCNTCH0SENT(x) (((x) >> S_TXDROPCNTCH0SENT) & M_TXDROPCNTCH0SENT)
+
+#define S_TXDROPCNTCH0RCVD    0
+#define M_TXDROPCNTCH0RCVD    0xffffU
+#define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD)
+#define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & M_TXDROPCNTCH0RCVD)
+
+#define A_TP_TX_DROP_CNT_CH1 0x12e
+
+#define S_TXDROPCNTCH1SENT    16
+#define M_TXDROPCNTCH1SENT    0xffffU
+#define V_TXDROPCNTCH1SENT(x) ((x) << S_TXDROPCNTCH1SENT)
+#define G_TXDROPCNTCH1SENT(x) (((x) >> S_TXDROPCNTCH1SENT) & M_TXDROPCNTCH1SENT)
+
+#define S_TXDROPCNTCH1RCVD    0
+#define M_TXDROPCNTCH1RCVD    0xffffU
+#define V_TXDROPCNTCH1RCVD(x) ((x) << S_TXDROPCNTCH1RCVD)
+#define G_TXDROPCNTCH1RCVD(x) (((x) >> S_TXDROPCNTCH1RCVD) & M_TXDROPCNTCH1RCVD)
+
+#define A_TP_TX_DROP_MODE 0x12f
+
+#define S_TXDROPMODECH3    3
+#define V_TXDROPMODECH3(x) ((x) << S_TXDROPMODECH3)
+#define F_TXDROPMODECH3    V_TXDROPMODECH3(1U)
+
+#define S_TXDROPMODECH2    2
+#define V_TXDROPMODECH2(x) ((x) << S_TXDROPMODECH2)
+#define F_TXDROPMODECH2    V_TXDROPMODECH2(1U)
+
+#define S_TXDROPMODECH1    1
+#define V_TXDROPMODECH1(x) ((x) << S_TXDROPMODECH1)
+#define F_TXDROPMODECH1    V_TXDROPMODECH1(1U)
+
+#define S_TXDROPMODECH0    0
+#define V_TXDROPMODECH0(x) ((x) << S_TXDROPMODECH0)
+#define F_TXDROPMODECH0    V_TXDROPMODECH0(1U)
+
+#define A_TP_DBG_ESIDE_PKT0 0x130
+
+#define S_ETXSOPCNT    28
+#define M_ETXSOPCNT    0xfU
+#define V_ETXSOPCNT(x) ((x) << S_ETXSOPCNT)
+#define G_ETXSOPCNT(x) (((x) >> S_ETXSOPCNT) & M_ETXSOPCNT)
+
+#define S_ETXEOPCNT    24
+#define M_ETXEOPCNT    0xfU
+#define V_ETXEOPCNT(x) ((x) << S_ETXEOPCNT)
+#define G_ETXEOPCNT(x) (((x) >> S_ETXEOPCNT) & M_ETXEOPCNT)
+
+#define S_ETXPLDSOPCNT    20
+#define M_ETXPLDSOPCNT    0xfU
+#define V_ETXPLDSOPCNT(x) ((x) << S_ETXPLDSOPCNT)
+#define G_ETXPLDSOPCNT(x) (((x) >> S_ETXPLDSOPCNT) & M_ETXPLDSOPCNT)
+
+#define S_ETXPLDEOPCNT    16
+#define M_ETXPLDEOPCNT    0xfU
+#define V_ETXPLDEOPCNT(x) ((x) << S_ETXPLDEOPCNT)
+#define G_ETXPLDEOPCNT(x) (((x) >> S_ETXPLDEOPCNT) & M_ETXPLDEOPCNT)
+
+#define S_ERXSOPCNT    12
+#define M_ERXSOPCNT    0xfU
+#define V_ERXSOPCNT(x) ((x) << S_ERXSOPCNT)
+#define G_ERXSOPCNT(x) (((x) >> S_ERXSOPCNT) & M_ERXSOPCNT)
+
+#define S_ERXEOPCNT    8
+#define M_ERXEOPCNT    0xfU
+#define V_ERXEOPCNT(x) ((x) << S_ERXEOPCNT)
+#define G_ERXEOPCNT(x) (((x) >> S_ERXEOPCNT) & M_ERXEOPCNT)
+
+#define S_ERXPLDSOPCNT    4
+#define M_ERXPLDSOPCNT    0xfU
+#define V_ERXPLDSOPCNT(x) ((x) << S_ERXPLDSOPCNT)
+#define G_ERXPLDSOPCNT(x) (((x) >> S_ERXPLDSOPCNT) & M_ERXPLDSOPCNT)
+
+#define S_ERXPLDEOPCNT    0
+#define M_ERXPLDEOPCNT    0xfU
+#define V_ERXPLDEOPCNT(x) ((x) << S_ERXPLDEOPCNT)
+#define G_ERXPLDEOPCNT(x) (((x) >> S_ERXPLDEOPCNT) & M_ERXPLDEOPCNT)
+
+#define A_TP_DBG_ESIDE_PKT1 0x131
+#define A_TP_DBG_ESIDE_PKT2 0x132
+#define A_TP_DBG_ESIDE_PKT3 0x133
+#define A_TP_DBG_ESIDE_FIFO0 0x134
+
+#define S_PLDRXCSUMVALID1    31
+#define V_PLDRXCSUMVALID1(x) ((x) << S_PLDRXCSUMVALID1)
+#define F_PLDRXCSUMVALID1    V_PLDRXCSUMVALID1(1U)
+
+#define S_PLDRXZEROPSRDY1    30
+#define V_PLDRXZEROPSRDY1(x) ((x) << S_PLDRXZEROPSRDY1)
+#define F_PLDRXZEROPSRDY1    V_PLDRXZEROPSRDY1(1U)
+
+#define S_PLDRXVALID1    29
+#define V_PLDRXVALID1(x) ((x) << S_PLDRXVALID1)
+#define F_PLDRXVALID1    V_PLDRXVALID1(1U)
+
+#define S_TCPRXVALID1    28
+#define V_TCPRXVALID1(x) ((x) << S_TCPRXVALID1)
+#define F_TCPRXVALID1    V_TCPRXVALID1(1U)
+
+#define S_IPRXVALID1    27
+#define V_IPRXVALID1(x) ((x) << S_IPRXVALID1)
+#define F_IPRXVALID1    V_IPRXVALID1(1U)
+
+#define S_ETHRXVALID1    26
+#define V_ETHRXVALID1(x) ((x) << S_ETHRXVALID1)
+#define F_ETHRXVALID1    V_ETHRXVALID1(1U)
+
+#define S_CPLRXVALID1    25
+#define V_CPLRXVALID1(x) ((x) << S_CPLRXVALID1)
+#define F_CPLRXVALID1    V_CPLRXVALID1(1U)
+
+#define S_FSTATIC1    24
+#define V_FSTATIC1(x) ((x) << S_FSTATIC1)
+#define F_FSTATIC1    V_FSTATIC1(1U)
+
+#define S_ERRORSRDY1    23
+#define V_ERRORSRDY1(x) ((x) << S_ERRORSRDY1)
+#define F_ERRORSRDY1    V_ERRORSRDY1(1U)
+
+#define S_PLDTXSRDY1    22
+#define V_PLDTXSRDY1(x) ((x) << S_PLDTXSRDY1)
+#define F_PLDTXSRDY1    V_PLDTXSRDY1(1U)
+
+#define S_DBVLD1    21
+#define V_DBVLD1(x) ((x) << S_DBVLD1)
+#define F_DBVLD1    V_DBVLD1(1U)
+
+#define S_PLDTXVALID1    20
+#define V_PLDTXVALID1(x) ((x) << S_PLDTXVALID1)
+#define F_PLDTXVALID1    V_PLDTXVALID1(1U)
+
+#define S_ETXVALID1    19
+#define V_ETXVALID1(x) ((x) << S_ETXVALID1)
+#define F_ETXVALID1    V_ETXVALID1(1U)
+
+#define S_ETXFULL1    18
+#define V_ETXFULL1(x) ((x) << S_ETXFULL1)
+#define F_ETXFULL1    V_ETXFULL1(1U)
+
+#define S_ERXVALID1    17
+#define V_ERXVALID1(x) ((x) << S_ERXVALID1)
+#define F_ERXVALID1    V_ERXVALID1(1U)
+
+#define S_ERXFULL1    16
+#define V_ERXFULL1(x) ((x) << S_ERXFULL1)
+#define F_ERXFULL1    V_ERXFULL1(1U)
+
+#define S_PLDRXCSUMVALID0    15
+#define V_PLDRXCSUMVALID0(x) ((x) << S_PLDRXCSUMVALID0)
+#define F_PLDRXCSUMVALID0    V_PLDRXCSUMVALID0(1U)
+
+#define S_PLDRXZEROPSRDY0    14
+#define V_PLDRXZEROPSRDY0(x) ((x) << S_PLDRXZEROPSRDY0)
+#define F_PLDRXZEROPSRDY0    V_PLDRXZEROPSRDY0(1U)
+
+#define S_PLDRXVALID0    13
+#define V_PLDRXVALID0(x) ((x) << S_PLDRXVALID0)
+#define F_PLDRXVALID0    V_PLDRXVALID0(1U)
+
+#define S_TCPRXVALID0    12
+#define V_TCPRXVALID0(x) ((x) << S_TCPRXVALID0)
+#define F_TCPRXVALID0    V_TCPRXVALID0(1U)
+
+#define S_IPRXVALID0    11
+#define V_IPRXVALID0(x) ((x) << S_IPRXVALID0)
+#define F_IPRXVALID0    V_IPRXVALID0(1U)
+
+#define S_ETHRXVALID0    10
+#define V_ETHRXVALID0(x) ((x) << S_ETHRXVALID0)
+#define F_ETHRXVALID0    V_ETHRXVALID0(1U)
+
+#define S_CPLRXVALID0    9
+#define V_CPLRXVALID0(x) ((x) << S_CPLRXVALID0)
+#define F_CPLRXVALID0    V_CPLRXVALID0(1U)
+
+#define S_FSTATIC0    8
+#define V_FSTATIC0(x) ((x) << S_FSTATIC0)
+#define F_FSTATIC0    V_FSTATIC0(1U)
+
+#define S_ERRORSRDY0    7
+#define V_ERRORSRDY0(x) ((x) << S_ERRORSRDY0)
+#define F_ERRORSRDY0    V_ERRORSRDY0(1U)
+
+#define S_PLDTXSRDY0    6
+#define V_PLDTXSRDY0(x) ((x) << S_PLDTXSRDY0)
+#define F_PLDTXSRDY0    V_PLDTXSRDY0(1U)
+
+#define S_DBVLD0    5
+#define V_DBVLD0(x) ((x) << S_DBVLD0)
+#define F_DBVLD0    V_DBVLD0(1U)
+
+#define S_PLDTXVALID0    4
+#define V_PLDTXVALID0(x) ((x) << S_PLDTXVALID0)
+#define F_PLDTXVALID0    V_PLDTXVALID0(1U)
+
+#define S_ETXVALID0    3
+#define V_ETXVALID0(x) ((x) << S_ETXVALID0)
+#define F_ETXVALID0    V_ETXVALID0(1U)
+
+#define S_ETXFULL0    2
+#define V_ETXFULL0(x) ((x) << S_ETXFULL0)
+#define F_ETXFULL0    V_ETXFULL0(1U)
+
+#define S_ERXVALID0    1
+#define V_ERXVALID0(x) ((x) << S_ERXVALID0)
+#define F_ERXVALID0    V_ERXVALID0(1U)
+
+#define S_ERXFULL0    0
+#define V_ERXFULL0(x) ((x) << S_ERXFULL0)
+#define F_ERXFULL0    V_ERXFULL0(1U)
+
+#define A_TP_DBG_ESIDE_FIFO1 0x135
+
+#define S_PLDRXCSUMVALID3    31
+#define V_PLDRXCSUMVALID3(x) ((x) << S_PLDRXCSUMVALID3)
+#define F_PLDRXCSUMVALID3    V_PLDRXCSUMVALID3(1U)
+
+#define S_PLDRXZEROPSRDY3    30
+#define V_PLDRXZEROPSRDY3(x) ((x) << S_PLDRXZEROPSRDY3)
+#define F_PLDRXZEROPSRDY3    V_PLDRXZEROPSRDY3(1U)
+
+#define S_PLDRXVALID3    29
+#define V_PLDRXVALID3(x) ((x) << S_PLDRXVALID3)
+#define F_PLDRXVALID3    V_PLDRXVALID3(1U)
+
+#define S_TCPRXVALID3    28
+#define V_TCPRXVALID3(x) ((x) << S_TCPRXVALID3)
+#define F_TCPRXVALID3    V_TCPRXVALID3(1U)
+
+#define S_IPRXVALID3    27
+#define V_IPRXVALID3(x) ((x) << S_IPRXVALID3)
+#define F_IPRXVALID3    V_IPRXVALID3(1U)
+
+#define S_ETHRXVALID3    26
+#define V_ETHRXVALID3(x) ((x) << S_ETHRXVALID3)
+#define F_ETHRXVALID3    V_ETHRXVALID3(1U)
+
+#define S_CPLRXVALID3    25
+#define V_CPLRXVALID3(x) ((x) << S_CPLRXVALID3)
+#define F_CPLRXVALID3    V_CPLRXVALID3(1U)
+
+#define S_FSTATIC3    24
+#define V_FSTATIC3(x) ((x) << S_FSTATIC3)
+#define F_FSTATIC3    V_FSTATIC3(1U)
+
+#define S_ERRORSRDY3    23
+#define V_ERRORSRDY3(x) ((x) << S_ERRORSRDY3)
+#define F_ERRORSRDY3    V_ERRORSRDY3(1U)
+
+#define S_PLDTXSRDY3    22
+#define V_PLDTXSRDY3(x) ((x) << S_PLDTXSRDY3)
+#define F_PLDTXSRDY3    V_PLDTXSRDY3(1U)
+
+#define S_DBVLD3    21
+#define V_DBVLD3(x) ((x) << S_DBVLD3)
+#define F_DBVLD3    V_DBVLD3(1U)
+
+#define S_PLDTXVALID3    20
+#define V_PLDTXVALID3(x) ((x) << S_PLDTXVALID3)
+#define F_PLDTXVALID3    V_PLDTXVALID3(1U)
+
+#define S_ETXVALID3    19
+#define V_ETXVALID3(x) ((x) << S_ETXVALID3)
+#define F_ETXVALID3    V_ETXVALID3(1U)
+
+#define S_ETXFULL3    18
+#define V_ETXFULL3(x) ((x) << S_ETXFULL3)
+#define F_ETXFULL3    V_ETXFULL3(1U)
+
+#define S_ERXVALID3    17
+#define V_ERXVALID3(x) ((x) << S_ERXVALID3)
+#define F_ERXVALID3    V_ERXVALID3(1U)
+
+#define S_ERXFULL3    16
+#define V_ERXFULL3(x) ((x) << S_ERXFULL3)
+#define F_ERXFULL3    V_ERXFULL3(1U)
+
+#define S_PLDRXCSUMVALID2    15
+#define V_PLDRXCSUMVALID2(x) ((x) << S_PLDRXCSUMVALID2)
+#define F_PLDRXCSUMVALID2    V_PLDRXCSUMVALID2(1U)
+
+#define S_PLDRXZEROPSRDY2    14
+#define V_PLDRXZEROPSRDY2(x) ((x) << S_PLDRXZEROPSRDY2)
+#define F_PLDRXZEROPSRDY2    V_PLDRXZEROPSRDY2(1U)
+
+#define S_PLDRXVALID2    13
+#define V_PLDRXVALID2(x) ((x) << S_PLDRXVALID2)
+#define F_PLDRXVALID2    V_PLDRXVALID2(1U)
+
+#define S_TCPRXVALID2    12
+#define V_TCPRXVALID2(x) ((x) << S_TCPRXVALID2)
+#define F_TCPRXVALID2    V_TCPRXVALID2(1U)
+
+#define S_IPRXVALID2    11
+#define V_IPRXVALID2(x) ((x) << S_IPRXVALID2)
+#define F_IPRXVALID2    V_IPRXVALID2(1U)
+
+#define S_ETHRXVALID2    10
+#define V_ETHRXVALID2(x) ((x) << S_ETHRXVALID2)
+#define F_ETHRXVALID2    V_ETHRXVALID2(1U)
+
+#define S_CPLRXVALID2    9
+#define V_CPLRXVALID2(x) ((x) << S_CPLRXVALID2)
+#define F_CPLRXVALID2    V_CPLRXVALID2(1U)
+
+#define S_FSTATIC2    8
+#define V_FSTATIC2(x) ((x) << S_FSTATIC2)
+#define F_FSTATIC2    V_FSTATIC2(1U)
+
+#define S_ERRORSRDY2    7
+#define V_ERRORSRDY2(x) ((x) << S_ERRORSRDY2)
+#define F_ERRORSRDY2    V_ERRORSRDY2(1U)
+
+#define S_PLDTXSRDY2    6
+#define V_PLDTXSRDY2(x) ((x) << S_PLDTXSRDY2)
+#define F_PLDTXSRDY2    V_PLDTXSRDY2(1U)
+
+#define S_DBVLD2    5
+#define V_DBVLD2(x) ((x) << S_DBVLD2)
+#define F_DBVLD2    V_DBVLD2(1U)
+
+#define S_PLDTXVALID2    4
+#define V_PLDTXVALID2(x) ((x) << S_PLDTXVALID2)
+#define F_PLDTXVALID2    V_PLDTXVALID2(1U)
+
+#define S_ETXVALID2    3
+#define V_ETXVALID2(x) ((x) << S_ETXVALID2)
+#define F_ETXVALID2    V_ETXVALID2(1U)
+
+#define S_ETXFULL2    2
+#define V_ETXFULL2(x) ((x) << S_ETXFULL2)
+#define F_ETXFULL2    V_ETXFULL2(1U)
+
+#define S_ERXVALID2    1
+#define V_ERXVALID2(x) ((x) << S_ERXVALID2)
+#define F_ERXVALID2    V_ERXVALID2(1U)
+
+#define S_ERXFULL2    0
+#define V_ERXFULL2(x) ((x) << S_ERXFULL2)
+#define F_ERXFULL2    V_ERXFULL2(1U)
+
+#define A_TP_DBG_ESIDE_DISP0 0x136
+
+#define S_RESRDY    31
+#define V_RESRDY(x) ((x) << S_RESRDY)
+#define F_RESRDY    V_RESRDY(1U)
+
+#define S_STATE    28
+#define M_STATE    0x7U
+#define V_STATE(x) ((x) << S_STATE)
+#define G_STATE(x) (((x) >> S_STATE) & M_STATE)
+
+#define S_FIFOCPL5RXVALID    27
+#define V_FIFOCPL5RXVALID(x) ((x) << S_FIFOCPL5RXVALID)
+#define F_FIFOCPL5RXVALID    V_FIFOCPL5RXVALID(1U)
+
+#define S_FIFOETHRXVALID    26
+#define V_FIFOETHRXVALID(x) ((x) << S_FIFOETHRXVALID)
+#define F_FIFOETHRXVALID    V_FIFOETHRXVALID(1U)
+
+#define S_FIFOETHRXSOCP    25
+#define V_FIFOETHRXSOCP(x) ((x) << S_FIFOETHRXSOCP)
+#define F_FIFOETHRXSOCP    V_FIFOETHRXSOCP(1U)
+
+#define S_FIFOPLDRXZEROP    24
+#define V_FIFOPLDRXZEROP(x) ((x) << S_FIFOPLDRXZEROP)
+#define F_FIFOPLDRXZEROP    V_FIFOPLDRXZEROP(1U)
+
+#define S_PLDRXVALID    23
+#define V_PLDRXVALID(x) ((x) << S_PLDRXVALID)
+#define F_PLDRXVALID    V_PLDRXVALID(1U)
+
+#define S_FIFOPLDRXZEROP_SRDY    22
+#define V_FIFOPLDRXZEROP_SRDY(x) ((x) << S_FIFOPLDRXZEROP_SRDY)
+#define F_FIFOPLDRXZEROP_SRDY    V_FIFOPLDRXZEROP_SRDY(1U)
+
+#define S_FIFOIPRXVALID    21
+#define V_FIFOIPRXVALID(x) ((x) << S_FIFOIPRXVALID)
+#define F_FIFOIPRXVALID    V_FIFOIPRXVALID(1U)
+
+#define S_FIFOTCPRXVALID    20
+#define V_FIFOTCPRXVALID(x) ((x) << S_FIFOTCPRXVALID)
+#define F_FIFOTCPRXVALID    V_FIFOTCPRXVALID(1U)
+
+#define S_PLDRXCSUMVALID    19
+#define V_PLDRXCSUMVALID(x) ((x) << S_PLDRXCSUMVALID)
+#define F_PLDRXCSUMVALID    V_PLDRXCSUMVALID(1U)
+
+#define S_FIFOIPCSUMSRDY    18
+#define V_FIFOIPCSUMSRDY(x) ((x) << S_FIFOIPCSUMSRDY)
+#define F_FIFOIPCSUMSRDY    V_FIFOIPCSUMSRDY(1U)
+
+#define S_FIFOIPPSEUDOCSUMSRDY    17
+#define V_FIFOIPPSEUDOCSUMSRDY(x) ((x) << S_FIFOIPPSEUDOCSUMSRDY)
+#define F_FIFOIPPSEUDOCSUMSRDY    V_FIFOIPPSEUDOCSUMSRDY(1U)
+
+#define S_FIFOTCPCSUMSRDY    16
+#define V_FIFOTCPCSUMSRDY(x) ((x) << S_FIFOTCPCSUMSRDY)
+#define F_FIFOTCPCSUMSRDY    V_FIFOTCPCSUMSRDY(1U)
+
+#define S_ESTATIC4    12
+#define M_ESTATIC4    0xfU
+#define V_ESTATIC4(x) ((x) << S_ESTATIC4)
+#define G_ESTATIC4(x) (((x) >> S_ESTATIC4) & M_ESTATIC4)
+
+#define S_FIFOCPLSOCPCNT    10
+#define M_FIFOCPLSOCPCNT    0x3U
+#define V_FIFOCPLSOCPCNT(x) ((x) << S_FIFOCPLSOCPCNT)
+#define G_FIFOCPLSOCPCNT(x) (((x) >> S_FIFOCPLSOCPCNT) & M_FIFOCPLSOCPCNT)
+
+#define S_FIFOETHSOCPCNT    8
+#define M_FIFOETHSOCPCNT    0x3U
+#define V_FIFOETHSOCPCNT(x) ((x) << S_FIFOETHSOCPCNT)
+#define G_FIFOETHSOCPCNT(x) (((x) >> S_FIFOETHSOCPCNT) & M_FIFOETHSOCPCNT)
+
+#define S_FIFOIPSOCPCNT    6
+#define M_FIFOIPSOCPCNT    0x3U
+#define V_FIFOIPSOCPCNT(x) ((x) << S_FIFOIPSOCPCNT)
+#define G_FIFOIPSOCPCNT(x) (((x) >> S_FIFOIPSOCPCNT) & M_FIFOIPSOCPCNT)
+
+#define S_FIFOTCPSOCPCNT    4
+#define M_FIFOTCPSOCPCNT    0x3U
+#define V_FIFOTCPSOCPCNT(x) ((x) << S_FIFOTCPSOCPCNT)
+#define G_FIFOTCPSOCPCNT(x) (((x) >> S_FIFOTCPSOCPCNT) & M_FIFOTCPSOCPCNT)
+
+#define S_PLD_RXZEROP_CNT    2
+#define M_PLD_RXZEROP_CNT    0x3U
+#define V_PLD_RXZEROP_CNT(x) ((x) << S_PLD_RXZEROP_CNT)
+#define G_PLD_RXZEROP_CNT(x) (((x) >> S_PLD_RXZEROP_CNT) & M_PLD_RXZEROP_CNT)
+
+#define S_ESTATIC6    1
+#define V_ESTATIC6(x) ((x) << S_ESTATIC6)
+#define F_ESTATIC6    V_ESTATIC6(1U)
+
+#define S_TXFULL    0
+#define V_TXFULL(x) ((x) << S_TXFULL)
+#define F_TXFULL    V_TXFULL(1U)
+
+#define A_TP_DBG_ESIDE_DISP1 0x137
+#define A_TP_MAC_MATCH_MAP0 0x138
+
+#define S_MAPVALUEWR    16
+#define M_MAPVALUEWR    0xffU
+#define V_MAPVALUEWR(x) ((x) << S_MAPVALUEWR)
+#define G_MAPVALUEWR(x) (((x) >> S_MAPVALUEWR) & M_MAPVALUEWR)
+
+#define S_MAPINDEX    2
+#define M_MAPINDEX    0x1ffU
+#define V_MAPINDEX(x) ((x) << S_MAPINDEX)
+#define G_MAPINDEX(x) (((x) >> S_MAPINDEX) & M_MAPINDEX)
+
+#define S_MAPREAD    1
+#define V_MAPREAD(x) ((x) << S_MAPREAD)
+#define F_MAPREAD    V_MAPREAD(1U)
+
+#define S_MAPWRITE    0
+#define V_MAPWRITE(x) ((x) << S_MAPWRITE)
+#define F_MAPWRITE    V_MAPWRITE(1U)
+
+#define A_TP_MAC_MATCH_MAP1 0x139
+
+#define S_MAPVALUERD    0
+#define M_MAPVALUERD    0x1ffU
+#define V_MAPVALUERD(x) ((x) << S_MAPVALUERD)
+#define G_MAPVALUERD(x) (((x) >> S_MAPVALUERD) & M_MAPVALUERD)
+
+#define A_TP_DBG_ESIDE_DISP2 0x13a
+#define A_TP_DBG_ESIDE_DISP3 0x13b
+#define A_TP_DBG_ESIDE_HDR0 0x13c
+
+#define S_TCPSOPCNT    28
+#define M_TCPSOPCNT    0xfU
+#define V_TCPSOPCNT(x) ((x) << S_TCPSOPCNT)
+#define G_TCPSOPCNT(x) (((x) >> S_TCPSOPCNT) & M_TCPSOPCNT)
+
+#define S_TCPEOPCNT    24
+#define M_TCPEOPCNT    0xfU
+#define V_TCPEOPCNT(x) ((x) << S_TCPEOPCNT)
+#define G_TCPEOPCNT(x) (((x) >> S_TCPEOPCNT) & M_TCPEOPCNT)
+
+#define S_IPSOPCNT    20
+#define M_IPSOPCNT    0xfU
+#define V_IPSOPCNT(x) ((x) << S_IPSOPCNT)
+#define G_IPSOPCNT(x) (((x) >> S_IPSOPCNT) & M_IPSOPCNT)
+
+#define S_IPEOPCNT    16
+#define M_IPEOPCNT    0xfU
+#define V_IPEOPCNT(x) ((x) << S_IPEOPCNT)
+#define G_IPEOPCNT(x) (((x) >> S_IPEOPCNT) & M_IPEOPCNT)
+
+#define S_ETHSOPCNT    12
+#define M_ETHSOPCNT    0xfU
+#define V_ETHSOPCNT(x) ((x) << S_ETHSOPCNT)
+#define G_ETHSOPCNT(x) (((x) >> S_ETHSOPCNT) & M_ETHSOPCNT)
+
+#define S_ETHEOPCNT    8
+#define M_ETHEOPCNT    0xfU
+#define V_ETHEOPCNT(x) ((x) << S_ETHEOPCNT)
+#define G_ETHEOPCNT(x) (((x) >> S_ETHEOPCNT) & M_ETHEOPCNT)
+
+#define S_CPLSOPCNT    4
+#define M_CPLSOPCNT    0xfU
+#define V_CPLSOPCNT(x) ((x) << S_CPLSOPCNT)
+#define G_CPLSOPCNT(x) (((x) >> S_CPLSOPCNT) & M_CPLSOPCNT)
+
+#define S_CPLEOPCNT    0
+#define M_CPLEOPCNT    0xfU
+#define V_CPLEOPCNT(x) ((x) << S_CPLEOPCNT)
+#define G_CPLEOPCNT(x) (((x) >> S_CPLEOPCNT) & M_CPLEOPCNT)
+
+#define A_TP_DBG_ESIDE_HDR1 0x13d
+#define A_TP_DBG_ESIDE_HDR2 0x13e
+#define A_TP_DBG_ESIDE_HDR3 0x13f
+#define A_TP_VLAN_PRI_MAP 0x140
+
+#define S_FRAGMENTATION    9
+#define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION)
+#define F_FRAGMENTATION    V_FRAGMENTATION(1U)
+
+#define S_MPSHITTYPE    8
+#define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE)
+#define F_MPSHITTYPE    V_MPSHITTYPE(1U)
+
+#define S_MACMATCH    7
+#define V_MACMATCH(x) ((x) << S_MACMATCH)
+#define F_MACMATCH    V_MACMATCH(1U)
+
+#define S_ETHERTYPE    6
+#define V_ETHERTYPE(x) ((x) << S_ETHERTYPE)
+#define F_ETHERTYPE    V_ETHERTYPE(1U)
+
+#define S_PROTOCOL    5
+#define V_PROTOCOL(x) ((x) << S_PROTOCOL)
+#define F_PROTOCOL    V_PROTOCOL(1U)
+
+#define S_TOS    4
+#define V_TOS(x) ((x) << S_TOS)
+#define F_TOS    V_TOS(1U)
+
+#define S_VLAN    3
+#define V_VLAN(x) ((x) << S_VLAN)
+#define F_VLAN    V_VLAN(1U)
+
+#define S_VNIC_ID    2
+#define V_VNIC_ID(x) ((x) << S_VNIC_ID)
+#define F_VNIC_ID    V_VNIC_ID(1U)
+
+#define S_PORT    1
+#define V_PORT(x) ((x) << S_PORT)
+#define F_PORT    V_PORT(1U)
+
+#define S_FCOE    0
+#define V_FCOE(x) ((x) << S_FCOE)
+#define F_FCOE    V_FCOE(1U)
+
+#define S_FILTERMODE    15
+#define V_FILTERMODE(x) ((x) << S_FILTERMODE)
+#define F_FILTERMODE    V_FILTERMODE(1U)
+
+#define S_FCOEMASK    14
+#define V_FCOEMASK(x) ((x) << S_FCOEMASK)
+#define F_FCOEMASK    V_FCOEMASK(1U)
+
+#define S_SRVRSRAM    13
+#define V_SRVRSRAM(x) ((x) << S_SRVRSRAM)
+#define F_SRVRSRAM    V_SRVRSRAM(1U)
+
+#define A_TP_INGRESS_CONFIG 0x141
+
+#define S_OPAQUE_TYPE    16
+#define M_OPAQUE_TYPE    0xffffU
+#define V_OPAQUE_TYPE(x) ((x) << S_OPAQUE_TYPE)
+#define G_OPAQUE_TYPE(x) (((x) >> S_OPAQUE_TYPE) & M_OPAQUE_TYPE)
+
+#define S_OPAQUE_RM    15
+#define V_OPAQUE_RM(x) ((x) << S_OPAQUE_RM)
+#define F_OPAQUE_RM    V_OPAQUE_RM(1U)
+
+#define S_OPAQUE_HDR_SIZE    14
+#define V_OPAQUE_HDR_SIZE(x) ((x) << S_OPAQUE_HDR_SIZE)
+#define F_OPAQUE_HDR_SIZE    V_OPAQUE_HDR_SIZE(1U)
+
+#define S_OPAQUE_RM_MAC_IN_MAC    13
+#define V_OPAQUE_RM_MAC_IN_MAC(x) ((x) << S_OPAQUE_RM_MAC_IN_MAC)
+#define F_OPAQUE_RM_MAC_IN_MAC    V_OPAQUE_RM_MAC_IN_MAC(1U)
+
+#define S_FCOE_TARGET    12
+#define V_FCOE_TARGET(x) ((x) << S_FCOE_TARGET)
+#define F_FCOE_TARGET    V_FCOE_TARGET(1U)
+
+#define S_VNIC    11
+#define V_VNIC(x) ((x) << S_VNIC)
+#define F_VNIC    V_VNIC(1U)
+
+#define S_CSUM_HAS_PSEUDO_HDR    10
+#define V_CSUM_HAS_PSEUDO_HDR(x) ((x) << S_CSUM_HAS_PSEUDO_HDR)
+#define F_CSUM_HAS_PSEUDO_HDR    V_CSUM_HAS_PSEUDO_HDR(1U)
+
+#define S_RM_OVLAN    9
+#define V_RM_OVLAN(x) ((x) << S_RM_OVLAN)
+#define F_RM_OVLAN    V_RM_OVLAN(1U)
+
+#define S_LOOKUPEVERYPKT    8
+#define V_LOOKUPEVERYPKT(x) ((x) << S_LOOKUPEVERYPKT)
+#define F_LOOKUPEVERYPKT    V_LOOKUPEVERYPKT(1U)
+
+#define S_IPV6_EXT_HDR_SKIP    0
+#define M_IPV6_EXT_HDR_SKIP    0xffU
+#define V_IPV6_EXT_HDR_SKIP(x) ((x) << S_IPV6_EXT_HDR_SKIP)
+#define G_IPV6_EXT_HDR_SKIP(x) (((x) >> S_IPV6_EXT_HDR_SKIP) & M_IPV6_EXT_HDR_SKIP)
+
+#define S_FRAG_LEN_MOD8_COMPAT    12
+#define V_FRAG_LEN_MOD8_COMPAT(x) ((x) << S_FRAG_LEN_MOD8_COMPAT)
+#define F_FRAG_LEN_MOD8_COMPAT    V_FRAG_LEN_MOD8_COMPAT(1U)
+
+#define A_TP_TX_DROP_CFG_CH2 0x142
+#define A_TP_TX_DROP_CFG_CH3 0x143
+#define A_TP_EGRESS_CONFIG 0x145
+
+#define S_REWRITEFORCETOSIZE    0
+#define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE)
+#define F_REWRITEFORCETOSIZE    V_REWRITEFORCETOSIZE(1U)
+
+#define A_TP_INGRESS_CONFIG2 0x145
+
+#define S_IPV6_UDP_CSUM_COMPAT    31
+#define V_IPV6_UDP_CSUM_COMPAT(x) ((x) << S_IPV6_UDP_CSUM_COMPAT)
+#define F_IPV6_UDP_CSUM_COMPAT    V_IPV6_UDP_CSUM_COMPAT(1U)
+
+#define S_VNTAGPLDENABLE    30
+#define V_VNTAGPLDENABLE(x) ((x) << S_VNTAGPLDENABLE)
+#define F_VNTAGPLDENABLE    V_VNTAGPLDENABLE(1U)
+
+#define S_TCP_PLD_FILTER_OFFSET    20
+#define M_TCP_PLD_FILTER_OFFSET    0x3ffU
+#define V_TCP_PLD_FILTER_OFFSET(x) ((x) << S_TCP_PLD_FILTER_OFFSET)
+#define G_TCP_PLD_FILTER_OFFSET(x) (((x) >> S_TCP_PLD_FILTER_OFFSET) & M_TCP_PLD_FILTER_OFFSET)
+
+#define S_UDP_PLD_FILTER_OFFSET    10
+#define M_UDP_PLD_FILTER_OFFSET    0x3ffU
+#define V_UDP_PLD_FILTER_OFFSET(x) ((x) << S_UDP_PLD_FILTER_OFFSET)
+#define G_UDP_PLD_FILTER_OFFSET(x) (((x) >> S_UDP_PLD_FILTER_OFFSET) & M_UDP_PLD_FILTER_OFFSET)
+
+#define S_TNL_PLD_FILTER_OFFSET    0
+#define M_TNL_PLD_FILTER_OFFSET    0x3ffU
+#define V_TNL_PLD_FILTER_OFFSET(x) ((x) << S_TNL_PLD_FILTER_OFFSET)
+#define G_TNL_PLD_FILTER_OFFSET(x) (((x) >> S_TNL_PLD_FILTER_OFFSET) & M_TNL_PLD_FILTER_OFFSET)
+
+#define A_TP_EHDR_CONFIG_LO 0x146
+
+#define S_CPLLIMIT    24
+#define M_CPLLIMIT    0xffU
+#define V_CPLLIMIT(x) ((x) << S_CPLLIMIT)
+#define G_CPLLIMIT(x) (((x) >> S_CPLLIMIT) & M_CPLLIMIT)
+
+#define S_ETHLIMIT    16
+#define M_ETHLIMIT    0xffU
+#define V_ETHLIMIT(x) ((x) << S_ETHLIMIT)
+#define G_ETHLIMIT(x) (((x) >> S_ETHLIMIT) & M_ETHLIMIT)
+
+#define S_IPLIMIT    8
+#define M_IPLIMIT    0xffU
+#define V_IPLIMIT(x) ((x) << S_IPLIMIT)
+#define G_IPLIMIT(x) (((x) >> S_IPLIMIT) & M_IPLIMIT)
+
+#define S_TCPLIMIT    0
+#define M_TCPLIMIT    0xffU
+#define V_TCPLIMIT(x) ((x) << S_TCPLIMIT)
+#define G_TCPLIMIT(x) (((x) >> S_TCPLIMIT) & M_TCPLIMIT)
+
+#define A_TP_EHDR_CONFIG_HI 0x147
+#define A_TP_DBG_ESIDE_INT 0x148
+
+#define S_ERXSOP2X    28
+#define M_ERXSOP2X    0xfU
+#define V_ERXSOP2X(x) ((x) << S_ERXSOP2X)
+#define G_ERXSOP2X(x) (((x) >> S_ERXSOP2X) & M_ERXSOP2X)
+
+#define S_ERXEOP2X    24
+#define M_ERXEOP2X    0xfU
+#define V_ERXEOP2X(x) ((x) << S_ERXEOP2X)
+#define G_ERXEOP2X(x) (((x) >> S_ERXEOP2X) & M_ERXEOP2X)
+
+#define S_ERXVALID2X    20
+#define M_ERXVALID2X    0xfU
+#define V_ERXVALID2X(x) ((x) << S_ERXVALID2X)
+#define G_ERXVALID2X(x) (((x) >> S_ERXVALID2X) & M_ERXVALID2X)
+
+#define S_ERXAFULL2X    16
+#define M_ERXAFULL2X    0xfU
+#define V_ERXAFULL2X(x) ((x) << S_ERXAFULL2X)
+#define G_ERXAFULL2X(x) (((x) >> S_ERXAFULL2X) & M_ERXAFULL2X)
+
+#define S_PLD2XTXVALID    12
+#define M_PLD2XTXVALID    0xfU
+#define V_PLD2XTXVALID(x) ((x) << S_PLD2XTXVALID)
+#define G_PLD2XTXVALID(x) (((x) >> S_PLD2XTXVALID) & M_PLD2XTXVALID)
+
+#define S_PLD2XTXAFULL    8
+#define M_PLD2XTXAFULL    0xfU
+#define V_PLD2XTXAFULL(x) ((x) << S_PLD2XTXAFULL)
+#define G_PLD2XTXAFULL(x) (((x) >> S_PLD2XTXAFULL) & M_PLD2XTXAFULL)
+
+#define S_ERRORSRDY    7
+#define V_ERRORSRDY(x) ((x) << S_ERRORSRDY)
+#define F_ERRORSRDY    V_ERRORSRDY(1U)
+
+#define S_ERRORDRDY    6
+#define V_ERRORDRDY(x) ((x) << S_ERRORDRDY)
+#define F_ERRORDRDY    V_ERRORDRDY(1U)
+
+#define S_TCPOPSRDY    5
+#define V_TCPOPSRDY(x) ((x) << S_TCPOPSRDY)
+#define F_TCPOPSRDY    V_TCPOPSRDY(1U)
+
+#define S_TCPOPDRDY    4
+#define V_TCPOPDRDY(x) ((x) << S_TCPOPDRDY)
+#define F_TCPOPDRDY    V_TCPOPDRDY(1U)
+
+#define S_PLDTXSRDY    3
+#define V_PLDTXSRDY(x) ((x) << S_PLDTXSRDY)
+#define F_PLDTXSRDY    V_PLDTXSRDY(1U)
+
+#define S_PLDTXDRDY    2
+#define V_PLDTXDRDY(x) ((x) << S_PLDTXDRDY)
+#define F_PLDTXDRDY    V_PLDTXDRDY(1U)
+
+#define S_TCPOPTTXVALID    1
+#define V_TCPOPTTXVALID(x) ((x) << S_TCPOPTTXVALID)
+#define F_TCPOPTTXVALID    V_TCPOPTTXVALID(1U)
+
+#define S_TCPOPTTXFULL    0
+#define V_TCPOPTTXFULL(x) ((x) << S_TCPOPTTXFULL)
+#define F_TCPOPTTXFULL    V_TCPOPTTXFULL(1U)
+
+#define A_TP_DBG_ESIDE_DEMUX 0x149
+
+#define S_EALLDONE    28
+#define M_EALLDONE    0xfU
+#define V_EALLDONE(x) ((x) << S_EALLDONE)
+#define G_EALLDONE(x) (((x) >> S_EALLDONE) & M_EALLDONE)
+
+#define S_EFIFOPLDDONE    24
+#define M_EFIFOPLDDONE    0xfU
+#define V_EFIFOPLDDONE(x) ((x) << S_EFIFOPLDDONE)
+#define G_EFIFOPLDDONE(x) (((x) >> S_EFIFOPLDDONE) & M_EFIFOPLDDONE)
+
+#define S_EDBDONE    20
+#define M_EDBDONE    0xfU
+#define V_EDBDONE(x) ((x) << S_EDBDONE)
+#define G_EDBDONE(x) (((x) >> S_EDBDONE) & M_EDBDONE)
+
+#define S_EISSFIFODONE    16
+#define M_EISSFIFODONE    0xfU
+#define V_EISSFIFODONE(x) ((x) << S_EISSFIFODONE)
+#define G_EISSFIFODONE(x) (((x) >> S_EISSFIFODONE) & M_EISSFIFODONE)
+
+#define S_EACKERRFIFODONE    12
+#define M_EACKERRFIFODONE    0xfU
+#define V_EACKERRFIFODONE(x) ((x) << S_EACKERRFIFODONE)
+#define G_EACKERRFIFODONE(x) (((x) >> S_EACKERRFIFODONE) & M_EACKERRFIFODONE)
+
+#define S_EFIFOERRORDONE    8
+#define M_EFIFOERRORDONE    0xfU
+#define V_EFIFOERRORDONE(x) ((x) << S_EFIFOERRORDONE)
+#define G_EFIFOERRORDONE(x) (((x) >> S_EFIFOERRORDONE) & M_EFIFOERRORDONE)
+
+#define S_ERXPKTATTRFIFOFDONE    4
+#define M_ERXPKTATTRFIFOFDONE    0xfU
+#define V_ERXPKTATTRFIFOFDONE(x) ((x) << S_ERXPKTATTRFIFOFDONE)
+#define G_ERXPKTATTRFIFOFDONE(x) (((x) >> S_ERXPKTATTRFIFOFDONE) & M_ERXPKTATTRFIFOFDONE)
+
+#define S_ETCPOPDONE    0
+#define M_ETCPOPDONE    0xfU
+#define V_ETCPOPDONE(x) ((x) << S_ETCPOPDONE)
+#define G_ETCPOPDONE(x) (((x) >> S_ETCPOPDONE) & M_ETCPOPDONE)
+
+#define A_TP_DBG_ESIDE_IN0 0x14a
+
+#define S_RXVALID    31
+#define V_RXVALID(x) ((x) << S_RXVALID)
+#define F_RXVALID    V_RXVALID(1U)
+
+#define S_RXFULL    30
+#define V_RXFULL(x) ((x) << S_RXFULL)
+#define F_RXFULL    V_RXFULL(1U)
+
+#define S_RXSOCP    29
+#define V_RXSOCP(x) ((x) << S_RXSOCP)
+#define F_RXSOCP    V_RXSOCP(1U)
+
+#define S_RXEOP    28
+#define V_RXEOP(x) ((x) << S_RXEOP)
+#define F_RXEOP    V_RXEOP(1U)
+
+#define S_RXVALID_I    27
+#define V_RXVALID_I(x) ((x) << S_RXVALID_I)
+#define F_RXVALID_I    V_RXVALID_I(1U)
+
+#define S_RXFULL_I    26
+#define V_RXFULL_I(x) ((x) << S_RXFULL_I)
+#define F_RXFULL_I    V_RXFULL_I(1U)
+
+#define S_RXSOCP_I    25
+#define V_RXSOCP_I(x) ((x) << S_RXSOCP_I)
+#define F_RXSOCP_I    V_RXSOCP_I(1U)
+
+#define S_RXEOP_I    24
+#define V_RXEOP_I(x) ((x) << S_RXEOP_I)
+#define F_RXEOP_I    V_RXEOP_I(1U)
+
+#define S_RXVALID_I2    23
+#define V_RXVALID_I2(x) ((x) << S_RXVALID_I2)
+#define F_RXVALID_I2    V_RXVALID_I2(1U)
+
+#define S_RXFULL_I2    22
+#define V_RXFULL_I2(x) ((x) << S_RXFULL_I2)
+#define F_RXFULL_I2    V_RXFULL_I2(1U)
+
+#define S_RXSOCP_I2    21
+#define V_RXSOCP_I2(x) ((x) << S_RXSOCP_I2)
+#define F_RXSOCP_I2    V_RXSOCP_I2(1U)
+
+#define S_RXEOP_I2    20
+#define V_RXEOP_I2(x) ((x) << S_RXEOP_I2)
+#define F_RXEOP_I2    V_RXEOP_I2(1U)
+
+#define S_CT_MPA_TXVALID_FIFO    19
+#define V_CT_MPA_TXVALID_FIFO(x) ((x) << S_CT_MPA_TXVALID_FIFO)
+#define F_CT_MPA_TXVALID_FIFO    V_CT_MPA_TXVALID_FIFO(1U)
+
+#define S_CT_MPA_TXFULL_FIFO    18
+#define V_CT_MPA_TXFULL_FIFO(x) ((x) << S_CT_MPA_TXFULL_FIFO)
+#define F_CT_MPA_TXFULL_FIFO    V_CT_MPA_TXFULL_FIFO(1U)
+
+#define S_CT_MPA_TXVALID    17
+#define V_CT_MPA_TXVALID(x) ((x) << S_CT_MPA_TXVALID)
+#define F_CT_MPA_TXVALID    V_CT_MPA_TXVALID(1U)
+
+#define S_CT_MPA_TXFULL    16
+#define V_CT_MPA_TXFULL(x) ((x) << S_CT_MPA_TXFULL)
+#define F_CT_MPA_TXFULL    V_CT_MPA_TXFULL(1U)
+
+#define S_RXVALID_BUF    15
+#define V_RXVALID_BUF(x) ((x) << S_RXVALID_BUF)
+#define F_RXVALID_BUF    V_RXVALID_BUF(1U)
+
+#define S_RXFULL_BUF    14
+#define V_RXFULL_BUF(x) ((x) << S_RXFULL_BUF)
+#define F_RXFULL_BUF    V_RXFULL_BUF(1U)
+
+#define S_PLD_TXVALID    13
+#define V_PLD_TXVALID(x) ((x) << S_PLD_TXVALID)
+#define F_PLD_TXVALID    V_PLD_TXVALID(1U)
+
+#define S_PLD_TXFULL    12
+#define V_PLD_TXFULL(x) ((x) << S_PLD_TXFULL)
+#define F_PLD_TXFULL    V_PLD_TXFULL(1U)
+
+#define S_ISS_FIFO_SRDY    11
+#define V_ISS_FIFO_SRDY(x) ((x) << S_ISS_FIFO_SRDY)
+#define F_ISS_FIFO_SRDY    V_ISS_FIFO_SRDY(1U)
+
+#define S_ISS_FIFO_DRDY    10
+#define V_ISS_FIFO_DRDY(x) ((x) << S_ISS_FIFO_DRDY)
+#define F_ISS_FIFO_DRDY    V_ISS_FIFO_DRDY(1U)
+
+#define S_CT_TCP_OP_ISS_SRDY    9
+#define V_CT_TCP_OP_ISS_SRDY(x) ((x) << S_CT_TCP_OP_ISS_SRDY)
+#define F_CT_TCP_OP_ISS_SRDY    V_CT_TCP_OP_ISS_SRDY(1U)
+
+#define S_CT_TCP_OP_ISS_DRDY    8
+#define V_CT_TCP_OP_ISS_DRDY(x) ((x) << S_CT_TCP_OP_ISS_DRDY)
+#define F_CT_TCP_OP_ISS_DRDY    V_CT_TCP_OP_ISS_DRDY(1U)
+
+#define S_P2CSUMERROR_SRDY    7
+#define V_P2CSUMERROR_SRDY(x) ((x) << S_P2CSUMERROR_SRDY)
+#define F_P2CSUMERROR_SRDY    V_P2CSUMERROR_SRDY(1U)
+
+#define S_P2CSUMERROR_DRDY    6
+#define V_P2CSUMERROR_DRDY(x) ((x) << S_P2CSUMERROR_DRDY)
+#define F_P2CSUMERROR_DRDY    V_P2CSUMERROR_DRDY(1U)
+
+#define S_FIFO_ERROR_SRDY    5
+#define V_FIFO_ERROR_SRDY(x) ((x) << S_FIFO_ERROR_SRDY)
+#define F_FIFO_ERROR_SRDY    V_FIFO_ERROR_SRDY(1U)
+
+#define S_FIFO_ERROR_DRDY    4
+#define V_FIFO_ERROR_DRDY(x) ((x) << S_FIFO_ERROR_DRDY)
+#define F_FIFO_ERROR_DRDY    V_FIFO_ERROR_DRDY(1U)
+
+#define S_PLD_SRDY    3
+#define V_PLD_SRDY(x) ((x) << S_PLD_SRDY)
+#define F_PLD_SRDY    V_PLD_SRDY(1U)
+
+#define S_PLD_DRDY    2
+#define V_PLD_DRDY(x) ((x) << S_PLD_DRDY)
+#define F_PLD_DRDY    V_PLD_DRDY(1U)
+
+#define S_RX_PKT_ATTR_SRDY    1
+#define V_RX_PKT_ATTR_SRDY(x) ((x) << S_RX_PKT_ATTR_SRDY)
+#define F_RX_PKT_ATTR_SRDY    V_RX_PKT_ATTR_SRDY(1U)
+
+#define S_RX_PKT_ATTR_DRDY    0
+#define V_RX_PKT_ATTR_DRDY(x) ((x) << S_RX_PKT_ATTR_DRDY)
+#define F_RX_PKT_ATTR_DRDY    V_RX_PKT_ATTR_DRDY(1U)
+
+#define S_RXRUNT    25
+#define V_RXRUNT(x) ((x) << S_RXRUNT)
+#define F_RXRUNT    V_RXRUNT(1U)
+
+#define S_RXRUNTPARSER    24
+#define V_RXRUNTPARSER(x) ((x) << S_RXRUNTPARSER)
+#define F_RXRUNTPARSER    V_RXRUNTPARSER(1U)
+
+#define S_ERROR_SRDY    5
+#define V_ERROR_SRDY(x) ((x) << S_ERROR_SRDY)
+#define F_ERROR_SRDY    V_ERROR_SRDY(1U)
+
+#define S_ERROR_DRDY    4
+#define V_ERROR_DRDY(x) ((x) << S_ERROR_DRDY)
+#define F_ERROR_DRDY    V_ERROR_DRDY(1U)
+
+#define A_TP_DBG_ESIDE_IN1 0x14b
+#define A_TP_DBG_ESIDE_IN2 0x14c
+#define A_TP_DBG_ESIDE_IN3 0x14d
+#define A_TP_DBG_ESIDE_FRM 0x14e
+
+#define S_ERX2XERROR    28
+#define M_ERX2XERROR    0xfU
+#define V_ERX2XERROR(x) ((x) << S_ERX2XERROR)
+#define G_ERX2XERROR(x) (((x) >> S_ERX2XERROR) & M_ERX2XERROR)
+
+#define S_EPLDTX2XERROR    24
+#define M_EPLDTX2XERROR    0xfU
+#define V_EPLDTX2XERROR(x) ((x) << S_EPLDTX2XERROR)
+#define G_EPLDTX2XERROR(x) (((x) >> S_EPLDTX2XERROR) & M_EPLDTX2XERROR)
+
+#define S_ETXERROR    20
+#define M_ETXERROR    0xfU
+#define V_ETXERROR(x) ((x) << S_ETXERROR)
+#define G_ETXERROR(x) (((x) >> S_ETXERROR) & M_ETXERROR)
+
+#define S_EPLDRXERROR    16
+#define M_EPLDRXERROR    0xfU
+#define V_EPLDRXERROR(x) ((x) << S_EPLDRXERROR)
+#define G_EPLDRXERROR(x) (((x) >> S_EPLDRXERROR) & M_EPLDRXERROR)
+
+#define S_ERXSIZEERROR3    12
+#define M_ERXSIZEERROR3    0xfU
+#define V_ERXSIZEERROR3(x) ((x) << S_ERXSIZEERROR3)
+#define G_ERXSIZEERROR3(x) (((x) >> S_ERXSIZEERROR3) & M_ERXSIZEERROR3)
+
+#define S_ERXSIZEERROR2    8
+#define M_ERXSIZEERROR2    0xfU
+#define V_ERXSIZEERROR2(x) ((x) << S_ERXSIZEERROR2)
+#define G_ERXSIZEERROR2(x) (((x) >> S_ERXSIZEERROR2) & M_ERXSIZEERROR2)
+
+#define S_ERXSIZEERROR1    4
+#define M_ERXSIZEERROR1    0xfU
+#define V_ERXSIZEERROR1(x) ((x) << S_ERXSIZEERROR1)
+#define G_ERXSIZEERROR1(x) (((x) >> S_ERXSIZEERROR1) & M_ERXSIZEERROR1)
+
+#define S_ERXSIZEERROR0    0
+#define M_ERXSIZEERROR0    0xfU
+#define V_ERXSIZEERROR0(x) ((x) << S_ERXSIZEERROR0)
+#define G_ERXSIZEERROR0(x) (((x) >> S_ERXSIZEERROR0) & M_ERXSIZEERROR0)
+
+#define A_TP_DBG_ESIDE_DRP 0x14f
+
+#define S_RXDROP3    24
+#define M_RXDROP3    0xffU
+#define V_RXDROP3(x) ((x) << S_RXDROP3)
+#define G_RXDROP3(x) (((x) >> S_RXDROP3) & M_RXDROP3)
+
+#define S_RXDROP2    16
+#define M_RXDROP2    0xffU
+#define V_RXDROP2(x) ((x) << S_RXDROP2)
+#define G_RXDROP2(x) (((x) >> S_RXDROP2) & M_RXDROP2)
+
+#define S_RXDROP1    8
+#define M_RXDROP1    0xffU
+#define V_RXDROP1(x) ((x) << S_RXDROP1)
+#define G_RXDROP1(x) (((x) >> S_RXDROP1) & M_RXDROP1)
+
+#define S_RXDROP0    0
+#define M_RXDROP0    0xffU
+#define V_RXDROP0(x) ((x) << S_RXDROP0)
+#define G_RXDROP0(x) (((x) >> S_RXDROP0) & M_RXDROP0)
+
+#define A_TP_DBG_ESIDE_TX 0x150
+
+#define S_ETXVALID    4
+#define M_ETXVALID    0xfU
+#define V_ETXVALID(x) ((x) << S_ETXVALID)
+#define G_ETXVALID(x) (((x) >> S_ETXVALID) & M_ETXVALID)
+
+#define S_ETXFULL    0
+#define M_ETXFULL    0xfU
+#define V_ETXFULL(x) ((x) << S_ETXFULL)
+#define G_ETXFULL(x) (((x) >> S_ETXFULL) & M_ETXFULL)
+
+#define A_TP_ESIDE_SVID_MASK 0x151
+#define A_TP_ESIDE_DVID_MASK 0x152
+#define A_TP_ESIDE_ALIGN_MASK 0x153
+
+#define S_USE_LOOP_BIT    24
+#define V_USE_LOOP_BIT(x) ((x) << S_USE_LOOP_BIT)
+#define F_USE_LOOP_BIT    V_USE_LOOP_BIT(1U)
+
+#define S_LOOP_OFFSET    16
+#define M_LOOP_OFFSET    0xffU
+#define V_LOOP_OFFSET(x) ((x) << S_LOOP_OFFSET)
+#define G_LOOP_OFFSET(x) (((x) >> S_LOOP_OFFSET) & M_LOOP_OFFSET)
+
+#define S_DVID_ID_OFFSET    8
+#define M_DVID_ID_OFFSET    0xffU
+#define V_DVID_ID_OFFSET(x) ((x) << S_DVID_ID_OFFSET)
+#define G_DVID_ID_OFFSET(x) (((x) >> S_DVID_ID_OFFSET) & M_DVID_ID_OFFSET)
+
+#define S_SVID_ID_OFFSET    0
+#define M_SVID_ID_OFFSET    0xffU
+#define V_SVID_ID_OFFSET(x) ((x) << S_SVID_ID_OFFSET)
+#define G_SVID_ID_OFFSET(x) (((x) >> S_SVID_ID_OFFSET) & M_SVID_ID_OFFSET)
+
+#define A_TP_DBG_ESIDE_OP 0x154
+
+#define S_OPT_PARSER_FATAL_CHANNEL0    29
+#define V_OPT_PARSER_FATAL_CHANNEL0(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL0)
+#define F_OPT_PARSER_FATAL_CHANNEL0    V_OPT_PARSER_FATAL_CHANNEL0(1U)
+
+#define S_OPT_PARSER_BUSY_CHANNEL0    28
+#define V_OPT_PARSER_BUSY_CHANNEL0(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL0)
+#define F_OPT_PARSER_BUSY_CHANNEL0    V_OPT_PARSER_BUSY_CHANNEL0(1U)
+
+#define S_OPT_PARSER_ITCP_STATE_CHANNEL0    26
+#define M_OPT_PARSER_ITCP_STATE_CHANNEL0    0x3U
+#define V_OPT_PARSER_ITCP_STATE_CHANNEL0(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL0)
+#define G_OPT_PARSER_ITCP_STATE_CHANNEL0(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL0) & M_OPT_PARSER_ITCP_STATE_CHANNEL0)
+
+#define S_OPT_PARSER_OTK_STATE_CHANNEL0    24
+#define M_OPT_PARSER_OTK_STATE_CHANNEL0    0x3U
+#define V_OPT_PARSER_OTK_STATE_CHANNEL0(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL0)
+#define G_OPT_PARSER_OTK_STATE_CHANNEL0(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL0) & M_OPT_PARSER_OTK_STATE_CHANNEL0)
+
+#define S_OPT_PARSER_FATAL_CHANNEL1    21
+#define V_OPT_PARSER_FATAL_CHANNEL1(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL1)
+#define F_OPT_PARSER_FATAL_CHANNEL1    V_OPT_PARSER_FATAL_CHANNEL1(1U)
+
+#define S_OPT_PARSER_BUSY_CHANNEL1    20
+#define V_OPT_PARSER_BUSY_CHANNEL1(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL1)
+#define F_OPT_PARSER_BUSY_CHANNEL1    V_OPT_PARSER_BUSY_CHANNEL1(1U)
+
+#define S_OPT_PARSER_ITCP_STATE_CHANNEL1    18
+#define M_OPT_PARSER_ITCP_STATE_CHANNEL1    0x3U
+#define V_OPT_PARSER_ITCP_STATE_CHANNEL1(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL1)
+#define G_OPT_PARSER_ITCP_STATE_CHANNEL1(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL1) & M_OPT_PARSER_ITCP_STATE_CHANNEL1)
+
+#define S_OPT_PARSER_OTK_STATE_CHANNEL1    16
+#define M_OPT_PARSER_OTK_STATE_CHANNEL1    0x3U
+#define V_OPT_PARSER_OTK_STATE_CHANNEL1(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL1)
+#define G_OPT_PARSER_OTK_STATE_CHANNEL1(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL1) & M_OPT_PARSER_OTK_STATE_CHANNEL1)
+
+#define S_OPT_PARSER_FATAL_CHANNEL2    13
+#define V_OPT_PARSER_FATAL_CHANNEL2(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL2)
+#define F_OPT_PARSER_FATAL_CHANNEL2    V_OPT_PARSER_FATAL_CHANNEL2(1U)
+
+#define S_OPT_PARSER_BUSY_CHANNEL2    12
+#define V_OPT_PARSER_BUSY_CHANNEL2(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL2)
+#define F_OPT_PARSER_BUSY_CHANNEL2    V_OPT_PARSER_BUSY_CHANNEL2(1U)
+
+#define S_OPT_PARSER_ITCP_STATE_CHANNEL2    10
+#define M_OPT_PARSER_ITCP_STATE_CHANNEL2    0x3U
+#define V_OPT_PARSER_ITCP_STATE_CHANNEL2(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL2)
+#define G_OPT_PARSER_ITCP_STATE_CHANNEL2(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL2) & M_OPT_PARSER_ITCP_STATE_CHANNEL2)
+
+#define S_OPT_PARSER_OTK_STATE_CHANNEL2    8
+#define M_OPT_PARSER_OTK_STATE_CHANNEL2    0x3U
+#define V_OPT_PARSER_OTK_STATE_CHANNEL2(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL2)
+#define G_OPT_PARSER_OTK_STATE_CHANNEL2(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL2) & M_OPT_PARSER_OTK_STATE_CHANNEL2)
+
+#define S_OPT_PARSER_FATAL_CHANNEL3    5
+#define V_OPT_PARSER_FATAL_CHANNEL3(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL3)
+#define F_OPT_PARSER_FATAL_CHANNEL3    V_OPT_PARSER_FATAL_CHANNEL3(1U)
+
+#define S_OPT_PARSER_BUSY_CHANNEL3    4
+#define V_OPT_PARSER_BUSY_CHANNEL3(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL3)
+#define F_OPT_PARSER_BUSY_CHANNEL3    V_OPT_PARSER_BUSY_CHANNEL3(1U)
+
+#define S_OPT_PARSER_ITCP_STATE_CHANNEL3    2
+#define M_OPT_PARSER_ITCP_STATE_CHANNEL3    0x3U
+#define V_OPT_PARSER_ITCP_STATE_CHANNEL3(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL3)
+#define G_OPT_PARSER_ITCP_STATE_CHANNEL3(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL3) & M_OPT_PARSER_ITCP_STATE_CHANNEL3)
+
+#define S_OPT_PARSER_OTK_STATE_CHANNEL3    0
+#define M_OPT_PARSER_OTK_STATE_CHANNEL3    0x3U
+#define V_OPT_PARSER_OTK_STATE_CHANNEL3(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL3)
+#define G_OPT_PARSER_OTK_STATE_CHANNEL3(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL3) & M_OPT_PARSER_OTK_STATE_CHANNEL3)
+
+#define A_TP_DBG_ESIDE_OP_ALT 0x155
+
+#define S_OPT_PARSER_PSTATE_FATAL_CHANNEL0    29
+#define V_OPT_PARSER_PSTATE_FATAL_CHANNEL0(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL0)
+#define F_OPT_PARSER_PSTATE_FATAL_CHANNEL0    V_OPT_PARSER_PSTATE_FATAL_CHANNEL0(1U)
+
+#define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0    24
+#define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL0    0x1fU
+#define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL0(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0)
+#define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL0(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL0)
+
+#define S_OPT_PARSER_PSTATE_FATAL_CHANNEL1    21
+#define V_OPT_PARSER_PSTATE_FATAL_CHANNEL1(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL1)
+#define F_OPT_PARSER_PSTATE_FATAL_CHANNEL1    V_OPT_PARSER_PSTATE_FATAL_CHANNEL1(1U)
+
+#define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1    16
+#define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL1    0x1fU
+#define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL1(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1)
+#define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL1(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL1)
+
+#define S_OPT_PARSER_PSTATE_FATAL_CHANNEL2    13
+#define V_OPT_PARSER_PSTATE_FATAL_CHANNEL2(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL2)
+#define F_OPT_PARSER_PSTATE_FATAL_CHANNEL2    V_OPT_PARSER_PSTATE_FATAL_CHANNEL2(1U)
+
+#define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2    8
+#define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL2    0x1fU
+#define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL2(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2)
+#define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL2(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL2)
+
+#define S_OPT_PARSER_PSTATE_FATAL_CHANNEL3    5
+#define V_OPT_PARSER_PSTATE_FATAL_CHANNEL3(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL3)
+#define F_OPT_PARSER_PSTATE_FATAL_CHANNEL3    V_OPT_PARSER_PSTATE_FATAL_CHANNEL3(1U)
+
+#define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3    0
+#define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL3    0x1fU
+#define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL3(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3)
+#define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL3(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL3)
+
+#define A_TP_DBG_ESIDE_OP_BUSY 0x156
+
+#define S_OPT_PARSER_BUSY_VEC_CHANNEL3    24
+#define M_OPT_PARSER_BUSY_VEC_CHANNEL3    0xffU
+#define V_OPT_PARSER_BUSY_VEC_CHANNEL3(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL3)
+#define G_OPT_PARSER_BUSY_VEC_CHANNEL3(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL3) & M_OPT_PARSER_BUSY_VEC_CHANNEL3)
+
+#define S_OPT_PARSER_BUSY_VEC_CHANNEL2    16
+#define M_OPT_PARSER_BUSY_VEC_CHANNEL2    0xffU
+#define V_OPT_PARSER_BUSY_VEC_CHANNEL2(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL2)
+#define G_OPT_PARSER_BUSY_VEC_CHANNEL2(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL2) & M_OPT_PARSER_BUSY_VEC_CHANNEL2)
+
+#define S_OPT_PARSER_BUSY_VEC_CHANNEL1    8
+#define M_OPT_PARSER_BUSY_VEC_CHANNEL1    0xffU
+#define V_OPT_PARSER_BUSY_VEC_CHANNEL1(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL1)
+#define G_OPT_PARSER_BUSY_VEC_CHANNEL1(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL1) & M_OPT_PARSER_BUSY_VEC_CHANNEL1)
+
+#define S_OPT_PARSER_BUSY_VEC_CHANNEL0    0
+#define M_OPT_PARSER_BUSY_VEC_CHANNEL0    0xffU
+#define V_OPT_PARSER_BUSY_VEC_CHANNEL0(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL0)
+#define G_OPT_PARSER_BUSY_VEC_CHANNEL0(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL0) & M_OPT_PARSER_BUSY_VEC_CHANNEL0)
+
+#define A_TP_DBG_ESIDE_OP_COOKIE 0x157
+
+#define S_OPT_PARSER_COOKIE_CHANNEL3    24
+#define M_OPT_PARSER_COOKIE_CHANNEL3    0xffU
+#define V_OPT_PARSER_COOKIE_CHANNEL3(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL3)
+#define G_OPT_PARSER_COOKIE_CHANNEL3(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL3) & M_OPT_PARSER_COOKIE_CHANNEL3)
+
+#define S_OPT_PARSER_COOKIE_CHANNEL2    16
+#define M_OPT_PARSER_COOKIE_CHANNEL2    0xffU
+#define V_OPT_PARSER_COOKIE_CHANNEL2(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL2)
+#define G_OPT_PARSER_COOKIE_CHANNEL2(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL2) & M_OPT_PARSER_COOKIE_CHANNEL2)
+
+#define S_OPT_PARSER_COOKIE_CHANNEL1    8
+#define M_OPT_PARSER_COOKIE_CHANNEL1    0xffU
+#define V_OPT_PARSER_COOKIE_CHANNEL1(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL1)
+#define G_OPT_PARSER_COOKIE_CHANNEL1(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL1) & M_OPT_PARSER_COOKIE_CHANNEL1)
+
+#define S_OPT_PARSER_COOKIE_CHANNEL0    0
+#define M_OPT_PARSER_COOKIE_CHANNEL0    0xffU
+#define V_OPT_PARSER_COOKIE_CHANNEL0(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL0)
+#define G_OPT_PARSER_COOKIE_CHANNEL0(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL0) & M_OPT_PARSER_COOKIE_CHANNEL0)
+
+#define A_TP_DBG_CSIDE_RX0 0x230
+
+#define S_CRXSOPCNT    28
+#define M_CRXSOPCNT    0xfU
+#define V_CRXSOPCNT(x) ((x) << S_CRXSOPCNT)
+#define G_CRXSOPCNT(x) (((x) >> S_CRXSOPCNT) & M_CRXSOPCNT)
+
+#define S_CRXEOPCNT    24
+#define M_CRXEOPCNT    0xfU
+#define V_CRXEOPCNT(x) ((x) << S_CRXEOPCNT)
+#define G_CRXEOPCNT(x) (((x) >> S_CRXEOPCNT) & M_CRXEOPCNT)
+
+#define S_CRXPLDSOPCNT    20
+#define M_CRXPLDSOPCNT    0xfU
+#define V_CRXPLDSOPCNT(x) ((x) << S_CRXPLDSOPCNT)
+#define G_CRXPLDSOPCNT(x) (((x) >> S_CRXPLDSOPCNT) & M_CRXPLDSOPCNT)
+
+#define S_CRXPLDEOPCNT    16
+#define M_CRXPLDEOPCNT    0xfU
+#define V_CRXPLDEOPCNT(x) ((x) << S_CRXPLDEOPCNT)
+#define G_CRXPLDEOPCNT(x) (((x) >> S_CRXPLDEOPCNT) & M_CRXPLDEOPCNT)
+
+#define S_CRXARBSOPCNT    12
+#define M_CRXARBSOPCNT    0xfU
+#define V_CRXARBSOPCNT(x) ((x) << S_CRXARBSOPCNT)
+#define G_CRXARBSOPCNT(x) (((x) >> S_CRXARBSOPCNT) & M_CRXARBSOPCNT)
+
+#define S_CRXARBEOPCNT    8
+#define M_CRXARBEOPCNT    0xfU
+#define V_CRXARBEOPCNT(x) ((x) << S_CRXARBEOPCNT)
+#define G_CRXARBEOPCNT(x) (((x) >> S_CRXARBEOPCNT) & M_CRXARBEOPCNT)
+
+#define S_CRXCPLSOPCNT    4
+#define M_CRXCPLSOPCNT    0xfU
+#define V_CRXCPLSOPCNT(x) ((x) << S_CRXCPLSOPCNT)
+#define G_CRXCPLSOPCNT(x) (((x) >> S_CRXCPLSOPCNT) & M_CRXCPLSOPCNT)
+
+#define S_CRXCPLEOPCNT    0
+#define M_CRXCPLEOPCNT    0xfU
+#define V_CRXCPLEOPCNT(x) ((x) << S_CRXCPLEOPCNT)
+#define G_CRXCPLEOPCNT(x) (((x) >> S_CRXCPLEOPCNT) & M_CRXCPLEOPCNT)
+
+#define A_TP_DBG_CSIDE_RX1 0x231
+#define A_TP_DBG_CSIDE_RX2 0x232
+#define A_TP_DBG_CSIDE_RX3 0x233
+#define A_TP_DBG_CSIDE_TX0 0x234
+
+#define S_TXSOPCNT    28
+#define M_TXSOPCNT    0xfU
+#define V_TXSOPCNT(x) ((x) << S_TXSOPCNT)
+#define G_TXSOPCNT(x) (((x) >> S_TXSOPCNT) & M_TXSOPCNT)
+
+#define S_TXEOPCNT    24
+#define M_TXEOPCNT    0xfU
+#define V_TXEOPCNT(x) ((x) << S_TXEOPCNT)
+#define G_TXEOPCNT(x) (((x) >> S_TXEOPCNT) & M_TXEOPCNT)
+
+#define S_TXPLDSOPCNT    20
+#define M_TXPLDSOPCNT    0xfU
+#define V_TXPLDSOPCNT(x) ((x) << S_TXPLDSOPCNT)
+#define G_TXPLDSOPCNT(x) (((x) >> S_TXPLDSOPCNT) & M_TXPLDSOPCNT)
+
+#define S_TXPLDEOPCNT    16
+#define M_TXPLDEOPCNT    0xfU
+#define V_TXPLDEOPCNT(x) ((x) << S_TXPLDEOPCNT)
+#define G_TXPLDEOPCNT(x) (((x) >> S_TXPLDEOPCNT) & M_TXPLDEOPCNT)
+
+#define S_TXARBSOPCNT    12
+#define M_TXARBSOPCNT    0xfU
+#define V_TXARBSOPCNT(x) ((x) << S_TXARBSOPCNT)
+#define G_TXARBSOPCNT(x) (((x) >> S_TXARBSOPCNT) & M_TXARBSOPCNT)
+
+#define S_TXARBEOPCNT    8
+#define M_TXARBEOPCNT    0xfU
+#define V_TXARBEOPCNT(x) ((x) << S_TXARBEOPCNT)
+#define G_TXARBEOPCNT(x) (((x) >> S_TXARBEOPCNT) & M_TXARBEOPCNT)
+
+#define S_TXCPLSOPCNT    4
+#define M_TXCPLSOPCNT    0xfU
+#define V_TXCPLSOPCNT(x) ((x) << S_TXCPLSOPCNT)
+#define G_TXCPLSOPCNT(x) (((x) >> S_TXCPLSOPCNT) & M_TXCPLSOPCNT)
+
+#define S_TXCPLEOPCNT    0
+#define M_TXCPLEOPCNT    0xfU
+#define V_TXCPLEOPCNT(x) ((x) << S_TXCPLEOPCNT)
+#define G_TXCPLEOPCNT(x) (((x) >> S_TXCPLEOPCNT) & M_TXCPLEOPCNT)
+
+#define A_TP_DBG_CSIDE_TX1 0x235
+#define A_TP_DBG_CSIDE_TX2 0x236
+#define A_TP_DBG_CSIDE_TX3 0x237
+#define A_TP_DBG_CSIDE_FIFO0 0x238
+
+#define S_PLD_RXZEROP_SRDY1    31
+#define V_PLD_RXZEROP_SRDY1(x) ((x) << S_PLD_RXZEROP_SRDY1)
+#define F_PLD_RXZEROP_SRDY1    V_PLD_RXZEROP_SRDY1(1U)
+
+#define S_PLD_RXZEROP_DRDY1    30
+#define V_PLD_RXZEROP_DRDY1(x) ((x) << S_PLD_RXZEROP_DRDY1)
+#define F_PLD_RXZEROP_DRDY1    V_PLD_RXZEROP_DRDY1(1U)
+
+#define S_PLD_TXZEROP_SRDY1    29
+#define V_PLD_TXZEROP_SRDY1(x) ((x) << S_PLD_TXZEROP_SRDY1)
+#define F_PLD_TXZEROP_SRDY1    V_PLD_TXZEROP_SRDY1(1U)
+
+#define S_PLD_TXZEROP_DRDY1    28
+#define V_PLD_TXZEROP_DRDY1(x) ((x) << S_PLD_TXZEROP_DRDY1)
+#define F_PLD_TXZEROP_DRDY1    V_PLD_TXZEROP_DRDY1(1U)
+
+#define S_PLD_TX_SRDY1    27
+#define V_PLD_TX_SRDY1(x) ((x) << S_PLD_TX_SRDY1)
+#define F_PLD_TX_SRDY1    V_PLD_TX_SRDY1(1U)
+
+#define S_PLD_TX_DRDY1    26
+#define V_PLD_TX_DRDY1(x) ((x) << S_PLD_TX_DRDY1)
+#define F_PLD_TX_DRDY1    V_PLD_TX_DRDY1(1U)
+
+#define S_ERROR_SRDY1    25
+#define V_ERROR_SRDY1(x) ((x) << S_ERROR_SRDY1)
+#define F_ERROR_SRDY1    V_ERROR_SRDY1(1U)
+
+#define S_ERROR_DRDY1    24
+#define V_ERROR_DRDY1(x) ((x) << S_ERROR_DRDY1)
+#define F_ERROR_DRDY1    V_ERROR_DRDY1(1U)
+
+#define S_DB_VLD1    23
+#define V_DB_VLD1(x) ((x) << S_DB_VLD1)
+#define F_DB_VLD1    V_DB_VLD1(1U)
+
+#define S_DB_GT1    22
+#define V_DB_GT1(x) ((x) << S_DB_GT1)
+#define F_DB_GT1    V_DB_GT1(1U)
+
+#define S_TXVALID1    21
+#define V_TXVALID1(x) ((x) << S_TXVALID1)
+#define F_TXVALID1    V_TXVALID1(1U)
+
+#define S_TXFULL1    20
+#define V_TXFULL1(x) ((x) << S_TXFULL1)
+#define F_TXFULL1    V_TXFULL1(1U)
+
+#define S_PLD_TXVALID1    19
+#define V_PLD_TXVALID1(x) ((x) << S_PLD_TXVALID1)
+#define F_PLD_TXVALID1    V_PLD_TXVALID1(1U)
+
+#define S_PLD_TXFULL1    18
+#define V_PLD_TXFULL1(x) ((x) << S_PLD_TXFULL1)
+#define F_PLD_TXFULL1    V_PLD_TXFULL1(1U)
+
+#define S_CPL5_TXVALID1    17
+#define V_CPL5_TXVALID1(x) ((x) << S_CPL5_TXVALID1)
+#define F_CPL5_TXVALID1    V_CPL5_TXVALID1(1U)
+
+#define S_CPL5_TXFULL1    16
+#define V_CPL5_TXFULL1(x) ((x) << S_CPL5_TXFULL1)
+#define F_CPL5_TXFULL1    V_CPL5_TXFULL1(1U)
+
+#define S_PLD_RXZEROP_SRDY0    15
+#define V_PLD_RXZEROP_SRDY0(x) ((x) << S_PLD_RXZEROP_SRDY0)
+#define F_PLD_RXZEROP_SRDY0    V_PLD_RXZEROP_SRDY0(1U)
+
+#define S_PLD_RXZEROP_DRDY0    14
+#define V_PLD_RXZEROP_DRDY0(x) ((x) << S_PLD_RXZEROP_DRDY0)
+#define F_PLD_RXZEROP_DRDY0    V_PLD_RXZEROP_DRDY0(1U)
+
+#define S_PLD_TXZEROP_SRDY0    13
+#define V_PLD_TXZEROP_SRDY0(x) ((x) << S_PLD_TXZEROP_SRDY0)
+#define F_PLD_TXZEROP_SRDY0    V_PLD_TXZEROP_SRDY0(1U)
+
+#define S_PLD_TXZEROP_DRDY0    12
+#define V_PLD_TXZEROP_DRDY0(x) ((x) << S_PLD_TXZEROP_DRDY0)
+#define F_PLD_TXZEROP_DRDY0    V_PLD_TXZEROP_DRDY0(1U)
+
+#define S_PLD_TX_SRDY0    11
+#define V_PLD_TX_SRDY0(x) ((x) << S_PLD_TX_SRDY0)
+#define F_PLD_TX_SRDY0    V_PLD_TX_SRDY0(1U)
+
+#define S_PLD_TX_DRDY0    10
+#define V_PLD_TX_DRDY0(x) ((x) << S_PLD_TX_DRDY0)
+#define F_PLD_TX_DRDY0    V_PLD_TX_DRDY0(1U)
+
+#define S_ERROR_SRDY0    9
+#define V_ERROR_SRDY0(x) ((x) << S_ERROR_SRDY0)
+#define F_ERROR_SRDY0    V_ERROR_SRDY0(1U)
+
+#define S_ERROR_DRDY0    8
+#define V_ERROR_DRDY0(x) ((x) << S_ERROR_DRDY0)
+#define F_ERROR_DRDY0    V_ERROR_DRDY0(1U)
+
+#define S_DB_VLD0    7
+#define V_DB_VLD0(x) ((x) << S_DB_VLD0)
+#define F_DB_VLD0    V_DB_VLD0(1U)
+
+#define S_DB_GT0    6
+#define V_DB_GT0(x) ((x) << S_DB_GT0)
+#define F_DB_GT0    V_DB_GT0(1U)
+
+#define S_TXVALID0    5
+#define V_TXVALID0(x) ((x) << S_TXVALID0)
+#define F_TXVALID0    V_TXVALID0(1U)
+
+#define S_TXFULL0    4
+#define V_TXFULL0(x) ((x) << S_TXFULL0)
+#define F_TXFULL0    V_TXFULL0(1U)
+
+#define S_PLD_TXVALID0    3
+#define V_PLD_TXVALID0(x) ((x) << S_PLD_TXVALID0)
+#define F_PLD_TXVALID0    V_PLD_TXVALID0(1U)
+
+#define S_PLD_TXFULL0    2
+#define V_PLD_TXFULL0(x) ((x) << S_PLD_TXFULL0)
+#define F_PLD_TXFULL0    V_PLD_TXFULL0(1U)
+
+#define S_CPL5_TXVALID0    1
+#define V_CPL5_TXVALID0(x) ((x) << S_CPL5_TXVALID0)
+#define F_CPL5_TXVALID0    V_CPL5_TXVALID0(1U)
+
+#define S_CPL5_TXFULL0    0
+#define V_CPL5_TXFULL0(x) ((x) << S_CPL5_TXFULL0)
+#define F_CPL5_TXFULL0    V_CPL5_TXFULL0(1U)
+
+#define A_TP_DBG_CSIDE_FIFO1 0x239
+
+#define S_PLD_RXZEROP_SRDY3    31
+#define V_PLD_RXZEROP_SRDY3(x) ((x) << S_PLD_RXZEROP_SRDY3)
+#define F_PLD_RXZEROP_SRDY3    V_PLD_RXZEROP_SRDY3(1U)
+
+#define S_PLD_RXZEROP_DRDY3    30
+#define V_PLD_RXZEROP_DRDY3(x) ((x) << S_PLD_RXZEROP_DRDY3)
+#define F_PLD_RXZEROP_DRDY3    V_PLD_RXZEROP_DRDY3(1U)
+
+#define S_PLD_TXZEROP_SRDY3    29
+#define V_PLD_TXZEROP_SRDY3(x) ((x) << S_PLD_TXZEROP_SRDY3)
+#define F_PLD_TXZEROP_SRDY3    V_PLD_TXZEROP_SRDY3(1U)
+
+#define S_PLD_TXZEROP_DRDY3    28
+#define V_PLD_TXZEROP_DRDY3(x) ((x) << S_PLD_TXZEROP_DRDY3)
+#define F_PLD_TXZEROP_DRDY3    V_PLD_TXZEROP_DRDY3(1U)
+
+#define S_PLD_TX_SRDY3    27
+#define V_PLD_TX_SRDY3(x) ((x) << S_PLD_TX_SRDY3)
+#define F_PLD_TX_SRDY3    V_PLD_TX_SRDY3(1U)
+
+#define S_PLD_TX_DRDY3    26
+#define V_PLD_TX_DRDY3(x) ((x) << S_PLD_TX_DRDY3)
+#define F_PLD_TX_DRDY3    V_PLD_TX_DRDY3(1U)
+
+#define S_ERROR_SRDY3    25
+#define V_ERROR_SRDY3(x) ((x) << S_ERROR_SRDY3)
+#define F_ERROR_SRDY3    V_ERROR_SRDY3(1U)
+
+#define S_ERROR_DRDY3    24
+#define V_ERROR_DRDY3(x) ((x) << S_ERROR_DRDY3)
+#define F_ERROR_DRDY3    V_ERROR_DRDY3(1U)
+
+#define S_DB_VLD3    23
+#define V_DB_VLD3(x) ((x) << S_DB_VLD3)
+#define F_DB_VLD3    V_DB_VLD3(1U)
+
+#define S_DB_GT3    22
+#define V_DB_GT3(x) ((x) << S_DB_GT3)
+#define F_DB_GT3    V_DB_GT3(1U)
+
+#define S_TXVALID3    21
+#define V_TXVALID3(x) ((x) << S_TXVALID3)
+#define F_TXVALID3    V_TXVALID3(1U)
+
+#define S_TXFULL3    20
+#define V_TXFULL3(x) ((x) << S_TXFULL3)
+#define F_TXFULL3    V_TXFULL3(1U)
+
+#define S_PLD_TXVALID3    19
+#define V_PLD_TXVALID3(x) ((x) << S_PLD_TXVALID3)
+#define F_PLD_TXVALID3    V_PLD_TXVALID3(1U)
+
+#define S_PLD_TXFULL3    18
+#define V_PLD_TXFULL3(x) ((x) << S_PLD_TXFULL3)
+#define F_PLD_TXFULL3    V_PLD_TXFULL3(1U)
+
+#define S_CPL5_TXVALID3    17
+#define V_CPL5_TXVALID3(x) ((x) << S_CPL5_TXVALID3)
+#define F_CPL5_TXVALID3    V_CPL5_TXVALID3(1U)
+
+#define S_CPL5_TXFULL3    16
+#define V_CPL5_TXFULL3(x) ((x) << S_CPL5_TXFULL3)
+#define F_CPL5_TXFULL3    V_CPL5_TXFULL3(1U)
+
+#define S_PLD_RXZEROP_SRDY2    15
+#define V_PLD_RXZEROP_SRDY2(x) ((x) << S_PLD_RXZEROP_SRDY2)
+#define F_PLD_RXZEROP_SRDY2    V_PLD_RXZEROP_SRDY2(1U)
+
+#define S_PLD_RXZEROP_DRDY2    14
+#define V_PLD_RXZEROP_DRDY2(x) ((x) << S_PLD_RXZEROP_DRDY2)
+#define F_PLD_RXZEROP_DRDY2    V_PLD_RXZEROP_DRDY2(1U)
+
+#define S_PLD_TXZEROP_SRDY2    13
+#define V_PLD_TXZEROP_SRDY2(x) ((x) << S_PLD_TXZEROP_SRDY2)
+#define F_PLD_TXZEROP_SRDY2    V_PLD_TXZEROP_SRDY2(1U)
+
+#define S_PLD_TXZEROP_DRDY2    12
+#define V_PLD_TXZEROP_DRDY2(x) ((x) << S_PLD_TXZEROP_DRDY2)
+#define F_PLD_TXZEROP_DRDY2    V_PLD_TXZEROP_DRDY2(1U)
+
+#define S_PLD_TX_SRDY2    11
+#define V_PLD_TX_SRDY2(x) ((x) << S_PLD_TX_SRDY2)
+#define F_PLD_TX_SRDY2    V_PLD_TX_SRDY2(1U)
+
+#define S_PLD_TX_DRDY2    10
+#define V_PLD_TX_DRDY2(x) ((x) << S_PLD_TX_DRDY2)
+#define F_PLD_TX_DRDY2    V_PLD_TX_DRDY2(1U)
+
+#define S_ERROR_SRDY2    9
+#define V_ERROR_SRDY2(x) ((x) << S_ERROR_SRDY2)
+#define F_ERROR_SRDY2    V_ERROR_SRDY2(1U)
+
+#define S_ERROR_DRDY2    8
+#define V_ERROR_DRDY2(x) ((x) << S_ERROR_DRDY2)
+#define F_ERROR_DRDY2    V_ERROR_DRDY2(1U)
+
+#define S_DB_VLD2    7
+#define V_DB_VLD2(x) ((x) << S_DB_VLD2)
+#define F_DB_VLD2    V_DB_VLD2(1U)
+
+#define S_DB_GT2    6
+#define V_DB_GT2(x) ((x) << S_DB_GT2)
+#define F_DB_GT2    V_DB_GT2(1U)
+
+#define S_TXVALID2    5
+#define V_TXVALID2(x) ((x) << S_TXVALID2)
+#define F_TXVALID2    V_TXVALID2(1U)
+
+#define S_TXFULL2    4
+#define V_TXFULL2(x) ((x) << S_TXFULL2)
+#define F_TXFULL2    V_TXFULL2(1U)
+
+#define S_PLD_TXVALID2    3
+#define V_PLD_TXVALID2(x) ((x) << S_PLD_TXVALID2)
+#define F_PLD_TXVALID2    V_PLD_TXVALID2(1U)
+
+#define S_PLD_TXFULL2    2
+#define V_PLD_TXFULL2(x) ((x) << S_PLD_TXFULL2)
+#define F_PLD_TXFULL2    V_PLD_TXFULL2(1U)
+
+#define S_CPL5_TXVALID2    1
+#define V_CPL5_TXVALID2(x) ((x) << S_CPL5_TXVALID2)
+#define F_CPL5_TXVALID2    V_CPL5_TXVALID2(1U)
+
+#define S_CPL5_TXFULL2    0
+#define V_CPL5_TXFULL2(x) ((x) << S_CPL5_TXFULL2)
+#define F_CPL5_TXFULL2    V_CPL5_TXFULL2(1U)
+
+#define A_TP_DBG_CSIDE_DISP0 0x23a
+
+#define S_CPL5RXVALID    27
+#define V_CPL5RXVALID(x) ((x) << S_CPL5RXVALID)
+#define F_CPL5RXVALID    V_CPL5RXVALID(1U)
+
+#define S_CSTATIC1    26
+#define V_CSTATIC1(x) ((x) << S_CSTATIC1)
+#define F_CSTATIC1    V_CSTATIC1(1U)
+
+#define S_CSTATIC2    25
+#define V_CSTATIC2(x) ((x) << S_CSTATIC2)
+#define F_CSTATIC2    V_CSTATIC2(1U)
+
+#define S_PLD_RXZEROP    24
+#define V_PLD_RXZEROP(x) ((x) << S_PLD_RXZEROP)
+#define F_PLD_RXZEROP    V_PLD_RXZEROP(1U)
+
+#define S_DDP_IN_PROGRESS    23
+#define V_DDP_IN_PROGRESS(x) ((x) << S_DDP_IN_PROGRESS)
+#define F_DDP_IN_PROGRESS    V_DDP_IN_PROGRESS(1U)
+
+#define S_PLD_RXZEROP_SRDY    22
+#define V_PLD_RXZEROP_SRDY(x) ((x) << S_PLD_RXZEROP_SRDY)
+#define F_PLD_RXZEROP_SRDY    V_PLD_RXZEROP_SRDY(1U)
+
+#define S_CSTATIC3    21
+#define V_CSTATIC3(x) ((x) << S_CSTATIC3)
+#define F_CSTATIC3    V_CSTATIC3(1U)
+
+#define S_DDP_DRDY    20
+#define V_DDP_DRDY(x) ((x) << S_DDP_DRDY)
+#define F_DDP_DRDY    V_DDP_DRDY(1U)
+
+#define S_DDP_PRE_STATE    17
+#define M_DDP_PRE_STATE    0x7U
+#define V_DDP_PRE_STATE(x) ((x) << S_DDP_PRE_STATE)
+#define G_DDP_PRE_STATE(x) (((x) >> S_DDP_PRE_STATE) & M_DDP_PRE_STATE)
+
+#define S_DDP_SRDY    16
+#define V_DDP_SRDY(x) ((x) << S_DDP_SRDY)
+#define F_DDP_SRDY    V_DDP_SRDY(1U)
+
+#define S_DDP_MSG_CODE    12
+#define M_DDP_MSG_CODE    0xfU
+#define V_DDP_MSG_CODE(x) ((x) << S_DDP_MSG_CODE)
+#define G_DDP_MSG_CODE(x) (((x) >> S_DDP_MSG_CODE) & M_DDP_MSG_CODE)
+
+#define S_CPL5_SOCP_CNT    10
+#define M_CPL5_SOCP_CNT    0x3U
+#define V_CPL5_SOCP_CNT(x) ((x) << S_CPL5_SOCP_CNT)
+#define G_CPL5_SOCP_CNT(x) (((x) >> S_CPL5_SOCP_CNT) & M_CPL5_SOCP_CNT)
+
+#define S_CSTATIC4    4
+#define M_CSTATIC4    0x3fU
+#define V_CSTATIC4(x) ((x) << S_CSTATIC4)
+#define G_CSTATIC4(x) (((x) >> S_CSTATIC4) & M_CSTATIC4)
+
+#define S_CMD_SEL    1
+#define V_CMD_SEL(x) ((x) << S_CMD_SEL)
+#define F_CMD_SEL    V_CMD_SEL(1U)
+
+#define S_CPL5RXFULL    26
+#define V_CPL5RXFULL(x) ((x) << S_CPL5RXFULL)
+#define F_CPL5RXFULL    V_CPL5RXFULL(1U)
+
+#define S_PLD2XRXVALID    23
+#define V_PLD2XRXVALID(x) ((x) << S_PLD2XRXVALID)
+#define F_PLD2XRXVALID    V_PLD2XRXVALID(1U)
+
+#define S_DDPSTATE    16
+#define M_DDPSTATE    0x1fU
+#define V_DDPSTATE(x) ((x) << S_DDPSTATE)
+#define G_DDPSTATE(x) (((x) >> S_DDPSTATE) & M_DDPSTATE)
+
+#define S_DDPMSGCODE    12
+#define M_DDPMSGCODE    0xfU
+#define V_DDPMSGCODE(x) ((x) << S_DDPMSGCODE)
+#define G_DDPMSGCODE(x) (((x) >> S_DDPMSGCODE) & M_DDPMSGCODE)
+
+#define S_CPL5SOCPCNT    8
+#define M_CPL5SOCPCNT    0xfU
+#define V_CPL5SOCPCNT(x) ((x) << S_CPL5SOCPCNT)
+#define G_CPL5SOCPCNT(x) (((x) >> S_CPL5SOCPCNT) & M_CPL5SOCPCNT)
+
+#define S_PLDRXZEROPCNT    4
+#define M_PLDRXZEROPCNT    0xfU
+#define V_PLDRXZEROPCNT(x) ((x) << S_PLDRXZEROPCNT)
+#define G_PLDRXZEROPCNT(x) (((x) >> S_PLDRXZEROPCNT) & M_PLDRXZEROPCNT)
+
+#define S_TXFRMERR2    3
+#define V_TXFRMERR2(x) ((x) << S_TXFRMERR2)
+#define F_TXFRMERR2    V_TXFRMERR2(1U)
+
+#define S_TXFRMERR1    2
+#define V_TXFRMERR1(x) ((x) << S_TXFRMERR1)
+#define F_TXFRMERR1    V_TXFRMERR1(1U)
+
+#define S_TXVALID2X    1
+#define V_TXVALID2X(x) ((x) << S_TXVALID2X)
+#define F_TXVALID2X    V_TXVALID2X(1U)
+
+#define S_TXFULL2X    0
+#define V_TXFULL2X(x) ((x) << S_TXFULL2X)
+#define F_TXFULL2X    V_TXFULL2X(1U)
+
+#define A_TP_DBG_CSIDE_DISP1 0x23b
+#define A_TP_DBG_CSIDE_DDP0 0x23c
+
+#define S_DDPMSGLATEST7    28
+#define M_DDPMSGLATEST7    0xfU
+#define V_DDPMSGLATEST7(x) ((x) << S_DDPMSGLATEST7)
+#define G_DDPMSGLATEST7(x) (((x) >> S_DDPMSGLATEST7) & M_DDPMSGLATEST7)
+
+#define S_DDPMSGLATEST6    24
+#define M_DDPMSGLATEST6    0xfU
+#define V_DDPMSGLATEST6(x) ((x) << S_DDPMSGLATEST6)
+#define G_DDPMSGLATEST6(x) (((x) >> S_DDPMSGLATEST6) & M_DDPMSGLATEST6)
+
+#define S_DDPMSGLATEST5    20
+#define M_DDPMSGLATEST5    0xfU
+#define V_DDPMSGLATEST5(x) ((x) << S_DDPMSGLATEST5)
+#define G_DDPMSGLATEST5(x) (((x) >> S_DDPMSGLATEST5) & M_DDPMSGLATEST5)
+
+#define S_DDPMSGLATEST4    16
+#define M_DDPMSGLATEST4    0xfU
+#define V_DDPMSGLATEST4(x) ((x) << S_DDPMSGLATEST4)
+#define G_DDPMSGLATEST4(x) (((x) >> S_DDPMSGLATEST4) & M_DDPMSGLATEST4)
+
+#define S_DDPMSGLATEST3    12
+#define M_DDPMSGLATEST3    0xfU
+#define V_DDPMSGLATEST3(x) ((x) << S_DDPMSGLATEST3)
+#define G_DDPMSGLATEST3(x) (((x) >> S_DDPMSGLATEST3) & M_DDPMSGLATEST3)
+
+#define S_DDPMSGLATEST2    8
+#define M_DDPMSGLATEST2    0xfU
+#define V_DDPMSGLATEST2(x) ((x) << S_DDPMSGLATEST2)
+#define G_DDPMSGLATEST2(x) (((x) >> S_DDPMSGLATEST2) & M_DDPMSGLATEST2)
+
+#define S_DDPMSGLATEST1    4
+#define M_DDPMSGLATEST1    0xfU
+#define V_DDPMSGLATEST1(x) ((x) << S_DDPMSGLATEST1)
+#define G_DDPMSGLATEST1(x) (((x) >> S_DDPMSGLATEST1) & M_DDPMSGLATEST1)
+
+#define S_DDPMSGLATEST0    0
+#define M_DDPMSGLATEST0    0xfU
+#define V_DDPMSGLATEST0(x) ((x) << S_DDPMSGLATEST0)
+#define G_DDPMSGLATEST0(x) (((x) >> S_DDPMSGLATEST0) & M_DDPMSGLATEST0)
+
+#define A_TP_DBG_CSIDE_DDP1 0x23d
+#define A_TP_DBG_CSIDE_FRM 0x23e
+
+#define S_CRX2XERROR    28
+#define M_CRX2XERROR    0xfU
+#define V_CRX2XERROR(x) ((x) << S_CRX2XERROR)
+#define G_CRX2XERROR(x) (((x) >> S_CRX2XERROR) & M_CRX2XERROR)
+
+#define S_CPLDTX2XERROR    24
+#define M_CPLDTX2XERROR    0xfU
+#define V_CPLDTX2XERROR(x) ((x) << S_CPLDTX2XERROR)
+#define G_CPLDTX2XERROR(x) (((x) >> S_CPLDTX2XERROR) & M_CPLDTX2XERROR)
+
+#define S_CTXERROR    22
+#define M_CTXERROR    0x3U
+#define V_CTXERROR(x) ((x) << S_CTXERROR)
+#define G_CTXERROR(x) (((x) >> S_CTXERROR) & M_CTXERROR)
+
+#define S_CPLDRXERROR    20
+#define M_CPLDRXERROR    0x3U
+#define V_CPLDRXERROR(x) ((x) << S_CPLDRXERROR)
+#define G_CPLDRXERROR(x) (((x) >> S_CPLDRXERROR) & M_CPLDRXERROR)
+
+#define S_CPLRXERROR    18
+#define M_CPLRXERROR    0x3U
+#define V_CPLRXERROR(x) ((x) << S_CPLRXERROR)
+#define G_CPLRXERROR(x) (((x) >> S_CPLRXERROR) & M_CPLRXERROR)
+
+#define S_CPLTXERROR    16
+#define M_CPLTXERROR    0x3U
+#define V_CPLTXERROR(x) ((x) << S_CPLTXERROR)
+#define G_CPLTXERROR(x) (((x) >> S_CPLTXERROR) & M_CPLTXERROR)
+
+#define S_CPRSERROR    0
+#define M_CPRSERROR    0xfU
+#define V_CPRSERROR(x) ((x) << S_CPRSERROR)
+#define G_CPRSERROR(x) (((x) >> S_CPRSERROR) & M_CPRSERROR)
+
+#define A_TP_DBG_CSIDE_INT 0x23f
+
+#define S_CRXVALID2X    28
+#define M_CRXVALID2X    0xfU
+#define V_CRXVALID2X(x) ((x) << S_CRXVALID2X)
+#define G_CRXVALID2X(x) (((x) >> S_CRXVALID2X) & M_CRXVALID2X)
+
+#define S_CRXAFULL2X    24
+#define M_CRXAFULL2X    0xfU
+#define V_CRXAFULL2X(x) ((x) << S_CRXAFULL2X)
+#define G_CRXAFULL2X(x) (((x) >> S_CRXAFULL2X) & M_CRXAFULL2X)
+
+#define S_CTXVALID2X    22
+#define M_CTXVALID2X    0x3U
+#define V_CTXVALID2X(x) ((x) << S_CTXVALID2X)
+#define G_CTXVALID2X(x) (((x) >> S_CTXVALID2X) & M_CTXVALID2X)
+
+#define S_CTXAFULL2X    20
+#define M_CTXAFULL2X    0x3U
+#define V_CTXAFULL2X(x) ((x) << S_CTXAFULL2X)
+#define G_CTXAFULL2X(x) (((x) >> S_CTXAFULL2X) & M_CTXAFULL2X)
+
+#define S_PLD2X_RXVALID    18
+#define M_PLD2X_RXVALID    0x3U
+#define V_PLD2X_RXVALID(x) ((x) << S_PLD2X_RXVALID)
+#define G_PLD2X_RXVALID(x) (((x) >> S_PLD2X_RXVALID) & M_PLD2X_RXVALID)
+
+#define S_PLD2X_RXAFULL    16
+#define M_PLD2X_RXAFULL    0x3U
+#define V_PLD2X_RXAFULL(x) ((x) << S_PLD2X_RXAFULL)
+#define G_PLD2X_RXAFULL(x) (((x) >> S_PLD2X_RXAFULL) & M_PLD2X_RXAFULL)
+
+#define S_CSIDE_DDP_VALID    14
+#define M_CSIDE_DDP_VALID    0x3U
+#define V_CSIDE_DDP_VALID(x) ((x) << S_CSIDE_DDP_VALID)
+#define G_CSIDE_DDP_VALID(x) (((x) >> S_CSIDE_DDP_VALID) & M_CSIDE_DDP_VALID)
+
+#define S_DDP_AFULL    12
+#define M_DDP_AFULL    0x3U
+#define V_DDP_AFULL(x) ((x) << S_DDP_AFULL)
+#define G_DDP_AFULL(x) (((x) >> S_DDP_AFULL) & M_DDP_AFULL)
+
+#define S_TRC_RXVALID    11
+#define V_TRC_RXVALID(x) ((x) << S_TRC_RXVALID)
+#define F_TRC_RXVALID    V_TRC_RXVALID(1U)
+
+#define S_TRC_RXFULL    10
+#define V_TRC_RXFULL(x) ((x) << S_TRC_RXFULL)
+#define F_TRC_RXFULL    V_TRC_RXFULL(1U)
+
+#define S_CPL5_TXVALID    9
+#define V_CPL5_TXVALID(x) ((x) << S_CPL5_TXVALID)
+#define F_CPL5_TXVALID    V_CPL5_TXVALID(1U)
+
+#define S_CPL5_TXFULL    8
+#define V_CPL5_TXFULL(x) ((x) << S_CPL5_TXFULL)
+#define F_CPL5_TXFULL    V_CPL5_TXFULL(1U)
+
+#define S_PLD2X_TXVALID    4
+#define M_PLD2X_TXVALID    0xfU
+#define V_PLD2X_TXVALID(x) ((x) << S_PLD2X_TXVALID)
+#define G_PLD2X_TXVALID(x) (((x) >> S_PLD2X_TXVALID) & M_PLD2X_TXVALID)
+
+#define S_PLD2X_TXAFULL    0
+#define M_PLD2X_TXAFULL    0xfU
+#define V_PLD2X_TXAFULL(x) ((x) << S_PLD2X_TXAFULL)
+#define G_PLD2X_TXAFULL(x) (((x) >> S_PLD2X_TXAFULL) & M_PLD2X_TXAFULL)
+
+#define A_TP_CHDR_CONFIG 0x240
+
+#define S_CH1HIGH    24
+#define M_CH1HIGH    0xffU
+#define V_CH1HIGH(x) ((x) << S_CH1HIGH)
+#define G_CH1HIGH(x) (((x) >> S_CH1HIGH) & M_CH1HIGH)
+
+#define S_CH1LOW    16
+#define M_CH1LOW    0xffU
+#define V_CH1LOW(x) ((x) << S_CH1LOW)
+#define G_CH1LOW(x) (((x) >> S_CH1LOW) & M_CH1LOW)
+
+#define S_CH0HIGH    8
+#define M_CH0HIGH    0xffU
+#define V_CH0HIGH(x) ((x) << S_CH0HIGH)
+#define G_CH0HIGH(x) (((x) >> S_CH0HIGH) & M_CH0HIGH)
+
+#define S_CH0LOW    0
+#define M_CH0LOW    0xffU
+#define V_CH0LOW(x) ((x) << S_CH0LOW)
+#define G_CH0LOW(x) (((x) >> S_CH0LOW) & M_CH0LOW)
+
+#define A_TP_UTRN_CONFIG 0x241
+
+#define S_CH2FIFOLIMIT    16
+#define M_CH2FIFOLIMIT    0xffU
+#define V_CH2FIFOLIMIT(x) ((x) << S_CH2FIFOLIMIT)
+#define G_CH2FIFOLIMIT(x) (((x) >> S_CH2FIFOLIMIT) & M_CH2FIFOLIMIT)
+
+#define S_CH1FIFOLIMIT    8
+#define M_CH1FIFOLIMIT    0xffU
+#define V_CH1FIFOLIMIT(x) ((x) << S_CH1FIFOLIMIT)
+#define G_CH1FIFOLIMIT(x) (((x) >> S_CH1FIFOLIMIT) & M_CH1FIFOLIMIT)
+
+#define S_CH0FIFOLIMIT    0
+#define M_CH0FIFOLIMIT    0xffU
+#define V_CH0FIFOLIMIT(x) ((x) << S_CH0FIFOLIMIT)
+#define G_CH0FIFOLIMIT(x) (((x) >> S_CH0FIFOLIMIT) & M_CH0FIFOLIMIT)
+
+#define A_TP_CDSP_CONFIG 0x242
+
+#define S_WRITEZEROEN    4
+#define V_WRITEZEROEN(x) ((x) << S_WRITEZEROEN)
+#define F_WRITEZEROEN    V_WRITEZEROEN(1U)
+
+#define S_WRITEZEROOP    0
+#define M_WRITEZEROOP    0xfU
+#define V_WRITEZEROOP(x) ((x) << S_WRITEZEROOP)
+#define G_WRITEZEROOP(x) (((x) >> S_WRITEZEROOP) & M_WRITEZEROOP)
+
+#define S_STARTSKIPPLD    7
+#define V_STARTSKIPPLD(x) ((x) << S_STARTSKIPPLD)
+#define F_STARTSKIPPLD    V_STARTSKIPPLD(1U)
+
+#define S_ATOMICCMDEN    5
+#define V_ATOMICCMDEN(x) ((x) << S_ATOMICCMDEN)
+#define F_ATOMICCMDEN    V_ATOMICCMDEN(1U)
+
+#define A_TP_CSPI_POWER 0x243
+
+#define S_GATECHNTX3    11
+#define V_GATECHNTX3(x) ((x) << S_GATECHNTX3)
+#define F_GATECHNTX3    V_GATECHNTX3(1U)
+
+#define S_GATECHNTX2    10
+#define V_GATECHNTX2(x) ((x) << S_GATECHNTX2)
+#define F_GATECHNTX2    V_GATECHNTX2(1U)
+
+#define S_GATECHNTX1    9
+#define V_GATECHNTX1(x) ((x) << S_GATECHNTX1)
+#define F_GATECHNTX1    V_GATECHNTX1(1U)
+
+#define S_GATECHNTX0    8
+#define V_GATECHNTX0(x) ((x) << S_GATECHNTX0)
+#define F_GATECHNTX0    V_GATECHNTX0(1U)
+
+#define S_GATECHNRX1    7
+#define V_GATECHNRX1(x) ((x) << S_GATECHNRX1)
+#define F_GATECHNRX1    V_GATECHNRX1(1U)
+
+#define S_GATECHNRX0    6
+#define V_GATECHNRX0(x) ((x) << S_GATECHNRX0)
+#define F_GATECHNRX0    V_GATECHNRX0(1U)
+
+#define S_SLEEPRDYUTRN    4
+#define V_SLEEPRDYUTRN(x) ((x) << S_SLEEPRDYUTRN)
+#define F_SLEEPRDYUTRN    V_SLEEPRDYUTRN(1U)
+
+#define S_SLEEPREQUTRN    0
+#define V_SLEEPREQUTRN(x) ((x) << S_SLEEPREQUTRN)
+#define F_SLEEPREQUTRN    V_SLEEPREQUTRN(1U)
+
+#define A_TP_TRC_CONFIG 0x244
+
+#define S_TRCRR    1
+#define V_TRCRR(x) ((x) << S_TRCRR)
+#define F_TRCRR    V_TRCRR(1U)
+
+#define S_TRCCH    0
+#define V_TRCCH(x) ((x) << S_TRCCH)
+#define F_TRCCH    V_TRCCH(1U)
+
+#define A_TP_TAG_CONFIG 0x245
+
+#define S_ETAGTYPE    16
+#define M_ETAGTYPE    0xffffU
+#define V_ETAGTYPE(x) ((x) << S_ETAGTYPE)
+#define G_ETAGTYPE(x) (((x) >> S_ETAGTYPE) & M_ETAGTYPE)
+
+#define A_TP_DBG_CSIDE_PRS 0x246
+
+#define S_CPRSSTATE3    24
+#define M_CPRSSTATE3    0x7U
+#define V_CPRSSTATE3(x) ((x) << S_CPRSSTATE3)
+#define G_CPRSSTATE3(x) (((x) >> S_CPRSSTATE3) & M_CPRSSTATE3)
+
+#define S_CPRSSTATE2    16
+#define M_CPRSSTATE2    0x7U
+#define V_CPRSSTATE2(x) ((x) << S_CPRSSTATE2)
+#define G_CPRSSTATE2(x) (((x) >> S_CPRSSTATE2) & M_CPRSSTATE2)
+
+#define S_CPRSSTATE1    8
+#define M_CPRSSTATE1    0x7U
+#define V_CPRSSTATE1(x) ((x) << S_CPRSSTATE1)
+#define G_CPRSSTATE1(x) (((x) >> S_CPRSSTATE1) & M_CPRSSTATE1)
+
+#define S_CPRSSTATE0    0
+#define M_CPRSSTATE0    0x7U
+#define V_CPRSSTATE0(x) ((x) << S_CPRSSTATE0)
+#define G_CPRSSTATE0(x) (((x) >> S_CPRSSTATE0) & M_CPRSSTATE0)
+
+#define S_C4TUPBUSY3    31
+#define V_C4TUPBUSY3(x) ((x) << S_C4TUPBUSY3)
+#define F_C4TUPBUSY3    V_C4TUPBUSY3(1U)
+
+#define S_CDBVALID3    30
+#define V_CDBVALID3(x) ((x) << S_CDBVALID3)
+#define F_CDBVALID3    V_CDBVALID3(1U)
+
+#define S_CRXVALID3    29
+#define V_CRXVALID3(x) ((x) << S_CRXVALID3)
+#define F_CRXVALID3    V_CRXVALID3(1U)
+
+#define S_CRXFULL3    28
+#define V_CRXFULL3(x) ((x) << S_CRXFULL3)
+#define F_CRXFULL3    V_CRXFULL3(1U)
+
+#define S_C4TUPBUSY2    23
+#define V_C4TUPBUSY2(x) ((x) << S_C4TUPBUSY2)
+#define F_C4TUPBUSY2    V_C4TUPBUSY2(1U)
+
+#define S_CDBVALID2    22
+#define V_CDBVALID2(x) ((x) << S_CDBVALID2)
+#define F_CDBVALID2    V_CDBVALID2(1U)
+
+#define S_CRXVALID2    21
+#define V_CRXVALID2(x) ((x) << S_CRXVALID2)
+#define F_CRXVALID2    V_CRXVALID2(1U)
+
+#define S_CRXFULL2    20
+#define V_CRXFULL2(x) ((x) << S_CRXFULL2)
+#define F_CRXFULL2    V_CRXFULL2(1U)
+
+#define S_C4TUPBUSY1    15
+#define V_C4TUPBUSY1(x) ((x) << S_C4TUPBUSY1)
+#define F_C4TUPBUSY1    V_C4TUPBUSY1(1U)
+
+#define S_CDBVALID1    14
+#define V_CDBVALID1(x) ((x) << S_CDBVALID1)
+#define F_CDBVALID1    V_CDBVALID1(1U)
+
+#define S_CRXVALID1    13
+#define V_CRXVALID1(x) ((x) << S_CRXVALID1)
+#define F_CRXVALID1    V_CRXVALID1(1U)
+
+#define S_CRXFULL1    12
+#define V_CRXFULL1(x) ((x) << S_CRXFULL1)
+#define F_CRXFULL1    V_CRXFULL1(1U)
+
+#define S_C4TUPBUSY0    7
+#define V_C4TUPBUSY0(x) ((x) << S_C4TUPBUSY0)
+#define F_C4TUPBUSY0    V_C4TUPBUSY0(1U)
+
+#define S_CDBVALID0    6
+#define V_CDBVALID0(x) ((x) << S_CDBVALID0)
+#define F_CDBVALID0    V_CDBVALID0(1U)
+
+#define S_CRXVALID0    5
+#define V_CRXVALID0(x) ((x) << S_CRXVALID0)
+#define F_CRXVALID0    V_CRXVALID0(1U)
+
+#define S_CRXFULL0    4
+#define V_CRXFULL0(x) ((x) << S_CRXFULL0)
+#define F_CRXFULL0    V_CRXFULL0(1U)
+
+#define A_TP_DBG_CSIDE_DEMUX 0x247
+
+#define S_CALLDONE    28
+#define M_CALLDONE    0xfU
+#define V_CALLDONE(x) ((x) << S_CALLDONE)
+#define G_CALLDONE(x) (((x) >> S_CALLDONE) & M_CALLDONE)
+
+#define S_CTCPL5DONE    24
+#define M_CTCPL5DONE    0xfU
+#define V_CTCPL5DONE(x) ((x) << S_CTCPL5DONE)
+#define G_CTCPL5DONE(x) (((x) >> S_CTCPL5DONE) & M_CTCPL5DONE)
+
+#define S_CTXZEROPDONE    20
+#define M_CTXZEROPDONE    0xfU
+#define V_CTXZEROPDONE(x) ((x) << S_CTXZEROPDONE)
+#define G_CTXZEROPDONE(x) (((x) >> S_CTXZEROPDONE) & M_CTXZEROPDONE)
+
+#define S_CPLDDONE    16
+#define M_CPLDDONE    0xfU
+#define V_CPLDDONE(x) ((x) << S_CPLDDONE)
+#define G_CPLDDONE(x) (((x) >> S_CPLDDONE) & M_CPLDDONE)
+
+#define S_CTTCPOPDONE    12
+#define M_CTTCPOPDONE    0xfU
+#define V_CTTCPOPDONE(x) ((x) << S_CTTCPOPDONE)
+#define G_CTTCPOPDONE(x) (((x) >> S_CTTCPOPDONE) & M_CTTCPOPDONE)
+
+#define S_CDBDONE    8
+#define M_CDBDONE    0xfU
+#define V_CDBDONE(x) ((x) << S_CDBDONE)
+#define G_CDBDONE(x) (((x) >> S_CDBDONE) & M_CDBDONE)
+
+#define S_CISSFIFODONE    4
+#define M_CISSFIFODONE    0xfU
+#define V_CISSFIFODONE(x) ((x) << S_CISSFIFODONE)
+#define G_CISSFIFODONE(x) (((x) >> S_CISSFIFODONE) & M_CISSFIFODONE)
+
+#define S_CTXPKTCSUMDONE    0
+#define M_CTXPKTCSUMDONE    0xfU
+#define V_CTXPKTCSUMDONE(x) ((x) << S_CTXPKTCSUMDONE)
+#define G_CTXPKTCSUMDONE(x) (((x) >> S_CTXPKTCSUMDONE) & M_CTXPKTCSUMDONE)
+
+#define S_CARBVALID    28
+#define M_CARBVALID    0xfU
+#define V_CARBVALID(x) ((x) << S_CARBVALID)
+#define G_CARBVALID(x) (((x) >> S_CARBVALID) & M_CARBVALID)
+
+#define S_CCPL5DONE    24
+#define M_CCPL5DONE    0xfU
+#define V_CCPL5DONE(x) ((x) << S_CCPL5DONE)
+#define G_CCPL5DONE(x) (((x) >> S_CCPL5DONE) & M_CCPL5DONE)
+
+#define S_CTCPOPDONE    12
+#define M_CTCPOPDONE    0xfU
+#define V_CTCPOPDONE(x) ((x) << S_CTCPOPDONE)
+#define G_CTCPOPDONE(x) (((x) >> S_CTCPOPDONE) & M_CTCPOPDONE)
+
+#define A_TP_DBG_CSIDE_ARBIT 0x248
+
+#define S_CPLVALID3    31
+#define V_CPLVALID3(x) ((x) << S_CPLVALID3)
+#define F_CPLVALID3    V_CPLVALID3(1U)
+
+#define S_PLDVALID3    30
+#define V_PLDVALID3(x) ((x) << S_PLDVALID3)
+#define F_PLDVALID3    V_PLDVALID3(1U)
+
+#define S_CRCVALID3    29
+#define V_CRCVALID3(x) ((x) << S_CRCVALID3)
+#define F_CRCVALID3    V_CRCVALID3(1U)
+
+#define S_ISSVALID3    28
+#define V_ISSVALID3(x) ((x) << S_ISSVALID3)
+#define F_ISSVALID3    V_ISSVALID3(1U)
+
+#define S_DBVALID3    27
+#define V_DBVALID3(x) ((x) << S_DBVALID3)
+#define F_DBVALID3    V_DBVALID3(1U)
+
+#define S_CHKVALID3    26
+#define V_CHKVALID3(x) ((x) << S_CHKVALID3)
+#define F_CHKVALID3    V_CHKVALID3(1U)
+
+#define S_ZRPVALID3    25
+#define V_ZRPVALID3(x) ((x) << S_ZRPVALID3)
+#define F_ZRPVALID3    V_ZRPVALID3(1U)
+
+#define S_ERRVALID3    24
+#define V_ERRVALID3(x) ((x) << S_ERRVALID3)
+#define F_ERRVALID3    V_ERRVALID3(1U)
+
+#define S_CPLVALID2    23
+#define V_CPLVALID2(x) ((x) << S_CPLVALID2)
+#define F_CPLVALID2    V_CPLVALID2(1U)
+
+#define S_PLDVALID2    22
+#define V_PLDVALID2(x) ((x) << S_PLDVALID2)
+#define F_PLDVALID2    V_PLDVALID2(1U)
+
+#define S_CRCVALID2    21
+#define V_CRCVALID2(x) ((x) << S_CRCVALID2)
+#define F_CRCVALID2    V_CRCVALID2(1U)
+
+#define S_ISSVALID2    20
+#define V_ISSVALID2(x) ((x) << S_ISSVALID2)
+#define F_ISSVALID2    V_ISSVALID2(1U)
+
+#define S_DBVALID2    19
+#define V_DBVALID2(x) ((x) << S_DBVALID2)
+#define F_DBVALID2    V_DBVALID2(1U)
+
+#define S_CHKVALID2    18
+#define V_CHKVALID2(x) ((x) << S_CHKVALID2)
+#define F_CHKVALID2    V_CHKVALID2(1U)
+
+#define S_ZRPVALID2    17
+#define V_ZRPVALID2(x) ((x) << S_ZRPVALID2)
+#define F_ZRPVALID2    V_ZRPVALID2(1U)
+
+#define S_ERRVALID2    16
+#define V_ERRVALID2(x) ((x) << S_ERRVALID2)
+#define F_ERRVALID2    V_ERRVALID2(1U)
+
+#define S_CPLVALID1    15
+#define V_CPLVALID1(x) ((x) << S_CPLVALID1)
+#define F_CPLVALID1    V_CPLVALID1(1U)
+
+#define S_PLDVALID1    14
+#define V_PLDVALID1(x) ((x) << S_PLDVALID1)
+#define F_PLDVALID1    V_PLDVALID1(1U)
+
+#define S_CRCVALID1    13
+#define V_CRCVALID1(x) ((x) << S_CRCVALID1)
+#define F_CRCVALID1    V_CRCVALID1(1U)
+
+#define S_ISSVALID1    12
+#define V_ISSVALID1(x) ((x) << S_ISSVALID1)
+#define F_ISSVALID1    V_ISSVALID1(1U)
+
+#define S_DBVALID1    11
+#define V_DBVALID1(x) ((x) << S_DBVALID1)
+#define F_DBVALID1    V_DBVALID1(1U)
+
+#define S_CHKVALID1    10
+#define V_CHKVALID1(x) ((x) << S_CHKVALID1)
+#define F_CHKVALID1    V_CHKVALID1(1U)
+
+#define S_ZRPVALID1    9
+#define V_ZRPVALID1(x) ((x) << S_ZRPVALID1)
+#define F_ZRPVALID1    V_ZRPVALID1(1U)
+
+#define S_ERRVALID1    8
+#define V_ERRVALID1(x) ((x) << S_ERRVALID1)
+#define F_ERRVALID1    V_ERRVALID1(1U)
+
+#define S_CPLVALID0    7
+#define V_CPLVALID0(x) ((x) << S_CPLVALID0)
+#define F_CPLVALID0    V_CPLVALID0(1U)
+
+#define S_PLDVALID0    6
+#define V_PLDVALID0(x) ((x) << S_PLDVALID0)
+#define F_PLDVALID0    V_PLDVALID0(1U)
+
+#define S_CRCVALID0    5
+#define V_CRCVALID0(x) ((x) << S_CRCVALID0)
+#define F_CRCVALID0    V_CRCVALID0(1U)
+
+#define S_ISSVALID0    4
+#define V_ISSVALID0(x) ((x) << S_ISSVALID0)
+#define F_ISSVALID0    V_ISSVALID0(1U)
+
+#define S_DBVALID0    3
+#define V_DBVALID0(x) ((x) << S_DBVALID0)
+#define F_DBVALID0    V_DBVALID0(1U)
+
+#define S_CHKVALID0    2
+#define V_CHKVALID0(x) ((x) << S_CHKVALID0)
+#define F_CHKVALID0    V_CHKVALID0(1U)
+
+#define S_ZRPVALID0    1
+#define V_ZRPVALID0(x) ((x) << S_ZRPVALID0)
+#define F_ZRPVALID0    V_ZRPVALID0(1U)
+
+#define S_ERRVALID0    0
+#define V_ERRVALID0(x) ((x) << S_ERRVALID0)
+#define F_ERRVALID0    V_ERRVALID0(1U)
+
+#define A_TP_FIFO_CONFIG 0x8c0
+
+#define S_CH1_OUTPUT    27
+#define M_CH1_OUTPUT    0x1fU
+#define V_CH1_OUTPUT(x) ((x) << S_CH1_OUTPUT)
+#define G_CH1_OUTPUT(x) (((x) >> S_CH1_OUTPUT) & M_CH1_OUTPUT)
+
+#define S_CH2_OUTPUT    22
+#define M_CH2_OUTPUT    0x1fU
+#define V_CH2_OUTPUT(x) ((x) << S_CH2_OUTPUT)
+#define G_CH2_OUTPUT(x) (((x) >> S_CH2_OUTPUT) & M_CH2_OUTPUT)
+
+#define S_STROBE1    16
+#define V_STROBE1(x) ((x) << S_STROBE1)
+#define F_STROBE1    V_STROBE1(1U)
+
+#define S_CH1_INPUT    11
+#define M_CH1_INPUT    0x1fU
+#define V_CH1_INPUT(x) ((x) << S_CH1_INPUT)
+#define G_CH1_INPUT(x) (((x) >> S_CH1_INPUT) & M_CH1_INPUT)
+
+#define S_CH2_INPUT    6
+#define M_CH2_INPUT    0x1fU
+#define V_CH2_INPUT(x) ((x) << S_CH2_INPUT)
+#define G_CH2_INPUT(x) (((x) >> S_CH2_INPUT) & M_CH2_INPUT)
+
+#define S_CH3_INPUT    1
+#define M_CH3_INPUT    0x1fU
+#define V_CH3_INPUT(x) ((x) << S_CH3_INPUT)
+#define G_CH3_INPUT(x) (((x) >> S_CH3_INPUT) & M_CH3_INPUT)
+
+#define S_STROBE0    0
+#define V_STROBE0(x) ((x) << S_STROBE0)
+#define F_STROBE0    V_STROBE0(1U)
+
+#define A_TP_MIB_MAC_IN_ERR_0 0x0
+#define A_TP_MIB_MAC_IN_ERR_1 0x1
+#define A_TP_MIB_MAC_IN_ERR_2 0x2
+#define A_TP_MIB_MAC_IN_ERR_3 0x3
+#define A_TP_MIB_HDR_IN_ERR_0 0x4
+#define A_TP_MIB_HDR_IN_ERR_1 0x5
+#define A_TP_MIB_HDR_IN_ERR_2 0x6
+#define A_TP_MIB_HDR_IN_ERR_3 0x7
+#define A_TP_MIB_TCP_IN_ERR_0 0x8
+#define A_TP_MIB_TCP_IN_ERR_1 0x9
+#define A_TP_MIB_TCP_IN_ERR_2 0xa
+#define A_TP_MIB_TCP_IN_ERR_3 0xb
+#define A_TP_MIB_TCP_OUT_RST 0xc
+#define A_TP_MIB_TCP_IN_SEG_HI 0x10
+#define A_TP_MIB_TCP_IN_SEG_LO 0x11
+#define A_TP_MIB_TCP_OUT_SEG_HI 0x12
+#define A_TP_MIB_TCP_OUT_SEG_LO 0x13
+#define A_TP_MIB_TCP_RXT_SEG_HI 0x14
+#define A_TP_MIB_TCP_RXT_SEG_LO 0x15
+#define A_TP_MIB_TNL_CNG_DROP_0 0x18
+#define A_TP_MIB_TNL_CNG_DROP_1 0x19
+#define A_TP_MIB_TNL_CNG_DROP_2 0x1a
+#define A_TP_MIB_TNL_CNG_DROP_3 0x1b
+#define A_TP_MIB_OFD_CHN_DROP_0 0x1c
+#define A_TP_MIB_OFD_CHN_DROP_1 0x1d
+#define A_TP_MIB_OFD_CHN_DROP_2 0x1e
+#define A_TP_MIB_OFD_CHN_DROP_3 0x1f
+#define A_TP_MIB_TNL_OUT_PKT_0 0x20
+#define A_TP_MIB_TNL_OUT_PKT_1 0x21
+#define A_TP_MIB_TNL_OUT_PKT_2 0x22
+#define A_TP_MIB_TNL_OUT_PKT_3 0x23
+#define A_TP_MIB_TNL_IN_PKT_0 0x24
+#define A_TP_MIB_TNL_IN_PKT_1 0x25
+#define A_TP_MIB_TNL_IN_PKT_2 0x26
+#define A_TP_MIB_TNL_IN_PKT_3 0x27
+#define A_TP_MIB_TCP_V6IN_ERR_0 0x28
+#define A_TP_MIB_TCP_V6IN_ERR_1 0x29
+#define A_TP_MIB_TCP_V6IN_ERR_2 0x2a
+#define A_TP_MIB_TCP_V6IN_ERR_3 0x2b
+#define A_TP_MIB_TCP_V6OUT_RST 0x2c
+#define A_TP_MIB_TCP_V6IN_SEG_HI 0x30
+#define A_TP_MIB_TCP_V6IN_SEG_LO 0x31
+#define A_TP_MIB_TCP_V6OUT_SEG_HI 0x32
+#define A_TP_MIB_TCP_V6OUT_SEG_LO 0x33
+#define A_TP_MIB_TCP_V6RXT_SEG_HI 0x34
+#define A_TP_MIB_TCP_V6RXT_SEG_LO 0x35
+#define A_TP_MIB_OFD_ARP_DROP 0x36
+#define A_TP_MIB_OFD_DFR_DROP 0x37
+#define A_TP_MIB_CPL_IN_REQ_0 0x38
+#define A_TP_MIB_CPL_IN_REQ_1 0x39
+#define A_TP_MIB_CPL_IN_REQ_2 0x3a
+#define A_TP_MIB_CPL_IN_REQ_3 0x3b
+#define A_TP_MIB_CPL_OUT_RSP_0 0x3c
+#define A_TP_MIB_CPL_OUT_RSP_1 0x3d
+#define A_TP_MIB_CPL_OUT_RSP_2 0x3e
+#define A_TP_MIB_CPL_OUT_RSP_3 0x3f
+#define A_TP_MIB_TNL_LPBK_0 0x40
+#define A_TP_MIB_TNL_LPBK_1 0x41
+#define A_TP_MIB_TNL_LPBK_2 0x42
+#define A_TP_MIB_TNL_LPBK_3 0x43
+#define A_TP_MIB_TNL_DROP_0 0x44
+#define A_TP_MIB_TNL_DROP_1 0x45
+#define A_TP_MIB_TNL_DROP_2 0x46
+#define A_TP_MIB_TNL_DROP_3 0x47
+#define A_TP_MIB_FCOE_DDP_0 0x48
+#define A_TP_MIB_FCOE_DDP_1 0x49
+#define A_TP_MIB_FCOE_DDP_2 0x4a
+#define A_TP_MIB_FCOE_DDP_3 0x4b
+#define A_TP_MIB_FCOE_DROP_0 0x4c
+#define A_TP_MIB_FCOE_DROP_1 0x4d
+#define A_TP_MIB_FCOE_DROP_2 0x4e
+#define A_TP_MIB_FCOE_DROP_3 0x4f
+#define A_TP_MIB_FCOE_BYTE_0_HI 0x50
+#define A_TP_MIB_FCOE_BYTE_0_LO 0x51
+#define A_TP_MIB_FCOE_BYTE_1_HI 0x52
+#define A_TP_MIB_FCOE_BYTE_1_LO 0x53
+#define A_TP_MIB_FCOE_BYTE_2_HI 0x54
+#define A_TP_MIB_FCOE_BYTE_2_LO 0x55
+#define A_TP_MIB_FCOE_BYTE_3_HI 0x56
+#define A_TP_MIB_FCOE_BYTE_3_LO 0x57
+#define A_TP_MIB_OFD_VLN_DROP_0 0x58
+#define A_TP_MIB_OFD_VLN_DROP_1 0x59
+#define A_TP_MIB_OFD_VLN_DROP_2 0x5a
+#define A_TP_MIB_OFD_VLN_DROP_3 0x5b
+#define A_TP_MIB_USM_PKTS 0x5c
+#define A_TP_MIB_USM_DROP 0x5d
+#define A_TP_MIB_USM_BYTES_HI 0x5e
+#define A_TP_MIB_USM_BYTES_LO 0x5f
+#define A_TP_MIB_TID_DEL 0x60
+#define A_TP_MIB_TID_INV 0x61
+#define A_TP_MIB_TID_ACT 0x62
+#define A_TP_MIB_TID_PAS 0x63
+#define A_TP_MIB_RQE_DFR_PKT 0x64
+#define A_TP_MIB_RQE_DFR_MOD 0x65
+#define A_TP_MIB_CPL_OUT_ERR_0 0x68
+#define A_TP_MIB_CPL_OUT_ERR_1 0x69
+#define A_TP_MIB_CPL_OUT_ERR_2 0x6a
+#define A_TP_MIB_CPL_OUT_ERR_3 0x6b
+#define A_TP_MIB_ENG_LINE_0 0x6c
+#define A_TP_MIB_ENG_LINE_1 0x6d
+#define A_TP_MIB_ENG_LINE_2 0x6e
+#define A_TP_MIB_ENG_LINE_3 0x6f
+
+/* registers for module ULP_TX */
+#define ULP_TX_BASE_ADDR 0x8dc0
+
+#define A_ULP_TX_CONFIG 0x8dc0
+
+#define S_STAG_MIX_ENABLE    2
+#define V_STAG_MIX_ENABLE(x) ((x) << S_STAG_MIX_ENABLE)
+#define F_STAG_MIX_ENABLE    V_STAG_MIX_ENABLE(1U)
+
+#define S_STAGF_FIX_DISABLE    1
+#define V_STAGF_FIX_DISABLE(x) ((x) << S_STAGF_FIX_DISABLE)
+#define F_STAGF_FIX_DISABLE    V_STAGF_FIX_DISABLE(1U)
+
+#define S_EXTRA_TAG_INSERTION_ENABLE    0
+#define V_EXTRA_TAG_INSERTION_ENABLE(x) ((x) << S_EXTRA_TAG_INSERTION_ENABLE)
+#define F_EXTRA_TAG_INSERTION_ENABLE    V_EXTRA_TAG_INSERTION_ENABLE(1U)
+
+#define S_PHYS_ADDR_RESP_EN    6
+#define V_PHYS_ADDR_RESP_EN(x) ((x) << S_PHYS_ADDR_RESP_EN)
+#define F_PHYS_ADDR_RESP_EN    V_PHYS_ADDR_RESP_EN(1U)
+
+#define S_ENDIANESS_CHANGE    5
+#define V_ENDIANESS_CHANGE(x) ((x) << S_ENDIANESS_CHANGE)
+#define F_ENDIANESS_CHANGE    V_ENDIANESS_CHANGE(1U)
+
+#define S_ERR_RTAG_EN    4
+#define V_ERR_RTAG_EN(x) ((x) << S_ERR_RTAG_EN)
+#define F_ERR_RTAG_EN    V_ERR_RTAG_EN(1U)
+
+#define S_TSO_ETHLEN_EN    3
+#define V_TSO_ETHLEN_EN(x) ((x) << S_TSO_ETHLEN_EN)
+#define F_TSO_ETHLEN_EN    V_TSO_ETHLEN_EN(1U)
+
+#define S_EMSG_MORE_INFO    2
+#define V_EMSG_MORE_INFO(x) ((x) << S_EMSG_MORE_INFO)
+#define F_EMSG_MORE_INFO    V_EMSG_MORE_INFO(1U)
+
+#define S_LOSDR    1
+#define V_LOSDR(x) ((x) << S_LOSDR)
+#define F_LOSDR    V_LOSDR(1U)
+
+#define A_ULP_TX_PERR_INJECT 0x8dc4
+#define A_ULP_TX_INT_ENABLE 0x8dc8
+
+#define S_PBL_BOUND_ERR_CH3    31
+#define V_PBL_BOUND_ERR_CH3(x) ((x) << S_PBL_BOUND_ERR_CH3)
+#define F_PBL_BOUND_ERR_CH3    V_PBL_BOUND_ERR_CH3(1U)
+
+#define S_PBL_BOUND_ERR_CH2    30
+#define V_PBL_BOUND_ERR_CH2(x) ((x) << S_PBL_BOUND_ERR_CH2)
+#define F_PBL_BOUND_ERR_CH2    V_PBL_BOUND_ERR_CH2(1U)
+
+#define S_PBL_BOUND_ERR_CH1    29
+#define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1)
+#define F_PBL_BOUND_ERR_CH1    V_PBL_BOUND_ERR_CH1(1U)
+
+#define S_PBL_BOUND_ERR_CH0    28
+#define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0)
+#define F_PBL_BOUND_ERR_CH0    V_PBL_BOUND_ERR_CH0(1U)
+
+#define S_SGE2ULP_FIFO_PERR_SET3    27
+#define V_SGE2ULP_FIFO_PERR_SET3(x) ((x) << S_SGE2ULP_FIFO_PERR_SET3)
+#define F_SGE2ULP_FIFO_PERR_SET3    V_SGE2ULP_FIFO_PERR_SET3(1U)
+
+#define S_SGE2ULP_FIFO_PERR_SET2    26
+#define V_SGE2ULP_FIFO_PERR_SET2(x) ((x) << S_SGE2ULP_FIFO_PERR_SET2)
+#define F_SGE2ULP_FIFO_PERR_SET2    V_SGE2ULP_FIFO_PERR_SET2(1U)
+
+#define S_SGE2ULP_FIFO_PERR_SET1    25
+#define V_SGE2ULP_FIFO_PERR_SET1(x) ((x) << S_SGE2ULP_FIFO_PERR_SET1)
+#define F_SGE2ULP_FIFO_PERR_SET1    V_SGE2ULP_FIFO_PERR_SET1(1U)
+
+#define S_SGE2ULP_FIFO_PERR_SET0    24
+#define V_SGE2ULP_FIFO_PERR_SET0(x) ((x) << S_SGE2ULP_FIFO_PERR_SET0)
+#define F_SGE2ULP_FIFO_PERR_SET0    V_SGE2ULP_FIFO_PERR_SET0(1U)
+
+#define S_CIM2ULP_FIFO_PERR_SET3    23
+#define V_CIM2ULP_FIFO_PERR_SET3(x) ((x) << S_CIM2ULP_FIFO_PERR_SET3)
+#define F_CIM2ULP_FIFO_PERR_SET3    V_CIM2ULP_FIFO_PERR_SET3(1U)
+
+#define S_CIM2ULP_FIFO_PERR_SET2    22
+#define V_CIM2ULP_FIFO_PERR_SET2(x) ((x) << S_CIM2ULP_FIFO_PERR_SET2)
+#define F_CIM2ULP_FIFO_PERR_SET2    V_CIM2ULP_FIFO_PERR_SET2(1U)
+
+#define S_CIM2ULP_FIFO_PERR_SET1    21
+#define V_CIM2ULP_FIFO_PERR_SET1(x) ((x) << S_CIM2ULP_FIFO_PERR_SET1)
+#define F_CIM2ULP_FIFO_PERR_SET1    V_CIM2ULP_FIFO_PERR_SET1(1U)
+
+#define S_CIM2ULP_FIFO_PERR_SET0    20
+#define V_CIM2ULP_FIFO_PERR_SET0(x) ((x) << S_CIM2ULP_FIFO_PERR_SET0)
+#define F_CIM2ULP_FIFO_PERR_SET0    V_CIM2ULP_FIFO_PERR_SET0(1U)
+
+#define S_CQE_FIFO_PERR_SET3    19
+#define V_CQE_FIFO_PERR_SET3(x) ((x) << S_CQE_FIFO_PERR_SET3)
+#define F_CQE_FIFO_PERR_SET3    V_CQE_FIFO_PERR_SET3(1U)
+
+#define S_CQE_FIFO_PERR_SET2    18
+#define V_CQE_FIFO_PERR_SET2(x) ((x) << S_CQE_FIFO_PERR_SET2)
+#define F_CQE_FIFO_PERR_SET2    V_CQE_FIFO_PERR_SET2(1U)
+
+#define S_CQE_FIFO_PERR_SET1    17
+#define V_CQE_FIFO_PERR_SET1(x) ((x) << S_CQE_FIFO_PERR_SET1)
+#define F_CQE_FIFO_PERR_SET1    V_CQE_FIFO_PERR_SET1(1U)
+
+#define S_CQE_FIFO_PERR_SET0    16
+#define V_CQE_FIFO_PERR_SET0(x) ((x) << S_CQE_FIFO_PERR_SET0)
+#define F_CQE_FIFO_PERR_SET0    V_CQE_FIFO_PERR_SET0(1U)
+
+#define S_PBL_FIFO_PERR_SET3    15
+#define V_PBL_FIFO_PERR_SET3(x) ((x) << S_PBL_FIFO_PERR_SET3)
+#define F_PBL_FIFO_PERR_SET3    V_PBL_FIFO_PERR_SET3(1U)
+
+#define S_PBL_FIFO_PERR_SET2    14
+#define V_PBL_FIFO_PERR_SET2(x) ((x) << S_PBL_FIFO_PERR_SET2)
+#define F_PBL_FIFO_PERR_SET2    V_PBL_FIFO_PERR_SET2(1U)
+
+#define S_PBL_FIFO_PERR_SET1    13
+#define V_PBL_FIFO_PERR_SET1(x) ((x) << S_PBL_FIFO_PERR_SET1)
+#define F_PBL_FIFO_PERR_SET1    V_PBL_FIFO_PERR_SET1(1U)
+
+#define S_PBL_FIFO_PERR_SET0    12
+#define V_PBL_FIFO_PERR_SET0(x) ((x) << S_PBL_FIFO_PERR_SET0)
+#define F_PBL_FIFO_PERR_SET0    V_PBL_FIFO_PERR_SET0(1U)
+
+#define S_CMD_FIFO_PERR_SET3    11
+#define V_CMD_FIFO_PERR_SET3(x) ((x) << S_CMD_FIFO_PERR_SET3)
+#define F_CMD_FIFO_PERR_SET3    V_CMD_FIFO_PERR_SET3(1U)
+
+#define S_CMD_FIFO_PERR_SET2    10
+#define V_CMD_FIFO_PERR_SET2(x) ((x) << S_CMD_FIFO_PERR_SET2)
+#define F_CMD_FIFO_PERR_SET2    V_CMD_FIFO_PERR_SET2(1U)
+
+#define S_CMD_FIFO_PERR_SET1    9
+#define V_CMD_FIFO_PERR_SET1(x) ((x) << S_CMD_FIFO_PERR_SET1)
+#define F_CMD_FIFO_PERR_SET1    V_CMD_FIFO_PERR_SET1(1U)
+
+#define S_CMD_FIFO_PERR_SET0    8
+#define V_CMD_FIFO_PERR_SET0(x) ((x) << S_CMD_FIFO_PERR_SET0)
+#define F_CMD_FIFO_PERR_SET0    V_CMD_FIFO_PERR_SET0(1U)
+
+#define S_LSO_HDR_SRAM_PERR_SET3    7
+#define V_LSO_HDR_SRAM_PERR_SET3(x) ((x) << S_LSO_HDR_SRAM_PERR_SET3)
+#define F_LSO_HDR_SRAM_PERR_SET3    V_LSO_HDR_SRAM_PERR_SET3(1U)
+
+#define S_LSO_HDR_SRAM_PERR_SET2    6
+#define V_LSO_HDR_SRAM_PERR_SET2(x) ((x) << S_LSO_HDR_SRAM_PERR_SET2)
+#define F_LSO_HDR_SRAM_PERR_SET2    V_LSO_HDR_SRAM_PERR_SET2(1U)
+
+#define S_LSO_HDR_SRAM_PERR_SET1    5
+#define V_LSO_HDR_SRAM_PERR_SET1(x) ((x) << S_LSO_HDR_SRAM_PERR_SET1)
+#define F_LSO_HDR_SRAM_PERR_SET1    V_LSO_HDR_SRAM_PERR_SET1(1U)
+
+#define S_LSO_HDR_SRAM_PERR_SET0    4
+#define V_LSO_HDR_SRAM_PERR_SET0(x) ((x) << S_LSO_HDR_SRAM_PERR_SET0)
+#define F_LSO_HDR_SRAM_PERR_SET0    V_LSO_HDR_SRAM_PERR_SET0(1U)
+
+#define S_IMM_DATA_PERR_SET_CH3    3
+#define V_IMM_DATA_PERR_SET_CH3(x) ((x) << S_IMM_DATA_PERR_SET_CH3)
+#define F_IMM_DATA_PERR_SET_CH3    V_IMM_DATA_PERR_SET_CH3(1U)
+
+#define S_IMM_DATA_PERR_SET_CH2    2
+#define V_IMM_DATA_PERR_SET_CH2(x) ((x) << S_IMM_DATA_PERR_SET_CH2)
+#define F_IMM_DATA_PERR_SET_CH2    V_IMM_DATA_PERR_SET_CH2(1U)
+
+#define S_IMM_DATA_PERR_SET_CH1    1
+#define V_IMM_DATA_PERR_SET_CH1(x) ((x) << S_IMM_DATA_PERR_SET_CH1)
+#define F_IMM_DATA_PERR_SET_CH1    V_IMM_DATA_PERR_SET_CH1(1U)
+
+#define S_IMM_DATA_PERR_SET_CH0    0
+#define V_IMM_DATA_PERR_SET_CH0(x) ((x) << S_IMM_DATA_PERR_SET_CH0)
+#define F_IMM_DATA_PERR_SET_CH0    V_IMM_DATA_PERR_SET_CH0(1U)
+
+#define A_ULP_TX_INT_CAUSE 0x8dcc
+#define A_ULP_TX_PERR_ENABLE 0x8dd0
+#define A_ULP_TX_TPT_LLIMIT 0x8dd4
+#define A_ULP_TX_TPT_ULIMIT 0x8dd8
+#define A_ULP_TX_PBL_LLIMIT 0x8ddc
+#define A_ULP_TX_PBL_ULIMIT 0x8de0
+#define A_ULP_TX_CPL_ERR_OFFSET 0x8de4
+#define A_ULP_TX_CPL_ERR_MASK_L 0x8de8
+#define A_ULP_TX_CPL_ERR_MASK_H 0x8dec
+#define A_ULP_TX_CPL_ERR_VALUE_L 0x8df0
+#define A_ULP_TX_CPL_ERR_VALUE_H 0x8df4
+#define A_ULP_TX_CPL_PACK_SIZE1 0x8df8
+
+#define S_CH3SIZE1    24
+#define M_CH3SIZE1    0xffU
+#define V_CH3SIZE1(x) ((x) << S_CH3SIZE1)
+#define G_CH3SIZE1(x) (((x) >> S_CH3SIZE1) & M_CH3SIZE1)
+
+#define S_CH2SIZE1    16
+#define M_CH2SIZE1    0xffU
+#define V_CH2SIZE1(x) ((x) << S_CH2SIZE1)
+#define G_CH2SIZE1(x) (((x) >> S_CH2SIZE1) & M_CH2SIZE1)
+
+#define S_CH1SIZE1    8
+#define M_CH1SIZE1    0xffU
+#define V_CH1SIZE1(x) ((x) << S_CH1SIZE1)
+#define G_CH1SIZE1(x) (((x) >> S_CH1SIZE1) & M_CH1SIZE1)
+
+#define S_CH0SIZE1    0
+#define M_CH0SIZE1    0xffU
+#define V_CH0SIZE1(x) ((x) << S_CH0SIZE1)
+#define G_CH0SIZE1(x) (((x) >> S_CH0SIZE1) & M_CH0SIZE1)
+
+#define A_ULP_TX_CPL_PACK_SIZE2 0x8dfc
+
+#define S_CH3SIZE2    24
+#define M_CH3SIZE2    0xffU
+#define V_CH3SIZE2(x) ((x) << S_CH3SIZE2)
+#define G_CH3SIZE2(x) (((x) >> S_CH3SIZE2) & M_CH3SIZE2)
+
+#define S_CH2SIZE2    16
+#define M_CH2SIZE2    0xffU
+#define V_CH2SIZE2(x) ((x) << S_CH2SIZE2)
+#define G_CH2SIZE2(x) (((x) >> S_CH2SIZE2) & M_CH2SIZE2)
+
+#define S_CH1SIZE2    8
+#define M_CH1SIZE2    0xffU
+#define V_CH1SIZE2(x) ((x) << S_CH1SIZE2)
+#define G_CH1SIZE2(x) (((x) >> S_CH1SIZE2) & M_CH1SIZE2)
+
+#define S_CH0SIZE2    0
+#define M_CH0SIZE2    0xffU
+#define V_CH0SIZE2(x) ((x) << S_CH0SIZE2)
+#define G_CH0SIZE2(x) (((x) >> S_CH0SIZE2) & M_CH0SIZE2)
+
+#define A_ULP_TX_ERR_MSG2CIM 0x8e00
+#define A_ULP_TX_ERR_TABLE_BASE 0x8e04
+#define A_ULP_TX_ERR_CNT_CH0 0x8e10
+
+#define S_ERR_CNT0    0
+#define M_ERR_CNT0    0xfffffU
+#define V_ERR_CNT0(x) ((x) << S_ERR_CNT0)
+#define G_ERR_CNT0(x) (((x) >> S_ERR_CNT0) & M_ERR_CNT0)
+
+#define A_ULP_TX_ERR_CNT_CH1 0x8e14
+
+#define S_ERR_CNT1    0
+#define M_ERR_CNT1    0xfffffU
+#define V_ERR_CNT1(x) ((x) << S_ERR_CNT1)
+#define G_ERR_CNT1(x) (((x) >> S_ERR_CNT1) & M_ERR_CNT1)
+
+#define A_ULP_TX_ERR_CNT_CH2 0x8e18
+
+#define S_ERR_CNT2    0
+#define M_ERR_CNT2    0xfffffU
+#define V_ERR_CNT2(x) ((x) << S_ERR_CNT2)
+#define G_ERR_CNT2(x) (((x) >> S_ERR_CNT2) & M_ERR_CNT2)
+
+#define A_ULP_TX_ERR_CNT_CH3 0x8e1c
+
+#define S_ERR_CNT3    0
+#define M_ERR_CNT3    0xfffffU
+#define V_ERR_CNT3(x) ((x) << S_ERR_CNT3)
+#define G_ERR_CNT3(x) (((x) >> S_ERR_CNT3) & M_ERR_CNT3)
+
+#define A_ULP_TX_FC_SOF 0x8e20
+
+#define S_SOF_FS3    24
+#define M_SOF_FS3    0xffU
+#define V_SOF_FS3(x) ((x) << S_SOF_FS3)
+#define G_SOF_FS3(x) (((x) >> S_SOF_FS3) & M_SOF_FS3)
+
+#define S_SOF_FS2    16
+#define M_SOF_FS2    0xffU
+#define V_SOF_FS2(x) ((x) << S_SOF_FS2)
+#define G_SOF_FS2(x) (((x) >> S_SOF_FS2) & M_SOF_FS2)
+
+#define S_SOF_3    8
+#define M_SOF_3    0xffU
+#define V_SOF_3(x) ((x) << S_SOF_3)
+#define G_SOF_3(x) (((x) >> S_SOF_3) & M_SOF_3)
+
+#define S_SOF_2    0
+#define M_SOF_2    0xffU
+#define V_SOF_2(x) ((x) << S_SOF_2)
+#define G_SOF_2(x) (((x) >> S_SOF_2) & M_SOF_2)
+
+#define A_ULP_TX_FC_EOF 0x8e24
+
+#define S_EOF_LS3    24
+#define M_EOF_LS3    0xffU
+#define V_EOF_LS3(x) ((x) << S_EOF_LS3)
+#define G_EOF_LS3(x) (((x) >> S_EOF_LS3) & M_EOF_LS3)
+
+#define S_EOF_LS2    16
+#define M_EOF_LS2    0xffU
+#define V_EOF_LS2(x) ((x) << S_EOF_LS2)
+#define G_EOF_LS2(x) (((x) >> S_EOF_LS2) & M_EOF_LS2)
+
+#define S_EOF_3    8
+#define M_EOF_3    0xffU
+#define V_EOF_3(x) ((x) << S_EOF_3)
+#define G_EOF_3(x) (((x) >> S_EOF_3) & M_EOF_3)
+
+#define S_EOF_2    0
+#define M_EOF_2    0xffU
+#define V_EOF_2(x) ((x) << S_EOF_2)
+#define G_EOF_2(x) (((x) >> S_EOF_2) & M_EOF_2)
+
+#define A_ULP_TX_CGEN_GLOBAL 0x8e28
+
+#define S_ULP_TX_GLOBAL_CGEN    0
+#define V_ULP_TX_GLOBAL_CGEN(x) ((x) << S_ULP_TX_GLOBAL_CGEN)
+#define F_ULP_TX_GLOBAL_CGEN    V_ULP_TX_GLOBAL_CGEN(1U)
+
+#define A_ULP_TX_CGEN 0x8e2c
+
+#define S_ULP_TX_CGEN_STORAGE    8
+#define M_ULP_TX_CGEN_STORAGE    0xfU
+#define V_ULP_TX_CGEN_STORAGE(x) ((x) << S_ULP_TX_CGEN_STORAGE)
+#define G_ULP_TX_CGEN_STORAGE(x) (((x) >> S_ULP_TX_CGEN_STORAGE) & M_ULP_TX_CGEN_STORAGE)
+
+#define S_ULP_TX_CGEN_RDMA    4
+#define M_ULP_TX_CGEN_RDMA    0xfU
+#define V_ULP_TX_CGEN_RDMA(x) ((x) << S_ULP_TX_CGEN_RDMA)
+#define G_ULP_TX_CGEN_RDMA(x) (((x) >> S_ULP_TX_CGEN_RDMA) & M_ULP_TX_CGEN_RDMA)
+
+#define S_ULP_TX_CGEN_CHANNEL    0
+#define M_ULP_TX_CGEN_CHANNEL    0xfU
+#define V_ULP_TX_CGEN_CHANNEL(x) ((x) << S_ULP_TX_CGEN_CHANNEL)
+#define G_ULP_TX_CGEN_CHANNEL(x) (((x) >> S_ULP_TX_CGEN_CHANNEL) & M_ULP_TX_CGEN_CHANNEL)
+
+#define A_ULP_TX_ULP2TP_BIST_CMD 0x8e30
+#define A_ULP_TX_MEM_CFG 0x8e30
+
+#define S_WRREQ_SZ    0
+#define M_WRREQ_SZ    0x7U
+#define V_WRREQ_SZ(x) ((x) << S_WRREQ_SZ)
+#define G_WRREQ_SZ(x) (((x) >> S_WRREQ_SZ) & M_WRREQ_SZ)
+
+#define A_ULP_TX_ULP2TP_BIST_ERROR_CNT 0x8e34
+#define A_ULP_TX_PERR_INJECT_2 0x8e34
+#define A_ULP_TX_FPGA_CMD_CTRL 0x8e38
+#define A_ULP_TX_T5_FPGA_CMD_CTRL 0x8e38
+
+#define S_CHANNEL_SEL    12
+#define M_CHANNEL_SEL    0x3U
+#define V_CHANNEL_SEL(x) ((x) << S_CHANNEL_SEL)
+#define G_CHANNEL_SEL(x) (((x) >> S_CHANNEL_SEL) & M_CHANNEL_SEL)
+
+#define S_INTF_SEL    4
+#define M_INTF_SEL    0xfU
+#define V_INTF_SEL(x) ((x) << S_INTF_SEL)
+#define G_INTF_SEL(x) (((x) >> S_INTF_SEL) & M_INTF_SEL)
+
+#define S_NUM_FLITS    1
+#define M_NUM_FLITS    0x7U
+#define V_NUM_FLITS(x) ((x) << S_NUM_FLITS)
+#define G_NUM_FLITS(x) (((x) >> S_NUM_FLITS) & M_NUM_FLITS)
+
+#define S_CMD_GEN_EN    0
+#define V_CMD_GEN_EN(x) ((x) << S_CMD_GEN_EN)
+#define F_CMD_GEN_EN    V_CMD_GEN_EN(1U)
+
+#define A_ULP_TX_FPGA_CMD_0 0x8e3c
+#define A_ULP_TX_T5_FPGA_CMD_0 0x8e3c
+#define A_ULP_TX_FPGA_CMD_1 0x8e40
+#define A_ULP_TX_T5_FPGA_CMD_1 0x8e40
+#define A_ULP_TX_FPGA_CMD_2 0x8e44
+#define A_ULP_TX_T5_FPGA_CMD_2 0x8e44
+#define A_ULP_TX_FPGA_CMD_3 0x8e48
+#define A_ULP_TX_T5_FPGA_CMD_3 0x8e48
+#define A_ULP_TX_FPGA_CMD_4 0x8e4c
+#define A_ULP_TX_T5_FPGA_CMD_4 0x8e4c
+#define A_ULP_TX_FPGA_CMD_5 0x8e50
+#define A_ULP_TX_T5_FPGA_CMD_5 0x8e50
+#define A_ULP_TX_FPGA_CMD_6 0x8e54
+#define A_ULP_TX_T5_FPGA_CMD_6 0x8e54
+#define A_ULP_TX_FPGA_CMD_7 0x8e58
+#define A_ULP_TX_T5_FPGA_CMD_7 0x8e58
+#define A_ULP_TX_FPGA_CMD_8 0x8e5c
+#define A_ULP_TX_T5_FPGA_CMD_8 0x8e5c
+#define A_ULP_TX_FPGA_CMD_9 0x8e60
+#define A_ULP_TX_T5_FPGA_CMD_9 0x8e60
+#define A_ULP_TX_FPGA_CMD_10 0x8e64
+#define A_ULP_TX_T5_FPGA_CMD_10 0x8e64
+#define A_ULP_TX_FPGA_CMD_11 0x8e68
+#define A_ULP_TX_T5_FPGA_CMD_11 0x8e68
+#define A_ULP_TX_FPGA_CMD_12 0x8e6c
+#define A_ULP_TX_T5_FPGA_CMD_12 0x8e6c
+#define A_ULP_TX_FPGA_CMD_13 0x8e70
+#define A_ULP_TX_T5_FPGA_CMD_13 0x8e70
+#define A_ULP_TX_FPGA_CMD_14 0x8e74
+#define A_ULP_TX_T5_FPGA_CMD_14 0x8e74
+#define A_ULP_TX_FPGA_CMD_15 0x8e78
+#define A_ULP_TX_T5_FPGA_CMD_15 0x8e78
+#define A_ULP_TX_INT_ENABLE_2 0x8e7c
+
+#define S_SMARBT2ULP_DATA_PERR_SET    12
+#define V_SMARBT2ULP_DATA_PERR_SET(x) ((x) << S_SMARBT2ULP_DATA_PERR_SET)
+#define F_SMARBT2ULP_DATA_PERR_SET    V_SMARBT2ULP_DATA_PERR_SET(1U)
+
+#define S_ULP2TP_DATA_PERR_SET    11
+#define V_ULP2TP_DATA_PERR_SET(x) ((x) << S_ULP2TP_DATA_PERR_SET)
+#define F_ULP2TP_DATA_PERR_SET    V_ULP2TP_DATA_PERR_SET(1U)
+
+#define S_MA2ULP_DATA_PERR_SET    10
+#define V_MA2ULP_DATA_PERR_SET(x) ((x) << S_MA2ULP_DATA_PERR_SET)
+#define F_MA2ULP_DATA_PERR_SET    V_MA2ULP_DATA_PERR_SET(1U)
+
+#define S_SGE2ULP_DATA_PERR_SET    9
+#define V_SGE2ULP_DATA_PERR_SET(x) ((x) << S_SGE2ULP_DATA_PERR_SET)
+#define F_SGE2ULP_DATA_PERR_SET    V_SGE2ULP_DATA_PERR_SET(1U)
+
+#define S_CIM2ULP_DATA_PERR_SET    8
+#define V_CIM2ULP_DATA_PERR_SET(x) ((x) << S_CIM2ULP_DATA_PERR_SET)
+#define F_CIM2ULP_DATA_PERR_SET    V_CIM2ULP_DATA_PERR_SET(1U)
+
+#define S_FSO_HDR_SRAM_PERR_SET3    7
+#define V_FSO_HDR_SRAM_PERR_SET3(x) ((x) << S_FSO_HDR_SRAM_PERR_SET3)
+#define F_FSO_HDR_SRAM_PERR_SET3    V_FSO_HDR_SRAM_PERR_SET3(1U)
+
+#define S_FSO_HDR_SRAM_PERR_SET2    6
+#define V_FSO_HDR_SRAM_PERR_SET2(x) ((x) << S_FSO_HDR_SRAM_PERR_SET2)
+#define F_FSO_HDR_SRAM_PERR_SET2    V_FSO_HDR_SRAM_PERR_SET2(1U)
+
+#define S_FSO_HDR_SRAM_PERR_SET1    5
+#define V_FSO_HDR_SRAM_PERR_SET1(x) ((x) << S_FSO_HDR_SRAM_PERR_SET1)
+#define F_FSO_HDR_SRAM_PERR_SET1    V_FSO_HDR_SRAM_PERR_SET1(1U)
+
+#define S_FSO_HDR_SRAM_PERR_SET0    4
+#define V_FSO_HDR_SRAM_PERR_SET0(x) ((x) << S_FSO_HDR_SRAM_PERR_SET0)
+#define F_FSO_HDR_SRAM_PERR_SET0    V_FSO_HDR_SRAM_PERR_SET0(1U)
+
+#define S_T10_PI_SRAM_PERR_SET3    3
+#define V_T10_PI_SRAM_PERR_SET3(x) ((x) << S_T10_PI_SRAM_PERR_SET3)
+#define F_T10_PI_SRAM_PERR_SET3    V_T10_PI_SRAM_PERR_SET3(1U)
+
+#define S_T10_PI_SRAM_PERR_SET2    2
+#define V_T10_PI_SRAM_PERR_SET2(x) ((x) << S_T10_PI_SRAM_PERR_SET2)
+#define F_T10_PI_SRAM_PERR_SET2    V_T10_PI_SRAM_PERR_SET2(1U)
+
+#define S_T10_PI_SRAM_PERR_SET1    1
+#define V_T10_PI_SRAM_PERR_SET1(x) ((x) << S_T10_PI_SRAM_PERR_SET1)
+#define F_T10_PI_SRAM_PERR_SET1    V_T10_PI_SRAM_PERR_SET1(1U)
+
+#define S_T10_PI_SRAM_PERR_SET0    0
+#define V_T10_PI_SRAM_PERR_SET0(x) ((x) << S_T10_PI_SRAM_PERR_SET0)
+#define F_T10_PI_SRAM_PERR_SET0    V_T10_PI_SRAM_PERR_SET0(1U)
+
+#define A_ULP_TX_INT_CAUSE_2 0x8e80
+#define A_ULP_TX_PERR_ENABLE_2 0x8e84
+#define A_ULP_TX_SE_CNT_ERR 0x8ea0
+
+#define S_ERR_CH3    12
+#define M_ERR_CH3    0xfU
+#define V_ERR_CH3(x) ((x) << S_ERR_CH3)
+#define G_ERR_CH3(x) (((x) >> S_ERR_CH3) & M_ERR_CH3)
+
+#define S_ERR_CH2    8
+#define M_ERR_CH2    0xfU
+#define V_ERR_CH2(x) ((x) << S_ERR_CH2)
+#define G_ERR_CH2(x) (((x) >> S_ERR_CH2) & M_ERR_CH2)
+
+#define S_ERR_CH1    4
+#define M_ERR_CH1    0xfU
+#define V_ERR_CH1(x) ((x) << S_ERR_CH1)
+#define G_ERR_CH1(x) (((x) >> S_ERR_CH1) & M_ERR_CH1)
+
+#define S_ERR_CH0    0
+#define M_ERR_CH0    0xfU
+#define V_ERR_CH0(x) ((x) << S_ERR_CH0)
+#define G_ERR_CH0(x) (((x) >> S_ERR_CH0) & M_ERR_CH0)
+
+#define A_ULP_TX_T5_SE_CNT_ERR 0x8ea0
+#define A_ULP_TX_SE_CNT_CLR 0x8ea4
+
+#define S_CLR_DROP    16
+#define M_CLR_DROP    0xfU
+#define V_CLR_DROP(x) ((x) << S_CLR_DROP)
+#define G_CLR_DROP(x) (((x) >> S_CLR_DROP) & M_CLR_DROP)
+
+#define S_CLR_CH3    12
+#define M_CLR_CH3    0xfU
+#define V_CLR_CH3(x) ((x) << S_CLR_CH3)
+#define G_CLR_CH3(x) (((x) >> S_CLR_CH3) & M_CLR_CH3)
+
+#define S_CLR_CH2    8
+#define M_CLR_CH2    0xfU
+#define V_CLR_CH2(x) ((x) << S_CLR_CH2)
+#define G_CLR_CH2(x) (((x) >> S_CLR_CH2) & M_CLR_CH2)
+
+#define S_CLR_CH1    4
+#define M_CLR_CH1    0xfU
+#define V_CLR_CH1(x) ((x) << S_CLR_CH1)
+#define G_CLR_CH1(x) (((x) >> S_CLR_CH1) & M_CLR_CH1)
+
+#define S_CLR_CH0    0
+#define M_CLR_CH0    0xfU
+#define V_CLR_CH0(x) ((x) << S_CLR_CH0)
+#define G_CLR_CH0(x) (((x) >> S_CLR_CH0) & M_CLR_CH0)
+
+#define A_ULP_TX_T5_SE_CNT_CLR 0x8ea4
+#define A_ULP_TX_SE_CNT_CH0 0x8ea8
+
+#define S_SOP_CNT_ULP2TP    28
+#define M_SOP_CNT_ULP2TP    0xfU
+#define V_SOP_CNT_ULP2TP(x) ((x) << S_SOP_CNT_ULP2TP)
+#define G_SOP_CNT_ULP2TP(x) (((x) >> S_SOP_CNT_ULP2TP) & M_SOP_CNT_ULP2TP)
+
+#define S_EOP_CNT_ULP2TP    24
+#define M_EOP_CNT_ULP2TP    0xfU
+#define V_EOP_CNT_ULP2TP(x) ((x) << S_EOP_CNT_ULP2TP)
+#define G_EOP_CNT_ULP2TP(x) (((x) >> S_EOP_CNT_ULP2TP) & M_EOP_CNT_ULP2TP)
+
+#define S_SOP_CNT_LSO_IN    20
+#define M_SOP_CNT_LSO_IN    0xfU
+#define V_SOP_CNT_LSO_IN(x) ((x) << S_SOP_CNT_LSO_IN)
+#define G_SOP_CNT_LSO_IN(x) (((x) >> S_SOP_CNT_LSO_IN) & M_SOP_CNT_LSO_IN)
+
+#define S_EOP_CNT_LSO_IN    16
+#define M_EOP_CNT_LSO_IN    0xfU
+#define V_EOP_CNT_LSO_IN(x) ((x) << S_EOP_CNT_LSO_IN)
+#define G_EOP_CNT_LSO_IN(x) (((x) >> S_EOP_CNT_LSO_IN) & M_EOP_CNT_LSO_IN)
+
+#define S_SOP_CNT_ALG_IN    12
+#define M_SOP_CNT_ALG_IN    0xfU
+#define V_SOP_CNT_ALG_IN(x) ((x) << S_SOP_CNT_ALG_IN)
+#define G_SOP_CNT_ALG_IN(x) (((x) >> S_SOP_CNT_ALG_IN) & M_SOP_CNT_ALG_IN)
+
+#define S_EOP_CNT_ALG_IN    8
+#define M_EOP_CNT_ALG_IN    0xfU
+#define V_EOP_CNT_ALG_IN(x) ((x) << S_EOP_CNT_ALG_IN)
+#define G_EOP_CNT_ALG_IN(x) (((x) >> S_EOP_CNT_ALG_IN) & M_EOP_CNT_ALG_IN)
+
+#define S_SOP_CNT_CIM2ULP    4
+#define M_SOP_CNT_CIM2ULP    0xfU
+#define V_SOP_CNT_CIM2ULP(x) ((x) << S_SOP_CNT_CIM2ULP)
+#define G_SOP_CNT_CIM2ULP(x) (((x) >> S_SOP_CNT_CIM2ULP) & M_SOP_CNT_CIM2ULP)
+
+#define S_EOP_CNT_CIM2ULP    0
+#define M_EOP_CNT_CIM2ULP    0xfU
+#define V_EOP_CNT_CIM2ULP(x) ((x) << S_EOP_CNT_CIM2ULP)
+#define G_EOP_CNT_CIM2ULP(x) (((x) >> S_EOP_CNT_CIM2ULP) & M_EOP_CNT_CIM2ULP)
+
+#define A_ULP_TX_T5_SE_CNT_CH0 0x8ea8
+#define A_ULP_TX_SE_CNT_CH1 0x8eac
+#define A_ULP_TX_T5_SE_CNT_CH1 0x8eac
+#define A_ULP_TX_SE_CNT_CH2 0x8eb0
+#define A_ULP_TX_T5_SE_CNT_CH2 0x8eb0
+#define A_ULP_TX_SE_CNT_CH3 0x8eb4
+#define A_ULP_TX_T5_SE_CNT_CH3 0x8eb4
+#define A_ULP_TX_DROP_CNT 0x8eb8
+
+#define S_DROP_CH3    12
+#define M_DROP_CH3    0xfU
+#define V_DROP_CH3(x) ((x) << S_DROP_CH3)
+#define G_DROP_CH3(x) (((x) >> S_DROP_CH3) & M_DROP_CH3)
+
+#define S_DROP_CH2    8
+#define M_DROP_CH2    0xfU
+#define V_DROP_CH2(x) ((x) << S_DROP_CH2)
+#define G_DROP_CH2(x) (((x) >> S_DROP_CH2) & M_DROP_CH2)
+
+#define S_DROP_CH1    4
+#define M_DROP_CH1    0xfU
+#define V_DROP_CH1(x) ((x) << S_DROP_CH1)
+#define G_DROP_CH1(x) (((x) >> S_DROP_CH1) & M_DROP_CH1)
+
+#define S_DROP_CH0    0
+#define M_DROP_CH0    0xfU
+#define V_DROP_CH0(x) ((x) << S_DROP_CH0)
+#define G_DROP_CH0(x) (((x) >> S_DROP_CH0) & M_DROP_CH0)
+
+#define A_ULP_TX_T5_DROP_CNT 0x8eb8
+#define A_ULP_TX_CSU_REVISION 0x8ebc
+#define A_ULP_TX_LA_RDPTR_0 0x8ec0
+#define A_ULP_TX_LA_RDDATA_0 0x8ec4
+#define A_ULP_TX_LA_WRPTR_0 0x8ec8
+#define A_ULP_TX_LA_RESERVED_0 0x8ecc
+#define A_ULP_TX_LA_RDPTR_1 0x8ed0
+#define A_ULP_TX_LA_RDDATA_1 0x8ed4
+#define A_ULP_TX_LA_WRPTR_1 0x8ed8
+#define A_ULP_TX_LA_RESERVED_1 0x8edc
+#define A_ULP_TX_LA_RDPTR_2 0x8ee0
+#define A_ULP_TX_LA_RDDATA_2 0x8ee4
+#define A_ULP_TX_LA_WRPTR_2 0x8ee8
+#define A_ULP_TX_LA_RESERVED_2 0x8eec
+#define A_ULP_TX_LA_RDPTR_3 0x8ef0
+#define A_ULP_TX_LA_RDDATA_3 0x8ef4
+#define A_ULP_TX_LA_WRPTR_3 0x8ef8
+#define A_ULP_TX_LA_RESERVED_3 0x8efc
+#define A_ULP_TX_LA_RDPTR_4 0x8f00
+#define A_ULP_TX_LA_RDDATA_4 0x8f04
+#define A_ULP_TX_LA_WRPTR_4 0x8f08
+#define A_ULP_TX_LA_RESERVED_4 0x8f0c
+#define A_ULP_TX_LA_RDPTR_5 0x8f10
+#define A_ULP_TX_LA_RDDATA_5 0x8f14
+#define A_ULP_TX_LA_WRPTR_5 0x8f18
+#define A_ULP_TX_LA_RESERVED_5 0x8f1c
+#define A_ULP_TX_LA_RDPTR_6 0x8f20
+#define A_ULP_TX_LA_RDDATA_6 0x8f24
+#define A_ULP_TX_LA_WRPTR_6 0x8f28
+#define A_ULP_TX_LA_RESERVED_6 0x8f2c
+#define A_ULP_TX_LA_RDPTR_7 0x8f30
+#define A_ULP_TX_LA_RDDATA_7 0x8f34
+#define A_ULP_TX_LA_WRPTR_7 0x8f38
+#define A_ULP_TX_LA_RESERVED_7 0x8f3c
+#define A_ULP_TX_LA_RDPTR_8 0x8f40
+#define A_ULP_TX_LA_RDDATA_8 0x8f44
+#define A_ULP_TX_LA_WRPTR_8 0x8f48
+#define A_ULP_TX_LA_RESERVED_8 0x8f4c
+#define A_ULP_TX_LA_RDPTR_9 0x8f50
+#define A_ULP_TX_LA_RDDATA_9 0x8f54
+#define A_ULP_TX_LA_WRPTR_9 0x8f58
+#define A_ULP_TX_LA_RESERVED_9 0x8f5c
+#define A_ULP_TX_LA_RDPTR_10 0x8f60
+#define A_ULP_TX_LA_RDDATA_10 0x8f64
+#define A_ULP_TX_LA_WRPTR_10 0x8f68
+#define A_ULP_TX_LA_RESERVED_10 0x8f6c
+#define A_ULP_TX_ASIC_DEBUG_CTRL 0x8f70
+
+#define S_LA_WR0    0
+#define V_LA_WR0(x) ((x) << S_LA_WR0)
+#define F_LA_WR0    V_LA_WR0(1U)
+
+#define A_ULP_TX_ASIC_DEBUG_0 0x8f74
+#define A_ULP_TX_ASIC_DEBUG_1 0x8f78
+#define A_ULP_TX_ASIC_DEBUG_2 0x8f7c
+#define A_ULP_TX_ASIC_DEBUG_3 0x8f80
+#define A_ULP_TX_ASIC_DEBUG_4 0x8f84
+
+/* registers for module PM_RX */
+#define PM_RX_BASE_ADDR 0x8fc0
+
+#define A_PM_RX_CFG 0x8fc0
+#define A_PM_RX_MODE 0x8fc4
+
+#define S_RX_USE_BUNDLE_LEN    4
+#define V_RX_USE_BUNDLE_LEN(x) ((x) << S_RX_USE_BUNDLE_LEN)
+#define F_RX_USE_BUNDLE_LEN    V_RX_USE_BUNDLE_LEN(1U)
+
+#define S_STAT_TO_CH    3
+#define V_STAT_TO_CH(x) ((x) << S_STAT_TO_CH)
+#define F_STAT_TO_CH    V_STAT_TO_CH(1U)
+
+#define S_STAT_FROM_CH    1
+#define M_STAT_FROM_CH    0x3U
+#define V_STAT_FROM_CH(x) ((x) << S_STAT_FROM_CH)
+#define G_STAT_FROM_CH(x) (((x) >> S_STAT_FROM_CH) & M_STAT_FROM_CH)
+
+#define S_PREFETCH_ENABLE    0
+#define V_PREFETCH_ENABLE(x) ((x) << S_PREFETCH_ENABLE)
+#define F_PREFETCH_ENABLE    V_PREFETCH_ENABLE(1U)
+
+#define A_PM_RX_STAT_CONFIG 0x8fc8
+#define A_PM_RX_STAT_COUNT 0x8fcc
+#define A_PM_RX_STAT_LSB 0x8fd0
+#define A_PM_RX_DBG_CTRL 0x8fd0
+
+#define S_OSPIWRBUSY_T5    21
+#define M_OSPIWRBUSY_T5    0x3U
+#define V_OSPIWRBUSY_T5(x) ((x) << S_OSPIWRBUSY_T5)
+#define G_OSPIWRBUSY_T5(x) (((x) >> S_OSPIWRBUSY_T5) & M_OSPIWRBUSY_T5)
+
+#define S_ISPIWRBUSY    17
+#define M_ISPIWRBUSY    0xfU
+#define V_ISPIWRBUSY(x) ((x) << S_ISPIWRBUSY)
+#define G_ISPIWRBUSY(x) (((x) >> S_ISPIWRBUSY) & M_ISPIWRBUSY)
+
+#define S_PMDBGADDR    0
+#define M_PMDBGADDR    0x1ffffU
+#define V_PMDBGADDR(x) ((x) << S_PMDBGADDR)
+#define G_PMDBGADDR(x) (((x) >> S_PMDBGADDR) & M_PMDBGADDR)
+
+#define A_PM_RX_STAT_MSB 0x8fd4
+#define A_PM_RX_DBG_DATA 0x8fd4
+#define A_PM_RX_INT_ENABLE 0x8fd8
+
+#define S_ZERO_E_CMD_ERROR    22
+#define V_ZERO_E_CMD_ERROR(x) ((x) << S_ZERO_E_CMD_ERROR)
+#define F_ZERO_E_CMD_ERROR    V_ZERO_E_CMD_ERROR(1U)
+
+#define S_IESPI0_FIFO2X_RX_FRAMING_ERROR    21
+#define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR)
+#define F_IESPI0_FIFO2X_RX_FRAMING_ERROR    V_IESPI0_FIFO2X_RX_FRAMING_ERROR(1U)
+
+#define S_IESPI1_FIFO2X_RX_FRAMING_ERROR    20
+#define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR)
+#define F_IESPI1_FIFO2X_RX_FRAMING_ERROR    V_IESPI1_FIFO2X_RX_FRAMING_ERROR(1U)
+
+#define S_IESPI2_FIFO2X_RX_FRAMING_ERROR    19
+#define V_IESPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI2_FIFO2X_RX_FRAMING_ERROR)
+#define F_IESPI2_FIFO2X_RX_FRAMING_ERROR    V_IESPI2_FIFO2X_RX_FRAMING_ERROR(1U)
+
+#define S_IESPI3_FIFO2X_RX_FRAMING_ERROR    18
+#define V_IESPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI3_FIFO2X_RX_FRAMING_ERROR)
+#define F_IESPI3_FIFO2X_RX_FRAMING_ERROR    V_IESPI3_FIFO2X_RX_FRAMING_ERROR(1U)
+
+#define S_IESPI0_RX_FRAMING_ERROR    17
+#define V_IESPI0_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_RX_FRAMING_ERROR)
+#define F_IESPI0_RX_FRAMING_ERROR    V_IESPI0_RX_FRAMING_ERROR(1U)
+
+#define S_IESPI1_RX_FRAMING_ERROR    16
+#define V_IESPI1_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_RX_FRAMING_ERROR)
+#define F_IESPI1_RX_FRAMING_ERROR    V_IESPI1_RX_FRAMING_ERROR(1U)
+
+#define S_IESPI2_RX_FRAMING_ERROR    15
+#define V_IESPI2_RX_FRAMING_ERROR(x) ((x) << S_IESPI2_RX_FRAMING_ERROR)
+#define F_IESPI2_RX_FRAMING_ERROR    V_IESPI2_RX_FRAMING_ERROR(1U)
+
+#define S_IESPI3_RX_FRAMING_ERROR    14
+#define V_IESPI3_RX_FRAMING_ERROR(x) ((x) << S_IESPI3_RX_FRAMING_ERROR)
+#define F_IESPI3_RX_FRAMING_ERROR    V_IESPI3_RX_FRAMING_ERROR(1U)
+
+#define S_IESPI0_TX_FRAMING_ERROR    13
+#define V_IESPI0_TX_FRAMING_ERROR(x) ((x) << S_IESPI0_TX_FRAMING_ERROR)
+#define F_IESPI0_TX_FRAMING_ERROR    V_IESPI0_TX_FRAMING_ERROR(1U)
+
+#define S_IESPI1_TX_FRAMING_ERROR    12
+#define V_IESPI1_TX_FRAMING_ERROR(x) ((x) << S_IESPI1_TX_FRAMING_ERROR)
+#define F_IESPI1_TX_FRAMING_ERROR    V_IESPI1_TX_FRAMING_ERROR(1U)
+
+#define S_IESPI2_TX_FRAMING_ERROR    11
+#define V_IESPI2_TX_FRAMING_ERROR(x) ((x) << S_IESPI2_TX_FRAMING_ERROR)
+#define F_IESPI2_TX_FRAMING_ERROR    V_IESPI2_TX_FRAMING_ERROR(1U)
+
+#define S_IESPI3_TX_FRAMING_ERROR    10
+#define V_IESPI3_TX_FRAMING_ERROR(x) ((x) << S_IESPI3_TX_FRAMING_ERROR)
+#define F_IESPI3_TX_FRAMING_ERROR    V_IESPI3_TX_FRAMING_ERROR(1U)
+
+#define S_OCSPI0_RX_FRAMING_ERROR    9
+#define V_OCSPI0_RX_FRAMING_ERROR(x) ((x) << S_OCSPI0_RX_FRAMING_ERROR)
+#define F_OCSPI0_RX_FRAMING_ERROR    V_OCSPI0_RX_FRAMING_ERROR(1U)
+
+#define S_OCSPI1_RX_FRAMING_ERROR    8
+#define V_OCSPI1_RX_FRAMING_ERROR(x) ((x) << S_OCSPI1_RX_FRAMING_ERROR)
+#define F_OCSPI1_RX_FRAMING_ERROR    V_OCSPI1_RX_FRAMING_ERROR(1U)
+
+#define S_OCSPI0_TX_FRAMING_ERROR    7
+#define V_OCSPI0_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_TX_FRAMING_ERROR)
+#define F_OCSPI0_TX_FRAMING_ERROR    V_OCSPI0_TX_FRAMING_ERROR(1U)
+
+#define S_OCSPI1_TX_FRAMING_ERROR    6
+#define V_OCSPI1_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_TX_FRAMING_ERROR)
+#define F_OCSPI1_TX_FRAMING_ERROR    V_OCSPI1_TX_FRAMING_ERROR(1U)
+
+#define S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR    5
+#define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR)
+#define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
+
+#define S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR    4
+#define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR)
+#define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
+
+#define S_OCSPI_PAR_ERROR    3
+#define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR)
+#define F_OCSPI_PAR_ERROR    V_OCSPI_PAR_ERROR(1U)
+
+#define S_DB_OPTIONS_PAR_ERROR    2
+#define V_DB_OPTIONS_PAR_ERROR(x) ((x) << S_DB_OPTIONS_PAR_ERROR)
+#define F_DB_OPTIONS_PAR_ERROR    V_DB_OPTIONS_PAR_ERROR(1U)
+
+#define S_IESPI_PAR_ERROR    1
+#define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR)
+#define F_IESPI_PAR_ERROR    V_IESPI_PAR_ERROR(1U)
+
+#define S_E_PCMD_PAR_ERROR    0
+#define V_E_PCMD_PAR_ERROR(x) ((x) << S_E_PCMD_PAR_ERROR)
+#define F_E_PCMD_PAR_ERROR    V_E_PCMD_PAR_ERROR(1U)
+
+#define S_OSPI_OVERFLOW1    28
+#define V_OSPI_OVERFLOW1(x) ((x) << S_OSPI_OVERFLOW1)
+#define F_OSPI_OVERFLOW1    V_OSPI_OVERFLOW1(1U)
+
+#define S_OSPI_OVERFLOW0    27
+#define V_OSPI_OVERFLOW0(x) ((x) << S_OSPI_OVERFLOW0)
+#define F_OSPI_OVERFLOW0    V_OSPI_OVERFLOW0(1U)
+
+#define S_MA_INTF_SDC_ERR    26
+#define V_MA_INTF_SDC_ERR(x) ((x) << S_MA_INTF_SDC_ERR)
+#define F_MA_INTF_SDC_ERR    V_MA_INTF_SDC_ERR(1U)
+
+#define S_BUNDLE_LEN_PARERR    25
+#define V_BUNDLE_LEN_PARERR(x) ((x) << S_BUNDLE_LEN_PARERR)
+#define F_BUNDLE_LEN_PARERR    V_BUNDLE_LEN_PARERR(1U)
+
+#define S_BUNDLE_LEN_OVFL    24
+#define V_BUNDLE_LEN_OVFL(x) ((x) << S_BUNDLE_LEN_OVFL)
+#define F_BUNDLE_LEN_OVFL    V_BUNDLE_LEN_OVFL(1U)
+
+#define S_SDC_ERR    23
+#define V_SDC_ERR(x) ((x) << S_SDC_ERR)
+#define F_SDC_ERR    V_SDC_ERR(1U)
+
+#define A_PM_RX_INT_CAUSE 0x8fdc
+#define A_PM_RX_ISPI_DBG_4B_DATA0 0x10000
+#define A_PM_RX_ISPI_DBG_4B_DATA1 0x10001
+#define A_PM_RX_ISPI_DBG_4B_DATA2 0x10002
+#define A_PM_RX_ISPI_DBG_4B_DATA3 0x10003
+#define A_PM_RX_ISPI_DBG_4B_DATA4 0x10004
+#define A_PM_RX_ISPI_DBG_4B_DATA5 0x10005
+#define A_PM_RX_ISPI_DBG_4B_DATA6 0x10006
+#define A_PM_RX_ISPI_DBG_4B_DATA7 0x10007
+#define A_PM_RX_ISPI_DBG_4B_DATA8 0x10008
+#define A_PM_RX_OSPI_DBG_4B_DATA0 0x10009
+#define A_PM_RX_OSPI_DBG_4B_DATA1 0x1000a
+#define A_PM_RX_OSPI_DBG_4B_DATA2 0x1000b
+#define A_PM_RX_OSPI_DBG_4B_DATA3 0x1000c
+#define A_PM_RX_OSPI_DBG_4B_DATA4 0x1000d
+#define A_PM_RX_OSPI_DBG_4B_DATA5 0x1000e
+#define A_PM_RX_OSPI_DBG_4B_DATA6 0x1000f
+#define A_PM_RX_OSPI_DBG_4B_DATA7 0x10010
+#define A_PM_RX_OSPI_DBG_4B_DATA8 0x10011
+#define A_PM_RX_OSPI_DBG_4B_DATA9 0x10012
+#define A_PM_RX_DBG_STAT_MSB 0x10013
+#define A_PM_RX_DBG_STAT_LSB 0x10014
+#define A_PM_RX_DBG_RSVD_FLIT_CNT 0x10015
+
+#define S_I_TO_O_PATH_RSVD_FLIT_BACKUP    12
+#define M_I_TO_O_PATH_RSVD_FLIT_BACKUP    0xfU
+#define V_I_TO_O_PATH_RSVD_FLIT_BACKUP(x) ((x) << S_I_TO_O_PATH_RSVD_FLIT_BACKUP)
+#define G_I_TO_O_PATH_RSVD_FLIT_BACKUP(x) (((x) >> S_I_TO_O_PATH_RSVD_FLIT_BACKUP) & M_I_TO_O_PATH_RSVD_FLIT_BACKUP)
+
+#define S_I_TO_O_PATH_RSVD_FLIT    8
+#define M_I_TO_O_PATH_RSVD_FLIT    0xfU
+#define V_I_TO_O_PATH_RSVD_FLIT(x) ((x) << S_I_TO_O_PATH_RSVD_FLIT)
+#define G_I_TO_O_PATH_RSVD_FLIT(x) (((x) >> S_I_TO_O_PATH_RSVD_FLIT) & M_I_TO_O_PATH_RSVD_FLIT)
+
+#define S_PRFCH_RSVD_FLIT    4
+#define M_PRFCH_RSVD_FLIT    0xfU
+#define V_PRFCH_RSVD_FLIT(x) ((x) << S_PRFCH_RSVD_FLIT)
+#define G_PRFCH_RSVD_FLIT(x) (((x) >> S_PRFCH_RSVD_FLIT) & M_PRFCH_RSVD_FLIT)
+
+#define S_OSPI_RSVD_FLIT    0
+#define M_OSPI_RSVD_FLIT    0xfU
+#define V_OSPI_RSVD_FLIT(x) ((x) << S_OSPI_RSVD_FLIT)
+#define G_OSPI_RSVD_FLIT(x) (((x) >> S_OSPI_RSVD_FLIT) & M_OSPI_RSVD_FLIT)
+
+#define A_PM_RX_SDC_EN 0x10016
+
+#define S_SDC_EN    0
+#define V_SDC_EN(x) ((x) << S_SDC_EN)
+#define F_SDC_EN    V_SDC_EN(1U)
+
+#define A_PM_RX_INOUT_FIFO_DBG_CHNL_SEL 0x10017
+
+#define S_CHNL_3_SEL    3
+#define V_CHNL_3_SEL(x) ((x) << S_CHNL_3_SEL)
+#define F_CHNL_3_SEL    V_CHNL_3_SEL(1U)
+
+#define S_CHNL_2_SEL    2
+#define V_CHNL_2_SEL(x) ((x) << S_CHNL_2_SEL)
+#define F_CHNL_2_SEL    V_CHNL_2_SEL(1U)
+
+#define S_CHNL_1_SEL    1
+#define V_CHNL_1_SEL(x) ((x) << S_CHNL_1_SEL)
+#define F_CHNL_1_SEL    V_CHNL_1_SEL(1U)
+
+#define S_CHNL_0_SEL    0
+#define V_CHNL_0_SEL(x) ((x) << S_CHNL_0_SEL)
+#define F_CHNL_0_SEL    V_CHNL_0_SEL(1U)
+
+#define A_PM_RX_INOUT_FIFO_DBG_WR 0x10018
+
+#define S_O_FIFO_WRITE    3
+#define V_O_FIFO_WRITE(x) ((x) << S_O_FIFO_WRITE)
+#define F_O_FIFO_WRITE    V_O_FIFO_WRITE(1U)
+
+#define S_I_FIFO_WRITE    2
+#define V_I_FIFO_WRITE(x) ((x) << S_I_FIFO_WRITE)
+#define F_I_FIFO_WRITE    V_I_FIFO_WRITE(1U)
+
+#define S_O_FIFO_READ    1
+#define V_O_FIFO_READ(x) ((x) << S_O_FIFO_READ)
+#define F_O_FIFO_READ    V_O_FIFO_READ(1U)
+
+#define S_I_FIFO_READ    0
+#define V_I_FIFO_READ(x) ((x) << S_I_FIFO_READ)
+#define F_I_FIFO_READ    V_I_FIFO_READ(1U)
+
+#define A_PM_RX_INPUT_FIFO_STR_FWD_EN 0x10019
+
+#define S_ISPI_STR_FWD_EN    0
+#define V_ISPI_STR_FWD_EN(x) ((x) << S_ISPI_STR_FWD_EN)
+#define F_ISPI_STR_FWD_EN    V_ISPI_STR_FWD_EN(1U)
+
+#define A_PM_RX_PRFTCH_ACROSS_BNDLE_EN 0x1001a
+
+#define S_PRFTCH_ACROSS_BNDLE_EN    0
+#define V_PRFTCH_ACROSS_BNDLE_EN(x) ((x) << S_PRFTCH_ACROSS_BNDLE_EN)
+#define F_PRFTCH_ACROSS_BNDLE_EN    V_PRFTCH_ACROSS_BNDLE_EN(1U)
+
+#define A_PM_RX_PRFTCH_WRR_ENABLE 0x1001b
+
+#define S_PRFTCH_WRR_ENABLE    0
+#define V_PRFTCH_WRR_ENABLE(x) ((x) << S_PRFTCH_WRR_ENABLE)
+#define F_PRFTCH_WRR_ENABLE    V_PRFTCH_WRR_ENABLE(1U)
+
+#define A_PM_RX_PRFTCH_WRR_MAX_DEFICIT_CNT 0x1001c
+
+#define S_CHNL1_MAX_DEFICIT_CNT    16
+#define M_CHNL1_MAX_DEFICIT_CNT    0xffffU
+#define V_CHNL1_MAX_DEFICIT_CNT(x) ((x) << S_CHNL1_MAX_DEFICIT_CNT)
+#define G_CHNL1_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL1_MAX_DEFICIT_CNT) & M_CHNL1_MAX_DEFICIT_CNT)
+
+#define S_CHNL0_MAX_DEFICIT_CNT    0
+#define M_CHNL0_MAX_DEFICIT_CNT    0xffffU
+#define V_CHNL0_MAX_DEFICIT_CNT(x) ((x) << S_CHNL0_MAX_DEFICIT_CNT)
+#define G_CHNL0_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL0_MAX_DEFICIT_CNT) & M_CHNL0_MAX_DEFICIT_CNT)
+
+#define A_PM_RX_FEATURE_EN 0x1001d
+
+#define S_PIO_CH_DEFICIT_CTL_EN_RX    0
+#define V_PIO_CH_DEFICIT_CTL_EN_RX(x) ((x) << S_PIO_CH_DEFICIT_CTL_EN_RX)
+#define F_PIO_CH_DEFICIT_CTL_EN_RX    V_PIO_CH_DEFICIT_CTL_EN_RX(1U)
+
+#define A_PM_RX_CH0_OSPI_DEFICIT_THRSHLD 0x1001e
+
+#define S_CH0_OSPI_DEFICIT_THRSHLD    0
+#define M_CH0_OSPI_DEFICIT_THRSHLD    0xfffU
+#define V_CH0_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH0_OSPI_DEFICIT_THRSHLD)
+#define G_CH0_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH0_OSPI_DEFICIT_THRSHLD) & M_CH0_OSPI_DEFICIT_THRSHLD)
+
+#define A_PM_RX_CH1_OSPI_DEFICIT_THRSHLD 0x1001f
+
+#define S_CH1_OSPI_DEFICIT_THRSHLD    0
+#define M_CH1_OSPI_DEFICIT_THRSHLD    0xfffU
+#define V_CH1_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH1_OSPI_DEFICIT_THRSHLD)
+#define G_CH1_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH1_OSPI_DEFICIT_THRSHLD) & M_CH1_OSPI_DEFICIT_THRSHLD)
+
+#define A_PM_RX_INT_CAUSE_MASK_HALT 0x10020
+#define A_PM_RX_DBG_STAT0 0x10021
+
+#define S_RX_RD_I_BUSY    29
+#define V_RX_RD_I_BUSY(x) ((x) << S_RX_RD_I_BUSY)
+#define F_RX_RD_I_BUSY    V_RX_RD_I_BUSY(1U)
+
+#define S_RX_WR_TO_O_BUSY    28
+#define V_RX_WR_TO_O_BUSY(x) ((x) << S_RX_WR_TO_O_BUSY)
+#define F_RX_WR_TO_O_BUSY    V_RX_WR_TO_O_BUSY(1U)
+
+#define S_RX_M_TO_O_BUSY    27
+#define V_RX_M_TO_O_BUSY(x) ((x) << S_RX_M_TO_O_BUSY)
+#define F_RX_M_TO_O_BUSY    V_RX_M_TO_O_BUSY(1U)
+
+#define S_RX_I_TO_M_BUSY    26
+#define V_RX_I_TO_M_BUSY(x) ((x) << S_RX_I_TO_M_BUSY)
+#define F_RX_I_TO_M_BUSY    V_RX_I_TO_M_BUSY(1U)
+
+#define S_RX_PCMD_FB_ONLY    25
+#define V_RX_PCMD_FB_ONLY(x) ((x) << S_RX_PCMD_FB_ONLY)
+#define F_RX_PCMD_FB_ONLY    V_RX_PCMD_FB_ONLY(1U)
+
+#define S_RX_PCMD_MEM    24
+#define V_RX_PCMD_MEM(x) ((x) << S_RX_PCMD_MEM)
+#define F_RX_PCMD_MEM    V_RX_PCMD_MEM(1U)
+
+#define S_RX_PCMD_BYPASS    23
+#define V_RX_PCMD_BYPASS(x) ((x) << S_RX_PCMD_BYPASS)
+#define F_RX_PCMD_BYPASS    V_RX_PCMD_BYPASS(1U)
+
+#define S_RX_PCMD_EOP    22
+#define V_RX_PCMD_EOP(x) ((x) << S_RX_PCMD_EOP)
+#define F_RX_PCMD_EOP    V_RX_PCMD_EOP(1U)
+
+#define S_RX_DUMPLICATE_PCMD_EOP    21
+#define V_RX_DUMPLICATE_PCMD_EOP(x) ((x) << S_RX_DUMPLICATE_PCMD_EOP)
+#define F_RX_DUMPLICATE_PCMD_EOP    V_RX_DUMPLICATE_PCMD_EOP(1U)
+
+#define S_RX_PCMD_EOB    20
+#define V_RX_PCMD_EOB(x) ((x) << S_RX_PCMD_EOB)
+#define F_RX_PCMD_EOB    V_RX_PCMD_EOB(1U)
+
+#define S_RX_PCMD_FB    16
+#define M_RX_PCMD_FB    0xfU
+#define V_RX_PCMD_FB(x) ((x) << S_RX_PCMD_FB)
+#define G_RX_PCMD_FB(x) (((x) >> S_RX_PCMD_FB) & M_RX_PCMD_FB)
+
+#define S_RX_PCMD_LEN    0
+#define M_RX_PCMD_LEN    0xffffU
+#define V_RX_PCMD_LEN(x) ((x) << S_RX_PCMD_LEN)
+#define G_RX_PCMD_LEN(x) (((x) >> S_RX_PCMD_LEN) & M_RX_PCMD_LEN)
+
+#define A_PM_RX_DBG_STAT1 0x10022
+
+#define S_RX_PCMD0_MEM    30
+#define V_RX_PCMD0_MEM(x) ((x) << S_RX_PCMD0_MEM)
+#define F_RX_PCMD0_MEM    V_RX_PCMD0_MEM(1U)
+
+#define S_RX_FREE_OSPI_CNT0    18
+#define M_RX_FREE_OSPI_CNT0    0xfffU
+#define V_RX_FREE_OSPI_CNT0(x) ((x) << S_RX_FREE_OSPI_CNT0)
+#define G_RX_FREE_OSPI_CNT0(x) (((x) >> S_RX_FREE_OSPI_CNT0) & M_RX_FREE_OSPI_CNT0)
+
+#define S_RX_PCMD0_FLIT_LEN    6
+#define M_RX_PCMD0_FLIT_LEN    0xfffU
+#define V_RX_PCMD0_FLIT_LEN(x) ((x) << S_RX_PCMD0_FLIT_LEN)
+#define G_RX_PCMD0_FLIT_LEN(x) (((x) >> S_RX_PCMD0_FLIT_LEN) & M_RX_PCMD0_FLIT_LEN)
+
+#define S_RX_PCMD0_CMD    2
+#define M_RX_PCMD0_CMD    0xfU
+#define V_RX_PCMD0_CMD(x) ((x) << S_RX_PCMD0_CMD)
+#define G_RX_PCMD0_CMD(x) (((x) >> S_RX_PCMD0_CMD) & M_RX_PCMD0_CMD)
+
+#define S_RX_OFIFO_FULL0    1
+#define V_RX_OFIFO_FULL0(x) ((x) << S_RX_OFIFO_FULL0)
+#define F_RX_OFIFO_FULL0    V_RX_OFIFO_FULL0(1U)
+
+#define S_RX_PCMD0_BYPASS    0
+#define V_RX_PCMD0_BYPASS(x) ((x) << S_RX_PCMD0_BYPASS)
+#define F_RX_PCMD0_BYPASS    V_RX_PCMD0_BYPASS(1U)
+
+#define A_PM_RX_DBG_STAT2 0x10023
+
+#define S_RX_PCMD1_MEM    30
+#define V_RX_PCMD1_MEM(x) ((x) << S_RX_PCMD1_MEM)
+#define F_RX_PCMD1_MEM    V_RX_PCMD1_MEM(1U)
+
+#define S_RX_FREE_OSPI_CNT1    18
+#define M_RX_FREE_OSPI_CNT1    0xfffU
+#define V_RX_FREE_OSPI_CNT1(x) ((x) << S_RX_FREE_OSPI_CNT1)
+#define G_RX_FREE_OSPI_CNT1(x) (((x) >> S_RX_FREE_OSPI_CNT1) & M_RX_FREE_OSPI_CNT1)
+
+#define S_RX_PCMD1_FLIT_LEN    6
+#define M_RX_PCMD1_FLIT_LEN    0xfffU
+#define V_RX_PCMD1_FLIT_LEN(x) ((x) << S_RX_PCMD1_FLIT_LEN)
+#define G_RX_PCMD1_FLIT_LEN(x) (((x) >> S_RX_PCMD1_FLIT_LEN) & M_RX_PCMD1_FLIT_LEN)
+
+#define S_RX_PCMD1_CMD    2
+#define M_RX_PCMD1_CMD    0xfU
+#define V_RX_PCMD1_CMD(x) ((x) << S_RX_PCMD1_CMD)
+#define G_RX_PCMD1_CMD(x) (((x) >> S_RX_PCMD1_CMD) & M_RX_PCMD1_CMD)
+
+#define S_RX_OFIFO_FULL1    1
+#define V_RX_OFIFO_FULL1(x) ((x) << S_RX_OFIFO_FULL1)
+#define F_RX_OFIFO_FULL1    V_RX_OFIFO_FULL1(1U)
+
+#define S_RX_PCMD1_BYPASS    0
+#define V_RX_PCMD1_BYPASS(x) ((x) << S_RX_PCMD1_BYPASS)
+#define F_RX_PCMD1_BYPASS    V_RX_PCMD1_BYPASS(1U)
+
+#define A_PM_RX_DBG_STAT3 0x10024
+
+#define S_RX_SET_PCMD_RES_RDY_RD    10
+#define M_RX_SET_PCMD_RES_RDY_RD    0x3U
+#define V_RX_SET_PCMD_RES_RDY_RD(x) ((x) << S_RX_SET_PCMD_RES_RDY_RD)
+#define G_RX_SET_PCMD_RES_RDY_RD(x) (((x) >> S_RX_SET_PCMD_RES_RDY_RD) & M_RX_SET_PCMD_RES_RDY_RD)
+
+#define S_RX_ISSUED_PREFETCH_RD_E_CLR    8
+#define M_RX_ISSUED_PREFETCH_RD_E_CLR    0x3U
+#define V_RX_ISSUED_PREFETCH_RD_E_CLR(x) ((x) << S_RX_ISSUED_PREFETCH_RD_E_CLR)
+#define G_RX_ISSUED_PREFETCH_RD_E_CLR(x) (((x) >> S_RX_ISSUED_PREFETCH_RD_E_CLR) & M_RX_ISSUED_PREFETCH_RD_E_CLR)
+
+#define S_RX_ISSUED_PREFETCH_RD    6
+#define M_RX_ISSUED_PREFETCH_RD    0x3U
+#define V_RX_ISSUED_PREFETCH_RD(x) ((x) << S_RX_ISSUED_PREFETCH_RD)
+#define G_RX_ISSUED_PREFETCH_RD(x) (((x) >> S_RX_ISSUED_PREFETCH_RD) & M_RX_ISSUED_PREFETCH_RD)
+
+#define S_RX_PCMD_RES_RDY    4
+#define M_RX_PCMD_RES_RDY    0x3U
+#define V_RX_PCMD_RES_RDY(x) ((x) << S_RX_PCMD_RES_RDY)
+#define G_RX_PCMD_RES_RDY(x) (((x) >> S_RX_PCMD_RES_RDY) & M_RX_PCMD_RES_RDY)
+
+#define S_RX_DB_VLD    3
+#define V_RX_DB_VLD(x) ((x) << S_RX_DB_VLD)
+#define F_RX_DB_VLD    V_RX_DB_VLD(1U)
+
+#define S_RX_FIRST_BUNDLE    1
+#define M_RX_FIRST_BUNDLE    0x3U
+#define V_RX_FIRST_BUNDLE(x) ((x) << S_RX_FIRST_BUNDLE)
+#define G_RX_FIRST_BUNDLE(x) (((x) >> S_RX_FIRST_BUNDLE) & M_RX_FIRST_BUNDLE)
+
+#define S_RX_SDC_DRDY    0
+#define V_RX_SDC_DRDY(x) ((x) << S_RX_SDC_DRDY)
+#define F_RX_SDC_DRDY    V_RX_SDC_DRDY(1U)
+
+#define A_PM_RX_DBG_STAT4 0x10025
+
+#define S_RX_PCMD_VLD    26
+#define V_RX_PCMD_VLD(x) ((x) << S_RX_PCMD_VLD)
+#define F_RX_PCMD_VLD    V_RX_PCMD_VLD(1U)
+
+#define S_RX_PCMD_TO_CH    25
+#define V_RX_PCMD_TO_CH(x) ((x) << S_RX_PCMD_TO_CH)
+#define F_RX_PCMD_TO_CH    V_RX_PCMD_TO_CH(1U)
+
+#define S_RX_PCMD_FROM_CH    23
+#define M_RX_PCMD_FROM_CH    0x3U
+#define V_RX_PCMD_FROM_CH(x) ((x) << S_RX_PCMD_FROM_CH)
+#define G_RX_PCMD_FROM_CH(x) (((x) >> S_RX_PCMD_FROM_CH) & M_RX_PCMD_FROM_CH)
+
+#define S_RX_LINE    18
+#define M_RX_LINE    0x1fU
+#define V_RX_LINE(x) ((x) << S_RX_LINE)
+#define G_RX_LINE(x) (((x) >> S_RX_LINE) & M_RX_LINE)
+
+#define S_RX_IESPI_TXVALID    14
+#define M_RX_IESPI_TXVALID    0xfU
+#define V_RX_IESPI_TXVALID(x) ((x) << S_RX_IESPI_TXVALID)
+#define G_RX_IESPI_TXVALID(x) (((x) >> S_RX_IESPI_TXVALID) & M_RX_IESPI_TXVALID)
+
+#define S_RX_IESPI_TXFULL    10
+#define M_RX_IESPI_TXFULL    0xfU
+#define V_RX_IESPI_TXFULL(x) ((x) << S_RX_IESPI_TXFULL)
+#define G_RX_IESPI_TXFULL(x) (((x) >> S_RX_IESPI_TXFULL) & M_RX_IESPI_TXFULL)
+
+#define S_RX_PCMD_SRDY    8
+#define M_RX_PCMD_SRDY    0x3U
+#define V_RX_PCMD_SRDY(x) ((x) << S_RX_PCMD_SRDY)
+#define G_RX_PCMD_SRDY(x) (((x) >> S_RX_PCMD_SRDY) & M_RX_PCMD_SRDY)
+
+#define S_RX_PCMD_DRDY    6
+#define M_RX_PCMD_DRDY    0x3U
+#define V_RX_PCMD_DRDY(x) ((x) << S_RX_PCMD_DRDY)
+#define G_RX_PCMD_DRDY(x) (((x) >> S_RX_PCMD_DRDY) & M_RX_PCMD_DRDY)
+
+#define S_RX_PCMD_CMD    2
+#define M_RX_PCMD_CMD    0xfU
+#define V_RX_PCMD_CMD(x) ((x) << S_RX_PCMD_CMD)
+#define G_RX_PCMD_CMD(x) (((x) >> S_RX_PCMD_CMD) & M_RX_PCMD_CMD)
+
+#define S_DUPLICATE    0
+#define M_DUPLICATE    0x3U
+#define V_DUPLICATE(x) ((x) << S_DUPLICATE)
+#define G_DUPLICATE(x) (((x) >> S_DUPLICATE) & M_DUPLICATE)
+
+#define A_PM_RX_DBG_STAT5 0x10026
+
+#define S_RX_ATLST_1_PCMD_CH1    29
+#define V_RX_ATLST_1_PCMD_CH1(x) ((x) << S_RX_ATLST_1_PCMD_CH1)
+#define F_RX_ATLST_1_PCMD_CH1    V_RX_ATLST_1_PCMD_CH1(1U)
+
+#define S_RX_ATLST_1_PCMD_CH0    28
+#define V_RX_ATLST_1_PCMD_CH0(x) ((x) << S_RX_ATLST_1_PCMD_CH0)
+#define F_RX_ATLST_1_PCMD_CH0    V_RX_ATLST_1_PCMD_CH0(1U)
+
+#define S_RX_ISPI_TXVALID    20
+#define M_RX_ISPI_TXVALID    0xfU
+#define V_RX_ISPI_TXVALID(x) ((x) << S_RX_ISPI_TXVALID)
+#define G_RX_ISPI_TXVALID(x) (((x) >> S_RX_ISPI_TXVALID) & M_RX_ISPI_TXVALID)
+
+#define S_RX_ISPI_FULL    16
+#define M_RX_ISPI_FULL    0xfU
+#define V_RX_ISPI_FULL(x) ((x) << S_RX_ISPI_FULL)
+#define G_RX_ISPI_FULL(x) (((x) >> S_RX_ISPI_FULL) & M_RX_ISPI_FULL)
+
+#define S_RX_OSPI_TXVALID    14
+#define M_RX_OSPI_TXVALID    0x3U
+#define V_RX_OSPI_TXVALID(x) ((x) << S_RX_OSPI_TXVALID)
+#define G_RX_OSPI_TXVALID(x) (((x) >> S_RX_OSPI_TXVALID) & M_RX_OSPI_TXVALID)
+
+#define S_RX_OSPI_FULL    12
+#define M_RX_OSPI_FULL    0x3U
+#define V_RX_OSPI_FULL(x) ((x) << S_RX_OSPI_FULL)
+#define G_RX_OSPI_FULL(x) (((x) >> S_RX_OSPI_FULL) & M_RX_OSPI_FULL)
+
+#define S_RX_E_RXVALID    8
+#define M_RX_E_RXVALID    0xfU
+#define V_RX_E_RXVALID(x) ((x) << S_RX_E_RXVALID)
+#define G_RX_E_RXVALID(x) (((x) >> S_RX_E_RXVALID) & M_RX_E_RXVALID)
+
+#define S_RX_E_RXAFULL    4
+#define M_RX_E_RXAFULL    0xfU
+#define V_RX_E_RXAFULL(x) ((x) << S_RX_E_RXAFULL)
+#define G_RX_E_RXAFULL(x) (((x) >> S_RX_E_RXAFULL) & M_RX_E_RXAFULL)
+
+#define S_RX_C_TXVALID    2
+#define M_RX_C_TXVALID    0x3U
+#define V_RX_C_TXVALID(x) ((x) << S_RX_C_TXVALID)
+#define G_RX_C_TXVALID(x) (((x) >> S_RX_C_TXVALID) & M_RX_C_TXVALID)
+
+#define S_RX_C_TXAFULL    0
+#define M_RX_C_TXAFULL    0x3U
+#define V_RX_C_TXAFULL(x) ((x) << S_RX_C_TXAFULL)
+#define G_RX_C_TXAFULL(x) (((x) >> S_RX_C_TXAFULL) & M_RX_C_TXAFULL)
+
+#define A_PM_RX_DBG_STAT6 0x10027
+
+#define S_RX_M_INTRNL_FIFO_CNT    4
+#define M_RX_M_INTRNL_FIFO_CNT    0x3U
+#define V_RX_M_INTRNL_FIFO_CNT(x) ((x) << S_RX_M_INTRNL_FIFO_CNT)
+#define G_RX_M_INTRNL_FIFO_CNT(x) (((x) >> S_RX_M_INTRNL_FIFO_CNT) & M_RX_M_INTRNL_FIFO_CNT)
+
+#define S_RX_M_REQADDRRDY    3
+#define V_RX_M_REQADDRRDY(x) ((x) << S_RX_M_REQADDRRDY)
+#define F_RX_M_REQADDRRDY    V_RX_M_REQADDRRDY(1U)
+
+#define S_RX_M_REQWRITE    2
+#define V_RX_M_REQWRITE(x) ((x) << S_RX_M_REQWRITE)
+#define F_RX_M_REQWRITE    V_RX_M_REQWRITE(1U)
+
+#define S_RX_M_REQDATAVLD    1
+#define V_RX_M_REQDATAVLD(x) ((x) << S_RX_M_REQDATAVLD)
+#define F_RX_M_REQDATAVLD    V_RX_M_REQDATAVLD(1U)
+
+#define S_RX_M_REQDATARDY    0
+#define V_RX_M_REQDATARDY(x) ((x) << S_RX_M_REQDATARDY)
+#define F_RX_M_REQDATARDY    V_RX_M_REQDATARDY(1U)
+
+#define A_PM_RX_DBG_STAT7 0x10028
+
+#define S_RX_PCMD1_FREE_CNT    7
+#define M_RX_PCMD1_FREE_CNT    0x7fU
+#define V_RX_PCMD1_FREE_CNT(x) ((x) << S_RX_PCMD1_FREE_CNT)
+#define G_RX_PCMD1_FREE_CNT(x) (((x) >> S_RX_PCMD1_FREE_CNT) & M_RX_PCMD1_FREE_CNT)
+
+#define S_RX_PCMD0_FREE_CNT    0
+#define M_RX_PCMD0_FREE_CNT    0x7fU
+#define V_RX_PCMD0_FREE_CNT(x) ((x) << S_RX_PCMD0_FREE_CNT)
+#define G_RX_PCMD0_FREE_CNT(x) (((x) >> S_RX_PCMD0_FREE_CNT) & M_RX_PCMD0_FREE_CNT)
+
+#define A_PM_RX_DBG_STAT8 0x10029
+
+#define S_RX_IN_EOP_CNT3    28
+#define M_RX_IN_EOP_CNT3    0xfU
+#define V_RX_IN_EOP_CNT3(x) ((x) << S_RX_IN_EOP_CNT3)
+#define G_RX_IN_EOP_CNT3(x) (((x) >> S_RX_IN_EOP_CNT3) & M_RX_IN_EOP_CNT3)
+
+#define S_RX_IN_EOP_CNT2    24
+#define M_RX_IN_EOP_CNT2    0xfU
+#define V_RX_IN_EOP_CNT2(x) ((x) << S_RX_IN_EOP_CNT2)
+#define G_RX_IN_EOP_CNT2(x) (((x) >> S_RX_IN_EOP_CNT2) & M_RX_IN_EOP_CNT2)
+
+#define S_RX_IN_EOP_CNT1    20
+#define M_RX_IN_EOP_CNT1    0xfU
+#define V_RX_IN_EOP_CNT1(x) ((x) << S_RX_IN_EOP_CNT1)
+#define G_RX_IN_EOP_CNT1(x) (((x) >> S_RX_IN_EOP_CNT1) & M_RX_IN_EOP_CNT1)
+
+#define S_RX_IN_EOP_CNT0    16
+#define M_RX_IN_EOP_CNT0    0xfU
+#define V_RX_IN_EOP_CNT0(x) ((x) << S_RX_IN_EOP_CNT0)
+#define G_RX_IN_EOP_CNT0(x) (((x) >> S_RX_IN_EOP_CNT0) & M_RX_IN_EOP_CNT0)
+
+#define S_RX_IN_SOP_CNT3    12
+#define M_RX_IN_SOP_CNT3    0xfU
+#define V_RX_IN_SOP_CNT3(x) ((x) << S_RX_IN_SOP_CNT3)
+#define G_RX_IN_SOP_CNT3(x) (((x) >> S_RX_IN_SOP_CNT3) & M_RX_IN_SOP_CNT3)
+
+#define S_RX_IN_SOP_CNT2    8
+#define M_RX_IN_SOP_CNT2    0xfU
+#define V_RX_IN_SOP_CNT2(x) ((x) << S_RX_IN_SOP_CNT2)
+#define G_RX_IN_SOP_CNT2(x) (((x) >> S_RX_IN_SOP_CNT2) & M_RX_IN_SOP_CNT2)
+
+#define S_RX_IN_SOP_CNT1    4
+#define M_RX_IN_SOP_CNT1    0xfU
+#define V_RX_IN_SOP_CNT1(x) ((x) << S_RX_IN_SOP_CNT1)
+#define G_RX_IN_SOP_CNT1(x) (((x) >> S_RX_IN_SOP_CNT1) & M_RX_IN_SOP_CNT1)
+
+#define S_RX_IN_SOP_CNT0    0
+#define M_RX_IN_SOP_CNT0    0xfU
+#define V_RX_IN_SOP_CNT0(x) ((x) << S_RX_IN_SOP_CNT0)
+#define G_RX_IN_SOP_CNT0(x) (((x) >> S_RX_IN_SOP_CNT0) & M_RX_IN_SOP_CNT0)
+
+#define A_PM_RX_DBG_STAT9 0x1002a
+
+#define S_RX_RSVD0    28
+#define M_RX_RSVD0    0xfU
+#define V_RX_RSVD0(x) ((x) << S_RX_RSVD0)
+#define G_RX_RSVD0(x) (((x) >> S_RX_RSVD0) & M_RX_RSVD0)
+
+#define S_RX_RSVD1    24
+#define M_RX_RSVD1    0xfU
+#define V_RX_RSVD1(x) ((x) << S_RX_RSVD1)
+#define G_RX_RSVD1(x) (((x) >> S_RX_RSVD1) & M_RX_RSVD1)
+
+#define S_RX_OUT_EOP_CNT1    20
+#define M_RX_OUT_EOP_CNT1    0xfU
+#define V_RX_OUT_EOP_CNT1(x) ((x) << S_RX_OUT_EOP_CNT1)
+#define G_RX_OUT_EOP_CNT1(x) (((x) >> S_RX_OUT_EOP_CNT1) & M_RX_OUT_EOP_CNT1)
+
+#define S_RX_OUT_EOP_CNT0    16
+#define M_RX_OUT_EOP_CNT0    0xfU
+#define V_RX_OUT_EOP_CNT0(x) ((x) << S_RX_OUT_EOP_CNT0)
+#define G_RX_OUT_EOP_CNT0(x) (((x) >> S_RX_OUT_EOP_CNT0) & M_RX_OUT_EOP_CNT0)
+
+#define S_RX_RSVD2    12
+#define M_RX_RSVD2    0xfU
+#define V_RX_RSVD2(x) ((x) << S_RX_RSVD2)
+#define G_RX_RSVD2(x) (((x) >> S_RX_RSVD2) & M_RX_RSVD2)
+
+#define S_RX_RSVD3    8
+#define M_RX_RSVD3    0xfU
+#define V_RX_RSVD3(x) ((x) << S_RX_RSVD3)
+#define G_RX_RSVD3(x) (((x) >> S_RX_RSVD3) & M_RX_RSVD3)
+
+#define S_RX_OUT_SOP_CNT1    4
+#define M_RX_OUT_SOP_CNT1    0xfU
+#define V_RX_OUT_SOP_CNT1(x) ((x) << S_RX_OUT_SOP_CNT1)
+#define G_RX_OUT_SOP_CNT1(x) (((x) >> S_RX_OUT_SOP_CNT1) & M_RX_OUT_SOP_CNT1)
+
+#define S_RX_OUT_SOP_CNT0    0
+#define M_RX_OUT_SOP_CNT0    0xfU
+#define V_RX_OUT_SOP_CNT0(x) ((x) << S_RX_OUT_SOP_CNT0)
+#define G_RX_OUT_SOP_CNT0(x) (((x) >> S_RX_OUT_SOP_CNT0) & M_RX_OUT_SOP_CNT0)
+
+#define A_PM_RX_DBG_STAT10 0x1002b
+
+#define S_RX_CH_DEFICIT_BLOWED    24
+#define V_RX_CH_DEFICIT_BLOWED(x) ((x) << S_RX_CH_DEFICIT_BLOWED)
+#define F_RX_CH_DEFICIT_BLOWED    V_RX_CH_DEFICIT_BLOWED(1U)
+
+#define S_RX_CH1_DEFICIT    12
+#define M_RX_CH1_DEFICIT    0xfffU
+#define V_RX_CH1_DEFICIT(x) ((x) << S_RX_CH1_DEFICIT)
+#define G_RX_CH1_DEFICIT(x) (((x) >> S_RX_CH1_DEFICIT) & M_RX_CH1_DEFICIT)
+
+#define S_RX_CH0_DEFICIT    0
+#define M_RX_CH0_DEFICIT    0xfffU
+#define V_RX_CH0_DEFICIT(x) ((x) << S_RX_CH0_DEFICIT)
+#define G_RX_CH0_DEFICIT(x) (((x) >> S_RX_CH0_DEFICIT) & M_RX_CH0_DEFICIT)
+
+#define A_PM_RX_DBG_STAT11 0x1002c
+
+#define S_RX_BUNDLE_LEN_SRDY    30
+#define M_RX_BUNDLE_LEN_SRDY    0x3U
+#define V_RX_BUNDLE_LEN_SRDY(x) ((x) << S_RX_BUNDLE_LEN_SRDY)
+#define G_RX_BUNDLE_LEN_SRDY(x) (((x) >> S_RX_BUNDLE_LEN_SRDY) & M_RX_BUNDLE_LEN_SRDY)
+
+#define S_RX_RSVD11_1    28
+#define M_RX_RSVD11_1    0x3U
+#define V_RX_RSVD11_1(x) ((x) << S_RX_RSVD11_1)
+#define G_RX_RSVD11_1(x) (((x) >> S_RX_RSVD11_1) & M_RX_RSVD11_1)
+
+#define S_RX_BUNDLE_LEN1    16
+#define M_RX_BUNDLE_LEN1    0xfffU
+#define V_RX_BUNDLE_LEN1(x) ((x) << S_RX_BUNDLE_LEN1)
+#define G_RX_BUNDLE_LEN1(x) (((x) >> S_RX_BUNDLE_LEN1) & M_RX_BUNDLE_LEN1)
+
+#define S_RX_RSVD11    12
+#define M_RX_RSVD11    0xfU
+#define V_RX_RSVD11(x) ((x) << S_RX_RSVD11)
+#define G_RX_RSVD11(x) (((x) >> S_RX_RSVD11) & M_RX_RSVD11)
+
+#define S_RX_BUNDLE_LEN0    0
+#define M_RX_BUNDLE_LEN0    0xfffU
+#define V_RX_BUNDLE_LEN0(x) ((x) << S_RX_BUNDLE_LEN0)
+#define G_RX_BUNDLE_LEN0(x) (((x) >> S_RX_BUNDLE_LEN0) & M_RX_BUNDLE_LEN0)
+
+/* registers for module PM_TX */
+#define PM_TX_BASE_ADDR 0x8fe0
+
+#define A_PM_TX_CFG 0x8fe0
+
+#define S_CH3_OUTPUT    17
+#define M_CH3_OUTPUT    0x1fU
+#define V_CH3_OUTPUT(x) ((x) << S_CH3_OUTPUT)
+#define G_CH3_OUTPUT(x) (((x) >> S_CH3_OUTPUT) & M_CH3_OUTPUT)
+
+#define A_PM_TX_MODE 0x8fe4
+
+#define S_CONG_THRESH3    25
+#define M_CONG_THRESH3    0x7fU
+#define V_CONG_THRESH3(x) ((x) << S_CONG_THRESH3)
+#define G_CONG_THRESH3(x) (((x) >> S_CONG_THRESH3) & M_CONG_THRESH3)
+
+#define S_CONG_THRESH2    18
+#define M_CONG_THRESH2    0x7fU
+#define V_CONG_THRESH2(x) ((x) << S_CONG_THRESH2)
+#define G_CONG_THRESH2(x) (((x) >> S_CONG_THRESH2) & M_CONG_THRESH2)
+
+#define S_CONG_THRESH1    11
+#define M_CONG_THRESH1    0x7fU
+#define V_CONG_THRESH1(x) ((x) << S_CONG_THRESH1)
+#define G_CONG_THRESH1(x) (((x) >> S_CONG_THRESH1) & M_CONG_THRESH1)
+
+#define S_CONG_THRESH0    4
+#define M_CONG_THRESH0    0x7fU
+#define V_CONG_THRESH0(x) ((x) << S_CONG_THRESH0)
+#define G_CONG_THRESH0(x) (((x) >> S_CONG_THRESH0) & M_CONG_THRESH0)
+
+#define S_TX_USE_BUNDLE_LEN    3
+#define V_TX_USE_BUNDLE_LEN(x) ((x) << S_TX_USE_BUNDLE_LEN)
+#define F_TX_USE_BUNDLE_LEN    V_TX_USE_BUNDLE_LEN(1U)
+
+#define S_STAT_CHANNEL    1
+#define M_STAT_CHANNEL    0x3U
+#define V_STAT_CHANNEL(x) ((x) << S_STAT_CHANNEL)
+#define G_STAT_CHANNEL(x) (((x) >> S_STAT_CHANNEL) & M_STAT_CHANNEL)
+
+#define A_PM_TX_STAT_CONFIG 0x8fe8
+#define A_PM_TX_STAT_COUNT 0x8fec
+#define A_PM_TX_STAT_LSB 0x8ff0
+#define A_PM_TX_DBG_CTRL 0x8ff0
+
+#define S_OSPIWRBUSY    21
+#define M_OSPIWRBUSY    0xfU
+#define V_OSPIWRBUSY(x) ((x) << S_OSPIWRBUSY)
+#define G_OSPIWRBUSY(x) (((x) >> S_OSPIWRBUSY) & M_OSPIWRBUSY)
+
+#define A_PM_TX_STAT_MSB 0x8ff4
+#define A_PM_TX_DBG_DATA 0x8ff4
+#define A_PM_TX_INT_ENABLE 0x8ff8
+
+#define S_PCMD_LEN_OVFL0    31
+#define V_PCMD_LEN_OVFL0(x) ((x) << S_PCMD_LEN_OVFL0)
+#define F_PCMD_LEN_OVFL0    V_PCMD_LEN_OVFL0(1U)
+
+#define S_PCMD_LEN_OVFL1    30
+#define V_PCMD_LEN_OVFL1(x) ((x) << S_PCMD_LEN_OVFL1)
+#define F_PCMD_LEN_OVFL1    V_PCMD_LEN_OVFL1(1U)
+
+#define S_PCMD_LEN_OVFL2    29
+#define V_PCMD_LEN_OVFL2(x) ((x) << S_PCMD_LEN_OVFL2)
+#define F_PCMD_LEN_OVFL2    V_PCMD_LEN_OVFL2(1U)
+
+#define S_ZERO_C_CMD_ERRO    28
+#define V_ZERO_C_CMD_ERRO(x) ((x) << S_ZERO_C_CMD_ERRO)
+#define F_ZERO_C_CMD_ERRO    V_ZERO_C_CMD_ERRO(1U)
+
+#define S_ICSPI0_FIFO2X_RX_FRAMING_ERROR    27
+#define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR)
+#define F_ICSPI0_FIFO2X_RX_FRAMING_ERROR    V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U)
+
+#define S_ICSPI1_FIFO2X_RX_FRAMING_ERROR    26
+#define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR)
+#define F_ICSPI1_FIFO2X_RX_FRAMING_ERROR    V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U)
+
+#define S_ICSPI2_FIFO2X_RX_FRAMING_ERROR    25
+#define V_ICSPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI2_FIFO2X_RX_FRAMING_ERROR)
+#define F_ICSPI2_FIFO2X_RX_FRAMING_ERROR    V_ICSPI2_FIFO2X_RX_FRAMING_ERROR(1U)
+
+#define S_ICSPI3_FIFO2X_RX_FRAMING_ERROR    24
+#define V_ICSPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI3_FIFO2X_RX_FRAMING_ERROR)
+#define F_ICSPI3_FIFO2X_RX_FRAMING_ERROR    V_ICSPI3_FIFO2X_RX_FRAMING_ERROR(1U)
+
+#define S_ICSPI0_RX_FRAMING_ERROR    23
+#define V_ICSPI0_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_RX_FRAMING_ERROR)
+#define F_ICSPI0_RX_FRAMING_ERROR    V_ICSPI0_RX_FRAMING_ERROR(1U)
+
+#define S_ICSPI1_RX_FRAMING_ERROR    22
+#define V_ICSPI1_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_RX_FRAMING_ERROR)
+#define F_ICSPI1_RX_FRAMING_ERROR    V_ICSPI1_RX_FRAMING_ERROR(1U)
+
+#define S_ICSPI2_RX_FRAMING_ERROR    21
+#define V_ICSPI2_RX_FRAMING_ERROR(x) ((x) << S_ICSPI2_RX_FRAMING_ERROR)
+#define F_ICSPI2_RX_FRAMING_ERROR    V_ICSPI2_RX_FRAMING_ERROR(1U)
+
+#define S_ICSPI3_RX_FRAMING_ERROR    20
+#define V_ICSPI3_RX_FRAMING_ERROR(x) ((x) << S_ICSPI3_RX_FRAMING_ERROR)
+#define F_ICSPI3_RX_FRAMING_ERROR    V_ICSPI3_RX_FRAMING_ERROR(1U)
+
+#define S_ICSPI0_TX_FRAMING_ERROR    19
+#define V_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_ICSPI0_TX_FRAMING_ERROR)
+#define F_ICSPI0_TX_FRAMING_ERROR    V_ICSPI0_TX_FRAMING_ERROR(1U)
+
+#define S_ICSPI1_TX_FRAMING_ERROR    18
+#define V_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_ICSPI1_TX_FRAMING_ERROR)
+#define F_ICSPI1_TX_FRAMING_ERROR    V_ICSPI1_TX_FRAMING_ERROR(1U)
+
+#define S_ICSPI2_TX_FRAMING_ERROR    17
+#define V_ICSPI2_TX_FRAMING_ERROR(x) ((x) << S_ICSPI2_TX_FRAMING_ERROR)
+#define F_ICSPI2_TX_FRAMING_ERROR    V_ICSPI2_TX_FRAMING_ERROR(1U)
+
+#define S_ICSPI3_TX_FRAMING_ERROR    16
+#define V_ICSPI3_TX_FRAMING_ERROR(x) ((x) << S_ICSPI3_TX_FRAMING_ERROR)
+#define F_ICSPI3_TX_FRAMING_ERROR    V_ICSPI3_TX_FRAMING_ERROR(1U)
+
+#define S_OESPI0_RX_FRAMING_ERROR    15
+#define V_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_OESPI0_RX_FRAMING_ERROR)
+#define F_OESPI0_RX_FRAMING_ERROR    V_OESPI0_RX_FRAMING_ERROR(1U)
+
+#define S_OESPI1_RX_FRAMING_ERROR    14
+#define V_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_OESPI1_RX_FRAMING_ERROR)
+#define F_OESPI1_RX_FRAMING_ERROR    V_OESPI1_RX_FRAMING_ERROR(1U)
+
+#define S_OESPI2_RX_FRAMING_ERROR    13
+#define V_OESPI2_RX_FRAMING_ERROR(x) ((x) << S_OESPI2_RX_FRAMING_ERROR)
+#define F_OESPI2_RX_FRAMING_ERROR    V_OESPI2_RX_FRAMING_ERROR(1U)
+
+#define S_OESPI3_RX_FRAMING_ERROR    12
+#define V_OESPI3_RX_FRAMING_ERROR(x) ((x) << S_OESPI3_RX_FRAMING_ERROR)
+#define F_OESPI3_RX_FRAMING_ERROR    V_OESPI3_RX_FRAMING_ERROR(1U)
+
+#define S_OESPI0_TX_FRAMING_ERROR    11
+#define V_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_TX_FRAMING_ERROR)
+#define F_OESPI0_TX_FRAMING_ERROR    V_OESPI0_TX_FRAMING_ERROR(1U)
+
+#define S_OESPI1_TX_FRAMING_ERROR    10
+#define V_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_TX_FRAMING_ERROR)
+#define F_OESPI1_TX_FRAMING_ERROR    V_OESPI1_TX_FRAMING_ERROR(1U)
+
+#define S_OESPI2_TX_FRAMING_ERROR    9
+#define V_OESPI2_TX_FRAMING_ERROR(x) ((x) << S_OESPI2_TX_FRAMING_ERROR)
+#define F_OESPI2_TX_FRAMING_ERROR    V_OESPI2_TX_FRAMING_ERROR(1U)
+
+#define S_OESPI3_TX_FRAMING_ERROR    8
+#define V_OESPI3_TX_FRAMING_ERROR(x) ((x) << S_OESPI3_TX_FRAMING_ERROR)
+#define F_OESPI3_TX_FRAMING_ERROR    V_OESPI3_TX_FRAMING_ERROR(1U)
+
+#define S_OESPI0_OFIFO2X_TX_FRAMING_ERROR    7
+#define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR)
+#define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR    V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
+
+#define S_OESPI1_OFIFO2X_TX_FRAMING_ERROR    6
+#define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
+#define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR    V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
+
+#define S_OESPI2_OFIFO2X_TX_FRAMING_ERROR    5
+#define V_OESPI2_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI2_OFIFO2X_TX_FRAMING_ERROR)
+#define F_OESPI2_OFIFO2X_TX_FRAMING_ERROR    V_OESPI2_OFIFO2X_TX_FRAMING_ERROR(1U)
+
+#define S_OESPI3_OFIFO2X_TX_FRAMING_ERROR    4
+#define V_OESPI3_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI3_OFIFO2X_TX_FRAMING_ERROR)
+#define F_OESPI3_OFIFO2X_TX_FRAMING_ERROR    V_OESPI3_OFIFO2X_TX_FRAMING_ERROR(1U)
+
+#define S_OESPI_PAR_ERROR    3
+#define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR)
+#define F_OESPI_PAR_ERROR    V_OESPI_PAR_ERROR(1U)
+
+#define S_ICSPI_PAR_ERROR    1
+#define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR)
+#define F_ICSPI_PAR_ERROR    V_ICSPI_PAR_ERROR(1U)
+
+#define S_C_PCMD_PAR_ERROR    0
+#define V_C_PCMD_PAR_ERROR(x) ((x) << S_C_PCMD_PAR_ERROR)
+#define F_C_PCMD_PAR_ERROR    V_C_PCMD_PAR_ERROR(1U)
+
+#define A_PM_TX_INT_CAUSE 0x8ffc
+
+#define S_ZERO_C_CMD_ERROR    28
+#define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR)
+#define F_ZERO_C_CMD_ERROR    V_ZERO_C_CMD_ERROR(1U)
+
+#define S_OSPI_OR_BUNDLE_LEN_PAR_ERR    3
+#define V_OSPI_OR_BUNDLE_LEN_PAR_ERR(x) ((x) << S_OSPI_OR_BUNDLE_LEN_PAR_ERR)
+#define F_OSPI_OR_BUNDLE_LEN_PAR_ERR    V_OSPI_OR_BUNDLE_LEN_PAR_ERR(1U)
+
+#define A_PM_TX_ISPI_DBG_4B_DATA0 0x10000
+#define A_PM_TX_ISPI_DBG_4B_DATA1 0x10001
+#define A_PM_TX_ISPI_DBG_4B_DATA2 0x10002
+#define A_PM_TX_ISPI_DBG_4B_DATA3 0x10003
+#define A_PM_TX_ISPI_DBG_4B_DATA4 0x10004
+#define A_PM_TX_ISPI_DBG_4B_DATA5 0x10005
+#define A_PM_TX_ISPI_DBG_4B_DATA6 0x10006
+#define A_PM_TX_ISPI_DBG_4B_DATA7 0x10007
+#define A_PM_TX_ISPI_DBG_4B_DATA8 0x10008
+#define A_PM_TX_OSPI_DBG_4B_DATA0 0x10009
+#define A_PM_TX_OSPI_DBG_4B_DATA1 0x1000a
+#define A_PM_TX_OSPI_DBG_4B_DATA2 0x1000b
+#define A_PM_TX_OSPI_DBG_4B_DATA3 0x1000c
+#define A_PM_TX_OSPI_DBG_4B_DATA4 0x1000d
+#define A_PM_TX_OSPI_DBG_4B_DATA5 0x1000e
+#define A_PM_TX_OSPI_DBG_4B_DATA6 0x1000f
+#define A_PM_TX_OSPI_DBG_4B_DATA7 0x10010
+#define A_PM_TX_OSPI_DBG_4B_DATA8 0x10011
+#define A_PM_TX_OSPI_DBG_4B_DATA9 0x10012
+#define A_PM_TX_OSPI_DBG_4B_DATA10 0x10013
+#define A_PM_TX_OSPI_DBG_4B_DATA11 0x10014
+#define A_PM_TX_OSPI_DBG_4B_DATA12 0x10015
+#define A_PM_TX_OSPI_DBG_4B_DATA13 0x10016
+#define A_PM_TX_OSPI_DBG_4B_DATA14 0x10017
+#define A_PM_TX_OSPI_DBG_4B_DATA15 0x10018
+#define A_PM_TX_OSPI_DBG_4B_DATA16 0x10019
+#define A_PM_TX_DBG_STAT_MSB 0x1001a
+#define A_PM_TX_DBG_STAT_LSB 0x1001b
+#define A_PM_TX_DBG_RSVD_FLIT_CNT 0x1001c
+#define A_PM_TX_SDC_EN 0x1001d
+#define A_PM_TX_INOUT_FIFO_DBG_CHNL_SEL 0x1001e
+#define A_PM_TX_INOUT_FIFO_DBG_WR 0x1001f
+#define A_PM_TX_INPUT_FIFO_STR_FWD_EN 0x10020
+#define A_PM_TX_FEATURE_EN 0x10021
+
+#define S_PIO_CH_DEFICIT_CTL_EN    2
+#define V_PIO_CH_DEFICIT_CTL_EN(x) ((x) << S_PIO_CH_DEFICIT_CTL_EN)
+#define F_PIO_CH_DEFICIT_CTL_EN    V_PIO_CH_DEFICIT_CTL_EN(1U)
+
+#define S_PIO_WRR_BASED_PRFTCH_EN    1
+#define V_PIO_WRR_BASED_PRFTCH_EN(x) ((x) << S_PIO_WRR_BASED_PRFTCH_EN)
+#define F_PIO_WRR_BASED_PRFTCH_EN    V_PIO_WRR_BASED_PRFTCH_EN(1U)
+
+#define A_PM_TX_T5_PM_TX_INT_ENABLE 0x10022
+
+#define S_OSPI_OVERFLOW3    7
+#define V_OSPI_OVERFLOW3(x) ((x) << S_OSPI_OVERFLOW3)
+#define F_OSPI_OVERFLOW3    V_OSPI_OVERFLOW3(1U)
+
+#define S_OSPI_OVERFLOW2    6
+#define V_OSPI_OVERFLOW2(x) ((x) << S_OSPI_OVERFLOW2)
+#define F_OSPI_OVERFLOW2    V_OSPI_OVERFLOW2(1U)
+
+#define S_M_INTFPERREN    3
+#define V_M_INTFPERREN(x) ((x) << S_M_INTFPERREN)
+#define F_M_INTFPERREN    V_M_INTFPERREN(1U)
+
+#define S_BUNDLE_LEN_PARERR_EN    2
+#define V_BUNDLE_LEN_PARERR_EN(x) ((x) << S_BUNDLE_LEN_PARERR_EN)
+#define F_BUNDLE_LEN_PARERR_EN    V_BUNDLE_LEN_PARERR_EN(1U)
+
+#define S_BUNDLE_LEN_OVFL_EN    1
+#define V_BUNDLE_LEN_OVFL_EN(x) ((x) << S_BUNDLE_LEN_OVFL_EN)
+#define F_BUNDLE_LEN_OVFL_EN    V_BUNDLE_LEN_OVFL_EN(1U)
+
+#define S_SDC_ERR_EN    0
+#define V_SDC_ERR_EN(x) ((x) << S_SDC_ERR_EN)
+#define F_SDC_ERR_EN    V_SDC_ERR_EN(1U)
+
+#define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD0 0x10023
+#define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD1 0x10024
+#define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD2 0x10025
+#define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD3 0x10026
+#define A_PM_TX_CH0_OSPI_DEFICIT_THRSHLD 0x10027
+#define A_PM_TX_CH1_OSPI_DEFICIT_THRSHLD 0x10028
+#define A_PM_TX_CH2_OSPI_DEFICIT_THRSHLD 0x10029
+
+#define S_CH2_OSPI_DEFICIT_THRSHLD    0
+#define M_CH2_OSPI_DEFICIT_THRSHLD    0xfffU
+#define V_CH2_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH2_OSPI_DEFICIT_THRSHLD)
+#define G_CH2_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH2_OSPI_DEFICIT_THRSHLD) & M_CH2_OSPI_DEFICIT_THRSHLD)
+
+#define A_PM_TX_CH3_OSPI_DEFICIT_THRSHLD 0x1002a
+
+#define S_CH3_OSPI_DEFICIT_THRSHLD    0
+#define M_CH3_OSPI_DEFICIT_THRSHLD    0xfffU
+#define V_CH3_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH3_OSPI_DEFICIT_THRSHLD)
+#define G_CH3_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH3_OSPI_DEFICIT_THRSHLD) & M_CH3_OSPI_DEFICIT_THRSHLD)
+
+#define A_PM_TX_INT_CAUSE_MASK_HALT 0x1002b
+#define A_PM_TX_DBG_STAT0 0x1002c
+
+#define S_RD_I_BUSY    28
+#define V_RD_I_BUSY(x) ((x) << S_RD_I_BUSY)
+#define F_RD_I_BUSY    V_RD_I_BUSY(1U)
+
+#define S_WR_O_ONLY    27
+#define V_WR_O_ONLY(x) ((x) << S_WR_O_ONLY)
+#define F_WR_O_ONLY    V_WR_O_ONLY(1U)
+
+#define S_M_TO_BUSY    26
+#define V_M_TO_BUSY(x) ((x) << S_M_TO_BUSY)
+#define F_M_TO_BUSY    V_M_TO_BUSY(1U)
+
+#define S_I_TO_M_BUSY    25
+#define V_I_TO_M_BUSY(x) ((x) << S_I_TO_M_BUSY)
+#define F_I_TO_M_BUSY    V_I_TO_M_BUSY(1U)
+
+#define S_PCMD_FB_ONLY    24
+#define V_PCMD_FB_ONLY(x) ((x) << S_PCMD_FB_ONLY)
+#define F_PCMD_FB_ONLY    V_PCMD_FB_ONLY(1U)
+
+#define S_PCMD_MEM    23
+#define V_PCMD_MEM(x) ((x) << S_PCMD_MEM)
+#define F_PCMD_MEM    V_PCMD_MEM(1U)
+
+#define S_PCMD_BYPASS    22
+#define V_PCMD_BYPASS(x) ((x) << S_PCMD_BYPASS)
+#define F_PCMD_BYPASS    V_PCMD_BYPASS(1U)
+
+#define S_PCMD_EOP    21
+#define V_PCMD_EOP(x) ((x) << S_PCMD_EOP)
+#define F_PCMD_EOP    V_PCMD_EOP(1U)
+
+#define S_PCMD_END_BUNDLE    20
+#define V_PCMD_END_BUNDLE(x) ((x) << S_PCMD_END_BUNDLE)
+#define F_PCMD_END_BUNDLE    V_PCMD_END_BUNDLE(1U)
+
+#define S_PCMD_FB_CMD    16
+#define M_PCMD_FB_CMD    0xfU
+#define V_PCMD_FB_CMD(x) ((x) << S_PCMD_FB_CMD)
+#define G_PCMD_FB_CMD(x) (((x) >> S_PCMD_FB_CMD) & M_PCMD_FB_CMD)
+
+#define S_CUR_PCMD_LEN    0
+#define M_CUR_PCMD_LEN    0xffffU
+#define V_CUR_PCMD_LEN(x) ((x) << S_CUR_PCMD_LEN)
+#define G_CUR_PCMD_LEN(x) (((x) >> S_CUR_PCMD_LEN) & M_CUR_PCMD_LEN)
+
+#define A_PM_TX_DBG_STAT1 0x1002d
+
+#define S_PCMD_MEM0    31
+#define V_PCMD_MEM0(x) ((x) << S_PCMD_MEM0)
+#define F_PCMD_MEM0    V_PCMD_MEM0(1U)
+
+#define S_FREE_OESPI_CNT0    19
+#define M_FREE_OESPI_CNT0    0xfffU
+#define V_FREE_OESPI_CNT0(x) ((x) << S_FREE_OESPI_CNT0)
+#define G_FREE_OESPI_CNT0(x) (((x) >> S_FREE_OESPI_CNT0) & M_FREE_OESPI_CNT0)
+
+#define S_PCMD_FLIT_LEN0    7
+#define M_PCMD_FLIT_LEN0    0xfffU
+#define V_PCMD_FLIT_LEN0(x) ((x) << S_PCMD_FLIT_LEN0)
+#define G_PCMD_FLIT_LEN0(x) (((x) >> S_PCMD_FLIT_LEN0) & M_PCMD_FLIT_LEN0)
+
+#define S_PCMD_CMD0    3
+#define M_PCMD_CMD0    0xfU
+#define V_PCMD_CMD0(x) ((x) << S_PCMD_CMD0)
+#define G_PCMD_CMD0(x) (((x) >> S_PCMD_CMD0) & M_PCMD_CMD0)
+
+#define S_OFIFO_FULL0    2
+#define V_OFIFO_FULL0(x) ((x) << S_OFIFO_FULL0)
+#define F_OFIFO_FULL0    V_OFIFO_FULL0(1U)
+
+#define S_GCSUM_DRDY0    1
+#define V_GCSUM_DRDY0(x) ((x) << S_GCSUM_DRDY0)
+#define F_GCSUM_DRDY0    V_GCSUM_DRDY0(1U)
+
+#define S_BYPASS0    0
+#define V_BYPASS0(x) ((x) << S_BYPASS0)
+#define F_BYPASS0    V_BYPASS0(1U)
+
+#define A_PM_TX_DBG_STAT2 0x1002e
+
+#define S_PCMD_MEM1    31
+#define V_PCMD_MEM1(x) ((x) << S_PCMD_MEM1)
+#define F_PCMD_MEM1    V_PCMD_MEM1(1U)
+
+#define S_FREE_OESPI_CNT1    19
+#define M_FREE_OESPI_CNT1    0xfffU
+#define V_FREE_OESPI_CNT1(x) ((x) << S_FREE_OESPI_CNT1)
+#define G_FREE_OESPI_CNT1(x) (((x) >> S_FREE_OESPI_CNT1) & M_FREE_OESPI_CNT1)
+
+#define S_PCMD_FLIT_LEN1    7
+#define M_PCMD_FLIT_LEN1    0xfffU
+#define V_PCMD_FLIT_LEN1(x) ((x) << S_PCMD_FLIT_LEN1)
+#define G_PCMD_FLIT_LEN1(x) (((x) >> S_PCMD_FLIT_LEN1) & M_PCMD_FLIT_LEN1)
+
+#define S_PCMD_CMD1    3
+#define M_PCMD_CMD1    0xfU
+#define V_PCMD_CMD1(x) ((x) << S_PCMD_CMD1)
+#define G_PCMD_CMD1(x) (((x) >> S_PCMD_CMD1) & M_PCMD_CMD1)
+
+#define S_OFIFO_FULL1    2
+#define V_OFIFO_FULL1(x) ((x) << S_OFIFO_FULL1)
+#define F_OFIFO_FULL1    V_OFIFO_FULL1(1U)
+
+#define S_GCSUM_DRDY1    1
+#define V_GCSUM_DRDY1(x) ((x) << S_GCSUM_DRDY1)
+#define F_GCSUM_DRDY1    V_GCSUM_DRDY1(1U)
+
+#define S_BYPASS1    0
+#define V_BYPASS1(x) ((x) << S_BYPASS1)
+#define F_BYPASS1    V_BYPASS1(1U)
+
+#define A_PM_TX_DBG_STAT3 0x1002f
+
+#define S_PCMD_MEM2    31
+#define V_PCMD_MEM2(x) ((x) << S_PCMD_MEM2)
+#define F_PCMD_MEM2    V_PCMD_MEM2(1U)
+
+#define S_FREE_OESPI_CNT2    19
+#define M_FREE_OESPI_CNT2    0xfffU
+#define V_FREE_OESPI_CNT2(x) ((x) << S_FREE_OESPI_CNT2)
+#define G_FREE_OESPI_CNT2(x) (((x) >> S_FREE_OESPI_CNT2) & M_FREE_OESPI_CNT2)
+
+#define S_PCMD_FLIT_LEN2    7
+#define M_PCMD_FLIT_LEN2    0xfffU
+#define V_PCMD_FLIT_LEN2(x) ((x) << S_PCMD_FLIT_LEN2)
+#define G_PCMD_FLIT_LEN2(x) (((x) >> S_PCMD_FLIT_LEN2) & M_PCMD_FLIT_LEN2)
+
+#define S_PCMD_CMD2    3
+#define M_PCMD_CMD2    0xfU
+#define V_PCMD_CMD2(x) ((x) << S_PCMD_CMD2)
+#define G_PCMD_CMD2(x) (((x) >> S_PCMD_CMD2) & M_PCMD_CMD2)
+
+#define S_OFIFO_FULL2    2
+#define V_OFIFO_FULL2(x) ((x) << S_OFIFO_FULL2)
+#define F_OFIFO_FULL2    V_OFIFO_FULL2(1U)
+
+#define S_GCSUM_DRDY2    1
+#define V_GCSUM_DRDY2(x) ((x) << S_GCSUM_DRDY2)
+#define F_GCSUM_DRDY2    V_GCSUM_DRDY2(1U)
+
+#define S_BYPASS2    0
+#define V_BYPASS2(x) ((x) << S_BYPASS2)
+#define F_BYPASS2    V_BYPASS2(1U)
+
+#define A_PM_TX_DBG_STAT4 0x10030
+
+#define S_PCMD_MEM3    31
+#define V_PCMD_MEM3(x) ((x) << S_PCMD_MEM3)
+#define F_PCMD_MEM3    V_PCMD_MEM3(1U)
+
+#define S_FREE_OESPI_CNT3    19
+#define M_FREE_OESPI_CNT3    0xfffU
+#define V_FREE_OESPI_CNT3(x) ((x) << S_FREE_OESPI_CNT3)
+#define G_FREE_OESPI_CNT3(x) (((x) >> S_FREE_OESPI_CNT3) & M_FREE_OESPI_CNT3)
+
+#define S_PCMD_FLIT_LEN3    7
+#define M_PCMD_FLIT_LEN3    0xfffU
+#define V_PCMD_FLIT_LEN3(x) ((x) << S_PCMD_FLIT_LEN3)
+#define G_PCMD_FLIT_LEN3(x) (((x) >> S_PCMD_FLIT_LEN3) & M_PCMD_FLIT_LEN3)
+
+#define S_PCMD_CMD3    3
+#define M_PCMD_CMD3    0xfU
+#define V_PCMD_CMD3(x) ((x) << S_PCMD_CMD3)
+#define G_PCMD_CMD3(x) (((x) >> S_PCMD_CMD3) & M_PCMD_CMD3)
+
+#define S_OFIFO_FULL3    2
+#define V_OFIFO_FULL3(x) ((x) << S_OFIFO_FULL3)
+#define F_OFIFO_FULL3    V_OFIFO_FULL3(1U)
+
+#define S_GCSUM_DRDY3    1
+#define V_GCSUM_DRDY3(x) ((x) << S_GCSUM_DRDY3)
+#define F_GCSUM_DRDY3    V_GCSUM_DRDY3(1U)
+
+#define S_BYPASS3    0
+#define V_BYPASS3(x) ((x) << S_BYPASS3)
+#define F_BYPASS3    V_BYPASS3(1U)
+
+#define A_PM_TX_DBG_STAT5 0x10031
+
+#define S_SET_PCMD_RES_RDY_RD    24
+#define M_SET_PCMD_RES_RDY_RD    0xfU
+#define V_SET_PCMD_RES_RDY_RD(x) ((x) << S_SET_PCMD_RES_RDY_RD)
+#define G_SET_PCMD_RES_RDY_RD(x) (((x) >> S_SET_PCMD_RES_RDY_RD) & M_SET_PCMD_RES_RDY_RD)
+
+#define S_ISSUED_PREF_RD_ER_CLR    20
+#define M_ISSUED_PREF_RD_ER_CLR    0xfU
+#define V_ISSUED_PREF_RD_ER_CLR(x) ((x) << S_ISSUED_PREF_RD_ER_CLR)
+#define G_ISSUED_PREF_RD_ER_CLR(x) (((x) >> S_ISSUED_PREF_RD_ER_CLR) & M_ISSUED_PREF_RD_ER_CLR)
+
+#define S_ISSUED_PREF_RD    16
+#define M_ISSUED_PREF_RD    0xfU
+#define V_ISSUED_PREF_RD(x) ((x) << S_ISSUED_PREF_RD)
+#define G_ISSUED_PREF_RD(x) (((x) >> S_ISSUED_PREF_RD) & M_ISSUED_PREF_RD)
+
+#define S_PCMD_RES_RDY    12
+#define M_PCMD_RES_RDY    0xfU
+#define V_PCMD_RES_RDY(x) ((x) << S_PCMD_RES_RDY)
+#define G_PCMD_RES_RDY(x) (((x) >> S_PCMD_RES_RDY) & M_PCMD_RES_RDY)
+
+#define S_DB_VLD    11
+#define V_DB_VLD(x) ((x) << S_DB_VLD)
+#define F_DB_VLD    V_DB_VLD(1U)
+
+#define S_INJECT0_DRDY    10
+#define V_INJECT0_DRDY(x) ((x) << S_INJECT0_DRDY)
+#define F_INJECT0_DRDY    V_INJECT0_DRDY(1U)
+
+#define S_INJECT1_DRDY    9
+#define V_INJECT1_DRDY(x) ((x) << S_INJECT1_DRDY)
+#define F_INJECT1_DRDY    V_INJECT1_DRDY(1U)
+
+#define S_FIRST_BUNDLE    5
+#define M_FIRST_BUNDLE    0xfU
+#define V_FIRST_BUNDLE(x) ((x) << S_FIRST_BUNDLE)
+#define G_FIRST_BUNDLE(x) (((x) >> S_FIRST_BUNDLE) & M_FIRST_BUNDLE)
+
+#define S_GCSUM_MORE_THAN_2_LEFT    1
+#define M_GCSUM_MORE_THAN_2_LEFT    0xfU
+#define V_GCSUM_MORE_THAN_2_LEFT(x) ((x) << S_GCSUM_MORE_THAN_2_LEFT)
+#define G_GCSUM_MORE_THAN_2_LEFT(x) (((x) >> S_GCSUM_MORE_THAN_2_LEFT) & M_GCSUM_MORE_THAN_2_LEFT)
+
+#define S_SDC_DRDY    0
+#define V_SDC_DRDY(x) ((x) << S_SDC_DRDY)
+#define F_SDC_DRDY    V_SDC_DRDY(1U)
+
+#define A_PM_TX_DBG_STAT6 0x10032
+
+#define S_PCMD_VLD    31
+#define V_PCMD_VLD(x) ((x) << S_PCMD_VLD)
+#define F_PCMD_VLD    V_PCMD_VLD(1U)
+
+#define S_PCMD_CH    29
+#define M_PCMD_CH    0x3U
+#define V_PCMD_CH(x) ((x) << S_PCMD_CH)
+#define G_PCMD_CH(x) (((x) >> S_PCMD_CH) & M_PCMD_CH)
+
+#define S_STATE_MACHINE_LOC    24
+#define M_STATE_MACHINE_LOC    0x1fU
+#define V_STATE_MACHINE_LOC(x) ((x) << S_STATE_MACHINE_LOC)
+#define G_STATE_MACHINE_LOC(x) (((x) >> S_STATE_MACHINE_LOC) & M_STATE_MACHINE_LOC)
+
+#define S_ICSPI_TXVALID    20
+#define M_ICSPI_TXVALID    0xfU
+#define V_ICSPI_TXVALID(x) ((x) << S_ICSPI_TXVALID)
+#define G_ICSPI_TXVALID(x) (((x) >> S_ICSPI_TXVALID) & M_ICSPI_TXVALID)
+
+#define S_ICSPI_TXFULL    16
+#define M_ICSPI_TXFULL    0xfU
+#define V_ICSPI_TXFULL(x) ((x) << S_ICSPI_TXFULL)
+#define G_ICSPI_TXFULL(x) (((x) >> S_ICSPI_TXFULL) & M_ICSPI_TXFULL)
+
+#define S_PCMD_SRDY    12
+#define M_PCMD_SRDY    0xfU
+#define V_PCMD_SRDY(x) ((x) << S_PCMD_SRDY)
+#define G_PCMD_SRDY(x) (((x) >> S_PCMD_SRDY) & M_PCMD_SRDY)
+
+#define S_PCMD_DRDY    8
+#define M_PCMD_DRDY    0xfU
+#define V_PCMD_DRDY(x) ((x) << S_PCMD_DRDY)
+#define G_PCMD_DRDY(x) (((x) >> S_PCMD_DRDY) & M_PCMD_DRDY)
+
+#define S_PCMD_CMD    4
+#define M_PCMD_CMD    0xfU
+#define V_PCMD_CMD(x) ((x) << S_PCMD_CMD)
+#define G_PCMD_CMD(x) (((x) >> S_PCMD_CMD) & M_PCMD_CMD)
+
+#define S_OEFIFO_FULL3    3
+#define V_OEFIFO_FULL3(x) ((x) << S_OEFIFO_FULL3)
+#define F_OEFIFO_FULL3    V_OEFIFO_FULL3(1U)
+
+#define S_OEFIFO_FULL2    2
+#define V_OEFIFO_FULL2(x) ((x) << S_OEFIFO_FULL2)
+#define F_OEFIFO_FULL2    V_OEFIFO_FULL2(1U)
+
+#define S_OEFIFO_FULL1    1
+#define V_OEFIFO_FULL1(x) ((x) << S_OEFIFO_FULL1)
+#define F_OEFIFO_FULL1    V_OEFIFO_FULL1(1U)
+
+#define S_OEFIFO_FULL0    0
+#define V_OEFIFO_FULL0(x) ((x) << S_OEFIFO_FULL0)
+#define F_OEFIFO_FULL0    V_OEFIFO_FULL0(1U)
+
+#define A_PM_TX_DBG_STAT7 0x10033
+
+#define S_ICSPI_RXVALID    28
+#define M_ICSPI_RXVALID    0xfU
+#define V_ICSPI_RXVALID(x) ((x) << S_ICSPI_RXVALID)
+#define G_ICSPI_RXVALID(x) (((x) >> S_ICSPI_RXVALID) & M_ICSPI_RXVALID)
+
+#define S_ICSPI_RXFULL    24
+#define M_ICSPI_RXFULL    0xfU
+#define V_ICSPI_RXFULL(x) ((x) << S_ICSPI_RXFULL)
+#define G_ICSPI_RXFULL(x) (((x) >> S_ICSPI_RXFULL) & M_ICSPI_RXFULL)
+
+#define S_OESPI_VALID    20
+#define M_OESPI_VALID    0xfU
+#define V_OESPI_VALID(x) ((x) << S_OESPI_VALID)
+#define G_OESPI_VALID(x) (((x) >> S_OESPI_VALID) & M_OESPI_VALID)
+
+#define S_OESPI_FULL    16
+#define M_OESPI_FULL    0xfU
+#define V_OESPI_FULL(x) ((x) << S_OESPI_FULL)
+#define G_OESPI_FULL(x) (((x) >> S_OESPI_FULL) & M_OESPI_FULL)
+
+#define S_C_RXVALID    12
+#define M_C_RXVALID    0xfU
+#define V_C_RXVALID(x) ((x) << S_C_RXVALID)
+#define G_C_RXVALID(x) (((x) >> S_C_RXVALID) & M_C_RXVALID)
+
+#define S_C_RXAFULL    8
+#define M_C_RXAFULL    0xfU
+#define V_C_RXAFULL(x) ((x) << S_C_RXAFULL)
+#define G_C_RXAFULL(x) (((x) >> S_C_RXAFULL) & M_C_RXAFULL)
+
+#define S_E_TXVALID3    7
+#define V_E_TXVALID3(x) ((x) << S_E_TXVALID3)
+#define F_E_TXVALID3    V_E_TXVALID3(1U)
+
+#define S_E_TXVALID2    6
+#define V_E_TXVALID2(x) ((x) << S_E_TXVALID2)
+#define F_E_TXVALID2    V_E_TXVALID2(1U)
+
+#define S_E_TXVALID1    5
+#define V_E_TXVALID1(x) ((x) << S_E_TXVALID1)
+#define F_E_TXVALID1    V_E_TXVALID1(1U)
+
+#define S_E_TXVALID0    4
+#define V_E_TXVALID0(x) ((x) << S_E_TXVALID0)
+#define F_E_TXVALID0    V_E_TXVALID0(1U)
+
+#define S_E_TXFULL3    3
+#define V_E_TXFULL3(x) ((x) << S_E_TXFULL3)
+#define F_E_TXFULL3    V_E_TXFULL3(1U)
+
+#define S_E_TXFULL2    2
+#define V_E_TXFULL2(x) ((x) << S_E_TXFULL2)
+#define F_E_TXFULL2    V_E_TXFULL2(1U)
+
+#define S_E_TXFULL1    1
+#define V_E_TXFULL1(x) ((x) << S_E_TXFULL1)
+#define F_E_TXFULL1    V_E_TXFULL1(1U)
+
+#define S_E_TXFULL0    0
+#define V_E_TXFULL0(x) ((x) << S_E_TXFULL0)
+#define F_E_TXFULL0    V_E_TXFULL0(1U)
+
+#define A_PM_TX_DBG_STAT8 0x10034
+
+#define S_MC_RSP_FIFO_CNT    24
+#define M_MC_RSP_FIFO_CNT    0x3U
+#define V_MC_RSP_FIFO_CNT(x) ((x) << S_MC_RSP_FIFO_CNT)
+#define G_MC_RSP_FIFO_CNT(x) (((x) >> S_MC_RSP_FIFO_CNT) & M_MC_RSP_FIFO_CNT)
+
+#define S_PCMD_FREE_CNT0    14
+#define M_PCMD_FREE_CNT0    0x3ffU
+#define V_PCMD_FREE_CNT0(x) ((x) << S_PCMD_FREE_CNT0)
+#define G_PCMD_FREE_CNT0(x) (((x) >> S_PCMD_FREE_CNT0) & M_PCMD_FREE_CNT0)
+
+#define S_PCMD_FREE_CNT1    4
+#define M_PCMD_FREE_CNT1    0x3ffU
+#define V_PCMD_FREE_CNT1(x) ((x) << S_PCMD_FREE_CNT1)
+#define G_PCMD_FREE_CNT1(x) (((x) >> S_PCMD_FREE_CNT1) & M_PCMD_FREE_CNT1)
+
+#define S_M_REQADDRRDY    3
+#define V_M_REQADDRRDY(x) ((x) << S_M_REQADDRRDY)
+#define F_M_REQADDRRDY    V_M_REQADDRRDY(1U)
+
+#define S_M_REQWRITE    2
+#define V_M_REQWRITE(x) ((x) << S_M_REQWRITE)
+#define F_M_REQWRITE    V_M_REQWRITE(1U)
+
+#define S_M_REQDATAVLD    1
+#define V_M_REQDATAVLD(x) ((x) << S_M_REQDATAVLD)
+#define F_M_REQDATAVLD    V_M_REQDATAVLD(1U)
+
+#define S_M_REQDATARDY    0
+#define V_M_REQDATARDY(x) ((x) << S_M_REQDATARDY)
+#define F_M_REQDATARDY    V_M_REQDATARDY(1U)
+
+#define A_PM_TX_DBG_STAT9 0x10035
+
+#define S_PCMD_FREE_CNT2    10
+#define M_PCMD_FREE_CNT2    0x3ffU
+#define V_PCMD_FREE_CNT2(x) ((x) << S_PCMD_FREE_CNT2)
+#define G_PCMD_FREE_CNT2(x) (((x) >> S_PCMD_FREE_CNT2) & M_PCMD_FREE_CNT2)
+
+#define S_PCMD_FREE_CNT3    0
+#define M_PCMD_FREE_CNT3    0x3ffU
+#define V_PCMD_FREE_CNT3(x) ((x) << S_PCMD_FREE_CNT3)
+#define G_PCMD_FREE_CNT3(x) (((x) >> S_PCMD_FREE_CNT3) & M_PCMD_FREE_CNT3)
+
+#define A_PM_TX_DBG_STAT10 0x10036
+
+#define S_IN_EOP_CNT3    28
+#define M_IN_EOP_CNT3    0xfU
+#define V_IN_EOP_CNT3(x) ((x) << S_IN_EOP_CNT3)
+#define G_IN_EOP_CNT3(x) (((x) >> S_IN_EOP_CNT3) & M_IN_EOP_CNT3)
+
+#define S_IN_EOP_CNT2    24
+#define M_IN_EOP_CNT2    0xfU
+#define V_IN_EOP_CNT2(x) ((x) << S_IN_EOP_CNT2)
+#define G_IN_EOP_CNT2(x) (((x) >> S_IN_EOP_CNT2) & M_IN_EOP_CNT2)
+
+#define S_IN_EOP_CNT1    20
+#define M_IN_EOP_CNT1    0xfU
+#define V_IN_EOP_CNT1(x) ((x) << S_IN_EOP_CNT1)
+#define G_IN_EOP_CNT1(x) (((x) >> S_IN_EOP_CNT1) & M_IN_EOP_CNT1)
+
+#define S_IN_EOP_CNT0    16
+#define M_IN_EOP_CNT0    0xfU
+#define V_IN_EOP_CNT0(x) ((x) << S_IN_EOP_CNT0)
+#define G_IN_EOP_CNT0(x) (((x) >> S_IN_EOP_CNT0) & M_IN_EOP_CNT0)
+
+#define S_IN_SOP_CNT3    12
+#define M_IN_SOP_CNT3    0xfU
+#define V_IN_SOP_CNT3(x) ((x) << S_IN_SOP_CNT3)
+#define G_IN_SOP_CNT3(x) (((x) >> S_IN_SOP_CNT3) & M_IN_SOP_CNT3)
+
+#define S_IN_SOP_CNT2    8
+#define M_IN_SOP_CNT2    0xfU
+#define V_IN_SOP_CNT2(x) ((x) << S_IN_SOP_CNT2)
+#define G_IN_SOP_CNT2(x) (((x) >> S_IN_SOP_CNT2) & M_IN_SOP_CNT2)
+
+#define S_IN_SOP_CNT1    4
+#define M_IN_SOP_CNT1    0xfU
+#define V_IN_SOP_CNT1(x) ((x) << S_IN_SOP_CNT1)
+#define G_IN_SOP_CNT1(x) (((x) >> S_IN_SOP_CNT1) & M_IN_SOP_CNT1)
+
+#define S_IN_SOP_CNT0    0
+#define M_IN_SOP_CNT0    0xfU
+#define V_IN_SOP_CNT0(x) ((x) << S_IN_SOP_CNT0)
+#define G_IN_SOP_CNT0(x) (((x) >> S_IN_SOP_CNT0) & M_IN_SOP_CNT0)
+
+#define A_PM_TX_DBG_STAT11 0x10037
+
+#define S_OUT_EOP_CNT3    28
+#define M_OUT_EOP_CNT3    0xfU
+#define V_OUT_EOP_CNT3(x) ((x) << S_OUT_EOP_CNT3)
+#define G_OUT_EOP_CNT3(x) (((x) >> S_OUT_EOP_CNT3) & M_OUT_EOP_CNT3)
+
+#define S_OUT_EOP_CNT2    24
+#define M_OUT_EOP_CNT2    0xfU
+#define V_OUT_EOP_CNT2(x) ((x) << S_OUT_EOP_CNT2)
+#define G_OUT_EOP_CNT2(x) (((x) >> S_OUT_EOP_CNT2) & M_OUT_EOP_CNT2)
+
+#define S_OUT_EOP_CNT1    20
+#define M_OUT_EOP_CNT1    0xfU
+#define V_OUT_EOP_CNT1(x) ((x) << S_OUT_EOP_CNT1)
+#define G_OUT_EOP_CNT1(x) (((x) >> S_OUT_EOP_CNT1) & M_OUT_EOP_CNT1)
+
+#define S_OUT_EOP_CNT0    16
+#define M_OUT_EOP_CNT0    0xfU
+#define V_OUT_EOP_CNT0(x) ((x) << S_OUT_EOP_CNT0)
+#define G_OUT_EOP_CNT0(x) (((x) >> S_OUT_EOP_CNT0) & M_OUT_EOP_CNT0)
+
+#define S_OUT_SOP_CNT3    12
+#define M_OUT_SOP_CNT3    0xfU
+#define V_OUT_SOP_CNT3(x) ((x) << S_OUT_SOP_CNT3)
+#define G_OUT_SOP_CNT3(x) (((x) >> S_OUT_SOP_CNT3) & M_OUT_SOP_CNT3)
+
+#define S_OUT_SOP_CNT2    8
+#define M_OUT_SOP_CNT2    0xfU
+#define V_OUT_SOP_CNT2(x) ((x) << S_OUT_SOP_CNT2)
+#define G_OUT_SOP_CNT2(x) (((x) >> S_OUT_SOP_CNT2) & M_OUT_SOP_CNT2)
+
+#define S_OUT_SOP_CNT1    4
+#define M_OUT_SOP_CNT1    0xfU
+#define V_OUT_SOP_CNT1(x) ((x) << S_OUT_SOP_CNT1)
+#define G_OUT_SOP_CNT1(x) (((x) >> S_OUT_SOP_CNT1) & M_OUT_SOP_CNT1)
+
+#define S_OUT_SOP_CNT0    0
+#define M_OUT_SOP_CNT0    0xfU
+#define V_OUT_SOP_CNT0(x) ((x) << S_OUT_SOP_CNT0)
+#define G_OUT_SOP_CNT0(x) (((x) >> S_OUT_SOP_CNT0) & M_OUT_SOP_CNT0)
+
+#define A_PM_TX_DBG_STAT12 0x10038
+#define A_PM_TX_DBG_STAT13 0x10039
+
+#define S_CH_DEFICIT_BLOWED    31
+#define V_CH_DEFICIT_BLOWED(x) ((x) << S_CH_DEFICIT_BLOWED)
+#define F_CH_DEFICIT_BLOWED    V_CH_DEFICIT_BLOWED(1U)
+
+#define S_CH1_DEFICIT    16
+#define M_CH1_DEFICIT    0xfffU
+#define V_CH1_DEFICIT(x) ((x) << S_CH1_DEFICIT)
+#define G_CH1_DEFICIT(x) (((x) >> S_CH1_DEFICIT) & M_CH1_DEFICIT)
+
+#define S_CH0_DEFICIT    0
+#define M_CH0_DEFICIT    0xfffU
+#define V_CH0_DEFICIT(x) ((x) << S_CH0_DEFICIT)
+#define G_CH0_DEFICIT(x) (((x) >> S_CH0_DEFICIT) & M_CH0_DEFICIT)
+
+#define A_PM_TX_DBG_STAT14 0x1003a
+
+#define S_CH3_DEFICIT    16
+#define M_CH3_DEFICIT    0xfffU
+#define V_CH3_DEFICIT(x) ((x) << S_CH3_DEFICIT)
+#define G_CH3_DEFICIT(x) (((x) >> S_CH3_DEFICIT) & M_CH3_DEFICIT)
+
+#define S_CH2_DEFICIT    0
+#define M_CH2_DEFICIT    0xfffU
+#define V_CH2_DEFICIT(x) ((x) << S_CH2_DEFICIT)
+#define G_CH2_DEFICIT(x) (((x) >> S_CH2_DEFICIT) & M_CH2_DEFICIT)
+
+#define A_PM_TX_DBG_STAT15 0x1003b
+
+#define S_BUNDLE_LEN_SRDY    28
+#define M_BUNDLE_LEN_SRDY    0xfU
+#define V_BUNDLE_LEN_SRDY(x) ((x) << S_BUNDLE_LEN_SRDY)
+#define G_BUNDLE_LEN_SRDY(x) (((x) >> S_BUNDLE_LEN_SRDY) & M_BUNDLE_LEN_SRDY)
+
+#define S_BUNDLE_LEN1    16
+#define M_BUNDLE_LEN1    0xfffU
+#define V_BUNDLE_LEN1(x) ((x) << S_BUNDLE_LEN1)
+#define G_BUNDLE_LEN1(x) (((x) >> S_BUNDLE_LEN1) & M_BUNDLE_LEN1)
+
+#define S_BUNDLE_LEN0    0
+#define M_BUNDLE_LEN0    0xfffU
+#define V_BUNDLE_LEN0(x) ((x) << S_BUNDLE_LEN0)
+#define G_BUNDLE_LEN0(x) (((x) >> S_BUNDLE_LEN0) & M_BUNDLE_LEN0)
+
+#define A_PM_TX_DBG_STAT16 0x1003c
+
+#define S_BUNDLE_LEN3    16
+#define M_BUNDLE_LEN3    0xfffU
+#define V_BUNDLE_LEN3(x) ((x) << S_BUNDLE_LEN3)
+#define G_BUNDLE_LEN3(x) (((x) >> S_BUNDLE_LEN3) & M_BUNDLE_LEN3)
+
+#define S_BUNDLE_LEN2    0
+#define M_BUNDLE_LEN2    0xfffU
+#define V_BUNDLE_LEN2(x) ((x) << S_BUNDLE_LEN2)
+#define G_BUNDLE_LEN2(x) (((x) >> S_BUNDLE_LEN2) & M_BUNDLE_LEN2)
+
+/* registers for module MPS */
+#define MPS_BASE_ADDR 0x9000
+
+#define A_MPS_PORT_CTL 0x0
+
+#define S_LPBKEN    31
+#define V_LPBKEN(x) ((x) << S_LPBKEN)
+#define F_LPBKEN    V_LPBKEN(1U)
+
+#define S_PORTTXEN    30
+#define V_PORTTXEN(x) ((x) << S_PORTTXEN)
+#define F_PORTTXEN    V_PORTTXEN(1U)
+
+#define S_PORTRXEN    29
+#define V_PORTRXEN(x) ((x) << S_PORTRXEN)
+#define F_PORTRXEN    V_PORTRXEN(1U)
+
+#define S_PPPEN    28
+#define V_PPPEN(x) ((x) << S_PPPEN)
+#define F_PPPEN    V_PPPEN(1U)
+
+#define S_FCSSTRIPEN    27
+#define V_FCSSTRIPEN(x) ((x) << S_FCSSTRIPEN)
+#define F_FCSSTRIPEN    V_FCSSTRIPEN(1U)
+
+#define S_PPPANDPAUSE    26
+#define V_PPPANDPAUSE(x) ((x) << S_PPPANDPAUSE)
+#define F_PPPANDPAUSE    V_PPPANDPAUSE(1U)
+
+#define S_PRIOPPPENMAP    16
+#define M_PRIOPPPENMAP    0xffU
+#define V_PRIOPPPENMAP(x) ((x) << S_PRIOPPPENMAP)
+#define G_PRIOPPPENMAP(x) (((x) >> S_PRIOPPPENMAP) & M_PRIOPPPENMAP)
+
+#define A_MPS_VF_CTL 0x0
+#define A_MPS_PORT_PAUSE_CTL 0x4
+
+#define S_TIMEUNIT    0
+#define M_TIMEUNIT    0xffffU
+#define V_TIMEUNIT(x) ((x) << S_TIMEUNIT)
+#define G_TIMEUNIT(x) (((x) >> S_TIMEUNIT) & M_TIMEUNIT)
+
+#define A_MPS_PORT_TX_PAUSE_CTL 0x8
+
+#define S_REGSENDOFF    24
+#define M_REGSENDOFF    0xffU
+#define V_REGSENDOFF(x) ((x) << S_REGSENDOFF)
+#define G_REGSENDOFF(x) (((x) >> S_REGSENDOFF) & M_REGSENDOFF)
+
+#define S_REGSENDON    16
+#define M_REGSENDON    0xffU
+#define V_REGSENDON(x) ((x) << S_REGSENDON)
+#define G_REGSENDON(x) (((x) >> S_REGSENDON) & M_REGSENDON)
+
+#define S_SGESENDEN    8
+#define M_SGESENDEN    0xffU
+#define V_SGESENDEN(x) ((x) << S_SGESENDEN)
+#define G_SGESENDEN(x) (((x) >> S_SGESENDEN) & M_SGESENDEN)
+
+#define S_RXSENDEN    0
+#define M_RXSENDEN    0xffU
+#define V_RXSENDEN(x) ((x) << S_RXSENDEN)
+#define G_RXSENDEN(x) (((x) >> S_RXSENDEN) & M_RXSENDEN)
+
+#define A_MPS_PORT_TX_PAUSE_CTL2 0xc
+
+#define S_XOFFDISABLE    0
+#define V_XOFFDISABLE(x) ((x) << S_XOFFDISABLE)
+#define F_XOFFDISABLE    V_XOFFDISABLE(1U)
+
+#define A_MPS_PORT_RX_PAUSE_CTL 0x10
+
+#define S_REGHALTON    8
+#define M_REGHALTON    0xffU
+#define V_REGHALTON(x) ((x) << S_REGHALTON)
+#define G_REGHALTON(x) (((x) >> S_REGHALTON) & M_REGHALTON)
+
+#define S_RXHALTEN    0
+#define M_RXHALTEN    0xffU
+#define V_RXHALTEN(x) ((x) << S_RXHALTEN)
+#define G_RXHALTEN(x) (((x) >> S_RXHALTEN) & M_RXHALTEN)
+
+#define A_MPS_PORT_TX_PAUSE_STATUS 0x14
+
+#define S_REGSENDING    16
+#define M_REGSENDING    0xffU
+#define V_REGSENDING(x) ((x) << S_REGSENDING)
+#define G_REGSENDING(x) (((x) >> S_REGSENDING) & M_REGSENDING)
+
+#define S_SGESENDING    8
+#define M_SGESENDING    0xffU
+#define V_SGESENDING(x) ((x) << S_SGESENDING)
+#define G_SGESENDING(x) (((x) >> S_SGESENDING) & M_SGESENDING)
+
+#define S_RXSENDING    0
+#define M_RXSENDING    0xffU
+#define V_RXSENDING(x) ((x) << S_RXSENDING)
+#define G_RXSENDING(x) (((x) >> S_RXSENDING) & M_RXSENDING)
+
+#define A_MPS_PORT_RX_PAUSE_STATUS 0x18
+
+#define S_REGHALTED    8
+#define M_REGHALTED    0xffU
+#define V_REGHALTED(x) ((x) << S_REGHALTED)
+#define G_REGHALTED(x) (((x) >> S_REGHALTED) & M_REGHALTED)
+
+#define S_RXHALTED    0
+#define M_RXHALTED    0xffU
+#define V_RXHALTED(x) ((x) << S_RXHALTED)
+#define G_RXHALTED(x) (((x) >> S_RXHALTED) & M_RXHALTED)
+
+#define A_MPS_PORT_TX_PAUSE_DEST_L 0x1c
+#define A_MPS_PORT_TX_PAUSE_DEST_H 0x20
+
+#define S_ADDR    0
+#define M_ADDR    0xffffU
+#define V_ADDR(x) ((x) << S_ADDR)
+#define G_ADDR(x) (((x) >> S_ADDR) & M_ADDR)
+
+#define A_MPS_PORT_TX_PAUSE_SOURCE_L 0x24
+#define A_MPS_PORT_TX_PAUSE_SOURCE_H 0x28
+#define A_MPS_PORT_PRTY_BUFFER_GROUP_MAP 0x2c
+
+#define S_PRTY7    14
+#define M_PRTY7    0x3U
+#define V_PRTY7(x) ((x) << S_PRTY7)
+#define G_PRTY7(x) (((x) >> S_PRTY7) & M_PRTY7)
+
+#define S_PRTY6    12
+#define M_PRTY6    0x3U
+#define V_PRTY6(x) ((x) << S_PRTY6)
+#define G_PRTY6(x) (((x) >> S_PRTY6) & M_PRTY6)
+
+#define S_PRTY5    10
+#define M_PRTY5    0x3U
+#define V_PRTY5(x) ((x) << S_PRTY5)
+#define G_PRTY5(x) (((x) >> S_PRTY5) & M_PRTY5)
+
+#define S_PRTY4    8
+#define M_PRTY4    0x3U
+#define V_PRTY4(x) ((x) << S_PRTY4)
+#define G_PRTY4(x) (((x) >> S_PRTY4) & M_PRTY4)
+
+#define S_PRTY3    6
+#define M_PRTY3    0x3U
+#define V_PRTY3(x) ((x) << S_PRTY3)
+#define G_PRTY3(x) (((x) >> S_PRTY3) & M_PRTY3)
+
+#define S_PRTY2    4
+#define M_PRTY2    0x3U
+#define V_PRTY2(x) ((x) << S_PRTY2)
+#define G_PRTY2(x) (((x) >> S_PRTY2) & M_PRTY2)
+
+#define S_PRTY1    2
+#define M_PRTY1    0x3U
+#define V_PRTY1(x) ((x) << S_PRTY1)
+#define G_PRTY1(x) (((x) >> S_PRTY1) & M_PRTY1)
+
+#define S_PRTY0    0
+#define M_PRTY0    0x3U
+#define V_PRTY0(x) ((x) << S_PRTY0)
+#define G_PRTY0(x) (((x) >> S_PRTY0) & M_PRTY0)
+
+#define A_MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP 0x30
+
+#define S_TXPRTY7    28
+#define M_TXPRTY7    0xfU
+#define V_TXPRTY7(x) ((x) << S_TXPRTY7)
+#define G_TXPRTY7(x) (((x) >> S_TXPRTY7) & M_TXPRTY7)
+
+#define S_TXPRTY6    24
+#define M_TXPRTY6    0xfU
+#define V_TXPRTY6(x) ((x) << S_TXPRTY6)
+#define G_TXPRTY6(x) (((x) >> S_TXPRTY6) & M_TXPRTY6)
+
+#define S_TXPRTY5    20
+#define M_TXPRTY5    0xfU
+#define V_TXPRTY5(x) ((x) << S_TXPRTY5)
+#define G_TXPRTY5(x) (((x) >> S_TXPRTY5) & M_TXPRTY5)
+
+#define S_TXPRTY4    16
+#define M_TXPRTY4    0xfU
+#define V_TXPRTY4(x) ((x) << S_TXPRTY4)
+#define G_TXPRTY4(x) (((x) >> S_TXPRTY4) & M_TXPRTY4)
+
+#define S_TXPRTY3    12
+#define M_TXPRTY3    0xfU
+#define V_TXPRTY3(x) ((x) << S_TXPRTY3)
+#define G_TXPRTY3(x) (((x) >> S_TXPRTY3) & M_TXPRTY3)
+
+#define S_TXPRTY2    8
+#define M_TXPRTY2    0xfU
+#define V_TXPRTY2(x) ((x) << S_TXPRTY2)
+#define G_TXPRTY2(x) (((x) >> S_TXPRTY2) & M_TXPRTY2)
+
+#define S_TXPRTY1    4
+#define M_TXPRTY1    0xfU
+#define V_TXPRTY1(x) ((x) << S_TXPRTY1)
+#define G_TXPRTY1(x) (((x) >> S_TXPRTY1) & M_TXPRTY1)
+
+#define S_TXPRTY0    0
+#define M_TXPRTY0    0xfU
+#define V_TXPRTY0(x) ((x) << S_TXPRTY0)
+#define G_TXPRTY0(x) (((x) >> S_TXPRTY0) & M_TXPRTY0)
+
+#define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L 0x80
+#define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_H 0x84
+#define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_L 0x88
+#define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_H 0x8c
+#define A_MPS_VF_STAT_TX_VF_MCAST_BYTES_L 0x90
+#define A_MPS_VF_STAT_TX_VF_MCAST_BYTES_H 0x94
+#define A_MPS_VF_STAT_TX_VF_MCAST_FRAMES_L 0x98
+#define A_MPS_VF_STAT_TX_VF_MCAST_FRAMES_H 0x9c
+#define A_MPS_VF_STAT_TX_VF_UCAST_BYTES_L 0xa0
+#define A_MPS_VF_STAT_TX_VF_UCAST_BYTES_H 0xa4
+#define A_MPS_VF_STAT_TX_VF_UCAST_FRAMES_L 0xa8
+#define A_MPS_VF_STAT_TX_VF_UCAST_FRAMES_H 0xac
+#define A_MPS_VF_STAT_TX_VF_DROP_FRAMES_L 0xb0
+#define A_MPS_VF_STAT_TX_VF_DROP_FRAMES_H 0xb4
+#define A_MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_L 0xb8
+#define A_MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_H 0xbc
+#define A_MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_L 0xc0
+#define A_MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_H 0xc4
+#define A_MPS_VF_STAT_RX_VF_BCAST_BYTES_L 0xc8
+#define A_MPS_VF_STAT_RX_VF_BCAST_BYTES_H 0xcc
+#define A_MPS_VF_STAT_RX_VF_BCAST_FRAMES_L 0xd0
+#define A_MPS_VF_STAT_RX_VF_BCAST_FRAMES_H 0xd4
+#define A_MPS_VF_STAT_RX_VF_MCAST_BYTES_L 0xd8
+#define A_MPS_VF_STAT_RX_VF_MCAST_BYTES_H 0xdc
+#define A_MPS_VF_STAT_RX_VF_MCAST_FRAMES_L 0xe0
+#define A_MPS_VF_STAT_RX_VF_MCAST_FRAMES_H 0xe4
+#define A_MPS_VF_STAT_RX_VF_UCAST_BYTES_L 0xe8
+#define A_MPS_VF_STAT_RX_VF_UCAST_BYTES_H 0xec
+#define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_L 0xf0
+#define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_H 0xf4
+#define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_L 0xf8
+#define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H 0xfc
+#define A_MPS_PORT_RX_CTL 0x100
+
+#define S_NO_RPLCT_M    20
+#define V_NO_RPLCT_M(x) ((x) << S_NO_RPLCT_M)
+#define F_NO_RPLCT_M    V_NO_RPLCT_M(1U)
+
+#define S_RPLCT_SEL_L    18
+#define M_RPLCT_SEL_L    0x3U
+#define V_RPLCT_SEL_L(x) ((x) << S_RPLCT_SEL_L)
+#define G_RPLCT_SEL_L(x) (((x) >> S_RPLCT_SEL_L) & M_RPLCT_SEL_L)
+
+#define S_FLTR_VLAN_SEL    17
+#define V_FLTR_VLAN_SEL(x) ((x) << S_FLTR_VLAN_SEL)
+#define F_FLTR_VLAN_SEL    V_FLTR_VLAN_SEL(1U)
+
+#define S_PRIO_VLAN_SEL    16
+#define V_PRIO_VLAN_SEL(x) ((x) << S_PRIO_VLAN_SEL)
+#define F_PRIO_VLAN_SEL    V_PRIO_VLAN_SEL(1U)
+
+#define S_CHK_8023_LEN_M    15
+#define V_CHK_8023_LEN_M(x) ((x) << S_CHK_8023_LEN_M)
+#define F_CHK_8023_LEN_M    V_CHK_8023_LEN_M(1U)
+
+#define S_CHK_8023_LEN_L    14
+#define V_CHK_8023_LEN_L(x) ((x) << S_CHK_8023_LEN_L)
+#define F_CHK_8023_LEN_L    V_CHK_8023_LEN_L(1U)
+
+#define S_NIV_DROP    13
+#define V_NIV_DROP(x) ((x) << S_NIV_DROP)
+#define F_NIV_DROP    V_NIV_DROP(1U)
+
+#define S_NOV_DROP    12
+#define V_NOV_DROP(x) ((x) << S_NOV_DROP)
+#define F_NOV_DROP    V_NOV_DROP(1U)
+
+#define S_CLS_PRT    11
+#define V_CLS_PRT(x) ((x) << S_CLS_PRT)
+#define F_CLS_PRT    V_CLS_PRT(1U)
+
+#define S_RX_QFC_EN    10
+#define V_RX_QFC_EN(x) ((x) << S_RX_QFC_EN)
+#define F_RX_QFC_EN    V_RX_QFC_EN(1U)
+
+#define S_QFC_FWD_UP    9
+#define V_QFC_FWD_UP(x) ((x) << S_QFC_FWD_UP)
+#define F_QFC_FWD_UP    V_QFC_FWD_UP(1U)
+
+#define S_PPP_FWD_UP    8
+#define V_PPP_FWD_UP(x) ((x) << S_PPP_FWD_UP)
+#define F_PPP_FWD_UP    V_PPP_FWD_UP(1U)
+
+#define S_PAUSE_FWD_UP    7
+#define V_PAUSE_FWD_UP(x) ((x) << S_PAUSE_FWD_UP)
+#define F_PAUSE_FWD_UP    V_PAUSE_FWD_UP(1U)
+
+#define S_LPBK_BP    6
+#define V_LPBK_BP(x) ((x) << S_LPBK_BP)
+#define F_LPBK_BP    V_LPBK_BP(1U)
+
+#define S_PASS_NO_MATCH    5
+#define V_PASS_NO_MATCH(x) ((x) << S_PASS_NO_MATCH)
+#define F_PASS_NO_MATCH    V_PASS_NO_MATCH(1U)
+
+#define S_IVLAN_EN    4
+#define V_IVLAN_EN(x) ((x) << S_IVLAN_EN)
+#define F_IVLAN_EN    V_IVLAN_EN(1U)
+
+#define S_OVLAN_EN3    3
+#define V_OVLAN_EN3(x) ((x) << S_OVLAN_EN3)
+#define F_OVLAN_EN3    V_OVLAN_EN3(1U)
+
+#define S_OVLAN_EN2    2
+#define V_OVLAN_EN2(x) ((x) << S_OVLAN_EN2)
+#define F_OVLAN_EN2    V_OVLAN_EN2(1U)
+
+#define S_OVLAN_EN1    1
+#define V_OVLAN_EN1(x) ((x) << S_OVLAN_EN1)
+#define F_OVLAN_EN1    V_OVLAN_EN1(1U)
+
+#define S_OVLAN_EN0    0
+#define V_OVLAN_EN0(x) ((x) << S_OVLAN_EN0)
+#define F_OVLAN_EN0    V_OVLAN_EN0(1U)
+
+#define S_PTP_FWD_UP    21
+#define V_PTP_FWD_UP(x) ((x) << S_PTP_FWD_UP)
+#define F_PTP_FWD_UP    V_PTP_FWD_UP(1U)
+
+#define A_MPS_PORT_RX_MTU 0x104
+#define A_MPS_PORT_RX_PF_MAP 0x108
+#define A_MPS_PORT_RX_VF_MAP0 0x10c
+#define A_MPS_PORT_RX_VF_MAP1 0x110
+#define A_MPS_PORT_RX_VF_MAP2 0x114
+#define A_MPS_PORT_RX_VF_MAP3 0x118
+#define A_MPS_PORT_RX_IVLAN 0x11c
+
+#define S_IVLAN_ETYPE    0
+#define M_IVLAN_ETYPE    0xffffU
+#define V_IVLAN_ETYPE(x) ((x) << S_IVLAN_ETYPE)
+#define G_IVLAN_ETYPE(x) (((x) >> S_IVLAN_ETYPE) & M_IVLAN_ETYPE)
+
+#define A_MPS_PORT_RX_OVLAN0 0x120
+
+#define S_OVLAN_MASK    16
+#define M_OVLAN_MASK    0xffffU
+#define V_OVLAN_MASK(x) ((x) << S_OVLAN_MASK)
+#define G_OVLAN_MASK(x) (((x) >> S_OVLAN_MASK) & M_OVLAN_MASK)
+
+#define S_OVLAN_ETYPE    0
+#define M_OVLAN_ETYPE    0xffffU
+#define V_OVLAN_ETYPE(x) ((x) << S_OVLAN_ETYPE)
+#define G_OVLAN_ETYPE(x) (((x) >> S_OVLAN_ETYPE) & M_OVLAN_ETYPE)
+
+#define A_MPS_PORT_RX_OVLAN1 0x124
+#define A_MPS_PORT_RX_OVLAN2 0x128
+#define A_MPS_PORT_RX_OVLAN3 0x12c
+#define A_MPS_PORT_RX_RSS_HASH 0x130
+#define A_MPS_PORT_RX_RSS_CONTROL 0x134
+
+#define S_RSS_CTRL    16
+#define M_RSS_CTRL    0xffU
+#define V_RSS_CTRL(x) ((x) << S_RSS_CTRL)
+#define G_RSS_CTRL(x) (((x) >> S_RSS_CTRL) & M_RSS_CTRL)
+
+#define S_QUE_NUM    0
+#define M_QUE_NUM    0xffffU
+#define V_QUE_NUM(x) ((x) << S_QUE_NUM)
+#define G_QUE_NUM(x) (((x) >> S_QUE_NUM) & M_QUE_NUM)
+
+#define A_MPS_PORT_RX_CTL1 0x138
+
+#define S_FIXED_PFVF_MAC    13
+#define V_FIXED_PFVF_MAC(x) ((x) << S_FIXED_PFVF_MAC)
+#define F_FIXED_PFVF_MAC    V_FIXED_PFVF_MAC(1U)
+
+#define S_FIXED_PFVF_LPBK    12
+#define V_FIXED_PFVF_LPBK(x) ((x) << S_FIXED_PFVF_LPBK)
+#define F_FIXED_PFVF_LPBK    V_FIXED_PFVF_LPBK(1U)
+
+#define S_FIXED_PFVF_LPBK_OV    11
+#define V_FIXED_PFVF_LPBK_OV(x) ((x) << S_FIXED_PFVF_LPBK_OV)
+#define F_FIXED_PFVF_LPBK_OV    V_FIXED_PFVF_LPBK_OV(1U)
+
+#define S_FIXED_PF    8
+#define M_FIXED_PF    0x7U
+#define V_FIXED_PF(x) ((x) << S_FIXED_PF)
+#define G_FIXED_PF(x) (((x) >> S_FIXED_PF) & M_FIXED_PF)
+
+#define S_FIXED_VF_VLD    7
+#define V_FIXED_VF_VLD(x) ((x) << S_FIXED_VF_VLD)
+#define F_FIXED_VF_VLD    V_FIXED_VF_VLD(1U)
+
+#define S_FIXED_VF    0
+#define M_FIXED_VF    0x7fU
+#define V_FIXED_VF(x) ((x) << S_FIXED_VF)
+#define G_FIXED_VF(x) (((x) >> S_FIXED_VF) & M_FIXED_VF)
+
+#define A_MPS_PORT_RX_SPARE 0x13c
+#define A_MPS_PORT_RX_PTP_RSS_HASH 0x140
+#define A_MPS_PORT_RX_PTP_RSS_CONTROL 0x144
+#define A_MPS_PORT_TX_MAC_RELOAD_CH0 0x190
+
+#define S_CREDIT    0
+#define M_CREDIT    0xffffU
+#define V_CREDIT(x) ((x) << S_CREDIT)
+#define G_CREDIT(x) (((x) >> S_CREDIT) & M_CREDIT)
+
+#define A_MPS_PORT_TX_MAC_RELOAD_CH1 0x194
+#define A_MPS_PORT_TX_MAC_RELOAD_CH2 0x198
+#define A_MPS_PORT_TX_MAC_RELOAD_CH3 0x19c
+#define A_MPS_PORT_TX_MAC_RELOAD_CH4 0x1a0
+#define A_MPS_PORT_TX_LPBK_RELOAD_CH0 0x1a8
+#define A_MPS_PORT_TX_LPBK_RELOAD_CH1 0x1ac
+#define A_MPS_PORT_TX_LPBK_RELOAD_CH2 0x1b0
+#define A_MPS_PORT_TX_LPBK_RELOAD_CH3 0x1b4
+#define A_MPS_PORT_TX_LPBK_RELOAD_CH4 0x1b8
+#define A_MPS_PORT_TX_FIFO_CTL 0x1c4
+
+#define S_FIFOTH    5
+#define M_FIFOTH    0x1ffU
+#define V_FIFOTH(x) ((x) << S_FIFOTH)
+#define G_FIFOTH(x) (((x) >> S_FIFOTH) & M_FIFOTH)
+
+#define S_FIFOEN    4
+#define V_FIFOEN(x) ((x) << S_FIFOEN)
+#define F_FIFOEN    V_FIFOEN(1U)
+
+#define S_MAXPKTCNT    0
+#define M_MAXPKTCNT    0xfU
+#define V_MAXPKTCNT(x) ((x) << S_MAXPKTCNT)
+#define G_MAXPKTCNT(x) (((x) >> S_MAXPKTCNT) & M_MAXPKTCNT)
+
+#define A_MPS_PORT_FPGA_PAUSE_CTL 0x1c8
+
+#define S_FPGAPAUSEEN    0
+#define V_FPGAPAUSEEN(x) ((x) << S_FPGAPAUSEEN)
+#define F_FPGAPAUSEEN    V_FPGAPAUSEEN(1U)
+
+#define A_MPS_PORT_TX_PAUSE_PENDING_STATUS 0x1d0
+
+#define S_OFF_PENDING    8
+#define M_OFF_PENDING    0xffU
+#define V_OFF_PENDING(x) ((x) << S_OFF_PENDING)
+#define G_OFF_PENDING(x) (((x) >> S_OFF_PENDING) & M_OFF_PENDING)
+
+#define S_ON_PENDING    0
+#define M_ON_PENDING    0xffU
+#define V_ON_PENDING(x) ((x) << S_ON_PENDING)
+#define G_ON_PENDING(x) (((x) >> S_ON_PENDING) & M_ON_PENDING)
+
+#define A_MPS_PORT_CLS_HASH_SRAM 0x200
+
+#define S_VALID    20
+#define V_VALID(x) ((x) << S_VALID)
+#define F_VALID    V_VALID(1U)
+
+#define S_HASHPORTMAP    16
+#define M_HASHPORTMAP    0xfU
+#define V_HASHPORTMAP(x) ((x) << S_HASHPORTMAP)
+#define G_HASHPORTMAP(x) (((x) >> S_HASHPORTMAP) & M_HASHPORTMAP)
+
+#define S_MULTILISTEN    15
+#define V_MULTILISTEN(x) ((x) << S_MULTILISTEN)
+#define F_MULTILISTEN    V_MULTILISTEN(1U)
+
+#define S_PRIORITY    12
+#define M_PRIORITY    0x7U
+#define V_PRIORITY(x) ((x) << S_PRIORITY)
+#define G_PRIORITY(x) (((x) >> S_PRIORITY) & M_PRIORITY)
+
+#define S_REPLICATE    11
+#define V_REPLICATE(x) ((x) << S_REPLICATE)
+#define F_REPLICATE    V_REPLICATE(1U)
+
+#define S_PF    8
+#define M_PF    0x7U
+#define V_PF(x) ((x) << S_PF)
+#define G_PF(x) (((x) >> S_PF) & M_PF)
+
+#define S_VF_VALID    7
+#define V_VF_VALID(x) ((x) << S_VF_VALID)
+#define F_VF_VALID    V_VF_VALID(1U)
+
+#define S_VF    0
+#define M_VF    0x7fU
+#define V_VF(x) ((x) << S_VF)
+#define G_VF(x) (((x) >> S_VF) & M_VF)
+
+#define A_MPS_PF_CTL 0x2c0
+
+#define S_TXEN    1
+#define V_TXEN(x) ((x) << S_TXEN)
+#define F_TXEN    V_TXEN(1U)
+
+#define S_RXEN    0
+#define V_RXEN(x) ((x) << S_RXEN)
+#define F_RXEN    V_RXEN(1U)
+
+#define A_MPS_PF_TX_QINQ_VLAN 0x2e0
+
+#define S_PROTOCOLID    16
+#define M_PROTOCOLID    0xffffU
+#define V_PROTOCOLID(x) ((x) << S_PROTOCOLID)
+#define G_PROTOCOLID(x) (((x) >> S_PROTOCOLID) & M_PROTOCOLID)
+
+#define S_VLAN_PRIO    13
+#define M_VLAN_PRIO    0x7U
+#define V_VLAN_PRIO(x) ((x) << S_VLAN_PRIO)
+#define G_VLAN_PRIO(x) (((x) >> S_VLAN_PRIO) & M_VLAN_PRIO)
+
+#define S_CFI    12
+#define V_CFI(x) ((x) << S_CFI)
+#define F_CFI    V_CFI(1U)
+
+#define S_TAG    0
+#define M_TAG    0xfffU
+#define V_TAG(x) ((x) << S_TAG)
+#define G_TAG(x) (((x) >> S_TAG) & M_TAG)
+
+#define A_MPS_PF_STAT_TX_PF_BCAST_BYTES_L 0x300
+#define A_MPS_PF_STAT_TX_PF_BCAST_BYTES_H 0x304
+#define A_MPS_PORT_CLS_HASH_CTL 0x304
+
+#define S_UNICASTENABLE    31
+#define V_UNICASTENABLE(x) ((x) << S_UNICASTENABLE)
+#define F_UNICASTENABLE    V_UNICASTENABLE(1U)
+
+#define A_MPS_PF_STAT_TX_PF_BCAST_FRAMES_L 0x308
+#define A_MPS_PORT_CLS_PROMISCUOUS_CTL 0x308
+
+#define S_PROMISCEN    31
+#define V_PROMISCEN(x) ((x) << S_PROMISCEN)
+#define F_PROMISCEN    V_PROMISCEN(1U)
+
+#define A_MPS_PF_STAT_TX_PF_BCAST_FRAMES_H 0x30c
+#define A_MPS_PORT_CLS_BMC_MAC_ADDR_L 0x30c
+#define A_MPS_PF_STAT_TX_PF_MCAST_BYTES_L 0x310
+#define A_MPS_PORT_CLS_BMC_MAC_ADDR_H 0x310
+
+#define S_MATCHBOTH    17
+#define V_MATCHBOTH(x) ((x) << S_MATCHBOTH)
+#define F_MATCHBOTH    V_MATCHBOTH(1U)
+
+#define S_BMC_VLD    16
+#define V_BMC_VLD(x) ((x) << S_BMC_VLD)
+#define F_BMC_VLD    V_BMC_VLD(1U)
+
+#define A_MPS_PF_STAT_TX_PF_MCAST_BYTES_H 0x314
+#define A_MPS_PORT_CLS_BMC_VLAN 0x314
+
+#define S_BMC_VLAN_SEL    13
+#define V_BMC_VLAN_SEL(x) ((x) << S_BMC_VLAN_SEL)
+#define F_BMC_VLAN_SEL    V_BMC_VLAN_SEL(1U)
+
+#define S_VLAN_VLD    12
+#define V_VLAN_VLD(x) ((x) << S_VLAN_VLD)
+#define F_VLAN_VLD    V_VLAN_VLD(1U)
+
+#define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_L 0x318
+#define A_MPS_PORT_CLS_CTL 0x318
+
+#define S_PF_VLAN_SEL    0
+#define V_PF_VLAN_SEL(x) ((x) << S_PF_VLAN_SEL)
+#define F_PF_VLAN_SEL    V_PF_VLAN_SEL(1U)
+
+#define S_LPBK_TCAM1_HIT_PRIORITY    14
+#define V_LPBK_TCAM1_HIT_PRIORITY(x) ((x) << S_LPBK_TCAM1_HIT_PRIORITY)
+#define F_LPBK_TCAM1_HIT_PRIORITY    V_LPBK_TCAM1_HIT_PRIORITY(1U)
+
+#define S_LPBK_TCAM0_HIT_PRIORITY    13
+#define V_LPBK_TCAM0_HIT_PRIORITY(x) ((x) << S_LPBK_TCAM0_HIT_PRIORITY)
+#define F_LPBK_TCAM0_HIT_PRIORITY    V_LPBK_TCAM0_HIT_PRIORITY(1U)
+
+#define S_LPBK_TCAM_PRIORITY    12
+#define V_LPBK_TCAM_PRIORITY(x) ((x) << S_LPBK_TCAM_PRIORITY)
+#define F_LPBK_TCAM_PRIORITY    V_LPBK_TCAM_PRIORITY(1U)
+
+#define S_LPBK_SMAC_TCAM_SEL    10
+#define M_LPBK_SMAC_TCAM_SEL    0x3U
+#define V_LPBK_SMAC_TCAM_SEL(x) ((x) << S_LPBK_SMAC_TCAM_SEL)
+#define G_LPBK_SMAC_TCAM_SEL(x) (((x) >> S_LPBK_SMAC_TCAM_SEL) & M_LPBK_SMAC_TCAM_SEL)
+
+#define S_LPBK_DMAC_TCAM_SEL    8
+#define M_LPBK_DMAC_TCAM_SEL    0x3U
+#define V_LPBK_DMAC_TCAM_SEL(x) ((x) << S_LPBK_DMAC_TCAM_SEL)
+#define G_LPBK_DMAC_TCAM_SEL(x) (((x) >> S_LPBK_DMAC_TCAM_SEL) & M_LPBK_DMAC_TCAM_SEL)
+
+#define S_TCAM1_HIT_PRIORITY    7
+#define V_TCAM1_HIT_PRIORITY(x) ((x) << S_TCAM1_HIT_PRIORITY)
+#define F_TCAM1_HIT_PRIORITY    V_TCAM1_HIT_PRIORITY(1U)
+
+#define S_TCAM0_HIT_PRIORITY    6
+#define V_TCAM0_HIT_PRIORITY(x) ((x) << S_TCAM0_HIT_PRIORITY)
+#define F_TCAM0_HIT_PRIORITY    V_TCAM0_HIT_PRIORITY(1U)
+
+#define S_TCAM_PRIORITY    5
+#define V_TCAM_PRIORITY(x) ((x) << S_TCAM_PRIORITY)
+#define F_TCAM_PRIORITY    V_TCAM_PRIORITY(1U)
+
+#define S_SMAC_TCAM_SEL    3
+#define M_SMAC_TCAM_SEL    0x3U
+#define V_SMAC_TCAM_SEL(x) ((x) << S_SMAC_TCAM_SEL)
+#define G_SMAC_TCAM_SEL(x) (((x) >> S_SMAC_TCAM_SEL) & M_SMAC_TCAM_SEL)
+
+#define S_DMAC_TCAM_SEL    1
+#define M_DMAC_TCAM_SEL    0x3U
+#define V_DMAC_TCAM_SEL(x) ((x) << S_DMAC_TCAM_SEL)
+#define G_DMAC_TCAM_SEL(x) (((x) >> S_DMAC_TCAM_SEL) & M_DMAC_TCAM_SEL)
+
+#define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_H 0x31c
+#define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_L 0x320
+#define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_H 0x324
+#define A_MPS_PF_STAT_TX_PF_UCAST_FRAMES_L 0x328
+#define A_MPS_PF_STAT_TX_PF_UCAST_FRAMES_H 0x32c
+#define A_MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L 0x330
+#define A_MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H 0x334
+#define A_MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L 0x338
+#define A_MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H 0x33c
+#define A_MPS_PF_STAT_RX_PF_BYTES_L 0x340
+#define A_MPS_PF_STAT_RX_PF_BYTES_H 0x344
+#define A_MPS_PF_STAT_RX_PF_FRAMES_L 0x348
+#define A_MPS_PF_STAT_RX_PF_FRAMES_H 0x34c
+#define A_MPS_PF_STAT_RX_PF_BCAST_BYTES_L 0x350
+#define A_MPS_PF_STAT_RX_PF_BCAST_BYTES_H 0x354
+#define A_MPS_PF_STAT_RX_PF_BCAST_FRAMES_L 0x358
+#define A_MPS_PF_STAT_RX_PF_BCAST_FRAMES_H 0x35c
+#define A_MPS_PF_STAT_RX_PF_MCAST_BYTES_L 0x360
+#define A_MPS_PF_STAT_RX_PF_MCAST_BYTES_H 0x364
+#define A_MPS_PF_STAT_RX_PF_MCAST_FRAMES_L 0x368
+#define A_MPS_PF_STAT_RX_PF_MCAST_FRAMES_H 0x36c
+#define A_MPS_PF_STAT_RX_PF_UCAST_BYTES_L 0x370
+#define A_MPS_PF_STAT_RX_PF_UCAST_BYTES_H 0x374
+#define A_MPS_PF_STAT_RX_PF_UCAST_FRAMES_L 0x378
+#define A_MPS_PF_STAT_RX_PF_UCAST_FRAMES_H 0x37c
+#define A_MPS_PF_STAT_RX_PF_ERR_FRAMES_L 0x380
+#define A_MPS_PF_STAT_RX_PF_ERR_FRAMES_H 0x384
+#define A_MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
+#define A_MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
+#define A_MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
+#define A_MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
+#define A_MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
+#define A_MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
+#define A_MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
+#define A_MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
+#define A_MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
+#define A_MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
+#define A_MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
+#define A_MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
+#define A_MPS_PORT_STAT_TX_PORT_64B_L 0x430
+#define A_MPS_PORT_STAT_TX_PORT_64B_H 0x434
+#define A_MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
+#define A_MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
+#define A_MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
+#define A_MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
+#define A_MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
+#define A_MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
+#define A_MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
+#define A_MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
+#define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
+#define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
+#define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
+#define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
+#define A_MPS_PORT_STAT_TX_PORT_DROP_L 0x468
+#define A_MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
+#define A_MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
+#define A_MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
+#define A_MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
+#define A_MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
+#define A_MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
+#define A_MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
+#define A_MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
+#define A_MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
+#define A_MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
+#define A_MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
+#define A_MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
+#define A_MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
+#define A_MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
+#define A_MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
+#define A_MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
+#define A_MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
+#define A_MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
+#define A_MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
+#define A_MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
+#define A_MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
+#define A_MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
+#define A_MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
+#define A_MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
+#define A_MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
+#define A_MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
+#define A_MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
+#define A_MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
+#define A_MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
+#define A_MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
+#define A_MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
+#define A_MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
+#define A_MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
+#define A_MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
+#define A_MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
+#define A_MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
+#define A_MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
+#define A_MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
+#define A_MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
+#define A_MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
+#define A_MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
+#define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
+#define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
+#define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
+#define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
+#define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
+#define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528
+#define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H 0x52c
+#define A_MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
+#define A_MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
+#define A_MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
+#define A_MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
+#define A_MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
+#define A_MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
+#define A_MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
+#define A_MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
+#define A_MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
+#define A_MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
+#define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
+#define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
+#define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
+#define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
+#define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
+#define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
+#define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
+#define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
+#define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
+#define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
+#define A_MPS_PORT_STAT_RX_PORT_64B_L 0x590
+#define A_MPS_PORT_STAT_RX_PORT_64B_H 0x594
+#define A_MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
+#define A_MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
+#define A_MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
+#define A_MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
+#define A_MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
+#define A_MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
+#define A_MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
+#define A_MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
+#define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
+#define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
+#define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
+#define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
+#define A_MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
+#define A_MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
+#define A_MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
+#define A_MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
+#define A_MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
+#define A_MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
+#define A_MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
+#define A_MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
+#define A_MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
+#define A_MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
+#define A_MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
+#define A_MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
+#define A_MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
+#define A_MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
+#define A_MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
+#define A_MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
+#define A_MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
+#define A_MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
+#define A_MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
+#define A_MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
+#define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_L 0x618
+#define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_H 0x61c
+#define A_MPS_CMN_CTL 0x9000
+
+#define S_DETECT8023    3
+#define V_DETECT8023(x) ((x) << S_DETECT8023)
+#define F_DETECT8023    V_DETECT8023(1U)
+
+#define S_VFDIRECTACCESS    2
+#define V_VFDIRECTACCESS(x) ((x) << S_VFDIRECTACCESS)
+#define F_VFDIRECTACCESS    V_VFDIRECTACCESS(1U)
+
+#define S_NUMPORTS    0
+#define M_NUMPORTS    0x3U
+#define V_NUMPORTS(x) ((x) << S_NUMPORTS)
+#define G_NUMPORTS(x) (((x) >> S_NUMPORTS) & M_NUMPORTS)
+
+#define S_LPBKCRDTCTRL    4
+#define V_LPBKCRDTCTRL(x) ((x) << S_LPBKCRDTCTRL)
+#define F_LPBKCRDTCTRL    V_LPBKCRDTCTRL(1U)
+
+#define A_MPS_INT_ENABLE 0x9004
+
+#define S_STATINTENB    5
+#define V_STATINTENB(x) ((x) << S_STATINTENB)
+#define F_STATINTENB    V_STATINTENB(1U)
+
+#define S_TXINTENB    4
+#define V_TXINTENB(x) ((x) << S_TXINTENB)
+#define F_TXINTENB    V_TXINTENB(1U)
+
+#define S_RXINTENB    3
+#define V_RXINTENB(x) ((x) << S_RXINTENB)
+#define F_RXINTENB    V_RXINTENB(1U)
+
+#define S_TRCINTENB    2
+#define V_TRCINTENB(x) ((x) << S_TRCINTENB)
+#define F_TRCINTENB    V_TRCINTENB(1U)
+
+#define S_CLSINTENB    1
+#define V_CLSINTENB(x) ((x) << S_CLSINTENB)
+#define F_CLSINTENB    V_CLSINTENB(1U)
+
+#define S_PLINTENB    0
+#define V_PLINTENB(x) ((x) << S_PLINTENB)
+#define F_PLINTENB    V_PLINTENB(1U)
+
+#define A_MPS_INT_CAUSE 0x9008
+
+#define S_STATINT    5
+#define V_STATINT(x) ((x) << S_STATINT)
+#define F_STATINT    V_STATINT(1U)
+
+#define S_TXINT    4
+#define V_TXINT(x) ((x) << S_TXINT)
+#define F_TXINT    V_TXINT(1U)
+
+#define S_RXINT    3
+#define V_RXINT(x) ((x) << S_RXINT)
+#define F_RXINT    V_RXINT(1U)
+
+#define S_TRCINT    2
+#define V_TRCINT(x) ((x) << S_TRCINT)
+#define F_TRCINT    V_TRCINT(1U)
+
+#define S_CLSINT    1
+#define V_CLSINT(x) ((x) << S_CLSINT)
+#define F_CLSINT    V_CLSINT(1U)
+
+#define S_PLINT    0
+#define V_PLINT(x) ((x) << S_PLINT)
+#define F_PLINT    V_PLINT(1U)
+
+#define A_MPS_CGEN_GLOBAL 0x900c
+
+#define S_MPS_GLOBAL_CGEN    0
+#define V_MPS_GLOBAL_CGEN(x) ((x) << S_MPS_GLOBAL_CGEN)
+#define F_MPS_GLOBAL_CGEN    V_MPS_GLOBAL_CGEN(1U)
+
+#define A_MPS_VF_TX_CTL_31_0 0x9010
+#define A_MPS_VF_TX_CTL_63_32 0x9014
+#define A_MPS_VF_TX_CTL_95_64 0x9018
+#define A_MPS_VF_TX_CTL_127_96 0x901c
+#define A_MPS_VF_RX_CTL_31_0 0x9020
+#define A_MPS_VF_RX_CTL_63_32 0x9024
+#define A_MPS_VF_RX_CTL_95_64 0x9028
+#define A_MPS_VF_RX_CTL_127_96 0x902c
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP0 0x9030
+
+#define S_VALUE    0
+#define M_VALUE    0xffffU
+#define V_VALUE(x) ((x) << S_VALUE)
+#define G_VALUE(x) (((x) >> S_VALUE) & M_VALUE)
+
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP1 0x9034
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP2 0x9038
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP3 0x903c
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP0 0x9040
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP1 0x9044
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP2 0x9048
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP3 0x904c
+#define A_MPS_TP_CSIDE_MUX_CTL_P0 0x9050
+
+#define S_WEIGHT    0
+#define M_WEIGHT    0xfffU
+#define V_WEIGHT(x) ((x) << S_WEIGHT)
+#define G_WEIGHT(x) (((x) >> S_WEIGHT) & M_WEIGHT)
+
+#define A_MPS_TP_CSIDE_MUX_CTL_P1 0x9054
+#define A_MPS_WOL_CTL_MODE 0x9058
+
+#define S_WOL_MODE    0
+#define V_WOL_MODE(x) ((x) << S_WOL_MODE)
+#define F_WOL_MODE    V_WOL_MODE(1U)
+
+#define A_MPS_FPGA_DEBUG 0x9060
+
+#define S_LPBK_EN    8
+#define V_LPBK_EN(x) ((x) << S_LPBK_EN)
+#define F_LPBK_EN    V_LPBK_EN(1U)
+
+#define S_CH_MAP3    6
+#define M_CH_MAP3    0x3U
+#define V_CH_MAP3(x) ((x) << S_CH_MAP3)
+#define G_CH_MAP3(x) (((x) >> S_CH_MAP3) & M_CH_MAP3)
+
+#define S_CH_MAP2    4
+#define M_CH_MAP2    0x3U
+#define V_CH_MAP2(x) ((x) << S_CH_MAP2)
+#define G_CH_MAP2(x) (((x) >> S_CH_MAP2) & M_CH_MAP2)
+
+#define S_CH_MAP1    2
+#define M_CH_MAP1    0x3U
+#define V_CH_MAP1(x) ((x) << S_CH_MAP1)
+#define G_CH_MAP1(x) (((x) >> S_CH_MAP1) & M_CH_MAP1)
+
+#define S_CH_MAP0    0
+#define M_CH_MAP0    0x3U
+#define V_CH_MAP0(x) ((x) << S_CH_MAP0)
+#define G_CH_MAP0(x) (((x) >> S_CH_MAP0) & M_CH_MAP0)
+
+#define S_FPGA_PTP_PORT    9
+#define M_FPGA_PTP_PORT    0x3U
+#define V_FPGA_PTP_PORT(x) ((x) << S_FPGA_PTP_PORT)
+#define G_FPGA_PTP_PORT(x) (((x) >> S_FPGA_PTP_PORT) & M_FPGA_PTP_PORT)
+
+#define A_MPS_DEBUG_CTL 0x9068
+
+#define S_DBGMODECTL_H    11
+#define V_DBGMODECTL_H(x) ((x) << S_DBGMODECTL_H)
+#define F_DBGMODECTL_H    V_DBGMODECTL_H(1U)
+
+#define S_DBGSEL_H    6
+#define M_DBGSEL_H    0x1fU
+#define V_DBGSEL_H(x) ((x) << S_DBGSEL_H)
+#define G_DBGSEL_H(x) (((x) >> S_DBGSEL_H) & M_DBGSEL_H)
+
+#define S_DBGMODECTL_L    5
+#define V_DBGMODECTL_L(x) ((x) << S_DBGMODECTL_L)
+#define F_DBGMODECTL_L    V_DBGMODECTL_L(1U)
+
+#define S_DBGSEL_L    0
+#define M_DBGSEL_L    0x1fU
+#define V_DBGSEL_L(x) ((x) << S_DBGSEL_L)
+#define G_DBGSEL_L(x) (((x) >> S_DBGSEL_L) & M_DBGSEL_L)
+
+#define A_MPS_DEBUG_DATA_REG_L 0x906c
+#define A_MPS_DEBUG_DATA_REG_H 0x9070
+#define A_MPS_TOP_SPARE 0x9074
+
+#define S_TOPSPARE    8
+#define M_TOPSPARE    0xffffffU
+#define V_TOPSPARE(x) ((x) << S_TOPSPARE)
+#define G_TOPSPARE(x) (((x) >> S_TOPSPARE) & M_TOPSPARE)
+
+#define S_OVLANSELLPBK3    7
+#define V_OVLANSELLPBK3(x) ((x) << S_OVLANSELLPBK3)
+#define F_OVLANSELLPBK3    V_OVLANSELLPBK3(1U)
+
+#define S_OVLANSELLPBK2    6
+#define V_OVLANSELLPBK2(x) ((x) << S_OVLANSELLPBK2)
+#define F_OVLANSELLPBK2    V_OVLANSELLPBK2(1U)
+
+#define S_OVLANSELLPBK1    5
+#define V_OVLANSELLPBK1(x) ((x) << S_OVLANSELLPBK1)
+#define F_OVLANSELLPBK1    V_OVLANSELLPBK1(1U)
+
+#define S_OVLANSELLPBK0    4
+#define V_OVLANSELLPBK0(x) ((x) << S_OVLANSELLPBK0)
+#define F_OVLANSELLPBK0    V_OVLANSELLPBK0(1U)
+
+#define S_OVLANSELMAC3    3
+#define V_OVLANSELMAC3(x) ((x) << S_OVLANSELMAC3)
+#define F_OVLANSELMAC3    V_OVLANSELMAC3(1U)
+
+#define S_OVLANSELMAC2    2
+#define V_OVLANSELMAC2(x) ((x) << S_OVLANSELMAC2)
+#define F_OVLANSELMAC2    V_OVLANSELMAC2(1U)
+
+#define S_OVLANSELMAC1    1
+#define V_OVLANSELMAC1(x) ((x) << S_OVLANSELMAC1)
+#define F_OVLANSELMAC1    V_OVLANSELMAC1(1U)
+
+#define S_OVLANSELMAC0    0
+#define V_OVLANSELMAC0(x) ((x) << S_OVLANSELMAC0)
+#define F_OVLANSELMAC0    V_OVLANSELMAC0(1U)
+
+#define S_T5_TOPSPARE    8
+#define M_T5_TOPSPARE    0xffffffU
+#define V_T5_TOPSPARE(x) ((x) << S_T5_TOPSPARE)
+#define G_T5_TOPSPARE(x) (((x) >> S_T5_TOPSPARE) & M_T5_TOPSPARE)
+
+#define A_MPS_T5_BUILD_REVISION 0x9078
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH0 0x907c
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH1 0x9080
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH2 0x9084
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH3 0x9088
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH4 0x908c
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH5 0x9090
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH6 0x9094
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH7 0x9098
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH8 0x909c
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH9 0x90a0
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH10 0x90a4
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH11 0x90a8
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH12 0x90ac
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH13 0x90b0
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH14 0x90b4
+#define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH15 0x90b8
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH0 0x90bc
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH1 0x90c0
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH2 0x90c4
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH3 0x90c8
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH4 0x90cc
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH5 0x90d0
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH6 0x90d4
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH7 0x90d8
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH8 0x90dc
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH9 0x90e0
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH10 0x90e4
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH11 0x90e8
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH12 0x90ec
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH13 0x90f0
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH14 0x90f4
+#define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH15 0x90f8
+#define A_MPS_BUILD_REVISION 0x90fc
+#define A_MPS_TX_PRTY_SEL 0x9400
+
+#define S_CH4_PRTY    20
+#define M_CH4_PRTY    0x7U
+#define V_CH4_PRTY(x) ((x) << S_CH4_PRTY)
+#define G_CH4_PRTY(x) (((x) >> S_CH4_PRTY) & M_CH4_PRTY)
+
+#define S_CH3_PRTY    16
+#define M_CH3_PRTY    0x7U
+#define V_CH3_PRTY(x) ((x) << S_CH3_PRTY)
+#define G_CH3_PRTY(x) (((x) >> S_CH3_PRTY) & M_CH3_PRTY)
+
+#define S_CH2_PRTY    12
+#define M_CH2_PRTY    0x7U
+#define V_CH2_PRTY(x) ((x) << S_CH2_PRTY)
+#define G_CH2_PRTY(x) (((x) >> S_CH2_PRTY) & M_CH2_PRTY)
+
+#define S_CH1_PRTY    8
+#define M_CH1_PRTY    0x7U
+#define V_CH1_PRTY(x) ((x) << S_CH1_PRTY)
+#define G_CH1_PRTY(x) (((x) >> S_CH1_PRTY) & M_CH1_PRTY)
+
+#define S_CH0_PRTY    4
+#define M_CH0_PRTY    0x7U
+#define V_CH0_PRTY(x) ((x) << S_CH0_PRTY)
+#define G_CH0_PRTY(x) (((x) >> S_CH0_PRTY) & M_CH0_PRTY)
+
+#define S_TP_SOURCE    2
+#define M_TP_SOURCE    0x3U
+#define V_TP_SOURCE(x) ((x) << S_TP_SOURCE)
+#define G_TP_SOURCE(x) (((x) >> S_TP_SOURCE) & M_TP_SOURCE)
+
+#define S_NCSI_SOURCE    0
+#define M_NCSI_SOURCE    0x3U
+#define V_NCSI_SOURCE(x) ((x) << S_NCSI_SOURCE)
+#define G_NCSI_SOURCE(x) (((x) >> S_NCSI_SOURCE) & M_NCSI_SOURCE)
+
+#define A_MPS_TX_INT_ENABLE 0x9404
+
+#define S_PORTERR    16
+#define V_PORTERR(x) ((x) << S_PORTERR)
+#define F_PORTERR    V_PORTERR(1U)
+
+#define S_FRMERR    15
+#define V_FRMERR(x) ((x) << S_FRMERR)
+#define F_FRMERR    V_FRMERR(1U)
+
+#define S_SECNTERR    14
+#define V_SECNTERR(x) ((x) << S_SECNTERR)
+#define F_SECNTERR    V_SECNTERR(1U)
+
+#define S_BUBBLE    13
+#define V_BUBBLE(x) ((x) << S_BUBBLE)
+#define F_BUBBLE    V_BUBBLE(1U)
+
+#define S_TXDESCFIFO    9
+#define M_TXDESCFIFO    0xfU
+#define V_TXDESCFIFO(x) ((x) << S_TXDESCFIFO)
+#define G_TXDESCFIFO(x) (((x) >> S_TXDESCFIFO) & M_TXDESCFIFO)
+
+#define S_TXDATAFIFO    5
+#define M_TXDATAFIFO    0xfU
+#define V_TXDATAFIFO(x) ((x) << S_TXDATAFIFO)
+#define G_TXDATAFIFO(x) (((x) >> S_TXDATAFIFO) & M_TXDATAFIFO)
+
+#define S_NCSIFIFO    4
+#define V_NCSIFIFO(x) ((x) << S_NCSIFIFO)
+#define F_NCSIFIFO    V_NCSIFIFO(1U)
+
+#define S_TPFIFO    0
+#define M_TPFIFO    0xfU
+#define V_TPFIFO(x) ((x) << S_TPFIFO)
+#define G_TPFIFO(x) (((x) >> S_TPFIFO) & M_TPFIFO)
+
+#define A_MPS_TX_INT_CAUSE 0x9408
+#define A_MPS_TX_PERR_ENABLE 0x9410
+#define A_MPS_TX_PERR_INJECT 0x9414
+
+#define S_MPSTXMEMSEL    1
+#define M_MPSTXMEMSEL    0x1fU
+#define V_MPSTXMEMSEL(x) ((x) << S_MPSTXMEMSEL)
+#define G_MPSTXMEMSEL(x) (((x) >> S_MPSTXMEMSEL) & M_MPSTXMEMSEL)
+
+#define A_MPS_TX_SE_CNT_TP01 0x9418
+#define A_MPS_TX_SE_CNT_TP23 0x941c
+#define A_MPS_TX_SE_CNT_MAC01 0x9420
+#define A_MPS_TX_SE_CNT_MAC23 0x9424
+#define A_MPS_TX_SECNT_SPI_BUBBLE_ERR 0x9428
+
+#define S_BUBBLEERR    16
+#define M_BUBBLEERR    0xffU
+#define V_BUBBLEERR(x) ((x) << S_BUBBLEERR)
+#define G_BUBBLEERR(x) (((x) >> S_BUBBLEERR) & M_BUBBLEERR)
+
+#define S_SPI    8
+#define M_SPI    0xffU
+#define V_SPI(x) ((x) << S_SPI)
+#define G_SPI(x) (((x) >> S_SPI) & M_SPI)
+
+#define S_SECNT    0
+#define M_SECNT    0xffU
+#define V_SECNT(x) ((x) << S_SECNT)
+#define G_SECNT(x) (((x) >> S_SECNT) & M_SECNT)
+
+#define A_MPS_TX_SECNT_BUBBLE_CLR 0x942c
+
+#define S_BUBBLECLR    8
+#define M_BUBBLECLR    0xffU
+#define V_BUBBLECLR(x) ((x) << S_BUBBLECLR)
+#define G_BUBBLECLR(x) (((x) >> S_BUBBLECLR) & M_BUBBLECLR)
+
+#define S_NCSISECNT    20
+#define V_NCSISECNT(x) ((x) << S_NCSISECNT)
+#define F_NCSISECNT    V_NCSISECNT(1U)
+
+#define S_LPBKSECNT    16
+#define M_LPBKSECNT    0xfU
+#define V_LPBKSECNT(x) ((x) << S_LPBKSECNT)
+#define G_LPBKSECNT(x) (((x) >> S_LPBKSECNT) & M_LPBKSECNT)
+
+#define A_MPS_TX_PORT_ERR 0x9430
+
+#define S_LPBKPT3    7
+#define V_LPBKPT3(x) ((x) << S_LPBKPT3)
+#define F_LPBKPT3    V_LPBKPT3(1U)
+
+#define S_LPBKPT2    6
+#define V_LPBKPT2(x) ((x) << S_LPBKPT2)
+#define F_LPBKPT2    V_LPBKPT2(1U)
+
+#define S_LPBKPT1    5
+#define V_LPBKPT1(x) ((x) << S_LPBKPT1)
+#define F_LPBKPT1    V_LPBKPT1(1U)
+
+#define S_LPBKPT0    4
+#define V_LPBKPT0(x) ((x) << S_LPBKPT0)
+#define F_LPBKPT0    V_LPBKPT0(1U)
+
+#define S_PT3    3
+#define V_PT3(x) ((x) << S_PT3)
+#define F_PT3    V_PT3(1U)
+
+#define S_PT2    2
+#define V_PT2(x) ((x) << S_PT2)
+#define F_PT2    V_PT2(1U)
+
+#define S_PT1    1
+#define V_PT1(x) ((x) << S_PT1)
+#define F_PT1    V_PT1(1U)
+
+#define S_PT0    0
+#define V_PT0(x) ((x) << S_PT0)
+#define F_PT0    V_PT0(1U)
+
+#define A_MPS_TX_LPBK_DROP_BP_CTL_CH0 0x9434
+
+#define S_BPEN    1
+#define V_BPEN(x) ((x) << S_BPEN)
+#define F_BPEN    V_BPEN(1U)
+
+#define S_DROPEN    0
+#define V_DROPEN(x) ((x) << S_DROPEN)
+#define F_DROPEN    V_DROPEN(1U)
+
+#define A_MPS_TX_LPBK_DROP_BP_CTL_CH1 0x9438
+#define A_MPS_TX_LPBK_DROP_BP_CTL_CH2 0x943c
+#define A_MPS_TX_LPBK_DROP_BP_CTL_CH3 0x9440
+#define A_MPS_TX_DEBUG_REG_TP2TX_10 0x9444
+
+#define S_SOPCH1    31
+#define V_SOPCH1(x) ((x) << S_SOPCH1)
+#define F_SOPCH1    V_SOPCH1(1U)
+
+#define S_EOPCH1    30
+#define V_EOPCH1(x) ((x) << S_EOPCH1)
+#define F_EOPCH1    V_EOPCH1(1U)
+
+#define S_SIZECH1    27
+#define M_SIZECH1    0x7U
+#define V_SIZECH1(x) ((x) << S_SIZECH1)
+#define G_SIZECH1(x) (((x) >> S_SIZECH1) & M_SIZECH1)
+
+#define S_ERRCH1    26
+#define V_ERRCH1(x) ((x) << S_ERRCH1)
+#define F_ERRCH1    V_ERRCH1(1U)
+
+#define S_FULLCH1    25
+#define V_FULLCH1(x) ((x) << S_FULLCH1)
+#define F_FULLCH1    V_FULLCH1(1U)
+
+#define S_VALIDCH1    24
+#define V_VALIDCH1(x) ((x) << S_VALIDCH1)
+#define F_VALIDCH1    V_VALIDCH1(1U)
+
+#define S_DATACH1    16
+#define M_DATACH1    0xffU
+#define V_DATACH1(x) ((x) << S_DATACH1)
+#define G_DATACH1(x) (((x) >> S_DATACH1) & M_DATACH1)
+
+#define S_SOPCH0    15
+#define V_SOPCH0(x) ((x) << S_SOPCH0)
+#define F_SOPCH0    V_SOPCH0(1U)
+
+#define S_EOPCH0    14
+#define V_EOPCH0(x) ((x) << S_EOPCH0)
+#define F_EOPCH0    V_EOPCH0(1U)
+
+#define S_SIZECH0    11
+#define M_SIZECH0    0x7U
+#define V_SIZECH0(x) ((x) << S_SIZECH0)
+#define G_SIZECH0(x) (((x) >> S_SIZECH0) & M_SIZECH0)
+
+#define S_ERRCH0    10
+#define V_ERRCH0(x) ((x) << S_ERRCH0)
+#define F_ERRCH0    V_ERRCH0(1U)
+
+#define S_FULLCH0    9
+#define V_FULLCH0(x) ((x) << S_FULLCH0)
+#define F_FULLCH0    V_FULLCH0(1U)
+
+#define S_VALIDCH0    8
+#define V_VALIDCH0(x) ((x) << S_VALIDCH0)
+#define F_VALIDCH0    V_VALIDCH0(1U)
+
+#define S_DATACH0    0
+#define M_DATACH0    0xffU
+#define V_DATACH0(x) ((x) << S_DATACH0)
+#define G_DATACH0(x) (((x) >> S_DATACH0) & M_DATACH0)
+
+#define A_MPS_TX_DEBUG_REG_TP2TX_32 0x9448
+
+#define S_SOPCH3    31
+#define V_SOPCH3(x) ((x) << S_SOPCH3)
+#define F_SOPCH3    V_SOPCH3(1U)
+
+#define S_EOPCH3    30
+#define V_EOPCH3(x) ((x) << S_EOPCH3)
+#define F_EOPCH3    V_EOPCH3(1U)
+
+#define S_SIZECH3    27
+#define M_SIZECH3    0x7U
+#define V_SIZECH3(x) ((x) << S_SIZECH3)
+#define G_SIZECH3(x) (((x) >> S_SIZECH3) & M_SIZECH3)
+
+#define S_ERRCH3    26
+#define V_ERRCH3(x) ((x) << S_ERRCH3)
+#define F_ERRCH3    V_ERRCH3(1U)
+
+#define S_FULLCH3    25
+#define V_FULLCH3(x) ((x) << S_FULLCH3)
+#define F_FULLCH3    V_FULLCH3(1U)
+
+#define S_VALIDCH3    24
+#define V_VALIDCH3(x) ((x) << S_VALIDCH3)
+#define F_VALIDCH3    V_VALIDCH3(1U)
+
+#define S_DATACH3    16
+#define M_DATACH3    0xffU
+#define V_DATACH3(x) ((x) << S_DATACH3)
+#define G_DATACH3(x) (((x) >> S_DATACH3) & M_DATACH3)
+
+#define S_SOPCH2    15
+#define V_SOPCH2(x) ((x) << S_SOPCH2)
+#define F_SOPCH2    V_SOPCH2(1U)
+
+#define S_EOPCH2    14
+#define V_EOPCH2(x) ((x) << S_EOPCH2)
+#define F_EOPCH2    V_EOPCH2(1U)
+
+#define S_SIZECH2    11
+#define M_SIZECH2    0x7U
+#define V_SIZECH2(x) ((x) << S_SIZECH2)
+#define G_SIZECH2(x) (((x) >> S_SIZECH2) & M_SIZECH2)
+
+#define S_ERRCH2    10
+#define V_ERRCH2(x) ((x) << S_ERRCH2)
+#define F_ERRCH2    V_ERRCH2(1U)
+
+#define S_FULLCH2    9
+#define V_FULLCH2(x) ((x) << S_FULLCH2)
+#define F_FULLCH2    V_FULLCH2(1U)
+
+#define S_VALIDCH2    8
+#define V_VALIDCH2(x) ((x) << S_VALIDCH2)
+#define F_VALIDCH2    V_VALIDCH2(1U)
+
+#define S_DATACH2    0
+#define M_DATACH2    0xffU
+#define V_DATACH2(x) ((x) << S_DATACH2)
+#define G_DATACH2(x) (((x) >> S_DATACH2) & M_DATACH2)
+
+#define A_MPS_TX_DEBUG_REG_TX2MAC_10 0x944c
+
+#define S_SOPPT1    31
+#define V_SOPPT1(x) ((x) << S_SOPPT1)
+#define F_SOPPT1    V_SOPPT1(1U)
+
+#define S_EOPPT1    30
+#define V_EOPPT1(x) ((x) << S_EOPPT1)
+#define F_EOPPT1    V_EOPPT1(1U)
+
+#define S_SIZEPT1    27
+#define M_SIZEPT1    0x7U
+#define V_SIZEPT1(x) ((x) << S_SIZEPT1)
+#define G_SIZEPT1(x) (((x) >> S_SIZEPT1) & M_SIZEPT1)
+
+#define S_ERRPT1    26
+#define V_ERRPT1(x) ((x) << S_ERRPT1)
+#define F_ERRPT1    V_ERRPT1(1U)
+
+#define S_FULLPT1    25
+#define V_FULLPT1(x) ((x) << S_FULLPT1)
+#define F_FULLPT1    V_FULLPT1(1U)
+
+#define S_VALIDPT1    24
+#define V_VALIDPT1(x) ((x) << S_VALIDPT1)
+#define F_VALIDPT1    V_VALIDPT1(1U)
+
+#define S_DATAPT1    16
+#define M_DATAPT1    0xffU
+#define V_DATAPT1(x) ((x) << S_DATAPT1)
+#define G_DATAPT1(x) (((x) >> S_DATAPT1) & M_DATAPT1)
+
+#define S_SOPPT0    15
+#define V_SOPPT0(x) ((x) << S_SOPPT0)
+#define F_SOPPT0    V_SOPPT0(1U)
+
+#define S_EOPPT0    14
+#define V_EOPPT0(x) ((x) << S_EOPPT0)
+#define F_EOPPT0    V_EOPPT0(1U)
+
+#define S_SIZEPT0    11
+#define M_SIZEPT0    0x7U
+#define V_SIZEPT0(x) ((x) << S_SIZEPT0)
+#define G_SIZEPT0(x) (((x) >> S_SIZEPT0) & M_SIZEPT0)
+
+#define S_ERRPT0    10
+#define V_ERRPT0(x) ((x) << S_ERRPT0)
+#define F_ERRPT0    V_ERRPT0(1U)
+
+#define S_FULLPT0    9
+#define V_FULLPT0(x) ((x) << S_FULLPT0)
+#define F_FULLPT0    V_FULLPT0(1U)
+
+#define S_VALIDPT0    8
+#define V_VALIDPT0(x) ((x) << S_VALIDPT0)
+#define F_VALIDPT0    V_VALIDPT0(1U)
+
+#define S_DATAPT0    0
+#define M_DATAPT0    0xffU
+#define V_DATAPT0(x) ((x) << S_DATAPT0)
+#define G_DATAPT0(x) (((x) >> S_DATAPT0) & M_DATAPT0)
+
+#define A_MPS_TX_DEBUG_REG_TX2MAC_32 0x9450
+
+#define S_SOPPT3    31
+#define V_SOPPT3(x) ((x) << S_SOPPT3)
+#define F_SOPPT3    V_SOPPT3(1U)
+
+#define S_EOPPT3    30
+#define V_EOPPT3(x) ((x) << S_EOPPT3)
+#define F_EOPPT3    V_EOPPT3(1U)
+
+#define S_SIZEPT3    27
+#define M_SIZEPT3    0x7U
+#define V_SIZEPT3(x) ((x) << S_SIZEPT3)
+#define G_SIZEPT3(x) (((x) >> S_SIZEPT3) & M_SIZEPT3)
+
+#define S_ERRPT3    26
+#define V_ERRPT3(x) ((x) << S_ERRPT3)
+#define F_ERRPT3    V_ERRPT3(1U)
+
+#define S_FULLPT3    25
+#define V_FULLPT3(x) ((x) << S_FULLPT3)
+#define F_FULLPT3    V_FULLPT3(1U)
+
+#define S_VALIDPT3    24
+#define V_VALIDPT3(x) ((x) << S_VALIDPT3)
+#define F_VALIDPT3    V_VALIDPT3(1U)
+
+#define S_DATAPT3    16
+#define M_DATAPT3    0xffU
+#define V_DATAPT3(x) ((x) << S_DATAPT3)
+#define G_DATAPT3(x) (((x) >> S_DATAPT3) & M_DATAPT3)
+
+#define S_SOPPT2    15
+#define V_SOPPT2(x) ((x) << S_SOPPT2)
+#define F_SOPPT2    V_SOPPT2(1U)
+
+#define S_EOPPT2    14
+#define V_EOPPT2(x) ((x) << S_EOPPT2)
+#define F_EOPPT2    V_EOPPT2(1U)
+
+#define S_SIZEPT2    11
+#define M_SIZEPT2    0x7U
+#define V_SIZEPT2(x) ((x) << S_SIZEPT2)
+#define G_SIZEPT2(x) (((x) >> S_SIZEPT2) & M_SIZEPT2)
+
+#define S_ERRPT2    10
+#define V_ERRPT2(x) ((x) << S_ERRPT2)
+#define F_ERRPT2    V_ERRPT2(1U)
+
+#define S_FULLPT2    9
+#define V_FULLPT2(x) ((x) << S_FULLPT2)
+#define F_FULLPT2    V_FULLPT2(1U)
+
+#define S_VALIDPT2    8
+#define V_VALIDPT2(x) ((x) << S_VALIDPT2)
+#define F_VALIDPT2    V_VALIDPT2(1U)
+
+#define S_DATAPT2    0
+#define M_DATAPT2    0xffU
+#define V_DATAPT2(x) ((x) << S_DATAPT2)
+#define G_DATAPT2(x) (((x) >> S_DATAPT2) & M_DATAPT2)
+
+#define A_MPS_TX_SGE_CH_PAUSE_IGNR 0x9454
+
+#define S_SGEPAUSEIGNR    0
+#define M_SGEPAUSEIGNR    0xfU
+#define V_SGEPAUSEIGNR(x) ((x) << S_SGEPAUSEIGNR)
+#define G_SGEPAUSEIGNR(x) (((x) >> S_SGEPAUSEIGNR) & M_SGEPAUSEIGNR)
+
+#define A_MPS_T5_TX_SGE_CH_PAUSE_IGNR 0x9454
+
+#define S_T5SGEPAUSEIGNR    0
+#define M_T5SGEPAUSEIGNR    0xffffU
+#define V_T5SGEPAUSEIGNR(x) ((x) << S_T5SGEPAUSEIGNR)
+#define G_T5SGEPAUSEIGNR(x) (((x) >> S_T5SGEPAUSEIGNR) & M_T5SGEPAUSEIGNR)
+
+#define A_MPS_TX_DEBUG_SUBPART_SEL 0x9458
+
+#define S_SUBPRTH    11
+#define M_SUBPRTH    0x1fU
+#define V_SUBPRTH(x) ((x) << S_SUBPRTH)
+#define G_SUBPRTH(x) (((x) >> S_SUBPRTH) & M_SUBPRTH)
+
+#define S_PORTH    8
+#define M_PORTH    0x7U
+#define V_PORTH(x) ((x) << S_PORTH)
+#define G_PORTH(x) (((x) >> S_PORTH) & M_PORTH)
+
+#define S_SUBPRTL    3
+#define M_SUBPRTL    0x1fU
+#define V_SUBPRTL(x) ((x) << S_SUBPRTL)
+#define G_SUBPRTL(x) (((x) >> S_SUBPRTL) & M_SUBPRTL)
+
+#define S_PORTL    0
+#define M_PORTL    0x7U
+#define V_PORTL(x) ((x) << S_PORTL)
+#define G_PORTL(x) (((x) >> S_PORTL) & M_PORTL)
+
+#define A_MPS_TX_PAD_CTL 0x945c
+
+#define S_LPBKPADENPT3    7
+#define V_LPBKPADENPT3(x) ((x) << S_LPBKPADENPT3)
+#define F_LPBKPADENPT3    V_LPBKPADENPT3(1U)
+
+#define S_LPBKPADENPT2    6
+#define V_LPBKPADENPT2(x) ((x) << S_LPBKPADENPT2)
+#define F_LPBKPADENPT2    V_LPBKPADENPT2(1U)
+
+#define S_LPBKPADENPT1    5
+#define V_LPBKPADENPT1(x) ((x) << S_LPBKPADENPT1)
+#define F_LPBKPADENPT1    V_LPBKPADENPT1(1U)
+
+#define S_LPBKPADENPT0    4
+#define V_LPBKPADENPT0(x) ((x) << S_LPBKPADENPT0)
+#define F_LPBKPADENPT0    V_LPBKPADENPT0(1U)
+
+#define S_MACPADENPT3    3
+#define V_MACPADENPT3(x) ((x) << S_MACPADENPT3)
+#define F_MACPADENPT3    V_MACPADENPT3(1U)
+
+#define S_MACPADENPT2    2
+#define V_MACPADENPT2(x) ((x) << S_MACPADENPT2)
+#define F_MACPADENPT2    V_MACPADENPT2(1U)
+
+#define S_MACPADENPT1    1
+#define V_MACPADENPT1(x) ((x) << S_MACPADENPT1)
+#define F_MACPADENPT1    V_MACPADENPT1(1U)
+
+#define S_MACPADENPT0    0
+#define V_MACPADENPT0(x) ((x) << S_MACPADENPT0)
+#define F_MACPADENPT0    V_MACPADENPT0(1U)
+
+#define A_MPS_TX_PFVF_PORT_DROP_TP 0x9460
+
+#define S_TP2MPS_CH3    24
+#define M_TP2MPS_CH3    0xffU
+#define V_TP2MPS_CH3(x) ((x) << S_TP2MPS_CH3)
+#define G_TP2MPS_CH3(x) (((x) >> S_TP2MPS_CH3) & M_TP2MPS_CH3)
+
+#define S_TP2MPS_CH2    16
+#define M_TP2MPS_CH2    0xffU
+#define V_TP2MPS_CH2(x) ((x) << S_TP2MPS_CH2)
+#define G_TP2MPS_CH2(x) (((x) >> S_TP2MPS_CH2) & M_TP2MPS_CH2)
+
+#define S_TP2MPS_CH1    8
+#define M_TP2MPS_CH1    0xffU
+#define V_TP2MPS_CH1(x) ((x) << S_TP2MPS_CH1)
+#define G_TP2MPS_CH1(x) (((x) >> S_TP2MPS_CH1) & M_TP2MPS_CH1)
+
+#define S_TP2MPS_CH0    0
+#define M_TP2MPS_CH0    0xffU
+#define V_TP2MPS_CH0(x) ((x) << S_TP2MPS_CH0)
+#define G_TP2MPS_CH0(x) (((x) >> S_TP2MPS_CH0) & M_TP2MPS_CH0)
+
+#define A_MPS_TX_PFVF_PORT_DROP_NCSI 0x9464
+
+#define S_NCSI_CH4    0
+#define M_NCSI_CH4    0xffU
+#define V_NCSI_CH4(x) ((x) << S_NCSI_CH4)
+#define G_NCSI_CH4(x) (((x) >> S_NCSI_CH4) & M_NCSI_CH4)
+
+#define A_MPS_TX_PFVF_PORT_DROP_CTL 0x9468
+
+#define S_PFNOVFDROP    5
+#define V_PFNOVFDROP(x) ((x) << S_PFNOVFDROP)
+#define F_PFNOVFDROP    V_PFNOVFDROP(1U)
+
+#define S_NCSI_CH4_CLR    4
+#define V_NCSI_CH4_CLR(x) ((x) << S_NCSI_CH4_CLR)
+#define F_NCSI_CH4_CLR    V_NCSI_CH4_CLR(1U)
+
+#define S_TP2MPS_CH3_CLR    3
+#define V_TP2MPS_CH3_CLR(x) ((x) << S_TP2MPS_CH3_CLR)
+#define F_TP2MPS_CH3_CLR    V_TP2MPS_CH3_CLR(1U)
+
+#define S_TP2MPS_CH2_CLR    2
+#define V_TP2MPS_CH2_CLR(x) ((x) << S_TP2MPS_CH2_CLR)
+#define F_TP2MPS_CH2_CLR    V_TP2MPS_CH2_CLR(1U)
+
+#define S_TP2MPS_CH1_CLR    1
+#define V_TP2MPS_CH1_CLR(x) ((x) << S_TP2MPS_CH1_CLR)
+#define F_TP2MPS_CH1_CLR    V_TP2MPS_CH1_CLR(1U)
+
+#define S_TP2MPS_CH0_CLR    0
+#define V_TP2MPS_CH0_CLR(x) ((x) << S_TP2MPS_CH0_CLR)
+#define F_TP2MPS_CH0_CLR    V_TP2MPS_CH0_CLR(1U)
+
+#define A_MPS_TX_CGEN 0x946c
+
+#define S_TXOUTLPBK3_CGEN    31
+#define V_TXOUTLPBK3_CGEN(x) ((x) << S_TXOUTLPBK3_CGEN)
+#define F_TXOUTLPBK3_CGEN    V_TXOUTLPBK3_CGEN(1U)
+
+#define S_TXOUTLPBK2_CGEN    30
+#define V_TXOUTLPBK2_CGEN(x) ((x) << S_TXOUTLPBK2_CGEN)
+#define F_TXOUTLPBK2_CGEN    V_TXOUTLPBK2_CGEN(1U)
+
+#define S_TXOUTLPBK1_CGEN    29
+#define V_TXOUTLPBK1_CGEN(x) ((x) << S_TXOUTLPBK1_CGEN)
+#define F_TXOUTLPBK1_CGEN    V_TXOUTLPBK1_CGEN(1U)
+
+#define S_TXOUTLPBK0_CGEN    28
+#define V_TXOUTLPBK0_CGEN(x) ((x) << S_TXOUTLPBK0_CGEN)
+#define F_TXOUTLPBK0_CGEN    V_TXOUTLPBK0_CGEN(1U)
+
+#define S_TXOUTMAC3_CGEN    27
+#define V_TXOUTMAC3_CGEN(x) ((x) << S_TXOUTMAC3_CGEN)
+#define F_TXOUTMAC3_CGEN    V_TXOUTMAC3_CGEN(1U)
+
+#define S_TXOUTMAC2_CGEN    26
+#define V_TXOUTMAC2_CGEN(x) ((x) << S_TXOUTMAC2_CGEN)
+#define F_TXOUTMAC2_CGEN    V_TXOUTMAC2_CGEN(1U)
+
+#define S_TXOUTMAC1_CGEN    25
+#define V_TXOUTMAC1_CGEN(x) ((x) << S_TXOUTMAC1_CGEN)
+#define F_TXOUTMAC1_CGEN    V_TXOUTMAC1_CGEN(1U)
+
+#define S_TXOUTMAC0_CGEN    24
+#define V_TXOUTMAC0_CGEN(x) ((x) << S_TXOUTMAC0_CGEN)
+#define F_TXOUTMAC0_CGEN    V_TXOUTMAC0_CGEN(1U)
+
+#define S_TXSCHLPBK3_CGEN    23
+#define V_TXSCHLPBK3_CGEN(x) ((x) << S_TXSCHLPBK3_CGEN)
+#define F_TXSCHLPBK3_CGEN    V_TXSCHLPBK3_CGEN(1U)
+
+#define S_TXSCHLPBK2_CGEN    22
+#define V_TXSCHLPBK2_CGEN(x) ((x) << S_TXSCHLPBK2_CGEN)
+#define F_TXSCHLPBK2_CGEN    V_TXSCHLPBK2_CGEN(1U)
+
+#define S_TXSCHLPBK1_CGEN    21
+#define V_TXSCHLPBK1_CGEN(x) ((x) << S_TXSCHLPBK1_CGEN)
+#define F_TXSCHLPBK1_CGEN    V_TXSCHLPBK1_CGEN(1U)
+
+#define S_TXSCHLPBK0_CGEN    20
+#define V_TXSCHLPBK0_CGEN(x) ((x) << S_TXSCHLPBK0_CGEN)
+#define F_TXSCHLPBK0_CGEN    V_TXSCHLPBK0_CGEN(1U)
+
+#define S_TXSCHMAC3_CGEN    19
+#define V_TXSCHMAC3_CGEN(x) ((x) << S_TXSCHMAC3_CGEN)
+#define F_TXSCHMAC3_CGEN    V_TXSCHMAC3_CGEN(1U)
+
+#define S_TXSCHMAC2_CGEN    18
+#define V_TXSCHMAC2_CGEN(x) ((x) << S_TXSCHMAC2_CGEN)
+#define F_TXSCHMAC2_CGEN    V_TXSCHMAC2_CGEN(1U)
+
+#define S_TXSCHMAC1_CGEN    17
+#define V_TXSCHMAC1_CGEN(x) ((x) << S_TXSCHMAC1_CGEN)
+#define F_TXSCHMAC1_CGEN    V_TXSCHMAC1_CGEN(1U)
+
+#define S_TXSCHMAC0_CGEN    16
+#define V_TXSCHMAC0_CGEN(x) ((x) << S_TXSCHMAC0_CGEN)
+#define F_TXSCHMAC0_CGEN    V_TXSCHMAC0_CGEN(1U)
+
+#define S_TXINCH4_CGEN    15
+#define V_TXINCH4_CGEN(x) ((x) << S_TXINCH4_CGEN)
+#define F_TXINCH4_CGEN    V_TXINCH4_CGEN(1U)
+
+#define S_TXINCH3_CGEN    14
+#define V_TXINCH3_CGEN(x) ((x) << S_TXINCH3_CGEN)
+#define F_TXINCH3_CGEN    V_TXINCH3_CGEN(1U)
+
+#define S_TXINCH2_CGEN    13
+#define V_TXINCH2_CGEN(x) ((x) << S_TXINCH2_CGEN)
+#define F_TXINCH2_CGEN    V_TXINCH2_CGEN(1U)
+
+#define S_TXINCH1_CGEN    12
+#define V_TXINCH1_CGEN(x) ((x) << S_TXINCH1_CGEN)
+#define F_TXINCH1_CGEN    V_TXINCH1_CGEN(1U)
+
+#define S_TXINCH0_CGEN    11
+#define V_TXINCH0_CGEN(x) ((x) << S_TXINCH0_CGEN)
+#define F_TXINCH0_CGEN    V_TXINCH0_CGEN(1U)
+
+#define A_MPS_TX_CGEN_DYNAMIC 0x9470
+#define A_MPS_STAT_CTL 0x9600
+
+#define S_COUNTVFINPF    1
+#define V_COUNTVFINPF(x) ((x) << S_COUNTVFINPF)
+#define F_COUNTVFINPF    V_COUNTVFINPF(1U)
+
+#define S_LPBKERRSTAT    0
+#define V_LPBKERRSTAT(x) ((x) << S_LPBKERRSTAT)
+#define F_LPBKERRSTAT    V_LPBKERRSTAT(1U)
+
+#define S_STATSTOPCTRL    10
+#define V_STATSTOPCTRL(x) ((x) << S_STATSTOPCTRL)
+#define F_STATSTOPCTRL    V_STATSTOPCTRL(1U)
+
+#define S_STOPSTAT    9
+#define V_STOPSTAT(x) ((x) << S_STOPSTAT)
+#define F_STOPSTAT    V_STOPSTAT(1U)
+
+#define S_STATWRITECTRL    8
+#define V_STATWRITECTRL(x) ((x) << S_STATWRITECTRL)
+#define F_STATWRITECTRL    V_STATWRITECTRL(1U)
+
+#define S_COUNTLBPF    7
+#define V_COUNTLBPF(x) ((x) << S_COUNTLBPF)
+#define F_COUNTLBPF    V_COUNTLBPF(1U)
+
+#define S_COUNTLBVF    6
+#define V_COUNTLBVF(x) ((x) << S_COUNTLBVF)
+#define F_COUNTLBVF    V_COUNTLBVF(1U)
+
+#define S_COUNTPAUSEMCRX    5
+#define V_COUNTPAUSEMCRX(x) ((x) << S_COUNTPAUSEMCRX)
+#define F_COUNTPAUSEMCRX    V_COUNTPAUSEMCRX(1U)
+
+#define S_COUNTPAUSESTATRX    4
+#define V_COUNTPAUSESTATRX(x) ((x) << S_COUNTPAUSESTATRX)
+#define F_COUNTPAUSESTATRX    V_COUNTPAUSESTATRX(1U)
+
+#define S_COUNTPAUSEMCTX    3
+#define V_COUNTPAUSEMCTX(x) ((x) << S_COUNTPAUSEMCTX)
+#define F_COUNTPAUSEMCTX    V_COUNTPAUSEMCTX(1U)
+
+#define S_COUNTPAUSESTATTX    2
+#define V_COUNTPAUSESTATTX(x) ((x) << S_COUNTPAUSESTATTX)
+#define F_COUNTPAUSESTATTX    V_COUNTPAUSESTATTX(1U)
+
+#define A_MPS_STAT_INT_ENABLE 0x9608
+
+#define S_PLREADSYNCERR    0
+#define V_PLREADSYNCERR(x) ((x) << S_PLREADSYNCERR)
+#define F_PLREADSYNCERR    V_PLREADSYNCERR(1U)
+
+#define A_MPS_STAT_INT_CAUSE 0x960c
+#define A_MPS_STAT_PERR_INT_ENABLE_SRAM 0x9610
+
+#define S_RXBG    20
+#define V_RXBG(x) ((x) << S_RXBG)
+#define F_RXBG    V_RXBG(1U)
+
+#define S_RXVF    18
+#define M_RXVF    0x3U
+#define V_RXVF(x) ((x) << S_RXVF)
+#define G_RXVF(x) (((x) >> S_RXVF) & M_RXVF)
+
+#define S_TXVF    16
+#define M_TXVF    0x3U
+#define V_TXVF(x) ((x) << S_TXVF)
+#define G_TXVF(x) (((x) >> S_TXVF) & M_TXVF)
+
+#define S_RXPF    13
+#define M_RXPF    0x7U
+#define V_RXPF(x) ((x) << S_RXPF)
+#define G_RXPF(x) (((x) >> S_RXPF) & M_RXPF)
+
+#define S_TXPF    11
+#define M_TXPF    0x3U
+#define V_TXPF(x) ((x) << S_TXPF)
+#define G_TXPF(x) (((x) >> S_TXPF) & M_TXPF)
+
+#define S_RXPORT    7
+#define M_RXPORT    0xfU
+#define V_RXPORT(x) ((x) << S_RXPORT)
+#define G_RXPORT(x) (((x) >> S_RXPORT) & M_RXPORT)
+
+#define S_LBPORT    4
+#define M_LBPORT    0x7U
+#define V_LBPORT(x) ((x) << S_LBPORT)
+#define G_LBPORT(x) (((x) >> S_LBPORT) & M_LBPORT)
+
+#define S_TXPORT    0
+#define M_TXPORT    0xfU
+#define V_TXPORT(x) ((x) << S_TXPORT)
+#define G_TXPORT(x) (((x) >> S_TXPORT) & M_TXPORT)
+
+#define S_T5_RXBG    27
+#define M_T5_RXBG    0x3U
+#define V_T5_RXBG(x) ((x) << S_T5_RXBG)
+#define G_T5_RXBG(x) (((x) >> S_T5_RXBG) & M_T5_RXBG)
+
+#define S_T5_RXPF    22
+#define M_T5_RXPF    0x1fU
+#define V_T5_RXPF(x) ((x) << S_T5_RXPF)
+#define G_T5_RXPF(x) (((x) >> S_T5_RXPF) & M_T5_RXPF)
+
+#define S_T5_TXPF    18
+#define M_T5_TXPF    0xfU
+#define V_T5_TXPF(x) ((x) << S_T5_TXPF)
+#define G_T5_TXPF(x) (((x) >> S_T5_TXPF) & M_T5_TXPF)
+
+#define S_T5_RXPORT    11
+#define M_T5_RXPORT    0x7fU
+#define V_T5_RXPORT(x) ((x) << S_T5_RXPORT)
+#define G_T5_RXPORT(x) (((x) >> S_T5_RXPORT) & M_T5_RXPORT)
+
+#define S_T5_LBPORT    6
+#define M_T5_LBPORT    0x1fU
+#define V_T5_LBPORT(x) ((x) << S_T5_LBPORT)
+#define G_T5_LBPORT(x) (((x) >> S_T5_LBPORT) & M_T5_LBPORT)
+
+#define S_T5_TXPORT    0
+#define M_T5_TXPORT    0x3fU
+#define V_T5_TXPORT(x) ((x) << S_T5_TXPORT)
+#define G_T5_TXPORT(x) (((x) >> S_T5_TXPORT) & M_T5_TXPORT)
+
+#define A_MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614
+#define A_MPS_STAT_PERR_ENABLE_SRAM 0x9618
+#define A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO 0x961c
+
+#define S_TX    12
+#define M_TX    0xffU
+#define V_TX(x) ((x) << S_TX)
+#define G_TX(x) (((x) >> S_TX) & M_TX)
+
+#define S_TXPAUSEFIFO    8
+#define M_TXPAUSEFIFO    0xfU
+#define V_TXPAUSEFIFO(x) ((x) << S_TXPAUSEFIFO)
+#define G_TXPAUSEFIFO(x) (((x) >> S_TXPAUSEFIFO) & M_TXPAUSEFIFO)
+
+#define S_DROP    0
+#define M_DROP    0xffU
+#define V_DROP(x) ((x) << S_DROP)
+#define G_DROP(x) (((x) >> S_DROP) & M_DROP)
+
+#define S_TXCH    20
+#define M_TXCH    0xfU
+#define V_TXCH(x) ((x) << S_TXCH)
+#define G_TXCH(x) (((x) >> S_TXCH) & M_TXCH)
+
+#define A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620
+#define A_MPS_STAT_PERR_ENABLE_TX_FIFO 0x9624
+#define A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO 0x9628
+
+#define S_PAUSEFIFO    20
+#define M_PAUSEFIFO    0xfU
+#define V_PAUSEFIFO(x) ((x) << S_PAUSEFIFO)
+#define G_PAUSEFIFO(x) (((x) >> S_PAUSEFIFO) & M_PAUSEFIFO)
+
+#define S_LPBK    16
+#define M_LPBK    0xfU
+#define V_LPBK(x) ((x) << S_LPBK)
+#define G_LPBK(x) (((x) >> S_LPBK) & M_LPBK)
+
+#define S_NQ    8
+#define M_NQ    0xffU
+#define V_NQ(x) ((x) << S_NQ)
+#define G_NQ(x) (((x) >> S_NQ) & M_NQ)
+
+#define S_PV    4
+#define M_PV    0xfU
+#define V_PV(x) ((x) << S_PV)
+#define G_PV(x) (((x) >> S_PV) & M_PV)
+
+#define S_MAC    0
+#define M_MAC    0xfU
+#define V_MAC(x) ((x) << S_MAC)
+#define G_MAC(x) (((x) >> S_MAC) & M_MAC)
+
+#define A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c
+#define A_MPS_STAT_PERR_ENABLE_RX_FIFO 0x9630
+#define A_MPS_STAT_PERR_INJECT 0x9634
+
+#define S_STATMEMSEL    1
+#define M_STATMEMSEL    0x7fU
+#define V_STATMEMSEL(x) ((x) << S_STATMEMSEL)
+#define G_STATMEMSEL(x) (((x) >> S_STATMEMSEL) & M_STATMEMSEL)
+
+#define A_MPS_STAT_DEBUG_SUB_SEL 0x9638
+
+#define S_STATSSUBPRTH    5
+#define M_STATSSUBPRTH    0x1fU
+#define V_STATSSUBPRTH(x) ((x) << S_STATSSUBPRTH)
+#define G_STATSSUBPRTH(x) (((x) >> S_STATSSUBPRTH) & M_STATSSUBPRTH)
+
+#define S_STATSSUBPRTL    0
+#define M_STATSSUBPRTL    0x1fU
+#define V_STATSSUBPRTL(x) ((x) << S_STATSSUBPRTL)
+#define G_STATSSUBPRTL(x) (((x) >> S_STATSSUBPRTL) & M_STATSSUBPRTL)
+
+#define S_STATSUBPRTH    5
+#define M_STATSUBPRTH    0x1fU
+#define V_STATSUBPRTH(x) ((x) << S_STATSUBPRTH)
+#define G_STATSUBPRTH(x) (((x) >> S_STATSUBPRTH) & M_STATSUBPRTH)
+
+#define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
+#define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
+#define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
+#define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
+#define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
+#define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
+#define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
+#define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
+#define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
+#define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
+#define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
+#define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
+#define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
+#define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
+#define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
+#define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
+#define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
+#define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
+#define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
+#define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
+#define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
+#define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
+#define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
+#define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
+#define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
+#define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
+#define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
+#define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
+#define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
+#define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
+#define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
+#define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
+#define A_MPS_STAT_PERR_INT_ENABLE_SRAM1 0x96c0
+
+#define S_T5_RXVF    5
+#define M_T5_RXVF    0x7U
+#define V_T5_RXVF(x) ((x) << S_T5_RXVF)
+#define G_T5_RXVF(x) (((x) >> S_T5_RXVF) & M_T5_RXVF)
+
+#define S_T5_TXVF    0
+#define M_T5_TXVF    0x1fU
+#define V_T5_TXVF(x) ((x) << S_T5_TXVF)
+#define G_T5_TXVF(x) (((x) >> S_T5_TXVF) & M_T5_TXVF)
+
+#define A_MPS_STAT_PERR_INT_CAUSE_SRAM1 0x96c4
+#define A_MPS_STAT_PERR_ENABLE_SRAM1 0x96c8
+#define A_MPS_STAT_STOP_UPD_BG 0x96cc
+
+#define S_BGRX    0
+#define M_BGRX    0xfU
+#define V_BGRX(x) ((x) << S_BGRX)
+#define G_BGRX(x) (((x) >> S_BGRX) & M_BGRX)
+
+#define A_MPS_STAT_STOP_UPD_PORT 0x96d0
+
+#define S_PTLPBK    8
+#define M_PTLPBK    0xfU
+#define V_PTLPBK(x) ((x) << S_PTLPBK)
+#define G_PTLPBK(x) (((x) >> S_PTLPBK) & M_PTLPBK)
+
+#define S_PTTX    4
+#define M_PTTX    0xfU
+#define V_PTTX(x) ((x) << S_PTTX)
+#define G_PTTX(x) (((x) >> S_PTTX) & M_PTTX)
+
+#define S_PTRX    0
+#define M_PTRX    0xfU
+#define V_PTRX(x) ((x) << S_PTRX)
+#define G_PTRX(x) (((x) >> S_PTRX) & M_PTRX)
+
+#define A_MPS_STAT_STOP_UPD_PF 0x96d4
+
+#define S_PFTX    8
+#define M_PFTX    0xffU
+#define V_PFTX(x) ((x) << S_PFTX)
+#define G_PFTX(x) (((x) >> S_PFTX) & M_PFTX)
+
+#define S_PFRX    0
+#define M_PFRX    0xffU
+#define V_PFRX(x) ((x) << S_PFRX)
+#define G_PFRX(x) (((x) >> S_PFRX) & M_PFRX)
+
+#define A_MPS_STAT_STOP_UPD_TX_VF_0_31 0x96d8
+#define A_MPS_STAT_STOP_UPD_TX_VF_32_63 0x96dc
+#define A_MPS_STAT_STOP_UPD_TX_VF_64_95 0x96e0
+#define A_MPS_STAT_STOP_UPD_TX_VF_96_127 0x96e4
+#define A_MPS_STAT_STOP_UPD_RX_VF_0_31 0x96e8
+#define A_MPS_STAT_STOP_UPD_RX_VF_32_63 0x96ec
+#define A_MPS_STAT_STOP_UPD_RX_VF_64_95 0x96f0
+#define A_MPS_STAT_STOP_UPD_RX_VF_96_127 0x96f4
+#define A_MPS_TRC_CFG 0x9800
+
+#define S_TRCFIFOEMPTY    4
+#define V_TRCFIFOEMPTY(x) ((x) << S_TRCFIFOEMPTY)
+#define F_TRCFIFOEMPTY    V_TRCFIFOEMPTY(1U)
+
+#define S_TRCIGNOREDROPINPUT    3
+#define V_TRCIGNOREDROPINPUT(x) ((x) << S_TRCIGNOREDROPINPUT)
+#define F_TRCIGNOREDROPINPUT    V_TRCIGNOREDROPINPUT(1U)
+
+#define S_TRCKEEPDUPLICATES    2
+#define V_TRCKEEPDUPLICATES(x) ((x) << S_TRCKEEPDUPLICATES)
+#define F_TRCKEEPDUPLICATES    V_TRCKEEPDUPLICATES(1U)
+
+#define S_TRCEN    1
+#define V_TRCEN(x) ((x) << S_TRCEN)
+#define F_TRCEN    V_TRCEN(1U)
+
+#define S_TRCMULTIFILTER    0
+#define V_TRCMULTIFILTER(x) ((x) << S_TRCMULTIFILTER)
+#define F_TRCMULTIFILTER    V_TRCMULTIFILTER(1U)
+
+#define S_TRCMULTIRSSFILTER    5
+#define V_TRCMULTIRSSFILTER(x) ((x) << S_TRCMULTIRSSFILTER)
+#define F_TRCMULTIRSSFILTER    V_TRCMULTIRSSFILTER(1U)
+
+#define A_MPS_TRC_RSS_HASH 0x9804
+#define A_MPS_TRC_FILTER0_RSS_HASH 0x9804
+#define A_MPS_TRC_RSS_CONTROL 0x9808
+
+#define S_RSSCONTROL    16
+#define M_RSSCONTROL    0xffU
+#define V_RSSCONTROL(x) ((x) << S_RSSCONTROL)
+#define G_RSSCONTROL(x) (((x) >> S_RSSCONTROL) & M_RSSCONTROL)
+
+#define S_QUEUENUMBER    0
+#define M_QUEUENUMBER    0xffffU
+#define V_QUEUENUMBER(x) ((x) << S_QUEUENUMBER)
+#define G_QUEUENUMBER(x) (((x) >> S_QUEUENUMBER) & M_QUEUENUMBER)
+
+#define A_MPS_TRC_FILTER0_RSS_CONTROL 0x9808
+#define A_MPS_TRC_FILTER_MATCH_CTL_A 0x9810
+
+#define S_TFINVERTMATCH    24
+#define V_TFINVERTMATCH(x) ((x) << S_TFINVERTMATCH)
+#define F_TFINVERTMATCH    V_TFINVERTMATCH(1U)
+
+#define S_TFPKTTOOLARGE    23
+#define V_TFPKTTOOLARGE(x) ((x) << S_TFPKTTOOLARGE)
+#define F_TFPKTTOOLARGE    V_TFPKTTOOLARGE(1U)
+
+#define S_TFEN    22
+#define V_TFEN(x) ((x) << S_TFEN)
+#define F_TFEN    V_TFEN(1U)
+
+#define S_TFPORT    18
+#define M_TFPORT    0xfU
+#define V_TFPORT(x) ((x) << S_TFPORT)
+#define G_TFPORT(x) (((x) >> S_TFPORT) & M_TFPORT)
+
+#define S_TFDROP    17
+#define V_TFDROP(x) ((x) << S_TFDROP)
+#define F_TFDROP    V_TFDROP(1U)
+
+#define S_TFSOPEOPERR    16
+#define V_TFSOPEOPERR(x) ((x) << S_TFSOPEOPERR)
+#define F_TFSOPEOPERR    V_TFSOPEOPERR(1U)
+
+#define S_TFLENGTH    8
+#define M_TFLENGTH    0x1fU
+#define V_TFLENGTH(x) ((x) << S_TFLENGTH)
+#define G_TFLENGTH(x) (((x) >> S_TFLENGTH) & M_TFLENGTH)
+
+#define S_TFOFFSET    0
+#define M_TFOFFSET    0x1fU
+#define V_TFOFFSET(x) ((x) << S_TFOFFSET)
+#define G_TFOFFSET(x) (((x) >> S_TFOFFSET) & M_TFOFFSET)
+
+#define S_TFINSERTACTLEN    27
+#define V_TFINSERTACTLEN(x) ((x) << S_TFINSERTACTLEN)
+#define F_TFINSERTACTLEN    V_TFINSERTACTLEN(1U)
+
+#define S_TFINSERTTIMER    26
+#define V_TFINSERTTIMER(x) ((x) << S_TFINSERTTIMER)
+#define F_TFINSERTTIMER    V_TFINSERTTIMER(1U)
+
+#define S_T5_TFINVERTMATCH    25
+#define V_T5_TFINVERTMATCH(x) ((x) << S_T5_TFINVERTMATCH)
+#define F_T5_TFINVERTMATCH    V_T5_TFINVERTMATCH(1U)
+
+#define S_T5_TFPKTTOOLARGE    24
+#define V_T5_TFPKTTOOLARGE(x) ((x) << S_T5_TFPKTTOOLARGE)
+#define F_T5_TFPKTTOOLARGE    V_T5_TFPKTTOOLARGE(1U)
+
+#define S_T5_TFEN    23
+#define V_T5_TFEN(x) ((x) << S_T5_TFEN)
+#define F_T5_TFEN    V_T5_TFEN(1U)
+
+#define S_T5_TFPORT    18
+#define M_T5_TFPORT    0x1fU
+#define V_T5_TFPORT(x) ((x) << S_T5_TFPORT)
+#define G_T5_TFPORT(x) (((x) >> S_T5_TFPORT) & M_T5_TFPORT)
+
+#define A_MPS_TRC_FILTER_MATCH_CTL_B 0x9820
+
+#define S_TFMINPKTSIZE    16
+#define M_TFMINPKTSIZE    0x1ffU
+#define V_TFMINPKTSIZE(x) ((x) << S_TFMINPKTSIZE)
+#define G_TFMINPKTSIZE(x) (((x) >> S_TFMINPKTSIZE) & M_TFMINPKTSIZE)
+
+#define S_TFCAPTUREMAX    0
+#define M_TFCAPTUREMAX    0x3fffU
+#define V_TFCAPTUREMAX(x) ((x) << S_TFCAPTUREMAX)
+#define G_TFCAPTUREMAX(x) (((x) >> S_TFCAPTUREMAX) & M_TFCAPTUREMAX)
+
+#define A_MPS_TRC_FILTER_RUNT_CTL 0x9830
+
+#define S_TFRUNTSIZE    0
+#define M_TFRUNTSIZE    0x3fU
+#define V_TFRUNTSIZE(x) ((x) << S_TFRUNTSIZE)
+#define G_TFRUNTSIZE(x) (((x) >> S_TFRUNTSIZE) & M_TFRUNTSIZE)
+
+#define A_MPS_TRC_FILTER_DROP 0x9840
+
+#define S_TFDROPINPCOUNT    16
+#define M_TFDROPINPCOUNT    0xffffU
+#define V_TFDROPINPCOUNT(x) ((x) << S_TFDROPINPCOUNT)
+#define G_TFDROPINPCOUNT(x) (((x) >> S_TFDROPINPCOUNT) & M_TFDROPINPCOUNT)
+
+#define S_TFDROPBUFFERCOUNT    0
+#define M_TFDROPBUFFERCOUNT    0xffffU
+#define V_TFDROPBUFFERCOUNT(x) ((x) << S_TFDROPBUFFERCOUNT)
+#define G_TFDROPBUFFERCOUNT(x) (((x) >> S_TFDROPBUFFERCOUNT) & M_TFDROPBUFFERCOUNT)
+
+#define A_MPS_TRC_PERR_INJECT 0x9850
+
+#define S_TRCMEMSEL    1
+#define M_TRCMEMSEL    0xfU
+#define V_TRCMEMSEL(x) ((x) << S_TRCMEMSEL)
+#define G_TRCMEMSEL(x) (((x) >> S_TRCMEMSEL) & M_TRCMEMSEL)
+
+#define A_MPS_TRC_PERR_ENABLE 0x9854
+
+#define S_MISCPERR    8
+#define V_MISCPERR(x) ((x) << S_MISCPERR)
+#define F_MISCPERR    V_MISCPERR(1U)
+
+#define S_PKTFIFO    4
+#define M_PKTFIFO    0xfU
+#define V_PKTFIFO(x) ((x) << S_PKTFIFO)
+#define G_PKTFIFO(x) (((x) >> S_PKTFIFO) & M_PKTFIFO)
+
+#define S_FILTMEM    0
+#define M_FILTMEM    0xfU
+#define V_FILTMEM(x) ((x) << S_FILTMEM)
+#define G_FILTMEM(x) (((x) >> S_FILTMEM) & M_FILTMEM)
+
+#define A_MPS_TRC_INT_ENABLE 0x9858
+
+#define S_TRCPLERRENB    9
+#define V_TRCPLERRENB(x) ((x) << S_TRCPLERRENB)
+#define F_TRCPLERRENB    V_TRCPLERRENB(1U)
+
+#define A_MPS_TRC_INT_CAUSE 0x985c
+#define A_MPS_TRC_TIMESTAMP_L 0x9860
+#define A_MPS_TRC_TIMESTAMP_H 0x9864
+#define A_MPS_TRC_FILTER0_MATCH 0x9c00
+#define A_MPS_TRC_FILTER0_DONT_CARE 0x9c80
+#define A_MPS_TRC_FILTER1_MATCH 0x9d00
+#define A_MPS_TRC_FILTER1_DONT_CARE 0x9d80
+#define A_MPS_TRC_FILTER2_MATCH 0x9e00
+#define A_MPS_TRC_FILTER2_DONT_CARE 0x9e80
+#define A_MPS_TRC_FILTER3_MATCH 0x9f00
+#define A_MPS_TRC_FILTER3_DONT_CARE 0x9f80
+#define A_MPS_TRC_FILTER1_RSS_HASH 0x9ff0
+#define A_MPS_TRC_FILTER1_RSS_CONTROL 0x9ff4
+#define A_MPS_TRC_FILTER2_RSS_HASH 0x9ff8
+#define A_MPS_TRC_FILTER2_RSS_CONTROL 0x9ffc
+#define A_MPS_TRC_FILTER3_RSS_HASH 0xa000
+#define A_MPS_TRC_FILTER3_RSS_CONTROL 0xa004
+#define A_MPS_T5_TRC_RSS_HASH 0xa008
+#define A_MPS_T5_TRC_RSS_CONTROL 0xa00c
+#define A_MPS_TRC_VF_OFF_FILTER_0 0xa010
+
+#define S_TRCMPS2TP_MACONLY    20
+#define V_TRCMPS2TP_MACONLY(x) ((x) << S_TRCMPS2TP_MACONLY)
+#define F_TRCMPS2TP_MACONLY    V_TRCMPS2TP_MACONLY(1U)
+
+#define S_TRCALLMPS2TP    19
+#define V_TRCALLMPS2TP(x) ((x) << S_TRCALLMPS2TP)
+#define F_TRCALLMPS2TP    V_TRCALLMPS2TP(1U)
+
+#define S_TRCALLTP2MPS    18
+#define V_TRCALLTP2MPS(x) ((x) << S_TRCALLTP2MPS)
+#define F_TRCALLTP2MPS    V_TRCALLTP2MPS(1U)
+
+#define S_TRCALLVF    17
+#define V_TRCALLVF(x) ((x) << S_TRCALLVF)
+#define F_TRCALLVF    V_TRCALLVF(1U)
+
+#define S_TRC_OFLD_EN    16
+#define V_TRC_OFLD_EN(x) ((x) << S_TRC_OFLD_EN)
+#define F_TRC_OFLD_EN    V_TRC_OFLD_EN(1U)
+
+#define S_VFFILTEN    15
+#define V_VFFILTEN(x) ((x) << S_VFFILTEN)
+#define F_VFFILTEN    V_VFFILTEN(1U)
+
+#define S_VFFILTMASK    8
+#define M_VFFILTMASK    0x7fU
+#define V_VFFILTMASK(x) ((x) << S_VFFILTMASK)
+#define G_VFFILTMASK(x) (((x) >> S_VFFILTMASK) & M_VFFILTMASK)
+
+#define S_VFFILTVALID    7
+#define V_VFFILTVALID(x) ((x) << S_VFFILTVALID)
+#define F_VFFILTVALID    V_VFFILTVALID(1U)
+
+#define S_VFFILTDATA    0
+#define M_VFFILTDATA    0x7fU
+#define V_VFFILTDATA(x) ((x) << S_VFFILTDATA)
+#define G_VFFILTDATA(x) (((x) >> S_VFFILTDATA) & M_VFFILTDATA)
+
+#define A_MPS_TRC_VF_OFF_FILTER_1 0xa014
+#define A_MPS_TRC_VF_OFF_FILTER_2 0xa018
+#define A_MPS_TRC_VF_OFF_FILTER_3 0xa01c
+#define A_MPS_TRC_CGEN 0xa020
+
+#define S_MPSTRCCGEN    0
+#define M_MPSTRCCGEN    0xfU
+#define V_MPSTRCCGEN(x) ((x) << S_MPSTRCCGEN)
+#define G_MPSTRCCGEN(x) (((x) >> S_MPSTRCCGEN) & M_MPSTRCCGEN)
+
+#define A_MPS_CLS_CTL 0xd000
+
+#define S_MEMWRITEFAULT    4
+#define V_MEMWRITEFAULT(x) ((x) << S_MEMWRITEFAULT)
+#define F_MEMWRITEFAULT    V_MEMWRITEFAULT(1U)
+
+#define S_MEMWRITEWAITING    3
+#define V_MEMWRITEWAITING(x) ((x) << S_MEMWRITEWAITING)
+#define F_MEMWRITEWAITING    V_MEMWRITEWAITING(1U)
+
+#define S_CIMNOPROMISCUOUS    2
+#define V_CIMNOPROMISCUOUS(x) ((x) << S_CIMNOPROMISCUOUS)
+#define F_CIMNOPROMISCUOUS    V_CIMNOPROMISCUOUS(1U)
+
+#define S_HYPERVISORONLY    1
+#define V_HYPERVISORONLY(x) ((x) << S_HYPERVISORONLY)
+#define F_HYPERVISORONLY    V_HYPERVISORONLY(1U)
+
+#define S_VLANCLSEN    0
+#define V_VLANCLSEN(x) ((x) << S_VLANCLSEN)
+#define F_VLANCLSEN    V_VLANCLSEN(1U)
+
+#define A_MPS_CLS_ARB_WEIGHT 0xd004
+
+#define S_PLWEIGHT    16
+#define M_PLWEIGHT    0x1fU
+#define V_PLWEIGHT(x) ((x) << S_PLWEIGHT)
+#define G_PLWEIGHT(x) (((x) >> S_PLWEIGHT) & M_PLWEIGHT)
+
+#define S_CIMWEIGHT    8
+#define M_CIMWEIGHT    0x1fU
+#define V_CIMWEIGHT(x) ((x) << S_CIMWEIGHT)
+#define G_CIMWEIGHT(x) (((x) >> S_CIMWEIGHT) & M_CIMWEIGHT)
+
+#define S_LPBKWEIGHT    0
+#define M_LPBKWEIGHT    0x1fU
+#define V_LPBKWEIGHT(x) ((x) << S_LPBKWEIGHT)
+#define G_LPBKWEIGHT(x) (((x) >> S_LPBKWEIGHT) & M_LPBKWEIGHT)
+
+#define A_MPS_CLS_BMC_MAC_ADDR_L 0xd010
+#define A_MPS_CLS_BMC_MAC_ADDR_H 0xd014
+#define A_MPS_CLS_BMC_VLAN 0xd018
+#define A_MPS_CLS_PERR_INJECT 0xd01c
+
+#define S_CLS_MEMSEL    1
+#define M_CLS_MEMSEL    0x3U
+#define V_CLS_MEMSEL(x) ((x) << S_CLS_MEMSEL)
+#define G_CLS_MEMSEL(x) (((x) >> S_CLS_MEMSEL) & M_CLS_MEMSEL)
+
+#define A_MPS_CLS_PERR_ENABLE 0xd020
+
+#define S_HASHSRAM    2
+#define V_HASHSRAM(x) ((x) << S_HASHSRAM)
+#define F_HASHSRAM    V_HASHSRAM(1U)
+
+#define S_MATCHTCAM    1
+#define V_MATCHTCAM(x) ((x) << S_MATCHTCAM)
+#define F_MATCHTCAM    V_MATCHTCAM(1U)
+
+#define S_MATCHSRAM    0
+#define V_MATCHSRAM(x) ((x) << S_MATCHSRAM)
+#define F_MATCHSRAM    V_MATCHSRAM(1U)
+
+#define A_MPS_CLS_INT_ENABLE 0xd024
+
+#define S_PLERRENB    3
+#define V_PLERRENB(x) ((x) << S_PLERRENB)
+#define F_PLERRENB    V_PLERRENB(1U)
+
+#define A_MPS_CLS_INT_CAUSE 0xd028
+#define A_MPS_CLS_PL_TEST_DATA_L 0xd02c
+#define A_MPS_CLS_PL_TEST_DATA_H 0xd030
+#define A_MPS_CLS_PL_TEST_RES_DATA 0xd034
+
+#define S_CLS_PRIORITY    24
+#define M_CLS_PRIORITY    0x7U
+#define V_CLS_PRIORITY(x) ((x) << S_CLS_PRIORITY)
+#define G_CLS_PRIORITY(x) (((x) >> S_CLS_PRIORITY) & M_CLS_PRIORITY)
+
+#define S_CLS_REPLICATE    23
+#define V_CLS_REPLICATE(x) ((x) << S_CLS_REPLICATE)
+#define F_CLS_REPLICATE    V_CLS_REPLICATE(1U)
+
+#define S_CLS_INDEX    14
+#define M_CLS_INDEX    0x1ffU
+#define V_CLS_INDEX(x) ((x) << S_CLS_INDEX)
+#define G_CLS_INDEX(x) (((x) >> S_CLS_INDEX) & M_CLS_INDEX)
+
+#define S_CLS_VF    7
+#define M_CLS_VF    0x7fU
+#define V_CLS_VF(x) ((x) << S_CLS_VF)
+#define G_CLS_VF(x) (((x) >> S_CLS_VF) & M_CLS_VF)
+
+#define S_CLS_VF_VLD    6
+#define V_CLS_VF_VLD(x) ((x) << S_CLS_VF_VLD)
+#define F_CLS_VF_VLD    V_CLS_VF_VLD(1U)
+
+#define S_CLS_PF    3
+#define M_CLS_PF    0x7U
+#define V_CLS_PF(x) ((x) << S_CLS_PF)
+#define G_CLS_PF(x) (((x) >> S_CLS_PF) & M_CLS_PF)
+
+#define S_CLS_MATCH    0
+#define M_CLS_MATCH    0x7U
+#define V_CLS_MATCH(x) ((x) << S_CLS_MATCH)
+#define G_CLS_MATCH(x) (((x) >> S_CLS_MATCH) & M_CLS_MATCH)
+
+#define A_MPS_CLS_PL_TEST_CTL 0xd038
+
+#define S_PLTESTCTL    0
+#define V_PLTESTCTL(x) ((x) << S_PLTESTCTL)
+#define F_PLTESTCTL    V_PLTESTCTL(1U)
+
+#define A_MPS_CLS_PORT_BMC_CTL 0xd03c
+
+#define S_PRTBMCCTL    0
+#define V_PRTBMCCTL(x) ((x) << S_PRTBMCCTL)
+#define F_PRTBMCCTL    V_PRTBMCCTL(1U)
+
+#define A_MPS_CLS_VLAN_TABLE 0xdfc0
+
+#define S_VLAN_MASK    16
+#define M_VLAN_MASK    0xfffU
+#define V_VLAN_MASK(x) ((x) << S_VLAN_MASK)
+#define G_VLAN_MASK(x) (((x) >> S_VLAN_MASK) & M_VLAN_MASK)
+
+#define S_VLANPF    13
+#define M_VLANPF    0x7U
+#define V_VLANPF(x) ((x) << S_VLANPF)
+#define G_VLANPF(x) (((x) >> S_VLANPF) & M_VLANPF)
+
+#define S_VLAN_VALID    12
+#define V_VLAN_VALID(x) ((x) << S_VLAN_VALID)
+#define F_VLAN_VALID    V_VLAN_VALID(1U)
+
+#define A_MPS_CLS_SRAM_L 0xe000
+
+#define S_MULTILISTEN3    28
+#define V_MULTILISTEN3(x) ((x) << S_MULTILISTEN3)
+#define F_MULTILISTEN3    V_MULTILISTEN3(1U)
+
+#define S_MULTILISTEN2    27
+#define V_MULTILISTEN2(x) ((x) << S_MULTILISTEN2)
+#define F_MULTILISTEN2    V_MULTILISTEN2(1U)
+
+#define S_MULTILISTEN1    26
+#define V_MULTILISTEN1(x) ((x) << S_MULTILISTEN1)
+#define F_MULTILISTEN1    V_MULTILISTEN1(1U)
+
+#define S_MULTILISTEN0    25
+#define V_MULTILISTEN0(x) ((x) << S_MULTILISTEN0)
+#define F_MULTILISTEN0    V_MULTILISTEN0(1U)
+
+#define S_SRAM_PRIO3    22
+#define M_SRAM_PRIO3    0x7U
+#define V_SRAM_PRIO3(x) ((x) << S_SRAM_PRIO3)
+#define G_SRAM_PRIO3(x) (((x) >> S_SRAM_PRIO3) & M_SRAM_PRIO3)
+
+#define S_SRAM_PRIO2    19
+#define M_SRAM_PRIO2    0x7U
+#define V_SRAM_PRIO2(x) ((x) << S_SRAM_PRIO2)
+#define G_SRAM_PRIO2(x) (((x) >> S_SRAM_PRIO2) & M_SRAM_PRIO2)
+
+#define S_SRAM_PRIO1    16
+#define M_SRAM_PRIO1    0x7U
+#define V_SRAM_PRIO1(x) ((x) << S_SRAM_PRIO1)
+#define G_SRAM_PRIO1(x) (((x) >> S_SRAM_PRIO1) & M_SRAM_PRIO1)
+
+#define S_SRAM_PRIO0    13
+#define M_SRAM_PRIO0    0x7U
+#define V_SRAM_PRIO0(x) ((x) << S_SRAM_PRIO0)
+#define G_SRAM_PRIO0(x) (((x) >> S_SRAM_PRIO0) & M_SRAM_PRIO0)
+
+#define S_SRAM_VLD    12
+#define V_SRAM_VLD(x) ((x) << S_SRAM_VLD)
+#define F_SRAM_VLD    V_SRAM_VLD(1U)
+
+#define A_MPS_T5_CLS_SRAM_L 0xe000
+#define A_MPS_CLS_SRAM_H 0xe004
+
+#define S_MACPARITY1    9
+#define V_MACPARITY1(x) ((x) << S_MACPARITY1)
+#define F_MACPARITY1    V_MACPARITY1(1U)
+
+#define S_MACPARITY0    8
+#define V_MACPARITY0(x) ((x) << S_MACPARITY0)
+#define F_MACPARITY0    V_MACPARITY0(1U)
+
+#define S_MACPARITYMASKSIZE    4
+#define M_MACPARITYMASKSIZE    0xfU
+#define V_MACPARITYMASKSIZE(x) ((x) << S_MACPARITYMASKSIZE)
+#define G_MACPARITYMASKSIZE(x) (((x) >> S_MACPARITYMASKSIZE) & M_MACPARITYMASKSIZE)
+
+#define S_PORTMAP    0
+#define M_PORTMAP    0xfU
+#define V_PORTMAP(x) ((x) << S_PORTMAP)
+#define G_PORTMAP(x) (((x) >> S_PORTMAP) & M_PORTMAP)
+
+#define A_MPS_T5_CLS_SRAM_H 0xe004
+#define A_MPS_CLS_TCAM_Y_L 0xf000
+#define A_MPS_CLS_TCAM_Y_H 0xf004
+
+#define S_TCAMYH    0
+#define M_TCAMYH    0xffffU
+#define V_TCAMYH(x) ((x) << S_TCAMYH)
+#define G_TCAMYH(x) (((x) >> S_TCAMYH) & M_TCAMYH)
+
+#define A_MPS_CLS_TCAM_X_L 0xf008
+#define A_MPS_CLS_TCAM_X_H 0xf00c
+
+#define S_TCAMXH    0
+#define M_TCAMXH    0xffffU
+#define V_TCAMXH(x) ((x) << S_TCAMXH)
+#define G_TCAMXH(x) (((x) >> S_TCAMXH) & M_TCAMXH)
+
+#define A_MPS_RX_CTL 0x11000
+
+#define S_FILT_VLAN_SEL    17
+#define V_FILT_VLAN_SEL(x) ((x) << S_FILT_VLAN_SEL)
+#define F_FILT_VLAN_SEL    V_FILT_VLAN_SEL(1U)
+
+#define S_CBA_EN    16
+#define V_CBA_EN(x) ((x) << S_CBA_EN)
+#define F_CBA_EN    V_CBA_EN(1U)
+
+#define S_BLK_SNDR    12
+#define M_BLK_SNDR    0xfU
+#define V_BLK_SNDR(x) ((x) << S_BLK_SNDR)
+#define G_BLK_SNDR(x) (((x) >> S_BLK_SNDR) & M_BLK_SNDR)
+
+#define S_CMPRS    8
+#define M_CMPRS    0xfU
+#define V_CMPRS(x) ((x) << S_CMPRS)
+#define G_CMPRS(x) (((x) >> S_CMPRS) & M_CMPRS)
+
+#define S_SNF    0
+#define M_SNF    0xffU
+#define V_SNF(x) ((x) << S_SNF)
+#define G_SNF(x) (((x) >> S_SNF) & M_SNF)
+
+#define A_MPS_RX_PORT_MUX_CTL 0x11004
+
+#define S_CTL_P3    12
+#define M_CTL_P3    0xfU
+#define V_CTL_P3(x) ((x) << S_CTL_P3)
+#define G_CTL_P3(x) (((x) >> S_CTL_P3) & M_CTL_P3)
+
+#define S_CTL_P2    8
+#define M_CTL_P2    0xfU
+#define V_CTL_P2(x) ((x) << S_CTL_P2)
+#define G_CTL_P2(x) (((x) >> S_CTL_P2) & M_CTL_P2)
+
+#define S_CTL_P1    4
+#define M_CTL_P1    0xfU
+#define V_CTL_P1(x) ((x) << S_CTL_P1)
+#define G_CTL_P1(x) (((x) >> S_CTL_P1) & M_CTL_P1)
+
+#define S_CTL_P0    0
+#define M_CTL_P0    0xfU
+#define V_CTL_P0(x) ((x) << S_CTL_P0)
+#define G_CTL_P0(x) (((x) >> S_CTL_P0) & M_CTL_P0)
+
+#define A_MPS_RX_PG_FL 0x11008
+
+#define S_RST    16
+#define V_RST(x) ((x) << S_RST)
+#define F_RST    V_RST(1U)
+
+#define S_CNT    0
+#define M_CNT    0xffffU
+#define V_CNT(x) ((x) << S_CNT)
+#define G_CNT(x) (((x) >> S_CNT) & M_CNT)
+
+#define A_MPS_RX_PKT_FL 0x1100c
+#define A_MPS_RX_PG_RSV0 0x11010
+
+#define S_CLR_INTR    31
+#define V_CLR_INTR(x) ((x) << S_CLR_INTR)
+#define F_CLR_INTR    V_CLR_INTR(1U)
+
+#define S_SET_INTR    30
+#define V_SET_INTR(x) ((x) << S_SET_INTR)
+#define F_SET_INTR    V_SET_INTR(1U)
+
+#define S_USED    16
+#define M_USED    0x7ffU
+#define V_USED(x) ((x) << S_USED)
+#define G_USED(x) (((x) >> S_USED) & M_USED)
+
+#define S_ALLOC    0
+#define M_ALLOC    0x7ffU
+#define V_ALLOC(x) ((x) << S_ALLOC)
+#define G_ALLOC(x) (((x) >> S_ALLOC) & M_ALLOC)
+
+#define S_T5_USED    16
+#define M_T5_USED    0xfffU
+#define V_T5_USED(x) ((x) << S_T5_USED)
+#define G_T5_USED(x) (((x) >> S_T5_USED) & M_T5_USED)
+
+#define S_T5_ALLOC    0
+#define M_T5_ALLOC    0xfffU
+#define V_T5_ALLOC(x) ((x) << S_T5_ALLOC)
+#define G_T5_ALLOC(x) (((x) >> S_T5_ALLOC) & M_T5_ALLOC)
+
+#define A_MPS_RX_PG_RSV1 0x11014
+#define A_MPS_RX_PG_RSV2 0x11018
+#define A_MPS_RX_PG_RSV3 0x1101c
+#define A_MPS_RX_PG_RSV4 0x11020
+#define A_MPS_RX_PG_RSV5 0x11024
+#define A_MPS_RX_PG_RSV6 0x11028
+#define A_MPS_RX_PG_RSV7 0x1102c
+#define A_MPS_RX_PG_SHR_BG0 0x11030
+
+#define S_EN    31
+#define V_EN(x) ((x) << S_EN)
+#define F_EN    V_EN(1U)
+
+#define S_SEL    30
+#define V_SEL(x) ((x) << S_SEL)
+#define F_SEL    V_SEL(1U)
+
+#define S_MAX    16
+#define M_MAX    0x7ffU
+#define V_MAX(x) ((x) << S_MAX)
+#define G_MAX(x) (((x) >> S_MAX) & M_MAX)
+
+#define S_BORW    0
+#define M_BORW    0x7ffU
+#define V_BORW(x) ((x) << S_BORW)
+#define G_BORW(x) (((x) >> S_BORW) & M_BORW)
+
+#define S_T5_MAX    16
+#define M_T5_MAX    0xfffU
+#define V_T5_MAX(x) ((x) << S_T5_MAX)
+#define G_T5_MAX(x) (((x) >> S_T5_MAX) & M_T5_MAX)
+
+#define S_T5_BORW    0
+#define M_T5_BORW    0xfffU
+#define V_T5_BORW(x) ((x) << S_T5_BORW)
+#define G_T5_BORW(x) (((x) >> S_T5_BORW) & M_T5_BORW)
+
+#define A_MPS_RX_PG_SHR_BG1 0x11034
+#define A_MPS_RX_PG_SHR_BG2 0x11038
+#define A_MPS_RX_PG_SHR_BG3 0x1103c
+#define A_MPS_RX_PG_SHR0 0x11040
+
+#define S_QUOTA    16
+#define M_QUOTA    0x7ffU
+#define V_QUOTA(x) ((x) << S_QUOTA)
+#define G_QUOTA(x) (((x) >> S_QUOTA) & M_QUOTA)
+
+#define S_SHR_USED    0
+#define M_SHR_USED    0x7ffU
+#define V_SHR_USED(x) ((x) << S_SHR_USED)
+#define G_SHR_USED(x) (((x) >> S_SHR_USED) & M_SHR_USED)
+
+#define S_T5_QUOTA    16
+#define M_T5_QUOTA    0xfffU
+#define V_T5_QUOTA(x) ((x) << S_T5_QUOTA)
+#define G_T5_QUOTA(x) (((x) >> S_T5_QUOTA) & M_T5_QUOTA)
+
+#define S_T5_SHR_USED    0
+#define M_T5_SHR_USED    0xfffU
+#define V_T5_SHR_USED(x) ((x) << S_T5_SHR_USED)
+#define G_T5_SHR_USED(x) (((x) >> S_T5_SHR_USED) & M_T5_SHR_USED)
+
+#define A_MPS_RX_PG_SHR1 0x11044
+#define A_MPS_RX_PG_HYST_BG0 0x11048
+
+#define S_TH    0
+#define M_TH    0x7ffU
+#define V_TH(x) ((x) << S_TH)
+#define G_TH(x) (((x) >> S_TH) & M_TH)
+
+#define S_T5_TH    0
+#define M_T5_TH    0xfffU
+#define V_T5_TH(x) ((x) << S_T5_TH)
+#define G_T5_TH(x) (((x) >> S_T5_TH) & M_T5_TH)
+
+#define A_MPS_RX_PG_HYST_BG1 0x1104c
+#define A_MPS_RX_PG_HYST_BG2 0x11050
+#define A_MPS_RX_PG_HYST_BG3 0x11054
+#define A_MPS_RX_OCH_CTL 0x11058
+
+#define S_DROP_WT    27
+#define M_DROP_WT    0x1fU
+#define V_DROP_WT(x) ((x) << S_DROP_WT)
+#define G_DROP_WT(x) (((x) >> S_DROP_WT) & M_DROP_WT)
+
+#define S_TRUNC_WT    22
+#define M_TRUNC_WT    0x1fU
+#define V_TRUNC_WT(x) ((x) << S_TRUNC_WT)
+#define G_TRUNC_WT(x) (((x) >> S_TRUNC_WT) & M_TRUNC_WT)
+
+#define S_OCH_DRAIN    13
+#define M_OCH_DRAIN    0x1fU
+#define V_OCH_DRAIN(x) ((x) << S_OCH_DRAIN)
+#define G_OCH_DRAIN(x) (((x) >> S_OCH_DRAIN) & M_OCH_DRAIN)
+
+#define S_OCH_DROP    8
+#define M_OCH_DROP    0x1fU
+#define V_OCH_DROP(x) ((x) << S_OCH_DROP)
+#define G_OCH_DROP(x) (((x) >> S_OCH_DROP) & M_OCH_DROP)
+
+#define S_STOP    0
+#define M_STOP    0x1fU
+#define V_STOP(x) ((x) << S_STOP)
+#define G_STOP(x) (((x) >> S_STOP) & M_STOP)
+
+#define A_MPS_RX_LPBK_BP0 0x1105c
+
+#define S_THRESH    0
+#define M_THRESH    0x7ffU
+#define V_THRESH(x) ((x) << S_THRESH)
+#define G_THRESH(x) (((x) >> S_THRESH) & M_THRESH)
+
+#define A_MPS_RX_LPBK_BP1 0x11060
+#define A_MPS_RX_LPBK_BP2 0x11064
+#define A_MPS_RX_LPBK_BP3 0x11068
+#define A_MPS_RX_PORT_GAP 0x1106c
+
+#define S_GAP    0
+#define M_GAP    0xfffffU
+#define V_GAP(x) ((x) << S_GAP)
+#define G_GAP(x) (((x) >> S_GAP) & M_GAP)
+
+#define A_MPS_RX_CHMN_CNT 0x11070
+#define A_MPS_RX_PERR_INT_CAUSE 0x11074
+
+#define S_FF    23
+#define V_FF(x) ((x) << S_FF)
+#define F_FF    V_FF(1U)
+
+#define S_PGMO    22
+#define V_PGMO(x) ((x) << S_PGMO)
+#define F_PGMO    V_PGMO(1U)
+
+#define S_PGME    21
+#define V_PGME(x) ((x) << S_PGME)
+#define F_PGME    V_PGME(1U)
+
+#define S_CHMN    20
+#define V_CHMN(x) ((x) << S_CHMN)
+#define F_CHMN    V_CHMN(1U)
+
+#define S_RPLC    19
+#define V_RPLC(x) ((x) << S_RPLC)
+#define F_RPLC    V_RPLC(1U)
+
+#define S_ATRB    18
+#define V_ATRB(x) ((x) << S_ATRB)
+#define F_ATRB    V_ATRB(1U)
+
+#define S_PSMX    17
+#define V_PSMX(x) ((x) << S_PSMX)
+#define F_PSMX    V_PSMX(1U)
+
+#define S_PGLL    16
+#define V_PGLL(x) ((x) << S_PGLL)
+#define F_PGLL    V_PGLL(1U)
+
+#define S_PGFL    15
+#define V_PGFL(x) ((x) << S_PGFL)
+#define F_PGFL    V_PGFL(1U)
+
+#define S_PKTQ    14
+#define V_PKTQ(x) ((x) << S_PKTQ)
+#define F_PKTQ    V_PKTQ(1U)
+
+#define S_PKFL    13
+#define V_PKFL(x) ((x) << S_PKFL)
+#define F_PKFL    V_PKFL(1U)
+
+#define S_PPM3    12
+#define V_PPM3(x) ((x) << S_PPM3)
+#define F_PPM3    V_PPM3(1U)
+
+#define S_PPM2    11
+#define V_PPM2(x) ((x) << S_PPM2)
+#define F_PPM2    V_PPM2(1U)
+
+#define S_PPM1    10
+#define V_PPM1(x) ((x) << S_PPM1)
+#define F_PPM1    V_PPM1(1U)
+
+#define S_PPM0    9
+#define V_PPM0(x) ((x) << S_PPM0)
+#define F_PPM0    V_PPM0(1U)
+
+#define S_SPMX    8
+#define V_SPMX(x) ((x) << S_SPMX)
+#define F_SPMX    V_SPMX(1U)
+
+#define S_CDL3    7
+#define V_CDL3(x) ((x) << S_CDL3)
+#define F_CDL3    V_CDL3(1U)
+
+#define S_CDL2    6
+#define V_CDL2(x) ((x) << S_CDL2)
+#define F_CDL2    V_CDL2(1U)
+
+#define S_CDL1    5
+#define V_CDL1(x) ((x) << S_CDL1)
+#define F_CDL1    V_CDL1(1U)
+
+#define S_CDL0    4
+#define V_CDL0(x) ((x) << S_CDL0)
+#define F_CDL0    V_CDL0(1U)
+
+#define S_CDM3    3
+#define V_CDM3(x) ((x) << S_CDM3)
+#define F_CDM3    V_CDM3(1U)
+
+#define S_CDM2    2
+#define V_CDM2(x) ((x) << S_CDM2)
+#define F_CDM2    V_CDM2(1U)
+
+#define S_CDM1    1
+#define V_CDM1(x) ((x) << S_CDM1)
+#define F_CDM1    V_CDM1(1U)
+
+#define S_CDM0    0
+#define V_CDM0(x) ((x) << S_CDM0)
+#define F_CDM0    V_CDM0(1U)
+
+#define A_MPS_RX_PERR_INT_ENABLE 0x11078
+#define A_MPS_RX_PERR_ENABLE 0x1107c
+#define A_MPS_RX_PERR_INJECT 0x11080
+#define A_MPS_RX_FUNC_INT_CAUSE 0x11084
+
+#define S_INT_ERR_INT    8
+#define M_INT_ERR_INT    0x1fU
+#define V_INT_ERR_INT(x) ((x) << S_INT_ERR_INT)
+#define G_INT_ERR_INT(x) (((x) >> S_INT_ERR_INT) & M_INT_ERR_INT)
+
+#define S_PG_TH_INT7    7
+#define V_PG_TH_INT7(x) ((x) << S_PG_TH_INT7)
+#define F_PG_TH_INT7    V_PG_TH_INT7(1U)
+
+#define S_PG_TH_INT6    6
+#define V_PG_TH_INT6(x) ((x) << S_PG_TH_INT6)
+#define F_PG_TH_INT6    V_PG_TH_INT6(1U)
+
+#define S_PG_TH_INT5    5
+#define V_PG_TH_INT5(x) ((x) << S_PG_TH_INT5)
+#define F_PG_TH_INT5    V_PG_TH_INT5(1U)
+
+#define S_PG_TH_INT4    4
+#define V_PG_TH_INT4(x) ((x) << S_PG_TH_INT4)
+#define F_PG_TH_INT4    V_PG_TH_INT4(1U)
+
+#define S_PG_TH_INT3    3
+#define V_PG_TH_INT3(x) ((x) << S_PG_TH_INT3)
+#define F_PG_TH_INT3    V_PG_TH_INT3(1U)
+
+#define S_PG_TH_INT2    2
+#define V_PG_TH_INT2(x) ((x) << S_PG_TH_INT2)
+#define F_PG_TH_INT2    V_PG_TH_INT2(1U)
+
+#define S_PG_TH_INT1    1
+#define V_PG_TH_INT1(x) ((x) << S_PG_TH_INT1)
+#define F_PG_TH_INT1    V_PG_TH_INT1(1U)
+
+#define S_PG_TH_INT0    0
+#define V_PG_TH_INT0(x) ((x) << S_PG_TH_INT0)
+#define F_PG_TH_INT0    V_PG_TH_INT0(1U)
+
+#define S_MTU_ERR_INT3    19
+#define V_MTU_ERR_INT3(x) ((x) << S_MTU_ERR_INT3)
+#define F_MTU_ERR_INT3    V_MTU_ERR_INT3(1U)
+
+#define S_MTU_ERR_INT2    18
+#define V_MTU_ERR_INT2(x) ((x) << S_MTU_ERR_INT2)
+#define F_MTU_ERR_INT2    V_MTU_ERR_INT2(1U)
+
+#define S_MTU_ERR_INT1    17
+#define V_MTU_ERR_INT1(x) ((x) << S_MTU_ERR_INT1)
+#define F_MTU_ERR_INT1    V_MTU_ERR_INT1(1U)
+
+#define S_MTU_ERR_INT0    16
+#define V_MTU_ERR_INT0(x) ((x) << S_MTU_ERR_INT0)
+#define F_MTU_ERR_INT0    V_MTU_ERR_INT0(1U)
+
+#define S_SE_CNT_ERR_INT    15
+#define V_SE_CNT_ERR_INT(x) ((x) << S_SE_CNT_ERR_INT)
+#define F_SE_CNT_ERR_INT    V_SE_CNT_ERR_INT(1U)
+
+#define S_FRM_ERR_INT    14
+#define V_FRM_ERR_INT(x) ((x) << S_FRM_ERR_INT)
+#define F_FRM_ERR_INT    V_FRM_ERR_INT(1U)
+
+#define S_LEN_ERR_INT    13
+#define V_LEN_ERR_INT(x) ((x) << S_LEN_ERR_INT)
+#define F_LEN_ERR_INT    V_LEN_ERR_INT(1U)
+
+#define A_MPS_RX_FUNC_INT_ENABLE 0x11088
+#define A_MPS_RX_PAUSE_GEN_TH_0 0x1108c
+
+#define S_TH_HIGH    16
+#define M_TH_HIGH    0xffffU
+#define V_TH_HIGH(x) ((x) << S_TH_HIGH)
+#define G_TH_HIGH(x) (((x) >> S_TH_HIGH) & M_TH_HIGH)
+
+#define S_TH_LOW    0
+#define M_TH_LOW    0xffffU
+#define V_TH_LOW(x) ((x) << S_TH_LOW)
+#define G_TH_LOW(x) (((x) >> S_TH_LOW) & M_TH_LOW)
+
+#define A_MPS_RX_PAUSE_GEN_TH_1 0x11090
+#define A_MPS_RX_PAUSE_GEN_TH_2 0x11094
+#define A_MPS_RX_PAUSE_GEN_TH_3 0x11098
+#define A_MPS_RX_PPP_ATRB 0x1109c
+
+#define S_ETYPE    16
+#define M_ETYPE    0xffffU
+#define V_ETYPE(x) ((x) << S_ETYPE)
+#define G_ETYPE(x) (((x) >> S_ETYPE) & M_ETYPE)
+
+#define S_OPCODE    0
+#define M_OPCODE    0xffffU
+#define V_OPCODE(x) ((x) << S_OPCODE)
+#define G_OPCODE(x) (((x) >> S_OPCODE) & M_OPCODE)
+
+#define A_MPS_RX_QFC0_ATRB 0x110a0
+
+#define S_DA    0
+#define M_DA    0xffffU
+#define V_DA(x) ((x) << S_DA)
+#define G_DA(x) (((x) >> S_DA) & M_DA)
+
+#define A_MPS_RX_QFC1_ATRB 0x110a4
+#define A_MPS_RX_PT_ARB0 0x110a8
+
+#define S_LPBK_WT    16
+#define M_LPBK_WT    0x3fffU
+#define V_LPBK_WT(x) ((x) << S_LPBK_WT)
+#define G_LPBK_WT(x) (((x) >> S_LPBK_WT) & M_LPBK_WT)
+
+#define S_MAC_WT    0
+#define M_MAC_WT    0x3fffU
+#define V_MAC_WT(x) ((x) << S_MAC_WT)
+#define G_MAC_WT(x) (((x) >> S_MAC_WT) & M_MAC_WT)
+
+#define A_MPS_RX_PT_ARB1 0x110ac
+#define A_MPS_RX_PT_ARB2 0x110b0
+#define A_MPS_RX_PT_ARB3 0x110b4
+#define A_MPS_RX_PT_ARB4 0x110b8
+#define A_MPS_PF_OUT_EN 0x110bc
+
+#define S_OUTEN    0
+#define M_OUTEN    0xffU
+#define V_OUTEN(x) ((x) << S_OUTEN)
+#define G_OUTEN(x) (((x) >> S_OUTEN) & M_OUTEN)
+
+#define A_MPS_BMC_MTU 0x110c0
+
+#define S_MTU    0
+#define M_MTU    0x3fffU
+#define V_MTU(x) ((x) << S_MTU)
+#define G_MTU(x) (((x) >> S_MTU) & M_MTU)
+
+#define A_MPS_BMC_PKT_CNT 0x110c4
+#define A_MPS_BMC_BYTE_CNT 0x110c8
+#define A_MPS_PFVF_ATRB_CTL 0x110cc
+
+#define S_RD_WRN    31
+#define V_RD_WRN(x) ((x) << S_RD_WRN)
+#define F_RD_WRN    V_RD_WRN(1U)
+
+#define S_PFVF    0
+#define M_PFVF    0xffU
+#define V_PFVF(x) ((x) << S_PFVF)
+#define G_PFVF(x) (((x) >> S_PFVF) & M_PFVF)
+
+#define A_MPS_PFVF_ATRB 0x110d0
+
+#define S_ATTR_PF    28
+#define M_ATTR_PF    0x7U
+#define V_ATTR_PF(x) ((x) << S_ATTR_PF)
+#define G_ATTR_PF(x) (((x) >> S_ATTR_PF) & M_ATTR_PF)
+
+#define S_OFF    18
+#define V_OFF(x) ((x) << S_OFF)
+#define F_OFF    V_OFF(1U)
+
+#define S_NV_DROP    17
+#define V_NV_DROP(x) ((x) << S_NV_DROP)
+#define F_NV_DROP    V_NV_DROP(1U)
+
+#define S_ATTR_MODE    16
+#define V_ATTR_MODE(x) ((x) << S_ATTR_MODE)
+#define F_ATTR_MODE    V_ATTR_MODE(1U)
+
+#define A_MPS_PFVF_ATRB_FLTR0 0x110d4
+
+#define S_VLAN_EN    16
+#define V_VLAN_EN(x) ((x) << S_VLAN_EN)
+#define F_VLAN_EN    V_VLAN_EN(1U)
+
+#define S_VLAN_ID    0
+#define M_VLAN_ID    0xfffU
+#define V_VLAN_ID(x) ((x) << S_VLAN_ID)
+#define G_VLAN_ID(x) (((x) >> S_VLAN_ID) & M_VLAN_ID)
+
+#define A_MPS_PFVF_ATRB_FLTR1 0x110d8
+#define A_MPS_PFVF_ATRB_FLTR2 0x110dc
+#define A_MPS_PFVF_ATRB_FLTR3 0x110e0
+#define A_MPS_PFVF_ATRB_FLTR4 0x110e4
+#define A_MPS_PFVF_ATRB_FLTR5 0x110e8
+#define A_MPS_PFVF_ATRB_FLTR6 0x110ec
+#define A_MPS_PFVF_ATRB_FLTR7 0x110f0
+#define A_MPS_PFVF_ATRB_FLTR8 0x110f4
+#define A_MPS_PFVF_ATRB_FLTR9 0x110f8
+#define A_MPS_PFVF_ATRB_FLTR10 0x110fc
+#define A_MPS_PFVF_ATRB_FLTR11 0x11100
+#define A_MPS_PFVF_ATRB_FLTR12 0x11104
+#define A_MPS_PFVF_ATRB_FLTR13 0x11108
+#define A_MPS_PFVF_ATRB_FLTR14 0x1110c
+#define A_MPS_PFVF_ATRB_FLTR15 0x11110
+#define A_MPS_RPLC_MAP_CTL 0x11114
+
+#define S_RPLC_MAP_ADDR    0
+#define M_RPLC_MAP_ADDR    0x3ffU
+#define V_RPLC_MAP_ADDR(x) ((x) << S_RPLC_MAP_ADDR)
+#define G_RPLC_MAP_ADDR(x) (((x) >> S_RPLC_MAP_ADDR) & M_RPLC_MAP_ADDR)
+
+#define A_MPS_PF_RPLCT_MAP 0x11118
+
+#define S_PF_EN    0
+#define M_PF_EN    0xffU
+#define V_PF_EN(x) ((x) << S_PF_EN)
+#define G_PF_EN(x) (((x) >> S_PF_EN) & M_PF_EN)
+
+#define A_MPS_VF_RPLCT_MAP0 0x1111c
+#define A_MPS_VF_RPLCT_MAP1 0x11120
+#define A_MPS_VF_RPLCT_MAP2 0x11124
+#define A_MPS_VF_RPLCT_MAP3 0x11128
+#define A_MPS_MEM_DBG_CTL 0x1112c
+
+#define S_PKD    17
+#define V_PKD(x) ((x) << S_PKD)
+#define F_PKD    V_PKD(1U)
+
+#define S_PGD    16
+#define V_PGD(x) ((x) << S_PGD)
+#define F_PGD    V_PGD(1U)
+
+#define A_MPS_PKD_MEM_DATA0 0x11130
+#define A_MPS_PKD_MEM_DATA1 0x11134
+#define A_MPS_PKD_MEM_DATA2 0x11138
+#define A_MPS_PGD_MEM_DATA 0x1113c
+#define A_MPS_RX_SE_CNT_ERR 0x11140
+
+#define S_RX_SE_ERRMAP    0
+#define M_RX_SE_ERRMAP    0xfffffU
+#define V_RX_SE_ERRMAP(x) ((x) << S_RX_SE_ERRMAP)
+#define G_RX_SE_ERRMAP(x) (((x) >> S_RX_SE_ERRMAP) & M_RX_SE_ERRMAP)
+
+#define A_MPS_RX_SE_CNT_CLR 0x11144
+#define A_MPS_RX_SE_CNT_IN0 0x11148
+
+#define S_SOP_CNT_PM    24
+#define M_SOP_CNT_PM    0xffU
+#define V_SOP_CNT_PM(x) ((x) << S_SOP_CNT_PM)
+#define G_SOP_CNT_PM(x) (((x) >> S_SOP_CNT_PM) & M_SOP_CNT_PM)
+
+#define S_EOP_CNT_PM    16
+#define M_EOP_CNT_PM    0xffU
+#define V_EOP_CNT_PM(x) ((x) << S_EOP_CNT_PM)
+#define G_EOP_CNT_PM(x) (((x) >> S_EOP_CNT_PM) & M_EOP_CNT_PM)
+
+#define S_SOP_CNT_IN    8
+#define M_SOP_CNT_IN    0xffU
+#define V_SOP_CNT_IN(x) ((x) << S_SOP_CNT_IN)
+#define G_SOP_CNT_IN(x) (((x) >> S_SOP_CNT_IN) & M_SOP_CNT_IN)
+
+#define S_EOP_CNT_IN    0
+#define M_EOP_CNT_IN    0xffU
+#define V_EOP_CNT_IN(x) ((x) << S_EOP_CNT_IN)
+#define G_EOP_CNT_IN(x) (((x) >> S_EOP_CNT_IN) & M_EOP_CNT_IN)
+
+#define A_MPS_RX_SE_CNT_IN1 0x1114c
+#define A_MPS_RX_SE_CNT_IN2 0x11150
+#define A_MPS_RX_SE_CNT_IN3 0x11154
+#define A_MPS_RX_SE_CNT_IN4 0x11158
+#define A_MPS_RX_SE_CNT_IN5 0x1115c
+#define A_MPS_RX_SE_CNT_IN6 0x11160
+#define A_MPS_RX_SE_CNT_IN7 0x11164
+#define A_MPS_RX_SE_CNT_OUT01 0x11168
+
+#define S_SOP_CNT_1    24
+#define M_SOP_CNT_1    0xffU
+#define V_SOP_CNT_1(x) ((x) << S_SOP_CNT_1)
+#define G_SOP_CNT_1(x) (((x) >> S_SOP_CNT_1) & M_SOP_CNT_1)
+
+#define S_EOP_CNT_1    16
+#define M_EOP_CNT_1    0xffU
+#define V_EOP_CNT_1(x) ((x) << S_EOP_CNT_1)
+#define G_EOP_CNT_1(x) (((x) >> S_EOP_CNT_1) & M_EOP_CNT_1)
+
+#define S_SOP_CNT_0    8
+#define M_SOP_CNT_0    0xffU
+#define V_SOP_CNT_0(x) ((x) << S_SOP_CNT_0)
+#define G_SOP_CNT_0(x) (((x) >> S_SOP_CNT_0) & M_SOP_CNT_0)
+
+#define S_EOP_CNT_0    0
+#define M_EOP_CNT_0    0xffU
+#define V_EOP_CNT_0(x) ((x) << S_EOP_CNT_0)
+#define G_EOP_CNT_0(x) (((x) >> S_EOP_CNT_0) & M_EOP_CNT_0)
+
+#define A_MPS_RX_SE_CNT_OUT23 0x1116c
+
+#define S_SOP_CNT_3    24
+#define M_SOP_CNT_3    0xffU
+#define V_SOP_CNT_3(x) ((x) << S_SOP_CNT_3)
+#define G_SOP_CNT_3(x) (((x) >> S_SOP_CNT_3) & M_SOP_CNT_3)
+
+#define S_EOP_CNT_3    16
+#define M_EOP_CNT_3    0xffU
+#define V_EOP_CNT_3(x) ((x) << S_EOP_CNT_3)
+#define G_EOP_CNT_3(x) (((x) >> S_EOP_CNT_3) & M_EOP_CNT_3)
+
+#define S_SOP_CNT_2    8
+#define M_SOP_CNT_2    0xffU
+#define V_SOP_CNT_2(x) ((x) << S_SOP_CNT_2)
+#define G_SOP_CNT_2(x) (((x) >> S_SOP_CNT_2) & M_SOP_CNT_2)
+
+#define S_EOP_CNT_2    0
+#define M_EOP_CNT_2    0xffU
+#define V_EOP_CNT_2(x) ((x) << S_EOP_CNT_2)
+#define G_EOP_CNT_2(x) (((x) >> S_EOP_CNT_2) & M_EOP_CNT_2)
+
+#define A_MPS_RX_SPI_ERR 0x11170
+
+#define S_LENERR    21
+#define M_LENERR    0xfU
+#define V_LENERR(x) ((x) << S_LENERR)
+#define G_LENERR(x) (((x) >> S_LENERR) & M_LENERR)
+
+#define S_SPIERR    0
+#define M_SPIERR    0x1fffffU
+#define V_SPIERR(x) ((x) << S_SPIERR)
+#define G_SPIERR(x) (((x) >> S_SPIERR) & M_SPIERR)
+
+#define A_MPS_RX_IN_BUS_STATE 0x11174
+
+#define S_ST3    24
+#define M_ST3    0xffU
+#define V_ST3(x) ((x) << S_ST3)
+#define G_ST3(x) (((x) >> S_ST3) & M_ST3)
+
+#define S_ST2    16
+#define M_ST2    0xffU
+#define V_ST2(x) ((x) << S_ST2)
+#define G_ST2(x) (((x) >> S_ST2) & M_ST2)
+
+#define S_ST1    8
+#define M_ST1    0xffU
+#define V_ST1(x) ((x) << S_ST1)
+#define G_ST1(x) (((x) >> S_ST1) & M_ST1)
+
+#define S_ST0    0
+#define M_ST0    0xffU
+#define V_ST0(x) ((x) << S_ST0)
+#define G_ST0(x) (((x) >> S_ST0) & M_ST0)
+
+#define A_MPS_RX_OUT_BUS_STATE 0x11178
+
+#define S_ST_NCSI    23
+#define M_ST_NCSI    0x1ffU
+#define V_ST_NCSI(x) ((x) << S_ST_NCSI)
+#define G_ST_NCSI(x) (((x) >> S_ST_NCSI) & M_ST_NCSI)
+
+#define S_ST_TP    0
+#define M_ST_TP    0x7fffffU
+#define V_ST_TP(x) ((x) << S_ST_TP)
+#define G_ST_TP(x) (((x) >> S_ST_TP) & M_ST_TP)
+
+#define A_MPS_RX_DBG_CTL 0x1117c
+
+#define S_OUT_DBG_CHNL    8
+#define M_OUT_DBG_CHNL    0x7U
+#define V_OUT_DBG_CHNL(x) ((x) << S_OUT_DBG_CHNL)
+#define G_OUT_DBG_CHNL(x) (((x) >> S_OUT_DBG_CHNL) & M_OUT_DBG_CHNL)
+
+#define S_DBG_PKD_QSEL    7
+#define V_DBG_PKD_QSEL(x) ((x) << S_DBG_PKD_QSEL)
+#define F_DBG_PKD_QSEL    V_DBG_PKD_QSEL(1U)
+
+#define S_DBG_CDS_INV    6
+#define V_DBG_CDS_INV(x) ((x) << S_DBG_CDS_INV)
+#define F_DBG_CDS_INV    V_DBG_CDS_INV(1U)
+
+#define S_IN_DBG_PORT    3
+#define M_IN_DBG_PORT    0x7U
+#define V_IN_DBG_PORT(x) ((x) << S_IN_DBG_PORT)
+#define G_IN_DBG_PORT(x) (((x) >> S_IN_DBG_PORT) & M_IN_DBG_PORT)
+
+#define S_IN_DBG_CHNL    0
+#define M_IN_DBG_CHNL    0x7U
+#define V_IN_DBG_CHNL(x) ((x) << S_IN_DBG_CHNL)
+#define G_IN_DBG_CHNL(x) (((x) >> S_IN_DBG_CHNL) & M_IN_DBG_CHNL)
+
+#define A_MPS_RX_CLS_DROP_CNT0 0x11180
+
+#define S_LPBK_CNT0    16
+#define M_LPBK_CNT0    0xffffU
+#define V_LPBK_CNT0(x) ((x) << S_LPBK_CNT0)
+#define G_LPBK_CNT0(x) (((x) >> S_LPBK_CNT0) & M_LPBK_CNT0)
+
+#define S_MAC_CNT0    0
+#define M_MAC_CNT0    0xffffU
+#define V_MAC_CNT0(x) ((x) << S_MAC_CNT0)
+#define G_MAC_CNT0(x) (((x) >> S_MAC_CNT0) & M_MAC_CNT0)
+
+#define A_MPS_RX_CLS_DROP_CNT1 0x11184
+
+#define S_LPBK_CNT1    16
+#define M_LPBK_CNT1    0xffffU
+#define V_LPBK_CNT1(x) ((x) << S_LPBK_CNT1)
+#define G_LPBK_CNT1(x) (((x) >> S_LPBK_CNT1) & M_LPBK_CNT1)
+
+#define S_MAC_CNT1    0
+#define M_MAC_CNT1    0xffffU
+#define V_MAC_CNT1(x) ((x) << S_MAC_CNT1)
+#define G_MAC_CNT1(x) (((x) >> S_MAC_CNT1) & M_MAC_CNT1)
+
+#define A_MPS_RX_CLS_DROP_CNT2 0x11188
+
+#define S_LPBK_CNT2    16
+#define M_LPBK_CNT2    0xffffU
+#define V_LPBK_CNT2(x) ((x) << S_LPBK_CNT2)
+#define G_LPBK_CNT2(x) (((x) >> S_LPBK_CNT2) & M_LPBK_CNT2)
+
+#define S_MAC_CNT2    0
+#define M_MAC_CNT2    0xffffU
+#define V_MAC_CNT2(x) ((x) << S_MAC_CNT2)
+#define G_MAC_CNT2(x) (((x) >> S_MAC_CNT2) & M_MAC_CNT2)
+
+#define A_MPS_RX_CLS_DROP_CNT3 0x1118c
+
+#define S_LPBK_CNT3    16
+#define M_LPBK_CNT3    0xffffU
+#define V_LPBK_CNT3(x) ((x) << S_LPBK_CNT3)
+#define G_LPBK_CNT3(x) (((x) >> S_LPBK_CNT3) & M_LPBK_CNT3)
+
+#define S_MAC_CNT3    0
+#define M_MAC_CNT3    0xffffU
+#define V_MAC_CNT3(x) ((x) << S_MAC_CNT3)
+#define G_MAC_CNT3(x) (((x) >> S_MAC_CNT3) & M_MAC_CNT3)
+
+#define A_MPS_RX_SPARE 0x11190
+#define A_MPS_RX_PTP_ETYPE 0x11194
+
+#define S_PETYPE2    16
+#define M_PETYPE2    0xffffU
+#define V_PETYPE2(x) ((x) << S_PETYPE2)
+#define G_PETYPE2(x) (((x) >> S_PETYPE2) & M_PETYPE2)
+
+#define S_PETYPE1    0
+#define M_PETYPE1    0xffffU
+#define V_PETYPE1(x) ((x) << S_PETYPE1)
+#define G_PETYPE1(x) (((x) >> S_PETYPE1) & M_PETYPE1)
+
+#define A_MPS_RX_PTP_TCP 0x11198
+
+#define S_PTCPORT2    16
+#define M_PTCPORT2    0xffffU
+#define V_PTCPORT2(x) ((x) << S_PTCPORT2)
+#define G_PTCPORT2(x) (((x) >> S_PTCPORT2) & M_PTCPORT2)
+
+#define S_PTCPORT1    0
+#define M_PTCPORT1    0xffffU
+#define V_PTCPORT1(x) ((x) << S_PTCPORT1)
+#define G_PTCPORT1(x) (((x) >> S_PTCPORT1) & M_PTCPORT1)
+
+#define A_MPS_RX_PTP_UDP 0x1119c
+
+#define S_PUDPORT2    16
+#define M_PUDPORT2    0xffffU
+#define V_PUDPORT2(x) ((x) << S_PUDPORT2)
+#define G_PUDPORT2(x) (((x) >> S_PUDPORT2) & M_PUDPORT2)
+
+#define S_PUDPORT1    0
+#define M_PUDPORT1    0xffffU
+#define V_PUDPORT1(x) ((x) << S_PUDPORT1)
+#define G_PUDPORT1(x) (((x) >> S_PUDPORT1) & M_PUDPORT1)
+
+#define A_MPS_RX_PTP_CTL 0x111a0
+
+#define S_MIN_PTP_SPACE    24
+#define M_MIN_PTP_SPACE    0x7fU
+#define V_MIN_PTP_SPACE(x) ((x) << S_MIN_PTP_SPACE)
+#define G_MIN_PTP_SPACE(x) (((x) >> S_MIN_PTP_SPACE) & M_MIN_PTP_SPACE)
+
+#define S_PUDP2EN    20
+#define M_PUDP2EN    0xfU
+#define V_PUDP2EN(x) ((x) << S_PUDP2EN)
+#define G_PUDP2EN(x) (((x) >> S_PUDP2EN) & M_PUDP2EN)
+
+#define S_PUDP1EN    16
+#define M_PUDP1EN    0xfU
+#define V_PUDP1EN(x) ((x) << S_PUDP1EN)
+#define G_PUDP1EN(x) (((x) >> S_PUDP1EN) & M_PUDP1EN)
+
+#define S_PTCP2EN    12
+#define M_PTCP2EN    0xfU
+#define V_PTCP2EN(x) ((x) << S_PTCP2EN)
+#define G_PTCP2EN(x) (((x) >> S_PTCP2EN) & M_PTCP2EN)
+
+#define S_PTCP1EN    8
+#define M_PTCP1EN    0xfU
+#define V_PTCP1EN(x) ((x) << S_PTCP1EN)
+#define G_PTCP1EN(x) (((x) >> S_PTCP1EN) & M_PTCP1EN)
+
+#define S_PETYPE2EN    4
+#define M_PETYPE2EN    0xfU
+#define V_PETYPE2EN(x) ((x) << S_PETYPE2EN)
+#define G_PETYPE2EN(x) (((x) >> S_PETYPE2EN) & M_PETYPE2EN)
+
+#define S_PETYPE1EN    0
+#define M_PETYPE1EN    0xfU
+#define V_PETYPE1EN(x) ((x) << S_PETYPE1EN)
+#define G_PETYPE1EN(x) (((x) >> S_PETYPE1EN) & M_PETYPE1EN)
+
+#define A_MPS_RX_PAUSE_GEN_TH_0_0 0x111a4
+#define A_MPS_RX_PAUSE_GEN_TH_0_1 0x111a8
+#define A_MPS_RX_PAUSE_GEN_TH_0_2 0x111ac
+#define A_MPS_RX_PAUSE_GEN_TH_0_3 0x111b0
+#define A_MPS_RX_PAUSE_GEN_TH_1_0 0x111b4
+#define A_MPS_RX_PAUSE_GEN_TH_1_1 0x111b8
+#define A_MPS_RX_PAUSE_GEN_TH_1_2 0x111bc
+#define A_MPS_RX_PAUSE_GEN_TH_1_3 0x111c0
+#define A_MPS_RX_PAUSE_GEN_TH_2_0 0x111c4
+#define A_MPS_RX_PAUSE_GEN_TH_2_1 0x111c8
+#define A_MPS_RX_PAUSE_GEN_TH_2_2 0x111cc
+#define A_MPS_RX_PAUSE_GEN_TH_2_3 0x111d0
+#define A_MPS_RX_PAUSE_GEN_TH_3_0 0x111d4
+#define A_MPS_RX_PAUSE_GEN_TH_3_1 0x111d8
+#define A_MPS_RX_PAUSE_GEN_TH_3_2 0x111dc
+#define A_MPS_RX_PAUSE_GEN_TH_3_3 0x111e0
+#define A_MPS_RX_MAC_CLS_DROP_CNT0 0x111e4
+#define A_MPS_RX_MAC_CLS_DROP_CNT1 0x111e8
+#define A_MPS_RX_MAC_CLS_DROP_CNT2 0x111ec
+#define A_MPS_RX_MAC_CLS_DROP_CNT3 0x111f0
+#define A_MPS_RX_LPBK_CLS_DROP_CNT0 0x111f4
+#define A_MPS_RX_LPBK_CLS_DROP_CNT1 0x111f8
+#define A_MPS_RX_LPBK_CLS_DROP_CNT2 0x111fc
+#define A_MPS_RX_LPBK_CLS_DROP_CNT3 0x11200
+#define A_MPS_RX_CGEN 0x11204
+
+#define S_MPS_RX_CGEN_NCSI    12
+#define V_MPS_RX_CGEN_NCSI(x) ((x) << S_MPS_RX_CGEN_NCSI)
+#define F_MPS_RX_CGEN_NCSI    V_MPS_RX_CGEN_NCSI(1U)
+
+#define S_MPS_RX_CGEN_OUT    8
+#define M_MPS_RX_CGEN_OUT    0xfU
+#define V_MPS_RX_CGEN_OUT(x) ((x) << S_MPS_RX_CGEN_OUT)
+#define G_MPS_RX_CGEN_OUT(x) (((x) >> S_MPS_RX_CGEN_OUT) & M_MPS_RX_CGEN_OUT)
+
+#define S_MPS_RX_CGEN_LPBK_IN    4
+#define M_MPS_RX_CGEN_LPBK_IN    0xfU
+#define V_MPS_RX_CGEN_LPBK_IN(x) ((x) << S_MPS_RX_CGEN_LPBK_IN)
+#define G_MPS_RX_CGEN_LPBK_IN(x) (((x) >> S_MPS_RX_CGEN_LPBK_IN) & M_MPS_RX_CGEN_LPBK_IN)
+
+#define S_MPS_RX_CGEN_MAC_IN    0
+#define M_MPS_RX_CGEN_MAC_IN    0xfU
+#define V_MPS_RX_CGEN_MAC_IN(x) ((x) << S_MPS_RX_CGEN_MAC_IN)
+#define G_MPS_RX_CGEN_MAC_IN(x) (((x) >> S_MPS_RX_CGEN_MAC_IN) & M_MPS_RX_CGEN_MAC_IN)
+
+/* registers for module CPL_SWITCH */
+#define CPL_SWITCH_BASE_ADDR 0x19040
+
+#define A_CPL_SWITCH_CNTRL 0x19040
+
+#define S_CPL_PKT_TID    8
+#define M_CPL_PKT_TID    0xffffffU
+#define V_CPL_PKT_TID(x) ((x) << S_CPL_PKT_TID)
+#define G_CPL_PKT_TID(x) (((x) >> S_CPL_PKT_TID) & M_CPL_PKT_TID)
+
+#define S_CIM_TRUNCATE_ENABLE    5
+#define V_CIM_TRUNCATE_ENABLE(x) ((x) << S_CIM_TRUNCATE_ENABLE)
+#define F_CIM_TRUNCATE_ENABLE    V_CIM_TRUNCATE_ENABLE(1U)
+
+#define S_CIM_TO_UP_FULL_SIZE    4
+#define V_CIM_TO_UP_FULL_SIZE(x) ((x) << S_CIM_TO_UP_FULL_SIZE)
+#define F_CIM_TO_UP_FULL_SIZE    V_CIM_TO_UP_FULL_SIZE(1U)
+
+#define S_CPU_NO_ENABLE    3
+#define V_CPU_NO_ENABLE(x) ((x) << S_CPU_NO_ENABLE)
+#define F_CPU_NO_ENABLE    V_CPU_NO_ENABLE(1U)
+
+#define S_SWITCH_TABLE_ENABLE    2
+#define V_SWITCH_TABLE_ENABLE(x) ((x) << S_SWITCH_TABLE_ENABLE)
+#define F_SWITCH_TABLE_ENABLE    V_SWITCH_TABLE_ENABLE(1U)
+
+#define S_SGE_ENABLE    1
+#define V_SGE_ENABLE(x) ((x) << S_SGE_ENABLE)
+#define F_SGE_ENABLE    V_SGE_ENABLE(1U)
+
+#define S_CIM_ENABLE    0
+#define V_CIM_ENABLE(x) ((x) << S_CIM_ENABLE)
+#define F_CIM_ENABLE    V_CIM_ENABLE(1U)
+
+#define S_CIM_SPLIT_ENABLE    6
+#define V_CIM_SPLIT_ENABLE(x) ((x) << S_CIM_SPLIT_ENABLE)
+#define F_CIM_SPLIT_ENABLE    V_CIM_SPLIT_ENABLE(1U)
+
+#define A_CPL_SWITCH_TBL_IDX 0x19044
+
+#define S_SWITCH_TBL_IDX    0
+#define M_SWITCH_TBL_IDX    0xfU
+#define V_SWITCH_TBL_IDX(x) ((x) << S_SWITCH_TBL_IDX)
+#define G_SWITCH_TBL_IDX(x) (((x) >> S_SWITCH_TBL_IDX) & M_SWITCH_TBL_IDX)
+
+#define A_CPL_SWITCH_TBL_DATA 0x19048
+#define A_CPL_SWITCH_ZERO_ERROR 0x1904c
+
+#define S_ZERO_CMD_CH1    8
+#define M_ZERO_CMD_CH1    0xffU
+#define V_ZERO_CMD_CH1(x) ((x) << S_ZERO_CMD_CH1)
+#define G_ZERO_CMD_CH1(x) (((x) >> S_ZERO_CMD_CH1) & M_ZERO_CMD_CH1)
+
+#define S_ZERO_CMD_CH0    0
+#define M_ZERO_CMD_CH0    0xffU
+#define V_ZERO_CMD_CH0(x) ((x) << S_ZERO_CMD_CH0)
+#define G_ZERO_CMD_CH0(x) (((x) >> S_ZERO_CMD_CH0) & M_ZERO_CMD_CH0)
+
+#define A_CPL_INTR_ENABLE 0x19050
+
+#define S_CIM_OP_MAP_PERR    5
+#define V_CIM_OP_MAP_PERR(x) ((x) << S_CIM_OP_MAP_PERR)
+#define F_CIM_OP_MAP_PERR    V_CIM_OP_MAP_PERR(1U)
+
+#define S_CIM_OVFL_ERROR    4
+#define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR)
+#define F_CIM_OVFL_ERROR    V_CIM_OVFL_ERROR(1U)
+
+#define S_TP_FRAMING_ERROR    3
+#define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR)
+#define F_TP_FRAMING_ERROR    V_TP_FRAMING_ERROR(1U)
+
+#define S_SGE_FRAMING_ERROR    2
+#define V_SGE_FRAMING_ERROR(x) ((x) << S_SGE_FRAMING_ERROR)
+#define F_SGE_FRAMING_ERROR    V_SGE_FRAMING_ERROR(1U)
+
+#define S_CIM_FRAMING_ERROR    1
+#define V_CIM_FRAMING_ERROR(x) ((x) << S_CIM_FRAMING_ERROR)
+#define F_CIM_FRAMING_ERROR    V_CIM_FRAMING_ERROR(1U)
+
+#define S_ZERO_SWITCH_ERROR    0
+#define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR)
+#define F_ZERO_SWITCH_ERROR    V_ZERO_SWITCH_ERROR(1U)
+
+#define S_PERR_CPL_128TO128_1    7
+#define V_PERR_CPL_128TO128_1(x) ((x) << S_PERR_CPL_128TO128_1)
+#define F_PERR_CPL_128TO128_1    V_PERR_CPL_128TO128_1(1U)
+
+#define S_PERR_CPL_128TO128_0    6
+#define V_PERR_CPL_128TO128_0(x) ((x) << S_PERR_CPL_128TO128_0)
+#define F_PERR_CPL_128TO128_0    V_PERR_CPL_128TO128_0(1U)
+
+#define A_CPL_INTR_CAUSE 0x19054
+#define A_CPL_MAP_TBL_IDX 0x19058
+
+#define S_MAP_TBL_IDX    0
+#define M_MAP_TBL_IDX    0xffU
+#define V_MAP_TBL_IDX(x) ((x) << S_MAP_TBL_IDX)
+#define G_MAP_TBL_IDX(x) (((x) >> S_MAP_TBL_IDX) & M_MAP_TBL_IDX)
+
+#define S_CIM_SPLIT_OPCODE_PROGRAM    8
+#define V_CIM_SPLIT_OPCODE_PROGRAM(x) ((x) << S_CIM_SPLIT_OPCODE_PROGRAM)
+#define F_CIM_SPLIT_OPCODE_PROGRAM    V_CIM_SPLIT_OPCODE_PROGRAM(1U)
+
+#define A_CPL_MAP_TBL_DATA 0x1905c
+
+#define S_MAP_TBL_DATA    0
+#define M_MAP_TBL_DATA    0xffU
+#define V_MAP_TBL_DATA(x) ((x) << S_MAP_TBL_DATA)
+#define G_MAP_TBL_DATA(x) (((x) >> S_MAP_TBL_DATA) & M_MAP_TBL_DATA)
+
+/* registers for module SMB */
+#define SMB_BASE_ADDR 0x19060
+
+#define A_SMB_GLOBAL_TIME_CFG 0x19060
+
+#define S_MACROCNTCFG    8
+#define M_MACROCNTCFG    0x1fU
+#define V_MACROCNTCFG(x) ((x) << S_MACROCNTCFG)
+#define G_MACROCNTCFG(x) (((x) >> S_MACROCNTCFG) & M_MACROCNTCFG)
+
+#define S_MICROCNTCFG    0
+#define M_MICROCNTCFG    0xffU
+#define V_MICROCNTCFG(x) ((x) << S_MICROCNTCFG)
+#define G_MICROCNTCFG(x) (((x) >> S_MICROCNTCFG) & M_MICROCNTCFG)
+
+#define A_SMB_MST_TIMEOUT_CFG 0x19064
+
+#define S_MSTTIMEOUTCFG    0
+#define M_MSTTIMEOUTCFG    0xffffffU
+#define V_MSTTIMEOUTCFG(x) ((x) << S_MSTTIMEOUTCFG)
+#define G_MSTTIMEOUTCFG(x) (((x) >> S_MSTTIMEOUTCFG) & M_MSTTIMEOUTCFG)
+
+#define A_SMB_MST_CTL_CFG 0x19068
+
+#define S_MSTFIFODBG    31
+#define V_MSTFIFODBG(x) ((x) << S_MSTFIFODBG)
+#define F_MSTFIFODBG    V_MSTFIFODBG(1U)
+
+#define S_MSTFIFODBGCLR    30
+#define V_MSTFIFODBGCLR(x) ((x) << S_MSTFIFODBGCLR)
+#define F_MSTFIFODBGCLR    V_MSTFIFODBGCLR(1U)
+
+#define S_MSTRXBYTECFG    12
+#define M_MSTRXBYTECFG    0x3fU
+#define V_MSTRXBYTECFG(x) ((x) << S_MSTRXBYTECFG)
+#define G_MSTRXBYTECFG(x) (((x) >> S_MSTRXBYTECFG) & M_MSTRXBYTECFG)
+
+#define S_MSTTXBYTECFG    6
+#define M_MSTTXBYTECFG    0x3fU
+#define V_MSTTXBYTECFG(x) ((x) << S_MSTTXBYTECFG)
+#define G_MSTTXBYTECFG(x) (((x) >> S_MSTTXBYTECFG) & M_MSTTXBYTECFG)
+
+#define S_MSTRESET    1
+#define V_MSTRESET(x) ((x) << S_MSTRESET)
+#define F_MSTRESET    V_MSTRESET(1U)
+
+#define S_MSTCTLEN    0
+#define V_MSTCTLEN(x) ((x) << S_MSTCTLEN)
+#define F_MSTCTLEN    V_MSTCTLEN(1U)
+
+#define A_SMB_MST_CTL_STS 0x1906c
+
+#define S_MSTRXBYTECNT    12
+#define M_MSTRXBYTECNT    0x3fU
+#define V_MSTRXBYTECNT(x) ((x) << S_MSTRXBYTECNT)
+#define G_MSTRXBYTECNT(x) (((x) >> S_MSTRXBYTECNT) & M_MSTRXBYTECNT)
+
+#define S_MSTTXBYTECNT    6
+#define M_MSTTXBYTECNT    0x3fU
+#define V_MSTTXBYTECNT(x) ((x) << S_MSTTXBYTECNT)
+#define G_MSTTXBYTECNT(x) (((x) >> S_MSTTXBYTECNT) & M_MSTTXBYTECNT)
+
+#define S_MSTBUSYSTS    0
+#define V_MSTBUSYSTS(x) ((x) << S_MSTBUSYSTS)
+#define F_MSTBUSYSTS    V_MSTBUSYSTS(1U)
+
+#define A_SMB_MST_TX_FIFO_RDWR 0x19070
+#define A_SMB_MST_RX_FIFO_RDWR 0x19074
+#define A_SMB_SLV_TIMEOUT_CFG 0x19078
+
+#define S_SLVTIMEOUTCFG    0
+#define M_SLVTIMEOUTCFG    0xffffffU
+#define V_SLVTIMEOUTCFG(x) ((x) << S_SLVTIMEOUTCFG)
+#define G_SLVTIMEOUTCFG(x) (((x) >> S_SLVTIMEOUTCFG) & M_SLVTIMEOUTCFG)
+
+#define A_SMB_SLV_CTL_CFG 0x1907c
+
+#define S_SLVFIFODBG    31
+#define V_SLVFIFODBG(x) ((x) << S_SLVFIFODBG)
+#define F_SLVFIFODBG    V_SLVFIFODBG(1U)
+
+#define S_SLVFIFODBGCLR    30
+#define V_SLVFIFODBGCLR(x) ((x) << S_SLVFIFODBGCLR)
+#define F_SLVFIFODBGCLR    V_SLVFIFODBGCLR(1U)
+
+#define S_SLVCRCOUTBITINV    21
+#define V_SLVCRCOUTBITINV(x) ((x) << S_SLVCRCOUTBITINV)
+#define F_SLVCRCOUTBITINV    V_SLVCRCOUTBITINV(1U)
+
+#define S_SLVCRCOUTBITREV    20
+#define V_SLVCRCOUTBITREV(x) ((x) << S_SLVCRCOUTBITREV)
+#define F_SLVCRCOUTBITREV    V_SLVCRCOUTBITREV(1U)
+
+#define S_SLVCRCINBITREV    19
+#define V_SLVCRCINBITREV(x) ((x) << S_SLVCRCINBITREV)
+#define F_SLVCRCINBITREV    V_SLVCRCINBITREV(1U)
+
+#define S_SLVCRCPRESET    11
+#define M_SLVCRCPRESET    0xffU
+#define V_SLVCRCPRESET(x) ((x) << S_SLVCRCPRESET)
+#define G_SLVCRCPRESET(x) (((x) >> S_SLVCRCPRESET) & M_SLVCRCPRESET)
+
+#define S_SLVADDRCFG    4
+#define M_SLVADDRCFG    0x7fU
+#define V_SLVADDRCFG(x) ((x) << S_SLVADDRCFG)
+#define G_SLVADDRCFG(x) (((x) >> S_SLVADDRCFG) & M_SLVADDRCFG)
+
+#define S_SLVALRTSET    2
+#define V_SLVALRTSET(x) ((x) << S_SLVALRTSET)
+#define F_SLVALRTSET    V_SLVALRTSET(1U)
+
+#define S_SLVRESET    1
+#define V_SLVRESET(x) ((x) << S_SLVRESET)
+#define F_SLVRESET    V_SLVRESET(1U)
+
+#define S_SLVCTLEN    0
+#define V_SLVCTLEN(x) ((x) << S_SLVCTLEN)
+#define F_SLVCTLEN    V_SLVCTLEN(1U)
+
+#define A_SMB_SLV_CTL_STS 0x19080
+
+#define S_SLVFIFOTXCNT    12
+#define M_SLVFIFOTXCNT    0x3fU
+#define V_SLVFIFOTXCNT(x) ((x) << S_SLVFIFOTXCNT)
+#define G_SLVFIFOTXCNT(x) (((x) >> S_SLVFIFOTXCNT) & M_SLVFIFOTXCNT)
+
+#define S_SLVFIFOCNT    6
+#define M_SLVFIFOCNT    0x3fU
+#define V_SLVFIFOCNT(x) ((x) << S_SLVFIFOCNT)
+#define G_SLVFIFOCNT(x) (((x) >> S_SLVFIFOCNT) & M_SLVFIFOCNT)
+
+#define S_SLVALRTSTS    2
+#define V_SLVALRTSTS(x) ((x) << S_SLVALRTSTS)
+#define F_SLVALRTSTS    V_SLVALRTSTS(1U)
+
+#define S_SLVBUSYSTS    0
+#define V_SLVBUSYSTS(x) ((x) << S_SLVBUSYSTS)
+#define F_SLVBUSYSTS    V_SLVBUSYSTS(1U)
+
+#define A_SMB_SLV_FIFO_RDWR 0x19084
+#define A_SMB_INT_ENABLE 0x1908c
+
+#define S_MSTTXFIFOPAREN    21
+#define V_MSTTXFIFOPAREN(x) ((x) << S_MSTTXFIFOPAREN)
+#define F_MSTTXFIFOPAREN    V_MSTTXFIFOPAREN(1U)
+
+#define S_MSTRXFIFOPAREN    20
+#define V_MSTRXFIFOPAREN(x) ((x) << S_MSTRXFIFOPAREN)
+#define F_MSTRXFIFOPAREN    V_MSTRXFIFOPAREN(1U)
+
+#define S_SLVFIFOPAREN    19
+#define V_SLVFIFOPAREN(x) ((x) << S_SLVFIFOPAREN)
+#define F_SLVFIFOPAREN    V_SLVFIFOPAREN(1U)
+
+#define S_SLVUNEXPBUSSTOPEN    18
+#define V_SLVUNEXPBUSSTOPEN(x) ((x) << S_SLVUNEXPBUSSTOPEN)
+#define F_SLVUNEXPBUSSTOPEN    V_SLVUNEXPBUSSTOPEN(1U)
+
+#define S_SLVUNEXPBUSSTARTEN    17
+#define V_SLVUNEXPBUSSTARTEN(x) ((x) << S_SLVUNEXPBUSSTARTEN)
+#define F_SLVUNEXPBUSSTARTEN    V_SLVUNEXPBUSSTARTEN(1U)
+
+#define S_SLVCOMMANDCODEINVEN    16
+#define V_SLVCOMMANDCODEINVEN(x) ((x) << S_SLVCOMMANDCODEINVEN)
+#define F_SLVCOMMANDCODEINVEN    V_SLVCOMMANDCODEINVEN(1U)
+
+#define S_SLVBYTECNTERREN    15
+#define V_SLVBYTECNTERREN(x) ((x) << S_SLVBYTECNTERREN)
+#define F_SLVBYTECNTERREN    V_SLVBYTECNTERREN(1U)
+
+#define S_SLVUNEXPACKMSTEN    14
+#define V_SLVUNEXPACKMSTEN(x) ((x) << S_SLVUNEXPACKMSTEN)
+#define F_SLVUNEXPACKMSTEN    V_SLVUNEXPACKMSTEN(1U)
+
+#define S_SLVUNEXPNACKMSTEN    13
+#define V_SLVUNEXPNACKMSTEN(x) ((x) << S_SLVUNEXPNACKMSTEN)
+#define F_SLVUNEXPNACKMSTEN    V_SLVUNEXPNACKMSTEN(1U)
+
+#define S_SLVNOBUSSTOPEN    12
+#define V_SLVNOBUSSTOPEN(x) ((x) << S_SLVNOBUSSTOPEN)
+#define F_SLVNOBUSSTOPEN    V_SLVNOBUSSTOPEN(1U)
+
+#define S_SLVNOREPSTARTEN    11
+#define V_SLVNOREPSTARTEN(x) ((x) << S_SLVNOREPSTARTEN)
+#define F_SLVNOREPSTARTEN    V_SLVNOREPSTARTEN(1U)
+
+#define S_SLVRXADDRINTEN    10
+#define V_SLVRXADDRINTEN(x) ((x) << S_SLVRXADDRINTEN)
+#define F_SLVRXADDRINTEN    V_SLVRXADDRINTEN(1U)
+
+#define S_SLVRXPECERRINTEN    9
+#define V_SLVRXPECERRINTEN(x) ((x) << S_SLVRXPECERRINTEN)
+#define F_SLVRXPECERRINTEN    V_SLVRXPECERRINTEN(1U)
+
+#define S_SLVPREPTOARPINTEN    8
+#define V_SLVPREPTOARPINTEN(x) ((x) << S_SLVPREPTOARPINTEN)
+#define F_SLVPREPTOARPINTEN    V_SLVPREPTOARPINTEN(1U)
+
+#define S_SLVTIMEOUTINTEN    7
+#define V_SLVTIMEOUTINTEN(x) ((x) << S_SLVTIMEOUTINTEN)
+#define F_SLVTIMEOUTINTEN    V_SLVTIMEOUTINTEN(1U)
+
+#define S_SLVERRINTEN    6
+#define V_SLVERRINTEN(x) ((x) << S_SLVERRINTEN)
+#define F_SLVERRINTEN    V_SLVERRINTEN(1U)
+
+#define S_SLVDONEINTEN    5
+#define V_SLVDONEINTEN(x) ((x) << S_SLVDONEINTEN)
+#define F_SLVDONEINTEN    V_SLVDONEINTEN(1U)
+
+#define S_SLVRXRDYINTEN    4
+#define V_SLVRXRDYINTEN(x) ((x) << S_SLVRXRDYINTEN)
+#define F_SLVRXRDYINTEN    V_SLVRXRDYINTEN(1U)
+
+#define S_MSTTIMEOUTINTEN    3
+#define V_MSTTIMEOUTINTEN(x) ((x) << S_MSTTIMEOUTINTEN)
+#define F_MSTTIMEOUTINTEN    V_MSTTIMEOUTINTEN(1U)
+
+#define S_MSTNACKINTEN    2
+#define V_MSTNACKINTEN(x) ((x) << S_MSTNACKINTEN)
+#define F_MSTNACKINTEN    V_MSTNACKINTEN(1U)
+
+#define S_MSTLOSTARBINTEN    1
+#define V_MSTLOSTARBINTEN(x) ((x) << S_MSTLOSTARBINTEN)
+#define F_MSTLOSTARBINTEN    V_MSTLOSTARBINTEN(1U)
+
+#define S_MSTDONEINTEN    0
+#define V_MSTDONEINTEN(x) ((x) << S_MSTDONEINTEN)
+#define F_MSTDONEINTEN    V_MSTDONEINTEN(1U)
+
+#define A_SMB_INT_CAUSE 0x19090
+
+#define S_MSTTXFIFOPARINT    21
+#define V_MSTTXFIFOPARINT(x) ((x) << S_MSTTXFIFOPARINT)
+#define F_MSTTXFIFOPARINT    V_MSTTXFIFOPARINT(1U)
+
+#define S_MSTRXFIFOPARINT    20
+#define V_MSTRXFIFOPARINT(x) ((x) << S_MSTRXFIFOPARINT)
+#define F_MSTRXFIFOPARINT    V_MSTRXFIFOPARINT(1U)
+
+#define S_SLVFIFOPARINT    19
+#define V_SLVFIFOPARINT(x) ((x) << S_SLVFIFOPARINT)
+#define F_SLVFIFOPARINT    V_SLVFIFOPARINT(1U)
+
+#define S_SLVUNEXPBUSSTOPINT    18
+#define V_SLVUNEXPBUSSTOPINT(x) ((x) << S_SLVUNEXPBUSSTOPINT)
+#define F_SLVUNEXPBUSSTOPINT    V_SLVUNEXPBUSSTOPINT(1U)
+
+#define S_SLVUNEXPBUSSTARTINT    17
+#define V_SLVUNEXPBUSSTARTINT(x) ((x) << S_SLVUNEXPBUSSTARTINT)
+#define F_SLVUNEXPBUSSTARTINT    V_SLVUNEXPBUSSTARTINT(1U)
+
+#define S_SLVCOMMANDCODEINVINT    16
+#define V_SLVCOMMANDCODEINVINT(x) ((x) << S_SLVCOMMANDCODEINVINT)
+#define F_SLVCOMMANDCODEINVINT    V_SLVCOMMANDCODEINVINT(1U)
+
+#define S_SLVBYTECNTERRINT    15
+#define V_SLVBYTECNTERRINT(x) ((x) << S_SLVBYTECNTERRINT)
+#define F_SLVBYTECNTERRINT    V_SLVBYTECNTERRINT(1U)
+
+#define S_SLVUNEXPACKMSTINT    14
+#define V_SLVUNEXPACKMSTINT(x) ((x) << S_SLVUNEXPACKMSTINT)
+#define F_SLVUNEXPACKMSTINT    V_SLVUNEXPACKMSTINT(1U)
+
+#define S_SLVUNEXPNACKMSTINT    13
+#define V_SLVUNEXPNACKMSTINT(x) ((x) << S_SLVUNEXPNACKMSTINT)
+#define F_SLVUNEXPNACKMSTINT    V_SLVUNEXPNACKMSTINT(1U)
+
+#define S_SLVNOBUSSTOPINT    12
+#define V_SLVNOBUSSTOPINT(x) ((x) << S_SLVNOBUSSTOPINT)
+#define F_SLVNOBUSSTOPINT    V_SLVNOBUSSTOPINT(1U)
+
+#define S_SLVNOREPSTARTINT    11
+#define V_SLVNOREPSTARTINT(x) ((x) << S_SLVNOREPSTARTINT)
+#define F_SLVNOREPSTARTINT    V_SLVNOREPSTARTINT(1U)
+
+#define S_SLVRXADDRINT    10
+#define V_SLVRXADDRINT(x) ((x) << S_SLVRXADDRINT)
+#define F_SLVRXADDRINT    V_SLVRXADDRINT(1U)
+
+#define S_SLVRXPECERRINT    9
+#define V_SLVRXPECERRINT(x) ((x) << S_SLVRXPECERRINT)
+#define F_SLVRXPECERRINT    V_SLVRXPECERRINT(1U)
+
+#define S_SLVPREPTOARPINT    8
+#define V_SLVPREPTOARPINT(x) ((x) << S_SLVPREPTOARPINT)
+#define F_SLVPREPTOARPINT    V_SLVPREPTOARPINT(1U)
+
+#define S_SLVTIMEOUTINT    7
+#define V_SLVTIMEOUTINT(x) ((x) << S_SLVTIMEOUTINT)
+#define F_SLVTIMEOUTINT    V_SLVTIMEOUTINT(1U)
+
+#define S_SLVERRINT    6
+#define V_SLVERRINT(x) ((x) << S_SLVERRINT)
+#define F_SLVERRINT    V_SLVERRINT(1U)
+
+#define S_SLVDONEINT    5
+#define V_SLVDONEINT(x) ((x) << S_SLVDONEINT)
+#define F_SLVDONEINT    V_SLVDONEINT(1U)
+
+#define S_SLVRXRDYINT    4
+#define V_SLVRXRDYINT(x) ((x) << S_SLVRXRDYINT)
+#define F_SLVRXRDYINT    V_SLVRXRDYINT(1U)
+
+#define S_MSTTIMEOUTINT    3
+#define V_MSTTIMEOUTINT(x) ((x) << S_MSTTIMEOUTINT)
+#define F_MSTTIMEOUTINT    V_MSTTIMEOUTINT(1U)
+
+#define S_MSTNACKINT    2
+#define V_MSTNACKINT(x) ((x) << S_MSTNACKINT)
+#define F_MSTNACKINT    V_MSTNACKINT(1U)
+
+#define S_MSTLOSTARBINT    1
+#define V_MSTLOSTARBINT(x) ((x) << S_MSTLOSTARBINT)
+#define F_MSTLOSTARBINT    V_MSTLOSTARBINT(1U)
+
+#define S_MSTDONEINT    0
+#define V_MSTDONEINT(x) ((x) << S_MSTDONEINT)
+#define F_MSTDONEINT    V_MSTDONEINT(1U)
+
+#define A_SMB_DEBUG_DATA 0x19094
+
+#define S_DEBUGDATAH    16
+#define M_DEBUGDATAH    0xffffU
+#define V_DEBUGDATAH(x) ((x) << S_DEBUGDATAH)
+#define G_DEBUGDATAH(x) (((x) >> S_DEBUGDATAH) & M_DEBUGDATAH)
+
+#define S_DEBUGDATAL    0
+#define M_DEBUGDATAL    0xffffU
+#define V_DEBUGDATAL(x) ((x) << S_DEBUGDATAL)
+#define G_DEBUGDATAL(x) (((x) >> S_DEBUGDATAL) & M_DEBUGDATAL)
+
+#define A_SMB_PERR_EN 0x19098
+
+#define S_MSTTXFIFOPERREN    2
+#define V_MSTTXFIFOPERREN(x) ((x) << S_MSTTXFIFOPERREN)
+#define F_MSTTXFIFOPERREN    V_MSTTXFIFOPERREN(1U)
+
+#define S_MSTRXFIFOPERREN    1
+#define V_MSTRXFIFOPERREN(x) ((x) << S_MSTRXFIFOPERREN)
+#define F_MSTRXFIFOPERREN    V_MSTRXFIFOPERREN(1U)
+
+#define S_SLVFIFOPERREN    0
+#define V_SLVFIFOPERREN(x) ((x) << S_SLVFIFOPERREN)
+#define F_SLVFIFOPERREN    V_SLVFIFOPERREN(1U)
+
+#define S_MSTTXFIFO    21
+#define V_MSTTXFIFO(x) ((x) << S_MSTTXFIFO)
+#define F_MSTTXFIFO    V_MSTTXFIFO(1U)
+
+#define S_MSTRXFIFO    19
+#define V_MSTRXFIFO(x) ((x) << S_MSTRXFIFO)
+#define F_MSTRXFIFO    V_MSTRXFIFO(1U)
+
+#define S_SLVFIFO    18
+#define V_SLVFIFO(x) ((x) << S_SLVFIFO)
+#define F_SLVFIFO    V_SLVFIFO(1U)
+
+#define A_SMB_PERR_INJ 0x1909c
+
+#define S_MSTTXINJDATAERR    3
+#define V_MSTTXINJDATAERR(x) ((x) << S_MSTTXINJDATAERR)
+#define F_MSTTXINJDATAERR    V_MSTTXINJDATAERR(1U)
+
+#define S_MSTRXINJDATAERR    2
+#define V_MSTRXINJDATAERR(x) ((x) << S_MSTRXINJDATAERR)
+#define F_MSTRXINJDATAERR    V_MSTRXINJDATAERR(1U)
+
+#define S_SLVINJDATAERR    1
+#define V_SLVINJDATAERR(x) ((x) << S_SLVINJDATAERR)
+#define F_SLVINJDATAERR    V_SLVINJDATAERR(1U)
+
+#define S_FIFOINJDATAERREN    0
+#define V_FIFOINJDATAERREN(x) ((x) << S_FIFOINJDATAERREN)
+#define F_FIFOINJDATAERREN    V_FIFOINJDATAERREN(1U)
+
+#define A_SMB_SLV_ARP_CTL 0x190a0
+
+#define S_ARPCOMMANDCODE    2
+#define M_ARPCOMMANDCODE    0xffU
+#define V_ARPCOMMANDCODE(x) ((x) << S_ARPCOMMANDCODE)
+#define G_ARPCOMMANDCODE(x) (((x) >> S_ARPCOMMANDCODE) & M_ARPCOMMANDCODE)
+
+#define S_ARPADDRRES    1
+#define V_ARPADDRRES(x) ((x) << S_ARPADDRRES)
+#define F_ARPADDRRES    V_ARPADDRRES(1U)
+
+#define S_ARPADDRVAL    0
+#define V_ARPADDRVAL(x) ((x) << S_ARPADDRVAL)
+#define F_ARPADDRVAL    V_ARPADDRVAL(1U)
+
+#define A_SMB_ARP_UDID0 0x190a4
+#define A_SMB_ARP_UDID1 0x190a8
+
+#define S_SUBSYSTEMVENDORID    16
+#define M_SUBSYSTEMVENDORID    0xffffU
+#define V_SUBSYSTEMVENDORID(x) ((x) << S_SUBSYSTEMVENDORID)
+#define G_SUBSYSTEMVENDORID(x) (((x) >> S_SUBSYSTEMVENDORID) & M_SUBSYSTEMVENDORID)
+
+#define S_SUBSYSTEMDEVICEID    0
+#define M_SUBSYSTEMDEVICEID    0xffffU
+#define V_SUBSYSTEMDEVICEID(x) ((x) << S_SUBSYSTEMDEVICEID)
+#define G_SUBSYSTEMDEVICEID(x) (((x) >> S_SUBSYSTEMDEVICEID) & M_SUBSYSTEMDEVICEID)
+
+#define A_SMB_ARP_UDID2 0x190ac
+
+#define S_DEVICEID    16
+#define M_DEVICEID    0xffffU
+#define V_DEVICEID(x) ((x) << S_DEVICEID)
+#define G_DEVICEID(x) (((x) >> S_DEVICEID) & M_DEVICEID)
+
+#define S_INTERFACE    0
+#define M_INTERFACE    0xffffU
+#define V_INTERFACE(x) ((x) << S_INTERFACE)
+#define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE)
+
+#define A_SMB_ARP_UDID3 0x190b0
+
+#define S_DEVICECAP    24
+#define M_DEVICECAP    0xffU
+#define V_DEVICECAP(x) ((x) << S_DEVICECAP)
+#define G_DEVICECAP(x) (((x) >> S_DEVICECAP) & M_DEVICECAP)
+
+#define S_VERSIONID    16
+#define M_VERSIONID    0xffU
+#define V_VERSIONID(x) ((x) << S_VERSIONID)
+#define G_VERSIONID(x) (((x) >> S_VERSIONID) & M_VERSIONID)
+
+#define S_VENDORID    0
+#define M_VENDORID    0xffffU
+#define V_VENDORID(x) ((x) << S_VENDORID)
+#define G_VENDORID(x) (((x) >> S_VENDORID) & M_VENDORID)
+
+#define A_SMB_SLV_AUX_ADDR0 0x190b4
+
+#define S_AUXADDR0VAL    6
+#define V_AUXADDR0VAL(x) ((x) << S_AUXADDR0VAL)
+#define F_AUXADDR0VAL    V_AUXADDR0VAL(1U)
+
+#define S_AUXADDR0    0
+#define M_AUXADDR0    0x3fU
+#define V_AUXADDR0(x) ((x) << S_AUXADDR0)
+#define G_AUXADDR0(x) (((x) >> S_AUXADDR0) & M_AUXADDR0)
+
+#define A_SMB_SLV_AUX_ADDR1 0x190b8
+
+#define S_AUXADDR1VAL    6
+#define V_AUXADDR1VAL(x) ((x) << S_AUXADDR1VAL)
+#define F_AUXADDR1VAL    V_AUXADDR1VAL(1U)
+
+#define S_AUXADDR1    0
+#define M_AUXADDR1    0x3fU
+#define V_AUXADDR1(x) ((x) << S_AUXADDR1)
+#define G_AUXADDR1(x) (((x) >> S_AUXADDR1) & M_AUXADDR1)
+
+#define A_SMB_SLV_AUX_ADDR2 0x190bc
+
+#define S_AUXADDR2VAL    6
+#define V_AUXADDR2VAL(x) ((x) << S_AUXADDR2VAL)
+#define F_AUXADDR2VAL    V_AUXADDR2VAL(1U)
+
+#define S_AUXADDR2    0
+#define M_AUXADDR2    0x3fU
+#define V_AUXADDR2(x) ((x) << S_AUXADDR2)
+#define G_AUXADDR2(x) (((x) >> S_AUXADDR2) & M_AUXADDR2)
+
+#define A_SMB_SLV_AUX_ADDR3 0x190c0
+
+#define S_AUXADDR3VAL    6
+#define V_AUXADDR3VAL(x) ((x) << S_AUXADDR3VAL)
+#define F_AUXADDR3VAL    V_AUXADDR3VAL(1U)
+
+#define S_AUXADDR3    0
+#define M_AUXADDR3    0x3fU
+#define V_AUXADDR3(x) ((x) << S_AUXADDR3)
+#define G_AUXADDR3(x) (((x) >> S_AUXADDR3) & M_AUXADDR3)
+
+#define A_SMB_COMMAND_CODE0 0x190c4
+
+#define S_SMBUSCOMMANDCODE0    0
+#define M_SMBUSCOMMANDCODE0    0xffU
+#define V_SMBUSCOMMANDCODE0(x) ((x) << S_SMBUSCOMMANDCODE0)
+#define G_SMBUSCOMMANDCODE0(x) (((x) >> S_SMBUSCOMMANDCODE0) & M_SMBUSCOMMANDCODE0)
+
+#define A_SMB_COMMAND_CODE1 0x190c8
+
+#define S_SMBUSCOMMANDCODE1    0
+#define M_SMBUSCOMMANDCODE1    0xffU
+#define V_SMBUSCOMMANDCODE1(x) ((x) << S_SMBUSCOMMANDCODE1)
+#define G_SMBUSCOMMANDCODE1(x) (((x) >> S_SMBUSCOMMANDCODE1) & M_SMBUSCOMMANDCODE1)
+
+#define A_SMB_COMMAND_CODE2 0x190cc
+
+#define S_SMBUSCOMMANDCODE2    0
+#define M_SMBUSCOMMANDCODE2    0xffU
+#define V_SMBUSCOMMANDCODE2(x) ((x) << S_SMBUSCOMMANDCODE2)
+#define G_SMBUSCOMMANDCODE2(x) (((x) >> S_SMBUSCOMMANDCODE2) & M_SMBUSCOMMANDCODE2)
+
+#define A_SMB_COMMAND_CODE3 0x190d0
+
+#define S_SMBUSCOMMANDCODE3    0
+#define M_SMBUSCOMMANDCODE3    0xffU
+#define V_SMBUSCOMMANDCODE3(x) ((x) << S_SMBUSCOMMANDCODE3)
+#define G_SMBUSCOMMANDCODE3(x) (((x) >> S_SMBUSCOMMANDCODE3) & M_SMBUSCOMMANDCODE3)
+
+#define A_SMB_COMMAND_CODE4 0x190d4
+
+#define S_SMBUSCOMMANDCODE4    0
+#define M_SMBUSCOMMANDCODE4    0xffU
+#define V_SMBUSCOMMANDCODE4(x) ((x) << S_SMBUSCOMMANDCODE4)
+#define G_SMBUSCOMMANDCODE4(x) (((x) >> S_SMBUSCOMMANDCODE4) & M_SMBUSCOMMANDCODE4)
+
+#define A_SMB_COMMAND_CODE5 0x190d8
+
+#define S_SMBUSCOMMANDCODE5    0
+#define M_SMBUSCOMMANDCODE5    0xffU
+#define V_SMBUSCOMMANDCODE5(x) ((x) << S_SMBUSCOMMANDCODE5)
+#define G_SMBUSCOMMANDCODE5(x) (((x) >> S_SMBUSCOMMANDCODE5) & M_SMBUSCOMMANDCODE5)
+
+#define A_SMB_COMMAND_CODE6 0x190dc
+
+#define S_SMBUSCOMMANDCODE6    0
+#define M_SMBUSCOMMANDCODE6    0xffU
+#define V_SMBUSCOMMANDCODE6(x) ((x) << S_SMBUSCOMMANDCODE6)
+#define G_SMBUSCOMMANDCODE6(x) (((x) >> S_SMBUSCOMMANDCODE6) & M_SMBUSCOMMANDCODE6)
+
+#define A_SMB_COMMAND_CODE7 0x190e0
+
+#define S_SMBUSCOMMANDCODE7    0
+#define M_SMBUSCOMMANDCODE7    0xffU
+#define V_SMBUSCOMMANDCODE7(x) ((x) << S_SMBUSCOMMANDCODE7)
+#define G_SMBUSCOMMANDCODE7(x) (((x) >> S_SMBUSCOMMANDCODE7) & M_SMBUSCOMMANDCODE7)
+
+#define A_SMB_MICRO_CNT_CLK_CFG 0x190e4
+
+#define S_MACROCNTCLKCFG    8
+#define M_MACROCNTCLKCFG    0x1fU
+#define V_MACROCNTCLKCFG(x) ((x) << S_MACROCNTCLKCFG)
+#define G_MACROCNTCLKCFG(x) (((x) >> S_MACROCNTCLKCFG) & M_MACROCNTCLKCFG)
+
+#define S_MICROCNTCLKCFG    0
+#define M_MICROCNTCLKCFG    0xffU
+#define V_MICROCNTCLKCFG(x) ((x) << S_MICROCNTCLKCFG)
+#define G_MICROCNTCLKCFG(x) (((x) >> S_MICROCNTCLKCFG) & M_MICROCNTCLKCFG)
+
+#define A_SMB_CTL_STATUS 0x190e8
+
+#define S_MSTBUSBUSY    2
+#define V_MSTBUSBUSY(x) ((x) << S_MSTBUSBUSY)
+#define F_MSTBUSBUSY    V_MSTBUSBUSY(1U)
+
+#define S_SLVBUSBUSY    1
+#define V_SLVBUSBUSY(x) ((x) << S_SLVBUSBUSY)
+#define F_SLVBUSBUSY    V_SLVBUSBUSY(1U)
+
+#define S_BUSBUSY    0
+#define V_BUSBUSY(x) ((x) << S_BUSBUSY)
+#define F_BUSBUSY    V_BUSBUSY(1U)
+
+/* registers for module I2CM */
+#define I2CM_BASE_ADDR 0x190f0
+
+#define A_I2CM_CFG 0x190f0
+
+#define S_I2C_CLKDIV    0
+#define M_I2C_CLKDIV    0xfffU
+#define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV)
+#define G_I2C_CLKDIV(x) (((x) >> S_I2C_CLKDIV) & M_I2C_CLKDIV)
+
+#define S_I2C_CLKDIV16B    0
+#define M_I2C_CLKDIV16B    0xffffU
+#define V_I2C_CLKDIV16B(x) ((x) << S_I2C_CLKDIV16B)
+#define G_I2C_CLKDIV16B(x) (((x) >> S_I2C_CLKDIV16B) & M_I2C_CLKDIV16B)
+
+#define A_I2CM_DATA 0x190f4
+
+#define S_I2C_DATA    0
+#define M_I2C_DATA    0xffU
+#define V_I2C_DATA(x) ((x) << S_I2C_DATA)
+#define G_I2C_DATA(x) (((x) >> S_I2C_DATA) & M_I2C_DATA)
+
+#define A_I2CM_OP 0x190f8
+
+#define S_I2C_ACK    30
+#define V_I2C_ACK(x) ((x) << S_I2C_ACK)
+#define F_I2C_ACK    V_I2C_ACK(1U)
+
+#define S_I2C_CONT    1
+#define V_I2C_CONT(x) ((x) << S_I2C_CONT)
+#define F_I2C_CONT    V_I2C_CONT(1U)
+
+#define S_OP    0
+#define V_OP(x) ((x) << S_OP)
+#define F_OP    V_OP(1U)
+
+/* registers for module MI */
+#define MI_BASE_ADDR 0x19100
+
+#define A_MI_CFG 0x19100
+
+#define S_T4_ST    14
+#define V_T4_ST(x) ((x) << S_T4_ST)
+#define F_T4_ST    V_T4_ST(1U)
+
+#define S_CLKDIV    5
+#define M_CLKDIV    0xffU
+#define V_CLKDIV(x) ((x) << S_CLKDIV)
+#define G_CLKDIV(x) (((x) >> S_CLKDIV) & M_CLKDIV)
+
+#define S_ST    3
+#define M_ST    0x3U
+#define V_ST(x) ((x) << S_ST)
+#define G_ST(x) (((x) >> S_ST) & M_ST)
+
+#define S_PREEN    2
+#define V_PREEN(x) ((x) << S_PREEN)
+#define F_PREEN    V_PREEN(1U)
+
+#define S_MDIINV    1
+#define V_MDIINV(x) ((x) << S_MDIINV)
+#define F_MDIINV    V_MDIINV(1U)
+
+#define S_MDIO_1P2V_SEL    0
+#define V_MDIO_1P2V_SEL(x) ((x) << S_MDIO_1P2V_SEL)
+#define F_MDIO_1P2V_SEL    V_MDIO_1P2V_SEL(1U)
+
+#define A_MI_ADDR 0x19104
+
+#define S_PHYADDR    5
+#define M_PHYADDR    0x1fU
+#define V_PHYADDR(x) ((x) << S_PHYADDR)
+#define G_PHYADDR(x) (((x) >> S_PHYADDR) & M_PHYADDR)
+
+#define S_REGADDR    0
+#define M_REGADDR    0x1fU
+#define V_REGADDR(x) ((x) << S_REGADDR)
+#define G_REGADDR(x) (((x) >> S_REGADDR) & M_REGADDR)
+
+#define A_MI_DATA 0x19108
+
+#define S_MDIDATA    0
+#define M_MDIDATA    0xffffU
+#define V_MDIDATA(x) ((x) << S_MDIDATA)
+#define G_MDIDATA(x) (((x) >> S_MDIDATA) & M_MDIDATA)
+
+#define A_MI_OP 0x1910c
+
+#define S_INC    2
+#define V_INC(x) ((x) << S_INC)
+#define F_INC    V_INC(1U)
+
+#define S_MDIOP    0
+#define M_MDIOP    0x3U
+#define V_MDIOP(x) ((x) << S_MDIOP)
+#define G_MDIOP(x) (((x) >> S_MDIOP) & M_MDIOP)
+
+/* registers for module UART */
+#define UART_BASE_ADDR 0x19110
+
+#define A_UART_CONFIG 0x19110
+
+#define S_STOPBITS    22
+#define M_STOPBITS    0x3U
+#define V_STOPBITS(x) ((x) << S_STOPBITS)
+#define G_STOPBITS(x) (((x) >> S_STOPBITS) & M_STOPBITS)
+
+#define S_PARITY    20
+#define M_PARITY    0x3U
+#define V_PARITY(x) ((x) << S_PARITY)
+#define G_PARITY(x) (((x) >> S_PARITY) & M_PARITY)
+
+#define S_DATABITS    16
+#define M_DATABITS    0xfU
+#define V_DATABITS(x) ((x) << S_DATABITS)
+#define G_DATABITS(x) (((x) >> S_DATABITS) & M_DATABITS)
+
+#define S_UART_CLKDIV    0
+#define M_UART_CLKDIV    0xfffU
+#define V_UART_CLKDIV(x) ((x) << S_UART_CLKDIV)
+#define G_UART_CLKDIV(x) (((x) >> S_UART_CLKDIV) & M_UART_CLKDIV)
+
+/* registers for module PMU */
+#define PMU_BASE_ADDR 0x19120
+
+#define A_PMU_PART_CG_PWRMODE 0x19120
+
+#define S_TPPARTCGEN    14
+#define V_TPPARTCGEN(x) ((x) << S_TPPARTCGEN)
+#define F_TPPARTCGEN    V_TPPARTCGEN(1U)
+
+#define S_PDPPARTCGEN    13
+#define V_PDPPARTCGEN(x) ((x) << S_PDPPARTCGEN)
+#define F_PDPPARTCGEN    V_PDPPARTCGEN(1U)
+
+#define S_PCIEPARTCGEN    12
+#define V_PCIEPARTCGEN(x) ((x) << S_PCIEPARTCGEN)
+#define F_PCIEPARTCGEN    V_PCIEPARTCGEN(1U)
+
+#define S_EDC1PARTCGEN    11
+#define V_EDC1PARTCGEN(x) ((x) << S_EDC1PARTCGEN)
+#define F_EDC1PARTCGEN    V_EDC1PARTCGEN(1U)
+
+#define S_MCPARTCGEN    10
+#define V_MCPARTCGEN(x) ((x) << S_MCPARTCGEN)
+#define F_MCPARTCGEN    V_MCPARTCGEN(1U)
+
+#define S_EDC0PARTCGEN    9
+#define V_EDC0PARTCGEN(x) ((x) << S_EDC0PARTCGEN)
+#define F_EDC0PARTCGEN    V_EDC0PARTCGEN(1U)
+
+#define S_LEPARTCGEN    8
+#define V_LEPARTCGEN(x) ((x) << S_LEPARTCGEN)
+#define F_LEPARTCGEN    V_LEPARTCGEN(1U)
+
+#define S_INITPOWERMODE    0
+#define M_INITPOWERMODE    0x3U
+#define V_INITPOWERMODE(x) ((x) << S_INITPOWERMODE)
+#define G_INITPOWERMODE(x) (((x) >> S_INITPOWERMODE) & M_INITPOWERMODE)
+
+#define S_SGE_PART_CGEN    19
+#define V_SGE_PART_CGEN(x) ((x) << S_SGE_PART_CGEN)
+#define F_SGE_PART_CGEN    V_SGE_PART_CGEN(1U)
+
+#define S_PDP_PART_CGEN    18
+#define V_PDP_PART_CGEN(x) ((x) << S_PDP_PART_CGEN)
+#define F_PDP_PART_CGEN    V_PDP_PART_CGEN(1U)
+
+#define S_TP_PART_CGEN    17
+#define V_TP_PART_CGEN(x) ((x) << S_TP_PART_CGEN)
+#define F_TP_PART_CGEN    V_TP_PART_CGEN(1U)
+
+#define S_EDC0_PART_CGEN    16
+#define V_EDC0_PART_CGEN(x) ((x) << S_EDC0_PART_CGEN)
+#define F_EDC0_PART_CGEN    V_EDC0_PART_CGEN(1U)
+
+#define S_EDC1_PART_CGEN    15
+#define V_EDC1_PART_CGEN(x) ((x) << S_EDC1_PART_CGEN)
+#define F_EDC1_PART_CGEN    V_EDC1_PART_CGEN(1U)
+
+#define S_LE_PART_CGEN    14
+#define V_LE_PART_CGEN(x) ((x) << S_LE_PART_CGEN)
+#define F_LE_PART_CGEN    V_LE_PART_CGEN(1U)
+
+#define S_MA_PART_CGEN    13
+#define V_MA_PART_CGEN(x) ((x) << S_MA_PART_CGEN)
+#define F_MA_PART_CGEN    V_MA_PART_CGEN(1U)
+
+#define S_MC0_PART_CGEN    12
+#define V_MC0_PART_CGEN(x) ((x) << S_MC0_PART_CGEN)
+#define F_MC0_PART_CGEN    V_MC0_PART_CGEN(1U)
+
+#define S_MC1_PART_CGEN    11
+#define V_MC1_PART_CGEN(x) ((x) << S_MC1_PART_CGEN)
+#define F_MC1_PART_CGEN    V_MC1_PART_CGEN(1U)
+
+#define S_PCIE_PART_CGEN    10
+#define V_PCIE_PART_CGEN(x) ((x) << S_PCIE_PART_CGEN)
+#define F_PCIE_PART_CGEN    V_PCIE_PART_CGEN(1U)
+
+#define A_PMU_SLEEPMODE_WAKEUP 0x19124
+
+#define S_HWWAKEUPEN    5
+#define V_HWWAKEUPEN(x) ((x) << S_HWWAKEUPEN)
+#define F_HWWAKEUPEN    V_HWWAKEUPEN(1U)
+
+#define S_PORT3SLEEPMODE    4
+#define V_PORT3SLEEPMODE(x) ((x) << S_PORT3SLEEPMODE)
+#define F_PORT3SLEEPMODE    V_PORT3SLEEPMODE(1U)
+
+#define S_PORT2SLEEPMODE    3
+#define V_PORT2SLEEPMODE(x) ((x) << S_PORT2SLEEPMODE)
+#define F_PORT2SLEEPMODE    V_PORT2SLEEPMODE(1U)
+
+#define S_PORT1SLEEPMODE    2
+#define V_PORT1SLEEPMODE(x) ((x) << S_PORT1SLEEPMODE)
+#define F_PORT1SLEEPMODE    V_PORT1SLEEPMODE(1U)
+
+#define S_PORT0SLEEPMODE    1
+#define V_PORT0SLEEPMODE(x) ((x) << S_PORT0SLEEPMODE)
+#define F_PORT0SLEEPMODE    V_PORT0SLEEPMODE(1U)
+
+#define S_WAKEUP    0
+#define V_WAKEUP(x) ((x) << S_WAKEUP)
+#define F_WAKEUP    V_WAKEUP(1U)
+
+#define S_GLOBALDEEPSLEEPEN    6
+#define V_GLOBALDEEPSLEEPEN(x) ((x) << S_GLOBALDEEPSLEEPEN)
+#define F_GLOBALDEEPSLEEPEN    V_GLOBALDEEPSLEEPEN(1U)
+
+/* registers for module ULP_RX */
+#define ULP_RX_BASE_ADDR 0x19150
+
+#define A_ULP_RX_CTL 0x19150
+
+#define S_PCMD1THRESHOLD    24
+#define M_PCMD1THRESHOLD    0xffU
+#define V_PCMD1THRESHOLD(x) ((x) << S_PCMD1THRESHOLD)
+#define G_PCMD1THRESHOLD(x) (((x) >> S_PCMD1THRESHOLD) & M_PCMD1THRESHOLD)
+
+#define S_PCMD0THRESHOLD    16
+#define M_PCMD0THRESHOLD    0xffU
+#define V_PCMD0THRESHOLD(x) ((x) << S_PCMD0THRESHOLD)
+#define G_PCMD0THRESHOLD(x) (((x) >> S_PCMD0THRESHOLD) & M_PCMD0THRESHOLD)
+
+#define S_DISABLE_0B_STAG_ERR    14
+#define V_DISABLE_0B_STAG_ERR(x) ((x) << S_DISABLE_0B_STAG_ERR)
+#define F_DISABLE_0B_STAG_ERR    V_DISABLE_0B_STAG_ERR(1U)
+
+#define S_RDMA_0B_WR_OPCODE    10
+#define M_RDMA_0B_WR_OPCODE    0xfU
+#define V_RDMA_0B_WR_OPCODE(x) ((x) << S_RDMA_0B_WR_OPCODE)
+#define G_RDMA_0B_WR_OPCODE(x) (((x) >> S_RDMA_0B_WR_OPCODE) & M_RDMA_0B_WR_OPCODE)
+
+#define S_RDMA_0B_WR_PASS    9
+#define V_RDMA_0B_WR_PASS(x) ((x) << S_RDMA_0B_WR_PASS)
+#define F_RDMA_0B_WR_PASS    V_RDMA_0B_WR_PASS(1U)
+
+#define S_STAG_RQE    8
+#define V_STAG_RQE(x) ((x) << S_STAG_RQE)
+#define F_STAG_RQE    V_STAG_RQE(1U)
+
+#define S_RDMA_STATE_EN    7
+#define V_RDMA_STATE_EN(x) ((x) << S_RDMA_STATE_EN)
+#define F_RDMA_STATE_EN    V_RDMA_STATE_EN(1U)
+
+#define S_CRC1_EN    6
+#define V_CRC1_EN(x) ((x) << S_CRC1_EN)
+#define F_CRC1_EN    V_CRC1_EN(1U)
+
+#define S_RDMA_0B_WR_CQE    5
+#define V_RDMA_0B_WR_CQE(x) ((x) << S_RDMA_0B_WR_CQE)
+#define F_RDMA_0B_WR_CQE    V_RDMA_0B_WR_CQE(1U)
+
+#define S_PCIE_ATRB_EN    4
+#define V_PCIE_ATRB_EN(x) ((x) << S_PCIE_ATRB_EN)
+#define F_PCIE_ATRB_EN    V_PCIE_ATRB_EN(1U)
+
+#define S_RDMA_PERMISSIVE_MODE    3
+#define V_RDMA_PERMISSIVE_MODE(x) ((x) << S_RDMA_PERMISSIVE_MODE)
+#define F_RDMA_PERMISSIVE_MODE    V_RDMA_PERMISSIVE_MODE(1U)
+
+#define S_PAGEPODME    2
+#define V_PAGEPODME(x) ((x) << S_PAGEPODME)
+#define F_PAGEPODME    V_PAGEPODME(1U)
+
+#define S_ISCSITAGTCB    1
+#define V_ISCSITAGTCB(x) ((x) << S_ISCSITAGTCB)
+#define F_ISCSITAGTCB    V_ISCSITAGTCB(1U)
+
+#define S_TDDPTAGTCB    0
+#define V_TDDPTAGTCB(x) ((x) << S_TDDPTAGTCB)
+#define F_TDDPTAGTCB    V_TDDPTAGTCB(1U)
+
+#define A_ULP_RX_INT_ENABLE 0x19154
+
+#define S_ENABLE_CTX_1    24
+#define V_ENABLE_CTX_1(x) ((x) << S_ENABLE_CTX_1)
+#define F_ENABLE_CTX_1    V_ENABLE_CTX_1(1U)
+
+#define S_ENABLE_CTX_0    23
+#define V_ENABLE_CTX_0(x) ((x) << S_ENABLE_CTX_0)
+#define F_ENABLE_CTX_0    V_ENABLE_CTX_0(1U)
+
+#define S_ENABLE_FF    22
+#define V_ENABLE_FF(x) ((x) << S_ENABLE_FF)
+#define F_ENABLE_FF    V_ENABLE_FF(1U)
+
+#define S_ENABLE_APF_1    21
+#define V_ENABLE_APF_1(x) ((x) << S_ENABLE_APF_1)
+#define F_ENABLE_APF_1    V_ENABLE_APF_1(1U)
+
+#define S_ENABLE_APF_0    20
+#define V_ENABLE_APF_0(x) ((x) << S_ENABLE_APF_0)
+#define F_ENABLE_APF_0    V_ENABLE_APF_0(1U)
+
+#define S_ENABLE_AF_1    19
+#define V_ENABLE_AF_1(x) ((x) << S_ENABLE_AF_1)
+#define F_ENABLE_AF_1    V_ENABLE_AF_1(1U)
+
+#define S_ENABLE_AF_0    18
+#define V_ENABLE_AF_0(x) ((x) << S_ENABLE_AF_0)
+#define F_ENABLE_AF_0    V_ENABLE_AF_0(1U)
+
+#define S_ENABLE_DDPDF_1    17
+#define V_ENABLE_DDPDF_1(x) ((x) << S_ENABLE_DDPDF_1)
+#define F_ENABLE_DDPDF_1    V_ENABLE_DDPDF_1(1U)
+
+#define S_ENABLE_DDPMF_1    16
+#define V_ENABLE_DDPMF_1(x) ((x) << S_ENABLE_DDPMF_1)
+#define F_ENABLE_DDPMF_1    V_ENABLE_DDPMF_1(1U)
+
+#define S_ENABLE_MEMRF_1    15
+#define V_ENABLE_MEMRF_1(x) ((x) << S_ENABLE_MEMRF_1)
+#define F_ENABLE_MEMRF_1    V_ENABLE_MEMRF_1(1U)
+
+#define S_ENABLE_PRSDF_1    14
+#define V_ENABLE_PRSDF_1(x) ((x) << S_ENABLE_PRSDF_1)
+#define F_ENABLE_PRSDF_1    V_ENABLE_PRSDF_1(1U)
+
+#define S_ENABLE_DDPDF_0    13
+#define V_ENABLE_DDPDF_0(x) ((x) << S_ENABLE_DDPDF_0)
+#define F_ENABLE_DDPDF_0    V_ENABLE_DDPDF_0(1U)
+
+#define S_ENABLE_DDPMF_0    12
+#define V_ENABLE_DDPMF_0(x) ((x) << S_ENABLE_DDPMF_0)
+#define F_ENABLE_DDPMF_0    V_ENABLE_DDPMF_0(1U)
+
+#define S_ENABLE_MEMRF_0    11
+#define V_ENABLE_MEMRF_0(x) ((x) << S_ENABLE_MEMRF_0)
+#define F_ENABLE_MEMRF_0    V_ENABLE_MEMRF_0(1U)
+
+#define S_ENABLE_PRSDF_0    10
+#define V_ENABLE_PRSDF_0(x) ((x) << S_ENABLE_PRSDF_0)
+#define F_ENABLE_PRSDF_0    V_ENABLE_PRSDF_0(1U)
+
+#define S_ENABLE_PCMDF_1    9
+#define V_ENABLE_PCMDF_1(x) ((x) << S_ENABLE_PCMDF_1)
+#define F_ENABLE_PCMDF_1    V_ENABLE_PCMDF_1(1U)
+
+#define S_ENABLE_TPTCF_1    8
+#define V_ENABLE_TPTCF_1(x) ((x) << S_ENABLE_TPTCF_1)
+#define F_ENABLE_TPTCF_1    V_ENABLE_TPTCF_1(1U)
+
+#define S_ENABLE_DDPCF_1    7
+#define V_ENABLE_DDPCF_1(x) ((x) << S_ENABLE_DDPCF_1)
+#define F_ENABLE_DDPCF_1    V_ENABLE_DDPCF_1(1U)
+
+#define S_ENABLE_MPARF_1    6
+#define V_ENABLE_MPARF_1(x) ((x) << S_ENABLE_MPARF_1)
+#define F_ENABLE_MPARF_1    V_ENABLE_MPARF_1(1U)
+
+#define S_ENABLE_MPARC_1    5
+#define V_ENABLE_MPARC_1(x) ((x) << S_ENABLE_MPARC_1)
+#define F_ENABLE_MPARC_1    V_ENABLE_MPARC_1(1U)
+
+#define S_ENABLE_PCMDF_0    4
+#define V_ENABLE_PCMDF_0(x) ((x) << S_ENABLE_PCMDF_0)
+#define F_ENABLE_PCMDF_0    V_ENABLE_PCMDF_0(1U)
+
+#define S_ENABLE_TPTCF_0    3
+#define V_ENABLE_TPTCF_0(x) ((x) << S_ENABLE_TPTCF_0)
+#define F_ENABLE_TPTCF_0    V_ENABLE_TPTCF_0(1U)
+
+#define S_ENABLE_DDPCF_0    2
+#define V_ENABLE_DDPCF_0(x) ((x) << S_ENABLE_DDPCF_0)
+#define F_ENABLE_DDPCF_0    V_ENABLE_DDPCF_0(1U)
+
+#define S_ENABLE_MPARF_0    1
+#define V_ENABLE_MPARF_0(x) ((x) << S_ENABLE_MPARF_0)
+#define F_ENABLE_MPARF_0    V_ENABLE_MPARF_0(1U)
+
+#define S_ENABLE_MPARC_0    0
+#define V_ENABLE_MPARC_0(x) ((x) << S_ENABLE_MPARC_0)
+#define F_ENABLE_MPARC_0    V_ENABLE_MPARC_0(1U)
+
+#define S_SE_CNT_MISMATCH_1    26
+#define V_SE_CNT_MISMATCH_1(x) ((x) << S_SE_CNT_MISMATCH_1)
+#define F_SE_CNT_MISMATCH_1    V_SE_CNT_MISMATCH_1(1U)
+
+#define S_SE_CNT_MISMATCH_0    25
+#define V_SE_CNT_MISMATCH_0(x) ((x) << S_SE_CNT_MISMATCH_0)
+#define F_SE_CNT_MISMATCH_0    V_SE_CNT_MISMATCH_0(1U)
+
+#define A_ULP_RX_INT_CAUSE 0x19158
+
+#define S_CAUSE_CTX_1    24
+#define V_CAUSE_CTX_1(x) ((x) << S_CAUSE_CTX_1)
+#define F_CAUSE_CTX_1    V_CAUSE_CTX_1(1U)
+
+#define S_CAUSE_CTX_0    23
+#define V_CAUSE_CTX_0(x) ((x) << S_CAUSE_CTX_0)
+#define F_CAUSE_CTX_0    V_CAUSE_CTX_0(1U)
+
+#define S_CAUSE_FF    22
+#define V_CAUSE_FF(x) ((x) << S_CAUSE_FF)
+#define F_CAUSE_FF    V_CAUSE_FF(1U)
+
+#define S_CAUSE_APF_1    21
+#define V_CAUSE_APF_1(x) ((x) << S_CAUSE_APF_1)
+#define F_CAUSE_APF_1    V_CAUSE_APF_1(1U)
+
+#define S_CAUSE_APF_0    20
+#define V_CAUSE_APF_0(x) ((x) << S_CAUSE_APF_0)
+#define F_CAUSE_APF_0    V_CAUSE_APF_0(1U)
+
+#define S_CAUSE_AF_1    19
+#define V_CAUSE_AF_1(x) ((x) << S_CAUSE_AF_1)
+#define F_CAUSE_AF_1    V_CAUSE_AF_1(1U)
+
+#define S_CAUSE_AF_0    18
+#define V_CAUSE_AF_0(x) ((x) << S_CAUSE_AF_0)
+#define F_CAUSE_AF_0    V_CAUSE_AF_0(1U)
+
+#define S_CAUSE_DDPDF_1    17
+#define V_CAUSE_DDPDF_1(x) ((x) << S_CAUSE_DDPDF_1)
+#define F_CAUSE_DDPDF_1    V_CAUSE_DDPDF_1(1U)
+
+#define S_CAUSE_DDPMF_1    16
+#define V_CAUSE_DDPMF_1(x) ((x) << S_CAUSE_DDPMF_1)
+#define F_CAUSE_DDPMF_1    V_CAUSE_DDPMF_1(1U)
+
+#define S_CAUSE_MEMRF_1    15
+#define V_CAUSE_MEMRF_1(x) ((x) << S_CAUSE_MEMRF_1)
+#define F_CAUSE_MEMRF_1    V_CAUSE_MEMRF_1(1U)
+
+#define S_CAUSE_PRSDF_1    14
+#define V_CAUSE_PRSDF_1(x) ((x) << S_CAUSE_PRSDF_1)
+#define F_CAUSE_PRSDF_1    V_CAUSE_PRSDF_1(1U)
+
+#define S_CAUSE_DDPDF_0    13
+#define V_CAUSE_DDPDF_0(x) ((x) << S_CAUSE_DDPDF_0)
+#define F_CAUSE_DDPDF_0    V_CAUSE_DDPDF_0(1U)
+
+#define S_CAUSE_DDPMF_0    12
+#define V_CAUSE_DDPMF_0(x) ((x) << S_CAUSE_DDPMF_0)
+#define F_CAUSE_DDPMF_0    V_CAUSE_DDPMF_0(1U)
+
+#define S_CAUSE_MEMRF_0    11
+#define V_CAUSE_MEMRF_0(x) ((x) << S_CAUSE_MEMRF_0)
+#define F_CAUSE_MEMRF_0    V_CAUSE_MEMRF_0(1U)
+
+#define S_CAUSE_PRSDF_0    10
+#define V_CAUSE_PRSDF_0(x) ((x) << S_CAUSE_PRSDF_0)
+#define F_CAUSE_PRSDF_0    V_CAUSE_PRSDF_0(1U)
+
+#define S_CAUSE_PCMDF_1    9
+#define V_CAUSE_PCMDF_1(x) ((x) << S_CAUSE_PCMDF_1)
+#define F_CAUSE_PCMDF_1    V_CAUSE_PCMDF_1(1U)
+
+#define S_CAUSE_TPTCF_1    8
+#define V_CAUSE_TPTCF_1(x) ((x) << S_CAUSE_TPTCF_1)
+#define F_CAUSE_TPTCF_1    V_CAUSE_TPTCF_1(1U)
+
+#define S_CAUSE_DDPCF_1    7
+#define V_CAUSE_DDPCF_1(x) ((x) << S_CAUSE_DDPCF_1)
+#define F_CAUSE_DDPCF_1    V_CAUSE_DDPCF_1(1U)
+
+#define S_CAUSE_MPARF_1    6
+#define V_CAUSE_MPARF_1(x) ((x) << S_CAUSE_MPARF_1)
+#define F_CAUSE_MPARF_1    V_CAUSE_MPARF_1(1U)
+
+#define S_CAUSE_MPARC_1    5
+#define V_CAUSE_MPARC_1(x) ((x) << S_CAUSE_MPARC_1)
+#define F_CAUSE_MPARC_1    V_CAUSE_MPARC_1(1U)
+
+#define S_CAUSE_PCMDF_0    4
+#define V_CAUSE_PCMDF_0(x) ((x) << S_CAUSE_PCMDF_0)
+#define F_CAUSE_PCMDF_0    V_CAUSE_PCMDF_0(1U)
+
+#define S_CAUSE_TPTCF_0    3
+#define V_CAUSE_TPTCF_0(x) ((x) << S_CAUSE_TPTCF_0)
+#define F_CAUSE_TPTCF_0    V_CAUSE_TPTCF_0(1U)
+
+#define S_CAUSE_DDPCF_0    2
+#define V_CAUSE_DDPCF_0(x) ((x) << S_CAUSE_DDPCF_0)
+#define F_CAUSE_DDPCF_0    V_CAUSE_DDPCF_0(1U)
+
+#define S_CAUSE_MPARF_0    1
+#define V_CAUSE_MPARF_0(x) ((x) << S_CAUSE_MPARF_0)
+#define F_CAUSE_MPARF_0    V_CAUSE_MPARF_0(1U)
+
+#define S_CAUSE_MPARC_0    0
+#define V_CAUSE_MPARC_0(x) ((x) << S_CAUSE_MPARC_0)
+#define F_CAUSE_MPARC_0    V_CAUSE_MPARC_0(1U)
+
+#define A_ULP_RX_ISCSI_LLIMIT 0x1915c
+
+#define S_ISCSILLIMIT    6
+#define M_ISCSILLIMIT    0x3ffffffU
+#define V_ISCSILLIMIT(x) ((x) << S_ISCSILLIMIT)
+#define G_ISCSILLIMIT(x) (((x) >> S_ISCSILLIMIT) & M_ISCSILLIMIT)
+
+#define A_ULP_RX_ISCSI_ULIMIT 0x19160
+
+#define S_ISCSIULIMIT    6
+#define M_ISCSIULIMIT    0x3ffffffU
+#define V_ISCSIULIMIT(x) ((x) << S_ISCSIULIMIT)
+#define G_ISCSIULIMIT(x) (((x) >> S_ISCSIULIMIT) & M_ISCSIULIMIT)
+
+#define A_ULP_RX_ISCSI_TAGMASK 0x19164
+
+#define S_ISCSITAGMASK    6
+#define M_ISCSITAGMASK    0x3ffffffU
+#define V_ISCSITAGMASK(x) ((x) << S_ISCSITAGMASK)
+#define G_ISCSITAGMASK(x) (((x) >> S_ISCSITAGMASK) & M_ISCSITAGMASK)
+
+#define A_ULP_RX_ISCSI_PSZ 0x19168
+
+#define S_HPZ3    24
+#define M_HPZ3    0xfU
+#define V_HPZ3(x) ((x) << S_HPZ3)
+#define G_HPZ3(x) (((x) >> S_HPZ3) & M_HPZ3)
+
+#define S_HPZ2    16
+#define M_HPZ2    0xfU
+#define V_HPZ2(x) ((x) << S_HPZ2)
+#define G_HPZ2(x) (((x) >> S_HPZ2) & M_HPZ2)
+
+#define S_HPZ1    8
+#define M_HPZ1    0xfU
+#define V_HPZ1(x) ((x) << S_HPZ1)
+#define G_HPZ1(x) (((x) >> S_HPZ1) & M_HPZ1)
+
+#define S_HPZ0    0
+#define M_HPZ0    0xfU
+#define V_HPZ0(x) ((x) << S_HPZ0)
+#define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
+
+#define A_ULP_RX_TDDP_LLIMIT 0x1916c
+
+#define S_TDDPLLIMIT    6
+#define M_TDDPLLIMIT    0x3ffffffU
+#define V_TDDPLLIMIT(x) ((x) << S_TDDPLLIMIT)
+#define G_TDDPLLIMIT(x) (((x) >> S_TDDPLLIMIT) & M_TDDPLLIMIT)
+
+#define A_ULP_RX_TDDP_ULIMIT 0x19170
+
+#define S_TDDPULIMIT    6
+#define M_TDDPULIMIT    0x3ffffffU
+#define V_TDDPULIMIT(x) ((x) << S_TDDPULIMIT)
+#define G_TDDPULIMIT(x) (((x) >> S_TDDPULIMIT) & M_TDDPULIMIT)
+
+#define A_ULP_RX_TDDP_TAGMASK 0x19174
+
+#define S_TDDPTAGMASK    6
+#define M_TDDPTAGMASK    0x3ffffffU
+#define V_TDDPTAGMASK(x) ((x) << S_TDDPTAGMASK)
+#define G_TDDPTAGMASK(x) (((x) >> S_TDDPTAGMASK) & M_TDDPTAGMASK)
+
+#define A_ULP_RX_TDDP_PSZ 0x19178
+#define A_ULP_RX_STAG_LLIMIT 0x1917c
+#define A_ULP_RX_STAG_ULIMIT 0x19180
+#define A_ULP_RX_RQ_LLIMIT 0x19184
+#define A_ULP_RX_RQ_ULIMIT 0x19188
+#define A_ULP_RX_PBL_LLIMIT 0x1918c
+#define A_ULP_RX_PBL_ULIMIT 0x19190
+#define A_ULP_RX_CTX_BASE 0x19194
+#define A_ULP_RX_PERR_ENABLE 0x1919c
+
+#define S_PERR_ENABLE_FF    22
+#define V_PERR_ENABLE_FF(x) ((x) << S_PERR_ENABLE_FF)
+#define F_PERR_ENABLE_FF    V_PERR_ENABLE_FF(1U)
+
+#define S_PERR_ENABLE_APF_1    21
+#define V_PERR_ENABLE_APF_1(x) ((x) << S_PERR_ENABLE_APF_1)
+#define F_PERR_ENABLE_APF_1    V_PERR_ENABLE_APF_1(1U)
+
+#define S_PERR_ENABLE_APF_0    20
+#define V_PERR_ENABLE_APF_0(x) ((x) << S_PERR_ENABLE_APF_0)
+#define F_PERR_ENABLE_APF_0    V_PERR_ENABLE_APF_0(1U)
+
+#define S_PERR_ENABLE_AF_1    19
+#define V_PERR_ENABLE_AF_1(x) ((x) << S_PERR_ENABLE_AF_1)
+#define F_PERR_ENABLE_AF_1    V_PERR_ENABLE_AF_1(1U)
+
+#define S_PERR_ENABLE_AF_0    18
+#define V_PERR_ENABLE_AF_0(x) ((x) << S_PERR_ENABLE_AF_0)
+#define F_PERR_ENABLE_AF_0    V_PERR_ENABLE_AF_0(1U)
+
+#define S_PERR_ENABLE_DDPDF_1    17
+#define V_PERR_ENABLE_DDPDF_1(x) ((x) << S_PERR_ENABLE_DDPDF_1)
+#define F_PERR_ENABLE_DDPDF_1    V_PERR_ENABLE_DDPDF_1(1U)
+
+#define S_PERR_ENABLE_DDPMF_1    16
+#define V_PERR_ENABLE_DDPMF_1(x) ((x) << S_PERR_ENABLE_DDPMF_1)
+#define F_PERR_ENABLE_DDPMF_1    V_PERR_ENABLE_DDPMF_1(1U)
+
+#define S_PERR_ENABLE_MEMRF_1    15
+#define V_PERR_ENABLE_MEMRF_1(x) ((x) << S_PERR_ENABLE_MEMRF_1)
+#define F_PERR_ENABLE_MEMRF_1    V_PERR_ENABLE_MEMRF_1(1U)
+
+#define S_PERR_ENABLE_PRSDF_1    14
+#define V_PERR_ENABLE_PRSDF_1(x) ((x) << S_PERR_ENABLE_PRSDF_1)
+#define F_PERR_ENABLE_PRSDF_1    V_PERR_ENABLE_PRSDF_1(1U)
+
+#define S_PERR_ENABLE_DDPDF_0    13
+#define V_PERR_ENABLE_DDPDF_0(x) ((x) << S_PERR_ENABLE_DDPDF_0)
+#define F_PERR_ENABLE_DDPDF_0    V_PERR_ENABLE_DDPDF_0(1U)
+
+#define S_PERR_ENABLE_DDPMF_0    12
+#define V_PERR_ENABLE_DDPMF_0(x) ((x) << S_PERR_ENABLE_DDPMF_0)
+#define F_PERR_ENABLE_DDPMF_0    V_PERR_ENABLE_DDPMF_0(1U)
+
+#define S_PERR_ENABLE_MEMRF_0    11
+#define V_PERR_ENABLE_MEMRF_0(x) ((x) << S_PERR_ENABLE_MEMRF_0)
+#define F_PERR_ENABLE_MEMRF_0    V_PERR_ENABLE_MEMRF_0(1U)
+
+#define S_PERR_ENABLE_PRSDF_0    10
+#define V_PERR_ENABLE_PRSDF_0(x) ((x) << S_PERR_ENABLE_PRSDF_0)
+#define F_PERR_ENABLE_PRSDF_0    V_PERR_ENABLE_PRSDF_0(1U)
+
+#define S_PERR_ENABLE_PCMDF_1    9
+#define V_PERR_ENABLE_PCMDF_1(x) ((x) << S_PERR_ENABLE_PCMDF_1)
+#define F_PERR_ENABLE_PCMDF_1    V_PERR_ENABLE_PCMDF_1(1U)
+
+#define S_PERR_ENABLE_TPTCF_1    8
+#define V_PERR_ENABLE_TPTCF_1(x) ((x) << S_PERR_ENABLE_TPTCF_1)
+#define F_PERR_ENABLE_TPTCF_1    V_PERR_ENABLE_TPTCF_1(1U)
+
+#define S_PERR_ENABLE_DDPCF_1    7
+#define V_PERR_ENABLE_DDPCF_1(x) ((x) << S_PERR_ENABLE_DDPCF_1)
+#define F_PERR_ENABLE_DDPCF_1    V_PERR_ENABLE_DDPCF_1(1U)
+
+#define S_PERR_ENABLE_MPARF_1    6
+#define V_PERR_ENABLE_MPARF_1(x) ((x) << S_PERR_ENABLE_MPARF_1)
+#define F_PERR_ENABLE_MPARF_1    V_PERR_ENABLE_MPARF_1(1U)
+
+#define S_PERR_ENABLE_MPARC_1    5
+#define V_PERR_ENABLE_MPARC_1(x) ((x) << S_PERR_ENABLE_MPARC_1)
+#define F_PERR_ENABLE_MPARC_1    V_PERR_ENABLE_MPARC_1(1U)
+
+#define S_PERR_ENABLE_PCMDF_0    4
+#define V_PERR_ENABLE_PCMDF_0(x) ((x) << S_PERR_ENABLE_PCMDF_0)
+#define F_PERR_ENABLE_PCMDF_0    V_PERR_ENABLE_PCMDF_0(1U)
+
+#define S_PERR_ENABLE_TPTCF_0    3
+#define V_PERR_ENABLE_TPTCF_0(x) ((x) << S_PERR_ENABLE_TPTCF_0)
+#define F_PERR_ENABLE_TPTCF_0    V_PERR_ENABLE_TPTCF_0(1U)
+
+#define S_PERR_ENABLE_DDPCF_0    2
+#define V_PERR_ENABLE_DDPCF_0(x) ((x) << S_PERR_ENABLE_DDPCF_0)
+#define F_PERR_ENABLE_DDPCF_0    V_PERR_ENABLE_DDPCF_0(1U)
+
+#define S_PERR_ENABLE_MPARF_0    1
+#define V_PERR_ENABLE_MPARF_0(x) ((x) << S_PERR_ENABLE_MPARF_0)
+#define F_PERR_ENABLE_MPARF_0    V_PERR_ENABLE_MPARF_0(1U)
+
+#define S_PERR_ENABLE_MPARC_0    0
+#define V_PERR_ENABLE_MPARC_0(x) ((x) << S_PERR_ENABLE_MPARC_0)
+#define F_PERR_ENABLE_MPARC_0    V_PERR_ENABLE_MPARC_0(1U)
+
+#define S_PERR_SE_CNT_MISMATCH_1    26
+#define V_PERR_SE_CNT_MISMATCH_1(x) ((x) << S_PERR_SE_CNT_MISMATCH_1)
+#define F_PERR_SE_CNT_MISMATCH_1    V_PERR_SE_CNT_MISMATCH_1(1U)
+
+#define S_PERR_SE_CNT_MISMATCH_0    25
+#define V_PERR_SE_CNT_MISMATCH_0(x) ((x) << S_PERR_SE_CNT_MISMATCH_0)
+#define F_PERR_SE_CNT_MISMATCH_0    V_PERR_SE_CNT_MISMATCH_0(1U)
+
+#define S_PERR_RSVD0    24
+#define V_PERR_RSVD0(x) ((x) << S_PERR_RSVD0)
+#define F_PERR_RSVD0    V_PERR_RSVD0(1U)
+
+#define S_PERR_RSVD1    23
+#define V_PERR_RSVD1(x) ((x) << S_PERR_RSVD1)
+#define F_PERR_RSVD1    V_PERR_RSVD1(1U)
+
+#define A_ULP_RX_PERR_INJECT 0x191a0
+#define A_ULP_RX_RQUDP_LLIMIT 0x191a4
+#define A_ULP_RX_RQUDP_ULIMIT 0x191a8
+#define A_ULP_RX_CTX_ACC_CH0 0x191ac
+
+#define S_REQ    21
+#define V_REQ(x) ((x) << S_REQ)
+#define F_REQ    V_REQ(1U)
+
+#define S_WB    20
+#define V_WB(x) ((x) << S_WB)
+#define F_WB    V_WB(1U)
+
+#define S_ULPRX_TID    0
+#define M_ULPRX_TID    0xfffffU
+#define V_ULPRX_TID(x) ((x) << S_ULPRX_TID)
+#define G_ULPRX_TID(x) (((x) >> S_ULPRX_TID) & M_ULPRX_TID)
+
+#define A_ULP_RX_CTX_ACC_CH1 0x191b0
+#define A_ULP_RX_SE_CNT_ERR 0x191d0
+#define A_ULP_RX_SE_CNT_CLR 0x191d4
+
+#define S_CLRCHAN0    4
+#define M_CLRCHAN0    0xfU
+#define V_CLRCHAN0(x) ((x) << S_CLRCHAN0)
+#define G_CLRCHAN0(x) (((x) >> S_CLRCHAN0) & M_CLRCHAN0)
+
+#define S_CLRCHAN1    0
+#define M_CLRCHAN1    0xfU
+#define V_CLRCHAN1(x) ((x) << S_CLRCHAN1)
+#define G_CLRCHAN1(x) (((x) >> S_CLRCHAN1) & M_CLRCHAN1)
+
+#define A_ULP_RX_SE_CNT_CH0 0x191d8
+
+#define S_SOP_CNT_OUT0    28
+#define M_SOP_CNT_OUT0    0xfU
+#define V_SOP_CNT_OUT0(x) ((x) << S_SOP_CNT_OUT0)
+#define G_SOP_CNT_OUT0(x) (((x) >> S_SOP_CNT_OUT0) & M_SOP_CNT_OUT0)
+
+#define S_EOP_CNT_OUT0    24
+#define M_EOP_CNT_OUT0    0xfU
+#define V_EOP_CNT_OUT0(x) ((x) << S_EOP_CNT_OUT0)
+#define G_EOP_CNT_OUT0(x) (((x) >> S_EOP_CNT_OUT0) & M_EOP_CNT_OUT0)
+
+#define S_SOP_CNT_AL0    20
+#define M_SOP_CNT_AL0    0xfU
+#define V_SOP_CNT_AL0(x) ((x) << S_SOP_CNT_AL0)
+#define G_SOP_CNT_AL0(x) (((x) >> S_SOP_CNT_AL0) & M_SOP_CNT_AL0)
+
+#define S_EOP_CNT_AL0    16
+#define M_EOP_CNT_AL0    0xfU
+#define V_EOP_CNT_AL0(x) ((x) << S_EOP_CNT_AL0)
+#define G_EOP_CNT_AL0(x) (((x) >> S_EOP_CNT_AL0) & M_EOP_CNT_AL0)
+
+#define S_SOP_CNT_MR0    12
+#define M_SOP_CNT_MR0    0xfU
+#define V_SOP_CNT_MR0(x) ((x) << S_SOP_CNT_MR0)
+#define G_SOP_CNT_MR0(x) (((x) >> S_SOP_CNT_MR0) & M_SOP_CNT_MR0)
+
+#define S_EOP_CNT_MR0    8
+#define M_EOP_CNT_MR0    0xfU
+#define V_EOP_CNT_MR0(x) ((x) << S_EOP_CNT_MR0)
+#define G_EOP_CNT_MR0(x) (((x) >> S_EOP_CNT_MR0) & M_EOP_CNT_MR0)
+
+#define S_SOP_CNT_IN0    4
+#define M_SOP_CNT_IN0    0xfU
+#define V_SOP_CNT_IN0(x) ((x) << S_SOP_CNT_IN0)
+#define G_SOP_CNT_IN0(x) (((x) >> S_SOP_CNT_IN0) & M_SOP_CNT_IN0)
+
+#define S_EOP_CNT_IN0    0
+#define M_EOP_CNT_IN0    0xfU
+#define V_EOP_CNT_IN0(x) ((x) << S_EOP_CNT_IN0)
+#define G_EOP_CNT_IN0(x) (((x) >> S_EOP_CNT_IN0) & M_EOP_CNT_IN0)
+
+#define A_ULP_RX_SE_CNT_CH1 0x191dc
+
+#define S_SOP_CNT_OUT1    28
+#define M_SOP_CNT_OUT1    0xfU
+#define V_SOP_CNT_OUT1(x) ((x) << S_SOP_CNT_OUT1)
+#define G_SOP_CNT_OUT1(x) (((x) >> S_SOP_CNT_OUT1) & M_SOP_CNT_OUT1)
+
+#define S_EOP_CNT_OUT1    24
+#define M_EOP_CNT_OUT1    0xfU
+#define V_EOP_CNT_OUT1(x) ((x) << S_EOP_CNT_OUT1)
+#define G_EOP_CNT_OUT1(x) (((x) >> S_EOP_CNT_OUT1) & M_EOP_CNT_OUT1)
+
+#define S_SOP_CNT_AL1    20
+#define M_SOP_CNT_AL1    0xfU
+#define V_SOP_CNT_AL1(x) ((x) << S_SOP_CNT_AL1)
+#define G_SOP_CNT_AL1(x) (((x) >> S_SOP_CNT_AL1) & M_SOP_CNT_AL1)
+
+#define S_EOP_CNT_AL1    16
+#define M_EOP_CNT_AL1    0xfU
+#define V_EOP_CNT_AL1(x) ((x) << S_EOP_CNT_AL1)
+#define G_EOP_CNT_AL1(x) (((x) >> S_EOP_CNT_AL1) & M_EOP_CNT_AL1)
+
+#define S_SOP_CNT_MR1    12
+#define M_SOP_CNT_MR1    0xfU
+#define V_SOP_CNT_MR1(x) ((x) << S_SOP_CNT_MR1)
+#define G_SOP_CNT_MR1(x) (((x) >> S_SOP_CNT_MR1) & M_SOP_CNT_MR1)
+
+#define S_EOP_CNT_MR1    8
+#define M_EOP_CNT_MR1    0xfU
+#define V_EOP_CNT_MR1(x) ((x) << S_EOP_CNT_MR1)
+#define G_EOP_CNT_MR1(x) (((x) >> S_EOP_CNT_MR1) & M_EOP_CNT_MR1)
+
+#define S_SOP_CNT_IN1    4
+#define M_SOP_CNT_IN1    0xfU
+#define V_SOP_CNT_IN1(x) ((x) << S_SOP_CNT_IN1)
+#define G_SOP_CNT_IN1(x) (((x) >> S_SOP_CNT_IN1) & M_SOP_CNT_IN1)
+
+#define S_EOP_CNT_IN1    0
+#define M_EOP_CNT_IN1    0xfU
+#define V_EOP_CNT_IN1(x) ((x) << S_EOP_CNT_IN1)
+#define G_EOP_CNT_IN1(x) (((x) >> S_EOP_CNT_IN1) & M_EOP_CNT_IN1)
+
+#define A_ULP_RX_DBG_CTL 0x191e0
+
+#define S_EN_DBG_H    17
+#define V_EN_DBG_H(x) ((x) << S_EN_DBG_H)
+#define F_EN_DBG_H    V_EN_DBG_H(1U)
+
+#define S_EN_DBG_L    16
+#define V_EN_DBG_L(x) ((x) << S_EN_DBG_L)
+#define F_EN_DBG_L    V_EN_DBG_L(1U)
+
+#define S_SEL_H    8
+#define M_SEL_H    0xffU
+#define V_SEL_H(x) ((x) << S_SEL_H)
+#define G_SEL_H(x) (((x) >> S_SEL_H) & M_SEL_H)
+
+#define S_SEL_L    0
+#define M_SEL_L    0xffU
+#define V_SEL_L(x) ((x) << S_SEL_L)
+#define G_SEL_L(x) (((x) >> S_SEL_L) & M_SEL_L)
+
+#define A_ULP_RX_DBG_DATAH 0x191e4
+#define A_ULP_RX_DBG_DATAL 0x191e8
+#define A_ULP_RX_LA_CHNL 0x19238
+
+#define S_CHNL_SEL    0
+#define V_CHNL_SEL(x) ((x) << S_CHNL_SEL)
+#define F_CHNL_SEL    V_CHNL_SEL(1U)
+
+#define A_ULP_RX_LA_CTL 0x1923c
+
+#define S_TRC_SEL    0
+#define V_TRC_SEL(x) ((x) << S_TRC_SEL)
+#define F_TRC_SEL    V_TRC_SEL(1U)
+
+#define A_ULP_RX_LA_RDPTR 0x19240
+
+#define S_RD_PTR    0
+#define M_RD_PTR    0x1ffU
+#define V_RD_PTR(x) ((x) << S_RD_PTR)
+#define G_RD_PTR(x) (((x) >> S_RD_PTR) & M_RD_PTR)
+
+#define A_ULP_RX_LA_RDDATA 0x19244
+#define A_ULP_RX_LA_WRPTR 0x19248
+
+#define S_WR_PTR    0
+#define M_WR_PTR    0x1ffU
+#define V_WR_PTR(x) ((x) << S_WR_PTR)
+#define G_WR_PTR(x) (((x) >> S_WR_PTR) & M_WR_PTR)
+
+#define A_ULP_RX_LA_RESERVED 0x1924c
+#define A_ULP_RX_CQE_GEN_EN 0x19250
+
+#define S_TERMIMATE_MSG    1
+#define V_TERMIMATE_MSG(x) ((x) << S_TERMIMATE_MSG)
+#define F_TERMIMATE_MSG    V_TERMIMATE_MSG(1U)
+
+#define S_TERMINATE_WITH_ERR    0
+#define V_TERMINATE_WITH_ERR(x) ((x) << S_TERMINATE_WITH_ERR)
+#define F_TERMINATE_WITH_ERR    V_TERMINATE_WITH_ERR(1U)
+
+#define A_ULP_RX_ATOMIC_OPCODES 0x19254
+
+#define S_ATOMIC_REQ_QNO    22
+#define M_ATOMIC_REQ_QNO    0x3U
+#define V_ATOMIC_REQ_QNO(x) ((x) << S_ATOMIC_REQ_QNO)
+#define G_ATOMIC_REQ_QNO(x) (((x) >> S_ATOMIC_REQ_QNO) & M_ATOMIC_REQ_QNO)
+
+#define S_ATOMIC_RSP_QNO    20
+#define M_ATOMIC_RSP_QNO    0x3U
+#define V_ATOMIC_RSP_QNO(x) ((x) << S_ATOMIC_RSP_QNO)
+#define G_ATOMIC_RSP_QNO(x) (((x) >> S_ATOMIC_RSP_QNO) & M_ATOMIC_RSP_QNO)
+
+#define S_IMMEDIATE_QNO    18
+#define M_IMMEDIATE_QNO    0x3U
+#define V_IMMEDIATE_QNO(x) ((x) << S_IMMEDIATE_QNO)
+#define G_IMMEDIATE_QNO(x) (((x) >> S_IMMEDIATE_QNO) & M_IMMEDIATE_QNO)
+
+#define S_IMMEDIATE_WITH_SE_QNO    16
+#define M_IMMEDIATE_WITH_SE_QNO    0x3U
+#define V_IMMEDIATE_WITH_SE_QNO(x) ((x) << S_IMMEDIATE_WITH_SE_QNO)
+#define G_IMMEDIATE_WITH_SE_QNO(x) (((x) >> S_IMMEDIATE_WITH_SE_QNO) & M_IMMEDIATE_WITH_SE_QNO)
+
+#define S_ATOMIC_WR_OPCODE    12
+#define M_ATOMIC_WR_OPCODE    0xfU
+#define V_ATOMIC_WR_OPCODE(x) ((x) << S_ATOMIC_WR_OPCODE)
+#define G_ATOMIC_WR_OPCODE(x) (((x) >> S_ATOMIC_WR_OPCODE) & M_ATOMIC_WR_OPCODE)
+
+#define S_ATOMIC_RD_OPCODE    8
+#define M_ATOMIC_RD_OPCODE    0xfU
+#define V_ATOMIC_RD_OPCODE(x) ((x) << S_ATOMIC_RD_OPCODE)
+#define G_ATOMIC_RD_OPCODE(x) (((x) >> S_ATOMIC_RD_OPCODE) & M_ATOMIC_RD_OPCODE)
+
+#define S_IMMEDIATE_OPCODE    4
+#define M_IMMEDIATE_OPCODE    0xfU
+#define V_IMMEDIATE_OPCODE(x) ((x) << S_IMMEDIATE_OPCODE)
+#define G_IMMEDIATE_OPCODE(x) (((x) >> S_IMMEDIATE_OPCODE) & M_IMMEDIATE_OPCODE)
+
+#define S_IMMEDIATE_WITH_SE_OPCODE    0
+#define M_IMMEDIATE_WITH_SE_OPCODE    0xfU
+#define V_IMMEDIATE_WITH_SE_OPCODE(x) ((x) << S_IMMEDIATE_WITH_SE_OPCODE)
+#define G_IMMEDIATE_WITH_SE_OPCODE(x) (((x) >> S_IMMEDIATE_WITH_SE_OPCODE) & M_IMMEDIATE_WITH_SE_OPCODE)
+
+#define A_ULP_RX_T10_CRC_ENDIAN_SWITCHING 0x19258
+
+#define S_EN_ORIG_DATA    0
+#define V_EN_ORIG_DATA(x) ((x) << S_EN_ORIG_DATA)
+#define F_EN_ORIG_DATA    V_EN_ORIG_DATA(1U)
+
+#define A_ULP_RX_MISC_FEATURE_ENABLE 0x1925c
+
+#define S_TERMINATE_STATUS_EN    4
+#define V_TERMINATE_STATUS_EN(x) ((x) << S_TERMINATE_STATUS_EN)
+#define F_TERMINATE_STATUS_EN    V_TERMINATE_STATUS_EN(1U)
+
+#define S_MULTIPLE_PREF_ENABLE    3
+#define V_MULTIPLE_PREF_ENABLE(x) ((x) << S_MULTIPLE_PREF_ENABLE)
+#define F_MULTIPLE_PREF_ENABLE    V_MULTIPLE_PREF_ENABLE(1U)
+
+#define S_UMUDP_PBL_PREF_ENABLE    2
+#define V_UMUDP_PBL_PREF_ENABLE(x) ((x) << S_UMUDP_PBL_PREF_ENABLE)
+#define F_UMUDP_PBL_PREF_ENABLE    V_UMUDP_PBL_PREF_ENABLE(1U)
+
+#define S_RDMA_PBL_PREF_EN    1
+#define V_RDMA_PBL_PREF_EN(x) ((x) << S_RDMA_PBL_PREF_EN)
+#define F_RDMA_PBL_PREF_EN    V_RDMA_PBL_PREF_EN(1U)
+
+#define S_SDC_CRC_PROT_EN    0
+#define V_SDC_CRC_PROT_EN(x) ((x) << S_SDC_CRC_PROT_EN)
+#define F_SDC_CRC_PROT_EN    V_SDC_CRC_PROT_EN(1U)
+
+#define A_ULP_RX_CH0_CGEN 0x19260
+
+#define S_BYPASS_CGEN    7
+#define V_BYPASS_CGEN(x) ((x) << S_BYPASS_CGEN)
+#define F_BYPASS_CGEN    V_BYPASS_CGEN(1U)
+
+#define S_TDDP_CGEN    6
+#define V_TDDP_CGEN(x) ((x) << S_TDDP_CGEN)
+#define F_TDDP_CGEN    V_TDDP_CGEN(1U)
+
+#define S_ISCSI_CGEN    5
+#define V_ISCSI_CGEN(x) ((x) << S_ISCSI_CGEN)
+#define F_ISCSI_CGEN    V_ISCSI_CGEN(1U)
+
+#define S_RDMA_CGEN    4
+#define V_RDMA_CGEN(x) ((x) << S_RDMA_CGEN)
+#define F_RDMA_CGEN    V_RDMA_CGEN(1U)
+
+#define S_CHANNEL_CGEN    3
+#define V_CHANNEL_CGEN(x) ((x) << S_CHANNEL_CGEN)
+#define F_CHANNEL_CGEN    V_CHANNEL_CGEN(1U)
+
+#define S_ALL_DATAPATH_CGEN    2
+#define V_ALL_DATAPATH_CGEN(x) ((x) << S_ALL_DATAPATH_CGEN)
+#define F_ALL_DATAPATH_CGEN    V_ALL_DATAPATH_CGEN(1U)
+
+#define S_T10DIFF_DATAPATH_CGEN    1
+#define V_T10DIFF_DATAPATH_CGEN(x) ((x) << S_T10DIFF_DATAPATH_CGEN)
+#define F_T10DIFF_DATAPATH_CGEN    V_T10DIFF_DATAPATH_CGEN(1U)
+
+#define S_RDMA_DATAPATH_CGEN    0
+#define V_RDMA_DATAPATH_CGEN(x) ((x) << S_RDMA_DATAPATH_CGEN)
+#define F_RDMA_DATAPATH_CGEN    V_RDMA_DATAPATH_CGEN(1U)
+
+#define A_ULP_RX_CH1_CGEN 0x19264
+#define A_ULP_RX_RFE_DISABLE 0x19268
+
+#define S_RQE_LIM_CHECK_RFE_DISABLE    0
+#define V_RQE_LIM_CHECK_RFE_DISABLE(x) ((x) << S_RQE_LIM_CHECK_RFE_DISABLE)
+#define F_RQE_LIM_CHECK_RFE_DISABLE    V_RQE_LIM_CHECK_RFE_DISABLE(1U)
+
+#define A_ULP_RX_INT_ENABLE_2 0x1926c
+
+#define S_ULPRX2MA_INTFPERR    8
+#define V_ULPRX2MA_INTFPERR(x) ((x) << S_ULPRX2MA_INTFPERR)
+#define F_ULPRX2MA_INTFPERR    V_ULPRX2MA_INTFPERR(1U)
+
+#define S_ALN_SDC_ERR_1    7
+#define V_ALN_SDC_ERR_1(x) ((x) << S_ALN_SDC_ERR_1)
+#define F_ALN_SDC_ERR_1    V_ALN_SDC_ERR_1(1U)
+
+#define S_ALN_SDC_ERR_0    6
+#define V_ALN_SDC_ERR_0(x) ((x) << S_ALN_SDC_ERR_0)
+#define F_ALN_SDC_ERR_0    V_ALN_SDC_ERR_0(1U)
+
+#define S_PF_UNTAGGED_TPT_1    5
+#define V_PF_UNTAGGED_TPT_1(x) ((x) << S_PF_UNTAGGED_TPT_1)
+#define F_PF_UNTAGGED_TPT_1    V_PF_UNTAGGED_TPT_1(1U)
+
+#define S_PF_UNTAGGED_TPT_0    4
+#define V_PF_UNTAGGED_TPT_0(x) ((x) << S_PF_UNTAGGED_TPT_0)
+#define F_PF_UNTAGGED_TPT_0    V_PF_UNTAGGED_TPT_0(1U)
+
+#define S_PF_PBL_1    3
+#define V_PF_PBL_1(x) ((x) << S_PF_PBL_1)
+#define F_PF_PBL_1    V_PF_PBL_1(1U)
+
+#define S_PF_PBL_0    2
+#define V_PF_PBL_0(x) ((x) << S_PF_PBL_0)
+#define F_PF_PBL_0    V_PF_PBL_0(1U)
+
+#define S_DDP_HINT_1    1
+#define V_DDP_HINT_1(x) ((x) << S_DDP_HINT_1)
+#define F_DDP_HINT_1    V_DDP_HINT_1(1U)
+
+#define S_DDP_HINT_0    0
+#define V_DDP_HINT_0(x) ((x) << S_DDP_HINT_0)
+#define F_DDP_HINT_0    V_DDP_HINT_0(1U)
+
+#define A_ULP_RX_INT_CAUSE_2 0x19270
+#define A_ULP_RX_PERR_ENABLE_2 0x19274
+
+#define S_ENABLE_ULPRX2MA_INTFPERR    8
+#define V_ENABLE_ULPRX2MA_INTFPERR(x) ((x) << S_ENABLE_ULPRX2MA_INTFPERR)
+#define F_ENABLE_ULPRX2MA_INTFPERR    V_ENABLE_ULPRX2MA_INTFPERR(1U)
+
+#define S_ENABLE_ALN_SDC_ERR_1    7
+#define V_ENABLE_ALN_SDC_ERR_1(x) ((x) << S_ENABLE_ALN_SDC_ERR_1)
+#define F_ENABLE_ALN_SDC_ERR_1    V_ENABLE_ALN_SDC_ERR_1(1U)
+
+#define S_ENABLE_ALN_SDC_ERR_0    6
+#define V_ENABLE_ALN_SDC_ERR_0(x) ((x) << S_ENABLE_ALN_SDC_ERR_0)
+#define F_ENABLE_ALN_SDC_ERR_0    V_ENABLE_ALN_SDC_ERR_0(1U)
+
+#define S_ENABLE_PF_UNTAGGED_TPT_1    5
+#define V_ENABLE_PF_UNTAGGED_TPT_1(x) ((x) << S_ENABLE_PF_UNTAGGED_TPT_1)
+#define F_ENABLE_PF_UNTAGGED_TPT_1    V_ENABLE_PF_UNTAGGED_TPT_1(1U)
+
+#define S_ENABLE_PF_UNTAGGED_TPT_0    4
+#define V_ENABLE_PF_UNTAGGED_TPT_0(x) ((x) << S_ENABLE_PF_UNTAGGED_TPT_0)
+#define F_ENABLE_PF_UNTAGGED_TPT_0    V_ENABLE_PF_UNTAGGED_TPT_0(1U)
+
+#define S_ENABLE_PF_PBL_1    3
+#define V_ENABLE_PF_PBL_1(x) ((x) << S_ENABLE_PF_PBL_1)
+#define F_ENABLE_PF_PBL_1    V_ENABLE_PF_PBL_1(1U)
+
+#define S_ENABLE_PF_PBL_0    2
+#define V_ENABLE_PF_PBL_0(x) ((x) << S_ENABLE_PF_PBL_0)
+#define F_ENABLE_PF_PBL_0    V_ENABLE_PF_PBL_0(1U)
+
+#define S_ENABLE_DDP_HINT_1    1
+#define V_ENABLE_DDP_HINT_1(x) ((x) << S_ENABLE_DDP_HINT_1)
+#define F_ENABLE_DDP_HINT_1    V_ENABLE_DDP_HINT_1(1U)
+
+#define S_ENABLE_DDP_HINT_0    0
+#define V_ENABLE_DDP_HINT_0(x) ((x) << S_ENABLE_DDP_HINT_0)
+#define F_ENABLE_DDP_HINT_0    V_ENABLE_DDP_HINT_0(1U)
+
+#define A_ULP_RX_RQE_PBL_MULTIPLE_OUTSTANDING_CNT 0x19278
+
+#define S_PIO_RQE_PBL_MULTIPLE_CNT    0
+#define M_PIO_RQE_PBL_MULTIPLE_CNT    0xfU
+#define V_PIO_RQE_PBL_MULTIPLE_CNT(x) ((x) << S_PIO_RQE_PBL_MULTIPLE_CNT)
+#define G_PIO_RQE_PBL_MULTIPLE_CNT(x) (((x) >> S_PIO_RQE_PBL_MULTIPLE_CNT) & M_PIO_RQE_PBL_MULTIPLE_CNT)
+
+#define A_ULP_RX_ATOMIC_LEN 0x1927c
+
+#define S_ATOMIC_RPL_LEN    16
+#define M_ATOMIC_RPL_LEN    0xffU
+#define V_ATOMIC_RPL_LEN(x) ((x) << S_ATOMIC_RPL_LEN)
+#define G_ATOMIC_RPL_LEN(x) (((x) >> S_ATOMIC_RPL_LEN) & M_ATOMIC_RPL_LEN)
+
+#define S_ATOMIC_REQ_LEN    8
+#define M_ATOMIC_REQ_LEN    0xffU
+#define V_ATOMIC_REQ_LEN(x) ((x) << S_ATOMIC_REQ_LEN)
+#define G_ATOMIC_REQ_LEN(x) (((x) >> S_ATOMIC_REQ_LEN) & M_ATOMIC_REQ_LEN)
+
+#define S_ATOMIC_IMMEDIATE_LEN    0
+#define M_ATOMIC_IMMEDIATE_LEN    0xffU
+#define V_ATOMIC_IMMEDIATE_LEN(x) ((x) << S_ATOMIC_IMMEDIATE_LEN)
+#define G_ATOMIC_IMMEDIATE_LEN(x) (((x) >> S_ATOMIC_IMMEDIATE_LEN) & M_ATOMIC_IMMEDIATE_LEN)
+
+#define A_ULP_RX_CGEN_GLOBAL 0x19280
+#define A_ULP_RX_CTX_SKIP_MA_REQ 0x19284
+
+#define S_CLEAR_CTX_ERR_CNT1    3
+#define V_CLEAR_CTX_ERR_CNT1(x) ((x) << S_CLEAR_CTX_ERR_CNT1)
+#define F_CLEAR_CTX_ERR_CNT1    V_CLEAR_CTX_ERR_CNT1(1U)
+
+#define S_CLEAR_CTX_ERR_CNT0    2
+#define V_CLEAR_CTX_ERR_CNT0(x) ((x) << S_CLEAR_CTX_ERR_CNT0)
+#define F_CLEAR_CTX_ERR_CNT0    V_CLEAR_CTX_ERR_CNT0(1U)
+
+#define S_SKIP_MA_REQ_EN1    1
+#define V_SKIP_MA_REQ_EN1(x) ((x) << S_SKIP_MA_REQ_EN1)
+#define F_SKIP_MA_REQ_EN1    V_SKIP_MA_REQ_EN1(1U)
+
+#define S_SKIP_MA_REQ_EN0    0
+#define V_SKIP_MA_REQ_EN0(x) ((x) << S_SKIP_MA_REQ_EN0)
+#define F_SKIP_MA_REQ_EN0    V_SKIP_MA_REQ_EN0(1U)
+
+#define A_ULP_RX_CHNL0_CTX_ERROR_COUNT_PER_TID 0x19288
+#define A_ULP_RX_CHNL1_CTX_ERROR_COUNT_PER_TID 0x1928c
+#define A_ULP_RX_MSN_CHECK_ENABLE 0x19290
+
+#define S_RD_OR_TERM_MSN_CHECK_ENABLE    2
+#define V_RD_OR_TERM_MSN_CHECK_ENABLE(x) ((x) << S_RD_OR_TERM_MSN_CHECK_ENABLE)
+#define F_RD_OR_TERM_MSN_CHECK_ENABLE    V_RD_OR_TERM_MSN_CHECK_ENABLE(1U)
+
+#define S_ATOMIC_OP_MSN_CHECK_ENABLE    1
+#define V_ATOMIC_OP_MSN_CHECK_ENABLE(x) ((x) << S_ATOMIC_OP_MSN_CHECK_ENABLE)
+#define F_ATOMIC_OP_MSN_CHECK_ENABLE    V_ATOMIC_OP_MSN_CHECK_ENABLE(1U)
+
+#define S_SEND_MSN_CHECK_ENABLE    0
+#define V_SEND_MSN_CHECK_ENABLE(x) ((x) << S_SEND_MSN_CHECK_ENABLE)
+#define F_SEND_MSN_CHECK_ENABLE    V_SEND_MSN_CHECK_ENABLE(1U)
+
+/* registers for module SF */
+#define SF_BASE_ADDR 0x193f8
+
+#define A_SF_DATA 0x193f8
+#define A_SF_OP 0x193fc
+
+#define S_SF_LOCK    4
+#define V_SF_LOCK(x) ((x) << S_SF_LOCK)
+#define F_SF_LOCK    V_SF_LOCK(1U)
+
+#define S_CONT    3
+#define V_CONT(x) ((x) << S_CONT)
+#define F_CONT    V_CONT(1U)
+
+#define S_BYTECNT    1
+#define M_BYTECNT    0x3U
+#define V_BYTECNT(x) ((x) << S_BYTECNT)
+#define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT)
+
+/* registers for module PL */
+#define PL_BASE_ADDR 0x19400
+
+#define A_PL_VF_WHOAMI 0x0
+
+#define S_PORTXMAP    24
+#define M_PORTXMAP    0x7U
+#define V_PORTXMAP(x) ((x) << S_PORTXMAP)
+#define G_PORTXMAP(x) (((x) >> S_PORTXMAP) & M_PORTXMAP)
+
+#define S_SOURCEBUS    16
+#define M_SOURCEBUS    0x3U
+#define V_SOURCEBUS(x) ((x) << S_SOURCEBUS)
+#define G_SOURCEBUS(x) (((x) >> S_SOURCEBUS) & M_SOURCEBUS)
+
+#define S_SOURCEPF    8
+#define M_SOURCEPF    0x7U
+#define V_SOURCEPF(x) ((x) << S_SOURCEPF)
+#define G_SOURCEPF(x) (((x) >> S_SOURCEPF) & M_SOURCEPF)
+
+#define S_ISVF    7
+#define V_ISVF(x) ((x) << S_ISVF)
+#define F_ISVF    V_ISVF(1U)
+
+#define S_VFID    0
+#define M_VFID    0x7fU
+#define V_VFID(x) ((x) << S_VFID)
+#define G_VFID(x) (((x) >> S_VFID) & M_VFID)
+
+#define A_PL_VF_REV 0x4
+
+#define S_CHIPID    4
+#define M_CHIPID    0xfU
+#define V_CHIPID(x) ((x) << S_CHIPID)
+#define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID)
+
+#define A_PL_VF_REVISION 0x8
+#define A_PL_PF_INT_CAUSE 0x3c0
+
+#define S_PFSW    3
+#define V_PFSW(x) ((x) << S_PFSW)
+#define F_PFSW    V_PFSW(1U)
+
+#define S_PFSGE    2
+#define V_PFSGE(x) ((x) << S_PFSGE)
+#define F_PFSGE    V_PFSGE(1U)
+
+#define S_PFCIM    1
+#define V_PFCIM(x) ((x) << S_PFCIM)
+#define F_PFCIM    V_PFCIM(1U)
+
+#define S_PFMPS    0
+#define V_PFMPS(x) ((x) << S_PFMPS)
+#define F_PFMPS    V_PFMPS(1U)
+
+#define A_PL_PF_INT_ENABLE 0x3c4
+#define A_PL_PF_CTL 0x3c8
+
+#define S_SWINT    0
+#define V_SWINT(x) ((x) << S_SWINT)
+#define F_SWINT    V_SWINT(1U)
+
+#define A_PL_WHOAMI 0x19400
+#define A_PL_PERR_CAUSE 0x19404
+
+#define S_UART    28
+#define V_UART(x) ((x) << S_UART)
+#define F_UART    V_UART(1U)
+
+#define S_ULP_TX    27
+#define V_ULP_TX(x) ((x) << S_ULP_TX)
+#define F_ULP_TX    V_ULP_TX(1U)
+
+#define S_SGE    26
+#define V_SGE(x) ((x) << S_SGE)
+#define F_SGE    V_SGE(1U)
+
+#define S_HMA    25
+#define V_HMA(x) ((x) << S_HMA)
+#define F_HMA    V_HMA(1U)
+
+#define S_CPL_SWITCH    24
+#define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH)
+#define F_CPL_SWITCH    V_CPL_SWITCH(1U)
+
+#define S_ULP_RX    23
+#define V_ULP_RX(x) ((x) << S_ULP_RX)
+#define F_ULP_RX    V_ULP_RX(1U)
+
+#define S_PM_RX    22
+#define V_PM_RX(x) ((x) << S_PM_RX)
+#define F_PM_RX    V_PM_RX(1U)
+
+#define S_PM_TX    21
+#define V_PM_TX(x) ((x) << S_PM_TX)
+#define F_PM_TX    V_PM_TX(1U)
+
+#define S_MA    20
+#define V_MA(x) ((x) << S_MA)
+#define F_MA    V_MA(1U)
+
+#define S_TP    19
+#define V_TP(x) ((x) << S_TP)
+#define F_TP    V_TP(1U)
+
+#define S_LE    18
+#define V_LE(x) ((x) << S_LE)
+#define F_LE    V_LE(1U)
+
+#define S_EDC1    17
+#define V_EDC1(x) ((x) << S_EDC1)
+#define F_EDC1    V_EDC1(1U)
+
+#define S_EDC0    16
+#define V_EDC0(x) ((x) << S_EDC0)
+#define F_EDC0    V_EDC0(1U)
+
+#define S_MC    15
+#define V_MC(x) ((x) << S_MC)
+#define F_MC    V_MC(1U)
+
+#define S_PCIE    14
+#define V_PCIE(x) ((x) << S_PCIE)
+#define F_PCIE    V_PCIE(1U)
+
+#define S_PMU    13
+#define V_PMU(x) ((x) << S_PMU)
+#define F_PMU    V_PMU(1U)
+
+#define S_XGMAC_KR1    12
+#define V_XGMAC_KR1(x) ((x) << S_XGMAC_KR1)
+#define F_XGMAC_KR1    V_XGMAC_KR1(1U)
+
+#define S_XGMAC_KR0    11
+#define V_XGMAC_KR0(x) ((x) << S_XGMAC_KR0)
+#define F_XGMAC_KR0    V_XGMAC_KR0(1U)
+
+#define S_XGMAC1    10
+#define V_XGMAC1(x) ((x) << S_XGMAC1)
+#define F_XGMAC1    V_XGMAC1(1U)
+
+#define S_XGMAC0    9
+#define V_XGMAC0(x) ((x) << S_XGMAC0)
+#define F_XGMAC0    V_XGMAC0(1U)
+
+#define S_SMB    8
+#define V_SMB(x) ((x) << S_SMB)
+#define F_SMB    V_SMB(1U)
+
+#define S_SF    7
+#define V_SF(x) ((x) << S_SF)
+#define F_SF    V_SF(1U)
+
+#define S_PL    6
+#define V_PL(x) ((x) << S_PL)
+#define F_PL    V_PL(1U)
+
+#define S_NCSI    5
+#define V_NCSI(x) ((x) << S_NCSI)
+#define F_NCSI    V_NCSI(1U)
+
+#define S_MPS    4
+#define V_MPS(x) ((x) << S_MPS)
+#define F_MPS    V_MPS(1U)
+
+#define S_MI    3
+#define V_MI(x) ((x) << S_MI)
+#define F_MI    V_MI(1U)
+
+#define S_DBG    2
+#define V_DBG(x) ((x) << S_DBG)
+#define F_DBG    V_DBG(1U)
+
+#define S_I2CM    1
+#define V_I2CM(x) ((x) << S_I2CM)
+#define F_I2CM    V_I2CM(1U)
+
+#define S_CIM    0
+#define V_CIM(x) ((x) << S_CIM)
+#define F_CIM    V_CIM(1U)
+
+#define S_MC1    31
+#define V_MC1(x) ((x) << S_MC1)
+#define F_MC1    V_MC1(1U)
+
+#define S_MC0    15
+#define V_MC0(x) ((x) << S_MC0)
+#define F_MC0    V_MC0(1U)
+
+#define S_ANYMAC    9
+#define V_ANYMAC(x) ((x) << S_ANYMAC)
+#define F_ANYMAC    V_ANYMAC(1U)
+
+#define A_PL_PERR_ENABLE 0x19408
+#define A_PL_INT_CAUSE 0x1940c
+
+#define S_FLR    30
+#define V_FLR(x) ((x) << S_FLR)
+#define F_FLR    V_FLR(1U)
+
+#define S_SW_CIM    29
+#define V_SW_CIM(x) ((x) << S_SW_CIM)
+#define F_SW_CIM    V_SW_CIM(1U)
+
+#define S_MAC3    12
+#define V_MAC3(x) ((x) << S_MAC3)
+#define F_MAC3    V_MAC3(1U)
+
+#define S_MAC2    11
+#define V_MAC2(x) ((x) << S_MAC2)
+#define F_MAC2    V_MAC2(1U)
+
+#define S_MAC1    10
+#define V_MAC1(x) ((x) << S_MAC1)
+#define F_MAC1    V_MAC1(1U)
+
+#define S_MAC0    9
+#define V_MAC0(x) ((x) << S_MAC0)
+#define F_MAC0    V_MAC0(1U)
+
+#define A_PL_INT_ENABLE 0x19410
+#define A_PL_INT_MAP0 0x19414
+
+#define S_MAPNCSI    16
+#define M_MAPNCSI    0x1ffU
+#define V_MAPNCSI(x) ((x) << S_MAPNCSI)
+#define G_MAPNCSI(x) (((x) >> S_MAPNCSI) & M_MAPNCSI)
+
+#define S_MAPDEFAULT    0
+#define M_MAPDEFAULT    0x1ffU
+#define V_MAPDEFAULT(x) ((x) << S_MAPDEFAULT)
+#define G_MAPDEFAULT(x) (((x) >> S_MAPDEFAULT) & M_MAPDEFAULT)
+
+#define A_PL_INT_MAP1 0x19418
+
+#define S_MAPXGMAC1    16
+#define M_MAPXGMAC1    0x1ffU
+#define V_MAPXGMAC1(x) ((x) << S_MAPXGMAC1)
+#define G_MAPXGMAC1(x) (((x) >> S_MAPXGMAC1) & M_MAPXGMAC1)
+
+#define S_MAPXGMAC0    0
+#define M_MAPXGMAC0    0x1ffU
+#define V_MAPXGMAC0(x) ((x) << S_MAPXGMAC0)
+#define G_MAPXGMAC0(x) (((x) >> S_MAPXGMAC0) & M_MAPXGMAC0)
+
+#define S_MAPMAC1    16
+#define M_MAPMAC1    0x1ffU
+#define V_MAPMAC1(x) ((x) << S_MAPMAC1)
+#define G_MAPMAC1(x) (((x) >> S_MAPMAC1) & M_MAPMAC1)
+
+#define S_MAPMAC0    0
+#define M_MAPMAC0    0x1ffU
+#define V_MAPMAC0(x) ((x) << S_MAPMAC0)
+#define G_MAPMAC0(x) (((x) >> S_MAPMAC0) & M_MAPMAC0)
+
+#define A_PL_INT_MAP2 0x1941c
+
+#define S_MAPXGMAC_KR1    16
+#define M_MAPXGMAC_KR1    0x1ffU
+#define V_MAPXGMAC_KR1(x) ((x) << S_MAPXGMAC_KR1)
+#define G_MAPXGMAC_KR1(x) (((x) >> S_MAPXGMAC_KR1) & M_MAPXGMAC_KR1)
+
+#define S_MAPXGMAC_KR0    0
+#define M_MAPXGMAC_KR0    0x1ffU
+#define V_MAPXGMAC_KR0(x) ((x) << S_MAPXGMAC_KR0)
+#define G_MAPXGMAC_KR0(x) (((x) >> S_MAPXGMAC_KR0) & M_MAPXGMAC_KR0)
+
+#define S_MAPMAC3    16
+#define M_MAPMAC3    0x1ffU
+#define V_MAPMAC3(x) ((x) << S_MAPMAC3)
+#define G_MAPMAC3(x) (((x) >> S_MAPMAC3) & M_MAPMAC3)
+
+#define S_MAPMAC2    0
+#define M_MAPMAC2    0x1ffU
+#define V_MAPMAC2(x) ((x) << S_MAPMAC2)
+#define G_MAPMAC2(x) (((x) >> S_MAPMAC2) & M_MAPMAC2)
+
+#define A_PL_INT_MAP3 0x19420
+
+#define S_MAPMI    16
+#define M_MAPMI    0x1ffU
+#define V_MAPMI(x) ((x) << S_MAPMI)
+#define G_MAPMI(x) (((x) >> S_MAPMI) & M_MAPMI)
+
+#define S_MAPSMB    0
+#define M_MAPSMB    0x1ffU
+#define V_MAPSMB(x) ((x) << S_MAPSMB)
+#define G_MAPSMB(x) (((x) >> S_MAPSMB) & M_MAPSMB)
+
+#define A_PL_INT_MAP4 0x19424
+
+#define S_MAPDBG    16
+#define M_MAPDBG    0x1ffU
+#define V_MAPDBG(x) ((x) << S_MAPDBG)
+#define G_MAPDBG(x) (((x) >> S_MAPDBG) & M_MAPDBG)
+
+#define S_MAPI2CM    0
+#define M_MAPI2CM    0x1ffU
+#define V_MAPI2CM(x) ((x) << S_MAPI2CM)
+#define G_MAPI2CM(x) (((x) >> S_MAPI2CM) & M_MAPI2CM)
+
+#define A_PL_RST 0x19428
+
+#define S_FATALPERREN    3
+#define V_FATALPERREN(x) ((x) << S_FATALPERREN)
+#define F_FATALPERREN    V_FATALPERREN(1U)
+
+#define S_SWINTCIM    2
+#define V_SWINTCIM(x) ((x) << S_SWINTCIM)
+#define F_SWINTCIM    V_SWINTCIM(1U)
+
+#define S_PIORST    1
+#define V_PIORST(x) ((x) << S_PIORST)
+#define F_PIORST    V_PIORST(1U)
+
+#define S_PIORSTMODE    0
+#define V_PIORSTMODE(x) ((x) << S_PIORSTMODE)
+#define F_PIORSTMODE    V_PIORSTMODE(1U)
+
+#define S_AUTOPCIEPAUSE    4
+#define V_AUTOPCIEPAUSE(x) ((x) << S_AUTOPCIEPAUSE)
+#define F_AUTOPCIEPAUSE    V_AUTOPCIEPAUSE(1U)
+
+#define A_PL_PL_PERR_INJECT 0x1942c
+
+#define S_PL_MEMSEL    1
+#define V_PL_MEMSEL(x) ((x) << S_PL_MEMSEL)
+#define F_PL_MEMSEL    V_PL_MEMSEL(1U)
+
+#define A_PL_PL_INT_CAUSE 0x19430
+
+#define S_PF_ENABLEERR    5
+#define V_PF_ENABLEERR(x) ((x) << S_PF_ENABLEERR)
+#define F_PF_ENABLEERR    V_PF_ENABLEERR(1U)
+
+#define S_FATALPERR    4
+#define V_FATALPERR(x) ((x) << S_FATALPERR)
+#define F_FATALPERR    V_FATALPERR(1U)
+
+#define S_INVALIDACCESS    3
+#define V_INVALIDACCESS(x) ((x) << S_INVALIDACCESS)
+#define F_INVALIDACCESS    V_INVALIDACCESS(1U)
+
+#define S_TIMEOUT    2
+#define V_TIMEOUT(x) ((x) << S_TIMEOUT)
+#define F_TIMEOUT    V_TIMEOUT(1U)
+
+#define S_PLERR    1
+#define V_PLERR(x) ((x) << S_PLERR)
+#define F_PLERR    V_PLERR(1U)
+
+#define S_PERRVFID    0
+#define V_PERRVFID(x) ((x) << S_PERRVFID)
+#define F_PERRVFID    V_PERRVFID(1U)
+
+#define S_PL_BUSPERR    6
+#define V_PL_BUSPERR(x) ((x) << S_PL_BUSPERR)
+#define F_PL_BUSPERR    V_PL_BUSPERR(1U)
+
+#define A_PL_PL_INT_ENABLE 0x19434
+#define A_PL_PL_PERR_ENABLE 0x19438
+#define A_PL_REV 0x1943c
+
+#define S_REV    0
+#define M_REV    0xfU
+#define V_REV(x) ((x) << S_REV)
+#define G_REV(x) (((x) >> S_REV) & M_REV)
+
+#define A_PL_PCIE_LINK 0x19440
+
+#define S_LN0_AESTAT    26
+#define M_LN0_AESTAT    0x7U
+#define V_LN0_AESTAT(x) ((x) << S_LN0_AESTAT)
+#define G_LN0_AESTAT(x) (((x) >> S_LN0_AESTAT) & M_LN0_AESTAT)
+
+#define S_LN0_AECMD    23
+#define M_LN0_AECMD    0x7U
+#define V_LN0_AECMD(x) ((x) << S_LN0_AECMD)
+#define G_LN0_AECMD(x) (((x) >> S_LN0_AECMD) & M_LN0_AECMD)
+
+#define S_PCIE_SPEED    8
+#define M_PCIE_SPEED    0x3U
+#define V_PCIE_SPEED(x) ((x) << S_PCIE_SPEED)
+#define G_PCIE_SPEED(x) (((x) >> S_PCIE_SPEED) & M_PCIE_SPEED)
+
+#define S_LTSSM    0
+#define M_LTSSM    0x3fU
+#define V_LTSSM(x) ((x) << S_LTSSM)
+#define G_LTSSM(x) (((x) >> S_LTSSM) & M_LTSSM)
+
+#define A_PL_PCIE_CTL_STAT 0x19444
+
+#define S_PCIE_STATUS    16
+#define M_PCIE_STATUS    0xffffU
+#define V_PCIE_STATUS(x) ((x) << S_PCIE_STATUS)
+#define G_PCIE_STATUS(x) (((x) >> S_PCIE_STATUS) & M_PCIE_STATUS)
+
+#define S_PCIE_CONTROL    0
+#define M_PCIE_CONTROL    0xffffU
+#define V_PCIE_CONTROL(x) ((x) << S_PCIE_CONTROL)
+#define G_PCIE_CONTROL(x) (((x) >> S_PCIE_CONTROL) & M_PCIE_CONTROL)
+
+#define A_PL_SEMAPHORE_CTL 0x1944c
+
+#define S_LOCKSTATUS    16
+#define M_LOCKSTATUS    0xffU
+#define V_LOCKSTATUS(x) ((x) << S_LOCKSTATUS)
+#define G_LOCKSTATUS(x) (((x) >> S_LOCKSTATUS) & M_LOCKSTATUS)
+
+#define S_OWNEROVERRIDE    8
+#define V_OWNEROVERRIDE(x) ((x) << S_OWNEROVERRIDE)
+#define F_OWNEROVERRIDE    V_OWNEROVERRIDE(1U)
+
+#define S_ENABLEPF    0
+#define M_ENABLEPF    0xffU
+#define V_ENABLEPF(x) ((x) << S_ENABLEPF)
+#define G_ENABLEPF(x) (((x) >> S_ENABLEPF) & M_ENABLEPF)
+
+#define A_PL_SEMAPHORE_LOCK 0x19450
+
+#define S_SEMLOCK    31
+#define V_SEMLOCK(x) ((x) << S_SEMLOCK)
+#define F_SEMLOCK    V_SEMLOCK(1U)
+
+#define S_SEMSRCBUS    3
+#define M_SEMSRCBUS    0x3U
+#define V_SEMSRCBUS(x) ((x) << S_SEMSRCBUS)
+#define G_SEMSRCBUS(x) (((x) >> S_SEMSRCBUS) & M_SEMSRCBUS)
+
+#define S_SEMSRCPF    0
+#define M_SEMSRCPF    0x7U
+#define V_SEMSRCPF(x) ((x) << S_SEMSRCPF)
+#define G_SEMSRCPF(x) (((x) >> S_SEMSRCPF) & M_SEMSRCPF)
+
+#define A_PL_PF_ENABLE 0x19470
+
+#define S_PF_ENABLE    0
+#define M_PF_ENABLE    0xffU
+#define V_PF_ENABLE(x) ((x) << S_PF_ENABLE)
+#define G_PF_ENABLE(x) (((x) >> S_PF_ENABLE) & M_PF_ENABLE)
+
+#define A_PL_PORTX_MAP 0x19474
+
+#define S_MAP7    28
+#define M_MAP7    0x7U
+#define V_MAP7(x) ((x) << S_MAP7)
+#define G_MAP7(x) (((x) >> S_MAP7) & M_MAP7)
+
+#define S_MAP6    24
+#define M_MAP6    0x7U
+#define V_MAP6(x) ((x) << S_MAP6)
+#define G_MAP6(x) (((x) >> S_MAP6) & M_MAP6)
+
+#define S_MAP5    20
+#define M_MAP5    0x7U
+#define V_MAP5(x) ((x) << S_MAP5)
+#define G_MAP5(x) (((x) >> S_MAP5) & M_MAP5)
+
+#define S_MAP4    16
+#define M_MAP4    0x7U
+#define V_MAP4(x) ((x) << S_MAP4)
+#define G_MAP4(x) (((x) >> S_MAP4) & M_MAP4)
+
+#define S_MAP3    12
+#define M_MAP3    0x7U
+#define V_MAP3(x) ((x) << S_MAP3)
+#define G_MAP3(x) (((x) >> S_MAP3) & M_MAP3)
+
+#define S_MAP2    8
+#define M_MAP2    0x7U
+#define V_MAP2(x) ((x) << S_MAP2)
+#define G_MAP2(x) (((x) >> S_MAP2) & M_MAP2)
+
+#define S_MAP1    4
+#define M_MAP1    0x7U
+#define V_MAP1(x) ((x) << S_MAP1)
+#define G_MAP1(x) (((x) >> S_MAP1) & M_MAP1)
+
+#define S_MAP0    0
+#define M_MAP0    0x7U
+#define V_MAP0(x) ((x) << S_MAP0)
+#define G_MAP0(x) (((x) >> S_MAP0) & M_MAP0)
+
+#define A_PL_VF_SLICE_L 0x19490
+
+#define S_LIMITADDR    16
+#define M_LIMITADDR    0x3ffU
+#define V_LIMITADDR(x) ((x) << S_LIMITADDR)
+#define G_LIMITADDR(x) (((x) >> S_LIMITADDR) & M_LIMITADDR)
+
+#define S_SLICEBASEADDR    0
+#define M_SLICEBASEADDR    0x3ffU
+#define V_SLICEBASEADDR(x) ((x) << S_SLICEBASEADDR)
+#define G_SLICEBASEADDR(x) (((x) >> S_SLICEBASEADDR) & M_SLICEBASEADDR)
+
+#define A_PL_VF_SLICE_H 0x19494
+
+#define S_MODINDX    16
+#define M_MODINDX    0x7U
+#define V_MODINDX(x) ((x) << S_MODINDX)
+#define G_MODINDX(x) (((x) >> S_MODINDX) & M_MODINDX)
+
+#define S_MODOFFSET    0
+#define M_MODOFFSET    0x3ffU
+#define V_MODOFFSET(x) ((x) << S_MODOFFSET)
+#define G_MODOFFSET(x) (((x) >> S_MODOFFSET) & M_MODOFFSET)
+
+#define A_PL_FLR_VF_STATUS 0x194d0
+#define A_PL_FLR_PF_STATUS 0x194e0
+
+#define S_FLR_PF    0
+#define M_FLR_PF    0xffU
+#define V_FLR_PF(x) ((x) << S_FLR_PF)
+#define G_FLR_PF(x) (((x) >> S_FLR_PF) & M_FLR_PF)
+
+#define A_PL_TIMEOUT_CTL 0x194f0
+
+#define S_PL_TIMEOUT    0
+#define M_PL_TIMEOUT    0xffffU
+#define V_PL_TIMEOUT(x) ((x) << S_PL_TIMEOUT)
+#define G_PL_TIMEOUT(x) (((x) >> S_PL_TIMEOUT) & M_PL_TIMEOUT)
+
+#define S_PERRCAPTURE    16
+#define V_PERRCAPTURE(x) ((x) << S_PERRCAPTURE)
+#define F_PERRCAPTURE    V_PERRCAPTURE(1U)
+
+#define A_PL_TIMEOUT_STATUS0 0x194f4
+
+#define S_PL_TOADDR    2
+#define M_PL_TOADDR    0xfffffffU
+#define V_PL_TOADDR(x) ((x) << S_PL_TOADDR)
+#define G_PL_TOADDR(x) (((x) >> S_PL_TOADDR) & M_PL_TOADDR)
+
+#define A_PL_TIMEOUT_STATUS1 0x194f8
+
+#define S_PL_TOVALID    31
+#define V_PL_TOVALID(x) ((x) << S_PL_TOVALID)
+#define F_PL_TOVALID    V_PL_TOVALID(1U)
+
+#define S_WRITE    22
+#define V_WRITE(x) ((x) << S_WRITE)
+#define F_WRITE    V_WRITE(1U)
+
+#define S_PL_TOBUS    20
+#define M_PL_TOBUS    0x3U
+#define V_PL_TOBUS(x) ((x) << S_PL_TOBUS)
+#define G_PL_TOBUS(x) (((x) >> S_PL_TOBUS) & M_PL_TOBUS)
+
+#define S_RGN    19
+#define V_RGN(x) ((x) << S_RGN)
+#define F_RGN    V_RGN(1U)
+
+#define S_PL_TOPF    16
+#define M_PL_TOPF    0x7U
+#define V_PL_TOPF(x) ((x) << S_PL_TOPF)
+#define G_PL_TOPF(x) (((x) >> S_PL_TOPF) & M_PL_TOPF)
+
+#define S_PL_TORID    0
+#define M_PL_TORID    0xffffU
+#define V_PL_TORID(x) ((x) << S_PL_TORID)
+#define G_PL_TORID(x) (((x) >> S_PL_TORID) & M_PL_TORID)
+
+#define S_VALIDPERR    30
+#define V_VALIDPERR(x) ((x) << S_VALIDPERR)
+#define F_VALIDPERR    V_VALIDPERR(1U)
+
+#define S_PL_TOVFID    0
+#define M_PL_TOVFID    0xffU
+#define V_PL_TOVFID(x) ((x) << S_PL_TOVFID)
+#define G_PL_TOVFID(x) (((x) >> S_PL_TOVFID) & M_PL_TOVFID)
+
+#define A_PL_VFID_MAP 0x19800
+
+#define S_VFID_VLD    7
+#define V_VFID_VLD(x) ((x) << S_VFID_VLD)
+#define F_VFID_VLD    V_VFID_VLD(1U)
+
+/* registers for module LE */
+#define LE_BASE_ADDR 0x19c00
+
+#define A_LE_BUF_CONFIG 0x19c00
+#define A_LE_DB_CONFIG 0x19c04
+
+#define S_TCAMCMDOVLAPEN    21
+#define V_TCAMCMDOVLAPEN(x) ((x) << S_TCAMCMDOVLAPEN)
+#define F_TCAMCMDOVLAPEN    V_TCAMCMDOVLAPEN(1U)
+
+#define S_HASHEN    20
+#define V_HASHEN(x) ((x) << S_HASHEN)
+#define F_HASHEN    V_HASHEN(1U)
+
+#define S_ASBOTHSRCHEN    18
+#define V_ASBOTHSRCHEN(x) ((x) << S_ASBOTHSRCHEN)
+#define F_ASBOTHSRCHEN    V_ASBOTHSRCHEN(1U)
+
+#define S_ASLIPCOMPEN    17
+#define V_ASLIPCOMPEN(x) ((x) << S_ASLIPCOMPEN)
+#define F_ASLIPCOMPEN    V_ASLIPCOMPEN(1U)
+
+#define S_BUILD    16
+#define V_BUILD(x) ((x) << S_BUILD)
+#define F_BUILD    V_BUILD(1U)
+
+#define S_FILTEREN    11
+#define V_FILTEREN(x) ((x) << S_FILTEREN)
+#define F_FILTEREN    V_FILTEREN(1U)
+
+#define S_SYNMODE    7
+#define M_SYNMODE    0x3U
+#define V_SYNMODE(x) ((x) << S_SYNMODE)
+#define G_SYNMODE(x) (((x) >> S_SYNMODE) & M_SYNMODE)
+
+#define S_LEBUSEN    5
+#define V_LEBUSEN(x) ((x) << S_LEBUSEN)
+#define F_LEBUSEN    V_LEBUSEN(1U)
+
+#define S_ELOOKDUMEN    4
+#define V_ELOOKDUMEN(x) ((x) << S_ELOOKDUMEN)
+#define F_ELOOKDUMEN    V_ELOOKDUMEN(1U)
+
+#define S_IPV4ONLYEN    3
+#define V_IPV4ONLYEN(x) ((x) << S_IPV4ONLYEN)
+#define F_IPV4ONLYEN    V_IPV4ONLYEN(1U)
+
+#define S_MOSTCMDOEN    2
+#define V_MOSTCMDOEN(x) ((x) << S_MOSTCMDOEN)
+#define F_MOSTCMDOEN    V_MOSTCMDOEN(1U)
+
+#define S_DELACTSYNOEN    1
+#define V_DELACTSYNOEN(x) ((x) << S_DELACTSYNOEN)
+#define F_DELACTSYNOEN    V_DELACTSYNOEN(1U)
+
+#define S_CMDOVERLAPDIS    0
+#define V_CMDOVERLAPDIS(x) ((x) << S_CMDOVERLAPDIS)
+#define F_CMDOVERLAPDIS    V_CMDOVERLAPDIS(1U)
+
+#define S_MASKCMDOLAPDIS    26
+#define V_MASKCMDOLAPDIS(x) ((x) << S_MASKCMDOLAPDIS)
+#define F_MASKCMDOLAPDIS    V_MASKCMDOLAPDIS(1U)
+
+#define S_IPV4HASHSIZEEN    25
+#define V_IPV4HASHSIZEEN(x) ((x) << S_IPV4HASHSIZEEN)
+#define F_IPV4HASHSIZEEN    V_IPV4HASHSIZEEN(1U)
+
+#define S_PROTOCOLMASKEN    24
+#define V_PROTOCOLMASKEN(x) ((x) << S_PROTOCOLMASKEN)
+#define F_PROTOCOLMASKEN    V_PROTOCOLMASKEN(1U)
+
+#define S_TUPLESIZEEN    23
+#define V_TUPLESIZEEN(x) ((x) << S_TUPLESIZEEN)
+#define F_TUPLESIZEEN    V_TUPLESIZEEN(1U)
+
+#define S_SRVRSRAMEN    22
+#define V_SRVRSRAMEN(x) ((x) << S_SRVRSRAMEN)
+#define F_SRVRSRAMEN    V_SRVRSRAMEN(1U)
+
+#define S_ASBOTHSRCHENPR    19
+#define V_ASBOTHSRCHENPR(x) ((x) << S_ASBOTHSRCHENPR)
+#define F_ASBOTHSRCHENPR    V_ASBOTHSRCHENPR(1U)
+
+#define S_POCLIPTID0    15
+#define V_POCLIPTID0(x) ((x) << S_POCLIPTID0)
+#define F_POCLIPTID0    V_POCLIPTID0(1U)
+
+#define S_TCAMARBOFF    14
+#define V_TCAMARBOFF(x) ((x) << S_TCAMARBOFF)
+#define F_TCAMARBOFF    V_TCAMARBOFF(1U)
+
+#define S_ACCNTFULLEN    13
+#define V_ACCNTFULLEN(x) ((x) << S_ACCNTFULLEN)
+#define F_ACCNTFULLEN    V_ACCNTFULLEN(1U)
+
+#define S_FILTERRWNOCLIP    12
+#define V_FILTERRWNOCLIP(x) ((x) << S_FILTERRWNOCLIP)
+#define F_FILTERRWNOCLIP    V_FILTERRWNOCLIP(1U)
+
+#define S_CRCHASH    10
+#define V_CRCHASH(x) ((x) << S_CRCHASH)
+#define F_CRCHASH    V_CRCHASH(1U)
+
+#define S_COMPTID    9
+#define V_COMPTID(x) ((x) << S_COMPTID)
+#define F_COMPTID    V_COMPTID(1U)
+
+#define S_SINGLETHREAD    6
+#define V_SINGLETHREAD(x) ((x) << S_SINGLETHREAD)
+#define F_SINGLETHREAD    V_SINGLETHREAD(1U)
+
+#define A_LE_MISC 0x19c08
+
+#define S_CMPUNVAIL    0
+#define M_CMPUNVAIL    0xfU
+#define V_CMPUNVAIL(x) ((x) << S_CMPUNVAIL)
+#define G_CMPUNVAIL(x) (((x) >> S_CMPUNVAIL) & M_CMPUNVAIL)
+
+#define S_SRAMDEEPSLEEP_STAT    11
+#define V_SRAMDEEPSLEEP_STAT(x) ((x) << S_SRAMDEEPSLEEP_STAT)
+#define F_SRAMDEEPSLEEP_STAT    V_SRAMDEEPSLEEP_STAT(1U)
+
+#define S_TCAMDEEPSLEEP1_STAT    10
+#define V_TCAMDEEPSLEEP1_STAT(x) ((x) << S_TCAMDEEPSLEEP1_STAT)
+#define F_TCAMDEEPSLEEP1_STAT    V_TCAMDEEPSLEEP1_STAT(1U)
+
+#define S_TCAMDEEPSLEEP0_STAT    9
+#define V_TCAMDEEPSLEEP0_STAT(x) ((x) << S_TCAMDEEPSLEEP0_STAT)
+#define F_TCAMDEEPSLEEP0_STAT    V_TCAMDEEPSLEEP0_STAT(1U)
+
+#define S_SRAMDEEPSLEEP    8
+#define V_SRAMDEEPSLEEP(x) ((x) << S_SRAMDEEPSLEEP)
+#define F_SRAMDEEPSLEEP    V_SRAMDEEPSLEEP(1U)
+
+#define S_TCAMDEEPSLEEP1    7
+#define V_TCAMDEEPSLEEP1(x) ((x) << S_TCAMDEEPSLEEP1)
+#define F_TCAMDEEPSLEEP1    V_TCAMDEEPSLEEP1(1U)
+
+#define S_TCAMDEEPSLEEP0    6
+#define V_TCAMDEEPSLEEP0(x) ((x) << S_TCAMDEEPSLEEP0)
+#define F_TCAMDEEPSLEEP0    V_TCAMDEEPSLEEP0(1U)
+
+#define S_SRVRAMCLKOFF    5
+#define V_SRVRAMCLKOFF(x) ((x) << S_SRVRAMCLKOFF)
+#define F_SRVRAMCLKOFF    V_SRVRAMCLKOFF(1U)
+
+#define S_HASHCLKOFF    4
+#define V_HASHCLKOFF(x) ((x) << S_HASHCLKOFF)
+#define F_HASHCLKOFF    V_HASHCLKOFF(1U)
+
+#define A_LE_DB_ROUTING_TABLE_INDEX 0x19c10
+
+#define S_RTINDX    7
+#define M_RTINDX    0x3fU
+#define V_RTINDX(x) ((x) << S_RTINDX)
+#define G_RTINDX(x) (((x) >> S_RTINDX) & M_RTINDX)
+
+#define A_LE_DB_FILTER_TABLE_INDEX 0x19c14
+
+#define S_FTINDX    7
+#define M_FTINDX    0x3fU
+#define V_FTINDX(x) ((x) << S_FTINDX)
+#define G_FTINDX(x) (((x) >> S_FTINDX) & M_FTINDX)
+
+#define A_LE_DB_SERVER_INDEX 0x19c18
+
+#define S_SRINDX    7
+#define M_SRINDX    0x3fU
+#define V_SRINDX(x) ((x) << S_SRINDX)
+#define G_SRINDX(x) (((x) >> S_SRINDX) & M_SRINDX)
+
+#define A_LE_DB_CLIP_TABLE_INDEX 0x19c1c
+
+#define S_CLIPTINDX    7
+#define M_CLIPTINDX    0x3fU
+#define V_CLIPTINDX(x) ((x) << S_CLIPTINDX)
+#define G_CLIPTINDX(x) (((x) >> S_CLIPTINDX) & M_CLIPTINDX)
+
+#define A_LE_DB_ACT_CNT_IPV4 0x19c20
+
+#define S_ACTCNTIPV4    0
+#define M_ACTCNTIPV4    0xfffffU
+#define V_ACTCNTIPV4(x) ((x) << S_ACTCNTIPV4)
+#define G_ACTCNTIPV4(x) (((x) >> S_ACTCNTIPV4) & M_ACTCNTIPV4)
+
+#define A_LE_DB_ACT_CNT_IPV6 0x19c24
+
+#define S_ACTCNTIPV6    0
+#define M_ACTCNTIPV6    0xfffffU
+#define V_ACTCNTIPV6(x) ((x) << S_ACTCNTIPV6)
+#define G_ACTCNTIPV6(x) (((x) >> S_ACTCNTIPV6) & M_ACTCNTIPV6)
+
+#define A_LE_DB_HASH_CONFIG 0x19c28
+
+#define S_HASHTIDSIZE    16
+#define M_HASHTIDSIZE    0x3fU
+#define V_HASHTIDSIZE(x) ((x) << S_HASHTIDSIZE)
+#define G_HASHTIDSIZE(x) (((x) >> S_HASHTIDSIZE) & M_HASHTIDSIZE)
+
+#define S_HASHSIZE    0
+#define M_HASHSIZE    0x3fU
+#define V_HASHSIZE(x) ((x) << S_HASHSIZE)
+#define G_HASHSIZE(x) (((x) >> S_HASHSIZE) & M_HASHSIZE)
+
+#define A_LE_DB_HASH_TABLE_BASE 0x19c2c
+#define A_LE_DB_HASH_TID_BASE 0x19c30
+#define A_LE_DB_SIZE 0x19c34
+#define A_LE_DB_INT_ENABLE 0x19c38
+
+#define S_MSGSEL    27
+#define M_MSGSEL    0x1fU
+#define V_MSGSEL(x) ((x) << S_MSGSEL)
+#define G_MSGSEL(x) (((x) >> S_MSGSEL) & M_MSGSEL)
+
+#define S_REQQPARERR    16
+#define V_REQQPARERR(x) ((x) << S_REQQPARERR)
+#define F_REQQPARERR    V_REQQPARERR(1U)
+
+#define S_UNKNOWNCMD    15
+#define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD)
+#define F_UNKNOWNCMD    V_UNKNOWNCMD(1U)
+
+#define S_DROPFILTERHIT    13
+#define V_DROPFILTERHIT(x) ((x) << S_DROPFILTERHIT)
+#define F_DROPFILTERHIT    V_DROPFILTERHIT(1U)
+
+#define S_FILTERHIT    12
+#define V_FILTERHIT(x) ((x) << S_FILTERHIT)
+#define F_FILTERHIT    V_FILTERHIT(1U)
+
+#define S_SYNCOOKIEOFF    11
+#define V_SYNCOOKIEOFF(x) ((x) << S_SYNCOOKIEOFF)
+#define F_SYNCOOKIEOFF    V_SYNCOOKIEOFF(1U)
+
+#define S_SYNCOOKIEBAD    10
+#define V_SYNCOOKIEBAD(x) ((x) << S_SYNCOOKIEBAD)
+#define F_SYNCOOKIEBAD    V_SYNCOOKIEBAD(1U)
+
+#define S_SYNCOOKIE    9
+#define V_SYNCOOKIE(x) ((x) << S_SYNCOOKIE)
+#define F_SYNCOOKIE    V_SYNCOOKIE(1U)
+
+#define S_NFASRCHFAIL    8
+#define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL)
+#define F_NFASRCHFAIL    V_NFASRCHFAIL(1U)
+
+#define S_ACTRGNFULL    7
+#define V_ACTRGNFULL(x) ((x) << S_ACTRGNFULL)
+#define F_ACTRGNFULL    V_ACTRGNFULL(1U)
+
+#define S_PARITYERR    6
+#define V_PARITYERR(x) ((x) << S_PARITYERR)
+#define F_PARITYERR    V_PARITYERR(1U)
+
+#define S_LIPMISS    5
+#define V_LIPMISS(x) ((x) << S_LIPMISS)
+#define F_LIPMISS    V_LIPMISS(1U)
+
+#define S_LIP0    4
+#define V_LIP0(x) ((x) << S_LIP0)
+#define F_LIP0    V_LIP0(1U)
+
+#define S_MISS    3
+#define V_MISS(x) ((x) << S_MISS)
+#define F_MISS    V_MISS(1U)
+
+#define S_ROUTINGHIT    2
+#define V_ROUTINGHIT(x) ((x) << S_ROUTINGHIT)
+#define F_ROUTINGHIT    V_ROUTINGHIT(1U)
+
+#define S_ACTIVEHIT    1
+#define V_ACTIVEHIT(x) ((x) << S_ACTIVEHIT)
+#define F_ACTIVEHIT    V_ACTIVEHIT(1U)
+
+#define S_SERVERHIT    0
+#define V_SERVERHIT(x) ((x) << S_SERVERHIT)
+#define F_SERVERHIT    V_SERVERHIT(1U)
+
+#define S_ACTCNTIPV6TZERO    21
+#define V_ACTCNTIPV6TZERO(x) ((x) << S_ACTCNTIPV6TZERO)
+#define F_ACTCNTIPV6TZERO    V_ACTCNTIPV6TZERO(1U)
+
+#define S_ACTCNTIPV4TZERO    20
+#define V_ACTCNTIPV4TZERO(x) ((x) << S_ACTCNTIPV4TZERO)
+#define F_ACTCNTIPV4TZERO    V_ACTCNTIPV4TZERO(1U)
+
+#define S_ACTCNTIPV6ZERO    19
+#define V_ACTCNTIPV6ZERO(x) ((x) << S_ACTCNTIPV6ZERO)
+#define F_ACTCNTIPV6ZERO    V_ACTCNTIPV6ZERO(1U)
+
+#define S_ACTCNTIPV4ZERO    18
+#define V_ACTCNTIPV4ZERO(x) ((x) << S_ACTCNTIPV4ZERO)
+#define F_ACTCNTIPV4ZERO    V_ACTCNTIPV4ZERO(1U)
+
+#define S_MARSPPARERR    17
+#define V_MARSPPARERR(x) ((x) << S_MARSPPARERR)
+#define F_MARSPPARERR    V_MARSPPARERR(1U)
+
+#define S_VFPARERR    14
+#define V_VFPARERR(x) ((x) << S_VFPARERR)
+#define F_VFPARERR    V_VFPARERR(1U)
+
+#define A_LE_DB_INT_CAUSE 0x19c3c
+#define A_LE_DB_INT_TID 0x19c40
+
+#define S_INTTID    0
+#define M_INTTID    0xfffffU
+#define V_INTTID(x) ((x) << S_INTTID)
+#define G_INTTID(x) (((x) >> S_INTTID) & M_INTTID)
+
+#define A_LE_DB_INT_PTID 0x19c44
+
+#define S_INTPTID    0
+#define M_INTPTID    0xfffffU
+#define V_INTPTID(x) ((x) << S_INTPTID)
+#define G_INTPTID(x) (((x) >> S_INTPTID) & M_INTPTID)
+
+#define A_LE_DB_INT_INDEX 0x19c48
+
+#define S_INTINDEX    0
+#define M_INTINDEX    0xfffffU
+#define V_INTINDEX(x) ((x) << S_INTINDEX)
+#define G_INTINDEX(x) (((x) >> S_INTINDEX) & M_INTINDEX)
+
+#define A_LE_DB_INT_CMD 0x19c4c
+
+#define S_INTCMD    0
+#define M_INTCMD    0xfU
+#define V_INTCMD(x) ((x) << S_INTCMD)
+#define G_INTCMD(x) (((x) >> S_INTCMD) & M_INTCMD)
+
+#define A_LE_DB_MASK_IPV4 0x19c50
+#define A_LE_T5_DB_MASK_IPV4 0x19c50
+#define A_LE_DB_ACT_CNT_IPV4_TCAM 0x19c94
+#define A_LE_DB_ACT_CNT_IPV6_TCAM 0x19c98
+#define A_LE_ACT_CNT_THRSH 0x19c9c
+
+#define S_ACT_CNT_THRSH    0
+#define M_ACT_CNT_THRSH    0x1fffffU
+#define V_ACT_CNT_THRSH(x) ((x) << S_ACT_CNT_THRSH)
+#define G_ACT_CNT_THRSH(x) (((x) >> S_ACT_CNT_THRSH) & M_ACT_CNT_THRSH)
+
+#define A_LE_DB_MASK_IPV6 0x19ca0
+#define A_LE_DB_REQ_RSP_CNT 0x19ce4
+
+#define S_RSPCNTLE    16
+#define M_RSPCNTLE    0xffffU
+#define V_RSPCNTLE(x) ((x) << S_RSPCNTLE)
+#define G_RSPCNTLE(x) (((x) >> S_RSPCNTLE) & M_RSPCNTLE)
+
+#define S_REQCNTLE    0
+#define M_REQCNTLE    0xffffU
+#define V_REQCNTLE(x) ((x) << S_REQCNTLE)
+#define G_REQCNTLE(x) (((x) >> S_REQCNTLE) & M_REQCNTLE)
+
+#define A_LE_DB_DBGI_CONFIG 0x19cf0
+
+#define S_DBGICMDPERR    31
+#define V_DBGICMDPERR(x) ((x) << S_DBGICMDPERR)
+#define F_DBGICMDPERR    V_DBGICMDPERR(1U)
+
+#define S_DBGICMDRANGE    22
+#define M_DBGICMDRANGE    0x7U
+#define V_DBGICMDRANGE(x) ((x) << S_DBGICMDRANGE)
+#define G_DBGICMDRANGE(x) (((x) >> S_DBGICMDRANGE) & M_DBGICMDRANGE)
+
+#define S_DBGICMDMSKTYPE    21
+#define V_DBGICMDMSKTYPE(x) ((x) << S_DBGICMDMSKTYPE)
+#define F_DBGICMDMSKTYPE    V_DBGICMDMSKTYPE(1U)
+
+#define S_DBGICMDSEARCH    20
+#define V_DBGICMDSEARCH(x) ((x) << S_DBGICMDSEARCH)
+#define F_DBGICMDSEARCH    V_DBGICMDSEARCH(1U)
+
+#define S_DBGICMDREAD    19
+#define V_DBGICMDREAD(x) ((x) << S_DBGICMDREAD)
+#define F_DBGICMDREAD    V_DBGICMDREAD(1U)
+
+#define S_DBGICMDLEARN    18
+#define V_DBGICMDLEARN(x) ((x) << S_DBGICMDLEARN)
+#define F_DBGICMDLEARN    V_DBGICMDLEARN(1U)
+
+#define S_DBGICMDERASE    17
+#define V_DBGICMDERASE(x) ((x) << S_DBGICMDERASE)
+#define F_DBGICMDERASE    V_DBGICMDERASE(1U)
+
+#define S_DBGICMDIPV6    16
+#define V_DBGICMDIPV6(x) ((x) << S_DBGICMDIPV6)
+#define F_DBGICMDIPV6    V_DBGICMDIPV6(1U)
+
+#define S_DBGICMDTYPE    13
+#define M_DBGICMDTYPE    0x7U
+#define V_DBGICMDTYPE(x) ((x) << S_DBGICMDTYPE)
+#define G_DBGICMDTYPE(x) (((x) >> S_DBGICMDTYPE) & M_DBGICMDTYPE)
+
+#define S_DBGICMDACKERR    12
+#define V_DBGICMDACKERR(x) ((x) << S_DBGICMDACKERR)
+#define F_DBGICMDACKERR    V_DBGICMDACKERR(1U)
+
+#define S_DBGICMDBUSY    3
+#define V_DBGICMDBUSY(x) ((x) << S_DBGICMDBUSY)
+#define F_DBGICMDBUSY    V_DBGICMDBUSY(1U)
+
+#define S_DBGICMDSTRT    2
+#define V_DBGICMDSTRT(x) ((x) << S_DBGICMDSTRT)
+#define F_DBGICMDSTRT    V_DBGICMDSTRT(1U)
+
+#define S_DBGICMDMODE    0
+#define M_DBGICMDMODE    0x3U
+#define V_DBGICMDMODE(x) ((x) << S_DBGICMDMODE)
+#define G_DBGICMDMODE(x) (((x) >> S_DBGICMDMODE) & M_DBGICMDMODE)
+
+#define A_LE_DB_DBGI_REQ_TCAM_CMD 0x19cf4
+
+#define S_DBGICMD    20
+#define M_DBGICMD    0xfU
+#define V_DBGICMD(x) ((x) << S_DBGICMD)
+#define G_DBGICMD(x) (((x) >> S_DBGICMD) & M_DBGICMD)
+
+#define S_DBGITINDEX    0
+#define M_DBGITINDEX    0xfffffU
+#define V_DBGITINDEX(x) ((x) << S_DBGITINDEX)
+#define G_DBGITINDEX(x) (((x) >> S_DBGITINDEX) & M_DBGITINDEX)
+
+#define A_LE_PERR_ENABLE 0x19cf8
+
+#define S_REQQUEUE    1
+#define V_REQQUEUE(x) ((x) << S_REQQUEUE)
+#define F_REQQUEUE    V_REQQUEUE(1U)
+
+#define S_TCAM    0
+#define V_TCAM(x) ((x) << S_TCAM)
+#define F_TCAM    V_TCAM(1U)
+
+#define S_MARSPPARERRLE    17
+#define V_MARSPPARERRLE(x) ((x) << S_MARSPPARERRLE)
+#define F_MARSPPARERRLE    V_MARSPPARERRLE(1U)
+
+#define S_REQQUEUELE    16
+#define V_REQQUEUELE(x) ((x) << S_REQQUEUELE)
+#define F_REQQUEUELE    V_REQQUEUELE(1U)
+
+#define S_VFPARERRLE    14
+#define V_VFPARERRLE(x) ((x) << S_VFPARERRLE)
+#define F_VFPARERRLE    V_VFPARERRLE(1U)
+
+#define S_TCAMLE    6
+#define V_TCAMLE(x) ((x) << S_TCAMLE)
+#define F_TCAMLE    V_TCAMLE(1U)
+
+#define A_LE_SPARE 0x19cfc
+#define A_LE_DB_DBGI_REQ_DATA 0x19d00
+#define A_LE_DB_DBGI_REQ_MASK 0x19d50
+#define A_LE_DB_DBGI_RSP_STATUS 0x19d94
+
+#define S_DBGIRSPINDEX    12
+#define M_DBGIRSPINDEX    0xfffffU
+#define V_DBGIRSPINDEX(x) ((x) << S_DBGIRSPINDEX)
+#define G_DBGIRSPINDEX(x) (((x) >> S_DBGIRSPINDEX) & M_DBGIRSPINDEX)
+
+#define S_DBGIRSPMSG    8
+#define M_DBGIRSPMSG    0xfU
+#define V_DBGIRSPMSG(x) ((x) << S_DBGIRSPMSG)
+#define G_DBGIRSPMSG(x) (((x) >> S_DBGIRSPMSG) & M_DBGIRSPMSG)
+
+#define S_DBGIRSPMSGVLD    7
+#define V_DBGIRSPMSGVLD(x) ((x) << S_DBGIRSPMSGVLD)
+#define F_DBGIRSPMSGVLD    V_DBGIRSPMSGVLD(1U)
+
+#define S_DBGIRSPMHIT    2
+#define V_DBGIRSPMHIT(x) ((x) << S_DBGIRSPMHIT)
+#define F_DBGIRSPMHIT    V_DBGIRSPMHIT(1U)
+
+#define S_DBGIRSPHIT    1
+#define V_DBGIRSPHIT(x) ((x) << S_DBGIRSPHIT)
+#define F_DBGIRSPHIT    V_DBGIRSPHIT(1U)
+
+#define S_DBGIRSPVALID    0
+#define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID)
+#define F_DBGIRSPVALID    V_DBGIRSPVALID(1U)
+
+#define A_LE_DB_DBGI_RSP_DATA 0x19da0
+#define A_LE_DB_DBGI_RSP_LAST_CMD 0x19de4
+
+#define S_LASTCMDB    16
+#define M_LASTCMDB    0x7ffU
+#define V_LASTCMDB(x) ((x) << S_LASTCMDB)
+#define G_LASTCMDB(x) (((x) >> S_LASTCMDB) & M_LASTCMDB)
+
+#define S_LASTCMDA    0
+#define M_LASTCMDA    0x7ffU
+#define V_LASTCMDA(x) ((x) << S_LASTCMDA)
+#define G_LASTCMDA(x) (((x) >> S_LASTCMDA) & M_LASTCMDA)
+
+#define A_LE_DB_DROP_FILTER_ENTRY 0x19de8
+
+#define S_DROPFILTEREN    31
+#define V_DROPFILTEREN(x) ((x) << S_DROPFILTEREN)
+#define F_DROPFILTEREN    V_DROPFILTEREN(1U)
+
+#define S_DROPFILTERCLEAR    17
+#define V_DROPFILTERCLEAR(x) ((x) << S_DROPFILTERCLEAR)
+#define F_DROPFILTERCLEAR    V_DROPFILTERCLEAR(1U)
+
+#define S_DROPFILTERSET    16
+#define V_DROPFILTERSET(x) ((x) << S_DROPFILTERSET)
+#define F_DROPFILTERSET    V_DROPFILTERSET(1U)
+
+#define S_DROPFILTERFIDX    0
+#define M_DROPFILTERFIDX    0x1fffU
+#define V_DROPFILTERFIDX(x) ((x) << S_DROPFILTERFIDX)
+#define G_DROPFILTERFIDX(x) (((x) >> S_DROPFILTERFIDX) & M_DROPFILTERFIDX)
+
+#define A_LE_DB_PTID_SVRBASE 0x19df0
+
+#define S_SVRBASE_ADDR    2
+#define M_SVRBASE_ADDR    0x3ffffU
+#define V_SVRBASE_ADDR(x) ((x) << S_SVRBASE_ADDR)
+#define G_SVRBASE_ADDR(x) (((x) >> S_SVRBASE_ADDR) & M_SVRBASE_ADDR)
+
+#define A_LE_DB_FTID_FLTRBASE 0x19df4
+
+#define S_FLTRBASE_ADDR    2
+#define M_FLTRBASE_ADDR    0x3ffffU
+#define V_FLTRBASE_ADDR(x) ((x) << S_FLTRBASE_ADDR)
+#define G_FLTRBASE_ADDR(x) (((x) >> S_FLTRBASE_ADDR) & M_FLTRBASE_ADDR)
+
+#define A_LE_DB_TID_HASHBASE 0x19df8
+
+#define S_HASHBASE_ADDR    2
+#define M_HASHBASE_ADDR    0xfffffU
+#define V_HASHBASE_ADDR(x) ((x) << S_HASHBASE_ADDR)
+#define G_HASHBASE_ADDR(x) (((x) >> S_HASHBASE_ADDR) & M_HASHBASE_ADDR)
+
+#define A_LE_PERR_INJECT 0x19dfc
+
+#define S_LEMEMSEL    1
+#define M_LEMEMSEL    0x7U
+#define V_LEMEMSEL(x) ((x) << S_LEMEMSEL)
+#define G_LEMEMSEL(x) (((x) >> S_LEMEMSEL) & M_LEMEMSEL)
+
+#define A_LE_DB_ACTIVE_MASK_IPV4 0x19e00
+#define A_LE_T5_DB_ACTIVE_MASK_IPV4 0x19e00
+#define A_LE_DB_ACTIVE_MASK_IPV6 0x19e50
+#define A_LE_HASH_MASK_GEN_IPV4 0x19ea0
+#define A_LE_HASH_MASK_GEN_IPV4T5 0x19ea0
+#define A_LE_HASH_MASK_GEN_IPV6 0x19eb0
+#define A_LE_HASH_MASK_GEN_IPV6T5 0x19eb4
+#define A_LE_HASH_MASK_CMP_IPV4 0x19ee0
+#define A_LE_HASH_MASK_CMP_IPV4T5 0x19ee4
+#define A_LE_HASH_MASK_CMP_IPV6 0x19ef0
+#define A_LE_HASH_MASK_CMP_IPV6T5 0x19ef8
+#define A_LE_DEBUG_LA_CONFIG 0x19f20
+#define A_LE_REQ_DEBUG_LA_DATA 0x19f24
+#define A_LE_REQ_DEBUG_LA_WRPTR 0x19f28
+#define A_LE_RSP_DEBUG_LA_DATA 0x19f2c
+#define A_LE_RSP_DEBUG_LA_WRPTR 0x19f30
+#define A_LE_DEBUG_LA_SELECTOR 0x19f34
+#define A_LE_SRVR_SRAM_INIT 0x19f34
+
+#define S_SRVRSRAMBASE    2
+#define M_SRVRSRAMBASE    0xfffffU
+#define V_SRVRSRAMBASE(x) ((x) << S_SRVRSRAMBASE)
+#define G_SRVRSRAMBASE(x) (((x) >> S_SRVRSRAMBASE) & M_SRVRSRAMBASE)
+
+#define S_SRVRINITBUSY    1
+#define V_SRVRINITBUSY(x) ((x) << S_SRVRINITBUSY)
+#define F_SRVRINITBUSY    V_SRVRINITBUSY(1U)
+
+#define S_SRVRINIT    0
+#define V_SRVRINIT(x) ((x) << S_SRVRINIT)
+#define F_SRVRINIT    V_SRVRINIT(1U)
+
+#define A_LE_DEBUG_LA_CAPTURED_DATA 0x19f38
+#define A_LE_SRVR_VF_SRCH_TABLE 0x19f38
+
+#define S_RDWR    21
+#define V_RDWR(x) ((x) << S_RDWR)
+#define F_RDWR    V_RDWR(1U)
+
+#define S_VFINDEX    14
+#define M_VFINDEX    0x7fU
+#define V_VFINDEX(x) ((x) << S_VFINDEX)
+#define G_VFINDEX(x) (((x) >> S_VFINDEX) & M_VFINDEX)
+
+#define S_SRCHHADDR    7
+#define M_SRCHHADDR    0x7fU
+#define V_SRCHHADDR(x) ((x) << S_SRCHHADDR)
+#define G_SRCHHADDR(x) (((x) >> S_SRCHHADDR) & M_SRCHHADDR)
+
+#define S_SRCHLADDR    0
+#define M_SRCHLADDR    0x7fU
+#define V_SRCHLADDR(x) ((x) << S_SRCHLADDR)
+#define G_SRCHLADDR(x) (((x) >> S_SRCHLADDR) & M_SRCHLADDR)
+
+#define A_LE_MA_DEBUG_LA_DATA 0x19f3c
+#define A_LE_RSP_DEBUG_LA_HASH_WRPTR 0x19f40
+#define A_LE_DB_SECOND_ACTIVE_MASK_IPV4 0x19f40
+#define A_LE_HASH_DEBUG_LA_DATA 0x19f44
+#define A_LE_RSP_DEBUG_LA_TCAM_WRPTR 0x19f48
+#define A_LE_TCAM_DEBUG_LA_DATA 0x19f4c
+#define A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 0x19f90
+#define A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 0x19fa4
+#define A_LE_HASH_COLLISION 0x19fc4
+#define A_LE_GLOBAL_COLLISION 0x19fc8
+#define A_LE_FULL_CNT_COLLISION 0x19fcc
+#define A_LE_DEBUG_LA_CONFIGT5 0x19fd0
+#define A_LE_REQ_DEBUG_LA_DATAT5 0x19fd4
+#define A_LE_REQ_DEBUG_LA_WRPTRT5 0x19fd8
+#define A_LE_RSP_DEBUG_LA_DATAT5 0x19fdc
+#define A_LE_RSP_DEBUG_LA_WRPTRT5 0x19fe0
+#define A_LE_DEBUG_LA_SEL_DATA 0x19fe4
+
+/* registers for module NCSI */
+#define NCSI_BASE_ADDR 0x1a000
+
+#define A_NCSI_PORT_CFGREG 0x1a000
+
+#define S_WIREEN    28
+#define M_WIREEN    0xfU
+#define V_WIREEN(x) ((x) << S_WIREEN)
+#define G_WIREEN(x) (((x) >> S_WIREEN) & M_WIREEN)
+
+#define S_STRP_CRC    24
+#define M_STRP_CRC    0xfU
+#define V_STRP_CRC(x) ((x) << S_STRP_CRC)
+#define G_STRP_CRC(x) (((x) >> S_STRP_CRC) & M_STRP_CRC)
+
+#define S_RX_HALT    22
+#define V_RX_HALT(x) ((x) << S_RX_HALT)
+#define F_RX_HALT    V_RX_HALT(1U)
+
+#define S_FLUSH_RX_FIFO    21
+#define V_FLUSH_RX_FIFO(x) ((x) << S_FLUSH_RX_FIFO)
+#define F_FLUSH_RX_FIFO    V_FLUSH_RX_FIFO(1U)
+
+#define S_HW_ARB_EN    20
+#define V_HW_ARB_EN(x) ((x) << S_HW_ARB_EN)
+#define F_HW_ARB_EN    V_HW_ARB_EN(1U)
+
+#define S_SOFT_PKG_SEL    19
+#define V_SOFT_PKG_SEL(x) ((x) << S_SOFT_PKG_SEL)
+#define F_SOFT_PKG_SEL    V_SOFT_PKG_SEL(1U)
+
+#define S_ERR_DISCARD_EN    18
+#define V_ERR_DISCARD_EN(x) ((x) << S_ERR_DISCARD_EN)
+#define F_ERR_DISCARD_EN    V_ERR_DISCARD_EN(1U)
+
+#define S_MAX_PKT_SIZE    4
+#define M_MAX_PKT_SIZE    0x3fffU
+#define V_MAX_PKT_SIZE(x) ((x) << S_MAX_PKT_SIZE)
+#define G_MAX_PKT_SIZE(x) (((x) >> S_MAX_PKT_SIZE) & M_MAX_PKT_SIZE)
+
+#define S_RX_BYTE_SWAP    3
+#define V_RX_BYTE_SWAP(x) ((x) << S_RX_BYTE_SWAP)
+#define F_RX_BYTE_SWAP    V_RX_BYTE_SWAP(1U)
+
+#define S_TX_BYTE_SWAP    2
+#define V_TX_BYTE_SWAP(x) ((x) << S_TX_BYTE_SWAP)
+#define F_TX_BYTE_SWAP    V_TX_BYTE_SWAP(1U)
+
+#define A_NCSI_RST_CTRL 0x1a004
+
+#define S_MAC_REF_RST    2
+#define V_MAC_REF_RST(x) ((x) << S_MAC_REF_RST)
+#define F_MAC_REF_RST    V_MAC_REF_RST(1U)
+
+#define S_MAC_RX_RST    1
+#define V_MAC_RX_RST(x) ((x) << S_MAC_RX_RST)
+#define F_MAC_RX_RST    V_MAC_RX_RST(1U)
+
+#define S_MAC_TX_RST    0
+#define V_MAC_TX_RST(x) ((x) << S_MAC_TX_RST)
+#define F_MAC_TX_RST    V_MAC_TX_RST(1U)
+
+#define A_NCSI_CH0_SADDR_LOW 0x1a010
+#define A_NCSI_CH0_SADDR_HIGH 0x1a014
+
+#define S_CHO_SADDR_EN    31
+#define V_CHO_SADDR_EN(x) ((x) << S_CHO_SADDR_EN)
+#define F_CHO_SADDR_EN    V_CHO_SADDR_EN(1U)
+
+#define S_CH0_SADDR_HIGH    0
+#define M_CH0_SADDR_HIGH    0xffffU
+#define V_CH0_SADDR_HIGH(x) ((x) << S_CH0_SADDR_HIGH)
+#define G_CH0_SADDR_HIGH(x) (((x) >> S_CH0_SADDR_HIGH) & M_CH0_SADDR_HIGH)
+
+#define A_NCSI_CH1_SADDR_LOW 0x1a018
+#define A_NCSI_CH1_SADDR_HIGH 0x1a01c
+
+#define S_CH1_SADDR_EN    31
+#define V_CH1_SADDR_EN(x) ((x) << S_CH1_SADDR_EN)
+#define F_CH1_SADDR_EN    V_CH1_SADDR_EN(1U)
+
+#define S_CH1_SADDR_HIGH    0
+#define M_CH1_SADDR_HIGH    0xffffU
+#define V_CH1_SADDR_HIGH(x) ((x) << S_CH1_SADDR_HIGH)
+#define G_CH1_SADDR_HIGH(x) (((x) >> S_CH1_SADDR_HIGH) & M_CH1_SADDR_HIGH)
+
+#define A_NCSI_CH2_SADDR_LOW 0x1a020
+#define A_NCSI_CH2_SADDR_HIGH 0x1a024
+
+#define S_CH2_SADDR_EN    31
+#define V_CH2_SADDR_EN(x) ((x) << S_CH2_SADDR_EN)
+#define F_CH2_SADDR_EN    V_CH2_SADDR_EN(1U)
+
+#define S_CH2_SADDR_HIGH    0
+#define M_CH2_SADDR_HIGH    0xffffU
+#define V_CH2_SADDR_HIGH(x) ((x) << S_CH2_SADDR_HIGH)
+#define G_CH2_SADDR_HIGH(x) (((x) >> S_CH2_SADDR_HIGH) & M_CH2_SADDR_HIGH)
+
+#define A_NCSI_CH3_SADDR_LOW 0x1a028
+#define A_NCSI_CH3_SADDR_HIGH 0x1a02c
+
+#define S_CH3_SADDR_EN    31
+#define V_CH3_SADDR_EN(x) ((x) << S_CH3_SADDR_EN)
+#define F_CH3_SADDR_EN    V_CH3_SADDR_EN(1U)
+
+#define S_CH3_SADDR_HIGH    0
+#define M_CH3_SADDR_HIGH    0xffffU
+#define V_CH3_SADDR_HIGH(x) ((x) << S_CH3_SADDR_HIGH)
+#define G_CH3_SADDR_HIGH(x) (((x) >> S_CH3_SADDR_HIGH) & M_CH3_SADDR_HIGH)
+
+#define A_NCSI_WORK_REQHDR_0 0x1a030
+#define A_NCSI_WORK_REQHDR_1 0x1a034
+#define A_NCSI_WORK_REQHDR_2 0x1a038
+#define A_NCSI_WORK_REQHDR_3 0x1a03c
+#define A_NCSI_MPS_HDR_LO 0x1a040
+#define A_NCSI_MPS_HDR_HI 0x1a044
+#define A_NCSI_CTL 0x1a048
+
+#define S_STRIP_OVLAN    3
+#define V_STRIP_OVLAN(x) ((x) << S_STRIP_OVLAN)
+#define F_STRIP_OVLAN    V_STRIP_OVLAN(1U)
+
+#define S_BMC_DROP_NON_BC    2
+#define V_BMC_DROP_NON_BC(x) ((x) << S_BMC_DROP_NON_BC)
+#define F_BMC_DROP_NON_BC    V_BMC_DROP_NON_BC(1U)
+
+#define S_BMC_RX_FWD_ALL    1
+#define V_BMC_RX_FWD_ALL(x) ((x) << S_BMC_RX_FWD_ALL)
+#define F_BMC_RX_FWD_ALL    V_BMC_RX_FWD_ALL(1U)
+
+#define S_FWD_BMC    0
+#define V_FWD_BMC(x) ((x) << S_FWD_BMC)
+#define F_FWD_BMC    V_FWD_BMC(1U)
+
+#define A_NCSI_NCSI_ETYPE 0x1a04c
+
+#define S_NCSI_ETHERTYPE    0
+#define M_NCSI_ETHERTYPE    0xffffU
+#define V_NCSI_ETHERTYPE(x) ((x) << S_NCSI_ETHERTYPE)
+#define G_NCSI_ETHERTYPE(x) (((x) >> S_NCSI_ETHERTYPE) & M_NCSI_ETHERTYPE)
+
+#define A_NCSI_RX_FIFO_CNT 0x1a050
+
+#define S_NCSI_RXFIFO_CNT    0
+#define M_NCSI_RXFIFO_CNT    0x7ffU
+#define V_NCSI_RXFIFO_CNT(x) ((x) << S_NCSI_RXFIFO_CNT)
+#define G_NCSI_RXFIFO_CNT(x) (((x) >> S_NCSI_RXFIFO_CNT) & M_NCSI_RXFIFO_CNT)
+
+#define A_NCSI_RX_ERR_CNT 0x1a054
+#define A_NCSI_RX_OF_CNT 0x1a058
+#define A_NCSI_RX_MS_CNT 0x1a05c
+#define A_NCSI_RX_IE_CNT 0x1a060
+#define A_NCSI_MPS_DEMUX_CNT 0x1a064
+
+#define S_MPS2CIM_CNT    16
+#define M_MPS2CIM_CNT    0x1ffU
+#define V_MPS2CIM_CNT(x) ((x) << S_MPS2CIM_CNT)
+#define G_MPS2CIM_CNT(x) (((x) >> S_MPS2CIM_CNT) & M_MPS2CIM_CNT)
+
+#define S_MPS2BMC_CNT    0
+#define M_MPS2BMC_CNT    0x1ffU
+#define V_MPS2BMC_CNT(x) ((x) << S_MPS2BMC_CNT)
+#define G_MPS2BMC_CNT(x) (((x) >> S_MPS2BMC_CNT) & M_MPS2BMC_CNT)
+
+#define A_NCSI_CIM_DEMUX_CNT 0x1a068
+
+#define S_CIM2MPS_CNT    16
+#define M_CIM2MPS_CNT    0x1ffU
+#define V_CIM2MPS_CNT(x) ((x) << S_CIM2MPS_CNT)
+#define G_CIM2MPS_CNT(x) (((x) >> S_CIM2MPS_CNT) & M_CIM2MPS_CNT)
+
+#define S_CIM2BMC_CNT    0
+#define M_CIM2BMC_CNT    0x1ffU
+#define V_CIM2BMC_CNT(x) ((x) << S_CIM2BMC_CNT)
+#define G_CIM2BMC_CNT(x) (((x) >> S_CIM2BMC_CNT) & M_CIM2BMC_CNT)
+
+#define A_NCSI_TX_FIFO_CNT 0x1a06c
+
+#define S_TX_FIFO_CNT    0
+#define M_TX_FIFO_CNT    0x3ffU
+#define V_TX_FIFO_CNT(x) ((x) << S_TX_FIFO_CNT)
+#define G_TX_FIFO_CNT(x) (((x) >> S_TX_FIFO_CNT) & M_TX_FIFO_CNT)
+
+#define A_NCSI_SE_CNT_CTL 0x1a0b0
+
+#define S_SE_CNT_CLR    0
+#define M_SE_CNT_CLR    0xfU
+#define V_SE_CNT_CLR(x) ((x) << S_SE_CNT_CLR)
+#define G_SE_CNT_CLR(x) (((x) >> S_SE_CNT_CLR) & M_SE_CNT_CLR)
+
+#define A_NCSI_SE_CNT_MPS 0x1a0b4
+
+#define S_NC2MPS_SOP_CNT    24
+#define M_NC2MPS_SOP_CNT    0xffU
+#define V_NC2MPS_SOP_CNT(x) ((x) << S_NC2MPS_SOP_CNT)
+#define G_NC2MPS_SOP_CNT(x) (((x) >> S_NC2MPS_SOP_CNT) & M_NC2MPS_SOP_CNT)
+
+#define S_NC2MPS_EOP_CNT    16
+#define M_NC2MPS_EOP_CNT    0x3fU
+#define V_NC2MPS_EOP_CNT(x) ((x) << S_NC2MPS_EOP_CNT)
+#define G_NC2MPS_EOP_CNT(x) (((x) >> S_NC2MPS_EOP_CNT) & M_NC2MPS_EOP_CNT)
+
+#define S_MPS2NC_SOP_CNT    8
+#define M_MPS2NC_SOP_CNT    0xffU
+#define V_MPS2NC_SOP_CNT(x) ((x) << S_MPS2NC_SOP_CNT)
+#define G_MPS2NC_SOP_CNT(x) (((x) >> S_MPS2NC_SOP_CNT) & M_MPS2NC_SOP_CNT)
+
+#define S_MPS2NC_EOP_CNT    0
+#define M_MPS2NC_EOP_CNT    0xffU
+#define V_MPS2NC_EOP_CNT(x) ((x) << S_MPS2NC_EOP_CNT)
+#define G_MPS2NC_EOP_CNT(x) (((x) >> S_MPS2NC_EOP_CNT) & M_MPS2NC_EOP_CNT)
+
+#define A_NCSI_SE_CNT_CIM 0x1a0b8
+
+#define S_NC2CIM_SOP_CNT    24
+#define M_NC2CIM_SOP_CNT    0xffU
+#define V_NC2CIM_SOP_CNT(x) ((x) << S_NC2CIM_SOP_CNT)
+#define G_NC2CIM_SOP_CNT(x) (((x) >> S_NC2CIM_SOP_CNT) & M_NC2CIM_SOP_CNT)
+
+#define S_NC2CIM_EOP_CNT    16
+#define M_NC2CIM_EOP_CNT    0x3fU
+#define V_NC2CIM_EOP_CNT(x) ((x) << S_NC2CIM_EOP_CNT)
+#define G_NC2CIM_EOP_CNT(x) (((x) >> S_NC2CIM_EOP_CNT) & M_NC2CIM_EOP_CNT)
+
+#define S_CIM2NC_SOP_CNT    8
+#define M_CIM2NC_SOP_CNT    0xffU
+#define V_CIM2NC_SOP_CNT(x) ((x) << S_CIM2NC_SOP_CNT)
+#define G_CIM2NC_SOP_CNT(x) (((x) >> S_CIM2NC_SOP_CNT) & M_CIM2NC_SOP_CNT)
+
+#define S_CIM2NC_EOP_CNT    0
+#define M_CIM2NC_EOP_CNT    0xffU
+#define V_CIM2NC_EOP_CNT(x) ((x) << S_CIM2NC_EOP_CNT)
+#define G_CIM2NC_EOP_CNT(x) (((x) >> S_CIM2NC_EOP_CNT) & M_CIM2NC_EOP_CNT)
+
+#define A_NCSI_BUS_DEBUG 0x1a0bc
+
+#define S_SOP_CNT_ERR    12
+#define M_SOP_CNT_ERR    0xfU
+#define V_SOP_CNT_ERR(x) ((x) << S_SOP_CNT_ERR)
+#define G_SOP_CNT_ERR(x) (((x) >> S_SOP_CNT_ERR) & M_SOP_CNT_ERR)
+
+#define S_BUS_STATE_MPS_OUT    6
+#define M_BUS_STATE_MPS_OUT    0x3U
+#define V_BUS_STATE_MPS_OUT(x) ((x) << S_BUS_STATE_MPS_OUT)
+#define G_BUS_STATE_MPS_OUT(x) (((x) >> S_BUS_STATE_MPS_OUT) & M_BUS_STATE_MPS_OUT)
+
+#define S_BUS_STATE_MPS_IN    4
+#define M_BUS_STATE_MPS_IN    0x3U
+#define V_BUS_STATE_MPS_IN(x) ((x) << S_BUS_STATE_MPS_IN)
+#define G_BUS_STATE_MPS_IN(x) (((x) >> S_BUS_STATE_MPS_IN) & M_BUS_STATE_MPS_IN)
+
+#define S_BUS_STATE_CIM_OUT    2
+#define M_BUS_STATE_CIM_OUT    0x3U
+#define V_BUS_STATE_CIM_OUT(x) ((x) << S_BUS_STATE_CIM_OUT)
+#define G_BUS_STATE_CIM_OUT(x) (((x) >> S_BUS_STATE_CIM_OUT) & M_BUS_STATE_CIM_OUT)
+
+#define S_BUS_STATE_CIM_IN    0
+#define M_BUS_STATE_CIM_IN    0x3U
+#define V_BUS_STATE_CIM_IN(x) ((x) << S_BUS_STATE_CIM_IN)
+#define G_BUS_STATE_CIM_IN(x) (((x) >> S_BUS_STATE_CIM_IN) & M_BUS_STATE_CIM_IN)
+
+#define A_NCSI_LA_RDPTR 0x1a0c0
+#define A_NCSI_LA_RDDATA 0x1a0c4
+#define A_NCSI_LA_WRPTR 0x1a0c8
+#define A_NCSI_LA_RESERVED 0x1a0cc
+#define A_NCSI_LA_CTL 0x1a0d0
+#define A_NCSI_INT_ENABLE 0x1a0d4
+
+#define S_CIM_DM_PRTY_ERR    8
+#define V_CIM_DM_PRTY_ERR(x) ((x) << S_CIM_DM_PRTY_ERR)
+#define F_CIM_DM_PRTY_ERR    V_CIM_DM_PRTY_ERR(1U)
+
+#define S_MPS_DM_PRTY_ERR    7
+#define V_MPS_DM_PRTY_ERR(x) ((x) << S_MPS_DM_PRTY_ERR)
+#define F_MPS_DM_PRTY_ERR    V_MPS_DM_PRTY_ERR(1U)
+
+#define S_TOKEN    6
+#define V_TOKEN(x) ((x) << S_TOKEN)
+#define F_TOKEN    V_TOKEN(1U)
+
+#define S_ARB_DONE    5
+#define V_ARB_DONE(x) ((x) << S_ARB_DONE)
+#define F_ARB_DONE    V_ARB_DONE(1U)
+
+#define S_ARB_STARTED    4
+#define V_ARB_STARTED(x) ((x) << S_ARB_STARTED)
+#define F_ARB_STARTED    V_ARB_STARTED(1U)
+
+#define S_WOL    3
+#define V_WOL(x) ((x) << S_WOL)
+#define F_WOL    V_WOL(1U)
+
+#define S_MACINT    2
+#define V_MACINT(x) ((x) << S_MACINT)
+#define F_MACINT    V_MACINT(1U)
+
+#define S_TXFIFO_PRTY_ERR    1
+#define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR)
+#define F_TXFIFO_PRTY_ERR    V_TXFIFO_PRTY_ERR(1U)
+
+#define S_RXFIFO_PRTY_ERR    0
+#define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR)
+#define F_RXFIFO_PRTY_ERR    V_RXFIFO_PRTY_ERR(1U)
+
+#define A_NCSI_INT_CAUSE 0x1a0d8
+#define A_NCSI_STATUS 0x1a0dc
+
+#define S_MASTER    1
+#define V_MASTER(x) ((x) << S_MASTER)
+#define F_MASTER    V_MASTER(1U)
+
+#define S_ARB_STATUS    0
+#define V_ARB_STATUS(x) ((x) << S_ARB_STATUS)
+#define F_ARB_STATUS    V_ARB_STATUS(1U)
+
+#define A_NCSI_PAUSE_CTRL 0x1a0e0
+
+#define S_FORCEPAUSE    0
+#define V_FORCEPAUSE(x) ((x) << S_FORCEPAUSE)
+#define F_FORCEPAUSE    V_FORCEPAUSE(1U)
+
+#define A_NCSI_PAUSE_TIMEOUT 0x1a0e4
+#define A_NCSI_PAUSE_WM 0x1a0ec
+
+#define S_PAUSEHWM    16
+#define M_PAUSEHWM    0x7ffU
+#define V_PAUSEHWM(x) ((x) << S_PAUSEHWM)
+#define G_PAUSEHWM(x) (((x) >> S_PAUSEHWM) & M_PAUSEHWM)
+
+#define S_PAUSELWM    0
+#define M_PAUSELWM    0x7ffU
+#define V_PAUSELWM(x) ((x) << S_PAUSELWM)
+#define G_PAUSELWM(x) (((x) >> S_PAUSELWM) & M_PAUSELWM)
+
+#define A_NCSI_DEBUG 0x1a0f0
+
+#define S_DEBUGSEL    0
+#define M_DEBUGSEL    0x3fU
+#define V_DEBUGSEL(x) ((x) << S_DEBUGSEL)
+#define G_DEBUGSEL(x) (((x) >> S_DEBUGSEL) & M_DEBUGSEL)
+
+#define S_TXFIFO_EMPTY    4
+#define V_TXFIFO_EMPTY(x) ((x) << S_TXFIFO_EMPTY)
+#define F_TXFIFO_EMPTY    V_TXFIFO_EMPTY(1U)
+
+#define S_TXFIFO_FULL    3
+#define V_TXFIFO_FULL(x) ((x) << S_TXFIFO_FULL)
+#define F_TXFIFO_FULL    V_TXFIFO_FULL(1U)
+
+#define S_PKG_ID    0
+#define M_PKG_ID    0x7U
+#define V_PKG_ID(x) ((x) << S_PKG_ID)
+#define G_PKG_ID(x) (((x) >> S_PKG_ID) & M_PKG_ID)
+
+#define A_NCSI_PERR_INJECT 0x1a0f4
+
+#define S_MCSIMELSEL    1
+#define V_MCSIMELSEL(x) ((x) << S_MCSIMELSEL)
+#define F_MCSIMELSEL    V_MCSIMELSEL(1U)
+
+#define A_NCSI_PERR_ENABLE 0x1a0f8
+#define A_NCSI_MACB_NETWORK_CTRL 0x1a100
+
+#define S_TXSNDZEROPAUSE    12
+#define V_TXSNDZEROPAUSE(x) ((x) << S_TXSNDZEROPAUSE)
+#define F_TXSNDZEROPAUSE    V_TXSNDZEROPAUSE(1U)
+
+#define S_TXSNDPAUSE    11
+#define V_TXSNDPAUSE(x) ((x) << S_TXSNDPAUSE)
+#define F_TXSNDPAUSE    V_TXSNDPAUSE(1U)
+
+#define S_TXSTOP    10
+#define V_TXSTOP(x) ((x) << S_TXSTOP)
+#define F_TXSTOP    V_TXSTOP(1U)
+
+#define S_TXSTART    9
+#define V_TXSTART(x) ((x) << S_TXSTART)
+#define F_TXSTART    V_TXSTART(1U)
+
+#define S_BACKPRESS    8
+#define V_BACKPRESS(x) ((x) << S_BACKPRESS)
+#define F_BACKPRESS    V_BACKPRESS(1U)
+
+#define S_STATWREN    7
+#define V_STATWREN(x) ((x) << S_STATWREN)
+#define F_STATWREN    V_STATWREN(1U)
+
+#define S_INCRSTAT    6
+#define V_INCRSTAT(x) ((x) << S_INCRSTAT)
+#define F_INCRSTAT    V_INCRSTAT(1U)
+
+#define S_CLEARSTAT    5
+#define V_CLEARSTAT(x) ((x) << S_CLEARSTAT)
+#define F_CLEARSTAT    V_CLEARSTAT(1U)
+
+#define S_ENMGMTPORT    4
+#define V_ENMGMTPORT(x) ((x) << S_ENMGMTPORT)
+#define F_ENMGMTPORT    V_ENMGMTPORT(1U)
+
+#define S_NCSITXEN    3
+#define V_NCSITXEN(x) ((x) << S_NCSITXEN)
+#define F_NCSITXEN    V_NCSITXEN(1U)
+
+#define S_NCSIRXEN    2
+#define V_NCSIRXEN(x) ((x) << S_NCSIRXEN)
+#define F_NCSIRXEN    V_NCSIRXEN(1U)
+
+#define S_LOOPLOCAL    1
+#define V_LOOPLOCAL(x) ((x) << S_LOOPLOCAL)
+#define F_LOOPLOCAL    V_LOOPLOCAL(1U)
+
+#define S_LOOPPHY    0
+#define V_LOOPPHY(x) ((x) << S_LOOPPHY)
+#define F_LOOPPHY    V_LOOPPHY(1U)
+
+#define A_NCSI_MACB_NETWORK_CFG 0x1a104
+
+#define S_PCLKDIV128    22
+#define V_PCLKDIV128(x) ((x) << S_PCLKDIV128)
+#define F_PCLKDIV128    V_PCLKDIV128(1U)
+
+#define S_COPYPAUSE    21
+#define V_COPYPAUSE(x) ((x) << S_COPYPAUSE)
+#define F_COPYPAUSE    V_COPYPAUSE(1U)
+
+#define S_NONSTDPREOK    20
+#define V_NONSTDPREOK(x) ((x) << S_NONSTDPREOK)
+#define F_NONSTDPREOK    V_NONSTDPREOK(1U)
+
+#define S_NOFCS    19
+#define V_NOFCS(x) ((x) << S_NOFCS)
+#define F_NOFCS    V_NOFCS(1U)
+
+#define S_RXENHALFDUP    18
+#define V_RXENHALFDUP(x) ((x) << S_RXENHALFDUP)
+#define F_RXENHALFDUP    V_RXENHALFDUP(1U)
+
+#define S_NOCOPYFCS    17
+#define V_NOCOPYFCS(x) ((x) << S_NOCOPYFCS)
+#define F_NOCOPYFCS    V_NOCOPYFCS(1U)
+
+#define S_LENCHKEN    16
+#define V_LENCHKEN(x) ((x) << S_LENCHKEN)
+#define F_LENCHKEN    V_LENCHKEN(1U)
+
+#define S_RXBUFOFFSET    14
+#define M_RXBUFOFFSET    0x3U
+#define V_RXBUFOFFSET(x) ((x) << S_RXBUFOFFSET)
+#define G_RXBUFOFFSET(x) (((x) >> S_RXBUFOFFSET) & M_RXBUFOFFSET)
+
+#define S_PAUSEEN    13
+#define V_PAUSEEN(x) ((x) << S_PAUSEEN)
+#define F_PAUSEEN    V_PAUSEEN(1U)
+
+#define S_RETRYTEST    12
+#define V_RETRYTEST(x) ((x) << S_RETRYTEST)
+#define F_RETRYTEST    V_RETRYTEST(1U)
+
+#define S_PCLKDIV    10
+#define M_PCLKDIV    0x3U
+#define V_PCLKDIV(x) ((x) << S_PCLKDIV)
+#define G_PCLKDIV(x) (((x) >> S_PCLKDIV) & M_PCLKDIV)
+
+#define S_EXTCLASS    9
+#define V_EXTCLASS(x) ((x) << S_EXTCLASS)
+#define F_EXTCLASS    V_EXTCLASS(1U)
+
+#define S_EN1536FRAME    8
+#define V_EN1536FRAME(x) ((x) << S_EN1536FRAME)
+#define F_EN1536FRAME    V_EN1536FRAME(1U)
+
+#define S_UCASTHASHEN    7
+#define V_UCASTHASHEN(x) ((x) << S_UCASTHASHEN)
+#define F_UCASTHASHEN    V_UCASTHASHEN(1U)
+
+#define S_MCASTHASHEN    6
+#define V_MCASTHASHEN(x) ((x) << S_MCASTHASHEN)
+#define F_MCASTHASHEN    V_MCASTHASHEN(1U)
+
+#define S_RXBCASTDIS    5
+#define V_RXBCASTDIS(x) ((x) << S_RXBCASTDIS)
+#define F_RXBCASTDIS    V_RXBCASTDIS(1U)
+
+#define S_NCSICOPYALLFRAMES    4
+#define V_NCSICOPYALLFRAMES(x) ((x) << S_NCSICOPYALLFRAMES)
+#define F_NCSICOPYALLFRAMES    V_NCSICOPYALLFRAMES(1U)
+
+#define S_JUMBOEN    3
+#define V_JUMBOEN(x) ((x) << S_JUMBOEN)
+#define F_JUMBOEN    V_JUMBOEN(1U)
+
+#define S_SEREN    2
+#define V_SEREN(x) ((x) << S_SEREN)
+#define F_SEREN    V_SEREN(1U)
+
+#define S_FULLDUPLEX    1
+#define V_FULLDUPLEX(x) ((x) << S_FULLDUPLEX)
+#define F_FULLDUPLEX    V_FULLDUPLEX(1U)
+
+#define S_SPEED    0
+#define V_SPEED(x) ((x) << S_SPEED)
+#define F_SPEED    V_SPEED(1U)
+
+#define A_NCSI_MACB_NETWORK_STATUS 0x1a108
+
+#define S_PHYMGMTSTATUS    2
+#define V_PHYMGMTSTATUS(x) ((x) << S_PHYMGMTSTATUS)
+#define F_PHYMGMTSTATUS    V_PHYMGMTSTATUS(1U)
+
+#define S_MDISTATUS    1
+#define V_MDISTATUS(x) ((x) << S_MDISTATUS)
+#define F_MDISTATUS    V_MDISTATUS(1U)
+
+#define S_LINKSTATUS    0
+#define V_LINKSTATUS(x) ((x) << S_LINKSTATUS)
+#define F_LINKSTATUS    V_LINKSTATUS(1U)
+
+#define A_NCSI_MACB_TX_STATUS 0x1a114
+
+#define S_UNDERRUNERR    6
+#define V_UNDERRUNERR(x) ((x) << S_UNDERRUNERR)
+#define F_UNDERRUNERR    V_UNDERRUNERR(1U)
+
+#define S_TXCOMPLETE    5
+#define V_TXCOMPLETE(x) ((x) << S_TXCOMPLETE)
+#define F_TXCOMPLETE    V_TXCOMPLETE(1U)
+
+#define S_BUFFEREXHAUSTED    4
+#define V_BUFFEREXHAUSTED(x) ((x) << S_BUFFEREXHAUSTED)
+#define F_BUFFEREXHAUSTED    V_BUFFEREXHAUSTED(1U)
+
+#define S_TXPROGRESS    3
+#define V_TXPROGRESS(x) ((x) << S_TXPROGRESS)
+#define F_TXPROGRESS    V_TXPROGRESS(1U)
+
+#define S_RETRYLIMIT    2
+#define V_RETRYLIMIT(x) ((x) << S_RETRYLIMIT)
+#define F_RETRYLIMIT    V_RETRYLIMIT(1U)
+
+#define S_COLEVENT    1
+#define V_COLEVENT(x) ((x) << S_COLEVENT)
+#define F_COLEVENT    V_COLEVENT(1U)
+
+#define S_USEDBITREAD    0
+#define V_USEDBITREAD(x) ((x) << S_USEDBITREAD)
+#define F_USEDBITREAD    V_USEDBITREAD(1U)
+
+#define A_NCSI_MACB_RX_BUF_QPTR 0x1a118
+
+#define S_RXBUFQPTR    2
+#define M_RXBUFQPTR    0x3fffffffU
+#define V_RXBUFQPTR(x) ((x) << S_RXBUFQPTR)
+#define G_RXBUFQPTR(x) (((x) >> S_RXBUFQPTR) & M_RXBUFQPTR)
+
+#define A_NCSI_MACB_TX_BUF_QPTR 0x1a11c
+
+#define S_TXBUFQPTR    2
+#define M_TXBUFQPTR    0x3fffffffU
+#define V_TXBUFQPTR(x) ((x) << S_TXBUFQPTR)
+#define G_TXBUFQPTR(x) (((x) >> S_TXBUFQPTR) & M_TXBUFQPTR)
+
+#define A_NCSI_MACB_RX_STATUS 0x1a120
+
+#define S_RXOVERRUNERR    2
+#define V_RXOVERRUNERR(x) ((x) << S_RXOVERRUNERR)
+#define F_RXOVERRUNERR    V_RXOVERRUNERR(1U)
+
+#define S_MACB_FRAMERCVD    1
+#define V_MACB_FRAMERCVD(x) ((x) << S_MACB_FRAMERCVD)
+#define F_MACB_FRAMERCVD    V_MACB_FRAMERCVD(1U)
+
+#define S_NORXBUF    0
+#define V_NORXBUF(x) ((x) << S_NORXBUF)
+#define F_NORXBUF    V_NORXBUF(1U)
+
+#define A_NCSI_MACB_INT_STATUS 0x1a124
+
+#define S_PAUSETIMEZERO    13
+#define V_PAUSETIMEZERO(x) ((x) << S_PAUSETIMEZERO)
+#define F_PAUSETIMEZERO    V_PAUSETIMEZERO(1U)
+
+#define S_PAUSERCVD    12
+#define V_PAUSERCVD(x) ((x) << S_PAUSERCVD)
+#define F_PAUSERCVD    V_PAUSERCVD(1U)
+
+#define S_HRESPNOTOK    11
+#define V_HRESPNOTOK(x) ((x) << S_HRESPNOTOK)
+#define F_HRESPNOTOK    V_HRESPNOTOK(1U)
+
+#define S_RXOVERRUN    10
+#define V_RXOVERRUN(x) ((x) << S_RXOVERRUN)
+#define F_RXOVERRUN    V_RXOVERRUN(1U)
+
+#define S_LINKCHANGE    9
+#define V_LINKCHANGE(x) ((x) << S_LINKCHANGE)
+#define F_LINKCHANGE    V_LINKCHANGE(1U)
+
+#define S_INT_TXCOMPLETE    7
+#define V_INT_TXCOMPLETE(x) ((x) << S_INT_TXCOMPLETE)
+#define F_INT_TXCOMPLETE    V_INT_TXCOMPLETE(1U)
+
+#define S_TXBUFERR    6
+#define V_TXBUFERR(x) ((x) << S_TXBUFERR)
+#define F_TXBUFERR    V_TXBUFERR(1U)
+
+#define S_RETRYLIMITERR    5
+#define V_RETRYLIMITERR(x) ((x) << S_RETRYLIMITERR)
+#define F_RETRYLIMITERR    V_RETRYLIMITERR(1U)
+
+#define S_TXBUFUNDERRUN    4
+#define V_TXBUFUNDERRUN(x) ((x) << S_TXBUFUNDERRUN)
+#define F_TXBUFUNDERRUN    V_TXBUFUNDERRUN(1U)
+
+#define S_TXUSEDBITREAD    3
+#define V_TXUSEDBITREAD(x) ((x) << S_TXUSEDBITREAD)
+#define F_TXUSEDBITREAD    V_TXUSEDBITREAD(1U)
+
+#define S_RXUSEDBITREAD    2
+#define V_RXUSEDBITREAD(x) ((x) << S_RXUSEDBITREAD)
+#define F_RXUSEDBITREAD    V_RXUSEDBITREAD(1U)
+
+#define S_RXCOMPLETE    1
+#define V_RXCOMPLETE(x) ((x) << S_RXCOMPLETE)
+#define F_RXCOMPLETE    V_RXCOMPLETE(1U)
+
+#define S_MGMTFRAMESENT    0
+#define V_MGMTFRAMESENT(x) ((x) << S_MGMTFRAMESENT)
+#define F_MGMTFRAMESENT    V_MGMTFRAMESENT(1U)
+
+#define A_NCSI_MACB_INT_EN 0x1a128
+#define A_NCSI_MACB_INT_DIS 0x1a12c
+#define A_NCSI_MACB_INT_MASK 0x1a130
+#define A_NCSI_MACB_PAUSE_TIME 0x1a138
+
+#define S_PAUSETIME    0
+#define M_PAUSETIME    0xffffU
+#define V_PAUSETIME(x) ((x) << S_PAUSETIME)
+#define G_PAUSETIME(x) (((x) >> S_PAUSETIME) & M_PAUSETIME)
+
+#define A_NCSI_MACB_PAUSE_FRAMES_RCVD 0x1a13c
+
+#define S_PAUSEFRRCVD    0
+#define M_PAUSEFRRCVD    0xffffU
+#define V_PAUSEFRRCVD(x) ((x) << S_PAUSEFRRCVD)
+#define G_PAUSEFRRCVD(x) (((x) >> S_PAUSEFRRCVD) & M_PAUSEFRRCVD)
+
+#define A_NCSI_MACB_TX_FRAMES_OK 0x1a140
+
+#define S_TXFRAMESOK    0
+#define M_TXFRAMESOK    0xffffffU
+#define V_TXFRAMESOK(x) ((x) << S_TXFRAMESOK)
+#define G_TXFRAMESOK(x) (((x) >> S_TXFRAMESOK) & M_TXFRAMESOK)
+
+#define A_NCSI_MACB_SINGLE_COL_FRAMES 0x1a144
+
+#define S_SINGLECOLTXFRAMES    0
+#define M_SINGLECOLTXFRAMES    0xffffU
+#define V_SINGLECOLTXFRAMES(x) ((x) << S_SINGLECOLTXFRAMES)
+#define G_SINGLECOLTXFRAMES(x) (((x) >> S_SINGLECOLTXFRAMES) & M_SINGLECOLTXFRAMES)
+
+#define A_NCSI_MACB_MUL_COL_FRAMES 0x1a148
+
+#define S_MULCOLTXFRAMES    0
+#define M_MULCOLTXFRAMES    0xffffU
+#define V_MULCOLTXFRAMES(x) ((x) << S_MULCOLTXFRAMES)
+#define G_MULCOLTXFRAMES(x) (((x) >> S_MULCOLTXFRAMES) & M_MULCOLTXFRAMES)
+
+#define A_NCSI_MACB_RX_FRAMES_OK 0x1a14c
+
+#define S_RXFRAMESOK    0
+#define M_RXFRAMESOK    0xffffffU
+#define V_RXFRAMESOK(x) ((x) << S_RXFRAMESOK)
+#define G_RXFRAMESOK(x) (((x) >> S_RXFRAMESOK) & M_RXFRAMESOK)
+
+#define A_NCSI_MACB_FCS_ERR 0x1a150
+
+#define S_RXFCSERR    0
+#define M_RXFCSERR    0xffU
+#define V_RXFCSERR(x) ((x) << S_RXFCSERR)
+#define G_RXFCSERR(x) (((x) >> S_RXFCSERR) & M_RXFCSERR)
+
+#define A_NCSI_MACB_ALIGN_ERR 0x1a154
+
+#define S_RXALIGNERR    0
+#define M_RXALIGNERR    0xffU
+#define V_RXALIGNERR(x) ((x) << S_RXALIGNERR)
+#define G_RXALIGNERR(x) (((x) >> S_RXALIGNERR) & M_RXALIGNERR)
+
+#define A_NCSI_MACB_DEF_TX_FRAMES 0x1a158
+
+#define S_TXDEFERREDFRAMES    0
+#define M_TXDEFERREDFRAMES    0xffffU
+#define V_TXDEFERREDFRAMES(x) ((x) << S_TXDEFERREDFRAMES)
+#define G_TXDEFERREDFRAMES(x) (((x) >> S_TXDEFERREDFRAMES) & M_TXDEFERREDFRAMES)
+
+#define A_NCSI_MACB_LATE_COL 0x1a15c
+
+#define S_LATECOLLISIONS    0
+#define M_LATECOLLISIONS    0xffffU
+#define V_LATECOLLISIONS(x) ((x) << S_LATECOLLISIONS)
+#define G_LATECOLLISIONS(x) (((x) >> S_LATECOLLISIONS) & M_LATECOLLISIONS)
+
+#define A_NCSI_MACB_EXCESSIVE_COL 0x1a160
+
+#define S_EXCESSIVECOLLISIONS    0
+#define M_EXCESSIVECOLLISIONS    0xffU
+#define V_EXCESSIVECOLLISIONS(x) ((x) << S_EXCESSIVECOLLISIONS)
+#define G_EXCESSIVECOLLISIONS(x) (((x) >> S_EXCESSIVECOLLISIONS) & M_EXCESSIVECOLLISIONS)
+
+#define A_NCSI_MACB_TX_UNDERRUN_ERR 0x1a164
+
+#define S_TXUNDERRUNERR    0
+#define M_TXUNDERRUNERR    0xffU
+#define V_TXUNDERRUNERR(x) ((x) << S_TXUNDERRUNERR)
+#define G_TXUNDERRUNERR(x) (((x) >> S_TXUNDERRUNERR) & M_TXUNDERRUNERR)
+
+#define A_NCSI_MACB_CARRIER_SENSE_ERR 0x1a168
+
+#define S_CARRIERSENSEERRS    0
+#define M_CARRIERSENSEERRS    0xffU
+#define V_CARRIERSENSEERRS(x) ((x) << S_CARRIERSENSEERRS)
+#define G_CARRIERSENSEERRS(x) (((x) >> S_CARRIERSENSEERRS) & M_CARRIERSENSEERRS)
+
+#define A_NCSI_MACB_RX_RESOURCE_ERR 0x1a16c
+
+#define S_RXRESOURCEERR    0
+#define M_RXRESOURCEERR    0xffffU
+#define V_RXRESOURCEERR(x) ((x) << S_RXRESOURCEERR)
+#define G_RXRESOURCEERR(x) (((x) >> S_RXRESOURCEERR) & M_RXRESOURCEERR)
+
+#define A_NCSI_MACB_RX_OVERRUN_ERR 0x1a170
+
+#define S_RXOVERRUNERRCNT    0
+#define M_RXOVERRUNERRCNT    0xffU
+#define V_RXOVERRUNERRCNT(x) ((x) << S_RXOVERRUNERRCNT)
+#define G_RXOVERRUNERRCNT(x) (((x) >> S_RXOVERRUNERRCNT) & M_RXOVERRUNERRCNT)
+
+#define A_NCSI_MACB_RX_SYMBOL_ERR 0x1a174
+
+#define S_RXSYMBOLERR    0
+#define M_RXSYMBOLERR    0xffU
+#define V_RXSYMBOLERR(x) ((x) << S_RXSYMBOLERR)
+#define G_RXSYMBOLERR(x) (((x) >> S_RXSYMBOLERR) & M_RXSYMBOLERR)
+
+#define A_NCSI_MACB_RX_OVERSIZE_FRAME 0x1a178
+
+#define S_RXOVERSIZEERR    0
+#define M_RXOVERSIZEERR    0xffU
+#define V_RXOVERSIZEERR(x) ((x) << S_RXOVERSIZEERR)
+#define G_RXOVERSIZEERR(x) (((x) >> S_RXOVERSIZEERR) & M_RXOVERSIZEERR)
+
+#define A_NCSI_MACB_RX_JABBER_ERR 0x1a17c
+
+#define S_RXJABBERERR    0
+#define M_RXJABBERERR    0xffU
+#define V_RXJABBERERR(x) ((x) << S_RXJABBERERR)
+#define G_RXJABBERERR(x) (((x) >> S_RXJABBERERR) & M_RXJABBERERR)
+
+#define A_NCSI_MACB_RX_UNDERSIZE_FRAME 0x1a180
+
+#define S_RXUNDERSIZEFR    0
+#define M_RXUNDERSIZEFR    0xffU
+#define V_RXUNDERSIZEFR(x) ((x) << S_RXUNDERSIZEFR)
+#define G_RXUNDERSIZEFR(x) (((x) >> S_RXUNDERSIZEFR) & M_RXUNDERSIZEFR)
+
+#define A_NCSI_MACB_SQE_TEST_ERR 0x1a184
+
+#define S_SQETESTERR    0
+#define M_SQETESTERR    0xffU
+#define V_SQETESTERR(x) ((x) << S_SQETESTERR)
+#define G_SQETESTERR(x) (((x) >> S_SQETESTERR) & M_SQETESTERR)
+
+#define A_NCSI_MACB_LENGTH_ERR 0x1a188
+
+#define S_LENGTHERR    0
+#define M_LENGTHERR    0xffU
+#define V_LENGTHERR(x) ((x) << S_LENGTHERR)
+#define G_LENGTHERR(x) (((x) >> S_LENGTHERR) & M_LENGTHERR)
+
+#define A_NCSI_MACB_TX_PAUSE_FRAMES 0x1a18c
+
+#define S_TXPAUSEFRAMES    0
+#define M_TXPAUSEFRAMES    0xffffU
+#define V_TXPAUSEFRAMES(x) ((x) << S_TXPAUSEFRAMES)
+#define G_TXPAUSEFRAMES(x) (((x) >> S_TXPAUSEFRAMES) & M_TXPAUSEFRAMES)
+
+#define A_NCSI_MACB_HASH_LOW 0x1a190
+#define A_NCSI_MACB_HASH_HIGH 0x1a194
+#define A_NCSI_MACB_SPECIFIC_1_LOW 0x1a198
+#define A_NCSI_MACB_SPECIFIC_1_HIGH 0x1a19c
+
+#define S_MATCHHIGH    0
+#define M_MATCHHIGH    0xffffU
+#define V_MATCHHIGH(x) ((x) << S_MATCHHIGH)
+#define G_MATCHHIGH(x) (((x) >> S_MATCHHIGH) & M_MATCHHIGH)
+
+#define A_NCSI_MACB_SPECIFIC_2_LOW 0x1a1a0
+#define A_NCSI_MACB_SPECIFIC_2_HIGH 0x1a1a4
+#define A_NCSI_MACB_SPECIFIC_3_LOW 0x1a1a8
+#define A_NCSI_MACB_SPECIFIC_3_HIGH 0x1a1ac
+#define A_NCSI_MACB_SPECIFIC_4_LOW 0x1a1b0
+#define A_NCSI_MACB_SPECIFIC_4_HIGH 0x1a1b4
+#define A_NCSI_MACB_TYPE_ID 0x1a1b8
+
+#define S_TYPEID    0
+#define M_TYPEID    0xffffU
+#define V_TYPEID(x) ((x) << S_TYPEID)
+#define G_TYPEID(x) (((x) >> S_TYPEID) & M_TYPEID)
+
+#define A_NCSI_MACB_TX_PAUSE_QUANTUM 0x1a1bc
+
+#define S_TXPAUSEQUANTUM    0
+#define M_TXPAUSEQUANTUM    0xffffU
+#define V_TXPAUSEQUANTUM(x) ((x) << S_TXPAUSEQUANTUM)
+#define G_TXPAUSEQUANTUM(x) (((x) >> S_TXPAUSEQUANTUM) & M_TXPAUSEQUANTUM)
+
+#define A_NCSI_MACB_USER_IO 0x1a1c0
+
+#define S_USERPROGINPUT    16
+#define M_USERPROGINPUT    0xffffU
+#define V_USERPROGINPUT(x) ((x) << S_USERPROGINPUT)
+#define G_USERPROGINPUT(x) (((x) >> S_USERPROGINPUT) & M_USERPROGINPUT)
+
+#define S_USERPROGOUTPUT    0
+#define M_USERPROGOUTPUT    0xffffU
+#define V_USERPROGOUTPUT(x) ((x) << S_USERPROGOUTPUT)
+#define G_USERPROGOUTPUT(x) (((x) >> S_USERPROGOUTPUT) & M_USERPROGOUTPUT)
+
+#define A_NCSI_MACB_WOL_CFG 0x1a1c4
+
+#define S_MCHASHEN    19
+#define V_MCHASHEN(x) ((x) << S_MCHASHEN)
+#define F_MCHASHEN    V_MCHASHEN(1U)
+
+#define S_SPECIFIC1EN    18
+#define V_SPECIFIC1EN(x) ((x) << S_SPECIFIC1EN)
+#define F_SPECIFIC1EN    V_SPECIFIC1EN(1U)
+
+#define S_ARPEN    17
+#define V_ARPEN(x) ((x) << S_ARPEN)
+#define F_ARPEN    V_ARPEN(1U)
+
+#define S_MAGICPKTEN    16
+#define V_MAGICPKTEN(x) ((x) << S_MAGICPKTEN)
+#define F_MAGICPKTEN    V_MAGICPKTEN(1U)
+
+#define S_ARPIPADDR    0
+#define M_ARPIPADDR    0xffffU
+#define V_ARPIPADDR(x) ((x) << S_ARPIPADDR)
+#define G_ARPIPADDR(x) (((x) >> S_ARPIPADDR) & M_ARPIPADDR)
+
+#define A_NCSI_MACB_REV_STATUS 0x1a1fc
+
+#define S_PARTREF    16
+#define M_PARTREF    0xffffU
+#define V_PARTREF(x) ((x) << S_PARTREF)
+#define G_PARTREF(x) (((x) >> S_PARTREF) & M_PARTREF)
+
+#define S_DESREV    0
+#define M_DESREV    0xffffU
+#define V_DESREV(x) ((x) << S_DESREV)
+#define G_DESREV(x) (((x) >> S_DESREV) & M_DESREV)
+
+/* registers for module XGMAC */
+#define XGMAC_BASE_ADDR 0x0
+
+#define A_XGMAC_PORT_CFG 0x1000
+
+#define S_XGMII_CLK_SEL    29
+#define M_XGMII_CLK_SEL    0x7U
+#define V_XGMII_CLK_SEL(x) ((x) << S_XGMII_CLK_SEL)
+#define G_XGMII_CLK_SEL(x) (((x) >> S_XGMII_CLK_SEL) & M_XGMII_CLK_SEL)
+
+#define S_SINKTX    27
+#define V_SINKTX(x) ((x) << S_SINKTX)
+#define F_SINKTX    V_SINKTX(1U)
+
+#define S_SINKTXONLINKDOWN    26
+#define V_SINKTXONLINKDOWN(x) ((x) << S_SINKTXONLINKDOWN)
+#define F_SINKTXONLINKDOWN    V_SINKTXONLINKDOWN(1U)
+
+#define S_XG2G_SPEED_MODE    25
+#define V_XG2G_SPEED_MODE(x) ((x) << S_XG2G_SPEED_MODE)
+#define F_XG2G_SPEED_MODE    V_XG2G_SPEED_MODE(1U)
+
+#define S_LOOPNOFWD    24
+#define V_LOOPNOFWD(x) ((x) << S_LOOPNOFWD)
+#define F_LOOPNOFWD    V_LOOPNOFWD(1U)
+
+#define S_XGM_TX_PAUSE_SIZE    23
+#define V_XGM_TX_PAUSE_SIZE(x) ((x) << S_XGM_TX_PAUSE_SIZE)
+#define F_XGM_TX_PAUSE_SIZE    V_XGM_TX_PAUSE_SIZE(1U)
+
+#define S_XGM_TX_PAUSE_FRAME    22
+#define V_XGM_TX_PAUSE_FRAME(x) ((x) << S_XGM_TX_PAUSE_FRAME)
+#define F_XGM_TX_PAUSE_FRAME    V_XGM_TX_PAUSE_FRAME(1U)
+
+#define S_XGM_TX_DISABLE_PRE    21
+#define V_XGM_TX_DISABLE_PRE(x) ((x) << S_XGM_TX_DISABLE_PRE)
+#define F_XGM_TX_DISABLE_PRE    V_XGM_TX_DISABLE_PRE(1U)
+
+#define S_XGM_TX_DISABLE_CRC    20
+#define V_XGM_TX_DISABLE_CRC(x) ((x) << S_XGM_TX_DISABLE_CRC)
+#define F_XGM_TX_DISABLE_CRC    V_XGM_TX_DISABLE_CRC(1U)
+
+#define S_SMUX_RX_LOOP    19
+#define V_SMUX_RX_LOOP(x) ((x) << S_SMUX_RX_LOOP)
+#define F_SMUX_RX_LOOP    V_SMUX_RX_LOOP(1U)
+
+#define S_RX_LANE_SWAP    18
+#define V_RX_LANE_SWAP(x) ((x) << S_RX_LANE_SWAP)
+#define F_RX_LANE_SWAP    V_RX_LANE_SWAP(1U)
+
+#define S_TX_LANE_SWAP    17
+#define V_TX_LANE_SWAP(x) ((x) << S_TX_LANE_SWAP)
+#define F_TX_LANE_SWAP    V_TX_LANE_SWAP(1U)
+
+#define S_SIGNAL_DET    14
+#define V_SIGNAL_DET(x) ((x) << S_SIGNAL_DET)
+#define F_SIGNAL_DET    V_SIGNAL_DET(1U)
+
+#define S_PMUX_RX_LOOP    13
+#define V_PMUX_RX_LOOP(x) ((x) << S_PMUX_RX_LOOP)
+#define F_PMUX_RX_LOOP    V_PMUX_RX_LOOP(1U)
+
+#define S_PMUX_TX_LOOP    12
+#define V_PMUX_TX_LOOP(x) ((x) << S_PMUX_TX_LOOP)
+#define F_PMUX_TX_LOOP    V_PMUX_TX_LOOP(1U)
+
+#define S_XGM_RX_SEL    10
+#define M_XGM_RX_SEL    0x3U
+#define V_XGM_RX_SEL(x) ((x) << S_XGM_RX_SEL)
+#define G_XGM_RX_SEL(x) (((x) >> S_XGM_RX_SEL) & M_XGM_RX_SEL)
+
+#define S_PCS_TX_SEL    8
+#define M_PCS_TX_SEL    0x3U
+#define V_PCS_TX_SEL(x) ((x) << S_PCS_TX_SEL)
+#define G_PCS_TX_SEL(x) (((x) >> S_PCS_TX_SEL) & M_PCS_TX_SEL)
+
+#define S_XAUI20_REM_PRE    5
+#define V_XAUI20_REM_PRE(x) ((x) << S_XAUI20_REM_PRE)
+#define F_XAUI20_REM_PRE    V_XAUI20_REM_PRE(1U)
+
+#define S_XAUI20_XGMII_SEL    4
+#define V_XAUI20_XGMII_SEL(x) ((x) << S_XAUI20_XGMII_SEL)
+#define F_XAUI20_XGMII_SEL    V_XAUI20_XGMII_SEL(1U)
+
+#define S_PORT_SEL    0
+#define V_PORT_SEL(x) ((x) << S_PORT_SEL)
+#define F_PORT_SEL    V_PORT_SEL(1U)
+
+#define A_XGMAC_PORT_RESET_CTRL 0x1004
+
+#define S_AUXEXT_RESET    10
+#define V_AUXEXT_RESET(x) ((x) << S_AUXEXT_RESET)
+#define F_AUXEXT_RESET    V_AUXEXT_RESET(1U)
+
+#define S_TXFIFO_RESET    9
+#define V_TXFIFO_RESET(x) ((x) << S_TXFIFO_RESET)
+#define F_TXFIFO_RESET    V_TXFIFO_RESET(1U)
+
+#define S_RXFIFO_RESET    8
+#define V_RXFIFO_RESET(x) ((x) << S_RXFIFO_RESET)
+#define F_RXFIFO_RESET    V_RXFIFO_RESET(1U)
+
+#define S_BEAN_RESET    7
+#define V_BEAN_RESET(x) ((x) << S_BEAN_RESET)
+#define F_BEAN_RESET    V_BEAN_RESET(1U)
+
+#define S_XAUI_RESET    6
+#define V_XAUI_RESET(x) ((x) << S_XAUI_RESET)
+#define F_XAUI_RESET    V_XAUI_RESET(1U)
+
+#define S_AE_RESET    5
+#define V_AE_RESET(x) ((x) << S_AE_RESET)
+#define F_AE_RESET    V_AE_RESET(1U)
+
+#define S_XGM_RESET    4
+#define V_XGM_RESET(x) ((x) << S_XGM_RESET)
+#define F_XGM_RESET    V_XGM_RESET(1U)
+
+#define S_XG2G_RESET    3
+#define V_XG2G_RESET(x) ((x) << S_XG2G_RESET)
+#define F_XG2G_RESET    V_XG2G_RESET(1U)
+
+#define S_WOL_RESET    2
+#define V_WOL_RESET(x) ((x) << S_WOL_RESET)
+#define F_WOL_RESET    V_WOL_RESET(1U)
+
+#define S_XFI_PCS_RESET    1
+#define V_XFI_PCS_RESET(x) ((x) << S_XFI_PCS_RESET)
+#define F_XFI_PCS_RESET    V_XFI_PCS_RESET(1U)
+
+#define S_HSS_RESET    0
+#define V_HSS_RESET(x) ((x) << S_HSS_RESET)
+#define F_HSS_RESET    V_HSS_RESET(1U)
+
+#define A_XGMAC_PORT_LED_CFG 0x1008
+
+#define S_LED1_CFG    5
+#define M_LED1_CFG    0x7U
+#define V_LED1_CFG(x) ((x) << S_LED1_CFG)
+#define G_LED1_CFG(x) (((x) >> S_LED1_CFG) & M_LED1_CFG)
+
+#define S_LED1_POLARITY_INV    4
+#define V_LED1_POLARITY_INV(x) ((x) << S_LED1_POLARITY_INV)
+#define F_LED1_POLARITY_INV    V_LED1_POLARITY_INV(1U)
+
+#define S_LED0_CFG    1
+#define M_LED0_CFG    0x7U
+#define V_LED0_CFG(x) ((x) << S_LED0_CFG)
+#define G_LED0_CFG(x) (((x) >> S_LED0_CFG) & M_LED0_CFG)
+
+#define S_LED0_POLARITY_INV    0
+#define V_LED0_POLARITY_INV(x) ((x) << S_LED0_POLARITY_INV)
+#define F_LED0_POLARITY_INV    V_LED0_POLARITY_INV(1U)
+
+#define A_XGMAC_PORT_LED_COUNTHI 0x100c
+
+#define S_LED_COUNT_HI    0
+#define M_LED_COUNT_HI    0x1ffffffU
+#define V_LED_COUNT_HI(x) ((x) << S_LED_COUNT_HI)
+#define G_LED_COUNT_HI(x) (((x) >> S_LED_COUNT_HI) & M_LED_COUNT_HI)
+
+#define A_XGMAC_PORT_LED_COUNTLO 0x1010
+
+#define S_LED_COUNT_LO    0
+#define M_LED_COUNT_LO    0x1ffffffU
+#define V_LED_COUNT_LO(x) ((x) << S_LED_COUNT_LO)
+#define G_LED_COUNT_LO(x) (((x) >> S_LED_COUNT_LO) & M_LED_COUNT_LO)
+
+#define A_XGMAC_PORT_DEBUG_CFG 0x1014
+
+#define S_TESTCLK_SEL    0
+#define M_TESTCLK_SEL    0xfU
+#define V_TESTCLK_SEL(x) ((x) << S_TESTCLK_SEL)
+#define G_TESTCLK_SEL(x) (((x) >> S_TESTCLK_SEL) & M_TESTCLK_SEL)
+
+#define A_XGMAC_PORT_CFG2 0x1018
+
+#define S_RX_POLARITY_INV    28
+#define M_RX_POLARITY_INV    0xfU
+#define V_RX_POLARITY_INV(x) ((x) << S_RX_POLARITY_INV)
+#define G_RX_POLARITY_INV(x) (((x) >> S_RX_POLARITY_INV) & M_RX_POLARITY_INV)
+
+#define S_TX_POLARITY_INV    24
+#define M_TX_POLARITY_INV    0xfU
+#define V_TX_POLARITY_INV(x) ((x) << S_TX_POLARITY_INV)
+#define G_TX_POLARITY_INV(x) (((x) >> S_TX_POLARITY_INV) & M_TX_POLARITY_INV)
+
+#define S_INSTANCENUM    22
+#define M_INSTANCENUM    0x3U
+#define V_INSTANCENUM(x) ((x) << S_INSTANCENUM)
+#define G_INSTANCENUM(x) (((x) >> S_INSTANCENUM) & M_INSTANCENUM)
+
+#define S_STOPONPERR    21
+#define V_STOPONPERR(x) ((x) << S_STOPONPERR)
+#define F_STOPONPERR    V_STOPONPERR(1U)
+
+#define S_MACTXEN    20
+#define V_MACTXEN(x) ((x) << S_MACTXEN)
+#define F_MACTXEN    V_MACTXEN(1U)
+
+#define S_MACRXEN    19
+#define V_MACRXEN(x) ((x) << S_MACRXEN)
+#define F_MACRXEN    V_MACRXEN(1U)
+
+#define S_PATEN    18
+#define V_PATEN(x) ((x) << S_PATEN)
+#define F_PATEN    V_PATEN(1U)
+
+#define S_MAGICEN    17
+#define V_MAGICEN(x) ((x) << S_MAGICEN)
+#define F_MAGICEN    V_MAGICEN(1U)
+
+#define S_TX_IPG    4
+#define M_TX_IPG    0x1fffU
+#define V_TX_IPG(x) ((x) << S_TX_IPG)
+#define G_TX_IPG(x) (((x) >> S_TX_IPG) & M_TX_IPG)
+
+#define S_AEC_PMA_TX_READY    1
+#define V_AEC_PMA_TX_READY(x) ((x) << S_AEC_PMA_TX_READY)
+#define F_AEC_PMA_TX_READY    V_AEC_PMA_TX_READY(1U)
+
+#define S_AEC_PMA_RX_READY    0
+#define V_AEC_PMA_RX_READY(x) ((x) << S_AEC_PMA_RX_READY)
+#define F_AEC_PMA_RX_READY    V_AEC_PMA_RX_READY(1U)
+
+#define A_XGMAC_PORT_PKT_COUNT 0x101c
+
+#define S_TX_SOP_COUNT    24
+#define M_TX_SOP_COUNT    0xffU
+#define V_TX_SOP_COUNT(x) ((x) << S_TX_SOP_COUNT)
+#define G_TX_SOP_COUNT(x) (((x) >> S_TX_SOP_COUNT) & M_TX_SOP_COUNT)
+
+#define S_TX_EOP_COUNT    16
+#define M_TX_EOP_COUNT    0xffU
+#define V_TX_EOP_COUNT(x) ((x) << S_TX_EOP_COUNT)
+#define G_TX_EOP_COUNT(x) (((x) >> S_TX_EOP_COUNT) & M_TX_EOP_COUNT)
+
+#define S_RX_SOP_COUNT    8
+#define M_RX_SOP_COUNT    0xffU
+#define V_RX_SOP_COUNT(x) ((x) << S_RX_SOP_COUNT)
+#define G_RX_SOP_COUNT(x) (((x) >> S_RX_SOP_COUNT) & M_RX_SOP_COUNT)
+
+#define S_RX_EOP_COUNT    0
+#define M_RX_EOP_COUNT    0xffU
+#define V_RX_EOP_COUNT(x) ((x) << S_RX_EOP_COUNT)
+#define G_RX_EOP_COUNT(x) (((x) >> S_RX_EOP_COUNT) & M_RX_EOP_COUNT)
+
+#define A_XGMAC_PORT_PERR_INJECT 0x1020
+
+#define S_XGMMEMSEL    1
+#define V_XGMMEMSEL(x) ((x) << S_XGMMEMSEL)
+#define F_XGMMEMSEL    V_XGMMEMSEL(1U)
+
+#define A_XGMAC_PORT_MAGIC_MACID_LO 0x1024
+#define A_XGMAC_PORT_MAGIC_MACID_HI 0x1028
+
+#define S_MAC_WOL_DA    0
+#define M_MAC_WOL_DA    0xffffU
+#define V_MAC_WOL_DA(x) ((x) << S_MAC_WOL_DA)
+#define G_MAC_WOL_DA(x) (((x) >> S_MAC_WOL_DA) & M_MAC_WOL_DA)
+
+#define A_XGMAC_PORT_BUILD_REVISION 0x102c
+#define A_XGMAC_PORT_XGMII_SE_COUNT 0x1030
+
+#define S_TXSOP    24
+#define M_TXSOP    0xffU
+#define V_TXSOP(x) ((x) << S_TXSOP)
+#define G_TXSOP(x) (((x) >> S_TXSOP) & M_TXSOP)
+
+#define S_TXEOP    16
+#define M_TXEOP    0xffU
+#define V_TXEOP(x) ((x) << S_TXEOP)
+#define G_TXEOP(x) (((x) >> S_TXEOP) & M_TXEOP)
+
+#define S_RXSOP    8
+#define M_RXSOP    0xffU
+#define V_RXSOP(x) ((x) << S_RXSOP)
+#define G_RXSOP(x) (((x) >> S_RXSOP) & M_RXSOP)
+
+#define A_XGMAC_PORT_LINK_STATUS 0x1034
+
+#define S_REMFLT    3
+#define V_REMFLT(x) ((x) << S_REMFLT)
+#define F_REMFLT    V_REMFLT(1U)
+
+#define S_LOCFLT    2
+#define V_LOCFLT(x) ((x) << S_LOCFLT)
+#define F_LOCFLT    V_LOCFLT(1U)
+
+#define S_LINKUP    1
+#define V_LINKUP(x) ((x) << S_LINKUP)
+#define F_LINKUP    V_LINKUP(1U)
+
+#define S_LINKDN    0
+#define V_LINKDN(x) ((x) << S_LINKDN)
+#define F_LINKDN    V_LINKDN(1U)
+
+#define A_XGMAC_PORT_CHECKIN 0x1038
+
+#define S_PREAMBLE    1
+#define V_PREAMBLE(x) ((x) << S_PREAMBLE)
+#define F_PREAMBLE    V_PREAMBLE(1U)
+
+#define S_CHECKIN    0
+#define V_CHECKIN(x) ((x) << S_CHECKIN)
+#define F_CHECKIN    V_CHECKIN(1U)
+
+#define A_XGMAC_PORT_FAULT_TEST 0x103c
+
+#define S_FLTTYPE    1
+#define V_FLTTYPE(x) ((x) << S_FLTTYPE)
+#define F_FLTTYPE    V_FLTTYPE(1U)
+
+#define S_FLTCTRL    0
+#define V_FLTCTRL(x) ((x) << S_FLTCTRL)
+#define F_FLTCTRL    V_FLTCTRL(1U)
+
+#define A_XGMAC_PORT_SPARE 0x1040
+#define A_XGMAC_PORT_HSS_SIGDET_STATUS 0x1044
+
+#define S_SIGNALDETECT    0
+#define M_SIGNALDETECT    0xfU
+#define V_SIGNALDETECT(x) ((x) << S_SIGNALDETECT)
+#define G_SIGNALDETECT(x) (((x) >> S_SIGNALDETECT) & M_SIGNALDETECT)
+
+#define A_XGMAC_PORT_EXT_LOS_STATUS 0x1048
+#define A_XGMAC_PORT_EXT_LOS_CTRL 0x104c
+
+#define S_CTRL    0
+#define M_CTRL    0xfU
+#define V_CTRL(x) ((x) << S_CTRL)
+#define G_CTRL(x) (((x) >> S_CTRL) & M_CTRL)
+
+#define A_XGMAC_PORT_FPGA_PAUSE_CTL 0x1050
+
+#define S_CTL    31
+#define V_CTL(x) ((x) << S_CTL)
+#define F_CTL    V_CTL(1U)
+
+#define S_HWM    13
+#define M_HWM    0x1fffU
+#define V_HWM(x) ((x) << S_HWM)
+#define G_HWM(x) (((x) >> S_HWM) & M_HWM)
+
+#define S_LWM    0
+#define M_LWM    0x1fffU
+#define V_LWM(x) ((x) << S_LWM)
+#define G_LWM(x) (((x) >> S_LWM) & M_LWM)
+
+#define A_XGMAC_PORT_FPGA_ERRPKT_CNT 0x1054
+#define A_XGMAC_PORT_LA_TX_0 0x1058
+#define A_XGMAC_PORT_LA_RX_0 0x105c
+#define A_XGMAC_PORT_FPGA_LA_CTL 0x1060
+
+#define S_RXRST    5
+#define V_RXRST(x) ((x) << S_RXRST)
+#define F_RXRST    V_RXRST(1U)
+
+#define S_TXRST    4
+#define V_TXRST(x) ((x) << S_TXRST)
+#define F_TXRST    V_TXRST(1U)
+
+#define S_XGMII    3
+#define V_XGMII(x) ((x) << S_XGMII)
+#define F_XGMII    V_XGMII(1U)
+
+#define S_LAPAUSE    2
+#define V_LAPAUSE(x) ((x) << S_LAPAUSE)
+#define F_LAPAUSE    V_LAPAUSE(1U)
+
+#define S_STOPERR    1
+#define V_STOPERR(x) ((x) << S_STOPERR)
+#define F_STOPERR    V_STOPERR(1U)
+
+#define S_LASTOP    0
+#define V_LASTOP(x) ((x) << S_LASTOP)
+#define F_LASTOP    V_LASTOP(1U)
+
+#define A_XGMAC_PORT_EPIO_DATA0 0x10c0
+#define A_XGMAC_PORT_EPIO_DATA1 0x10c4
+#define A_XGMAC_PORT_EPIO_DATA2 0x10c8
+#define A_XGMAC_PORT_EPIO_DATA3 0x10cc
+#define A_XGMAC_PORT_EPIO_OP 0x10d0
+
+#define S_EPIOWR    8
+#define V_EPIOWR(x) ((x) << S_EPIOWR)
+#define F_EPIOWR    V_EPIOWR(1U)
+
+#define S_ADDRESS    0
+#define M_ADDRESS    0xffU
+#define V_ADDRESS(x) ((x) << S_ADDRESS)
+#define G_ADDRESS(x) (((x) >> S_ADDRESS) & M_ADDRESS)
+
+#define A_XGMAC_PORT_WOL_STATUS 0x10d4
+
+#define S_MAGICDETECTED    31
+#define V_MAGICDETECTED(x) ((x) << S_MAGICDETECTED)
+#define F_MAGICDETECTED    V_MAGICDETECTED(1U)
+
+#define S_PATDETECTED    30
+#define V_PATDETECTED(x) ((x) << S_PATDETECTED)
+#define F_PATDETECTED    V_PATDETECTED(1U)
+
+#define S_CLEARMAGIC    4
+#define V_CLEARMAGIC(x) ((x) << S_CLEARMAGIC)
+#define F_CLEARMAGIC    V_CLEARMAGIC(1U)
+
+#define S_CLEARMATCH    3
+#define V_CLEARMATCH(x) ((x) << S_CLEARMATCH)
+#define F_CLEARMATCH    V_CLEARMATCH(1U)
+
+#define S_MATCHEDFILTER    0
+#define M_MATCHEDFILTER    0x7U
+#define V_MATCHEDFILTER(x) ((x) << S_MATCHEDFILTER)
+#define G_MATCHEDFILTER(x) (((x) >> S_MATCHEDFILTER) & M_MATCHEDFILTER)
+
+#define A_XGMAC_PORT_INT_EN 0x10d8
+
+#define S_EXT_LOS    28
+#define V_EXT_LOS(x) ((x) << S_EXT_LOS)
+#define F_EXT_LOS    V_EXT_LOS(1U)
+
+#define S_INCMPTBL_LINK    27
+#define V_INCMPTBL_LINK(x) ((x) << S_INCMPTBL_LINK)
+#define F_INCMPTBL_LINK    V_INCMPTBL_LINK(1U)
+
+#define S_PATDETWAKE    26
+#define V_PATDETWAKE(x) ((x) << S_PATDETWAKE)
+#define F_PATDETWAKE    V_PATDETWAKE(1U)
+
+#define S_MAGICWAKE    25
+#define V_MAGICWAKE(x) ((x) << S_MAGICWAKE)
+#define F_MAGICWAKE    V_MAGICWAKE(1U)
+
+#define S_SIGDETCHG    24
+#define V_SIGDETCHG(x) ((x) << S_SIGDETCHG)
+#define F_SIGDETCHG    V_SIGDETCHG(1U)
+
+#define S_PCSR_FEC_CORR    23
+#define V_PCSR_FEC_CORR(x) ((x) << S_PCSR_FEC_CORR)
+#define F_PCSR_FEC_CORR    V_PCSR_FEC_CORR(1U)
+
+#define S_AE_TRAIN_LOCAL    22
+#define V_AE_TRAIN_LOCAL(x) ((x) << S_AE_TRAIN_LOCAL)
+#define F_AE_TRAIN_LOCAL    V_AE_TRAIN_LOCAL(1U)
+
+#define S_HSSPLL_LOCK    21
+#define V_HSSPLL_LOCK(x) ((x) << S_HSSPLL_LOCK)
+#define F_HSSPLL_LOCK    V_HSSPLL_LOCK(1U)
+
+#define S_HSSPRT_READY    20
+#define V_HSSPRT_READY(x) ((x) << S_HSSPRT_READY)
+#define F_HSSPRT_READY    V_HSSPRT_READY(1U)
+
+#define S_AUTONEG_DONE    19
+#define V_AUTONEG_DONE(x) ((x) << S_AUTONEG_DONE)
+#define F_AUTONEG_DONE    V_AUTONEG_DONE(1U)
+
+#define S_PCSR_HI_BER    18
+#define V_PCSR_HI_BER(x) ((x) << S_PCSR_HI_BER)
+#define F_PCSR_HI_BER    V_PCSR_HI_BER(1U)
+
+#define S_PCSR_FEC_ERROR    17
+#define V_PCSR_FEC_ERROR(x) ((x) << S_PCSR_FEC_ERROR)
+#define F_PCSR_FEC_ERROR    V_PCSR_FEC_ERROR(1U)
+
+#define S_PCSR_LINK_FAIL    16
+#define V_PCSR_LINK_FAIL(x) ((x) << S_PCSR_LINK_FAIL)
+#define F_PCSR_LINK_FAIL    V_PCSR_LINK_FAIL(1U)
+
+#define S_XAUI_DEC_ERROR    15
+#define V_XAUI_DEC_ERROR(x) ((x) << S_XAUI_DEC_ERROR)
+#define F_XAUI_DEC_ERROR    V_XAUI_DEC_ERROR(1U)
+
+#define S_XAUI_LINK_FAIL    14
+#define V_XAUI_LINK_FAIL(x) ((x) << S_XAUI_LINK_FAIL)
+#define F_XAUI_LINK_FAIL    V_XAUI_LINK_FAIL(1U)
+
+#define S_PCS_CTC_ERROR    13
+#define V_PCS_CTC_ERROR(x) ((x) << S_PCS_CTC_ERROR)
+#define F_PCS_CTC_ERROR    V_PCS_CTC_ERROR(1U)
+
+#define S_PCS_LINK_GOOD    12
+#define V_PCS_LINK_GOOD(x) ((x) << S_PCS_LINK_GOOD)
+#define F_PCS_LINK_GOOD    V_PCS_LINK_GOOD(1U)
+
+#define S_PCS_LINK_FAIL    11
+#define V_PCS_LINK_FAIL(x) ((x) << S_PCS_LINK_FAIL)
+#define F_PCS_LINK_FAIL    V_PCS_LINK_FAIL(1U)
+
+#define S_RXFIFOOVERFLOW    10
+#define V_RXFIFOOVERFLOW(x) ((x) << S_RXFIFOOVERFLOW)
+#define F_RXFIFOOVERFLOW    V_RXFIFOOVERFLOW(1U)
+
+#define S_HSSPRBSERR    9
+#define V_HSSPRBSERR(x) ((x) << S_HSSPRBSERR)
+#define F_HSSPRBSERR    V_HSSPRBSERR(1U)
+
+#define S_HSSEYEQUAL    8
+#define V_HSSEYEQUAL(x) ((x) << S_HSSEYEQUAL)
+#define F_HSSEYEQUAL    V_HSSEYEQUAL(1U)
+
+#define S_REMOTEFAULT    7
+#define V_REMOTEFAULT(x) ((x) << S_REMOTEFAULT)
+#define F_REMOTEFAULT    V_REMOTEFAULT(1U)
+
+#define S_LOCALFAULT    6
+#define V_LOCALFAULT(x) ((x) << S_LOCALFAULT)
+#define F_LOCALFAULT    V_LOCALFAULT(1U)
+
+#define S_MAC_LINK_DOWN    5
+#define V_MAC_LINK_DOWN(x) ((x) << S_MAC_LINK_DOWN)
+#define F_MAC_LINK_DOWN    V_MAC_LINK_DOWN(1U)
+
+#define S_MAC_LINK_UP    4
+#define V_MAC_LINK_UP(x) ((x) << S_MAC_LINK_UP)
+#define F_MAC_LINK_UP    V_MAC_LINK_UP(1U)
+
+#define S_BEAN_INT    3
+#define V_BEAN_INT(x) ((x) << S_BEAN_INT)
+#define F_BEAN_INT    V_BEAN_INT(1U)
+
+#define S_XGM_INT    2
+#define V_XGM_INT(x) ((x) << S_XGM_INT)
+#define F_XGM_INT    V_XGM_INT(1U)
+
+#define A_XGMAC_PORT_INT_CAUSE 0x10dc
+#define A_XGMAC_PORT_HSS_CFG0 0x10e0
+
+#define S_TXDTS    31
+#define V_TXDTS(x) ((x) << S_TXDTS)
+#define F_TXDTS    V_TXDTS(1U)
+
+#define S_TXCTS    30
+#define V_TXCTS(x) ((x) << S_TXCTS)
+#define F_TXCTS    V_TXCTS(1U)
+
+#define S_TXBTS    29
+#define V_TXBTS(x) ((x) << S_TXBTS)
+#define F_TXBTS    V_TXBTS(1U)
+
+#define S_TXATS    28
+#define V_TXATS(x) ((x) << S_TXATS)
+#define F_TXATS    V_TXATS(1U)
+
+#define S_TXDOBS    27
+#define V_TXDOBS(x) ((x) << S_TXDOBS)
+#define F_TXDOBS    V_TXDOBS(1U)
+
+#define S_TXCOBS    26
+#define V_TXCOBS(x) ((x) << S_TXCOBS)
+#define F_TXCOBS    V_TXCOBS(1U)
+
+#define S_TXBOBS    25
+#define V_TXBOBS(x) ((x) << S_TXBOBS)
+#define F_TXBOBS    V_TXBOBS(1U)
+
+#define S_TXAOBS    24
+#define V_TXAOBS(x) ((x) << S_TXAOBS)
+#define F_TXAOBS    V_TXAOBS(1U)
+
+#define S_HSSREFCLKSEL    20
+#define V_HSSREFCLKSEL(x) ((x) << S_HSSREFCLKSEL)
+#define F_HSSREFCLKSEL    V_HSSREFCLKSEL(1U)
+
+#define S_HSSAVDHI    17
+#define V_HSSAVDHI(x) ((x) << S_HSSAVDHI)
+#define F_HSSAVDHI    V_HSSAVDHI(1U)
+
+#define S_HSSRXTS    16
+#define V_HSSRXTS(x) ((x) << S_HSSRXTS)
+#define F_HSSRXTS    V_HSSRXTS(1U)
+
+#define S_HSSTXACMODE    15
+#define V_HSSTXACMODE(x) ((x) << S_HSSTXACMODE)
+#define F_HSSTXACMODE    V_HSSTXACMODE(1U)
+
+#define S_HSSRXACMODE    14
+#define V_HSSRXACMODE(x) ((x) << S_HSSRXACMODE)
+#define F_HSSRXACMODE    V_HSSRXACMODE(1U)
+
+#define S_HSSRESYNC    13
+#define V_HSSRESYNC(x) ((x) << S_HSSRESYNC)
+#define F_HSSRESYNC    V_HSSRESYNC(1U)
+
+#define S_HSSRECCAL    12
+#define V_HSSRECCAL(x) ((x) << S_HSSRECCAL)
+#define F_HSSRECCAL    V_HSSRECCAL(1U)
+
+#define S_HSSPDWNPLL    11
+#define V_HSSPDWNPLL(x) ((x) << S_HSSPDWNPLL)
+#define F_HSSPDWNPLL    V_HSSPDWNPLL(1U)
+
+#define S_HSSDIVSEL    9
+#define M_HSSDIVSEL    0x3U
+#define V_HSSDIVSEL(x) ((x) << S_HSSDIVSEL)
+#define G_HSSDIVSEL(x) (((x) >> S_HSSDIVSEL) & M_HSSDIVSEL)
+
+#define S_HSSREFDIV    8
+#define V_HSSREFDIV(x) ((x) << S_HSSREFDIV)
+#define F_HSSREFDIV    V_HSSREFDIV(1U)
+
+#define S_HSSPLLBYP    7
+#define V_HSSPLLBYP(x) ((x) << S_HSSPLLBYP)
+#define F_HSSPLLBYP    V_HSSPLLBYP(1U)
+
+#define S_HSSLOFREQPLL    6
+#define V_HSSLOFREQPLL(x) ((x) << S_HSSLOFREQPLL)
+#define F_HSSLOFREQPLL    V_HSSLOFREQPLL(1U)
+
+#define S_HSSLOFREQ2PLL    5
+#define V_HSSLOFREQ2PLL(x) ((x) << S_HSSLOFREQ2PLL)
+#define F_HSSLOFREQ2PLL    V_HSSLOFREQ2PLL(1U)
+
+#define S_HSSEXTC16SEL    4
+#define V_HSSEXTC16SEL(x) ((x) << S_HSSEXTC16SEL)
+#define F_HSSEXTC16SEL    V_HSSEXTC16SEL(1U)
+
+#define S_HSSRSTCONFIG    1
+#define M_HSSRSTCONFIG    0x7U
+#define V_HSSRSTCONFIG(x) ((x) << S_HSSRSTCONFIG)
+#define G_HSSRSTCONFIG(x) (((x) >> S_HSSRSTCONFIG) & M_HSSRSTCONFIG)
+
+#define S_HSSPRBSEN    0
+#define V_HSSPRBSEN(x) ((x) << S_HSSPRBSEN)
+#define F_HSSPRBSEN    V_HSSPRBSEN(1U)
+
+#define A_XGMAC_PORT_HSS_CFG1 0x10e4
+
+#define S_RXDPRBSRST    28
+#define V_RXDPRBSRST(x) ((x) << S_RXDPRBSRST)
+#define F_RXDPRBSRST    V_RXDPRBSRST(1U)
+
+#define S_RXDPRBSEN    27
+#define V_RXDPRBSEN(x) ((x) << S_RXDPRBSEN)
+#define F_RXDPRBSEN    V_RXDPRBSEN(1U)
+
+#define S_RXDPRBSFRCERR    26
+#define V_RXDPRBSFRCERR(x) ((x) << S_RXDPRBSFRCERR)
+#define F_RXDPRBSFRCERR    V_RXDPRBSFRCERR(1U)
+
+#define S_TXDPRBSRST    25
+#define V_TXDPRBSRST(x) ((x) << S_TXDPRBSRST)
+#define F_TXDPRBSRST    V_TXDPRBSRST(1U)
+
+#define S_TXDPRBSEN    24
+#define V_TXDPRBSEN(x) ((x) << S_TXDPRBSEN)
+#define F_TXDPRBSEN    V_TXDPRBSEN(1U)
+
+#define S_RXCPRBSRST    20
+#define V_RXCPRBSRST(x) ((x) << S_RXCPRBSRST)
+#define F_RXCPRBSRST    V_RXCPRBSRST(1U)
+
+#define S_RXCPRBSEN    19
+#define V_RXCPRBSEN(x) ((x) << S_RXCPRBSEN)
+#define F_RXCPRBSEN    V_RXCPRBSEN(1U)
+
+#define S_RXCPRBSFRCERR    18
+#define V_RXCPRBSFRCERR(x) ((x) << S_RXCPRBSFRCERR)
+#define F_RXCPRBSFRCERR    V_RXCPRBSFRCERR(1U)
+
+#define S_TXCPRBSRST    17
+#define V_TXCPRBSRST(x) ((x) << S_TXCPRBSRST)
+#define F_TXCPRBSRST    V_TXCPRBSRST(1U)
+
+#define S_TXCPRBSEN    16
+#define V_TXCPRBSEN(x) ((x) << S_TXCPRBSEN)
+#define F_TXCPRBSEN    V_TXCPRBSEN(1U)
+
+#define S_RXBPRBSRST    12
+#define V_RXBPRBSRST(x) ((x) << S_RXBPRBSRST)
+#define F_RXBPRBSRST    V_RXBPRBSRST(1U)
+
+#define S_RXBPRBSEN    11
+#define V_RXBPRBSEN(x) ((x) << S_RXBPRBSEN)
+#define F_RXBPRBSEN    V_RXBPRBSEN(1U)
+
+#define S_RXBPRBSFRCERR    10
+#define V_RXBPRBSFRCERR(x) ((x) << S_RXBPRBSFRCERR)
+#define F_RXBPRBSFRCERR    V_RXBPRBSFRCERR(1U)
+
+#define S_TXBPRBSRST    9
+#define V_TXBPRBSRST(x) ((x) << S_TXBPRBSRST)
+#define F_TXBPRBSRST    V_TXBPRBSRST(1U)
+
+#define S_TXBPRBSEN    8
+#define V_TXBPRBSEN(x) ((x) << S_TXBPRBSEN)
+#define F_TXBPRBSEN    V_TXBPRBSEN(1U)
+
+#define S_RXAPRBSRST    4
+#define V_RXAPRBSRST(x) ((x) << S_RXAPRBSRST)
+#define F_RXAPRBSRST    V_RXAPRBSRST(1U)
+
+#define S_RXAPRBSEN    3
+#define V_RXAPRBSEN(x) ((x) << S_RXAPRBSEN)
+#define F_RXAPRBSEN    V_RXAPRBSEN(1U)
+
+#define S_RXAPRBSFRCERR    2
+#define V_RXAPRBSFRCERR(x) ((x) << S_RXAPRBSFRCERR)
+#define F_RXAPRBSFRCERR    V_RXAPRBSFRCERR(1U)
+
+#define S_TXAPRBSRST    1
+#define V_TXAPRBSRST(x) ((x) << S_TXAPRBSRST)
+#define F_TXAPRBSRST    V_TXAPRBSRST(1U)
+
+#define S_TXAPRBSEN    0
+#define V_TXAPRBSEN(x) ((x) << S_TXAPRBSEN)
+#define F_TXAPRBSEN    V_TXAPRBSEN(1U)
+
+#define A_XGMAC_PORT_HSS_CFG2 0x10e8
+
+#define S_RXDDATASYNC    23
+#define V_RXDDATASYNC(x) ((x) << S_RXDDATASYNC)
+#define F_RXDDATASYNC    V_RXDDATASYNC(1U)
+
+#define S_RXCDATASYNC    22
+#define V_RXCDATASYNC(x) ((x) << S_RXCDATASYNC)
+#define F_RXCDATASYNC    V_RXCDATASYNC(1U)
+
+#define S_RXBDATASYNC    21
+#define V_RXBDATASYNC(x) ((x) << S_RXBDATASYNC)
+#define F_RXBDATASYNC    V_RXBDATASYNC(1U)
+
+#define S_RXADATASYNC    20
+#define V_RXADATASYNC(x) ((x) << S_RXADATASYNC)
+#define F_RXADATASYNC    V_RXADATASYNC(1U)
+
+#define S_RXDEARLYIN    19
+#define V_RXDEARLYIN(x) ((x) << S_RXDEARLYIN)
+#define F_RXDEARLYIN    V_RXDEARLYIN(1U)
+
+#define S_RXDLATEIN    18
+#define V_RXDLATEIN(x) ((x) << S_RXDLATEIN)
+#define F_RXDLATEIN    V_RXDLATEIN(1U)
+
+#define S_RXDPHSLOCK    17
+#define V_RXDPHSLOCK(x) ((x) << S_RXDPHSLOCK)
+#define F_RXDPHSLOCK    V_RXDPHSLOCK(1U)
+
+#define S_RXDPHSDNIN    16
+#define V_RXDPHSDNIN(x) ((x) << S_RXDPHSDNIN)
+#define F_RXDPHSDNIN    V_RXDPHSDNIN(1U)
+
+#define S_RXDPHSUPIN    15
+#define V_RXDPHSUPIN(x) ((x) << S_RXDPHSUPIN)
+#define F_RXDPHSUPIN    V_RXDPHSUPIN(1U)
+
+#define S_RXCEARLYIN    14
+#define V_RXCEARLYIN(x) ((x) << S_RXCEARLYIN)
+#define F_RXCEARLYIN    V_RXCEARLYIN(1U)
+
+#define S_RXCLATEIN    13
+#define V_RXCLATEIN(x) ((x) << S_RXCLATEIN)
+#define F_RXCLATEIN    V_RXCLATEIN(1U)
+
+#define S_RXCPHSLOCK    12
+#define V_RXCPHSLOCK(x) ((x) << S_RXCPHSLOCK)
+#define F_RXCPHSLOCK    V_RXCPHSLOCK(1U)
+
+#define S_RXCPHSDNIN    11
+#define V_RXCPHSDNIN(x) ((x) << S_RXCPHSDNIN)
+#define F_RXCPHSDNIN    V_RXCPHSDNIN(1U)
+
+#define S_RXCPHSUPIN    10
+#define V_RXCPHSUPIN(x) ((x) << S_RXCPHSUPIN)
+#define F_RXCPHSUPIN    V_RXCPHSUPIN(1U)
+
+#define S_RXBEARLYIN    9
+#define V_RXBEARLYIN(x) ((x) << S_RXBEARLYIN)
+#define F_RXBEARLYIN    V_RXBEARLYIN(1U)
+
+#define S_RXBLATEIN    8
+#define V_RXBLATEIN(x) ((x) << S_RXBLATEIN)
+#define F_RXBLATEIN    V_RXBLATEIN(1U)
+
+#define S_RXBPHSLOCK    7
+#define V_RXBPHSLOCK(x) ((x) << S_RXBPHSLOCK)
+#define F_RXBPHSLOCK    V_RXBPHSLOCK(1U)
+
+#define S_RXBPHSDNIN    6
+#define V_RXBPHSDNIN(x) ((x) << S_RXBPHSDNIN)
+#define F_RXBPHSDNIN    V_RXBPHSDNIN(1U)
+
+#define S_RXBPHSUPIN    5
+#define V_RXBPHSUPIN(x) ((x) << S_RXBPHSUPIN)
+#define F_RXBPHSUPIN    V_RXBPHSUPIN(1U)
+
+#define S_RXAEARLYIN    4
+#define V_RXAEARLYIN(x) ((x) << S_RXAEARLYIN)
+#define F_RXAEARLYIN    V_RXAEARLYIN(1U)
+
+#define S_RXALATEIN    3
+#define V_RXALATEIN(x) ((x) << S_RXALATEIN)
+#define F_RXALATEIN    V_RXALATEIN(1U)
+
+#define S_RXAPHSLOCK    2
+#define V_RXAPHSLOCK(x) ((x) << S_RXAPHSLOCK)
+#define F_RXAPHSLOCK    V_RXAPHSLOCK(1U)
+
+#define S_RXAPHSDNIN    1
+#define V_RXAPHSDNIN(x) ((x) << S_RXAPHSDNIN)
+#define F_RXAPHSDNIN    V_RXAPHSDNIN(1U)
+
+#define S_RXAPHSUPIN    0
+#define V_RXAPHSUPIN(x) ((x) << S_RXAPHSUPIN)
+#define F_RXAPHSUPIN    V_RXAPHSUPIN(1U)
+
+#define A_XGMAC_PORT_HSS_STATUS 0x10ec
+
+#define S_RXDPRBSSYNC    15
+#define V_RXDPRBSSYNC(x) ((x) << S_RXDPRBSSYNC)
+#define F_RXDPRBSSYNC    V_RXDPRBSSYNC(1U)
+
+#define S_RXCPRBSSYNC    14
+#define V_RXCPRBSSYNC(x) ((x) << S_RXCPRBSSYNC)
+#define F_RXCPRBSSYNC    V_RXCPRBSSYNC(1U)
+
+#define S_RXBPRBSSYNC    13
+#define V_RXBPRBSSYNC(x) ((x) << S_RXBPRBSSYNC)
+#define F_RXBPRBSSYNC    V_RXBPRBSSYNC(1U)
+
+#define S_RXAPRBSSYNC    12
+#define V_RXAPRBSSYNC(x) ((x) << S_RXAPRBSSYNC)
+#define F_RXAPRBSSYNC    V_RXAPRBSSYNC(1U)
+
+#define S_RXDPRBSERR    11
+#define V_RXDPRBSERR(x) ((x) << S_RXDPRBSERR)
+#define F_RXDPRBSERR    V_RXDPRBSERR(1U)
+
+#define S_RXCPRBSERR    10
+#define V_RXCPRBSERR(x) ((x) << S_RXCPRBSERR)
+#define F_RXCPRBSERR    V_RXCPRBSERR(1U)
+
+#define S_RXBPRBSERR    9
+#define V_RXBPRBSERR(x) ((x) << S_RXBPRBSERR)
+#define F_RXBPRBSERR    V_RXBPRBSERR(1U)
+
+#define S_RXAPRBSERR    8
+#define V_RXAPRBSERR(x) ((x) << S_RXAPRBSERR)
+#define F_RXAPRBSERR    V_RXAPRBSERR(1U)
+
+#define S_RXDSIGDET    7
+#define V_RXDSIGDET(x) ((x) << S_RXDSIGDET)
+#define F_RXDSIGDET    V_RXDSIGDET(1U)
+
+#define S_RXCSIGDET    6
+#define V_RXCSIGDET(x) ((x) << S_RXCSIGDET)
+#define F_RXCSIGDET    V_RXCSIGDET(1U)
+
+#define S_RXBSIGDET    5
+#define V_RXBSIGDET(x) ((x) << S_RXBSIGDET)
+#define F_RXBSIGDET    V_RXBSIGDET(1U)
+
+#define S_RXASIGDET    4
+#define V_RXASIGDET(x) ((x) << S_RXASIGDET)
+#define F_RXASIGDET    V_RXASIGDET(1U)
+
+#define S_HSSPLLLOCK    1
+#define V_HSSPLLLOCK(x) ((x) << S_HSSPLLLOCK)
+#define F_HSSPLLLOCK    V_HSSPLLLOCK(1U)
+
+#define S_HSSPRTREADY    0
+#define V_HSSPRTREADY(x) ((x) << S_HSSPRTREADY)
+#define F_HSSPRTREADY    V_HSSPRTREADY(1U)
+
+#define A_XGMAC_PORT_XGM_TX_CTRL 0x1200
+
+#define S_SENDPAUSE    2
+#define V_SENDPAUSE(x) ((x) << S_SENDPAUSE)
+#define F_SENDPAUSE    V_SENDPAUSE(1U)
+
+#define S_SENDZEROPAUSE    1
+#define V_SENDZEROPAUSE(x) ((x) << S_SENDZEROPAUSE)
+#define F_SENDZEROPAUSE    V_SENDZEROPAUSE(1U)
+
+#define S_XGM_TXEN    0
+#define V_XGM_TXEN(x) ((x) << S_XGM_TXEN)
+#define F_XGM_TXEN    V_XGM_TXEN(1U)
+
+#define A_XGMAC_PORT_XGM_TX_CFG 0x1204
+
+#define S_CRCCAL    8
+#define M_CRCCAL    0x3U
+#define V_CRCCAL(x) ((x) << S_CRCCAL)
+#define G_CRCCAL(x) (((x) >> S_CRCCAL) & M_CRCCAL)
+
+#define S_DISDEFIDLECNT    7
+#define V_DISDEFIDLECNT(x) ((x) << S_DISDEFIDLECNT)
+#define F_DISDEFIDLECNT    V_DISDEFIDLECNT(1U)
+
+#define S_DECAVGTXIPG    6
+#define V_DECAVGTXIPG(x) ((x) << S_DECAVGTXIPG)
+#define F_DECAVGTXIPG    V_DECAVGTXIPG(1U)
+
+#define S_UNIDIRTXEN    5
+#define V_UNIDIRTXEN(x) ((x) << S_UNIDIRTXEN)
+#define F_UNIDIRTXEN    V_UNIDIRTXEN(1U)
+
+#define S_CFGCLKSPEED    2
+#define M_CFGCLKSPEED    0x7U
+#define V_CFGCLKSPEED(x) ((x) << S_CFGCLKSPEED)
+#define G_CFGCLKSPEED(x) (((x) >> S_CFGCLKSPEED) & M_CFGCLKSPEED)
+
+#define S_STRETCHMODE    1
+#define V_STRETCHMODE(x) ((x) << S_STRETCHMODE)
+#define F_STRETCHMODE    V_STRETCHMODE(1U)
+
+#define S_TXPAUSEEN    0
+#define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN)
+#define F_TXPAUSEEN    V_TXPAUSEEN(1U)
+
+#define A_XGMAC_PORT_XGM_TX_PAUSE_QUANTA 0x1208
+
+#define S_TXPAUSEQUANTA    0
+#define M_TXPAUSEQUANTA    0xffffU
+#define V_TXPAUSEQUANTA(x) ((x) << S_TXPAUSEQUANTA)
+#define G_TXPAUSEQUANTA(x) (((x) >> S_TXPAUSEQUANTA) & M_TXPAUSEQUANTA)
+
+#define A_XGMAC_PORT_XGM_RX_CTRL 0x120c
+#define A_XGMAC_PORT_XGM_RX_CFG 0x1210
+
+#define S_RXCRCCAL    16
+#define M_RXCRCCAL    0x3U
+#define V_RXCRCCAL(x) ((x) << S_RXCRCCAL)
+#define G_RXCRCCAL(x) (((x) >> S_RXCRCCAL) & M_RXCRCCAL)
+
+#define S_STATLOCALFAULT    15
+#define V_STATLOCALFAULT(x) ((x) << S_STATLOCALFAULT)
+#define F_STATLOCALFAULT    V_STATLOCALFAULT(1U)
+
+#define S_STATREMOTEFAULT    14
+#define V_STATREMOTEFAULT(x) ((x) << S_STATREMOTEFAULT)
+#define F_STATREMOTEFAULT    V_STATREMOTEFAULT(1U)
+
+#define S_LENERRFRAMEDIS    13
+#define V_LENERRFRAMEDIS(x) ((x) << S_LENERRFRAMEDIS)
+#define F_LENERRFRAMEDIS    V_LENERRFRAMEDIS(1U)
+
+#define S_CON802_3PREAMBLE    12
+#define V_CON802_3PREAMBLE(x) ((x) << S_CON802_3PREAMBLE)
+#define F_CON802_3PREAMBLE    V_CON802_3PREAMBLE(1U)
+
+#define S_ENNON802_3PREAMBLE    11
+#define V_ENNON802_3PREAMBLE(x) ((x) << S_ENNON802_3PREAMBLE)
+#define F_ENNON802_3PREAMBLE    V_ENNON802_3PREAMBLE(1U)
+
+#define S_COPYPREAMBLE    10
+#define V_COPYPREAMBLE(x) ((x) << S_COPYPREAMBLE)
+#define F_COPYPREAMBLE    V_COPYPREAMBLE(1U)
+
+#define S_DISPAUSEFRAMES    9
+#define V_DISPAUSEFRAMES(x) ((x) << S_DISPAUSEFRAMES)
+#define F_DISPAUSEFRAMES    V_DISPAUSEFRAMES(1U)
+
+#define S_EN1536BFRAMES    8
+#define V_EN1536BFRAMES(x) ((x) << S_EN1536BFRAMES)
+#define F_EN1536BFRAMES    V_EN1536BFRAMES(1U)
+
+#define S_ENJUMBO    7
+#define V_ENJUMBO(x) ((x) << S_ENJUMBO)
+#define F_ENJUMBO    V_ENJUMBO(1U)
+
+#define S_RMFCS    6
+#define V_RMFCS(x) ((x) << S_RMFCS)
+#define F_RMFCS    V_RMFCS(1U)
+
+#define S_DISNONVLAN    5
+#define V_DISNONVLAN(x) ((x) << S_DISNONVLAN)
+#define F_DISNONVLAN    V_DISNONVLAN(1U)
+
+#define S_ENEXTMATCH    4
+#define V_ENEXTMATCH(x) ((x) << S_ENEXTMATCH)
+#define F_ENEXTMATCH    V_ENEXTMATCH(1U)
+
+#define S_ENHASHUCAST    3
+#define V_ENHASHUCAST(x) ((x) << S_ENHASHUCAST)
+#define F_ENHASHUCAST    V_ENHASHUCAST(1U)
+
+#define S_ENHASHMCAST    2
+#define V_ENHASHMCAST(x) ((x) << S_ENHASHMCAST)
+#define F_ENHASHMCAST    V_ENHASHMCAST(1U)
+
+#define S_DISBCAST    1
+#define V_DISBCAST(x) ((x) << S_DISBCAST)
+#define F_DISBCAST    V_DISBCAST(1U)
+
+#define S_COPYALLFRAMES    0
+#define V_COPYALLFRAMES(x) ((x) << S_COPYALLFRAMES)
+#define F_COPYALLFRAMES    V_COPYALLFRAMES(1U)
+
+#define A_XGMAC_PORT_XGM_RX_HASH_LOW 0x1214
+#define A_XGMAC_PORT_XGM_RX_HASH_HIGH 0x1218
+#define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_1 0x121c
+#define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_1 0x1220
+
+#define S_ADDRESS_HIGH    0
+#define M_ADDRESS_HIGH    0xffffU
+#define V_ADDRESS_HIGH(x) ((x) << S_ADDRESS_HIGH)
+#define G_ADDRESS_HIGH(x) (((x) >> S_ADDRESS_HIGH) & M_ADDRESS_HIGH)
+
+#define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_2 0x1224
+#define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_2 0x1228
+#define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_3 0x122c
+#define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_3 0x1230
+#define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_4 0x1234
+#define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_4 0x1238
+#define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_5 0x123c
+#define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_5 0x1240
+#define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_6 0x1244
+#define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_6 0x1248
+#define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_7 0x124c
+#define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_7 0x1250
+#define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_8 0x1254
+#define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_8 0x1258
+#define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_1 0x125c
+
+#define S_ENTYPEMATCH    31
+#define V_ENTYPEMATCH(x) ((x) << S_ENTYPEMATCH)
+#define F_ENTYPEMATCH    V_ENTYPEMATCH(1U)
+
+#define S_TYPE    0
+#define M_TYPE    0xffffU
+#define V_TYPE(x) ((x) << S_TYPE)
+#define G_TYPE(x) (((x) >> S_TYPE) & M_TYPE)
+
+#define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_2 0x1260
+#define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_3 0x1264
+#define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_4 0x1268
+#define A_XGMAC_PORT_XGM_INT_STATUS 0x126c
+
+#define S_XGMIIEXTINT    10
+#define V_XGMIIEXTINT(x) ((x) << S_XGMIIEXTINT)
+#define F_XGMIIEXTINT    V_XGMIIEXTINT(1U)
+
+#define S_LINKFAULTCHANGE    9
+#define V_LINKFAULTCHANGE(x) ((x) << S_LINKFAULTCHANGE)
+#define F_LINKFAULTCHANGE    V_LINKFAULTCHANGE(1U)
+
+#define S_PHYFRAMECOMPLETE    8
+#define V_PHYFRAMECOMPLETE(x) ((x) << S_PHYFRAMECOMPLETE)
+#define F_PHYFRAMECOMPLETE    V_PHYFRAMECOMPLETE(1U)
+
+#define S_PAUSEFRAMETXMT    7
+#define V_PAUSEFRAMETXMT(x) ((x) << S_PAUSEFRAMETXMT)
+#define F_PAUSEFRAMETXMT    V_PAUSEFRAMETXMT(1U)
+
+#define S_PAUSECNTRTIMEOUT    6
+#define V_PAUSECNTRTIMEOUT(x) ((x) << S_PAUSECNTRTIMEOUT)
+#define F_PAUSECNTRTIMEOUT    V_PAUSECNTRTIMEOUT(1U)
+
+#define S_NON0PAUSERCVD    5
+#define V_NON0PAUSERCVD(x) ((x) << S_NON0PAUSERCVD)
+#define F_NON0PAUSERCVD    V_NON0PAUSERCVD(1U)
+
+#define S_STATOFLOW    4
+#define V_STATOFLOW(x) ((x) << S_STATOFLOW)
+#define F_STATOFLOW    V_STATOFLOW(1U)
+
+#define S_TXERRFIFO    3
+#define V_TXERRFIFO(x) ((x) << S_TXERRFIFO)
+#define F_TXERRFIFO    V_TXERRFIFO(1U)
+
+#define S_TXUFLOW    2
+#define V_TXUFLOW(x) ((x) << S_TXUFLOW)
+#define F_TXUFLOW    V_TXUFLOW(1U)
+
+#define S_FRAMETXMT    1
+#define V_FRAMETXMT(x) ((x) << S_FRAMETXMT)
+#define F_FRAMETXMT    V_FRAMETXMT(1U)
+
+#define S_FRAMERCVD    0
+#define V_FRAMERCVD(x) ((x) << S_FRAMERCVD)
+#define F_FRAMERCVD    V_FRAMERCVD(1U)
+
+#define A_XGMAC_PORT_XGM_INT_MASK 0x1270
+#define A_XGMAC_PORT_XGM_INT_EN 0x1274
+#define A_XGMAC_PORT_XGM_INT_DISABLE 0x1278
+#define A_XGMAC_PORT_XGM_TX_PAUSE_TIMER 0x127c
+
+#define S_CURPAUSETIMER    0
+#define M_CURPAUSETIMER    0xffffU
+#define V_CURPAUSETIMER(x) ((x) << S_CURPAUSETIMER)
+#define G_CURPAUSETIMER(x) (((x) >> S_CURPAUSETIMER) & M_CURPAUSETIMER)
+
+#define A_XGMAC_PORT_XGM_STAT_CTRL 0x1280
+
+#define S_READSNPSHOT    4
+#define V_READSNPSHOT(x) ((x) << S_READSNPSHOT)
+#define F_READSNPSHOT    V_READSNPSHOT(1U)
+
+#define S_TAKESNPSHOT    3
+#define V_TAKESNPSHOT(x) ((x) << S_TAKESNPSHOT)
+#define F_TAKESNPSHOT    V_TAKESNPSHOT(1U)
+
+#define S_CLRSTATS    2
+#define V_CLRSTATS(x) ((x) << S_CLRSTATS)
+#define F_CLRSTATS    V_CLRSTATS(1U)
+
+#define S_INCRSTATS    1
+#define V_INCRSTATS(x) ((x) << S_INCRSTATS)
+#define F_INCRSTATS    V_INCRSTATS(1U)
+
+#define S_ENTESTMODEWR    0
+#define V_ENTESTMODEWR(x) ((x) << S_ENTESTMODEWR)
+#define F_ENTESTMODEWR    V_ENTESTMODEWR(1U)
+
+#define A_XGMAC_PORT_XGM_MDIO_CTRL 0x1284
+
+#define S_FRAMETYPE    30
+#define M_FRAMETYPE    0x3U
+#define V_FRAMETYPE(x) ((x) << S_FRAMETYPE)
+#define G_FRAMETYPE(x) (((x) >> S_FRAMETYPE) & M_FRAMETYPE)
+
+#define S_OPERATION    28
+#define M_OPERATION    0x3U
+#define V_OPERATION(x) ((x) << S_OPERATION)
+#define G_OPERATION(x) (((x) >> S_OPERATION) & M_OPERATION)
+
+#define S_PORTADDR    23
+#define M_PORTADDR    0x1fU
+#define V_PORTADDR(x) ((x) << S_PORTADDR)
+#define G_PORTADDR(x) (((x) >> S_PORTADDR) & M_PORTADDR)
+
+#define S_DEVADDR    18
+#define M_DEVADDR    0x1fU
+#define V_DEVADDR(x) ((x) << S_DEVADDR)
+#define G_DEVADDR(x) (((x) >> S_DEVADDR) & M_DEVADDR)
+
+#define S_RESRV    16
+#define M_RESRV    0x3U
+#define V_RESRV(x) ((x) << S_RESRV)
+#define G_RESRV(x) (((x) >> S_RESRV) & M_RESRV)
+
+#define S_DATA    0
+#define M_DATA    0xffffU
+#define V_DATA(x) ((x) << S_DATA)
+#define G_DATA(x) (((x) >> S_DATA) & M_DATA)
+
+#define A_XGMAC_PORT_XGM_MODULE_ID 0x12fc
+
+#define S_MODULEID    16
+#define M_MODULEID    0xffffU
+#define V_MODULEID(x) ((x) << S_MODULEID)
+#define G_MODULEID(x) (((x) >> S_MODULEID) & M_MODULEID)
+
+#define S_MODULEREV    0
+#define M_MODULEREV    0xffffU
+#define V_MODULEREV(x) ((x) << S_MODULEREV)
+#define G_MODULEREV(x) (((x) >> S_MODULEREV) & M_MODULEREV)
+
+#define A_XGMAC_PORT_XGM_STAT_TX_BYTE_LOW 0x1300
+#define A_XGMAC_PORT_XGM_STAT_TX_BYTE_HIGH 0x1304
+
+#define S_TXBYTES_HIGH    0
+#define M_TXBYTES_HIGH    0x1fffU
+#define V_TXBYTES_HIGH(x) ((x) << S_TXBYTES_HIGH)
+#define G_TXBYTES_HIGH(x) (((x) >> S_TXBYTES_HIGH) & M_TXBYTES_HIGH)
+
+#define A_XGMAC_PORT_XGM_STAT_TX_FRAME_LOW 0x1308
+#define A_XGMAC_PORT_XGM_STAT_TX_FRAME_HIGH 0x130c
+
+#define S_TXFRAMES_HIGH    0
+#define M_TXFRAMES_HIGH    0xfU
+#define V_TXFRAMES_HIGH(x) ((x) << S_TXFRAMES_HIGH)
+#define G_TXFRAMES_HIGH(x) (((x) >> S_TXFRAMES_HIGH) & M_TXFRAMES_HIGH)
+
+#define A_XGMAC_PORT_XGM_STAT_TX_BCAST 0x1310
+#define A_XGMAC_PORT_XGM_STAT_TX_MCAST 0x1314
+#define A_XGMAC_PORT_XGM_STAT_TX_PAUSE 0x1318
+#define A_XGMAC_PORT_XGM_STAT_TX_64B_FRAMES 0x131c
+#define A_XGMAC_PORT_XGM_STAT_TX_65_127B_FRAMES 0x1320
+#define A_XGMAC_PORT_XGM_STAT_TX_128_255B_FRAMES 0x1324
+#define A_XGMAC_PORT_XGM_STAT_TX_256_511B_FRAMES 0x1328
+#define A_XGMAC_PORT_XGM_STAT_TX_512_1023B_FRAMES 0x132c
+#define A_XGMAC_PORT_XGM_STAT_TX_1024_1518B_FRAMES 0x1330
+#define A_XGMAC_PORT_XGM_STAT_TX_1519_MAXB_FRAMES 0x1334
+#define A_XGMAC_PORT_XGM_STAT_TX_ERR_FRAMES 0x1338
+#define A_XGMAC_PORT_XGM_STAT_RX_BYTES_LOW 0x133c
+#define A_XGMAC_PORT_XGM_STAT_RX_BYTES_HIGH 0x1340
+
+#define S_RXBYTES_HIGH    0
+#define M_RXBYTES_HIGH    0x1fffU
+#define V_RXBYTES_HIGH(x) ((x) << S_RXBYTES_HIGH)
+#define G_RXBYTES_HIGH(x) (((x) >> S_RXBYTES_HIGH) & M_RXBYTES_HIGH)
+
+#define A_XGMAC_PORT_XGM_STAT_RX_FRAMES_LOW 0x1344
+#define A_XGMAC_PORT_XGM_STAT_RX_FRAMES_HIGH 0x1348
+
+#define S_RXFRAMES_HIGH    0
+#define M_RXFRAMES_HIGH    0xfU
+#define V_RXFRAMES_HIGH(x) ((x) << S_RXFRAMES_HIGH)
+#define G_RXFRAMES_HIGH(x) (((x) >> S_RXFRAMES_HIGH) & M_RXFRAMES_HIGH)
+
+#define A_XGMAC_PORT_XGM_STAT_RX_BCAST_FRAMES 0x134c
+#define A_XGMAC_PORT_XGM_STAT_RX_MCAST_FRAMES 0x1350
+#define A_XGMAC_PORT_XGM_STAT_RX_PAUSE_FRAMES 0x1354
+
+#define S_RXPAUSEFRAMES    0
+#define M_RXPAUSEFRAMES    0xffffU
+#define V_RXPAUSEFRAMES(x) ((x) << S_RXPAUSEFRAMES)
+#define G_RXPAUSEFRAMES(x) (((x) >> S_RXPAUSEFRAMES) & M_RXPAUSEFRAMES)
+
+#define A_XGMAC_PORT_XGM_STAT_RX_64B_FRAMES 0x1358
+#define A_XGMAC_PORT_XGM_STAT_RX_65_127B_FRAMES 0x135c
+#define A_XGMAC_PORT_XGM_STAT_RX_128_255B_FRAMES 0x1360
+#define A_XGMAC_PORT_XGM_STAT_RX_256_511B_FRAMES 0x1364
+#define A_XGMAC_PORT_XGM_STAT_RX_512_1023B_FRAMES 0x1368
+#define A_XGMAC_PORT_XGM_STAT_RX_1024_1518B_FRAMES 0x136c
+#define A_XGMAC_PORT_XGM_STAT_RX_1519_MAXB_FRAMES 0x1370
+#define A_XGMAC_PORT_XGM_STAT_RX_SHORT_FRAMES 0x1374
+
+#define S_RXSHORTFRAMES    0
+#define M_RXSHORTFRAMES    0xffffU
+#define V_RXSHORTFRAMES(x) ((x) << S_RXSHORTFRAMES)
+#define G_RXSHORTFRAMES(x) (((x) >> S_RXSHORTFRAMES) & M_RXSHORTFRAMES)
+
+#define A_XGMAC_PORT_XGM_STAT_RX_OVERSIZE_FRAMES 0x1378
+
+#define S_RXOVERSIZEFRAMES    0
+#define M_RXOVERSIZEFRAMES    0xffffU
+#define V_RXOVERSIZEFRAMES(x) ((x) << S_RXOVERSIZEFRAMES)
+#define G_RXOVERSIZEFRAMES(x) (((x) >> S_RXOVERSIZEFRAMES) & M_RXOVERSIZEFRAMES)
+
+#define A_XGMAC_PORT_XGM_STAT_RX_JABBER_FRAMES 0x137c
+
+#define S_RXJABBERFRAMES    0
+#define M_RXJABBERFRAMES    0xffffU
+#define V_RXJABBERFRAMES(x) ((x) << S_RXJABBERFRAMES)
+#define G_RXJABBERFRAMES(x) (((x) >> S_RXJABBERFRAMES) & M_RXJABBERFRAMES)
+
+#define A_XGMAC_PORT_XGM_STAT_RX_CRC_ERR_FRAMES 0x1380
+
+#define S_RXCRCERRFRAMES    0
+#define M_RXCRCERRFRAMES    0xffffU
+#define V_RXCRCERRFRAMES(x) ((x) << S_RXCRCERRFRAMES)
+#define G_RXCRCERRFRAMES(x) (((x) >> S_RXCRCERRFRAMES) & M_RXCRCERRFRAMES)
+
+#define A_XGMAC_PORT_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x1384
+
+#define S_RXLENGTHERRFRAMES    0
+#define M_RXLENGTHERRFRAMES    0xffffU
+#define V_RXLENGTHERRFRAMES(x) ((x) << S_RXLENGTHERRFRAMES)
+#define G_RXLENGTHERRFRAMES(x) (((x) >> S_RXLENGTHERRFRAMES) & M_RXLENGTHERRFRAMES)
+
+#define A_XGMAC_PORT_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x1388
+
+#define S_RXSYMCODEERRFRAMES    0
+#define M_RXSYMCODEERRFRAMES    0xffffU
+#define V_RXSYMCODEERRFRAMES(x) ((x) << S_RXSYMCODEERRFRAMES)
+#define G_RXSYMCODEERRFRAMES(x) (((x) >> S_RXSYMCODEERRFRAMES) & M_RXSYMCODEERRFRAMES)
+
+#define A_XGMAC_PORT_XAUI_CTRL 0x1400
+
+#define S_POLARITY_INV_RX    8
+#define M_POLARITY_INV_RX    0xfU
+#define V_POLARITY_INV_RX(x) ((x) << S_POLARITY_INV_RX)
+#define G_POLARITY_INV_RX(x) (((x) >> S_POLARITY_INV_RX) & M_POLARITY_INV_RX)
+
+#define S_POLARITY_INV_TX    4
+#define M_POLARITY_INV_TX    0xfU
+#define V_POLARITY_INV_TX(x) ((x) << S_POLARITY_INV_TX)
+#define G_POLARITY_INV_TX(x) (((x) >> S_POLARITY_INV_TX) & M_POLARITY_INV_TX)
+
+#define S_TEST_SEL    2
+#define M_TEST_SEL    0x3U
+#define V_TEST_SEL(x) ((x) << S_TEST_SEL)
+#define G_TEST_SEL(x) (((x) >> S_TEST_SEL) & M_TEST_SEL)
+
+#define S_TEST_EN    0
+#define V_TEST_EN(x) ((x) << S_TEST_EN)
+#define F_TEST_EN    V_TEST_EN(1U)
+
+#define A_XGMAC_PORT_XAUI_STATUS 0x1404
+
+#define S_DECODE_ERROR    12
+#define M_DECODE_ERROR    0xffU
+#define V_DECODE_ERROR(x) ((x) << S_DECODE_ERROR)
+#define G_DECODE_ERROR(x) (((x) >> S_DECODE_ERROR) & M_DECODE_ERROR)
+
+#define S_LANE3_CTC_STATUS    11
+#define V_LANE3_CTC_STATUS(x) ((x) << S_LANE3_CTC_STATUS)
+#define F_LANE3_CTC_STATUS    V_LANE3_CTC_STATUS(1U)
+
+#define S_LANE2_CTC_STATUS    10
+#define V_LANE2_CTC_STATUS(x) ((x) << S_LANE2_CTC_STATUS)
+#define F_LANE2_CTC_STATUS    V_LANE2_CTC_STATUS(1U)
+
+#define S_LANE1_CTC_STATUS    9
+#define V_LANE1_CTC_STATUS(x) ((x) << S_LANE1_CTC_STATUS)
+#define F_LANE1_CTC_STATUS    V_LANE1_CTC_STATUS(1U)
+
+#define S_LANE0_CTC_STATUS    8
+#define V_LANE0_CTC_STATUS(x) ((x) << S_LANE0_CTC_STATUS)
+#define F_LANE0_CTC_STATUS    V_LANE0_CTC_STATUS(1U)
+
+#define S_ALIGN_STATUS    4
+#define V_ALIGN_STATUS(x) ((x) << S_ALIGN_STATUS)
+#define F_ALIGN_STATUS    V_ALIGN_STATUS(1U)
+
+#define S_LANE3_SYNC_STATUS    3
+#define V_LANE3_SYNC_STATUS(x) ((x) << S_LANE3_SYNC_STATUS)
+#define F_LANE3_SYNC_STATUS    V_LANE3_SYNC_STATUS(1U)
+
+#define S_LANE2_SYNC_STATUS    2
+#define V_LANE2_SYNC_STATUS(x) ((x) << S_LANE2_SYNC_STATUS)
+#define F_LANE2_SYNC_STATUS    V_LANE2_SYNC_STATUS(1U)
+
+#define S_LANE1_SYNC_STATUS    1
+#define V_LANE1_SYNC_STATUS(x) ((x) << S_LANE1_SYNC_STATUS)
+#define F_LANE1_SYNC_STATUS    V_LANE1_SYNC_STATUS(1U)
+
+#define S_LANE0_SYNC_STATUS    0
+#define V_LANE0_SYNC_STATUS(x) ((x) << S_LANE0_SYNC_STATUS)
+#define F_LANE0_SYNC_STATUS    V_LANE0_SYNC_STATUS(1U)
+
+#define A_XGMAC_PORT_PCSR_CTRL 0x1500
+
+#define S_RX_CLK_SPEED    7
+#define V_RX_CLK_SPEED(x) ((x) << S_RX_CLK_SPEED)
+#define F_RX_CLK_SPEED    V_RX_CLK_SPEED(1U)
+
+#define S_SCRBYPASS    6
+#define V_SCRBYPASS(x) ((x) << S_SCRBYPASS)
+#define F_SCRBYPASS    V_SCRBYPASS(1U)
+
+#define S_FECERRINDEN    5
+#define V_FECERRINDEN(x) ((x) << S_FECERRINDEN)
+#define F_FECERRINDEN    V_FECERRINDEN(1U)
+
+#define S_FECEN    4
+#define V_FECEN(x) ((x) << S_FECEN)
+#define F_FECEN    V_FECEN(1U)
+
+#define S_TESTSEL    2
+#define M_TESTSEL    0x3U
+#define V_TESTSEL(x) ((x) << S_TESTSEL)
+#define G_TESTSEL(x) (((x) >> S_TESTSEL) & M_TESTSEL)
+
+#define S_SCRLOOPEN    1
+#define V_SCRLOOPEN(x) ((x) << S_SCRLOOPEN)
+#define F_SCRLOOPEN    V_SCRLOOPEN(1U)
+
+#define S_XGMIILOOPEN    0
+#define V_XGMIILOOPEN(x) ((x) << S_XGMIILOOPEN)
+#define F_XGMIILOOPEN    V_XGMIILOOPEN(1U)
+
+#define A_XGMAC_PORT_PCSR_TXTEST_CTRL 0x1510
+
+#define S_TX_PRBS9_EN    4
+#define V_TX_PRBS9_EN(x) ((x) << S_TX_PRBS9_EN)
+#define F_TX_PRBS9_EN    V_TX_PRBS9_EN(1U)
+
+#define S_TX_PRBS31_EN    3
+#define V_TX_PRBS31_EN(x) ((x) << S_TX_PRBS31_EN)
+#define F_TX_PRBS31_EN    V_TX_PRBS31_EN(1U)
+
+#define S_TX_TST_DAT_SEL    2
+#define V_TX_TST_DAT_SEL(x) ((x) << S_TX_TST_DAT_SEL)
+#define F_TX_TST_DAT_SEL    V_TX_TST_DAT_SEL(1U)
+
+#define S_TX_TST_SEL    1
+#define V_TX_TST_SEL(x) ((x) << S_TX_TST_SEL)
+#define F_TX_TST_SEL    V_TX_TST_SEL(1U)
+
+#define S_TX_TST_EN    0
+#define V_TX_TST_EN(x) ((x) << S_TX_TST_EN)
+#define F_TX_TST_EN    V_TX_TST_EN(1U)
+
+#define A_XGMAC_PORT_PCSR_TXTEST_SEEDA_LOWER 0x1514
+#define A_XGMAC_PORT_PCSR_TXTEST_SEEDA_UPPER 0x1518
+
+#define S_SEEDA_UPPER    0
+#define M_SEEDA_UPPER    0x3ffffffU
+#define V_SEEDA_UPPER(x) ((x) << S_SEEDA_UPPER)
+#define G_SEEDA_UPPER(x) (((x) >> S_SEEDA_UPPER) & M_SEEDA_UPPER)
+
+#define A_XGMAC_PORT_PCSR_TXTEST_SEEDB_LOWER 0x152c
+#define A_XGMAC_PORT_PCSR_TXTEST_SEEDB_UPPER 0x1530
+
+#define S_SEEDB_UPPER    0
+#define M_SEEDB_UPPER    0x3ffffffU
+#define V_SEEDB_UPPER(x) ((x) << S_SEEDB_UPPER)
+#define G_SEEDB_UPPER(x) (((x) >> S_SEEDB_UPPER) & M_SEEDB_UPPER)
+
+#define A_XGMAC_PORT_PCSR_RXTEST_CTRL 0x153c
+
+#define S_TPTER_CNT_RST    7
+#define V_TPTER_CNT_RST(x) ((x) << S_TPTER_CNT_RST)
+#define F_TPTER_CNT_RST    V_TPTER_CNT_RST(1U)
+
+#define S_TEST_CNT_125US    6
+#define V_TEST_CNT_125US(x) ((x) << S_TEST_CNT_125US)
+#define F_TEST_CNT_125US    V_TEST_CNT_125US(1U)
+
+#define S_TEST_CNT_PRE    5
+#define V_TEST_CNT_PRE(x) ((x) << S_TEST_CNT_PRE)
+#define F_TEST_CNT_PRE    V_TEST_CNT_PRE(1U)
+
+#define S_BER_CNT_RST    4
+#define V_BER_CNT_RST(x) ((x) << S_BER_CNT_RST)
+#define F_BER_CNT_RST    V_BER_CNT_RST(1U)
+
+#define S_ERR_BLK_CNT_RST    3
+#define V_ERR_BLK_CNT_RST(x) ((x) << S_ERR_BLK_CNT_RST)
+#define F_ERR_BLK_CNT_RST    V_ERR_BLK_CNT_RST(1U)
+
+#define S_RX_PRBS31_EN    2
+#define V_RX_PRBS31_EN(x) ((x) << S_RX_PRBS31_EN)
+#define F_RX_PRBS31_EN    V_RX_PRBS31_EN(1U)
+
+#define S_RX_TST_DAT_SEL    1
+#define V_RX_TST_DAT_SEL(x) ((x) << S_RX_TST_DAT_SEL)
+#define F_RX_TST_DAT_SEL    V_RX_TST_DAT_SEL(1U)
+
+#define S_RX_TST_EN    0
+#define V_RX_TST_EN(x) ((x) << S_RX_TST_EN)
+#define F_RX_TST_EN    V_RX_TST_EN(1U)
+
+#define A_XGMAC_PORT_PCSR_STATUS 0x1550
+
+#define S_ERR_BLK_CNT    16
+#define M_ERR_BLK_CNT    0xffU
+#define V_ERR_BLK_CNT(x) ((x) << S_ERR_BLK_CNT)
+#define G_ERR_BLK_CNT(x) (((x) >> S_ERR_BLK_CNT) & M_ERR_BLK_CNT)
+
+#define S_BER_COUNT    8
+#define M_BER_COUNT    0x3fU
+#define V_BER_COUNT(x) ((x) << S_BER_COUNT)
+#define G_BER_COUNT(x) (((x) >> S_BER_COUNT) & M_BER_COUNT)
+
+#define S_HI_BER    2
+#define V_HI_BER(x) ((x) << S_HI_BER)
+#define F_HI_BER    V_HI_BER(1U)
+
+#define S_RX_FAULT    1
+#define V_RX_FAULT(x) ((x) << S_RX_FAULT)
+#define F_RX_FAULT    V_RX_FAULT(1U)
+
+#define S_TX_FAULT    0
+#define V_TX_FAULT(x) ((x) << S_TX_FAULT)
+#define F_TX_FAULT    V_TX_FAULT(1U)
+
+#define A_XGMAC_PORT_PCSR_TEST_STATUS 0x1554
+
+#define S_TPT_ERR_CNT    0
+#define M_TPT_ERR_CNT    0xffffU
+#define V_TPT_ERR_CNT(x) ((x) << S_TPT_ERR_CNT)
+#define G_TPT_ERR_CNT(x) (((x) >> S_TPT_ERR_CNT) & M_TPT_ERR_CNT)
+
+#define A_XGMAC_PORT_AN_CONTROL 0x1600
+
+#define S_SOFT_RESET    15
+#define V_SOFT_RESET(x) ((x) << S_SOFT_RESET)
+#define F_SOFT_RESET    V_SOFT_RESET(1U)
+
+#define S_AN_ENABLE    12
+#define V_AN_ENABLE(x) ((x) << S_AN_ENABLE)
+#define F_AN_ENABLE    V_AN_ENABLE(1U)
+
+#define S_RESTART_AN    9
+#define V_RESTART_AN(x) ((x) << S_RESTART_AN)
+#define F_RESTART_AN    V_RESTART_AN(1U)
+
+#define A_XGMAC_PORT_AN_STATUS 0x1604
+
+#define S_NONCER_MATCH    31
+#define V_NONCER_MATCH(x) ((x) << S_NONCER_MATCH)
+#define F_NONCER_MATCH    V_NONCER_MATCH(1U)
+
+#define S_PARALLEL_DET_FAULT    9
+#define V_PARALLEL_DET_FAULT(x) ((x) << S_PARALLEL_DET_FAULT)
+#define F_PARALLEL_DET_FAULT    V_PARALLEL_DET_FAULT(1U)
+
+#define S_PAGE_RECEIVED    6
+#define V_PAGE_RECEIVED(x) ((x) << S_PAGE_RECEIVED)
+#define F_PAGE_RECEIVED    V_PAGE_RECEIVED(1U)
+
+#define S_AN_COMPLETE    5
+#define V_AN_COMPLETE(x) ((x) << S_AN_COMPLETE)
+#define F_AN_COMPLETE    V_AN_COMPLETE(1U)
+
+#define S_STAT_REMFAULT    4
+#define V_STAT_REMFAULT(x) ((x) << S_STAT_REMFAULT)
+#define F_STAT_REMFAULT    V_STAT_REMFAULT(1U)
+
+#define S_AN_ABILITY    3
+#define V_AN_ABILITY(x) ((x) << S_AN_ABILITY)
+#define F_AN_ABILITY    V_AN_ABILITY(1U)
+
+#define S_LINK_STATUS    2
+#define V_LINK_STATUS(x) ((x) << S_LINK_STATUS)
+#define F_LINK_STATUS    V_LINK_STATUS(1U)
+
+#define S_PARTNER_AN_ABILITY    0
+#define V_PARTNER_AN_ABILITY(x) ((x) << S_PARTNER_AN_ABILITY)
+#define F_PARTNER_AN_ABILITY    V_PARTNER_AN_ABILITY(1U)
+
+#define A_XGMAC_PORT_AN_ADVERTISEMENT 0x1608
+
+#define S_FEC_ENABLE    31
+#define V_FEC_ENABLE(x) ((x) << S_FEC_ENABLE)
+#define F_FEC_ENABLE    V_FEC_ENABLE(1U)
+
+#define S_FEC_ABILITY    30
+#define V_FEC_ABILITY(x) ((x) << S_FEC_ABILITY)
+#define F_FEC_ABILITY    V_FEC_ABILITY(1U)
+
+#define S_10GBASE_KR_CAPABLE    23
+#define V_10GBASE_KR_CAPABLE(x) ((x) << S_10GBASE_KR_CAPABLE)
+#define F_10GBASE_KR_CAPABLE    V_10GBASE_KR_CAPABLE(1U)
+
+#define S_10GBASE_KX4_CAPABLE    22
+#define V_10GBASE_KX4_CAPABLE(x) ((x) << S_10GBASE_KX4_CAPABLE)
+#define F_10GBASE_KX4_CAPABLE    V_10GBASE_KX4_CAPABLE(1U)
+
+#define S_1000BASE_KX_CAPABLE    21
+#define V_1000BASE_KX_CAPABLE(x) ((x) << S_1000BASE_KX_CAPABLE)
+#define F_1000BASE_KX_CAPABLE    V_1000BASE_KX_CAPABLE(1U)
+
+#define S_TRANSMITTED_NONCE    16
+#define M_TRANSMITTED_NONCE    0x1fU
+#define V_TRANSMITTED_NONCE(x) ((x) << S_TRANSMITTED_NONCE)
+#define G_TRANSMITTED_NONCE(x) (((x) >> S_TRANSMITTED_NONCE) & M_TRANSMITTED_NONCE)
+
+#define S_NP    15
+#define V_NP(x) ((x) << S_NP)
+#define F_NP    V_NP(1U)
+
+#define S_ACK    14
+#define V_ACK(x) ((x) << S_ACK)
+#define F_ACK    V_ACK(1U)
+
+#define S_REMOTE_FAULT    13
+#define V_REMOTE_FAULT(x) ((x) << S_REMOTE_FAULT)
+#define F_REMOTE_FAULT    V_REMOTE_FAULT(1U)
+
+#define S_ASM_DIR    11
+#define V_ASM_DIR(x) ((x) << S_ASM_DIR)
+#define F_ASM_DIR    V_ASM_DIR(1U)
+
+#define S_PAUSE    10
+#define V_PAUSE(x) ((x) << S_PAUSE)
+#define F_PAUSE    V_PAUSE(1U)
+
+#define S_ECHOED_NONCE    5
+#define M_ECHOED_NONCE    0x1fU
+#define V_ECHOED_NONCE(x) ((x) << S_ECHOED_NONCE)
+#define G_ECHOED_NONCE(x) (((x) >> S_ECHOED_NONCE) & M_ECHOED_NONCE)
+
+#define A_XGMAC_PORT_AN_LINK_PARTNER_ABILITY 0x160c
+
+#define S_SELECTOR_FIELD    0
+#define M_SELECTOR_FIELD    0x1fU
+#define V_SELECTOR_FIELD(x) ((x) << S_SELECTOR_FIELD)
+#define G_SELECTOR_FIELD(x) (((x) >> S_SELECTOR_FIELD) & M_SELECTOR_FIELD)
+
+#define A_XGMAC_PORT_AN_NP_LOWER_TRANSMIT 0x1610
+
+#define S_NP_INFO    16
+#define M_NP_INFO    0xffffU
+#define V_NP_INFO(x) ((x) << S_NP_INFO)
+#define G_NP_INFO(x) (((x) >> S_NP_INFO) & M_NP_INFO)
+
+#define S_NP_INDICATION    15
+#define V_NP_INDICATION(x) ((x) << S_NP_INDICATION)
+#define F_NP_INDICATION    V_NP_INDICATION(1U)
+
+#define S_MESSAGE_PAGE    13
+#define V_MESSAGE_PAGE(x) ((x) << S_MESSAGE_PAGE)
+#define F_MESSAGE_PAGE    V_MESSAGE_PAGE(1U)
+
+#define S_ACK_2    12
+#define V_ACK_2(x) ((x) << S_ACK_2)
+#define F_ACK_2    V_ACK_2(1U)
+
+#define S_TOGGLE    11
+#define V_TOGGLE(x) ((x) << S_TOGGLE)
+#define F_TOGGLE    V_TOGGLE(1U)
+
+#define A_XGMAC_PORT_AN_NP_UPPER_TRANSMIT 0x1614
+
+#define S_NP_INFO_HI    0
+#define M_NP_INFO_HI    0xffffU
+#define V_NP_INFO_HI(x) ((x) << S_NP_INFO_HI)
+#define G_NP_INFO_HI(x) (((x) >> S_NP_INFO_HI) & M_NP_INFO_HI)
+
+#define A_XGMAC_PORT_AN_LP_NP_LOWER 0x1618
+#define A_XGMAC_PORT_AN_LP_NP_UPPER 0x161c
+#define A_XGMAC_PORT_AN_BACKPLANE_ETHERNET_STATUS 0x1624
+
+#define S_TX_PAUSE_OKAY    6
+#define V_TX_PAUSE_OKAY(x) ((x) << S_TX_PAUSE_OKAY)
+#define F_TX_PAUSE_OKAY    V_TX_PAUSE_OKAY(1U)
+
+#define S_RX_PAUSE_OKAY    5
+#define V_RX_PAUSE_OKAY(x) ((x) << S_RX_PAUSE_OKAY)
+#define F_RX_PAUSE_OKAY    V_RX_PAUSE_OKAY(1U)
+
+#define S_10GBASE_KR_FEC_NEG    4
+#define V_10GBASE_KR_FEC_NEG(x) ((x) << S_10GBASE_KR_FEC_NEG)
+#define F_10GBASE_KR_FEC_NEG    V_10GBASE_KR_FEC_NEG(1U)
+
+#define S_10GBASE_KR_NEG    3
+#define V_10GBASE_KR_NEG(x) ((x) << S_10GBASE_KR_NEG)
+#define F_10GBASE_KR_NEG    V_10GBASE_KR_NEG(1U)
+
+#define S_10GBASE_KX4_NEG    2
+#define V_10GBASE_KX4_NEG(x) ((x) << S_10GBASE_KX4_NEG)
+#define F_10GBASE_KX4_NEG    V_10GBASE_KX4_NEG(1U)
+
+#define S_1000BASE_KX_NEG    1
+#define V_1000BASE_KX_NEG(x) ((x) << S_1000BASE_KX_NEG)
+#define F_1000BASE_KX_NEG    V_1000BASE_KX_NEG(1U)
+
+#define S_BP_AN_ABILITY    0
+#define V_BP_AN_ABILITY(x) ((x) << S_BP_AN_ABILITY)
+#define F_BP_AN_ABILITY    V_BP_AN_ABILITY(1U)
+
+#define A_XGMAC_PORT_AN_TX_NONCE_CONTROL 0x1628
+
+#define S_BYPASS_LFSR    15
+#define V_BYPASS_LFSR(x) ((x) << S_BYPASS_LFSR)
+#define F_BYPASS_LFSR    V_BYPASS_LFSR(1U)
+
+#define S_LFSR_INIT    0
+#define M_LFSR_INIT    0x7fffU
+#define V_LFSR_INIT(x) ((x) << S_LFSR_INIT)
+#define G_LFSR_INIT(x) (((x) >> S_LFSR_INIT) & M_LFSR_INIT)
+
+#define A_XGMAC_PORT_AN_INTERRUPT_STATUS 0x162c
+
+#define S_NP_FROM_LP    3
+#define V_NP_FROM_LP(x) ((x) << S_NP_FROM_LP)
+#define F_NP_FROM_LP    V_NP_FROM_LP(1U)
+
+#define S_PARALLELDETFAULTINT    2
+#define V_PARALLELDETFAULTINT(x) ((x) << S_PARALLELDETFAULTINT)
+#define F_PARALLELDETFAULTINT    V_PARALLELDETFAULTINT(1U)
+
+#define S_BP_FROM_LP    1
+#define V_BP_FROM_LP(x) ((x) << S_BP_FROM_LP)
+#define F_BP_FROM_LP    V_BP_FROM_LP(1U)
+
+#define S_PCS_AN_COMPLETE    0
+#define V_PCS_AN_COMPLETE(x) ((x) << S_PCS_AN_COMPLETE)
+#define F_PCS_AN_COMPLETE    V_PCS_AN_COMPLETE(1U)
+
+#define A_XGMAC_PORT_AN_GENERIC_TIMER_TIMEOUT 0x1630
+
+#define S_GENERIC_TIMEOUT    0
+#define M_GENERIC_TIMEOUT    0x7fffffU
+#define V_GENERIC_TIMEOUT(x) ((x) << S_GENERIC_TIMEOUT)
+#define G_GENERIC_TIMEOUT(x) (((x) >> S_GENERIC_TIMEOUT) & M_GENERIC_TIMEOUT)
+
+#define A_XGMAC_PORT_AN_BREAK_LINK_TIMEOUT 0x1634
+
+#define S_BREAK_LINK_TIMEOUT    0
+#define M_BREAK_LINK_TIMEOUT    0xffffffU
+#define V_BREAK_LINK_TIMEOUT(x) ((x) << S_BREAK_LINK_TIMEOUT)
+#define G_BREAK_LINK_TIMEOUT(x) (((x) >> S_BREAK_LINK_TIMEOUT) & M_BREAK_LINK_TIMEOUT)
+
+#define A_XGMAC_PORT_AN_MODULE_ID 0x163c
+
+#define S_MODULE_ID    16
+#define M_MODULE_ID    0xffffU
+#define V_MODULE_ID(x) ((x) << S_MODULE_ID)
+#define G_MODULE_ID(x) (((x) >> S_MODULE_ID) & M_MODULE_ID)
+
+#define S_MODULE_REVISION    0
+#define M_MODULE_REVISION    0xffffU
+#define V_MODULE_REVISION(x) ((x) << S_MODULE_REVISION)
+#define G_MODULE_REVISION(x) (((x) >> S_MODULE_REVISION) & M_MODULE_REVISION)
+
+#define A_XGMAC_PORT_AE_RX_COEF_REQ 0x1700
+
+#define S_RXREQ_CPRE    13
+#define V_RXREQ_CPRE(x) ((x) << S_RXREQ_CPRE)
+#define F_RXREQ_CPRE    V_RXREQ_CPRE(1U)
+
+#define S_RXREQ_CINIT    12
+#define V_RXREQ_CINIT(x) ((x) << S_RXREQ_CINIT)
+#define F_RXREQ_CINIT    V_RXREQ_CINIT(1U)
+
+#define S_RXREQ_C0    4
+#define M_RXREQ_C0    0x3U
+#define V_RXREQ_C0(x) ((x) << S_RXREQ_C0)
+#define G_RXREQ_C0(x) (((x) >> S_RXREQ_C0) & M_RXREQ_C0)
+
+#define S_RXREQ_C1    2
+#define M_RXREQ_C1    0x3U
+#define V_RXREQ_C1(x) ((x) << S_RXREQ_C1)
+#define G_RXREQ_C1(x) (((x) >> S_RXREQ_C1) & M_RXREQ_C1)
+
+#define S_RXREQ_C2    0
+#define M_RXREQ_C2    0x3U
+#define V_RXREQ_C2(x) ((x) << S_RXREQ_C2)
+#define G_RXREQ_C2(x) (((x) >> S_RXREQ_C2) & M_RXREQ_C2)
+
+#define A_XGMAC_PORT_AE_RX_COEF_STAT 0x1704
+
+#define S_RXSTAT_RDY    15
+#define V_RXSTAT_RDY(x) ((x) << S_RXSTAT_RDY)
+#define F_RXSTAT_RDY    V_RXSTAT_RDY(1U)
+
+#define S_RXSTAT_C0    4
+#define M_RXSTAT_C0    0x3U
+#define V_RXSTAT_C0(x) ((x) << S_RXSTAT_C0)
+#define G_RXSTAT_C0(x) (((x) >> S_RXSTAT_C0) & M_RXSTAT_C0)
+
+#define S_RXSTAT_C1    2
+#define M_RXSTAT_C1    0x3U
+#define V_RXSTAT_C1(x) ((x) << S_RXSTAT_C1)
+#define G_RXSTAT_C1(x) (((x) >> S_RXSTAT_C1) & M_RXSTAT_C1)
+
+#define S_RXSTAT_C2    0
+#define M_RXSTAT_C2    0x3U
+#define V_RXSTAT_C2(x) ((x) << S_RXSTAT_C2)
+#define G_RXSTAT_C2(x) (((x) >> S_RXSTAT_C2) & M_RXSTAT_C2)
+
+#define A_XGMAC_PORT_AE_TX_COEF_REQ 0x1708
+
+#define S_TXREQ_CPRE    13
+#define V_TXREQ_CPRE(x) ((x) << S_TXREQ_CPRE)
+#define F_TXREQ_CPRE    V_TXREQ_CPRE(1U)
+
+#define S_TXREQ_CINIT    12
+#define V_TXREQ_CINIT(x) ((x) << S_TXREQ_CINIT)
+#define F_TXREQ_CINIT    V_TXREQ_CINIT(1U)
+
+#define S_TXREQ_C0    4
+#define M_TXREQ_C0    0x3U
+#define V_TXREQ_C0(x) ((x) << S_TXREQ_C0)
+#define G_TXREQ_C0(x) (((x) >> S_TXREQ_C0) & M_TXREQ_C0)
+
+#define S_TXREQ_C1    2
+#define M_TXREQ_C1    0x3U
+#define V_TXREQ_C1(x) ((x) << S_TXREQ_C1)
+#define G_TXREQ_C1(x) (((x) >> S_TXREQ_C1) & M_TXREQ_C1)
+
+#define S_TXREQ_C2    0
+#define M_TXREQ_C2    0x3U
+#define V_TXREQ_C2(x) ((x) << S_TXREQ_C2)
+#define G_TXREQ_C2(x) (((x) >> S_TXREQ_C2) & M_TXREQ_C2)
+
+#define A_XGMAC_PORT_AE_TX_COEF_STAT 0x170c
+
+#define S_TXSTAT_RDY    15
+#define V_TXSTAT_RDY(x) ((x) << S_TXSTAT_RDY)
+#define F_TXSTAT_RDY    V_TXSTAT_RDY(1U)
+
+#define S_TXSTAT_C0    4
+#define M_TXSTAT_C0    0x3U
+#define V_TXSTAT_C0(x) ((x) << S_TXSTAT_C0)
+#define G_TXSTAT_C0(x) (((x) >> S_TXSTAT_C0) & M_TXSTAT_C0)
+
+#define S_TXSTAT_C1    2
+#define M_TXSTAT_C1    0x3U
+#define V_TXSTAT_C1(x) ((x) << S_TXSTAT_C1)
+#define G_TXSTAT_C1(x) (((x) >> S_TXSTAT_C1) & M_TXSTAT_C1)
+
+#define S_TXSTAT_C2    0
+#define M_TXSTAT_C2    0x3U
+#define V_TXSTAT_C2(x) ((x) << S_TXSTAT_C2)
+#define G_TXSTAT_C2(x) (((x) >> S_TXSTAT_C2) & M_TXSTAT_C2)
+
+#define A_XGMAC_PORT_AE_REG_MODE 0x1710
+
+#define S_MAN_DEC    4
+#define M_MAN_DEC    0x3U
+#define V_MAN_DEC(x) ((x) << S_MAN_DEC)
+#define G_MAN_DEC(x) (((x) >> S_MAN_DEC) & M_MAN_DEC)
+
+#define S_MANUAL_RDY    3
+#define V_MANUAL_RDY(x) ((x) << S_MANUAL_RDY)
+#define F_MANUAL_RDY    V_MANUAL_RDY(1U)
+
+#define S_MWT_DISABLE    2
+#define V_MWT_DISABLE(x) ((x) << S_MWT_DISABLE)
+#define F_MWT_DISABLE    V_MWT_DISABLE(1U)
+
+#define S_MDIO_OVR    1
+#define V_MDIO_OVR(x) ((x) << S_MDIO_OVR)
+#define F_MDIO_OVR    V_MDIO_OVR(1U)
+
+#define S_STICKY_MODE    0
+#define V_STICKY_MODE(x) ((x) << S_STICKY_MODE)
+#define F_STICKY_MODE    V_STICKY_MODE(1U)
+
+#define A_XGMAC_PORT_AE_PRBS_CTL 0x1714
+
+#define S_PRBS_CHK_ERRCNT    8
+#define M_PRBS_CHK_ERRCNT    0xffU
+#define V_PRBS_CHK_ERRCNT(x) ((x) << S_PRBS_CHK_ERRCNT)
+#define G_PRBS_CHK_ERRCNT(x) (((x) >> S_PRBS_CHK_ERRCNT) & M_PRBS_CHK_ERRCNT)
+
+#define S_PRBS_SYNCCNT    5
+#define M_PRBS_SYNCCNT    0x7U
+#define V_PRBS_SYNCCNT(x) ((x) << S_PRBS_SYNCCNT)
+#define G_PRBS_SYNCCNT(x) (((x) >> S_PRBS_SYNCCNT) & M_PRBS_SYNCCNT)
+
+#define S_PRBS_CHK_SYNC    4
+#define V_PRBS_CHK_SYNC(x) ((x) << S_PRBS_CHK_SYNC)
+#define F_PRBS_CHK_SYNC    V_PRBS_CHK_SYNC(1U)
+
+#define S_PRBS_CHK_RST    3
+#define V_PRBS_CHK_RST(x) ((x) << S_PRBS_CHK_RST)
+#define F_PRBS_CHK_RST    V_PRBS_CHK_RST(1U)
+
+#define S_PRBS_CHK_OFF    2
+#define V_PRBS_CHK_OFF(x) ((x) << S_PRBS_CHK_OFF)
+#define F_PRBS_CHK_OFF    V_PRBS_CHK_OFF(1U)
+
+#define S_PRBS_GEN_FRCERR    1
+#define V_PRBS_GEN_FRCERR(x) ((x) << S_PRBS_GEN_FRCERR)
+#define F_PRBS_GEN_FRCERR    V_PRBS_GEN_FRCERR(1U)
+
+#define S_PRBS_GEN_OFF    0
+#define V_PRBS_GEN_OFF(x) ((x) << S_PRBS_GEN_OFF)
+#define F_PRBS_GEN_OFF    V_PRBS_GEN_OFF(1U)
+
+#define A_XGMAC_PORT_AE_FSM_CTL 0x1718
+
+#define S_FSM_TR_LCL    14
+#define V_FSM_TR_LCL(x) ((x) << S_FSM_TR_LCL)
+#define F_FSM_TR_LCL    V_FSM_TR_LCL(1U)
+
+#define S_FSM_GDMRK    11
+#define M_FSM_GDMRK    0x7U
+#define V_FSM_GDMRK(x) ((x) << S_FSM_GDMRK)
+#define G_FSM_GDMRK(x) (((x) >> S_FSM_GDMRK) & M_FSM_GDMRK)
+
+#define S_FSM_BADMRK    8
+#define M_FSM_BADMRK    0x7U
+#define V_FSM_BADMRK(x) ((x) << S_FSM_BADMRK)
+#define G_FSM_BADMRK(x) (((x) >> S_FSM_BADMRK) & M_FSM_BADMRK)
+
+#define S_FSM_TR_FAIL    7
+#define V_FSM_TR_FAIL(x) ((x) << S_FSM_TR_FAIL)
+#define F_FSM_TR_FAIL    V_FSM_TR_FAIL(1U)
+
+#define S_FSM_TR_ACT    6
+#define V_FSM_TR_ACT(x) ((x) << S_FSM_TR_ACT)
+#define F_FSM_TR_ACT    V_FSM_TR_ACT(1U)
+
+#define S_FSM_FRM_LCK    5
+#define V_FSM_FRM_LCK(x) ((x) << S_FSM_FRM_LCK)
+#define F_FSM_FRM_LCK    V_FSM_FRM_LCK(1U)
+
+#define S_FSM_TR_COMP    4
+#define V_FSM_TR_COMP(x) ((x) << S_FSM_TR_COMP)
+#define F_FSM_TR_COMP    V_FSM_TR_COMP(1U)
+
+#define S_MC_RX_RDY    3
+#define V_MC_RX_RDY(x) ((x) << S_MC_RX_RDY)
+#define F_MC_RX_RDY    V_MC_RX_RDY(1U)
+
+#define S_FSM_CU_DIS    2
+#define V_FSM_CU_DIS(x) ((x) << S_FSM_CU_DIS)
+#define F_FSM_CU_DIS    V_FSM_CU_DIS(1U)
+
+#define S_FSM_TR_RST    1
+#define V_FSM_TR_RST(x) ((x) << S_FSM_TR_RST)
+#define F_FSM_TR_RST    V_FSM_TR_RST(1U)
+
+#define S_FSM_TR_EN    0
+#define V_FSM_TR_EN(x) ((x) << S_FSM_TR_EN)
+#define F_FSM_TR_EN    V_FSM_TR_EN(1U)
+
+#define A_XGMAC_PORT_AE_FSM_STATE 0x171c
+
+#define S_CC2FSM_STATE    13
+#define M_CC2FSM_STATE    0x7U
+#define V_CC2FSM_STATE(x) ((x) << S_CC2FSM_STATE)
+#define G_CC2FSM_STATE(x) (((x) >> S_CC2FSM_STATE) & M_CC2FSM_STATE)
+
+#define S_CC1FSM_STATE    10
+#define M_CC1FSM_STATE    0x7U
+#define V_CC1FSM_STATE(x) ((x) << S_CC1FSM_STATE)
+#define G_CC1FSM_STATE(x) (((x) >> S_CC1FSM_STATE) & M_CC1FSM_STATE)
+
+#define S_CC0FSM_STATE    7
+#define M_CC0FSM_STATE    0x7U
+#define V_CC0FSM_STATE(x) ((x) << S_CC0FSM_STATE)
+#define G_CC0FSM_STATE(x) (((x) >> S_CC0FSM_STATE) & M_CC0FSM_STATE)
+
+#define S_FLFSM_STATE    4
+#define M_FLFSM_STATE    0x7U
+#define V_FLFSM_STATE(x) ((x) << S_FLFSM_STATE)
+#define G_FLFSM_STATE(x) (((x) >> S_FLFSM_STATE) & M_FLFSM_STATE)
+
+#define S_TFSM_STATE    0
+#define M_TFSM_STATE    0x7U
+#define V_TFSM_STATE(x) ((x) << S_TFSM_STATE)
+#define G_TFSM_STATE(x) (((x) >> S_TFSM_STATE) & M_TFSM_STATE)
+
+#define A_XGMAC_PORT_AE_TX_DIS 0x1780
+
+#define S_PMD_TX_DIS    0
+#define V_PMD_TX_DIS(x) ((x) << S_PMD_TX_DIS)
+#define F_PMD_TX_DIS    V_PMD_TX_DIS(1U)
+
+#define A_XGMAC_PORT_AE_KR_CTRL 0x1784
+
+#define S_TRAINING_ENABLE    1
+#define V_TRAINING_ENABLE(x) ((x) << S_TRAINING_ENABLE)
+#define F_TRAINING_ENABLE    V_TRAINING_ENABLE(1U)
+
+#define S_RESTART_TRAINING    0
+#define V_RESTART_TRAINING(x) ((x) << S_RESTART_TRAINING)
+#define F_RESTART_TRAINING    V_RESTART_TRAINING(1U)
+
+#define A_XGMAC_PORT_AE_RX_SIGDET 0x1788
+
+#define S_PMD_SIGDET    0
+#define V_PMD_SIGDET(x) ((x) << S_PMD_SIGDET)
+#define F_PMD_SIGDET    V_PMD_SIGDET(1U)
+
+#define A_XGMAC_PORT_AE_KR_STATUS 0x178c
+
+#define S_TRAINING_FAILURE    3
+#define V_TRAINING_FAILURE(x) ((x) << S_TRAINING_FAILURE)
+#define F_TRAINING_FAILURE    V_TRAINING_FAILURE(1U)
+
+#define S_TRAINING    2
+#define V_TRAINING(x) ((x) << S_TRAINING)
+#define F_TRAINING    V_TRAINING(1U)
+
+#define S_FRAME_LOCK    1
+#define V_FRAME_LOCK(x) ((x) << S_FRAME_LOCK)
+#define F_FRAME_LOCK    V_FRAME_LOCK(1U)
+
+#define S_RX_TRAINED    0
+#define V_RX_TRAINED(x) ((x) << S_RX_TRAINED)
+#define F_RX_TRAINED    V_RX_TRAINED(1U)
+
+#define A_XGMAC_PORT_HSS_TXA_MODE_CFG 0x1800
+
+#define S_BWSEL    2
+#define M_BWSEL    0x3U
+#define V_BWSEL(x) ((x) << S_BWSEL)
+#define G_BWSEL(x) (((x) >> S_BWSEL) & M_BWSEL)
+
+#define S_RTSEL    0
+#define M_RTSEL    0x3U
+#define V_RTSEL(x) ((x) << S_RTSEL)
+#define G_RTSEL(x) (((x) >> S_RTSEL) & M_RTSEL)
+
+#define A_XGMAC_PORT_HSS_TXA_TEST_CTRL 0x1804
+
+#define S_TWDP    5
+#define V_TWDP(x) ((x) << S_TWDP)
+#define F_TWDP    V_TWDP(1U)
+
+#define S_TPGRST    4
+#define V_TPGRST(x) ((x) << S_TPGRST)
+#define F_TPGRST    V_TPGRST(1U)
+
+#define S_TPGEN    3
+#define V_TPGEN(x) ((x) << S_TPGEN)
+#define F_TPGEN    V_TPGEN(1U)
+
+#define S_TPSEL    0
+#define M_TPSEL    0x7U
+#define V_TPSEL(x) ((x) << S_TPSEL)
+#define G_TPSEL(x) (((x) >> S_TPSEL) & M_TPSEL)
+
+#define A_XGMAC_PORT_HSS_TXA_COEFF_CTRL 0x1808
+
+#define S_AEINVPOL    6
+#define V_AEINVPOL(x) ((x) << S_AEINVPOL)
+#define F_AEINVPOL    V_AEINVPOL(1U)
+
+#define S_AESOURCE    5
+#define V_AESOURCE(x) ((x) << S_AESOURCE)
+#define F_AESOURCE    V_AESOURCE(1U)
+
+#define S_EQMODE    4
+#define V_EQMODE(x) ((x) << S_EQMODE)
+#define F_EQMODE    V_EQMODE(1U)
+
+#define S_OCOEF    3
+#define V_OCOEF(x) ((x) << S_OCOEF)
+#define F_OCOEF    V_OCOEF(1U)
+
+#define S_COEFRST    2
+#define V_COEFRST(x) ((x) << S_COEFRST)
+#define F_COEFRST    V_COEFRST(1U)
+
+#define S_SPEN    1
+#define V_SPEN(x) ((x) << S_SPEN)
+#define F_SPEN    V_SPEN(1U)
+
+#define S_ALOAD    0
+#define V_ALOAD(x) ((x) << S_ALOAD)
+#define F_ALOAD    V_ALOAD(1U)
+
+#define A_XGMAC_PORT_HSS_TXA_DRIVER_MODE 0x180c
+
+#define S_DRVOFFT    5
+#define V_DRVOFFT(x) ((x) << S_DRVOFFT)
+#define F_DRVOFFT    V_DRVOFFT(1U)
+
+#define S_SLEW    2
+#define M_SLEW    0x7U
+#define V_SLEW(x) ((x) << S_SLEW)
+#define G_SLEW(x) (((x) >> S_SLEW) & M_SLEW)
+
+#define S_FFE    0
+#define M_FFE    0x3U
+#define V_FFE(x) ((x) << S_FFE)
+#define G_FFE(x) (((x) >> S_FFE) & M_FFE)
+
+#define A_XGMAC_PORT_HSS_TXA_DRIVER_OVR_CTRL 0x1810
+
+#define S_VLINC    7
+#define V_VLINC(x) ((x) << S_VLINC)
+#define F_VLINC    V_VLINC(1U)
+
+#define S_VLDEC    6
+#define V_VLDEC(x) ((x) << S_VLDEC)
+#define F_VLDEC    V_VLDEC(1U)
+
+#define S_LOPWR    5
+#define V_LOPWR(x) ((x) << S_LOPWR)
+#define F_LOPWR    V_LOPWR(1U)
+
+#define S_TDMEN    4
+#define V_TDMEN(x) ((x) << S_TDMEN)
+#define F_TDMEN    V_TDMEN(1U)
+
+#define S_DCCEN    3
+#define V_DCCEN(x) ((x) << S_DCCEN)
+#define F_DCCEN    V_DCCEN(1U)
+
+#define S_VHSEL    2
+#define V_VHSEL(x) ((x) << S_VHSEL)
+#define F_VHSEL    V_VHSEL(1U)
+
+#define S_IDAC    0
+#define M_IDAC    0x3U
+#define V_IDAC(x) ((x) << S_IDAC)
+#define G_IDAC(x) (((x) >> S_IDAC) & M_IDAC)
+
+#define A_XGMAC_PORT_HSS_TXA_TDM_BIASGEN_STANDBY_TIMER 0x1814
+
+#define S_STBY    0
+#define M_STBY    0xffffU
+#define V_STBY(x) ((x) << S_STBY)
+#define G_STBY(x) (((x) >> S_STBY) & M_STBY)
+
+#define A_XGMAC_PORT_HSS_TXA_TDM_BIASGEN_PWRON_TIMER 0x1818
+
+#define S_PON    0
+#define M_PON    0xffffU
+#define V_PON(x) ((x) << S_PON)
+#define G_PON(x) (((x) >> S_PON) & M_PON)
+
+#define A_XGMAC_PORT_HSS_TXA_TAP0_COEFF 0x1820
+
+#define S_NXTT0    0
+#define M_NXTT0    0xfU
+#define V_NXTT0(x) ((x) << S_NXTT0)
+#define G_NXTT0(x) (((x) >> S_NXTT0) & M_NXTT0)
+
+#define A_XGMAC_PORT_HSS_TXA_TAP1_COEFF 0x1824
+
+#define S_NXTT1    0
+#define M_NXTT1    0x3fU
+#define V_NXTT1(x) ((x) << S_NXTT1)
+#define G_NXTT1(x) (((x) >> S_NXTT1) & M_NXTT1)
+
+#define A_XGMAC_PORT_HSS_TXA_TAP2_COEFF 0x1828
+
+#define S_NXTT2    0
+#define M_NXTT2    0x1fU
+#define V_NXTT2(x) ((x) << S_NXTT2)
+#define G_NXTT2(x) (((x) >> S_NXTT2) & M_NXTT2)
+
+#define A_XGMAC_PORT_HSS_TXA_PWR 0x1830
+
+#define S_TXPWR    0
+#define M_TXPWR    0x7fU
+#define V_TXPWR(x) ((x) << S_TXPWR)
+#define G_TXPWR(x) (((x) >> S_TXPWR) & M_TXPWR)
+
+#define A_XGMAC_PORT_HSS_TXA_POLARITY 0x1834
+
+#define S_TXPOL    4
+#define M_TXPOL    0x7U
+#define V_TXPOL(x) ((x) << S_TXPOL)
+#define G_TXPOL(x) (((x) >> S_TXPOL) & M_TXPOL)
+
+#define S_NTXPOL    0
+#define M_NTXPOL    0x7U
+#define V_NTXPOL(x) ((x) << S_NTXPOL)
+#define G_NTXPOL(x) (((x) >> S_NTXPOL) & M_NTXPOL)
+
+#define A_XGMAC_PORT_HSS_TXA_8023AP_AE_CMD 0x1838
+
+#define S_CXPRESET    13
+#define V_CXPRESET(x) ((x) << S_CXPRESET)
+#define F_CXPRESET    V_CXPRESET(1U)
+
+#define S_CXINIT    12
+#define V_CXINIT(x) ((x) << S_CXINIT)
+#define F_CXINIT    V_CXINIT(1U)
+
+#define S_C2UPDT    4
+#define M_C2UPDT    0x3U
+#define V_C2UPDT(x) ((x) << S_C2UPDT)
+#define G_C2UPDT(x) (((x) >> S_C2UPDT) & M_C2UPDT)
+
+#define S_C1UPDT    2
+#define M_C1UPDT    0x3U
+#define V_C1UPDT(x) ((x) << S_C1UPDT)
+#define G_C1UPDT(x) (((x) >> S_C1UPDT) & M_C1UPDT)
+
+#define S_C0UPDT    0
+#define M_C0UPDT    0x3U
+#define V_C0UPDT(x) ((x) << S_C0UPDT)
+#define G_C0UPDT(x) (((x) >> S_C0UPDT) & M_C0UPDT)
+
+#define A_XGMAC_PORT_HSS_TXA_8023AP_AE_STATUS 0x183c
+
+#define S_C2STAT    4
+#define M_C2STAT    0x3U
+#define V_C2STAT(x) ((x) << S_C2STAT)
+#define G_C2STAT(x) (((x) >> S_C2STAT) & M_C2STAT)
+
+#define S_C1STAT    2
+#define M_C1STAT    0x3U
+#define V_C1STAT(x) ((x) << S_C1STAT)
+#define G_C1STAT(x) (((x) >> S_C1STAT) & M_C1STAT)
+
+#define S_C0STAT    0
+#define M_C0STAT    0x3U
+#define V_C0STAT(x) ((x) << S_C0STAT)
+#define G_C0STAT(x) (((x) >> S_C0STAT) & M_C0STAT)
+
+#define A_XGMAC_PORT_HSS_TXA_TAP0_IDAC_OVR 0x1840
+
+#define S_NIDAC0    0
+#define M_NIDAC0    0x1fU
+#define V_NIDAC0(x) ((x) << S_NIDAC0)
+#define G_NIDAC0(x) (((x) >> S_NIDAC0) & M_NIDAC0)
+
+#define A_XGMAC_PORT_HSS_TXA_TAP1_IDAC_OVR 0x1844
+
+#define S_NIDAC1    0
+#define M_NIDAC1    0x7fU
+#define V_NIDAC1(x) ((x) << S_NIDAC1)
+#define G_NIDAC1(x) (((x) >> S_NIDAC1) & M_NIDAC1)
+
+#define A_XGMAC_PORT_HSS_TXA_TAP2_IDAC_OVR 0x1848
+
+#define S_NIDAC2    0
+#define M_NIDAC2    0x3fU
+#define V_NIDAC2(x) ((x) << S_NIDAC2)
+#define G_NIDAC2(x) (((x) >> S_NIDAC2) & M_NIDAC2)
+
+#define A_XGMAC_PORT_HSS_TXA_PWR_DAC_OVR 0x1850
+
+#define S_OPEN    7
+#define V_OPEN(x) ((x) << S_OPEN)
+#define F_OPEN    V_OPEN(1U)
+
+#define S_OPVAL    0
+#define M_OPVAL    0x1fU
+#define V_OPVAL(x) ((x) << S_OPVAL)
+#define G_OPVAL(x) (((x) >> S_OPVAL) & M_OPVAL)
+
+#define A_XGMAC_PORT_HSS_TXA_PWR_DAC 0x1854
+
+#define S_PDAC    0
+#define M_PDAC    0x1fU
+#define V_PDAC(x) ((x) << S_PDAC)
+#define G_PDAC(x) (((x) >> S_PDAC) & M_PDAC)
+
+#define A_XGMAC_PORT_HSS_TXA_TAP0_IDAC_APP 0x1860
+
+#define S_AIDAC0    0
+#define M_AIDAC0    0x1fU
+#define V_AIDAC0(x) ((x) << S_AIDAC0)
+#define G_AIDAC0(x) (((x) >> S_AIDAC0) & M_AIDAC0)
+
+#define A_XGMAC_PORT_HSS_TXA_TAP1_IDAC_APP 0x1864
+
+#define S_AIDAC1    0
+#define M_AIDAC1    0x1fU
+#define V_AIDAC1(x) ((x) << S_AIDAC1)
+#define G_AIDAC1(x) (((x) >> S_AIDAC1) & M_AIDAC1)
+
+#define A_XGMAC_PORT_HSS_TXA_TAP2_IDAC_APP 0x1868
+
+#define S_TXA_AIDAC2    0
+#define M_TXA_AIDAC2    0x1fU
+#define V_TXA_AIDAC2(x) ((x) << S_TXA_AIDAC2)
+#define G_TXA_AIDAC2(x) (((x) >> S_TXA_AIDAC2) & M_TXA_AIDAC2)
+
+#define A_XGMAC_PORT_HSS_TXA_SEG_DIS_APP 0x1870
+
+#define S_CURSD    0
+#define M_CURSD    0x7fU
+#define V_CURSD(x) ((x) << S_CURSD)
+#define G_CURSD(x) (((x) >> S_CURSD) & M_CURSD)
+
+#define A_XGMAC_PORT_HSS_TXA_EXT_ADDR_DATA 0x1878
+
+#define S_XDATA    0
+#define M_XDATA    0xffffU
+#define V_XDATA(x) ((x) << S_XDATA)
+#define G_XDATA(x) (((x) >> S_XDATA) & M_XDATA)
+
+#define A_XGMAC_PORT_HSS_TXA_EXT_ADDR 0x187c
+
+#define S_EXTADDR    1
+#define M_EXTADDR    0x1fU
+#define V_EXTADDR(x) ((x) << S_EXTADDR)
+#define G_EXTADDR(x) (((x) >> S_EXTADDR) & M_EXTADDR)
+
+#define S_XWR    0
+#define V_XWR(x) ((x) << S_XWR)
+#define F_XWR    V_XWR(1U)
+
+#define A_XGMAC_PORT_HSS_TXB_MODE_CFG 0x1880
+#define A_XGMAC_PORT_HSS_TXB_TEST_CTRL 0x1884
+#define A_XGMAC_PORT_HSS_TXB_COEFF_CTRL 0x1888
+#define A_XGMAC_PORT_HSS_TXB_DRIVER_MODE 0x188c
+#define A_XGMAC_PORT_HSS_TXB_DRIVER_OVR_CTRL 0x1890
+#define A_XGMAC_PORT_HSS_TXB_TDM_BIASGEN_STANDBY_TIMER 0x1894
+#define A_XGMAC_PORT_HSS_TXB_TDM_BIASGEN_PWRON_TIMER 0x1898
+#define A_XGMAC_PORT_HSS_TXB_TAP0_COEFF 0x18a0
+#define A_XGMAC_PORT_HSS_TXB_TAP1_COEFF 0x18a4
+#define A_XGMAC_PORT_HSS_TXB_TAP2_COEFF 0x18a8
+#define A_XGMAC_PORT_HSS_TXB_PWR 0x18b0
+#define A_XGMAC_PORT_HSS_TXB_POLARITY 0x18b4
+#define A_XGMAC_PORT_HSS_TXB_8023AP_AE_CMD 0x18b8
+#define A_XGMAC_PORT_HSS_TXB_8023AP_AE_STATUS 0x18bc
+#define A_XGMAC_PORT_HSS_TXB_TAP0_IDAC_OVR 0x18c0
+#define A_XGMAC_PORT_HSS_TXB_TAP1_IDAC_OVR 0x18c4
+#define A_XGMAC_PORT_HSS_TXB_TAP2_IDAC_OVR 0x18c8
+#define A_XGMAC_PORT_HSS_TXB_PWR_DAC_OVR 0x18d0
+#define A_XGMAC_PORT_HSS_TXB_PWR_DAC 0x18d4
+#define A_XGMAC_PORT_HSS_TXB_TAP0_IDAC_APP 0x18e0
+#define A_XGMAC_PORT_HSS_TXB_TAP1_IDAC_APP 0x18e4
+#define A_XGMAC_PORT_HSS_TXB_TAP2_IDAC_APP 0x18e8
+
+#define S_AIDAC2    0
+#define M_AIDAC2    0x3fU
+#define V_AIDAC2(x) ((x) << S_AIDAC2)
+#define G_AIDAC2(x) (((x) >> S_AIDAC2) & M_AIDAC2)
+
+#define A_XGMAC_PORT_HSS_TXB_SEG_DIS_APP 0x18f0
+#define A_XGMAC_PORT_HSS_TXB_EXT_ADDR_DATA 0x18f8
+#define A_XGMAC_PORT_HSS_TXB_EXT_ADDR 0x18fc
+
+#define S_XADDR    2
+#define M_XADDR    0xfU
+#define V_XADDR(x) ((x) << S_XADDR)
+#define G_XADDR(x) (((x) >> S_XADDR) & M_XADDR)
+
+#define A_XGMAC_PORT_HSS_RXA_CFG_MODE 0x1900
+
+#define S_BW810    8
+#define V_BW810(x) ((x) << S_BW810)
+#define F_BW810    V_BW810(1U)
+
+#define S_AUXCLK    7
+#define V_AUXCLK(x) ((x) << S_AUXCLK)
+#define F_AUXCLK    V_AUXCLK(1U)
+
+#define S_DMSEL    4
+#define M_DMSEL    0x7U
+#define V_DMSEL(x) ((x) << S_DMSEL)
+#define G_DMSEL(x) (((x) >> S_DMSEL) & M_DMSEL)
+
+#define A_XGMAC_PORT_HSS_RXA_TEST_CTRL 0x1904
+
+#define S_RCLKEN    15
+#define V_RCLKEN(x) ((x) << S_RCLKEN)
+#define F_RCLKEN    V_RCLKEN(1U)
+
+#define S_RRATE    13
+#define M_RRATE    0x3U
+#define V_RRATE(x) ((x) << S_RRATE)
+#define G_RRATE(x) (((x) >> S_RRATE) & M_RRATE)
+
+#define S_LBFRCERROR    10
+#define V_LBFRCERROR(x) ((x) << S_LBFRCERROR)
+#define F_LBFRCERROR    V_LBFRCERROR(1U)
+
+#define S_LBERROR    9
+#define V_LBERROR(x) ((x) << S_LBERROR)
+#define F_LBERROR    V_LBERROR(1U)
+
+#define S_LBSYNC    8
+#define V_LBSYNC(x) ((x) << S_LBSYNC)
+#define F_LBSYNC    V_LBSYNC(1U)
+
+#define S_FDWRAPCLK    7
+#define V_FDWRAPCLK(x) ((x) << S_FDWRAPCLK)
+#define F_FDWRAPCLK    V_FDWRAPCLK(1U)
+
+#define S_FDWRAP    6
+#define V_FDWRAP(x) ((x) << S_FDWRAP)
+#define F_FDWRAP    V_FDWRAP(1U)
+
+#define S_PRST    4
+#define V_PRST(x) ((x) << S_PRST)
+#define F_PRST    V_PRST(1U)
+
+#define S_PCHKEN    3
+#define V_PCHKEN(x) ((x) << S_PCHKEN)
+#define F_PCHKEN    V_PCHKEN(1U)
+
+#define S_PRBSSEL    0
+#define M_PRBSSEL    0x7U
+#define V_PRBSSEL(x) ((x) << S_PRBSSEL)
+#define G_PRBSSEL(x) (((x) >> S_PRBSSEL) & M_PRBSSEL)
+
+#define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_CTRL 0x1908
+
+#define S_FTHROT    12
+#define M_FTHROT    0xfU
+#define V_FTHROT(x) ((x) << S_FTHROT)
+#define G_FTHROT(x) (((x) >> S_FTHROT) & M_FTHROT)
+
+#define S_RTHROT    11
+#define V_RTHROT(x) ((x) << S_RTHROT)
+#define F_RTHROT    V_RTHROT(1U)
+
+#define S_FILTCTL    7
+#define M_FILTCTL    0xfU
+#define V_FILTCTL(x) ((x) << S_FILTCTL)
+#define G_FILTCTL(x) (((x) >> S_FILTCTL) & M_FILTCTL)
+
+#define S_RSRVO    5
+#define M_RSRVO    0x3U
+#define V_RSRVO(x) ((x) << S_RSRVO)
+#define G_RSRVO(x) (((x) >> S_RSRVO) & M_RSRVO)
+
+#define S_EXTEL    4
+#define V_EXTEL(x) ((x) << S_EXTEL)
+#define F_EXTEL    V_EXTEL(1U)
+
+#define S_RSTONSTUCK    3
+#define V_RSTONSTUCK(x) ((x) << S_RSTONSTUCK)
+#define F_RSTONSTUCK    V_RSTONSTUCK(1U)
+
+#define S_FREEZEFW    2
+#define V_FREEZEFW(x) ((x) << S_FREEZEFW)
+#define F_FREEZEFW    V_FREEZEFW(1U)
+
+#define S_RESETFW    1
+#define V_RESETFW(x) ((x) << S_RESETFW)
+#define F_RESETFW    V_RESETFW(1U)
+
+#define S_SSCENABLE    0
+#define V_SSCENABLE(x) ((x) << S_SSCENABLE)
+#define F_SSCENABLE    V_SSCENABLE(1U)
+
+#define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_OFFSET_CTRL 0x190c
+
+#define S_RSNP    11
+#define V_RSNP(x) ((x) << S_RSNP)
+#define F_RSNP    V_RSNP(1U)
+
+#define S_TSOEN    10
+#define V_TSOEN(x) ((x) << S_TSOEN)
+#define F_TSOEN    V_TSOEN(1U)
+
+#define S_OFFEN    9
+#define V_OFFEN(x) ((x) << S_OFFEN)
+#define F_OFFEN    V_OFFEN(1U)
+
+#define S_TMSCAL    7
+#define M_TMSCAL    0x3U
+#define V_TMSCAL(x) ((x) << S_TMSCAL)
+#define G_TMSCAL(x) (((x) >> S_TMSCAL) & M_TMSCAL)
+
+#define S_APADJ    6
+#define V_APADJ(x) ((x) << S_APADJ)
+#define F_APADJ    V_APADJ(1U)
+
+#define S_RSEL    5
+#define V_RSEL(x) ((x) << S_RSEL)
+#define F_RSEL    V_RSEL(1U)
+
+#define S_PHOFFS    0
+#define M_PHOFFS    0x1fU
+#define V_PHOFFS(x) ((x) << S_PHOFFS)
+#define G_PHOFFS(x) (((x) >> S_PHOFFS) & M_PHOFFS)
+
+#define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION1 0x1910
+
+#define S_ROT0A    8
+#define M_ROT0A    0x3fU
+#define V_ROT0A(x) ((x) << S_ROT0A)
+#define G_ROT0A(x) (((x) >> S_ROT0A) & M_ROT0A)
+
+#define S_RTSEL_SNAPSHOT    0
+#define M_RTSEL_SNAPSHOT    0x3fU
+#define V_RTSEL_SNAPSHOT(x) ((x) << S_RTSEL_SNAPSHOT)
+#define G_RTSEL_SNAPSHOT(x) (((x) >> S_RTSEL_SNAPSHOT) & M_RTSEL_SNAPSHOT)
+
+#define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION2 0x1914
+
+#define S_ROT90    0
+#define M_ROT90    0x3fU
+#define V_ROT90(x) ((x) << S_ROT90)
+#define G_ROT90(x) (((x) >> S_ROT90) & M_ROT90)
+
+#define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_STATIC_PH_OFFSET 0x1918
+
+#define S_RCALER    15
+#define V_RCALER(x) ((x) << S_RCALER)
+#define F_RCALER    V_RCALER(1U)
+
+#define S_RAOOFF    10
+#define M_RAOOFF    0x1fU
+#define V_RAOOFF(x) ((x) << S_RAOOFF)
+#define G_RAOOFF(x) (((x) >> S_RAOOFF) & M_RAOOFF)
+
+#define S_RAEOFF    5
+#define M_RAEOFF    0x1fU
+#define V_RAEOFF(x) ((x) << S_RAEOFF)
+#define G_RAEOFF(x) (((x) >> S_RAEOFF) & M_RAEOFF)
+
+#define S_RDOFF    0
+#define M_RDOFF    0x1fU
+#define V_RDOFF(x) ((x) << S_RDOFF)
+#define G_RDOFF(x) (((x) >> S_RDOFF) & M_RDOFF)
+
+#define A_XGMAC_PORT_HSS_RXA_SIGDET_CTRL 0x191c
+
+#define S_SIGNSD    13
+#define M_SIGNSD    0x3U
+#define V_SIGNSD(x) ((x) << S_SIGNSD)
+#define G_SIGNSD(x) (((x) >> S_SIGNSD) & M_SIGNSD)
+
+#define S_DACSD    8
+#define M_DACSD    0x1fU
+#define V_DACSD(x) ((x) << S_DACSD)
+#define G_DACSD(x) (((x) >> S_DACSD) & M_DACSD)
+
+#define S_SDPDN    6
+#define V_SDPDN(x) ((x) << S_SDPDN)
+#define F_SDPDN    V_SDPDN(1U)
+
+#define S_SIGDET    5
+#define V_SIGDET(x) ((x) << S_SIGDET)
+#define F_SIGDET    V_SIGDET(1U)
+
+#define S_SDLVL    0
+#define M_SDLVL    0x1fU
+#define V_SDLVL(x) ((x) << S_SDLVL)
+#define G_SDLVL(x) (((x) >> S_SDLVL) & M_SDLVL)
+
+#define A_XGMAC_PORT_HSS_RXA_DFE_CTRL 0x1920
+
+#define S_REQCMP    15
+#define V_REQCMP(x) ((x) << S_REQCMP)
+#define F_REQCMP    V_REQCMP(1U)
+
+#define S_DFEREQ    14
+#define V_DFEREQ(x) ((x) << S_DFEREQ)
+#define F_DFEREQ    V_DFEREQ(1U)
+
+#define S_SPCEN    13
+#define V_SPCEN(x) ((x) << S_SPCEN)
+#define F_SPCEN    V_SPCEN(1U)
+
+#define S_GATEEN    12
+#define V_GATEEN(x) ((x) << S_GATEEN)
+#define F_GATEEN    V_GATEEN(1U)
+
+#define S_SPIFMT    9
+#define M_SPIFMT    0x7U
+#define V_SPIFMT(x) ((x) << S_SPIFMT)
+#define G_SPIFMT(x) (((x) >> S_SPIFMT) & M_SPIFMT)
+
+#define S_DFEPWR    6
+#define M_DFEPWR    0x7U
+#define V_DFEPWR(x) ((x) << S_DFEPWR)
+#define G_DFEPWR(x) (((x) >> S_DFEPWR) & M_DFEPWR)
+
+#define S_STNDBY    5
+#define V_STNDBY(x) ((x) << S_STNDBY)
+#define F_STNDBY    V_STNDBY(1U)
+
+#define S_FRCH    4
+#define V_FRCH(x) ((x) << S_FRCH)
+#define F_FRCH    V_FRCH(1U)
+
+#define S_NONRND    3
+#define V_NONRND(x) ((x) << S_NONRND)
+#define F_NONRND    V_NONRND(1U)
+
+#define S_NONRNF    2
+#define V_NONRNF(x) ((x) << S_NONRNF)
+#define F_NONRNF    V_NONRNF(1U)
+
+#define S_FSTLCK    1
+#define V_FSTLCK(x) ((x) << S_FSTLCK)
+#define F_FSTLCK    V_FSTLCK(1U)
+
+#define S_DFERST    0
+#define V_DFERST(x) ((x) << S_DFERST)
+#define F_DFERST    V_DFERST(1U)
+
+#define A_XGMAC_PORT_HSS_RXA_DFE_DATA_EDGE_SAMPLE 0x1924
+
+#define S_ESAMP    8
+#define M_ESAMP    0xffU
+#define V_ESAMP(x) ((x) << S_ESAMP)
+#define G_ESAMP(x) (((x) >> S_ESAMP) & M_ESAMP)
+
+#define S_DSAMP    0
+#define M_DSAMP    0xffU
+#define V_DSAMP(x) ((x) << S_DSAMP)
+#define G_DSAMP(x) (((x) >> S_DSAMP) & M_DSAMP)
+
+#define A_XGMAC_PORT_HSS_RXA_DFE_AMP_SAMPLE 0x1928
+
+#define S_SMODE    8
+#define M_SMODE    0xfU
+#define V_SMODE(x) ((x) << S_SMODE)
+#define G_SMODE(x) (((x) >> S_SMODE) & M_SMODE)
+
+#define S_ADCORR    7
+#define V_ADCORR(x) ((x) << S_ADCORR)
+#define F_ADCORR    V_ADCORR(1U)
+
+#define S_TRAINEN    6
+#define V_TRAINEN(x) ((x) << S_TRAINEN)
+#define F_TRAINEN    V_TRAINEN(1U)
+
+#define S_ASAMPQ    3
+#define M_ASAMPQ    0x7U
+#define V_ASAMPQ(x) ((x) << S_ASAMPQ)
+#define G_ASAMPQ(x) (((x) >> S_ASAMPQ) & M_ASAMPQ)
+
+#define S_ASAMP    0
+#define M_ASAMP    0x7U
+#define V_ASAMP(x) ((x) << S_ASAMP)
+#define G_ASAMP(x) (((x) >> S_ASAMP) & M_ASAMP)
+
+#define A_XGMAC_PORT_HSS_RXA_VGA_CTRL1 0x192c
+
+#define S_POLE    12
+#define M_POLE    0x3U
+#define V_POLE(x) ((x) << S_POLE)
+#define G_POLE(x) (((x) >> S_POLE) & M_POLE)
+
+#define S_PEAK    8
+#define M_PEAK    0x7U
+#define V_PEAK(x) ((x) << S_PEAK)
+#define G_PEAK(x) (((x) >> S_PEAK) & M_PEAK)
+
+#define S_VOFFSN    6
+#define M_VOFFSN    0x3U
+#define V_VOFFSN(x) ((x) << S_VOFFSN)
+#define G_VOFFSN(x) (((x) >> S_VOFFSN) & M_VOFFSN)
+
+#define S_VOFFA    0
+#define M_VOFFA    0x3fU
+#define V_VOFFA(x) ((x) << S_VOFFA)
+#define G_VOFFA(x) (((x) >> S_VOFFA) & M_VOFFA)
+
+#define A_XGMAC_PORT_HSS_RXA_VGA_CTRL2 0x1930
+
+#define S_SHORTV    10
+#define V_SHORTV(x) ((x) << S_SHORTV)
+#define F_SHORTV    V_SHORTV(1U)
+
+#define S_VGAIN    0
+#define M_VGAIN    0xfU
+#define V_VGAIN(x) ((x) << S_VGAIN)
+#define G_VGAIN(x) (((x) >> S_VGAIN) & M_VGAIN)
+
+#define A_XGMAC_PORT_HSS_RXA_VGA_CTRL3 0x1934
+
+#define S_HBND1    10
+#define V_HBND1(x) ((x) << S_HBND1)
+#define F_HBND1    V_HBND1(1U)
+
+#define S_HBND0    9
+#define V_HBND0(x) ((x) << S_HBND0)
+#define F_HBND0    V_HBND0(1U)
+
+#define S_VLCKD    8
+#define V_VLCKD(x) ((x) << S_VLCKD)
+#define F_VLCKD    V_VLCKD(1U)
+
+#define S_VLCKDF    7
+#define V_VLCKDF(x) ((x) << S_VLCKDF)
+#define F_VLCKDF    V_VLCKDF(1U)
+
+#define S_AMAXT    0
+#define M_AMAXT    0x7fU
+#define V_AMAXT(x) ((x) << S_AMAXT)
+#define G_AMAXT(x) (((x) >> S_AMAXT) & M_AMAXT)
+
+#define A_XGMAC_PORT_HSS_RXA_DFE_D00_D01_OFFSET 0x1938
+
+#define S_D01SN    13
+#define M_D01SN    0x3U
+#define V_D01SN(x) ((x) << S_D01SN)
+#define G_D01SN(x) (((x) >> S_D01SN) & M_D01SN)
+
+#define S_D01AMP    8
+#define M_D01AMP    0x1fU
+#define V_D01AMP(x) ((x) << S_D01AMP)
+#define G_D01AMP(x) (((x) >> S_D01AMP) & M_D01AMP)
+
+#define S_D00SN    5
+#define M_D00SN    0x3U
+#define V_D00SN(x) ((x) << S_D00SN)
+#define G_D00SN(x) (((x) >> S_D00SN) & M_D00SN)
+
+#define S_D00AMP    0
+#define M_D00AMP    0x1fU
+#define V_D00AMP(x) ((x) << S_D00AMP)
+#define G_D00AMP(x) (((x) >> S_D00AMP) & M_D00AMP)
+
+#define A_XGMAC_PORT_HSS_RXA_DFE_D10_D11_OFFSET 0x193c
+
+#define S_D11SN    13
+#define M_D11SN    0x3U
+#define V_D11SN(x) ((x) << S_D11SN)
+#define G_D11SN(x) (((x) >> S_D11SN) & M_D11SN)
+
+#define S_D11AMP    8
+#define M_D11AMP    0x1fU
+#define V_D11AMP(x) ((x) << S_D11AMP)
+#define G_D11AMP(x) (((x) >> S_D11AMP) & M_D11AMP)
+
+#define S_D10SN    5
+#define M_D10SN    0x3U
+#define V_D10SN(x) ((x) << S_D10SN)
+#define G_D10SN(x) (((x) >> S_D10SN) & M_D10SN)
+
+#define S_D10AMP    0
+#define M_D10AMP    0x1fU
+#define V_D10AMP(x) ((x) << S_D10AMP)
+#define G_D10AMP(x) (((x) >> S_D10AMP) & M_D10AMP)
+
+#define A_XGMAC_PORT_HSS_RXA_DFE_E0_E1_OFFSET 0x1940
+
+#define S_E1SN    13
+#define M_E1SN    0x3U
+#define V_E1SN(x) ((x) << S_E1SN)
+#define G_E1SN(x) (((x) >> S_E1SN) & M_E1SN)
+
+#define S_E1AMP    8
+#define M_E1AMP    0x1fU
+#define V_E1AMP(x) ((x) << S_E1AMP)
+#define G_E1AMP(x) (((x) >> S_E1AMP) & M_E1AMP)
+
+#define S_E0SN    5
+#define M_E0SN    0x3U
+#define V_E0SN(x) ((x) << S_E0SN)
+#define G_E0SN(x) (((x) >> S_E0SN) & M_E0SN)
+
+#define S_E0AMP    0
+#define M_E0AMP    0x1fU
+#define V_E0AMP(x) ((x) << S_E0AMP)
+#define G_E0AMP(x) (((x) >> S_E0AMP) & M_E0AMP)
+
+#define A_XGMAC_PORT_HSS_RXA_DACA_OFFSET 0x1944
+
+#define S_AOFFO    8
+#define M_AOFFO    0x3fU
+#define V_AOFFO(x) ((x) << S_AOFFO)
+#define G_AOFFO(x) (((x) >> S_AOFFO) & M_AOFFO)
+
+#define S_AOFFE    0
+#define M_AOFFE    0x3fU
+#define V_AOFFE(x) ((x) << S_AOFFE)
+#define G_AOFFE(x) (((x) >> S_AOFFE) & M_AOFFE)
+
+#define A_XGMAC_PORT_HSS_RXA_DACAP_DAC_AN_OFFSET 0x1948
+
+#define S_DACAN    8
+#define M_DACAN    0xffU
+#define V_DACAN(x) ((x) << S_DACAN)
+#define G_DACAN(x) (((x) >> S_DACAN) & M_DACAN)
+
+#define S_DACAP    0
+#define M_DACAP    0xffU
+#define V_DACAP(x) ((x) << S_DACAP)
+#define G_DACAP(x) (((x) >> S_DACAP) & M_DACAP)
+
+#define A_XGMAC_PORT_HSS_RXA_DACA_MIN 0x194c
+
+#define S_DACAZ    8
+#define M_DACAZ    0xffU
+#define V_DACAZ(x) ((x) << S_DACAZ)
+#define G_DACAZ(x) (((x) >> S_DACAZ) & M_DACAZ)
+
+#define S_DACAM    0
+#define M_DACAM    0xffU
+#define V_DACAM(x) ((x) << S_DACAM)
+#define G_DACAM(x) (((x) >> S_DACAM) & M_DACAM)
+
+#define A_XGMAC_PORT_HSS_RXA_ADAC_CTRL 0x1950
+
+#define S_ADSN    7
+#define M_ADSN    0x3U
+#define V_ADSN(x) ((x) << S_ADSN)
+#define G_ADSN(x) (((x) >> S_ADSN) & M_ADSN)
+
+#define S_ADMAG    0
+#define M_ADMAG    0x7fU
+#define V_ADMAG(x) ((x) << S_ADMAG)
+#define G_ADMAG(x) (((x) >> S_ADMAG) & M_ADMAG)
+
+#define A_XGMAC_PORT_HSS_RXA_DIGITAL_EYE_CTRL 0x1954
+
+#define S_BLKAZ    15
+#define V_BLKAZ(x) ((x) << S_BLKAZ)
+#define F_BLKAZ    V_BLKAZ(1U)
+
+#define S_WIDTH    10
+#define M_WIDTH    0x1fU
+#define V_WIDTH(x) ((x) << S_WIDTH)
+#define G_WIDTH(x) (((x) >> S_WIDTH) & M_WIDTH)
+
+#define S_MINWIDTH    5
+#define M_MINWIDTH    0x1fU
+#define V_MINWIDTH(x) ((x) << S_MINWIDTH)
+#define G_MINWIDTH(x) (((x) >> S_MINWIDTH) & M_MINWIDTH)
+
+#define S_MINAMP    0
+#define M_MINAMP    0x1fU
+#define V_MINAMP(x) ((x) << S_MINAMP)
+#define G_MINAMP(x) (((x) >> S_MINAMP) & M_MINAMP)
+
+#define A_XGMAC_PORT_HSS_RXA_DIGITAL_EYE_METRICS 0x1958
+
+#define S_EMBRDY    10
+#define V_EMBRDY(x) ((x) << S_EMBRDY)
+#define F_EMBRDY    V_EMBRDY(1U)
+
+#define S_EMBUMP    7
+#define V_EMBUMP(x) ((x) << S_EMBUMP)
+#define F_EMBUMP    V_EMBUMP(1U)
+
+#define S_EMMD    5
+#define M_EMMD    0x3U
+#define V_EMMD(x) ((x) << S_EMMD)
+#define G_EMMD(x) (((x) >> S_EMMD) & M_EMMD)
+
+#define S_EMPAT    1
+#define V_EMPAT(x) ((x) << S_EMPAT)
+#define F_EMPAT    V_EMPAT(1U)
+
+#define S_EMEN    0
+#define V_EMEN(x) ((x) << S_EMEN)
+#define F_EMEN    V_EMEN(1U)
+
+#define A_XGMAC_PORT_HSS_RXA_DFE_H1 0x195c
+
+#define S_H1OSN    14
+#define M_H1OSN    0x3U
+#define V_H1OSN(x) ((x) << S_H1OSN)
+#define G_H1OSN(x) (((x) >> S_H1OSN) & M_H1OSN)
+
+#define S_H1OMAG    8
+#define M_H1OMAG    0x3fU
+#define V_H1OMAG(x) ((x) << S_H1OMAG)
+#define G_H1OMAG(x) (((x) >> S_H1OMAG) & M_H1OMAG)
+
+#define S_H1ESN    6
+#define M_H1ESN    0x3U
+#define V_H1ESN(x) ((x) << S_H1ESN)
+#define G_H1ESN(x) (((x) >> S_H1ESN) & M_H1ESN)
+
+#define S_H1EMAG    0
+#define M_H1EMAG    0x3fU
+#define V_H1EMAG(x) ((x) << S_H1EMAG)
+#define G_H1EMAG(x) (((x) >> S_H1EMAG) & M_H1EMAG)
+
+#define A_XGMAC_PORT_HSS_RXA_DFE_H2 0x1960
+
+#define S_H2OSN    13
+#define M_H2OSN    0x3U
+#define V_H2OSN(x) ((x) << S_H2OSN)
+#define G_H2OSN(x) (((x) >> S_H2OSN) & M_H2OSN)
+
+#define S_H2OMAG    8
+#define M_H2OMAG    0x1fU
+#define V_H2OMAG(x) ((x) << S_H2OMAG)
+#define G_H2OMAG(x) (((x) >> S_H2OMAG) & M_H2OMAG)
+
+#define S_H2ESN    5
+#define M_H2ESN    0x3U
+#define V_H2ESN(x) ((x) << S_H2ESN)
+#define G_H2ESN(x) (((x) >> S_H2ESN) & M_H2ESN)
+
+#define S_H2EMAG    0
+#define M_H2EMAG    0x1fU
+#define V_H2EMAG(x) ((x) << S_H2EMAG)
+#define G_H2EMAG(x) (((x) >> S_H2EMAG) & M_H2EMAG)
+
+#define A_XGMAC_PORT_HSS_RXA_DFE_H3 0x1964
+
+#define S_H3OSN    12
+#define M_H3OSN    0x3U
+#define V_H3OSN(x) ((x) << S_H3OSN)
+#define G_H3OSN(x) (((x) >> S_H3OSN) & M_H3OSN)
+
+#define S_H3OMAG    8
+#define M_H3OMAG    0xfU
+#define V_H3OMAG(x) ((x) << S_H3OMAG)
+#define G_H3OMAG(x) (((x) >> S_H3OMAG) & M_H3OMAG)
+
+#define S_H3ESN    4
+#define M_H3ESN    0x3U
+#define V_H3ESN(x) ((x) << S_H3ESN)
+#define G_H3ESN(x) (((x) >> S_H3ESN) & M_H3ESN)
+
+#define S_H3EMAG    0
+#define M_H3EMAG    0xfU
+#define V_H3EMAG(x) ((x) << S_H3EMAG)
+#define G_H3EMAG(x) (((x) >> S_H3EMAG) & M_H3EMAG)
+
+#define A_XGMAC_PORT_HSS_RXA_DFE_H4 0x1968
+
+#define S_H4OSN    12
+#define M_H4OSN    0x3U
+#define V_H4OSN(x) ((x) << S_H4OSN)
+#define G_H4OSN(x) (((x) >> S_H4OSN) & M_H4OSN)
+
+#define S_H4OMAG    8
+#define M_H4OMAG    0xfU
+#define V_H4OMAG(x) ((x) << S_H4OMAG)
+#define G_H4OMAG(x) (((x) >> S_H4OMAG) & M_H4OMAG)
+
+#define S_H4ESN    4
+#define M_H4ESN    0x3U
+#define V_H4ESN(x) ((x) << S_H4ESN)
+#define G_H4ESN(x) (((x) >> S_H4ESN) & M_H4ESN)
+
+#define S_H4EMAG    0
+#define M_H4EMAG    0xfU
+#define V_H4EMAG(x) ((x) << S_H4EMAG)
+#define G_H4EMAG(x) (((x) >> S_H4EMAG) & M_H4EMAG)
+
+#define A_XGMAC_PORT_HSS_RXA_DFE_H5 0x196c
+
+#define S_H5OSN    12
+#define M_H5OSN    0x3U
+#define V_H5OSN(x) ((x) << S_H5OSN)
+#define G_H5OSN(x) (((x) >> S_H5OSN) & M_H5OSN)
+
+#define S_H5OMAG    8
+#define M_H5OMAG    0xfU
+#define V_H5OMAG(x) ((x) << S_H5OMAG)
+#define G_H5OMAG(x) (((x) >> S_H5OMAG) & M_H5OMAG)
+
+#define S_H5ESN    4
+#define M_H5ESN    0x3U
+#define V_H5ESN(x) ((x) << S_H5ESN)
+#define G_H5ESN(x) (((x) >> S_H5ESN) & M_H5ESN)
+
+#define S_H5EMAG    0
+#define M_H5EMAG    0xfU
+#define V_H5EMAG(x) ((x) << S_H5EMAG)
+#define G_H5EMAG(x) (((x) >> S_H5EMAG) & M_H5EMAG)
+
+#define A_XGMAC_PORT_HSS_RXA_DAC_DPC 0x1970
+
+#define S_DPCCVG    13
+#define V_DPCCVG(x) ((x) << S_DPCCVG)
+#define F_DPCCVG    V_DPCCVG(1U)
+
+#define S_DACCVG    12
+#define V_DACCVG(x) ((x) << S_DACCVG)
+#define F_DACCVG    V_DACCVG(1U)
+
+#define S_DPCTGT    9
+#define M_DPCTGT    0x7U
+#define V_DPCTGT(x) ((x) << S_DPCTGT)
+#define G_DPCTGT(x) (((x) >> S_DPCTGT) & M_DPCTGT)
+
+#define S_BLKH1T    8
+#define V_BLKH1T(x) ((x) << S_BLKH1T)
+#define F_BLKH1T    V_BLKH1T(1U)
+
+#define S_BLKOAE    7
+#define V_BLKOAE(x) ((x) << S_BLKOAE)
+#define F_BLKOAE    V_BLKOAE(1U)
+
+#define S_H1TGT    4
+#define M_H1TGT    0x7U
+#define V_H1TGT(x) ((x) << S_H1TGT)
+#define G_H1TGT(x) (((x) >> S_H1TGT) & M_H1TGT)
+
+#define S_OAE    0
+#define M_OAE    0xfU
+#define V_OAE(x) ((x) << S_OAE)
+#define G_OAE(x) (((x) >> S_OAE) & M_OAE)
+
+#define A_XGMAC_PORT_HSS_RXA_DDC 0x1974
+
+#define S_OLS    11
+#define M_OLS    0x1fU
+#define V_OLS(x) ((x) << S_OLS)
+#define G_OLS(x) (((x) >> S_OLS) & M_OLS)
+
+#define S_OES    6
+#define M_OES    0x1fU
+#define V_OES(x) ((x) << S_OES)
+#define G_OES(x) (((x) >> S_OES) & M_OES)
+
+#define S_BLKODEC    5
+#define V_BLKODEC(x) ((x) << S_BLKODEC)
+#define F_BLKODEC    V_BLKODEC(1U)
+
+#define S_ODEC    0
+#define M_ODEC    0x1fU
+#define V_ODEC(x) ((x) << S_ODEC)
+#define G_ODEC(x) (((x) >> S_ODEC) & M_ODEC)
+
+#define A_XGMAC_PORT_HSS_RXA_INTERNAL_STATUS 0x1978
+
+#define S_BER6    15
+#define V_BER6(x) ((x) << S_BER6)
+#define F_BER6    V_BER6(1U)
+
+#define S_BER6VAL    14
+#define V_BER6VAL(x) ((x) << S_BER6VAL)
+#define F_BER6VAL    V_BER6VAL(1U)
+
+#define S_BER3VAL    13
+#define V_BER3VAL(x) ((x) << S_BER3VAL)
+#define F_BER3VAL    V_BER3VAL(1U)
+
+#define S_DPCCMP    9
+#define V_DPCCMP(x) ((x) << S_DPCCMP)
+#define F_DPCCMP    V_DPCCMP(1U)
+
+#define S_DACCMP    8
+#define V_DACCMP(x) ((x) << S_DACCMP)
+#define F_DACCMP    V_DACCMP(1U)
+
+#define S_DDCCMP    7
+#define V_DDCCMP(x) ((x) << S_DDCCMP)
+#define F_DDCCMP    V_DDCCMP(1U)
+
+#define S_AERRFLG    6
+#define V_AERRFLG(x) ((x) << S_AERRFLG)
+#define F_AERRFLG    V_AERRFLG(1U)
+
+#define S_WERRFLG    5
+#define V_WERRFLG(x) ((x) << S_WERRFLG)
+#define F_WERRFLG    V_WERRFLG(1U)
+
+#define S_TRCMP    4
+#define V_TRCMP(x) ((x) << S_TRCMP)
+#define F_TRCMP    V_TRCMP(1U)
+
+#define S_VLCKF    3
+#define V_VLCKF(x) ((x) << S_VLCKF)
+#define F_VLCKF    V_VLCKF(1U)
+
+#define S_ROCADJ    2
+#define V_ROCADJ(x) ((x) << S_ROCADJ)
+#define F_ROCADJ    V_ROCADJ(1U)
+
+#define S_ROCCMP    1
+#define V_ROCCMP(x) ((x) << S_ROCCMP)
+#define F_ROCCMP    V_ROCCMP(1U)
+
+#define S_OCCMP    0
+#define V_OCCMP(x) ((x) << S_OCCMP)
+#define F_OCCMP    V_OCCMP(1U)
+
+#define A_XGMAC_PORT_HSS_RXA_DFE_FUNC_CTRL 0x197c
+
+#define S_FDPC    15
+#define V_FDPC(x) ((x) << S_FDPC)
+#define F_FDPC    V_FDPC(1U)
+
+#define S_FDAC    14
+#define V_FDAC(x) ((x) << S_FDAC)
+#define F_FDAC    V_FDAC(1U)
+
+#define S_FDDC    13
+#define V_FDDC(x) ((x) << S_FDDC)
+#define F_FDDC    V_FDDC(1U)
+
+#define S_FNRND    12
+#define V_FNRND(x) ((x) << S_FNRND)
+#define F_FNRND    V_FNRND(1U)
+
+#define S_FVGAIN    11
+#define V_FVGAIN(x) ((x) << S_FVGAIN)
+#define F_FVGAIN    V_FVGAIN(1U)
+
+#define S_FVOFF    10
+#define V_FVOFF(x) ((x) << S_FVOFF)
+#define F_FVOFF    V_FVOFF(1U)
+
+#define S_FSDET    9
+#define V_FSDET(x) ((x) << S_FSDET)
+#define F_FSDET    V_FSDET(1U)
+
+#define S_FBER6    8
+#define V_FBER6(x) ((x) << S_FBER6)
+#define F_FBER6    V_FBER6(1U)
+
+#define S_FROTO    7
+#define V_FROTO(x) ((x) << S_FROTO)
+#define F_FROTO    V_FROTO(1U)
+
+#define S_FH4H5    6
+#define V_FH4H5(x) ((x) << S_FH4H5)
+#define F_FH4H5    V_FH4H5(1U)
+
+#define S_FH2H3    5
+#define V_FH2H3(x) ((x) << S_FH2H3)
+#define F_FH2H3    V_FH2H3(1U)
+
+#define S_FH1    4
+#define V_FH1(x) ((x) << S_FH1)
+#define F_FH1    V_FH1(1U)
+
+#define S_FH1SN    3
+#define V_FH1SN(x) ((x) << S_FH1SN)
+#define F_FH1SN    V_FH1SN(1U)
+
+#define S_FNRDF    2
+#define V_FNRDF(x) ((x) << S_FNRDF)
+#define F_FNRDF    V_FNRDF(1U)
+
+#define S_FADAC    0
+#define V_FADAC(x) ((x) << S_FADAC)
+#define F_FADAC    V_FADAC(1U)
+
+#define A_XGMAC_PORT_HSS_RXB_CFG_MODE 0x1980
+#define A_XGMAC_PORT_HSS_RXB_TEST_CTRL 0x1984
+#define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_CTRL 0x1988
+#define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_OFFSET_CTRL 0x198c
+#define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION1 0x1990
+#define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION2 0x1994
+#define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_STATIC_PH_OFFSET 0x1998
+#define A_XGMAC_PORT_HSS_RXB_SIGDET_CTRL 0x199c
+#define A_XGMAC_PORT_HSS_RXB_DFE_CTRL 0x19a0
+#define A_XGMAC_PORT_HSS_RXB_DFE_DATA_EDGE_SAMPLE 0x19a4
+#define A_XGMAC_PORT_HSS_RXB_DFE_AMP_SAMPLE 0x19a8
+#define A_XGMAC_PORT_HSS_RXB_VGA_CTRL1 0x19ac
+#define A_XGMAC_PORT_HSS_RXB_VGA_CTRL2 0x19b0
+#define A_XGMAC_PORT_HSS_RXB_VGA_CTRL3 0x19b4
+#define A_XGMAC_PORT_HSS_RXB_DFE_D00_D01_OFFSET 0x19b8
+#define A_XGMAC_PORT_HSS_RXB_DFE_D10_D11_OFFSET 0x19bc
+#define A_XGMAC_PORT_HSS_RXB_DFE_E0_E1_OFFSET 0x19c0
+#define A_XGMAC_PORT_HSS_RXB_DACA_OFFSET 0x19c4
+#define A_XGMAC_PORT_HSS_RXB_DACAP_DAC_AN_OFFSET 0x19c8
+#define A_XGMAC_PORT_HSS_RXB_DACA_MIN 0x19cc
+#define A_XGMAC_PORT_HSS_RXB_ADAC_CTRL 0x19d0
+#define A_XGMAC_PORT_HSS_RXB_DIGITAL_EYE_CTRL 0x19d4
+#define A_XGMAC_PORT_HSS_RXB_DIGITAL_EYE_METRICS 0x19d8
+#define A_XGMAC_PORT_HSS_RXB_DFE_H1 0x19dc
+#define A_XGMAC_PORT_HSS_RXB_DFE_H2 0x19e0
+#define A_XGMAC_PORT_HSS_RXB_DFE_H3 0x19e4
+#define A_XGMAC_PORT_HSS_RXB_DFE_H4 0x19e8
+#define A_XGMAC_PORT_HSS_RXB_DFE_H5 0x19ec
+#define A_XGMAC_PORT_HSS_RXB_DAC_DPC 0x19f0
+#define A_XGMAC_PORT_HSS_RXB_DDC 0x19f4
+#define A_XGMAC_PORT_HSS_RXB_INTERNAL_STATUS 0x19f8
+#define A_XGMAC_PORT_HSS_RXB_DFE_FUNC_CTRL 0x19fc
+#define A_XGMAC_PORT_HSS_TXC_MODE_CFG 0x1a00
+#define A_XGMAC_PORT_HSS_TXC_TEST_CTRL 0x1a04
+#define A_XGMAC_PORT_HSS_TXC_COEFF_CTRL 0x1a08
+#define A_XGMAC_PORT_HSS_TXC_DRIVER_MODE 0x1a0c
+#define A_XGMAC_PORT_HSS_TXC_DRIVER_OVR_CTRL 0x1a10
+#define A_XGMAC_PORT_HSS_TXC_TDM_BIASGEN_STANDBY_TIMER 0x1a14
+#define A_XGMAC_PORT_HSS_TXC_TDM_BIASGEN_PWRON_TIMER 0x1a18
+#define A_XGMAC_PORT_HSS_TXC_TAP0_COEFF 0x1a20
+#define A_XGMAC_PORT_HSS_TXC_TAP1_COEFF 0x1a24
+#define A_XGMAC_PORT_HSS_TXC_TAP2_COEFF 0x1a28
+#define A_XGMAC_PORT_HSS_TXC_PWR 0x1a30
+#define A_XGMAC_PORT_HSS_TXC_POLARITY 0x1a34
+#define A_XGMAC_PORT_HSS_TXC_8023AP_AE_CMD 0x1a38
+#define A_XGMAC_PORT_HSS_TXC_8023AP_AE_STATUS 0x1a3c
+#define A_XGMAC_PORT_HSS_TXC_TAP0_IDAC_OVR 0x1a40
+#define A_XGMAC_PORT_HSS_TXC_TAP1_IDAC_OVR 0x1a44
+#define A_XGMAC_PORT_HSS_TXC_TAP2_IDAC_OVR 0x1a48
+#define A_XGMAC_PORT_HSS_TXC_PWR_DAC_OVR 0x1a50
+#define A_XGMAC_PORT_HSS_TXC_PWR_DAC 0x1a54
+#define A_XGMAC_PORT_HSS_TXC_TAP0_IDAC_APP 0x1a60
+#define A_XGMAC_PORT_HSS_TXC_TAP1_IDAC_APP 0x1a64
+#define A_XGMAC_PORT_HSS_TXC_TAP2_IDAC_APP 0x1a68
+#define A_XGMAC_PORT_HSS_TXC_SEG_DIS_APP 0x1a70
+#define A_XGMAC_PORT_HSS_TXC_EXT_ADDR_DATA 0x1a78
+#define A_XGMAC_PORT_HSS_TXC_EXT_ADDR 0x1a7c
+#define A_XGMAC_PORT_HSS_TXD_MODE_CFG 0x1a80
+#define A_XGMAC_PORT_HSS_TXD_TEST_CTRL 0x1a84
+#define A_XGMAC_PORT_HSS_TXD_COEFF_CTRL 0x1a88
+#define A_XGMAC_PORT_HSS_TXD_DRIVER_MODE 0x1a8c
+#define A_XGMAC_PORT_HSS_TXD_DRIVER_OVR_CTRL 0x1a90
+#define A_XGMAC_PORT_HSS_TXD_TDM_BIASGEN_STANDBY_TIMER 0x1a94
+#define A_XGMAC_PORT_HSS_TXD_TDM_BIASGEN_PWRON_TIMER 0x1a98
+#define A_XGMAC_PORT_HSS_TXD_TAP0_COEFF 0x1aa0
+#define A_XGMAC_PORT_HSS_TXD_TAP1_COEFF 0x1aa4
+#define A_XGMAC_PORT_HSS_TXD_TAP2_COEFF 0x1aa8
+#define A_XGMAC_PORT_HSS_TXD_PWR 0x1ab0
+#define A_XGMAC_PORT_HSS_TXD_POLARITY 0x1ab4
+#define A_XGMAC_PORT_HSS_TXD_8023AP_AE_CMD 0x1ab8
+#define A_XGMAC_PORT_HSS_TXD_8023AP_AE_STATUS 0x1abc
+#define A_XGMAC_PORT_HSS_TXD_TAP0_IDAC_OVR 0x1ac0
+#define A_XGMAC_PORT_HSS_TXD_TAP1_IDAC_OVR 0x1ac4
+#define A_XGMAC_PORT_HSS_TXD_TAP2_IDAC_OVR 0x1ac8
+#define A_XGMAC_PORT_HSS_TXD_PWR_DAC_OVR 0x1ad0
+#define A_XGMAC_PORT_HSS_TXD_PWR_DAC 0x1ad4
+#define A_XGMAC_PORT_HSS_TXD_TAP0_IDAC_APP 0x1ae0
+#define A_XGMAC_PORT_HSS_TXD_TAP1_IDAC_APP 0x1ae4
+#define A_XGMAC_PORT_HSS_TXD_TAP2_IDAC_APP 0x1ae8
+#define A_XGMAC_PORT_HSS_TXD_SEG_DIS_APP 0x1af0
+#define A_XGMAC_PORT_HSS_TXD_EXT_ADDR_DATA 0x1af8
+#define A_XGMAC_PORT_HSS_TXD_EXT_ADDR 0x1afc
+#define A_XGMAC_PORT_HSS_RXC_CFG_MODE 0x1b00
+#define A_XGMAC_PORT_HSS_RXC_TEST_CTRL 0x1b04
+#define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_CTRL 0x1b08
+#define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_OFFSET_CTRL 0x1b0c
+#define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION1 0x1b10
+#define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION2 0x1b14
+#define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_STATIC_PH_OFFSET 0x1b18
+#define A_XGMAC_PORT_HSS_RXC_SIGDET_CTRL 0x1b1c
+#define A_XGMAC_PORT_HSS_RXC_DFE_CTRL 0x1b20
+#define A_XGMAC_PORT_HSS_RXC_DFE_DATA_EDGE_SAMPLE 0x1b24
+#define A_XGMAC_PORT_HSS_RXC_DFE_AMP_SAMPLE 0x1b28
+#define A_XGMAC_PORT_HSS_RXC_VGA_CTRL1 0x1b2c
+#define A_XGMAC_PORT_HSS_RXC_VGA_CTRL2 0x1b30
+#define A_XGMAC_PORT_HSS_RXC_VGA_CTRL3 0x1b34
+#define A_XGMAC_PORT_HSS_RXC_DFE_D00_D01_OFFSET 0x1b38
+#define A_XGMAC_PORT_HSS_RXC_DFE_D10_D11_OFFSET 0x1b3c
+#define A_XGMAC_PORT_HSS_RXC_DFE_E0_E1_OFFSET 0x1b40
+#define A_XGMAC_PORT_HSS_RXC_DACA_OFFSET 0x1b44
+#define A_XGMAC_PORT_HSS_RXC_DACAP_DAC_AN_OFFSET 0x1b48
+#define A_XGMAC_PORT_HSS_RXC_DACA_MIN 0x1b4c
+#define A_XGMAC_PORT_HSS_RXC_ADAC_CTRL 0x1b50
+#define A_XGMAC_PORT_HSS_RXC_DIGITAL_EYE_CTRL 0x1b54
+#define A_XGMAC_PORT_HSS_RXC_DIGITAL_EYE_METRICS 0x1b58
+#define A_XGMAC_PORT_HSS_RXC_DFE_H1 0x1b5c
+#define A_XGMAC_PORT_HSS_RXC_DFE_H2 0x1b60
+#define A_XGMAC_PORT_HSS_RXC_DFE_H3 0x1b64
+#define A_XGMAC_PORT_HSS_RXC_DFE_H4 0x1b68
+#define A_XGMAC_PORT_HSS_RXC_DFE_H5 0x1b6c
+#define A_XGMAC_PORT_HSS_RXC_DAC_DPC 0x1b70
+#define A_XGMAC_PORT_HSS_RXC_DDC 0x1b74
+#define A_XGMAC_PORT_HSS_RXC_INTERNAL_STATUS 0x1b78
+#define A_XGMAC_PORT_HSS_RXC_DFE_FUNC_CTRL 0x1b7c
+#define A_XGMAC_PORT_HSS_RXD_CFG_MODE 0x1b80
+#define A_XGMAC_PORT_HSS_RXD_TEST_CTRL 0x1b84
+#define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_CTRL 0x1b88
+#define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_OFFSET_CTRL 0x1b8c
+#define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION1 0x1b90
+#define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION2 0x1b94
+#define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_STATIC_PH_OFFSET 0x1b98
+#define A_XGMAC_PORT_HSS_RXD_SIGDET_CTRL 0x1b9c
+#define A_XGMAC_PORT_HSS_RXD_DFE_CTRL 0x1ba0
+#define A_XGMAC_PORT_HSS_RXD_DFE_DATA_EDGE_SAMPLE 0x1ba4
+#define A_XGMAC_PORT_HSS_RXD_DFE_AMP_SAMPLE 0x1ba8
+#define A_XGMAC_PORT_HSS_RXD_VGA_CTRL1 0x1bac
+#define A_XGMAC_PORT_HSS_RXD_VGA_CTRL2 0x1bb0
+#define A_XGMAC_PORT_HSS_RXD_VGA_CTRL3 0x1bb4
+#define A_XGMAC_PORT_HSS_RXD_DFE_D00_D01_OFFSET 0x1bb8
+#define A_XGMAC_PORT_HSS_RXD_DFE_D10_D11_OFFSET 0x1bbc
+#define A_XGMAC_PORT_HSS_RXD_DFE_E0_E1_OFFSET 0x1bc0
+#define A_XGMAC_PORT_HSS_RXD_DACA_OFFSET 0x1bc4
+#define A_XGMAC_PORT_HSS_RXD_DACAP_DAC_AN_OFFSET 0x1bc8
+#define A_XGMAC_PORT_HSS_RXD_DACA_MIN 0x1bcc
+#define A_XGMAC_PORT_HSS_RXD_ADAC_CTRL 0x1bd0
+#define A_XGMAC_PORT_HSS_RXD_DIGITAL_EYE_CTRL 0x1bd4
+#define A_XGMAC_PORT_HSS_RXD_DIGITAL_EYE_METRICS 0x1bd8
+#define A_XGMAC_PORT_HSS_RXD_DFE_H1 0x1bdc
+#define A_XGMAC_PORT_HSS_RXD_DFE_H2 0x1be0
+#define A_XGMAC_PORT_HSS_RXD_DFE_H3 0x1be4
+#define A_XGMAC_PORT_HSS_RXD_DFE_H4 0x1be8
+#define A_XGMAC_PORT_HSS_RXD_DFE_H5 0x1bec
+#define A_XGMAC_PORT_HSS_RXD_DAC_DPC 0x1bf0
+#define A_XGMAC_PORT_HSS_RXD_DDC 0x1bf4
+#define A_XGMAC_PORT_HSS_RXD_INTERNAL_STATUS 0x1bf8
+#define A_XGMAC_PORT_HSS_RXD_DFE_FUNC_CTRL 0x1bfc
+#define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_0 0x1c00
+
+#define S_BSELO    0
+#define M_BSELO    0xfU
+#define V_BSELO(x) ((x) << S_BSELO)
+#define G_BSELO(x) (((x) >> S_BSELO) & M_BSELO)
+
+#define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_1 0x1c04
+
+#define S_LDET    4
+#define V_LDET(x) ((x) << S_LDET)
+#define F_LDET    V_LDET(1U)
+
+#define S_CCERR    3
+#define V_CCERR(x) ((x) << S_CCERR)
+#define F_CCERR    V_CCERR(1U)
+
+#define S_CCCMP    2
+#define V_CCCMP(x) ((x) << S_CCCMP)
+#define F_CCCMP    V_CCCMP(1U)
+
+#define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_2 0x1c08
+
+#define S_BSELI    0
+#define M_BSELI    0xfU
+#define V_BSELI(x) ((x) << S_BSELI)
+#define G_BSELI(x) (((x) >> S_BSELI) & M_BSELI)
+
+#define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_3 0x1c0c
+
+#define S_VISEL    4
+#define V_VISEL(x) ((x) << S_VISEL)
+#define F_VISEL    V_VISEL(1U)
+
+#define S_FMIN    3
+#define V_FMIN(x) ((x) << S_FMIN)
+#define F_FMIN    V_FMIN(1U)
+
+#define S_FMAX    2
+#define V_FMAX(x) ((x) << S_FMAX)
+#define F_FMAX    V_FMAX(1U)
+
+#define S_CVHOLD    1
+#define V_CVHOLD(x) ((x) << S_CVHOLD)
+#define F_CVHOLD    V_CVHOLD(1U)
+
+#define S_TCDIS    0
+#define V_TCDIS(x) ((x) << S_TCDIS)
+#define F_TCDIS    V_TCDIS(1U)
+
+#define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_4 0x1c10
+
+#define S_CMETH    2
+#define V_CMETH(x) ((x) << S_CMETH)
+#define F_CMETH    V_CMETH(1U)
+
+#define S_RECAL    1
+#define V_RECAL(x) ((x) << S_RECAL)
+#define F_RECAL    V_RECAL(1U)
+
+#define S_CCLD    0
+#define V_CCLD(x) ((x) << S_CCLD)
+#define F_CCLD    V_CCLD(1U)
+
+#define A_XGMAC_PORT_HSS_ANALOG_TEST_MUX 0x1c14
+
+#define S_ATST    0
+#define M_ATST    0x1fU
+#define V_ATST(x) ((x) << S_ATST)
+#define G_ATST(x) (((x) >> S_ATST) & M_ATST)
+
+#define A_XGMAC_PORT_HSS_PORT_EN_0 0x1c18
+
+#define S_RXDEN    7
+#define V_RXDEN(x) ((x) << S_RXDEN)
+#define F_RXDEN    V_RXDEN(1U)
+
+#define S_RXCEN    6
+#define V_RXCEN(x) ((x) << S_RXCEN)
+#define F_RXCEN    V_RXCEN(1U)
+
+#define S_TXDEN    5
+#define V_TXDEN(x) ((x) << S_TXDEN)
+#define F_TXDEN    V_TXDEN(1U)
+
+#define S_TXCEN    4
+#define V_TXCEN(x) ((x) << S_TXCEN)
+#define F_TXCEN    V_TXCEN(1U)
+
+#define S_RXBEN    3
+#define V_RXBEN(x) ((x) << S_RXBEN)
+#define F_RXBEN    V_RXBEN(1U)
+
+#define S_RXAEN    2
+#define V_RXAEN(x) ((x) << S_RXAEN)
+#define F_RXAEN    V_RXAEN(1U)
+
+#define S_TXBEN    1
+#define V_TXBEN(x) ((x) << S_TXBEN)
+#define F_TXBEN    V_TXBEN(1U)
+
+#define S_TXAEN    0
+#define V_TXAEN(x) ((x) << S_TXAEN)
+#define F_TXAEN    V_TXAEN(1U)
+
+#define A_XGMAC_PORT_HSS_PORT_RESET_0 0x1c20
+
+#define S_RXDRST    7
+#define V_RXDRST(x) ((x) << S_RXDRST)
+#define F_RXDRST    V_RXDRST(1U)
+
+#define S_RXCRST    6
+#define V_RXCRST(x) ((x) << S_RXCRST)
+#define F_RXCRST    V_RXCRST(1U)
+
+#define S_TXDRST    5
+#define V_TXDRST(x) ((x) << S_TXDRST)
+#define F_TXDRST    V_TXDRST(1U)
+
+#define S_TXCRST    4
+#define V_TXCRST(x) ((x) << S_TXCRST)
+#define F_TXCRST    V_TXCRST(1U)
+
+#define S_RXBRST    3
+#define V_RXBRST(x) ((x) << S_RXBRST)
+#define F_RXBRST    V_RXBRST(1U)
+
+#define S_RXARST    2
+#define V_RXARST(x) ((x) << S_RXARST)
+#define F_RXARST    V_RXARST(1U)
+
+#define S_TXBRST    1
+#define V_TXBRST(x) ((x) << S_TXBRST)
+#define F_TXBRST    V_TXBRST(1U)
+
+#define S_TXARST    0
+#define V_TXARST(x) ((x) << S_TXARST)
+#define F_TXARST    V_TXARST(1U)
+
+#define A_XGMAC_PORT_HSS_CHARGE_PUMP_CTRL 0x1c28
+
+#define S_ENCPIS    2
+#define V_ENCPIS(x) ((x) << S_ENCPIS)
+#define F_ENCPIS    V_ENCPIS(1U)
+
+#define S_CPISEL    0
+#define M_CPISEL    0x3U
+#define V_CPISEL(x) ((x) << S_CPISEL)
+#define G_CPISEL(x) (((x) >> S_CPISEL) & M_CPISEL)
+
+#define A_XGMAC_PORT_HSS_BAND_GAP_CTRL 0x1c2c
+
+#define S_BGCTL    0
+#define M_BGCTL    0x1fU
+#define V_BGCTL(x) ((x) << S_BGCTL)
+#define G_BGCTL(x) (((x) >> S_BGCTL) & M_BGCTL)
+
+#define A_XGMAC_PORT_HSS_LOFREQ_OVR 0x1c30
+
+#define S_LFREQ2    3
+#define V_LFREQ2(x) ((x) << S_LFREQ2)
+#define F_LFREQ2    V_LFREQ2(1U)
+
+#define S_LFREQ1    2
+#define V_LFREQ1(x) ((x) << S_LFREQ1)
+#define F_LFREQ1    V_LFREQ1(1U)
+
+#define S_LFREQO    1
+#define V_LFREQO(x) ((x) << S_LFREQO)
+#define F_LFREQO    V_LFREQO(1U)
+
+#define S_LFSEL    0
+#define V_LFSEL(x) ((x) << S_LFSEL)
+#define F_LFSEL    V_LFSEL(1U)
+
+#define A_XGMAC_PORT_HSS_VOLTAGE_BOOST_CTRL 0x1c38
+
+#define S_PFVAL    2
+#define V_PFVAL(x) ((x) << S_PFVAL)
+#define F_PFVAL    V_PFVAL(1U)
+
+#define S_PFEN    1
+#define V_PFEN(x) ((x) << S_PFEN)
+#define F_PFEN    V_PFEN(1U)
+
+#define S_VBADJ    0
+#define V_VBADJ(x) ((x) << S_VBADJ)
+#define F_VBADJ    V_VBADJ(1U)
+
+#define A_XGMAC_PORT_HSS_TX_MODE_CFG 0x1c80
+#define A_XGMAC_PORT_HSS_TXTEST_CTRL 0x1c84
+#define A_XGMAC_PORT_HSS_TX_COEFF_CTRL 0x1c88
+#define A_XGMAC_PORT_HSS_TX_DRIVER_MODE 0x1c8c
+#define A_XGMAC_PORT_HSS_TX_DRIVER_OVR_CTRL 0x1c90
+#define A_XGMAC_PORT_HSS_TX_TDM_BIASGEN_STANDBY_TIMER 0x1c94
+#define A_XGMAC_PORT_HSS_TX_TDM_BIASGEN_PWRON_TIMER 0x1c98
+#define A_XGMAC_PORT_HSS_TX_TAP0_COEFF 0x1ca0
+#define A_XGMAC_PORT_HSS_TX_TAP1_COEFF 0x1ca4
+#define A_XGMAC_PORT_HSS_TX_TAP2_COEFF 0x1ca8
+#define A_XGMAC_PORT_HSS_TX_PWR 0x1cb0
+#define A_XGMAC_PORT_HSS_TX_POLARITY 0x1cb4
+#define A_XGMAC_PORT_HSS_TX_8023AP_AE_CMD 0x1cb8
+#define A_XGMAC_PORT_HSS_TX_8023AP_AE_STATUS 0x1cbc
+#define A_XGMAC_PORT_HSS_TX_TAP0_IDAC_OVR 0x1cc0
+#define A_XGMAC_PORT_HSS_TX_TAP1_IDAC_OVR 0x1cc4
+#define A_XGMAC_PORT_HSS_TX_TAP2_IDAC_OVR 0x1cc8
+#define A_XGMAC_PORT_HSS_TX_PWR_DAC_OVR 0x1cd0
+#define A_XGMAC_PORT_HSS_TX_PWR_DAC 0x1cd4
+#define A_XGMAC_PORT_HSS_TX_TAP0_IDAC_APP 0x1ce0
+#define A_XGMAC_PORT_HSS_TX_TAP1_IDAC_APP 0x1ce4
+#define A_XGMAC_PORT_HSS_TX_TAP2_IDAC_APP 0x1ce8
+#define A_XGMAC_PORT_HSS_TX_SEG_DIS_APP 0x1cf0
+#define A_XGMAC_PORT_HSS_TX_EXT_ADDR_DATA 0x1cf8
+#define A_XGMAC_PORT_HSS_TX_EXT_ADDR 0x1cfc
+#define A_XGMAC_PORT_HSS_RX_CFG_MODE 0x1d00
+#define A_XGMAC_PORT_HSS_RXTEST_CTRL 0x1d04
+#define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_CTRL 0x1d08
+#define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_OFFSET_CTRL 0x1d0c
+#define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION1 0x1d10
+#define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION2 0x1d14
+#define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_STATIC_PH_OFFSET 0x1d18
+#define A_XGMAC_PORT_HSS_RX_SIGDET_CTRL 0x1d1c
+#define A_XGMAC_PORT_HSS_RX_DFE_CTRL 0x1d20
+#define A_XGMAC_PORT_HSS_RX_DFE_DATA_EDGE_SAMPLE 0x1d24
+#define A_XGMAC_PORT_HSS_RX_DFE_AMP_SAMPLE 0x1d28
+#define A_XGMAC_PORT_HSS_RX_VGA_CTRL1 0x1d2c
+#define A_XGMAC_PORT_HSS_RX_VGA_CTRL2 0x1d30
+#define A_XGMAC_PORT_HSS_RX_VGA_CTRL3 0x1d34
+#define A_XGMAC_PORT_HSS_RX_DFE_D00_D01_OFFSET 0x1d38
+#define A_XGMAC_PORT_HSS_RX_DFE_D10_D11_OFFSET 0x1d3c
+#define A_XGMAC_PORT_HSS_RX_DFE_E0_E1_OFFSET 0x1d40
+#define A_XGMAC_PORT_HSS_RX_DACA_OFFSET 0x1d44
+#define A_XGMAC_PORT_HSS_RX_DACAP_DAC_AN_OFFSET 0x1d48
+#define A_XGMAC_PORT_HSS_RX_DACA_MIN 0x1d4c
+#define A_XGMAC_PORT_HSS_RX_ADAC_CTRL 0x1d50
+#define A_XGMAC_PORT_HSS_RX_DIGITAL_EYE_CTRL 0x1d54
+#define A_XGMAC_PORT_HSS_RX_DIGITAL_EYE_METRICS 0x1d58
+#define A_XGMAC_PORT_HSS_RX_DFE_H1 0x1d5c
+#define A_XGMAC_PORT_HSS_RX_DFE_H2 0x1d60
+#define A_XGMAC_PORT_HSS_RX_DFE_H3 0x1d64
+#define A_XGMAC_PORT_HSS_RX_DFE_H4 0x1d68
+#define A_XGMAC_PORT_HSS_RX_DFE_H5 0x1d6c
+#define A_XGMAC_PORT_HSS_RX_DAC_DPC 0x1d70
+#define A_XGMAC_PORT_HSS_RX_DDC 0x1d74
+#define A_XGMAC_PORT_HSS_RX_INTERNAL_STATUS 0x1d78
+#define A_XGMAC_PORT_HSS_RX_DFE_FUNC_CTRL 0x1d7c
+#define A_XGMAC_PORT_HSS_TXRX_CFG_MODE 0x1e00
+#define A_XGMAC_PORT_HSS_TXRXTEST_CTRL 0x1e04
+
+/* registers for module UP */
+#define UP_BASE_ADDR 0x0
+
+#define A_UP_IBQ_CONFIG 0x0
+
+#define S_IBQGEN2    2
+#define M_IBQGEN2    0x3fffffffU
+#define V_IBQGEN2(x) ((x) << S_IBQGEN2)
+#define G_IBQGEN2(x) (((x) >> S_IBQGEN2) & M_IBQGEN2)
+
+#define S_IBQBUSY    1
+#define V_IBQBUSY(x) ((x) << S_IBQBUSY)
+#define F_IBQBUSY    V_IBQBUSY(1U)
+
+#define S_IBQEN    0
+#define V_IBQEN(x) ((x) << S_IBQEN)
+#define F_IBQEN    V_IBQEN(1U)
+
+#define A_UP_OBQ_CONFIG 0x4
+
+#define S_OBQGEN2    2
+#define M_OBQGEN2    0x3fffffffU
+#define V_OBQGEN2(x) ((x) << S_OBQGEN2)
+#define G_OBQGEN2(x) (((x) >> S_OBQGEN2) & M_OBQGEN2)
+
+#define S_OBQBUSY    1
+#define V_OBQBUSY(x) ((x) << S_OBQBUSY)
+#define F_OBQBUSY    V_OBQBUSY(1U)
+
+#define S_OBQEN    0
+#define V_OBQEN(x) ((x) << S_OBQEN)
+#define F_OBQEN    V_OBQEN(1U)
+
+#define A_UP_IBQ_GEN 0x8
+
+#define S_IBQGEN0    22
+#define M_IBQGEN0    0x3ffU
+#define V_IBQGEN0(x) ((x) << S_IBQGEN0)
+#define G_IBQGEN0(x) (((x) >> S_IBQGEN0) & M_IBQGEN0)
+
+#define S_IBQTSCHCHNLRDY    18
+#define M_IBQTSCHCHNLRDY    0xfU
+#define V_IBQTSCHCHNLRDY(x) ((x) << S_IBQTSCHCHNLRDY)
+#define G_IBQTSCHCHNLRDY(x) (((x) >> S_IBQTSCHCHNLRDY) & M_IBQTSCHCHNLRDY)
+
+#define S_IBQMBVFSTATUS    17
+#define V_IBQMBVFSTATUS(x) ((x) << S_IBQMBVFSTATUS)
+#define F_IBQMBVFSTATUS    V_IBQMBVFSTATUS(1U)
+
+#define S_IBQMBSTATUS    16
+#define V_IBQMBSTATUS(x) ((x) << S_IBQMBSTATUS)
+#define F_IBQMBSTATUS    V_IBQMBSTATUS(1U)
+
+#define S_IBQGEN1    6
+#define M_IBQGEN1    0x3ffU
+#define V_IBQGEN1(x) ((x) << S_IBQGEN1)
+#define G_IBQGEN1(x) (((x) >> S_IBQGEN1) & M_IBQGEN1)
+
+#define S_IBQEMPTY    0
+#define M_IBQEMPTY    0x3fU
+#define V_IBQEMPTY(x) ((x) << S_IBQEMPTY)
+#define G_IBQEMPTY(x) (((x) >> S_IBQEMPTY) & M_IBQEMPTY)
+
+#define A_UP_OBQ_GEN 0xc
+
+#define S_OBQGEN    6
+#define M_OBQGEN    0x3ffffffU
+#define V_OBQGEN(x) ((x) << S_OBQGEN)
+#define G_OBQGEN(x) (((x) >> S_OBQGEN) & M_OBQGEN)
+
+#define S_OBQFULL    0
+#define M_OBQFULL    0x3fU
+#define V_OBQFULL(x) ((x) << S_OBQFULL)
+#define G_OBQFULL(x) (((x) >> S_OBQFULL) & M_OBQFULL)
+
+#define S_T5_OBQGEN    8
+#define M_T5_OBQGEN    0xffffffU
+#define V_T5_OBQGEN(x) ((x) << S_T5_OBQGEN)
+#define G_T5_OBQGEN(x) (((x) >> S_T5_OBQGEN) & M_T5_OBQGEN)
+
+#define S_T5_OBQFULL    0
+#define M_T5_OBQFULL    0xffU
+#define V_T5_OBQFULL(x) ((x) << S_T5_OBQFULL)
+#define G_T5_OBQFULL(x) (((x) >> S_T5_OBQFULL) & M_T5_OBQFULL)
+
+#define A_UP_IBQ_0_RDADDR 0x10
+
+#define S_QUEID    13
+#define M_QUEID    0x7ffffU
+#define V_QUEID(x) ((x) << S_QUEID)
+#define G_QUEID(x) (((x) >> S_QUEID) & M_QUEID)
+
+#define S_IBQRDADDR    0
+#define M_IBQRDADDR    0x1fffU
+#define V_IBQRDADDR(x) ((x) << S_IBQRDADDR)
+#define G_IBQRDADDR(x) (((x) >> S_IBQRDADDR) & M_IBQRDADDR)
+
+#define A_UP_IBQ_0_WRADDR 0x14
+
+#define S_IBQWRADDR    0
+#define M_IBQWRADDR    0x1fffU
+#define V_IBQWRADDR(x) ((x) << S_IBQWRADDR)
+#define G_IBQWRADDR(x) (((x) >> S_IBQWRADDR) & M_IBQWRADDR)
+
+#define A_UP_IBQ_0_STATUS 0x18
+
+#define S_QUEERRFRAME    31
+#define V_QUEERRFRAME(x) ((x) << S_QUEERRFRAME)
+#define F_QUEERRFRAME    V_QUEERRFRAME(1U)
+
+#define S_QUEREMFLITS    0
+#define M_QUEREMFLITS    0x7ffU
+#define V_QUEREMFLITS(x) ((x) << S_QUEREMFLITS)
+#define G_QUEREMFLITS(x) (((x) >> S_QUEREMFLITS) & M_QUEREMFLITS)
+
+#define A_UP_IBQ_0_PKTCNT 0x1c
+
+#define S_QUEEOPCNT    16
+#define M_QUEEOPCNT    0xfffU
+#define V_QUEEOPCNT(x) ((x) << S_QUEEOPCNT)
+#define G_QUEEOPCNT(x) (((x) >> S_QUEEOPCNT) & M_QUEEOPCNT)
+
+#define S_QUESOPCNT    0
+#define M_QUESOPCNT    0xfffU
+#define V_QUESOPCNT(x) ((x) << S_QUESOPCNT)
+#define G_QUESOPCNT(x) (((x) >> S_QUESOPCNT) & M_QUESOPCNT)
+
+#define A_UP_IBQ_1_RDADDR 0x20
+#define A_UP_IBQ_1_WRADDR 0x24
+#define A_UP_IBQ_1_STATUS 0x28
+#define A_UP_IBQ_1_PKTCNT 0x2c
+#define A_UP_IBQ_2_RDADDR 0x30
+#define A_UP_IBQ_2_WRADDR 0x34
+#define A_UP_IBQ_2_STATUS 0x38
+#define A_UP_IBQ_2_PKTCNT 0x3c
+#define A_UP_IBQ_3_RDADDR 0x40
+#define A_UP_IBQ_3_WRADDR 0x44
+#define A_UP_IBQ_3_STATUS 0x48
+#define A_UP_IBQ_3_PKTCNT 0x4c
+#define A_UP_IBQ_4_RDADDR 0x50
+#define A_UP_IBQ_4_WRADDR 0x54
+#define A_UP_IBQ_4_STATUS 0x58
+#define A_UP_IBQ_4_PKTCNT 0x5c
+#define A_UP_IBQ_5_RDADDR 0x60
+#define A_UP_IBQ_5_WRADDR 0x64
+#define A_UP_IBQ_5_STATUS 0x68
+#define A_UP_IBQ_5_PKTCNT 0x6c
+#define A_UP_OBQ_0_RDADDR 0x70
+
+#define S_OBQID    15
+#define M_OBQID    0x1ffffU
+#define V_OBQID(x) ((x) << S_OBQID)
+#define G_OBQID(x) (((x) >> S_OBQID) & M_OBQID)
+
+#define S_QUERDADDR    0
+#define M_QUERDADDR    0x7fffU
+#define V_QUERDADDR(x) ((x) << S_QUERDADDR)
+#define G_QUERDADDR(x) (((x) >> S_QUERDADDR) & M_QUERDADDR)
+
+#define A_UP_OBQ_0_WRADDR 0x74
+
+#define S_QUEWRADDR    0
+#define M_QUEWRADDR    0x7fffU
+#define V_QUEWRADDR(x) ((x) << S_QUEWRADDR)
+#define G_QUEWRADDR(x) (((x) >> S_QUEWRADDR) & M_QUEWRADDR)
+
+#define A_UP_OBQ_0_STATUS 0x78
+#define A_UP_OBQ_0_PKTCNT 0x7c
+#define A_UP_OBQ_1_RDADDR 0x80
+#define A_UP_OBQ_1_WRADDR 0x84
+#define A_UP_OBQ_1_STATUS 0x88
+#define A_UP_OBQ_1_PKTCNT 0x8c
+#define A_UP_OBQ_2_RDADDR 0x90
+#define A_UP_OBQ_2_WRADDR 0x94
+#define A_UP_OBQ_2_STATUS 0x98
+#define A_UP_OBQ_2_PKTCNT 0x9c
+#define A_UP_OBQ_3_RDADDR 0xa0
+#define A_UP_OBQ_3_WRADDR 0xa4
+#define A_UP_OBQ_3_STATUS 0xa8
+#define A_UP_OBQ_3_PKTCNT 0xac
+#define A_UP_OBQ_4_RDADDR 0xb0
+#define A_UP_OBQ_4_WRADDR 0xb4
+#define A_UP_OBQ_4_STATUS 0xb8
+#define A_UP_OBQ_4_PKTCNT 0xbc
+#define A_UP_OBQ_5_RDADDR 0xc0
+#define A_UP_OBQ_5_WRADDR 0xc4
+#define A_UP_OBQ_5_STATUS 0xc8
+#define A_UP_OBQ_5_PKTCNT 0xcc
+#define A_UP_IBQ_0_CONFIG 0xd0
+
+#define S_QUESIZE    26
+#define M_QUESIZE    0x3fU
+#define V_QUESIZE(x) ((x) << S_QUESIZE)
+#define G_QUESIZE(x) (((x) >> S_QUESIZE) & M_QUESIZE)
+
+#define S_QUEBASE    8
+#define M_QUEBASE    0x3fU
+#define V_QUEBASE(x) ((x) << S_QUEBASE)
+#define G_QUEBASE(x) (((x) >> S_QUEBASE) & M_QUEBASE)
+
+#define S_QUEDBG8BEN    7
+#define V_QUEDBG8BEN(x) ((x) << S_QUEDBG8BEN)
+#define F_QUEDBG8BEN    V_QUEDBG8BEN(1U)
+
+#define S_QUEBAREADDR    0
+#define V_QUEBAREADDR(x) ((x) << S_QUEBAREADDR)
+#define F_QUEBAREADDR    V_QUEBAREADDR(1U)
+
+#define A_UP_IBQ_0_REALADDR 0xd4
+
+#define S_QUERDADDRWRAP    31
+#define V_QUERDADDRWRAP(x) ((x) << S_QUERDADDRWRAP)
+#define F_QUERDADDRWRAP    V_QUERDADDRWRAP(1U)
+
+#define S_QUEWRADDRWRAP    30
+#define V_QUEWRADDRWRAP(x) ((x) << S_QUEWRADDRWRAP)
+#define F_QUEWRADDRWRAP    V_QUEWRADDRWRAP(1U)
+
+#define S_QUEMEMADDR    3
+#define M_QUEMEMADDR    0x7ffU
+#define V_QUEMEMADDR(x) ((x) << S_QUEMEMADDR)
+#define G_QUEMEMADDR(x) (((x) >> S_QUEMEMADDR) & M_QUEMEMADDR)
+
+#define A_UP_IBQ_1_CONFIG 0xd8
+#define A_UP_IBQ_1_REALADDR 0xdc
+#define A_UP_IBQ_2_CONFIG 0xe0
+#define A_UP_IBQ_2_REALADDR 0xe4
+#define A_UP_IBQ_3_CONFIG 0xe8
+#define A_UP_IBQ_3_REALADDR 0xec
+#define A_UP_IBQ_4_CONFIG 0xf0
+#define A_UP_IBQ_4_REALADDR 0xf4
+#define A_UP_IBQ_5_CONFIG 0xf8
+#define A_UP_IBQ_5_REALADDR 0xfc
+#define A_UP_OBQ_0_CONFIG 0x100
+#define A_UP_OBQ_0_REALADDR 0x104
+#define A_UP_OBQ_1_CONFIG 0x108
+#define A_UP_OBQ_1_REALADDR 0x10c
+#define A_UP_OBQ_2_CONFIG 0x110
+#define A_UP_OBQ_2_REALADDR 0x114
+#define A_UP_OBQ_3_CONFIG 0x118
+#define A_UP_OBQ_3_REALADDR 0x11c
+#define A_UP_OBQ_4_CONFIG 0x120
+#define A_UP_OBQ_4_REALADDR 0x124
+#define A_UP_OBQ_5_CONFIG 0x128
+#define A_UP_OBQ_5_REALADDR 0x12c
+#define A_UP_MAILBOX_STATUS 0x130
+
+#define S_MBGEN0    20
+#define M_MBGEN0    0xfffU
+#define V_MBGEN0(x) ((x) << S_MBGEN0)
+#define G_MBGEN0(x) (((x) >> S_MBGEN0) & M_MBGEN0)
+
+#define S_GENTIMERTRIGGER    16
+#define M_GENTIMERTRIGGER    0xfU
+#define V_GENTIMERTRIGGER(x) ((x) << S_GENTIMERTRIGGER)
+#define G_GENTIMERTRIGGER(x) (((x) >> S_GENTIMERTRIGGER) & M_GENTIMERTRIGGER)
+
+#define S_MBGEN1    8
+#define M_MBGEN1    0xffU
+#define V_MBGEN1(x) ((x) << S_MBGEN1)
+#define G_MBGEN1(x) (((x) >> S_MBGEN1) & M_MBGEN1)
+
+#define S_MBPFINT    0
+#define M_MBPFINT    0xffU
+#define V_MBPFINT(x) ((x) << S_MBPFINT)
+#define G_MBPFINT(x) (((x) >> S_MBPFINT) & M_MBPFINT)
+
+#define A_UP_UP_DBG_LA_CFG 0x140
+
+#define S_UPDBGLACAPTBUB    31
+#define V_UPDBGLACAPTBUB(x) ((x) << S_UPDBGLACAPTBUB)
+#define F_UPDBGLACAPTBUB    V_UPDBGLACAPTBUB(1U)
+
+#define S_UPDBGLACAPTPCONLY    30
+#define V_UPDBGLACAPTPCONLY(x) ((x) << S_UPDBGLACAPTPCONLY)
+#define F_UPDBGLACAPTPCONLY    V_UPDBGLACAPTPCONLY(1U)
+
+#define S_UPDBGLAMASKSTOP    29
+#define V_UPDBGLAMASKSTOP(x) ((x) << S_UPDBGLAMASKSTOP)
+#define F_UPDBGLAMASKSTOP    V_UPDBGLAMASKSTOP(1U)
+
+#define S_UPDBGLAMASKTRIG    28
+#define V_UPDBGLAMASKTRIG(x) ((x) << S_UPDBGLAMASKTRIG)
+#define F_UPDBGLAMASKTRIG    V_UPDBGLAMASKTRIG(1U)
+
+#define S_UPDBGLAWRPTR    16
+#define M_UPDBGLAWRPTR    0xfffU
+#define V_UPDBGLAWRPTR(x) ((x) << S_UPDBGLAWRPTR)
+#define G_UPDBGLAWRPTR(x) (((x) >> S_UPDBGLAWRPTR) & M_UPDBGLAWRPTR)
+
+#define S_UPDBGLARDPTR    2
+#define M_UPDBGLARDPTR    0xfffU
+#define V_UPDBGLARDPTR(x) ((x) << S_UPDBGLARDPTR)
+#define G_UPDBGLARDPTR(x) (((x) >> S_UPDBGLARDPTR) & M_UPDBGLARDPTR)
+
+#define S_UPDBGLARDEN    1
+#define V_UPDBGLARDEN(x) ((x) << S_UPDBGLARDEN)
+#define F_UPDBGLARDEN    V_UPDBGLARDEN(1U)
+
+#define S_UPDBGLAEN    0
+#define V_UPDBGLAEN(x) ((x) << S_UPDBGLAEN)
+#define F_UPDBGLAEN    V_UPDBGLAEN(1U)
+
+#define S_UPDBGLABUSY    14
+#define V_UPDBGLABUSY(x) ((x) << S_UPDBGLABUSY)
+#define F_UPDBGLABUSY    V_UPDBGLABUSY(1U)
+
+#define A_UP_UP_DBG_LA_DATA 0x144
+#define A_UP_PIO_MST_CONFIG 0x148
+
+#define S_FLSRC    24
+#define M_FLSRC    0x7U
+#define V_FLSRC(x) ((x) << S_FLSRC)
+#define G_FLSRC(x) (((x) >> S_FLSRC) & M_FLSRC)
+
+#define S_SEPROT    23
+#define V_SEPROT(x) ((x) << S_SEPROT)
+#define F_SEPROT    V_SEPROT(1U)
+
+#define S_SESRC    20
+#define M_SESRC    0x7U
+#define V_SESRC(x) ((x) << S_SESRC)
+#define G_SESRC(x) (((x) >> S_SESRC) & M_SESRC)
+
+#define S_UPRGN    19
+#define V_UPRGN(x) ((x) << S_UPRGN)
+#define F_UPRGN    V_UPRGN(1U)
+
+#define S_UPPF    16
+#define M_UPPF    0x7U
+#define V_UPPF(x) ((x) << S_UPPF)
+#define G_UPPF(x) (((x) >> S_UPPF) & M_UPPF)
+
+#define S_UPRID    0
+#define M_UPRID    0xffffU
+#define V_UPRID(x) ((x) << S_UPRID)
+#define G_UPRID(x) (((x) >> S_UPRID) & M_UPRID)
+
+#define S_REQVFVLD    27
+#define V_REQVFVLD(x) ((x) << S_REQVFVLD)
+#define F_REQVFVLD    V_REQVFVLD(1U)
+
+#define S_T5_UPRID    0
+#define M_T5_UPRID    0xffU
+#define V_T5_UPRID(x) ((x) << S_T5_UPRID)
+#define G_T5_UPRID(x) (((x) >> S_T5_UPRID) & M_T5_UPRID)
+
+#define A_UP_UP_SELF_CONTROL 0x14c
+
+#define S_UPSELFRESET    0
+#define V_UPSELFRESET(x) ((x) << S_UPSELFRESET)
+#define F_UPSELFRESET    V_UPSELFRESET(1U)
+
+#define A_UP_MAILBOX_PF0_CTL 0x180
+#define A_UP_MAILBOX_PF1_CTL 0x190
+#define A_UP_MAILBOX_PF2_CTL 0x1a0
+#define A_UP_MAILBOX_PF3_CTL 0x1b0
+#define A_UP_MAILBOX_PF4_CTL 0x1c0
+#define A_UP_MAILBOX_PF5_CTL 0x1d0
+#define A_UP_MAILBOX_PF6_CTL 0x1e0
+#define A_UP_MAILBOX_PF7_CTL 0x1f0
+#define A_UP_TSCH_CHNLN_CLASS_RDY 0x200
+
+#define S_ECO_15444_SGE_DB_BUSY    31
+#define V_ECO_15444_SGE_DB_BUSY(x) ((x) << S_ECO_15444_SGE_DB_BUSY)
+#define F_ECO_15444_SGE_DB_BUSY    V_ECO_15444_SGE_DB_BUSY(1U)
+
+#define S_ECO_15444_PL_INTF_BUSY    30
+#define V_ECO_15444_PL_INTF_BUSY(x) ((x) << S_ECO_15444_PL_INTF_BUSY)
+#define F_ECO_15444_PL_INTF_BUSY    V_ECO_15444_PL_INTF_BUSY(1U)
+
+#define S_TSCHCHNLCRDY    0
+#define M_TSCHCHNLCRDY    0x3fffffffU
+#define V_TSCHCHNLCRDY(x) ((x) << S_TSCHCHNLCRDY)
+#define G_TSCHCHNLCRDY(x) (((x) >> S_TSCHCHNLCRDY) & M_TSCHCHNLCRDY)
+
+#define A_UP_TSCH_CHNLN_CLASS_WATCH_RDY 0x204
+
+#define S_TSCHWRRLIMIT    16
+#define M_TSCHWRRLIMIT    0xffffU
+#define V_TSCHWRRLIMIT(x) ((x) << S_TSCHWRRLIMIT)
+#define G_TSCHWRRLIMIT(x) (((x) >> S_TSCHWRRLIMIT) & M_TSCHWRRLIMIT)
+
+#define S_TSCHCHNLCWRDY    0
+#define M_TSCHCHNLCWRDY    0xffffU
+#define V_TSCHCHNLCWRDY(x) ((x) << S_TSCHCHNLCWRDY)
+#define G_TSCHCHNLCWRDY(x) (((x) >> S_TSCHCHNLCWRDY) & M_TSCHCHNLCWRDY)
+
+#define A_UP_TSCH_CHNLN_CLASS_WATCH_LIST 0x208
+
+#define S_TSCHWRRRELOAD    16
+#define M_TSCHWRRRELOAD    0xffffU
+#define V_TSCHWRRRELOAD(x) ((x) << S_TSCHWRRRELOAD)
+#define G_TSCHWRRRELOAD(x) (((x) >> S_TSCHWRRRELOAD) & M_TSCHWRRRELOAD)
+
+#define S_TSCHCHNLCWATCH    0
+#define M_TSCHCHNLCWATCH    0xffffU
+#define V_TSCHCHNLCWATCH(x) ((x) << S_TSCHCHNLCWATCH)
+#define G_TSCHCHNLCWATCH(x) (((x) >> S_TSCHCHNLCWATCH) & M_TSCHCHNLCWATCH)
+
+#define A_UP_TSCH_CHNLN_CLASS_TAKE 0x20c
+
+#define S_TSCHCHNLCNUM    24
+#define M_TSCHCHNLCNUM    0x1fU
+#define V_TSCHCHNLCNUM(x) ((x) << S_TSCHCHNLCNUM)
+#define G_TSCHCHNLCNUM(x) (((x) >> S_TSCHCHNLCNUM) & M_TSCHCHNLCNUM)
+
+#define S_TSCHCHNLCCNT    0
+#define M_TSCHCHNLCCNT    0xffffffU
+#define V_TSCHCHNLCCNT(x) ((x) << S_TSCHCHNLCCNT)
+#define G_TSCHCHNLCCNT(x) (((x) >> S_TSCHCHNLCCNT) & M_TSCHCHNLCCNT)
+
+#define A_UP_UPLADBGPCCHKDATA_0 0x240
+#define A_UP_UPLADBGPCCHKMASK_0 0x244
+#define A_UP_UPLADBGPCCHKDATA_1 0x250
+#define A_UP_UPLADBGPCCHKMASK_1 0x254
+#define A_UP_UPLADBGPCCHKDATA_2 0x260
+#define A_UP_UPLADBGPCCHKMASK_2 0x264
+#define A_UP_UPLADBGPCCHKDATA_3 0x270
+#define A_UP_UPLADBGPCCHKMASK_3 0x274
+#define A_UP_IBQ_0_SHADOW_RDADDR 0x280
+#define A_UP_IBQ_0_SHADOW_WRADDR 0x284
+#define A_UP_IBQ_0_SHADOW_STATUS 0x288
+#define A_UP_IBQ_0_SHADOW_PKTCNT 0x28c
+#define A_UP_IBQ_1_SHADOW_RDADDR 0x290
+#define A_UP_IBQ_1_SHADOW_WRADDR 0x294
+#define A_UP_IBQ_1_SHADOW_STATUS 0x298
+#define A_UP_IBQ_1_SHADOW_PKTCNT 0x29c
+#define A_UP_IBQ_2_SHADOW_RDADDR 0x2a0
+#define A_UP_IBQ_2_SHADOW_WRADDR 0x2a4
+#define A_UP_IBQ_2_SHADOW_STATUS 0x2a8
+#define A_UP_IBQ_2_SHADOW_PKTCNT 0x2ac
+#define A_UP_IBQ_3_SHADOW_RDADDR 0x2b0
+#define A_UP_IBQ_3_SHADOW_WRADDR 0x2b4
+#define A_UP_IBQ_3_SHADOW_STATUS 0x2b8
+#define A_UP_IBQ_3_SHADOW_PKTCNT 0x2bc
+#define A_UP_IBQ_4_SHADOW_RDADDR 0x2c0
+#define A_UP_IBQ_4_SHADOW_WRADDR 0x2c4
+#define A_UP_IBQ_4_SHADOW_STATUS 0x2c8
+#define A_UP_IBQ_4_SHADOW_PKTCNT 0x2cc
+#define A_UP_IBQ_5_SHADOW_RDADDR 0x2d0
+#define A_UP_IBQ_5_SHADOW_WRADDR 0x2d4
+#define A_UP_IBQ_5_SHADOW_STATUS 0x2d8
+#define A_UP_IBQ_5_SHADOW_PKTCNT 0x2dc
+#define A_UP_OBQ_0_SHADOW_RDADDR 0x2e0
+#define A_UP_OBQ_0_SHADOW_WRADDR 0x2e4
+#define A_UP_OBQ_0_SHADOW_STATUS 0x2e8
+#define A_UP_OBQ_0_SHADOW_PKTCNT 0x2ec
+#define A_UP_OBQ_1_SHADOW_RDADDR 0x2f0
+#define A_UP_OBQ_1_SHADOW_WRADDR 0x2f4
+#define A_UP_OBQ_1_SHADOW_STATUS 0x2f8
+#define A_UP_OBQ_1_SHADOW_PKTCNT 0x2fc
+#define A_UP_OBQ_2_SHADOW_RDADDR 0x300
+#define A_UP_OBQ_2_SHADOW_WRADDR 0x304
+#define A_UP_OBQ_2_SHADOW_STATUS 0x308
+#define A_UP_OBQ_2_SHADOW_PKTCNT 0x30c
+#define A_UP_OBQ_3_SHADOW_RDADDR 0x310
+#define A_UP_OBQ_3_SHADOW_WRADDR 0x314
+#define A_UP_OBQ_3_SHADOW_STATUS 0x318
+#define A_UP_OBQ_3_SHADOW_PKTCNT 0x31c
+#define A_UP_OBQ_4_SHADOW_RDADDR 0x320
+#define A_UP_OBQ_4_SHADOW_WRADDR 0x324
+#define A_UP_OBQ_4_SHADOW_STATUS 0x328
+#define A_UP_OBQ_4_SHADOW_PKTCNT 0x32c
+#define A_UP_OBQ_5_SHADOW_RDADDR 0x330
+#define A_UP_OBQ_5_SHADOW_WRADDR 0x334
+#define A_UP_OBQ_5_SHADOW_STATUS 0x338
+#define A_UP_OBQ_5_SHADOW_PKTCNT 0x33c
+#define A_UP_OBQ_6_SHADOW_RDADDR 0x340
+#define A_UP_OBQ_6_SHADOW_WRADDR 0x344
+#define A_UP_OBQ_6_SHADOW_STATUS 0x348
+#define A_UP_OBQ_6_SHADOW_PKTCNT 0x34c
+#define A_UP_OBQ_7_SHADOW_RDADDR 0x350
+#define A_UP_OBQ_7_SHADOW_WRADDR 0x354
+#define A_UP_OBQ_7_SHADOW_STATUS 0x358
+#define A_UP_OBQ_7_SHADOW_PKTCNT 0x35c
+#define A_UP_IBQ_0_SHADOW_CONFIG 0x360
+#define A_UP_IBQ_0_SHADOW_REALADDR 0x364
+#define A_UP_IBQ_1_SHADOW_CONFIG 0x368
+#define A_UP_IBQ_1_SHADOW_REALADDR 0x36c
+#define A_UP_IBQ_2_SHADOW_CONFIG 0x370
+#define A_UP_IBQ_2_SHADOW_REALADDR 0x374
+#define A_UP_IBQ_3_SHADOW_CONFIG 0x378
+#define A_UP_IBQ_3_SHADOW_REALADDR 0x37c
+#define A_UP_IBQ_4_SHADOW_CONFIG 0x380
+#define A_UP_IBQ_4_SHADOW_REALADDR 0x384
+#define A_UP_IBQ_5_SHADOW_CONFIG 0x388
+#define A_UP_IBQ_5_SHADOW_REALADDR 0x38c
+#define A_UP_OBQ_0_SHADOW_CONFIG 0x390
+#define A_UP_OBQ_0_SHADOW_REALADDR 0x394
+#define A_UP_OBQ_1_SHADOW_CONFIG 0x398
+#define A_UP_OBQ_1_SHADOW_REALADDR 0x39c
+#define A_UP_OBQ_2_SHADOW_CONFIG 0x3a0
+#define A_UP_OBQ_2_SHADOW_REALADDR 0x3a4
+#define A_UP_OBQ_3_SHADOW_CONFIG 0x3a8
+#define A_UP_OBQ_3_SHADOW_REALADDR 0x3ac
+#define A_UP_OBQ_4_SHADOW_CONFIG 0x3b0
+#define A_UP_OBQ_4_SHADOW_REALADDR 0x3b4
+#define A_UP_OBQ_5_SHADOW_CONFIG 0x3b8
+#define A_UP_OBQ_5_SHADOW_REALADDR 0x3bc
+#define A_UP_OBQ_6_SHADOW_CONFIG 0x3c0
+#define A_UP_OBQ_6_SHADOW_REALADDR 0x3c4
+#define A_UP_OBQ_7_SHADOW_CONFIG 0x3c8
+#define A_UP_OBQ_7_SHADOW_REALADDR 0x3cc
+
+/* registers for module CIM_CTL */
+#define CIM_CTL_BASE_ADDR 0x0
+
+#define A_CIM_CTL_CONFIG 0x0
+
+#define S_AUTOPREFLOC    17
+#define M_AUTOPREFLOC    0x1fU
+#define V_AUTOPREFLOC(x) ((x) << S_AUTOPREFLOC)
+#define G_AUTOPREFLOC(x) (((x) >> S_AUTOPREFLOC) & M_AUTOPREFLOC)
+
+#define S_AUTOPREFEN    16
+#define V_AUTOPREFEN(x) ((x) << S_AUTOPREFEN)
+#define F_AUTOPREFEN    V_AUTOPREFEN(1U)
+
+#define S_DISMATIMEOUT    15
+#define V_DISMATIMEOUT(x) ((x) << S_DISMATIMEOUT)
+#define F_DISMATIMEOUT    V_DISMATIMEOUT(1U)
+
+#define S_PIFMULTICMD    8
+#define V_PIFMULTICMD(x) ((x) << S_PIFMULTICMD)
+#define F_PIFMULTICMD    V_PIFMULTICMD(1U)
+
+#define S_UPSELFRESETTOUT    7
+#define V_UPSELFRESETTOUT(x) ((x) << S_UPSELFRESETTOUT)
+#define F_UPSELFRESETTOUT    V_UPSELFRESETTOUT(1U)
+
+#define S_PLSWAPDISWR    6
+#define V_PLSWAPDISWR(x) ((x) << S_PLSWAPDISWR)
+#define F_PLSWAPDISWR    V_PLSWAPDISWR(1U)
+
+#define S_PLSWAPDISRD    5
+#define V_PLSWAPDISRD(x) ((x) << S_PLSWAPDISRD)
+#define F_PLSWAPDISRD    V_PLSWAPDISRD(1U)
+
+#define S_PREFEN    0
+#define V_PREFEN(x) ((x) << S_PREFEN)
+#define F_PREFEN    V_PREFEN(1U)
+
+#define A_CIM_CTL_PREFADDR 0x4
+#define A_CIM_CTL_ALLOCADDR 0x8
+#define A_CIM_CTL_INVLDTADDR 0xc
+#define A_CIM_CTL_STATIC_PREFADDR0 0x10
+#define A_CIM_CTL_STATIC_PREFADDR1 0x14
+#define A_CIM_CTL_STATIC_PREFADDR2 0x18
+#define A_CIM_CTL_STATIC_PREFADDR3 0x1c
+#define A_CIM_CTL_STATIC_PREFADDR4 0x20
+#define A_CIM_CTL_STATIC_PREFADDR5 0x24
+#define A_CIM_CTL_STATIC_PREFADDR6 0x28
+#define A_CIM_CTL_STATIC_PREFADDR7 0x2c
+#define A_CIM_CTL_STATIC_PREFADDR8 0x30
+#define A_CIM_CTL_STATIC_PREFADDR9 0x34
+#define A_CIM_CTL_STATIC_PREFADDR10 0x38
+#define A_CIM_CTL_STATIC_PREFADDR11 0x3c
+#define A_CIM_CTL_STATIC_PREFADDR12 0x40
+#define A_CIM_CTL_STATIC_PREFADDR13 0x44
+#define A_CIM_CTL_STATIC_PREFADDR14 0x48
+#define A_CIM_CTL_STATIC_PREFADDR15 0x4c
+#define A_CIM_CTL_STATIC_ALLOCADDR0 0x50
+#define A_CIM_CTL_STATIC_ALLOCADDR1 0x54
+#define A_CIM_CTL_STATIC_ALLOCADDR2 0x58
+#define A_CIM_CTL_STATIC_ALLOCADDR3 0x5c
+#define A_CIM_CTL_STATIC_ALLOCADDR4 0x60
+#define A_CIM_CTL_STATIC_ALLOCADDR5 0x64
+#define A_CIM_CTL_STATIC_ALLOCADDR6 0x68
+#define A_CIM_CTL_STATIC_ALLOCADDR7 0x6c
+#define A_CIM_CTL_STATIC_ALLOCADDR8 0x70
+#define A_CIM_CTL_STATIC_ALLOCADDR9 0x74
+#define A_CIM_CTL_STATIC_ALLOCADDR10 0x78
+#define A_CIM_CTL_STATIC_ALLOCADDR11 0x7c
+#define A_CIM_CTL_STATIC_ALLOCADDR12 0x80
+#define A_CIM_CTL_STATIC_ALLOCADDR13 0x84
+#define A_CIM_CTL_STATIC_ALLOCADDR14 0x88
+#define A_CIM_CTL_STATIC_ALLOCADDR15 0x8c
+#define A_CIM_CTL_FIFO_CNT 0x90
+
+#define S_CTLFIFOCNT    0
+#define M_CTLFIFOCNT    0xfU
+#define V_CTLFIFOCNT(x) ((x) << S_CTLFIFOCNT)
+#define G_CTLFIFOCNT(x) (((x) >> S_CTLFIFOCNT) & M_CTLFIFOCNT)
+
+#define A_CIM_CTL_GLB_TIMER 0x94
+#define A_CIM_CTL_TIMER0 0x98
+#define A_CIM_CTL_TIMER1 0x9c
+#define A_CIM_CTL_GEN0 0xa0
+#define A_CIM_CTL_GEN1 0xa4
+#define A_CIM_CTL_GEN2 0xa8
+#define A_CIM_CTL_GEN3 0xac
+#define A_CIM_CTL_GLB_TIMER_TICK 0xb0
+#define A_CIM_CTL_GEN_TIMER0_CTL 0xb4
+
+#define S_GENTIMERRUN    7
+#define V_GENTIMERRUN(x) ((x) << S_GENTIMERRUN)
+#define F_GENTIMERRUN    V_GENTIMERRUN(1U)
+
+#define S_GENTIMERTRIG    6
+#define V_GENTIMERTRIG(x) ((x) << S_GENTIMERTRIG)
+#define F_GENTIMERTRIG    V_GENTIMERTRIG(1U)
+
+#define S_GENTIMERACT    4
+#define M_GENTIMERACT    0x3U
+#define V_GENTIMERACT(x) ((x) << S_GENTIMERACT)
+#define G_GENTIMERACT(x) (((x) >> S_GENTIMERACT) & M_GENTIMERACT)
+
+#define S_GENTIMERCFG    2
+#define M_GENTIMERCFG    0x3U
+#define V_GENTIMERCFG(x) ((x) << S_GENTIMERCFG)
+#define G_GENTIMERCFG(x) (((x) >> S_GENTIMERCFG) & M_GENTIMERCFG)
+
+#define S_GENTIMERSTOP    1
+#define V_GENTIMERSTOP(x) ((x) << S_GENTIMERSTOP)
+#define F_GENTIMERSTOP    V_GENTIMERSTOP(1U)
+
+#define S_GENTIMERSTRT    0
+#define V_GENTIMERSTRT(x) ((x) << S_GENTIMERSTRT)
+#define F_GENTIMERSTRT    V_GENTIMERSTRT(1U)
+
+#define A_CIM_CTL_GEN_TIMER0 0xb8
+#define A_CIM_CTL_GEN_TIMER1_CTL 0xbc
+#define A_CIM_CTL_GEN_TIMER1 0xc0
+#define A_CIM_CTL_GEN_TIMER2_CTL 0xc4
+#define A_CIM_CTL_GEN_TIMER2 0xc8
+#define A_CIM_CTL_GEN_TIMER3_CTL 0xcc
+#define A_CIM_CTL_GEN_TIMER3 0xd0
+#define A_CIM_CTL_MAILBOX_VF_STATUS 0xe0
+#define A_CIM_CTL_MAILBOX_VFN_CTL 0x100
+#define A_CIM_CTL_TSCH_CHNLN_CTL 0x900
+
+#define S_TSCHNLEN    31
+#define V_TSCHNLEN(x) ((x) << S_TSCHNLEN)
+#define F_TSCHNLEN    V_TSCHNLEN(1U)
+
+#define S_TSCHNRESET    30
+#define V_TSCHNRESET(x) ((x) << S_TSCHNRESET)
+#define F_TSCHNRESET    V_TSCHNRESET(1U)
+
+#define A_CIM_CTL_TSCH_CHNLN_TICK 0x904
+
+#define S_TSCHNLTICK    0
+#define M_TSCHNLTICK    0xffffU
+#define V_TSCHNLTICK(x) ((x) << S_TSCHNLTICK)
+#define G_TSCHNLTICK(x) (((x) >> S_TSCHNLTICK) & M_TSCHNLTICK)
+
+#define A_CIM_CTL_TSCH_CHNLN_CLASS_ENABLE_A 0x908
+
+#define S_TSC15WRREN    31
+#define V_TSC15WRREN(x) ((x) << S_TSC15WRREN)
+#define F_TSC15WRREN    V_TSC15WRREN(1U)
+
+#define S_TSC15RATEEN    30
+#define V_TSC15RATEEN(x) ((x) << S_TSC15RATEEN)
+#define F_TSC15RATEEN    V_TSC15RATEEN(1U)
+
+#define S_TSC14WRREN    29
+#define V_TSC14WRREN(x) ((x) << S_TSC14WRREN)
+#define F_TSC14WRREN    V_TSC14WRREN(1U)
+
+#define S_TSC14RATEEN    28
+#define V_TSC14RATEEN(x) ((x) << S_TSC14RATEEN)
+#define F_TSC14RATEEN    V_TSC14RATEEN(1U)
+
+#define S_TSC13WRREN    27
+#define V_TSC13WRREN(x) ((x) << S_TSC13WRREN)
+#define F_TSC13WRREN    V_TSC13WRREN(1U)
+
+#define S_TSC13RATEEN    26
+#define V_TSC13RATEEN(x) ((x) << S_TSC13RATEEN)
+#define F_TSC13RATEEN    V_TSC13RATEEN(1U)
+
+#define S_TSC12WRREN    25
+#define V_TSC12WRREN(x) ((x) << S_TSC12WRREN)
+#define F_TSC12WRREN    V_TSC12WRREN(1U)
+
+#define S_TSC12RATEEN    24
+#define V_TSC12RATEEN(x) ((x) << S_TSC12RATEEN)
+#define F_TSC12RATEEN    V_TSC12RATEEN(1U)
+
+#define S_TSC11WRREN    23
+#define V_TSC11WRREN(x) ((x) << S_TSC11WRREN)
+#define F_TSC11WRREN    V_TSC11WRREN(1U)
+
+#define S_TSC11RATEEN    22
+#define V_TSC11RATEEN(x) ((x) << S_TSC11RATEEN)
+#define F_TSC11RATEEN    V_TSC11RATEEN(1U)
+
+#define S_TSC10WRREN    21
+#define V_TSC10WRREN(x) ((x) << S_TSC10WRREN)
+#define F_TSC10WRREN    V_TSC10WRREN(1U)
+
+#define S_TSC10RATEEN    20
+#define V_TSC10RATEEN(x) ((x) << S_TSC10RATEEN)
+#define F_TSC10RATEEN    V_TSC10RATEEN(1U)
+
+#define S_TSC9WRREN    19
+#define V_TSC9WRREN(x) ((x) << S_TSC9WRREN)
+#define F_TSC9WRREN    V_TSC9WRREN(1U)
+
+#define S_TSC9RATEEN    18
+#define V_TSC9RATEEN(x) ((x) << S_TSC9RATEEN)
+#define F_TSC9RATEEN    V_TSC9RATEEN(1U)
+
+#define S_TSC8WRREN    17
+#define V_TSC8WRREN(x) ((x) << S_TSC8WRREN)
+#define F_TSC8WRREN    V_TSC8WRREN(1U)
+
+#define S_TSC8RATEEN    16
+#define V_TSC8RATEEN(x) ((x) << S_TSC8RATEEN)
+#define F_TSC8RATEEN    V_TSC8RATEEN(1U)
+
+#define S_TSC7WRREN    15
+#define V_TSC7WRREN(x) ((x) << S_TSC7WRREN)
+#define F_TSC7WRREN    V_TSC7WRREN(1U)
+
+#define S_TSC7RATEEN    14
+#define V_TSC7RATEEN(x) ((x) << S_TSC7RATEEN)
+#define F_TSC7RATEEN    V_TSC7RATEEN(1U)
+
+#define S_TSC6WRREN    13
+#define V_TSC6WRREN(x) ((x) << S_TSC6WRREN)
+#define F_TSC6WRREN    V_TSC6WRREN(1U)
+
+#define S_TSC6RATEEN    12
+#define V_TSC6RATEEN(x) ((x) << S_TSC6RATEEN)
+#define F_TSC6RATEEN    V_TSC6RATEEN(1U)
+
+#define S_TSC5WRREN    11
+#define V_TSC5WRREN(x) ((x) << S_TSC5WRREN)
+#define F_TSC5WRREN    V_TSC5WRREN(1U)
+
+#define S_TSC5RATEEN    10
+#define V_TSC5RATEEN(x) ((x) << S_TSC5RATEEN)
+#define F_TSC5RATEEN    V_TSC5RATEEN(1U)
+
+#define S_TSC4WRREN    9
+#define V_TSC4WRREN(x) ((x) << S_TSC4WRREN)
+#define F_TSC4WRREN    V_TSC4WRREN(1U)
+
+#define S_TSC4RATEEN    8
+#define V_TSC4RATEEN(x) ((x) << S_TSC4RATEEN)
+#define F_TSC4RATEEN    V_TSC4RATEEN(1U)
+
+#define S_TSC3WRREN    7
+#define V_TSC3WRREN(x) ((x) << S_TSC3WRREN)
+#define F_TSC3WRREN    V_TSC3WRREN(1U)
+
+#define S_TSC3RATEEN    6
+#define V_TSC3RATEEN(x) ((x) << S_TSC3RATEEN)
+#define F_TSC3RATEEN    V_TSC3RATEEN(1U)
+
+#define S_TSC2WRREN    5
+#define V_TSC2WRREN(x) ((x) << S_TSC2WRREN)
+#define F_TSC2WRREN    V_TSC2WRREN(1U)
+
+#define S_TSC2RATEEN    4
+#define V_TSC2RATEEN(x) ((x) << S_TSC2RATEEN)
+#define F_TSC2RATEEN    V_TSC2RATEEN(1U)
+
+#define S_TSC1WRREN    3
+#define V_TSC1WRREN(x) ((x) << S_TSC1WRREN)
+#define F_TSC1WRREN    V_TSC1WRREN(1U)
+
+#define S_TSC1RATEEN    2
+#define V_TSC1RATEEN(x) ((x) << S_TSC1RATEEN)
+#define F_TSC1RATEEN    V_TSC1RATEEN(1U)
+
+#define S_TSC0WRREN    1
+#define V_TSC0WRREN(x) ((x) << S_TSC0WRREN)
+#define F_TSC0WRREN    V_TSC0WRREN(1U)
+
+#define S_TSC0RATEEN    0
+#define V_TSC0RATEEN(x) ((x) << S_TSC0RATEEN)
+#define F_TSC0RATEEN    V_TSC0RATEEN(1U)
+
+#define A_CIM_CTL_TSCH_MIN_MAX_EN 0x90c
+
+#define S_MIN_MAX_EN    0
+#define V_MIN_MAX_EN(x) ((x) << S_MIN_MAX_EN)
+#define F_MIN_MAX_EN    V_MIN_MAX_EN(1U)
+
+#define A_CIM_CTL_TSCH_CHNLN_RATE_LIMITER 0x910
+
+#define S_TSCHNLRATENEG    31
+#define V_TSCHNLRATENEG(x) ((x) << S_TSCHNLRATENEG)
+#define F_TSCHNLRATENEG    V_TSCHNLRATENEG(1U)
+
+#define S_TSCHNLRATEL    0
+#define M_TSCHNLRATEL    0x7fffffffU
+#define V_TSCHNLRATEL(x) ((x) << S_TSCHNLRATEL)
+#define G_TSCHNLRATEL(x) (((x) >> S_TSCHNLRATEL) & M_TSCHNLRATEL)
+
+#define A_CIM_CTL_TSCH_CHNLN_RATE_PROPERTIES 0x914
+
+#define S_TSCHNLRMAX    16
+#define M_TSCHNLRMAX    0xffffU
+#define V_TSCHNLRMAX(x) ((x) << S_TSCHNLRMAX)
+#define G_TSCHNLRMAX(x) (((x) >> S_TSCHNLRMAX) & M_TSCHNLRMAX)
+
+#define S_TSCHNLRINCR    0
+#define M_TSCHNLRINCR    0xffffU
+#define V_TSCHNLRINCR(x) ((x) << S_TSCHNLRINCR)
+#define G_TSCHNLRINCR(x) (((x) >> S_TSCHNLRINCR) & M_TSCHNLRINCR)
+
+#define A_CIM_CTL_TSCH_CHNLN_WRR 0x918
+#define A_CIM_CTL_TSCH_CHNLN_WEIGHT 0x91c
+
+#define S_TSCHNLWEIGHT    0
+#define M_TSCHNLWEIGHT    0x3fffffU
+#define V_TSCHNLWEIGHT(x) ((x) << S_TSCHNLWEIGHT)
+#define G_TSCHNLWEIGHT(x) (((x) >> S_TSCHNLWEIGHT) & M_TSCHNLWEIGHT)
+
+#define A_CIM_CTL_TSCH_CHNLN_CLASSM_RATE_LIMITER 0x920
+
+#define S_TSCCLRATENEG    31
+#define V_TSCCLRATENEG(x) ((x) << S_TSCCLRATENEG)
+#define F_TSCCLRATENEG    V_TSCCLRATENEG(1U)
+
+#define S_TSCCLRATEL    0
+#define M_TSCCLRATEL    0xffffffU
+#define V_TSCCLRATEL(x) ((x) << S_TSCCLRATEL)
+#define G_TSCCLRATEL(x) (((x) >> S_TSCCLRATEL) & M_TSCCLRATEL)
+
+#define A_CIM_CTL_TSCH_CHNLN_CLASSM_RATE_PROPERTIES 0x924
+
+#define S_TSCCLRMAX    16
+#define M_TSCCLRMAX    0xffffU
+#define V_TSCCLRMAX(x) ((x) << S_TSCCLRMAX)
+#define G_TSCCLRMAX(x) (((x) >> S_TSCCLRMAX) & M_TSCCLRMAX)
+
+#define S_TSCCLRINCR    0
+#define M_TSCCLRINCR    0xffffU
+#define V_TSCCLRINCR(x) ((x) << S_TSCCLRINCR)
+#define G_TSCCLRINCR(x) (((x) >> S_TSCCLRINCR) & M_TSCCLRINCR)
+
+#define A_CIM_CTL_TSCH_CHNLN_CLASSM_WRR 0x928
+
+#define S_TSCCLWRRNEG    31
+#define V_TSCCLWRRNEG(x) ((x) << S_TSCCLWRRNEG)
+#define F_TSCCLWRRNEG    V_TSCCLWRRNEG(1U)
+
+#define S_TSCCLWRR    0
+#define M_TSCCLWRR    0x3ffffffU
+#define V_TSCCLWRR(x) ((x) << S_TSCCLWRR)
+#define G_TSCCLWRR(x) (((x) >> S_TSCCLWRR) & M_TSCCLWRR)
+
+#define A_CIM_CTL_TSCH_CHNLN_CLASSM_WEIGHT 0x92c
+
+#define S_TSCCLWEIGHT    0
+#define M_TSCCLWEIGHT    0xffffU
+#define V_TSCCLWEIGHT(x) ((x) << S_TSCCLWEIGHT)
+#define G_TSCCLWEIGHT(x) (((x) >> S_TSCCLWEIGHT) & M_TSCCLWEIGHT)
+
+#define A_CIM_CTL_MAILBOX_PF0_CTL 0xd84
+#define A_CIM_CTL_MAILBOX_PF1_CTL 0xd88
+#define A_CIM_CTL_MAILBOX_PF2_CTL 0xd8c
+#define A_CIM_CTL_MAILBOX_PF3_CTL 0xd90
+#define A_CIM_CTL_MAILBOX_PF4_CTL 0xd94
+#define A_CIM_CTL_MAILBOX_PF5_CTL 0xd98
+#define A_CIM_CTL_MAILBOX_PF6_CTL 0xd9c
+#define A_CIM_CTL_MAILBOX_PF7_CTL 0xda0
+#define A_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xda4
+
+#define S_PF7_OWNER_PL    15
+#define V_PF7_OWNER_PL(x) ((x) << S_PF7_OWNER_PL)
+#define F_PF7_OWNER_PL    V_PF7_OWNER_PL(1U)
+
+#define S_PF6_OWNER_PL    14
+#define V_PF6_OWNER_PL(x) ((x) << S_PF6_OWNER_PL)
+#define F_PF6_OWNER_PL    V_PF6_OWNER_PL(1U)
+
+#define S_PF5_OWNER_PL    13
+#define V_PF5_OWNER_PL(x) ((x) << S_PF5_OWNER_PL)
+#define F_PF5_OWNER_PL    V_PF5_OWNER_PL(1U)
+
+#define S_PF4_OWNER_PL    12
+#define V_PF4_OWNER_PL(x) ((x) << S_PF4_OWNER_PL)
+#define F_PF4_OWNER_PL    V_PF4_OWNER_PL(1U)
+
+#define S_PF3_OWNER_PL    11
+#define V_PF3_OWNER_PL(x) ((x) << S_PF3_OWNER_PL)
+#define F_PF3_OWNER_PL    V_PF3_OWNER_PL(1U)
+
+#define S_PF2_OWNER_PL    10
+#define V_PF2_OWNER_PL(x) ((x) << S_PF2_OWNER_PL)
+#define F_PF2_OWNER_PL    V_PF2_OWNER_PL(1U)
+
+#define S_PF1_OWNER_PL    9
+#define V_PF1_OWNER_PL(x) ((x) << S_PF1_OWNER_PL)
+#define F_PF1_OWNER_PL    V_PF1_OWNER_PL(1U)
+
+#define S_PF0_OWNER_PL    8
+#define V_PF0_OWNER_PL(x) ((x) << S_PF0_OWNER_PL)
+#define F_PF0_OWNER_PL    V_PF0_OWNER_PL(1U)
+
+#define S_PF7_OWNER_UP    7
+#define V_PF7_OWNER_UP(x) ((x) << S_PF7_OWNER_UP)
+#define F_PF7_OWNER_UP    V_PF7_OWNER_UP(1U)
+
+#define S_PF6_OWNER_UP    6
+#define V_PF6_OWNER_UP(x) ((x) << S_PF6_OWNER_UP)
+#define F_PF6_OWNER_UP    V_PF6_OWNER_UP(1U)
+
+#define S_PF5_OWNER_UP    5
+#define V_PF5_OWNER_UP(x) ((x) << S_PF5_OWNER_UP)
+#define F_PF5_OWNER_UP    V_PF5_OWNER_UP(1U)
+
+#define S_PF4_OWNER_UP    4
+#define V_PF4_OWNER_UP(x) ((x) << S_PF4_OWNER_UP)
+#define F_PF4_OWNER_UP    V_PF4_OWNER_UP(1U)
+
+#define S_PF3_OWNER_UP    3
+#define V_PF3_OWNER_UP(x) ((x) << S_PF3_OWNER_UP)
+#define F_PF3_OWNER_UP    V_PF3_OWNER_UP(1U)
+
+#define S_PF2_OWNER_UP    2
+#define V_PF2_OWNER_UP(x) ((x) << S_PF2_OWNER_UP)
+#define F_PF2_OWNER_UP    V_PF2_OWNER_UP(1U)
+
+#define S_PF1_OWNER_UP    1
+#define V_PF1_OWNER_UP(x) ((x) << S_PF1_OWNER_UP)
+#define F_PF1_OWNER_UP    V_PF1_OWNER_UP(1U)
+
+#define S_PF0_OWNER_UP    0
+#define V_PF0_OWNER_UP(x) ((x) << S_PF0_OWNER_UP)
+#define F_PF0_OWNER_UP    V_PF0_OWNER_UP(1U)
+
+#define A_CIM_CTL_PIO_MST_CONFIG 0xda8
+
+#define S_T5_CTLRID    0
+#define M_T5_CTLRID    0xffU
+#define V_T5_CTLRID(x) ((x) << S_T5_CTLRID)
+#define G_T5_CTLRID(x) (((x) >> S_T5_CTLRID) & M_T5_CTLRID)
+
+/* registers for module MAC */
+#define MAC_BASE_ADDR 0x0
+
+#define A_MAC_PORT_CFG 0x800
+
+#define S_MAC_CLK_SEL    29
+#define M_MAC_CLK_SEL    0x7U
+#define V_MAC_CLK_SEL(x) ((x) << S_MAC_CLK_SEL)
+#define G_MAC_CLK_SEL(x) (((x) >> S_MAC_CLK_SEL) & M_MAC_CLK_SEL)
+
+#define S_SMUXTXSEL    9
+#define V_SMUXTXSEL(x) ((x) << S_SMUXTXSEL)
+#define F_SMUXTXSEL    V_SMUXTXSEL(1U)
+
+#define S_SMUXRXSEL    8
+#define V_SMUXRXSEL(x) ((x) << S_SMUXRXSEL)
+#define F_SMUXRXSEL    V_SMUXRXSEL(1U)
+
+#define S_PORTSPEED    4
+#define M_PORTSPEED    0x3U
+#define V_PORTSPEED(x) ((x) << S_PORTSPEED)
+#define G_PORTSPEED(x) (((x) >> S_PORTSPEED) & M_PORTSPEED)
+
+#define A_MAC_PORT_RESET_CTRL 0x804
+
+#define S_TWGDSK_HSSC16B    31
+#define V_TWGDSK_HSSC16B(x) ((x) << S_TWGDSK_HSSC16B)
+#define F_TWGDSK_HSSC16B    V_TWGDSK_HSSC16B(1U)
+
+#define S_EEE_RESET    30
+#define V_EEE_RESET(x) ((x) << S_EEE_RESET)
+#define F_EEE_RESET    V_EEE_RESET(1U)
+
+#define S_PTP_TIMER    29
+#define V_PTP_TIMER(x) ((x) << S_PTP_TIMER)
+#define F_PTP_TIMER    V_PTP_TIMER(1U)
+
+#define S_MTIPREFRESET    28
+#define V_MTIPREFRESET(x) ((x) << S_MTIPREFRESET)
+#define F_MTIPREFRESET    V_MTIPREFRESET(1U)
+
+#define S_MTIPTXFFRESET    27
+#define V_MTIPTXFFRESET(x) ((x) << S_MTIPTXFFRESET)
+#define F_MTIPTXFFRESET    V_MTIPTXFFRESET(1U)
+
+#define S_MTIPRXFFRESET    26
+#define V_MTIPRXFFRESET(x) ((x) << S_MTIPRXFFRESET)
+#define F_MTIPRXFFRESET    V_MTIPRXFFRESET(1U)
+
+#define S_MTIPREGRESET    25
+#define V_MTIPREGRESET(x) ((x) << S_MTIPREGRESET)
+#define F_MTIPREGRESET    V_MTIPREGRESET(1U)
+
+#define S_AEC3RESET    23
+#define V_AEC3RESET(x) ((x) << S_AEC3RESET)
+#define F_AEC3RESET    V_AEC3RESET(1U)
+
+#define S_AEC2RESET    22
+#define V_AEC2RESET(x) ((x) << S_AEC2RESET)
+#define F_AEC2RESET    V_AEC2RESET(1U)
+
+#define S_AEC1RESET    21
+#define V_AEC1RESET(x) ((x) << S_AEC1RESET)
+#define F_AEC1RESET    V_AEC1RESET(1U)
+
+#define S_AEC0RESET    20
+#define V_AEC0RESET(x) ((x) << S_AEC0RESET)
+#define F_AEC0RESET    V_AEC0RESET(1U)
+
+#define S_AET3RESET    19
+#define V_AET3RESET(x) ((x) << S_AET3RESET)
+#define F_AET3RESET    V_AET3RESET(1U)
+
+#define S_AET2RESET    18
+#define V_AET2RESET(x) ((x) << S_AET2RESET)
+#define F_AET2RESET    V_AET2RESET(1U)
+
+#define S_AET1RESET    17
+#define V_AET1RESET(x) ((x) << S_AET1RESET)
+#define F_AET1RESET    V_AET1RESET(1U)
+
+#define S_AET0RESET    16
+#define V_AET0RESET(x) ((x) << S_AET0RESET)
+#define F_AET0RESET    V_AET0RESET(1U)
+
+#define S_TXIF_RESET    12
+#define V_TXIF_RESET(x) ((x) << S_TXIF_RESET)
+#define F_TXIF_RESET    V_TXIF_RESET(1U)
+
+#define S_RXIF_RESET    11
+#define V_RXIF_RESET(x) ((x) << S_RXIF_RESET)
+#define F_RXIF_RESET    V_RXIF_RESET(1U)
+
+#define S_MTIPSD3TXRST    9
+#define V_MTIPSD3TXRST(x) ((x) << S_MTIPSD3TXRST)
+#define F_MTIPSD3TXRST    V_MTIPSD3TXRST(1U)
+
+#define S_MTIPSD2TXRST    8
+#define V_MTIPSD2TXRST(x) ((x) << S_MTIPSD2TXRST)
+#define F_MTIPSD2TXRST    V_MTIPSD2TXRST(1U)
+
+#define S_MTIPSD1TXRST    7
+#define V_MTIPSD1TXRST(x) ((x) << S_MTIPSD1TXRST)
+#define F_MTIPSD1TXRST    V_MTIPSD1TXRST(1U)
+
+#define S_MTIPSD0TXRST    6
+#define V_MTIPSD0TXRST(x) ((x) << S_MTIPSD0TXRST)
+#define F_MTIPSD0TXRST    V_MTIPSD0TXRST(1U)
+
+#define S_MTIPSD3RXRST    5
+#define V_MTIPSD3RXRST(x) ((x) << S_MTIPSD3RXRST)
+#define F_MTIPSD3RXRST    V_MTIPSD3RXRST(1U)
+
+#define S_MTIPSD2RXRST    4
+#define V_MTIPSD2RXRST(x) ((x) << S_MTIPSD2RXRST)
+#define F_MTIPSD2RXRST    V_MTIPSD2RXRST(1U)
+
+#define S_MTIPSD1RXRST    3
+#define V_MTIPSD1RXRST(x) ((x) << S_MTIPSD1RXRST)
+#define F_MTIPSD1RXRST    V_MTIPSD1RXRST(1U)
+
+#define S_MTIPSD0RXRST    1
+#define V_MTIPSD0RXRST(x) ((x) << S_MTIPSD0RXRST)
+#define F_MTIPSD0RXRST    V_MTIPSD0RXRST(1U)
+
+#define A_MAC_PORT_LED_CFG 0x808
+#define A_MAC_PORT_LED_COUNTHI 0x80c
+#define A_MAC_PORT_LED_COUNTLO 0x810
+#define A_MAC_PORT_CFG3 0x814
+
+#define S_FCSDISCTRL    25
+#define V_FCSDISCTRL(x) ((x) << S_FCSDISCTRL)
+#define F_FCSDISCTRL    V_FCSDISCTRL(1U)
+
+#define S_SIGDETCTRL    24
+#define V_SIGDETCTRL(x) ((x) << S_SIGDETCTRL)
+#define F_SIGDETCTRL    V_SIGDETCTRL(1U)
+
+#define S_TX_LANE    23
+#define V_TX_LANE(x) ((x) << S_TX_LANE)
+#define F_TX_LANE    V_TX_LANE(1U)
+
+#define S_RX_LANE    22
+#define V_RX_LANE(x) ((x) << S_RX_LANE)
+#define F_RX_LANE    V_RX_LANE(1U)
+
+#define S_SE_CLR    21
+#define V_SE_CLR(x) ((x) << S_SE_CLR)
+#define F_SE_CLR    V_SE_CLR(1U)
+
+#define S_AN_ENA    17
+#define M_AN_ENA    0xfU
+#define V_AN_ENA(x) ((x) << S_AN_ENA)
+#define G_AN_ENA(x) (((x) >> S_AN_ENA) & M_AN_ENA)
+
+#define S_SD_RX_CLK_ENA    13
+#define M_SD_RX_CLK_ENA    0xfU
+#define V_SD_RX_CLK_ENA(x) ((x) << S_SD_RX_CLK_ENA)
+#define G_SD_RX_CLK_ENA(x) (((x) >> S_SD_RX_CLK_ENA) & M_SD_RX_CLK_ENA)
+
+#define S_SD_TX_CLK_ENA    9
+#define M_SD_TX_CLK_ENA    0xfU
+#define V_SD_TX_CLK_ENA(x) ((x) << S_SD_TX_CLK_ENA)
+#define G_SD_TX_CLK_ENA(x) (((x) >> S_SD_TX_CLK_ENA) & M_SD_TX_CLK_ENA)
+
+#define S_SGMIISEL    8
+#define V_SGMIISEL(x) ((x) << S_SGMIISEL)
+#define F_SGMIISEL    V_SGMIISEL(1U)
+
+#define S_HSSPLLSEL    4
+#define M_HSSPLLSEL    0xfU
+#define V_HSSPLLSEL(x) ((x) << S_HSSPLLSEL)
+#define G_HSSPLLSEL(x) (((x) >> S_HSSPLLSEL) & M_HSSPLLSEL)
+
+#define S_HSSC16C20SEL    0
+#define M_HSSC16C20SEL    0xfU
+#define V_HSSC16C20SEL(x) ((x) << S_HSSC16C20SEL)
+#define G_HSSC16C20SEL(x) (((x) >> S_HSSC16C20SEL) & M_HSSC16C20SEL)
+
+#define A_MAC_PORT_CFG2 0x818
+
+#define S_T5_AEC_PMA_TX_READY    4
+#define M_T5_AEC_PMA_TX_READY    0xfU
+#define V_T5_AEC_PMA_TX_READY(x) ((x) << S_T5_AEC_PMA_TX_READY)
+#define G_T5_AEC_PMA_TX_READY(x) (((x) >> S_T5_AEC_PMA_TX_READY) & M_T5_AEC_PMA_TX_READY)
+
+#define S_T5_AEC_PMA_RX_READY    0
+#define M_T5_AEC_PMA_RX_READY    0xfU
+#define V_T5_AEC_PMA_RX_READY(x) ((x) << S_T5_AEC_PMA_RX_READY)
+#define G_T5_AEC_PMA_RX_READY(x) (((x) >> S_T5_AEC_PMA_RX_READY) & M_T5_AEC_PMA_RX_READY)
+
+#define A_MAC_PORT_PKT_COUNT 0x81c
+#define A_MAC_PORT_CFG4 0x820
+
+#define S_AEC3_RX_WIDTH    14
+#define M_AEC3_RX_WIDTH    0x3U
+#define V_AEC3_RX_WIDTH(x) ((x) << S_AEC3_RX_WIDTH)
+#define G_AEC3_RX_WIDTH(x) (((x) >> S_AEC3_RX_WIDTH) & M_AEC3_RX_WIDTH)
+
+#define S_AEC2_RX_WIDTH    12
+#define M_AEC2_RX_WIDTH    0x3U
+#define V_AEC2_RX_WIDTH(x) ((x) << S_AEC2_RX_WIDTH)
+#define G_AEC2_RX_WIDTH(x) (((x) >> S_AEC2_RX_WIDTH) & M_AEC2_RX_WIDTH)
+
+#define S_AEC1_RX_WIDTH    10
+#define M_AEC1_RX_WIDTH    0x3U
+#define V_AEC1_RX_WIDTH(x) ((x) << S_AEC1_RX_WIDTH)
+#define G_AEC1_RX_WIDTH(x) (((x) >> S_AEC1_RX_WIDTH) & M_AEC1_RX_WIDTH)
+
+#define S_AEC0_RX_WIDTH    8
+#define M_AEC0_RX_WIDTH    0x3U
+#define V_AEC0_RX_WIDTH(x) ((x) << S_AEC0_RX_WIDTH)
+#define G_AEC0_RX_WIDTH(x) (((x) >> S_AEC0_RX_WIDTH) & M_AEC0_RX_WIDTH)
+
+#define S_AEC3_TX_WIDTH    6
+#define M_AEC3_TX_WIDTH    0x3U
+#define V_AEC3_TX_WIDTH(x) ((x) << S_AEC3_TX_WIDTH)
+#define G_AEC3_TX_WIDTH(x) (((x) >> S_AEC3_TX_WIDTH) & M_AEC3_TX_WIDTH)
+
+#define S_AEC2_TX_WIDTH    4
+#define M_AEC2_TX_WIDTH    0x3U
+#define V_AEC2_TX_WIDTH(x) ((x) << S_AEC2_TX_WIDTH)
+#define G_AEC2_TX_WIDTH(x) (((x) >> S_AEC2_TX_WIDTH) & M_AEC2_TX_WIDTH)
+
+#define S_AEC1_TX_WIDTH    2
+#define M_AEC1_TX_WIDTH    0x3U
+#define V_AEC1_TX_WIDTH(x) ((x) << S_AEC1_TX_WIDTH)
+#define G_AEC1_TX_WIDTH(x) (((x) >> S_AEC1_TX_WIDTH) & M_AEC1_TX_WIDTH)
+
+#define S_AEC0_TX_WIDTH    0
+#define M_AEC0_TX_WIDTH    0x3U
+#define V_AEC0_TX_WIDTH(x) ((x) << S_AEC0_TX_WIDTH)
+#define G_AEC0_TX_WIDTH(x) (((x) >> S_AEC0_TX_WIDTH) & M_AEC0_TX_WIDTH)
+
+#define A_MAC_PORT_MAGIC_MACID_LO 0x824
+#define A_MAC_PORT_MAGIC_MACID_HI 0x828
+#define A_MAC_PORT_LINK_STATUS 0x834
+
+#define S_AN_DONE    6
+#define V_AN_DONE(x) ((x) << S_AN_DONE)
+#define F_AN_DONE    V_AN_DONE(1U)
+
+#define S_ALIGN_DONE    5
+#define V_ALIGN_DONE(x) ((x) << S_ALIGN_DONE)
+#define F_ALIGN_DONE    V_ALIGN_DONE(1U)
+
+#define S_BLOCK_LOCK    4
+#define V_BLOCK_LOCK(x) ((x) << S_BLOCK_LOCK)
+#define F_BLOCK_LOCK    V_BLOCK_LOCK(1U)
+
+#define A_MAC_PORT_EPIO_DATA0 0x8c0
+#define A_MAC_PORT_EPIO_DATA1 0x8c4
+#define A_MAC_PORT_EPIO_DATA2 0x8c8
+#define A_MAC_PORT_EPIO_DATA3 0x8cc
+#define A_MAC_PORT_EPIO_OP 0x8d0
+#define A_MAC_PORT_WOL_STATUS 0x8d4
+#define A_MAC_PORT_INT_EN 0x8d8
+
+#define S_TX_TS_AVAIL    29
+#define V_TX_TS_AVAIL(x) ((x) << S_TX_TS_AVAIL)
+#define F_TX_TS_AVAIL    V_TX_TS_AVAIL(1U)
+
+#define S_AN_PAGE_RCVD    2
+#define V_AN_PAGE_RCVD(x) ((x) << S_AN_PAGE_RCVD)
+#define F_AN_PAGE_RCVD    V_AN_PAGE_RCVD(1U)
+
+#define A_MAC_PORT_INT_CAUSE 0x8dc
+#define A_MAC_PORT_PERR_INT_EN 0x8e0
+
+#define S_PERR_PKT_RAM    24
+#define V_PERR_PKT_RAM(x) ((x) << S_PERR_PKT_RAM)
+#define F_PERR_PKT_RAM    V_PERR_PKT_RAM(1U)
+
+#define S_PERR_MASK_RAM    23
+#define V_PERR_MASK_RAM(x) ((x) << S_PERR_MASK_RAM)
+#define F_PERR_MASK_RAM    V_PERR_MASK_RAM(1U)
+
+#define S_PERR_CRC_RAM    22
+#define V_PERR_CRC_RAM(x) ((x) << S_PERR_CRC_RAM)
+#define F_PERR_CRC_RAM    V_PERR_CRC_RAM(1U)
+
+#define S_RX_DFF_SEG0    21
+#define V_RX_DFF_SEG0(x) ((x) << S_RX_DFF_SEG0)
+#define F_RX_DFF_SEG0    V_RX_DFF_SEG0(1U)
+
+#define S_RX_SFF_SEG0    20
+#define V_RX_SFF_SEG0(x) ((x) << S_RX_SFF_SEG0)
+#define F_RX_SFF_SEG0    V_RX_SFF_SEG0(1U)
+
+#define S_RX_DFF_MAC10    19
+#define V_RX_DFF_MAC10(x) ((x) << S_RX_DFF_MAC10)
+#define F_RX_DFF_MAC10    V_RX_DFF_MAC10(1U)
+
+#define S_RX_SFF_MAC10    18
+#define V_RX_SFF_MAC10(x) ((x) << S_RX_SFF_MAC10)
+#define F_RX_SFF_MAC10    V_RX_SFF_MAC10(1U)
+
+#define S_TX_DFF_SEG0    17
+#define V_TX_DFF_SEG0(x) ((x) << S_TX_DFF_SEG0)
+#define F_TX_DFF_SEG0    V_TX_DFF_SEG0(1U)
+
+#define S_TX_SFF_SEG0    16
+#define V_TX_SFF_SEG0(x) ((x) << S_TX_SFF_SEG0)
+#define F_TX_SFF_SEG0    V_TX_SFF_SEG0(1U)
+
+#define S_TX_DFF_MAC10    15
+#define V_TX_DFF_MAC10(x) ((x) << S_TX_DFF_MAC10)
+#define F_TX_DFF_MAC10    V_TX_DFF_MAC10(1U)
+
+#define S_TX_SFF_MAC10    14
+#define V_TX_SFF_MAC10(x) ((x) << S_TX_SFF_MAC10)
+#define F_TX_SFF_MAC10    V_TX_SFF_MAC10(1U)
+
+#define S_RX_STATS    13
+#define V_RX_STATS(x) ((x) << S_RX_STATS)
+#define F_RX_STATS    V_RX_STATS(1U)
+
+#define S_TX_STATS    12
+#define V_TX_STATS(x) ((x) << S_TX_STATS)
+#define F_TX_STATS    V_TX_STATS(1U)
+
+#define S_PERR3_RX_MIX    11
+#define V_PERR3_RX_MIX(x) ((x) << S_PERR3_RX_MIX)
+#define F_PERR3_RX_MIX    V_PERR3_RX_MIX(1U)
+
+#define S_PERR3_RX_SD    10
+#define V_PERR3_RX_SD(x) ((x) << S_PERR3_RX_SD)
+#define F_PERR3_RX_SD    V_PERR3_RX_SD(1U)
+
+#define S_PERR3_TX    9
+#define V_PERR3_TX(x) ((x) << S_PERR3_TX)
+#define F_PERR3_TX    V_PERR3_TX(1U)
+
+#define S_PERR2_RX_MIX    8
+#define V_PERR2_RX_MIX(x) ((x) << S_PERR2_RX_MIX)
+#define F_PERR2_RX_MIX    V_PERR2_RX_MIX(1U)
+
+#define S_PERR2_RX_SD    7
+#define V_PERR2_RX_SD(x) ((x) << S_PERR2_RX_SD)
+#define F_PERR2_RX_SD    V_PERR2_RX_SD(1U)
+
+#define S_PERR2_TX    6
+#define V_PERR2_TX(x) ((x) << S_PERR2_TX)
+#define F_PERR2_TX    V_PERR2_TX(1U)
+
+#define S_PERR1_RX_MIX    5
+#define V_PERR1_RX_MIX(x) ((x) << S_PERR1_RX_MIX)
+#define F_PERR1_RX_MIX    V_PERR1_RX_MIX(1U)
+
+#define S_PERR1_RX_SD    4
+#define V_PERR1_RX_SD(x) ((x) << S_PERR1_RX_SD)
+#define F_PERR1_RX_SD    V_PERR1_RX_SD(1U)
+
+#define S_PERR1_TX    3
+#define V_PERR1_TX(x) ((x) << S_PERR1_TX)
+#define F_PERR1_TX    V_PERR1_TX(1U)
+
+#define S_PERR0_RX_MIX    2
+#define V_PERR0_RX_MIX(x) ((x) << S_PERR0_RX_MIX)
+#define F_PERR0_RX_MIX    V_PERR0_RX_MIX(1U)
+
+#define S_PERR0_RX_SD    1
+#define V_PERR0_RX_SD(x) ((x) << S_PERR0_RX_SD)
+#define F_PERR0_RX_SD    V_PERR0_RX_SD(1U)
+
+#define S_PERR0_TX    0
+#define V_PERR0_TX(x) ((x) << S_PERR0_TX)
+#define F_PERR0_TX    V_PERR0_TX(1U)
+
+#define A_MAC_PORT_PERR_INT_CAUSE 0x8e4
+#define A_MAC_PORT_PERR_ENABLE 0x8e8
+#define A_MAC_PORT_PERR_INJECT 0x8ec
+#define A_MAC_PORT_HSS_CFG0 0x8f0
+
+#define S_HSSREFCLKVALIDA    20
+#define V_HSSREFCLKVALIDA(x) ((x) << S_HSSREFCLKVALIDA)
+#define F_HSSREFCLKVALIDA    V_HSSREFCLKVALIDA(1U)
+
+#define S_HSSREFCLKVALIDB    19
+#define V_HSSREFCLKVALIDB(x) ((x) << S_HSSREFCLKVALIDB)
+#define F_HSSREFCLKVALIDB    V_HSSREFCLKVALIDB(1U)
+
+#define S_HSSRESYNCA    18
+#define V_HSSRESYNCA(x) ((x) << S_HSSRESYNCA)
+#define F_HSSRESYNCA    V_HSSRESYNCA(1U)
+
+#define S_HSSRESYNCB    16
+#define V_HSSRESYNCB(x) ((x) << S_HSSRESYNCB)
+#define F_HSSRESYNCB    V_HSSRESYNCB(1U)
+
+#define S_HSSRECCALA    15
+#define V_HSSRECCALA(x) ((x) << S_HSSRECCALA)
+#define F_HSSRECCALA    V_HSSRECCALA(1U)
+
+#define S_HSSRECCALB    13
+#define V_HSSRECCALB(x) ((x) << S_HSSRECCALB)
+#define F_HSSRECCALB    V_HSSRECCALB(1U)
+
+#define S_HSSPLLBYPA    12
+#define V_HSSPLLBYPA(x) ((x) << S_HSSPLLBYPA)
+#define F_HSSPLLBYPA    V_HSSPLLBYPA(1U)
+
+#define S_HSSPLLBYPB    11
+#define V_HSSPLLBYPB(x) ((x) << S_HSSPLLBYPB)
+#define F_HSSPLLBYPB    V_HSSPLLBYPB(1U)
+
+#define S_HSSPDWNPLLA    10
+#define V_HSSPDWNPLLA(x) ((x) << S_HSSPDWNPLLA)
+#define F_HSSPDWNPLLA    V_HSSPDWNPLLA(1U)
+
+#define S_HSSPDWNPLLB    9
+#define V_HSSPDWNPLLB(x) ((x) << S_HSSPDWNPLLB)
+#define F_HSSPDWNPLLB    V_HSSPDWNPLLB(1U)
+
+#define S_HSSVCOSELA    8
+#define V_HSSVCOSELA(x) ((x) << S_HSSVCOSELA)
+#define F_HSSVCOSELA    V_HSSVCOSELA(1U)
+
+#define S_HSSVCOSELB    7
+#define V_HSSVCOSELB(x) ((x) << S_HSSVCOSELB)
+#define F_HSSVCOSELB    V_HSSVCOSELB(1U)
+
+#define S_HSSCALCOMP    6
+#define V_HSSCALCOMP(x) ((x) << S_HSSCALCOMP)
+#define F_HSSCALCOMP    V_HSSCALCOMP(1U)
+
+#define S_HSSCALENAB    5
+#define V_HSSCALENAB(x) ((x) << S_HSSCALENAB)
+#define F_HSSCALENAB    V_HSSCALENAB(1U)
+
+#define A_MAC_PORT_HSS_CFG1 0x8f4
+
+#define S_RXACONFIGSEL    30
+#define M_RXACONFIGSEL    0x3U
+#define V_RXACONFIGSEL(x) ((x) << S_RXACONFIGSEL)
+#define G_RXACONFIGSEL(x) (((x) >> S_RXACONFIGSEL) & M_RXACONFIGSEL)
+
+#define S_RXAQUIET    29
+#define V_RXAQUIET(x) ((x) << S_RXAQUIET)
+#define F_RXAQUIET    V_RXAQUIET(1U)
+
+#define S_RXAREFRESH    28
+#define V_RXAREFRESH(x) ((x) << S_RXAREFRESH)
+#define F_RXAREFRESH    V_RXAREFRESH(1U)
+
+#define S_RXBCONFIGSEL    26
+#define M_RXBCONFIGSEL    0x3U
+#define V_RXBCONFIGSEL(x) ((x) << S_RXBCONFIGSEL)
+#define G_RXBCONFIGSEL(x) (((x) >> S_RXBCONFIGSEL) & M_RXBCONFIGSEL)
+
+#define S_RXBQUIET    25
+#define V_RXBQUIET(x) ((x) << S_RXBQUIET)
+#define F_RXBQUIET    V_RXBQUIET(1U)
+
+#define S_RXBREFRESH    24
+#define V_RXBREFRESH(x) ((x) << S_RXBREFRESH)
+#define F_RXBREFRESH    V_RXBREFRESH(1U)
+
+#define S_RXCCONFIGSEL    22
+#define M_RXCCONFIGSEL    0x3U
+#define V_RXCCONFIGSEL(x) ((x) << S_RXCCONFIGSEL)
+#define G_RXCCONFIGSEL(x) (((x) >> S_RXCCONFIGSEL) & M_RXCCONFIGSEL)
+
+#define S_RXCQUIET    21
+#define V_RXCQUIET(x) ((x) << S_RXCQUIET)
+#define F_RXCQUIET    V_RXCQUIET(1U)
+
+#define S_RXCREFRESH    20
+#define V_RXCREFRESH(x) ((x) << S_RXCREFRESH)
+#define F_RXCREFRESH    V_RXCREFRESH(1U)
+
+#define S_RXDCONFIGSEL    18
+#define M_RXDCONFIGSEL    0x3U
+#define V_RXDCONFIGSEL(x) ((x) << S_RXDCONFIGSEL)
+#define G_RXDCONFIGSEL(x) (((x) >> S_RXDCONFIGSEL) & M_RXDCONFIGSEL)
+
+#define S_RXDQUIET    17
+#define V_RXDQUIET(x) ((x) << S_RXDQUIET)
+#define F_RXDQUIET    V_RXDQUIET(1U)
+
+#define S_RXDREFRESH    16
+#define V_RXDREFRESH(x) ((x) << S_RXDREFRESH)
+#define F_RXDREFRESH    V_RXDREFRESH(1U)
+
+#define S_TXACONFIGSEL    14
+#define M_TXACONFIGSEL    0x3U
+#define V_TXACONFIGSEL(x) ((x) << S_TXACONFIGSEL)
+#define G_TXACONFIGSEL(x) (((x) >> S_TXACONFIGSEL) & M_TXACONFIGSEL)
+
+#define S_TXAQUIET    13
+#define V_TXAQUIET(x) ((x) << S_TXAQUIET)
+#define F_TXAQUIET    V_TXAQUIET(1U)
+
+#define S_TXAREFRESH    12
+#define V_TXAREFRESH(x) ((x) << S_TXAREFRESH)
+#define F_TXAREFRESH    V_TXAREFRESH(1U)
+
+#define S_TXBCONFIGSEL    10
+#define M_TXBCONFIGSEL    0x3U
+#define V_TXBCONFIGSEL(x) ((x) << S_TXBCONFIGSEL)
+#define G_TXBCONFIGSEL(x) (((x) >> S_TXBCONFIGSEL) & M_TXBCONFIGSEL)
+
+#define S_TXBQUIET    9
+#define V_TXBQUIET(x) ((x) << S_TXBQUIET)
+#define F_TXBQUIET    V_TXBQUIET(1U)
+
+#define S_TXBREFRESH    8
+#define V_TXBREFRESH(x) ((x) << S_TXBREFRESH)
+#define F_TXBREFRESH    V_TXBREFRESH(1U)
+
+#define S_TXCCONFIGSEL    6
+#define M_TXCCONFIGSEL    0x3U
+#define V_TXCCONFIGSEL(x) ((x) << S_TXCCONFIGSEL)
+#define G_TXCCONFIGSEL(x) (((x) >> S_TXCCONFIGSEL) & M_TXCCONFIGSEL)
+
+#define S_TXCQUIET    5
+#define V_TXCQUIET(x) ((x) << S_TXCQUIET)
+#define F_TXCQUIET    V_TXCQUIET(1U)
+
+#define S_TXCREFRESH    4
+#define V_TXCREFRESH(x) ((x) << S_TXCREFRESH)
+#define F_TXCREFRESH    V_TXCREFRESH(1U)
+
+#define S_TXDCONFIGSEL    2
+#define M_TXDCONFIGSEL    0x3U
+#define V_TXDCONFIGSEL(x) ((x) << S_TXDCONFIGSEL)
+#define G_TXDCONFIGSEL(x) (((x) >> S_TXDCONFIGSEL) & M_TXDCONFIGSEL)
+
+#define S_TXDQUIET    1
+#define V_TXDQUIET(x) ((x) << S_TXDQUIET)
+#define F_TXDQUIET    V_TXDQUIET(1U)
+
+#define S_TXDREFRESH    0
+#define V_TXDREFRESH(x) ((x) << S_TXDREFRESH)
+#define F_TXDREFRESH    V_TXDREFRESH(1U)
+
+#define A_MAC_PORT_HSS_CFG2 0x8f8
+
+#define S_RXAASSTCLK    31
+#define V_RXAASSTCLK(x) ((x) << S_RXAASSTCLK)
+#define F_RXAASSTCLK    V_RXAASSTCLK(1U)
+
+#define S_T5RXAPRBSRST    30
+#define V_T5RXAPRBSRST(x) ((x) << S_T5RXAPRBSRST)
+#define F_T5RXAPRBSRST    V_T5RXAPRBSRST(1U)
+
+#define S_RXBASSTCLK    29
+#define V_RXBASSTCLK(x) ((x) << S_RXBASSTCLK)
+#define F_RXBASSTCLK    V_RXBASSTCLK(1U)
+
+#define S_T5RXBPRBSRST    28
+#define V_T5RXBPRBSRST(x) ((x) << S_T5RXBPRBSRST)
+#define F_T5RXBPRBSRST    V_T5RXBPRBSRST(1U)
+
+#define S_RXCASSTCLK    27
+#define V_RXCASSTCLK(x) ((x) << S_RXCASSTCLK)
+#define F_RXCASSTCLK    V_RXCASSTCLK(1U)
+
+#define S_T5RXCPRBSRST    26
+#define V_T5RXCPRBSRST(x) ((x) << S_T5RXCPRBSRST)
+#define F_T5RXCPRBSRST    V_T5RXCPRBSRST(1U)
+
+#define S_RXDASSTCLK    25
+#define V_RXDASSTCLK(x) ((x) << S_RXDASSTCLK)
+#define F_RXDASSTCLK    V_RXDASSTCLK(1U)
+
+#define S_T5RXDPRBSRST    24
+#define V_T5RXDPRBSRST(x) ((x) << S_T5RXDPRBSRST)
+#define F_T5RXDPRBSRST    V_T5RXDPRBSRST(1U)
+
+#define A_MAC_PORT_HSS_CFG3 0x8fc
+
+#define S_HSSCALSSTN    25
+#define M_HSSCALSSTN    0x7U
+#define V_HSSCALSSTN(x) ((x) << S_HSSCALSSTN)
+#define G_HSSCALSSTN(x) (((x) >> S_HSSCALSSTN) & M_HSSCALSSTN)
+
+#define S_HSSCALSSTP    22
+#define M_HSSCALSSTP    0x7U
+#define V_HSSCALSSTP(x) ((x) << S_HSSCALSSTP)
+#define G_HSSCALSSTP(x) (((x) >> S_HSSCALSSTP) & M_HSSCALSSTP)
+
+#define S_HSSVBOOSTDIVB    19
+#define M_HSSVBOOSTDIVB    0x7U
+#define V_HSSVBOOSTDIVB(x) ((x) << S_HSSVBOOSTDIVB)
+#define G_HSSVBOOSTDIVB(x) (((x) >> S_HSSVBOOSTDIVB) & M_HSSVBOOSTDIVB)
+
+#define S_HSSVBOOSTDIVA    16
+#define M_HSSVBOOSTDIVA    0x7U
+#define V_HSSVBOOSTDIVA(x) ((x) << S_HSSVBOOSTDIVA)
+#define G_HSSVBOOSTDIVA(x) (((x) >> S_HSSVBOOSTDIVA) & M_HSSVBOOSTDIVA)
+
+#define S_HSSPLLCONFIGB    8
+#define M_HSSPLLCONFIGB    0xffU
+#define V_HSSPLLCONFIGB(x) ((x) << S_HSSPLLCONFIGB)
+#define G_HSSPLLCONFIGB(x) (((x) >> S_HSSPLLCONFIGB) & M_HSSPLLCONFIGB)
+
+#define S_HSSPLLCONFIGA    0
+#define M_HSSPLLCONFIGA    0xffU
+#define V_HSSPLLCONFIGA(x) ((x) << S_HSSPLLCONFIGA)
+#define G_HSSPLLCONFIGA(x) (((x) >> S_HSSPLLCONFIGA) & M_HSSPLLCONFIGA)
+
+#define A_MAC_PORT_HSS_CFG4 0x900
+
+#define S_HSSDIVSELA    9
+#define M_HSSDIVSELA    0x1ffU
+#define V_HSSDIVSELA(x) ((x) << S_HSSDIVSELA)
+#define G_HSSDIVSELA(x) (((x) >> S_HSSDIVSELA) & M_HSSDIVSELA)
+
+#define S_HSSDIVSELB    0
+#define M_HSSDIVSELB    0x1ffU
+#define V_HSSDIVSELB(x) ((x) << S_HSSDIVSELB)
+#define G_HSSDIVSELB(x) (((x) >> S_HSSDIVSELB) & M_HSSDIVSELB)
+
+#define A_MAC_PORT_HSS_STATUS 0x904
+
+#define S_HSSPLLLOCKB    3
+#define V_HSSPLLLOCKB(x) ((x) << S_HSSPLLLOCKB)
+#define F_HSSPLLLOCKB    V_HSSPLLLOCKB(1U)
+
+#define S_HSSPLLLOCKA    2
+#define V_HSSPLLLOCKA(x) ((x) << S_HSSPLLLOCKA)
+#define F_HSSPLLLOCKA    V_HSSPLLLOCKA(1U)
+
+#define S_HSSPRTREADYB    1
+#define V_HSSPRTREADYB(x) ((x) << S_HSSPRTREADYB)
+#define F_HSSPRTREADYB    V_HSSPRTREADYB(1U)
+
+#define S_HSSPRTREADYA    0
+#define V_HSSPRTREADYA(x) ((x) << S_HSSPRTREADYA)
+#define F_HSSPRTREADYA    V_HSSPRTREADYA(1U)
+
+#define A_MAC_PORT_HSS_EEE_STATUS 0x908
+
+#define S_RXAQUIET_STATUS    15
+#define V_RXAQUIET_STATUS(x) ((x) << S_RXAQUIET_STATUS)
+#define F_RXAQUIET_STATUS    V_RXAQUIET_STATUS(1U)
+
+#define S_RXAREFRESH_STATUS    14
+#define V_RXAREFRESH_STATUS(x) ((x) << S_RXAREFRESH_STATUS)
+#define F_RXAREFRESH_STATUS    V_RXAREFRESH_STATUS(1U)
+
+#define S_RXBQUIET_STATUS    13
+#define V_RXBQUIET_STATUS(x) ((x) << S_RXBQUIET_STATUS)
+#define F_RXBQUIET_STATUS    V_RXBQUIET_STATUS(1U)
+
+#define S_RXBREFRESH_STATUS    12
+#define V_RXBREFRESH_STATUS(x) ((x) << S_RXBREFRESH_STATUS)
+#define F_RXBREFRESH_STATUS    V_RXBREFRESH_STATUS(1U)
+
+#define S_RXCQUIET_STATUS    11
+#define V_RXCQUIET_STATUS(x) ((x) << S_RXCQUIET_STATUS)
+#define F_RXCQUIET_STATUS    V_RXCQUIET_STATUS(1U)
+
+#define S_RXCREFRESH_STATUS    10
+#define V_RXCREFRESH_STATUS(x) ((x) << S_RXCREFRESH_STATUS)
+#define F_RXCREFRESH_STATUS    V_RXCREFRESH_STATUS(1U)
+
+#define S_RXDQUIET_STATUS    9
+#define V_RXDQUIET_STATUS(x) ((x) << S_RXDQUIET_STATUS)
+#define F_RXDQUIET_STATUS    V_RXDQUIET_STATUS(1U)
+
+#define S_RXDREFRESH_STATUS    8
+#define V_RXDREFRESH_STATUS(x) ((x) << S_RXDREFRESH_STATUS)
+#define F_RXDREFRESH_STATUS    V_RXDREFRESH_STATUS(1U)
+
+#define S_TXAQUIET_STATUS    7
+#define V_TXAQUIET_STATUS(x) ((x) << S_TXAQUIET_STATUS)
+#define F_TXAQUIET_STATUS    V_TXAQUIET_STATUS(1U)
+
+#define S_TXAREFRESH_STATUS    6
+#define V_TXAREFRESH_STATUS(x) ((x) << S_TXAREFRESH_STATUS)
+#define F_TXAREFRESH_STATUS    V_TXAREFRESH_STATUS(1U)
+
+#define S_TXBQUIET_STATUS    5
+#define V_TXBQUIET_STATUS(x) ((x) << S_TXBQUIET_STATUS)
+#define F_TXBQUIET_STATUS    V_TXBQUIET_STATUS(1U)
+
+#define S_TXBREFRESH_STATUS    4
+#define V_TXBREFRESH_STATUS(x) ((x) << S_TXBREFRESH_STATUS)
+#define F_TXBREFRESH_STATUS    V_TXBREFRESH_STATUS(1U)
+
+#define S_TXCQUIET_STATUS    3
+#define V_TXCQUIET_STATUS(x) ((x) << S_TXCQUIET_STATUS)
+#define F_TXCQUIET_STATUS    V_TXCQUIET_STATUS(1U)
+
+#define S_TXCREFRESH_STATUS    2
+#define V_TXCREFRESH_STATUS(x) ((x) << S_TXCREFRESH_STATUS)
+#define F_TXCREFRESH_STATUS    V_TXCREFRESH_STATUS(1U)
+
+#define S_TXDQUIET_STATUS    1
+#define V_TXDQUIET_STATUS(x) ((x) << S_TXDQUIET_STATUS)
+#define F_TXDQUIET_STATUS    V_TXDQUIET_STATUS(1U)
+
+#define S_TXDREFRESH_STATUS    0
+#define V_TXDREFRESH_STATUS(x) ((x) << S_TXDREFRESH_STATUS)
+#define F_TXDREFRESH_STATUS    V_TXDREFRESH_STATUS(1U)
+
+#define A_MAC_PORT_HSS_SIGDET_STATUS 0x90c
+#define A_MAC_PORT_HSS_PL_CTL 0x910
+
+#define S_TOV    16
+#define M_TOV    0xffU
+#define V_TOV(x) ((x) << S_TOV)
+#define G_TOV(x) (((x) >> S_TOV) & M_TOV)
+
+#define S_TSU    8
+#define M_TSU    0xffU
+#define V_TSU(x) ((x) << S_TSU)
+#define G_TSU(x) (((x) >> S_TSU) & M_TSU)
+
+#define S_IPW    0
+#define M_IPW    0xffU
+#define V_IPW(x) ((x) << S_IPW)
+#define G_IPW(x) (((x) >> S_IPW) & M_IPW)
+
+#define A_MAC_PORT_RUNT_FRAME 0x914
+
+#define S_RUNTCLEAR    16
+#define V_RUNTCLEAR(x) ((x) << S_RUNTCLEAR)
+#define F_RUNTCLEAR    V_RUNTCLEAR(1U)
+
+#define S_RUNT    0
+#define M_RUNT    0xffffU
+#define V_RUNT(x) ((x) << S_RUNT)
+#define G_RUNT(x) (((x) >> S_RUNT) & M_RUNT)
+
+#define A_MAC_PORT_EEE_STATUS 0x918
+
+#define S_EEE_TX_10G_STATE    10
+#define M_EEE_TX_10G_STATE    0x3U
+#define V_EEE_TX_10G_STATE(x) ((x) << S_EEE_TX_10G_STATE)
+#define G_EEE_TX_10G_STATE(x) (((x) >> S_EEE_TX_10G_STATE) & M_EEE_TX_10G_STATE)
+
+#define S_EEE_RX_10G_STATE    8
+#define M_EEE_RX_10G_STATE    0x3U
+#define V_EEE_RX_10G_STATE(x) ((x) << S_EEE_RX_10G_STATE)
+#define G_EEE_RX_10G_STATE(x) (((x) >> S_EEE_RX_10G_STATE) & M_EEE_RX_10G_STATE)
+
+#define S_EEE_TX_1G_STATE    6
+#define M_EEE_TX_1G_STATE    0x3U
+#define V_EEE_TX_1G_STATE(x) ((x) << S_EEE_TX_1G_STATE)
+#define G_EEE_TX_1G_STATE(x) (((x) >> S_EEE_TX_1G_STATE) & M_EEE_TX_1G_STATE)
+
+#define S_EEE_RX_1G_STATE    4
+#define M_EEE_RX_1G_STATE    0x3U
+#define V_EEE_RX_1G_STATE(x) ((x) << S_EEE_RX_1G_STATE)
+#define G_EEE_RX_1G_STATE(x) (((x) >> S_EEE_RX_1G_STATE) & M_EEE_RX_1G_STATE)
+
+#define S_PMA_RX_REFRESH    3
+#define V_PMA_RX_REFRESH(x) ((x) << S_PMA_RX_REFRESH)
+#define F_PMA_RX_REFRESH    V_PMA_RX_REFRESH(1U)
+
+#define S_PMA_RX_QUIET    2
+#define V_PMA_RX_QUIET(x) ((x) << S_PMA_RX_QUIET)
+#define F_PMA_RX_QUIET    V_PMA_RX_QUIET(1U)
+
+#define S_PMA_TX_REFRESH    1
+#define V_PMA_TX_REFRESH(x) ((x) << S_PMA_TX_REFRESH)
+#define F_PMA_TX_REFRESH    V_PMA_TX_REFRESH(1U)
+
+#define S_PMA_TX_QUIET    0
+#define V_PMA_TX_QUIET(x) ((x) << S_PMA_TX_QUIET)
+#define F_PMA_TX_QUIET    V_PMA_TX_QUIET(1U)
+
+#define A_MAC_PORT_CGEN 0x91c
+
+#define S_CGEN    8
+#define V_CGEN(x) ((x) << S_CGEN)
+#define F_CGEN    V_CGEN(1U)
+
+#define S_SD7_CGEN    7
+#define V_SD7_CGEN(x) ((x) << S_SD7_CGEN)
+#define F_SD7_CGEN    V_SD7_CGEN(1U)
+
+#define S_SD6_CGEN    6
+#define V_SD6_CGEN(x) ((x) << S_SD6_CGEN)
+#define F_SD6_CGEN    V_SD6_CGEN(1U)
+
+#define S_SD5_CGEN    5
+#define V_SD5_CGEN(x) ((x) << S_SD5_CGEN)
+#define F_SD5_CGEN    V_SD5_CGEN(1U)
+
+#define S_SD4_CGEN    4
+#define V_SD4_CGEN(x) ((x) << S_SD4_CGEN)
+#define F_SD4_CGEN    V_SD4_CGEN(1U)
+
+#define S_SD3_CGEN    3
+#define V_SD3_CGEN(x) ((x) << S_SD3_CGEN)
+#define F_SD3_CGEN    V_SD3_CGEN(1U)
+
+#define S_SD2_CGEN    2
+#define V_SD2_CGEN(x) ((x) << S_SD2_CGEN)
+#define F_SD2_CGEN    V_SD2_CGEN(1U)
+
+#define S_SD1_CGEN    1
+#define V_SD1_CGEN(x) ((x) << S_SD1_CGEN)
+#define F_SD1_CGEN    V_SD1_CGEN(1U)
+
+#define S_SD0_CGEN    0
+#define V_SD0_CGEN(x) ((x) << S_SD0_CGEN)
+#define F_SD0_CGEN    V_SD0_CGEN(1U)
+
+#define A_MAC_PORT_CGEN_MTIP 0x920
+
+#define S_MACSEG5_CGEN    11
+#define V_MACSEG5_CGEN(x) ((x) << S_MACSEG5_CGEN)
+#define F_MACSEG5_CGEN    V_MACSEG5_CGEN(1U)
+
+#define S_PCSSEG5_CGEN    10
+#define V_PCSSEG5_CGEN(x) ((x) << S_PCSSEG5_CGEN)
+#define F_PCSSEG5_CGEN    V_PCSSEG5_CGEN(1U)
+
+#define S_MACSEG4_CGEN    9
+#define V_MACSEG4_CGEN(x) ((x) << S_MACSEG4_CGEN)
+#define F_MACSEG4_CGEN    V_MACSEG4_CGEN(1U)
+
+#define S_PCSSEG4_CGEN    8
+#define V_PCSSEG4_CGEN(x) ((x) << S_PCSSEG4_CGEN)
+#define F_PCSSEG4_CGEN    V_PCSSEG4_CGEN(1U)
+
+#define S_MACSEG3_CGEN    7
+#define V_MACSEG3_CGEN(x) ((x) << S_MACSEG3_CGEN)
+#define F_MACSEG3_CGEN    V_MACSEG3_CGEN(1U)
+
+#define S_PCSSEG3_CGEN    6
+#define V_PCSSEG3_CGEN(x) ((x) << S_PCSSEG3_CGEN)
+#define F_PCSSEG3_CGEN    V_PCSSEG3_CGEN(1U)
+
+#define S_MACSEG2_CGEN    5
+#define V_MACSEG2_CGEN(x) ((x) << S_MACSEG2_CGEN)
+#define F_MACSEG2_CGEN    V_MACSEG2_CGEN(1U)
+
+#define S_PCSSEG2_CGEN    4
+#define V_PCSSEG2_CGEN(x) ((x) << S_PCSSEG2_CGEN)
+#define F_PCSSEG2_CGEN    V_PCSSEG2_CGEN(1U)
+
+#define S_MACSEG1_CGEN    3
+#define V_MACSEG1_CGEN(x) ((x) << S_MACSEG1_CGEN)
+#define F_MACSEG1_CGEN    V_MACSEG1_CGEN(1U)
+
+#define S_PCSSEG1_CGEN    2
+#define V_PCSSEG1_CGEN(x) ((x) << S_PCSSEG1_CGEN)
+#define F_PCSSEG1_CGEN    V_PCSSEG1_CGEN(1U)
+
+#define S_MACSEG0_CGEN    1
+#define V_MACSEG0_CGEN(x) ((x) << S_MACSEG0_CGEN)
+#define F_MACSEG0_CGEN    V_MACSEG0_CGEN(1U)
+
+#define S_PCSSEG0_CGEN    0
+#define V_PCSSEG0_CGEN(x) ((x) << S_PCSSEG0_CGEN)
+#define F_PCSSEG0_CGEN    V_PCSSEG0_CGEN(1U)
+
+#define A_MAC_PORT_TX_TS_ID 0x924
+
+#define S_TS_ID    0
+#define M_TS_ID    0x7U
+#define V_TS_ID(x) ((x) << S_TS_ID)
+#define G_TS_ID(x) (((x) >> S_TS_ID) & M_TS_ID)
+
+#define A_MAC_PORT_TX_TS_VAL_LO 0x928
+#define A_MAC_PORT_TX_TS_VAL_HI 0x92c
+#define A_MAC_PORT_EEE_CTL 0x930
+
+#define S_EEE_CTRL    2
+#define M_EEE_CTRL    0x3fffffffU
+#define V_EEE_CTRL(x) ((x) << S_EEE_CTRL)
+#define G_EEE_CTRL(x) (((x) >> S_EEE_CTRL) & M_EEE_CTRL)
+
+#define S_TICK_START    1
+#define V_TICK_START(x) ((x) << S_TICK_START)
+#define F_TICK_START    V_TICK_START(1U)
+
+#define S_EEE_ENABLE    0
+#define V_EEE_ENABLE(x) ((x) << S_EEE_ENABLE)
+#define F_EEE_ENABLE    V_EEE_ENABLE(1U)
+
+#define A_MAC_PORT_EEE_TX_CTL 0x934
+
+#define S_WAKE_TIMER    16
+#define M_WAKE_TIMER    0xffffU
+#define V_WAKE_TIMER(x) ((x) << S_WAKE_TIMER)
+#define G_WAKE_TIMER(x) (((x) >> S_WAKE_TIMER) & M_WAKE_TIMER)
+
+#define S_HSS_TIMER    5
+#define M_HSS_TIMER    0xfU
+#define V_HSS_TIMER(x) ((x) << S_HSS_TIMER)
+#define G_HSS_TIMER(x) (((x) >> S_HSS_TIMER) & M_HSS_TIMER)
+
+#define S_HSS_CTL    4
+#define V_HSS_CTL(x) ((x) << S_HSS_CTL)
+#define F_HSS_CTL    V_HSS_CTL(1U)
+
+#define S_LPI_ACTIVE    3
+#define V_LPI_ACTIVE(x) ((x) << S_LPI_ACTIVE)
+#define F_LPI_ACTIVE    V_LPI_ACTIVE(1U)
+
+#define S_LPI_TXHOLD    2
+#define V_LPI_TXHOLD(x) ((x) << S_LPI_TXHOLD)
+#define F_LPI_TXHOLD    V_LPI_TXHOLD(1U)
+
+#define S_LPI_REQ    1
+#define V_LPI_REQ(x) ((x) << S_LPI_REQ)
+#define F_LPI_REQ    V_LPI_REQ(1U)
+
+#define S_EEE_TX_RESET    0
+#define V_EEE_TX_RESET(x) ((x) << S_EEE_TX_RESET)
+#define F_EEE_TX_RESET    V_EEE_TX_RESET(1U)
+
+#define A_MAC_PORT_EEE_RX_CTL 0x938
+
+#define S_LPI_IND    1
+#define V_LPI_IND(x) ((x) << S_LPI_IND)
+#define F_LPI_IND    V_LPI_IND(1U)
+
+#define S_EEE_RX_RESET    0
+#define V_EEE_RX_RESET(x) ((x) << S_EEE_RX_RESET)
+#define F_EEE_RX_RESET    V_EEE_RX_RESET(1U)
+
+#define A_MAC_PORT_EEE_TX_10G_SLEEP_TIMER 0x93c
+#define A_MAC_PORT_EEE_TX_10G_QUIET_TIMER 0x940
+#define A_MAC_PORT_EEE_TX_10G_WAKE_TIMER 0x944
+#define A_MAC_PORT_EEE_TX_1G_SLEEP_TIMER 0x948
+#define A_MAC_PORT_EEE_TX_1G_QUIET_TIMER 0x94c
+#define A_MAC_PORT_EEE_TX_1G_REFRESH_TIMER 0x950
+#define A_MAC_PORT_EEE_RX_10G_QUIET_TIMER 0x954
+#define A_MAC_PORT_EEE_RX_10G_WAKE_TIMER 0x958
+#define A_MAC_PORT_EEE_RX_10G_WF_TIMER 0x95c
+#define A_MAC_PORT_EEE_RX_1G_QUIET_TIMER 0x960
+#define A_MAC_PORT_EEE_RX_1G_WAKE_TIMER 0x964
+#define A_MAC_PORT_EEE_WF_COUNT 0x968
+
+#define S_WAKE_CNT_CLR    16
+#define V_WAKE_CNT_CLR(x) ((x) << S_WAKE_CNT_CLR)
+#define F_WAKE_CNT_CLR    V_WAKE_CNT_CLR(1U)
+
+#define S_WAKE_CNT    0
+#define M_WAKE_CNT    0xffffU
+#define V_WAKE_CNT(x) ((x) << S_WAKE_CNT)
+#define G_WAKE_CNT(x) (((x) >> S_WAKE_CNT) & M_WAKE_CNT)
+
+#define A_MAC_PORT_PTP_TIMER_RD0_LO 0x96c
+#define A_MAC_PORT_PTP_TIMER_RD0_HI 0x970
+#define A_MAC_PORT_PTP_TIMER_RD1_LO 0x974
+#define A_MAC_PORT_PTP_TIMER_RD1_HI 0x978
+#define A_MAC_PORT_PTP_TIMER_WR_LO 0x97c
+#define A_MAC_PORT_PTP_TIMER_WR_HI 0x980
+#define A_MAC_PORT_PTP_TIMER_OFFSET_0 0x984
+#define A_MAC_PORT_PTP_TIMER_OFFSET_1 0x988
+#define A_MAC_PORT_PTP_TIMER_OFFSET_2 0x98c
+
+#define S_PTP_OFFSET    0
+#define M_PTP_OFFSET    0xffU
+#define V_PTP_OFFSET(x) ((x) << S_PTP_OFFSET)
+#define G_PTP_OFFSET(x) (((x) >> S_PTP_OFFSET) & M_PTP_OFFSET)
+
+#define A_MAC_PORT_PTP_SUM_LO 0x990
+#define A_MAC_PORT_PTP_SUM_HI 0x994
+#define A_MAC_PORT_PTP_TIMER_INCR0 0x998
+
+#define S_Y    16
+#define M_Y    0xffffU
+#define V_Y(x) ((x) << S_Y)
+#define G_Y(x) (((x) >> S_Y) & M_Y)
+
+#define S_X    0
+#define M_X    0xffffU
+#define V_X(x) ((x) << S_X)
+#define G_X(x) (((x) >> S_X) & M_X)
+
+#define A_MAC_PORT_PTP_TIMER_INCR1 0x99c
+
+#define S_Y_TICK    16
+#define M_Y_TICK    0xffffU
+#define V_Y_TICK(x) ((x) << S_Y_TICK)
+#define G_Y_TICK(x) (((x) >> S_Y_TICK) & M_Y_TICK)
+
+#define S_X_TICK    0
+#define M_X_TICK    0xffffU
+#define V_X_TICK(x) ((x) << S_X_TICK)
+#define G_X_TICK(x) (((x) >> S_X_TICK) & M_X_TICK)
+
+#define A_MAC_PORT_PTP_DRIFT_ADJUST_COUNT 0x9a0
+#define A_MAC_PORT_PTP_OFFSET_ADJUST_FINE 0x9a4
+
+#define S_B    16
+#define M_B    0xffffU
+#define V_B(x) ((x) << S_B)
+#define G_B(x) (((x) >> S_B) & M_B)
+
+#define S_A    0
+#define M_A    0xffffU
+#define V_A(x) ((x) << S_A)
+#define G_A(x) (((x) >> S_A) & M_A)
+
+#define A_MAC_PORT_PTP_OFFSET_ADJUST_TOTAL 0x9a8
+#define A_MAC_PORT_PTP_CFG 0x9ac
+
+#define S_FRZ    18
+#define V_FRZ(x) ((x) << S_FRZ)
+#define F_FRZ    V_FRZ(1U)
+
+#define S_OFFSER_ADJUST_SIGN    17
+#define V_OFFSER_ADJUST_SIGN(x) ((x) << S_OFFSER_ADJUST_SIGN)
+#define F_OFFSER_ADJUST_SIGN    V_OFFSER_ADJUST_SIGN(1U)
+
+#define S_ADD_OFFSET    16
+#define V_ADD_OFFSET(x) ((x) << S_ADD_OFFSET)
+#define F_ADD_OFFSET    V_ADD_OFFSET(1U)
+
+#define S_CYCLE1    8
+#define M_CYCLE1    0xffU
+#define V_CYCLE1(x) ((x) << S_CYCLE1)
+#define G_CYCLE1(x) (((x) >> S_CYCLE1) & M_CYCLE1)
+
+#define S_Q    0
+#define M_Q    0xffU
+#define V_Q(x) ((x) << S_Q)
+#define G_Q(x) (((x) >> S_Q) & M_Q)
+
+#define A_MAC_PORT_MTIP_REVISION 0xa00
+
+#define S_CUSTREV    16
+#define M_CUSTREV    0xffffU
+#define V_CUSTREV(x) ((x) << S_CUSTREV)
+#define G_CUSTREV(x) (((x) >> S_CUSTREV) & M_CUSTREV)
+
+#define S_VER    8
+#define M_VER    0xffU
+#define V_VER(x) ((x) << S_VER)
+#define G_VER(x) (((x) >> S_VER) & M_VER)
+
+#define S_MTIP_REV    0
+#define M_MTIP_REV    0xffU
+#define V_MTIP_REV(x) ((x) << S_MTIP_REV)
+#define G_MTIP_REV(x) (((x) >> S_MTIP_REV) & M_MTIP_REV)
+
+#define A_MAC_PORT_MTIP_SCRATCH 0xa04
+#define A_MAC_PORT_MTIP_COMMAND_CONFIG 0xa08
+
+#define S_TX_FLUSH_ENABLE    22
+#define V_TX_FLUSH_ENABLE(x) ((x) << S_TX_FLUSH_ENABLE)
+#define F_TX_FLUSH_ENABLE    V_TX_FLUSH_ENABLE(1U)
+
+#define S_RX_SFD_ANY    21
+#define V_RX_SFD_ANY(x) ((x) << S_RX_SFD_ANY)
+#define F_RX_SFD_ANY    V_RX_SFD_ANY(1U)
+
+#define S_PAUSE_PFC_COMP    20
+#define V_PAUSE_PFC_COMP(x) ((x) << S_PAUSE_PFC_COMP)
+#define F_PAUSE_PFC_COMP    V_PAUSE_PFC_COMP(1U)
+
+#define S_PFC_MODE    19
+#define V_PFC_MODE(x) ((x) << S_PFC_MODE)
+#define F_PFC_MODE    V_PFC_MODE(1U)
+
+#define S_RS_COL_CNT_EXT    18
+#define V_RS_COL_CNT_EXT(x) ((x) << S_RS_COL_CNT_EXT)
+#define F_RS_COL_CNT_EXT    V_RS_COL_CNT_EXT(1U)
+
+#define S_NO_LGTH_CHECK    17
+#define V_NO_LGTH_CHECK(x) ((x) << S_NO_LGTH_CHECK)
+#define F_NO_LGTH_CHECK    V_NO_LGTH_CHECK(1U)
+
+#define S_SEND_IDLE    16
+#define V_SEND_IDLE(x) ((x) << S_SEND_IDLE)
+#define F_SEND_IDLE    V_SEND_IDLE(1U)
+
+#define S_PHY_TXENA    15
+#define V_PHY_TXENA(x) ((x) << S_PHY_TXENA)
+#define F_PHY_TXENA    V_PHY_TXENA(1U)
+
+#define S_RX_ERR_DISC    14
+#define V_RX_ERR_DISC(x) ((x) << S_RX_ERR_DISC)
+#define F_RX_ERR_DISC    V_RX_ERR_DISC(1U)
+
+#define S_CMD_FRAME_ENA    13
+#define V_CMD_FRAME_ENA(x) ((x) << S_CMD_FRAME_ENA)
+#define F_CMD_FRAME_ENA    V_CMD_FRAME_ENA(1U)
+
+#define S_SW_RESET    12
+#define V_SW_RESET(x) ((x) << S_SW_RESET)
+#define F_SW_RESET    V_SW_RESET(1U)
+
+#define S_TX_PAD_EN    11
+#define V_TX_PAD_EN(x) ((x) << S_TX_PAD_EN)
+#define F_TX_PAD_EN    V_TX_PAD_EN(1U)
+
+#define S_PHY_LOOPBACK_EN    10
+#define V_PHY_LOOPBACK_EN(x) ((x) << S_PHY_LOOPBACK_EN)
+#define F_PHY_LOOPBACK_EN    V_PHY_LOOPBACK_EN(1U)
+
+#define S_TX_ADDR_INS    9
+#define V_TX_ADDR_INS(x) ((x) << S_TX_ADDR_INS)
+#define F_TX_ADDR_INS    V_TX_ADDR_INS(1U)
+
+#define S_PAUSE_IGNORE    8
+#define V_PAUSE_IGNORE(x) ((x) << S_PAUSE_IGNORE)
+#define F_PAUSE_IGNORE    V_PAUSE_IGNORE(1U)
+
+#define S_PAUSE_FWD    7
+#define V_PAUSE_FWD(x) ((x) << S_PAUSE_FWD)
+#define F_PAUSE_FWD    V_PAUSE_FWD(1U)
+
+#define S_CRC_FWD    6
+#define V_CRC_FWD(x) ((x) << S_CRC_FWD)
+#define F_CRC_FWD    V_CRC_FWD(1U)
+
+#define S_PAD_EN    5
+#define V_PAD_EN(x) ((x) << S_PAD_EN)
+#define F_PAD_EN    V_PAD_EN(1U)
+
+#define S_PROMIS_EN    4
+#define V_PROMIS_EN(x) ((x) << S_PROMIS_EN)
+#define F_PROMIS_EN    V_PROMIS_EN(1U)
+
+#define S_WAN_MODE    3
+#define V_WAN_MODE(x) ((x) << S_WAN_MODE)
+#define F_WAN_MODE    V_WAN_MODE(1U)
+
+#define S_RX_ENA    1
+#define V_RX_ENA(x) ((x) << S_RX_ENA)
+#define F_RX_ENA    V_RX_ENA(1U)
+
+#define S_TX_ENA    0
+#define V_TX_ENA(x) ((x) << S_TX_ENA)
+#define F_TX_ENA    V_TX_ENA(1U)
+
+#define A_MAC_PORT_MTIP_MAC_ADDR_0 0xa0c
+#define A_MAC_PORT_MTIP_MAC_ADDR_1 0xa10
+
+#define S_MACADDRHI    0
+#define M_MACADDRHI    0xffffU
+#define V_MACADDRHI(x) ((x) << S_MACADDRHI)
+#define G_MACADDRHI(x) (((x) >> S_MACADDRHI) & M_MACADDRHI)
+
+#define A_MAC_PORT_MTIP_FRM_LENGTH 0xa14
+
+#define S_LEN    0
+#define M_LEN    0xffffU
+#define V_LEN(x) ((x) << S_LEN)
+#define G_LEN(x) (((x) >> S_LEN) & M_LEN)
+
+#define A_MAC_PORT_MTIP_RX_FIFO_SECTIONS 0xa1c
+
+#define S_AVAIL    16
+#define M_AVAIL    0xffffU
+#define V_AVAIL(x) ((x) << S_AVAIL)
+#define G_AVAIL(x) (((x) >> S_AVAIL) & M_AVAIL)
+
+#define S_EMPTY    0
+#define M_EMPTY    0xffffU
+#define V_EMPTY(x) ((x) << S_EMPTY)
+#define G_EMPTY(x) (((x) >> S_EMPTY) & M_EMPTY)
+
+#define A_MAC_PORT_MTIP_TX_FIFO_SECTIONS 0xa20
+#define A_MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E 0xa24
+
+#define S_ALMSTFULL    16
+#define M_ALMSTFULL    0xffffU
+#define V_ALMSTFULL(x) ((x) << S_ALMSTFULL)
+#define G_ALMSTFULL(x) (((x) >> S_ALMSTFULL) & M_ALMSTFULL)
+
+#define S_ALMSTEMPTY    0
+#define M_ALMSTEMPTY    0xffffU
+#define V_ALMSTEMPTY(x) ((x) << S_ALMSTEMPTY)
+#define G_ALMSTEMPTY(x) (((x) >> S_ALMSTEMPTY) & M_ALMSTEMPTY)
+
+#define A_MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E 0xa28
+#define A_MAC_PORT_MTIP_HASHTABLE_LOAD 0xa2c
+
+#define S_ENABLE_MCAST_RX    8
+#define V_ENABLE_MCAST_RX(x) ((x) << S_ENABLE_MCAST_RX)
+#define F_ENABLE_MCAST_RX    V_ENABLE_MCAST_RX(1U)
+
+#define S_HASHTABLE_ADDR    0
+#define M_HASHTABLE_ADDR    0x3fU
+#define V_HASHTABLE_ADDR(x) ((x) << S_HASHTABLE_ADDR)
+#define G_HASHTABLE_ADDR(x) (((x) >> S_HASHTABLE_ADDR) & M_HASHTABLE_ADDR)
+
+#define A_MAC_PORT_MTIP_MAC_STATUS 0xa40
+
+#define S_TS_AVAIL    3
+#define V_TS_AVAIL(x) ((x) << S_TS_AVAIL)
+#define F_TS_AVAIL    V_TS_AVAIL(1U)
+
+#define S_PHY_LOS    2
+#define V_PHY_LOS(x) ((x) << S_PHY_LOS)
+#define F_PHY_LOS    V_PHY_LOS(1U)
+
+#define S_RX_REM_FAULT    1
+#define V_RX_REM_FAULT(x) ((x) << S_RX_REM_FAULT)
+#define F_RX_REM_FAULT    V_RX_REM_FAULT(1U)
+
+#define S_RX_LOC_FAULT    0
+#define V_RX_LOC_FAULT(x) ((x) << S_RX_LOC_FAULT)
+#define F_RX_LOC_FAULT    V_RX_LOC_FAULT(1U)
+
+#define A_MAC_PORT_MTIP_TX_IPG_LENGTH 0xa44
+
+#define S_IPG    0
+#define M_IPG    0x7fU
+#define V_IPG(x) ((x) << S_IPG)
+#define G_IPG(x) (((x) >> S_IPG) & M_IPG)
+
+#define A_MAC_PORT_MTIP_MAC_CREDIT_TRIGGER 0xa48
+
+#define S_RXFIFORST    0
+#define V_RXFIFORST(x) ((x) << S_RXFIFORST)
+#define F_RXFIFORST    V_RXFIFORST(1U)
+
+#define A_MAC_PORT_MTIP_INIT_CREDIT 0xa4c
+
+#define S_MACCRDRST    0
+#define M_MACCRDRST    0xffU
+#define V_MACCRDRST(x) ((x) << S_MACCRDRST)
+#define G_MACCRDRST(x) (((x) >> S_MACCRDRST) & M_MACCRDRST)
+
+#define A_MAC_PORT_MTIP_CURRENT_CREDIT 0xa50
+
+#define S_INITCREDIT    0
+#define M_INITCREDIT    0xffU
+#define V_INITCREDIT(x) ((x) << S_INITCREDIT)
+#define G_INITCREDIT(x) (((x) >> S_INITCREDIT) & M_INITCREDIT)
+
+#define A_MAC_PORT_RX_PAUSE_STATUS 0xa74
+
+#define S_STATUS    0
+#define M_STATUS    0xffU
+#define V_STATUS(x) ((x) << S_STATUS)
+#define G_STATUS(x) (((x) >> S_STATUS) & M_STATUS)
+
+#define A_MAC_PORT_MTIP_TS_TIMESTAMP 0xa7c
+#define A_MAC_PORT_AFRAMESTRANSMITTEDOK 0xa80
+#define A_MAC_PORT_AFRAMESTRANSMITTEDOKHI 0xa84
+#define A_MAC_PORT_AFRAMESRECEIVEDOK 0xa88
+#define A_MAC_PORT_AFRAMESRECEIVEDOKHI 0xa8c
+#define A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS 0xa90
+#define A_MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI 0xa94
+#define A_MAC_PORT_AALIGNMENTERRORS 0xa98
+#define A_MAC_PORT_AALIGNMENTERRORSHI 0xa9c
+#define A_MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED 0xaa0
+#define A_MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI 0xaa4
+#define A_MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED 0xaa8
+#define A_MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI 0xaac
+#define A_MAC_PORT_AFRAMETOOLONGERRORS 0xab0
+#define A_MAC_PORT_AFRAMETOOLONGERRORSHI 0xab4
+#define A_MAC_PORT_AINRANGELENGTHERRORS 0xab8
+#define A_MAC_PORT_AINRANGELENGTHERRORSHI 0xabc
+#define A_MAC_PORT_VLANTRANSMITTEDOK 0xac0
+#define A_MAC_PORT_VLANTRANSMITTEDOKHI 0xac4
+#define A_MAC_PORT_VLANRECEIVEDOK 0xac8
+#define A_MAC_PORT_VLANRECEIVEDOKHI 0xacc
+#define A_MAC_PORT_AOCTETSTRANSMITTEDOK 0xad0
+#define A_MAC_PORT_AOCTETSTRANSMITTEDOKHI 0xad4
+#define A_MAC_PORT_AOCTETSRECEIVEDOK 0xad8
+#define A_MAC_PORT_AOCTETSRECEIVEDOKHI 0xadc
+#define A_MAC_PORT_IFINUCASTPKTS 0xae0
+#define A_MAC_PORT_IFINUCASTPKTSHI 0xae4
+#define A_MAC_PORT_IFINMULTICASTPKTS 0xae8
+#define A_MAC_PORT_IFINMULTICASTPKTSHI 0xaec
+#define A_MAC_PORT_IFINBROADCASTPKTS 0xaf0
+#define A_MAC_PORT_IFINBROADCASTPKTSHI 0xaf4
+#define A_MAC_PORT_IFOUTERRORS 0xaf8
+#define A_MAC_PORT_IFOUTERRORSHI 0xafc
+#define A_MAC_PORT_IFOUTUCASTPKTS 0xb08
+#define A_MAC_PORT_IFOUTUCASTPKTSHI 0xb0c
+#define A_MAC_PORT_IFOUTMULTICASTPKTS 0xb10
+#define A_MAC_PORT_IFOUTMULTICASTPKTSHI 0xb14
+#define A_MAC_PORT_IFOUTBROADCASTPKTS 0xb18
+#define A_MAC_PORT_IFOUTBROADCASTPKTSHI 0xb1c
+#define A_MAC_PORT_ETHERSTATSDROPEVENTS 0xb20
+#define A_MAC_PORT_ETHERSTATSDROPEVENTSHI 0xb24
+#define A_MAC_PORT_ETHERSTATSOCTETS 0xb28
+#define A_MAC_PORT_ETHERSTATSOCTETSHI 0xb2c
+#define A_MAC_PORT_ETHERSTATSPKTS 0xb30
+#define A_MAC_PORT_ETHERSTATSPKTSHI 0xb34
+#define A_MAC_PORT_ETHERSTATSUNDERSIZEPKTS 0xb38
+#define A_MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI 0xb3c
+#define A_MAC_PORT_ETHERSTATSPKTS64OCTETS 0xb40
+#define A_MAC_PORT_ETHERSTATSPKTS64OCTETSHI 0xb44
+#define A_MAC_PORT_ETHERSTATSPKTS65TO127OCTETS 0xb48
+#define A_MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI 0xb4c
+#define A_MAC_PORT_ETHERSTATSPKTS128TO255OCTETS 0xb50
+#define A_MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI 0xb54
+#define A_MAC_PORT_ETHERSTATSPKTS256TO511OCTETS 0xb58
+#define A_MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI 0xb5c
+#define A_MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS 0xb60
+#define A_MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI 0xb64
+#define A_MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS 0xb68
+#define A_MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI 0xb6c
+#define A_MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS 0xb70
+#define A_MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI 0xb74
+#define A_MAC_PORT_ETHERSTATSOVERSIZEPKTS 0xb78
+#define A_MAC_PORT_ETHERSTATSOVERSIZEPKTSHI 0xb7c
+#define A_MAC_PORT_ETHERSTATSJABBERS 0xb80
+#define A_MAC_PORT_ETHERSTATSJABBERSHI 0xb84
+#define A_MAC_PORT_ETHERSTATSFRAGMENTS 0xb88
+#define A_MAC_PORT_ETHERSTATSFRAGMENTSHI 0xb8c
+#define A_MAC_PORT_IFINERRORS 0xb90
+#define A_MAC_PORT_IFINERRORSHI 0xb94
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0 0xb98
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI 0xb9c
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1 0xba0
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI 0xba4
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2 0xba8
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI 0xbac
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3 0xbb0
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI 0xbb4
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4 0xbb8
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI 0xbbc
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5 0xbc0
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI 0xbc4
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6 0xbc8
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI 0xbcc
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7 0xbd0
+#define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI 0xbd4
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0 0xbd8
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI 0xbdc
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1 0xbe0
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI 0xbe4
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2 0xbe8
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI 0xbec
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3 0xbf0
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI 0xbf4
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4 0xbf8
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI 0xbfc
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5 0xc00
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI 0xc04
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6 0xc08
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI 0xc0c
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7 0xc10
+#define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI 0xc14
+#define A_MAC_PORT_AMACCONTROLFRAMESTRANSMITTED 0xc18
+#define A_MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI 0xc1c
+#define A_MAC_PORT_AMACCONTROLFRAMESRECEIVED 0xc20
+#define A_MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI 0xc24
+#define A_MAC_PORT_MTIP_SGMII_CONTROL 0xd00
+
+#define S_RESET    15
+#define V_RESET(x) ((x) << S_RESET)
+#define F_RESET    V_RESET(1U)
+
+#define S_LOOPBACK    14
+#define V_LOOPBACK(x) ((x) << S_LOOPBACK)
+#define F_LOOPBACK    V_LOOPBACK(1U)
+
+#define S_SPPEDSEL1    13
+#define V_SPPEDSEL1(x) ((x) << S_SPPEDSEL1)
+#define F_SPPEDSEL1    V_SPPEDSEL1(1U)
+
+#define S_AN_EN    12
+#define V_AN_EN(x) ((x) << S_AN_EN)
+#define F_AN_EN    V_AN_EN(1U)
+
+#define S_PWRDWN    11
+#define V_PWRDWN(x) ((x) << S_PWRDWN)
+#define F_PWRDWN    V_PWRDWN(1U)
+
+#define S_ISOLATE    10
+#define V_ISOLATE(x) ((x) << S_ISOLATE)
+#define F_ISOLATE    V_ISOLATE(1U)
+
+#define S_AN_RESTART    9
+#define V_AN_RESTART(x) ((x) << S_AN_RESTART)
+#define F_AN_RESTART    V_AN_RESTART(1U)
+
+#define S_DPLX    8
+#define V_DPLX(x) ((x) << S_DPLX)
+#define F_DPLX    V_DPLX(1U)
+
+#define S_COLLISIONTEST    7
+#define V_COLLISIONTEST(x) ((x) << S_COLLISIONTEST)
+#define F_COLLISIONTEST    V_COLLISIONTEST(1U)
+
+#define S_SPEEDSEL0    6
+#define V_SPEEDSEL0(x) ((x) << S_SPEEDSEL0)
+#define F_SPEEDSEL0    V_SPEEDSEL0(1U)
+
+#define A_MAC_PORT_MTIP_SGMII_STATUS 0xd04
+
+#define S_100BASET4    15
+#define V_100BASET4(x) ((x) << S_100BASET4)
+#define F_100BASET4    V_100BASET4(1U)
+
+#define S_100BASEXFULLDPLX    14
+#define V_100BASEXFULLDPLX(x) ((x) << S_100BASEXFULLDPLX)
+#define F_100BASEXFULLDPLX    V_100BASEXFULLDPLX(1U)
+
+#define S_100BASEXHALFDPLX    13
+#define V_100BASEXHALFDPLX(x) ((x) << S_100BASEXHALFDPLX)
+#define F_100BASEXHALFDPLX    V_100BASEXHALFDPLX(1U)
+
+#define S_10MBPSFULLDPLX    12
+#define V_10MBPSFULLDPLX(x) ((x) << S_10MBPSFULLDPLX)
+#define F_10MBPSFULLDPLX    V_10MBPSFULLDPLX(1U)
+
+#define S_10MBPSHALFDPLX    11
+#define V_10MBPSHALFDPLX(x) ((x) << S_10MBPSHALFDPLX)
+#define F_10MBPSHALFDPLX    V_10MBPSHALFDPLX(1U)
+
+#define S_100BASET2FULLDPLX    10
+#define V_100BASET2FULLDPLX(x) ((x) << S_100BASET2FULLDPLX)
+#define F_100BASET2FULLDPLX    V_100BASET2FULLDPLX(1U)
+
+#define S_100BASET2HALFDPLX    9
+#define V_100BASET2HALFDPLX(x) ((x) << S_100BASET2HALFDPLX)
+#define F_100BASET2HALFDPLX    V_100BASET2HALFDPLX(1U)
+
+#define S_EXTDSTATUS    8
+#define V_EXTDSTATUS(x) ((x) << S_EXTDSTATUS)
+#define F_EXTDSTATUS    V_EXTDSTATUS(1U)
+
+#define S_SGMII_REM_FAULT    4
+#define V_SGMII_REM_FAULT(x) ((x) << S_SGMII_REM_FAULT)
+#define F_SGMII_REM_FAULT    V_SGMII_REM_FAULT(1U)
+
+#define S_JABBERDETECT    1
+#define V_JABBERDETECT(x) ((x) << S_JABBERDETECT)
+#define F_JABBERDETECT    V_JABBERDETECT(1U)
+
+#define S_EXTDCAPABILITY    0
+#define V_EXTDCAPABILITY(x) ((x) << S_EXTDCAPABILITY)
+#define F_EXTDCAPABILITY    V_EXTDCAPABILITY(1U)
+
+#define A_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0 0xd08
+#define A_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1 0xd0c
+#define A_MAC_PORT_MTIP_SGMII_DEV_ABILITY 0xd10
+
+#define S_RF2    13
+#define V_RF2(x) ((x) << S_RF2)
+#define F_RF2    V_RF2(1U)
+
+#define S_RF1    12
+#define V_RF1(x) ((x) << S_RF1)
+#define F_RF1    V_RF1(1U)
+
+#define S_PS2    8
+#define V_PS2(x) ((x) << S_PS2)
+#define F_PS2    V_PS2(1U)
+
+#define S_PS1    7
+#define V_PS1(x) ((x) << S_PS1)
+#define F_PS1    V_PS1(1U)
+
+#define S_HD    6
+#define V_HD(x) ((x) << S_HD)
+#define F_HD    V_HD(1U)
+
+#define S_FD    5
+#define V_FD(x) ((x) << S_FD)
+#define F_FD    V_FD(1U)
+
+#define A_MAC_PORT_MTIP_SGMII_PARTNER_ABILITY 0xd14
+
+#define S_CULINKSTATUS    15
+#define V_CULINKSTATUS(x) ((x) << S_CULINKSTATUS)
+#define F_CULINKSTATUS    V_CULINKSTATUS(1U)
+
+#define S_CUDPLXSTATUS    12
+#define V_CUDPLXSTATUS(x) ((x) << S_CUDPLXSTATUS)
+#define F_CUDPLXSTATUS    V_CUDPLXSTATUS(1U)
+
+#define S_CUSPEED    10
+#define M_CUSPEED    0x3U
+#define V_CUSPEED(x) ((x) << S_CUSPEED)
+#define G_CUSPEED(x) (((x) >> S_CUSPEED) & M_CUSPEED)
+
+#define A_MAC_PORT_MTIP_SGMII_AN_EXPANSION 0xd18
+
+#define S_PGRCVD    1
+#define V_PGRCVD(x) ((x) << S_PGRCVD)
+#define F_PGRCVD    V_PGRCVD(1U)
+
+#define S_REALTIMEPGRCVD    0
+#define V_REALTIMEPGRCVD(x) ((x) << S_REALTIMEPGRCVD)
+#define F_REALTIMEPGRCVD    V_REALTIMEPGRCVD(1U)
+
+#define A_MAC_PORT_MTIP_SGMII_DEVICE_NP 0xd1c
+#define A_MAC_PORT_MTIP_SGMII_PARTNER_NP 0xd20
+#define A_MAC_PORT_MTIP_SGMII_EXTENDED_STATUS 0xd3c
+#define A_MAC_PORT_MTIP_SGMII_LINK_TIMER_LO 0xd48
+
+#define S_COUNT_LO    0
+#define M_COUNT_LO    0xffffU
+#define V_COUNT_LO(x) ((x) << S_COUNT_LO)
+#define G_COUNT_LO(x) (((x) >> S_COUNT_LO) & M_COUNT_LO)
+
+#define A_MAC_PORT_MTIP_SGMII_LINK_TIMER_HI 0xd4c
+
+#define S_COUNT_HI    0
+#define M_COUNT_HI    0x1fU
+#define V_COUNT_HI(x) ((x) << S_COUNT_HI)
+#define G_COUNT_HI(x) (((x) >> S_COUNT_HI) & M_COUNT_HI)
+
+#define A_MAC_PORT_MTIP_SGMII_IF_MODE 0xd50
+
+#define S_SGMII_PCS_ENABLE    5
+#define V_SGMII_PCS_ENABLE(x) ((x) << S_SGMII_PCS_ENABLE)
+#define F_SGMII_PCS_ENABLE    V_SGMII_PCS_ENABLE(1U)
+
+#define S_SGMII_HDUPLEX    4
+#define V_SGMII_HDUPLEX(x) ((x) << S_SGMII_HDUPLEX)
+#define F_SGMII_HDUPLEX    V_SGMII_HDUPLEX(1U)
+
+#define S_SGMII_SPEED    2
+#define M_SGMII_SPEED    0x3U
+#define V_SGMII_SPEED(x) ((x) << S_SGMII_SPEED)
+#define G_SGMII_SPEED(x) (((x) >> S_SGMII_SPEED) & M_SGMII_SPEED)
+
+#define S_USE_SGMII_AN    1
+#define V_USE_SGMII_AN(x) ((x) << S_USE_SGMII_AN)
+#define F_USE_SGMII_AN    V_USE_SGMII_AN(1U)
+
+#define S_SGMII_ENA    0
+#define V_SGMII_ENA(x) ((x) << S_SGMII_ENA)
+#define F_SGMII_ENA    V_SGMII_ENA(1U)
+
+#define A_MAC_PORT_MTIP_ACT_CTL_SEG 0x1200
+
+#define S_ACTIVE    0
+#define M_ACTIVE    0x3fU
+#define V_ACTIVE(x) ((x) << S_ACTIVE)
+#define G_ACTIVE(x) (((x) >> S_ACTIVE) & M_ACTIVE)
+
+#define A_MAC_PORT_MTIP_MODE_CTL_SEG 0x1204
+
+#define S_MODE_CTL    0
+#define M_MODE_CTL    0x3U
+#define V_MODE_CTL(x) ((x) << S_MODE_CTL)
+#define G_MODE_CTL(x) (((x) >> S_MODE_CTL) & M_MODE_CTL)
+
+#define A_MAC_PORT_MTIP_TXCLK_CTL_SEG 0x1208
+
+#define S_TXCLK_CTL    0
+#define M_TXCLK_CTL    0xffffU
+#define V_TXCLK_CTL(x) ((x) << S_TXCLK_CTL)
+#define G_TXCLK_CTL(x) (((x) >> S_TXCLK_CTL) & M_TXCLK_CTL)
+
+#define A_MAC_PORT_MTIP_TX_PRMBL_CTL_SEG 0x120c
+#define A_MAC_PORT_MTIP_WAN_RS_COL_CNT 0x1220
+
+#define S_COL_CNT    0
+#define M_COL_CNT    0xffffU
+#define V_COL_CNT(x) ((x) << S_COL_CNT)
+#define G_COL_CNT(x) (((x) >> S_COL_CNT) & M_COL_CNT)
+
+#define A_MAC_PORT_MTIP_VL_INTVL 0x1240
+
+#define S_VL_INTVL    1
+#define V_VL_INTVL(x) ((x) << S_VL_INTVL)
+#define F_VL_INTVL    V_VL_INTVL(1U)
+
+#define A_MAC_PORT_MTIP_MDIO_CFG_STATUS 0x1600
+
+#define S_CLK_DIV    7
+#define M_CLK_DIV    0x1ffU
+#define V_CLK_DIV(x) ((x) << S_CLK_DIV)
+#define G_CLK_DIV(x) (((x) >> S_CLK_DIV) & M_CLK_DIV)
+
+#define S_CL45_EN    6
+#define V_CL45_EN(x) ((x) << S_CL45_EN)
+#define F_CL45_EN    V_CL45_EN(1U)
+
+#define S_DISABLE_PREAMBLE    5
+#define V_DISABLE_PREAMBLE(x) ((x) << S_DISABLE_PREAMBLE)
+#define F_DISABLE_PREAMBLE    V_DISABLE_PREAMBLE(1U)
+
+#define S_MDIO_HOLD_TIME    2
+#define M_MDIO_HOLD_TIME    0x7U
+#define V_MDIO_HOLD_TIME(x) ((x) << S_MDIO_HOLD_TIME)
+#define G_MDIO_HOLD_TIME(x) (((x) >> S_MDIO_HOLD_TIME) & M_MDIO_HOLD_TIME)
+
+#define S_MDIO_READ_ERR    1
+#define V_MDIO_READ_ERR(x) ((x) << S_MDIO_READ_ERR)
+#define F_MDIO_READ_ERR    V_MDIO_READ_ERR(1U)
+
+#define S_MDIO_BUSY    0
+#define V_MDIO_BUSY(x) ((x) << S_MDIO_BUSY)
+#define F_MDIO_BUSY    V_MDIO_BUSY(1U)
+
+#define A_MAC_PORT_MTIP_MDIO_COMMAND 0x1604
+
+#define S_MDIO_CMD_READ    15
+#define V_MDIO_CMD_READ(x) ((x) << S_MDIO_CMD_READ)
+#define F_MDIO_CMD_READ    V_MDIO_CMD_READ(1U)
+
+#define S_READ_INCR    14
+#define V_READ_INCR(x) ((x) << S_READ_INCR)
+#define F_READ_INCR    V_READ_INCR(1U)
+
+#define S_PORT_ADDR    5
+#define M_PORT_ADDR    0x1fU
+#define V_PORT_ADDR(x) ((x) << S_PORT_ADDR)
+#define G_PORT_ADDR(x) (((x) >> S_PORT_ADDR) & M_PORT_ADDR)
+
+#define S_DEV_ADDR    0
+#define M_DEV_ADDR    0x1fU
+#define V_DEV_ADDR(x) ((x) << S_DEV_ADDR)
+#define G_DEV_ADDR(x) (((x) >> S_DEV_ADDR) & M_DEV_ADDR)
+
+#define A_MAC_PORT_MTIP_MDIO_DATA 0x1608
+
+#define S_READBUSY    31
+#define V_READBUSY(x) ((x) << S_READBUSY)
+#define F_READBUSY    V_READBUSY(1U)
+
+#define S_DATA_WORD    0
+#define M_DATA_WORD    0xffffU
+#define V_DATA_WORD(x) ((x) << S_DATA_WORD)
+#define G_DATA_WORD(x) (((x) >> S_DATA_WORD) & M_DATA_WORD)
+
+#define A_MAC_PORT_MTIP_MDIO_REGADDR 0x160c
+
+#define S_MDIO_ADDR    0
+#define M_MDIO_ADDR    0xffffU
+#define V_MDIO_ADDR(x) ((x) << S_MDIO_ADDR)
+#define G_MDIO_ADDR(x) (((x) >> S_MDIO_ADDR) & M_MDIO_ADDR)
+
+#define A_MAC_PORT_MTIP_VLAN_TPID_0 0x1a00
+
+#define S_VLANTAG    0
+#define M_VLANTAG    0xffffU
+#define V_VLANTAG(x) ((x) << S_VLANTAG)
+#define G_VLANTAG(x) (((x) >> S_VLANTAG) & M_VLANTAG)
+
+#define A_MAC_PORT_MTIP_VLAN_TPID_1 0x1a04
+#define A_MAC_PORT_MTIP_VLAN_TPID_2 0x1a08
+#define A_MAC_PORT_MTIP_VLAN_TPID_3 0x1a0c
+#define A_MAC_PORT_MTIP_VLAN_TPID_4 0x1a10
+#define A_MAC_PORT_MTIP_VLAN_TPID_5 0x1a14
+#define A_MAC_PORT_MTIP_VLAN_TPID_6 0x1a18
+#define A_MAC_PORT_MTIP_VLAN_TPID_7 0x1a1c
+#define A_MAC_PORT_MTIP_PCS_CTL 0x1e00
+
+#define S_PCS_LPBK    14
+#define V_PCS_LPBK(x) ((x) << S_PCS_LPBK)
+#define F_PCS_LPBK    V_PCS_LPBK(1U)
+
+#define S_SPEED_SEL1    13
+#define V_SPEED_SEL1(x) ((x) << S_SPEED_SEL1)
+#define F_SPEED_SEL1    V_SPEED_SEL1(1U)
+
+#define S_LP_MODE    11
+#define V_LP_MODE(x) ((x) << S_LP_MODE)
+#define F_LP_MODE    V_LP_MODE(1U)
+
+#define S_SPEED_SEL0    6
+#define V_SPEED_SEL0(x) ((x) << S_SPEED_SEL0)
+#define F_SPEED_SEL0    V_SPEED_SEL0(1U)
+
+#define S_PCS_SPEED    2
+#define M_PCS_SPEED    0xfU
+#define V_PCS_SPEED(x) ((x) << S_PCS_SPEED)
+#define G_PCS_SPEED(x) (((x) >> S_PCS_SPEED) & M_PCS_SPEED)
+
+#define A_MAC_PORT_MTIP_PCS_STATUS1 0x1e04
+
+#define S_FAULTDET    7
+#define V_FAULTDET(x) ((x) << S_FAULTDET)
+#define F_FAULTDET    V_FAULTDET(1U)
+
+#define S_RX_LINK_STATUS    2
+#define V_RX_LINK_STATUS(x) ((x) << S_RX_LINK_STATUS)
+#define F_RX_LINK_STATUS    V_RX_LINK_STATUS(1U)
+
+#define S_LOPWRABL    1
+#define V_LOPWRABL(x) ((x) << S_LOPWRABL)
+#define F_LOPWRABL    V_LOPWRABL(1U)
+
+#define A_MAC_PORT_MTIP_PCS_DEVICE_ID0 0x1e08
+
+#define S_DEVICE_ID0    0
+#define M_DEVICE_ID0    0xffffU
+#define V_DEVICE_ID0(x) ((x) << S_DEVICE_ID0)
+#define G_DEVICE_ID0(x) (((x) >> S_DEVICE_ID0) & M_DEVICE_ID0)
+
+#define A_MAC_PORT_MTIP_PCS_DEVICE_ID1 0x1e0c
+
+#define S_DEVICE_ID1    0
+#define M_DEVICE_ID1    0xffffU
+#define V_DEVICE_ID1(x) ((x) << S_DEVICE_ID1)
+#define G_DEVICE_ID1(x) (((x) >> S_DEVICE_ID1) & M_DEVICE_ID1)
+
+#define A_MAC_PORT_MTIP_PCS_SPEED_ABILITY 0x1e10
+
+#define S_100G    8
+#define V_100G(x) ((x) << S_100G)
+#define F_100G    V_100G(1U)
+
+#define S_40G    7
+#define V_40G(x) ((x) << S_40G)
+#define F_40G    V_40G(1U)
+
+#define S_10BASE_TL    1
+#define V_10BASE_TL(x) ((x) << S_10BASE_TL)
+#define F_10BASE_TL    V_10BASE_TL(1U)
+
+#define S_10G    0
+#define V_10G(x) ((x) << S_10G)
+#define F_10G    V_10G(1U)
+
+#define A_MAC_PORT_MTIP_PCS_DEVICE_PKG1 0x1e14
+
+#define S_TC_PRESENT    6
+#define V_TC_PRESENT(x) ((x) << S_TC_PRESENT)
+#define F_TC_PRESENT    V_TC_PRESENT(1U)
+
+#define S_DTEXS    5
+#define V_DTEXS(x) ((x) << S_DTEXS)
+#define F_DTEXS    V_DTEXS(1U)
+
+#define S_PHYXS    4
+#define V_PHYXS(x) ((x) << S_PHYXS)
+#define F_PHYXS    V_PHYXS(1U)
+
+#define S_PCS    3
+#define V_PCS(x) ((x) << S_PCS)
+#define F_PCS    V_PCS(1U)
+
+#define S_WIS    2
+#define V_WIS(x) ((x) << S_WIS)
+#define F_WIS    V_WIS(1U)
+
+#define S_PMD_PMA    1
+#define V_PMD_PMA(x) ((x) << S_PMD_PMA)
+#define F_PMD_PMA    V_PMD_PMA(1U)
+
+#define S_CL22    0
+#define V_CL22(x) ((x) << S_CL22)
+#define F_CL22    V_CL22(1U)
+
+#define A_MAC_PORT_MTIP_PCS_DEVICE_PKG2 0x1e18
+
+#define S_VENDDEV2    15
+#define V_VENDDEV2(x) ((x) << S_VENDDEV2)
+#define F_VENDDEV2    V_VENDDEV2(1U)
+
+#define S_VENDDEV1    14
+#define V_VENDDEV1(x) ((x) << S_VENDDEV1)
+#define F_VENDDEV1    V_VENDDEV1(1U)
+
+#define S_CL22EXT    13
+#define V_CL22EXT(x) ((x) << S_CL22EXT)
+#define F_CL22EXT    V_CL22EXT(1U)
+
+#define A_MAC_PORT_MTIP_PCS_CTL2 0x1e1c
+
+#define S_PCSTYPE    0
+#define M_PCSTYPE    0x7U
+#define V_PCSTYPE(x) ((x) << S_PCSTYPE)
+#define G_PCSTYPE(x) (((x) >> S_PCSTYPE) & M_PCSTYPE)
+
+#define A_MAC_PORT_MTIP_PCS_STATUS2 0x1e20
+
+#define S_PCS_STAT2_DEVICE    15
+#define V_PCS_STAT2_DEVICE(x) ((x) << S_PCS_STAT2_DEVICE)
+#define F_PCS_STAT2_DEVICE    V_PCS_STAT2_DEVICE(1U)
+
+#define S_TXFAULT    7
+#define V_TXFAULT(x) ((x) << S_TXFAULT)
+#define F_TXFAULT    V_TXFAULT(1U)
+
+#define S_RXFAULT    6
+#define V_RXFAULT(x) ((x) << S_RXFAULT)
+#define F_RXFAULT    V_RXFAULT(1U)
+
+#define S_100BASE_R    5
+#define V_100BASE_R(x) ((x) << S_100BASE_R)
+#define F_100BASE_R    V_100BASE_R(1U)
+
+#define S_40GBASE_R    4
+#define V_40GBASE_R(x) ((x) << S_40GBASE_R)
+#define F_40GBASE_R    V_40GBASE_R(1U)
+
+#define S_10GBASE_T    3
+#define V_10GBASE_T(x) ((x) << S_10GBASE_T)
+#define F_10GBASE_T    V_10GBASE_T(1U)
+
+#define S_10GBASE_W    2
+#define V_10GBASE_W(x) ((x) << S_10GBASE_W)
+#define F_10GBASE_W    V_10GBASE_W(1U)
+
+#define S_10GBASE_X    1
+#define V_10GBASE_X(x) ((x) << S_10GBASE_X)
+#define F_10GBASE_X    V_10GBASE_X(1U)
+
+#define S_10GBASE_R    0
+#define V_10GBASE_R(x) ((x) << S_10GBASE_R)
+#define F_10GBASE_R    V_10GBASE_R(1U)
+
+#define A_MAC_PORT_MTIP_PCS_PKG_ID0 0x1e38
+
+#define S_PKG_ID0    0
+#define M_PKG_ID0    0xffffU
+#define V_PKG_ID0(x) ((x) << S_PKG_ID0)
+#define G_PKG_ID0(x) (((x) >> S_PKG_ID0) & M_PKG_ID0)
+
+#define A_MAC_PORT_MTIP_PCS_PKG_ID1 0x1e3c
+
+#define S_PKG_ID1    0
+#define M_PKG_ID1    0xffffU
+#define V_PKG_ID1(x) ((x) << S_PKG_ID1)
+#define G_PKG_ID1(x) (((x) >> S_PKG_ID1) & M_PKG_ID1)
+
+#define A_MAC_PORT_MTIP_PCS_BASER_STATUS1 0x1e80
+
+#define S_RXLINKSTATUS    12
+#define V_RXLINKSTATUS(x) ((x) << S_RXLINKSTATUS)
+#define F_RXLINKSTATUS    V_RXLINKSTATUS(1U)
+
+#define S_RESEREVED    4
+#define M_RESEREVED    0xffU
+#define V_RESEREVED(x) ((x) << S_RESEREVED)
+#define G_RESEREVED(x) (((x) >> S_RESEREVED) & M_RESEREVED)
+
+#define S_10GPRBS9    3
+#define V_10GPRBS9(x) ((x) << S_10GPRBS9)
+#define F_10GPRBS9    V_10GPRBS9(1U)
+
+#define S_10GPRBS31    2
+#define V_10GPRBS31(x) ((x) << S_10GPRBS31)
+#define F_10GPRBS31    V_10GPRBS31(1U)
+
+#define S_HIBER    1
+#define V_HIBER(x) ((x) << S_HIBER)
+#define F_HIBER    V_HIBER(1U)
+
+#define S_BLOCKLOCK    0
+#define V_BLOCKLOCK(x) ((x) << S_BLOCKLOCK)
+#define F_BLOCKLOCK    V_BLOCKLOCK(1U)
+
+#define A_MAC_PORT_MTIP_PCS_BASER_STATUS2 0x1e84
+
+#define S_BLOCKLOCKLL    15
+#define V_BLOCKLOCKLL(x) ((x) << S_BLOCKLOCKLL)
+#define F_BLOCKLOCKLL    V_BLOCKLOCKLL(1U)
+
+#define S_HIBERLH    14
+#define V_HIBERLH(x) ((x) << S_HIBERLH)
+#define F_HIBERLH    V_HIBERLH(1U)
+
+#define S_HIBERCOUNT    8
+#define M_HIBERCOUNT    0x3fU
+#define V_HIBERCOUNT(x) ((x) << S_HIBERCOUNT)
+#define G_HIBERCOUNT(x) (((x) >> S_HIBERCOUNT) & M_HIBERCOUNT)
+
+#define S_ERRBLKCNT    0
+#define M_ERRBLKCNT    0xffU
+#define V_ERRBLKCNT(x) ((x) << S_ERRBLKCNT)
+#define G_ERRBLKCNT(x) (((x) >> S_ERRBLKCNT) & M_ERRBLKCNT)
+
+#define A_MAC_PORT_MTIP_10GBASER_SEED_A 0x1e88
+
+#define S_SEEDA    0
+#define M_SEEDA    0xffffU
+#define V_SEEDA(x) ((x) << S_SEEDA)
+#define G_SEEDA(x) (((x) >> S_SEEDA) & M_SEEDA)
+
+#define A_MAC_PORT_MTIP_10GBASER_SEED_A1 0x1e8c
+
+#define S_SEEDA1    0
+#define M_SEEDA1    0xffffU
+#define V_SEEDA1(x) ((x) << S_SEEDA1)
+#define G_SEEDA1(x) (((x) >> S_SEEDA1) & M_SEEDA1)
+
+#define A_MAC_PORT_MTIP_10GBASER_SEED_A2 0x1e90
+
+#define S_SEEDA2    0
+#define M_SEEDA2    0xffffU
+#define V_SEEDA2(x) ((x) << S_SEEDA2)
+#define G_SEEDA2(x) (((x) >> S_SEEDA2) & M_SEEDA2)
+
+#define A_MAC_PORT_MTIP_10GBASER_SEED_A3 0x1e94
+
+#define S_SEEDA3    0
+#define M_SEEDA3    0x3ffU
+#define V_SEEDA3(x) ((x) << S_SEEDA3)
+#define G_SEEDA3(x) (((x) >> S_SEEDA3) & M_SEEDA3)
+
+#define A_MAC_PORT_MTIP_10GBASER_SEED_B 0x1e98
+
+#define S_SEEDB    0
+#define M_SEEDB    0xffffU
+#define V_SEEDB(x) ((x) << S_SEEDB)
+#define G_SEEDB(x) (((x) >> S_SEEDB) & M_SEEDB)
+
+#define A_MAC_PORT_MTIP_10GBASER_SEED_B1 0x1e9c
+
+#define S_SEEDB1    0
+#define M_SEEDB1    0xffffU
+#define V_SEEDB1(x) ((x) << S_SEEDB1)
+#define G_SEEDB1(x) (((x) >> S_SEEDB1) & M_SEEDB1)
+
+#define A_MAC_PORT_MTIP_10GBASER_SEED_B2 0x1ea0
+
+#define S_SEEDB2    0
+#define M_SEEDB2    0xffffU
+#define V_SEEDB2(x) ((x) << S_SEEDB2)
+#define G_SEEDB2(x) (((x) >> S_SEEDB2) & M_SEEDB2)
+
+#define A_MAC_PORT_MTIP_10GBASER_SEED_B3 0x1ea4
+
+#define S_SEEDB3    0
+#define M_SEEDB3    0x3ffU
+#define V_SEEDB3(x) ((x) << S_SEEDB3)
+#define G_SEEDB3(x) (((x) >> S_SEEDB3) & M_SEEDB3)
+
+#define A_MAC_PORT_MTIP_BASER_TEST_CTRL 0x1ea8
+
+#define S_TXPRBS9    6
+#define V_TXPRBS9(x) ((x) << S_TXPRBS9)
+#define F_TXPRBS9    V_TXPRBS9(1U)
+
+#define S_RXPRBS31    5
+#define V_RXPRBS31(x) ((x) << S_RXPRBS31)
+#define F_RXPRBS31    V_RXPRBS31(1U)
+
+#define S_TXPRBS31    4
+#define V_TXPRBS31(x) ((x) << S_TXPRBS31)
+#define F_TXPRBS31    V_TXPRBS31(1U)
+
+#define S_TXTESTPATEN    3
+#define V_TXTESTPATEN(x) ((x) << S_TXTESTPATEN)
+#define F_TXTESTPATEN    V_TXTESTPATEN(1U)
+
+#define S_RXTESTPATEN    2
+#define V_RXTESTPATEN(x) ((x) << S_RXTESTPATEN)
+#define F_RXTESTPATEN    V_RXTESTPATEN(1U)
+
+#define S_TESTPATSEL    1
+#define V_TESTPATSEL(x) ((x) << S_TESTPATSEL)
+#define F_TESTPATSEL    V_TESTPATSEL(1U)
+
+#define S_DATAPATSEL    0
+#define V_DATAPATSEL(x) ((x) << S_DATAPATSEL)
+#define F_DATAPATSEL    V_DATAPATSEL(1U)
+
+#define A_MAC_PORT_MTIP_BASER_TEST_ERR_CNT 0x1eac
+
+#define S_TEST_ERR_CNT    0
+#define M_TEST_ERR_CNT    0xffffU
+#define V_TEST_ERR_CNT(x) ((x) << S_TEST_ERR_CNT)
+#define G_TEST_ERR_CNT(x) (((x) >> S_TEST_ERR_CNT) & M_TEST_ERR_CNT)
+
+#define A_MAC_PORT_MTIP_BER_HIGH_ORDER_CNT 0x1eb0
+
+#define S_BER_CNT_HI    0
+#define M_BER_CNT_HI    0xffffU
+#define V_BER_CNT_HI(x) ((x) << S_BER_CNT_HI)
+#define G_BER_CNT_HI(x) (((x) >> S_BER_CNT_HI) & M_BER_CNT_HI)
+
+#define A_MAC_PORT_MTIP_BLK_HIGH_ORDER_CNT 0x1eb4
+
+#define S_HICOUNTPRSNT    15
+#define V_HICOUNTPRSNT(x) ((x) << S_HICOUNTPRSNT)
+#define F_HICOUNTPRSNT    V_HICOUNTPRSNT(1U)
+
+#define S_BLOCK_CNT_HI    0
+#define M_BLOCK_CNT_HI    0x3fffU
+#define V_BLOCK_CNT_HI(x) ((x) << S_BLOCK_CNT_HI)
+#define G_BLOCK_CNT_HI(x) (((x) >> S_BLOCK_CNT_HI) & M_BLOCK_CNT_HI)
+
+#define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS1 0x1ec8
+
+#define S_ALIGNSTATUS    12
+#define V_ALIGNSTATUS(x) ((x) << S_ALIGNSTATUS)
+#define F_ALIGNSTATUS    V_ALIGNSTATUS(1U)
+
+#define S_LANE7    7
+#define V_LANE7(x) ((x) << S_LANE7)
+#define F_LANE7    V_LANE7(1U)
+
+#define S_LANE6    6
+#define V_LANE6(x) ((x) << S_LANE6)
+#define F_LANE6    V_LANE6(1U)
+
+#define S_LANE5    5
+#define V_LANE5(x) ((x) << S_LANE5)
+#define F_LANE5    V_LANE5(1U)
+
+#define S_LANE4    4
+#define V_LANE4(x) ((x) << S_LANE4)
+#define F_LANE4    V_LANE4(1U)
+
+#define S_LANE3    3
+#define V_LANE3(x) ((x) << S_LANE3)
+#define F_LANE3    V_LANE3(1U)
+
+#define S_LANE2    2
+#define V_LANE2(x) ((x) << S_LANE2)
+#define F_LANE2    V_LANE2(1U)
+
+#define S_LANE1    1
+#define V_LANE1(x) ((x) << S_LANE1)
+#define F_LANE1    V_LANE1(1U)
+
+#define S_LANE0    0
+#define V_LANE0(x) ((x) << S_LANE0)
+#define F_LANE0    V_LANE0(1U)
+
+#define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS2 0x1ecc
+
+#define S_LANE19    11
+#define V_LANE19(x) ((x) << S_LANE19)
+#define F_LANE19    V_LANE19(1U)
+
+#define S_LANE18    10
+#define V_LANE18(x) ((x) << S_LANE18)
+#define F_LANE18    V_LANE18(1U)
+
+#define S_LANE17    9
+#define V_LANE17(x) ((x) << S_LANE17)
+#define F_LANE17    V_LANE17(1U)
+
+#define S_LANE16    8
+#define V_LANE16(x) ((x) << S_LANE16)
+#define F_LANE16    V_LANE16(1U)
+
+#define S_LANE15    7
+#define V_LANE15(x) ((x) << S_LANE15)
+#define F_LANE15    V_LANE15(1U)
+
+#define S_LANE14    6
+#define V_LANE14(x) ((x) << S_LANE14)
+#define F_LANE14    V_LANE14(1U)
+
+#define S_LANE13    5
+#define V_LANE13(x) ((x) << S_LANE13)
+#define F_LANE13    V_LANE13(1U)
+
+#define S_LANE12    4
+#define V_LANE12(x) ((x) << S_LANE12)
+#define F_LANE12    V_LANE12(1U)
+
+#define S_LANE11    3
+#define V_LANE11(x) ((x) << S_LANE11)
+#define F_LANE11    V_LANE11(1U)
+
+#define S_LANE10    2
+#define V_LANE10(x) ((x) << S_LANE10)
+#define F_LANE10    V_LANE10(1U)
+
+#define S_LANE9    1
+#define V_LANE9(x) ((x) << S_LANE9)
+#define F_LANE9    V_LANE9(1U)
+
+#define S_LANE8    0
+#define V_LANE8(x) ((x) << S_LANE8)
+#define F_LANE8    V_LANE8(1U)
+
+#define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS3 0x1ed0
+
+#define S_AMLOCK7    7
+#define V_AMLOCK7(x) ((x) << S_AMLOCK7)
+#define F_AMLOCK7    V_AMLOCK7(1U)
+
+#define S_AMLOCK6    6
+#define V_AMLOCK6(x) ((x) << S_AMLOCK6)
+#define F_AMLOCK6    V_AMLOCK6(1U)
+
+#define S_AMLOCK5    5
+#define V_AMLOCK5(x) ((x) << S_AMLOCK5)
+#define F_AMLOCK5    V_AMLOCK5(1U)
+
+#define S_AMLOCK4    4
+#define V_AMLOCK4(x) ((x) << S_AMLOCK4)
+#define F_AMLOCK4    V_AMLOCK4(1U)
+
+#define S_AMLOCK3    3
+#define V_AMLOCK3(x) ((x) << S_AMLOCK3)
+#define F_AMLOCK3    V_AMLOCK3(1U)
+
+#define S_AMLOCK2    2
+#define V_AMLOCK2(x) ((x) << S_AMLOCK2)
+#define F_AMLOCK2    V_AMLOCK2(1U)
+
+#define S_AMLOCK1    1
+#define V_AMLOCK1(x) ((x) << S_AMLOCK1)
+#define F_AMLOCK1    V_AMLOCK1(1U)
+
+#define S_AMLOCK0    0
+#define V_AMLOCK0(x) ((x) << S_AMLOCK0)
+#define F_AMLOCK0    V_AMLOCK0(1U)
+
+#define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS4 0x1ed4
+
+#define S_AMLOCK19    11
+#define V_AMLOCK19(x) ((x) << S_AMLOCK19)
+#define F_AMLOCK19    V_AMLOCK19(1U)
+
+#define S_AMLOCK18    10
+#define V_AMLOCK18(x) ((x) << S_AMLOCK18)
+#define F_AMLOCK18    V_AMLOCK18(1U)
+
+#define S_AMLOCK17    9
+#define V_AMLOCK17(x) ((x) << S_AMLOCK17)
+#define F_AMLOCK17    V_AMLOCK17(1U)
+
+#define S_AMLOCK16    8
+#define V_AMLOCK16(x) ((x) << S_AMLOCK16)
+#define F_AMLOCK16    V_AMLOCK16(1U)
+
+#define S_AMLOCK15    7
+#define V_AMLOCK15(x) ((x) << S_AMLOCK15)
+#define F_AMLOCK15    V_AMLOCK15(1U)
+
+#define S_AMLOCK14    6
+#define V_AMLOCK14(x) ((x) << S_AMLOCK14)
+#define F_AMLOCK14    V_AMLOCK14(1U)
+
+#define S_AMLOCK13    5
+#define V_AMLOCK13(x) ((x) << S_AMLOCK13)
+#define F_AMLOCK13    V_AMLOCK13(1U)
+
+#define S_AMLOCK12    4
+#define V_AMLOCK12(x) ((x) << S_AMLOCK12)
+#define F_AMLOCK12    V_AMLOCK12(1U)
+
+#define S_AMLOCK11    3
+#define V_AMLOCK11(x) ((x) << S_AMLOCK11)
+#define F_AMLOCK11    V_AMLOCK11(1U)
+
+#define S_AMLOCK10    2
+#define V_AMLOCK10(x) ((x) << S_AMLOCK10)
+#define F_AMLOCK10    V_AMLOCK10(1U)
+
+#define S_AMLOCK9    1
+#define V_AMLOCK9(x) ((x) << S_AMLOCK9)
+#define F_AMLOCK9    V_AMLOCK9(1U)
+
+#define S_AMLOCK8    0
+#define V_AMLOCK8(x) ((x) << S_AMLOCK8)
+#define F_AMLOCK8    V_AMLOCK8(1U)
+
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_0 0x1f68
+
+#define S_BIPERR_CNT    0
+#define M_BIPERR_CNT    0xffffU
+#define V_BIPERR_CNT(x) ((x) << S_BIPERR_CNT)
+#define G_BIPERR_CNT(x) (((x) >> S_BIPERR_CNT) & M_BIPERR_CNT)
+
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_1 0x1f6c
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_2 0x1f70
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_3 0x1f74
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_4 0x1f78
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_5 0x1f7c
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_6 0x1f80
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_7 0x1f84
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_8 0x1f88
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_9 0x1f8c
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_10 0x1f90
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_11 0x1f94
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_12 0x1f98
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_13 0x1f9c
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_14 0x1fa0
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_15 0x1fa4
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_16 0x1fa8
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_17 0x1fac
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_18 0x1fb0
+#define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_19 0x1fb4
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_0 0x1fb8
+
+#define S_MAP    0
+#define M_MAP    0x1fU
+#define V_MAP(x) ((x) << S_MAP)
+#define G_MAP(x) (((x) >> S_MAP) & M_MAP)
+
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_1 0x1fbc
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_2 0x1fc0
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_3 0x1fc4
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_4 0x1fc8
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_5 0x1fcc
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_6 0x1fd0
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_7 0x1fd4
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_8 0x1fd8
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_9 0x1fdc
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_10 0x1fe0
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_11 0x1fe4
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_12 0x1fe8
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_13 0x1fec
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_14 0x1ff0
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_15 0x1ff4
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_16 0x1ff8
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_17 0x1ffc
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_18 0x2000
+#define A_MAC_PORT_MTIP_PCS_LANE_MAP_19 0x2004
+#define A_MAC_PORT_BEAN_CTL 0x2200
+
+#define S_AN_RESET    15
+#define V_AN_RESET(x) ((x) << S_AN_RESET)
+#define F_AN_RESET    V_AN_RESET(1U)
+
+#define S_EXT_NXP_CTRL    13
+#define V_EXT_NXP_CTRL(x) ((x) << S_EXT_NXP_CTRL)
+#define F_EXT_NXP_CTRL    V_EXT_NXP_CTRL(1U)
+
+#define S_BEAN_EN    12
+#define V_BEAN_EN(x) ((x) << S_BEAN_EN)
+#define F_BEAN_EN    V_BEAN_EN(1U)
+
+#define S_RESTART_BEAN    9
+#define V_RESTART_BEAN(x) ((x) << S_RESTART_BEAN)
+#define F_RESTART_BEAN    V_RESTART_BEAN(1U)
+
+#define A_MAC_PORT_BEAN_STATUS 0x2204
+
+#define S_PDF    9
+#define V_PDF(x) ((x) << S_PDF)
+#define F_PDF    V_PDF(1U)
+
+#define S_EXT_NXP_STATUS    7
+#define V_EXT_NXP_STATUS(x) ((x) << S_EXT_NXP_STATUS)
+#define F_EXT_NXP_STATUS    V_EXT_NXP_STATUS(1U)
+
+#define S_PAGE_RCVD    6
+#define V_PAGE_RCVD(x) ((x) << S_PAGE_RCVD)
+#define F_PAGE_RCVD    V_PAGE_RCVD(1U)
+
+#define S_BEAN_COMPLETE    5
+#define V_BEAN_COMPLETE(x) ((x) << S_BEAN_COMPLETE)
+#define F_BEAN_COMPLETE    V_BEAN_COMPLETE(1U)
+
+#define S_REM_FAULT_STATUS    4
+#define V_REM_FAULT_STATUS(x) ((x) << S_REM_FAULT_STATUS)
+#define F_REM_FAULT_STATUS    V_REM_FAULT_STATUS(1U)
+
+#define S_BEAN_ABILITY    3
+#define V_BEAN_ABILITY(x) ((x) << S_BEAN_ABILITY)
+#define F_BEAN_ABILITY    V_BEAN_ABILITY(1U)
+
+#define S_LP_BEAN_ABILITY    0
+#define V_LP_BEAN_ABILITY(x) ((x) << S_LP_BEAN_ABILITY)
+#define F_LP_BEAN_ABILITY    V_LP_BEAN_ABILITY(1U)
+
+#define A_MAC_PORT_BEAN_ABILITY_0 0x2208
+
+#define S_NXP    15
+#define V_NXP(x) ((x) << S_NXP)
+#define F_NXP    V_NXP(1U)
+
+#define S_REM_FAULT    13
+#define V_REM_FAULT(x) ((x) << S_REM_FAULT)
+#define F_REM_FAULT    V_REM_FAULT(1U)
+
+#define S_PAUSE_ABILITY    10
+#define M_PAUSE_ABILITY    0x7U
+#define V_PAUSE_ABILITY(x) ((x) << S_PAUSE_ABILITY)
+#define G_PAUSE_ABILITY(x) (((x) >> S_PAUSE_ABILITY) & M_PAUSE_ABILITY)
+
+#define S_ECHO_NONCE    5
+#define M_ECHO_NONCE    0x1fU
+#define V_ECHO_NONCE(x) ((x) << S_ECHO_NONCE)
+#define G_ECHO_NONCE(x) (((x) >> S_ECHO_NONCE) & M_ECHO_NONCE)
+
+#define S_SELECTOR    0
+#define M_SELECTOR    0x1fU
+#define V_SELECTOR(x) ((x) << S_SELECTOR)
+#define G_SELECTOR(x) (((x) >> S_SELECTOR) & M_SELECTOR)
+
+#define A_MAC_PORT_BEAN_ABILITY_1 0x220c
+
+#define S_TECH_ABILITY_1    5
+#define M_TECH_ABILITY_1    0x7ffU
+#define V_TECH_ABILITY_1(x) ((x) << S_TECH_ABILITY_1)
+#define G_TECH_ABILITY_1(x) (((x) >> S_TECH_ABILITY_1) & M_TECH_ABILITY_1)
+
+#define S_TX_NONCE    0
+#define M_TX_NONCE    0x1fU
+#define V_TX_NONCE(x) ((x) << S_TX_NONCE)
+#define G_TX_NONCE(x) (((x) >> S_TX_NONCE) & M_TX_NONCE)
+
+#define A_MAC_PORT_BEAN_ABILITY_2 0x2210
+
+#define S_T5_FEC_ABILITY    14
+#define M_T5_FEC_ABILITY    0x3U
+#define V_T5_FEC_ABILITY(x) ((x) << S_T5_FEC_ABILITY)
+#define G_T5_FEC_ABILITY(x) (((x) >> S_T5_FEC_ABILITY) & M_T5_FEC_ABILITY)
+
+#define S_TECH_ABILITY_2    0
+#define M_TECH_ABILITY_2    0x3fffU
+#define V_TECH_ABILITY_2(x) ((x) << S_TECH_ABILITY_2)
+#define G_TECH_ABILITY_2(x) (((x) >> S_TECH_ABILITY_2) & M_TECH_ABILITY_2)
+
+#define A_MAC_PORT_BEAN_REM_ABILITY_0 0x2214
+#define A_MAC_PORT_BEAN_REM_ABILITY_1 0x2218
+#define A_MAC_PORT_BEAN_REM_ABILITY_2 0x221c
+#define A_MAC_PORT_BEAN_MS_COUNT 0x2220
+
+#define S_MS_COUNT    0
+#define M_MS_COUNT    0xffffU
+#define V_MS_COUNT(x) ((x) << S_MS_COUNT)
+#define G_MS_COUNT(x) (((x) >> S_MS_COUNT) & M_MS_COUNT)
+
+#define A_MAC_PORT_BEAN_XNP_0 0x2224
+
+#define S_XNP    15
+#define V_XNP(x) ((x) << S_XNP)
+#define F_XNP    V_XNP(1U)
+
+#define S_ACKNOWLEDGE    14
+#define V_ACKNOWLEDGE(x) ((x) << S_ACKNOWLEDGE)
+#define F_ACKNOWLEDGE    V_ACKNOWLEDGE(1U)
+
+#define S_MP    13
+#define V_MP(x) ((x) << S_MP)
+#define F_MP    V_MP(1U)
+
+#define S_ACK2    12
+#define V_ACK2(x) ((x) << S_ACK2)
+#define F_ACK2    V_ACK2(1U)
+
+#define S_MU    0
+#define M_MU    0x7ffU
+#define V_MU(x) ((x) << S_MU)
+#define G_MU(x) (((x) >> S_MU) & M_MU)
+
+#define A_MAC_PORT_BEAN_XNP_1 0x2228
+
+#define S_UNFORMATED    0
+#define M_UNFORMATED    0xffffU
+#define V_UNFORMATED(x) ((x) << S_UNFORMATED)
+#define G_UNFORMATED(x) (((x) >> S_UNFORMATED) & M_UNFORMATED)
+
+#define A_MAC_PORT_BEAN_XNP_2 0x222c
+#define A_MAC_PORT_LP_BEAN_XNP_0 0x2230
+#define A_MAC_PORT_LP_BEAN_XNP_1 0x2234
+#define A_MAC_PORT_LP_BEAN_XNP_2 0x2238
+#define A_MAC_PORT_BEAN_ETH_STATUS 0x223c
+
+#define S_100GCR10    8
+#define V_100GCR10(x) ((x) << S_100GCR10)
+#define F_100GCR10    V_100GCR10(1U)
+
+#define S_40GCR4    6
+#define V_40GCR4(x) ((x) << S_40GCR4)
+#define F_40GCR4    V_40GCR4(1U)
+
+#define S_40GKR4    5
+#define V_40GKR4(x) ((x) << S_40GKR4)
+#define F_40GKR4    V_40GKR4(1U)
+
+#define S_FEC    4
+#define V_FEC(x) ((x) << S_FEC)
+#define F_FEC    V_FEC(1U)
+
+#define S_10GKR    3
+#define V_10GKR(x) ((x) << S_10GKR)
+#define F_10GKR    V_10GKR(1U)
+
+#define S_10GKX4    2
+#define V_10GKX4(x) ((x) << S_10GKX4)
+#define F_10GKX4    V_10GKX4(1U)
+
+#define S_1GKX    1
+#define V_1GKX(x) ((x) << S_1GKX)
+#define F_1GKX    V_1GKX(1U)
+
+#define A_MAC_PORT_BEAN_CTL_LANE1 0x2240
+#define A_MAC_PORT_BEAN_STATUS_LANE1 0x2244
+#define A_MAC_PORT_BEAN_ABILITY_0_LANE1 0x2248
+#define A_MAC_PORT_BEAN_ABILITY_1_LANE1 0x224c
+#define A_MAC_PORT_BEAN_ABILITY_2_LANE1 0x2250
+#define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE1 0x2254
+#define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE1 0x2258
+#define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE1 0x225c
+#define A_MAC_PORT_BEAN_MS_COUNT_LANE1 0x2260
+#define A_MAC_PORT_BEAN_XNP_0_LANE1 0x2264
+#define A_MAC_PORT_BEAN_XNP_1_LANE1 0x2268
+#define A_MAC_PORT_BEAN_XNP_2_LANE1 0x226c
+#define A_MAC_PORT_LP_BEAN_XNP_0_LANE1 0x2270
+#define A_MAC_PORT_LP_BEAN_XNP_1_LANE1 0x2274
+#define A_MAC_PORT_LP_BEAN_XNP_2_LANE1 0x2278
+#define A_MAC_PORT_BEAN_ETH_STATUS_LANE1 0x227c
+#define A_MAC_PORT_BEAN_CTL_LANE2 0x2280
+#define A_MAC_PORT_BEAN_STATUS_LANE2 0x2284
+#define A_MAC_PORT_BEAN_ABILITY_0_LANE2 0x2288
+#define A_MAC_PORT_BEAN_ABILITY_1_LANE2 0x228c
+#define A_MAC_PORT_BEAN_ABILITY_2_LANE2 0x2290
+#define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE2 0x2294
+#define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE2 0x2298
+#define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE2 0x229c
+#define A_MAC_PORT_BEAN_MS_COUNT_LANE2 0x22a0
+#define A_MAC_PORT_BEAN_XNP_0_LANE2 0x22a4
+#define A_MAC_PORT_BEAN_XNP_1_LANE2 0x22a8
+#define A_MAC_PORT_BEAN_XNP_2_LANE2 0x22ac
+#define A_MAC_PORT_LP_BEAN_XNP_0_LANE2 0x22b0
+#define A_MAC_PORT_LP_BEAN_XNP_1_LANE2 0x22b4
+#define A_MAC_PORT_LP_BEAN_XNP_2_LANE2 0x22b8
+#define A_MAC_PORT_BEAN_ETH_STATUS_LANE2 0x22bc
+#define A_MAC_PORT_BEAN_CTL_LANE3 0x22c0
+#define A_MAC_PORT_BEAN_STATUS_LANE3 0x22c4
+#define A_MAC_PORT_BEAN_ABILITY_0_LANE3 0x22c8
+#define A_MAC_PORT_BEAN_ABILITY_1_LANE3 0x22cc
+#define A_MAC_PORT_BEAN_ABILITY_2_LANE3 0x22d0
+#define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE3 0x22d4
+#define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE3 0x22d8
+#define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE3 0x22dc
+#define A_MAC_PORT_BEAN_MS_COUNT_LANE3 0x22e0
+#define A_MAC_PORT_BEAN_XNP_0_LANE3 0x22e4
+#define A_MAC_PORT_BEAN_XNP_1_LANE3 0x22e8
+#define A_MAC_PORT_BEAN_XNP_2_LANE3 0x22ec
+#define A_MAC_PORT_LP_BEAN_XNP_0_LANE3 0x22f0
+#define A_MAC_PORT_LP_BEAN_XNP_1_LANE3 0x22f4
+#define A_MAC_PORT_LP_BEAN_XNP_2_LANE3 0x22f8
+#define A_MAC_PORT_BEAN_ETH_STATUS_LANE3 0x22fc
+#define A_MAC_PORT_FEC_KR_CONTROL 0x2600
+
+#define S_ENABLE_TR    1
+#define V_ENABLE_TR(x) ((x) << S_ENABLE_TR)
+#define F_ENABLE_TR    V_ENABLE_TR(1U)
+
+#define S_RESTART_TR    0
+#define V_RESTART_TR(x) ((x) << S_RESTART_TR)
+#define F_RESTART_TR    V_RESTART_TR(1U)
+
+#define A_MAC_PORT_FEC_KR_STATUS 0x2604
+
+#define S_FECKRSIGDET    15
+#define V_FECKRSIGDET(x) ((x) << S_FECKRSIGDET)
+#define F_FECKRSIGDET    V_FECKRSIGDET(1U)
+
+#define S_TRAIN_FAIL    3
+#define V_TRAIN_FAIL(x) ((x) << S_TRAIN_FAIL)
+#define F_TRAIN_FAIL    V_TRAIN_FAIL(1U)
+
+#define S_STARTUP_STATUS    2
+#define V_STARTUP_STATUS(x) ((x) << S_STARTUP_STATUS)
+#define F_STARTUP_STATUS    V_STARTUP_STATUS(1U)
+
+#define S_RX_STATUS    0
+#define V_RX_STATUS(x) ((x) << S_RX_STATUS)
+#define F_RX_STATUS    V_RX_STATUS(1U)
+
+#define A_MAC_PORT_FEC_KR_LP_COEFF 0x2608
+
+#define S_PRESET    13
+#define V_PRESET(x) ((x) << S_PRESET)
+#define F_PRESET    V_PRESET(1U)
+
+#define S_INITIALIZE    12
+#define V_INITIALIZE(x) ((x) << S_INITIALIZE)
+#define F_INITIALIZE    V_INITIALIZE(1U)
+
+#define S_CP1_UPD    4
+#define M_CP1_UPD    0x3U
+#define V_CP1_UPD(x) ((x) << S_CP1_UPD)
+#define G_CP1_UPD(x) (((x) >> S_CP1_UPD) & M_CP1_UPD)
+
+#define S_C0_UPD    2
+#define M_C0_UPD    0x3U
+#define V_C0_UPD(x) ((x) << S_C0_UPD)
+#define G_C0_UPD(x) (((x) >> S_C0_UPD) & M_C0_UPD)
+
+#define S_CN1_UPD    0
+#define M_CN1_UPD    0x3U
+#define V_CN1_UPD(x) ((x) << S_CN1_UPD)
+#define G_CN1_UPD(x) (((x) >> S_CN1_UPD) & M_CN1_UPD)
+
+#define A_MAC_PORT_FEC_KR_LP_STAT 0x260c
+
+#define S_RX_READY    15
+#define V_RX_READY(x) ((x) << S_RX_READY)
+#define F_RX_READY    V_RX_READY(1U)
+
+#define S_CP1_STAT    4
+#define M_CP1_STAT    0x3U
+#define V_CP1_STAT(x) ((x) << S_CP1_STAT)
+#define G_CP1_STAT(x) (((x) >> S_CP1_STAT) & M_CP1_STAT)
+
+#define S_C0_STAT    2
+#define M_C0_STAT    0x3U
+#define V_C0_STAT(x) ((x) << S_C0_STAT)
+#define G_C0_STAT(x) (((x) >> S_C0_STAT) & M_C0_STAT)
+
+#define S_CN1_STAT    0
+#define M_CN1_STAT    0x3U
+#define V_CN1_STAT(x) ((x) << S_CN1_STAT)
+#define G_CN1_STAT(x) (((x) >> S_CN1_STAT) & M_CN1_STAT)
+
+#define A_MAC_PORT_FEC_KR_LD_COEFF 0x2610
+#define A_MAC_PORT_FEC_KR_LD_STAT 0x2614
+#define A_MAC_PORT_FEC_ABILITY 0x2618
+
+#define S_FEC_IND_ABILITY    1
+#define V_FEC_IND_ABILITY(x) ((x) << S_FEC_IND_ABILITY)
+#define F_FEC_IND_ABILITY    V_FEC_IND_ABILITY(1U)
+
+#define S_ABILITY    0
+#define V_ABILITY(x) ((x) << S_ABILITY)
+#define F_ABILITY    V_ABILITY(1U)
+
+#define A_MAC_PORT_FEC_CONTROL 0x261c
+
+#define S_FEC_EN_ERR_IND    1
+#define V_FEC_EN_ERR_IND(x) ((x) << S_FEC_EN_ERR_IND)
+#define F_FEC_EN_ERR_IND    V_FEC_EN_ERR_IND(1U)
+
+#define S_FEC_EN    0
+#define V_FEC_EN(x) ((x) << S_FEC_EN)
+#define F_FEC_EN    V_FEC_EN(1U)
+
+#define A_MAC_PORT_FEC_STATUS 0x2620
+
+#define S_FEC_LOCKED_100    1
+#define V_FEC_LOCKED_100(x) ((x) << S_FEC_LOCKED_100)
+#define F_FEC_LOCKED_100    V_FEC_LOCKED_100(1U)
+
+#define S_FEC_LOCKED    0
+#define V_FEC_LOCKED(x) ((x) << S_FEC_LOCKED)
+#define F_FEC_LOCKED    V_FEC_LOCKED(1U)
+
+#define A_MAC_PORT_FEC_CERR_CNT_0 0x2624
+
+#define S_FEC_CERR_CNT_0    0
+#define M_FEC_CERR_CNT_0    0xffffU
+#define V_FEC_CERR_CNT_0(x) ((x) << S_FEC_CERR_CNT_0)
+#define G_FEC_CERR_CNT_0(x) (((x) >> S_FEC_CERR_CNT_0) & M_FEC_CERR_CNT_0)
+
+#define A_MAC_PORT_FEC_CERR_CNT_1 0x2628
+
+#define S_FEC_CERR_CNT_1    0
+#define M_FEC_CERR_CNT_1    0xffffU
+#define V_FEC_CERR_CNT_1(x) ((x) << S_FEC_CERR_CNT_1)
+#define G_FEC_CERR_CNT_1(x) (((x) >> S_FEC_CERR_CNT_1) & M_FEC_CERR_CNT_1)
+
+#define A_MAC_PORT_FEC_NCERR_CNT_0 0x262c
+
+#define S_FEC_NCERR_CNT_0    0
+#define M_FEC_NCERR_CNT_0    0xffffU
+#define V_FEC_NCERR_CNT_0(x) ((x) << S_FEC_NCERR_CNT_0)
+#define G_FEC_NCERR_CNT_0(x) (((x) >> S_FEC_NCERR_CNT_0) & M_FEC_NCERR_CNT_0)
+
+#define A_MAC_PORT_FEC_NCERR_CNT_1 0x2630
+
+#define S_FEC_NCERR_CNT_1    0
+#define M_FEC_NCERR_CNT_1    0xffffU
+#define V_FEC_NCERR_CNT_1(x) ((x) << S_FEC_NCERR_CNT_1)
+#define G_FEC_NCERR_CNT_1(x) (((x) >> S_FEC_NCERR_CNT_1) & M_FEC_NCERR_CNT_1)
+
+#define A_MAC_PORT_AE_RX_COEF_REQ 0x2a00
+
+#define S_T5_RXREQ_C2    4
+#define M_T5_RXREQ_C2    0x3U
+#define V_T5_RXREQ_C2(x) ((x) << S_T5_RXREQ_C2)
+#define G_T5_RXREQ_C2(x) (((x) >> S_T5_RXREQ_C2) & M_T5_RXREQ_C2)
+
+#define S_T5_RXREQ_C1    2
+#define M_T5_RXREQ_C1    0x3U
+#define V_T5_RXREQ_C1(x) ((x) << S_T5_RXREQ_C1)
+#define G_T5_RXREQ_C1(x) (((x) >> S_T5_RXREQ_C1) & M_T5_RXREQ_C1)
+
+#define S_T5_RXREQ_C0    0
+#define M_T5_RXREQ_C0    0x3U
+#define V_T5_RXREQ_C0(x) ((x) << S_T5_RXREQ_C0)
+#define G_T5_RXREQ_C0(x) (((x) >> S_T5_RXREQ_C0) & M_T5_RXREQ_C0)
+
+#define A_MAC_PORT_AE_RX_COEF_STAT 0x2a04
+
+#define S_T5_AE0_RXSTAT_RDY    15
+#define V_T5_AE0_RXSTAT_RDY(x) ((x) << S_T5_AE0_RXSTAT_RDY)
+#define F_T5_AE0_RXSTAT_RDY    V_T5_AE0_RXSTAT_RDY(1U)
+
+#define S_T5_AE0_RXSTAT_C2    4
+#define M_T5_AE0_RXSTAT_C2    0x3U
+#define V_T5_AE0_RXSTAT_C2(x) ((x) << S_T5_AE0_RXSTAT_C2)
+#define G_T5_AE0_RXSTAT_C2(x) (((x) >> S_T5_AE0_RXSTAT_C2) & M_T5_AE0_RXSTAT_C2)
+
+#define S_T5_AE0_RXSTAT_C1    2
+#define M_T5_AE0_RXSTAT_C1    0x3U
+#define V_T5_AE0_RXSTAT_C1(x) ((x) << S_T5_AE0_RXSTAT_C1)
+#define G_T5_AE0_RXSTAT_C1(x) (((x) >> S_T5_AE0_RXSTAT_C1) & M_T5_AE0_RXSTAT_C1)
+
+#define S_T5_AE0_RXSTAT_C0    0
+#define M_T5_AE0_RXSTAT_C0    0x3U
+#define V_T5_AE0_RXSTAT_C0(x) ((x) << S_T5_AE0_RXSTAT_C0)
+#define G_T5_AE0_RXSTAT_C0(x) (((x) >> S_T5_AE0_RXSTAT_C0) & M_T5_AE0_RXSTAT_C0)
+
+#define A_MAC_PORT_AE_TX_COEF_REQ 0x2a08
+
+#define S_T5_TXREQ_C2    4
+#define M_T5_TXREQ_C2    0x3U
+#define V_T5_TXREQ_C2(x) ((x) << S_T5_TXREQ_C2)
+#define G_T5_TXREQ_C2(x) (((x) >> S_T5_TXREQ_C2) & M_T5_TXREQ_C2)
+
+#define S_T5_TXREQ_C1    2
+#define M_T5_TXREQ_C1    0x3U
+#define V_T5_TXREQ_C1(x) ((x) << S_T5_TXREQ_C1)
+#define G_T5_TXREQ_C1(x) (((x) >> S_T5_TXREQ_C1) & M_T5_TXREQ_C1)
+
+#define S_T5_TXREQ_C0    0
+#define M_T5_TXREQ_C0    0x3U
+#define V_T5_TXREQ_C0(x) ((x) << S_T5_TXREQ_C0)
+#define G_T5_TXREQ_C0(x) (((x) >> S_T5_TXREQ_C0) & M_T5_TXREQ_C0)
+
+#define A_MAC_PORT_AE_TX_COEF_STAT 0x2a0c
+
+#define S_T5_TXSTAT_C2    4
+#define M_T5_TXSTAT_C2    0x3U
+#define V_T5_TXSTAT_C2(x) ((x) << S_T5_TXSTAT_C2)
+#define G_T5_TXSTAT_C2(x) (((x) >> S_T5_TXSTAT_C2) & M_T5_TXSTAT_C2)
+
+#define S_T5_TXSTAT_C1    2
+#define M_T5_TXSTAT_C1    0x3U
+#define V_T5_TXSTAT_C1(x) ((x) << S_T5_TXSTAT_C1)
+#define G_T5_TXSTAT_C1(x) (((x) >> S_T5_TXSTAT_C1) & M_T5_TXSTAT_C1)
+
+#define S_T5_TXSTAT_C0    0
+#define M_T5_TXSTAT_C0    0x3U
+#define V_T5_TXSTAT_C0(x) ((x) << S_T5_TXSTAT_C0)
+#define G_T5_TXSTAT_C0(x) (((x) >> S_T5_TXSTAT_C0) & M_T5_TXSTAT_C0)
+
+#define A_MAC_PORT_AE_REG_MODE 0x2a10
+
+#define S_AET_RSVD    7
+#define V_AET_RSVD(x) ((x) << S_AET_RSVD)
+#define F_AET_RSVD    V_AET_RSVD(1U)
+
+#define S_AET_ENABLE    6
+#define V_AET_ENABLE(x) ((x) << S_AET_ENABLE)
+#define F_AET_ENABLE    V_AET_ENABLE(1U)
+
+#define A_MAC_PORT_AE_PRBS_CTL 0x2a14
+#define A_MAC_PORT_AE_FSM_CTL 0x2a18
+
+#define S_CIN_ENABLE    15
+#define V_CIN_ENABLE(x) ((x) << S_CIN_ENABLE)
+#define F_CIN_ENABLE    V_CIN_ENABLE(1U)
+
+#define A_MAC_PORT_AE_FSM_STATE 0x2a1c
+#define A_MAC_PORT_AE_RX_COEF_REQ_1 0x2a20
+#define A_MAC_PORT_AE_RX_COEF_STAT_1 0x2a24
+
+#define S_T5_AE1_RXSTAT_RDY    15
+#define V_T5_AE1_RXSTAT_RDY(x) ((x) << S_T5_AE1_RXSTAT_RDY)
+#define F_T5_AE1_RXSTAT_RDY    V_T5_AE1_RXSTAT_RDY(1U)
+
+#define S_T5_AE1_RXSTAT_C2    4
+#define M_T5_AE1_RXSTAT_C2    0x3U
+#define V_T5_AE1_RXSTAT_C2(x) ((x) << S_T5_AE1_RXSTAT_C2)
+#define G_T5_AE1_RXSTAT_C2(x) (((x) >> S_T5_AE1_RXSTAT_C2) & M_T5_AE1_RXSTAT_C2)
+
+#define S_T5_AE1_RXSTAT_C1    2
+#define M_T5_AE1_RXSTAT_C1    0x3U
+#define V_T5_AE1_RXSTAT_C1(x) ((x) << S_T5_AE1_RXSTAT_C1)
+#define G_T5_AE1_RXSTAT_C1(x) (((x) >> S_T5_AE1_RXSTAT_C1) & M_T5_AE1_RXSTAT_C1)
+
+#define S_T5_AE1_RXSTAT_C0    0
+#define M_T5_AE1_RXSTAT_C0    0x3U
+#define V_T5_AE1_RXSTAT_C0(x) ((x) << S_T5_AE1_RXSTAT_C0)
+#define G_T5_AE1_RXSTAT_C0(x) (((x) >> S_T5_AE1_RXSTAT_C0) & M_T5_AE1_RXSTAT_C0)
+
+#define A_MAC_PORT_AE_TX_COEF_REQ_1 0x2a28
+#define A_MAC_PORT_AE_TX_COEF_STAT_1 0x2a2c
+#define A_MAC_PORT_AE_REG_MODE_1 0x2a30
+#define A_MAC_PORT_AE_PRBS_CTL_1 0x2a34
+#define A_MAC_PORT_AE_FSM_CTL_1 0x2a38
+#define A_MAC_PORT_AE_FSM_STATE_1 0x2a3c
+#define A_MAC_PORT_AE_RX_COEF_REQ_2 0x2a40
+#define A_MAC_PORT_AE_RX_COEF_STAT_2 0x2a44
+
+#define S_T5_AE2_RXSTAT_RDY    15
+#define V_T5_AE2_RXSTAT_RDY(x) ((x) << S_T5_AE2_RXSTAT_RDY)
+#define F_T5_AE2_RXSTAT_RDY    V_T5_AE2_RXSTAT_RDY(1U)
+
+#define S_T5_AE2_RXSTAT_C2    4
+#define M_T5_AE2_RXSTAT_C2    0x3U
+#define V_T5_AE2_RXSTAT_C2(x) ((x) << S_T5_AE2_RXSTAT_C2)
+#define G_T5_AE2_RXSTAT_C2(x) (((x) >> S_T5_AE2_RXSTAT_C2) & M_T5_AE2_RXSTAT_C2)
+
+#define S_T5_AE2_RXSTAT_C1    2
+#define M_T5_AE2_RXSTAT_C1    0x3U
+#define V_T5_AE2_RXSTAT_C1(x) ((x) << S_T5_AE2_RXSTAT_C1)
+#define G_T5_AE2_RXSTAT_C1(x) (((x) >> S_T5_AE2_RXSTAT_C1) & M_T5_AE2_RXSTAT_C1)
+
+#define S_T5_AE2_RXSTAT_C0    0
+#define M_T5_AE2_RXSTAT_C0    0x3U
+#define V_T5_AE2_RXSTAT_C0(x) ((x) << S_T5_AE2_RXSTAT_C0)
+#define G_T5_AE2_RXSTAT_C0(x) (((x) >> S_T5_AE2_RXSTAT_C0) & M_T5_AE2_RXSTAT_C0)
+
+#define A_MAC_PORT_AE_TX_COEF_REQ_2 0x2a48
+#define A_MAC_PORT_AE_TX_COEF_STAT_2 0x2a4c
+#define A_MAC_PORT_AE_REG_MODE_2 0x2a50
+#define A_MAC_PORT_AE_PRBS_CTL_2 0x2a54
+#define A_MAC_PORT_AE_FSM_CTL_2 0x2a58
+#define A_MAC_PORT_AE_FSM_STATE_2 0x2a5c
+#define A_MAC_PORT_AE_RX_COEF_REQ_3 0x2a60
+#define A_MAC_PORT_AE_RX_COEF_STAT_3 0x2a64
+
+#define S_T5_AE3_RXSTAT_RDY    15
+#define V_T5_AE3_RXSTAT_RDY(x) ((x) << S_T5_AE3_RXSTAT_RDY)
+#define F_T5_AE3_RXSTAT_RDY    V_T5_AE3_RXSTAT_RDY(1U)
+
+#define S_T5_AE3_RXSTAT_C2    4
+#define M_T5_AE3_RXSTAT_C2    0x3U
+#define V_T5_AE3_RXSTAT_C2(x) ((x) << S_T5_AE3_RXSTAT_C2)
+#define G_T5_AE3_RXSTAT_C2(x) (((x) >> S_T5_AE3_RXSTAT_C2) & M_T5_AE3_RXSTAT_C2)
+
+#define S_T5_AE3_RXSTAT_C1    2
+#define M_T5_AE3_RXSTAT_C1    0x3U
+#define V_T5_AE3_RXSTAT_C1(x) ((x) << S_T5_AE3_RXSTAT_C1)
+#define G_T5_AE3_RXSTAT_C1(x) (((x) >> S_T5_AE3_RXSTAT_C1) & M_T5_AE3_RXSTAT_C1)
+
+#define S_T5_AE3_RXSTAT_C0    0
+#define M_T5_AE3_RXSTAT_C0    0x3U
+#define V_T5_AE3_RXSTAT_C0(x) ((x) << S_T5_AE3_RXSTAT_C0)
+#define G_T5_AE3_RXSTAT_C0(x) (((x) >> S_T5_AE3_RXSTAT_C0) & M_T5_AE3_RXSTAT_C0)
+
+#define A_MAC_PORT_AE_TX_COEF_REQ_3 0x2a68
+#define A_MAC_PORT_AE_TX_COEF_STAT_3 0x2a6c
+#define A_MAC_PORT_AE_REG_MODE_3 0x2a70
+#define A_MAC_PORT_AE_PRBS_CTL_3 0x2a74
+#define A_MAC_PORT_AE_FSM_CTL_3 0x2a78
+#define A_MAC_PORT_AE_FSM_STATE_3 0x2a7c
+#define A_MAC_PORT_AE_TX_DIS 0x2a80
+#define A_MAC_PORT_AE_KR_CTRL 0x2a84
+#define A_MAC_PORT_AE_RX_SIGDET 0x2a88
+#define A_MAC_PORT_AE_KR_STATUS 0x2a8c
+#define A_MAC_PORT_AE_TX_DIS_1 0x2a90
+#define A_MAC_PORT_AE_KR_CTRL_1 0x2a94
+#define A_MAC_PORT_AE_RX_SIGDET_1 0x2a98
+#define A_MAC_PORT_AE_KR_STATUS_1 0x2a9c
+#define A_MAC_PORT_AE_TX_DIS_2 0x2aa0
+#define A_MAC_PORT_AE_KR_CTRL_2 0x2aa4
+#define A_MAC_PORT_AE_RX_SIGDET_2 0x2aa8
+#define A_MAC_PORT_AE_KR_STATUS_2 0x2aac
+#define A_MAC_PORT_AE_TX_DIS_3 0x2ab0
+#define A_MAC_PORT_AE_KR_CTRL_3 0x2ab4
+#define A_MAC_PORT_AE_RX_SIGDET_3 0x2ab8
+#define A_MAC_PORT_AE_KR_STATUS_3 0x2abc
+#define A_MAC_PORT_AET_STAGE_CONFIGURATION_0 0x2b00
+
+#define S_EN_HOLD_FAIL    14
+#define V_EN_HOLD_FAIL(x) ((x) << S_EN_HOLD_FAIL)
+#define F_EN_HOLD_FAIL    V_EN_HOLD_FAIL(1U)
+
+#define S_INIT_METH    12
+#define M_INIT_METH    0x3U
+#define V_INIT_METH(x) ((x) << S_INIT_METH)
+#define G_INIT_METH(x) (((x) >> S_INIT_METH) & M_INIT_METH)
+
+#define S_CE_DECS    8
+#define M_CE_DECS    0xfU
+#define V_CE_DECS(x) ((x) << S_CE_DECS)
+#define G_CE_DECS(x) (((x) >> S_CE_DECS) & M_CE_DECS)
+
+#define S_EN_ZFE    7
+#define V_EN_ZFE(x) ((x) << S_EN_ZFE)
+#define F_EN_ZFE    V_EN_ZFE(1U)
+
+#define S_EN_GAIN_TOG    6
+#define V_EN_GAIN_TOG(x) ((x) << S_EN_GAIN_TOG)
+#define F_EN_GAIN_TOG    V_EN_GAIN_TOG(1U)
+
+#define S_EN_AI_C1    5
+#define V_EN_AI_C1(x) ((x) << S_EN_AI_C1)
+#define F_EN_AI_C1    V_EN_AI_C1(1U)
+
+#define S_EN_MAX_ST    4
+#define V_EN_MAX_ST(x) ((x) << S_EN_MAX_ST)
+#define F_EN_MAX_ST    V_EN_MAX_ST(1U)
+
+#define S_EN_H1T_EQ    3
+#define V_EN_H1T_EQ(x) ((x) << S_EN_H1T_EQ)
+#define F_EN_H1T_EQ    V_EN_H1T_EQ(1U)
+
+#define S_H1TEQ_GOAL    0
+#define M_H1TEQ_GOAL    0x7U
+#define V_H1TEQ_GOAL(x) ((x) << S_H1TEQ_GOAL)
+#define G_H1TEQ_GOAL(x) (((x) >> S_H1TEQ_GOAL) & M_H1TEQ_GOAL)
+
+#define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0 0x2b04
+
+#define S_GAIN_TH    6
+#define M_GAIN_TH    0x1fU
+#define V_GAIN_TH(x) ((x) << S_GAIN_TH)
+#define G_GAIN_TH(x) (((x) >> S_GAIN_TH) & M_GAIN_TH)
+
+#define S_EN_SD_TH    5
+#define V_EN_SD_TH(x) ((x) << S_EN_SD_TH)
+#define F_EN_SD_TH    V_EN_SD_TH(1U)
+
+#define S_EN_AMIN_TH    4
+#define V_EN_AMIN_TH(x) ((x) << S_EN_AMIN_TH)
+#define F_EN_AMIN_TH    V_EN_AMIN_TH(1U)
+
+#define S_AMIN_TH    0
+#define M_AMIN_TH    0xfU
+#define V_AMIN_TH(x) ((x) << S_AMIN_TH)
+#define G_AMIN_TH(x) (((x) >> S_AMIN_TH) & M_AMIN_TH)
+
+#define A_MAC_PORT_AET_ZFE_LIMITS_0 0x2b08
+
+#define S_ACC_LIM    8
+#define M_ACC_LIM    0xfU
+#define V_ACC_LIM(x) ((x) << S_ACC_LIM)
+#define G_ACC_LIM(x) (((x) >> S_ACC_LIM) & M_ACC_LIM)
+
+#define S_CNV_LIM    4
+#define M_CNV_LIM    0xfU
+#define V_CNV_LIM(x) ((x) << S_CNV_LIM)
+#define G_CNV_LIM(x) (((x) >> S_CNV_LIM) & M_CNV_LIM)
+
+#define S_TOG_LIM    0
+#define M_TOG_LIM    0xfU
+#define V_TOG_LIM(x) ((x) << S_TOG_LIM)
+#define G_TOG_LIM(x) (((x) >> S_TOG_LIM) & M_TOG_LIM)
+
+#define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0 0x2b0c
+
+#define S_BOOT_LUT7    12
+#define M_BOOT_LUT7    0xfU
+#define V_BOOT_LUT7(x) ((x) << S_BOOT_LUT7)
+#define G_BOOT_LUT7(x) (((x) >> S_BOOT_LUT7) & M_BOOT_LUT7)
+
+#define S_BOOT_LUT6    8
+#define M_BOOT_LUT6    0xfU
+#define V_BOOT_LUT6(x) ((x) << S_BOOT_LUT6)
+#define G_BOOT_LUT6(x) (((x) >> S_BOOT_LUT6) & M_BOOT_LUT6)
+
+#define S_BOOT_LUT45    4
+#define M_BOOT_LUT45    0xfU
+#define V_BOOT_LUT45(x) ((x) << S_BOOT_LUT45)
+#define G_BOOT_LUT45(x) (((x) >> S_BOOT_LUT45) & M_BOOT_LUT45)
+
+#define S_BOOT_LUT0123    2
+#define M_BOOT_LUT0123    0x3U
+#define V_BOOT_LUT0123(x) ((x) << S_BOOT_LUT0123)
+#define G_BOOT_LUT0123(x) (((x) >> S_BOOT_LUT0123) & M_BOOT_LUT0123)
+
+#define S_BOOT_DEC_C0    1
+#define V_BOOT_DEC_C0(x) ((x) << S_BOOT_DEC_C0)
+#define F_BOOT_DEC_C0    V_BOOT_DEC_C0(1U)
+
+#define A_MAC_PORT_AET_STATUS_0 0x2b10
+
+#define S_AET_STAT    9
+#define M_AET_STAT    0xfU
+#define V_AET_STAT(x) ((x) << S_AET_STAT)
+#define G_AET_STAT(x) (((x) >> S_AET_STAT) & M_AET_STAT)
+
+#define S_NEU_STATE    5
+#define M_NEU_STATE    0xfU
+#define V_NEU_STATE(x) ((x) << S_NEU_STATE)
+#define G_NEU_STATE(x) (((x) >> S_NEU_STATE) & M_NEU_STATE)
+
+#define S_CTRL_STATE    0
+#define M_CTRL_STATE    0x1fU
+#define V_CTRL_STATE(x) ((x) << S_CTRL_STATE)
+#define G_CTRL_STATE(x) (((x) >> S_CTRL_STATE) & M_CTRL_STATE)
+
+#define A_MAC_PORT_AET_STAGE_CONFIGURATION_1 0x2b20
+#define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1 0x2b24
+#define A_MAC_PORT_AET_ZFE_LIMITS_1 0x2b28
+#define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1 0x2b2c
+#define A_MAC_PORT_AET_STATUS_1 0x2b30
+#define A_MAC_PORT_AET_STAGE_CONFIGURATION_2 0x2b40
+#define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2 0x2b44
+#define A_MAC_PORT_AET_ZFE_LIMITS_2 0x2b48
+#define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2 0x2b4c
+#define A_MAC_PORT_AET_STATUS_2 0x2b50
+#define A_MAC_PORT_AET_STAGE_CONFIGURATION_3 0x2b60
+#define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3 0x2b64
+#define A_MAC_PORT_AET_ZFE_LIMITS_3 0x2b68
+#define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3 0x2b6c
+#define A_MAC_PORT_AET_STATUS_3 0x2b70
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE 0x3000
+
+#define S_T5_TX_LINKEN    15
+#define V_T5_TX_LINKEN(x) ((x) << S_T5_TX_LINKEN)
+#define F_T5_TX_LINKEN    V_T5_TX_LINKEN(1U)
+
+#define S_T5_TX_LINKRST    14
+#define V_T5_TX_LINKRST(x) ((x) << S_T5_TX_LINKRST)
+#define F_T5_TX_LINKRST    V_T5_TX_LINKRST(1U)
+
+#define S_T5_TX_CFGWRT    13
+#define V_T5_TX_CFGWRT(x) ((x) << S_T5_TX_CFGWRT)
+#define F_T5_TX_CFGWRT    V_T5_TX_CFGWRT(1U)
+
+#define S_T5_TX_CFGPTR    11
+#define M_T5_TX_CFGPTR    0x3U
+#define V_T5_TX_CFGPTR(x) ((x) << S_T5_TX_CFGPTR)
+#define G_T5_TX_CFGPTR(x) (((x) >> S_T5_TX_CFGPTR) & M_T5_TX_CFGPTR)
+
+#define S_T5_TX_CFGEXT    10
+#define V_T5_TX_CFGEXT(x) ((x) << S_T5_TX_CFGEXT)
+#define F_T5_TX_CFGEXT    V_T5_TX_CFGEXT(1U)
+
+#define S_T5_TX_CFGACT    9
+#define V_T5_TX_CFGACT(x) ((x) << S_T5_TX_CFGACT)
+#define F_T5_TX_CFGACT    V_T5_TX_CFGACT(1U)
+
+#define S_T5_TX_RSYNCC    8
+#define V_T5_TX_RSYNCC(x) ((x) << S_T5_TX_RSYNCC)
+#define F_T5_TX_RSYNCC    V_T5_TX_RSYNCC(1U)
+
+#define S_T5_TX_PLLSEL    6
+#define M_T5_TX_PLLSEL    0x3U
+#define V_T5_TX_PLLSEL(x) ((x) << S_T5_TX_PLLSEL)
+#define G_T5_TX_PLLSEL(x) (((x) >> S_T5_TX_PLLSEL) & M_T5_TX_PLLSEL)
+
+#define S_T5_TX_EXTC16    5
+#define V_T5_TX_EXTC16(x) ((x) << S_T5_TX_EXTC16)
+#define F_T5_TX_EXTC16    V_T5_TX_EXTC16(1U)
+
+#define S_T5_TX_DCKSEL    4
+#define V_T5_TX_DCKSEL(x) ((x) << S_T5_TX_DCKSEL)
+#define F_T5_TX_DCKSEL    V_T5_TX_DCKSEL(1U)
+
+#define S_T5_TX_RXLOOP    3
+#define V_T5_TX_RXLOOP(x) ((x) << S_T5_TX_RXLOOP)
+#define F_T5_TX_RXLOOP    V_T5_TX_RXLOOP(1U)
+
+#define S_T5_TX_BWSEL    2
+#define V_T5_TX_BWSEL(x) ((x) << S_T5_TX_BWSEL)
+#define F_T5_TX_BWSEL    V_T5_TX_BWSEL(1U)
+
+#define S_T5_TX_RTSEL    0
+#define M_T5_TX_RTSEL    0x3U
+#define V_T5_TX_RTSEL(x) ((x) << S_T5_TX_RTSEL)
+#define G_T5_TX_RTSEL(x) (((x) >> S_T5_TX_RTSEL) & M_T5_TX_RTSEL)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL 0x3004
+
+#define S_SPSEL    11
+#define M_SPSEL    0x7U
+#define V_SPSEL(x) ((x) << S_SPSEL)
+#define G_SPSEL(x) (((x) >> S_SPSEL) & M_SPSEL)
+
+#define S_AFDWEN    7
+#define V_AFDWEN(x) ((x) << S_AFDWEN)
+#define F_AFDWEN    V_AFDWEN(1U)
+
+#define S_TPGMD    3
+#define V_TPGMD(x) ((x) << S_TPGMD)
+#define F_TPGMD    V_TPGMD(1U)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL 0x3008
+
+#define S_ZCALOVRD    8
+#define V_ZCALOVRD(x) ((x) << S_ZCALOVRD)
+#define F_ZCALOVRD    V_ZCALOVRD(1U)
+
+#define S_AMMODE    7
+#define V_AMMODE(x) ((x) << S_AMMODE)
+#define F_AMMODE    V_AMMODE(1U)
+
+#define S_AEPOL    6
+#define V_AEPOL(x) ((x) << S_AEPOL)
+#define F_AEPOL    V_AEPOL(1U)
+
+#define S_AESRC    5
+#define V_AESRC(x) ((x) << S_AESRC)
+#define F_AESRC    V_AESRC(1U)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL 0x300c
+
+#define S_T5DRVHIZ    5
+#define V_T5DRVHIZ(x) ((x) << S_T5DRVHIZ)
+#define F_T5DRVHIZ    V_T5DRVHIZ(1U)
+
+#define S_T5SASIMP    4
+#define V_T5SASIMP(x) ((x) << S_T5SASIMP)
+#define F_T5SASIMP    V_T5SASIMP(1U)
+
+#define S_T5SLEW    2
+#define M_T5SLEW    0x3U
+#define V_T5SLEW(x) ((x) << S_T5SLEW)
+#define G_T5SLEW(x) (((x) >> S_T5SLEW) & M_T5SLEW)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3010
+
+#define S_T5C2BUFDCEN    5
+#define V_T5C2BUFDCEN(x) ((x) << S_T5C2BUFDCEN)
+#define F_T5C2BUFDCEN    V_T5C2BUFDCEN(1U)
+
+#define S_T5DCCEN    4
+#define V_T5DCCEN(x) ((x) << S_T5DCCEN)
+#define F_T5DCCEN    V_T5DCCEN(1U)
+
+#define S_T5REGBYP    3
+#define V_T5REGBYP(x) ((x) << S_T5REGBYP)
+#define F_T5REGBYP    V_T5REGBYP(1U)
+
+#define S_T5REGAEN    2
+#define V_T5REGAEN(x) ((x) << S_T5REGAEN)
+#define F_T5REGAEN    V_T5REGAEN(1U)
+
+#define S_T5REGAMP    0
+#define M_T5REGAMP    0x3U
+#define V_T5REGAMP(x) ((x) << S_T5REGAMP)
+#define G_T5REGAMP(x) (((x) >> S_T5REGAMP) & M_T5REGAMP)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3014
+
+#define S_RSTEP    15
+#define V_RSTEP(x) ((x) << S_RSTEP)
+#define F_RSTEP    V_RSTEP(1U)
+
+#define S_RLOCK    14
+#define V_RLOCK(x) ((x) << S_RLOCK)
+#define F_RLOCK    V_RLOCK(1U)
+
+#define S_RPOS    8
+#define M_RPOS    0x3fU
+#define V_RPOS(x) ((x) << S_RPOS)
+#define G_RPOS(x) (((x) >> S_RPOS) & M_RPOS)
+
+#define S_DCLKSAM    7
+#define V_DCLKSAM(x) ((x) << S_DCLKSAM)
+#define F_DCLKSAM    V_DCLKSAM(1U)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3018
+
+#define S_CALSSTN    3
+#define M_CALSSTN    0x7U
+#define V_CALSSTN(x) ((x) << S_CALSSTN)
+#define G_CALSSTN(x) (((x) >> S_CALSSTN) & M_CALSSTN)
+
+#define S_CALSSTP    0
+#define M_CALSSTP    0x7U
+#define V_CALSSTP(x) ((x) << S_CALSSTP)
+#define G_CALSSTP(x) (((x) >> S_CALSSTP) & M_CALSSTP)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x301c
+
+#define S_DRTOL    0
+#define M_DRTOL    0x1fU
+#define V_DRTOL(x) ((x) << S_DRTOL)
+#define G_DRTOL(x) (((x) >> S_DRTOL) & M_DRTOL)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT 0x3020
+
+#define S_T5NXTT0    0
+#define M_T5NXTT0    0x1fU
+#define V_T5NXTT0(x) ((x) << S_T5NXTT0)
+#define G_T5NXTT0(x) (((x) >> S_T5NXTT0) & M_T5NXTT0)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT 0x3024
+
+#define S_T5NXTT1    0
+#define M_T5NXTT1    0x3fU
+#define V_T5NXTT1(x) ((x) << S_T5NXTT1)
+#define G_T5NXTT1(x) (((x) >> S_T5NXTT1) & M_T5NXTT1)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT 0x3028
+
+#define S_T5NXTT2    0
+#define M_T5NXTT2    0x3fU
+#define V_T5NXTT2(x) ((x) << S_T5NXTT2)
+#define G_T5NXTT2(x) (((x) >> S_T5NXTT2) & M_T5NXTT2)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE 0x3030
+
+#define S_T5TXPWR    0
+#define M_T5TXPWR    0x3fU
+#define V_T5TXPWR(x) ((x) << S_T5TXPWR)
+#define G_T5TXPWR(x) (((x) >> S_T5TXPWR) & M_T5TXPWR)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_POLARITY 0x3034
+
+#define S_NXTPOL    0
+#define M_NXTPOL    0x7U
+#define V_NXTPOL(x) ((x) << S_NXTPOL)
+#define G_NXTPOL(x) (((x) >> S_NXTPOL) & M_NXTPOL)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3038
+
+#define S_CPREST    13
+#define V_CPREST(x) ((x) << S_CPREST)
+#define F_CPREST    V_CPREST(1U)
+
+#define S_CINIT    12
+#define V_CINIT(x) ((x) << S_CINIT)
+#define F_CINIT    V_CINIT(1U)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x303c
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3040
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3044
+
+#define S_T5NIDAC1    0
+#define M_T5NIDAC1    0x3fU
+#define V_T5NIDAC1(x) ((x) << S_T5NIDAC1)
+#define G_T5NIDAC1(x) (((x) >> S_T5NIDAC1) & M_T5NIDAC1)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3048
+
+#define S_T5NIDAC2    0
+#define M_T5NIDAC2    0x3fU
+#define V_T5NIDAC2(x) ((x) << S_T5NIDAC2)
+#define G_T5NIDAC2(x) (((x) >> S_T5NIDAC2) & M_T5NIDAC2)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3060
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3064
+
+#define S_T5AIDAC1    0
+#define M_T5AIDAC1    0x3fU
+#define V_T5AIDAC1(x) ((x) << S_T5AIDAC1)
+#define G_T5AIDAC1(x) (((x) >> S_T5AIDAC1) & M_T5AIDAC1)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3068
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3070
+
+#define S_MAINSC    6
+#define M_MAINSC    0x3fU
+#define V_MAINSC(x) ((x) << S_MAINSC)
+#define G_MAINSC(x) (((x) >> S_MAINSC) & M_MAINSC)
+
+#define S_POSTSC    0
+#define M_POSTSC    0x3fU
+#define V_POSTSC(x) ((x) << S_POSTSC)
+#define G_POSTSC(x) (((x) >> S_POSTSC) & M_POSTSC)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3074
+
+#define S_PRESC    0
+#define M_PRESC    0x1fU
+#define V_PRESC(x) ((x) << S_PRESC)
+#define G_PRESC(x) (((x) >> S_PRESC) & M_PRESC)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3078
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x307c
+
+#define S_T5XADDR    1
+#define M_T5XADDR    0x1fU
+#define V_T5XADDR(x) ((x) << S_T5XADDR)
+#define G_T5XADDR(x) (((x) >> S_T5XADDR) & M_T5XADDR)
+
+#define S_T5XWR    0
+#define V_T5XWR(x) ((x) << S_T5XWR)
+#define F_T5XWR    V_T5XWR(1U)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3080
+
+#define S_XDAT10    0
+#define M_XDAT10    0xffffU
+#define V_XDAT10(x) ((x) << S_XDAT10)
+#define G_XDAT10(x) (((x) >> S_XDAT10) & M_XDAT10)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3084
+
+#define S_XDAT32    0
+#define M_XDAT32    0xffffU
+#define V_XDAT32(x) ((x) << S_XDAT32)
+#define G_XDAT32(x) (((x) >> S_XDAT32) & M_XDAT32)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3088
+
+#define S_XDAT4    0
+#define M_XDAT4    0xffU
+#define V_XDAT4(x) ((x) << S_XDAT4)
+#define G_XDAT4(x) (((x) >> S_XDAT4) & M_XDAT4)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL 0x308c
+
+#define S_DCCTIMEDOUT    15
+#define V_DCCTIMEDOUT(x) ((x) << S_DCCTIMEDOUT)
+#define F_DCCTIMEDOUT    V_DCCTIMEDOUT(1U)
+
+#define S_DCCTIMEEN    14
+#define V_DCCTIMEEN(x) ((x) << S_DCCTIMEEN)
+#define F_DCCTIMEEN    V_DCCTIMEEN(1U)
+
+#define S_DCCLOCK    13
+#define V_DCCLOCK(x) ((x) << S_DCCLOCK)
+#define F_DCCLOCK    V_DCCLOCK(1U)
+
+#define S_DCCOFFSET    8
+#define M_DCCOFFSET    0x1fU
+#define V_DCCOFFSET(x) ((x) << S_DCCOFFSET)
+#define G_DCCOFFSET(x) (((x) >> S_DCCOFFSET) & M_DCCOFFSET)
+
+#define S_DCCSTEP    6
+#define M_DCCSTEP    0x3U
+#define V_DCCSTEP(x) ((x) << S_DCCSTEP)
+#define G_DCCSTEP(x) (((x) >> S_DCCSTEP) & M_DCCSTEP)
+
+#define S_DCCASTEP    1
+#define M_DCCASTEP    0x1fU
+#define V_DCCASTEP(x) ((x) << S_DCCASTEP)
+#define G_DCCASTEP(x) (((x) >> S_DCCASTEP) & M_DCCASTEP)
+
+#define S_DCCAEN    0
+#define V_DCCAEN(x) ((x) << S_DCCAEN)
+#define F_DCCAEN    V_DCCAEN(1U)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE 0x3090
+
+#define S_DCCOUT    12
+#define V_DCCOUT(x) ((x) << S_DCCOUT)
+#define F_DCCOUT    V_DCCOUT(1U)
+
+#define S_DCCCLK    11
+#define V_DCCCLK(x) ((x) << S_DCCCLK)
+#define F_DCCCLK    V_DCCCLK(1U)
+
+#define S_DCCHOLD    10
+#define V_DCCHOLD(x) ((x) << S_DCCHOLD)
+#define F_DCCHOLD    V_DCCHOLD(1U)
+
+#define S_DCCSIGN    8
+#define M_DCCSIGN    0x3U
+#define V_DCCSIGN(x) ((x) << S_DCCSIGN)
+#define G_DCCSIGN(x) (((x) >> S_DCCSIGN) & M_DCCSIGN)
+
+#define S_DCCAMP    1
+#define M_DCCAMP    0x7fU
+#define V_DCCAMP(x) ((x) << S_DCCAMP)
+#define G_DCCAMP(x) (((x) >> S_DCCAMP) & M_DCCAMP)
+
+#define S_DCCOEN    0
+#define V_DCCOEN(x) ((x) << S_DCCOEN)
+#define F_DCCOEN    V_DCCOEN(1U)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED 0x3094
+
+#define S_DCCASIGN    7
+#define M_DCCASIGN    0x3U
+#define V_DCCASIGN(x) ((x) << S_DCCASIGN)
+#define G_DCCASIGN(x) (((x) >> S_DCCASIGN) & M_DCCASIGN)
+
+#define S_DCCAAMP    0
+#define M_DCCAAMP    0x7fU
+#define V_DCCAAMP(x) ((x) << S_DCCAAMP)
+#define G_DCCAAMP(x) (((x) >> S_DCCAAMP) & M_DCCAAMP)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT 0x3098
+
+#define S_DCCTIMEOUTVAL    0
+#define M_DCCTIMEOUTVAL    0xffffU
+#define V_DCCTIMEOUTVAL(x) ((x) << S_DCCTIMEOUTVAL)
+#define G_DCCTIMEOUTVAL(x) (((x) >> S_DCCTIMEOUTVAL) & M_DCCTIMEOUTVAL)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL 0x309c
+
+#define S_LPIDCLK    4
+#define V_LPIDCLK(x) ((x) << S_LPIDCLK)
+#define F_LPIDCLK    V_LPIDCLK(1U)
+
+#define S_LPITERM    2
+#define M_LPITERM    0x3U
+#define V_LPITERM(x) ((x) << S_LPITERM)
+#define G_LPITERM(x) (((x) >> S_LPITERM) & M_LPITERM)
+
+#define S_LPIPRCD    0
+#define M_LPIPRCD    0x3U
+#define V_LPIPRCD(x) ((x) << S_LPIPRCD)
+#define G_LPIPRCD(x) (((x) >> S_LPIPRCD) & M_LPIPRCD)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4 0x30f0
+
+#define S_SDOVRDEN    8
+#define V_SDOVRDEN(x) ((x) << S_SDOVRDEN)
+#define F_SDOVRDEN    V_SDOVRDEN(1U)
+
+#define S_SDOVRD    0
+#define M_SDOVRD    0xffU
+#define V_SDOVRD(x) ((x) << S_SDOVRD)
+#define G_SDOVRD(x) (((x) >> S_SDOVRD) & M_SDOVRD)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3 0x30f4
+
+#define S_SLEWCODE    1
+#define M_SLEWCODE    0x3U
+#define V_SLEWCODE(x) ((x) << S_SLEWCODE)
+#define G_SLEWCODE(x) (((x) >> S_SLEWCODE) & M_SLEWCODE)
+
+#define S_ASEGEN    0
+#define V_ASEGEN(x) ((x) << S_ASEGEN)
+#define F_ASEGEN    V_ASEGEN(1U)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2 0x30f8
+
+#define S_AECMDVAL    14
+#define V_AECMDVAL(x) ((x) << S_AECMDVAL)
+#define F_AECMDVAL    V_AECMDVAL(1U)
+
+#define S_AECMD1312    12
+#define M_AECMD1312    0x3U
+#define V_AECMD1312(x) ((x) << S_AECMD1312)
+#define G_AECMD1312(x) (((x) >> S_AECMD1312) & M_AECMD1312)
+
+#define S_AECMD70    0
+#define M_AECMD70    0xffU
+#define V_AECMD70(x) ((x) << S_AECMD70)
+#define G_AECMD70(x) (((x) >> S_AECMD70) & M_AECMD70)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1 0x30fc
+
+#define S_C48DIVCTL    12
+#define M_C48DIVCTL    0x7U
+#define V_C48DIVCTL(x) ((x) << S_C48DIVCTL)
+#define G_C48DIVCTL(x) (((x) >> S_C48DIVCTL) & M_C48DIVCTL)
+
+#define S_RATEDIVCTL    9
+#define M_RATEDIVCTL    0x7U
+#define V_RATEDIVCTL(x) ((x) << S_RATEDIVCTL)
+#define G_RATEDIVCTL(x) (((x) >> S_RATEDIVCTL) & M_RATEDIVCTL)
+
+#define S_ANLGFLSH    8
+#define V_ANLGFLSH(x) ((x) << S_ANLGFLSH)
+#define F_ANLGFLSH    V_ANLGFLSH(1U)
+
+#define S_DCCTSTOUT    7
+#define V_DCCTSTOUT(x) ((x) << S_DCCTSTOUT)
+#define F_DCCTSTOUT    V_DCCTSTOUT(1U)
+
+#define S_BSOUT    6
+#define V_BSOUT(x) ((x) << S_BSOUT)
+#define F_BSOUT    V_BSOUT(1U)
+
+#define S_BSIN    5
+#define V_BSIN(x) ((x) << S_BSIN)
+#define F_BSIN    V_BSIN(1U)
+
+#define S_JTAGAMPL    3
+#define M_JTAGAMPL    0x3U
+#define V_JTAGAMPL(x) ((x) << S_JTAGAMPL)
+#define G_JTAGAMPL(x) (((x) >> S_JTAGAMPL) & M_JTAGAMPL)
+
+#define S_JTAGTS    2
+#define V_JTAGTS(x) ((x) << S_JTAGTS)
+#define F_JTAGTS    V_JTAGTS(1U)
+
+#define S_TS    1
+#define V_TS(x) ((x) << S_TS)
+#define F_TS    V_TS(1U)
+
+#define S_OBS    0
+#define V_OBS(x) ((x) << S_OBS)
+#define F_OBS    V_OBS(1U)
+
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE 0x3100
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL 0x3104
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL 0x3108
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL 0x310c
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3110
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3114
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3118
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x311c
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT 0x3120
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT 0x3124
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT 0x3128
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE 0x3130
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_POLARITY 0x3134
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3138
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x313c
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3140
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3144
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3148
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3160
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3164
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3168
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3170
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3174
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3178
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x317c
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3180
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3184
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3188
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL 0x318c
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE 0x3190
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED 0x3194
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT 0x3198
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL 0x319c
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4 0x31f0
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3 0x31f4
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2 0x31f8
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1 0x31fc
+#define A_MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE 0x3200
+
+#define S_T5_RX_LINKEN    15
+#define V_T5_RX_LINKEN(x) ((x) << S_T5_RX_LINKEN)
+#define F_T5_RX_LINKEN    V_T5_RX_LINKEN(1U)
+
+#define S_T5_RX_LINKRST    14
+#define V_T5_RX_LINKRST(x) ((x) << S_T5_RX_LINKRST)
+#define F_T5_RX_LINKRST    V_T5_RX_LINKRST(1U)
+
+#define S_T5_RX_CFGWRT    13
+#define V_T5_RX_CFGWRT(x) ((x) << S_T5_RX_CFGWRT)
+#define F_T5_RX_CFGWRT    V_T5_RX_CFGWRT(1U)
+
+#define S_T5_RX_CFGPTR    11
+#define M_T5_RX_CFGPTR    0x3U
+#define V_T5_RX_CFGPTR(x) ((x) << S_T5_RX_CFGPTR)
+#define G_T5_RX_CFGPTR(x) (((x) >> S_T5_RX_CFGPTR) & M_T5_RX_CFGPTR)
+
+#define S_T5_RX_CFGEXT    10
+#define V_T5_RX_CFGEXT(x) ((x) << S_T5_RX_CFGEXT)
+#define F_T5_RX_CFGEXT    V_T5_RX_CFGEXT(1U)
+
+#define S_T5_RX_CFGACT    9
+#define V_T5_RX_CFGACT(x) ((x) << S_T5_RX_CFGACT)
+#define F_T5_RX_CFGACT    V_T5_RX_CFGACT(1U)
+
+#define S_T5_RX_AUXCLK    8
+#define V_T5_RX_AUXCLK(x) ((x) << S_T5_RX_AUXCLK)
+#define F_T5_RX_AUXCLK    V_T5_RX_AUXCLK(1U)
+
+#define S_T5_RX_PLLSEL    6
+#define M_T5_RX_PLLSEL    0x3U
+#define V_T5_RX_PLLSEL(x) ((x) << S_T5_RX_PLLSEL)
+#define G_T5_RX_PLLSEL(x) (((x) >> S_T5_RX_PLLSEL) & M_T5_RX_PLLSEL)
+
+#define S_T5_RX_DMSEL    4
+#define M_T5_RX_DMSEL    0x3U
+#define V_T5_RX_DMSEL(x) ((x) << S_T5_RX_DMSEL)
+#define G_T5_RX_DMSEL(x) (((x) >> S_T5_RX_DMSEL) & M_T5_RX_DMSEL)
+
+#define S_T5_RX_BWSEL    2
+#define M_T5_RX_BWSEL    0x3U
+#define V_T5_RX_BWSEL(x) ((x) << S_T5_RX_BWSEL)
+#define G_T5_RX_BWSEL(x) (((x) >> S_T5_RX_BWSEL) & M_T5_RX_BWSEL)
+
+#define S_T5_RX_RTSEL    0
+#define M_T5_RX_RTSEL    0x3U
+#define V_T5_RX_RTSEL(x) ((x) << S_T5_RX_RTSEL)
+#define G_T5_RX_RTSEL(x) (((x) >> S_T5_RX_RTSEL) & M_T5_RX_RTSEL)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL 0x3204
+
+#define S_FERRST    10
+#define V_FERRST(x) ((x) << S_FERRST)
+#define F_FERRST    V_FERRST(1U)
+
+#define S_ERRST    9
+#define V_ERRST(x) ((x) << S_ERRST)
+#define F_ERRST    V_ERRST(1U)
+
+#define S_SYNCST    8
+#define V_SYNCST(x) ((x) << S_SYNCST)
+#define F_SYNCST    V_SYNCST(1U)
+
+#define S_WRPSM    7
+#define V_WRPSM(x) ((x) << S_WRPSM)
+#define F_WRPSM    V_WRPSM(1U)
+
+#define S_WPLPEN    6
+#define V_WPLPEN(x) ((x) << S_WPLPEN)
+#define F_WPLPEN    V_WPLPEN(1U)
+
+#define S_WRPMD    5
+#define V_WRPMD(x) ((x) << S_WRPMD)
+#define F_WRPMD    V_WRPMD(1U)
+
+#define S_PATSEL    0
+#define M_PATSEL    0x7U
+#define V_PATSEL(x) ((x) << S_PATSEL)
+#define G_PATSEL(x) (((x) >> S_PATSEL) & M_PATSEL)
+
+#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL 0x3208
+
+#define S_RSTUCK    3
+#define V_RSTUCK(x) ((x) << S_RSTUCK)
+#define F_RSTUCK    V_RSTUCK(1U)
+
+#define S_FRZFW    2
+#define V_FRZFW(x) ((x) << S_FRZFW)
+#define F_FRZFW    V_FRZFW(1U)
+
+#define S_RSTFW    1
+#define V_RSTFW(x) ((x) << S_RSTFW)
+#define F_RSTFW    V_RSTFW(1U)
+
+#define S_SSCEN    0
+#define V_SSCEN(x) ((x) << S_SSCEN)
+#define F_SSCEN    V_SSCEN(1U)
+
+#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL 0x320c
+#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1 0x3210
+
+#define S_ROT00    0
+#define M_ROT00    0x3fU
+#define V_ROT00(x) ((x) << S_ROT00)
+#define G_ROT00(x) (((x) >> S_ROT00) & M_ROT00)
+
+#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2 0x3214
+
+#define S_FREQFW    8
+#define M_FREQFW    0xffU
+#define V_FREQFW(x) ((x) << S_FREQFW)
+#define G_FREQFW(x) (((x) >> S_FREQFW) & M_FREQFW)
+
+#define S_FWSNAP    7
+#define V_FWSNAP(x) ((x) << S_FWSNAP)
+#define F_FWSNAP    V_FWSNAP(1U)
+
+#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3218
+#define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x321c
+
+#define S_RBOOFF    10
+#define M_RBOOFF    0x1fU
+#define V_RBOOFF(x) ((x) << S_RBOOFF)
+#define G_RBOOFF(x) (((x) >> S_RBOOFF) & M_RBOOFF)
+
+#define S_RBEOFF    5
+#define M_RBEOFF    0x1fU
+#define V_RBEOFF(x) ((x) << S_RBEOFF)
+#define G_RBEOFF(x) (((x) >> S_RBEOFF) & M_RBEOFF)
+
+#define A_MAC_PORT_RX_LINKA_DFE_CONTROL 0x3220
+#define A_MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1 0x3224
+
+#define S_T5BYTE1    8
+#define M_T5BYTE1    0xffU
+#define V_T5BYTE1(x) ((x) << S_T5BYTE1)
+#define G_T5BYTE1(x) (((x) >> S_T5BYTE1) & M_T5BYTE1)
+
+#define S_T5BYTE0    0
+#define M_T5BYTE0    0xffU
+#define V_T5BYTE0(x) ((x) << S_T5BYTE0)
+#define G_T5BYTE0(x) (((x) >> S_T5BYTE0) & M_T5BYTE0)
+
+#define A_MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2 0x3228
+
+#define S_T5_RX_SMODE    8
+#define M_T5_RX_SMODE    0x7U
+#define V_T5_RX_SMODE(x) ((x) << S_T5_RX_SMODE)
+#define G_T5_RX_SMODE(x) (((x) >> S_T5_RX_SMODE) & M_T5_RX_SMODE)
+
+#define S_T5_RX_ADCORR    7
+#define V_T5_RX_ADCORR(x) ((x) << S_T5_RX_ADCORR)
+#define F_T5_RX_ADCORR    V_T5_RX_ADCORR(1U)
+
+#define S_T5_RX_TRAINEN    6
+#define V_T5_RX_TRAINEN(x) ((x) << S_T5_RX_TRAINEN)
+#define F_T5_RX_TRAINEN    V_T5_RX_TRAINEN(1U)
+
+#define S_T5_RX_ASAMPQ    3
+#define M_T5_RX_ASAMPQ    0x7U
+#define V_T5_RX_ASAMPQ(x) ((x) << S_T5_RX_ASAMPQ)
+#define G_T5_RX_ASAMPQ(x) (((x) >> S_T5_RX_ASAMPQ) & M_T5_RX_ASAMPQ)
+
+#define S_T5_RX_ASAMP    0
+#define M_T5_RX_ASAMP    0x7U
+#define V_T5_RX_ASAMP(x) ((x) << S_T5_RX_ASAMP)
+#define G_T5_RX_ASAMP(x) (((x) >> S_T5_RX_ASAMP) & M_T5_RX_ASAMP)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1 0x322c
+#define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2 0x3230
+
+#define S_T5SHORTV    10
+#define V_T5SHORTV(x) ((x) << S_T5SHORTV)
+#define F_T5SHORTV    V_T5SHORTV(1U)
+
+#define S_T5VGAIN    0
+#define M_T5VGAIN    0x1fU
+#define V_T5VGAIN(x) ((x) << S_T5VGAIN)
+#define G_T5VGAIN(x) (((x) >> S_T5VGAIN) & M_T5VGAIN)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3 0x3234
+#define A_MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1 0x3238
+
+#define S_IQSEP    10
+#define M_IQSEP    0x1fU
+#define V_IQSEP(x) ((x) << S_IQSEP)
+#define G_IQSEP(x) (((x) >> S_IQSEP) & M_IQSEP)
+
+#define S_DUTYQ    5
+#define M_DUTYQ    0x1fU
+#define V_DUTYQ(x) ((x) << S_DUTYQ)
+#define G_DUTYQ(x) (((x) >> S_DUTYQ) & M_DUTYQ)
+
+#define S_DUTYI    0
+#define M_DUTYI    0x1fU
+#define V_DUTYI(x) ((x) << S_DUTYI)
+#define G_DUTYI(x) (((x) >> S_DUTYI) & M_DUTYI)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3 0x3240
+
+#define S_DTHR    8
+#define M_DTHR    0x3fU
+#define V_DTHR(x) ((x) << S_DTHR)
+#define G_DTHR(x) (((x) >> S_DTHR) & M_DTHR)
+
+#define S_SNUL    0
+#define M_SNUL    0x1fU
+#define V_SNUL(x) ((x) << S_SNUL)
+#define G_SNUL(x) (((x) >> S_SNUL) & M_SNUL)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN 0x3248
+#define A_MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ 0x324c
+#define A_MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL 0x3250
+
+#define S_ADSN_READWRITE    8
+#define V_ADSN_READWRITE(x) ((x) << S_ADSN_READWRITE)
+#define F_ADSN_READWRITE    V_ADSN_READWRITE(1U)
+
+#define S_ADSN_READONLY    7
+#define V_ADSN_READONLY(x) ((x) << S_ADSN_READONLY)
+#define F_ADSN_READONLY    V_ADSN_READONLY(1U)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x325c
+
+#define S_H1O2    8
+#define M_H1O2    0x3fU
+#define V_H1O2(x) ((x) << S_H1O2)
+#define G_H1O2(x) (((x) >> S_H1O2) & M_H1O2)
+
+#define S_H1E2    0
+#define M_H1E2    0x3fU
+#define V_H1E2(x) ((x) << S_H1E2)
+#define G_H1E2(x) (((x) >> S_H1E2) & M_H1E2)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3260
+
+#define S_H1O3    8
+#define M_H1O3    0x3fU
+#define V_H1O3(x) ((x) << S_H1O3)
+#define G_H1O3(x) (((x) >> S_H1O3) & M_H1O3)
+
+#define S_H1E3    0
+#define M_H1E3    0x3fU
+#define V_H1E3(x) ((x) << S_H1E3)
+#define G_H1E3(x) (((x) >> S_H1E3) & M_H1E3)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3264
+
+#define S_H1O4    8
+#define M_H1O4    0x3fU
+#define V_H1O4(x) ((x) << S_H1O4)
+#define G_H1O4(x) (((x) >> S_H1O4) & M_H1O4)
+
+#define S_H1E4    0
+#define M_H1E4    0x3fU
+#define V_H1E4(x) ((x) << S_H1E4)
+#define G_H1E4(x) (((x) >> S_H1E4) & M_H1E4)
+
+#define A_MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3270
+
+#define S_DPCMD    14
+#define V_DPCMD(x) ((x) << S_DPCMD)
+#define F_DPCMD    V_DPCMD(1U)
+
+#define A_MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC 0x3274
+#define A_MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS 0x3278
+
+#define S_T5BER6VAL    15
+#define V_T5BER6VAL(x) ((x) << S_T5BER6VAL)
+#define F_T5BER6VAL    V_T5BER6VAL(1U)
+
+#define S_T5BER6    14
+#define V_T5BER6(x) ((x) << S_T5BER6)
+#define F_T5BER6    V_T5BER6(1U)
+
+#define S_T5BER3VAL    13
+#define V_T5BER3VAL(x) ((x) << S_T5BER3VAL)
+#define F_T5BER3VAL    V_T5BER3VAL(1U)
+
+#define S_T5TOOFAST    12
+#define V_T5TOOFAST(x) ((x) << S_T5TOOFAST)
+#define F_T5TOOFAST    V_T5TOOFAST(1U)
+
+#define S_T5DPCCMP    9
+#define V_T5DPCCMP(x) ((x) << S_T5DPCCMP)
+#define F_T5DPCCMP    V_T5DPCCMP(1U)
+
+#define S_T5DACCMP    8
+#define V_T5DACCMP(x) ((x) << S_T5DACCMP)
+#define F_T5DACCMP    V_T5DACCMP(1U)
+
+#define S_T5DDCCMP    7
+#define V_T5DDCCMP(x) ((x) << S_T5DDCCMP)
+#define F_T5DDCCMP    V_T5DDCCMP(1U)
+
+#define S_T5AERRFLG    6
+#define V_T5AERRFLG(x) ((x) << S_T5AERRFLG)
+#define F_T5AERRFLG    V_T5AERRFLG(1U)
+
+#define S_T5WERRFLG    5
+#define V_T5WERRFLG(x) ((x) << S_T5WERRFLG)
+#define F_T5WERRFLG    V_T5WERRFLG(1U)
+
+#define S_T5TRCMP    4
+#define V_T5TRCMP(x) ((x) << S_T5TRCMP)
+#define F_T5TRCMP    V_T5TRCMP(1U)
+
+#define S_T5VLCKF    3
+#define V_T5VLCKF(x) ((x) << S_T5VLCKF)
+#define F_T5VLCKF    V_T5VLCKF(1U)
+
+#define S_T5ROCCMP    2
+#define V_T5ROCCMP(x) ((x) << S_T5ROCCMP)
+#define F_T5ROCCMP    V_T5ROCCMP(1U)
+
+#define S_T5DQCCCMP    1
+#define V_T5DQCCCMP(x) ((x) << S_T5DQCCCMP)
+#define F_T5DQCCCMP    V_T5DQCCCMP(1U)
+
+#define S_T5OCCMP    0
+#define V_T5OCCMP(x) ((x) << S_T5OCCMP)
+#define F_T5OCCMP    V_T5OCCMP(1U)
+
+#define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1 0x327c
+
+#define S_FLOFF    1
+#define V_FLOFF(x) ((x) << S_FLOFF)
+#define F_FLOFF    V_FLOFF(1U)
+
+#define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2 0x3280
+
+#define S_H25SPC    15
+#define V_H25SPC(x) ((x) << S_H25SPC)
+#define F_H25SPC    V_H25SPC(1U)
+
+#define S_FTOOFAST    8
+#define V_FTOOFAST(x) ((x) << S_FTOOFAST)
+#define F_FTOOFAST    V_FTOOFAST(1U)
+
+#define S_FINTTRIM    7
+#define V_FINTTRIM(x) ((x) << S_FINTTRIM)
+#define F_FINTTRIM    V_FINTTRIM(1U)
+
+#define S_FDINV    6
+#define V_FDINV(x) ((x) << S_FDINV)
+#define F_FDINV    V_FDINV(1U)
+
+#define S_FHGS    5
+#define V_FHGS(x) ((x) << S_FHGS)
+#define F_FHGS    V_FHGS(1U)
+
+#define S_FH6H12    4
+#define V_FH6H12(x) ((x) << S_FH6H12)
+#define F_FH6H12    V_FH6H12(1U)
+
+#define S_FH1CAL    3
+#define V_FH1CAL(x) ((x) << S_FH1CAL)
+#define F_FH1CAL    V_FH1CAL(1U)
+
+#define S_FINTCAL    2
+#define V_FINTCAL(x) ((x) << S_FINTCAL)
+#define F_FINTCAL    V_FINTCAL(1U)
+
+#define S_FDCA    1
+#define V_FDCA(x) ((x) << S_FDCA)
+#define F_FDCA    V_FDCA(1U)
+
+#define S_FDQCC    0
+#define V_FDQCC(x) ((x) << S_FDQCC)
+#define F_FDQCC    V_FDQCC(1U)
+
+#define A_MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2 0x3284
+
+#define S_LOFE2S_READWRITE    16
+#define V_LOFE2S_READWRITE(x) ((x) << S_LOFE2S_READWRITE)
+#define F_LOFE2S_READWRITE    V_LOFE2S_READWRITE(1U)
+
+#define S_LOFE2S_READONLY    14
+#define M_LOFE2S_READONLY    0x3U
+#define V_LOFE2S_READONLY(x) ((x) << S_LOFE2S_READONLY)
+#define G_LOFE2S_READONLY(x) (((x) >> S_LOFE2S_READONLY) & M_LOFE2S_READONLY)
+
+#define S_LOFE2    8
+#define M_LOFE2    0x3fU
+#define V_LOFE2(x) ((x) << S_LOFE2)
+#define G_LOFE2(x) (((x) >> S_LOFE2) & M_LOFE2)
+
+#define S_LOFE1S_READWRITE    7
+#define V_LOFE1S_READWRITE(x) ((x) << S_LOFE1S_READWRITE)
+#define F_LOFE1S_READWRITE    V_LOFE1S_READWRITE(1U)
+
+#define S_LOFE1S_READONLY    6
+#define V_LOFE1S_READONLY(x) ((x) << S_LOFE1S_READONLY)
+#define F_LOFE1S_READONLY    V_LOFE1S_READONLY(1U)
+
+#define S_LOFE1    0
+#define M_LOFE1    0x3fU
+#define V_LOFE1(x) ((x) << S_LOFE1)
+#define G_LOFE1(x) (((x) >> S_LOFE1) & M_LOFE1)
+
+#define A_MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2 0x3288
+
+#define S_LOFO2S_READWRITE    15
+#define V_LOFO2S_READWRITE(x) ((x) << S_LOFO2S_READWRITE)
+#define F_LOFO2S_READWRITE    V_LOFO2S_READWRITE(1U)
+
+#define S_LOFO2S_READONLY    14
+#define V_LOFO2S_READONLY(x) ((x) << S_LOFO2S_READONLY)
+#define F_LOFO2S_READONLY    V_LOFO2S_READONLY(1U)
+
+#define S_LOFO2    8
+#define M_LOFO2    0x3fU
+#define V_LOFO2(x) ((x) << S_LOFO2)
+#define G_LOFO2(x) (((x) >> S_LOFO2) & M_LOFO2)
+
+#define S_LOFO1S_READWRITE    7
+#define V_LOFO1S_READWRITE(x) ((x) << S_LOFO1S_READWRITE)
+#define F_LOFO1S_READWRITE    V_LOFO1S_READWRITE(1U)
+
+#define S_LOFO1S_READONLY    6
+#define V_LOFO1S_READONLY(x) ((x) << S_LOFO1S_READONLY)
+#define F_LOFO1S_READONLY    V_LOFO1S_READONLY(1U)
+
+#define S_LOFO1    0
+#define M_LOFO1    0x3fU
+#define V_LOFO1(x) ((x) << S_LOFO1)
+#define G_LOFO1(x) (((x) >> S_LOFO1) & M_LOFO1)
+
+#define A_MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4 0x328c
+
+#define S_LOFE4S_READWRITE    15
+#define V_LOFE4S_READWRITE(x) ((x) << S_LOFE4S_READWRITE)
+#define F_LOFE4S_READWRITE    V_LOFE4S_READWRITE(1U)
+
+#define S_LOFE4S_READONLY    14
+#define V_LOFE4S_READONLY(x) ((x) << S_LOFE4S_READONLY)
+#define F_LOFE4S_READONLY    V_LOFE4S_READONLY(1U)
+
+#define S_LOFE    8
+#define M_LOFE    0x3fU
+#define V_LOFE(x) ((x) << S_LOFE)
+#define G_LOFE(x) (((x) >> S_LOFE) & M_LOFE)
+
+#define S_LOFE3S_READWRITE    7
+#define V_LOFE3S_READWRITE(x) ((x) << S_LOFE3S_READWRITE)
+#define F_LOFE3S_READWRITE    V_LOFE3S_READWRITE(1U)
+
+#define S_LOFE3S_READONLY    6
+#define V_LOFE3S_READONLY(x) ((x) << S_LOFE3S_READONLY)
+#define F_LOFE3S_READONLY    V_LOFE3S_READONLY(1U)
+
+#define S_LOFE3    0
+#define M_LOFE3    0x3fU
+#define V_LOFE3(x) ((x) << S_LOFE3)
+#define G_LOFE3(x) (((x) >> S_LOFE3) & M_LOFE3)
+
+#define A_MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4 0x3290
+
+#define S_LOFO4S_READWRITE    15
+#define V_LOFO4S_READWRITE(x) ((x) << S_LOFO4S_READWRITE)
+#define F_LOFO4S_READWRITE    V_LOFO4S_READWRITE(1U)
+
+#define S_LOFO4S_READONLY    14
+#define V_LOFO4S_READONLY(x) ((x) << S_LOFO4S_READONLY)
+#define F_LOFO4S_READONLY    V_LOFO4S_READONLY(1U)
+
+#define S_LOFO4    8
+#define M_LOFO4    0x3fU
+#define V_LOFO4(x) ((x) << S_LOFO4)
+#define G_LOFO4(x) (((x) >> S_LOFO4) & M_LOFO4)
+
+#define S_LOFO3S_READWRITE    7
+#define V_LOFO3S_READWRITE(x) ((x) << S_LOFO3S_READWRITE)
+#define F_LOFO3S_READWRITE    V_LOFO3S_READWRITE(1U)
+
+#define S_LOFO3S_READONLY    6
+#define V_LOFO3S_READONLY(x) ((x) << S_LOFO3S_READONLY)
+#define F_LOFO3S_READONLY    V_LOFO3S_READONLY(1U)
+
+#define S_LOFO3    0
+#define M_LOFO3    0x3fU
+#define V_LOFO3(x) ((x) << S_LOFO3)
+#define G_LOFO3(x) (((x) >> S_LOFO3) & M_LOFO3)
+
+#define A_MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET 0x3294
+
+#define S_T5E1SN_READWRITE    15
+#define V_T5E1SN_READWRITE(x) ((x) << S_T5E1SN_READWRITE)
+#define F_T5E1SN_READWRITE    V_T5E1SN_READWRITE(1U)
+
+#define S_T5E1SN_READONLY    14
+#define V_T5E1SN_READONLY(x) ((x) << S_T5E1SN_READONLY)
+#define F_T5E1SN_READONLY    V_T5E1SN_READONLY(1U)
+
+#define S_T5E1AMP    8
+#define M_T5E1AMP    0x3fU
+#define V_T5E1AMP(x) ((x) << S_T5E1AMP)
+#define G_T5E1AMP(x) (((x) >> S_T5E1AMP) & M_T5E1AMP)
+
+#define S_T5E0SN_READWRITE    7
+#define V_T5E0SN_READWRITE(x) ((x) << S_T5E0SN_READWRITE)
+#define F_T5E0SN_READWRITE    V_T5E0SN_READWRITE(1U)
+
+#define S_T5E0SN_READONLY    6
+#define V_T5E0SN_READONLY(x) ((x) << S_T5E0SN_READONLY)
+#define F_T5E0SN_READONLY    V_T5E0SN_READONLY(1U)
+
+#define S_T5E0AMP    0
+#define M_T5E0AMP    0x3fU
+#define V_T5E0AMP(x) ((x) << S_T5E0AMP)
+#define G_T5E0AMP(x) (((x) >> S_T5E0AMP) & M_T5E0AMP)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL 0x3298
+
+#define S_T5LFREG    12
+#define V_T5LFREG(x) ((x) << S_T5LFREG)
+#define F_T5LFREG    V_T5LFREG(1U)
+
+#define S_T5LFRC    11
+#define V_T5LFRC(x) ((x) << S_T5LFRC)
+#define F_T5LFRC    V_T5LFRC(1U)
+
+#define S_T5LFSEL    8
+#define M_T5LFSEL    0x7U
+#define V_T5LFSEL(x) ((x) << S_T5LFSEL)
+#define G_T5LFSEL(x) (((x) >> S_T5LFSEL) & M_T5LFSEL)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL 0x329c
+
+#define S_OFFSN_READWRITE    14
+#define V_OFFSN_READWRITE(x) ((x) << S_OFFSN_READWRITE)
+#define F_OFFSN_READWRITE    V_OFFSN_READWRITE(1U)
+
+#define S_OFFSN_READONLY    13
+#define V_OFFSN_READONLY(x) ((x) << S_OFFSN_READONLY)
+#define F_OFFSN_READONLY    V_OFFSN_READONLY(1U)
+
+#define S_OFFAMP    8
+#define M_OFFAMP    0x1fU
+#define V_OFFAMP(x) ((x) << S_OFFAMP)
+#define G_OFFAMP(x) (((x) >> S_OFFAMP) & M_OFFAMP)
+
+#define S_SDACDC    7
+#define V_SDACDC(x) ((x) << S_SDACDC)
+#define F_SDACDC    V_SDACDC(1U)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH 0x32a0
+
+#define S_T5_RX_SETHDIS    7
+#define V_T5_RX_SETHDIS(x) ((x) << S_T5_RX_SETHDIS)
+#define F_T5_RX_SETHDIS    V_T5_RX_SETHDIS(1U)
+
+#define S_T5_RX_PDTERM    6
+#define V_T5_RX_PDTERM(x) ((x) << S_T5_RX_PDTERM)
+#define F_T5_RX_PDTERM    V_T5_RX_PDTERM(1U)
+
+#define S_T5_RX_BYPASS    5
+#define V_T5_RX_BYPASS(x) ((x) << S_T5_RX_BYPASS)
+#define F_T5_RX_BYPASS    V_T5_RX_BYPASS(1U)
+
+#define S_T5_RX_LPFEN    4
+#define V_T5_RX_LPFEN(x) ((x) << S_T5_RX_LPFEN)
+#define F_T5_RX_LPFEN    V_T5_RX_LPFEN(1U)
+
+#define S_T5_RX_VGABOD    3
+#define V_T5_RX_VGABOD(x) ((x) << S_T5_RX_VGABOD)
+#define F_T5_RX_VGABOD    V_T5_RX_VGABOD(1U)
+
+#define S_T5_RX_VTBYP    2
+#define V_T5_RX_VTBYP(x) ((x) << S_T5_RX_VTBYP)
+#define F_T5_RX_VTBYP    V_T5_RX_VTBYP(1U)
+
+#define S_T5_RX_VTERM    0
+#define M_T5_RX_VTERM    0x3U
+#define V_T5_RX_VTERM(x) ((x) << S_T5_RX_VTERM)
+#define G_T5_RX_VTERM(x) (((x) >> S_T5_RX_VTERM) & M_T5_RX_VTERM)
+
+#define A_MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET 0x32a4
+
+#define S_ISTRIMS    14
+#define M_ISTRIMS    0x3U
+#define V_ISTRIMS(x) ((x) << S_ISTRIMS)
+#define G_ISTRIMS(x) (((x) >> S_ISTRIMS) & M_ISTRIMS)
+
+#define S_ISTRIM    8
+#define M_ISTRIM    0x3fU
+#define V_ISTRIM(x) ((x) << S_ISTRIM)
+#define G_ISTRIM(x) (((x) >> S_ISTRIM) & M_ISTRIM)
+
+#define S_HALF1    7
+#define V_HALF1(x) ((x) << S_HALF1)
+#define F_HALF1    V_HALF1(1U)
+
+#define S_HALF2    6
+#define V_HALF2(x) ((x) << S_HALF2)
+#define F_HALF2    V_HALF2(1U)
+
+#define S_INTDAC    0
+#define M_INTDAC    0x3fU
+#define V_INTDAC(x) ((x) << S_INTDAC)
+#define G_INTDAC(x) (((x) >> S_INTDAC) & M_INTDAC)
+
+#define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL 0x32a8
+
+#define S_MINWDTH    5
+#define M_MINWDTH    0x1fU
+#define V_MINWDTH(x) ((x) << S_MINWDTH)
+#define G_MINWDTH(x) (((x) >> S_MINWDTH) & M_MINWDTH)
+
+#define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS 0x32ac
+
+#define S_T5SMQM    13
+#define M_T5SMQM    0x7U
+#define V_T5SMQM(x) ((x) << S_T5SMQM)
+#define G_T5SMQM(x) (((x) >> S_T5SMQM) & M_T5SMQM)
+
+#define S_T5SMQ    5
+#define M_T5SMQ    0xffU
+#define V_T5SMQ(x) ((x) << S_T5SMQ)
+#define G_T5SMQ(x) (((x) >> S_T5SMQ) & M_T5SMQ)
+
+#define S_T5EMMD    3
+#define M_T5EMMD    0x3U
+#define V_T5EMMD(x) ((x) << S_T5EMMD)
+#define G_T5EMMD(x) (((x) >> S_T5EMMD) & M_T5EMMD)
+
+#define S_T5EMBRDY    2
+#define V_T5EMBRDY(x) ((x) << S_T5EMBRDY)
+#define F_T5EMBRDY    V_T5EMBRDY(1U)
+
+#define S_T5EMBUMP    1
+#define V_T5EMBUMP(x) ((x) << S_T5EMBUMP)
+#define F_T5EMBUMP    V_T5EMBUMP(1U)
+
+#define S_T5EMEN    0
+#define V_T5EMEN(x) ((x) << S_T5EMEN)
+#define F_T5EMEN    V_T5EMEN(1U)
+
+#define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT 0x32b0
+
+#define S_EMF8    15
+#define V_EMF8(x) ((x) << S_EMF8)
+#define F_EMF8    V_EMF8(1U)
+
+#define S_EMCNT    4
+#define M_EMCNT    0xffU
+#define V_EMCNT(x) ((x) << S_EMCNT)
+#define G_EMCNT(x) (((x) >> S_EMCNT) & M_EMCNT)
+
+#define S_EMOFLO    2
+#define V_EMOFLO(x) ((x) << S_EMOFLO)
+#define F_EMOFLO    V_EMOFLO(1U)
+
+#define S_EMCRST    1
+#define V_EMCRST(x) ((x) << S_EMCRST)
+#define F_EMCRST    V_EMCRST(1U)
+
+#define S_EMCEN    0
+#define V_EMCEN(x) ((x) << S_EMCEN)
+#define F_EMCEN    V_EMCEN(1U)
+
+#define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x32b4
+
+#define S_SM2RDY    15
+#define V_SM2RDY(x) ((x) << S_SM2RDY)
+#define F_SM2RDY    V_SM2RDY(1U)
+
+#define S_SM2RST    14
+#define V_SM2RST(x) ((x) << S_SM2RST)
+#define F_SM2RST    V_SM2RST(1U)
+
+#define S_APDF    0
+#define M_APDF    0xfffU
+#define V_APDF(x) ((x) << S_APDF)
+#define G_APDF(x) (((x) >> S_APDF) & M_APDF)
+
+#define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x32b8
+
+#define S_SM0LEN    0
+#define M_SM0LEN    0x7fffU
+#define V_SM0LEN(x) ((x) << S_SM0LEN)
+#define G_SM0LEN(x) (((x) >> S_SM0LEN) & M_SM0LEN)
+
+#define A_MAC_PORT_RX_LINKA_DFE_TAP_ENABLE 0x32c0
+
+#define S_H_EN    1
+#define M_H_EN    0xfffU
+#define V_H_EN(x) ((x) << S_H_EN)
+#define G_H_EN(x) (((x) >> S_H_EN) & M_H_EN)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H1 0x32c4
+#define A_MAC_PORT_RX_LINKA_DFE_H2 0x32c8
+
+#define S_H2OSN_READWRITE    14
+#define V_H2OSN_READWRITE(x) ((x) << S_H2OSN_READWRITE)
+#define F_H2OSN_READWRITE    V_H2OSN_READWRITE(1U)
+
+#define S_H2OSN_READONLY    13
+#define V_H2OSN_READONLY(x) ((x) << S_H2OSN_READONLY)
+#define F_H2OSN_READONLY    V_H2OSN_READONLY(1U)
+
+#define S_H2ESN_READWRITE    6
+#define V_H2ESN_READWRITE(x) ((x) << S_H2ESN_READWRITE)
+#define F_H2ESN_READWRITE    V_H2ESN_READWRITE(1U)
+
+#define S_H2ESN_READONLY    5
+#define V_H2ESN_READONLY(x) ((x) << S_H2ESN_READONLY)
+#define F_H2ESN_READONLY    V_H2ESN_READONLY(1U)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H3 0x32cc
+
+#define S_H3OSN_READWRITE    13
+#define V_H3OSN_READWRITE(x) ((x) << S_H3OSN_READWRITE)
+#define F_H3OSN_READWRITE    V_H3OSN_READWRITE(1U)
+
+#define S_H3OSN_READONLY    12
+#define V_H3OSN_READONLY(x) ((x) << S_H3OSN_READONLY)
+#define F_H3OSN_READONLY    V_H3OSN_READONLY(1U)
+
+#define S_H3ESN_READWRITE    5
+#define V_H3ESN_READWRITE(x) ((x) << S_H3ESN_READWRITE)
+#define F_H3ESN_READWRITE    V_H3ESN_READWRITE(1U)
+
+#define S_H3ESN_READONLY    4
+#define V_H3ESN_READONLY(x) ((x) << S_H3ESN_READONLY)
+#define F_H3ESN_READONLY    V_H3ESN_READONLY(1U)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H4 0x32d0
+
+#define S_H4OGS    14
+#define M_H4OGS    0x3U
+#define V_H4OGS(x) ((x) << S_H4OGS)
+#define G_H4OGS(x) (((x) >> S_H4OGS) & M_H4OGS)
+
+#define S_H4OSN_READWRITE    13
+#define V_H4OSN_READWRITE(x) ((x) << S_H4OSN_READWRITE)
+#define F_H4OSN_READWRITE    V_H4OSN_READWRITE(1U)
+
+#define S_H4OSN_READONLY    12
+#define V_H4OSN_READONLY(x) ((x) << S_H4OSN_READONLY)
+#define F_H4OSN_READONLY    V_H4OSN_READONLY(1U)
+
+#define S_H4EGS    6
+#define M_H4EGS    0x3U
+#define V_H4EGS(x) ((x) << S_H4EGS)
+#define G_H4EGS(x) (((x) >> S_H4EGS) & M_H4EGS)
+
+#define S_H4ESN_READWRITE    5
+#define V_H4ESN_READWRITE(x) ((x) << S_H4ESN_READWRITE)
+#define F_H4ESN_READWRITE    V_H4ESN_READWRITE(1U)
+
+#define S_H4ESN_READONLY    4
+#define V_H4ESN_READONLY(x) ((x) << S_H4ESN_READONLY)
+#define F_H4ESN_READONLY    V_H4ESN_READONLY(1U)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H5 0x32d4
+
+#define S_H5OGS    14
+#define M_H5OGS    0x3U
+#define V_H5OGS(x) ((x) << S_H5OGS)
+#define G_H5OGS(x) (((x) >> S_H5OGS) & M_H5OGS)
+
+#define S_H5OSN_READWRITE    13
+#define V_H5OSN_READWRITE(x) ((x) << S_H5OSN_READWRITE)
+#define F_H5OSN_READWRITE    V_H5OSN_READWRITE(1U)
+
+#define S_H5OSN_READONLY    12
+#define V_H5OSN_READONLY(x) ((x) << S_H5OSN_READONLY)
+#define F_H5OSN_READONLY    V_H5OSN_READONLY(1U)
+
+#define S_H5EGS    6
+#define M_H5EGS    0x3U
+#define V_H5EGS(x) ((x) << S_H5EGS)
+#define G_H5EGS(x) (((x) >> S_H5EGS) & M_H5EGS)
+
+#define S_H5ESN_READWRITE    5
+#define V_H5ESN_READWRITE(x) ((x) << S_H5ESN_READWRITE)
+#define F_H5ESN_READWRITE    V_H5ESN_READWRITE(1U)
+
+#define S_H5ESN_READONLY    4
+#define V_H5ESN_READONLY(x) ((x) << S_H5ESN_READONLY)
+#define F_H5ESN_READONLY    V_H5ESN_READONLY(1U)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H6_AND_H7 0x32d8
+
+#define S_H7GS    14
+#define M_H7GS    0x3U
+#define V_H7GS(x) ((x) << S_H7GS)
+#define G_H7GS(x) (((x) >> S_H7GS) & M_H7GS)
+
+#define S_H7SN_READWRITE    13
+#define V_H7SN_READWRITE(x) ((x) << S_H7SN_READWRITE)
+#define F_H7SN_READWRITE    V_H7SN_READWRITE(1U)
+
+#define S_H7SN_READONLY    12
+#define V_H7SN_READONLY(x) ((x) << S_H7SN_READONLY)
+#define F_H7SN_READONLY    V_H7SN_READONLY(1U)
+
+#define S_H7MAG    8
+#define M_H7MAG    0xfU
+#define V_H7MAG(x) ((x) << S_H7MAG)
+#define G_H7MAG(x) (((x) >> S_H7MAG) & M_H7MAG)
+
+#define S_H6GS    6
+#define M_H6GS    0x3U
+#define V_H6GS(x) ((x) << S_H6GS)
+#define G_H6GS(x) (((x) >> S_H6GS) & M_H6GS)
+
+#define S_H6SN_READWRITE    5
+#define V_H6SN_READWRITE(x) ((x) << S_H6SN_READWRITE)
+#define F_H6SN_READWRITE    V_H6SN_READWRITE(1U)
+
+#define S_H6SN_READONLY    4
+#define V_H6SN_READONLY(x) ((x) << S_H6SN_READONLY)
+#define F_H6SN_READONLY    V_H6SN_READONLY(1U)
+
+#define S_H6MAG    0
+#define M_H6MAG    0xfU
+#define V_H6MAG(x) ((x) << S_H6MAG)
+#define G_H6MAG(x) (((x) >> S_H6MAG) & M_H6MAG)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H8_AND_H9 0x32dc
+
+#define S_H9GS    14
+#define M_H9GS    0x3U
+#define V_H9GS(x) ((x) << S_H9GS)
+#define G_H9GS(x) (((x) >> S_H9GS) & M_H9GS)
+
+#define S_H9SN_READWRITE    13
+#define V_H9SN_READWRITE(x) ((x) << S_H9SN_READWRITE)
+#define F_H9SN_READWRITE    V_H9SN_READWRITE(1U)
+
+#define S_H9SN_READONLY    12
+#define V_H9SN_READONLY(x) ((x) << S_H9SN_READONLY)
+#define F_H9SN_READONLY    V_H9SN_READONLY(1U)
+
+#define S_H9MAG    8
+#define M_H9MAG    0xfU
+#define V_H9MAG(x) ((x) << S_H9MAG)
+#define G_H9MAG(x) (((x) >> S_H9MAG) & M_H9MAG)
+
+#define S_H8GS    6
+#define M_H8GS    0x3U
+#define V_H8GS(x) ((x) << S_H8GS)
+#define G_H8GS(x) (((x) >> S_H8GS) & M_H8GS)
+
+#define S_H8SN_READWRITE    5
+#define V_H8SN_READWRITE(x) ((x) << S_H8SN_READWRITE)
+#define F_H8SN_READWRITE    V_H8SN_READWRITE(1U)
+
+#define S_H8SN_READONLY    4
+#define V_H8SN_READONLY(x) ((x) << S_H8SN_READONLY)
+#define F_H8SN_READONLY    V_H8SN_READONLY(1U)
+
+#define S_H8MAG    0
+#define M_H8MAG    0xfU
+#define V_H8MAG(x) ((x) << S_H8MAG)
+#define G_H8MAG(x) (((x) >> S_H8MAG) & M_H8MAG)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H10_AND_H11 0x32e0
+
+#define S_H11GS    14
+#define M_H11GS    0x3U
+#define V_H11GS(x) ((x) << S_H11GS)
+#define G_H11GS(x) (((x) >> S_H11GS) & M_H11GS)
+
+#define S_H11SN_READWRITE    13
+#define V_H11SN_READWRITE(x) ((x) << S_H11SN_READWRITE)
+#define F_H11SN_READWRITE    V_H11SN_READWRITE(1U)
+
+#define S_H11SN_READONLY    12
+#define V_H11SN_READONLY(x) ((x) << S_H11SN_READONLY)
+#define F_H11SN_READONLY    V_H11SN_READONLY(1U)
+
+#define S_H11MAG    8
+#define M_H11MAG    0xfU
+#define V_H11MAG(x) ((x) << S_H11MAG)
+#define G_H11MAG(x) (((x) >> S_H11MAG) & M_H11MAG)
+
+#define S_H10GS    6
+#define M_H10GS    0x3U
+#define V_H10GS(x) ((x) << S_H10GS)
+#define G_H10GS(x) (((x) >> S_H10GS) & M_H10GS)
+
+#define S_H10SN_READWRITE    5
+#define V_H10SN_READWRITE(x) ((x) << S_H10SN_READWRITE)
+#define F_H10SN_READWRITE    V_H10SN_READWRITE(1U)
+
+#define S_H10SN_READONLY    4
+#define V_H10SN_READONLY(x) ((x) << S_H10SN_READONLY)
+#define F_H10SN_READONLY    V_H10SN_READONLY(1U)
+
+#define S_H10MAG    0
+#define M_H10MAG    0xfU
+#define V_H10MAG(x) ((x) << S_H10MAG)
+#define G_H10MAG(x) (((x) >> S_H10MAG) & M_H10MAG)
+
+#define A_MAC_PORT_RX_LINKA_DFE_H12 0x32e4
+
+#define S_H12GS    6
+#define M_H12GS    0x3U
+#define V_H12GS(x) ((x) << S_H12GS)
+#define G_H12GS(x) (((x) >> S_H12GS) & M_H12GS)
+
+#define S_H12SN_READWRITE    5
+#define V_H12SN_READWRITE(x) ((x) << S_H12SN_READWRITE)
+#define F_H12SN_READWRITE    V_H12SN_READWRITE(1U)
+
+#define S_H12SN_READONLY    4
+#define V_H12SN_READONLY(x) ((x) << S_H12SN_READONLY)
+#define F_H12SN_READONLY    V_H12SN_READONLY(1U)
+
+#define S_H12MAG    0
+#define M_H12MAG    0xfU
+#define V_H12MAG(x) ((x) << S_H12MAG)
+#define G_H12MAG(x) (((x) >> S_H12MAG) & M_H12MAG)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2 0x32f8
+
+#define S_DFEDACLSSD    6
+#define V_DFEDACLSSD(x) ((x) << S_DFEDACLSSD)
+#define F_DFEDACLSSD    V_DFEDACLSSD(1U)
+
+#define S_SDLSSD    5
+#define V_SDLSSD(x) ((x) << S_SDLSSD)
+#define F_SDLSSD    V_SDLSSD(1U)
+
+#define S_DFEOBSBIAS    4
+#define V_DFEOBSBIAS(x) ((x) << S_DFEOBSBIAS)
+#define F_DFEOBSBIAS    V_DFEOBSBIAS(1U)
+
+#define S_GBOFSTLSSD    3
+#define V_GBOFSTLSSD(x) ((x) << S_GBOFSTLSSD)
+#define F_GBOFSTLSSD    V_GBOFSTLSSD(1U)
+
+#define S_RXDOBS    2
+#define V_RXDOBS(x) ((x) << S_RXDOBS)
+#define F_RXDOBS    V_RXDOBS(1U)
+
+#define S_ACJZPT    1
+#define V_ACJZPT(x) ((x) << S_ACJZPT)
+#define F_ACJZPT    V_ACJZPT(1U)
+
+#define S_ACJZNT    0
+#define V_ACJZNT(x) ((x) << S_ACJZNT)
+#define F_ACJZNT    V_ACJZNT(1U)
+
+#define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1 0x32fc
+
+#define S_PHSLOCK    10
+#define V_PHSLOCK(x) ((x) << S_PHSLOCK)
+#define F_PHSLOCK    V_PHSLOCK(1U)
+
+#define S_TESTMODE    9
+#define V_TESTMODE(x) ((x) << S_TESTMODE)
+#define F_TESTMODE    V_TESTMODE(1U)
+
+#define S_CALMODE    8
+#define V_CALMODE(x) ((x) << S_CALMODE)
+#define F_CALMODE    V_CALMODE(1U)
+
+#define S_AMPSEL    7
+#define V_AMPSEL(x) ((x) << S_AMPSEL)
+#define F_AMPSEL    V_AMPSEL(1U)
+
+#define S_WHICHNRZ    6
+#define V_WHICHNRZ(x) ((x) << S_WHICHNRZ)
+#define F_WHICHNRZ    V_WHICHNRZ(1U)
+
+#define S_BANKA    5
+#define V_BANKA(x) ((x) << S_BANKA)
+#define F_BANKA    V_BANKA(1U)
+
+#define S_BANKB    4
+#define V_BANKB(x) ((x) << S_BANKB)
+#define F_BANKB    V_BANKB(1U)
+
+#define S_ACJPDP    3
+#define V_ACJPDP(x) ((x) << S_ACJPDP)
+#define F_ACJPDP    V_ACJPDP(1U)
+
+#define S_ACJPDN    2
+#define V_ACJPDN(x) ((x) << S_ACJPDN)
+#define F_ACJPDN    V_ACJPDN(1U)
+
+#define S_LSSDT    1
+#define V_LSSDT(x) ((x) << S_LSSDT)
+#define F_LSSDT    V_LSSDT(1U)
+
+#define S_MTHOLD    0
+#define V_MTHOLD(x) ((x) << S_MTHOLD)
+#define F_MTHOLD    V_MTHOLD(1U)
+
+#define A_MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE 0x3300
+#define A_MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL 0x3304
+#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL 0x3308
+#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL 0x330c
+#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1 0x3310
+#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2 0x3314
+#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3318
+#define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x331c
+#define A_MAC_PORT_RX_LINKB_DFE_CONTROL 0x3320
+#define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1 0x3324
+#define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2 0x3328
+#define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1 0x332c
+#define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2 0x3330
+#define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3 0x3334
+#define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1 0x3338
+#define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3 0x3340
+#define A_MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN 0x3348
+#define A_MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ 0x334c
+#define A_MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL 0x3350
+#define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x335c
+#define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3360
+#define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3364
+#define A_MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3370
+#define A_MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC 0x3374
+#define A_MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS 0x3378
+#define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1 0x337c
+#define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2 0x3380
+#define A_MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2 0x3384
+#define A_MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2 0x3388
+#define A_MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4 0x338c
+#define A_MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4 0x3390
+#define A_MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET 0x3394
+#define A_MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL 0x3398
+#define A_MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL 0x339c
+#define A_MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH 0x33a0
+#define A_MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET 0x33a4
+#define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL 0x33a8
+#define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS 0x33ac
+#define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT 0x33b0
+#define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x33b4
+#define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x33b8
+#define A_MAC_PORT_RX_LINKB_DFE_TAP_ENABLE 0x33c0
+#define A_MAC_PORT_RX_LINKB_DFE_H1 0x33c4
+#define A_MAC_PORT_RX_LINKB_DFE_H2 0x33c8
+#define A_MAC_PORT_RX_LINKB_DFE_H3 0x33cc
+#define A_MAC_PORT_RX_LINKB_DFE_H4 0x33d0
+#define A_MAC_PORT_RX_LINKB_DFE_H5 0x33d4
+#define A_MAC_PORT_RX_LINKB_DFE_H6_AND_H7 0x33d8
+#define A_MAC_PORT_RX_LINKB_DFE_H8_AND_H9 0x33dc
+#define A_MAC_PORT_RX_LINKB_DFE_H10_AND_H11 0x33e0
+#define A_MAC_PORT_RX_LINKB_DFE_H12 0x33e4
+#define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2 0x33f8
+#define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1 0x33fc
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE 0x3400
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL 0x3404
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL 0x3408
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL 0x340c
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3410
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3414
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3418
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x341c
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT 0x3420
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT 0x3424
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT 0x3428
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE 0x3430
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_POLARITY 0x3434
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3438
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x343c
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3440
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3444
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3448
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3460
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3464
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3468
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3470
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3474
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3478
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x347c
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3480
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3484
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3488
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL 0x348c
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE 0x3490
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED 0x3494
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT 0x3498
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL 0x349c
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4 0x34f0
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3 0x34f4
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2 0x34f8
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1 0x34fc
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE 0x3500
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL 0x3504
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL 0x3508
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL 0x350c
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3510
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3514
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3518
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x351c
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT 0x3520
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT 0x3524
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT 0x3528
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE 0x3530
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_POLARITY 0x3534
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3538
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x353c
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3540
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3544
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3548
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3560
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3564
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3568
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3570
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3574
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3578
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x357c
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3580
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3584
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3588
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL 0x358c
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE 0x3590
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED 0x3594
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT 0x3598
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL 0x359c
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4 0x35f0
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3 0x35f4
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2 0x35f8
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1 0x35fc
+#define A_MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE 0x3600
+#define A_MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL 0x3604
+#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL 0x3608
+#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL 0x360c
+#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1 0x3610
+#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2 0x3614
+#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3618
+#define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x361c
+#define A_MAC_PORT_RX_LINKC_DFE_CONTROL 0x3620
+#define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1 0x3624
+#define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2 0x3628
+#define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1 0x362c
+#define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2 0x3630
+#define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3 0x3634
+#define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1 0x3638
+#define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3 0x3640
+#define A_MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN 0x3648
+#define A_MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ 0x364c
+#define A_MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL 0x3650
+#define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x365c
+#define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3660
+#define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3664
+#define A_MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3670
+#define A_MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC 0x3674
+#define A_MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS 0x3678
+#define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1 0x367c
+#define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2 0x3680
+#define A_MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2 0x3684
+#define A_MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2 0x3688
+#define A_MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4 0x368c
+#define A_MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4 0x3690
+#define A_MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET 0x3694
+#define A_MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL 0x3698
+#define A_MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL 0x369c
+#define A_MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH 0x36a0
+#define A_MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET 0x36a4
+#define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL 0x36a8
+#define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS 0x36ac
+#define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT 0x36b0
+#define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x36b4
+#define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x36b8
+#define A_MAC_PORT_RX_LINKC_DFE_TAP_ENABLE 0x36c0
+#define A_MAC_PORT_RX_LINKC_DFE_H1 0x36c4
+#define A_MAC_PORT_RX_LINKC_DFE_H2 0x36c8
+#define A_MAC_PORT_RX_LINKC_DFE_H3 0x36cc
+#define A_MAC_PORT_RX_LINKC_DFE_H4 0x36d0
+#define A_MAC_PORT_RX_LINKC_DFE_H5 0x36d4
+#define A_MAC_PORT_RX_LINKC_DFE_H6_AND_H7 0x36d8
+#define A_MAC_PORT_RX_LINKC_DFE_H8_AND_H9 0x36dc
+#define A_MAC_PORT_RX_LINKC_DFE_H10_AND_H11 0x36e0
+#define A_MAC_PORT_RX_LINKC_DFE_H12 0x36e4
+#define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2 0x36f8
+#define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1 0x36fc
+#define A_MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE 0x3700
+#define A_MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL 0x3704
+#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL 0x3708
+#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL 0x370c
+#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1 0x3710
+#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2 0x3714
+#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3718
+#define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x371c
+#define A_MAC_PORT_RX_LINKD_DFE_CONTROL 0x3720
+#define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1 0x3724
+#define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2 0x3728
+#define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1 0x372c
+#define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2 0x3730
+#define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3 0x3734
+#define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1 0x3738
+#define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3 0x3740
+#define A_MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN 0x3748
+#define A_MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ 0x374c
+#define A_MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL 0x3750
+#define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x375c
+#define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3760
+#define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3764
+#define A_MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3770
+#define A_MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC 0x3774
+#define A_MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS 0x3778
+#define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1 0x377c
+#define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2 0x3780
+#define A_MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2 0x3784
+#define A_MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2 0x3788
+#define A_MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4 0x378c
+#define A_MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4 0x3790
+#define A_MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET 0x3794
+#define A_MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL 0x3798
+#define A_MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL 0x379c
+#define A_MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH 0x37a0
+#define A_MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET 0x37a4
+#define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL 0x37a8
+#define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS 0x37ac
+#define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT 0x37b0
+#define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x37b4
+#define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x37b8
+#define A_MAC_PORT_RX_LINKD_DFE_TAP_ENABLE 0x37c0
+#define A_MAC_PORT_RX_LINKD_DFE_H1 0x37c4
+#define A_MAC_PORT_RX_LINKD_DFE_H2 0x37c8
+#define A_MAC_PORT_RX_LINKD_DFE_H3 0x37cc
+#define A_MAC_PORT_RX_LINKD_DFE_H4 0x37d0
+#define A_MAC_PORT_RX_LINKD_DFE_H5 0x37d4
+#define A_MAC_PORT_RX_LINKD_DFE_H6_AND_H7 0x37d8
+#define A_MAC_PORT_RX_LINKD_DFE_H8_AND_H9 0x37dc
+#define A_MAC_PORT_RX_LINKD_DFE_H10_AND_H11 0x37e0
+#define A_MAC_PORT_RX_LINKD_DFE_H12 0x37e4
+#define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2 0x37f8
+#define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1 0x37fc
+#define A_MAC_PORT_ANALOG_TEST_MUX 0x3814
+#define A_MAC_PORT_BANDGAP_CONTROL 0x382c
+
+#define S_T5BGCTL    0
+#define M_T5BGCTL    0xfU
+#define V_T5BGCTL(x) ((x) << S_T5BGCTL)
+#define G_T5BGCTL(x) (((x) >> S_T5BGCTL) & M_T5BGCTL)
+
+#define A_MAC_PORT_RESISTOR_CALIBRATION_CONTROL 0x3880
+
+#define S_RCCTL1    5
+#define V_RCCTL1(x) ((x) << S_RCCTL1)
+#define F_RCCTL1    V_RCCTL1(1U)
+
+#define S_RCCTL0    4
+#define V_RCCTL0(x) ((x) << S_RCCTL0)
+#define F_RCCTL0    V_RCCTL0(1U)
+
+#define S_RCAMP1    3
+#define V_RCAMP1(x) ((x) << S_RCAMP1)
+#define F_RCAMP1    V_RCAMP1(1U)
+
+#define S_RCAMP0    2
+#define V_RCAMP0(x) ((x) << S_RCAMP0)
+#define F_RCAMP0    V_RCAMP0(1U)
+
+#define S_RCAMPEN    1
+#define V_RCAMPEN(x) ((x) << S_RCAMPEN)
+#define F_RCAMPEN    V_RCAMPEN(1U)
+
+#define S_RCRST    0
+#define V_RCRST(x) ((x) << S_RCRST)
+#define F_RCRST    V_RCRST(1U)
+
+#define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_1 0x3884
+
+#define S_RCERR    1
+#define V_RCERR(x) ((x) << S_RCERR)
+#define F_RCERR    V_RCERR(1U)
+
+#define S_RCCOMP    0
+#define V_RCCOMP(x) ((x) << S_RCCOMP)
+#define F_RCCOMP    V_RCCOMP(1U)
+
+#define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_2 0x3888
+
+#define S_RESREG2    0
+#define M_RESREG2    0xffU
+#define V_RESREG2(x) ((x) << S_RESREG2)
+#define G_RESREG2(x) (((x) >> S_RESREG2) & M_RESREG2)
+
+#define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_3 0x388c
+
+#define S_RESREG3    0
+#define M_RESREG3    0xffU
+#define V_RESREG3(x) ((x) << S_RESREG3)
+#define G_RESREG3(x) (((x) >> S_RESREG3) & M_RESREG3)
+
+#define A_MAC_PORT_MACRO_TEST_CONTROL_6 0x38e8
+
+#define S_LBIST    7
+#define V_LBIST(x) ((x) << S_LBIST)
+#define F_LBIST    V_LBIST(1U)
+
+#define S_LOGICTEST    6
+#define V_LOGICTEST(x) ((x) << S_LOGICTEST)
+#define F_LOGICTEST    V_LOGICTEST(1U)
+
+#define S_MAVDHI    5
+#define V_MAVDHI(x) ((x) << S_MAVDHI)
+#define F_MAVDHI    V_MAVDHI(1U)
+
+#define S_AUXEN    4
+#define V_AUXEN(x) ((x) << S_AUXEN)
+#define F_AUXEN    V_AUXEN(1U)
+
+#define S_JTAGMD    3
+#define V_JTAGMD(x) ((x) << S_JTAGMD)
+#define F_JTAGMD    V_JTAGMD(1U)
+
+#define S_RXACMODE    2
+#define V_RXACMODE(x) ((x) << S_RXACMODE)
+#define F_RXACMODE    V_RXACMODE(1U)
+
+#define S_HSSACJPC    1
+#define V_HSSACJPC(x) ((x) << S_HSSACJPC)
+#define F_HSSACJPC    V_HSSACJPC(1U)
+
+#define S_HSSACJAC    0
+#define V_HSSACJAC(x) ((x) << S_HSSACJAC)
+#define F_HSSACJAC    V_HSSACJAC(1U)
+
+#define A_MAC_PORT_MACRO_TEST_CONTROL_5 0x38ec
+
+#define S_REFVALIDD    6
+#define V_REFVALIDD(x) ((x) << S_REFVALIDD)
+#define F_REFVALIDD    V_REFVALIDD(1U)
+
+#define S_REFVALIDC    5
+#define V_REFVALIDC(x) ((x) << S_REFVALIDC)
+#define F_REFVALIDC    V_REFVALIDC(1U)
+
+#define S_REFVALIDB    4
+#define V_REFVALIDB(x) ((x) << S_REFVALIDB)
+#define F_REFVALIDB    V_REFVALIDB(1U)
+
+#define S_REFVALIDA    3
+#define V_REFVALIDA(x) ((x) << S_REFVALIDA)
+#define F_REFVALIDA    V_REFVALIDA(1U)
+
+#define S_REFSELRESET    2
+#define V_REFSELRESET(x) ((x) << S_REFSELRESET)
+#define F_REFSELRESET    V_REFSELRESET(1U)
+
+#define S_SOFTRESET    1
+#define V_SOFTRESET(x) ((x) << S_SOFTRESET)
+#define F_SOFTRESET    V_SOFTRESET(1U)
+
+#define S_MACROTEST    0
+#define V_MACROTEST(x) ((x) << S_MACROTEST)
+#define F_MACROTEST    V_MACROTEST(1U)
+
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE 0x3900
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL 0x3904
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL 0x3908
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL 0x390c
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3910
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3914
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3918
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x391c
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT 0x3920
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT 0x3924
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT 0x3928
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE 0x3930
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY 0x3934
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3938
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x393c
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3940
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3944
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3948
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3960
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3964
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3968
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3970
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3974
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3978
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x397c
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3980
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3984
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3988
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL 0x398c
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE 0x3990
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED 0x3994
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT 0x3998
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL 0x399c
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4 0x39f0
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3 0x39f4
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2 0x39f8
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1 0x39fc
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE 0x3a00
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL 0x3a04
+#define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL 0x3a08
+#define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL 0x3a0c
+#define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1 0x3a10
+#define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2 0x3a14
+#define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3a18
+#define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x3a1c
+#define A_MAC_PORT_RX_LINK_BCST_DFE_CONTROL 0x3a20
+#define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1 0x3a24
+#define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2 0x3a28
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1 0x3a2c
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2 0x3a30
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3 0x3a34
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1 0x3a38
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_3 0x3a40
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN 0x3a48
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN_AND_DACAZ 0x3a4c
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL 0x3a50
+#define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x3a5c
+#define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3a60
+#define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3a64
+#define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3a70
+#define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC 0x3a74
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS 0x3a78
+#define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1 0x3a7c
+#define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2 0x3a80
+#define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN1_EVN2 0x3a84
+#define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD1_ODD2 0x3a88
+#define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN3_EVN4 0x3a8c
+#define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD3_ODD4 0x3a90
+#define A_MAC_PORT_RX_LINK_BCST_DFE_E0_AND_E1_OFFSET 0x3a94
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL 0x3a98
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL 0x3a9c
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH 0x3aa0
+#define A_MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET 0x3aa4
+#define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL 0x3aa8
+#define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS 0x3aac
+#define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT 0x3ab0
+#define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x3ab4
+#define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x3ab8
+#define A_MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE 0x3ac0
+#define A_MAC_PORT_RX_LINK_BCST_DFE_H1 0x3ac4
+#define A_MAC_PORT_RX_LINK_BCST_DFE_H2 0x3ac8
+#define A_MAC_PORT_RX_LINK_BCST_DFE_H3 0x3acc
+#define A_MAC_PORT_RX_LINK_BCST_DFE_H4 0x3ad0
+#define A_MAC_PORT_RX_LINK_BCST_DFE_H5 0x3ad4
+#define A_MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7 0x3ad8
+#define A_MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9 0x3adc
+#define A_MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11 0x3ae0
+#define A_MAC_PORT_RX_LINK_BCST_DFE_H12 0x3ae4
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_2 0x3af8
+#define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1 0x3afc
+#define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0 0x3b00
+#define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1 0x3b04
+#define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2 0x3b08
+#define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3 0x3b0c
+#define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4 0x3b10
+#define A_MAC_PORT_PLLA_CHARGE_PUMP_CONTROL 0x3b28
+
+#define S_T5CPISEL    0
+#define M_T5CPISEL    0x7U
+#define V_T5CPISEL(x) ((x) << S_T5CPISEL)
+#define G_T5CPISEL(x) (((x) >> S_T5CPISEL) & M_T5CPISEL)
+
+#define A_MAC_PORT_PLLA_PCLK_CONTROL 0x3b3c
+
+#define S_SPEDIV    3
+#define M_SPEDIV    0x1fU
+#define V_SPEDIV(x) ((x) << S_SPEDIV)
+#define G_SPEDIV(x) (((x) >> S_SPEDIV) & M_SPEDIV)
+
+#define S_PCKSEL    0
+#define M_PCKSEL    0x7U
+#define V_PCKSEL(x) ((x) << S_PCKSEL)
+#define G_PCKSEL(x) (((x) >> S_PCKSEL) & M_PCKSEL)
+
+#define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL 0x3b40
+
+#define S_EMIL    2
+#define V_EMIL(x) ((x) << S_EMIL)
+#define F_EMIL    V_EMIL(1U)
+
+#define S_EMID    1
+#define V_EMID(x) ((x) << S_EMID)
+#define F_EMID    V_EMID(1U)
+
+#define S_EMIS    0
+#define V_EMIS(x) ((x) << S_EMIS)
+#define F_EMIS    V_EMIS(1U)
+
+#define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1 0x3b44
+
+#define S_EMIL1    0
+#define M_EMIL1    0xffU
+#define V_EMIL1(x) ((x) << S_EMIL1)
+#define G_EMIL1(x) (((x) >> S_EMIL1) & M_EMIL1)
+
+#define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2 0x3b48
+
+#define S_EMIL2    0
+#define M_EMIL2    0xffU
+#define V_EMIL2(x) ((x) << S_EMIL2)
+#define G_EMIL2(x) (((x) >> S_EMIL2) & M_EMIL2)
+
+#define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3 0x3b4c
+
+#define S_EMIL3    0
+#define M_EMIL3    0xffU
+#define V_EMIL3(x) ((x) << S_EMIL3)
+#define G_EMIL3(x) (((x) >> S_EMIL3) & M_EMIL3)
+
+#define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4 0x3b50
+
+#define S_EMIL4    0
+#define M_EMIL4    0xffU
+#define V_EMIL4(x) ((x) << S_EMIL4)
+#define G_EMIL4(x) (((x) >> S_EMIL4) & M_EMIL4)
+
+#define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_4 0x3bf0
+
+#define S_VBST    1
+#define M_VBST    0x7U
+#define V_VBST(x) ((x) << S_VBST)
+#define G_VBST(x) (((x) >> S_VBST) & M_VBST)
+
+#define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_3 0x3bf4
+
+#define S_RESYNC    6
+#define V_RESYNC(x) ((x) << S_RESYNC)
+#define F_RESYNC    V_RESYNC(1U)
+
+#define S_RXCLKSEL    5
+#define V_RXCLKSEL(x) ((x) << S_RXCLKSEL)
+#define F_RXCLKSEL    V_RXCLKSEL(1U)
+
+#define S_FRCBAND    4
+#define V_FRCBAND(x) ((x) << S_FRCBAND)
+#define F_FRCBAND    V_FRCBAND(1U)
+
+#define S_PLLBYP    3
+#define V_PLLBYP(x) ((x) << S_PLLBYP)
+#define F_PLLBYP    V_PLLBYP(1U)
+
+#define S_PDWNP    2
+#define V_PDWNP(x) ((x) << S_PDWNP)
+#define F_PDWNP    V_PDWNP(1U)
+
+#define S_VCOSEL    1
+#define V_VCOSEL(x) ((x) << S_VCOSEL)
+#define F_VCOSEL    V_VCOSEL(1U)
+
+#define S_DIVSEL8    0
+#define V_DIVSEL8(x) ((x) << S_DIVSEL8)
+#define F_DIVSEL8    V_DIVSEL8(1U)
+
+#define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_2 0x3bf8
+
+#define S_DIVSEL    0
+#define M_DIVSEL    0xffU
+#define V_DIVSEL(x) ((x) << S_DIVSEL)
+#define G_DIVSEL(x) (((x) >> S_DIVSEL) & M_DIVSEL)
+
+#define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_1 0x3bfc
+
+#define S_CONFIG    0
+#define M_CONFIG    0xffU
+#define V_CONFIG(x) ((x) << S_CONFIG)
+#define G_CONFIG(x) (((x) >> S_CONFIG) & M_CONFIG)
+
+#define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0 0x3c00
+#define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1 0x3c04
+#define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2 0x3c08
+#define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3 0x3c0c
+#define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4 0x3c10
+#define A_MAC_PORT_PLLB_CHARGE_PUMP_CONTROL 0x3c28
+#define A_MAC_PORT_PLLB_PCLK_CONTROL 0x3c3c
+#define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL 0x3c40
+#define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1 0x3c44
+#define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2 0x3c48
+#define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3 0x3c4c
+#define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4 0x3c50
+#define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_4 0x3cf0
+#define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_3 0x3cf4
+#define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_2 0x3cf8
+#define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_1 0x3cfc
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
+
+#define S_STEP    0
+#define M_STEP    0x7U
+#define V_STEP(x) ((x) << S_STEP)
+#define G_STEP(x) (((x) >> S_STEP) & M_STEP)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
+
+#define S_C0INIT    0
+#define M_C0INIT    0x1fU
+#define V_C0INIT(x) ((x) << S_C0INIT)
+#define G_C0INIT(x) (((x) >> S_C0INIT) & M_C0INIT)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
+
+#define S_C0MAX    8
+#define M_C0MAX    0x1fU
+#define V_C0MAX(x) ((x) << S_C0MAX)
+#define G_C0MAX(x) (((x) >> S_C0MAX) & M_C0MAX)
+
+#define S_C0MIN    0
+#define M_C0MIN    0x1fU
+#define V_C0MIN(x) ((x) << S_C0MIN)
+#define G_C0MIN(x) (((x) >> S_C0MIN) & M_C0MIN)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
+
+#define S_C1INIT    0
+#define M_C1INIT    0x7fU
+#define V_C1INIT(x) ((x) << S_C1INIT)
+#define G_C1INIT(x) (((x) >> S_C1INIT) & M_C1INIT)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
+
+#define S_C1MAX    8
+#define M_C1MAX    0x7fU
+#define V_C1MAX(x) ((x) << S_C1MAX)
+#define G_C1MAX(x) (((x) >> S_C1MAX) & M_C1MAX)
+
+#define S_C1MIN    0
+#define M_C1MIN    0x7fU
+#define V_C1MIN(x) ((x) << S_C1MIN)
+#define G_C1MIN(x) (((x) >> S_C1MIN) & M_C1MIN)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
+
+#define S_C2INIT    0
+#define M_C2INIT    0x3fU
+#define V_C2INIT(x) ((x) << S_C2INIT)
+#define G_C2INIT(x) (((x) >> S_C2INIT) & M_C2INIT)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
+
+#define S_C2MAX    8
+#define M_C2MAX    0x3fU
+#define V_C2MAX(x) ((x) << S_C2MAX)
+#define G_C2MAX(x) (((x) >> S_C2MAX) & M_C2MAX)
+
+#define S_C2MIN    0
+#define M_C2MIN    0x3fU
+#define V_C2MIN(x) ((x) << S_C2MIN)
+#define G_C2MIN(x) (((x) >> S_C2MIN) & M_C2MIN)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
+
+#define S_VMMAX    0
+#define M_VMMAX    0x7fU
+#define V_VMMAX(x) ((x) << S_VMMAX)
+#define G_VMMAX(x) (((x) >> S_VMMAX) & M_VMMAX)
+
+#define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
+
+#define S_V2MIN    0
+#define M_V2MIN    0x7fU
+#define V_V2MIN(x) ((x) << S_V2MIN)
+#define G_V2MIN(x) (((x) >> S_V2MIN) & M_V2MIN)
+
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
+#define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
+#define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
+#define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
+#define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
+
+/* registers for module MC_0 */
+#define MC_0_BASE_ADDR 0x40000
+
+#define A_MC_UPCTL_SCFG 0x40000
+
+#define S_BBFLAGS_TIMING    8
+#define M_BBFLAGS_TIMING    0xfU
+#define V_BBFLAGS_TIMING(x) ((x) << S_BBFLAGS_TIMING)
+#define G_BBFLAGS_TIMING(x) (((x) >> S_BBFLAGS_TIMING) & M_BBFLAGS_TIMING)
+
+#define S_NFIFO_NIF1_DIS    6
+#define V_NFIFO_NIF1_DIS(x) ((x) << S_NFIFO_NIF1_DIS)
+#define F_NFIFO_NIF1_DIS    V_NFIFO_NIF1_DIS(1U)
+
+#define A_MC_UPCTL_SCTL 0x40004
+#define A_MC_UPCTL_STAT 0x40008
+
+#define S_LP_TRIG    4
+#define M_LP_TRIG    0x7U
+#define V_LP_TRIG(x) ((x) << S_LP_TRIG)
+#define G_LP_TRIG(x) (((x) >> S_LP_TRIG) & M_LP_TRIG)
+
+#define A_MC_UPCTL_INTRSTAT 0x4000c
+
+#define S_PARITY_INTR    1
+#define V_PARITY_INTR(x) ((x) << S_PARITY_INTR)
+#define F_PARITY_INTR    V_PARITY_INTR(1U)
+
+#define S_ECC_INTR    0
+#define V_ECC_INTR(x) ((x) << S_ECC_INTR)
+#define F_ECC_INTR    V_ECC_INTR(1U)
+
+#define A_MC_UPCTL_MCMD 0x40040
+
+#define S_CMD_OPCODE0    0
+#define M_CMD_OPCODE0    0xfU
+#define V_CMD_OPCODE0(x) ((x) << S_CMD_OPCODE0)
+#define G_CMD_OPCODE0(x) (((x) >> S_CMD_OPCODE0) & M_CMD_OPCODE0)
+
+#define A_MC_UPCTL_POWCTL 0x40044
+#define A_MC_UPCTL_POWSTAT 0x40048
+#define A_MC_UPCTL_CMDTSTAT 0x4004c
+
+#define S_CMD_TSTAT    0
+#define V_CMD_TSTAT(x) ((x) << S_CMD_TSTAT)
+#define F_CMD_TSTAT    V_CMD_TSTAT(1U)
+
+#define A_MC_UPCTL_CMDTSTATEN 0x40050
+
+#define S_CMD_TSTAT_EN    0
+#define V_CMD_TSTAT_EN(x) ((x) << S_CMD_TSTAT_EN)
+#define F_CMD_TSTAT_EN    V_CMD_TSTAT_EN(1U)
+
+#define A_MC_UPCTL_MRRCFG0 0x40060
+
+#define S_MRR_BYTE_SEL    0
+#define M_MRR_BYTE_SEL    0xfU
+#define V_MRR_BYTE_SEL(x) ((x) << S_MRR_BYTE_SEL)
+#define G_MRR_BYTE_SEL(x) (((x) >> S_MRR_BYTE_SEL) & M_MRR_BYTE_SEL)
+
+#define A_MC_UPCTL_MRRSTAT0 0x40064
+
+#define S_MRRSTAT_BEAT3    24
+#define M_MRRSTAT_BEAT3    0xffU
+#define V_MRRSTAT_BEAT3(x) ((x) << S_MRRSTAT_BEAT3)
+#define G_MRRSTAT_BEAT3(x) (((x) >> S_MRRSTAT_BEAT3) & M_MRRSTAT_BEAT3)
+
+#define S_MRRSTAT_BEAT2    16
+#define M_MRRSTAT_BEAT2    0xffU
+#define V_MRRSTAT_BEAT2(x) ((x) << S_MRRSTAT_BEAT2)
+#define G_MRRSTAT_BEAT2(x) (((x) >> S_MRRSTAT_BEAT2) & M_MRRSTAT_BEAT2)
+
+#define S_MRRSTAT_BEAT1    8
+#define M_MRRSTAT_BEAT1    0xffU
+#define V_MRRSTAT_BEAT1(x) ((x) << S_MRRSTAT_BEAT1)
+#define G_MRRSTAT_BEAT1(x) (((x) >> S_MRRSTAT_BEAT1) & M_MRRSTAT_BEAT1)
+
+#define S_MRRSTAT_BEAT0    0
+#define M_MRRSTAT_BEAT0    0xffU
+#define V_MRRSTAT_BEAT0(x) ((x) << S_MRRSTAT_BEAT0)
+#define G_MRRSTAT_BEAT0(x) (((x) >> S_MRRSTAT_BEAT0) & M_MRRSTAT_BEAT0)
+
+#define A_MC_UPCTL_MRRSTAT1 0x40068
+
+#define S_MRRSTAT_BEAT7    24
+#define M_MRRSTAT_BEAT7    0xffU
+#define V_MRRSTAT_BEAT7(x) ((x) << S_MRRSTAT_BEAT7)
+#define G_MRRSTAT_BEAT7(x) (((x) >> S_MRRSTAT_BEAT7) & M_MRRSTAT_BEAT7)
+
+#define S_MRRSTAT_BEAT6    16
+#define M_MRRSTAT_BEAT6    0xffU
+#define V_MRRSTAT_BEAT6(x) ((x) << S_MRRSTAT_BEAT6)
+#define G_MRRSTAT_BEAT6(x) (((x) >> S_MRRSTAT_BEAT6) & M_MRRSTAT_BEAT6)
+
+#define S_MRRSTAT_BEAT5    8
+#define M_MRRSTAT_BEAT5    0xffU
+#define V_MRRSTAT_BEAT5(x) ((x) << S_MRRSTAT_BEAT5)
+#define G_MRRSTAT_BEAT5(x) (((x) >> S_MRRSTAT_BEAT5) & M_MRRSTAT_BEAT5)
+
+#define S_MRRSTAT_BEAT4    0
+#define M_MRRSTAT_BEAT4    0xffU
+#define V_MRRSTAT_BEAT4(x) ((x) << S_MRRSTAT_BEAT4)
+#define G_MRRSTAT_BEAT4(x) (((x) >> S_MRRSTAT_BEAT4) & M_MRRSTAT_BEAT4)
+
+#define A_MC_UPCTL_MCFG1 0x4007c
+
+#define S_HW_EXIT_IDLE_EN    31
+#define V_HW_EXIT_IDLE_EN(x) ((x) << S_HW_EXIT_IDLE_EN)
+#define F_HW_EXIT_IDLE_EN    V_HW_EXIT_IDLE_EN(1U)
+
+#define S_HW_IDLE    16
+#define M_HW_IDLE    0xffU
+#define V_HW_IDLE(x) ((x) << S_HW_IDLE)
+#define G_HW_IDLE(x) (((x) >> S_HW_IDLE) & M_HW_IDLE)
+
+#define S_SR_IDLE    0
+#define M_SR_IDLE    0xffU
+#define V_SR_IDLE(x) ((x) << S_SR_IDLE)
+#define G_SR_IDLE(x) (((x) >> S_SR_IDLE) & M_SR_IDLE)
+
+#define A_MC_UPCTL_MCFG 0x40080
+
+#define S_MDDR_LPDDR2_CLK_STOP_IDLE    24
+#define M_MDDR_LPDDR2_CLK_STOP_IDLE    0xffU
+#define V_MDDR_LPDDR2_CLK_STOP_IDLE(x) ((x) << S_MDDR_LPDDR2_CLK_STOP_IDLE)
+#define G_MDDR_LPDDR2_CLK_STOP_IDLE(x) (((x) >> S_MDDR_LPDDR2_CLK_STOP_IDLE) & M_MDDR_LPDDR2_CLK_STOP_IDLE)
+
+#define S_MDDR_LPDDR2_EN    22
+#define M_MDDR_LPDDR2_EN    0x3U
+#define V_MDDR_LPDDR2_EN(x) ((x) << S_MDDR_LPDDR2_EN)
+#define G_MDDR_LPDDR2_EN(x) (((x) >> S_MDDR_LPDDR2_EN) & M_MDDR_LPDDR2_EN)
+
+#define S_MDDR_LPDDR2_BL    20
+#define M_MDDR_LPDDR2_BL    0x3U
+#define V_MDDR_LPDDR2_BL(x) ((x) << S_MDDR_LPDDR2_BL)
+#define G_MDDR_LPDDR2_BL(x) (((x) >> S_MDDR_LPDDR2_BL) & M_MDDR_LPDDR2_BL)
+
+#define S_LPDDR2_S4    6
+#define V_LPDDR2_S4(x) ((x) << S_LPDDR2_S4)
+#define F_LPDDR2_S4    V_LPDDR2_S4(1U)
+
+#define S_STAGGER_CS    4
+#define V_STAGGER_CS(x) ((x) << S_STAGGER_CS)
+#define F_STAGGER_CS    V_STAGGER_CS(1U)
+
+#define S_CKE_OR_EN    1
+#define V_CKE_OR_EN(x) ((x) << S_CKE_OR_EN)
+#define F_CKE_OR_EN    V_CKE_OR_EN(1U)
+
+#define A_MC_UPCTL_PPCFG 0x40084
+#define A_MC_UPCTL_MSTAT 0x40088
+
+#define S_SELF_REFRESH    2
+#define V_SELF_REFRESH(x) ((x) << S_SELF_REFRESH)
+#define F_SELF_REFRESH    V_SELF_REFRESH(1U)
+
+#define S_CLOCK_STOP    1
+#define V_CLOCK_STOP(x) ((x) << S_CLOCK_STOP)
+#define F_CLOCK_STOP    V_CLOCK_STOP(1U)
+
+#define A_MC_UPCTL_LPDDR2ZQCFG 0x4008c
+
+#define S_ZQCL_OP    24
+#define M_ZQCL_OP    0xffU
+#define V_ZQCL_OP(x) ((x) << S_ZQCL_OP)
+#define G_ZQCL_OP(x) (((x) >> S_ZQCL_OP) & M_ZQCL_OP)
+
+#define S_ZQCL_MA    16
+#define M_ZQCL_MA    0xffU
+#define V_ZQCL_MA(x) ((x) << S_ZQCL_MA)
+#define G_ZQCL_MA(x) (((x) >> S_ZQCL_MA) & M_ZQCL_MA)
+
+#define S_ZQCS_OP    8
+#define M_ZQCS_OP    0xffU
+#define V_ZQCS_OP(x) ((x) << S_ZQCS_OP)
+#define G_ZQCS_OP(x) (((x) >> S_ZQCS_OP) & M_ZQCS_OP)
+
+#define S_ZQCS_MA    0
+#define M_ZQCS_MA    0xffU
+#define V_ZQCS_MA(x) ((x) << S_ZQCS_MA)
+#define G_ZQCS_MA(x) (((x) >> S_ZQCS_MA) & M_ZQCS_MA)
+
+#define A_MC_UPCTL_DTUPDES 0x40094
+
+#define S_DTU_ERR_B7    7
+#define V_DTU_ERR_B7(x) ((x) << S_DTU_ERR_B7)
+#define F_DTU_ERR_B7    V_DTU_ERR_B7(1U)
+
+#define A_MC_UPCTL_DTUNA 0x40098
+#define A_MC_UPCTL_DTUNE 0x4009c
+#define A_MC_UPCTL_DTUPRD0 0x400a0
+#define A_MC_UPCTL_DTUPRD1 0x400a4
+#define A_MC_UPCTL_DTUPRD2 0x400a8
+#define A_MC_UPCTL_DTUPRD3 0x400ac
+#define A_MC_UPCTL_DTUAWDT 0x400b0
+#define A_MC_UPCTL_TOGCNT1U 0x400c0
+#define A_MC_UPCTL_TINIT 0x400c4
+#define A_MC_UPCTL_TRSTH 0x400c8
+#define A_MC_UPCTL_TOGCNT100N 0x400cc
+#define A_MC_UPCTL_TREFI 0x400d0
+#define A_MC_UPCTL_TMRD 0x400d4
+#define A_MC_UPCTL_TRFC 0x400d8
+
+#define S_T_RFC0    0
+#define M_T_RFC0    0x1ffU
+#define V_T_RFC0(x) ((x) << S_T_RFC0)
+#define G_T_RFC0(x) (((x) >> S_T_RFC0) & M_T_RFC0)
+
+#define A_MC_UPCTL_TRP 0x400dc
+
+#define S_PREA_EXTRA    16
+#define M_PREA_EXTRA    0x3U
+#define V_PREA_EXTRA(x) ((x) << S_PREA_EXTRA)
+#define G_PREA_EXTRA(x) (((x) >> S_PREA_EXTRA) & M_PREA_EXTRA)
+
+#define A_MC_UPCTL_TRTW 0x400e0
+
+#define S_T_RTW0    0
+#define M_T_RTW0    0xfU
+#define V_T_RTW0(x) ((x) << S_T_RTW0)
+#define G_T_RTW0(x) (((x) >> S_T_RTW0) & M_T_RTW0)
+
+#define A_MC_UPCTL_TAL 0x400e4
+#define A_MC_UPCTL_TCL 0x400e8
+#define A_MC_UPCTL_TCWL 0x400ec
+#define A_MC_UPCTL_TRAS 0x400f0
+#define A_MC_UPCTL_TRC 0x400f4
+#define A_MC_UPCTL_TRCD 0x400f8
+#define A_MC_UPCTL_TRRD 0x400fc
+#define A_MC_UPCTL_TRTP 0x40100
+
+#define S_T_RTP0    0
+#define M_T_RTP0    0xfU
+#define V_T_RTP0(x) ((x) << S_T_RTP0)
+#define G_T_RTP0(x) (((x) >> S_T_RTP0) & M_T_RTP0)
+
+#define A_MC_UPCTL_TWR 0x40104
+
+#define S_U_T_WR    0
+#define M_U_T_WR    0x1fU
+#define V_U_T_WR(x) ((x) << S_U_T_WR)
+#define G_U_T_WR(x) (((x) >> S_U_T_WR) & M_U_T_WR)
+
+#define A_MC_UPCTL_TWTR 0x40108
+
+#define S_T_WTR0    0
+#define M_T_WTR0    0xfU
+#define V_T_WTR0(x) ((x) << S_T_WTR0)
+#define G_T_WTR0(x) (((x) >> S_T_WTR0) & M_T_WTR0)
+
+#define A_MC_UPCTL_TEXSR 0x4010c
+#define A_MC_UPCTL_TXP 0x40110
+#define A_MC_UPCTL_TXPDLL 0x40114
+#define A_MC_UPCTL_TZQCS 0x40118
+#define A_MC_UPCTL_TZQCSI 0x4011c
+#define A_MC_UPCTL_TDQS 0x40120
+#define A_MC_UPCTL_TCKSRE 0x40124
+
+#define S_T_CKSRE0    0
+#define M_T_CKSRE0    0x1fU
+#define V_T_CKSRE0(x) ((x) << S_T_CKSRE0)
+#define G_T_CKSRE0(x) (((x) >> S_T_CKSRE0) & M_T_CKSRE0)
+
+#define A_MC_UPCTL_TCKSRX 0x40128
+
+#define S_T_CKSRX0    0
+#define M_T_CKSRX0    0x1fU
+#define V_T_CKSRX0(x) ((x) << S_T_CKSRX0)
+#define G_T_CKSRX0(x) (((x) >> S_T_CKSRX0) & M_T_CKSRX0)
+
+#define A_MC_UPCTL_TCKE 0x4012c
+#define A_MC_UPCTL_TMOD 0x40130
+
+#define S_T_MOD0    0
+#define M_T_MOD0    0x1fU
+#define V_T_MOD0(x) ((x) << S_T_MOD0)
+#define G_T_MOD0(x) (((x) >> S_T_MOD0) & M_T_MOD0)
+
+#define A_MC_UPCTL_TRSTL 0x40134
+
+#define S_T_RSTL    0
+#define M_T_RSTL    0x7fU
+#define V_T_RSTL(x) ((x) << S_T_RSTL)
+#define G_T_RSTL(x) (((x) >> S_T_RSTL) & M_T_RSTL)
+
+#define A_MC_UPCTL_TZQCL 0x40138
+#define A_MC_UPCTL_TMRR 0x4013c
+
+#define S_T_MRR    0
+#define M_T_MRR    0xffU
+#define V_T_MRR(x) ((x) << S_T_MRR)
+#define G_T_MRR(x) (((x) >> S_T_MRR) & M_T_MRR)
+
+#define A_MC_UPCTL_TCKESR 0x40140
+
+#define S_T_CKESR    0
+#define M_T_CKESR    0xfU
+#define V_T_CKESR(x) ((x) << S_T_CKESR)
+#define G_T_CKESR(x) (((x) >> S_T_CKESR) & M_T_CKESR)
+
+#define A_MC_UPCTL_TDPD 0x40144
+
+#define S_T_DPD    0
+#define M_T_DPD    0x3ffU
+#define V_T_DPD(x) ((x) << S_T_DPD)
+#define G_T_DPD(x) (((x) >> S_T_DPD) & M_T_DPD)
+
+#define A_MC_UPCTL_ECCCFG 0x40180
+#define A_MC_UPCTL_ECCTST 0x40184
+
+#define S_ECC_TEST_MASK0    0
+#define M_ECC_TEST_MASK0    0x7fU
+#define V_ECC_TEST_MASK0(x) ((x) << S_ECC_TEST_MASK0)
+#define G_ECC_TEST_MASK0(x) (((x) >> S_ECC_TEST_MASK0) & M_ECC_TEST_MASK0)
+
+#define A_MC_UPCTL_ECCCLR 0x40188
+#define A_MC_UPCTL_ECCLOG 0x4018c
+#define A_MC_UPCTL_DTUWACTL 0x40200
+
+#define S_DTU_WR_ROW0    13
+#define M_DTU_WR_ROW0    0xffffU
+#define V_DTU_WR_ROW0(x) ((x) << S_DTU_WR_ROW0)
+#define G_DTU_WR_ROW0(x) (((x) >> S_DTU_WR_ROW0) & M_DTU_WR_ROW0)
+
+#define A_MC_UPCTL_DTURACTL 0x40204
+
+#define S_DTU_RD_ROW0    13
+#define M_DTU_RD_ROW0    0xffffU
+#define V_DTU_RD_ROW0(x) ((x) << S_DTU_RD_ROW0)
+#define G_DTU_RD_ROW0(x) (((x) >> S_DTU_RD_ROW0) & M_DTU_RD_ROW0)
+
+#define A_MC_UPCTL_DTUCFG 0x40208
+#define A_MC_UPCTL_DTUECTL 0x4020c
+#define A_MC_UPCTL_DTUWD0 0x40210
+#define A_MC_UPCTL_DTUWD1 0x40214
+#define A_MC_UPCTL_DTUWD2 0x40218
+#define A_MC_UPCTL_DTUWD3 0x4021c
+#define A_MC_UPCTL_DTUWDM 0x40220
+#define A_MC_UPCTL_DTURD0 0x40224
+#define A_MC_UPCTL_DTURD1 0x40228
+#define A_MC_UPCTL_DTURD2 0x4022c
+#define A_MC_UPCTL_DTURD3 0x40230
+#define A_MC_UPCTL_DTULFSRWD 0x40234
+#define A_MC_UPCTL_DTULFSRRD 0x40238
+#define A_MC_UPCTL_DTUEAF 0x4023c
+
+#define S_EA_ROW0    13
+#define M_EA_ROW0    0xffffU
+#define V_EA_ROW0(x) ((x) << S_EA_ROW0)
+#define G_EA_ROW0(x) (((x) >> S_EA_ROW0) & M_EA_ROW0)
+
+#define A_MC_UPCTL_DFITCTRLDELAY 0x40240
+
+#define S_TCTRL_DELAY    0
+#define M_TCTRL_DELAY    0xfU
+#define V_TCTRL_DELAY(x) ((x) << S_TCTRL_DELAY)
+#define G_TCTRL_DELAY(x) (((x) >> S_TCTRL_DELAY) & M_TCTRL_DELAY)
+
+#define A_MC_UPCTL_DFIODTCFG 0x40244
+
+#define S_RANK3_ODT_WRITE_NSEL    26
+#define V_RANK3_ODT_WRITE_NSEL(x) ((x) << S_RANK3_ODT_WRITE_NSEL)
+#define F_RANK3_ODT_WRITE_NSEL    V_RANK3_ODT_WRITE_NSEL(1U)
+
+#define A_MC_UPCTL_DFIODTCFG1 0x40248
+
+#define S_ODT_LEN_B8_R    24
+#define M_ODT_LEN_B8_R    0x7U
+#define V_ODT_LEN_B8_R(x) ((x) << S_ODT_LEN_B8_R)
+#define G_ODT_LEN_B8_R(x) (((x) >> S_ODT_LEN_B8_R) & M_ODT_LEN_B8_R)
+
+#define S_ODT_LEN_BL8_W    16
+#define M_ODT_LEN_BL8_W    0x7U
+#define V_ODT_LEN_BL8_W(x) ((x) << S_ODT_LEN_BL8_W)
+#define G_ODT_LEN_BL8_W(x) (((x) >> S_ODT_LEN_BL8_W) & M_ODT_LEN_BL8_W)
+
+#define S_ODT_LAT_R    8
+#define M_ODT_LAT_R    0x1fU
+#define V_ODT_LAT_R(x) ((x) << S_ODT_LAT_R)
+#define G_ODT_LAT_R(x) (((x) >> S_ODT_LAT_R) & M_ODT_LAT_R)
+
+#define S_ODT_LAT_W    0
+#define M_ODT_LAT_W    0x1fU
+#define V_ODT_LAT_W(x) ((x) << S_ODT_LAT_W)
+#define G_ODT_LAT_W(x) (((x) >> S_ODT_LAT_W) & M_ODT_LAT_W)
+
+#define A_MC_UPCTL_DFIODTRANKMAP 0x4024c
+
+#define S_ODT_RANK_MAP3    12
+#define M_ODT_RANK_MAP3    0xfU
+#define V_ODT_RANK_MAP3(x) ((x) << S_ODT_RANK_MAP3)
+#define G_ODT_RANK_MAP3(x) (((x) >> S_ODT_RANK_MAP3) & M_ODT_RANK_MAP3)
+
+#define S_ODT_RANK_MAP2    8
+#define M_ODT_RANK_MAP2    0xfU
+#define V_ODT_RANK_MAP2(x) ((x) << S_ODT_RANK_MAP2)
+#define G_ODT_RANK_MAP2(x) (((x) >> S_ODT_RANK_MAP2) & M_ODT_RANK_MAP2)
+
+#define S_ODT_RANK_MAP1    4
+#define M_ODT_RANK_MAP1    0xfU
+#define V_ODT_RANK_MAP1(x) ((x) << S_ODT_RANK_MAP1)
+#define G_ODT_RANK_MAP1(x) (((x) >> S_ODT_RANK_MAP1) & M_ODT_RANK_MAP1)
+
+#define S_ODT_RANK_MAP0    0
+#define M_ODT_RANK_MAP0    0xfU
+#define V_ODT_RANK_MAP0(x) ((x) << S_ODT_RANK_MAP0)
+#define G_ODT_RANK_MAP0(x) (((x) >> S_ODT_RANK_MAP0) & M_ODT_RANK_MAP0)
+
+#define A_MC_UPCTL_DFITPHYWRDATA 0x40250
+
+#define S_TPHY_WRDATA    0
+#define M_TPHY_WRDATA    0x1fU
+#define V_TPHY_WRDATA(x) ((x) << S_TPHY_WRDATA)
+#define G_TPHY_WRDATA(x) (((x) >> S_TPHY_WRDATA) & M_TPHY_WRDATA)
+
+#define A_MC_UPCTL_DFITPHYWRLAT 0x40254
+
+#define S_TPHY_WRLAT    0
+#define M_TPHY_WRLAT    0x1fU
+#define V_TPHY_WRLAT(x) ((x) << S_TPHY_WRLAT)
+#define G_TPHY_WRLAT(x) (((x) >> S_TPHY_WRLAT) & M_TPHY_WRLAT)
+
+#define A_MC_UPCTL_DFITRDDATAEN 0x40260
+
+#define S_TRDDATA_EN    0
+#define M_TRDDATA_EN    0x1fU
+#define V_TRDDATA_EN(x) ((x) << S_TRDDATA_EN)
+#define G_TRDDATA_EN(x) (((x) >> S_TRDDATA_EN) & M_TRDDATA_EN)
+
+#define A_MC_UPCTL_DFITPHYRDLAT 0x40264
+
+#define S_TPHY_RDLAT    0
+#define M_TPHY_RDLAT    0x3fU
+#define V_TPHY_RDLAT(x) ((x) << S_TPHY_RDLAT)
+#define G_TPHY_RDLAT(x) (((x) >> S_TPHY_RDLAT) & M_TPHY_RDLAT)
+
+#define A_MC_UPCTL_DFITPHYUPDTYPE0 0x40270
+
+#define S_TPHYUPD_TYPE0    0
+#define M_TPHYUPD_TYPE0    0xfffU
+#define V_TPHYUPD_TYPE0(x) ((x) << S_TPHYUPD_TYPE0)
+#define G_TPHYUPD_TYPE0(x) (((x) >> S_TPHYUPD_TYPE0) & M_TPHYUPD_TYPE0)
+
+#define A_MC_UPCTL_DFITPHYUPDTYPE1 0x40274
+
+#define S_TPHYUPD_TYPE1    0
+#define M_TPHYUPD_TYPE1    0xfffU
+#define V_TPHYUPD_TYPE1(x) ((x) << S_TPHYUPD_TYPE1)
+#define G_TPHYUPD_TYPE1(x) (((x) >> S_TPHYUPD_TYPE1) & M_TPHYUPD_TYPE1)
+
+#define A_MC_UPCTL_DFITPHYUPDTYPE2 0x40278
+
+#define S_TPHYUPD_TYPE2    0
+#define M_TPHYUPD_TYPE2    0xfffU
+#define V_TPHYUPD_TYPE2(x) ((x) << S_TPHYUPD_TYPE2)
+#define G_TPHYUPD_TYPE2(x) (((x) >> S_TPHYUPD_TYPE2) & M_TPHYUPD_TYPE2)
+
+#define A_MC_UPCTL_DFITPHYUPDTYPE3 0x4027c
+
+#define S_TPHYUPD_TYPE3    0
+#define M_TPHYUPD_TYPE3    0xfffU
+#define V_TPHYUPD_TYPE3(x) ((x) << S_TPHYUPD_TYPE3)
+#define G_TPHYUPD_TYPE3(x) (((x) >> S_TPHYUPD_TYPE3) & M_TPHYUPD_TYPE3)
+
+#define A_MC_UPCTL_DFITCTRLUPDMIN 0x40280
+
+#define S_TCTRLUPD_MIN    0
+#define M_TCTRLUPD_MIN    0xffffU
+#define V_TCTRLUPD_MIN(x) ((x) << S_TCTRLUPD_MIN)
+#define G_TCTRLUPD_MIN(x) (((x) >> S_TCTRLUPD_MIN) & M_TCTRLUPD_MIN)
+
+#define A_MC_UPCTL_DFITCTRLUPDMAX 0x40284
+
+#define S_TCTRLUPD_MAX    0
+#define M_TCTRLUPD_MAX    0xffffU
+#define V_TCTRLUPD_MAX(x) ((x) << S_TCTRLUPD_MAX)
+#define G_TCTRLUPD_MAX(x) (((x) >> S_TCTRLUPD_MAX) & M_TCTRLUPD_MAX)
+
+#define A_MC_UPCTL_DFITCTRLUPDDLY 0x40288
+
+#define S_TCTRLUPD_DLY    0
+#define M_TCTRLUPD_DLY    0xfU
+#define V_TCTRLUPD_DLY(x) ((x) << S_TCTRLUPD_DLY)
+#define G_TCTRLUPD_DLY(x) (((x) >> S_TCTRLUPD_DLY) & M_TCTRLUPD_DLY)
+
+#define A_MC_UPCTL_DFIUPDCFG 0x40290
+
+#define S_DFI_PHYUPD_EN    1
+#define V_DFI_PHYUPD_EN(x) ((x) << S_DFI_PHYUPD_EN)
+#define F_DFI_PHYUPD_EN    V_DFI_PHYUPD_EN(1U)
+
+#define S_DFI_CTRLUPD_EN    0
+#define V_DFI_CTRLUPD_EN(x) ((x) << S_DFI_CTRLUPD_EN)
+#define F_DFI_CTRLUPD_EN    V_DFI_CTRLUPD_EN(1U)
+
+#define A_MC_UPCTL_DFITREFMSKI 0x40294
+
+#define S_TREFMSKI    0
+#define M_TREFMSKI    0xffU
+#define V_TREFMSKI(x) ((x) << S_TREFMSKI)
+#define G_TREFMSKI(x) (((x) >> S_TREFMSKI) & M_TREFMSKI)
+
+#define A_MC_UPCTL_DFITCTRLUPDI 0x40298
+#define A_MC_UPCTL_DFITRCFG0 0x402ac
+
+#define S_DFI_WRLVL_RANK_SEL    16
+#define M_DFI_WRLVL_RANK_SEL    0xfU
+#define V_DFI_WRLVL_RANK_SEL(x) ((x) << S_DFI_WRLVL_RANK_SEL)
+#define G_DFI_WRLVL_RANK_SEL(x) (((x) >> S_DFI_WRLVL_RANK_SEL) & M_DFI_WRLVL_RANK_SEL)
+
+#define S_DFI_RDLVL_EDGE    4
+#define M_DFI_RDLVL_EDGE    0x1ffU
+#define V_DFI_RDLVL_EDGE(x) ((x) << S_DFI_RDLVL_EDGE)
+#define G_DFI_RDLVL_EDGE(x) (((x) >> S_DFI_RDLVL_EDGE) & M_DFI_RDLVL_EDGE)
+
+#define S_DFI_RDLVL_RANK_SEL    0
+#define M_DFI_RDLVL_RANK_SEL    0xfU
+#define V_DFI_RDLVL_RANK_SEL(x) ((x) << S_DFI_RDLVL_RANK_SEL)
+#define G_DFI_RDLVL_RANK_SEL(x) (((x) >> S_DFI_RDLVL_RANK_SEL) & M_DFI_RDLVL_RANK_SEL)
+
+#define A_MC_UPCTL_DFITRSTAT0 0x402b0
+
+#define S_DFI_WRLVL_MODE    16
+#define M_DFI_WRLVL_MODE    0x3U
+#define V_DFI_WRLVL_MODE(x) ((x) << S_DFI_WRLVL_MODE)
+#define G_DFI_WRLVL_MODE(x) (((x) >> S_DFI_WRLVL_MODE) & M_DFI_WRLVL_MODE)
+
+#define S_DFI_RDLVL_GATE_MODE    8
+#define M_DFI_RDLVL_GATE_MODE    0x3U
+#define V_DFI_RDLVL_GATE_MODE(x) ((x) << S_DFI_RDLVL_GATE_MODE)
+#define G_DFI_RDLVL_GATE_MODE(x) (((x) >> S_DFI_RDLVL_GATE_MODE) & M_DFI_RDLVL_GATE_MODE)
+
+#define S_DFI_RDLVL_MODE    0
+#define M_DFI_RDLVL_MODE    0x3U
+#define V_DFI_RDLVL_MODE(x) ((x) << S_DFI_RDLVL_MODE)
+#define G_DFI_RDLVL_MODE(x) (((x) >> S_DFI_RDLVL_MODE) & M_DFI_RDLVL_MODE)
+
+#define A_MC_UPCTL_DFITRWRLVLEN 0x402b4
+
+#define S_DFI_WRLVL_EN    0
+#define M_DFI_WRLVL_EN    0x1ffU
+#define V_DFI_WRLVL_EN(x) ((x) << S_DFI_WRLVL_EN)
+#define G_DFI_WRLVL_EN(x) (((x) >> S_DFI_WRLVL_EN) & M_DFI_WRLVL_EN)
+
+#define A_MC_UPCTL_DFITRRDLVLEN 0x402b8
+
+#define S_DFI_RDLVL_EN    0
+#define M_DFI_RDLVL_EN    0x1ffU
+#define V_DFI_RDLVL_EN(x) ((x) << S_DFI_RDLVL_EN)
+#define G_DFI_RDLVL_EN(x) (((x) >> S_DFI_RDLVL_EN) & M_DFI_RDLVL_EN)
+
+#define A_MC_UPCTL_DFITRRDLVLGATEEN 0x402bc
+
+#define S_DFI_RDLVL_GATE_EN    0
+#define M_DFI_RDLVL_GATE_EN    0x1ffU
+#define V_DFI_RDLVL_GATE_EN(x) ((x) << S_DFI_RDLVL_GATE_EN)
+#define G_DFI_RDLVL_GATE_EN(x) (((x) >> S_DFI_RDLVL_GATE_EN) & M_DFI_RDLVL_GATE_EN)
+
+#define A_MC_UPCTL_DFISTSTAT0 0x402c0
+
+#define S_DFI_DATA_BYTE_DISABLE    16
+#define M_DFI_DATA_BYTE_DISABLE    0x1ffU
+#define V_DFI_DATA_BYTE_DISABLE(x) ((x) << S_DFI_DATA_BYTE_DISABLE)
+#define G_DFI_DATA_BYTE_DISABLE(x) (((x) >> S_DFI_DATA_BYTE_DISABLE) & M_DFI_DATA_BYTE_DISABLE)
+
+#define S_DFI_FREQ_RATIO    4
+#define M_DFI_FREQ_RATIO    0x3U
+#define V_DFI_FREQ_RATIO(x) ((x) << S_DFI_FREQ_RATIO)
+#define G_DFI_FREQ_RATIO(x) (((x) >> S_DFI_FREQ_RATIO) & M_DFI_FREQ_RATIO)
+
+#define S_DFI_INIT_START0    1
+#define V_DFI_INIT_START0(x) ((x) << S_DFI_INIT_START0)
+#define F_DFI_INIT_START0    V_DFI_INIT_START0(1U)
+
+#define S_DFI_INIT_COMPLETE    0
+#define V_DFI_INIT_COMPLETE(x) ((x) << S_DFI_INIT_COMPLETE)
+#define F_DFI_INIT_COMPLETE    V_DFI_INIT_COMPLETE(1U)
+
+#define A_MC_UPCTL_DFISTCFG0 0x402c4
+
+#define S_DFI_DATA_BYTE_DISABLE_EN    2
+#define V_DFI_DATA_BYTE_DISABLE_EN(x) ((x) << S_DFI_DATA_BYTE_DISABLE_EN)
+#define F_DFI_DATA_BYTE_DISABLE_EN    V_DFI_DATA_BYTE_DISABLE_EN(1U)
+
+#define S_DFI_FREQ_RATIO_EN    1
+#define V_DFI_FREQ_RATIO_EN(x) ((x) << S_DFI_FREQ_RATIO_EN)
+#define F_DFI_FREQ_RATIO_EN    V_DFI_FREQ_RATIO_EN(1U)
+
+#define S_DFI_INIT_START    0
+#define V_DFI_INIT_START(x) ((x) << S_DFI_INIT_START)
+#define F_DFI_INIT_START    V_DFI_INIT_START(1U)
+
+#define A_MC_UPCTL_DFISTCFG1 0x402c8
+
+#define S_DFI_DRAM_CLK_DISABLE_EN_DPD    1
+#define V_DFI_DRAM_CLK_DISABLE_EN_DPD(x) ((x) << S_DFI_DRAM_CLK_DISABLE_EN_DPD)
+#define F_DFI_DRAM_CLK_DISABLE_EN_DPD    V_DFI_DRAM_CLK_DISABLE_EN_DPD(1U)
+
+#define S_DFI_DRAM_CLK_DISABLE_EN    0
+#define V_DFI_DRAM_CLK_DISABLE_EN(x) ((x) << S_DFI_DRAM_CLK_DISABLE_EN)
+#define F_DFI_DRAM_CLK_DISABLE_EN    V_DFI_DRAM_CLK_DISABLE_EN(1U)
+
+#define A_MC_UPCTL_DFITDRAMCLKEN 0x402d0
+
+#define S_TDRAM_CLK_ENABLE    0
+#define M_TDRAM_CLK_ENABLE    0xfU
+#define V_TDRAM_CLK_ENABLE(x) ((x) << S_TDRAM_CLK_ENABLE)
+#define G_TDRAM_CLK_ENABLE(x) (((x) >> S_TDRAM_CLK_ENABLE) & M_TDRAM_CLK_ENABLE)
+
+#define A_MC_UPCTL_DFITDRAMCLKDIS 0x402d4
+
+#define S_TDRAM_CLK_DISABLE    0
+#define M_TDRAM_CLK_DISABLE    0xfU
+#define V_TDRAM_CLK_DISABLE(x) ((x) << S_TDRAM_CLK_DISABLE)
+#define G_TDRAM_CLK_DISABLE(x) (((x) >> S_TDRAM_CLK_DISABLE) & M_TDRAM_CLK_DISABLE)
+
+#define A_MC_UPCTL_DFISTCFG2 0x402d8
+
+#define S_PARITY_EN    1
+#define V_PARITY_EN(x) ((x) << S_PARITY_EN)
+#define F_PARITY_EN    V_PARITY_EN(1U)
+
+#define S_PARITY_INTR_EN    0
+#define V_PARITY_INTR_EN(x) ((x) << S_PARITY_INTR_EN)
+#define F_PARITY_INTR_EN    V_PARITY_INTR_EN(1U)
+
+#define A_MC_UPCTL_DFISTPARCLR 0x402dc
+
+#define S_PARITY_LOG_CLR    1
+#define V_PARITY_LOG_CLR(x) ((x) << S_PARITY_LOG_CLR)
+#define F_PARITY_LOG_CLR    V_PARITY_LOG_CLR(1U)
+
+#define S_PARITY_INTR_CLR    0
+#define V_PARITY_INTR_CLR(x) ((x) << S_PARITY_INTR_CLR)
+#define F_PARITY_INTR_CLR    V_PARITY_INTR_CLR(1U)
+
+#define A_MC_UPCTL_DFISTPARLOG 0x402e0
+#define A_MC_UPCTL_DFILPCFG0 0x402f0
+
+#define S_DFI_LP_WAKEUP_DPD    28
+#define M_DFI_LP_WAKEUP_DPD    0xfU
+#define V_DFI_LP_WAKEUP_DPD(x) ((x) << S_DFI_LP_WAKEUP_DPD)
+#define G_DFI_LP_WAKEUP_DPD(x) (((x) >> S_DFI_LP_WAKEUP_DPD) & M_DFI_LP_WAKEUP_DPD)
+
+#define S_DFI_LP_EN_DPD    24
+#define V_DFI_LP_EN_DPD(x) ((x) << S_DFI_LP_EN_DPD)
+#define F_DFI_LP_EN_DPD    V_DFI_LP_EN_DPD(1U)
+
+#define S_DFI_TLP_RESP    16
+#define M_DFI_TLP_RESP    0xfU
+#define V_DFI_TLP_RESP(x) ((x) << S_DFI_TLP_RESP)
+#define G_DFI_TLP_RESP(x) (((x) >> S_DFI_TLP_RESP) & M_DFI_TLP_RESP)
+
+#define S_DFI_LP_EN_SR    8
+#define V_DFI_LP_EN_SR(x) ((x) << S_DFI_LP_EN_SR)
+#define F_DFI_LP_EN_SR    V_DFI_LP_EN_SR(1U)
+
+#define S_DFI_LP_WAKEUP_PD    4
+#define M_DFI_LP_WAKEUP_PD    0xfU
+#define V_DFI_LP_WAKEUP_PD(x) ((x) << S_DFI_LP_WAKEUP_PD)
+#define G_DFI_LP_WAKEUP_PD(x) (((x) >> S_DFI_LP_WAKEUP_PD) & M_DFI_LP_WAKEUP_PD)
+
+#define S_DFI_LP_EN_PD    0
+#define V_DFI_LP_EN_PD(x) ((x) << S_DFI_LP_EN_PD)
+#define F_DFI_LP_EN_PD    V_DFI_LP_EN_PD(1U)
+
+#define A_MC_UPCTL_DFITRWRLVLRESP0 0x40300
+#define A_MC_UPCTL_DFITRWRLVLRESP1 0x40304
+#define A_MC_UPCTL_DFITRWRLVLRESP2 0x40308
+
+#define S_DFI_WRLVL_RESP2    0
+#define M_DFI_WRLVL_RESP2    0xffU
+#define V_DFI_WRLVL_RESP2(x) ((x) << S_DFI_WRLVL_RESP2)
+#define G_DFI_WRLVL_RESP2(x) (((x) >> S_DFI_WRLVL_RESP2) & M_DFI_WRLVL_RESP2)
+
+#define A_MC_UPCTL_DFITRRDLVLRESP0 0x4030c
+#define A_MC_UPCTL_DFITRRDLVLRESP1 0x40310
+#define A_MC_UPCTL_DFITRRDLVLRESP2 0x40314
+
+#define S_DFI_RDLVL_RESP2    0
+#define M_DFI_RDLVL_RESP2    0xffU
+#define V_DFI_RDLVL_RESP2(x) ((x) << S_DFI_RDLVL_RESP2)
+#define G_DFI_RDLVL_RESP2(x) (((x) >> S_DFI_RDLVL_RESP2) & M_DFI_RDLVL_RESP2)
+
+#define A_MC_UPCTL_DFITRWRLVLDELAY0 0x40318
+#define A_MC_UPCTL_DFITRWRLVLDELAY1 0x4031c
+#define A_MC_UPCTL_DFITRWRLVLDELAY2 0x40320
+
+#define S_DFI_WRLVL_DELAY2    0
+#define M_DFI_WRLVL_DELAY2    0xffU
+#define V_DFI_WRLVL_DELAY2(x) ((x) << S_DFI_WRLVL_DELAY2)
+#define G_DFI_WRLVL_DELAY2(x) (((x) >> S_DFI_WRLVL_DELAY2) & M_DFI_WRLVL_DELAY2)
+
+#define A_MC_UPCTL_DFITRRDLVLDELAY0 0x40324
+#define A_MC_UPCTL_DFITRRDLVLDELAY1 0x40328
+#define A_MC_UPCTL_DFITRRDLVLDELAY2 0x4032c
+
+#define S_DFI_RDLVL_DELAY2    0
+#define M_DFI_RDLVL_DELAY2    0xffU
+#define V_DFI_RDLVL_DELAY2(x) ((x) << S_DFI_RDLVL_DELAY2)
+#define G_DFI_RDLVL_DELAY2(x) (((x) >> S_DFI_RDLVL_DELAY2) & M_DFI_RDLVL_DELAY2)
+
+#define A_MC_UPCTL_DFITRRDLVLGATEDELAY0 0x40330
+#define A_MC_UPCTL_DFITRRDLVLGATEDELAY1 0x40334
+#define A_MC_UPCTL_DFITRRDLVLGATEDELAY2 0x40338
+
+#define S_DFI_RDLVL_GATE_DELAY2    0
+#define M_DFI_RDLVL_GATE_DELAY2    0xffU
+#define V_DFI_RDLVL_GATE_DELAY2(x) ((x) << S_DFI_RDLVL_GATE_DELAY2)
+#define G_DFI_RDLVL_GATE_DELAY2(x) (((x) >> S_DFI_RDLVL_GATE_DELAY2) & M_DFI_RDLVL_GATE_DELAY2)
+
+#define A_MC_UPCTL_DFITRCMD 0x4033c
+
+#define S_DFITRCMD_START    31
+#define V_DFITRCMD_START(x) ((x) << S_DFITRCMD_START)
+#define F_DFITRCMD_START    V_DFITRCMD_START(1U)
+
+#define S_DFITRCMD_EN    4
+#define M_DFITRCMD_EN    0x1ffU
+#define V_DFITRCMD_EN(x) ((x) << S_DFITRCMD_EN)
+#define G_DFITRCMD_EN(x) (((x) >> S_DFITRCMD_EN) & M_DFITRCMD_EN)
+
+#define S_DFITRCMD_OPCODE    0
+#define M_DFITRCMD_OPCODE    0x3U
+#define V_DFITRCMD_OPCODE(x) ((x) << S_DFITRCMD_OPCODE)
+#define G_DFITRCMD_OPCODE(x) (((x) >> S_DFITRCMD_OPCODE) & M_DFITRCMD_OPCODE)
+
+#define A_MC_UPCTL_IPVR 0x403f8
+#define A_MC_UPCTL_IPTR 0x403fc
+#define A_MC_P_DDRPHY_RST_CTRL 0x41300
+
+#define S_PHY_DRAM_WL    17
+#define M_PHY_DRAM_WL    0x1fU
+#define V_PHY_DRAM_WL(x) ((x) << S_PHY_DRAM_WL)
+#define G_PHY_DRAM_WL(x) (((x) >> S_PHY_DRAM_WL) & M_PHY_DRAM_WL)
+
+#define S_PHY_CALIB_DONE    5
+#define V_PHY_CALIB_DONE(x) ((x) << S_PHY_CALIB_DONE)
+#define F_PHY_CALIB_DONE    V_PHY_CALIB_DONE(1U)
+
+#define S_CTL_CAL_REQ    4
+#define V_CTL_CAL_REQ(x) ((x) << S_CTL_CAL_REQ)
+#define F_CTL_CAL_REQ    V_CTL_CAL_REQ(1U)
+
+#define S_CTL_CKE    3
+#define V_CTL_CKE(x) ((x) << S_CTL_CKE)
+#define F_CTL_CKE    V_CTL_CKE(1U)
+
+#define S_CTL_RST_N    2
+#define V_CTL_RST_N(x) ((x) << S_CTL_RST_N)
+#define F_CTL_RST_N    V_CTL_RST_N(1U)
+
+#define A_MC_P_PERFORMANCE_CTRL 0x41304
+#define A_MC_P_ECC_CTRL 0x41308
+#define A_MC_P_PAR_ENABLE 0x4130c
+#define A_MC_P_PAR_CAUSE 0x41310
+#define A_MC_P_INT_ENABLE 0x41314
+#define A_MC_P_INT_CAUSE 0x41318
+#define A_MC_P_ECC_STATUS 0x4131c
+#define A_MC_P_PHY_CTRL 0x41320
+#define A_MC_P_STATIC_CFG_STATUS 0x41324
+
+#define S_STATIC_AWEN    23
+#define V_STATIC_AWEN(x) ((x) << S_STATIC_AWEN)
+#define F_STATIC_AWEN    V_STATIC_AWEN(1U)
+
+#define S_STATIC_SWLAT    18
+#define M_STATIC_SWLAT    0x1fU
+#define V_STATIC_SWLAT(x) ((x) << S_STATIC_SWLAT)
+#define G_STATIC_SWLAT(x) (((x) >> S_STATIC_SWLAT) & M_STATIC_SWLAT)
+
+#define S_STATIC_WLAT    17
+#define V_STATIC_WLAT(x) ((x) << S_STATIC_WLAT)
+#define F_STATIC_WLAT    V_STATIC_WLAT(1U)
+
+#define S_STATIC_ALIGN    16
+#define V_STATIC_ALIGN(x) ((x) << S_STATIC_ALIGN)
+#define F_STATIC_ALIGN    V_STATIC_ALIGN(1U)
+
+#define S_STATIC_SLAT    11
+#define M_STATIC_SLAT    0x1fU
+#define V_STATIC_SLAT(x) ((x) << S_STATIC_SLAT)
+#define G_STATIC_SLAT(x) (((x) >> S_STATIC_SLAT) & M_STATIC_SLAT)
+
+#define S_STATIC_LAT    10
+#define V_STATIC_LAT(x) ((x) << S_STATIC_LAT)
+#define F_STATIC_LAT    V_STATIC_LAT(1U)
+
+#define A_MC_P_CORE_PCTL_STAT 0x41328
+#define A_MC_P_DEBUG_CNT 0x4132c
+#define A_MC_CE_ERR_DATA_RDATA 0x41330
+#define A_MC_CE_COR_DATA_RDATA 0x41350
+#define A_MC_UE_ERR_DATA_RDATA 0x41370
+#define A_MC_UE_COR_DATA_RDATA 0x41390
+#define A_MC_CE_ADDR 0x413b0
+#define A_MC_UE_ADDR 0x413b4
+#define A_MC_P_DEEP_SLEEP 0x413b8
+
+#define S_SLEEPSTATUS    1
+#define V_SLEEPSTATUS(x) ((x) << S_SLEEPSTATUS)
+#define F_SLEEPSTATUS    V_SLEEPSTATUS(1U)
+
+#define S_SLEEPREQ    0
+#define V_SLEEPREQ(x) ((x) << S_SLEEPREQ)
+#define F_SLEEPREQ    V_SLEEPREQ(1U)
+
+#define A_MC_P_FPGA_BONUS 0x413bc
+#define A_MC_P_DEBUG_CFG 0x413c0
+#define A_MC_P_DEBUG_RPT 0x413c4
+#define A_MC_P_BIST_CMD 0x41400
+
+#define S_BURST_LEN    16
+#define M_BURST_LEN    0x3U
+#define V_BURST_LEN(x) ((x) << S_BURST_LEN)
+#define G_BURST_LEN(x) (((x) >> S_BURST_LEN) & M_BURST_LEN)
+
+#define A_MC_P_BIST_CMD_ADDR 0x41404
+#define A_MC_P_BIST_CMD_LEN 0x41408
+#define A_MC_P_BIST_DATA_PATTERN 0x4140c
+#define A_MC_P_BIST_USER_WDATA0 0x41414
+#define A_MC_P_BIST_USER_WDATA1 0x41418
+#define A_MC_P_BIST_USER_WDATA2 0x4141c
+
+#define S_USER_DATA_MASK    8
+#define M_USER_DATA_MASK    0x1ffU
+#define V_USER_DATA_MASK(x) ((x) << S_USER_DATA_MASK)
+#define G_USER_DATA_MASK(x) (((x) >> S_USER_DATA_MASK) & M_USER_DATA_MASK)
+
+#define A_MC_P_BIST_NUM_ERR 0x41480
+#define A_MC_P_BIST_ERR_FIRST_ADDR 0x41484
+#define A_MC_P_BIST_STATUS_RDATA 0x41488
+#define A_MC_P_BIST_CRC_SEED 0x414d0
+#define A_MC_DDRPHY_DP18_DATA_BIT_ENABLE0 0x44000
+
+#define S_DATA_BIT_ENABLE_0_15    0
+#define M_DATA_BIT_ENABLE_0_15    0xffffU
+#define V_DATA_BIT_ENABLE_0_15(x) ((x) << S_DATA_BIT_ENABLE_0_15)
+#define G_DATA_BIT_ENABLE_0_15(x) (((x) >> S_DATA_BIT_ENABLE_0_15) & M_DATA_BIT_ENABLE_0_15)
+
+#define A_MC_DDRPHY_DP18_DATA_BIT_ENABLE1 0x44004
+
+#define S_DATA_BIT_ENABLE_16_23    8
+#define M_DATA_BIT_ENABLE_16_23    0xffU
+#define V_DATA_BIT_ENABLE_16_23(x) ((x) << S_DATA_BIT_ENABLE_16_23)
+#define G_DATA_BIT_ENABLE_16_23(x) (((x) >> S_DATA_BIT_ENABLE_16_23) & M_DATA_BIT_ENABLE_16_23)
+
+#define S_DFT_FORCE_OUTPUTS    7
+#define V_DFT_FORCE_OUTPUTS(x) ((x) << S_DFT_FORCE_OUTPUTS)
+#define F_DFT_FORCE_OUTPUTS    V_DFT_FORCE_OUTPUTS(1U)
+
+#define S_DFT_PRBS7_GEN_EN    6
+#define V_DFT_PRBS7_GEN_EN(x) ((x) << S_DFT_PRBS7_GEN_EN)
+#define F_DFT_PRBS7_GEN_EN    V_DFT_PRBS7_GEN_EN(1U)
+
+#define S_WRAPSEL    5
+#define V_WRAPSEL(x) ((x) << S_WRAPSEL)
+#define F_WRAPSEL    V_WRAPSEL(1U)
+
+#define S_MRS_CMD_DATA_N0    3
+#define V_MRS_CMD_DATA_N0(x) ((x) << S_MRS_CMD_DATA_N0)
+#define F_MRS_CMD_DATA_N0    V_MRS_CMD_DATA_N0(1U)
+
+#define S_MRS_CMD_DATA_N1    2
+#define V_MRS_CMD_DATA_N1(x) ((x) << S_MRS_CMD_DATA_N1)
+#define F_MRS_CMD_DATA_N1    V_MRS_CMD_DATA_N1(1U)
+
+#define S_MRS_CMD_DATA_N2    1
+#define V_MRS_CMD_DATA_N2(x) ((x) << S_MRS_CMD_DATA_N2)
+#define F_MRS_CMD_DATA_N2    V_MRS_CMD_DATA_N2(1U)
+
+#define S_MRS_CMD_DATA_N3    0
+#define V_MRS_CMD_DATA_N3(x) ((x) << S_MRS_CMD_DATA_N3)
+#define F_MRS_CMD_DATA_N3    V_MRS_CMD_DATA_N3(1U)
+
+#define A_MC_DDRPHY_DP18_DATA_BIT_DIR0 0x44008
+
+#define S_DATA_BIT_DIR_0_15    0
+#define M_DATA_BIT_DIR_0_15    0xffffU
+#define V_DATA_BIT_DIR_0_15(x) ((x) << S_DATA_BIT_DIR_0_15)
+#define G_DATA_BIT_DIR_0_15(x) (((x) >> S_DATA_BIT_DIR_0_15) & M_DATA_BIT_DIR_0_15)
+
+#define A_MC_DDRPHY_DP18_DATA_BIT_DIR1 0x4400c
+
+#define S_DATA_BIT_DIR_16_23    8
+#define M_DATA_BIT_DIR_16_23    0xffU
+#define V_DATA_BIT_DIR_16_23(x) ((x) << S_DATA_BIT_DIR_16_23)
+#define G_DATA_BIT_DIR_16_23(x) (((x) >> S_DATA_BIT_DIR_16_23) & M_DATA_BIT_DIR_16_23)
+
+#define S_WL_ADVANCE_DISABLE    7
+#define V_WL_ADVANCE_DISABLE(x) ((x) << S_WL_ADVANCE_DISABLE)
+#define F_WL_ADVANCE_DISABLE    V_WL_ADVANCE_DISABLE(1U)
+
+#define S_DISABLE_PING_PONG    6
+#define V_DISABLE_PING_PONG(x) ((x) << S_DISABLE_PING_PONG)
+#define F_DISABLE_PING_PONG    V_DISABLE_PING_PONG(1U)
+
+#define S_DELAY_PING_PONG_HALF    5
+#define V_DELAY_PING_PONG_HALF(x) ((x) << S_DELAY_PING_PONG_HALF)
+#define F_DELAY_PING_PONG_HALF    V_DELAY_PING_PONG_HALF(1U)
+
+#define S_ADVANCE_PING_PONG    4
+#define V_ADVANCE_PING_PONG(x) ((x) << S_ADVANCE_PING_PONG)
+#define F_ADVANCE_PING_PONG    V_ADVANCE_PING_PONG(1U)
+
+#define S_ATEST_MUX_CTL0    3
+#define V_ATEST_MUX_CTL0(x) ((x) << S_ATEST_MUX_CTL0)
+#define F_ATEST_MUX_CTL0    V_ATEST_MUX_CTL0(1U)
+
+#define S_ATEST_MUX_CTL1    2
+#define V_ATEST_MUX_CTL1(x) ((x) << S_ATEST_MUX_CTL1)
+#define F_ATEST_MUX_CTL1    V_ATEST_MUX_CTL1(1U)
+
+#define S_ATEST_MUX_CTL2    1
+#define V_ATEST_MUX_CTL2(x) ((x) << S_ATEST_MUX_CTL2)
+#define F_ATEST_MUX_CTL2    V_ATEST_MUX_CTL2(1U)
+
+#define S_ATEST_MUX_CTL3    0
+#define V_ATEST_MUX_CTL3(x) ((x) << S_ATEST_MUX_CTL3)
+#define F_ATEST_MUX_CTL3    V_ATEST_MUX_CTL3(1U)
+
+#define A_MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR 0x44010
+
+#define S_QUAD0_CLK16_BIT0    15
+#define V_QUAD0_CLK16_BIT0(x) ((x) << S_QUAD0_CLK16_BIT0)
+#define F_QUAD0_CLK16_BIT0    V_QUAD0_CLK16_BIT0(1U)
+
+#define S_QUAD1_CLK16_BIT1    14
+#define V_QUAD1_CLK16_BIT1(x) ((x) << S_QUAD1_CLK16_BIT1)
+#define F_QUAD1_CLK16_BIT1    V_QUAD1_CLK16_BIT1(1U)
+
+#define S_QUAD2_CLK16_BIT2    13
+#define V_QUAD2_CLK16_BIT2(x) ((x) << S_QUAD2_CLK16_BIT2)
+#define F_QUAD2_CLK16_BIT2    V_QUAD2_CLK16_BIT2(1U)
+
+#define S_QUAD3_CLK16_BIT3    12
+#define V_QUAD3_CLK16_BIT3(x) ((x) << S_QUAD3_CLK16_BIT3)
+#define F_QUAD3_CLK16_BIT3    V_QUAD3_CLK16_BIT3(1U)
+
+#define S_QUAD0_CLK18_BIT4    11
+#define V_QUAD0_CLK18_BIT4(x) ((x) << S_QUAD0_CLK18_BIT4)
+#define F_QUAD0_CLK18_BIT4    V_QUAD0_CLK18_BIT4(1U)
+
+#define S_QUAD1_CLK18_BIT5    10
+#define V_QUAD1_CLK18_BIT5(x) ((x) << S_QUAD1_CLK18_BIT5)
+#define F_QUAD1_CLK18_BIT5    V_QUAD1_CLK18_BIT5(1U)
+
+#define S_QUAD2_CLK20_BIT6    9
+#define V_QUAD2_CLK20_BIT6(x) ((x) << S_QUAD2_CLK20_BIT6)
+#define F_QUAD2_CLK20_BIT6    V_QUAD2_CLK20_BIT6(1U)
+
+#define S_QUAD3_CLK20_BIT7    8
+#define V_QUAD3_CLK20_BIT7(x) ((x) << S_QUAD3_CLK20_BIT7)
+#define F_QUAD3_CLK20_BIT7    V_QUAD3_CLK20_BIT7(1U)
+
+#define S_QUAD2_CLK22_BIT8    7
+#define V_QUAD2_CLK22_BIT8(x) ((x) << S_QUAD2_CLK22_BIT8)
+#define F_QUAD2_CLK22_BIT8    V_QUAD2_CLK22_BIT8(1U)
+
+#define S_QUAD3_CLK22_BIT9    6
+#define V_QUAD3_CLK22_BIT9(x) ((x) << S_QUAD3_CLK22_BIT9)
+#define F_QUAD3_CLK22_BIT9    V_QUAD3_CLK22_BIT9(1U)
+
+#define S_CLK16_SINGLE_ENDED_BIT10    5
+#define V_CLK16_SINGLE_ENDED_BIT10(x) ((x) << S_CLK16_SINGLE_ENDED_BIT10)
+#define F_CLK16_SINGLE_ENDED_BIT10    V_CLK16_SINGLE_ENDED_BIT10(1U)
+
+#define S_CLK18_SINGLE_ENDED_BIT11    4
+#define V_CLK18_SINGLE_ENDED_BIT11(x) ((x) << S_CLK18_SINGLE_ENDED_BIT11)
+#define F_CLK18_SINGLE_ENDED_BIT11    V_CLK18_SINGLE_ENDED_BIT11(1U)
+
+#define S_CLK20_SINGLE_ENDED_BIT12    3
+#define V_CLK20_SINGLE_ENDED_BIT12(x) ((x) << S_CLK20_SINGLE_ENDED_BIT12)
+#define F_CLK20_SINGLE_ENDED_BIT12    V_CLK20_SINGLE_ENDED_BIT12(1U)
+
+#define S_CLK22_SINGLE_ENDED_BIT13    2
+#define V_CLK22_SINGLE_ENDED_BIT13(x) ((x) << S_CLK22_SINGLE_ENDED_BIT13)
+#define F_CLK22_SINGLE_ENDED_BIT13    V_CLK22_SINGLE_ENDED_BIT13(1U)
+
+#define A_MC_DDRPHY_DP18_WRCLK_EN_RP 0x44014
+
+#define S_QUAD2_CLK18_BIT14    1
+#define V_QUAD2_CLK18_BIT14(x) ((x) << S_QUAD2_CLK18_BIT14)
+#define F_QUAD2_CLK18_BIT14    V_QUAD2_CLK18_BIT14(1U)
+
+#define S_QUAD3_CLK18_BIT15    0
+#define V_QUAD3_CLK18_BIT15(x) ((x) << S_QUAD3_CLK18_BIT15)
+#define F_QUAD3_CLK18_BIT15    V_QUAD3_CLK18_BIT15(1U)
+
+#define A_MC_DDRPHY_DP18_RX_PEAK_AMP 0x44018
+
+#define S_PEAK_AMP_CTL_SIDE0    13
+#define M_PEAK_AMP_CTL_SIDE0    0x7U
+#define V_PEAK_AMP_CTL_SIDE0(x) ((x) << S_PEAK_AMP_CTL_SIDE0)
+#define G_PEAK_AMP_CTL_SIDE0(x) (((x) >> S_PEAK_AMP_CTL_SIDE0) & M_PEAK_AMP_CTL_SIDE0)
+
+#define S_PEAK_AMP_CTL_SIDE1    9
+#define M_PEAK_AMP_CTL_SIDE1    0x7U
+#define V_PEAK_AMP_CTL_SIDE1(x) ((x) << S_PEAK_AMP_CTL_SIDE1)
+#define G_PEAK_AMP_CTL_SIDE1(x) (((x) >> S_PEAK_AMP_CTL_SIDE1) & M_PEAK_AMP_CTL_SIDE1)
+
+#define S_SXMCVREF_0_3    4
+#define M_SXMCVREF_0_3    0xfU
+#define V_SXMCVREF_0_3(x) ((x) << S_SXMCVREF_0_3)
+#define G_SXMCVREF_0_3(x) (((x) >> S_SXMCVREF_0_3) & M_SXMCVREF_0_3)
+
+#define S_SXPODVREF    3
+#define V_SXPODVREF(x) ((x) << S_SXPODVREF)
+#define F_SXPODVREF    V_SXPODVREF(1U)
+
+#define S_DISABLE_TERMINATION    2
+#define V_DISABLE_TERMINATION(x) ((x) << S_DISABLE_TERMINATION)
+#define F_DISABLE_TERMINATION    V_DISABLE_TERMINATION(1U)
+
+#define S_READ_CENTERING_MODE    0
+#define M_READ_CENTERING_MODE    0x3U
+#define V_READ_CENTERING_MODE(x) ((x) << S_READ_CENTERING_MODE)
+#define G_READ_CENTERING_MODE(x) (((x) >> S_READ_CENTERING_MODE) & M_READ_CENTERING_MODE)
+
+#define A_MC_DDRPHY_DP18_SYSCLK_PR 0x4401c
+
+#define S_SYSCLK_PHASE_ALIGN_RESET    6
+#define V_SYSCLK_PHASE_ALIGN_RESET(x) ((x) << S_SYSCLK_PHASE_ALIGN_RESET)
+#define F_SYSCLK_PHASE_ALIGN_RESET    V_SYSCLK_PHASE_ALIGN_RESET(1U)
+
+#define A_MC_DDRPHY_DP18_DFT_DIG_EYE 0x44020
+
+#define S_DIGITAL_EYE_EN    15
+#define V_DIGITAL_EYE_EN(x) ((x) << S_DIGITAL_EYE_EN)
+#define F_DIGITAL_EYE_EN    V_DIGITAL_EYE_EN(1U)
+
+#define S_BUMP    14
+#define V_BUMP(x) ((x) << S_BUMP)
+#define F_BUMP    V_BUMP(1U)
+
+#define S_TRIG_PERIOD    13
+#define V_TRIG_PERIOD(x) ((x) << S_TRIG_PERIOD)
+#define F_TRIG_PERIOD    V_TRIG_PERIOD(1U)
+
+#define S_CNTL_POL    12
+#define V_CNTL_POL(x) ((x) << S_CNTL_POL)
+#define F_CNTL_POL    V_CNTL_POL(1U)
+
+#define S_CNTL_SRC    8
+#define V_CNTL_SRC(x) ((x) << S_CNTL_SRC)
+#define F_CNTL_SRC    V_CNTL_SRC(1U)
+
+#define S_DIGITAL_EYE_VALUE    0
+#define M_DIGITAL_EYE_VALUE    0xffU
+#define V_DIGITAL_EYE_VALUE(x) ((x) << S_DIGITAL_EYE_VALUE)
+#define G_DIGITAL_EYE_VALUE(x) (((x) >> S_DIGITAL_EYE_VALUE) & M_DIGITAL_EYE_VALUE)
+
+#define A_MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR 0x44024
+
+#define S_DQSCLK_SELECT0    14
+#define M_DQSCLK_SELECT0    0x3U
+#define V_DQSCLK_SELECT0(x) ((x) << S_DQSCLK_SELECT0)
+#define G_DQSCLK_SELECT0(x) (((x) >> S_DQSCLK_SELECT0) & M_DQSCLK_SELECT0)
+
+#define S_RDCLK_SELECT0    12
+#define M_RDCLK_SELECT0    0x3U
+#define V_RDCLK_SELECT0(x) ((x) << S_RDCLK_SELECT0)
+#define G_RDCLK_SELECT0(x) (((x) >> S_RDCLK_SELECT0) & M_RDCLK_SELECT0)
+
+#define S_DQSCLK_SELECT1    10
+#define M_DQSCLK_SELECT1    0x3U
+#define V_DQSCLK_SELECT1(x) ((x) << S_DQSCLK_SELECT1)
+#define G_DQSCLK_SELECT1(x) (((x) >> S_DQSCLK_SELECT1) & M_DQSCLK_SELECT1)
+
+#define S_RDCLK_SELECT1    8
+#define M_RDCLK_SELECT1    0x3U
+#define V_RDCLK_SELECT1(x) ((x) << S_RDCLK_SELECT1)
+#define G_RDCLK_SELECT1(x) (((x) >> S_RDCLK_SELECT1) & M_RDCLK_SELECT1)
+
+#define S_DQSCLK_SELECT2    6
+#define M_DQSCLK_SELECT2    0x3U
+#define V_DQSCLK_SELECT2(x) ((x) << S_DQSCLK_SELECT2)
+#define G_DQSCLK_SELECT2(x) (((x) >> S_DQSCLK_SELECT2) & M_DQSCLK_SELECT2)
+
+#define S_RDCLK_SELECT2    4
+#define M_RDCLK_SELECT2    0x3U
+#define V_RDCLK_SELECT2(x) ((x) << S_RDCLK_SELECT2)
+#define G_RDCLK_SELECT2(x) (((x) >> S_RDCLK_SELECT2) & M_RDCLK_SELECT2)
+
+#define S_DQSCLK_SELECT3    2
+#define M_DQSCLK_SELECT3    0x3U
+#define V_DQSCLK_SELECT3(x) ((x) << S_DQSCLK_SELECT3)
+#define G_DQSCLK_SELECT3(x) (((x) >> S_DQSCLK_SELECT3) & M_DQSCLK_SELECT3)
+
+#define S_RDCLK_SELECT3    0
+#define M_RDCLK_SELECT3    0x3U
+#define V_RDCLK_SELECT3(x) ((x) << S_RDCLK_SELECT3)
+#define G_RDCLK_SELECT3(x) (((x) >> S_RDCLK_SELECT3) & M_RDCLK_SELECT3)
+
+#define A_MC_DDRPHY_DP18_DRIFT_LIMITS 0x44028
+
+#define S_MIN_RD_EYE_SIZE    8
+#define M_MIN_RD_EYE_SIZE    0x3fU
+#define V_MIN_RD_EYE_SIZE(x) ((x) << S_MIN_RD_EYE_SIZE)
+#define G_MIN_RD_EYE_SIZE(x) (((x) >> S_MIN_RD_EYE_SIZE) & M_MIN_RD_EYE_SIZE)
+
+#define S_MAX_DQS_DRIFT    0
+#define M_MAX_DQS_DRIFT    0x3fU
+#define V_MAX_DQS_DRIFT(x) ((x) << S_MAX_DQS_DRIFT)
+#define G_MAX_DQS_DRIFT(x) (((x) >> S_MAX_DQS_DRIFT) & M_MAX_DQS_DRIFT)
+
+#define A_MC_DDRPHY_DP18_DEBUG_SEL 0x4402c
+
+#define S_HS_PROBE_A_SEL    11
+#define M_HS_PROBE_A_SEL    0x1fU
+#define V_HS_PROBE_A_SEL(x) ((x) << S_HS_PROBE_A_SEL)
+#define G_HS_PROBE_A_SEL(x) (((x) >> S_HS_PROBE_A_SEL) & M_HS_PROBE_A_SEL)
+
+#define S_HS_PROBE_B_SEL    6
+#define M_HS_PROBE_B_SEL    0x1fU
+#define V_HS_PROBE_B_SEL(x) ((x) << S_HS_PROBE_B_SEL)
+#define G_HS_PROBE_B_SEL(x) (((x) >> S_HS_PROBE_B_SEL) & M_HS_PROBE_B_SEL)
+
+#define S_RD_DEBUG_SEL    3
+#define M_RD_DEBUG_SEL    0x7U
+#define V_RD_DEBUG_SEL(x) ((x) << S_RD_DEBUG_SEL)
+#define G_RD_DEBUG_SEL(x) (((x) >> S_RD_DEBUG_SEL) & M_RD_DEBUG_SEL)
+
+#define S_WR_DEBUG_SEL    0
+#define M_WR_DEBUG_SEL    0x7U
+#define V_WR_DEBUG_SEL(x) ((x) << S_WR_DEBUG_SEL)
+#define G_WR_DEBUG_SEL(x) (((x) >> S_WR_DEBUG_SEL) & M_WR_DEBUG_SEL)
+
+#define A_MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR 0x44030
+
+#define S_OFFSET_BITS1_7    8
+#define M_OFFSET_BITS1_7    0x7fU
+#define V_OFFSET_BITS1_7(x) ((x) << S_OFFSET_BITS1_7)
+#define G_OFFSET_BITS1_7(x) (((x) >> S_OFFSET_BITS1_7) & M_OFFSET_BITS1_7)
+
+#define S_OFFSET_BITS9_15    0
+#define M_OFFSET_BITS9_15    0x7fU
+#define V_OFFSET_BITS9_15(x) ((x) << S_OFFSET_BITS9_15)
+#define G_OFFSET_BITS9_15(x) (((x) >> S_OFFSET_BITS9_15) & M_OFFSET_BITS9_15)
+
+#define A_MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR 0x44034
+#define A_MC_DDRPHY_DP18_RD_LVL_STATUS0 0x44038
+
+#define S_LEADING_EDGE_NOT_FOUND_0    0
+#define M_LEADING_EDGE_NOT_FOUND_0    0xffffU
+#define V_LEADING_EDGE_NOT_FOUND_0(x) ((x) << S_LEADING_EDGE_NOT_FOUND_0)
+#define G_LEADING_EDGE_NOT_FOUND_0(x) (((x) >> S_LEADING_EDGE_NOT_FOUND_0) & M_LEADING_EDGE_NOT_FOUND_0)
+
+#define A_MC_DDRPHY_DP18_RD_LVL_STATUS1 0x4403c
+
+#define S_LEADING_EDGE_NOT_FOUND_1    8
+#define M_LEADING_EDGE_NOT_FOUND_1    0xffU
+#define V_LEADING_EDGE_NOT_FOUND_1(x) ((x) << S_LEADING_EDGE_NOT_FOUND_1)
+#define G_LEADING_EDGE_NOT_FOUND_1(x) (((x) >> S_LEADING_EDGE_NOT_FOUND_1) & M_LEADING_EDGE_NOT_FOUND_1)
+
+#define A_MC_DDRPHY_DP18_RD_LVL_STATUS2 0x44040
+
+#define S_TRAILING_EDGE_NOT_FOUND    0
+#define M_TRAILING_EDGE_NOT_FOUND    0xffffU
+#define V_TRAILING_EDGE_NOT_FOUND(x) ((x) << S_TRAILING_EDGE_NOT_FOUND)
+#define G_TRAILING_EDGE_NOT_FOUND(x) (((x) >> S_TRAILING_EDGE_NOT_FOUND) & M_TRAILING_EDGE_NOT_FOUND)
+
+#define A_MC_DDRPHY_DP18_RD_LVL_STATUS3 0x44044
+
+#define S_TRAILING_EDGE_NOT_FOUND_16_23    8
+#define M_TRAILING_EDGE_NOT_FOUND_16_23    0xffU
+#define V_TRAILING_EDGE_NOT_FOUND_16_23(x) ((x) << S_TRAILING_EDGE_NOT_FOUND_16_23)
+#define G_TRAILING_EDGE_NOT_FOUND_16_23(x) (((x) >> S_TRAILING_EDGE_NOT_FOUND_16_23) & M_TRAILING_EDGE_NOT_FOUND_16_23)
+
+#define A_MC_DDRPHY_DP18_RD_DIA_CONFIG5 0x44048
+
+#define S_DYN_POWER_CNTL_EN    15
+#define V_DYN_POWER_CNTL_EN(x) ((x) << S_DYN_POWER_CNTL_EN)
+#define F_DYN_POWER_CNTL_EN    V_DYN_POWER_CNTL_EN(1U)
+
+#define S_DYN_MCTERM_CNTL_EN    14
+#define V_DYN_MCTERM_CNTL_EN(x) ((x) << S_DYN_MCTERM_CNTL_EN)
+#define F_DYN_MCTERM_CNTL_EN    V_DYN_MCTERM_CNTL_EN(1U)
+
+#define S_DYN_RX_GATE_CNTL_EN    13
+#define V_DYN_RX_GATE_CNTL_EN(x) ((x) << S_DYN_RX_GATE_CNTL_EN)
+#define F_DYN_RX_GATE_CNTL_EN    V_DYN_RX_GATE_CNTL_EN(1U)
+
+#define S_CALGATE_ON    12
+#define V_CALGATE_ON(x) ((x) << S_CALGATE_ON)
+#define F_CALGATE_ON    V_CALGATE_ON(1U)
+
+#define S_PER_RDCLK_UPDATE_DIS    11
+#define V_PER_RDCLK_UPDATE_DIS(x) ((x) << S_PER_RDCLK_UPDATE_DIS)
+#define F_PER_RDCLK_UPDATE_DIS    V_PER_RDCLK_UPDATE_DIS(1U)
+
+#define A_MC_DDRPHY_DP18_DQS_GATE_DELAY_RP 0x4404c
+
+#define S_DQS_GATE_DELAY_N0    12
+#define M_DQS_GATE_DELAY_N0    0x7U
+#define V_DQS_GATE_DELAY_N0(x) ((x) << S_DQS_GATE_DELAY_N0)
+#define G_DQS_GATE_DELAY_N0(x) (((x) >> S_DQS_GATE_DELAY_N0) & M_DQS_GATE_DELAY_N0)
+
+#define S_DQS_GATE_DELAY_N1    8
+#define M_DQS_GATE_DELAY_N1    0x7U
+#define V_DQS_GATE_DELAY_N1(x) ((x) << S_DQS_GATE_DELAY_N1)
+#define G_DQS_GATE_DELAY_N1(x) (((x) >> S_DQS_GATE_DELAY_N1) & M_DQS_GATE_DELAY_N1)
+
+#define S_DQS_GATE_DELAY_N2    4
+#define M_DQS_GATE_DELAY_N2    0x7U
+#define V_DQS_GATE_DELAY_N2(x) ((x) << S_DQS_GATE_DELAY_N2)
+#define G_DQS_GATE_DELAY_N2(x) (((x) >> S_DQS_GATE_DELAY_N2) & M_DQS_GATE_DELAY_N2)
+
+#define S_DQS_GATE_DELAY_N3    0
+#define M_DQS_GATE_DELAY_N3    0x7U
+#define V_DQS_GATE_DELAY_N3(x) ((x) << S_DQS_GATE_DELAY_N3)
+#define G_DQS_GATE_DELAY_N3(x) (((x) >> S_DQS_GATE_DELAY_N3) & M_DQS_GATE_DELAY_N3)
+
+#define A_MC_DDRPHY_DP18_RD_STATUS0 0x44050
+
+#define S_NO_EYE_DETECTED    15
+#define V_NO_EYE_DETECTED(x) ((x) << S_NO_EYE_DETECTED)
+#define F_NO_EYE_DETECTED    V_NO_EYE_DETECTED(1U)
+
+#define S_LEADING_EDGE_FOUND    14
+#define V_LEADING_EDGE_FOUND(x) ((x) << S_LEADING_EDGE_FOUND)
+#define F_LEADING_EDGE_FOUND    V_LEADING_EDGE_FOUND(1U)
+
+#define S_TRAILING_EDGE_FOUND    13
+#define V_TRAILING_EDGE_FOUND(x) ((x) << S_TRAILING_EDGE_FOUND)
+#define F_TRAILING_EDGE_FOUND    V_TRAILING_EDGE_FOUND(1U)
+
+#define S_INCOMPLETE_RD_CAL_N0    12
+#define V_INCOMPLETE_RD_CAL_N0(x) ((x) << S_INCOMPLETE_RD_CAL_N0)
+#define F_INCOMPLETE_RD_CAL_N0    V_INCOMPLETE_RD_CAL_N0(1U)
+
+#define S_INCOMPLETE_RD_CAL_N1    11
+#define V_INCOMPLETE_RD_CAL_N1(x) ((x) << S_INCOMPLETE_RD_CAL_N1)
+#define F_INCOMPLETE_RD_CAL_N1    V_INCOMPLETE_RD_CAL_N1(1U)
+
+#define S_INCOMPLETE_RD_CAL_N2    10
+#define V_INCOMPLETE_RD_CAL_N2(x) ((x) << S_INCOMPLETE_RD_CAL_N2)
+#define F_INCOMPLETE_RD_CAL_N2    V_INCOMPLETE_RD_CAL_N2(1U)
+
+#define S_INCOMPLETE_RD_CAL_N3    9
+#define V_INCOMPLETE_RD_CAL_N3(x) ((x) << S_INCOMPLETE_RD_CAL_N3)
+#define F_INCOMPLETE_RD_CAL_N3    V_INCOMPLETE_RD_CAL_N3(1U)
+
+#define S_COARSE_PATTERN_ERR_N0    8
+#define V_COARSE_PATTERN_ERR_N0(x) ((x) << S_COARSE_PATTERN_ERR_N0)
+#define F_COARSE_PATTERN_ERR_N0    V_COARSE_PATTERN_ERR_N0(1U)
+
+#define S_COARSE_PATTERN_ERR_N1    7
+#define V_COARSE_PATTERN_ERR_N1(x) ((x) << S_COARSE_PATTERN_ERR_N1)
+#define F_COARSE_PATTERN_ERR_N1    V_COARSE_PATTERN_ERR_N1(1U)
+
+#define S_COARSE_PATTERN_ERR_N2    6
+#define V_COARSE_PATTERN_ERR_N2(x) ((x) << S_COARSE_PATTERN_ERR_N2)
+#define F_COARSE_PATTERN_ERR_N2    V_COARSE_PATTERN_ERR_N2(1U)
+
+#define S_COARSE_PATTERN_ERR_N3    5
+#define V_COARSE_PATTERN_ERR_N3(x) ((x) << S_COARSE_PATTERN_ERR_N3)
+#define F_COARSE_PATTERN_ERR_N3    V_COARSE_PATTERN_ERR_N3(1U)
+
+#define S_EYE_CLIPPING    4
+#define V_EYE_CLIPPING(x) ((x) << S_EYE_CLIPPING)
+#define F_EYE_CLIPPING    V_EYE_CLIPPING(1U)
+
+#define S_NO_DQS    3
+#define V_NO_DQS(x) ((x) << S_NO_DQS)
+#define F_NO_DQS    V_NO_DQS(1U)
+
+#define S_NO_LOCK    2
+#define V_NO_LOCK(x) ((x) << S_NO_LOCK)
+#define F_NO_LOCK    V_NO_LOCK(1U)
+
+#define S_DRIFT_ERROR    1
+#define V_DRIFT_ERROR(x) ((x) << S_DRIFT_ERROR)
+#define F_DRIFT_ERROR    V_DRIFT_ERROR(1U)
+
+#define S_MIN_EYE    0
+#define V_MIN_EYE(x) ((x) << S_MIN_EYE)
+#define F_MIN_EYE    V_MIN_EYE(1U)
+
+#define A_MC_DDRPHY_DP18_RD_ERROR_MASK0 0x44054
+
+#define S_NO_EYE_DETECTED_MASK    15
+#define V_NO_EYE_DETECTED_MASK(x) ((x) << S_NO_EYE_DETECTED_MASK)
+#define F_NO_EYE_DETECTED_MASK    V_NO_EYE_DETECTED_MASK(1U)
+
+#define S_LEADING_EDGE_FOUND_MASK    14
+#define V_LEADING_EDGE_FOUND_MASK(x) ((x) << S_LEADING_EDGE_FOUND_MASK)
+#define F_LEADING_EDGE_FOUND_MASK    V_LEADING_EDGE_FOUND_MASK(1U)
+
+#define S_TRAILING_EDGE_FOUND_MASK    13
+#define V_TRAILING_EDGE_FOUND_MASK(x) ((x) << S_TRAILING_EDGE_FOUND_MASK)
+#define F_TRAILING_EDGE_FOUND_MASK    V_TRAILING_EDGE_FOUND_MASK(1U)
+
+#define S_INCOMPLETE_RD_CAL_N0_MASK    12
+#define V_INCOMPLETE_RD_CAL_N0_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N0_MASK)
+#define F_INCOMPLETE_RD_CAL_N0_MASK    V_INCOMPLETE_RD_CAL_N0_MASK(1U)
+
+#define S_INCOMPLETE_RD_CAL_N1_MASK    11
+#define V_INCOMPLETE_RD_CAL_N1_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N1_MASK)
+#define F_INCOMPLETE_RD_CAL_N1_MASK    V_INCOMPLETE_RD_CAL_N1_MASK(1U)
+
+#define S_INCOMPLETE_RD_CAL_N2_MASK    10
+#define V_INCOMPLETE_RD_CAL_N2_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N2_MASK)
+#define F_INCOMPLETE_RD_CAL_N2_MASK    V_INCOMPLETE_RD_CAL_N2_MASK(1U)
+
+#define S_INCOMPLETE_RD_CAL_N3_MASK    9
+#define V_INCOMPLETE_RD_CAL_N3_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N3_MASK)
+#define F_INCOMPLETE_RD_CAL_N3_MASK    V_INCOMPLETE_RD_CAL_N3_MASK(1U)
+
+#define S_COARSE_PATTERN_ERR_N0_MASK    8
+#define V_COARSE_PATTERN_ERR_N0_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N0_MASK)
+#define F_COARSE_PATTERN_ERR_N0_MASK    V_COARSE_PATTERN_ERR_N0_MASK(1U)
+
+#define S_COARSE_PATTERN_ERR_N1_MASK    7
+#define V_COARSE_PATTERN_ERR_N1_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N1_MASK)
+#define F_COARSE_PATTERN_ERR_N1_MASK    V_COARSE_PATTERN_ERR_N1_MASK(1U)
+
+#define S_COARSE_PATTERN_ERR_N2_MASK    6
+#define V_COARSE_PATTERN_ERR_N2_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N2_MASK)
+#define F_COARSE_PATTERN_ERR_N2_MASK    V_COARSE_PATTERN_ERR_N2_MASK(1U)
+
+#define S_COARSE_PATTERN_ERR_N3_MASK    5
+#define V_COARSE_PATTERN_ERR_N3_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N3_MASK)
+#define F_COARSE_PATTERN_ERR_N3_MASK    V_COARSE_PATTERN_ERR_N3_MASK(1U)
+
+#define S_EYE_CLIPPING_MASK    4
+#define V_EYE_CLIPPING_MASK(x) ((x) << S_EYE_CLIPPING_MASK)
+#define F_EYE_CLIPPING_MASK    V_EYE_CLIPPING_MASK(1U)
+
+#define S_NO_DQS_MASK    3
+#define V_NO_DQS_MASK(x) ((x) << S_NO_DQS_MASK)
+#define F_NO_DQS_MASK    V_NO_DQS_MASK(1U)
+
+#define S_NO_LOCK_MASK    2
+#define V_NO_LOCK_MASK(x) ((x) << S_NO_LOCK_MASK)
+#define F_NO_LOCK_MASK    V_NO_LOCK_MASK(1U)
+
+#define S_DRIFT_ERROR_MASK    1
+#define V_DRIFT_ERROR_MASK(x) ((x) << S_DRIFT_ERROR_MASK)
+#define F_DRIFT_ERROR_MASK    V_DRIFT_ERROR_MASK(1U)
+
+#define S_MIN_EYE_MASK    0
+#define V_MIN_EYE_MASK(x) ((x) << S_MIN_EYE_MASK)
+#define F_MIN_EYE_MASK    V_MIN_EYE_MASK(1U)
+
+#define A_MC_DDRPHY_DP18_WR_LVL_STATUS0 0x4405c
+
+#define S_CLK_LEVEL    14
+#define M_CLK_LEVEL    0x3U
+#define V_CLK_LEVEL(x) ((x) << S_CLK_LEVEL)
+#define G_CLK_LEVEL(x) (((x) >> S_CLK_LEVEL) & M_CLK_LEVEL)
+
+#define S_FINE_STEPPING    13
+#define V_FINE_STEPPING(x) ((x) << S_FINE_STEPPING)
+#define F_FINE_STEPPING    V_FINE_STEPPING(1U)
+
+#define S_DONE    12
+#define V_DONE(x) ((x) << S_DONE)
+#define F_DONE    V_DONE(1U)
+
+#define S_WL_ERR_CLK16_ST    11
+#define V_WL_ERR_CLK16_ST(x) ((x) << S_WL_ERR_CLK16_ST)
+#define F_WL_ERR_CLK16_ST    V_WL_ERR_CLK16_ST(1U)
+
+#define S_WL_ERR_CLK18_ST    10
+#define V_WL_ERR_CLK18_ST(x) ((x) << S_WL_ERR_CLK18_ST)
+#define F_WL_ERR_CLK18_ST    V_WL_ERR_CLK18_ST(1U)
+
+#define S_WL_ERR_CLK20_ST    9
+#define V_WL_ERR_CLK20_ST(x) ((x) << S_WL_ERR_CLK20_ST)
+#define F_WL_ERR_CLK20_ST    V_WL_ERR_CLK20_ST(1U)
+
+#define S_WL_ERR_CLK22_ST    8
+#define V_WL_ERR_CLK22_ST(x) ((x) << S_WL_ERR_CLK22_ST)
+#define F_WL_ERR_CLK22_ST    V_WL_ERR_CLK22_ST(1U)
+
+#define S_ZERO_DETECTED    7
+#define V_ZERO_DETECTED(x) ((x) << S_ZERO_DETECTED)
+#define F_ZERO_DETECTED    V_ZERO_DETECTED(1U)
+
+#define A_MC_DDRPHY_DP18_WR_CNTR_STATUS0 0x44060
+
+#define S_BIT_CENTERED    11
+#define M_BIT_CENTERED    0x1fU
+#define V_BIT_CENTERED(x) ((x) << S_BIT_CENTERED)
+#define G_BIT_CENTERED(x) (((x) >> S_BIT_CENTERED) & M_BIT_CENTERED)
+
+#define S_SMALL_STEP_LEFT    10
+#define V_SMALL_STEP_LEFT(x) ((x) << S_SMALL_STEP_LEFT)
+#define F_SMALL_STEP_LEFT    V_SMALL_STEP_LEFT(1U)
+
+#define S_BIG_STEP_RIGHT    9
+#define V_BIG_STEP_RIGHT(x) ((x) << S_BIG_STEP_RIGHT)
+#define F_BIG_STEP_RIGHT    V_BIG_STEP_RIGHT(1U)
+
+#define S_MATCH_STEP_RIGHT    8
+#define V_MATCH_STEP_RIGHT(x) ((x) << S_MATCH_STEP_RIGHT)
+#define F_MATCH_STEP_RIGHT    V_MATCH_STEP_RIGHT(1U)
+
+#define S_JUMP_BACK_RIGHT    7
+#define V_JUMP_BACK_RIGHT(x) ((x) << S_JUMP_BACK_RIGHT)
+#define F_JUMP_BACK_RIGHT    V_JUMP_BACK_RIGHT(1U)
+
+#define S_SMALL_STEP_RIGHT    6
+#define V_SMALL_STEP_RIGHT(x) ((x) << S_SMALL_STEP_RIGHT)
+#define F_SMALL_STEP_RIGHT    V_SMALL_STEP_RIGHT(1U)
+
+#define S_DDONE    5
+#define V_DDONE(x) ((x) << S_DDONE)
+#define F_DDONE    V_DDONE(1U)
+
+#define A_MC_DDRPHY_DP18_WR_CNTR_STATUS1 0x44064
+
+#define S_FW_LEFT_SIDE    5
+#define M_FW_LEFT_SIDE    0x7ffU
+#define V_FW_LEFT_SIDE(x) ((x) << S_FW_LEFT_SIDE)
+#define G_FW_LEFT_SIDE(x) (((x) >> S_FW_LEFT_SIDE) & M_FW_LEFT_SIDE)
+
+#define A_MC_DDRPHY_DP18_WR_CNTR_STATUS2 0x44068
+
+#define S_FW_RIGHT_SIDE    5
+#define M_FW_RIGHT_SIDE    0x7ffU
+#define V_FW_RIGHT_SIDE(x) ((x) << S_FW_RIGHT_SIDE)
+#define G_FW_RIGHT_SIDE(x) (((x) >> S_FW_RIGHT_SIDE) & M_FW_RIGHT_SIDE)
+
+#define A_MC_DDRPHY_DP18_WR_ERROR0 0x4406c
+
+#define S_WL_ERR_CLK16    15
+#define V_WL_ERR_CLK16(x) ((x) << S_WL_ERR_CLK16)
+#define F_WL_ERR_CLK16    V_WL_ERR_CLK16(1U)
+
+#define S_WL_ERR_CLK18    14
+#define V_WL_ERR_CLK18(x) ((x) << S_WL_ERR_CLK18)
+#define F_WL_ERR_CLK18    V_WL_ERR_CLK18(1U)
+
+#define S_WL_ERR_CLK20    13
+#define V_WL_ERR_CLK20(x) ((x) << S_WL_ERR_CLK20)
+#define F_WL_ERR_CLK20    V_WL_ERR_CLK20(1U)
+
+#define S_WL_ERR_CLK22    12
+#define V_WL_ERR_CLK22(x) ((x) << S_WL_ERR_CLK22)
+#define F_WL_ERR_CLK22    V_WL_ERR_CLK22(1U)
+
+#define S_VALID_NS_BIG_L    7
+#define V_VALID_NS_BIG_L(x) ((x) << S_VALID_NS_BIG_L)
+#define F_VALID_NS_BIG_L    V_VALID_NS_BIG_L(1U)
+
+#define S_INVALID_NS_SMALL_L    6
+#define V_INVALID_NS_SMALL_L(x) ((x) << S_INVALID_NS_SMALL_L)
+#define F_INVALID_NS_SMALL_L    V_INVALID_NS_SMALL_L(1U)
+
+#define S_VALID_NS_BIG_R    5
+#define V_VALID_NS_BIG_R(x) ((x) << S_VALID_NS_BIG_R)
+#define F_VALID_NS_BIG_R    V_VALID_NS_BIG_R(1U)
+
+#define S_INVALID_NS_BIG_R    4
+#define V_INVALID_NS_BIG_R(x) ((x) << S_INVALID_NS_BIG_R)
+#define F_INVALID_NS_BIG_R    V_INVALID_NS_BIG_R(1U)
+
+#define S_VALID_NS_JUMP_BACK    3
+#define V_VALID_NS_JUMP_BACK(x) ((x) << S_VALID_NS_JUMP_BACK)
+#define F_VALID_NS_JUMP_BACK    V_VALID_NS_JUMP_BACK(1U)
+
+#define S_INVALID_NS_SMALL_R    2
+#define V_INVALID_NS_SMALL_R(x) ((x) << S_INVALID_NS_SMALL_R)
+#define F_INVALID_NS_SMALL_R    V_INVALID_NS_SMALL_R(1U)
+
+#define S_OFFSET_ERR    1
+#define V_OFFSET_ERR(x) ((x) << S_OFFSET_ERR)
+#define F_OFFSET_ERR    V_OFFSET_ERR(1U)
+
+#define A_MC_DDRPHY_DP18_WR_ERROR_MASK0 0x44070
+
+#define S_WL_ERR_CLK16_MASK    15
+#define V_WL_ERR_CLK16_MASK(x) ((x) << S_WL_ERR_CLK16_MASK)
+#define F_WL_ERR_CLK16_MASK    V_WL_ERR_CLK16_MASK(1U)
+
+#define S_WL_ERR_CLK18_MASK    14
+#define V_WL_ERR_CLK18_MASK(x) ((x) << S_WL_ERR_CLK18_MASK)
+#define F_WL_ERR_CLK18_MASK    V_WL_ERR_CLK18_MASK(1U)
+
+#define S_WL_ERR_CLK20_MASK    13
+#define V_WL_ERR_CLK20_MASK(x) ((x) << S_WL_ERR_CLK20_MASK)
+#define F_WL_ERR_CLK20_MASK    V_WL_ERR_CLK20_MASK(1U)
+
+#define S_WR_ERR_CLK22_MASK    12
+#define V_WR_ERR_CLK22_MASK(x) ((x) << S_WR_ERR_CLK22_MASK)
+#define F_WR_ERR_CLK22_MASK    V_WR_ERR_CLK22_MASK(1U)
+
+#define S_VALID_NS_BIG_L_MASK    7
+#define V_VALID_NS_BIG_L_MASK(x) ((x) << S_VALID_NS_BIG_L_MASK)
+#define F_VALID_NS_BIG_L_MASK    V_VALID_NS_BIG_L_MASK(1U)
+
+#define S_INVALID_NS_SMALL_L_MASK    6
+#define V_INVALID_NS_SMALL_L_MASK(x) ((x) << S_INVALID_NS_SMALL_L_MASK)
+#define F_INVALID_NS_SMALL_L_MASK    V_INVALID_NS_SMALL_L_MASK(1U)
+
+#define S_VALID_NS_BIG_R_MASK    5
+#define V_VALID_NS_BIG_R_MASK(x) ((x) << S_VALID_NS_BIG_R_MASK)
+#define F_VALID_NS_BIG_R_MASK    V_VALID_NS_BIG_R_MASK(1U)
+
+#define S_INVALID_NS_BIG_R_MASK    4
+#define V_INVALID_NS_BIG_R_MASK(x) ((x) << S_INVALID_NS_BIG_R_MASK)
+#define F_INVALID_NS_BIG_R_MASK    V_INVALID_NS_BIG_R_MASK(1U)
+
+#define S_VALID_NS_JUMP_BACK_MASK    3
+#define V_VALID_NS_JUMP_BACK_MASK(x) ((x) << S_VALID_NS_JUMP_BACK_MASK)
+#define F_VALID_NS_JUMP_BACK_MASK    V_VALID_NS_JUMP_BACK_MASK(1U)
+
+#define S_INVALID_NS_SMALL_R_MASK    2
+#define V_INVALID_NS_SMALL_R_MASK(x) ((x) << S_INVALID_NS_SMALL_R_MASK)
+#define F_INVALID_NS_SMALL_R_MASK    V_INVALID_NS_SMALL_R_MASK(1U)
+
+#define S_OFFSET_ERR_MASK    1
+#define V_OFFSET_ERR_MASK(x) ((x) << S_OFFSET_ERR_MASK)
+#define F_OFFSET_ERR_MASK    V_OFFSET_ERR_MASK(1U)
+
+#define A_MC_DDRPHY_DP18_DFT_WRAP_STATUS 0x44074
+
+#define S_CHECKER_RESET    14
+#define V_CHECKER_RESET(x) ((x) << S_CHECKER_RESET)
+#define F_CHECKER_RESET    V_CHECKER_RESET(1U)
+
+#define S_DP18_DFT_SYNC    6
+#define M_DP18_DFT_SYNC    0x3fU
+#define V_DP18_DFT_SYNC(x) ((x) << S_DP18_DFT_SYNC)
+#define G_DP18_DFT_SYNC(x) (((x) >> S_DP18_DFT_SYNC) & M_DP18_DFT_SYNC)
+
+#define S_ERROR    0
+#define M_ERROR    0x3fU
+#define V_ERROR(x) ((x) << S_ERROR)
+#define G_ERROR(x) (((x) >> S_ERROR) & M_ERROR)
+
+#define A_MC_DDRPHY_DP18_RD_DIA_CONFIG0 0x44078
+#define A_MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR 0x440c0
+
+#define S_DQSCLK_ROT_CLK_N0_N2    8
+#define M_DQSCLK_ROT_CLK_N0_N2    0x7fU
+#define V_DQSCLK_ROT_CLK_N0_N2(x) ((x) << S_DQSCLK_ROT_CLK_N0_N2)
+#define G_DQSCLK_ROT_CLK_N0_N2(x) (((x) >> S_DQSCLK_ROT_CLK_N0_N2) & M_DQSCLK_ROT_CLK_N0_N2)
+
+#define S_DQSCLK_ROT_CLK_N1_N3    0
+#define M_DQSCLK_ROT_CLK_N1_N3    0x7fU
+#define V_DQSCLK_ROT_CLK_N1_N3(x) ((x) << S_DQSCLK_ROT_CLK_N1_N3)
+#define G_DQSCLK_ROT_CLK_N1_N3(x) (((x) >> S_DQSCLK_ROT_CLK_N1_N3) & M_DQSCLK_ROT_CLK_N1_N3)
+
+#define A_MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR 0x440c4
+#define A_MC_DDRPHY_DP18_PATTERN_POS_0 0x440c8
+
+#define S_MEMINTD00_POS    14
+#define M_MEMINTD00_POS    0x3U
+#define V_MEMINTD00_POS(x) ((x) << S_MEMINTD00_POS)
+#define G_MEMINTD00_POS(x) (((x) >> S_MEMINTD00_POS) & M_MEMINTD00_POS)
+
+#define S_MEMINTD01_PO    12
+#define M_MEMINTD01_PO    0x3U
+#define V_MEMINTD01_PO(x) ((x) << S_MEMINTD01_PO)
+#define G_MEMINTD01_PO(x) (((x) >> S_MEMINTD01_PO) & M_MEMINTD01_PO)
+
+#define S_MEMINTD02_POS    10
+#define M_MEMINTD02_POS    0x3U
+#define V_MEMINTD02_POS(x) ((x) << S_MEMINTD02_POS)
+#define G_MEMINTD02_POS(x) (((x) >> S_MEMINTD02_POS) & M_MEMINTD02_POS)
+
+#define S_MEMINTD03_POS    8
+#define M_MEMINTD03_POS    0x3U
+#define V_MEMINTD03_POS(x) ((x) << S_MEMINTD03_POS)
+#define G_MEMINTD03_POS(x) (((x) >> S_MEMINTD03_POS) & M_MEMINTD03_POS)
+
+#define S_MEMINTD04_POS    6
+#define M_MEMINTD04_POS    0x3U
+#define V_MEMINTD04_POS(x) ((x) << S_MEMINTD04_POS)
+#define G_MEMINTD04_POS(x) (((x) >> S_MEMINTD04_POS) & M_MEMINTD04_POS)
+
+#define S_MEMINTD05_POS    4
+#define M_MEMINTD05_POS    0x3U
+#define V_MEMINTD05_POS(x) ((x) << S_MEMINTD05_POS)
+#define G_MEMINTD05_POS(x) (((x) >> S_MEMINTD05_POS) & M_MEMINTD05_POS)
+
+#define S_MEMINTD06_POS    2
+#define M_MEMINTD06_POS    0x3U
+#define V_MEMINTD06_POS(x) ((x) << S_MEMINTD06_POS)
+#define G_MEMINTD06_POS(x) (((x) >> S_MEMINTD06_POS) & M_MEMINTD06_POS)
+
+#define S_MEMINTD07_POS    0
+#define M_MEMINTD07_POS    0x3U
+#define V_MEMINTD07_POS(x) ((x) << S_MEMINTD07_POS)
+#define G_MEMINTD07_POS(x) (((x) >> S_MEMINTD07_POS) & M_MEMINTD07_POS)
+
+#define A_MC_DDRPHY_DP18_PATTERN_POS_1 0x440cc
+
+#define S_MEMINTD08_POS    14
+#define M_MEMINTD08_POS    0x3U
+#define V_MEMINTD08_POS(x) ((x) << S_MEMINTD08_POS)
+#define G_MEMINTD08_POS(x) (((x) >> S_MEMINTD08_POS) & M_MEMINTD08_POS)
+
+#define S_MEMINTD09_POS    12
+#define M_MEMINTD09_POS    0x3U
+#define V_MEMINTD09_POS(x) ((x) << S_MEMINTD09_POS)
+#define G_MEMINTD09_POS(x) (((x) >> S_MEMINTD09_POS) & M_MEMINTD09_POS)
+
+#define S_MEMINTD10_POS    10
+#define M_MEMINTD10_POS    0x3U
+#define V_MEMINTD10_POS(x) ((x) << S_MEMINTD10_POS)
+#define G_MEMINTD10_POS(x) (((x) >> S_MEMINTD10_POS) & M_MEMINTD10_POS)
+
+#define S_MEMINTD11_POS    8
+#define M_MEMINTD11_POS    0x3U
+#define V_MEMINTD11_POS(x) ((x) << S_MEMINTD11_POS)
+#define G_MEMINTD11_POS(x) (((x) >> S_MEMINTD11_POS) & M_MEMINTD11_POS)
+
+#define S_MEMINTD12_POS    6
+#define M_MEMINTD12_POS    0x3U
+#define V_MEMINTD12_POS(x) ((x) << S_MEMINTD12_POS)
+#define G_MEMINTD12_POS(x) (((x) >> S_MEMINTD12_POS) & M_MEMINTD12_POS)
+
+#define S_MEMINTD13_POS    4
+#define M_MEMINTD13_POS    0x3U
+#define V_MEMINTD13_POS(x) ((x) << S_MEMINTD13_POS)
+#define G_MEMINTD13_POS(x) (((x) >> S_MEMINTD13_POS) & M_MEMINTD13_POS)
+
+#define S_MEMINTD14_POS    2
+#define M_MEMINTD14_POS    0x3U
+#define V_MEMINTD14_POS(x) ((x) << S_MEMINTD14_POS)
+#define G_MEMINTD14_POS(x) (((x) >> S_MEMINTD14_POS) & M_MEMINTD14_POS)
+
+#define S_MEMINTD15_POS    0
+#define M_MEMINTD15_POS    0x3U
+#define V_MEMINTD15_POS(x) ((x) << S_MEMINTD15_POS)
+#define G_MEMINTD15_POS(x) (((x) >> S_MEMINTD15_POS) & M_MEMINTD15_POS)
+
+#define A_MC_DDRPHY_DP18_PATTERN_POS_2 0x440d0
+
+#define S_MEMINTD16_POS    14
+#define M_MEMINTD16_POS    0x3U
+#define V_MEMINTD16_POS(x) ((x) << S_MEMINTD16_POS)
+#define G_MEMINTD16_POS(x) (((x) >> S_MEMINTD16_POS) & M_MEMINTD16_POS)
+
+#define S_MEMINTD17_POS    12
+#define M_MEMINTD17_POS    0x3U
+#define V_MEMINTD17_POS(x) ((x) << S_MEMINTD17_POS)
+#define G_MEMINTD17_POS(x) (((x) >> S_MEMINTD17_POS) & M_MEMINTD17_POS)
+
+#define S_MEMINTD18_POS    10
+#define M_MEMINTD18_POS    0x3U
+#define V_MEMINTD18_POS(x) ((x) << S_MEMINTD18_POS)
+#define G_MEMINTD18_POS(x) (((x) >> S_MEMINTD18_POS) & M_MEMINTD18_POS)
+
+#define S_MEMINTD19_POS    8
+#define M_MEMINTD19_POS    0x3U
+#define V_MEMINTD19_POS(x) ((x) << S_MEMINTD19_POS)
+#define G_MEMINTD19_POS(x) (((x) >> S_MEMINTD19_POS) & M_MEMINTD19_POS)
+
+#define S_MEMINTD20_POS    6
+#define M_MEMINTD20_POS    0x3U
+#define V_MEMINTD20_POS(x) ((x) << S_MEMINTD20_POS)
+#define G_MEMINTD20_POS(x) (((x) >> S_MEMINTD20_POS) & M_MEMINTD20_POS)
+
+#define S_MEMINTD21_POS    4
+#define M_MEMINTD21_POS    0x3U
+#define V_MEMINTD21_POS(x) ((x) << S_MEMINTD21_POS)
+#define G_MEMINTD21_POS(x) (((x) >> S_MEMINTD21_POS) & M_MEMINTD21_POS)
+
+#define S_MEMINTD22_POS    2
+#define M_MEMINTD22_POS    0x3U
+#define V_MEMINTD22_POS(x) ((x) << S_MEMINTD22_POS)
+#define G_MEMINTD22_POS(x) (((x) >> S_MEMINTD22_POS) & M_MEMINTD22_POS)
+
+#define S_MEMINTD23_POS    0
+#define M_MEMINTD23_POS    0x3U
+#define V_MEMINTD23_POS(x) ((x) << S_MEMINTD23_POS)
+#define G_MEMINTD23_POS(x) (((x) >> S_MEMINTD23_POS) & M_MEMINTD23_POS)
+
+#define A_MC_DDRPHY_DP18_RD_DIA_CONFIG1 0x440d4
+#define A_MC_DDRPHY_DP18_RD_DIA_CONFIG2 0x440d8
+#define A_MC_DDRPHY_DP18_DQSCLK_OFFSET 0x440dc
+
+#define S_DQS_OFFSET    8
+#define M_DQS_OFFSET    0x7fU
+#define V_DQS_OFFSET(x) ((x) << S_DQS_OFFSET)
+#define G_DQS_OFFSET(x) (((x) >> S_DQS_OFFSET) & M_DQS_OFFSET)
+
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP 0x440e0
+
+#define S_WR_DELAY    6
+#define M_WR_DELAY    0x3ffU
+#define V_WR_DELAY(x) ((x) << S_WR_DELAY)
+#define G_WR_DELAY(x) (((x) >> S_WR_DELAY) & M_WR_DELAY)
+
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP 0x440e4
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP 0x440e8
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP 0x440ec
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP 0x440f0
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP 0x440f4
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP 0x440f8
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP 0x440fc
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP 0x44100
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP 0x44104
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP 0x44108
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP 0x4410c
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP 0x44110
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP 0x44114
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP 0x44118
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP 0x4411c
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP 0x44120
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP 0x44124
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP 0x44128
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP 0x4412c
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP 0x44130
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP 0x44134
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP 0x44138
+#define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP 0x4413c
+#define A_MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR 0x44140
+
+#define S_RD_DELAY_BITS0_6    9
+#define M_RD_DELAY_BITS0_6    0x7fU
+#define V_RD_DELAY_BITS0_6(x) ((x) << S_RD_DELAY_BITS0_6)
+#define G_RD_DELAY_BITS0_6(x) (((x) >> S_RD_DELAY_BITS0_6) & M_RD_DELAY_BITS0_6)
+
+#define S_RD_DELAY_BITS8_14    1
+#define M_RD_DELAY_BITS8_14    0x7fU
+#define V_RD_DELAY_BITS8_14(x) ((x) << S_RD_DELAY_BITS8_14)
+#define G_RD_DELAY_BITS8_14(x) (((x) >> S_RD_DELAY_BITS8_14) & M_RD_DELAY_BITS8_14)
+
+#define A_MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR 0x44144
+#define A_MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR 0x44148
+#define A_MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR 0x4414c
+#define A_MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR 0x44150
+#define A_MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR 0x44154
+#define A_MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR 0x44158
+#define A_MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR 0x4415c
+#define A_MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR 0x44160
+#define A_MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR 0x44164
+#define A_MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR 0x44168
+#define A_MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR 0x4416c
+#define A_MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR 0x44170
+
+#define S_INITIAL_DQS_ROT_N0_N2    8
+#define M_INITIAL_DQS_ROT_N0_N2    0x7fU
+#define V_INITIAL_DQS_ROT_N0_N2(x) ((x) << S_INITIAL_DQS_ROT_N0_N2)
+#define G_INITIAL_DQS_ROT_N0_N2(x) (((x) >> S_INITIAL_DQS_ROT_N0_N2) & M_INITIAL_DQS_ROT_N0_N2)
+
+#define S_INITIAL_DQS_ROT_N1_N3    0
+#define M_INITIAL_DQS_ROT_N1_N3    0x7fU
+#define V_INITIAL_DQS_ROT_N1_N3(x) ((x) << S_INITIAL_DQS_ROT_N1_N3)
+#define G_INITIAL_DQS_ROT_N1_N3(x) (((x) >> S_INITIAL_DQS_ROT_N1_N3) & M_INITIAL_DQS_ROT_N1_N3)
+
+#define A_MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR 0x44174
+#define A_MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR 0x44180
+
+#define S_RD_EYE_SIZE_BITS2_7    8
+#define M_RD_EYE_SIZE_BITS2_7    0x3fU
+#define V_RD_EYE_SIZE_BITS2_7(x) ((x) << S_RD_EYE_SIZE_BITS2_7)
+#define G_RD_EYE_SIZE_BITS2_7(x) (((x) >> S_RD_EYE_SIZE_BITS2_7) & M_RD_EYE_SIZE_BITS2_7)
+
+#define S_RD_EYE_SIZE_BITS10_15    0
+#define M_RD_EYE_SIZE_BITS10_15    0x3fU
+#define V_RD_EYE_SIZE_BITS10_15(x) ((x) << S_RD_EYE_SIZE_BITS10_15)
+#define G_RD_EYE_SIZE_BITS10_15(x) (((x) >> S_RD_EYE_SIZE_BITS10_15) & M_RD_EYE_SIZE_BITS10_15)
+
+#define A_MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR 0x44184
+#define A_MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR 0x44188
+#define A_MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR 0x4418c
+#define A_MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR 0x44190
+#define A_MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR 0x44194
+#define A_MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR 0x44198
+#define A_MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR 0x4419c
+#define A_MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR 0x441a0
+#define A_MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR 0x441a4
+#define A_MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR 0x441a8
+#define A_MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR 0x441ac
+#define A_MC_DDRPHY_DP18_RD_DIA_CONFIG3 0x441b4
+#define A_MC_DDRPHY_DP18_RD_DIA_CONFIG4 0x441b8
+#define A_MC_DDRPHY_DP18_READ_TIMING_REFERENCE0 0x441c0
+
+#define S_REFERENCE_BITS1_7    8
+#define M_REFERENCE_BITS1_7    0x7fU
+#define V_REFERENCE_BITS1_7(x) ((x) << S_REFERENCE_BITS1_7)
+#define G_REFERENCE_BITS1_7(x) (((x) >> S_REFERENCE_BITS1_7) & M_REFERENCE_BITS1_7)
+
+#define S_REFERENCE_BITS9_15    0
+#define M_REFERENCE_BITS9_15    0x7fU
+#define V_REFERENCE_BITS9_15(x) ((x) << S_REFERENCE_BITS9_15)
+#define G_REFERENCE_BITS9_15(x) (((x) >> S_REFERENCE_BITS9_15) & M_REFERENCE_BITS9_15)
+
+#define A_MC_DDRPHY_DP18_READ_TIMING_REFERENCE1 0x441c4
+#define A_MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE 0x441c8
+
+#define S_REFERENCE    8
+#define M_REFERENCE    0x7fU
+#define V_REFERENCE(x) ((x) << S_REFERENCE)
+#define G_REFERENCE(x) (((x) >> S_REFERENCE) & M_REFERENCE)
+
+#define A_MC_DDRPHY_DP18_SYSCLK_PR_VALUE 0x441cc
+#define A_MC_DDRPHY_DP18_WRCLK_PR 0x441d0
+#define A_MC_DDRPHY_DP18_IO_TX_CONFIG0 0x441d4
+
+#define S_INTERP_SIG_SLEW    12
+#define M_INTERP_SIG_SLEW    0xfU
+#define V_INTERP_SIG_SLEW(x) ((x) << S_INTERP_SIG_SLEW)
+#define G_INTERP_SIG_SLEW(x) (((x) >> S_INTERP_SIG_SLEW) & M_INTERP_SIG_SLEW)
+
+#define S_POST_CURSOR    8
+#define M_POST_CURSOR    0xfU
+#define V_POST_CURSOR(x) ((x) << S_POST_CURSOR)
+#define G_POST_CURSOR(x) (((x) >> S_POST_CURSOR) & M_POST_CURSOR)
+
+#define S_SLEW_CTL    4
+#define M_SLEW_CTL    0xfU
+#define V_SLEW_CTL(x) ((x) << S_SLEW_CTL)
+#define G_SLEW_CTL(x) (((x) >> S_SLEW_CTL) & M_SLEW_CTL)
+
+#define A_MC_DDRPHY_DP18_PLL_CONFIG0 0x441d8
+#define A_MC_DDRPHY_DP18_PLL_CONFIG1 0x441dc
+
+#define S_CE0DLTVCCA    7
+#define V_CE0DLTVCCA(x) ((x) << S_CE0DLTVCCA)
+#define F_CE0DLTVCCA    V_CE0DLTVCCA(1U)
+
+#define S_CE0DLTVCCD1    4
+#define V_CE0DLTVCCD1(x) ((x) << S_CE0DLTVCCD1)
+#define F_CE0DLTVCCD1    V_CE0DLTVCCD1(1U)
+
+#define S_CE0DLTVCCD2    3
+#define V_CE0DLTVCCD2(x) ((x) << S_CE0DLTVCCD2)
+#define F_CE0DLTVCCD2    V_CE0DLTVCCD2(1U)
+
+#define S_S0INSDLYTAP    2
+#define V_S0INSDLYTAP(x) ((x) << S_S0INSDLYTAP)
+#define F_S0INSDLYTAP    V_S0INSDLYTAP(1U)
+
+#define S_S1INSDLYTAP    1
+#define V_S1INSDLYTAP(x) ((x) << S_S1INSDLYTAP)
+#define F_S1INSDLYTAP    V_S1INSDLYTAP(1U)
+
+#define A_MC_DDRPHY_DP18_IO_TX_NFET_SLICE 0x441e0
+
+#define S_EN_SLICE_N_WR    8
+#define M_EN_SLICE_N_WR    0xffU
+#define V_EN_SLICE_N_WR(x) ((x) << S_EN_SLICE_N_WR)
+#define G_EN_SLICE_N_WR(x) (((x) >> S_EN_SLICE_N_WR) & M_EN_SLICE_N_WR)
+
+#define A_MC_DDRPHY_DP18_IO_TX_PFET_SLICE 0x441e4
+#define A_MC_DDRPHY_DP18_IO_TX_NFET_TERM 0x441e8
+
+#define S_EN_TERM_N_WR    8
+#define M_EN_TERM_N_WR    0xffU
+#define V_EN_TERM_N_WR(x) ((x) << S_EN_TERM_N_WR)
+#define G_EN_TERM_N_WR(x) (((x) >> S_EN_TERM_N_WR) & M_EN_TERM_N_WR)
+
+#define S_EN_TERM_N_WR_FFE    4
+#define M_EN_TERM_N_WR_FFE    0xfU
+#define V_EN_TERM_N_WR_FFE(x) ((x) << S_EN_TERM_N_WR_FFE)
+#define G_EN_TERM_N_WR_FFE(x) (((x) >> S_EN_TERM_N_WR_FFE) & M_EN_TERM_N_WR_FFE)
+
+#define A_MC_DDRPHY_DP18_IO_TX_PFET_TERM 0x441ec
+
+#define S_EN_TERM_P_WR    8
+#define M_EN_TERM_P_WR    0xffU
+#define V_EN_TERM_P_WR(x) ((x) << S_EN_TERM_P_WR)
+#define G_EN_TERM_P_WR(x) (((x) >> S_EN_TERM_P_WR) & M_EN_TERM_P_WR)
+
+#define S_EN_TERM_P_WR_FFE    4
+#define M_EN_TERM_P_WR_FFE    0xfU
+#define V_EN_TERM_P_WR_FFE(x) ((x) << S_EN_TERM_P_WR_FFE)
+#define G_EN_TERM_P_WR_FFE(x) (((x) >> S_EN_TERM_P_WR_FFE) & M_EN_TERM_P_WR_FFE)
+
+#define A_MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP 0x441f0
+
+#define S_DATA_BIT_DISABLE_0_15    0
+#define M_DATA_BIT_DISABLE_0_15    0xffffU
+#define V_DATA_BIT_DISABLE_0_15(x) ((x) << S_DATA_BIT_DISABLE_0_15)
+#define G_DATA_BIT_DISABLE_0_15(x) (((x) >> S_DATA_BIT_DISABLE_0_15) & M_DATA_BIT_DISABLE_0_15)
+
+#define A_MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP 0x441f4
+
+#define S_DATA_BIT_DISABLE_16_23    8
+#define M_DATA_BIT_DISABLE_16_23    0xffU
+#define V_DATA_BIT_DISABLE_16_23(x) ((x) << S_DATA_BIT_DISABLE_16_23)
+#define G_DATA_BIT_DISABLE_16_23(x) (((x) >> S_DATA_BIT_DISABLE_16_23) & M_DATA_BIT_DISABLE_16_23)
+
+#define A_MC_DDRPHY_DP18_DQ_WR_OFFSET_RP 0x441f8
+
+#define S_DQ_WR_OFFSET_N0    12
+#define M_DQ_WR_OFFSET_N0    0xfU
+#define V_DQ_WR_OFFSET_N0(x) ((x) << S_DQ_WR_OFFSET_N0)
+#define G_DQ_WR_OFFSET_N0(x) (((x) >> S_DQ_WR_OFFSET_N0) & M_DQ_WR_OFFSET_N0)
+
+#define S_DQ_WR_OFFSET_N1    8
+#define M_DQ_WR_OFFSET_N1    0xfU
+#define V_DQ_WR_OFFSET_N1(x) ((x) << S_DQ_WR_OFFSET_N1)
+#define G_DQ_WR_OFFSET_N1(x) (((x) >> S_DQ_WR_OFFSET_N1) & M_DQ_WR_OFFSET_N1)
+
+#define S_DQ_WR_OFFSET_N2    4
+#define M_DQ_WR_OFFSET_N2    0xfU
+#define V_DQ_WR_OFFSET_N2(x) ((x) << S_DQ_WR_OFFSET_N2)
+#define G_DQ_WR_OFFSET_N2(x) (((x) >> S_DQ_WR_OFFSET_N2) & M_DQ_WR_OFFSET_N2)
+
+#define S_DQ_WR_OFFSET_N3    0
+#define M_DQ_WR_OFFSET_N3    0xfU
+#define V_DQ_WR_OFFSET_N3(x) ((x) << S_DQ_WR_OFFSET_N3)
+#define G_DQ_WR_OFFSET_N3(x) (((x) >> S_DQ_WR_OFFSET_N3) & M_DQ_WR_OFFSET_N3)
+
+#define A_MC_DDRPHY_DP18_POWERDOWN_1 0x441fc
+#define A_MC_ADR_DDRPHY_ADR_BIT_ENABLE 0x45000
+
+#define S_BIT_ENABLE_0_11    4
+#define M_BIT_ENABLE_0_11    0xfffU
+#define V_BIT_ENABLE_0_11(x) ((x) << S_BIT_ENABLE_0_11)
+#define G_BIT_ENABLE_0_11(x) (((x) >> S_BIT_ENABLE_0_11) & M_BIT_ENABLE_0_11)
+
+#define S_BIT_ENABLE_12_15    0
+#define M_BIT_ENABLE_12_15    0xfU
+#define V_BIT_ENABLE_12_15(x) ((x) << S_BIT_ENABLE_12_15)
+#define G_BIT_ENABLE_12_15(x) (((x) >> S_BIT_ENABLE_12_15) & M_BIT_ENABLE_12_15)
+
+#define A_MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE 0x45004
+
+#define S_DI_ADR0_ADR1    15
+#define V_DI_ADR0_ADR1(x) ((x) << S_DI_ADR0_ADR1)
+#define F_DI_ADR0_ADR1    V_DI_ADR0_ADR1(1U)
+
+#define S_DI_ADR2_ADR3    14
+#define V_DI_ADR2_ADR3(x) ((x) << S_DI_ADR2_ADR3)
+#define F_DI_ADR2_ADR3    V_DI_ADR2_ADR3(1U)
+
+#define S_DI_ADR4_ADR5    13
+#define V_DI_ADR4_ADR5(x) ((x) << S_DI_ADR4_ADR5)
+#define F_DI_ADR4_ADR5    V_DI_ADR4_ADR5(1U)
+
+#define S_DI_ADR6_ADR7    12
+#define V_DI_ADR6_ADR7(x) ((x) << S_DI_ADR6_ADR7)
+#define F_DI_ADR6_ADR7    V_DI_ADR6_ADR7(1U)
+
+#define S_DI_ADR8_ADR9    11
+#define V_DI_ADR8_ADR9(x) ((x) << S_DI_ADR8_ADR9)
+#define F_DI_ADR8_ADR9    V_DI_ADR8_ADR9(1U)
+
+#define S_DI_ADR10_ADR11    10
+#define V_DI_ADR10_ADR11(x) ((x) << S_DI_ADR10_ADR11)
+#define F_DI_ADR10_ADR11    V_DI_ADR10_ADR11(1U)
+
+#define S_DI_ADR12_ADR13    9
+#define V_DI_ADR12_ADR13(x) ((x) << S_DI_ADR12_ADR13)
+#define F_DI_ADR12_ADR13    V_DI_ADR12_ADR13(1U)
+
+#define S_DI_ADR14_ADR15    8
+#define V_DI_ADR14_ADR15(x) ((x) << S_DI_ADR14_ADR15)
+#define F_DI_ADR14_ADR15    V_DI_ADR14_ADR15(1U)
+
+#define A_MC_ADR_DDRPHY_ADR_DELAY0 0x45010
+
+#define S_ADR_DELAY_BITS1_7    8
+#define M_ADR_DELAY_BITS1_7    0x7fU
+#define V_ADR_DELAY_BITS1_7(x) ((x) << S_ADR_DELAY_BITS1_7)
+#define G_ADR_DELAY_BITS1_7(x) (((x) >> S_ADR_DELAY_BITS1_7) & M_ADR_DELAY_BITS1_7)
+
+#define S_ADR_DELAY_BITS9_15    0
+#define M_ADR_DELAY_BITS9_15    0x7fU
+#define V_ADR_DELAY_BITS9_15(x) ((x) << S_ADR_DELAY_BITS9_15)
+#define G_ADR_DELAY_BITS9_15(x) (((x) >> S_ADR_DELAY_BITS9_15) & M_ADR_DELAY_BITS9_15)
+
+#define A_MC_ADR_DDRPHY_ADR_DELAY1 0x45014
+#define A_MC_ADR_DDRPHY_ADR_DELAY2 0x45018
+#define A_MC_ADR_DDRPHY_ADR_DELAY3 0x4501c
+#define A_MC_ADR_DDRPHY_ADR_DELAY4 0x45020
+#define A_MC_ADR_DDRPHY_ADR_DELAY5 0x45024
+#define A_MC_ADR_DDRPHY_ADR_DELAY6 0x45028
+#define A_MC_ADR_DDRPHY_ADR_DELAY7 0x4502c
+#define A_MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL 0x45030
+
+#define S_ADR_TEST_LANE_PAIR_FAIL    8
+#define M_ADR_TEST_LANE_PAIR_FAIL    0xffU
+#define V_ADR_TEST_LANE_PAIR_FAIL(x) ((x) << S_ADR_TEST_LANE_PAIR_FAIL)
+#define G_ADR_TEST_LANE_PAIR_FAIL(x) (((x) >> S_ADR_TEST_LANE_PAIR_FAIL) & M_ADR_TEST_LANE_PAIR_FAIL)
+
+#define S_ADR_TEST_DATA_EN    7
+#define V_ADR_TEST_DATA_EN(x) ((x) << S_ADR_TEST_DATA_EN)
+#define F_ADR_TEST_DATA_EN    V_ADR_TEST_DATA_EN(1U)
+
+#define S_DADR_TEST_MODE    5
+#define M_DADR_TEST_MODE    0x3U
+#define V_DADR_TEST_MODE(x) ((x) << S_DADR_TEST_MODE)
+#define G_DADR_TEST_MODE(x) (((x) >> S_DADR_TEST_MODE) & M_DADR_TEST_MODE)
+
+#define S_ADR_TEST_4TO1_MODE    4
+#define V_ADR_TEST_4TO1_MODE(x) ((x) << S_ADR_TEST_4TO1_MODE)
+#define F_ADR_TEST_4TO1_MODE    V_ADR_TEST_4TO1_MODE(1U)
+
+#define S_ADR_TEST_RESET    3
+#define V_ADR_TEST_RESET(x) ((x) << S_ADR_TEST_RESET)
+#define F_ADR_TEST_RESET    V_ADR_TEST_RESET(1U)
+
+#define S_ADR_TEST_GEN_EN    2
+#define V_ADR_TEST_GEN_EN(x) ((x) << S_ADR_TEST_GEN_EN)
+#define F_ADR_TEST_GEN_EN    V_ADR_TEST_GEN_EN(1U)
+
+#define S_ADR_TEST_CLEAR_ERROR    1
+#define V_ADR_TEST_CLEAR_ERROR(x) ((x) << S_ADR_TEST_CLEAR_ERROR)
+#define F_ADR_TEST_CLEAR_ERROR    V_ADR_TEST_CLEAR_ERROR(1U)
+
+#define S_ADR_TEST_CHECK_EN    0
+#define V_ADR_TEST_CHECK_EN(x) ((x) << S_ADR_TEST_CHECK_EN)
+#define F_ADR_TEST_CHECK_EN    V_ADR_TEST_CHECK_EN(1U)
+
+#define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0 0x45040
+
+#define S_EN_SLICE_N_WR_0    8
+#define M_EN_SLICE_N_WR_0    0xffU
+#define V_EN_SLICE_N_WR_0(x) ((x) << S_EN_SLICE_N_WR_0)
+#define G_EN_SLICE_N_WR_0(x) (((x) >> S_EN_SLICE_N_WR_0) & M_EN_SLICE_N_WR_0)
+
+#define S_EN_SLICE_N_WR_FFE    4
+#define M_EN_SLICE_N_WR_FFE    0xfU
+#define V_EN_SLICE_N_WR_FFE(x) ((x) << S_EN_SLICE_N_WR_FFE)
+#define G_EN_SLICE_N_WR_FFE(x) (((x) >> S_EN_SLICE_N_WR_FFE) & M_EN_SLICE_N_WR_FFE)
+
+#define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1 0x45044
+
+#define S_EN_SLICE_N_WR_1    8
+#define M_EN_SLICE_N_WR_1    0xffU
+#define V_EN_SLICE_N_WR_1(x) ((x) << S_EN_SLICE_N_WR_1)
+#define G_EN_SLICE_N_WR_1(x) (((x) >> S_EN_SLICE_N_WR_1) & M_EN_SLICE_N_WR_1)
+
+#define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2 0x45048
+
+#define S_EN_SLICE_N_WR_2    8
+#define M_EN_SLICE_N_WR_2    0xffU
+#define V_EN_SLICE_N_WR_2(x) ((x) << S_EN_SLICE_N_WR_2)
+#define G_EN_SLICE_N_WR_2(x) (((x) >> S_EN_SLICE_N_WR_2) & M_EN_SLICE_N_WR_2)
+
+#define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3 0x4504c
+
+#define S_EN_SLICE_N_WR_3    8
+#define M_EN_SLICE_N_WR_3    0xffU
+#define V_EN_SLICE_N_WR_3(x) ((x) << S_EN_SLICE_N_WR_3)
+#define G_EN_SLICE_N_WR_3(x) (((x) >> S_EN_SLICE_N_WR_3) & M_EN_SLICE_N_WR_3)
+
+#define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0 0x45050
+
+#define S_EN_SLICE_P_WR    8
+#define M_EN_SLICE_P_WR    0xffU
+#define V_EN_SLICE_P_WR(x) ((x) << S_EN_SLICE_P_WR)
+#define G_EN_SLICE_P_WR(x) (((x) >> S_EN_SLICE_P_WR) & M_EN_SLICE_P_WR)
+
+#define S_EN_SLICE_P_WR_FFE    4
+#define M_EN_SLICE_P_WR_FFE    0xfU
+#define V_EN_SLICE_P_WR_FFE(x) ((x) << S_EN_SLICE_P_WR_FFE)
+#define G_EN_SLICE_P_WR_FFE(x) (((x) >> S_EN_SLICE_P_WR_FFE) & M_EN_SLICE_P_WR_FFE)
+
+#define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1 0x45054
+#define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2 0x45058
+#define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3 0x4505c
+#define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE 0x45060
+
+#define S_POST_CURSOR0    12
+#define M_POST_CURSOR0    0xfU
+#define V_POST_CURSOR0(x) ((x) << S_POST_CURSOR0)
+#define G_POST_CURSOR0(x) (((x) >> S_POST_CURSOR0) & M_POST_CURSOR0)
+
+#define S_POST_CURSOR1    8
+#define M_POST_CURSOR1    0xfU
+#define V_POST_CURSOR1(x) ((x) << S_POST_CURSOR1)
+#define G_POST_CURSOR1(x) (((x) >> S_POST_CURSOR1) & M_POST_CURSOR1)
+
+#define S_POST_CURSOR2    4
+#define M_POST_CURSOR2    0xfU
+#define V_POST_CURSOR2(x) ((x) << S_POST_CURSOR2)
+#define G_POST_CURSOR2(x) (((x) >> S_POST_CURSOR2) & M_POST_CURSOR2)
+
+#define S_POST_CURSOR3    0
+#define M_POST_CURSOR3    0xfU
+#define V_POST_CURSOR3(x) ((x) << S_POST_CURSOR3)
+#define G_POST_CURSOR3(x) (((x) >> S_POST_CURSOR3) & M_POST_CURSOR3)
+
+#define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE 0x45068
+
+#define S_SLEW_CTL0    12
+#define M_SLEW_CTL0    0xfU
+#define V_SLEW_CTL0(x) ((x) << S_SLEW_CTL0)
+#define G_SLEW_CTL0(x) (((x) >> S_SLEW_CTL0) & M_SLEW_CTL0)
+
+#define S_SLEW_CTL1    8
+#define M_SLEW_CTL1    0xfU
+#define V_SLEW_CTL1(x) ((x) << S_SLEW_CTL1)
+#define G_SLEW_CTL1(x) (((x) >> S_SLEW_CTL1) & M_SLEW_CTL1)
+
+#define S_SLEW_CTL2    4
+#define M_SLEW_CTL2    0xfU
+#define V_SLEW_CTL2(x) ((x) << S_SLEW_CTL2)
+#define G_SLEW_CTL2(x) (((x) >> S_SLEW_CTL2) & M_SLEW_CTL2)
+
+#define S_SLEW_CTL3    0
+#define M_SLEW_CTL3    0xfU
+#define V_SLEW_CTL3(x) ((x) << S_SLEW_CTL3)
+#define G_SLEW_CTL3(x) (((x) >> S_SLEW_CTL3) & M_SLEW_CTL3)
+
+#define A_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0 0x45080
+
+#define S_SLICE_SEL_REG_BITS0_1    14
+#define M_SLICE_SEL_REG_BITS0_1    0x3U
+#define V_SLICE_SEL_REG_BITS0_1(x) ((x) << S_SLICE_SEL_REG_BITS0_1)
+#define G_SLICE_SEL_REG_BITS0_1(x) (((x) >> S_SLICE_SEL_REG_BITS0_1) & M_SLICE_SEL_REG_BITS0_1)
+
+#define S_SLICE_SEL_REG_BITS2_3    12
+#define M_SLICE_SEL_REG_BITS2_3    0x3U
+#define V_SLICE_SEL_REG_BITS2_3(x) ((x) << S_SLICE_SEL_REG_BITS2_3)
+#define G_SLICE_SEL_REG_BITS2_3(x) (((x) >> S_SLICE_SEL_REG_BITS2_3) & M_SLICE_SEL_REG_BITS2_3)
+
+#define S_SLICE_SEL_REG_BITS4_5    10
+#define M_SLICE_SEL_REG_BITS4_5    0x3U
+#define V_SLICE_SEL_REG_BITS4_5(x) ((x) << S_SLICE_SEL_REG_BITS4_5)
+#define G_SLICE_SEL_REG_BITS4_5(x) (((x) >> S_SLICE_SEL_REG_BITS4_5) & M_SLICE_SEL_REG_BITS4_5)
+
+#define S_SLICE_SEL_REG_BITS6_7    8
+#define M_SLICE_SEL_REG_BITS6_7    0x3U
+#define V_SLICE_SEL_REG_BITS6_7(x) ((x) << S_SLICE_SEL_REG_BITS6_7)
+#define G_SLICE_SEL_REG_BITS6_7(x) (((x) >> S_SLICE_SEL_REG_BITS6_7) & M_SLICE_SEL_REG_BITS6_7)
+
+#define S_SLICE_SEL_REG_BITS8_9    6
+#define M_SLICE_SEL_REG_BITS8_9    0x3U
+#define V_SLICE_SEL_REG_BITS8_9(x) ((x) << S_SLICE_SEL_REG_BITS8_9)
+#define G_SLICE_SEL_REG_BITS8_9(x) (((x) >> S_SLICE_SEL_REG_BITS8_9) & M_SLICE_SEL_REG_BITS8_9)
+
+#define S_SLICE_SEL_REG_BITS10_11    4
+#define M_SLICE_SEL_REG_BITS10_11    0x3U
+#define V_SLICE_SEL_REG_BITS10_11(x) ((x) << S_SLICE_SEL_REG_BITS10_11)
+#define G_SLICE_SEL_REG_BITS10_11(x) (((x) >> S_SLICE_SEL_REG_BITS10_11) & M_SLICE_SEL_REG_BITS10_11)
+
+#define S_SLICE_SEL_REG_BITS12_13    2
+#define M_SLICE_SEL_REG_BITS12_13    0x3U
+#define V_SLICE_SEL_REG_BITS12_13(x) ((x) << S_SLICE_SEL_REG_BITS12_13)
+#define G_SLICE_SEL_REG_BITS12_13(x) (((x) >> S_SLICE_SEL_REG_BITS12_13) & M_SLICE_SEL_REG_BITS12_13)
+
+#define S_SLICE_SEL_REG_BITS14_15    0
+#define M_SLICE_SEL_REG_BITS14_15    0x3U
+#define V_SLICE_SEL_REG_BITS14_15(x) ((x) << S_SLICE_SEL_REG_BITS14_15)
+#define G_SLICE_SEL_REG_BITS14_15(x) (((x) >> S_SLICE_SEL_REG_BITS14_15) & M_SLICE_SEL_REG_BITS14_15)
+
+#define A_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1 0x45084
+#define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0 0x450a0
+
+#define S_POST_CUR_SEL_BITS0_1    14
+#define M_POST_CUR_SEL_BITS0_1    0x3U
+#define V_POST_CUR_SEL_BITS0_1(x) ((x) << S_POST_CUR_SEL_BITS0_1)
+#define G_POST_CUR_SEL_BITS0_1(x) (((x) >> S_POST_CUR_SEL_BITS0_1) & M_POST_CUR_SEL_BITS0_1)
+
+#define S_POST_CUR_SEL_BITS2_3    12
+#define M_POST_CUR_SEL_BITS2_3    0x3U
+#define V_POST_CUR_SEL_BITS2_3(x) ((x) << S_POST_CUR_SEL_BITS2_3)
+#define G_POST_CUR_SEL_BITS2_3(x) (((x) >> S_POST_CUR_SEL_BITS2_3) & M_POST_CUR_SEL_BITS2_3)
+
+#define S_POST_CUR_SEL_BITS4_5    10
+#define M_POST_CUR_SEL_BITS4_5    0x3U
+#define V_POST_CUR_SEL_BITS4_5(x) ((x) << S_POST_CUR_SEL_BITS4_5)
+#define G_POST_CUR_SEL_BITS4_5(x) (((x) >> S_POST_CUR_SEL_BITS4_5) & M_POST_CUR_SEL_BITS4_5)
+
+#define S_POST_CUR_SEL_BITS6_7    8
+#define M_POST_CUR_SEL_BITS6_7    0x3U
+#define V_POST_CUR_SEL_BITS6_7(x) ((x) << S_POST_CUR_SEL_BITS6_7)
+#define G_POST_CUR_SEL_BITS6_7(x) (((x) >> S_POST_CUR_SEL_BITS6_7) & M_POST_CUR_SEL_BITS6_7)
+
+#define S_POST_CUR_SEL_BITS8_9    6
+#define M_POST_CUR_SEL_BITS8_9    0x3U
+#define V_POST_CUR_SEL_BITS8_9(x) ((x) << S_POST_CUR_SEL_BITS8_9)
+#define G_POST_CUR_SEL_BITS8_9(x) (((x) >> S_POST_CUR_SEL_BITS8_9) & M_POST_CUR_SEL_BITS8_9)
+
+#define S_POST_CUR_SEL_BITS10_11    4
+#define M_POST_CUR_SEL_BITS10_11    0x3U
+#define V_POST_CUR_SEL_BITS10_11(x) ((x) << S_POST_CUR_SEL_BITS10_11)
+#define G_POST_CUR_SEL_BITS10_11(x) (((x) >> S_POST_CUR_SEL_BITS10_11) & M_POST_CUR_SEL_BITS10_11)
+
+#define S_POST_CUR_SEL_BITS12_13    2
+#define M_POST_CUR_SEL_BITS12_13    0x3U
+#define V_POST_CUR_SEL_BITS12_13(x) ((x) << S_POST_CUR_SEL_BITS12_13)
+#define G_POST_CUR_SEL_BITS12_13(x) (((x) >> S_POST_CUR_SEL_BITS12_13) & M_POST_CUR_SEL_BITS12_13)
+
+#define S_POST_CUR_SEL_BITS14_15    0
+#define M_POST_CUR_SEL_BITS14_15    0x3U
+#define V_POST_CUR_SEL_BITS14_15(x) ((x) << S_POST_CUR_SEL_BITS14_15)
+#define G_POST_CUR_SEL_BITS14_15(x) (((x) >> S_POST_CUR_SEL_BITS14_15) & M_POST_CUR_SEL_BITS14_15)
+
+#define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1 0x450a4
+#define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0 0x450a8
+
+#define S_SLEW_CTL_SEL_BITS0_1    14
+#define M_SLEW_CTL_SEL_BITS0_1    0x3U
+#define V_SLEW_CTL_SEL_BITS0_1(x) ((x) << S_SLEW_CTL_SEL_BITS0_1)
+#define G_SLEW_CTL_SEL_BITS0_1(x) (((x) >> S_SLEW_CTL_SEL_BITS0_1) & M_SLEW_CTL_SEL_BITS0_1)
+
+#define S_SLEW_CTL_SEL_BITS2_3    12
+#define M_SLEW_CTL_SEL_BITS2_3    0x3U
+#define V_SLEW_CTL_SEL_BITS2_3(x) ((x) << S_SLEW_CTL_SEL_BITS2_3)
+#define G_SLEW_CTL_SEL_BITS2_3(x) (((x) >> S_SLEW_CTL_SEL_BITS2_3) & M_SLEW_CTL_SEL_BITS2_3)
+
+#define S_SLEW_CTL_SEL_BITS4_5    10
+#define M_SLEW_CTL_SEL_BITS4_5    0x3U
+#define V_SLEW_CTL_SEL_BITS4_5(x) ((x) << S_SLEW_CTL_SEL_BITS4_5)
+#define G_SLEW_CTL_SEL_BITS4_5(x) (((x) >> S_SLEW_CTL_SEL_BITS4_5) & M_SLEW_CTL_SEL_BITS4_5)
+
+#define S_SLEW_CTL_SEL_BITS6_7    8
+#define M_SLEW_CTL_SEL_BITS6_7    0x3U
+#define V_SLEW_CTL_SEL_BITS6_7(x) ((x) << S_SLEW_CTL_SEL_BITS6_7)
+#define G_SLEW_CTL_SEL_BITS6_7(x) (((x) >> S_SLEW_CTL_SEL_BITS6_7) & M_SLEW_CTL_SEL_BITS6_7)
+
+#define S_SLEW_CTL_SEL_BITS8_9    6
+#define M_SLEW_CTL_SEL_BITS8_9    0x3U
+#define V_SLEW_CTL_SEL_BITS8_9(x) ((x) << S_SLEW_CTL_SEL_BITS8_9)
+#define G_SLEW_CTL_SEL_BITS8_9(x) (((x) >> S_SLEW_CTL_SEL_BITS8_9) & M_SLEW_CTL_SEL_BITS8_9)
+
+#define S_SLEW_CTL_SEL_BITS10_11    4
+#define M_SLEW_CTL_SEL_BITS10_11    0x3U
+#define V_SLEW_CTL_SEL_BITS10_11(x) ((x) << S_SLEW_CTL_SEL_BITS10_11)
+#define G_SLEW_CTL_SEL_BITS10_11(x) (((x) >> S_SLEW_CTL_SEL_BITS10_11) & M_SLEW_CTL_SEL_BITS10_11)
+
+#define S_SLEW_CTL_SEL_BITS12_13    2
+#define M_SLEW_CTL_SEL_BITS12_13    0x3U
+#define V_SLEW_CTL_SEL_BITS12_13(x) ((x) << S_SLEW_CTL_SEL_BITS12_13)
+#define G_SLEW_CTL_SEL_BITS12_13(x) (((x) >> S_SLEW_CTL_SEL_BITS12_13) & M_SLEW_CTL_SEL_BITS12_13)
+
+#define S_SLEW_CTL_SEL_BITS14_15    0
+#define M_SLEW_CTL_SEL_BITS14_15    0x3U
+#define V_SLEW_CTL_SEL_BITS14_15(x) ((x) << S_SLEW_CTL_SEL_BITS14_15)
+#define G_SLEW_CTL_SEL_BITS14_15(x) (((x) >> S_SLEW_CTL_SEL_BITS14_15) & M_SLEW_CTL_SEL_BITS14_15)
+
+#define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1 0x450ac
+#define A_MC_ADR_DDRPHY_ADR_POWERDOWN_2 0x450b0
+
+#define S_ADR_LANE_0_11_PD    4
+#define M_ADR_LANE_0_11_PD    0xfffU
+#define V_ADR_LANE_0_11_PD(x) ((x) << S_ADR_LANE_0_11_PD)
+#define G_ADR_LANE_0_11_PD(x) (((x) >> S_ADR_LANE_0_11_PD) & M_ADR_LANE_0_11_PD)
+
+#define S_ADR_LANE_12_15_PD    0
+#define M_ADR_LANE_12_15_PD    0xfU
+#define V_ADR_LANE_12_15_PD(x) ((x) << S_ADR_LANE_12_15_PD)
+#define G_ADR_LANE_12_15_PD(x) (((x) >> S_ADR_LANE_12_15_PD) & M_ADR_LANE_12_15_PD)
+
+#define A_MC_DDRPHY_ADR_PLL_VREG_CONFIG_0 0x460c0
+
+#define S_PLL_TUNE_0_2    13
+#define M_PLL_TUNE_0_2    0x7U
+#define V_PLL_TUNE_0_2(x) ((x) << S_PLL_TUNE_0_2)
+#define G_PLL_TUNE_0_2(x) (((x) >> S_PLL_TUNE_0_2) & M_PLL_TUNE_0_2)
+
+#define S_PLL_TUNECP_0_2    10
+#define M_PLL_TUNECP_0_2    0x7U
+#define V_PLL_TUNECP_0_2(x) ((x) << S_PLL_TUNECP_0_2)
+#define G_PLL_TUNECP_0_2(x) (((x) >> S_PLL_TUNECP_0_2) & M_PLL_TUNECP_0_2)
+
+#define S_PLL_TUNEF_0_5    4
+#define M_PLL_TUNEF_0_5    0x3fU
+#define V_PLL_TUNEF_0_5(x) ((x) << S_PLL_TUNEF_0_5)
+#define G_PLL_TUNEF_0_5(x) (((x) >> S_PLL_TUNEF_0_5) & M_PLL_TUNEF_0_5)
+
+#define S_PLL_TUNEVCO_0_1    2
+#define M_PLL_TUNEVCO_0_1    0x3U
+#define V_PLL_TUNEVCO_0_1(x) ((x) << S_PLL_TUNEVCO_0_1)
+#define G_PLL_TUNEVCO_0_1(x) (((x) >> S_PLL_TUNEVCO_0_1) & M_PLL_TUNEVCO_0_1)
+
+#define S_PLL_PLLXTR_0_1    0
+#define M_PLL_PLLXTR_0_1    0x3U
+#define V_PLL_PLLXTR_0_1(x) ((x) << S_PLL_PLLXTR_0_1)
+#define G_PLL_PLLXTR_0_1(x) (((x) >> S_PLL_PLLXTR_0_1) & M_PLL_PLLXTR_0_1)
+
+#define A_MC_DDRPHY_ADR_PLL_VREG_CONFIG_1 0x460c4
+
+#define S_PLL_TUNETDIV_0_2    13
+#define M_PLL_TUNETDIV_0_2    0x7U
+#define V_PLL_TUNETDIV_0_2(x) ((x) << S_PLL_TUNETDIV_0_2)
+#define G_PLL_TUNETDIV_0_2(x) (((x) >> S_PLL_TUNETDIV_0_2) & M_PLL_TUNETDIV_0_2)
+
+#define S_PLL_TUNEMDIV_0_1    11
+#define M_PLL_TUNEMDIV_0_1    0x3U
+#define V_PLL_TUNEMDIV_0_1(x) ((x) << S_PLL_TUNEMDIV_0_1)
+#define G_PLL_TUNEMDIV_0_1(x) (((x) >> S_PLL_TUNEMDIV_0_1) & M_PLL_TUNEMDIV_0_1)
+
+#define S_PLL_TUNEATST    10
+#define V_PLL_TUNEATST(x) ((x) << S_PLL_TUNEATST)
+#define F_PLL_TUNEATST    V_PLL_TUNEATST(1U)
+
+#define S_VREG_RANGE_0_1    8
+#define M_VREG_RANGE_0_1    0x3U
+#define V_VREG_RANGE_0_1(x) ((x) << S_VREG_RANGE_0_1)
+#define G_VREG_RANGE_0_1(x) (((x) >> S_VREG_RANGE_0_1) & M_VREG_RANGE_0_1)
+
+#define S_VREG_VREGSPARE    7
+#define V_VREG_VREGSPARE(x) ((x) << S_VREG_VREGSPARE)
+#define F_VREG_VREGSPARE    V_VREG_VREGSPARE(1U)
+
+#define S_VREG_VCCTUNE_0_1    5
+#define M_VREG_VCCTUNE_0_1    0x3U
+#define V_VREG_VCCTUNE_0_1(x) ((x) << S_VREG_VCCTUNE_0_1)
+#define G_VREG_VCCTUNE_0_1(x) (((x) >> S_VREG_VCCTUNE_0_1) & M_VREG_VCCTUNE_0_1)
+
+#define S_INTERP_SIG_SLEW_0_3    1
+#define M_INTERP_SIG_SLEW_0_3    0xfU
+#define V_INTERP_SIG_SLEW_0_3(x) ((x) << S_INTERP_SIG_SLEW_0_3)
+#define G_INTERP_SIG_SLEW_0_3(x) (((x) >> S_INTERP_SIG_SLEW_0_3) & M_INTERP_SIG_SLEW_0_3)
+
+#define S_ANALOG_WRAPON    0
+#define V_ANALOG_WRAPON(x) ((x) << S_ANALOG_WRAPON)
+#define F_ANALOG_WRAPON    V_ANALOG_WRAPON(1U)
+
+#define A_MC_DDRPHY_ADR_SYSCLK_CNTL_PR 0x460c8
+
+#define S_SYSCLK_ENABLE    15
+#define V_SYSCLK_ENABLE(x) ((x) << S_SYSCLK_ENABLE)
+#define F_SYSCLK_ENABLE    V_SYSCLK_ENABLE(1U)
+
+#define S_SYSCLK_ROT_OVERRIDE    8
+#define M_SYSCLK_ROT_OVERRIDE    0x7fU
+#define V_SYSCLK_ROT_OVERRIDE(x) ((x) << S_SYSCLK_ROT_OVERRIDE)
+#define G_SYSCLK_ROT_OVERRIDE(x) (((x) >> S_SYSCLK_ROT_OVERRIDE) & M_SYSCLK_ROT_OVERRIDE)
+
+#define S_SYSCLK_ROT_OVERRIDE_EN    7
+#define V_SYSCLK_ROT_OVERRIDE_EN(x) ((x) << S_SYSCLK_ROT_OVERRIDE_EN)
+#define F_SYSCLK_ROT_OVERRIDE_EN    V_SYSCLK_ROT_OVERRIDE_EN(1U)
+
+#define S_SYSCLK_PHASE_ALIGN_RESE    6
+#define V_SYSCLK_PHASE_ALIGN_RESE(x) ((x) << S_SYSCLK_PHASE_ALIGN_RESE)
+#define F_SYSCLK_PHASE_ALIGN_RESE    V_SYSCLK_PHASE_ALIGN_RESE(1U)
+
+#define S_SYSCLK_PHASE_CNTL_EN    5
+#define V_SYSCLK_PHASE_CNTL_EN(x) ((x) << S_SYSCLK_PHASE_CNTL_EN)
+#define F_SYSCLK_PHASE_CNTL_EN    V_SYSCLK_PHASE_CNTL_EN(1U)
+
+#define S_SYSCLK_PHASE_DEFAULT_EN    4
+#define V_SYSCLK_PHASE_DEFAULT_EN(x) ((x) << S_SYSCLK_PHASE_DEFAULT_EN)
+#define F_SYSCLK_PHASE_DEFAULT_EN    V_SYSCLK_PHASE_DEFAULT_EN(1U)
+
+#define S_SYSCLK_POS_EDGE_ALIGN    3
+#define V_SYSCLK_POS_EDGE_ALIGN(x) ((x) << S_SYSCLK_POS_EDGE_ALIGN)
+#define F_SYSCLK_POS_EDGE_ALIGN    V_SYSCLK_POS_EDGE_ALIGN(1U)
+
+#define S_CONTINUOUS_UPDATE    2
+#define V_CONTINUOUS_UPDATE(x) ((x) << S_CONTINUOUS_UPDATE)
+#define F_CONTINUOUS_UPDATE    V_CONTINUOUS_UPDATE(1U)
+
+#define S_CE0DLTVCC    0
+#define M_CE0DLTVCC    0x3U
+#define V_CE0DLTVCC(x) ((x) << S_CE0DLTVCC)
+#define G_CE0DLTVCC(x) (((x) >> S_CE0DLTVCC) & M_CE0DLTVCC)
+
+#define A_MC_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET 0x460cc
+
+#define S_TSYS_WRCLK    8
+#define M_TSYS_WRCLK    0x7fU
+#define V_TSYS_WRCLK(x) ((x) << S_TSYS_WRCLK)
+#define G_TSYS_WRCLK(x) (((x) >> S_TSYS_WRCLK) & M_TSYS_WRCLK)
+
+#define A_MC_DDRPHY_ADR_SYSCLK_PR_VALUE_RO 0x460d0
+
+#define S_SLEW_LATE_SAMPLE    15
+#define V_SLEW_LATE_SAMPLE(x) ((x) << S_SLEW_LATE_SAMPLE)
+#define F_SLEW_LATE_SAMPLE    V_SLEW_LATE_SAMPLE(1U)
+
+#define S_SYSCLK_ROT    8
+#define M_SYSCLK_ROT    0x7fU
+#define V_SYSCLK_ROT(x) ((x) << S_SYSCLK_ROT)
+#define G_SYSCLK_ROT(x) (((x) >> S_SYSCLK_ROT) & M_SYSCLK_ROT)
+
+#define S_BB_LOCK    7
+#define V_BB_LOCK(x) ((x) << S_BB_LOCK)
+#define F_BB_LOCK    V_BB_LOCK(1U)
+
+#define S_SLEW_EARLY_SAMPLE    6
+#define V_SLEW_EARLY_SAMPLE(x) ((x) << S_SLEW_EARLY_SAMPLE)
+#define F_SLEW_EARLY_SAMPLE    V_SLEW_EARLY_SAMPLE(1U)
+
+#define S_SLEW_DONE_STATUS    4
+#define M_SLEW_DONE_STATUS    0x3U
+#define V_SLEW_DONE_STATUS(x) ((x) << S_SLEW_DONE_STATUS)
+#define G_SLEW_DONE_STATUS(x) (((x) >> S_SLEW_DONE_STATUS) & M_SLEW_DONE_STATUS)
+
+#define S_SLEW_CNTL    0
+#define M_SLEW_CNTL    0xfU
+#define V_SLEW_CNTL(x) ((x) << S_SLEW_CNTL)
+#define G_SLEW_CNTL(x) (((x) >> S_SLEW_CNTL) & M_SLEW_CNTL)
+
+#define A_MC_DDRPHY_ADR_GMTEST_ATEST_CNTL 0x460d4
+
+#define S_FLUSH    15
+#define V_FLUSH(x) ((x) << S_FLUSH)
+#define F_FLUSH    V_FLUSH(1U)
+
+#define S_GIANT_MUX_TEST_EN    14
+#define V_GIANT_MUX_TEST_EN(x) ((x) << S_GIANT_MUX_TEST_EN)
+#define F_GIANT_MUX_TEST_EN    V_GIANT_MUX_TEST_EN(1U)
+
+#define S_GIANT_MUX_TEST_VAL    13
+#define V_GIANT_MUX_TEST_VAL(x) ((x) << S_GIANT_MUX_TEST_VAL)
+#define F_GIANT_MUX_TEST_VAL    V_GIANT_MUX_TEST_VAL(1U)
+
+#define S_HS_PROBE_A_SEL_    8
+#define M_HS_PROBE_A_SEL_    0xfU
+#define V_HS_PROBE_A_SEL_(x) ((x) << S_HS_PROBE_A_SEL_)
+#define G_HS_PROBE_A_SEL_(x) (((x) >> S_HS_PROBE_A_SEL_) & M_HS_PROBE_A_SEL_)
+
+#define S_HS_PROBE_B_SEL_    4
+#define M_HS_PROBE_B_SEL_    0xfU
+#define V_HS_PROBE_B_SEL_(x) ((x) << S_HS_PROBE_B_SEL_)
+#define G_HS_PROBE_B_SEL_(x) (((x) >> S_HS_PROBE_B_SEL_) & M_HS_PROBE_B_SEL_)
+
+#define S_ATEST1CTL0    3
+#define V_ATEST1CTL0(x) ((x) << S_ATEST1CTL0)
+#define F_ATEST1CTL0    V_ATEST1CTL0(1U)
+
+#define S_ATEST1CTL1    2
+#define V_ATEST1CTL1(x) ((x) << S_ATEST1CTL1)
+#define F_ATEST1CTL1    V_ATEST1CTL1(1U)
+
+#define S_ATEST1CTL2    1
+#define V_ATEST1CTL2(x) ((x) << S_ATEST1CTL2)
+#define F_ATEST1CTL2    V_ATEST1CTL2(1U)
+
+#define S_ATEST1CTL3    0
+#define V_ATEST1CTL3(x) ((x) << S_ATEST1CTL3)
+#define F_ATEST1CTL3    V_ATEST1CTL3(1U)
+
+#define A_MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A0 0x460d8
+
+#define S_GIANT_MUX_TEST_RESULTS    0
+#define M_GIANT_MUX_TEST_RESULTS    0xffffU
+#define V_GIANT_MUX_TEST_RESULTS(x) ((x) << S_GIANT_MUX_TEST_RESULTS)
+#define G_GIANT_MUX_TEST_RESULTS(x) (((x) >> S_GIANT_MUX_TEST_RESULTS) & M_GIANT_MUX_TEST_RESULTS)
+
+#define A_MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A1 0x460dc
+#define A_MC_DDRPHY_ADR_POWERDOWN_1 0x460e0
+
+#define S_MASTER_PD_CNTL    15
+#define V_MASTER_PD_CNTL(x) ((x) << S_MASTER_PD_CNTL)
+#define F_MASTER_PD_CNTL    V_MASTER_PD_CNTL(1U)
+
+#define S_ANALOG_INPUT_STAB2    14
+#define V_ANALOG_INPUT_STAB2(x) ((x) << S_ANALOG_INPUT_STAB2)
+#define F_ANALOG_INPUT_STAB2    V_ANALOG_INPUT_STAB2(1U)
+
+#define S_ANALOG_INPUT_STAB1    8
+#define V_ANALOG_INPUT_STAB1(x) ((x) << S_ANALOG_INPUT_STAB1)
+#define F_ANALOG_INPUT_STAB1    V_ANALOG_INPUT_STAB1(1U)
+
+#define S_SYSCLK_CLK_GATE    6
+#define M_SYSCLK_CLK_GATE    0x3U
+#define V_SYSCLK_CLK_GATE(x) ((x) << S_SYSCLK_CLK_GATE)
+#define G_SYSCLK_CLK_GATE(x) (((x) >> S_SYSCLK_CLK_GATE) & M_SYSCLK_CLK_GATE)
+
+#define S_WR_FIFO_STAB    5
+#define V_WR_FIFO_STAB(x) ((x) << S_WR_FIFO_STAB)
+#define F_WR_FIFO_STAB    V_WR_FIFO_STAB(1U)
+
+#define S_ADR_RX_PD    4
+#define V_ADR_RX_PD(x) ((x) << S_ADR_RX_PD)
+#define F_ADR_RX_PD    V_ADR_RX_PD(1U)
+
+#define S_TX_TRISTATE_CNTL    1
+#define V_TX_TRISTATE_CNTL(x) ((x) << S_TX_TRISTATE_CNTL)
+#define F_TX_TRISTATE_CNTL    V_TX_TRISTATE_CNTL(1U)
+
+#define S_DVCC_REG_PD    0
+#define V_DVCC_REG_PD(x) ((x) << S_DVCC_REG_PD)
+#define F_DVCC_REG_PD    V_DVCC_REG_PD(1U)
+
+#define A_MC_DDRPHY_ADR_SLEW_CAL_CNTL 0x460e4
+
+#define S_SLEW_CAL_ENABLE    15
+#define V_SLEW_CAL_ENABLE(x) ((x) << S_SLEW_CAL_ENABLE)
+#define F_SLEW_CAL_ENABLE    V_SLEW_CAL_ENABLE(1U)
+
+#define S_SLEW_CAL_START    14
+#define V_SLEW_CAL_START(x) ((x) << S_SLEW_CAL_START)
+#define F_SLEW_CAL_START    V_SLEW_CAL_START(1U)
+
+#define S_SLEW_CAL_OVERRIDE_EN    12
+#define V_SLEW_CAL_OVERRIDE_EN(x) ((x) << S_SLEW_CAL_OVERRIDE_EN)
+#define F_SLEW_CAL_OVERRIDE_EN    V_SLEW_CAL_OVERRIDE_EN(1U)
+
+#define S_SLEW_CAL_OVERRIDE    8
+#define M_SLEW_CAL_OVERRIDE    0xfU
+#define V_SLEW_CAL_OVERRIDE(x) ((x) << S_SLEW_CAL_OVERRIDE)
+#define G_SLEW_CAL_OVERRIDE(x) (((x) >> S_SLEW_CAL_OVERRIDE) & M_SLEW_CAL_OVERRIDE)
+
+#define S_SLEW_TARGET_PR_OFFSET    0
+#define M_SLEW_TARGET_PR_OFFSET    0x1fU
+#define V_SLEW_TARGET_PR_OFFSET(x) ((x) << S_SLEW_TARGET_PR_OFFSET)
+#define G_SLEW_TARGET_PR_OFFSET(x) (((x) >> S_SLEW_TARGET_PR_OFFSET) & M_SLEW_TARGET_PR_OFFSET)
+
+#define A_MC_DDRPHY_PC_DP18_PLL_LOCK_STATUS 0x47000
+
+#define S_DP18_PLL_LOCK    1
+#define M_DP18_PLL_LOCK    0x7fffU
+#define V_DP18_PLL_LOCK(x) ((x) << S_DP18_PLL_LOCK)
+#define G_DP18_PLL_LOCK(x) (((x) >> S_DP18_PLL_LOCK) & M_DP18_PLL_LOCK)
+
+#define A_MC_DDRPHY_PC_AD32S_PLL_LOCK_STATUS 0x47004
+
+#define S_AD32S_PLL_LOCK    14
+#define M_AD32S_PLL_LOCK    0x3U
+#define V_AD32S_PLL_LOCK(x) ((x) << S_AD32S_PLL_LOCK)
+#define G_AD32S_PLL_LOCK(x) (((x) >> S_AD32S_PLL_LOCK) & M_AD32S_PLL_LOCK)
+
+#define A_MC_DDRPHY_PC_RANK_PAIR0 0x47008
+
+#define S_RANK_PAIR0_PRI    13
+#define M_RANK_PAIR0_PRI    0x7U
+#define V_RANK_PAIR0_PRI(x) ((x) << S_RANK_PAIR0_PRI)
+#define G_RANK_PAIR0_PRI(x) (((x) >> S_RANK_PAIR0_PRI) & M_RANK_PAIR0_PRI)
+
+#define S_RANK_PAIR0_PRI_V    12
+#define V_RANK_PAIR0_PRI_V(x) ((x) << S_RANK_PAIR0_PRI_V)
+#define F_RANK_PAIR0_PRI_V    V_RANK_PAIR0_PRI_V(1U)
+
+#define S_RANK_PAIR0_SEC    9
+#define M_RANK_PAIR0_SEC    0x7U
+#define V_RANK_PAIR0_SEC(x) ((x) << S_RANK_PAIR0_SEC)
+#define G_RANK_PAIR0_SEC(x) (((x) >> S_RANK_PAIR0_SEC) & M_RANK_PAIR0_SEC)
+
+#define S_RANK_PAIR0_SEC_V    8
+#define V_RANK_PAIR0_SEC_V(x) ((x) << S_RANK_PAIR0_SEC_V)
+#define F_RANK_PAIR0_SEC_V    V_RANK_PAIR0_SEC_V(1U)
+
+#define S_RANK_PAIR1_PRI    5
+#define M_RANK_PAIR1_PRI    0x7U
+#define V_RANK_PAIR1_PRI(x) ((x) << S_RANK_PAIR1_PRI)
+#define G_RANK_PAIR1_PRI(x) (((x) >> S_RANK_PAIR1_PRI) & M_RANK_PAIR1_PRI)
+
+#define S_RANK_PAIR1_PRI_V    4
+#define V_RANK_PAIR1_PRI_V(x) ((x) << S_RANK_PAIR1_PRI_V)
+#define F_RANK_PAIR1_PRI_V    V_RANK_PAIR1_PRI_V(1U)
+
+#define S_RANK_PAIR1_SEC    1
+#define M_RANK_PAIR1_SEC    0x7U
+#define V_RANK_PAIR1_SEC(x) ((x) << S_RANK_PAIR1_SEC)
+#define G_RANK_PAIR1_SEC(x) (((x) >> S_RANK_PAIR1_SEC) & M_RANK_PAIR1_SEC)
+
+#define S_RANK_PAIR1_SEC_V    0
+#define V_RANK_PAIR1_SEC_V(x) ((x) << S_RANK_PAIR1_SEC_V)
+#define F_RANK_PAIR1_SEC_V    V_RANK_PAIR1_SEC_V(1U)
+
+#define A_MC_DDRPHY_PC_RANK_PAIR1 0x4700c
+
+#define S_RANK_PAIR2_PRI    13
+#define M_RANK_PAIR2_PRI    0x7U
+#define V_RANK_PAIR2_PRI(x) ((x) << S_RANK_PAIR2_PRI)
+#define G_RANK_PAIR2_PRI(x) (((x) >> S_RANK_PAIR2_PRI) & M_RANK_PAIR2_PRI)
+
+#define S_RANK_PAIR2_PRI_V    12
+#define V_RANK_PAIR2_PRI_V(x) ((x) << S_RANK_PAIR2_PRI_V)
+#define F_RANK_PAIR2_PRI_V    V_RANK_PAIR2_PRI_V(1U)
+
+#define S_RANK_PAIR2_SEC    9
+#define M_RANK_PAIR2_SEC    0x7U
+#define V_RANK_PAIR2_SEC(x) ((x) << S_RANK_PAIR2_SEC)
+#define G_RANK_PAIR2_SEC(x) (((x) >> S_RANK_PAIR2_SEC) & M_RANK_PAIR2_SEC)
+
+#define S_RANK_PAIR2_SEC_V    8
+#define V_RANK_PAIR2_SEC_V(x) ((x) << S_RANK_PAIR2_SEC_V)
+#define F_RANK_PAIR2_SEC_V    V_RANK_PAIR2_SEC_V(1U)
+
+#define S_RANK_PAIR3_PRI    5
+#define M_RANK_PAIR3_PRI    0x7U
+#define V_RANK_PAIR3_PRI(x) ((x) << S_RANK_PAIR3_PRI)
+#define G_RANK_PAIR3_PRI(x) (((x) >> S_RANK_PAIR3_PRI) & M_RANK_PAIR3_PRI)
+
+#define S_RANK_PAIR3_PRI_V    4
+#define V_RANK_PAIR3_PRI_V(x) ((x) << S_RANK_PAIR3_PRI_V)
+#define F_RANK_PAIR3_PRI_V    V_RANK_PAIR3_PRI_V(1U)
+
+#define S_RANK_PAIR3_SEC    1
+#define M_RANK_PAIR3_SEC    0x7U
+#define V_RANK_PAIR3_SEC(x) ((x) << S_RANK_PAIR3_SEC)
+#define G_RANK_PAIR3_SEC(x) (((x) >> S_RANK_PAIR3_SEC) & M_RANK_PAIR3_SEC)
+
+#define S_RANK_PAIR3_SEC_V    0
+#define V_RANK_PAIR3_SEC_V(x) ((x) << S_RANK_PAIR3_SEC_V)
+#define F_RANK_PAIR3_SEC_V    V_RANK_PAIR3_SEC_V(1U)
+
+#define A_MC_DDRPHY_PC_BASE_CNTR0 0x47010
+
+#define S_PERIODIC_BASE_CNTR0    0
+#define M_PERIODIC_BASE_CNTR0    0xffffU
+#define V_PERIODIC_BASE_CNTR0(x) ((x) << S_PERIODIC_BASE_CNTR0)
+#define G_PERIODIC_BASE_CNTR0(x) (((x) >> S_PERIODIC_BASE_CNTR0) & M_PERIODIC_BASE_CNTR0)
+
+#define A_MC_DDRPHY_PC_RELOAD_VALUE0 0x47014
+
+#define S_PERIODIC_CAL_REQ_EN    15
+#define V_PERIODIC_CAL_REQ_EN(x) ((x) << S_PERIODIC_CAL_REQ_EN)
+#define F_PERIODIC_CAL_REQ_EN    V_PERIODIC_CAL_REQ_EN(1U)
+
+#define S_PERIODIC_RELOAD_VALUE0    0
+#define M_PERIODIC_RELOAD_VALUE0    0x7fffU
+#define V_PERIODIC_RELOAD_VALUE0(x) ((x) << S_PERIODIC_RELOAD_VALUE0)
+#define G_PERIODIC_RELOAD_VALUE0(x) (((x) >> S_PERIODIC_RELOAD_VALUE0) & M_PERIODIC_RELOAD_VALUE0)
+
+#define A_MC_DDRPHY_PC_BASE_CNTR1 0x47018
+
+#define S_PERIODIC_BASE_CNTR1    0
+#define M_PERIODIC_BASE_CNTR1    0xffffU
+#define V_PERIODIC_BASE_CNTR1(x) ((x) << S_PERIODIC_BASE_CNTR1)
+#define G_PERIODIC_BASE_CNTR1(x) (((x) >> S_PERIODIC_BASE_CNTR1) & M_PERIODIC_BASE_CNTR1)
+
+#define A_MC_DDRPHY_PC_CAL_TIMER 0x4701c
+
+#define S_PERIODIC_CAL_TIMER    0
+#define M_PERIODIC_CAL_TIMER    0xffffU
+#define V_PERIODIC_CAL_TIMER(x) ((x) << S_PERIODIC_CAL_TIMER)
+#define G_PERIODIC_CAL_TIMER(x) (((x) >> S_PERIODIC_CAL_TIMER) & M_PERIODIC_CAL_TIMER)
+
+#define A_MC_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE 0x47020
+
+#define S_PERIODIC_TIMER_RELOAD_VALUE    0
+#define M_PERIODIC_TIMER_RELOAD_VALUE    0xffffU
+#define V_PERIODIC_TIMER_RELOAD_VALUE(x) ((x) << S_PERIODIC_TIMER_RELOAD_VALUE)
+#define G_PERIODIC_TIMER_RELOAD_VALUE(x) (((x) >> S_PERIODIC_TIMER_RELOAD_VALUE) & M_PERIODIC_TIMER_RELOAD_VALUE)
+
+#define A_MC_DDRPHY_PC_ZCAL_TIMER 0x47024
+
+#define S_PERIODIC_ZCAL_TIMER    0
+#define M_PERIODIC_ZCAL_TIMER    0xffffU
+#define V_PERIODIC_ZCAL_TIMER(x) ((x) << S_PERIODIC_ZCAL_TIMER)
+#define G_PERIODIC_ZCAL_TIMER(x) (((x) >> S_PERIODIC_ZCAL_TIMER) & M_PERIODIC_ZCAL_TIMER)
+
+#define A_MC_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE 0x47028
+#define A_MC_DDRPHY_PC_PER_CAL_CONFIG 0x4702c
+
+#define S_PER_ENA_RANK_PAIR    12
+#define M_PER_ENA_RANK_PAIR    0xfU
+#define V_PER_ENA_RANK_PAIR(x) ((x) << S_PER_ENA_RANK_PAIR)
+#define G_PER_ENA_RANK_PAIR(x) (((x) >> S_PER_ENA_RANK_PAIR) & M_PER_ENA_RANK_PAIR)
+
+#define S_PER_ENA_ZCAL    11
+#define V_PER_ENA_ZCAL(x) ((x) << S_PER_ENA_ZCAL)
+#define F_PER_ENA_ZCAL    V_PER_ENA_ZCAL(1U)
+
+#define S_PER_ENA_SYSCLK_ALIGN    10
+#define V_PER_ENA_SYSCLK_ALIGN(x) ((x) << S_PER_ENA_SYSCLK_ALIGN)
+#define F_PER_ENA_SYSCLK_ALIGN    V_PER_ENA_SYSCLK_ALIGN(1U)
+
+#define S_ENA_PER_RDCLK_ALIGN    9
+#define V_ENA_PER_RDCLK_ALIGN(x) ((x) << S_ENA_PER_RDCLK_ALIGN)
+#define F_ENA_PER_RDCLK_ALIGN    V_ENA_PER_RDCLK_ALIGN(1U)
+
+#define S_ENA_PER_DQS_ALIGN    8
+#define V_ENA_PER_DQS_ALIGN(x) ((x) << S_ENA_PER_DQS_ALIGN)
+#define F_ENA_PER_DQS_ALIGN    V_ENA_PER_DQS_ALIGN(1U)
+
+#define S_ENA_PER_READ_CTR    7
+#define V_ENA_PER_READ_CTR(x) ((x) << S_ENA_PER_READ_CTR)
+#define F_ENA_PER_READ_CTR    V_ENA_PER_READ_CTR(1U)
+
+#define S_PER_NEXT_RANK_PAIR    5
+#define M_PER_NEXT_RANK_PAIR    0x3U
+#define V_PER_NEXT_RANK_PAIR(x) ((x) << S_PER_NEXT_RANK_PAIR)
+#define G_PER_NEXT_RANK_PAIR(x) (((x) >> S_PER_NEXT_RANK_PAIR) & M_PER_NEXT_RANK_PAIR)
+
+#define S_FAST_SIM_PER_CNTR    4
+#define V_FAST_SIM_PER_CNTR(x) ((x) << S_FAST_SIM_PER_CNTR)
+#define F_FAST_SIM_PER_CNTR    V_FAST_SIM_PER_CNTR(1U)
+
+#define S_START_INIT_CAL    3
+#define V_START_INIT_CAL(x) ((x) << S_START_INIT_CAL)
+#define F_START_INIT_CAL    V_START_INIT_CAL(1U)
+
+#define S_START_PER_CAL    2
+#define V_START_PER_CAL(x) ((x) << S_START_PER_CAL)
+#define F_START_PER_CAL    V_START_PER_CAL(1U)
+
+#define A_MC_DDRPHY_PC_CONFIG0 0x47030
+
+#define S_PROTOCOL_DDR    12
+#define M_PROTOCOL_DDR    0xfU
+#define V_PROTOCOL_DDR(x) ((x) << S_PROTOCOL_DDR)
+#define G_PROTOCOL_DDR(x) (((x) >> S_PROTOCOL_DDR) & M_PROTOCOL_DDR)
+
+#define S_DATA_MUX4_1MODE    11
+#define V_DATA_MUX4_1MODE(x) ((x) << S_DATA_MUX4_1MODE)
+#define F_DATA_MUX4_1MODE    V_DATA_MUX4_1MODE(1U)
+
+#define S_DDR4_CMD_SIG_REDUCTION    9
+#define V_DDR4_CMD_SIG_REDUCTION(x) ((x) << S_DDR4_CMD_SIG_REDUCTION)
+#define F_DDR4_CMD_SIG_REDUCTION    V_DDR4_CMD_SIG_REDUCTION(1U)
+
+#define S_SYSCLK_2X_MEMINTCLKO    8
+#define V_SYSCLK_2X_MEMINTCLKO(x) ((x) << S_SYSCLK_2X_MEMINTCLKO)
+#define F_SYSCLK_2X_MEMINTCLKO    V_SYSCLK_2X_MEMINTCLKO(1U)
+
+#define S_RANK_OVERRIDE    7
+#define V_RANK_OVERRIDE(x) ((x) << S_RANK_OVERRIDE)
+#define F_RANK_OVERRIDE    V_RANK_OVERRIDE(1U)
+
+#define S_RANK_OVERRIDE_VALUE    4
+#define M_RANK_OVERRIDE_VALUE    0x7U
+#define V_RANK_OVERRIDE_VALUE(x) ((x) << S_RANK_OVERRIDE_VALUE)
+#define G_RANK_OVERRIDE_VALUE(x) (((x) >> S_RANK_OVERRIDE_VALUE) & M_RANK_OVERRIDE_VALUE)
+
+#define S_LOW_LATENCY    3
+#define V_LOW_LATENCY(x) ((x) << S_LOW_LATENCY)
+#define F_LOW_LATENCY    V_LOW_LATENCY(1U)
+
+#define S_DDR4_BANK_REFRESH    2
+#define V_DDR4_BANK_REFRESH(x) ((x) << S_DDR4_BANK_REFRESH)
+#define F_DDR4_BANK_REFRESH    V_DDR4_BANK_REFRESH(1U)
+
+#define S_DDR4_VLEVEL_BANK_GROUP    1
+#define V_DDR4_VLEVEL_BANK_GROUP(x) ((x) << S_DDR4_VLEVEL_BANK_GROUP)
+#define F_DDR4_VLEVEL_BANK_GROUP    V_DDR4_VLEVEL_BANK_GROUP(1U)
+
+#define A_MC_DDRPHY_PC_CONFIG1 0x47034
+
+#define S_WRITE_LATENCY_OFFSET    12
+#define M_WRITE_LATENCY_OFFSET    0xfU
+#define V_WRITE_LATENCY_OFFSET(x) ((x) << S_WRITE_LATENCY_OFFSET)
+#define G_WRITE_LATENCY_OFFSET(x) (((x) >> S_WRITE_LATENCY_OFFSET) & M_WRITE_LATENCY_OFFSET)
+
+#define S_READ_LATENCY_OFFSET    8
+#define M_READ_LATENCY_OFFSET    0xfU
+#define V_READ_LATENCY_OFFSET(x) ((x) << S_READ_LATENCY_OFFSET)
+#define G_READ_LATENCY_OFFSET(x) (((x) >> S_READ_LATENCY_OFFSET) & M_READ_LATENCY_OFFSET)
+
+#define S_MEMCTL_CIC_FAST    7
+#define V_MEMCTL_CIC_FAST(x) ((x) << S_MEMCTL_CIC_FAST)
+#define F_MEMCTL_CIC_FAST    V_MEMCTL_CIC_FAST(1U)
+
+#define S_MEMCTL_CTRN_IGNORE    6
+#define V_MEMCTL_CTRN_IGNORE(x) ((x) << S_MEMCTL_CTRN_IGNORE)
+#define F_MEMCTL_CTRN_IGNORE    V_MEMCTL_CTRN_IGNORE(1U)
+
+#define S_DISABLE_MEMCTL_CAL    5
+#define V_DISABLE_MEMCTL_CAL(x) ((x) << S_DISABLE_MEMCTL_CAL)
+#define F_DISABLE_MEMCTL_CAL    V_DISABLE_MEMCTL_CAL(1U)
+
+#define A_MC_DDRPHY_PC_RESETS 0x47038
+
+#define S_PLL_RESET    15
+#define V_PLL_RESET(x) ((x) << S_PLL_RESET)
+#define F_PLL_RESET    V_PLL_RESET(1U)
+
+#define S_SYSCLK_RESET    14
+#define V_SYSCLK_RESET(x) ((x) << S_SYSCLK_RESET)
+#define F_SYSCLK_RESET    V_SYSCLK_RESET(1U)
+
+#define A_MC_DDRPHY_PC_PER_ZCAL_CONFIG 0x4703c
+
+#define S_PER_ZCAL_ENA_RANK    8
+#define M_PER_ZCAL_ENA_RANK    0xffU
+#define V_PER_ZCAL_ENA_RANK(x) ((x) << S_PER_ZCAL_ENA_RANK)
+#define G_PER_ZCAL_ENA_RANK(x) (((x) >> S_PER_ZCAL_ENA_RANK) & M_PER_ZCAL_ENA_RANK)
+
+#define S_PER_ZCAL_NEXT_RANK    5
+#define M_PER_ZCAL_NEXT_RANK    0x7U
+#define V_PER_ZCAL_NEXT_RANK(x) ((x) << S_PER_ZCAL_NEXT_RANK)
+#define G_PER_ZCAL_NEXT_RANK(x) (((x) >> S_PER_ZCAL_NEXT_RANK) & M_PER_ZCAL_NEXT_RANK)
+
+#define S_START_PER_ZCAL    4
+#define V_START_PER_ZCAL(x) ((x) << S_START_PER_ZCAL)
+#define F_START_PER_ZCAL    V_START_PER_ZCAL(1U)
+
+#define A_MC_DDRPHY_PC_RANK_GROUP 0x47044
+
+#define S_ADDR_MIRROR_RP0_PRI    15
+#define V_ADDR_MIRROR_RP0_PRI(x) ((x) << S_ADDR_MIRROR_RP0_PRI)
+#define F_ADDR_MIRROR_RP0_PRI    V_ADDR_MIRROR_RP0_PRI(1U)
+
+#define S_ADDR_MIRROR_RP0_SEC    14
+#define V_ADDR_MIRROR_RP0_SEC(x) ((x) << S_ADDR_MIRROR_RP0_SEC)
+#define F_ADDR_MIRROR_RP0_SEC    V_ADDR_MIRROR_RP0_SEC(1U)
+
+#define S_ADDR_MIRROR_RP1_PRI    13
+#define V_ADDR_MIRROR_RP1_PRI(x) ((x) << S_ADDR_MIRROR_RP1_PRI)
+#define F_ADDR_MIRROR_RP1_PRI    V_ADDR_MIRROR_RP1_PRI(1U)
+
+#define S_ADDR_MIRROR_RP1_SEC    12
+#define V_ADDR_MIRROR_RP1_SEC(x) ((x) << S_ADDR_MIRROR_RP1_SEC)
+#define F_ADDR_MIRROR_RP1_SEC    V_ADDR_MIRROR_RP1_SEC(1U)
+
+#define S_ADDR_MIRROR_RP2_PRI    11
+#define V_ADDR_MIRROR_RP2_PRI(x) ((x) << S_ADDR_MIRROR_RP2_PRI)
+#define F_ADDR_MIRROR_RP2_PRI    V_ADDR_MIRROR_RP2_PRI(1U)
+
+#define S_ADDR_MIRROR_RP2_SEC    10
+#define V_ADDR_MIRROR_RP2_SEC(x) ((x) << S_ADDR_MIRROR_RP2_SEC)
+#define F_ADDR_MIRROR_RP2_SEC    V_ADDR_MIRROR_RP2_SEC(1U)
+
+#define S_ADDR_MIRROR_RP3_PRI    9
+#define V_ADDR_MIRROR_RP3_PRI(x) ((x) << S_ADDR_MIRROR_RP3_PRI)
+#define F_ADDR_MIRROR_RP3_PRI    V_ADDR_MIRROR_RP3_PRI(1U)
+
+#define S_ADDR_MIRROR_RP3_SEC    8
+#define V_ADDR_MIRROR_RP3_SEC(x) ((x) << S_ADDR_MIRROR_RP3_SEC)
+#define F_ADDR_MIRROR_RP3_SEC    V_ADDR_MIRROR_RP3_SEC(1U)
+
+#define S_RANK_GROUPING    6
+#define M_RANK_GROUPING    0x3U
+#define V_RANK_GROUPING(x) ((x) << S_RANK_GROUPING)
+#define G_RANK_GROUPING(x) (((x) >> S_RANK_GROUPING) & M_RANK_GROUPING)
+
+#define A_MC_DDRPHY_PC_ERROR_STATUS0 0x47048
+
+#define S_RC_ERROR    15
+#define V_RC_ERROR(x) ((x) << S_RC_ERROR)
+#define F_RC_ERROR    V_RC_ERROR(1U)
+
+#define S_WC_ERROR    14
+#define V_WC_ERROR(x) ((x) << S_WC_ERROR)
+#define F_WC_ERROR    V_WC_ERROR(1U)
+
+#define S_SEQ_ERROR    13
+#define V_SEQ_ERROR(x) ((x) << S_SEQ_ERROR)
+#define F_SEQ_ERROR    V_SEQ_ERROR(1U)
+
+#define S_CC_ERROR    12
+#define V_CC_ERROR(x) ((x) << S_CC_ERROR)
+#define F_CC_ERROR    V_CC_ERROR(1U)
+
+#define S_APB_ERROR    11
+#define V_APB_ERROR(x) ((x) << S_APB_ERROR)
+#define F_APB_ERROR    V_APB_ERROR(1U)
+
+#define S_PC_ERROR    10
+#define V_PC_ERROR(x) ((x) << S_PC_ERROR)
+#define F_PC_ERROR    V_PC_ERROR(1U)
+
+#define A_MC_DDRPHY_PC_ERROR_MASK0 0x4704c
+
+#define S_RC_ERROR_MASK    15
+#define V_RC_ERROR_MASK(x) ((x) << S_RC_ERROR_MASK)
+#define F_RC_ERROR_MASK    V_RC_ERROR_MASK(1U)
+
+#define S_WC_ERROR_MASK    14
+#define V_WC_ERROR_MASK(x) ((x) << S_WC_ERROR_MASK)
+#define F_WC_ERROR_MASK    V_WC_ERROR_MASK(1U)
+
+#define S_SEQ_ERROR_MASK    13
+#define V_SEQ_ERROR_MASK(x) ((x) << S_SEQ_ERROR_MASK)
+#define F_SEQ_ERROR_MASK    V_SEQ_ERROR_MASK(1U)
+
+#define S_CC_ERROR_MASK    12
+#define V_CC_ERROR_MASK(x) ((x) << S_CC_ERROR_MASK)
+#define F_CC_ERROR_MASK    V_CC_ERROR_MASK(1U)
+
+#define S_APB_ERROR_MASK    11
+#define V_APB_ERROR_MASK(x) ((x) << S_APB_ERROR_MASK)
+#define F_APB_ERROR_MASK    V_APB_ERROR_MASK(1U)
+
+#define S_PC_ERROR_MASK    10
+#define V_PC_ERROR_MASK(x) ((x) << S_PC_ERROR_MASK)
+#define F_PC_ERROR_MASK    V_PC_ERROR_MASK(1U)
+
+#define A_MC_DDRPHY_PC_IO_PVT_FET_CONTROL 0x47050
+
+#define S_PVTP    11
+#define M_PVTP    0x1fU
+#define V_PVTP(x) ((x) << S_PVTP)
+#define G_PVTP(x) (((x) >> S_PVTP) & M_PVTP)
+
+#define S_PVTN    6
+#define M_PVTN    0x1fU
+#define V_PVTN(x) ((x) << S_PVTN)
+#define G_PVTN(x) (((x) >> S_PVTN) & M_PVTN)
+
+#define S_PVT_OVERRIDE    5
+#define V_PVT_OVERRIDE(x) ((x) << S_PVT_OVERRIDE)
+#define F_PVT_OVERRIDE    V_PVT_OVERRIDE(1U)
+
+#define S_ENABLE_ZCAL    4
+#define V_ENABLE_ZCAL(x) ((x) << S_ENABLE_ZCAL)
+#define F_ENABLE_ZCAL    V_ENABLE_ZCAL(1U)
+
+#define A_MC_DDRPHY_PC_VREF_DRV_CONTROL 0x47054
+
+#define S_VREFDQ0DSGN    15
+#define V_VREFDQ0DSGN(x) ((x) << S_VREFDQ0DSGN)
+#define F_VREFDQ0DSGN    V_VREFDQ0DSGN(1U)
+
+#define S_VREFDQ0D    11
+#define M_VREFDQ0D    0xfU
+#define V_VREFDQ0D(x) ((x) << S_VREFDQ0D)
+#define G_VREFDQ0D(x) (((x) >> S_VREFDQ0D) & M_VREFDQ0D)
+
+#define S_VREFDQ1DSGN    10
+#define V_VREFDQ1DSGN(x) ((x) << S_VREFDQ1DSGN)
+#define F_VREFDQ1DSGN    V_VREFDQ1DSGN(1U)
+
+#define S_VREFDQ1D    6
+#define M_VREFDQ1D    0xfU
+#define V_VREFDQ1D(x) ((x) << S_VREFDQ1D)
+#define G_VREFDQ1D(x) (((x) >> S_VREFDQ1D) & M_VREFDQ1D)
+
+#define A_MC_DDRPHY_PC_INIT_CAL_CONFIG0 0x47058
+
+#define S_ENA_WR_LEVEL    15
+#define V_ENA_WR_LEVEL(x) ((x) << S_ENA_WR_LEVEL)
+#define F_ENA_WR_LEVEL    V_ENA_WR_LEVEL(1U)
+
+#define S_ENA_INITIAL_PAT_WR    14
+#define V_ENA_INITIAL_PAT_WR(x) ((x) << S_ENA_INITIAL_PAT_WR)
+#define F_ENA_INITIAL_PAT_WR    V_ENA_INITIAL_PAT_WR(1U)
+
+#define S_ENA_DQS_ALIGN    13
+#define V_ENA_DQS_ALIGN(x) ((x) << S_ENA_DQS_ALIGN)
+#define F_ENA_DQS_ALIGN    V_ENA_DQS_ALIGN(1U)
+
+#define S_ENA_RDCLK_ALIGN    12
+#define V_ENA_RDCLK_ALIGN(x) ((x) << S_ENA_RDCLK_ALIGN)
+#define F_ENA_RDCLK_ALIGN    V_ENA_RDCLK_ALIGN(1U)
+
+#define S_ENA_READ_CTR    11
+#define V_ENA_READ_CTR(x) ((x) << S_ENA_READ_CTR)
+#define F_ENA_READ_CTR    V_ENA_READ_CTR(1U)
+
+#define S_ENA_WRITE_CTR    10
+#define V_ENA_WRITE_CTR(x) ((x) << S_ENA_WRITE_CTR)
+#define F_ENA_WRITE_CTR    V_ENA_WRITE_CTR(1U)
+
+#define S_ENA_INITIAL_COARSE_WR    9
+#define V_ENA_INITIAL_COARSE_WR(x) ((x) << S_ENA_INITIAL_COARSE_WR)
+#define F_ENA_INITIAL_COARSE_WR    V_ENA_INITIAL_COARSE_WR(1U)
+
+#define S_ENA_COARSE_RD    8
+#define V_ENA_COARSE_RD(x) ((x) << S_ENA_COARSE_RD)
+#define F_ENA_COARSE_RD    V_ENA_COARSE_RD(1U)
+
+#define S_ENA_CUSTOM_RD    7
+#define V_ENA_CUSTOM_RD(x) ((x) << S_ENA_CUSTOM_RD)
+#define F_ENA_CUSTOM_RD    V_ENA_CUSTOM_RD(1U)
+
+#define S_ENA_CUSTOM_WR    6
+#define V_ENA_CUSTOM_WR(x) ((x) << S_ENA_CUSTOM_WR)
+#define F_ENA_CUSTOM_WR    V_ENA_CUSTOM_WR(1U)
+
+#define S_ABORT_ON_CAL_ERROR    5
+#define V_ABORT_ON_CAL_ERROR(x) ((x) << S_ABORT_ON_CAL_ERROR)
+#define F_ABORT_ON_CAL_ERROR    V_ABORT_ON_CAL_ERROR(1U)
+
+#define S_ENA_DIGITAL_EYE    4
+#define V_ENA_DIGITAL_EYE(x) ((x) << S_ENA_DIGITAL_EYE)
+#define F_ENA_DIGITAL_EYE    V_ENA_DIGITAL_EYE(1U)
+
+#define S_ENA_RANK_PAIR    0
+#define M_ENA_RANK_PAIR    0xfU
+#define V_ENA_RANK_PAIR(x) ((x) << S_ENA_RANK_PAIR)
+#define G_ENA_RANK_PAIR(x) (((x) >> S_ENA_RANK_PAIR) & M_ENA_RANK_PAIR)
+
+#define A_MC_DDRPHY_PC_INIT_CAL_CONFIG1 0x4705c
+
+#define S_REFRESH_COUNT    12
+#define M_REFRESH_COUNT    0xfU
+#define V_REFRESH_COUNT(x) ((x) << S_REFRESH_COUNT)
+#define G_REFRESH_COUNT(x) (((x) >> S_REFRESH_COUNT) & M_REFRESH_COUNT)
+
+#define S_REFRESH_CONTROL    10
+#define M_REFRESH_CONTROL    0x3U
+#define V_REFRESH_CONTROL(x) ((x) << S_REFRESH_CONTROL)
+#define G_REFRESH_CONTROL(x) (((x) >> S_REFRESH_CONTROL) & M_REFRESH_CONTROL)
+
+#define S_REFRESH_ALL_RANKS    9
+#define V_REFRESH_ALL_RANKS(x) ((x) << S_REFRESH_ALL_RANKS)
+#define F_REFRESH_ALL_RANKS    V_REFRESH_ALL_RANKS(1U)
+
+#define S_REFRESH_INTERVAL    0
+#define M_REFRESH_INTERVAL    0x7fU
+#define V_REFRESH_INTERVAL(x) ((x) << S_REFRESH_INTERVAL)
+#define G_REFRESH_INTERVAL(x) (((x) >> S_REFRESH_INTERVAL) & M_REFRESH_INTERVAL)
+
+#define A_MC_DDRPHY_PC_INIT_CAL_ERROR 0x47060
+
+#define S_ERROR_WR_LEVEL    15
+#define V_ERROR_WR_LEVEL(x) ((x) << S_ERROR_WR_LEVEL)
+#define F_ERROR_WR_LEVEL    V_ERROR_WR_LEVEL(1U)
+
+#define S_ERROR_INITIAL_PAT_WRITE    14
+#define V_ERROR_INITIAL_PAT_WRITE(x) ((x) << S_ERROR_INITIAL_PAT_WRITE)
+#define F_ERROR_INITIAL_PAT_WRITE    V_ERROR_INITIAL_PAT_WRITE(1U)
+
+#define S_ERROR_DQS_ALIGN    13
+#define V_ERROR_DQS_ALIGN(x) ((x) << S_ERROR_DQS_ALIGN)
+#define F_ERROR_DQS_ALIGN    V_ERROR_DQS_ALIGN(1U)
+
+#define S_ERROR_RDCLK_ALIGN    12
+#define V_ERROR_RDCLK_ALIGN(x) ((x) << S_ERROR_RDCLK_ALIGN)
+#define F_ERROR_RDCLK_ALIGN    V_ERROR_RDCLK_ALIGN(1U)
+
+#define S_ERROR_READ_CTR    11
+#define V_ERROR_READ_CTR(x) ((x) << S_ERROR_READ_CTR)
+#define F_ERROR_READ_CTR    V_ERROR_READ_CTR(1U)
+
+#define S_ERROR_WRITE_CTR    10
+#define V_ERROR_WRITE_CTR(x) ((x) << S_ERROR_WRITE_CTR)
+#define F_ERROR_WRITE_CTR    V_ERROR_WRITE_CTR(1U)
+
+#define S_ERROR_INITIAL_COARSE_WR    9
+#define V_ERROR_INITIAL_COARSE_WR(x) ((x) << S_ERROR_INITIAL_COARSE_WR)
+#define F_ERROR_INITIAL_COARSE_WR    V_ERROR_INITIAL_COARSE_WR(1U)
+
+#define S_ERROR_COARSE_RD    8
+#define V_ERROR_COARSE_RD(x) ((x) << S_ERROR_COARSE_RD)
+#define F_ERROR_COARSE_RD    V_ERROR_COARSE_RD(1U)
+
+#define S_ERROR_CUSTOM_RD    7
+#define V_ERROR_CUSTOM_RD(x) ((x) << S_ERROR_CUSTOM_RD)
+#define F_ERROR_CUSTOM_RD    V_ERROR_CUSTOM_RD(1U)
+
+#define S_ERROR_CUSTOM_WR    6
+#define V_ERROR_CUSTOM_WR(x) ((x) << S_ERROR_CUSTOM_WR)
+#define F_ERROR_CUSTOM_WR    V_ERROR_CUSTOM_WR(1U)
+
+#define S_ERROR_DIGITAL_EYE    5
+#define V_ERROR_DIGITAL_EYE(x) ((x) << S_ERROR_DIGITAL_EYE)
+#define F_ERROR_DIGITAL_EYE    V_ERROR_DIGITAL_EYE(1U)
+
+#define S_ERROR_RANK_PAIR    0
+#define M_ERROR_RANK_PAIR    0xfU
+#define V_ERROR_RANK_PAIR(x) ((x) << S_ERROR_RANK_PAIR)
+#define G_ERROR_RANK_PAIR(x) (((x) >> S_ERROR_RANK_PAIR) & M_ERROR_RANK_PAIR)
+
+#define A_MC_DDRPHY_PC_INIT_CAL_STATUS 0x47064
+
+#define S_INIT_CAL_COMPLETE    12
+#define M_INIT_CAL_COMPLETE    0xfU
+#define V_INIT_CAL_COMPLETE(x) ((x) << S_INIT_CAL_COMPLETE)
+#define G_INIT_CAL_COMPLETE(x) (((x) >> S_INIT_CAL_COMPLETE) & M_INIT_CAL_COMPLETE)
+
+#define A_MC_DDRPHY_PC_INIT_CAL_MASK 0x47068
+
+#define S_ERROR_WR_LEVEL_MASK    15
+#define V_ERROR_WR_LEVEL_MASK(x) ((x) << S_ERROR_WR_LEVEL_MASK)
+#define F_ERROR_WR_LEVEL_MASK    V_ERROR_WR_LEVEL_MASK(1U)
+
+#define S_ERROR_INITIAL_PAT_WRITE_MASK    14
+#define V_ERROR_INITIAL_PAT_WRITE_MASK(x) ((x) << S_ERROR_INITIAL_PAT_WRITE_MASK)
+#define F_ERROR_INITIAL_PAT_WRITE_MASK    V_ERROR_INITIAL_PAT_WRITE_MASK(1U)
+
+#define S_ERROR_DQS_ALIGN_MASK    13
+#define V_ERROR_DQS_ALIGN_MASK(x) ((x) << S_ERROR_DQS_ALIGN_MASK)
+#define F_ERROR_DQS_ALIGN_MASK    V_ERROR_DQS_ALIGN_MASK(1U)
+
+#define S_ERROR_RDCLK_ALIGN_MASK    12
+#define V_ERROR_RDCLK_ALIGN_MASK(x) ((x) << S_ERROR_RDCLK_ALIGN_MASK)
+#define F_ERROR_RDCLK_ALIGN_MASK    V_ERROR_RDCLK_ALIGN_MASK(1U)
+
+#define S_ERROR_READ_CTR_MASK    11
+#define V_ERROR_READ_CTR_MASK(x) ((x) << S_ERROR_READ_CTR_MASK)
+#define F_ERROR_READ_CTR_MASK    V_ERROR_READ_CTR_MASK(1U)
+
+#define S_ERROR_WRITE_CTR_MASK    10
+#define V_ERROR_WRITE_CTR_MASK(x) ((x) << S_ERROR_WRITE_CTR_MASK)
+#define F_ERROR_WRITE_CTR_MASK    V_ERROR_WRITE_CTR_MASK(1U)
+
+#define S_ERROR_INITIAL_COARSE_WR_MASK    9
+#define V_ERROR_INITIAL_COARSE_WR_MASK(x) ((x) << S_ERROR_INITIAL_COARSE_WR_MASK)
+#define F_ERROR_INITIAL_COARSE_WR_MASK    V_ERROR_INITIAL_COARSE_WR_MASK(1U)
+
+#define S_ERROR_COARSE_RD_MASK    8
+#define V_ERROR_COARSE_RD_MASK(x) ((x) << S_ERROR_COARSE_RD_MASK)
+#define F_ERROR_COARSE_RD_MASK    V_ERROR_COARSE_RD_MASK(1U)
+
+#define S_ERROR_CUSTOM_RD_MASK    7
+#define V_ERROR_CUSTOM_RD_MASK(x) ((x) << S_ERROR_CUSTOM_RD_MASK)
+#define F_ERROR_CUSTOM_RD_MASK    V_ERROR_CUSTOM_RD_MASK(1U)
+
+#define S_ERROR_CUSTOM_WR_MASK    6
+#define V_ERROR_CUSTOM_WR_MASK(x) ((x) << S_ERROR_CUSTOM_WR_MASK)
+#define F_ERROR_CUSTOM_WR_MASK    V_ERROR_CUSTOM_WR_MASK(1U)
+
+#define S_ERROR_DIGITAL_EYE_MASK    5
+#define V_ERROR_DIGITAL_EYE_MASK(x) ((x) << S_ERROR_DIGITAL_EYE_MASK)
+#define F_ERROR_DIGITAL_EYE_MASK    V_ERROR_DIGITAL_EYE_MASK(1U)
+
+#define A_MC_DDRPHY_PC_IO_PVT_FET_STATUS 0x4706c
+#define A_MC_DDRPHY_PC_MR0_PRI_RP 0x47070
+
+#define S_MODEREGISTER0VALUE    0
+#define M_MODEREGISTER0VALUE    0xffffU
+#define V_MODEREGISTER0VALUE(x) ((x) << S_MODEREGISTER0VALUE)
+#define G_MODEREGISTER0VALUE(x) (((x) >> S_MODEREGISTER0VALUE) & M_MODEREGISTER0VALUE)
+
+#define A_MC_DDRPHY_PC_MR1_PRI_RP 0x47074
+
+#define S_MODEREGISTER1VALUE    0
+#define M_MODEREGISTER1VALUE    0xffffU
+#define V_MODEREGISTER1VALUE(x) ((x) << S_MODEREGISTER1VALUE)
+#define G_MODEREGISTER1VALUE(x) (((x) >> S_MODEREGISTER1VALUE) & M_MODEREGISTER1VALUE)
+
+#define A_MC_DDRPHY_PC_MR2_PRI_RP 0x47078
+
+#define S_MODEREGISTER2VALUE    0
+#define M_MODEREGISTER2VALUE    0xffffU
+#define V_MODEREGISTER2VALUE(x) ((x) << S_MODEREGISTER2VALUE)
+#define G_MODEREGISTER2VALUE(x) (((x) >> S_MODEREGISTER2VALUE) & M_MODEREGISTER2VALUE)
+
+#define A_MC_DDRPHY_PC_MR3_PRI_RP 0x4707c
+
+#define S_MODEREGISTER3VALUE    0
+#define M_MODEREGISTER3VALUE    0xffffU
+#define V_MODEREGISTER3VALUE(x) ((x) << S_MODEREGISTER3VALUE)
+#define G_MODEREGISTER3VALUE(x) (((x) >> S_MODEREGISTER3VALUE) & M_MODEREGISTER3VALUE)
+
+#define A_MC_DDRPHY_PC_MR0_SEC_RP 0x47080
+#define A_MC_DDRPHY_PC_MR1_SEC_RP 0x47084
+#define A_MC_DDRPHY_PC_MR2_SEC_RP 0x47088
+#define A_MC_DDRPHY_PC_MR3_SEC_RP 0x4708c
+
+#define S_MODE_REGISTER_3_VALUE    0
+#define M_MODE_REGISTER_3_VALUE    0xffffU
+#define V_MODE_REGISTER_3_VALUE(x) ((x) << S_MODE_REGISTER_3_VALUE)
+#define G_MODE_REGISTER_3_VALUE(x) (((x) >> S_MODE_REGISTER_3_VALUE) & M_MODE_REGISTER_3_VALUE)
+
+#define A_MC_DDRPHY_SEQ_RD_WR_DATA0 0x47200
+
+#define S_DRD_WR_DATA_REG    0
+#define M_DRD_WR_DATA_REG    0xffffU
+#define V_DRD_WR_DATA_REG(x) ((x) << S_DRD_WR_DATA_REG)
+#define G_DRD_WR_DATA_REG(x) (((x) >> S_DRD_WR_DATA_REG) & M_DRD_WR_DATA_REG)
+
+#define A_MC_DDRPHY_SEQ_RD_WR_DATA1 0x47204
+#define A_MC_DDRPHY_SEQ_CONFIG0 0x47208
+
+#define S_MPR_PATTERN_BIT    15
+#define V_MPR_PATTERN_BIT(x) ((x) << S_MPR_PATTERN_BIT)
+#define F_MPR_PATTERN_BIT    V_MPR_PATTERN_BIT(1U)
+
+#define S_TWO_CYCLE_ADDR_EN    14
+#define V_TWO_CYCLE_ADDR_EN(x) ((x) << S_TWO_CYCLE_ADDR_EN)
+#define F_TWO_CYCLE_ADDR_EN    V_TWO_CYCLE_ADDR_EN(1U)
+
+#define S_MR_MASK_EN    10
+#define M_MR_MASK_EN    0xfU
+#define V_MR_MASK_EN(x) ((x) << S_MR_MASK_EN)
+#define G_MR_MASK_EN(x) (((x) >> S_MR_MASK_EN) & M_MR_MASK_EN)
+
+#define A_MC_DDRPHY_SEQ_RESERVED_ADDR0 0x4720c
+#define A_MC_DDRPHY_SEQ_RESERVED_ADDR1 0x47210
+#define A_MC_DDRPHY_SEQ_RESERVED_ADDR2 0x47214
+#define A_MC_DDRPHY_SEQ_RESERVED_ADDR3 0x47218
+#define A_MC_DDRPHY_SEQ_RESERVED_ADDR4 0x4721c
+#define A_MC_DDRPHY_SEQ_ERROR_STATUS0 0x47220
+
+#define S_MULTIPLE_REQ_ERROR    15
+#define V_MULTIPLE_REQ_ERROR(x) ((x) << S_MULTIPLE_REQ_ERROR)
+#define F_MULTIPLE_REQ_ERROR    V_MULTIPLE_REQ_ERROR(1U)
+
+#define S_INVALID_REQTYPE_ERRO    14
+#define V_INVALID_REQTYPE_ERRO(x) ((x) << S_INVALID_REQTYPE_ERRO)
+#define F_INVALID_REQTYPE_ERRO    V_INVALID_REQTYPE_ERRO(1U)
+
+#define S_EARLY_REQ_ERROR    13
+#define V_EARLY_REQ_ERROR(x) ((x) << S_EARLY_REQ_ERROR)
+#define F_EARLY_REQ_ERROR    V_EARLY_REQ_ERROR(1U)
+
+#define S_MULTIPLE_REQ_SOURCE    10
+#define M_MULTIPLE_REQ_SOURCE    0x7U
+#define V_MULTIPLE_REQ_SOURCE(x) ((x) << S_MULTIPLE_REQ_SOURCE)
+#define G_MULTIPLE_REQ_SOURCE(x) (((x) >> S_MULTIPLE_REQ_SOURCE) & M_MULTIPLE_REQ_SOURCE)
+
+#define S_INVALID_REQTYPE    6
+#define M_INVALID_REQTYPE    0xfU
+#define V_INVALID_REQTYPE(x) ((x) << S_INVALID_REQTYPE)
+#define G_INVALID_REQTYPE(x) (((x) >> S_INVALID_REQTYPE) & M_INVALID_REQTYPE)
+
+#define S_INVALID_REQ_SOURCE    3
+#define M_INVALID_REQ_SOURCE    0x7U
+#define V_INVALID_REQ_SOURCE(x) ((x) << S_INVALID_REQ_SOURCE)
+#define G_INVALID_REQ_SOURCE(x) (((x) >> S_INVALID_REQ_SOURCE) & M_INVALID_REQ_SOURCE)
+
+#define S_EARLY_REQ_SOURCE    0
+#define M_EARLY_REQ_SOURCE    0x7U
+#define V_EARLY_REQ_SOURCE(x) ((x) << S_EARLY_REQ_SOURCE)
+#define G_EARLY_REQ_SOURCE(x) (((x) >> S_EARLY_REQ_SOURCE) & M_EARLY_REQ_SOURCE)
+
+#define A_MC_DDRPHY_SEQ_ERROR_MASK0 0x47224
+
+#define S_MULT_REQ_ERR_MASK    15
+#define V_MULT_REQ_ERR_MASK(x) ((x) << S_MULT_REQ_ERR_MASK)
+#define F_MULT_REQ_ERR_MASK    V_MULT_REQ_ERR_MASK(1U)
+
+#define S_INVALID_REQTYPE_ERR_MASK    14
+#define V_INVALID_REQTYPE_ERR_MASK(x) ((x) << S_INVALID_REQTYPE_ERR_MASK)
+#define F_INVALID_REQTYPE_ERR_MASK    V_INVALID_REQTYPE_ERR_MASK(1U)
+
+#define S_EARLY_REQ_ERR_MASK    13
+#define V_EARLY_REQ_ERR_MASK(x) ((x) << S_EARLY_REQ_ERR_MASK)
+#define F_EARLY_REQ_ERR_MASK    V_EARLY_REQ_ERR_MASK(1U)
+
+#define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG0 0x47228
+
+#define S_ODT_WR_VALUES_BITS0_7    8
+#define M_ODT_WR_VALUES_BITS0_7    0xffU
+#define V_ODT_WR_VALUES_BITS0_7(x) ((x) << S_ODT_WR_VALUES_BITS0_7)
+#define G_ODT_WR_VALUES_BITS0_7(x) (((x) >> S_ODT_WR_VALUES_BITS0_7) & M_ODT_WR_VALUES_BITS0_7)
+
+#define S_ODT_WR_VALUES_BITS8_15    0
+#define M_ODT_WR_VALUES_BITS8_15    0xffU
+#define V_ODT_WR_VALUES_BITS8_15(x) ((x) << S_ODT_WR_VALUES_BITS8_15)
+#define G_ODT_WR_VALUES_BITS8_15(x) (((x) >> S_ODT_WR_VALUES_BITS8_15) & M_ODT_WR_VALUES_BITS8_15)
+
+#define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG1 0x4722c
+#define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG2 0x47230
+#define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG3 0x47234
+#define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG0 0x47238
+
+#define S_ODT_RD_VALUES_X2    8
+#define M_ODT_RD_VALUES_X2    0xffU
+#define V_ODT_RD_VALUES_X2(x) ((x) << S_ODT_RD_VALUES_X2)
+#define G_ODT_RD_VALUES_X2(x) (((x) >> S_ODT_RD_VALUES_X2) & M_ODT_RD_VALUES_X2)
+
+#define S_ODT_RD_VALUES_X2PLUS1    0
+#define M_ODT_RD_VALUES_X2PLUS1    0xffU
+#define V_ODT_RD_VALUES_X2PLUS1(x) ((x) << S_ODT_RD_VALUES_X2PLUS1)
+#define G_ODT_RD_VALUES_X2PLUS1(x) (((x) >> S_ODT_RD_VALUES_X2PLUS1) & M_ODT_RD_VALUES_X2PLUS1)
+
+#define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG1 0x4723c
+#define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG2 0x47240
+#define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG3 0x47244
+#define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM0 0x47248
+
+#define S_TMOD_CYCLES    12
+#define M_TMOD_CYCLES    0xfU
+#define V_TMOD_CYCLES(x) ((x) << S_TMOD_CYCLES)
+#define G_TMOD_CYCLES(x) (((x) >> S_TMOD_CYCLES) & M_TMOD_CYCLES)
+
+#define S_TRCD_CYCLES    8
+#define M_TRCD_CYCLES    0xfU
+#define V_TRCD_CYCLES(x) ((x) << S_TRCD_CYCLES)
+#define G_TRCD_CYCLES(x) (((x) >> S_TRCD_CYCLES) & M_TRCD_CYCLES)
+
+#define S_TRP_CYCLES    4
+#define M_TRP_CYCLES    0xfU
+#define V_TRP_CYCLES(x) ((x) << S_TRP_CYCLES)
+#define G_TRP_CYCLES(x) (((x) >> S_TRP_CYCLES) & M_TRP_CYCLES)
+
+#define S_TRFC_CYCLES    0
+#define M_TRFC_CYCLES    0xfU
+#define V_TRFC_CYCLES(x) ((x) << S_TRFC_CYCLES)
+#define G_TRFC_CYCLES(x) (((x) >> S_TRFC_CYCLES) & M_TRFC_CYCLES)
+
+#define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM1 0x4724c
+
+#define S_TZQINIT_CYCLES    12
+#define M_TZQINIT_CYCLES    0xfU
+#define V_TZQINIT_CYCLES(x) ((x) << S_TZQINIT_CYCLES)
+#define G_TZQINIT_CYCLES(x) (((x) >> S_TZQINIT_CYCLES) & M_TZQINIT_CYCLES)
+
+#define S_TZQCS_CYCLES    8
+#define M_TZQCS_CYCLES    0xfU
+#define V_TZQCS_CYCLES(x) ((x) << S_TZQCS_CYCLES)
+#define G_TZQCS_CYCLES(x) (((x) >> S_TZQCS_CYCLES) & M_TZQCS_CYCLES)
+
+#define S_TWLDQSEN_CYCLES    4
+#define M_TWLDQSEN_CYCLES    0xfU
+#define V_TWLDQSEN_CYCLES(x) ((x) << S_TWLDQSEN_CYCLES)
+#define G_TWLDQSEN_CYCLES(x) (((x) >> S_TWLDQSEN_CYCLES) & M_TWLDQSEN_CYCLES)
+
+#define S_TWRMRD_CYCLES    0
+#define M_TWRMRD_CYCLES    0xfU
+#define V_TWRMRD_CYCLES(x) ((x) << S_TWRMRD_CYCLES)
+#define G_TWRMRD_CYCLES(x) (((x) >> S_TWRMRD_CYCLES) & M_TWRMRD_CYCLES)
+
+#define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM2 0x47250
+
+#define S_TODTLON_OFF_CYCLES    12
+#define M_TODTLON_OFF_CYCLES    0xfU
+#define V_TODTLON_OFF_CYCLES(x) ((x) << S_TODTLON_OFF_CYCLES)
+#define G_TODTLON_OFF_CYCLES(x) (((x) >> S_TODTLON_OFF_CYCLES) & M_TODTLON_OFF_CYCLES)
+
+#define S_TRC_CYCLES    8
+#define M_TRC_CYCLES    0xfU
+#define V_TRC_CYCLES(x) ((x) << S_TRC_CYCLES)
+#define G_TRC_CYCLES(x) (((x) >> S_TRC_CYCLES) & M_TRC_CYCLES)
+
+#define S_TMRSC_CYCLES    4
+#define M_TMRSC_CYCLES    0xfU
+#define V_TMRSC_CYCLES(x) ((x) << S_TMRSC_CYCLES)
+#define G_TMRSC_CYCLES(x) (((x) >> S_TMRSC_CYCLES) & M_TMRSC_CYCLES)
+
+#define A_MC_DDRPHY_RC_CONFIG0 0x47400
+
+#define S_GLOBAL_PHY_OFFSET    12
+#define M_GLOBAL_PHY_OFFSET    0xfU
+#define V_GLOBAL_PHY_OFFSET(x) ((x) << S_GLOBAL_PHY_OFFSET)
+#define G_GLOBAL_PHY_OFFSET(x) (((x) >> S_GLOBAL_PHY_OFFSET) & M_GLOBAL_PHY_OFFSET)
+
+#define S_ADVANCE_RD_VALID    11
+#define V_ADVANCE_RD_VALID(x) ((x) << S_ADVANCE_RD_VALID)
+#define F_ADVANCE_RD_VALID    V_ADVANCE_RD_VALID(1U)
+
+#define S_SINGLE_BIT_MPR_RP0    6
+#define V_SINGLE_BIT_MPR_RP0(x) ((x) << S_SINGLE_BIT_MPR_RP0)
+#define F_SINGLE_BIT_MPR_RP0    V_SINGLE_BIT_MPR_RP0(1U)
+
+#define S_SINGLE_BIT_MPR_RP1    5
+#define V_SINGLE_BIT_MPR_RP1(x) ((x) << S_SINGLE_BIT_MPR_RP1)
+#define F_SINGLE_BIT_MPR_RP1    V_SINGLE_BIT_MPR_RP1(1U)
+
+#define S_SINGLE_BIT_MPR_RP2    4
+#define V_SINGLE_BIT_MPR_RP2(x) ((x) << S_SINGLE_BIT_MPR_RP2)
+#define F_SINGLE_BIT_MPR_RP2    V_SINGLE_BIT_MPR_RP2(1U)
+
+#define S_SINGLE_BIT_MPR_RP3    3
+#define V_SINGLE_BIT_MPR_RP3(x) ((x) << S_SINGLE_BIT_MPR_RP3)
+#define F_SINGLE_BIT_MPR_RP3    V_SINGLE_BIT_MPR_RP3(1U)
+
+#define S_ALIGN_ON_EVEN_CYCLES    2
+#define V_ALIGN_ON_EVEN_CYCLES(x) ((x) << S_ALIGN_ON_EVEN_CYCLES)
+#define F_ALIGN_ON_EVEN_CYCLES    V_ALIGN_ON_EVEN_CYCLES(1U)
+
+#define S_PERFORM_RDCLK_ALIGN    1
+#define V_PERFORM_RDCLK_ALIGN(x) ((x) << S_PERFORM_RDCLK_ALIGN)
+#define F_PERFORM_RDCLK_ALIGN    V_PERFORM_RDCLK_ALIGN(1U)
+
+#define S_STAGGERED_PATTERN    0
+#define V_STAGGERED_PATTERN(x) ((x) << S_STAGGERED_PATTERN)
+#define F_STAGGERED_PATTERN    V_STAGGERED_PATTERN(1U)
+
+#define A_MC_DDRPHY_RC_CONFIG1 0x47404
+
+#define S_OUTER_LOOP_CNT    2
+#define M_OUTER_LOOP_CNT    0x3fffU
+#define V_OUTER_LOOP_CNT(x) ((x) << S_OUTER_LOOP_CNT)
+#define G_OUTER_LOOP_CNT(x) (((x) >> S_OUTER_LOOP_CNT) & M_OUTER_LOOP_CNT)
+
+#define A_MC_DDRPHY_RC_CONFIG2 0x47408
+
+#define S_CONSEQ_PASS    11
+#define M_CONSEQ_PASS    0x1fU
+#define V_CONSEQ_PASS(x) ((x) << S_CONSEQ_PASS)
+#define G_CONSEQ_PASS(x) (((x) >> S_CONSEQ_PASS) & M_CONSEQ_PASS)
+
+#define S_BURST_WINDOW    5
+#define M_BURST_WINDOW    0x3U
+#define V_BURST_WINDOW(x) ((x) << S_BURST_WINDOW)
+#define G_BURST_WINDOW(x) (((x) >> S_BURST_WINDOW) & M_BURST_WINDOW)
+
+#define S_ALLOW_RD_FIFO_AUTO_R_ESET    4
+#define V_ALLOW_RD_FIFO_AUTO_R_ESET(x) ((x) << S_ALLOW_RD_FIFO_AUTO_R_ESET)
+#define F_ALLOW_RD_FIFO_AUTO_R_ESET    V_ALLOW_RD_FIFO_AUTO_R_ESET(1U)
+
+#define A_MC_DDRPHY_RC_ERROR_STATUS0 0x47414
+
+#define S_RD_CNTL_ERROR    15
+#define V_RD_CNTL_ERROR(x) ((x) << S_RD_CNTL_ERROR)
+#define F_RD_CNTL_ERROR    V_RD_CNTL_ERROR(1U)
+
+#define A_MC_DDRPHY_RC_ERROR_MASK0 0x47418
+
+#define S_RD_CNTL_ERROR_MASK    15
+#define V_RD_CNTL_ERROR_MASK(x) ((x) << S_RD_CNTL_ERROR_MASK)
+#define F_RD_CNTL_ERROR_MASK    V_RD_CNTL_ERROR_MASK(1U)
+
+#define A_MC_DDRPHY_RC_CONFIG3 0x4741c
+
+#define S_FINE_CAL_STEP_SIZE    13
+#define M_FINE_CAL_STEP_SIZE    0x7U
+#define V_FINE_CAL_STEP_SIZE(x) ((x) << S_FINE_CAL_STEP_SIZE)
+#define G_FINE_CAL_STEP_SIZE(x) (((x) >> S_FINE_CAL_STEP_SIZE) & M_FINE_CAL_STEP_SIZE)
+
+#define S_COARSE_CAL_STEP_SIZE    9
+#define M_COARSE_CAL_STEP_SIZE    0xfU
+#define V_COARSE_CAL_STEP_SIZE(x) ((x) << S_COARSE_CAL_STEP_SIZE)
+#define G_COARSE_CAL_STEP_SIZE(x) (((x) >> S_COARSE_CAL_STEP_SIZE) & M_COARSE_CAL_STEP_SIZE)
+
+#define S_DQ_SEL_QUAD    7
+#define M_DQ_SEL_QUAD    0x3U
+#define V_DQ_SEL_QUAD(x) ((x) << S_DQ_SEL_QUAD)
+#define G_DQ_SEL_QUAD(x) (((x) >> S_DQ_SEL_QUAD) & M_DQ_SEL_QUAD)
+
+#define S_DQ_SEL_LANE    4
+#define M_DQ_SEL_LANE    0x7U
+#define V_DQ_SEL_LANE(x) ((x) << S_DQ_SEL_LANE)
+#define G_DQ_SEL_LANE(x) (((x) >> S_DQ_SEL_LANE) & M_DQ_SEL_LANE)
+
+#define A_MC_DDRPHY_RC_PERIODIC 0x47420
+#define A_MC_DDRPHY_WC_CONFIG0 0x47600
+
+#define S_TWLO_TWLOE    8
+#define M_TWLO_TWLOE    0xffU
+#define V_TWLO_TWLOE(x) ((x) << S_TWLO_TWLOE)
+#define G_TWLO_TWLOE(x) (((x) >> S_TWLO_TWLOE) & M_TWLO_TWLOE)
+
+#define S_WL_ONE_DQS_PULSE    7
+#define V_WL_ONE_DQS_PULSE(x) ((x) << S_WL_ONE_DQS_PULSE)
+#define F_WL_ONE_DQS_PULSE    V_WL_ONE_DQS_PULSE(1U)
+
+#define S_FW_WR_RD    1
+#define M_FW_WR_RD    0x3fU
+#define V_FW_WR_RD(x) ((x) << S_FW_WR_RD)
+#define G_FW_WR_RD(x) (((x) >> S_FW_WR_RD) & M_FW_WR_RD)
+
+#define S_CUSTOM_INIT_WRITE    0
+#define V_CUSTOM_INIT_WRITE(x) ((x) << S_CUSTOM_INIT_WRITE)
+#define F_CUSTOM_INIT_WRITE    V_CUSTOM_INIT_WRITE(1U)
+
+#define A_MC_DDRPHY_WC_CONFIG1 0x47604
+
+#define S_BIG_STEP    12
+#define M_BIG_STEP    0xfU
+#define V_BIG_STEP(x) ((x) << S_BIG_STEP)
+#define G_BIG_STEP(x) (((x) >> S_BIG_STEP) & M_BIG_STEP)
+
+#define S_SMALL_STEP    9
+#define M_SMALL_STEP    0x7U
+#define V_SMALL_STEP(x) ((x) << S_SMALL_STEP)
+#define G_SMALL_STEP(x) (((x) >> S_SMALL_STEP) & M_SMALL_STEP)
+
+#define S_WR_PRE_DLY    3
+#define M_WR_PRE_DLY    0x3fU
+#define V_WR_PRE_DLY(x) ((x) << S_WR_PRE_DLY)
+#define G_WR_PRE_DLY(x) (((x) >> S_WR_PRE_DLY) & M_WR_PRE_DLY)
+
+#define A_MC_DDRPHY_WC_CONFIG2 0x47608
+
+#define S_NUM_VALID_SAMPLES    12
+#define M_NUM_VALID_SAMPLES    0xfU
+#define V_NUM_VALID_SAMPLES(x) ((x) << S_NUM_VALID_SAMPLES)
+#define G_NUM_VALID_SAMPLES(x) (((x) >> S_NUM_VALID_SAMPLES) & M_NUM_VALID_SAMPLES)
+
+#define S_FW_RD_WR    6
+#define M_FW_RD_WR    0x3fU
+#define V_FW_RD_WR(x) ((x) << S_FW_RD_WR)
+#define G_FW_RD_WR(x) (((x) >> S_FW_RD_WR) & M_FW_RD_WR)
+
+#define A_MC_DDRPHY_WC_ERROR_STATUS0 0x4760c
+
+#define S_WR_CNTL_ERROR    15
+#define V_WR_CNTL_ERROR(x) ((x) << S_WR_CNTL_ERROR)
+#define F_WR_CNTL_ERROR    V_WR_CNTL_ERROR(1U)
+
+#define A_MC_DDRPHY_WC_ERROR_MASK0 0x47610
+
+#define S_WR_CNTL_ERROR_MASK    15
+#define V_WR_CNTL_ERROR_MASK(x) ((x) << S_WR_CNTL_ERROR_MASK)
+#define F_WR_CNTL_ERROR_MASK    V_WR_CNTL_ERROR_MASK(1U)
+
+#define A_MC_DDRPHY_WC_CONFIG3 0x47614
+
+#define S_DDR4_MRS_CMD_DQ_EN    15
+#define V_DDR4_MRS_CMD_DQ_EN(x) ((x) << S_DDR4_MRS_CMD_DQ_EN)
+#define F_DDR4_MRS_CMD_DQ_EN    V_DDR4_MRS_CMD_DQ_EN(1U)
+
+#define S_MRS_CMD_DQ_ON    9
+#define M_MRS_CMD_DQ_ON    0x3fU
+#define V_MRS_CMD_DQ_ON(x) ((x) << S_MRS_CMD_DQ_ON)
+#define G_MRS_CMD_DQ_ON(x) (((x) >> S_MRS_CMD_DQ_ON) & M_MRS_CMD_DQ_ON)
+
+#define S_MRS_CMD_DQ_OFF    3
+#define M_MRS_CMD_DQ_OFF    0x3fU
+#define V_MRS_CMD_DQ_OFF(x) ((x) << S_MRS_CMD_DQ_OFF)
+#define G_MRS_CMD_DQ_OFF(x) (((x) >> S_MRS_CMD_DQ_OFF) & M_MRS_CMD_DQ_OFF)
+
+#define A_MC_DDRPHY_WC_WRCLK_CNTL 0x47618
+
+#define S_WRCLK_CAL_START    15
+#define V_WRCLK_CAL_START(x) ((x) << S_WRCLK_CAL_START)
+#define F_WRCLK_CAL_START    V_WRCLK_CAL_START(1U)
+
+#define S_WRCLK_CAL_DONE    14
+#define V_WRCLK_CAL_DONE(x) ((x) << S_WRCLK_CAL_DONE)
+#define F_WRCLK_CAL_DONE    V_WRCLK_CAL_DONE(1U)
+
+#define A_MC_DDRPHY_APB_CONFIG0 0x47800
+
+#define S_DISABLE_PARITY_CHECKER    15
+#define V_DISABLE_PARITY_CHECKER(x) ((x) << S_DISABLE_PARITY_CHECKER)
+#define F_DISABLE_PARITY_CHECKER    V_DISABLE_PARITY_CHECKER(1U)
+
+#define S_GENERATE_EVEN_PARITY    14
+#define V_GENERATE_EVEN_PARITY(x) ((x) << S_GENERATE_EVEN_PARITY)
+#define F_GENERATE_EVEN_PARITY    V_GENERATE_EVEN_PARITY(1U)
+
+#define S_FORCE_ON_CLK_GATE    13
+#define V_FORCE_ON_CLK_GATE(x) ((x) << S_FORCE_ON_CLK_GATE)
+#define F_FORCE_ON_CLK_GATE    V_FORCE_ON_CLK_GATE(1U)
+
+#define S_DEBUG_BUS_SEL_LO    12
+#define V_DEBUG_BUS_SEL_LO(x) ((x) << S_DEBUG_BUS_SEL_LO)
+#define F_DEBUG_BUS_SEL_LO    V_DEBUG_BUS_SEL_LO(1U)
+
+#define S_DEBUG_BUS_SEL_HI    8
+#define M_DEBUG_BUS_SEL_HI    0xfU
+#define V_DEBUG_BUS_SEL_HI(x) ((x) << S_DEBUG_BUS_SEL_HI)
+#define G_DEBUG_BUS_SEL_HI(x) (((x) >> S_DEBUG_BUS_SEL_HI) & M_DEBUG_BUS_SEL_HI)
+
+#define A_MC_DDRPHY_APB_ERROR_STATUS0 0x47804
+
+#define S_INVALID_ADDRESS    15
+#define V_INVALID_ADDRESS(x) ((x) << S_INVALID_ADDRESS)
+#define F_INVALID_ADDRESS    V_INVALID_ADDRESS(1U)
+
+#define S_WR_PAR_ERR    14
+#define V_WR_PAR_ERR(x) ((x) << S_WR_PAR_ERR)
+#define F_WR_PAR_ERR    V_WR_PAR_ERR(1U)
+
+#define A_MC_DDRPHY_APB_ERROR_MASK0 0x47808
+
+#define S_INVALID_ADDRESS_MASK    15
+#define V_INVALID_ADDRESS_MASK(x) ((x) << S_INVALID_ADDRESS_MASK)
+#define F_INVALID_ADDRESS_MASK    V_INVALID_ADDRESS_MASK(1U)
+
+#define S_WR_PAR_ERR_MASK    14
+#define V_WR_PAR_ERR_MASK(x) ((x) << S_WR_PAR_ERR_MASK)
+#define F_WR_PAR_ERR_MASK    V_WR_PAR_ERR_MASK(1U)
+
+#define A_MC_DDRPHY_APB_DP18_POPULATION 0x4780c
+
+#define S_DP18_0_POPULATED    15
+#define V_DP18_0_POPULATED(x) ((x) << S_DP18_0_POPULATED)
+#define F_DP18_0_POPULATED    V_DP18_0_POPULATED(1U)
+
+#define S_DP18_1_POPULATED    14
+#define V_DP18_1_POPULATED(x) ((x) << S_DP18_1_POPULATED)
+#define F_DP18_1_POPULATED    V_DP18_1_POPULATED(1U)
+
+#define S_DP18_2_POPULATED    13
+#define V_DP18_2_POPULATED(x) ((x) << S_DP18_2_POPULATED)
+#define F_DP18_2_POPULATED    V_DP18_2_POPULATED(1U)
+
+#define S_DP18_3_POPULATED    12
+#define V_DP18_3_POPULATED(x) ((x) << S_DP18_3_POPULATED)
+#define F_DP18_3_POPULATED    V_DP18_3_POPULATED(1U)
+
+#define S_DP18_4_POPULATED    11
+#define V_DP18_4_POPULATED(x) ((x) << S_DP18_4_POPULATED)
+#define F_DP18_4_POPULATED    V_DP18_4_POPULATED(1U)
+
+#define S_DP18_5_POPULATED    10
+#define V_DP18_5_POPULATED(x) ((x) << S_DP18_5_POPULATED)
+#define F_DP18_5_POPULATED    V_DP18_5_POPULATED(1U)
+
+#define S_DP18_6_POPULATED    9
+#define V_DP18_6_POPULATED(x) ((x) << S_DP18_6_POPULATED)
+#define F_DP18_6_POPULATED    V_DP18_6_POPULATED(1U)
+
+#define S_DP18_7_POPULATED    8
+#define V_DP18_7_POPULATED(x) ((x) << S_DP18_7_POPULATED)
+#define F_DP18_7_POPULATED    V_DP18_7_POPULATED(1U)
+
+#define S_DP18_8_POPULATED    7
+#define V_DP18_8_POPULATED(x) ((x) << S_DP18_8_POPULATED)
+#define F_DP18_8_POPULATED    V_DP18_8_POPULATED(1U)
+
+#define S_DP18_9_POPULATED    6
+#define V_DP18_9_POPULATED(x) ((x) << S_DP18_9_POPULATED)
+#define F_DP18_9_POPULATED    V_DP18_9_POPULATED(1U)
+
+#define S_DP18_10_POPULATED    5
+#define V_DP18_10_POPULATED(x) ((x) << S_DP18_10_POPULATED)
+#define F_DP18_10_POPULATED    V_DP18_10_POPULATED(1U)
+
+#define S_DP18_11_POPULATED    4
+#define V_DP18_11_POPULATED(x) ((x) << S_DP18_11_POPULATED)
+#define F_DP18_11_POPULATED    V_DP18_11_POPULATED(1U)
+
+#define S_DP18_12_POPULATED    3
+#define V_DP18_12_POPULATED(x) ((x) << S_DP18_12_POPULATED)
+#define F_DP18_12_POPULATED    V_DP18_12_POPULATED(1U)
+
+#define S_DP18_13_POPULATED    2
+#define V_DP18_13_POPULATED(x) ((x) << S_DP18_13_POPULATED)
+#define F_DP18_13_POPULATED    V_DP18_13_POPULATED(1U)
+
+#define S_DP18_14_POPULATED    1
+#define V_DP18_14_POPULATED(x) ((x) << S_DP18_14_POPULATED)
+#define F_DP18_14_POPULATED    V_DP18_14_POPULATED(1U)
+
+#define A_MC_DDRPHY_APB_ADR_POPULATION 0x47810
+
+#define S_ADR16_0_POPULATED    15
+#define V_ADR16_0_POPULATED(x) ((x) << S_ADR16_0_POPULATED)
+#define F_ADR16_0_POPULATED    V_ADR16_0_POPULATED(1U)
+
+#define S_ADR16_1_POPULATED    14
+#define V_ADR16_1_POPULATED(x) ((x) << S_ADR16_1_POPULATED)
+#define F_ADR16_1_POPULATED    V_ADR16_1_POPULATED(1U)
+
+#define S_ADR16_2_POPULATED    13
+#define V_ADR16_2_POPULATED(x) ((x) << S_ADR16_2_POPULATED)
+#define F_ADR16_2_POPULATED    V_ADR16_2_POPULATED(1U)
+
+#define S_ADR16_3_POPULATED    12
+#define V_ADR16_3_POPULATED(x) ((x) << S_ADR16_3_POPULATED)
+#define F_ADR16_3_POPULATED    V_ADR16_3_POPULATED(1U)
+
+#define S_ADR12_0_POPULATED    7
+#define V_ADR12_0_POPULATED(x) ((x) << S_ADR12_0_POPULATED)
+#define F_ADR12_0_POPULATED    V_ADR12_0_POPULATED(1U)
+
+#define S_ADR12_1_POPULATED    6
+#define V_ADR12_1_POPULATED(x) ((x) << S_ADR12_1_POPULATED)
+#define F_ADR12_1_POPULATED    V_ADR12_1_POPULATED(1U)
+
+#define S_ADR12_2_POPULATED    5
+#define V_ADR12_2_POPULATED(x) ((x) << S_ADR12_2_POPULATED)
+#define F_ADR12_2_POPULATED    V_ADR12_2_POPULATED(1U)
+
+#define S_ADR12_3_POPULATED    4
+#define V_ADR12_3_POPULATED(x) ((x) << S_ADR12_3_POPULATED)
+#define F_ADR12_3_POPULATED    V_ADR12_3_POPULATED(1U)
+
+#define A_MC_DDRPHY_APB_ATEST_MUX_SEL 0x47814
+
+#define S_ATEST_CNTL    10
+#define M_ATEST_CNTL    0x3fU
+#define V_ATEST_CNTL(x) ((x) << S_ATEST_CNTL)
+#define G_ATEST_CNTL(x) (((x) >> S_ATEST_CNTL) & M_ATEST_CNTL)
+
+/* registers for module MC_1 */
+#define MC_1_BASE_ADDR 0x48000
+
+/* registers for module EDC_T50 */
+#define EDC_T50_BASE_ADDR 0x50000
+
+#define A_EDC_H_REF 0x50000
+
+#define S_EDC_SLEEPSTATUS    31
+#define V_EDC_SLEEPSTATUS(x) ((x) << S_EDC_SLEEPSTATUS)
+#define F_EDC_SLEEPSTATUS    V_EDC_SLEEPSTATUS(1U)
+
+#define S_EDC_SLEEPREQ    30
+#define V_EDC_SLEEPREQ(x) ((x) << S_EDC_SLEEPREQ)
+#define F_EDC_SLEEPREQ    V_EDC_SLEEPREQ(1U)
+
+#define S_PING_PONG    29
+#define V_PING_PONG(x) ((x) << S_PING_PONG)
+#define F_PING_PONG    V_PING_PONG(1U)
+
+#define A_EDC_H_BIST_CMD 0x50004
+#define A_EDC_H_BIST_CMD_ADDR 0x50008
+#define A_EDC_H_BIST_CMD_LEN 0x5000c
+#define A_EDC_H_BIST_DATA_PATTERN 0x50010
+#define A_EDC_H_BIST_USER_WDATA0 0x50014
+#define A_EDC_H_BIST_USER_WDATA1 0x50018
+#define A_EDC_H_BIST_USER_WDATA2 0x5001c
+#define A_EDC_H_BIST_NUM_ERR 0x50020
+#define A_EDC_H_BIST_ERR_FIRST_ADDR 0x50024
+#define A_EDC_H_BIST_STATUS_RDATA 0x50028
+#define A_EDC_H_PAR_ENABLE 0x50070
+
+#define S_PERR_PAR_ENABLE    0
+#define V_PERR_PAR_ENABLE(x) ((x) << S_PERR_PAR_ENABLE)
+#define F_PERR_PAR_ENABLE    V_PERR_PAR_ENABLE(1U)
+
+#define A_EDC_H_INT_ENABLE 0x50074
+#define A_EDC_H_INT_CAUSE 0x50078
+#define A_EDC_H_ECC_STATUS 0x5007c
+#define A_EDC_H_ECC_ERR_SEL 0x50080
+
+#define S_CFG    0
+#define M_CFG    0x3U
+#define V_CFG(x) ((x) << S_CFG)
+#define G_CFG(x) (((x) >> S_CFG) & M_CFG)
+
+#define A_EDC_H_ECC_ERR_ADDR 0x50084
+
+#define S_ECC_ADDR    0
+#define M_ECC_ADDR    0x7fffffU
+#define V_ECC_ADDR(x) ((x) << S_ECC_ADDR)
+#define G_ECC_ADDR(x) (((x) >> S_ECC_ADDR) & M_ECC_ADDR)
+
+#define A_EDC_H_ECC_ERR_DATA_RDATA 0x50090
+#define A_EDC_H_BIST_CRC_SEED 0x50400
+
+/* registers for module EDC_T51 */
+#define EDC_T51_BASE_ADDR 0x50800
+
+/* registers for module HMA_T5 */
+#define HMA_T5_BASE_ADDR 0x51000
+
+#define A_HMA_TABLE_ACCESS 0x51000
+
+#define S_TRIG    31
+#define V_TRIG(x) ((x) << S_TRIG)
+#define F_TRIG    V_TRIG(1U)
+
+#define S_RW    30
+#define V_RW(x) ((x) << S_RW)
+#define F_RW    V_RW(1U)
+
+#define S_L_SEL    0
+#define M_L_SEL    0xfU
+#define V_L_SEL(x) ((x) << S_L_SEL)
+#define G_L_SEL(x) (((x) >> S_L_SEL) & M_L_SEL)
+
+#define A_HMA_TABLE_LINE0 0x51004
+
+#define S_CLIENT_EN    0
+#define M_CLIENT_EN    0x1fffU
+#define V_CLIENT_EN(x) ((x) << S_CLIENT_EN)
+#define G_CLIENT_EN(x) (((x) >> S_CLIENT_EN) & M_CLIENT_EN)
+
+#define A_HMA_TABLE_LINE1 0x51008
+#define A_HMA_TABLE_LINE2 0x5100c
+#define A_HMA_TABLE_LINE3 0x51010
+#define A_HMA_TABLE_LINE4 0x51014
+#define A_HMA_TABLE_LINE5 0x51018
+
+#define S_FID    16
+#define M_FID    0x7ffU
+#define V_FID(x) ((x) << S_FID)
+#define G_FID(x) (((x) >> S_FID) & M_FID)
+
+#define S_NOS    15
+#define V_NOS(x) ((x) << S_NOS)
+#define F_NOS    V_NOS(1U)
+
+#define S_RO    14
+#define V_RO(x) ((x) << S_RO)
+#define F_RO    V_RO(1U)
+
+#define A_HMA_COOKIE 0x5101c
+
+#define S_C_REQ    31
+#define V_C_REQ(x) ((x) << S_C_REQ)
+#define F_C_REQ    V_C_REQ(1U)
+
+#define S_C_FID    18
+#define M_C_FID    0x7ffU
+#define V_C_FID(x) ((x) << S_C_FID)
+#define G_C_FID(x) (((x) >> S_C_FID) & M_C_FID)
+
+#define S_C_VAL    8
+#define M_C_VAL    0x3ffU
+#define V_C_VAL(x) ((x) << S_C_VAL)
+#define G_C_VAL(x) (((x) >> S_C_VAL) & M_C_VAL)
+
+#define S_C_SEL    0
+#define M_C_SEL    0xfU
+#define V_C_SEL(x) ((x) << S_C_SEL)
+#define G_C_SEL(x) (((x) >> S_C_SEL) & M_C_SEL)
+
+#define A_HMA_PAR_ENABLE 0x51300
+#define A_HMA_INT_ENABLE 0x51304
+#define A_HMA_INT_CAUSE 0x51308
diff --git a/contrib/ofed/libcxgb4/src/t4fw_interface.h b/contrib/ofed/libcxgb4/src/t4fw_interface.h
new file mode 100644
index 0000000..988b513
--- /dev/null
+++ b/contrib/ofed/libcxgb4/src/t4fw_interface.h
@@ -0,0 +1,7811 @@
+/*
+ * Chelsio Terminator 4 (T4) Firmware interface header file.
+ *
+ * Copyright (C) 2009-2014 Chelsio Communications.  All rights reserved.
+ *
+ * Written by felix marti (felix@chelsio.com)
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the LICENSE file included in this
+ * release for licensing terms and conditions.
+ */
+
+#ifndef _T4FW_INTERFACE_H_
+#define _T4FW_INTERFACE_H_
+
+/******************************************************************************
+ *   R E T U R N   V A L U E S
+ ********************************/
+
+enum fw_retval {
+	FW_SUCCESS		= 0,	/* completed sucessfully */
+	FW_EPERM		= 1,	/* operation not permitted */
+	FW_ENOENT		= 2,	/* no such file or directory */
+	FW_EIO			= 5,	/* input/output error; hw bad */
+	FW_ENOEXEC		= 8,	/* exec format error; inv microcode */
+	FW_EAGAIN		= 11,	/* try again */
+	FW_ENOMEM		= 12,	/* out of memory */
+	FW_EFAULT		= 14,	/* bad address; fw bad */
+	FW_EBUSY		= 16,	/* resource busy */
+	FW_EEXIST		= 17,	/* file exists */
+	FW_ENODEV		= 19,	/* no such device */
+	FW_EINVAL		= 22,	/* invalid argument */
+	FW_ENOSPC		= 28,	/* no space left on device */
+	FW_ENOSYS		= 38,	/* functionality not implemented */
+	FW_ENODATA		= 61,	/* no data available */
+	FW_EPROTO		= 71,	/* protocol error */
+	FW_EADDRINUSE		= 98,	/* address already in use */
+	FW_EADDRNOTAVAIL	= 99,	/* cannot assigned requested address */
+	FW_ENETDOWN		= 100,	/* network is down */
+	FW_ENETUNREACH		= 101,	/* network is unreachable */
+	FW_ENOBUFS		= 105,	/* no buffer space available */
+	FW_ETIMEDOUT		= 110,	/* timeout */
+	FW_EINPROGRESS		= 115,	/* fw internal */
+	FW_SCSI_ABORT_REQUESTED	= 128,	/* */
+	FW_SCSI_ABORT_TIMEDOUT	= 129,	/* */
+	FW_SCSI_ABORTED		= 130,	/* */
+	FW_SCSI_CLOSE_REQUESTED	= 131,	/* */
+	FW_ERR_LINK_DOWN	= 132,	/* */
+	FW_RDEV_NOT_READY	= 133,	/* */
+	FW_ERR_RDEV_LOST	= 134,	/* */
+	FW_ERR_RDEV_LOGO	= 135,	/* */
+	FW_FCOE_NO_XCHG		= 136,	/* */
+	FW_SCSI_RSP_ERR		= 137,	/* */
+	FW_ERR_RDEV_IMPL_LOGO	= 138,	/* */
+	FW_SCSI_UNDER_FLOW_ERR  = 139,	/* */
+	FW_SCSI_OVER_FLOW_ERR   = 140,	/* */
+	FW_SCSI_DDP_ERR		= 141,	/* DDP error*/
+	FW_SCSI_TASK_ERR	= 142,	/* No SCSI tasks available */
+};
+
+/******************************************************************************
+ *   M E M O R Y   T Y P E s
+ ******************************/
+
+enum fw_memtype {
+	FW_MEMTYPE_EDC0		= 0x0,
+	FW_MEMTYPE_EDC1		= 0x1,
+	FW_MEMTYPE_EXTMEM	= 0x2,
+	FW_MEMTYPE_FLASH	= 0x4,
+	FW_MEMTYPE_INTERNAL	= 0x5,
+	FW_MEMTYPE_EXTMEM1	= 0x6,
+};
+
+/******************************************************************************
+ *   W O R K   R E Q U E S T s
+ ********************************/
+
+enum fw_wr_opcodes {
+	FW_FRAG_WR		= 0x1d,
+	FW_FILTER_WR		= 0x02,
+	FW_ULPTX_WR		= 0x04,
+	FW_TP_WR		= 0x05,
+	FW_ETH_TX_PKT_WR	= 0x08,
+	FW_ETH_TX_PKT2_WR	= 0x44,
+	FW_ETH_TX_PKTS_WR	= 0x09,
+	FW_ETH_TX_UO_WR		= 0x1c,
+	FW_EQ_FLUSH_WR		= 0x1b,
+	FW_OFLD_CONNECTION_WR	= 0x2f,
+	FW_FLOWC_WR		= 0x0a,
+	FW_OFLD_TX_DATA_WR	= 0x0b,
+	FW_CMD_WR		= 0x10,
+	FW_ETH_TX_PKT_VM_WR	= 0x11,
+	FW_RI_RES_WR		= 0x0c,
+	FW_RI_RDMA_WRITE_WR	= 0x14,
+	FW_RI_SEND_WR		= 0x15,
+	FW_RI_RDMA_READ_WR	= 0x16,
+	FW_RI_RECV_WR		= 0x17,
+	FW_RI_BIND_MW_WR	= 0x18,
+	FW_RI_FR_NSMR_WR	= 0x19,
+	FW_RI_INV_LSTAG_WR	= 0x1a,
+	FW_RI_SEND_IMMEDIATE_WR	= 0x15,
+	FW_RI_ATOMIC_WR		= 0x16,
+	FW_RI_WR		= 0x0d,
+	FW_CHNET_IFCONF_WR	= 0x6b,
+	FW_RDEV_WR		= 0x38,
+	FW_FOISCSI_NODE_WR	= 0x60,
+	FW_FOISCSI_CTRL_WR	= 0x6a,
+	FW_FOISCSI_CHAP_WR	= 0x6c,
+	FW_FCOE_ELS_CT_WR	= 0x30,
+	FW_SCSI_WRITE_WR	= 0x31,
+	FW_SCSI_READ_WR		= 0x32,
+	FW_SCSI_CMD_WR		= 0x33,
+	FW_SCSI_ABRT_CLS_WR	= 0x34,
+	FW_SCSI_TGT_ACC_WR	= 0x35,
+	FW_SCSI_TGT_XMIT_WR	= 0x36,
+	FW_SCSI_TGT_RSP_WR	= 0x37,
+	FW_POFCOE_TCB_WR	= 0x42,
+	FW_POFCOE_ULPTX_WR	= 0x43,
+	FW_LASTC2E_WR		= 0x70
+};
+
+/*
+ * Generic work request header flit0
+ */
+struct fw_wr_hdr {
+	__be32 hi;
+	__be32 lo;
+};
+
+/*	work request opcode (hi)
+ */
+#define S_FW_WR_OP		24
+#define M_FW_WR_OP		0xff
+#define V_FW_WR_OP(x)		((x) << S_FW_WR_OP)
+#define G_FW_WR_OP(x)		(((x) >> S_FW_WR_OP) & M_FW_WR_OP)
+
+/*	atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER
+ */
+#define S_FW_WR_ATOMIC		23
+#define M_FW_WR_ATOMIC		0x1
+#define V_FW_WR_ATOMIC(x)	((x) << S_FW_WR_ATOMIC)
+#define G_FW_WR_ATOMIC(x)	\
+    (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC)
+#define F_FW_WR_ATOMIC		V_FW_WR_ATOMIC(1U)
+
+/*	flush flag (hi) - firmware flushes flushable work request buffered
+ *			      in the flow context.
+ */
+#define S_FW_WR_FLUSH     22
+#define M_FW_WR_FLUSH     0x1
+#define V_FW_WR_FLUSH(x)  ((x) << S_FW_WR_FLUSH)
+#define G_FW_WR_FLUSH(x)  \
+    (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH)
+#define F_FW_WR_FLUSH     V_FW_WR_FLUSH(1U)
+
+/*	completion flag (hi) - firmware generates a cpl_fw6_ack
+ */
+#define S_FW_WR_COMPL     21
+#define M_FW_WR_COMPL     0x1
+#define V_FW_WR_COMPL(x)  ((x) << S_FW_WR_COMPL)
+#define G_FW_WR_COMPL(x)  \
+    (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL)
+#define F_FW_WR_COMPL     V_FW_WR_COMPL(1U)
+
+
+/*	work request immediate data lengh (hi)
+ */
+#define S_FW_WR_IMMDLEN	0
+#define M_FW_WR_IMMDLEN	0xff
+#define V_FW_WR_IMMDLEN(x)	((x) << S_FW_WR_IMMDLEN)
+#define G_FW_WR_IMMDLEN(x)	\
+    (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
+
+/*	egress queue status update to associated ingress queue entry (lo)
+ */
+#define S_FW_WR_EQUIQ		31
+#define M_FW_WR_EQUIQ		0x1
+#define V_FW_WR_EQUIQ(x)	((x) << S_FW_WR_EQUIQ)
+#define G_FW_WR_EQUIQ(x)	(((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ)
+#define F_FW_WR_EQUIQ		V_FW_WR_EQUIQ(1U)
+
+/*	egress queue status update to egress queue status entry (lo)
+ */
+#define S_FW_WR_EQUEQ		30
+#define M_FW_WR_EQUEQ		0x1
+#define V_FW_WR_EQUEQ(x)	((x) << S_FW_WR_EQUEQ)
+#define G_FW_WR_EQUEQ(x)	(((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
+#define F_FW_WR_EQUEQ		V_FW_WR_EQUEQ(1U)
+
+/*	flow context identifier (lo)
+ */
+#define S_FW_WR_FLOWID		8
+#define M_FW_WR_FLOWID		0xfffff
+#define V_FW_WR_FLOWID(x)	((x) << S_FW_WR_FLOWID)
+#define G_FW_WR_FLOWID(x)	(((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID)
+
+/*	length in units of 16-bytes (lo)
+ */
+#define S_FW_WR_LEN16		0
+#define M_FW_WR_LEN16		0xff
+#define V_FW_WR_LEN16(x)	((x) << S_FW_WR_LEN16)
+#define G_FW_WR_LEN16(x)	(((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
+
+struct fw_frag_wr {
+	__be32 op_to_fragoff16;
+	__be32 flowid_len16;
+	__be64 r4;
+};
+
+#define S_FW_FRAG_WR_EOF	15
+#define M_FW_FRAG_WR_EOF	0x1
+#define V_FW_FRAG_WR_EOF(x)	((x) << S_FW_FRAG_WR_EOF)
+#define G_FW_FRAG_WR_EOF(x)	(((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF)
+#define F_FW_FRAG_WR_EOF	V_FW_FRAG_WR_EOF(1U)
+
+#define S_FW_FRAG_WR_FRAGOFF16		8
+#define M_FW_FRAG_WR_FRAGOFF16		0x7f
+#define V_FW_FRAG_WR_FRAGOFF16(x)	((x) << S_FW_FRAG_WR_FRAGOFF16)
+#define G_FW_FRAG_WR_FRAGOFF16(x)	\
+    (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16)
+
+/* valid filter configurations for compressed tuple
+ * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple
+ * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH,
+ * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN,
+ * OV - Outer VLAN/VNIC_ID,
+*/
+#define HW_TPL_FR_MT_M_E_P_FC		0x3C3
+#define HW_TPL_FR_MT_M_PR_T_FC		0x3B3
+#define HW_TPL_FR_MT_M_IV_P_FC		0x38B
+#define HW_TPL_FR_MT_M_OV_P_FC		0x387
+#define HW_TPL_FR_MT_E_PR_T		0x370
+#define HW_TPL_FR_MT_E_PR_P_FC		0X363
+#define HW_TPL_FR_MT_E_T_P_FC		0X353
+#define HW_TPL_FR_MT_PR_IV_P_FC		0X32B
+#define HW_TPL_FR_MT_PR_OV_P_FC		0X327
+#define HW_TPL_FR_MT_T_IV_P_FC		0X31B
+#define HW_TPL_FR_MT_T_OV_P_FC		0X317
+#define HW_TPL_FR_M_E_PR_FC		0X2E1
+#define HW_TPL_FR_M_E_T_FC		0X2D1
+#define HW_TPL_FR_M_PR_IV_FC		0X2A9
+#define HW_TPL_FR_M_PR_OV_FC		0X2A5
+#define HW_TPL_FR_M_T_IV_FC		0X299
+#define HW_TPL_FR_M_T_OV_FC		0X295
+#define HW_TPL_FR_E_PR_T_P		0X272
+#define HW_TPL_FR_E_PR_T_FC		0X271
+#define HW_TPL_FR_E_IV_FC		0X249
+#define HW_TPL_FR_E_OV_FC		0X245
+#define HW_TPL_FR_PR_T_IV_FC		0X239
+#define HW_TPL_FR_PR_T_OV_FC		0X235
+#define HW_TPL_FR_IV_OV_FC		0X20D
+#define HW_TPL_MT_M_E_PR		0X1E0
+#define HW_TPL_MT_M_E_T			0X1D0
+#define HW_TPL_MT_E_PR_T_FC		0X171
+#define HW_TPL_MT_E_IV			0X148
+#define HW_TPL_MT_E_OV			0X144
+#define HW_TPL_MT_PR_T_IV		0X138
+#define HW_TPL_MT_PR_T_OV		0X134
+#define HW_TPL_M_E_PR_P			0X0E2
+#define HW_TPL_M_E_T_P			0X0D2
+#define HW_TPL_E_PR_T_P_FC		0X073
+#define HW_TPL_E_IV_P			0X04A
+#define HW_TPL_E_OV_P			0X046
+#define HW_TPL_PR_T_IV_P		0X03A
+#define HW_TPL_PR_T_OV_P		0X036
+
+/* filter wr reply code in cookie in CPL_SET_TCB_RPL */
+enum fw_filter_wr_cookie {
+	FW_FILTER_WR_SUCCESS,
+	FW_FILTER_WR_FLT_ADDED,
+	FW_FILTER_WR_FLT_DELETED,
+	FW_FILTER_WR_SMT_TBL_FULL,
+	FW_FILTER_WR_EINVAL,
+};
+
+struct fw_filter_wr {
+	__be32 op_pkd;
+	__be32 len16_pkd;
+	__be64 r3;
+	__be32 tid_to_iq;
+	__be32 del_filter_to_l2tix;
+	__be16 ethtype;
+	__be16 ethtypem;
+	__u8   frag_to_ovlan_vldm;
+	__u8   smac_sel;
+	__be16 rx_chan_rx_rpl_iq;
+	__be32 maci_to_matchtypem;
+	__u8   ptcl;
+	__u8   ptclm;
+	__u8   ttyp;
+	__u8   ttypm;
+	__be16 ivlan;
+	__be16 ivlanm;
+	__be16 ovlan;
+	__be16 ovlanm;
+	__u8   lip[16];
+	__u8   lipm[16];
+	__u8   fip[16];
+	__u8   fipm[16];
+	__be16 lp;
+	__be16 lpm;
+	__be16 fp;
+	__be16 fpm;
+	__be16 r7;
+	__u8   sma[6];
+};
+
+#define S_FW_FILTER_WR_TID	12
+#define M_FW_FILTER_WR_TID	0xfffff
+#define V_FW_FILTER_WR_TID(x)	((x) << S_FW_FILTER_WR_TID)
+#define G_FW_FILTER_WR_TID(x)	\
+    (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID)
+
+#define S_FW_FILTER_WR_RQTYPE		11
+#define M_FW_FILTER_WR_RQTYPE		0x1
+#define V_FW_FILTER_WR_RQTYPE(x)	((x) << S_FW_FILTER_WR_RQTYPE)
+#define G_FW_FILTER_WR_RQTYPE(x)	\
+    (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE)
+#define F_FW_FILTER_WR_RQTYPE	V_FW_FILTER_WR_RQTYPE(1U)
+
+#define S_FW_FILTER_WR_NOREPLY		10
+#define M_FW_FILTER_WR_NOREPLY		0x1
+#define V_FW_FILTER_WR_NOREPLY(x)	((x) << S_FW_FILTER_WR_NOREPLY)
+#define G_FW_FILTER_WR_NOREPLY(x)	\
+    (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY)
+#define F_FW_FILTER_WR_NOREPLY	V_FW_FILTER_WR_NOREPLY(1U)
+
+#define S_FW_FILTER_WR_IQ	0
+#define M_FW_FILTER_WR_IQ	0x3ff
+#define V_FW_FILTER_WR_IQ(x)	((x) << S_FW_FILTER_WR_IQ)
+#define G_FW_FILTER_WR_IQ(x)	\
+    (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ)
+
+#define S_FW_FILTER_WR_DEL_FILTER	31
+#define M_FW_FILTER_WR_DEL_FILTER	0x1
+#define V_FW_FILTER_WR_DEL_FILTER(x)	((x) << S_FW_FILTER_WR_DEL_FILTER)
+#define G_FW_FILTER_WR_DEL_FILTER(x)	\
+    (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER)
+#define F_FW_FILTER_WR_DEL_FILTER	V_FW_FILTER_WR_DEL_FILTER(1U)
+
+#define S_FW_FILTER_WR_RPTTID		25
+#define M_FW_FILTER_WR_RPTTID		0x1
+#define V_FW_FILTER_WR_RPTTID(x)	((x) << S_FW_FILTER_WR_RPTTID)
+#define G_FW_FILTER_WR_RPTTID(x)	\
+    (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID)
+#define F_FW_FILTER_WR_RPTTID	V_FW_FILTER_WR_RPTTID(1U)
+
+#define S_FW_FILTER_WR_DROP	24
+#define M_FW_FILTER_WR_DROP	0x1
+#define V_FW_FILTER_WR_DROP(x)	((x) << S_FW_FILTER_WR_DROP)
+#define G_FW_FILTER_WR_DROP(x)	\
+    (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP)
+#define F_FW_FILTER_WR_DROP	V_FW_FILTER_WR_DROP(1U)
+
+#define S_FW_FILTER_WR_DIRSTEER		23
+#define M_FW_FILTER_WR_DIRSTEER		0x1
+#define V_FW_FILTER_WR_DIRSTEER(x)	((x) << S_FW_FILTER_WR_DIRSTEER)
+#define G_FW_FILTER_WR_DIRSTEER(x)	\
+    (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER)
+#define F_FW_FILTER_WR_DIRSTEER	V_FW_FILTER_WR_DIRSTEER(1U)
+
+#define S_FW_FILTER_WR_MASKHASH		22
+#define M_FW_FILTER_WR_MASKHASH		0x1
+#define V_FW_FILTER_WR_MASKHASH(x)	((x) << S_FW_FILTER_WR_MASKHASH)
+#define G_FW_FILTER_WR_MASKHASH(x)	\
+    (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH)
+#define F_FW_FILTER_WR_MASKHASH	V_FW_FILTER_WR_MASKHASH(1U)
+
+#define S_FW_FILTER_WR_DIRSTEERHASH	21
+#define M_FW_FILTER_WR_DIRSTEERHASH	0x1
+#define V_FW_FILTER_WR_DIRSTEERHASH(x)	((x) << S_FW_FILTER_WR_DIRSTEERHASH)
+#define G_FW_FILTER_WR_DIRSTEERHASH(x)	\
+    (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH)
+#define F_FW_FILTER_WR_DIRSTEERHASH	V_FW_FILTER_WR_DIRSTEERHASH(1U)
+
+#define S_FW_FILTER_WR_LPBK	20
+#define M_FW_FILTER_WR_LPBK	0x1
+#define V_FW_FILTER_WR_LPBK(x)	((x) << S_FW_FILTER_WR_LPBK)
+#define G_FW_FILTER_WR_LPBK(x)	\
+    (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK)
+#define F_FW_FILTER_WR_LPBK	V_FW_FILTER_WR_LPBK(1U)
+
+#define S_FW_FILTER_WR_DMAC	19
+#define M_FW_FILTER_WR_DMAC	0x1
+#define V_FW_FILTER_WR_DMAC(x)	((x) << S_FW_FILTER_WR_DMAC)
+#define G_FW_FILTER_WR_DMAC(x)	\
+    (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC)
+#define F_FW_FILTER_WR_DMAC	V_FW_FILTER_WR_DMAC(1U)
+
+#define S_FW_FILTER_WR_SMAC	18
+#define M_FW_FILTER_WR_SMAC	0x1
+#define V_FW_FILTER_WR_SMAC(x)	((x) << S_FW_FILTER_WR_SMAC)
+#define G_FW_FILTER_WR_SMAC(x)	\
+    (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC)
+#define F_FW_FILTER_WR_SMAC	V_FW_FILTER_WR_SMAC(1U)
+
+#define S_FW_FILTER_WR_INSVLAN		17
+#define M_FW_FILTER_WR_INSVLAN		0x1
+#define V_FW_FILTER_WR_INSVLAN(x)	((x) << S_FW_FILTER_WR_INSVLAN)
+#define G_FW_FILTER_WR_INSVLAN(x)	\
+    (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN)
+#define F_FW_FILTER_WR_INSVLAN	V_FW_FILTER_WR_INSVLAN(1U)
+
+#define S_FW_FILTER_WR_RMVLAN		16
+#define M_FW_FILTER_WR_RMVLAN		0x1
+#define V_FW_FILTER_WR_RMVLAN(x)	((x) << S_FW_FILTER_WR_RMVLAN)
+#define G_FW_FILTER_WR_RMVLAN(x)	\
+    (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN)
+#define F_FW_FILTER_WR_RMVLAN	V_FW_FILTER_WR_RMVLAN(1U)
+
+#define S_FW_FILTER_WR_HITCNTS		15
+#define M_FW_FILTER_WR_HITCNTS		0x1
+#define V_FW_FILTER_WR_HITCNTS(x)	((x) << S_FW_FILTER_WR_HITCNTS)
+#define G_FW_FILTER_WR_HITCNTS(x)	\
+    (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS)
+#define F_FW_FILTER_WR_HITCNTS	V_FW_FILTER_WR_HITCNTS(1U)
+
+#define S_FW_FILTER_WR_TXCHAN		13
+#define M_FW_FILTER_WR_TXCHAN		0x3
+#define V_FW_FILTER_WR_TXCHAN(x)	((x) << S_FW_FILTER_WR_TXCHAN)
+#define G_FW_FILTER_WR_TXCHAN(x)	\
+    (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN)
+
+#define S_FW_FILTER_WR_PRIO	12
+#define M_FW_FILTER_WR_PRIO	0x1
+#define V_FW_FILTER_WR_PRIO(x)	((x) << S_FW_FILTER_WR_PRIO)
+#define G_FW_FILTER_WR_PRIO(x)	\
+    (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO)
+#define F_FW_FILTER_WR_PRIO	V_FW_FILTER_WR_PRIO(1U)
+
+#define S_FW_FILTER_WR_L2TIX	0
+#define M_FW_FILTER_WR_L2TIX	0xfff
+#define V_FW_FILTER_WR_L2TIX(x)	((x) << S_FW_FILTER_WR_L2TIX)
+#define G_FW_FILTER_WR_L2TIX(x)	\
+    (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX)
+
+#define S_FW_FILTER_WR_FRAG	7
+#define M_FW_FILTER_WR_FRAG	0x1
+#define V_FW_FILTER_WR_FRAG(x)	((x) << S_FW_FILTER_WR_FRAG)
+#define G_FW_FILTER_WR_FRAG(x)	\
+    (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG)
+#define F_FW_FILTER_WR_FRAG	V_FW_FILTER_WR_FRAG(1U)
+
+#define S_FW_FILTER_WR_FRAGM	6
+#define M_FW_FILTER_WR_FRAGM	0x1
+#define V_FW_FILTER_WR_FRAGM(x)	((x) << S_FW_FILTER_WR_FRAGM)
+#define G_FW_FILTER_WR_FRAGM(x)	\
+    (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM)
+#define F_FW_FILTER_WR_FRAGM	V_FW_FILTER_WR_FRAGM(1U)
+
+#define S_FW_FILTER_WR_IVLAN_VLD	5
+#define M_FW_FILTER_WR_IVLAN_VLD	0x1
+#define V_FW_FILTER_WR_IVLAN_VLD(x)	((x) << S_FW_FILTER_WR_IVLAN_VLD)
+#define G_FW_FILTER_WR_IVLAN_VLD(x)	\
+    (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD)
+#define F_FW_FILTER_WR_IVLAN_VLD	V_FW_FILTER_WR_IVLAN_VLD(1U)
+
+#define S_FW_FILTER_WR_OVLAN_VLD	4
+#define M_FW_FILTER_WR_OVLAN_VLD	0x1
+#define V_FW_FILTER_WR_OVLAN_VLD(x)	((x) << S_FW_FILTER_WR_OVLAN_VLD)
+#define G_FW_FILTER_WR_OVLAN_VLD(x)	\
+    (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD)
+#define F_FW_FILTER_WR_OVLAN_VLD	V_FW_FILTER_WR_OVLAN_VLD(1U)
+
+#define S_FW_FILTER_WR_IVLAN_VLDM	3
+#define M_FW_FILTER_WR_IVLAN_VLDM	0x1
+#define V_FW_FILTER_WR_IVLAN_VLDM(x)	((x) << S_FW_FILTER_WR_IVLAN_VLDM)
+#define G_FW_FILTER_WR_IVLAN_VLDM(x)	\
+    (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM)
+#define F_FW_FILTER_WR_IVLAN_VLDM	V_FW_FILTER_WR_IVLAN_VLDM(1U)
+
+#define S_FW_FILTER_WR_OVLAN_VLDM	2
+#define M_FW_FILTER_WR_OVLAN_VLDM	0x1
+#define V_FW_FILTER_WR_OVLAN_VLDM(x)	((x) << S_FW_FILTER_WR_OVLAN_VLDM)
+#define G_FW_FILTER_WR_OVLAN_VLDM(x)	\
+    (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM)
+#define F_FW_FILTER_WR_OVLAN_VLDM	V_FW_FILTER_WR_OVLAN_VLDM(1U)
+
+#define S_FW_FILTER_WR_RX_CHAN		15
+#define M_FW_FILTER_WR_RX_CHAN		0x1
+#define V_FW_FILTER_WR_RX_CHAN(x)	((x) << S_FW_FILTER_WR_RX_CHAN)
+#define G_FW_FILTER_WR_RX_CHAN(x)	\
+    (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN)
+#define F_FW_FILTER_WR_RX_CHAN	V_FW_FILTER_WR_RX_CHAN(1U)
+
+#define S_FW_FILTER_WR_RX_RPL_IQ	0
+#define M_FW_FILTER_WR_RX_RPL_IQ	0x3ff
+#define V_FW_FILTER_WR_RX_RPL_IQ(x)	((x) << S_FW_FILTER_WR_RX_RPL_IQ)
+#define G_FW_FILTER_WR_RX_RPL_IQ(x)	\
+    (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ)
+
+#define S_FW_FILTER_WR_MACI	23
+#define M_FW_FILTER_WR_MACI	0x1ff
+#define V_FW_FILTER_WR_MACI(x)	((x) << S_FW_FILTER_WR_MACI)
+#define G_FW_FILTER_WR_MACI(x)	\
+    (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI)
+
+#define S_FW_FILTER_WR_MACIM	14
+#define M_FW_FILTER_WR_MACIM	0x1ff
+#define V_FW_FILTER_WR_MACIM(x)	((x) << S_FW_FILTER_WR_MACIM)
+#define G_FW_FILTER_WR_MACIM(x)	\
+    (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM)
+
+#define S_FW_FILTER_WR_FCOE	13
+#define M_FW_FILTER_WR_FCOE	0x1
+#define V_FW_FILTER_WR_FCOE(x)	((x) << S_FW_FILTER_WR_FCOE)
+#define G_FW_FILTER_WR_FCOE(x)	\
+    (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE)
+#define F_FW_FILTER_WR_FCOE	V_FW_FILTER_WR_FCOE(1U)
+
+#define S_FW_FILTER_WR_FCOEM	12
+#define M_FW_FILTER_WR_FCOEM	0x1
+#define V_FW_FILTER_WR_FCOEM(x)	((x) << S_FW_FILTER_WR_FCOEM)
+#define G_FW_FILTER_WR_FCOEM(x)	\
+    (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM)
+#define F_FW_FILTER_WR_FCOEM	V_FW_FILTER_WR_FCOEM(1U)
+
+#define S_FW_FILTER_WR_PORT	9
+#define M_FW_FILTER_WR_PORT	0x7
+#define V_FW_FILTER_WR_PORT(x)	((x) << S_FW_FILTER_WR_PORT)
+#define G_FW_FILTER_WR_PORT(x)	\
+    (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT)
+
+#define S_FW_FILTER_WR_PORTM	6
+#define M_FW_FILTER_WR_PORTM	0x7
+#define V_FW_FILTER_WR_PORTM(x)	((x) << S_FW_FILTER_WR_PORTM)
+#define G_FW_FILTER_WR_PORTM(x)	\
+    (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM)
+
+#define S_FW_FILTER_WR_MATCHTYPE	3
+#define M_FW_FILTER_WR_MATCHTYPE	0x7
+#define V_FW_FILTER_WR_MATCHTYPE(x)	((x) << S_FW_FILTER_WR_MATCHTYPE)
+#define G_FW_FILTER_WR_MATCHTYPE(x)	\
+    (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE)
+
+#define S_FW_FILTER_WR_MATCHTYPEM	0
+#define M_FW_FILTER_WR_MATCHTYPEM	0x7
+#define V_FW_FILTER_WR_MATCHTYPEM(x)	((x) << S_FW_FILTER_WR_MATCHTYPEM)
+#define G_FW_FILTER_WR_MATCHTYPEM(x)	\
+    (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM)
+
+struct fw_ulptx_wr {
+	__be32 op_to_compl;
+	__be32 flowid_len16;
+	__u64  cookie;
+};
+
+struct fw_tp_wr {
+	__be32 op_to_immdlen;
+	__be32 flowid_len16;
+	__u64  cookie;
+};
+
+struct fw_eth_tx_pkt_wr {
+	__be32 op_immdlen;
+	__be32 equiq_to_len16;
+	__be64 r3;
+};
+
+#define S_FW_ETH_TX_PKT_WR_IMMDLEN	0
+#define M_FW_ETH_TX_PKT_WR_IMMDLEN	0x1ff
+#define V_FW_ETH_TX_PKT_WR_IMMDLEN(x)	((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
+#define G_FW_ETH_TX_PKT_WR_IMMDLEN(x)	\
+    (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
+
+struct fw_eth_tx_pkt2_wr {
+	__be32 op_immdlen;
+	__be32 equiq_to_len16;
+	__be32 r3;
+	__be32 L4ChkDisable_to_IpHdrLen;
+};
+
+#define S_FW_ETH_TX_PKT2_WR_IMMDLEN	0
+#define M_FW_ETH_TX_PKT2_WR_IMMDLEN	0x1ff
+#define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x)	((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN)
+#define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x)	\
+    (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN)
+
+#define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE	31
+#define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE	0x1
+#define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x)	\
+    ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
+#define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x)	\
+    (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \
+     M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
+#define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE	\
+    V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U)
+
+#define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE	30
+#define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE	0x1
+#define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x)	\
+    ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
+#define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x)	\
+    (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \
+     M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
+#define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE	\
+    V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U)
+
+#define S_FW_ETH_TX_PKT2_WR_IVLAN	28
+#define M_FW_ETH_TX_PKT2_WR_IVLAN	0x1
+#define V_FW_ETH_TX_PKT2_WR_IVLAN(x)	((x) << S_FW_ETH_TX_PKT2_WR_IVLAN)
+#define G_FW_ETH_TX_PKT2_WR_IVLAN(x)	\
+    (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN)
+#define F_FW_ETH_TX_PKT2_WR_IVLAN	V_FW_ETH_TX_PKT2_WR_IVLAN(1U)
+
+#define S_FW_ETH_TX_PKT2_WR_IVLANTAG	12
+#define M_FW_ETH_TX_PKT2_WR_IVLANTAG	0xffff
+#define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x)	((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG)
+#define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x)	\
+    (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG)
+
+#define S_FW_ETH_TX_PKT2_WR_CHKTYPE	8
+#define M_FW_ETH_TX_PKT2_WR_CHKTYPE	0xf
+#define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x)	((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE)
+#define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x)	\
+    (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE)
+
+#define S_FW_ETH_TX_PKT2_WR_IPHDRLEN	0
+#define M_FW_ETH_TX_PKT2_WR_IPHDRLEN	0xff
+#define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x)	((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN)
+#define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x)	\
+    (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN)
+
+struct fw_eth_tx_pkts_wr {
+	__be32 op_pkd;
+	__be32 equiq_to_len16;
+	__be32 r3;
+	__be16 plen;
+	__u8   npkt;
+	__u8   type;
+};
+
+struct fw_eth_tx_uo_wr {
+	__be32 op_immdlen;
+	__be32 equiq_to_len16;
+	__be64 r3;
+	__u8   r4;
+	__u8   ethlen;
+	__be16 iplen;
+	__u8   udplen;
+	__u8   rtplen;
+	__be16 r5;
+	__be16 mss;
+	__be16 schedpktsize;
+	__be32 length;
+};
+
+struct fw_eq_flush_wr {
+	__u8   opcode;
+	__u8   r1[3];
+	__be32 equiq_to_len16;
+	__be64 r3;
+};
+
+struct fw_ofld_connection_wr {
+	__be32 op_compl;
+	__be32 len16_pkd;
+	__u64  cookie;
+	__be64 r2;
+	__be64 r3;
+	struct fw_ofld_connection_le {
+		__be32 version_cpl;
+		__be32 filter;
+		__be32 r1;
+		__be16 lport;
+		__be16 pport;
+		union fw_ofld_connection_leip {
+			struct fw_ofld_connection_le_ipv4 {
+				__be32 pip;
+				__be32 lip;
+				__be64 r0;
+				__be64 r1;
+				__be64 r2;
+			} ipv4;
+			struct fw_ofld_connection_le_ipv6 {
+				__be64 pip_hi;
+				__be64 pip_lo;
+				__be64 lip_hi;
+				__be64 lip_lo;
+			} ipv6;
+		} u;
+	} le;
+	struct fw_ofld_connection_tcb {
+		__be32 t_state_to_astid;
+		__be16 cplrxdataack_cplpassacceptrpl;
+		__be16 rcv_adv;
+		__be32 rcv_nxt;
+		__be32 tx_max;
+		__be64 opt0;
+		__be32 opt2;
+		__be32 r1;
+		__be64 r2;
+		__be64 r3;
+	} tcb;
+};
+
+#define S_FW_OFLD_CONNECTION_WR_VERSION		31
+#define M_FW_OFLD_CONNECTION_WR_VERSION		0x1
+#define V_FW_OFLD_CONNECTION_WR_VERSION(x)	\
+    ((x) << S_FW_OFLD_CONNECTION_WR_VERSION)
+#define G_FW_OFLD_CONNECTION_WR_VERSION(x)	\
+    (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \
+     M_FW_OFLD_CONNECTION_WR_VERSION)
+#define F_FW_OFLD_CONNECTION_WR_VERSION	V_FW_OFLD_CONNECTION_WR_VERSION(1U)
+
+#define S_FW_OFLD_CONNECTION_WR_CPL	30
+#define M_FW_OFLD_CONNECTION_WR_CPL	0x1
+#define V_FW_OFLD_CONNECTION_WR_CPL(x)	((x) << S_FW_OFLD_CONNECTION_WR_CPL)
+#define G_FW_OFLD_CONNECTION_WR_CPL(x)	\
+    (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL)
+#define F_FW_OFLD_CONNECTION_WR_CPL	V_FW_OFLD_CONNECTION_WR_CPL(1U)
+
+#define S_FW_OFLD_CONNECTION_WR_T_STATE		28
+#define M_FW_OFLD_CONNECTION_WR_T_STATE		0xf
+#define V_FW_OFLD_CONNECTION_WR_T_STATE(x)	\
+    ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE)
+#define G_FW_OFLD_CONNECTION_WR_T_STATE(x)	\
+    (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \
+     M_FW_OFLD_CONNECTION_WR_T_STATE)
+
+#define S_FW_OFLD_CONNECTION_WR_RCV_SCALE	24
+#define M_FW_OFLD_CONNECTION_WR_RCV_SCALE	0xf
+#define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x)	\
+    ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE)
+#define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x)	\
+    (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \
+     M_FW_OFLD_CONNECTION_WR_RCV_SCALE)
+
+#define S_FW_OFLD_CONNECTION_WR_ASTID		0
+#define M_FW_OFLD_CONNECTION_WR_ASTID		0xffffff
+#define V_FW_OFLD_CONNECTION_WR_ASTID(x)	\
+    ((x) << S_FW_OFLD_CONNECTION_WR_ASTID)
+#define G_FW_OFLD_CONNECTION_WR_ASTID(x)	\
+    (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID)
+
+#define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK	15
+#define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK	0x1
+#define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x)	\
+    ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
+#define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x)	\
+    (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \
+     M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
+#define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK	\
+    V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U)
+
+#define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL	14
+#define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL	0x1
+#define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x)	\
+    ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
+#define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x)	\
+    (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \
+     M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
+#define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL	\
+    V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U)
+
+enum fw_flowc_mnem_tcpstate {
+	FW_FLOWC_MNEM_TCPSTATE_CLOSED	= 0, /* illegal */
+	FW_FLOWC_MNEM_TCPSTATE_LISTEN	= 1, /* illegal */
+	FW_FLOWC_MNEM_TCPSTATE_SYNSENT	= 2, /* illegal */
+	FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */
+	FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */
+	FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */
+	FW_FLOWC_MNEM_TCPSTATE_FINWAIT1	= 6, /* haven't gotten ACK for FIN and
+					      * will resend FIN - equiv ESTAB
+					      */
+	FW_FLOWC_MNEM_TCPSTATE_CLOSING	= 7, /* haven't gotten ACK for FIN and
+					      * will resend FIN but have
+					      * received FIN
+					      */
+	FW_FLOWC_MNEM_TCPSTATE_LASTACK	= 8, /* haven't gotten ACK for FIN and
+					      * will resend FIN but have
+					      * received FIN
+					      */
+	FW_FLOWC_MNEM_TCPSTATE_FINWAIT2	= 9, /* sent FIN and got FIN + ACK,
+					      * waiting for FIN
+					      */
+	FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT	= 10, /* not expected */
+};
+
+enum fw_flowc_mnem_uostate {
+	FW_FLOWC_MNEM_UOSTATE_CLOSED	= 0, /* illegal */
+	FW_FLOWC_MNEM_UOSTATE_ESTABLISHED = 1, /* default */
+	FW_FLOWC_MNEM_UOSTATE_CLOSING	= 2, /* graceful close, after sending
+					      * outstanding payload
+					      */
+	FW_FLOWC_MNEM_UOSTATE_ABORTING	= 3, /* immediate close, after
+					      * discarding outstanding payload
+					      */
+};
+
+enum fw_flowc_mnem {
+	FW_FLOWC_MNEM_PFNVFN		= 0, /* PFN [15:8] VFN [7:0] */
+	FW_FLOWC_MNEM_CH		= 1,
+	FW_FLOWC_MNEM_PORT		= 2,
+	FW_FLOWC_MNEM_IQID		= 3,
+	FW_FLOWC_MNEM_SNDNXT		= 4,
+	FW_FLOWC_MNEM_RCVNXT		= 5,
+	FW_FLOWC_MNEM_SNDBUF		= 6,
+	FW_FLOWC_MNEM_MSS		= 7,
+	FW_FLOWC_MNEM_TXDATAPLEN_MAX	= 8,
+	FW_FLOWC_MNEM_TCPSTATE		= 9,
+	FW_FLOWC_MNEM_UOSTATE		= 10,
+	FW_FLOWC_MNEM_SCHEDCLASS	= 11,
+	FW_FLOWC_MNEM_DCBPRIO		= 12,
+};
+
+struct fw_flowc_mnemval {
+	__u8   mnemonic;
+	__u8   r4[3];
+	__be32 val;
+};
+
+struct fw_flowc_wr {
+	__be32 op_to_nparams;
+	__be32 flowid_len16;
+#ifndef C99_NOT_SUPPORTED
+	struct fw_flowc_mnemval mnemval[0];
+#endif
+};
+
+#define S_FW_FLOWC_WR_NPARAMS		0
+#define M_FW_FLOWC_WR_NPARAMS		0xff
+#define V_FW_FLOWC_WR_NPARAMS(x)	((x) << S_FW_FLOWC_WR_NPARAMS)
+#define G_FW_FLOWC_WR_NPARAMS(x)	\
+    (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS)
+
+struct fw_ofld_tx_data_wr {
+	__be32 op_to_immdlen;
+	__be32 flowid_len16;
+	__be32 plen;
+	__be32 lsodisable_to_proxy;
+};
+
+#define S_FW_OFLD_TX_DATA_WR_LSODISABLE		31
+#define M_FW_OFLD_TX_DATA_WR_LSODISABLE		0x1
+#define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x)	\
+    ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE)
+#define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x)	\
+    (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \
+     M_FW_OFLD_TX_DATA_WR_LSODISABLE)
+#define F_FW_OFLD_TX_DATA_WR_LSODISABLE	V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U)
+
+#define S_FW_OFLD_TX_DATA_WR_ALIGNPLD		30
+#define M_FW_OFLD_TX_DATA_WR_ALIGNPLD		0x1
+#define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x)	\
+    ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD)
+#define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x)	\
+    (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD)
+#define F_FW_OFLD_TX_DATA_WR_ALIGNPLD	V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U)
+
+#define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE	29
+#define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE	0x1
+#define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x)	\
+    ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)
+#define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x)	\
+    (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \
+     M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)
+#define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE	\
+    V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U)
+
+#define S_FW_OFLD_TX_DATA_WR_TUNNEL	19
+#define M_FW_OFLD_TX_DATA_WR_TUNNEL	0x1
+#define V_FW_OFLD_TX_DATA_WR_TUNNEL(x)	((x) << S_FW_OFLD_TX_DATA_WR_TUNNEL)
+#define G_FW_OFLD_TX_DATA_WR_TUNNEL(x)	\
+    (((x) >> S_FW_OFLD_TX_DATA_WR_TUNNEL) & M_FW_OFLD_TX_DATA_WR_TUNNEL)
+#define F_FW_OFLD_TX_DATA_WR_TUNNEL	V_FW_OFLD_TX_DATA_WR_TUNNEL(1U)
+
+#define S_FW_OFLD_TX_DATA_WR_SAVE	18
+#define M_FW_OFLD_TX_DATA_WR_SAVE	0x1
+#define V_FW_OFLD_TX_DATA_WR_SAVE(x)	((x) << S_FW_OFLD_TX_DATA_WR_SAVE)
+#define G_FW_OFLD_TX_DATA_WR_SAVE(x)	\
+    (((x) >> S_FW_OFLD_TX_DATA_WR_SAVE) & M_FW_OFLD_TX_DATA_WR_SAVE)
+#define F_FW_OFLD_TX_DATA_WR_SAVE	V_FW_OFLD_TX_DATA_WR_SAVE(1U)
+
+#define S_FW_OFLD_TX_DATA_WR_FLUSH	17
+#define M_FW_OFLD_TX_DATA_WR_FLUSH	0x1
+#define V_FW_OFLD_TX_DATA_WR_FLUSH(x)	((x) << S_FW_OFLD_TX_DATA_WR_FLUSH)
+#define G_FW_OFLD_TX_DATA_WR_FLUSH(x)	\
+    (((x) >> S_FW_OFLD_TX_DATA_WR_FLUSH) & M_FW_OFLD_TX_DATA_WR_FLUSH)
+#define F_FW_OFLD_TX_DATA_WR_FLUSH	V_FW_OFLD_TX_DATA_WR_FLUSH(1U)
+
+#define S_FW_OFLD_TX_DATA_WR_URGENT	16
+#define M_FW_OFLD_TX_DATA_WR_URGENT	0x1
+#define V_FW_OFLD_TX_DATA_WR_URGENT(x)	((x) << S_FW_OFLD_TX_DATA_WR_URGENT)
+#define G_FW_OFLD_TX_DATA_WR_URGENT(x)	\
+    (((x) >> S_FW_OFLD_TX_DATA_WR_URGENT) & M_FW_OFLD_TX_DATA_WR_URGENT)
+#define F_FW_OFLD_TX_DATA_WR_URGENT	V_FW_OFLD_TX_DATA_WR_URGENT(1U)
+
+#define S_FW_OFLD_TX_DATA_WR_MORE	15
+#define M_FW_OFLD_TX_DATA_WR_MORE	0x1
+#define V_FW_OFLD_TX_DATA_WR_MORE(x)	((x) << S_FW_OFLD_TX_DATA_WR_MORE)
+#define G_FW_OFLD_TX_DATA_WR_MORE(x)	\
+    (((x) >> S_FW_OFLD_TX_DATA_WR_MORE) & M_FW_OFLD_TX_DATA_WR_MORE)
+#define F_FW_OFLD_TX_DATA_WR_MORE	V_FW_OFLD_TX_DATA_WR_MORE(1U)
+
+#define S_FW_OFLD_TX_DATA_WR_SHOVE	14
+#define M_FW_OFLD_TX_DATA_WR_SHOVE	0x1
+#define V_FW_OFLD_TX_DATA_WR_SHOVE(x)	((x) << S_FW_OFLD_TX_DATA_WR_SHOVE)
+#define G_FW_OFLD_TX_DATA_WR_SHOVE(x)	\
+    (((x) >> S_FW_OFLD_TX_DATA_WR_SHOVE) & M_FW_OFLD_TX_DATA_WR_SHOVE)
+#define F_FW_OFLD_TX_DATA_WR_SHOVE	V_FW_OFLD_TX_DATA_WR_SHOVE(1U)
+
+#define S_FW_OFLD_TX_DATA_WR_ULPMODE	10
+#define M_FW_OFLD_TX_DATA_WR_ULPMODE	0xf
+#define V_FW_OFLD_TX_DATA_WR_ULPMODE(x)	((x) << S_FW_OFLD_TX_DATA_WR_ULPMODE)
+#define G_FW_OFLD_TX_DATA_WR_ULPMODE(x)	\
+    (((x) >> S_FW_OFLD_TX_DATA_WR_ULPMODE) & M_FW_OFLD_TX_DATA_WR_ULPMODE)
+
+#define S_FW_OFLD_TX_DATA_WR_ULPSUBMODE		6
+#define M_FW_OFLD_TX_DATA_WR_ULPSUBMODE		0xf
+#define V_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x)	\
+    ((x) << S_FW_OFLD_TX_DATA_WR_ULPSUBMODE)
+#define G_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x)	\
+    (((x) >> S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) & \
+     M_FW_OFLD_TX_DATA_WR_ULPSUBMODE)
+
+#define S_FW_OFLD_TX_DATA_WR_PROXY	5
+#define M_FW_OFLD_TX_DATA_WR_PROXY	0x1
+#define V_FW_OFLD_TX_DATA_WR_PROXY(x)	((x) << S_FW_OFLD_TX_DATA_WR_PROXY)
+#define G_FW_OFLD_TX_DATA_WR_PROXY(x)	\
+    (((x) >> S_FW_OFLD_TX_DATA_WR_PROXY) & M_FW_OFLD_TX_DATA_WR_PROXY)
+#define F_FW_OFLD_TX_DATA_WR_PROXY	V_FW_OFLD_TX_DATA_WR_PROXY(1U)
+
+struct fw_cmd_wr {
+	__be32 op_dma;
+	__be32 len16_pkd;
+	__be64 cookie_daddr;
+};
+
+#define S_FW_CMD_WR_DMA		17
+#define M_FW_CMD_WR_DMA		0x1
+#define V_FW_CMD_WR_DMA(x)	((x) << S_FW_CMD_WR_DMA)
+#define G_FW_CMD_WR_DMA(x)	(((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA)
+#define F_FW_CMD_WR_DMA	V_FW_CMD_WR_DMA(1U)
+
+struct fw_eth_tx_pkt_vm_wr {
+	__be32 op_immdlen;
+	__be32 equiq_to_len16;
+	__be32 r3[2];
+	__u8   ethmacdst[6];
+	__u8   ethmacsrc[6];
+	__be16 ethtype;
+	__be16 vlantci;
+};
+
+/******************************************************************************
+ *   R I   W O R K   R E Q U E S T s
+ **************************************/
+
+enum fw_ri_wr_opcode {
+	FW_RI_RDMA_WRITE		= 0x0,	/* IETF RDMAP v1.0 ... */
+	FW_RI_READ_REQ			= 0x1,
+	FW_RI_READ_RESP			= 0x2,
+	FW_RI_SEND			= 0x3,
+	FW_RI_SEND_WITH_INV		= 0x4,
+	FW_RI_SEND_WITH_SE		= 0x5,
+	FW_RI_SEND_WITH_SE_INV		= 0x6,
+	FW_RI_TERMINATE			= 0x7,
+	FW_RI_RDMA_INIT			= 0x8,	/* CHELSIO RI specific ... */
+	FW_RI_BIND_MW			= 0x9,
+	FW_RI_FAST_REGISTER		= 0xa,
+	FW_RI_LOCAL_INV			= 0xb,
+	FW_RI_QP_MODIFY			= 0xc,
+	FW_RI_BYPASS			= 0xd,
+	FW_RI_RECEIVE			= 0xe,
+#if 0
+	FW_RI_SEND_IMMEDIATE		= 0x8,
+	FW_RI_SEND_IMMEDIATE_WITH_SE	= 0x9,
+	FW_RI_ATOMIC_REQUEST		= 0xa,
+	FW_RI_ATOMIC_RESPONSE		= 0xb,
+
+	FW_RI_BIND_MW			= 0xc, /* CHELSIO RI specific ... */
+	FW_RI_FAST_REGISTER		= 0xd,
+	FW_RI_LOCAL_INV			= 0xe,
+#endif
+	FW_RI_SGE_EC_CR_RETURN		= 0xf
+};
+
+enum fw_ri_wr_flags {
+	FW_RI_COMPLETION_FLAG		= 0x01,
+	FW_RI_NOTIFICATION_FLAG		= 0x02,
+	FW_RI_SOLICITED_EVENT_FLAG	= 0x04,
+	FW_RI_READ_FENCE_FLAG		= 0x08,
+	FW_RI_LOCAL_FENCE_FLAG		= 0x10,
+	FW_RI_RDMA_READ_INVALIDATE	= 0x20
+};
+
+enum fw_ri_mpa_attrs {
+	FW_RI_MPA_RX_MARKER_ENABLE	= 0x01,
+	FW_RI_MPA_TX_MARKER_ENABLE	= 0x02,
+	FW_RI_MPA_CRC_ENABLE		= 0x04,
+	FW_RI_MPA_IETF_ENABLE		= 0x08
+};
+
+enum fw_ri_qp_caps {
+	FW_RI_QP_RDMA_READ_ENABLE	= 0x01,
+	FW_RI_QP_RDMA_WRITE_ENABLE	= 0x02,
+	FW_RI_QP_BIND_ENABLE		= 0x04,
+	FW_RI_QP_FAST_REGISTER_ENABLE	= 0x08,
+	FW_RI_QP_STAG0_ENABLE		= 0x10,
+	FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80,
+};
+
+enum fw_ri_addr_type {
+	FW_RI_ZERO_BASED_TO		= 0x00,
+	FW_RI_VA_BASED_TO		= 0x01
+};
+
+enum fw_ri_mem_perms {
+	FW_RI_MEM_ACCESS_REM_WRITE	= 0x01,
+	FW_RI_MEM_ACCESS_REM_READ	= 0x02,
+	FW_RI_MEM_ACCESS_REM		= 0x03,
+	FW_RI_MEM_ACCESS_LOCAL_WRITE	= 0x04,
+	FW_RI_MEM_ACCESS_LOCAL_READ	= 0x08,
+	FW_RI_MEM_ACCESS_LOCAL		= 0x0C
+};
+
+enum fw_ri_stag_type {
+	FW_RI_STAG_NSMR			= 0x00,
+	FW_RI_STAG_SMR			= 0x01,
+	FW_RI_STAG_MW			= 0x02,
+	FW_RI_STAG_MW_RELAXED		= 0x03
+};
+
+enum fw_ri_data_op {
+	FW_RI_DATA_IMMD			= 0x81,
+	FW_RI_DATA_DSGL			= 0x82,
+	FW_RI_DATA_ISGL			= 0x83
+};
+
+enum fw_ri_sgl_depth {
+	FW_RI_SGL_DEPTH_MAX_SQ		= 16,
+	FW_RI_SGL_DEPTH_MAX_RQ		= 4
+};
+
+enum fw_ri_cqe_err {
+	FW_RI_CQE_ERR_SUCCESS		= 0x00,	/* success, no error detected */
+	FW_RI_CQE_ERR_STAG		= 0x01, /* STAG invalid */
+	FW_RI_CQE_ERR_PDID		= 0x02, /* PDID mismatch */
+	FW_RI_CQE_ERR_QPID		= 0x03, /* QPID mismatch */
+	FW_RI_CQE_ERR_ACCESS		= 0x04, /* Invalid access right */
+	FW_RI_CQE_ERR_WRAP		= 0x05, /* Wrap error */
+	FW_RI_CQE_ERR_BOUND		= 0x06, /* base and bounds violation */
+	FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */
+	FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */
+	FW_RI_CQE_ERR_ECC		= 0x09,	/* ECC error detected */
+	FW_RI_CQE_ERR_ECC_PSTAG		= 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */
+	FW_RI_CQE_ERR_PBL_ADDR_BOUND	= 0x0B, /* pbl address out of bound : software error */
+	FW_RI_CQE_ERR_CRC		= 0x10,	/* CRC error */
+	FW_RI_CQE_ERR_MARKER		= 0x11,	/* Marker error */
+	FW_RI_CQE_ERR_PDU_LEN_ERR	= 0x12,	/* invalid PDU length */
+	FW_RI_CQE_ERR_OUT_OF_RQE	= 0x13,	/* out of RQE */
+	FW_RI_CQE_ERR_DDP_VERSION	= 0x14,	/* wrong DDP version */
+	FW_RI_CQE_ERR_RDMA_VERSION	= 0x15,	/* wrong RDMA version */
+	FW_RI_CQE_ERR_OPCODE		= 0x16,	/* invalid rdma opcode */
+	FW_RI_CQE_ERR_DDP_QUEUE_NUM	= 0x17,	/* invalid ddp queue number */
+	FW_RI_CQE_ERR_MSN		= 0x18, /* MSN error */
+	FW_RI_CQE_ERR_TBIT		= 0x19, /* tag bit not set correctly */
+	FW_RI_CQE_ERR_MO		= 0x1A, /* MO not zero for TERMINATE or READ_REQ */
+	FW_RI_CQE_ERR_MSN_GAP		= 0x1B, /* */
+	FW_RI_CQE_ERR_MSN_RANGE		= 0x1C, /* */
+	FW_RI_CQE_ERR_IRD_OVERFLOW	= 0x1D, /* */
+	FW_RI_CQE_ERR_RQE_ADDR_BOUND	= 0x1E, /*  RQE address out of bound : software error */
+	FW_RI_CQE_ERR_INTERNAL_ERR	= 0x1F  /* internel error (opcode mismatch) */
+
+};
+
+struct fw_ri_dsge_pair {
+	__be32	len[2];
+	__be64	addr[2];
+};
+
+struct fw_ri_dsgl {
+	__u8	op;
+	__u8	r1;
+	__be16	nsge;
+	__be32	len0;
+	__be64	addr0;
+#ifndef C99_NOT_SUPPORTED
+	struct fw_ri_dsge_pair sge[0];
+#endif
+};
+
+struct fw_ri_sge {
+	__be32 stag;
+	__be32 len;
+	__be64 to;
+};
+
+struct fw_ri_isgl {
+	__u8	op;
+	__u8	r1;
+	__be16	nsge;
+	__be32	r2;
+#ifndef C99_NOT_SUPPORTED
+	struct fw_ri_sge sge[0];
+#endif
+};
+
+struct fw_ri_immd {
+	__u8	op;
+	__u8	r1;
+	__be16	r2;
+	__be32	immdlen;
+#ifndef C99_NOT_SUPPORTED
+	__u8	data[0];
+#endif
+};
+
+struct fw_ri_tpte {
+	__be32 valid_to_pdid;
+	__be32 locread_to_qpid;
+	__be32 nosnoop_pbladdr;
+	__be32 len_lo;
+	__be32 va_hi;
+	__be32 va_lo_fbo;
+	__be32 dca_mwbcnt_pstag;
+	__be32 len_hi;
+};
+
+#define S_FW_RI_TPTE_VALID		31
+#define M_FW_RI_TPTE_VALID		0x1
+#define V_FW_RI_TPTE_VALID(x)		((x) << S_FW_RI_TPTE_VALID)
+#define G_FW_RI_TPTE_VALID(x)		\
+    (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID)
+#define F_FW_RI_TPTE_VALID		V_FW_RI_TPTE_VALID(1U)
+
+#define S_FW_RI_TPTE_STAGKEY		23
+#define M_FW_RI_TPTE_STAGKEY		0xff
+#define V_FW_RI_TPTE_STAGKEY(x)		((x) << S_FW_RI_TPTE_STAGKEY)
+#define G_FW_RI_TPTE_STAGKEY(x)		\
+    (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY)
+
+#define S_FW_RI_TPTE_STAGSTATE		22
+#define M_FW_RI_TPTE_STAGSTATE		0x1
+#define V_FW_RI_TPTE_STAGSTATE(x)	((x) << S_FW_RI_TPTE_STAGSTATE)
+#define G_FW_RI_TPTE_STAGSTATE(x)	\
+    (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE)
+#define F_FW_RI_TPTE_STAGSTATE		V_FW_RI_TPTE_STAGSTATE(1U)
+
+#define S_FW_RI_TPTE_STAGTYPE		20
+#define M_FW_RI_TPTE_STAGTYPE		0x3
+#define V_FW_RI_TPTE_STAGTYPE(x)	((x) << S_FW_RI_TPTE_STAGTYPE)
+#define G_FW_RI_TPTE_STAGTYPE(x)	\
+    (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE)
+
+#define S_FW_RI_TPTE_PDID		0
+#define M_FW_RI_TPTE_PDID		0xfffff
+#define V_FW_RI_TPTE_PDID(x)		((x) << S_FW_RI_TPTE_PDID)
+#define G_FW_RI_TPTE_PDID(x)		\
+    (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID)
+
+#define S_FW_RI_TPTE_PERM		28
+#define M_FW_RI_TPTE_PERM		0xf
+#define V_FW_RI_TPTE_PERM(x)		((x) << S_FW_RI_TPTE_PERM)
+#define G_FW_RI_TPTE_PERM(x)		\
+    (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM)
+
+#define S_FW_RI_TPTE_REMINVDIS		27
+#define M_FW_RI_TPTE_REMINVDIS		0x1
+#define V_FW_RI_TPTE_REMINVDIS(x)	((x) << S_FW_RI_TPTE_REMINVDIS)
+#define G_FW_RI_TPTE_REMINVDIS(x)	\
+    (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS)
+#define F_FW_RI_TPTE_REMINVDIS		V_FW_RI_TPTE_REMINVDIS(1U)
+
+#define S_FW_RI_TPTE_ADDRTYPE		26
+#define M_FW_RI_TPTE_ADDRTYPE		1
+#define V_FW_RI_TPTE_ADDRTYPE(x)	((x) << S_FW_RI_TPTE_ADDRTYPE)
+#define G_FW_RI_TPTE_ADDRTYPE(x)	\
+    (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE)
+#define F_FW_RI_TPTE_ADDRTYPE		V_FW_RI_TPTE_ADDRTYPE(1U)
+
+#define S_FW_RI_TPTE_MWBINDEN		25
+#define M_FW_RI_TPTE_MWBINDEN		0x1
+#define V_FW_RI_TPTE_MWBINDEN(x)	((x) << S_FW_RI_TPTE_MWBINDEN)
+#define G_FW_RI_TPTE_MWBINDEN(x)	\
+    (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN)
+#define F_FW_RI_TPTE_MWBINDEN		V_FW_RI_TPTE_MWBINDEN(1U)
+
+#define S_FW_RI_TPTE_PS			20
+#define M_FW_RI_TPTE_PS			0x1f
+#define V_FW_RI_TPTE_PS(x)		((x) << S_FW_RI_TPTE_PS)
+#define G_FW_RI_TPTE_PS(x)		\
+    (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS)
+
+#define S_FW_RI_TPTE_QPID		0
+#define M_FW_RI_TPTE_QPID		0xfffff
+#define V_FW_RI_TPTE_QPID(x)		((x) << S_FW_RI_TPTE_QPID)
+#define G_FW_RI_TPTE_QPID(x)		\
+    (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID)
+
+#define S_FW_RI_TPTE_NOSNOOP		31
+#define M_FW_RI_TPTE_NOSNOOP		0x1
+#define V_FW_RI_TPTE_NOSNOOP(x)		((x) << S_FW_RI_TPTE_NOSNOOP)
+#define G_FW_RI_TPTE_NOSNOOP(x)		\
+    (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP)
+#define F_FW_RI_TPTE_NOSNOOP		V_FW_RI_TPTE_NOSNOOP(1U)
+
+#define S_FW_RI_TPTE_PBLADDR		0
+#define M_FW_RI_TPTE_PBLADDR		0x1fffffff
+#define V_FW_RI_TPTE_PBLADDR(x)		((x) << S_FW_RI_TPTE_PBLADDR)
+#define G_FW_RI_TPTE_PBLADDR(x)		\
+    (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR)
+
+#define S_FW_RI_TPTE_DCA		24
+#define M_FW_RI_TPTE_DCA		0x1f
+#define V_FW_RI_TPTE_DCA(x)		((x) << S_FW_RI_TPTE_DCA)
+#define G_FW_RI_TPTE_DCA(x)		\
+    (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA)
+
+#define S_FW_RI_TPTE_MWBCNT_PSTAG	0
+#define M_FW_RI_TPTE_MWBCNT_PSTAG	0xffffff
+#define V_FW_RI_TPTE_MWBCNT_PSTAT(x)	\
+    ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG)
+#define G_FW_RI_TPTE_MWBCNT_PSTAG(x)	\
+    (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG)
+
+enum fw_ri_cqe_rxtx {
+	FW_RI_CQE_RXTX_RX = 0x0,
+	FW_RI_CQE_RXTX_TX = 0x1,
+};
+
+struct fw_ri_cqe {
+	union fw_ri_rxtx {
+		struct fw_ri_scqe {
+		__be32	qpid_n_stat_rxtx_type;
+		__be32	plen;
+		__be32	reserved;
+		__be32	wrid;
+		} scqe;
+		struct fw_ri_rcqe {
+		__be32	qpid_n_stat_rxtx_type;
+		__be32	plen;
+		__be32	stag;
+		__be32	msn;
+		} rcqe;
+	} u;
+};
+
+#define S_FW_RI_CQE_QPID      12
+#define M_FW_RI_CQE_QPID      0xfffff
+#define V_FW_RI_CQE_QPID(x)   ((x) << S_FW_RI_CQE_QPID)
+#define G_FW_RI_CQE_QPID(x)   \
+    (((x) >> S_FW_RI_CQE_QPID) &  M_FW_RI_CQE_QPID)
+
+#define S_FW_RI_CQE_NOTIFY    10
+#define M_FW_RI_CQE_NOTIFY    0x1
+#define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY)
+#define G_FW_RI_CQE_NOTIFY(x) \
+    (((x) >> S_FW_RI_CQE_NOTIFY) &  M_FW_RI_CQE_NOTIFY)
+
+#define S_FW_RI_CQE_STATUS    5
+#define M_FW_RI_CQE_STATUS    0x1f
+#define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS)
+#define G_FW_RI_CQE_STATUS(x) \
+    (((x) >> S_FW_RI_CQE_STATUS) &  M_FW_RI_CQE_STATUS)
+
+
+#define S_FW_RI_CQE_RXTX      4
+#define M_FW_RI_CQE_RXTX      0x1
+#define V_FW_RI_CQE_RXTX(x)   ((x) << S_FW_RI_CQE_RXTX)
+#define G_FW_RI_CQE_RXTX(x)   \
+    (((x) >> S_FW_RI_CQE_RXTX) &  M_FW_RI_CQE_RXTX)
+
+#define S_FW_RI_CQE_TYPE      0
+#define M_FW_RI_CQE_TYPE      0xf
+#define V_FW_RI_CQE_TYPE(x)   ((x) << S_FW_RI_CQE_TYPE)
+#define G_FW_RI_CQE_TYPE(x)   \
+    (((x) >> S_FW_RI_CQE_TYPE) &  M_FW_RI_CQE_TYPE)
+
+enum fw_ri_res_type {
+	FW_RI_RES_TYPE_SQ,
+	FW_RI_RES_TYPE_RQ,
+	FW_RI_RES_TYPE_CQ,
+};
+
+enum fw_ri_res_op {
+	FW_RI_RES_OP_WRITE,
+	FW_RI_RES_OP_RESET,
+};
+
+struct fw_ri_res {
+	union fw_ri_restype {
+		struct fw_ri_res_sqrq {
+			__u8   restype;
+			__u8   op;
+			__be16 r3;
+			__be32 eqid;
+			__be32 r4[2];
+			__be32 fetchszm_to_iqid;
+			__be32 dcaen_to_eqsize;
+			__be64 eqaddr;
+		} sqrq;
+		struct fw_ri_res_cq {
+			__u8   restype;
+			__u8   op;
+			__be16 r3;
+			__be32 iqid;
+			__be32 r4[2];
+			__be32 iqandst_to_iqandstindex;
+			__be16 iqdroprss_to_iqesize;
+			__be16 iqsize;
+			__be64 iqaddr;
+			__be32 iqns_iqro;
+			__be32 r6_lo;
+			__be64 r7;
+		} cq;
+	} u;
+};
+
+struct fw_ri_res_wr {
+	__be32 op_nres;
+	__be32 len16_pkd;
+	__u64  cookie;
+#ifndef C99_NOT_SUPPORTED
+	struct fw_ri_res res[0];
+#endif
+};
+
+#define S_FW_RI_RES_WR_NRES	0
+#define M_FW_RI_RES_WR_NRES	0xff
+#define V_FW_RI_RES_WR_NRES(x)	((x) << S_FW_RI_RES_WR_NRES)
+#define G_FW_RI_RES_WR_NRES(x)	\
+    (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES)
+
+#define S_FW_RI_RES_WR_FETCHSZM		26
+#define M_FW_RI_RES_WR_FETCHSZM		0x1
+#define V_FW_RI_RES_WR_FETCHSZM(x)	((x) << S_FW_RI_RES_WR_FETCHSZM)
+#define G_FW_RI_RES_WR_FETCHSZM(x)	\
+    (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM)
+#define F_FW_RI_RES_WR_FETCHSZM	V_FW_RI_RES_WR_FETCHSZM(1U)
+
+#define S_FW_RI_RES_WR_STATUSPGNS	25
+#define M_FW_RI_RES_WR_STATUSPGNS	0x1
+#define V_FW_RI_RES_WR_STATUSPGNS(x)	((x) << S_FW_RI_RES_WR_STATUSPGNS)
+#define G_FW_RI_RES_WR_STATUSPGNS(x)	\
+    (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS)
+#define F_FW_RI_RES_WR_STATUSPGNS	V_FW_RI_RES_WR_STATUSPGNS(1U)
+
+#define S_FW_RI_RES_WR_STATUSPGRO	24
+#define M_FW_RI_RES_WR_STATUSPGRO	0x1
+#define V_FW_RI_RES_WR_STATUSPGRO(x)	((x) << S_FW_RI_RES_WR_STATUSPGRO)
+#define G_FW_RI_RES_WR_STATUSPGRO(x)	\
+    (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO)
+#define F_FW_RI_RES_WR_STATUSPGRO	V_FW_RI_RES_WR_STATUSPGRO(1U)
+
+#define S_FW_RI_RES_WR_FETCHNS		23
+#define M_FW_RI_RES_WR_FETCHNS		0x1
+#define V_FW_RI_RES_WR_FETCHNS(x)	((x) << S_FW_RI_RES_WR_FETCHNS)
+#define G_FW_RI_RES_WR_FETCHNS(x)	\
+    (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS)
+#define F_FW_RI_RES_WR_FETCHNS	V_FW_RI_RES_WR_FETCHNS(1U)
+
+#define S_FW_RI_RES_WR_FETCHRO		22
+#define M_FW_RI_RES_WR_FETCHRO		0x1
+#define V_FW_RI_RES_WR_FETCHRO(x)	((x) << S_FW_RI_RES_WR_FETCHRO)
+#define G_FW_RI_RES_WR_FETCHRO(x)	\
+    (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO)
+#define F_FW_RI_RES_WR_FETCHRO	V_FW_RI_RES_WR_FETCHRO(1U)
+
+#define S_FW_RI_RES_WR_HOSTFCMODE	20
+#define M_FW_RI_RES_WR_HOSTFCMODE	0x3
+#define V_FW_RI_RES_WR_HOSTFCMODE(x)	((x) << S_FW_RI_RES_WR_HOSTFCMODE)
+#define G_FW_RI_RES_WR_HOSTFCMODE(x)	\
+    (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE)
+
+#define S_FW_RI_RES_WR_CPRIO	19
+#define M_FW_RI_RES_WR_CPRIO	0x1
+#define V_FW_RI_RES_WR_CPRIO(x)	((x) << S_FW_RI_RES_WR_CPRIO)
+#define G_FW_RI_RES_WR_CPRIO(x)	\
+    (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO)
+#define F_FW_RI_RES_WR_CPRIO	V_FW_RI_RES_WR_CPRIO(1U)
+
+#define S_FW_RI_RES_WR_ONCHIP		18
+#define M_FW_RI_RES_WR_ONCHIP		0x1
+#define V_FW_RI_RES_WR_ONCHIP(x)	((x) << S_FW_RI_RES_WR_ONCHIP)
+#define G_FW_RI_RES_WR_ONCHIP(x)	\
+    (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP)
+#define F_FW_RI_RES_WR_ONCHIP	V_FW_RI_RES_WR_ONCHIP(1U)
+
+#define S_FW_RI_RES_WR_PCIECHN		16
+#define M_FW_RI_RES_WR_PCIECHN		0x3
+#define V_FW_RI_RES_WR_PCIECHN(x)	((x) << S_FW_RI_RES_WR_PCIECHN)
+#define G_FW_RI_RES_WR_PCIECHN(x)	\
+    (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN)
+
+#define S_FW_RI_RES_WR_IQID	0
+#define M_FW_RI_RES_WR_IQID	0xffff
+#define V_FW_RI_RES_WR_IQID(x)	((x) << S_FW_RI_RES_WR_IQID)
+#define G_FW_RI_RES_WR_IQID(x)	\
+    (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID)
+
+#define S_FW_RI_RES_WR_DCAEN	31
+#define M_FW_RI_RES_WR_DCAEN	0x1
+#define V_FW_RI_RES_WR_DCAEN(x)	((x) << S_FW_RI_RES_WR_DCAEN)
+#define G_FW_RI_RES_WR_DCAEN(x)	\
+    (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN)
+#define F_FW_RI_RES_WR_DCAEN	V_FW_RI_RES_WR_DCAEN(1U)
+
+#define S_FW_RI_RES_WR_DCACPU		26
+#define M_FW_RI_RES_WR_DCACPU		0x1f
+#define V_FW_RI_RES_WR_DCACPU(x)	((x) << S_FW_RI_RES_WR_DCACPU)
+#define G_FW_RI_RES_WR_DCACPU(x)	\
+    (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU)
+
+#define S_FW_RI_RES_WR_FBMIN	23
+#define M_FW_RI_RES_WR_FBMIN	0x7
+#define V_FW_RI_RES_WR_FBMIN(x)	((x) << S_FW_RI_RES_WR_FBMIN)
+#define G_FW_RI_RES_WR_FBMIN(x)	\
+    (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN)
+
+#define S_FW_RI_RES_WR_FBMAX	20
+#define M_FW_RI_RES_WR_FBMAX	0x7
+#define V_FW_RI_RES_WR_FBMAX(x)	((x) << S_FW_RI_RES_WR_FBMAX)
+#define G_FW_RI_RES_WR_FBMAX(x)	\
+    (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX)
+
+#define S_FW_RI_RES_WR_CIDXFTHRESHO	19
+#define M_FW_RI_RES_WR_CIDXFTHRESHO	0x1
+#define V_FW_RI_RES_WR_CIDXFTHRESHO(x)	((x) << S_FW_RI_RES_WR_CIDXFTHRESHO)
+#define G_FW_RI_RES_WR_CIDXFTHRESHO(x)	\
+    (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO)
+#define F_FW_RI_RES_WR_CIDXFTHRESHO	V_FW_RI_RES_WR_CIDXFTHRESHO(1U)
+
+#define S_FW_RI_RES_WR_CIDXFTHRESH	16
+#define M_FW_RI_RES_WR_CIDXFTHRESH	0x7
+#define V_FW_RI_RES_WR_CIDXFTHRESH(x)	((x) << S_FW_RI_RES_WR_CIDXFTHRESH)
+#define G_FW_RI_RES_WR_CIDXFTHRESH(x)	\
+    (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH)
+
+#define S_FW_RI_RES_WR_EQSIZE		0
+#define M_FW_RI_RES_WR_EQSIZE		0xffff
+#define V_FW_RI_RES_WR_EQSIZE(x)	((x) << S_FW_RI_RES_WR_EQSIZE)
+#define G_FW_RI_RES_WR_EQSIZE(x)	\
+    (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE)
+
+#define S_FW_RI_RES_WR_IQANDST		15
+#define M_FW_RI_RES_WR_IQANDST		0x1
+#define V_FW_RI_RES_WR_IQANDST(x)	((x) << S_FW_RI_RES_WR_IQANDST)
+#define G_FW_RI_RES_WR_IQANDST(x)	\
+    (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST)
+#define F_FW_RI_RES_WR_IQANDST	V_FW_RI_RES_WR_IQANDST(1U)
+
+#define S_FW_RI_RES_WR_IQANUS		14
+#define M_FW_RI_RES_WR_IQANUS		0x1
+#define V_FW_RI_RES_WR_IQANUS(x)	((x) << S_FW_RI_RES_WR_IQANUS)
+#define G_FW_RI_RES_WR_IQANUS(x)	\
+    (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS)
+#define F_FW_RI_RES_WR_IQANUS	V_FW_RI_RES_WR_IQANUS(1U)
+
+#define S_FW_RI_RES_WR_IQANUD		12
+#define M_FW_RI_RES_WR_IQANUD		0x3
+#define V_FW_RI_RES_WR_IQANUD(x)	((x) << S_FW_RI_RES_WR_IQANUD)
+#define G_FW_RI_RES_WR_IQANUD(x)	\
+    (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD)
+
+#define S_FW_RI_RES_WR_IQANDSTINDEX	0
+#define M_FW_RI_RES_WR_IQANDSTINDEX	0xfff
+#define V_FW_RI_RES_WR_IQANDSTINDEX(x)	((x) << S_FW_RI_RES_WR_IQANDSTINDEX)
+#define G_FW_RI_RES_WR_IQANDSTINDEX(x)	\
+    (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX)
+
+#define S_FW_RI_RES_WR_IQDROPRSS	15
+#define M_FW_RI_RES_WR_IQDROPRSS	0x1
+#define V_FW_RI_RES_WR_IQDROPRSS(x)	((x) << S_FW_RI_RES_WR_IQDROPRSS)
+#define G_FW_RI_RES_WR_IQDROPRSS(x)	\
+    (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS)
+#define F_FW_RI_RES_WR_IQDROPRSS	V_FW_RI_RES_WR_IQDROPRSS(1U)
+
+#define S_FW_RI_RES_WR_IQGTSMODE	14
+#define M_FW_RI_RES_WR_IQGTSMODE	0x1
+#define V_FW_RI_RES_WR_IQGTSMODE(x)	((x) << S_FW_RI_RES_WR_IQGTSMODE)
+#define G_FW_RI_RES_WR_IQGTSMODE(x)	\
+    (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE)
+#define F_FW_RI_RES_WR_IQGTSMODE	V_FW_RI_RES_WR_IQGTSMODE(1U)
+
+#define S_FW_RI_RES_WR_IQPCIECH		12
+#define M_FW_RI_RES_WR_IQPCIECH		0x3
+#define V_FW_RI_RES_WR_IQPCIECH(x)	((x) << S_FW_RI_RES_WR_IQPCIECH)
+#define G_FW_RI_RES_WR_IQPCIECH(x)	\
+    (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH)
+
+#define S_FW_RI_RES_WR_IQDCAEN		11
+#define M_FW_RI_RES_WR_IQDCAEN		0x1
+#define V_FW_RI_RES_WR_IQDCAEN(x)	((x) << S_FW_RI_RES_WR_IQDCAEN)
+#define G_FW_RI_RES_WR_IQDCAEN(x)	\
+    (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN)
+#define F_FW_RI_RES_WR_IQDCAEN	V_FW_RI_RES_WR_IQDCAEN(1U)
+
+#define S_FW_RI_RES_WR_IQDCACPU		6
+#define M_FW_RI_RES_WR_IQDCACPU		0x1f
+#define V_FW_RI_RES_WR_IQDCACPU(x)	((x) << S_FW_RI_RES_WR_IQDCACPU)
+#define G_FW_RI_RES_WR_IQDCACPU(x)	\
+    (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU)
+
+#define S_FW_RI_RES_WR_IQINTCNTTHRESH		4
+#define M_FW_RI_RES_WR_IQINTCNTTHRESH		0x3
+#define V_FW_RI_RES_WR_IQINTCNTTHRESH(x)	\
+    ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH)
+#define G_FW_RI_RES_WR_IQINTCNTTHRESH(x)	\
+    (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH)
+
+#define S_FW_RI_RES_WR_IQO	3
+#define M_FW_RI_RES_WR_IQO	0x1
+#define V_FW_RI_RES_WR_IQO(x)	((x) << S_FW_RI_RES_WR_IQO)
+#define G_FW_RI_RES_WR_IQO(x)	\
+    (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO)
+#define F_FW_RI_RES_WR_IQO	V_FW_RI_RES_WR_IQO(1U)
+
+#define S_FW_RI_RES_WR_IQCPRIO		2
+#define M_FW_RI_RES_WR_IQCPRIO		0x1
+#define V_FW_RI_RES_WR_IQCPRIO(x)	((x) << S_FW_RI_RES_WR_IQCPRIO)
+#define G_FW_RI_RES_WR_IQCPRIO(x)	\
+    (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO)
+#define F_FW_RI_RES_WR_IQCPRIO	V_FW_RI_RES_WR_IQCPRIO(1U)
+
+#define S_FW_RI_RES_WR_IQESIZE		0
+#define M_FW_RI_RES_WR_IQESIZE		0x3
+#define V_FW_RI_RES_WR_IQESIZE(x)	((x) << S_FW_RI_RES_WR_IQESIZE)
+#define G_FW_RI_RES_WR_IQESIZE(x)	\
+    (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE)
+
+#define S_FW_RI_RES_WR_IQNS	31
+#define M_FW_RI_RES_WR_IQNS	0x1
+#define V_FW_RI_RES_WR_IQNS(x)	((x) << S_FW_RI_RES_WR_IQNS)
+#define G_FW_RI_RES_WR_IQNS(x)	\
+    (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS)
+#define F_FW_RI_RES_WR_IQNS	V_FW_RI_RES_WR_IQNS(1U)
+
+#define S_FW_RI_RES_WR_IQRO	30
+#define M_FW_RI_RES_WR_IQRO	0x1
+#define V_FW_RI_RES_WR_IQRO(x)	((x) << S_FW_RI_RES_WR_IQRO)
+#define G_FW_RI_RES_WR_IQRO(x)	\
+    (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO)
+#define F_FW_RI_RES_WR_IQRO	V_FW_RI_RES_WR_IQRO(1U)
+
+struct fw_ri_rdma_write_wr {
+	__u8   opcode;
+	__u8   flags;
+	__u16  wrid;
+	__u8   r1[3];
+	__u8   len16;
+	__be64 r2;
+	__be32 plen;
+	__be32 stag_sink;
+	__be64 to_sink;
+#ifndef C99_NOT_SUPPORTED
+	union {
+		struct fw_ri_immd immd_src[0];
+		struct fw_ri_isgl isgl_src[0];
+	} u;
+#endif
+};
+
+struct fw_ri_send_wr {
+	__u8   opcode;
+	__u8   flags;
+	__u16  wrid;
+	__u8   r1[3];
+	__u8   len16;
+	__be32 sendop_pkd;
+	__be32 stag_inv;
+	__be32 plen;
+	__be32 r3;
+	__be64 r4;
+#ifndef C99_NOT_SUPPORTED
+	union {
+		struct fw_ri_immd immd_src[0];
+		struct fw_ri_isgl isgl_src[0];
+	} u;
+#endif
+};
+
+#define S_FW_RI_SEND_WR_SENDOP		0
+#define M_FW_RI_SEND_WR_SENDOP		0xf
+#define V_FW_RI_SEND_WR_SENDOP(x)	((x) << S_FW_RI_SEND_WR_SENDOP)
+#define G_FW_RI_SEND_WR_SENDOP(x)	\
+    (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP)
+
+struct fw_ri_rdma_read_wr {
+	__u8   opcode;
+	__u8   flags;
+	__u16  wrid;
+	__u8   r1[3];
+	__u8   len16;
+	__be64 r2;
+	__be32 stag_sink;
+	__be32 to_sink_hi;
+	__be32 to_sink_lo;
+	__be32 plen;
+	__be32 stag_src;
+	__be32 to_src_hi;
+	__be32 to_src_lo;
+	__be32 r5;
+};
+
+struct fw_ri_recv_wr {
+	__u8   opcode;
+	__u8   r1;
+	__u16  wrid;
+	__u8   r2[3];
+	__u8   len16;
+	struct fw_ri_isgl isgl;
+};
+
+struct fw_ri_bind_mw_wr {
+	__u8   opcode;
+	__u8   flags;
+	__u16  wrid;
+	__u8   r1[3];
+	__u8   len16;
+	__u8   qpbinde_to_dcacpu;
+	__u8   pgsz_shift;
+	__u8   addr_type;
+	__u8   mem_perms;
+	__be32 stag_mr;
+	__be32 stag_mw;
+	__be32 r3;
+	__be64 len_mw;
+	__be64 va_fbo;
+	__be64 r4;
+};
+
+#define S_FW_RI_BIND_MW_WR_QPBINDE	6
+#define M_FW_RI_BIND_MW_WR_QPBINDE	0x1
+#define V_FW_RI_BIND_MW_WR_QPBINDE(x)	((x) << S_FW_RI_BIND_MW_WR_QPBINDE)
+#define G_FW_RI_BIND_MW_WR_QPBINDE(x)	\
+    (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE)
+#define F_FW_RI_BIND_MW_WR_QPBINDE	V_FW_RI_BIND_MW_WR_QPBINDE(1U)
+
+#define S_FW_RI_BIND_MW_WR_NS		5
+#define M_FW_RI_BIND_MW_WR_NS		0x1
+#define V_FW_RI_BIND_MW_WR_NS(x)	((x) << S_FW_RI_BIND_MW_WR_NS)
+#define G_FW_RI_BIND_MW_WR_NS(x)	\
+    (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS)
+#define F_FW_RI_BIND_MW_WR_NS	V_FW_RI_BIND_MW_WR_NS(1U)
+
+#define S_FW_RI_BIND_MW_WR_DCACPU	0
+#define M_FW_RI_BIND_MW_WR_DCACPU	0x1f
+#define V_FW_RI_BIND_MW_WR_DCACPU(x)	((x) << S_FW_RI_BIND_MW_WR_DCACPU)
+#define G_FW_RI_BIND_MW_WR_DCACPU(x)	\
+    (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU)
+
+struct fw_ri_fr_nsmr_wr {
+	__u8   opcode;
+	__u8   flags;
+	__u16  wrid;
+	__u8   r1[3];
+	__u8   len16;
+	__u8   qpbinde_to_dcacpu;
+	__u8   pgsz_shift;
+	__u8   addr_type;
+	__u8   mem_perms;
+	__be32 stag;
+	__be32 len_hi;
+	__be32 len_lo;
+	__be32 va_hi;
+	__be32 va_lo_fbo;
+};
+
+#define S_FW_RI_FR_NSMR_WR_QPBINDE	6
+#define M_FW_RI_FR_NSMR_WR_QPBINDE	0x1
+#define V_FW_RI_FR_NSMR_WR_QPBINDE(x)	((x) << S_FW_RI_FR_NSMR_WR_QPBINDE)
+#define G_FW_RI_FR_NSMR_WR_QPBINDE(x)	\
+    (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE)
+#define F_FW_RI_FR_NSMR_WR_QPBINDE	V_FW_RI_FR_NSMR_WR_QPBINDE(1U)
+
+#define S_FW_RI_FR_NSMR_WR_NS		5
+#define M_FW_RI_FR_NSMR_WR_NS		0x1
+#define V_FW_RI_FR_NSMR_WR_NS(x)	((x) << S_FW_RI_FR_NSMR_WR_NS)
+#define G_FW_RI_FR_NSMR_WR_NS(x)	\
+    (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS)
+#define F_FW_RI_FR_NSMR_WR_NS	V_FW_RI_FR_NSMR_WR_NS(1U)
+
+#define S_FW_RI_FR_NSMR_WR_DCACPU	0
+#define M_FW_RI_FR_NSMR_WR_DCACPU	0x1f
+#define V_FW_RI_FR_NSMR_WR_DCACPU(x)	((x) << S_FW_RI_FR_NSMR_WR_DCACPU)
+#define G_FW_RI_FR_NSMR_WR_DCACPU(x)	\
+    (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU)
+
+struct fw_ri_inv_lstag_wr {
+	__u8   opcode;
+	__u8   flags;
+	__u16  wrid;
+	__u8   r1[3];
+	__u8   len16;
+	__be32 r2;
+	__be32 stag_inv;
+};
+
+struct fw_ri_send_immediate_wr {
+	__u8   opcode;
+	__u8   flags;
+	__u16  wrid;
+	__u8   r1[3];
+	__u8   len16;
+	__be32 sendimmop_pkd;
+	__be32 r3;
+	__be32 plen;
+	__be32 r4;
+	__be64 r5;
+#ifndef C99_NOT_SUPPORTED
+	struct fw_ri_immd immd_src[0];
+#endif
+};
+
+#define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP	0
+#define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP	0xf
+#define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x)	\
+    ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
+#define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x)	\
+    (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \
+     M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
+
+enum fw_ri_atomic_op {
+	FW_RI_ATOMIC_OP_FETCHADD,
+	FW_RI_ATOMIC_OP_SWAP,
+	FW_RI_ATOMIC_OP_CMDSWAP,
+};
+
+struct fw_ri_atomic_wr {
+	__u8   opcode;
+	__u8   flags;
+	__u16  wrid;
+	__u8   r1[3];
+	__u8   len16;
+	__be32 atomicop_pkd;
+	__be64 r3;
+	__be32 aopcode_pkd;
+	__be32 reqid;
+	__be32 stag;
+	__be32 to_hi;
+	__be32 to_lo;
+	__be32 addswap_data_hi;
+	__be32 addswap_data_lo;
+	__be32 addswap_mask_hi;
+	__be32 addswap_mask_lo;
+	__be32 compare_data_hi;
+	__be32 compare_data_lo;
+	__be32 compare_mask_hi;
+	__be32 compare_mask_lo;
+	__be32 r5;
+};
+
+#define S_FW_RI_ATOMIC_WR_ATOMICOP	0
+#define M_FW_RI_ATOMIC_WR_ATOMICOP	0xf
+#define V_FW_RI_ATOMIC_WR_ATOMICOP(x)	((x) << S_FW_RI_ATOMIC_WR_ATOMICOP)
+#define G_FW_RI_ATOMIC_WR_ATOMICOP(x)	\
+    (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP)
+
+#define S_FW_RI_ATOMIC_WR_AOPCODE	0
+#define M_FW_RI_ATOMIC_WR_AOPCODE	0xf
+#define V_FW_RI_ATOMIC_WR_AOPCODE(x)	((x) << S_FW_RI_ATOMIC_WR_AOPCODE)
+#define G_FW_RI_ATOMIC_WR_AOPCODE(x)	\
+    (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE)
+
+enum fw_ri_type {
+	FW_RI_TYPE_INIT,
+	FW_RI_TYPE_FINI,
+	FW_RI_TYPE_TERMINATE
+};
+
+enum fw_ri_init_p2ptype {
+	FW_RI_INIT_P2PTYPE_RDMA_WRITE		= FW_RI_RDMA_WRITE,
+	FW_RI_INIT_P2PTYPE_READ_REQ		= FW_RI_READ_REQ,
+	FW_RI_INIT_P2PTYPE_SEND			= FW_RI_SEND,
+	FW_RI_INIT_P2PTYPE_SEND_WITH_INV	= FW_RI_SEND_WITH_INV,
+	FW_RI_INIT_P2PTYPE_SEND_WITH_SE		= FW_RI_SEND_WITH_SE,
+	FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV	= FW_RI_SEND_WITH_SE_INV,
+	FW_RI_INIT_P2PTYPE_DISABLED		= 0xf,
+};
+
+struct fw_ri_wr {
+	__be32 op_compl;
+	__be32 flowid_len16;
+	__u64  cookie;
+	union fw_ri {
+		struct fw_ri_init {
+			__u8   type;
+			__u8   mpareqbit_p2ptype;
+			__u8   r4[2];
+			__u8   mpa_attrs;
+			__u8   qp_caps;
+			__be16 nrqe;
+			__be32 pdid;
+			__be32 qpid;
+			__be32 sq_eqid;
+			__be32 rq_eqid;
+			__be32 scqid;
+			__be32 rcqid;
+			__be32 ord_max;
+			__be32 ird_max;
+			__be32 iss;
+			__be32 irs;
+			__be32 hwrqsize;
+			__be32 hwrqaddr;
+			__be64 r5;
+			union fw_ri_init_p2p {
+				struct fw_ri_rdma_write_wr write;
+				struct fw_ri_rdma_read_wr read;
+				struct fw_ri_send_wr send;
+			} u;
+		} init;
+		struct fw_ri_fini {
+			__u8   type;
+			__u8   r3[7];
+			__be64 r4;
+		} fini;
+		struct fw_ri_terminate {
+			__u8   type;
+			__u8   r3[3];
+			__be32 immdlen;
+			__u8   termmsg[40];
+		} terminate;
+	} u;
+};
+
+#define S_FW_RI_WR_MPAREQBIT	7
+#define M_FW_RI_WR_MPAREQBIT	0x1
+#define V_FW_RI_WR_MPAREQBIT(x)	((x) << S_FW_RI_WR_MPAREQBIT)
+#define G_FW_RI_WR_MPAREQBIT(x)	\
+    (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT)
+#define F_FW_RI_WR_MPAREQBIT	V_FW_RI_WR_MPAREQBIT(1U)
+
+#define S_FW_RI_WR_0BRRBIT	6
+#define M_FW_RI_WR_0BRRBIT	0x1
+#define V_FW_RI_WR_0BRRBIT(x)	((x) << S_FW_RI_WR_0BRRBIT)
+#define G_FW_RI_WR_0BRRBIT(x)	\
+    (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT)
+#define F_FW_RI_WR_0BRRBIT	V_FW_RI_WR_0BRRBIT(1U)
+
+#define S_FW_RI_WR_P2PTYPE	0
+#define M_FW_RI_WR_P2PTYPE	0xf
+#define V_FW_RI_WR_P2PTYPE(x)	((x) << S_FW_RI_WR_P2PTYPE)
+#define G_FW_RI_WR_P2PTYPE(x)	\
+    (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE)
+
+/******************************************************************************
+ *  F O i S C S I   W O R K R E Q U E S T s
+ *********************************************/
+
+#define	FW_FOISCSI_NAME_MAX_LEN		224
+#define	FW_FOISCSI_ALIAS_MAX_LEN	224
+#define FW_FOISCSI_CHAP_SEC_MAX_LEN	128
+#define	FW_FOISCSI_INIT_NODE_MAX	8
+
+enum fw_chnet_ifconf_wr_subop {
+	FW_CHNET_IFCONF_WR_SUBOP_NONE = 0,
+	
+	FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET,
+	FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET,
+	
+	FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET,
+	FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET,
+
+	FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET,
+	FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET,
+
+	FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET,
+	FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET,
+
+	FW_CHNET_IFCONF_WR_SUBOP_MTU_SET,
+	FW_CHNET_IFCONF_WR_SUBOP_MTU_GET,
+
+	FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET,
+	FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET,
+
+	FW_CHNET_IFCONF_WR_SUBOP_MAX,
+};
+
+struct fw_chnet_ifconf_wr {
+	__be32 op_compl;
+	__be32 flowid_len16;
+	__be64 cookie;
+	__be32 if_flowid;
+	__u8   idx;
+	__u8   subop;
+	__u8   retval;
+	__u8   r2;
+	__be64 r3;
+	struct fw_chnet_ifconf_params {
+		__be32 r0;
+		__be16 vlanid;
+		__be16 mtu;
+		union fw_chnet_ifconf_addr_type {
+			struct fw_chnet_ifconf_ipv4 {
+				__be32 addr;
+				__be32 mask;
+				__be32 router;
+				__be32 r0;
+				__be64 r1;
+			} ipv4;
+			struct fw_chnet_ifconf_ipv6 {
+				__be64 linklocal_lo;
+				__be64 linklocal_hi;
+				__be64 router_hi;
+				__be64 router_lo;
+				__be64 aconf_hi;
+				__be64 aconf_lo;
+				__be64 linklocal_aconf_hi;
+				__be64 linklocal_aconf_lo;
+				__be64 router_aconf_hi;
+				__be64 router_aconf_lo;
+				__be64 r0;
+			} ipv6;
+		} in_attr;
+	} param;
+};
+
+enum fw_foiscsi_node_type {
+	FW_FOISCSI_NODE_TYPE_INITIATOR = 0,
+	FW_FOISCSI_NODE_TYPE_TARGET,
+};
+
+enum fw_foiscsi_session_type {
+	FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0,
+	FW_FOISCSI_SESSION_TYPE_NORMAL,
+};
+
+enum fw_foiscsi_auth_policy {
+	FW_FOISCSI_AUTH_POLICY_ONEWAY = 0,
+	FW_FOISCSI_AUTH_POLICY_MUTUAL,
+};
+
+enum fw_foiscsi_auth_method {
+	FW_FOISCSI_AUTH_METHOD_NONE = 0,
+	FW_FOISCSI_AUTH_METHOD_CHAP,
+	FW_FOISCSI_AUTH_METHOD_CHAP_FST,
+	FW_FOISCSI_AUTH_METHOD_CHAP_SEC,
+};
+
+enum fw_foiscsi_digest_type {
+	FW_FOISCSI_DIGEST_TYPE_NONE = 0,
+	FW_FOISCSI_DIGEST_TYPE_CRC32,
+	FW_FOISCSI_DIGEST_TYPE_CRC32_FST,
+	FW_FOISCSI_DIGEST_TYPE_CRC32_SEC,
+};
+
+enum fw_foiscsi_wr_subop {
+	FW_FOISCSI_WR_SUBOP_ADD = 1,
+	FW_FOISCSI_WR_SUBOP_DEL = 2,
+	FW_FOISCSI_WR_SUBOP_MOD = 4,
+};
+
+enum fw_foiscsi_ctrl_state {
+	FW_FOISCSI_CTRL_STATE_FREE = 0,
+	FW_FOISCSI_CTRL_STATE_ONLINE = 1,
+	FW_FOISCSI_CTRL_STATE_FAILED,
+	FW_FOISCSI_CTRL_STATE_IN_RECOVERY,
+	FW_FOISCSI_CTRL_STATE_REDIRECT,
+};
+
+struct fw_rdev_wr {
+	__be32 op_to_immdlen;
+	__be32 alloc_to_len16;
+	__be64 cookie;
+	__u8   protocol;
+	__u8   event_cause;
+	__u8   cur_state;
+	__u8   prev_state;
+	__be32 flags_to_assoc_flowid;
+	union rdev_entry {
+		struct fcoe_rdev_entry {
+			__be32 flowid;
+			__u8   protocol;
+			__u8   event_cause;
+			__u8   flags;
+			__u8   rjt_reason;
+			__u8   cur_login_st;
+			__u8   prev_login_st;
+			__be16 rcv_fr_sz;
+			__u8   rd_xfer_rdy_to_rport_type;
+			__u8   vft_to_qos;
+			__u8   org_proc_assoc_to_acc_rsp_code;
+			__u8   enh_disc_to_tgt;
+			__u8   wwnn[8];
+			__u8   wwpn[8];
+			__be16 iqid;
+			__u8   fc_oui[3];
+			__u8   r_id[3];
+		} fcoe_rdev;
+		struct iscsi_rdev_entry {
+			__be32 flowid;
+			__u8   protocol;
+			__u8   event_cause;
+			__u8   flags;
+			__u8   r3;
+			__be16 iscsi_opts;
+			__be16 tcp_opts;
+			__be16 ip_opts;
+			__be16 max_rcv_len;
+			__be16 max_snd_len;
+			__be16 first_brst_len;
+			__be16 max_brst_len;
+			__be16 r4;
+			__be16 def_time2wait;
+			__be16 def_time2ret;
+			__be16 nop_out_intrvl;
+			__be16 non_scsi_to;
+			__be16 isid;
+			__be16 tsid;
+			__be16 port;
+			__be16 tpgt;
+			__u8   r5[6];
+			__be16 iqid;
+		} iscsi_rdev;
+	} u;
+};
+
+#define S_FW_RDEV_WR_IMMDLEN	0
+#define M_FW_RDEV_WR_IMMDLEN	0xff
+#define V_FW_RDEV_WR_IMMDLEN(x)	((x) << S_FW_RDEV_WR_IMMDLEN)
+#define G_FW_RDEV_WR_IMMDLEN(x)	\
+    (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN)
+
+#define S_FW_RDEV_WR_ALLOC	31
+#define M_FW_RDEV_WR_ALLOC	0x1
+#define V_FW_RDEV_WR_ALLOC(x)	((x) << S_FW_RDEV_WR_ALLOC)
+#define G_FW_RDEV_WR_ALLOC(x)	\
+    (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC)
+#define F_FW_RDEV_WR_ALLOC	V_FW_RDEV_WR_ALLOC(1U)
+
+#define S_FW_RDEV_WR_FREE	30
+#define M_FW_RDEV_WR_FREE	0x1
+#define V_FW_RDEV_WR_FREE(x)	((x) << S_FW_RDEV_WR_FREE)
+#define G_FW_RDEV_WR_FREE(x)	\
+    (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE)
+#define F_FW_RDEV_WR_FREE	V_FW_RDEV_WR_FREE(1U)
+
+#define S_FW_RDEV_WR_MODIFY	29
+#define M_FW_RDEV_WR_MODIFY	0x1
+#define V_FW_RDEV_WR_MODIFY(x)	((x) << S_FW_RDEV_WR_MODIFY)
+#define G_FW_RDEV_WR_MODIFY(x)	\
+    (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY)
+#define F_FW_RDEV_WR_MODIFY	V_FW_RDEV_WR_MODIFY(1U)
+
+#define S_FW_RDEV_WR_FLOWID	8
+#define M_FW_RDEV_WR_FLOWID	0xfffff
+#define V_FW_RDEV_WR_FLOWID(x)	((x) << S_FW_RDEV_WR_FLOWID)
+#define G_FW_RDEV_WR_FLOWID(x)	\
+    (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID)
+
+#define S_FW_RDEV_WR_LEN16	0
+#define M_FW_RDEV_WR_LEN16	0xff
+#define V_FW_RDEV_WR_LEN16(x)	((x) << S_FW_RDEV_WR_LEN16)
+#define G_FW_RDEV_WR_LEN16(x)	\
+    (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16)
+
+#define S_FW_RDEV_WR_FLAGS	24
+#define M_FW_RDEV_WR_FLAGS	0xff
+#define V_FW_RDEV_WR_FLAGS(x)	((x) << S_FW_RDEV_WR_FLAGS)
+#define G_FW_RDEV_WR_FLAGS(x)	\
+    (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS)
+
+#define S_FW_RDEV_WR_GET_NEXT		20
+#define M_FW_RDEV_WR_GET_NEXT		0xf
+#define V_FW_RDEV_WR_GET_NEXT(x)	((x) << S_FW_RDEV_WR_GET_NEXT)
+#define G_FW_RDEV_WR_GET_NEXT(x)	\
+    (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT)
+
+#define S_FW_RDEV_WR_ASSOC_FLOWID	0
+#define M_FW_RDEV_WR_ASSOC_FLOWID	0xfffff
+#define V_FW_RDEV_WR_ASSOC_FLOWID(x)	((x) << S_FW_RDEV_WR_ASSOC_FLOWID)
+#define G_FW_RDEV_WR_ASSOC_FLOWID(x)	\
+    (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID)
+
+#define S_FW_RDEV_WR_RJT	7
+#define M_FW_RDEV_WR_RJT	0x1
+#define V_FW_RDEV_WR_RJT(x)	((x) << S_FW_RDEV_WR_RJT)
+#define G_FW_RDEV_WR_RJT(x)	(((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT)
+#define F_FW_RDEV_WR_RJT	V_FW_RDEV_WR_RJT(1U)
+
+#define S_FW_RDEV_WR_REASON	0
+#define M_FW_RDEV_WR_REASON	0x7f
+#define V_FW_RDEV_WR_REASON(x)	((x) << S_FW_RDEV_WR_REASON)
+#define G_FW_RDEV_WR_REASON(x)	\
+    (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON)
+
+#define S_FW_RDEV_WR_RD_XFER_RDY	7
+#define M_FW_RDEV_WR_RD_XFER_RDY	0x1
+#define V_FW_RDEV_WR_RD_XFER_RDY(x)	((x) << S_FW_RDEV_WR_RD_XFER_RDY)
+#define G_FW_RDEV_WR_RD_XFER_RDY(x)	\
+    (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY)
+#define F_FW_RDEV_WR_RD_XFER_RDY	V_FW_RDEV_WR_RD_XFER_RDY(1U)
+
+#define S_FW_RDEV_WR_WR_XFER_RDY	6
+#define M_FW_RDEV_WR_WR_XFER_RDY	0x1
+#define V_FW_RDEV_WR_WR_XFER_RDY(x)	((x) << S_FW_RDEV_WR_WR_XFER_RDY)
+#define G_FW_RDEV_WR_WR_XFER_RDY(x)	\
+    (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY)
+#define F_FW_RDEV_WR_WR_XFER_RDY	V_FW_RDEV_WR_WR_XFER_RDY(1U)
+
+#define S_FW_RDEV_WR_FC_SP	5
+#define M_FW_RDEV_WR_FC_SP	0x1
+#define V_FW_RDEV_WR_FC_SP(x)	((x) << S_FW_RDEV_WR_FC_SP)
+#define G_FW_RDEV_WR_FC_SP(x)	\
+    (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP)
+#define F_FW_RDEV_WR_FC_SP	V_FW_RDEV_WR_FC_SP(1U)
+
+#define S_FW_RDEV_WR_RPORT_TYPE		0
+#define M_FW_RDEV_WR_RPORT_TYPE		0x1f
+#define V_FW_RDEV_WR_RPORT_TYPE(x)	((x) << S_FW_RDEV_WR_RPORT_TYPE)
+#define G_FW_RDEV_WR_RPORT_TYPE(x)	\
+    (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE)
+
+#define S_FW_RDEV_WR_VFT	7
+#define M_FW_RDEV_WR_VFT	0x1
+#define V_FW_RDEV_WR_VFT(x)	((x) << S_FW_RDEV_WR_VFT)
+#define G_FW_RDEV_WR_VFT(x)	(((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT)
+#define F_FW_RDEV_WR_VFT	V_FW_RDEV_WR_VFT(1U)
+
+#define S_FW_RDEV_WR_NPIV	6
+#define M_FW_RDEV_WR_NPIV	0x1
+#define V_FW_RDEV_WR_NPIV(x)	((x) << S_FW_RDEV_WR_NPIV)
+#define G_FW_RDEV_WR_NPIV(x)	\
+    (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV)
+#define F_FW_RDEV_WR_NPIV	V_FW_RDEV_WR_NPIV(1U)
+
+#define S_FW_RDEV_WR_CLASS	4
+#define M_FW_RDEV_WR_CLASS	0x3
+#define V_FW_RDEV_WR_CLASS(x)	((x) << S_FW_RDEV_WR_CLASS)
+#define G_FW_RDEV_WR_CLASS(x)	\
+    (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS)
+
+#define S_FW_RDEV_WR_SEQ_DEL	3
+#define M_FW_RDEV_WR_SEQ_DEL	0x1
+#define V_FW_RDEV_WR_SEQ_DEL(x)	((x) << S_FW_RDEV_WR_SEQ_DEL)
+#define G_FW_RDEV_WR_SEQ_DEL(x)	\
+    (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL)
+#define F_FW_RDEV_WR_SEQ_DEL	V_FW_RDEV_WR_SEQ_DEL(1U)
+
+#define S_FW_RDEV_WR_PRIO_PREEMP	2
+#define M_FW_RDEV_WR_PRIO_PREEMP	0x1
+#define V_FW_RDEV_WR_PRIO_PREEMP(x)	((x) << S_FW_RDEV_WR_PRIO_PREEMP)
+#define G_FW_RDEV_WR_PRIO_PREEMP(x)	\
+    (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP)
+#define F_FW_RDEV_WR_PRIO_PREEMP	V_FW_RDEV_WR_PRIO_PREEMP(1U)
+
+#define S_FW_RDEV_WR_PREF	1
+#define M_FW_RDEV_WR_PREF	0x1
+#define V_FW_RDEV_WR_PREF(x)	((x) << S_FW_RDEV_WR_PREF)
+#define G_FW_RDEV_WR_PREF(x)	\
+    (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF)
+#define F_FW_RDEV_WR_PREF	V_FW_RDEV_WR_PREF(1U)
+
+#define S_FW_RDEV_WR_QOS	0
+#define M_FW_RDEV_WR_QOS	0x1
+#define V_FW_RDEV_WR_QOS(x)	((x) << S_FW_RDEV_WR_QOS)
+#define G_FW_RDEV_WR_QOS(x)	(((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS)
+#define F_FW_RDEV_WR_QOS	V_FW_RDEV_WR_QOS(1U)
+
+#define S_FW_RDEV_WR_ORG_PROC_ASSOC	7
+#define M_FW_RDEV_WR_ORG_PROC_ASSOC	0x1
+#define V_FW_RDEV_WR_ORG_PROC_ASSOC(x)	((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC)
+#define G_FW_RDEV_WR_ORG_PROC_ASSOC(x)	\
+    (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC)
+#define F_FW_RDEV_WR_ORG_PROC_ASSOC	V_FW_RDEV_WR_ORG_PROC_ASSOC(1U)
+
+#define S_FW_RDEV_WR_RSP_PROC_ASSOC	6
+#define M_FW_RDEV_WR_RSP_PROC_ASSOC	0x1
+#define V_FW_RDEV_WR_RSP_PROC_ASSOC(x)	((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC)
+#define G_FW_RDEV_WR_RSP_PROC_ASSOC(x)	\
+    (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC)
+#define F_FW_RDEV_WR_RSP_PROC_ASSOC	V_FW_RDEV_WR_RSP_PROC_ASSOC(1U)
+
+#define S_FW_RDEV_WR_IMAGE_PAIR		5
+#define M_FW_RDEV_WR_IMAGE_PAIR		0x1
+#define V_FW_RDEV_WR_IMAGE_PAIR(x)	((x) << S_FW_RDEV_WR_IMAGE_PAIR)
+#define G_FW_RDEV_WR_IMAGE_PAIR(x)	\
+    (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR)
+#define F_FW_RDEV_WR_IMAGE_PAIR	V_FW_RDEV_WR_IMAGE_PAIR(1U)
+
+#define S_FW_RDEV_WR_ACC_RSP_CODE	0
+#define M_FW_RDEV_WR_ACC_RSP_CODE	0x1f
+#define V_FW_RDEV_WR_ACC_RSP_CODE(x)	((x) << S_FW_RDEV_WR_ACC_RSP_CODE)
+#define G_FW_RDEV_WR_ACC_RSP_CODE(x)	\
+    (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE)
+
+#define S_FW_RDEV_WR_ENH_DISC		7
+#define M_FW_RDEV_WR_ENH_DISC		0x1
+#define V_FW_RDEV_WR_ENH_DISC(x)	((x) << S_FW_RDEV_WR_ENH_DISC)
+#define G_FW_RDEV_WR_ENH_DISC(x)	\
+    (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC)
+#define F_FW_RDEV_WR_ENH_DISC	V_FW_RDEV_WR_ENH_DISC(1U)
+
+#define S_FW_RDEV_WR_REC	6
+#define M_FW_RDEV_WR_REC	0x1
+#define V_FW_RDEV_WR_REC(x)	((x) << S_FW_RDEV_WR_REC)
+#define G_FW_RDEV_WR_REC(x)	(((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC)
+#define F_FW_RDEV_WR_REC	V_FW_RDEV_WR_REC(1U)
+
+#define S_FW_RDEV_WR_TASK_RETRY_ID	5
+#define M_FW_RDEV_WR_TASK_RETRY_ID	0x1
+#define V_FW_RDEV_WR_TASK_RETRY_ID(x)	((x) << S_FW_RDEV_WR_TASK_RETRY_ID)
+#define G_FW_RDEV_WR_TASK_RETRY_ID(x)	\
+    (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID)
+#define F_FW_RDEV_WR_TASK_RETRY_ID	V_FW_RDEV_WR_TASK_RETRY_ID(1U)
+
+#define S_FW_RDEV_WR_RETRY	4
+#define M_FW_RDEV_WR_RETRY	0x1
+#define V_FW_RDEV_WR_RETRY(x)	((x) << S_FW_RDEV_WR_RETRY)
+#define G_FW_RDEV_WR_RETRY(x)	\
+    (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY)
+#define F_FW_RDEV_WR_RETRY	V_FW_RDEV_WR_RETRY(1U)
+
+#define S_FW_RDEV_WR_CONF_CMPL		3
+#define M_FW_RDEV_WR_CONF_CMPL		0x1
+#define V_FW_RDEV_WR_CONF_CMPL(x)	((x) << S_FW_RDEV_WR_CONF_CMPL)
+#define G_FW_RDEV_WR_CONF_CMPL(x)	\
+    (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL)
+#define F_FW_RDEV_WR_CONF_CMPL	V_FW_RDEV_WR_CONF_CMPL(1U)
+
+#define S_FW_RDEV_WR_DATA_OVLY		2
+#define M_FW_RDEV_WR_DATA_OVLY		0x1
+#define V_FW_RDEV_WR_DATA_OVLY(x)	((x) << S_FW_RDEV_WR_DATA_OVLY)
+#define G_FW_RDEV_WR_DATA_OVLY(x)	\
+    (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY)
+#define F_FW_RDEV_WR_DATA_OVLY	V_FW_RDEV_WR_DATA_OVLY(1U)
+
+#define S_FW_RDEV_WR_INI	1
+#define M_FW_RDEV_WR_INI	0x1
+#define V_FW_RDEV_WR_INI(x)	((x) << S_FW_RDEV_WR_INI)
+#define G_FW_RDEV_WR_INI(x)	(((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI)
+#define F_FW_RDEV_WR_INI	V_FW_RDEV_WR_INI(1U)
+
+#define S_FW_RDEV_WR_TGT	0
+#define M_FW_RDEV_WR_TGT	0x1
+#define V_FW_RDEV_WR_TGT(x)	((x) << S_FW_RDEV_WR_TGT)
+#define G_FW_RDEV_WR_TGT(x)	(((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT)
+#define F_FW_RDEV_WR_TGT	V_FW_RDEV_WR_TGT(1U)
+
+struct fw_foiscsi_node_wr {
+	__be32 op_to_immdlen;
+	__be32 flowid_len16;
+	__u64  cookie;
+	__u8   subop;
+	__u8   status;
+	__u8   alias_len;
+	__u8   iqn_len;
+	__be32 node_flowid;
+	__be16 nodeid;
+	__be16 login_retry;
+	__be16 retry_timeout;
+	__be16 r3;
+	__u8   iqn[224];
+	__u8   alias[224];
+};
+
+#define S_FW_FOISCSI_NODE_WR_IMMDLEN	0
+#define M_FW_FOISCSI_NODE_WR_IMMDLEN	0xffff
+#define V_FW_FOISCSI_NODE_WR_IMMDLEN(x)	((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN)
+#define G_FW_FOISCSI_NODE_WR_IMMDLEN(x)	\
+    (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN)
+
+struct fw_foiscsi_ctrl_wr {
+	__be32 op_compl;
+	__be32 flowid_len16;
+	__u64  cookie;
+	__u8   subop;
+	__u8   status;
+	__u8   ctrl_state;
+	__u8   io_state;
+	__be32 node_id;
+	__be32 ctrl_id;
+	__be32 io_id;
+	struct fw_foiscsi_sess_attr {
+		__be32 sess_type_to_erl;
+		__be16 max_conn;
+		__be16 max_r2t;
+		__be16 time2wait;
+		__be16 time2retain;
+		__be32 max_burst;
+		__be32 first_burst;
+		__be32 r1;
+	} sess_attr;
+	struct fw_foiscsi_conn_attr {
+		__be32 hdigest_to_ddp_pgsz;
+		__be32 max_rcv_dsl;
+		__be32 ping_tmo;
+		__be16 dst_port;
+		__be16 src_port;
+		union fw_foiscsi_conn_attr_addr {
+			struct fw_foiscsi_conn_attr_ipv6 {
+				__be64 dst_addr[2];
+				__be64 src_addr[2];
+			} ipv6_addr;
+			struct fw_foiscsi_conn_attr_ipv4 {
+				__be32 dst_addr;
+				__be32 src_addr;
+			} ipv4_addr;
+		} u;
+	} conn_attr;
+	__u8   tgt_name_len;
+	__u8   r3[7];
+	__u8   tgt_name[FW_FOISCSI_NAME_MAX_LEN];
+};
+
+#define S_FW_FOISCSI_CTRL_WR_SESS_TYPE		30
+#define M_FW_FOISCSI_CTRL_WR_SESS_TYPE		0x3
+#define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x)	\
+    ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE)
+#define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x)	\
+    (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE)
+
+#define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER	29
+#define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER	0x1
+#define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x)	\
+    ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
+#define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x)	\
+    (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \
+     M_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
+#define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER	\
+    V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U)
+
+#define S_FW_FOISCSI_CTRL_WR_PDU_INORDER	28
+#define M_FW_FOISCSI_CTRL_WR_PDU_INORDER	0x1
+#define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x)	\
+    ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER)
+#define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x)	\
+    (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \
+     M_FW_FOISCSI_CTRL_WR_PDU_INORDER)
+#define F_FW_FOISCSI_CTRL_WR_PDU_INORDER	\
+    V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U)
+
+#define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN	27
+#define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN	0x1
+#define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x)	\
+    ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
+#define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x)	\
+    (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \
+     M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
+#define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN	\
+    V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U)
+
+#define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN	26
+#define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN	0x1
+#define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x)	\
+    ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
+#define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x)	\
+    (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \
+     M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
+#define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN	\
+    V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U)
+
+#define S_FW_FOISCSI_CTRL_WR_ERL	24
+#define M_FW_FOISCSI_CTRL_WR_ERL	0x3
+#define V_FW_FOISCSI_CTRL_WR_ERL(x)	((x) << S_FW_FOISCSI_CTRL_WR_ERL)
+#define G_FW_FOISCSI_CTRL_WR_ERL(x)	\
+    (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL)
+
+#define S_FW_FOISCSI_CTRL_WR_HDIGEST	30
+#define M_FW_FOISCSI_CTRL_WR_HDIGEST	0x3
+#define V_FW_FOISCSI_CTRL_WR_HDIGEST(x)	((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST)
+#define G_FW_FOISCSI_CTRL_WR_HDIGEST(x)	\
+    (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST)
+
+#define S_FW_FOISCSI_CTRL_WR_DDIGEST	28
+#define M_FW_FOISCSI_CTRL_WR_DDIGEST	0x3
+#define V_FW_FOISCSI_CTRL_WR_DDIGEST(x)	((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST)
+#define G_FW_FOISCSI_CTRL_WR_DDIGEST(x)	\
+    (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST)
+
+#define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD	25
+#define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD	0x7
+#define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x)	\
+    ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
+#define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x)	\
+    (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \
+     M_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
+
+#define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY	23
+#define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY	0x3
+#define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x)	\
+    ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
+#define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x)	\
+    (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \
+     M_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
+
+#define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ		21
+#define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ		0x3
+#define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x)	\
+    ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ)
+#define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x)	\
+    (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ)
+
+struct fw_foiscsi_chap_wr {
+	__be32 op_compl;
+	__be32 flowid_len16;
+	__u64  cookie;
+	__u8   status;
+	__u8   id_len;
+	__u8   sec_len;
+	__u8   node_type;
+	__be16 node_id;
+	__u8   r3[2];
+	__u8   chap_id[FW_FOISCSI_NAME_MAX_LEN];
+	__u8   chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN];
+};
+
+/******************************************************************************
+ *  F O F C O E   W O R K R E Q U E S T s
+ *******************************************/
+
+struct fw_fcoe_els_ct_wr {
+	__be32 op_immdlen;
+	__be32 flowid_len16;
+	__be64 cookie;
+	__be16 iqid;
+	__u8   tmo_val;
+	__u8   els_ct_type;
+	__u8   ctl_pri;
+	__u8   cp_en_class;
+	__be16 xfer_cnt;
+	__u8   fl_to_sp;
+	__u8   l_id[3];
+	__u8   r5;
+	__u8   r_id[3];
+	__be64 rsp_dmaaddr;
+	__be32 rsp_dmalen;
+	__be32 r6;
+};
+
+#define S_FW_FCOE_ELS_CT_WR_OPCODE	24
+#define M_FW_FCOE_ELS_CT_WR_OPCODE	0xff
+#define V_FW_FCOE_ELS_CT_WR_OPCODE(x)	((x) << S_FW_FCOE_ELS_CT_WR_OPCODE)
+#define G_FW_FCOE_ELS_CT_WR_OPCODE(x)	\
+    (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE)
+
+#define S_FW_FCOE_ELS_CT_WR_IMMDLEN	0
+#define M_FW_FCOE_ELS_CT_WR_IMMDLEN	0xff
+#define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x)	((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN)
+#define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x)	\
+    (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN)
+
+#define S_FW_FCOE_ELS_CT_WR_FLOWID	8
+#define M_FW_FCOE_ELS_CT_WR_FLOWID	0xfffff
+#define V_FW_FCOE_ELS_CT_WR_FLOWID(x)	((x) << S_FW_FCOE_ELS_CT_WR_FLOWID)
+#define G_FW_FCOE_ELS_CT_WR_FLOWID(x)	\
+    (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID)
+
+#define S_FW_FCOE_ELS_CT_WR_LEN16	0
+#define M_FW_FCOE_ELS_CT_WR_LEN16	0xff
+#define V_FW_FCOE_ELS_CT_WR_LEN16(x)	((x) << S_FW_FCOE_ELS_CT_WR_LEN16)
+#define G_FW_FCOE_ELS_CT_WR_LEN16(x)	\
+    (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16)
+
+#define S_FW_FCOE_ELS_CT_WR_CP_EN	6
+#define M_FW_FCOE_ELS_CT_WR_CP_EN	0x3
+#define V_FW_FCOE_ELS_CT_WR_CP_EN(x)	((x) << S_FW_FCOE_ELS_CT_WR_CP_EN)
+#define G_FW_FCOE_ELS_CT_WR_CP_EN(x)	\
+    (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN)
+
+#define S_FW_FCOE_ELS_CT_WR_CLASS	4
+#define M_FW_FCOE_ELS_CT_WR_CLASS	0x3
+#define V_FW_FCOE_ELS_CT_WR_CLASS(x)	((x) << S_FW_FCOE_ELS_CT_WR_CLASS)
+#define G_FW_FCOE_ELS_CT_WR_CLASS(x)	\
+    (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS)
+
+#define S_FW_FCOE_ELS_CT_WR_FL		2
+#define M_FW_FCOE_ELS_CT_WR_FL		0x1
+#define V_FW_FCOE_ELS_CT_WR_FL(x)	((x) << S_FW_FCOE_ELS_CT_WR_FL)
+#define G_FW_FCOE_ELS_CT_WR_FL(x)	\
+    (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL)
+#define F_FW_FCOE_ELS_CT_WR_FL	V_FW_FCOE_ELS_CT_WR_FL(1U)
+
+#define S_FW_FCOE_ELS_CT_WR_NPIV	1
+#define M_FW_FCOE_ELS_CT_WR_NPIV	0x1
+#define V_FW_FCOE_ELS_CT_WR_NPIV(x)	((x) << S_FW_FCOE_ELS_CT_WR_NPIV)
+#define G_FW_FCOE_ELS_CT_WR_NPIV(x)	\
+    (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV)
+#define F_FW_FCOE_ELS_CT_WR_NPIV	V_FW_FCOE_ELS_CT_WR_NPIV(1U)
+
+#define S_FW_FCOE_ELS_CT_WR_SP		0
+#define M_FW_FCOE_ELS_CT_WR_SP		0x1
+#define V_FW_FCOE_ELS_CT_WR_SP(x)	((x) << S_FW_FCOE_ELS_CT_WR_SP)
+#define G_FW_FCOE_ELS_CT_WR_SP(x)	\
+    (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP)
+#define F_FW_FCOE_ELS_CT_WR_SP	V_FW_FCOE_ELS_CT_WR_SP(1U)
+
+/******************************************************************************
+ *  S C S I   W O R K R E Q U E S T s   (FOiSCSI and FCOE unified data path)
+ *****************************************************************************/
+
+struct fw_scsi_write_wr {
+	__be32 op_immdlen;
+	__be32 flowid_len16;
+	__be64 cookie;
+	__be16 iqid;
+	__u8   tmo_val;
+	__u8   use_xfer_cnt;
+	union fw_scsi_write_priv {
+		struct fcoe_write_priv {
+			__u8   ctl_pri;
+			__u8   cp_en_class;
+			__u8   r3_lo[2];
+		} fcoe;
+		struct iscsi_write_priv {
+			__u8   r3[4];
+		} iscsi;
+	} u;
+	__be32 xfer_cnt;
+	__be32 ini_xfer_cnt;
+	__be64 rsp_dmaaddr;
+	__be32 rsp_dmalen;
+	__be32 r4;
+};
+
+#define S_FW_SCSI_WRITE_WR_OPCODE	24
+#define M_FW_SCSI_WRITE_WR_OPCODE	0xff
+#define V_FW_SCSI_WRITE_WR_OPCODE(x)	((x) << S_FW_SCSI_WRITE_WR_OPCODE)
+#define G_FW_SCSI_WRITE_WR_OPCODE(x)	\
+    (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE)
+
+#define S_FW_SCSI_WRITE_WR_IMMDLEN	0
+#define M_FW_SCSI_WRITE_WR_IMMDLEN	0xff
+#define V_FW_SCSI_WRITE_WR_IMMDLEN(x)	((x) << S_FW_SCSI_WRITE_WR_IMMDLEN)
+#define G_FW_SCSI_WRITE_WR_IMMDLEN(x)	\
+    (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN)
+
+#define S_FW_SCSI_WRITE_WR_FLOWID	8
+#define M_FW_SCSI_WRITE_WR_FLOWID	0xfffff
+#define V_FW_SCSI_WRITE_WR_FLOWID(x)	((x) << S_FW_SCSI_WRITE_WR_FLOWID)
+#define G_FW_SCSI_WRITE_WR_FLOWID(x)	\
+    (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID)
+
+#define S_FW_SCSI_WRITE_WR_LEN16	0
+#define M_FW_SCSI_WRITE_WR_LEN16	0xff
+#define V_FW_SCSI_WRITE_WR_LEN16(x)	((x) << S_FW_SCSI_WRITE_WR_LEN16)
+#define G_FW_SCSI_WRITE_WR_LEN16(x)	\
+    (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16)
+
+#define S_FW_SCSI_WRITE_WR_CP_EN	6
+#define M_FW_SCSI_WRITE_WR_CP_EN	0x3
+#define V_FW_SCSI_WRITE_WR_CP_EN(x)	((x) << S_FW_SCSI_WRITE_WR_CP_EN)
+#define G_FW_SCSI_WRITE_WR_CP_EN(x)	\
+    (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN)
+
+#define S_FW_SCSI_WRITE_WR_CLASS	4
+#define M_FW_SCSI_WRITE_WR_CLASS	0x3
+#define V_FW_SCSI_WRITE_WR_CLASS(x)	((x) << S_FW_SCSI_WRITE_WR_CLASS)
+#define G_FW_SCSI_WRITE_WR_CLASS(x)	\
+    (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS)
+
+struct fw_scsi_read_wr {
+	__be32 op_immdlen;
+	__be32 flowid_len16;
+	__be64 cookie;
+	__be16 iqid;
+	__u8   tmo_val;
+	__u8   use_xfer_cnt;
+	union fw_scsi_read_priv {
+		struct fcoe_read_priv {
+			__u8   ctl_pri;
+			__u8   cp_en_class;
+			__u8   r3_lo[2];
+		} fcoe;
+		struct iscsi_read_priv {
+			__u8   r3[4];
+		} iscsi;
+	} u;
+	__be32 xfer_cnt;
+	__be32 ini_xfer_cnt;
+	__be64 rsp_dmaaddr;
+	__be32 rsp_dmalen;
+	__be32 r4;
+};
+
+#define S_FW_SCSI_READ_WR_OPCODE	24
+#define M_FW_SCSI_READ_WR_OPCODE	0xff
+#define V_FW_SCSI_READ_WR_OPCODE(x)	((x) << S_FW_SCSI_READ_WR_OPCODE)
+#define G_FW_SCSI_READ_WR_OPCODE(x)	\
+    (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE)
+
+#define S_FW_SCSI_READ_WR_IMMDLEN	0
+#define M_FW_SCSI_READ_WR_IMMDLEN	0xff
+#define V_FW_SCSI_READ_WR_IMMDLEN(x)	((x) << S_FW_SCSI_READ_WR_IMMDLEN)
+#define G_FW_SCSI_READ_WR_IMMDLEN(x)	\
+    (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN)
+
+#define S_FW_SCSI_READ_WR_FLOWID	8
+#define M_FW_SCSI_READ_WR_FLOWID	0xfffff
+#define V_FW_SCSI_READ_WR_FLOWID(x)	((x) << S_FW_SCSI_READ_WR_FLOWID)
+#define G_FW_SCSI_READ_WR_FLOWID(x)	\
+    (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID)
+
+#define S_FW_SCSI_READ_WR_LEN16		0
+#define M_FW_SCSI_READ_WR_LEN16		0xff
+#define V_FW_SCSI_READ_WR_LEN16(x)	((x) << S_FW_SCSI_READ_WR_LEN16)
+#define G_FW_SCSI_READ_WR_LEN16(x)	\
+    (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16)
+
+#define S_FW_SCSI_READ_WR_CP_EN		6
+#define M_FW_SCSI_READ_WR_CP_EN		0x3
+#define V_FW_SCSI_READ_WR_CP_EN(x)	((x) << S_FW_SCSI_READ_WR_CP_EN)
+#define G_FW_SCSI_READ_WR_CP_EN(x)	\
+    (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN)
+
+#define S_FW_SCSI_READ_WR_CLASS		4
+#define M_FW_SCSI_READ_WR_CLASS		0x3
+#define V_FW_SCSI_READ_WR_CLASS(x)	((x) << S_FW_SCSI_READ_WR_CLASS)
+#define G_FW_SCSI_READ_WR_CLASS(x)	\
+    (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS)
+
+struct fw_scsi_cmd_wr {
+	__be32 op_immdlen;
+	__be32 flowid_len16;
+	__be64 cookie;
+	__be16 iqid;
+	__u8   tmo_val;
+	__u8   r3;
+	union fw_scsi_cmd_priv {
+		struct fcoe_cmd_priv {
+			__u8   ctl_pri;
+			__u8   cp_en_class;
+			__u8   r4_lo[2];
+		} fcoe;
+		struct iscsi_cmd_priv {
+			__u8   r4[4];
+		} iscsi;
+	} u;
+	__u8   r5[8];
+	__be64 rsp_dmaaddr;
+	__be32 rsp_dmalen;
+	__be32 r6;
+};
+
+#define S_FW_SCSI_CMD_WR_OPCODE		24
+#define M_FW_SCSI_CMD_WR_OPCODE		0xff
+#define V_FW_SCSI_CMD_WR_OPCODE(x)	((x) << S_FW_SCSI_CMD_WR_OPCODE)
+#define G_FW_SCSI_CMD_WR_OPCODE(x)	\
+    (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE)
+
+#define S_FW_SCSI_CMD_WR_IMMDLEN	0
+#define M_FW_SCSI_CMD_WR_IMMDLEN	0xff
+#define V_FW_SCSI_CMD_WR_IMMDLEN(x)	((x) << S_FW_SCSI_CMD_WR_IMMDLEN)
+#define G_FW_SCSI_CMD_WR_IMMDLEN(x)	\
+    (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN)
+
+#define S_FW_SCSI_CMD_WR_FLOWID		8
+#define M_FW_SCSI_CMD_WR_FLOWID		0xfffff
+#define V_FW_SCSI_CMD_WR_FLOWID(x)	((x) << S_FW_SCSI_CMD_WR_FLOWID)
+#define G_FW_SCSI_CMD_WR_FLOWID(x)	\
+    (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID)
+
+#define S_FW_SCSI_CMD_WR_LEN16		0
+#define M_FW_SCSI_CMD_WR_LEN16		0xff
+#define V_FW_SCSI_CMD_WR_LEN16(x)	((x) << S_FW_SCSI_CMD_WR_LEN16)
+#define G_FW_SCSI_CMD_WR_LEN16(x)	\
+    (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16)
+
+#define S_FW_SCSI_CMD_WR_CP_EN		6
+#define M_FW_SCSI_CMD_WR_CP_EN		0x3
+#define V_FW_SCSI_CMD_WR_CP_EN(x)	((x) << S_FW_SCSI_CMD_WR_CP_EN)
+#define G_FW_SCSI_CMD_WR_CP_EN(x)	\
+    (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN)
+
+#define S_FW_SCSI_CMD_WR_CLASS		4
+#define M_FW_SCSI_CMD_WR_CLASS		0x3
+#define V_FW_SCSI_CMD_WR_CLASS(x)	((x) << S_FW_SCSI_CMD_WR_CLASS)
+#define G_FW_SCSI_CMD_WR_CLASS(x)	\
+    (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS)
+
+struct fw_scsi_abrt_cls_wr {
+	__be32 op_immdlen;
+	__be32 flowid_len16;
+	__be64 cookie;
+	__be16 iqid;
+	__u8   tmo_val;
+	__u8   sub_opcode_to_chk_all_io;
+	__u8   r3[4];
+	__be64 t_cookie;
+};
+
+#define S_FW_SCSI_ABRT_CLS_WR_OPCODE	24
+#define M_FW_SCSI_ABRT_CLS_WR_OPCODE	0xff
+#define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE)
+#define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x)	\
+    (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE)
+
+#define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN		0
+#define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN		0xff
+#define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x)	\
+    ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
+#define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x)	\
+    (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
+
+#define S_FW_SCSI_ABRT_CLS_WR_FLOWID	8
+#define M_FW_SCSI_ABRT_CLS_WR_FLOWID	0xfffff
+#define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID)
+#define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x)	\
+    (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID)
+
+#define S_FW_SCSI_ABRT_CLS_WR_LEN16	0
+#define M_FW_SCSI_ABRT_CLS_WR_LEN16	0xff
+#define V_FW_SCSI_ABRT_CLS_WR_LEN16(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16)
+#define G_FW_SCSI_ABRT_CLS_WR_LEN16(x)	\
+    (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16)
+
+#define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE	2
+#define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE	0x3f
+#define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x)	\
+    ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)
+#define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x)	\
+    (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \
+     M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)
+
+#define S_FW_SCSI_ABRT_CLS_WR_UNSOL	1
+#define M_FW_SCSI_ABRT_CLS_WR_UNSOL	0x1
+#define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL)
+#define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x)	\
+    (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL)
+#define F_FW_SCSI_ABRT_CLS_WR_UNSOL	V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U)
+
+#define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO	0
+#define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO	0x1
+#define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x)	\
+    ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
+#define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x)	\
+    (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \
+     M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
+#define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO	\
+    V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U)
+
+struct fw_scsi_tgt_acc_wr {
+	__be32 op_immdlen;
+	__be32 flowid_len16;
+	__be64 cookie;
+	__be16 iqid;
+	__u8   r3;
+	__u8   use_burst_len;
+	union fw_scsi_tgt_acc_priv {
+		struct fcoe_tgt_acc_priv {
+			__u8   ctl_pri;
+			__u8   cp_en_class;
+			__u8   r4_lo[2];
+		} fcoe;
+		struct iscsi_tgt_acc_priv {
+			__u8   r4[4];
+		} iscsi;
+	} u;
+	__be32 burst_len;
+	__be32 rel_off;
+	__be64 r5;
+	__be32 r6;
+	__be32 tot_xfer_len;
+};
+
+#define S_FW_SCSI_TGT_ACC_WR_OPCODE	24
+#define M_FW_SCSI_TGT_ACC_WR_OPCODE	0xff
+#define V_FW_SCSI_TGT_ACC_WR_OPCODE(x)	((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE)
+#define G_FW_SCSI_TGT_ACC_WR_OPCODE(x)	\
+    (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE)
+
+#define S_FW_SCSI_TGT_ACC_WR_IMMDLEN	0
+#define M_FW_SCSI_TGT_ACC_WR_IMMDLEN	0xff
+#define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x)	((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN)
+#define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x)	\
+    (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN)
+
+#define S_FW_SCSI_TGT_ACC_WR_FLOWID	8
+#define M_FW_SCSI_TGT_ACC_WR_FLOWID	0xfffff
+#define V_FW_SCSI_TGT_ACC_WR_FLOWID(x)	((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID)
+#define G_FW_SCSI_TGT_ACC_WR_FLOWID(x)	\
+    (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID)
+
+#define S_FW_SCSI_TGT_ACC_WR_LEN16	0
+#define M_FW_SCSI_TGT_ACC_WR_LEN16	0xff
+#define V_FW_SCSI_TGT_ACC_WR_LEN16(x)	((x) << S_FW_SCSI_TGT_ACC_WR_LEN16)
+#define G_FW_SCSI_TGT_ACC_WR_LEN16(x)	\
+    (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16)
+
+#define S_FW_SCSI_TGT_ACC_WR_CP_EN	6
+#define M_FW_SCSI_TGT_ACC_WR_CP_EN	0x3
+#define V_FW_SCSI_TGT_ACC_WR_CP_EN(x)	((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN)
+#define G_FW_SCSI_TGT_ACC_WR_CP_EN(x)	\
+    (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN)
+
+#define S_FW_SCSI_TGT_ACC_WR_CLASS	4
+#define M_FW_SCSI_TGT_ACC_WR_CLASS	0x3
+#define V_FW_SCSI_TGT_ACC_WR_CLASS(x)	((x) << S_FW_SCSI_TGT_ACC_WR_CLASS)
+#define G_FW_SCSI_TGT_ACC_WR_CLASS(x)	\
+    (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS)
+
+struct fw_scsi_tgt_xmit_wr {
+	__be32 op_immdlen;
+	__be32 flowid_len16;
+	__be64 cookie;
+	__be16 iqid;
+	__u8   auto_rsp;
+	__u8   use_xfer_cnt;
+	union fw_scsi_tgt_xmit_priv {
+		struct fcoe_tgt_xmit_priv {
+			__u8   ctl_pri;
+			__u8   cp_en_class;
+			__u8   r3_lo[2];
+		} fcoe;
+		struct iscsi_tgt_xmit_priv {
+			__u8   r3[4];
+		} iscsi;
+	} u;
+	__be32 xfer_cnt;
+	__be32 r4;
+	__be64 r5;
+	__be32 r6;
+	__be32 tot_xfer_len;
+};
+
+#define S_FW_SCSI_TGT_XMIT_WR_OPCODE	24
+#define M_FW_SCSI_TGT_XMIT_WR_OPCODE	0xff
+#define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE)
+#define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x)	\
+    (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE)
+
+#define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN		0
+#define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN		0xff
+#define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x)	\
+    ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
+#define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x)	\
+    (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
+
+#define S_FW_SCSI_TGT_XMIT_WR_FLOWID	8
+#define M_FW_SCSI_TGT_XMIT_WR_FLOWID	0xfffff
+#define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID)
+#define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x)	\
+    (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID)
+
+#define S_FW_SCSI_TGT_XMIT_WR_LEN16	0
+#define M_FW_SCSI_TGT_XMIT_WR_LEN16	0xff
+#define V_FW_SCSI_TGT_XMIT_WR_LEN16(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16)
+#define G_FW_SCSI_TGT_XMIT_WR_LEN16(x)	\
+    (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16)
+
+#define S_FW_SCSI_TGT_XMIT_WR_CP_EN	6
+#define M_FW_SCSI_TGT_XMIT_WR_CP_EN	0x3
+#define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN)
+#define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x)	\
+    (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN)
+
+#define S_FW_SCSI_TGT_XMIT_WR_CLASS	4
+#define M_FW_SCSI_TGT_XMIT_WR_CLASS	0x3
+#define V_FW_SCSI_TGT_XMIT_WR_CLASS(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS)
+#define G_FW_SCSI_TGT_XMIT_WR_CLASS(x)	\
+    (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS)
+
+struct fw_scsi_tgt_rsp_wr {
+	__be32 op_immdlen;
+	__be32 flowid_len16;
+	__be64 cookie;
+	__be16 iqid;
+	__u8   r3[2];
+	union fw_scsi_tgt_rsp_priv {
+		struct fcoe_tgt_rsp_priv {
+			__u8   ctl_pri;
+			__u8   cp_en_class;
+			__u8   r4_lo[2];
+		} fcoe;
+		struct iscsi_tgt_rsp_priv {
+			__u8   r4[4];
+		} iscsi;
+	} u;
+	__u8   r5[8];
+};
+
+#define S_FW_SCSI_TGT_RSP_WR_OPCODE	24
+#define M_FW_SCSI_TGT_RSP_WR_OPCODE	0xff
+#define V_FW_SCSI_TGT_RSP_WR_OPCODE(x)	((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE)
+#define G_FW_SCSI_TGT_RSP_WR_OPCODE(x)	\
+    (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE)
+
+#define S_FW_SCSI_TGT_RSP_WR_IMMDLEN	0
+#define M_FW_SCSI_TGT_RSP_WR_IMMDLEN	0xff
+#define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x)	((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN)
+#define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x)	\
+    (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN)
+
+#define S_FW_SCSI_TGT_RSP_WR_FLOWID	8
+#define M_FW_SCSI_TGT_RSP_WR_FLOWID	0xfffff
+#define V_FW_SCSI_TGT_RSP_WR_FLOWID(x)	((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID)
+#define G_FW_SCSI_TGT_RSP_WR_FLOWID(x)	\
+    (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID)
+
+#define S_FW_SCSI_TGT_RSP_WR_LEN16	0
+#define M_FW_SCSI_TGT_RSP_WR_LEN16	0xff
+#define V_FW_SCSI_TGT_RSP_WR_LEN16(x)	((x) << S_FW_SCSI_TGT_RSP_WR_LEN16)
+#define G_FW_SCSI_TGT_RSP_WR_LEN16(x)	\
+    (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16)
+
+#define S_FW_SCSI_TGT_RSP_WR_CP_EN	6
+#define M_FW_SCSI_TGT_RSP_WR_CP_EN	0x3
+#define V_FW_SCSI_TGT_RSP_WR_CP_EN(x)	((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN)
+#define G_FW_SCSI_TGT_RSP_WR_CP_EN(x)	\
+    (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN)
+
+#define S_FW_SCSI_TGT_RSP_WR_CLASS	4
+#define M_FW_SCSI_TGT_RSP_WR_CLASS	0x3
+#define V_FW_SCSI_TGT_RSP_WR_CLASS(x)	((x) << S_FW_SCSI_TGT_RSP_WR_CLASS)
+#define G_FW_SCSI_TGT_RSP_WR_CLASS(x)	\
+    (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS)
+
+struct fw_pofcoe_tcb_wr {
+	__be32 op_compl;
+	__be32 equiq_to_len16;
+	__be64 cookie;
+	__be32 tid_to_port;
+	__be16 x_id;
+	__be16 vlan_id;
+	__be32 s_id;
+	__be32 d_id;
+	__be32 tag;
+	__be32 xfer_len;
+	__be32 r4;
+	__be16 r5;
+	__be16 iqid;
+};
+
+#define S_FW_POFCOE_TCB_WR_TID		12
+#define M_FW_POFCOE_TCB_WR_TID		0xfffff
+#define V_FW_POFCOE_TCB_WR_TID(x)	((x) << S_FW_POFCOE_TCB_WR_TID)
+#define G_FW_POFCOE_TCB_WR_TID(x)	\
+    (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID)
+
+#define S_FW_POFCOE_TCB_WR_ALLOC	4
+#define M_FW_POFCOE_TCB_WR_ALLOC	0x1
+#define V_FW_POFCOE_TCB_WR_ALLOC(x)	((x) << S_FW_POFCOE_TCB_WR_ALLOC)
+#define G_FW_POFCOE_TCB_WR_ALLOC(x)	\
+    (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC)
+#define F_FW_POFCOE_TCB_WR_ALLOC	V_FW_POFCOE_TCB_WR_ALLOC(1U)
+
+#define S_FW_POFCOE_TCB_WR_FREE		3
+#define M_FW_POFCOE_TCB_WR_FREE		0x1
+#define V_FW_POFCOE_TCB_WR_FREE(x)	((x) << S_FW_POFCOE_TCB_WR_FREE)
+#define G_FW_POFCOE_TCB_WR_FREE(x)	\
+    (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE)
+#define F_FW_POFCOE_TCB_WR_FREE	V_FW_POFCOE_TCB_WR_FREE(1U)
+
+#define S_FW_POFCOE_TCB_WR_PORT		0
+#define M_FW_POFCOE_TCB_WR_PORT		0x7
+#define V_FW_POFCOE_TCB_WR_PORT(x)	((x) << S_FW_POFCOE_TCB_WR_PORT)
+#define G_FW_POFCOE_TCB_WR_PORT(x)	\
+    (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT)
+
+struct fw_pofcoe_ulptx_wr {
+	__be32 op_pkd;
+	__be32 equiq_to_len16;
+	__u64  cookie;
+};
+
+
+/******************************************************************************
+ *  C O M M A N D s
+ *********************/
+
+/*
+ * The maximum length of time, in miliseconds, that we expect any firmware
+ * command to take to execute and return a reply to the host.  The RESET
+ * and INITIALIZE commands can take a fair amount of time to execute but
+ * most execute in far less time than this maximum.  This constant is used
+ * by host software to determine how long to wait for a firmware command
+ * reply before declaring the firmware as dead/unreachable ...
+ */
+#define FW_CMD_MAX_TIMEOUT	10000
+
+/*
+ * If a host driver does a HELLO and discovers that there's already a MASTER
+ * selected, we may have to wait for that MASTER to finish issuing RESET,
+ * configuration and INITIALIZE commands.  Also, there's a possibility that
+ * our own HELLO may get lost if it happens right as the MASTER is issuign a
+ * RESET command, so we need to be willing to make a few retries of our HELLO.
+ */
+#define FW_CMD_HELLO_TIMEOUT	(3 * FW_CMD_MAX_TIMEOUT)
+#define FW_CMD_HELLO_RETRIES	3
+
+enum fw_cmd_opcodes {
+	FW_LDST_CMD                    = 0x01,
+	FW_RESET_CMD                   = 0x03,
+	FW_HELLO_CMD                   = 0x04,
+	FW_BYE_CMD                     = 0x05,
+	FW_INITIALIZE_CMD              = 0x06,
+	FW_CAPS_CONFIG_CMD             = 0x07,
+	FW_PARAMS_CMD                  = 0x08,
+	FW_PFVF_CMD                    = 0x09,
+	FW_IQ_CMD                      = 0x10,
+	FW_EQ_MNGT_CMD                 = 0x11,
+	FW_EQ_ETH_CMD                  = 0x12,
+	FW_EQ_CTRL_CMD                 = 0x13,
+	FW_EQ_OFLD_CMD                 = 0x21,
+	FW_VI_CMD                      = 0x14,
+	FW_VI_MAC_CMD                  = 0x15,
+	FW_VI_RXMODE_CMD               = 0x16,
+	FW_VI_ENABLE_CMD               = 0x17,
+	FW_VI_STATS_CMD                = 0x1a,
+	FW_ACL_MAC_CMD                 = 0x18,
+	FW_ACL_VLAN_CMD                = 0x19,
+	FW_PORT_CMD                    = 0x1b,
+	FW_PORT_STATS_CMD              = 0x1c,
+	FW_PORT_LB_STATS_CMD           = 0x1d,
+	FW_PORT_TRACE_CMD              = 0x1e,
+	FW_PORT_TRACE_MMAP_CMD         = 0x1f,
+	FW_RSS_IND_TBL_CMD             = 0x20,
+	FW_RSS_GLB_CONFIG_CMD          = 0x22,
+	FW_RSS_VI_CONFIG_CMD           = 0x23,
+	FW_SCHED_CMD                   = 0x24,
+	FW_DEVLOG_CMD                  = 0x25,
+	FW_WATCHDOG_CMD                = 0x27,
+	FW_CLIP_CMD                    = 0x28,
+	FW_CHNET_IFACE_CMD             = 0x26,
+	FW_FCOE_RES_INFO_CMD           = 0x31,
+	FW_FCOE_LINK_CMD               = 0x32,
+	FW_FCOE_VNP_CMD                = 0x33,
+	FW_FCOE_SPARAMS_CMD            = 0x35,
+	FW_FCOE_STATS_CMD              = 0x37,
+	FW_FCOE_FCF_CMD                = 0x38,
+	FW_LASTC2E_CMD                 = 0x40,
+	FW_ERROR_CMD                   = 0x80,
+	FW_DEBUG_CMD                   = 0x81,
+};
+
+enum fw_cmd_cap {
+	FW_CMD_CAP_PF                  = 0x01,
+	FW_CMD_CAP_DMAQ                = 0x02,
+	FW_CMD_CAP_PORT                = 0x04,
+	FW_CMD_CAP_PORTPROMISC         = 0x08,
+	FW_CMD_CAP_PORTSTATS           = 0x10,
+	FW_CMD_CAP_VF                  = 0x80,
+};
+
+/*
+ * Generic command header flit0
+ */
+struct fw_cmd_hdr {
+	__be32 hi;
+	__be32 lo;
+};
+
+#define S_FW_CMD_OP		24
+#define M_FW_CMD_OP		0xff
+#define V_FW_CMD_OP(x)		((x) << S_FW_CMD_OP)
+#define G_FW_CMD_OP(x)		(((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
+
+#define S_FW_CMD_REQUEST	23
+#define M_FW_CMD_REQUEST	0x1
+#define V_FW_CMD_REQUEST(x)	((x) << S_FW_CMD_REQUEST)
+#define G_FW_CMD_REQUEST(x)	(((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
+#define F_FW_CMD_REQUEST	V_FW_CMD_REQUEST(1U)
+
+#define S_FW_CMD_READ		22
+#define M_FW_CMD_READ		0x1
+#define V_FW_CMD_READ(x)	((x) << S_FW_CMD_READ)
+#define G_FW_CMD_READ(x)	(((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
+#define F_FW_CMD_READ		V_FW_CMD_READ(1U)
+
+#define S_FW_CMD_WRITE		21
+#define M_FW_CMD_WRITE		0x1
+#define V_FW_CMD_WRITE(x)	((x) << S_FW_CMD_WRITE)
+#define G_FW_CMD_WRITE(x)	(((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
+#define F_FW_CMD_WRITE		V_FW_CMD_WRITE(1U)
+
+#define S_FW_CMD_EXEC		20
+#define M_FW_CMD_EXEC		0x1
+#define V_FW_CMD_EXEC(x)	((x) << S_FW_CMD_EXEC)
+#define G_FW_CMD_EXEC(x)	(((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
+#define F_FW_CMD_EXEC		V_FW_CMD_EXEC(1U)
+
+#define S_FW_CMD_RAMASK		20
+#define M_FW_CMD_RAMASK		0xf
+#define V_FW_CMD_RAMASK(x)	((x) << S_FW_CMD_RAMASK)
+#define G_FW_CMD_RAMASK(x)	(((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK)
+
+#define S_FW_CMD_RETVAL		8
+#define M_FW_CMD_RETVAL		0xff
+#define V_FW_CMD_RETVAL(x)	((x) << S_FW_CMD_RETVAL)
+#define G_FW_CMD_RETVAL(x)	(((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
+
+#define S_FW_CMD_LEN16		0
+#define M_FW_CMD_LEN16		0xff
+#define V_FW_CMD_LEN16(x)	((x) << S_FW_CMD_LEN16)
+#define G_FW_CMD_LEN16(x)	(((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
+
+#define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16)
+
+/*
+ *	address spaces
+ */
+enum fw_ldst_addrspc {
+	FW_LDST_ADDRSPC_FIRMWARE  = 0x0001,
+	FW_LDST_ADDRSPC_SGE_EGRC  = 0x0008,
+	FW_LDST_ADDRSPC_SGE_INGC  = 0x0009,
+	FW_LDST_ADDRSPC_SGE_FLMC  = 0x000a,
+	FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
+	FW_LDST_ADDRSPC_TP_PIO    = 0x0010,
+	FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
+	FW_LDST_ADDRSPC_TP_MIB    = 0x0012,
+	FW_LDST_ADDRSPC_MDIO      = 0x0018,
+	FW_LDST_ADDRSPC_MPS       = 0x0020,
+	FW_LDST_ADDRSPC_FUNC      = 0x0028,
+	FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
+	FW_LDST_ADDRSPC_FUNC_I2C  = 0x002A, /* legacy */
+	FW_LDST_ADDRSPC_LE	  = 0x0030,
+	FW_LDST_ADDRSPC_I2C       = 0x0038,
+	FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040,
+	FW_LDST_ADDRSPC_PCIE_DBG  = 0x0041,
+	FW_LDST_ADDRSPC_PCIE_PHY  = 0x0042,
+};
+
+/*
+ *	MDIO VSC8634 register access control field
+ */
+enum fw_ldst_mdio_vsc8634_aid {
+	FW_LDST_MDIO_VS_STANDARD,
+	FW_LDST_MDIO_VS_EXTENDED,
+	FW_LDST_MDIO_VS_GPIO
+};
+
+enum fw_ldst_mps_fid {
+	FW_LDST_MPS_ATRB,
+	FW_LDST_MPS_RPLC
+};
+
+enum fw_ldst_func_access_ctl {
+	FW_LDST_FUNC_ACC_CTL_VIID,
+	FW_LDST_FUNC_ACC_CTL_FID
+};
+
+enum fw_ldst_func_mod_index {
+	FW_LDST_FUNC_MPS
+};
+
+struct fw_ldst_cmd {
+	__be32 op_to_addrspace;
+	__be32 cycles_to_len16;
+	union fw_ldst {
+		struct fw_ldst_addrval {
+			__be32 addr;
+			__be32 val;
+		} addrval;
+		struct fw_ldst_idctxt {
+			__be32 physid;
+			__be32 msg_ctxtflush;
+			__be32 ctxt_data7;
+			__be32 ctxt_data6;
+			__be32 ctxt_data5;
+			__be32 ctxt_data4;
+			__be32 ctxt_data3;
+			__be32 ctxt_data2;
+			__be32 ctxt_data1;
+			__be32 ctxt_data0;
+		} idctxt;
+		struct fw_ldst_mdio {
+			__be16 paddr_mmd;
+			__be16 raddr;
+			__be16 vctl;
+			__be16 rval;
+		} mdio;
+		struct fw_ldst_mps {
+			__be16 fid_ctl;
+			__be16 rplcpf_pkd;
+			__be32 rplc127_96;
+			__be32 rplc95_64;
+			__be32 rplc63_32;
+			__be32 rplc31_0;
+			__be32 atrb;
+			__be16 vlan[16];
+		} mps;
+		struct fw_ldst_func {
+			__u8   access_ctl;
+			__u8   mod_index;
+			__be16 ctl_id;
+			__be32 offset;
+			__be64 data0;
+			__be64 data1;
+		} func;
+		struct fw_ldst_pcie {
+			__u8   ctrl_to_fn;
+			__u8   bnum;
+			__u8   r;
+			__u8   ext_r;
+			__u8   select_naccess;
+			__u8   pcie_fn;
+			__be16 nset_pkd;
+			__be32 data[12];
+		} pcie;
+		struct fw_ldst_i2c_deprecated {
+			__u8   pid_pkd;
+			__u8   base;
+			__u8   boffset;
+			__u8   data;
+			__be32 r9;
+		} i2c_deprecated;
+		struct fw_ldst_i2c {
+			__u8   pid;
+			__u8   did;
+			__u8   boffset;
+			__u8   blen;
+			__be32 r9;
+			__u8   data[48];
+		} i2c;
+		struct fw_ldst_le {
+			__be32 index;
+			__be32 r9;
+			__u8   val[33];
+			__u8   r11[7];
+		} le;
+	} u;
+};
+
+#define S_FW_LDST_CMD_ADDRSPACE		0
+#define M_FW_LDST_CMD_ADDRSPACE		0xff
+#define V_FW_LDST_CMD_ADDRSPACE(x)	((x) << S_FW_LDST_CMD_ADDRSPACE)
+#define G_FW_LDST_CMD_ADDRSPACE(x)	\
+    (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE)
+
+#define S_FW_LDST_CMD_CYCLES	16
+#define M_FW_LDST_CMD_CYCLES	0xffff
+#define V_FW_LDST_CMD_CYCLES(x)	((x) << S_FW_LDST_CMD_CYCLES)
+#define G_FW_LDST_CMD_CYCLES(x)	\
+    (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES)
+
+#define S_FW_LDST_CMD_MSG	31
+#define M_FW_LDST_CMD_MSG	0x1
+#define V_FW_LDST_CMD_MSG(x)	((x) << S_FW_LDST_CMD_MSG)
+#define G_FW_LDST_CMD_MSG(x)	\
+    (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG)
+#define F_FW_LDST_CMD_MSG	V_FW_LDST_CMD_MSG(1U)
+
+#define S_FW_LDST_CMD_CTXTFLUSH		30
+#define M_FW_LDST_CMD_CTXTFLUSH		0x1
+#define V_FW_LDST_CMD_CTXTFLUSH(x)	((x) << S_FW_LDST_CMD_CTXTFLUSH)
+#define G_FW_LDST_CMD_CTXTFLUSH(x)	\
+    (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH)
+#define F_FW_LDST_CMD_CTXTFLUSH	V_FW_LDST_CMD_CTXTFLUSH(1U)
+
+#define S_FW_LDST_CMD_PADDR	8
+#define M_FW_LDST_CMD_PADDR	0x1f
+#define V_FW_LDST_CMD_PADDR(x)	((x) << S_FW_LDST_CMD_PADDR)
+#define G_FW_LDST_CMD_PADDR(x)	\
+    (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR)
+
+#define S_FW_LDST_CMD_MMD	0
+#define M_FW_LDST_CMD_MMD	0x1f
+#define V_FW_LDST_CMD_MMD(x)	((x) << S_FW_LDST_CMD_MMD)
+#define G_FW_LDST_CMD_MMD(x)	\
+    (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD)
+
+#define S_FW_LDST_CMD_FID	15
+#define M_FW_LDST_CMD_FID	0x1
+#define V_FW_LDST_CMD_FID(x)	((x) << S_FW_LDST_CMD_FID)
+#define G_FW_LDST_CMD_FID(x)	\
+    (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID)
+#define F_FW_LDST_CMD_FID	V_FW_LDST_CMD_FID(1U)
+
+#define S_FW_LDST_CMD_CTL	0
+#define M_FW_LDST_CMD_CTL	0x7fff
+#define V_FW_LDST_CMD_CTL(x)	((x) << S_FW_LDST_CMD_CTL)
+#define G_FW_LDST_CMD_CTL(x)	\
+    (((x) >> S_FW_LDST_CMD_CTL) & M_FW_LDST_CMD_CTL)
+
+#define S_FW_LDST_CMD_RPLCPF	0
+#define M_FW_LDST_CMD_RPLCPF	0xff
+#define V_FW_LDST_CMD_RPLCPF(x)	((x) << S_FW_LDST_CMD_RPLCPF)
+#define G_FW_LDST_CMD_RPLCPF(x)	\
+    (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF)
+
+#define S_FW_LDST_CMD_CTRL	7
+#define M_FW_LDST_CMD_CTRL	0x1
+#define V_FW_LDST_CMD_CTRL(x)	((x) << S_FW_LDST_CMD_CTRL)
+#define G_FW_LDST_CMD_CTRL(x)	\
+    (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL)
+#define F_FW_LDST_CMD_CTRL	V_FW_LDST_CMD_CTRL(1U)
+
+#define S_FW_LDST_CMD_LC	4
+#define M_FW_LDST_CMD_LC	0x1
+#define V_FW_LDST_CMD_LC(x)	((x) << S_FW_LDST_CMD_LC)
+#define G_FW_LDST_CMD_LC(x)	(((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC)
+#define F_FW_LDST_CMD_LC	V_FW_LDST_CMD_LC(1U)
+
+#define S_FW_LDST_CMD_AI	3
+#define M_FW_LDST_CMD_AI	0x1
+#define V_FW_LDST_CMD_AI(x)	((x) << S_FW_LDST_CMD_AI)
+#define G_FW_LDST_CMD_AI(x)	(((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI)
+#define F_FW_LDST_CMD_AI	V_FW_LDST_CMD_AI(1U)
+
+#define S_FW_LDST_CMD_FN	0
+#define M_FW_LDST_CMD_FN	0x7
+#define V_FW_LDST_CMD_FN(x)	((x) << S_FW_LDST_CMD_FN)
+#define G_FW_LDST_CMD_FN(x)	(((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN)
+
+#define S_FW_LDST_CMD_SELECT	4
+#define M_FW_LDST_CMD_SELECT	0xf
+#define V_FW_LDST_CMD_SELECT(x)	((x) << S_FW_LDST_CMD_SELECT)
+#define G_FW_LDST_CMD_SELECT(x)	\
+    (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT)
+
+#define S_FW_LDST_CMD_NACCESS		0
+#define M_FW_LDST_CMD_NACCESS		0xf
+#define V_FW_LDST_CMD_NACCESS(x)	((x) << S_FW_LDST_CMD_NACCESS)
+#define G_FW_LDST_CMD_NACCESS(x)	\
+    (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS)
+
+#define S_FW_LDST_CMD_NSET	14
+#define M_FW_LDST_CMD_NSET	0x3
+#define V_FW_LDST_CMD_NSET(x)	((x) << S_FW_LDST_CMD_NSET)
+#define G_FW_LDST_CMD_NSET(x)	\
+    (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET)
+
+#define S_FW_LDST_CMD_PID	6
+#define M_FW_LDST_CMD_PID	0x3
+#define V_FW_LDST_CMD_PID(x)	((x) << S_FW_LDST_CMD_PID)
+#define G_FW_LDST_CMD_PID(x)	\
+    (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID)
+
+struct fw_reset_cmd {
+	__be32 op_to_write;
+	__be32 retval_len16;
+	__be32 val;
+	__be32 halt_pkd;
+};
+
+#define S_FW_RESET_CMD_HALT	31
+#define M_FW_RESET_CMD_HALT	0x1
+#define V_FW_RESET_CMD_HALT(x)	((x) << S_FW_RESET_CMD_HALT)
+#define G_FW_RESET_CMD_HALT(x)	\
+    (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
+#define F_FW_RESET_CMD_HALT	V_FW_RESET_CMD_HALT(1U)
+
+enum {
+	FW_HELLO_CMD_STAGE_OS		= 0,
+	FW_HELLO_CMD_STAGE_PREOS0	= 1,
+	FW_HELLO_CMD_STAGE_PREOS1	= 2,
+	FW_HELLO_CMD_STAGE_POSTOS	= 3,
+};
+
+struct fw_hello_cmd {
+	__be32 op_to_write;
+	__be32 retval_len16;
+	__be32 err_to_clearinit;
+	__be32 fwrev;
+};
+
+#define S_FW_HELLO_CMD_ERR	31
+#define M_FW_HELLO_CMD_ERR	0x1
+#define V_FW_HELLO_CMD_ERR(x)	((x) << S_FW_HELLO_CMD_ERR)
+#define G_FW_HELLO_CMD_ERR(x)	\
+    (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
+#define F_FW_HELLO_CMD_ERR	V_FW_HELLO_CMD_ERR(1U)
+
+#define S_FW_HELLO_CMD_INIT	30
+#define M_FW_HELLO_CMD_INIT	0x1
+#define V_FW_HELLO_CMD_INIT(x)	((x) << S_FW_HELLO_CMD_INIT)
+#define G_FW_HELLO_CMD_INIT(x)	\
+    (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
+#define F_FW_HELLO_CMD_INIT	V_FW_HELLO_CMD_INIT(1U)
+
+#define S_FW_HELLO_CMD_MASTERDIS	29
+#define M_FW_HELLO_CMD_MASTERDIS	0x1
+#define V_FW_HELLO_CMD_MASTERDIS(x)	((x) << S_FW_HELLO_CMD_MASTERDIS)
+#define G_FW_HELLO_CMD_MASTERDIS(x)	\
+    (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
+#define F_FW_HELLO_CMD_MASTERDIS	V_FW_HELLO_CMD_MASTERDIS(1U)
+
+#define S_FW_HELLO_CMD_MASTERFORCE	28
+#define M_FW_HELLO_CMD_MASTERFORCE	0x1
+#define V_FW_HELLO_CMD_MASTERFORCE(x)	((x) << S_FW_HELLO_CMD_MASTERFORCE)
+#define G_FW_HELLO_CMD_MASTERFORCE(x)	\
+    (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
+#define F_FW_HELLO_CMD_MASTERFORCE	V_FW_HELLO_CMD_MASTERFORCE(1U)
+
+#define S_FW_HELLO_CMD_MBMASTER		24
+#define M_FW_HELLO_CMD_MBMASTER		0xf
+#define V_FW_HELLO_CMD_MBMASTER(x)	((x) << S_FW_HELLO_CMD_MBMASTER)
+#define G_FW_HELLO_CMD_MBMASTER(x)	\
+    (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
+
+#define S_FW_HELLO_CMD_MBASYNCNOTINT	23
+#define M_FW_HELLO_CMD_MBASYNCNOTINT	0x1
+#define V_FW_HELLO_CMD_MBASYNCNOTINT(x)	((x) << S_FW_HELLO_CMD_MBASYNCNOTINT)
+#define G_FW_HELLO_CMD_MBASYNCNOTINT(x)	\
+    (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT)
+#define F_FW_HELLO_CMD_MBASYNCNOTINT	V_FW_HELLO_CMD_MBASYNCNOTINT(1U)
+
+#define S_FW_HELLO_CMD_MBASYNCNOT	20
+#define M_FW_HELLO_CMD_MBASYNCNOT	0x7
+#define V_FW_HELLO_CMD_MBASYNCNOT(x)	((x) << S_FW_HELLO_CMD_MBASYNCNOT)
+#define G_FW_HELLO_CMD_MBASYNCNOT(x)	\
+    (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
+
+#define S_FW_HELLO_CMD_STAGE	17
+#define M_FW_HELLO_CMD_STAGE	0x7
+#define V_FW_HELLO_CMD_STAGE(x)	((x) << S_FW_HELLO_CMD_STAGE)
+#define G_FW_HELLO_CMD_STAGE(x)	\
+    (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
+
+#define S_FW_HELLO_CMD_CLEARINIT	16
+#define M_FW_HELLO_CMD_CLEARINIT	0x1
+#define V_FW_HELLO_CMD_CLEARINIT(x)	((x) << S_FW_HELLO_CMD_CLEARINIT)
+#define G_FW_HELLO_CMD_CLEARINIT(x)	\
+    (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
+#define F_FW_HELLO_CMD_CLEARINIT	V_FW_HELLO_CMD_CLEARINIT(1U)
+
+struct fw_bye_cmd {
+	__be32 op_to_write;
+	__be32 retval_len16;
+	__be64 r3;
+};
+
+struct fw_initialize_cmd {
+	__be32 op_to_write;
+	__be32 retval_len16;
+	__be64 r3;
+};
+
+enum fw_caps_config_hm {
+	FW_CAPS_CONFIG_HM_PCIE		= 0x00000001,
+	FW_CAPS_CONFIG_HM_PL		= 0x00000002,
+	FW_CAPS_CONFIG_HM_SGE		= 0x00000004,
+	FW_CAPS_CONFIG_HM_CIM		= 0x00000008,
+	FW_CAPS_CONFIG_HM_ULPTX		= 0x00000010,
+	FW_CAPS_CONFIG_HM_TP		= 0x00000020,
+	FW_CAPS_CONFIG_HM_ULPRX		= 0x00000040,
+	FW_CAPS_CONFIG_HM_PMRX		= 0x00000080,
+	FW_CAPS_CONFIG_HM_PMTX		= 0x00000100,
+	FW_CAPS_CONFIG_HM_MC		= 0x00000200,
+	FW_CAPS_CONFIG_HM_LE		= 0x00000400,
+	FW_CAPS_CONFIG_HM_MPS		= 0x00000800,
+	FW_CAPS_CONFIG_HM_XGMAC		= 0x00001000,
+	FW_CAPS_CONFIG_HM_CPLSWITCH	= 0x00002000,
+	FW_CAPS_CONFIG_HM_T4DBG		= 0x00004000,
+	FW_CAPS_CONFIG_HM_MI		= 0x00008000,
+	FW_CAPS_CONFIG_HM_I2CM		= 0x00010000,
+	FW_CAPS_CONFIG_HM_NCSI		= 0x00020000,
+	FW_CAPS_CONFIG_HM_SMB		= 0x00040000,
+	FW_CAPS_CONFIG_HM_MA		= 0x00080000,
+	FW_CAPS_CONFIG_HM_EDRAM		= 0x00100000,
+	FW_CAPS_CONFIG_HM_PMU		= 0x00200000,
+	FW_CAPS_CONFIG_HM_UART		= 0x00400000,
+	FW_CAPS_CONFIG_HM_SF		= 0x00800000,
+};
+
+/*
+ * The VF Register Map.
+ *
+ * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local
+ * bus module (PL) and CPU Interface Module (CIM) components are mapped via
+ * the Slice to Module Map Table (see below) in the Physical Function Register
+ * Map.  The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base
+ * and Offset registers in the PF Register Map.  The MBDATA base address is
+ * quite constrained as it determines the Mailbox Data addresses for both PFs
+ * and VFs, and therefore must fit in both the VF and PF Register Maps without
+ * overlapping other registers.
+ */
+#define FW_T4VF_SGE_BASE_ADDR      0x0000
+#define FW_T4VF_MPS_BASE_ADDR      0x0100
+#define FW_T4VF_PL_BASE_ADDR       0x0200
+#define FW_T4VF_MBDATA_BASE_ADDR   0x0240
+#define FW_T4VF_CIM_BASE_ADDR      0x0300
+
+#define FW_T4VF_REGMAP_START       0x0000
+#define FW_T4VF_REGMAP_SIZE        0x0400
+
+enum fw_caps_config_nbm {
+	FW_CAPS_CONFIG_NBM_IPMI		= 0x00000001,
+	FW_CAPS_CONFIG_NBM_NCSI		= 0x00000002,
+};
+
+enum fw_caps_config_link {
+	FW_CAPS_CONFIG_LINK_PPP		= 0x00000001,
+	FW_CAPS_CONFIG_LINK_QFC		= 0x00000002,
+	FW_CAPS_CONFIG_LINK_DCBX	= 0x00000004,
+};
+
+enum fw_caps_config_switch {
+	FW_CAPS_CONFIG_SWITCH_INGRESS	= 0x00000001,
+	FW_CAPS_CONFIG_SWITCH_EGRESS	= 0x00000002,
+};
+
+enum fw_caps_config_nic {
+	FW_CAPS_CONFIG_NIC		= 0x00000001,
+	FW_CAPS_CONFIG_NIC_VM		= 0x00000002,
+	FW_CAPS_CONFIG_NIC_IDS		= 0x00000004,
+	FW_CAPS_CONFIG_NIC_UM		= 0x00000008,
+	FW_CAPS_CONFIG_NIC_UM_ISGL	= 0x00000010,
+	FW_CAPS_CONFIG_NIC_HASHFILTER	= 0x00000020,
+	FW_CAPS_CONFIG_NIC_ETHOFLD	= 0x00000040,
+};
+
+enum fw_caps_config_toe {
+	FW_CAPS_CONFIG_TOE		= 0x00000001,
+};
+
+enum fw_caps_config_rdma {
+	FW_CAPS_CONFIG_RDMA_RDDP	= 0x00000001,
+	FW_CAPS_CONFIG_RDMA_RDMAC	= 0x00000002,
+};
+
+enum fw_caps_config_iscsi {
+	FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
+	FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
+	FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
+	FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
+	FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010,
+	FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020,
+};
+
+enum fw_caps_config_fcoe {
+	FW_CAPS_CONFIG_FCOE_INITIATOR	= 0x00000001,
+	FW_CAPS_CONFIG_FCOE_TARGET	= 0x00000002,
+	FW_CAPS_CONFIG_FCOE_CTRL_OFLD   = 0x00000004,
+	FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008,
+	FW_CAPS_CONFIG_POFCOE_TARGET    = 0x00000010,
+};
+
+enum fw_memtype_cf {
+	FW_MEMTYPE_CF_EDC0		= FW_MEMTYPE_EDC0,
+	FW_MEMTYPE_CF_EDC1		= FW_MEMTYPE_EDC1,
+	FW_MEMTYPE_CF_EXTMEM		= FW_MEMTYPE_EXTMEM,
+	FW_MEMTYPE_CF_FLASH		= FW_MEMTYPE_FLASH,
+	FW_MEMTYPE_CF_INTERNAL		= FW_MEMTYPE_INTERNAL,
+	FW_MEMTYPE_CF_EXTMEM1		= FW_MEMTYPE_EXTMEM1,
+};
+
+struct fw_caps_config_cmd {
+	__be32 op_to_write;
+	__be32 cfvalid_to_len16;
+	__be32 r2;
+	__be32 hwmbitmap;
+	__be16 nbmcaps;
+	__be16 linkcaps;
+	__be16 switchcaps;
+	__be16 r3;
+	__be16 niccaps;
+	__be16 toecaps;
+	__be16 rdmacaps;
+	__be16 r4;
+	__be16 iscsicaps;
+	__be16 fcoecaps;
+	__be32 cfcsum;
+	__be32 finiver;
+	__be32 finicsum;
+};
+
+#define S_FW_CAPS_CONFIG_CMD_CFVALID	27
+#define M_FW_CAPS_CONFIG_CMD_CFVALID	0x1
+#define V_FW_CAPS_CONFIG_CMD_CFVALID(x)	((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
+#define G_FW_CAPS_CONFIG_CMD_CFVALID(x)	\
+    (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
+#define F_FW_CAPS_CONFIG_CMD_CFVALID	V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
+
+#define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF		24
+#define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF		0x7
+#define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x)	\
+    ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
+#define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x)	\
+    (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
+     M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
+
+#define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF	16
+#define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF	0xff
+#define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x)	\
+    ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
+#define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x)	\
+    (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
+     M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
+
+/*
+ * params command mnemonics
+ */
+enum fw_params_mnem {
+	FW_PARAMS_MNEM_DEV		= 1,	/* device params */
+	FW_PARAMS_MNEM_PFVF		= 2,	/* function params */
+	FW_PARAMS_MNEM_REG		= 3,	/* limited register access */
+	FW_PARAMS_MNEM_DMAQ		= 4,	/* dma queue params */
+	FW_PARAMS_MNEM_LAST
+};
+
+/*
+ * device parameters
+ */
+enum fw_params_param_dev {
+	FW_PARAMS_PARAM_DEV_CCLK	= 0x00, /* chip core clock in khz */
+	FW_PARAMS_PARAM_DEV_PORTVEC	= 0x01, /* the port vector */
+	FW_PARAMS_PARAM_DEV_NTID	= 0x02, /* reads the number of TIDs
+						 * allocated by the device's
+						 * Lookup Engine
+						 */
+	FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
+	FW_PARAMS_PARAM_DEV_INTFVER_NIC	= 0x04,
+	FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05,
+	FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06,
+	FW_PARAMS_PARAM_DEV_INTFVER_RI	= 0x07,
+	FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08,
+	FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09,
+	FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A,
+	FW_PARAMS_PARAM_DEV_FWREV	= 0x0B,
+	FW_PARAMS_PARAM_DEV_TPREV	= 0x0C,
+	FW_PARAMS_PARAM_DEV_CF		= 0x0D,
+	FW_PARAMS_PARAM_DEV_BYPASS	= 0x0E,
+	FW_PARAMS_PARAM_DEV_PHYFW	= 0x0F,
+	FW_PARAMS_PARAM_DEV_LOAD	= 0x10,
+	FW_PARAMS_PARAM_DEV_DIAG	= 0x11,
+	FW_PARAMS_PARAM_DEV_UCLK	= 0x12, /* uP clock in khz */
+	FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD
+						 */
+	FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD
+						 */
+	FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15,
+	FW_PARAMS_PARAM_DEV_MCINIT	= 0x16,
+	FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
+};
+
+/*
+ * physical and virtual function parameters
+ */
+enum fw_params_param_pfvf {
+	FW_PARAMS_PARAM_PFVF_RWXCAPS	= 0x00,
+	FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
+	FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
+	FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
+	FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
+	FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
+	FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
+	FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
+	FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
+	FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
+	FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
+	FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
+	FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
+	FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
+	FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
+	FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
+	FW_PARAMS_PARAM_PFVF_RQ_END	= 0x10,
+	FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
+	FW_PARAMS_PARAM_PFVF_PBL_END	= 0x12,
+	FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
+	FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
+	FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
+	FW_PARAMS_PARAM_PFVF_SQRQ_END	= 0x16,
+	FW_PARAMS_PARAM_PFVF_CQ_START	= 0x17,
+	FW_PARAMS_PARAM_PFVF_CQ_END	= 0x18,
+	FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
+	FW_PARAMS_PARAM_PFVF_VIID	= 0x24,
+	FW_PARAMS_PARAM_PFVF_CPMASK	= 0x25,
+	FW_PARAMS_PARAM_PFVF_OCQ_START	= 0x26,
+	FW_PARAMS_PARAM_PFVF_OCQ_END	= 0x27,
+	FW_PARAMS_PARAM_PFVF_CONM_MAP   = 0x28,
+	FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
+	FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
+	FW_PARAMS_PARAM_PFVF_EQ_START	= 0x2B,
+	FW_PARAMS_PARAM_PFVF_EQ_END	= 0x2C,
+	FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
+	FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
+	FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F,
+	FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
+	FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31
+};
+
+/*
+ * dma queue parameters
+ */
+enum fw_params_param_dmaq {
+	FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
+	FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
+	FW_PARAMS_PARAM_DMAQ_IQ_INTIDX	= 0x02,
+	FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
+	FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
+	FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
+	FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
+	FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20,
+};
+
+/*
+ * dev bypass parameters; actions and modes
+ */
+enum fw_params_param_dev_bypass {
+
+	/* actions
+	 */
+	FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00,
+	FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01,
+
+	/* modes
+	 */
+	FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00,
+	FW_PARAMS_PARAM_DEV_BYPASS_DROP	= 0x1,
+	FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2,
+};
+
+enum fw_params_phyfw_actions {
+	FW_PARAMS_PARAM_PHYFW_DOWNLOAD	= 0x00,
+	FW_PARAMS_PARAM_PHYFW_VERSION	= 0x01,
+};
+
+enum fw_params_param_dev_diag {
+	FW_PARAM_DEV_DIAG_TMP = 0x00,
+	FW_PARAM_DEV_DIAG_VDD = 0x01,
+};
+
+#define S_FW_PARAMS_MNEM	24
+#define M_FW_PARAMS_MNEM	0xff
+#define V_FW_PARAMS_MNEM(x)	((x) << S_FW_PARAMS_MNEM)
+#define G_FW_PARAMS_MNEM(x)	\
+    (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
+
+#define S_FW_PARAMS_PARAM_X	16
+#define M_FW_PARAMS_PARAM_X	0xff
+#define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
+#define G_FW_PARAMS_PARAM_X(x) \
+    (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
+
+#define S_FW_PARAMS_PARAM_Y	8
+#define M_FW_PARAMS_PARAM_Y	0xff
+#define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
+#define G_FW_PARAMS_PARAM_Y(x) \
+    (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
+
+#define S_FW_PARAMS_PARAM_Z	0
+#define M_FW_PARAMS_PARAM_Z	0xff
+#define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
+#define G_FW_PARAMS_PARAM_Z(x) \
+    (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
+
+#define S_FW_PARAMS_PARAM_XYZ	0
+#define M_FW_PARAMS_PARAM_XYZ	0xffffff
+#define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
+#define G_FW_PARAMS_PARAM_XYZ(x) \
+    (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ)
+
+#define S_FW_PARAMS_PARAM_YZ	0
+#define M_FW_PARAMS_PARAM_YZ	0xffff
+#define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
+#define G_FW_PARAMS_PARAM_YZ(x) \
+    (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
+
+struct fw_params_cmd {
+	__be32 op_to_vfn;
+	__be32 retval_len16;
+	struct fw_params_param {
+		__be32 mnem;
+		__be32 val;
+	} param[7];
+};
+
+#define S_FW_PARAMS_CMD_PFN	8
+#define M_FW_PARAMS_CMD_PFN	0x7
+#define V_FW_PARAMS_CMD_PFN(x)	((x) << S_FW_PARAMS_CMD_PFN)
+#define G_FW_PARAMS_CMD_PFN(x)	\
+    (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
+
+#define S_FW_PARAMS_CMD_VFN	0
+#define M_FW_PARAMS_CMD_VFN	0xff
+#define V_FW_PARAMS_CMD_VFN(x)	((x) << S_FW_PARAMS_CMD_VFN)
+#define G_FW_PARAMS_CMD_VFN(x)	\
+    (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
+
+struct fw_pfvf_cmd {
+	__be32 op_to_vfn;
+	__be32 retval_len16;
+	__be32 niqflint_niq;
+	__be32 type_to_neq;
+	__be32 tc_to_nexactf;
+	__be32 r_caps_to_nethctrl;
+	__be16 nricq;
+	__be16 nriqp;
+	__be32 r4;
+};
+
+#define S_FW_PFVF_CMD_PFN	8
+#define M_FW_PFVF_CMD_PFN	0x7
+#define V_FW_PFVF_CMD_PFN(x)	((x) << S_FW_PFVF_CMD_PFN)
+#define G_FW_PFVF_CMD_PFN(x)	\
+    (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN)
+
+#define S_FW_PFVF_CMD_VFN	0
+#define M_FW_PFVF_CMD_VFN	0xff
+#define V_FW_PFVF_CMD_VFN(x)	((x) << S_FW_PFVF_CMD_VFN)
+#define G_FW_PFVF_CMD_VFN(x)	\
+    (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN)
+
+#define S_FW_PFVF_CMD_NIQFLINT		20
+#define M_FW_PFVF_CMD_NIQFLINT		0xfff
+#define V_FW_PFVF_CMD_NIQFLINT(x)	((x) << S_FW_PFVF_CMD_NIQFLINT)
+#define G_FW_PFVF_CMD_NIQFLINT(x)	\
+    (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
+
+#define S_FW_PFVF_CMD_NIQ	0
+#define M_FW_PFVF_CMD_NIQ	0xfffff
+#define V_FW_PFVF_CMD_NIQ(x)	((x) << S_FW_PFVF_CMD_NIQ)
+#define G_FW_PFVF_CMD_NIQ(x)	\
+    (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
+
+#define S_FW_PFVF_CMD_TYPE	31
+#define M_FW_PFVF_CMD_TYPE	0x1
+#define V_FW_PFVF_CMD_TYPE(x)	((x) << S_FW_PFVF_CMD_TYPE)
+#define G_FW_PFVF_CMD_TYPE(x)	\
+    (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE)
+#define F_FW_PFVF_CMD_TYPE	V_FW_PFVF_CMD_TYPE(1U)
+
+#define S_FW_PFVF_CMD_CMASK	24
+#define M_FW_PFVF_CMD_CMASK	0xf
+#define V_FW_PFVF_CMD_CMASK(x)	((x) << S_FW_PFVF_CMD_CMASK)
+#define G_FW_PFVF_CMD_CMASK(x)	\
+    (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK)
+
+#define S_FW_PFVF_CMD_PMASK	20
+#define M_FW_PFVF_CMD_PMASK	0xf
+#define V_FW_PFVF_CMD_PMASK(x)	((x) << S_FW_PFVF_CMD_PMASK)
+#define G_FW_PFVF_CMD_PMASK(x)	\
+    (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
+
+#define S_FW_PFVF_CMD_NEQ	0
+#define M_FW_PFVF_CMD_NEQ	0xfffff
+#define V_FW_PFVF_CMD_NEQ(x)	((x) << S_FW_PFVF_CMD_NEQ)
+#define G_FW_PFVF_CMD_NEQ(x)	\
+    (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
+
+#define S_FW_PFVF_CMD_TC	24
+#define M_FW_PFVF_CMD_TC	0xff
+#define V_FW_PFVF_CMD_TC(x)	((x) << S_FW_PFVF_CMD_TC)
+#define G_FW_PFVF_CMD_TC(x)	(((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
+
+#define S_FW_PFVF_CMD_NVI	16
+#define M_FW_PFVF_CMD_NVI	0xff
+#define V_FW_PFVF_CMD_NVI(x)	((x) << S_FW_PFVF_CMD_NVI)
+#define G_FW_PFVF_CMD_NVI(x)	\
+    (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
+
+#define S_FW_PFVF_CMD_NEXACTF		0
+#define M_FW_PFVF_CMD_NEXACTF		0xffff
+#define V_FW_PFVF_CMD_NEXACTF(x)	((x) << S_FW_PFVF_CMD_NEXACTF)
+#define G_FW_PFVF_CMD_NEXACTF(x)	\
+    (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
+
+#define S_FW_PFVF_CMD_R_CAPS	24
+#define M_FW_PFVF_CMD_R_CAPS	0xff
+#define V_FW_PFVF_CMD_R_CAPS(x)	((x) << S_FW_PFVF_CMD_R_CAPS)
+#define G_FW_PFVF_CMD_R_CAPS(x)	\
+    (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
+
+#define S_FW_PFVF_CMD_WX_CAPS		16
+#define M_FW_PFVF_CMD_WX_CAPS		0xff
+#define V_FW_PFVF_CMD_WX_CAPS(x)	((x) << S_FW_PFVF_CMD_WX_CAPS)
+#define G_FW_PFVF_CMD_WX_CAPS(x)	\
+    (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
+
+#define S_FW_PFVF_CMD_NETHCTRL		0
+#define M_FW_PFVF_CMD_NETHCTRL		0xffff
+#define V_FW_PFVF_CMD_NETHCTRL(x)	((x) << S_FW_PFVF_CMD_NETHCTRL)
+#define G_FW_PFVF_CMD_NETHCTRL(x)	\
+    (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
+
+/*
+ *	ingress queue type; the first 1K ingress queues can have associated 0,
+ *	1 or 2 free lists and an interrupt, all other ingress queues lack these
+ *	capabilities
+ */
+enum fw_iq_type {
+	FW_IQ_TYPE_FL_INT_CAP,
+	FW_IQ_TYPE_NO_FL_INT_CAP
+};
+
+struct fw_iq_cmd {
+	__be32 op_to_vfn;
+	__be32 alloc_to_len16;
+	__be16 physiqid;
+	__be16 iqid;
+	__be16 fl0id;
+	__be16 fl1id;
+	__be32 type_to_iqandstindex;
+	__be16 iqdroprss_to_iqesize;
+	__be16 iqsize;
+	__be64 iqaddr;
+	__be32 iqns_to_fl0congen;
+	__be16 fl0dcaen_to_fl0cidxfthresh;
+	__be16 fl0size;
+	__be64 fl0addr;
+	__be32 fl1cngchmap_to_fl1congen;
+	__be16 fl1dcaen_to_fl1cidxfthresh;
+	__be16 fl1size;
+	__be64 fl1addr;
+};
+
+#define S_FW_IQ_CMD_PFN		8
+#define M_FW_IQ_CMD_PFN		0x7
+#define V_FW_IQ_CMD_PFN(x)	((x) << S_FW_IQ_CMD_PFN)
+#define G_FW_IQ_CMD_PFN(x)	(((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
+
+#define S_FW_IQ_CMD_VFN		0
+#define M_FW_IQ_CMD_VFN		0xff
+#define V_FW_IQ_CMD_VFN(x)	((x) << S_FW_IQ_CMD_VFN)
+#define G_FW_IQ_CMD_VFN(x)	(((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
+
+#define S_FW_IQ_CMD_ALLOC	31
+#define M_FW_IQ_CMD_ALLOC	0x1
+#define V_FW_IQ_CMD_ALLOC(x)	((x) << S_FW_IQ_CMD_ALLOC)
+#define G_FW_IQ_CMD_ALLOC(x)	\
+    (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
+#define F_FW_IQ_CMD_ALLOC	V_FW_IQ_CMD_ALLOC(1U)
+
+#define S_FW_IQ_CMD_FREE	30
+#define M_FW_IQ_CMD_FREE	0x1
+#define V_FW_IQ_CMD_FREE(x)	((x) << S_FW_IQ_CMD_FREE)
+#define G_FW_IQ_CMD_FREE(x)	(((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
+#define F_FW_IQ_CMD_FREE	V_FW_IQ_CMD_FREE(1U)
+
+#define S_FW_IQ_CMD_MODIFY	29
+#define M_FW_IQ_CMD_MODIFY	0x1
+#define V_FW_IQ_CMD_MODIFY(x)	((x) << S_FW_IQ_CMD_MODIFY)
+#define G_FW_IQ_CMD_MODIFY(x)	\
+    (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY)
+#define F_FW_IQ_CMD_MODIFY	V_FW_IQ_CMD_MODIFY(1U)
+
+#define S_FW_IQ_CMD_IQSTART	28
+#define M_FW_IQ_CMD_IQSTART	0x1
+#define V_FW_IQ_CMD_IQSTART(x)	((x) << S_FW_IQ_CMD_IQSTART)
+#define G_FW_IQ_CMD_IQSTART(x)	\
+    (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
+#define F_FW_IQ_CMD_IQSTART	V_FW_IQ_CMD_IQSTART(1U)
+
+#define S_FW_IQ_CMD_IQSTOP	27
+#define M_FW_IQ_CMD_IQSTOP	0x1
+#define V_FW_IQ_CMD_IQSTOP(x)	((x) << S_FW_IQ_CMD_IQSTOP)
+#define G_FW_IQ_CMD_IQSTOP(x)	\
+    (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
+#define F_FW_IQ_CMD_IQSTOP	V_FW_IQ_CMD_IQSTOP(1U)
+
+#define S_FW_IQ_CMD_TYPE	29
+#define M_FW_IQ_CMD_TYPE	0x7
+#define V_FW_IQ_CMD_TYPE(x)	((x) << S_FW_IQ_CMD_TYPE)
+#define G_FW_IQ_CMD_TYPE(x)	(((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
+
+#define S_FW_IQ_CMD_IQASYNCH	28
+#define M_FW_IQ_CMD_IQASYNCH	0x1
+#define V_FW_IQ_CMD_IQASYNCH(x)	((x) << S_FW_IQ_CMD_IQASYNCH)
+#define G_FW_IQ_CMD_IQASYNCH(x)	\
+    (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
+#define F_FW_IQ_CMD_IQASYNCH	V_FW_IQ_CMD_IQASYNCH(1U)
+
+#define S_FW_IQ_CMD_VIID	16
+#define M_FW_IQ_CMD_VIID	0xfff
+#define V_FW_IQ_CMD_VIID(x)	((x) << S_FW_IQ_CMD_VIID)
+#define G_FW_IQ_CMD_VIID(x)	(((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
+
+#define S_FW_IQ_CMD_IQANDST	15
+#define M_FW_IQ_CMD_IQANDST	0x1
+#define V_FW_IQ_CMD_IQANDST(x)	((x) << S_FW_IQ_CMD_IQANDST)
+#define G_FW_IQ_CMD_IQANDST(x)	\
+    (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
+#define F_FW_IQ_CMD_IQANDST	V_FW_IQ_CMD_IQANDST(1U)
+
+#define S_FW_IQ_CMD_IQANUS	14
+#define M_FW_IQ_CMD_IQANUS	0x1
+#define V_FW_IQ_CMD_IQANUS(x)	((x) << S_FW_IQ_CMD_IQANUS)
+#define G_FW_IQ_CMD_IQANUS(x)	\
+    (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS)
+#define F_FW_IQ_CMD_IQANUS	V_FW_IQ_CMD_IQANUS(1U)
+
+#define S_FW_IQ_CMD_IQANUD	12
+#define M_FW_IQ_CMD_IQANUD	0x3
+#define V_FW_IQ_CMD_IQANUD(x)	((x) << S_FW_IQ_CMD_IQANUD)
+#define G_FW_IQ_CMD_IQANUD(x)	\
+    (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
+
+#define S_FW_IQ_CMD_IQANDSTINDEX	0
+#define M_FW_IQ_CMD_IQANDSTINDEX	0xfff
+#define V_FW_IQ_CMD_IQANDSTINDEX(x)	((x) << S_FW_IQ_CMD_IQANDSTINDEX)
+#define G_FW_IQ_CMD_IQANDSTINDEX(x)	\
+    (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
+
+#define S_FW_IQ_CMD_IQDROPRSS		15
+#define M_FW_IQ_CMD_IQDROPRSS		0x1
+#define V_FW_IQ_CMD_IQDROPRSS(x)	((x) << S_FW_IQ_CMD_IQDROPRSS)
+#define G_FW_IQ_CMD_IQDROPRSS(x)	\
+    (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS)
+#define F_FW_IQ_CMD_IQDROPRSS	V_FW_IQ_CMD_IQDROPRSS(1U)
+
+#define S_FW_IQ_CMD_IQGTSMODE		14
+#define M_FW_IQ_CMD_IQGTSMODE		0x1
+#define V_FW_IQ_CMD_IQGTSMODE(x)	((x) << S_FW_IQ_CMD_IQGTSMODE)
+#define G_FW_IQ_CMD_IQGTSMODE(x)	\
+    (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
+#define F_FW_IQ_CMD_IQGTSMODE	V_FW_IQ_CMD_IQGTSMODE(1U)
+
+#define S_FW_IQ_CMD_IQPCIECH	12
+#define M_FW_IQ_CMD_IQPCIECH	0x3
+#define V_FW_IQ_CMD_IQPCIECH(x)	((x) << S_FW_IQ_CMD_IQPCIECH)
+#define G_FW_IQ_CMD_IQPCIECH(x)	\
+    (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
+
+#define S_FW_IQ_CMD_IQDCAEN	11
+#define M_FW_IQ_CMD_IQDCAEN	0x1
+#define V_FW_IQ_CMD_IQDCAEN(x)	((x) << S_FW_IQ_CMD_IQDCAEN)
+#define G_FW_IQ_CMD_IQDCAEN(x)	\
+    (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN)
+#define F_FW_IQ_CMD_IQDCAEN	V_FW_IQ_CMD_IQDCAEN(1U)
+
+#define S_FW_IQ_CMD_IQDCACPU	6
+#define M_FW_IQ_CMD_IQDCACPU	0x1f
+#define V_FW_IQ_CMD_IQDCACPU(x)	((x) << S_FW_IQ_CMD_IQDCACPU)
+#define G_FW_IQ_CMD_IQDCACPU(x)	\
+    (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU)
+
+#define S_FW_IQ_CMD_IQINTCNTTHRESH	4
+#define M_FW_IQ_CMD_IQINTCNTTHRESH	0x3
+#define V_FW_IQ_CMD_IQINTCNTTHRESH(x)	((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
+#define G_FW_IQ_CMD_IQINTCNTTHRESH(x)	\
+    (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
+
+#define S_FW_IQ_CMD_IQO		3
+#define M_FW_IQ_CMD_IQO		0x1
+#define V_FW_IQ_CMD_IQO(x)	((x) << S_FW_IQ_CMD_IQO)
+#define G_FW_IQ_CMD_IQO(x)	(((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO)
+#define F_FW_IQ_CMD_IQO	V_FW_IQ_CMD_IQO(1U)
+
+#define S_FW_IQ_CMD_IQCPRIO	2
+#define M_FW_IQ_CMD_IQCPRIO	0x1
+#define V_FW_IQ_CMD_IQCPRIO(x)	((x) << S_FW_IQ_CMD_IQCPRIO)
+#define G_FW_IQ_CMD_IQCPRIO(x)	\
+    (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO)
+#define F_FW_IQ_CMD_IQCPRIO	V_FW_IQ_CMD_IQCPRIO(1U)
+
+#define S_FW_IQ_CMD_IQESIZE	0
+#define M_FW_IQ_CMD_IQESIZE	0x3
+#define V_FW_IQ_CMD_IQESIZE(x)	((x) << S_FW_IQ_CMD_IQESIZE)
+#define G_FW_IQ_CMD_IQESIZE(x)	\
+    (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
+
+#define S_FW_IQ_CMD_IQNS	31
+#define M_FW_IQ_CMD_IQNS	0x1
+#define V_FW_IQ_CMD_IQNS(x)	((x) << S_FW_IQ_CMD_IQNS)
+#define G_FW_IQ_CMD_IQNS(x)	(((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS)
+#define F_FW_IQ_CMD_IQNS	V_FW_IQ_CMD_IQNS(1U)
+
+#define S_FW_IQ_CMD_IQRO	30
+#define M_FW_IQ_CMD_IQRO	0x1
+#define V_FW_IQ_CMD_IQRO(x)	((x) << S_FW_IQ_CMD_IQRO)
+#define G_FW_IQ_CMD_IQRO(x)	(((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
+#define F_FW_IQ_CMD_IQRO	V_FW_IQ_CMD_IQRO(1U)
+
+#define S_FW_IQ_CMD_IQFLINTIQHSEN	28
+#define M_FW_IQ_CMD_IQFLINTIQHSEN	0x3
+#define V_FW_IQ_CMD_IQFLINTIQHSEN(x)	((x) << S_FW_IQ_CMD_IQFLINTIQHSEN)
+#define G_FW_IQ_CMD_IQFLINTIQHSEN(x)	\
+    (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN)
+
+#define S_FW_IQ_CMD_IQFLINTCONGEN	27
+#define M_FW_IQ_CMD_IQFLINTCONGEN	0x1
+#define V_FW_IQ_CMD_IQFLINTCONGEN(x)	((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
+#define G_FW_IQ_CMD_IQFLINTCONGEN(x)	\
+    (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
+#define F_FW_IQ_CMD_IQFLINTCONGEN	V_FW_IQ_CMD_IQFLINTCONGEN(1U)
+
+#define S_FW_IQ_CMD_IQFLINTISCSIC	26
+#define M_FW_IQ_CMD_IQFLINTISCSIC	0x1
+#define V_FW_IQ_CMD_IQFLINTISCSIC(x)	((x) << S_FW_IQ_CMD_IQFLINTISCSIC)
+#define G_FW_IQ_CMD_IQFLINTISCSIC(x)	\
+    (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC)
+#define F_FW_IQ_CMD_IQFLINTISCSIC	V_FW_IQ_CMD_IQFLINTISCSIC(1U)
+
+#define S_FW_IQ_CMD_FL0CNGCHMAP		20
+#define M_FW_IQ_CMD_FL0CNGCHMAP		0xf
+#define V_FW_IQ_CMD_FL0CNGCHMAP(x)	((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
+#define G_FW_IQ_CMD_FL0CNGCHMAP(x)	\
+    (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
+
+#define S_FW_IQ_CMD_FL0CACHELOCK	15
+#define M_FW_IQ_CMD_FL0CACHELOCK	0x1
+#define V_FW_IQ_CMD_FL0CACHELOCK(x)	((x) << S_FW_IQ_CMD_FL0CACHELOCK)
+#define G_FW_IQ_CMD_FL0CACHELOCK(x)	\
+    (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK)
+#define F_FW_IQ_CMD_FL0CACHELOCK	V_FW_IQ_CMD_FL0CACHELOCK(1U)
+
+#define S_FW_IQ_CMD_FL0DBP	14
+#define M_FW_IQ_CMD_FL0DBP	0x1
+#define V_FW_IQ_CMD_FL0DBP(x)	((x) << S_FW_IQ_CMD_FL0DBP)
+#define G_FW_IQ_CMD_FL0DBP(x)	\
+    (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP)
+#define F_FW_IQ_CMD_FL0DBP	V_FW_IQ_CMD_FL0DBP(1U)
+
+#define S_FW_IQ_CMD_FL0DATANS		13
+#define M_FW_IQ_CMD_FL0DATANS		0x1
+#define V_FW_IQ_CMD_FL0DATANS(x)	((x) << S_FW_IQ_CMD_FL0DATANS)
+#define G_FW_IQ_CMD_FL0DATANS(x)	\
+    (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS)
+#define F_FW_IQ_CMD_FL0DATANS	V_FW_IQ_CMD_FL0DATANS(1U)
+
+#define S_FW_IQ_CMD_FL0DATARO		12
+#define M_FW_IQ_CMD_FL0DATARO		0x1
+#define V_FW_IQ_CMD_FL0DATARO(x)	((x) << S_FW_IQ_CMD_FL0DATARO)
+#define G_FW_IQ_CMD_FL0DATARO(x)	\
+    (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
+#define F_FW_IQ_CMD_FL0DATARO	V_FW_IQ_CMD_FL0DATARO(1U)
+
+#define S_FW_IQ_CMD_FL0CONGCIF		11
+#define M_FW_IQ_CMD_FL0CONGCIF		0x1
+#define V_FW_IQ_CMD_FL0CONGCIF(x)	((x) << S_FW_IQ_CMD_FL0CONGCIF)
+#define G_FW_IQ_CMD_FL0CONGCIF(x)	\
+    (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
+#define F_FW_IQ_CMD_FL0CONGCIF	V_FW_IQ_CMD_FL0CONGCIF(1U)
+
+#define S_FW_IQ_CMD_FL0ONCHIP		10
+#define M_FW_IQ_CMD_FL0ONCHIP		0x1
+#define V_FW_IQ_CMD_FL0ONCHIP(x)	((x) << S_FW_IQ_CMD_FL0ONCHIP)
+#define G_FW_IQ_CMD_FL0ONCHIP(x)	\
+    (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP)
+#define F_FW_IQ_CMD_FL0ONCHIP	V_FW_IQ_CMD_FL0ONCHIP(1U)
+
+#define S_FW_IQ_CMD_FL0STATUSPGNS	9
+#define M_FW_IQ_CMD_FL0STATUSPGNS	0x1
+#define V_FW_IQ_CMD_FL0STATUSPGNS(x)	((x) << S_FW_IQ_CMD_FL0STATUSPGNS)
+#define G_FW_IQ_CMD_FL0STATUSPGNS(x)	\
+    (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS)
+#define F_FW_IQ_CMD_FL0STATUSPGNS	V_FW_IQ_CMD_FL0STATUSPGNS(1U)
+
+#define S_FW_IQ_CMD_FL0STATUSPGRO	8
+#define M_FW_IQ_CMD_FL0STATUSPGRO	0x1
+#define V_FW_IQ_CMD_FL0STATUSPGRO(x)	((x) << S_FW_IQ_CMD_FL0STATUSPGRO)
+#define G_FW_IQ_CMD_FL0STATUSPGRO(x)	\
+    (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO)
+#define F_FW_IQ_CMD_FL0STATUSPGRO	V_FW_IQ_CMD_FL0STATUSPGRO(1U)
+
+#define S_FW_IQ_CMD_FL0FETCHNS		7
+#define M_FW_IQ_CMD_FL0FETCHNS		0x1
+#define V_FW_IQ_CMD_FL0FETCHNS(x)	((x) << S_FW_IQ_CMD_FL0FETCHNS)
+#define G_FW_IQ_CMD_FL0FETCHNS(x)	\
+    (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS)
+#define F_FW_IQ_CMD_FL0FETCHNS	V_FW_IQ_CMD_FL0FETCHNS(1U)
+
+#define S_FW_IQ_CMD_FL0FETCHRO		6
+#define M_FW_IQ_CMD_FL0FETCHRO		0x1
+#define V_FW_IQ_CMD_FL0FETCHRO(x)	((x) << S_FW_IQ_CMD_FL0FETCHRO)
+#define G_FW_IQ_CMD_FL0FETCHRO(x)	\
+    (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
+#define F_FW_IQ_CMD_FL0FETCHRO	V_FW_IQ_CMD_FL0FETCHRO(1U)
+
+#define S_FW_IQ_CMD_FL0HOSTFCMODE	4
+#define M_FW_IQ_CMD_FL0HOSTFCMODE	0x3
+#define V_FW_IQ_CMD_FL0HOSTFCMODE(x)	((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
+#define G_FW_IQ_CMD_FL0HOSTFCMODE(x)	\
+    (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
+
+#define S_FW_IQ_CMD_FL0CPRIO	3
+#define M_FW_IQ_CMD_FL0CPRIO	0x1
+#define V_FW_IQ_CMD_FL0CPRIO(x)	((x) << S_FW_IQ_CMD_FL0CPRIO)
+#define G_FW_IQ_CMD_FL0CPRIO(x)	\
+    (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO)
+#define F_FW_IQ_CMD_FL0CPRIO	V_FW_IQ_CMD_FL0CPRIO(1U)
+
+#define S_FW_IQ_CMD_FL0PADEN	2
+#define M_FW_IQ_CMD_FL0PADEN	0x1
+#define V_FW_IQ_CMD_FL0PADEN(x)	((x) << S_FW_IQ_CMD_FL0PADEN)
+#define G_FW_IQ_CMD_FL0PADEN(x)	\
+    (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
+#define F_FW_IQ_CMD_FL0PADEN	V_FW_IQ_CMD_FL0PADEN(1U)
+
+#define S_FW_IQ_CMD_FL0PACKEN		1
+#define M_FW_IQ_CMD_FL0PACKEN		0x1
+#define V_FW_IQ_CMD_FL0PACKEN(x)	((x) << S_FW_IQ_CMD_FL0PACKEN)
+#define G_FW_IQ_CMD_FL0PACKEN(x)	\
+    (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
+#define F_FW_IQ_CMD_FL0PACKEN	V_FW_IQ_CMD_FL0PACKEN(1U)
+
+#define S_FW_IQ_CMD_FL0CONGEN		0
+#define M_FW_IQ_CMD_FL0CONGEN		0x1
+#define V_FW_IQ_CMD_FL0CONGEN(x)	((x) << S_FW_IQ_CMD_FL0CONGEN)
+#define G_FW_IQ_CMD_FL0CONGEN(x)	\
+    (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
+#define F_FW_IQ_CMD_FL0CONGEN	V_FW_IQ_CMD_FL0CONGEN(1U)
+
+#define S_FW_IQ_CMD_FL0DCAEN	15
+#define M_FW_IQ_CMD_FL0DCAEN	0x1
+#define V_FW_IQ_CMD_FL0DCAEN(x)	((x) << S_FW_IQ_CMD_FL0DCAEN)
+#define G_FW_IQ_CMD_FL0DCAEN(x)	\
+    (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN)
+#define F_FW_IQ_CMD_FL0DCAEN	V_FW_IQ_CMD_FL0DCAEN(1U)
+
+#define S_FW_IQ_CMD_FL0DCACPU		10
+#define M_FW_IQ_CMD_FL0DCACPU		0x1f
+#define V_FW_IQ_CMD_FL0DCACPU(x)	((x) << S_FW_IQ_CMD_FL0DCACPU)
+#define G_FW_IQ_CMD_FL0DCACPU(x)	\
+    (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU)
+
+#define S_FW_IQ_CMD_FL0FBMIN	7
+#define M_FW_IQ_CMD_FL0FBMIN	0x7
+#define V_FW_IQ_CMD_FL0FBMIN(x)	((x) << S_FW_IQ_CMD_FL0FBMIN)
+#define G_FW_IQ_CMD_FL0FBMIN(x)	\
+    (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
+
+#define S_FW_IQ_CMD_FL0FBMAX	4
+#define M_FW_IQ_CMD_FL0FBMAX	0x7
+#define V_FW_IQ_CMD_FL0FBMAX(x)	((x) << S_FW_IQ_CMD_FL0FBMAX)
+#define G_FW_IQ_CMD_FL0FBMAX(x)	\
+    (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
+
+#define S_FW_IQ_CMD_FL0CIDXFTHRESHO	3
+#define M_FW_IQ_CMD_FL0CIDXFTHRESHO	0x1
+#define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x)	((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO)
+#define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x)	\
+    (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO)
+#define F_FW_IQ_CMD_FL0CIDXFTHRESHO	V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U)
+
+#define S_FW_IQ_CMD_FL0CIDXFTHRESH	0
+#define M_FW_IQ_CMD_FL0CIDXFTHRESH	0x7
+#define V_FW_IQ_CMD_FL0CIDXFTHRESH(x)	((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH)
+#define G_FW_IQ_CMD_FL0CIDXFTHRESH(x)	\
+    (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH)
+
+#define S_FW_IQ_CMD_FL1CNGCHMAP		20
+#define M_FW_IQ_CMD_FL1CNGCHMAP		0xf
+#define V_FW_IQ_CMD_FL1CNGCHMAP(x)	((x) << S_FW_IQ_CMD_FL1CNGCHMAP)
+#define G_FW_IQ_CMD_FL1CNGCHMAP(x)	\
+    (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP)
+
+#define S_FW_IQ_CMD_FL1CACHELOCK	15
+#define M_FW_IQ_CMD_FL1CACHELOCK	0x1
+#define V_FW_IQ_CMD_FL1CACHELOCK(x)	((x) << S_FW_IQ_CMD_FL1CACHELOCK)
+#define G_FW_IQ_CMD_FL1CACHELOCK(x)	\
+    (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK)
+#define F_FW_IQ_CMD_FL1CACHELOCK	V_FW_IQ_CMD_FL1CACHELOCK(1U)
+
+#define S_FW_IQ_CMD_FL1DBP	14
+#define M_FW_IQ_CMD_FL1DBP	0x1
+#define V_FW_IQ_CMD_FL1DBP(x)	((x) << S_FW_IQ_CMD_FL1DBP)
+#define G_FW_IQ_CMD_FL1DBP(x)	\
+    (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP)
+#define F_FW_IQ_CMD_FL1DBP	V_FW_IQ_CMD_FL1DBP(1U)
+
+#define S_FW_IQ_CMD_FL1DATANS		13
+#define M_FW_IQ_CMD_FL1DATANS		0x1
+#define V_FW_IQ_CMD_FL1DATANS(x)	((x) << S_FW_IQ_CMD_FL1DATANS)
+#define G_FW_IQ_CMD_FL1DATANS(x)	\
+    (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS)
+#define F_FW_IQ_CMD_FL1DATANS	V_FW_IQ_CMD_FL1DATANS(1U)
+
+#define S_FW_IQ_CMD_FL1DATARO		12
+#define M_FW_IQ_CMD_FL1DATARO		0x1
+#define V_FW_IQ_CMD_FL1DATARO(x)	((x) << S_FW_IQ_CMD_FL1DATARO)
+#define G_FW_IQ_CMD_FL1DATARO(x)	\
+    (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO)
+#define F_FW_IQ_CMD_FL1DATARO	V_FW_IQ_CMD_FL1DATARO(1U)
+
+#define S_FW_IQ_CMD_FL1CONGCIF		11
+#define M_FW_IQ_CMD_FL1CONGCIF		0x1
+#define V_FW_IQ_CMD_FL1CONGCIF(x)	((x) << S_FW_IQ_CMD_FL1CONGCIF)
+#define G_FW_IQ_CMD_FL1CONGCIF(x)	\
+    (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF)
+#define F_FW_IQ_CMD_FL1CONGCIF	V_FW_IQ_CMD_FL1CONGCIF(1U)
+
+#define S_FW_IQ_CMD_FL1ONCHIP		10
+#define M_FW_IQ_CMD_FL1ONCHIP		0x1
+#define V_FW_IQ_CMD_FL1ONCHIP(x)	((x) << S_FW_IQ_CMD_FL1ONCHIP)
+#define G_FW_IQ_CMD_FL1ONCHIP(x)	\
+    (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP)
+#define F_FW_IQ_CMD_FL1ONCHIP	V_FW_IQ_CMD_FL1ONCHIP(1U)
+
+#define S_FW_IQ_CMD_FL1STATUSPGNS	9
+#define M_FW_IQ_CMD_FL1STATUSPGNS	0x1
+#define V_FW_IQ_CMD_FL1STATUSPGNS(x)	((x) << S_FW_IQ_CMD_FL1STATUSPGNS)
+#define G_FW_IQ_CMD_FL1STATUSPGNS(x)	\
+    (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS)
+#define F_FW_IQ_CMD_FL1STATUSPGNS	V_FW_IQ_CMD_FL1STATUSPGNS(1U)
+
+#define S_FW_IQ_CMD_FL1STATUSPGRO	8
+#define M_FW_IQ_CMD_FL1STATUSPGRO	0x1
+#define V_FW_IQ_CMD_FL1STATUSPGRO(x)	((x) << S_FW_IQ_CMD_FL1STATUSPGRO)
+#define G_FW_IQ_CMD_FL1STATUSPGRO(x)	\
+    (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO)
+#define F_FW_IQ_CMD_FL1STATUSPGRO	V_FW_IQ_CMD_FL1STATUSPGRO(1U)
+
+#define S_FW_IQ_CMD_FL1FETCHNS		7
+#define M_FW_IQ_CMD_FL1FETCHNS		0x1
+#define V_FW_IQ_CMD_FL1FETCHNS(x)	((x) << S_FW_IQ_CMD_FL1FETCHNS)
+#define G_FW_IQ_CMD_FL1FETCHNS(x)	\
+    (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS)
+#define F_FW_IQ_CMD_FL1FETCHNS	V_FW_IQ_CMD_FL1FETCHNS(1U)
+
+#define S_FW_IQ_CMD_FL1FETCHRO		6
+#define M_FW_IQ_CMD_FL1FETCHRO		0x1
+#define V_FW_IQ_CMD_FL1FETCHRO(x)	((x) << S_FW_IQ_CMD_FL1FETCHRO)
+#define G_FW_IQ_CMD_FL1FETCHRO(x)	\
+    (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO)
+#define F_FW_IQ_CMD_FL1FETCHRO	V_FW_IQ_CMD_FL1FETCHRO(1U)
+
+#define S_FW_IQ_CMD_FL1HOSTFCMODE	4
+#define M_FW_IQ_CMD_FL1HOSTFCMODE	0x3
+#define V_FW_IQ_CMD_FL1HOSTFCMODE(x)	((x) << S_FW_IQ_CMD_FL1HOSTFCMODE)
+#define G_FW_IQ_CMD_FL1HOSTFCMODE(x)	\
+    (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE)
+
+#define S_FW_IQ_CMD_FL1CPRIO	3
+#define M_FW_IQ_CMD_FL1CPRIO	0x1
+#define V_FW_IQ_CMD_FL1CPRIO(x)	((x) << S_FW_IQ_CMD_FL1CPRIO)
+#define G_FW_IQ_CMD_FL1CPRIO(x)	\
+    (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO)
+#define F_FW_IQ_CMD_FL1CPRIO	V_FW_IQ_CMD_FL1CPRIO(1U)
+
+#define S_FW_IQ_CMD_FL1PADEN	2
+#define M_FW_IQ_CMD_FL1PADEN	0x1
+#define V_FW_IQ_CMD_FL1PADEN(x)	((x) << S_FW_IQ_CMD_FL1PADEN)
+#define G_FW_IQ_CMD_FL1PADEN(x)	\
+    (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN)
+#define F_FW_IQ_CMD_FL1PADEN	V_FW_IQ_CMD_FL1PADEN(1U)
+
+#define S_FW_IQ_CMD_FL1PACKEN		1
+#define M_FW_IQ_CMD_FL1PACKEN		0x1
+#define V_FW_IQ_CMD_FL1PACKEN(x)	((x) << S_FW_IQ_CMD_FL1PACKEN)
+#define G_FW_IQ_CMD_FL1PACKEN(x)	\
+    (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN)
+#define F_FW_IQ_CMD_FL1PACKEN	V_FW_IQ_CMD_FL1PACKEN(1U)
+
+#define S_FW_IQ_CMD_FL1CONGEN		0
+#define M_FW_IQ_CMD_FL1CONGEN		0x1
+#define V_FW_IQ_CMD_FL1CONGEN(x)	((x) << S_FW_IQ_CMD_FL1CONGEN)
+#define G_FW_IQ_CMD_FL1CONGEN(x)	\
+    (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN)
+#define F_FW_IQ_CMD_FL1CONGEN	V_FW_IQ_CMD_FL1CONGEN(1U)
+
+#define S_FW_IQ_CMD_FL1DCAEN	15
+#define M_FW_IQ_CMD_FL1DCAEN	0x1
+#define V_FW_IQ_CMD_FL1DCAEN(x)	((x) << S_FW_IQ_CMD_FL1DCAEN)
+#define G_FW_IQ_CMD_FL1DCAEN(x)	\
+    (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN)
+#define F_FW_IQ_CMD_FL1DCAEN	V_FW_IQ_CMD_FL1DCAEN(1U)
+
+#define S_FW_IQ_CMD_FL1DCACPU		10
+#define M_FW_IQ_CMD_FL1DCACPU		0x1f
+#define V_FW_IQ_CMD_FL1DCACPU(x)	((x) << S_FW_IQ_CMD_FL1DCACPU)
+#define G_FW_IQ_CMD_FL1DCACPU(x)	\
+    (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU)
+
+#define S_FW_IQ_CMD_FL1FBMIN	7
+#define M_FW_IQ_CMD_FL1FBMIN	0x7
+#define V_FW_IQ_CMD_FL1FBMIN(x)	((x) << S_FW_IQ_CMD_FL1FBMIN)
+#define G_FW_IQ_CMD_FL1FBMIN(x)	\
+    (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN)
+
+#define S_FW_IQ_CMD_FL1FBMAX	4
+#define M_FW_IQ_CMD_FL1FBMAX	0x7
+#define V_FW_IQ_CMD_FL1FBMAX(x)	((x) << S_FW_IQ_CMD_FL1FBMAX)
+#define G_FW_IQ_CMD_FL1FBMAX(x)	\
+    (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX)
+
+#define S_FW_IQ_CMD_FL1CIDXFTHRESHO	3
+#define M_FW_IQ_CMD_FL1CIDXFTHRESHO	0x1
+#define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x)	((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO)
+#define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x)	\
+    (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO)
+#define F_FW_IQ_CMD_FL1CIDXFTHRESHO	V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U)
+
+#define S_FW_IQ_CMD_FL1CIDXFTHRESH	0
+#define M_FW_IQ_CMD_FL1CIDXFTHRESH	0x7
+#define V_FW_IQ_CMD_FL1CIDXFTHRESH(x)	((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH)
+#define G_FW_IQ_CMD_FL1CIDXFTHRESH(x)	\
+    (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH)
+
+struct fw_eq_mngt_cmd {
+	__be32 op_to_vfn;
+	__be32 alloc_to_len16;
+	__be32 cmpliqid_eqid;
+	__be32 physeqid_pkd;
+	__be32 fetchszm_to_iqid;
+	__be32 dcaen_to_eqsize;
+	__be64 eqaddr;
+};
+
+#define S_FW_EQ_MNGT_CMD_PFN	8
+#define M_FW_EQ_MNGT_CMD_PFN	0x7
+#define V_FW_EQ_MNGT_CMD_PFN(x)	((x) << S_FW_EQ_MNGT_CMD_PFN)
+#define G_FW_EQ_MNGT_CMD_PFN(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN)
+
+#define S_FW_EQ_MNGT_CMD_VFN	0
+#define M_FW_EQ_MNGT_CMD_VFN	0xff
+#define V_FW_EQ_MNGT_CMD_VFN(x)	((x) << S_FW_EQ_MNGT_CMD_VFN)
+#define G_FW_EQ_MNGT_CMD_VFN(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN)
+
+#define S_FW_EQ_MNGT_CMD_ALLOC		31
+#define M_FW_EQ_MNGT_CMD_ALLOC		0x1
+#define V_FW_EQ_MNGT_CMD_ALLOC(x)	((x) << S_FW_EQ_MNGT_CMD_ALLOC)
+#define G_FW_EQ_MNGT_CMD_ALLOC(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC)
+#define F_FW_EQ_MNGT_CMD_ALLOC	V_FW_EQ_MNGT_CMD_ALLOC(1U)
+
+#define S_FW_EQ_MNGT_CMD_FREE		30
+#define M_FW_EQ_MNGT_CMD_FREE		0x1
+#define V_FW_EQ_MNGT_CMD_FREE(x)	((x) << S_FW_EQ_MNGT_CMD_FREE)
+#define G_FW_EQ_MNGT_CMD_FREE(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE)
+#define F_FW_EQ_MNGT_CMD_FREE	V_FW_EQ_MNGT_CMD_FREE(1U)
+
+#define S_FW_EQ_MNGT_CMD_MODIFY		29
+#define M_FW_EQ_MNGT_CMD_MODIFY		0x1
+#define V_FW_EQ_MNGT_CMD_MODIFY(x)	((x) << S_FW_EQ_MNGT_CMD_MODIFY)
+#define G_FW_EQ_MNGT_CMD_MODIFY(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY)
+#define F_FW_EQ_MNGT_CMD_MODIFY	V_FW_EQ_MNGT_CMD_MODIFY(1U)
+
+#define S_FW_EQ_MNGT_CMD_EQSTART	28
+#define M_FW_EQ_MNGT_CMD_EQSTART	0x1
+#define V_FW_EQ_MNGT_CMD_EQSTART(x)	((x) << S_FW_EQ_MNGT_CMD_EQSTART)
+#define G_FW_EQ_MNGT_CMD_EQSTART(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART)
+#define F_FW_EQ_MNGT_CMD_EQSTART	V_FW_EQ_MNGT_CMD_EQSTART(1U)
+
+#define S_FW_EQ_MNGT_CMD_EQSTOP		27
+#define M_FW_EQ_MNGT_CMD_EQSTOP		0x1
+#define V_FW_EQ_MNGT_CMD_EQSTOP(x)	((x) << S_FW_EQ_MNGT_CMD_EQSTOP)
+#define G_FW_EQ_MNGT_CMD_EQSTOP(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP)
+#define F_FW_EQ_MNGT_CMD_EQSTOP	V_FW_EQ_MNGT_CMD_EQSTOP(1U)
+
+#define S_FW_EQ_MNGT_CMD_CMPLIQID	20
+#define M_FW_EQ_MNGT_CMD_CMPLIQID	0xfff
+#define V_FW_EQ_MNGT_CMD_CMPLIQID(x)	((x) << S_FW_EQ_MNGT_CMD_CMPLIQID)
+#define G_FW_EQ_MNGT_CMD_CMPLIQID(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID)
+
+#define S_FW_EQ_MNGT_CMD_EQID		0
+#define M_FW_EQ_MNGT_CMD_EQID		0xfffff
+#define V_FW_EQ_MNGT_CMD_EQID(x)	((x) << S_FW_EQ_MNGT_CMD_EQID)
+#define G_FW_EQ_MNGT_CMD_EQID(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID)
+
+#define S_FW_EQ_MNGT_CMD_PHYSEQID	0
+#define M_FW_EQ_MNGT_CMD_PHYSEQID	0xfffff
+#define V_FW_EQ_MNGT_CMD_PHYSEQID(x)	((x) << S_FW_EQ_MNGT_CMD_PHYSEQID)
+#define G_FW_EQ_MNGT_CMD_PHYSEQID(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID)
+
+#define S_FW_EQ_MNGT_CMD_FETCHSZM	26
+#define M_FW_EQ_MNGT_CMD_FETCHSZM	0x1
+#define V_FW_EQ_MNGT_CMD_FETCHSZM(x)	((x) << S_FW_EQ_MNGT_CMD_FETCHSZM)
+#define G_FW_EQ_MNGT_CMD_FETCHSZM(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM)
+#define F_FW_EQ_MNGT_CMD_FETCHSZM	V_FW_EQ_MNGT_CMD_FETCHSZM(1U)
+
+#define S_FW_EQ_MNGT_CMD_STATUSPGNS	25
+#define M_FW_EQ_MNGT_CMD_STATUSPGNS	0x1
+#define V_FW_EQ_MNGT_CMD_STATUSPGNS(x)	((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS)
+#define G_FW_EQ_MNGT_CMD_STATUSPGNS(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS)
+#define F_FW_EQ_MNGT_CMD_STATUSPGNS	V_FW_EQ_MNGT_CMD_STATUSPGNS(1U)
+
+#define S_FW_EQ_MNGT_CMD_STATUSPGRO	24
+#define M_FW_EQ_MNGT_CMD_STATUSPGRO	0x1
+#define V_FW_EQ_MNGT_CMD_STATUSPGRO(x)	((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO)
+#define G_FW_EQ_MNGT_CMD_STATUSPGRO(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO)
+#define F_FW_EQ_MNGT_CMD_STATUSPGRO	V_FW_EQ_MNGT_CMD_STATUSPGRO(1U)
+
+#define S_FW_EQ_MNGT_CMD_FETCHNS	23
+#define M_FW_EQ_MNGT_CMD_FETCHNS	0x1
+#define V_FW_EQ_MNGT_CMD_FETCHNS(x)	((x) << S_FW_EQ_MNGT_CMD_FETCHNS)
+#define G_FW_EQ_MNGT_CMD_FETCHNS(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS)
+#define F_FW_EQ_MNGT_CMD_FETCHNS	V_FW_EQ_MNGT_CMD_FETCHNS(1U)
+
+#define S_FW_EQ_MNGT_CMD_FETCHRO	22
+#define M_FW_EQ_MNGT_CMD_FETCHRO	0x1
+#define V_FW_EQ_MNGT_CMD_FETCHRO(x)	((x) << S_FW_EQ_MNGT_CMD_FETCHRO)
+#define G_FW_EQ_MNGT_CMD_FETCHRO(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO)
+#define F_FW_EQ_MNGT_CMD_FETCHRO	V_FW_EQ_MNGT_CMD_FETCHRO(1U)
+
+#define S_FW_EQ_MNGT_CMD_HOSTFCMODE	20
+#define M_FW_EQ_MNGT_CMD_HOSTFCMODE	0x3
+#define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x)	((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE)
+#define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE)
+
+#define S_FW_EQ_MNGT_CMD_CPRIO		19
+#define M_FW_EQ_MNGT_CMD_CPRIO		0x1
+#define V_FW_EQ_MNGT_CMD_CPRIO(x)	((x) << S_FW_EQ_MNGT_CMD_CPRIO)
+#define G_FW_EQ_MNGT_CMD_CPRIO(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO)
+#define F_FW_EQ_MNGT_CMD_CPRIO	V_FW_EQ_MNGT_CMD_CPRIO(1U)
+
+#define S_FW_EQ_MNGT_CMD_ONCHIP		18
+#define M_FW_EQ_MNGT_CMD_ONCHIP		0x1
+#define V_FW_EQ_MNGT_CMD_ONCHIP(x)	((x) << S_FW_EQ_MNGT_CMD_ONCHIP)
+#define G_FW_EQ_MNGT_CMD_ONCHIP(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP)
+#define F_FW_EQ_MNGT_CMD_ONCHIP	V_FW_EQ_MNGT_CMD_ONCHIP(1U)
+
+#define S_FW_EQ_MNGT_CMD_PCIECHN	16
+#define M_FW_EQ_MNGT_CMD_PCIECHN	0x3
+#define V_FW_EQ_MNGT_CMD_PCIECHN(x)	((x) << S_FW_EQ_MNGT_CMD_PCIECHN)
+#define G_FW_EQ_MNGT_CMD_PCIECHN(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN)
+
+#define S_FW_EQ_MNGT_CMD_IQID		0
+#define M_FW_EQ_MNGT_CMD_IQID		0xffff
+#define V_FW_EQ_MNGT_CMD_IQID(x)	((x) << S_FW_EQ_MNGT_CMD_IQID)
+#define G_FW_EQ_MNGT_CMD_IQID(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID)
+
+#define S_FW_EQ_MNGT_CMD_DCAEN		31
+#define M_FW_EQ_MNGT_CMD_DCAEN		0x1
+#define V_FW_EQ_MNGT_CMD_DCAEN(x)	((x) << S_FW_EQ_MNGT_CMD_DCAEN)
+#define G_FW_EQ_MNGT_CMD_DCAEN(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN)
+#define F_FW_EQ_MNGT_CMD_DCAEN	V_FW_EQ_MNGT_CMD_DCAEN(1U)
+
+#define S_FW_EQ_MNGT_CMD_DCACPU		26
+#define M_FW_EQ_MNGT_CMD_DCACPU		0x1f
+#define V_FW_EQ_MNGT_CMD_DCACPU(x)	((x) << S_FW_EQ_MNGT_CMD_DCACPU)
+#define G_FW_EQ_MNGT_CMD_DCACPU(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU)
+
+#define S_FW_EQ_MNGT_CMD_FBMIN		23
+#define M_FW_EQ_MNGT_CMD_FBMIN		0x7
+#define V_FW_EQ_MNGT_CMD_FBMIN(x)	((x) << S_FW_EQ_MNGT_CMD_FBMIN)
+#define G_FW_EQ_MNGT_CMD_FBMIN(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN)
+
+#define S_FW_EQ_MNGT_CMD_FBMAX		20
+#define M_FW_EQ_MNGT_CMD_FBMAX		0x7
+#define V_FW_EQ_MNGT_CMD_FBMAX(x)	((x) << S_FW_EQ_MNGT_CMD_FBMAX)
+#define G_FW_EQ_MNGT_CMD_FBMAX(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX)
+
+#define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO		19
+#define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO		0x1
+#define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x)	\
+    ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO)
+#define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO)
+#define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO	V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U)
+
+#define S_FW_EQ_MNGT_CMD_CIDXFTHRESH	16
+#define M_FW_EQ_MNGT_CMD_CIDXFTHRESH	0x7
+#define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x)	((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH)
+#define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH)
+
+#define S_FW_EQ_MNGT_CMD_EQSIZE		0
+#define M_FW_EQ_MNGT_CMD_EQSIZE		0xffff
+#define V_FW_EQ_MNGT_CMD_EQSIZE(x)	((x) << S_FW_EQ_MNGT_CMD_EQSIZE)
+#define G_FW_EQ_MNGT_CMD_EQSIZE(x)	\
+    (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE)
+
+struct fw_eq_eth_cmd {
+	__be32 op_to_vfn;
+	__be32 alloc_to_len16;
+	__be32 eqid_pkd;
+	__be32 physeqid_pkd;
+	__be32 fetchszm_to_iqid;
+	__be32 dcaen_to_eqsize;
+	__be64 eqaddr;
+	__be32 viid_pkd;
+	__be32 r8_lo;
+	__be64 r9;
+};
+
+#define S_FW_EQ_ETH_CMD_PFN	8
+#define M_FW_EQ_ETH_CMD_PFN	0x7
+#define V_FW_EQ_ETH_CMD_PFN(x)	((x) << S_FW_EQ_ETH_CMD_PFN)
+#define G_FW_EQ_ETH_CMD_PFN(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
+
+#define S_FW_EQ_ETH_CMD_VFN	0
+#define M_FW_EQ_ETH_CMD_VFN	0xff
+#define V_FW_EQ_ETH_CMD_VFN(x)	((x) << S_FW_EQ_ETH_CMD_VFN)
+#define G_FW_EQ_ETH_CMD_VFN(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
+
+#define S_FW_EQ_ETH_CMD_ALLOC		31
+#define M_FW_EQ_ETH_CMD_ALLOC		0x1
+#define V_FW_EQ_ETH_CMD_ALLOC(x)	((x) << S_FW_EQ_ETH_CMD_ALLOC)
+#define G_FW_EQ_ETH_CMD_ALLOC(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
+#define F_FW_EQ_ETH_CMD_ALLOC	V_FW_EQ_ETH_CMD_ALLOC(1U)
+
+#define S_FW_EQ_ETH_CMD_FREE	30
+#define M_FW_EQ_ETH_CMD_FREE	0x1
+#define V_FW_EQ_ETH_CMD_FREE(x)	((x) << S_FW_EQ_ETH_CMD_FREE)
+#define G_FW_EQ_ETH_CMD_FREE(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
+#define F_FW_EQ_ETH_CMD_FREE	V_FW_EQ_ETH_CMD_FREE(1U)
+
+#define S_FW_EQ_ETH_CMD_MODIFY		29
+#define M_FW_EQ_ETH_CMD_MODIFY		0x1
+#define V_FW_EQ_ETH_CMD_MODIFY(x)	((x) << S_FW_EQ_ETH_CMD_MODIFY)
+#define G_FW_EQ_ETH_CMD_MODIFY(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY)
+#define F_FW_EQ_ETH_CMD_MODIFY	V_FW_EQ_ETH_CMD_MODIFY(1U)
+
+#define S_FW_EQ_ETH_CMD_EQSTART		28
+#define M_FW_EQ_ETH_CMD_EQSTART		0x1
+#define V_FW_EQ_ETH_CMD_EQSTART(x)	((x) << S_FW_EQ_ETH_CMD_EQSTART)
+#define G_FW_EQ_ETH_CMD_EQSTART(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
+#define F_FW_EQ_ETH_CMD_EQSTART	V_FW_EQ_ETH_CMD_EQSTART(1U)
+
+#define S_FW_EQ_ETH_CMD_EQSTOP		27
+#define M_FW_EQ_ETH_CMD_EQSTOP		0x1
+#define V_FW_EQ_ETH_CMD_EQSTOP(x)	((x) << S_FW_EQ_ETH_CMD_EQSTOP)
+#define G_FW_EQ_ETH_CMD_EQSTOP(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP)
+#define F_FW_EQ_ETH_CMD_EQSTOP	V_FW_EQ_ETH_CMD_EQSTOP(1U)
+
+#define S_FW_EQ_ETH_CMD_EQID	0
+#define M_FW_EQ_ETH_CMD_EQID	0xfffff
+#define V_FW_EQ_ETH_CMD_EQID(x)	((x) << S_FW_EQ_ETH_CMD_EQID)
+#define G_FW_EQ_ETH_CMD_EQID(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
+
+#define S_FW_EQ_ETH_CMD_PHYSEQID	0
+#define M_FW_EQ_ETH_CMD_PHYSEQID	0xfffff
+#define V_FW_EQ_ETH_CMD_PHYSEQID(x)	((x) << S_FW_EQ_ETH_CMD_PHYSEQID)
+#define G_FW_EQ_ETH_CMD_PHYSEQID(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
+
+#define S_FW_EQ_ETH_CMD_FETCHSZM	26
+#define M_FW_EQ_ETH_CMD_FETCHSZM	0x1
+#define V_FW_EQ_ETH_CMD_FETCHSZM(x)	((x) << S_FW_EQ_ETH_CMD_FETCHSZM)
+#define G_FW_EQ_ETH_CMD_FETCHSZM(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM)
+#define F_FW_EQ_ETH_CMD_FETCHSZM	V_FW_EQ_ETH_CMD_FETCHSZM(1U)
+
+#define S_FW_EQ_ETH_CMD_STATUSPGNS	25
+#define M_FW_EQ_ETH_CMD_STATUSPGNS	0x1
+#define V_FW_EQ_ETH_CMD_STATUSPGNS(x)	((x) << S_FW_EQ_ETH_CMD_STATUSPGNS)
+#define G_FW_EQ_ETH_CMD_STATUSPGNS(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS)
+#define F_FW_EQ_ETH_CMD_STATUSPGNS	V_FW_EQ_ETH_CMD_STATUSPGNS(1U)
+
+#define S_FW_EQ_ETH_CMD_STATUSPGRO	24
+#define M_FW_EQ_ETH_CMD_STATUSPGRO	0x1
+#define V_FW_EQ_ETH_CMD_STATUSPGRO(x)	((x) << S_FW_EQ_ETH_CMD_STATUSPGRO)
+#define G_FW_EQ_ETH_CMD_STATUSPGRO(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO)
+#define F_FW_EQ_ETH_CMD_STATUSPGRO	V_FW_EQ_ETH_CMD_STATUSPGRO(1U)
+
+#define S_FW_EQ_ETH_CMD_FETCHNS		23
+#define M_FW_EQ_ETH_CMD_FETCHNS		0x1
+#define V_FW_EQ_ETH_CMD_FETCHNS(x)	((x) << S_FW_EQ_ETH_CMD_FETCHNS)
+#define G_FW_EQ_ETH_CMD_FETCHNS(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS)
+#define F_FW_EQ_ETH_CMD_FETCHNS	V_FW_EQ_ETH_CMD_FETCHNS(1U)
+
+#define S_FW_EQ_ETH_CMD_FETCHRO		22
+#define M_FW_EQ_ETH_CMD_FETCHRO		0x1
+#define V_FW_EQ_ETH_CMD_FETCHRO(x)	((x) << S_FW_EQ_ETH_CMD_FETCHRO)
+#define G_FW_EQ_ETH_CMD_FETCHRO(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
+#define F_FW_EQ_ETH_CMD_FETCHRO	V_FW_EQ_ETH_CMD_FETCHRO(1U)
+
+#define S_FW_EQ_ETH_CMD_HOSTFCMODE	20
+#define M_FW_EQ_ETH_CMD_HOSTFCMODE	0x3
+#define V_FW_EQ_ETH_CMD_HOSTFCMODE(x)	((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
+#define G_FW_EQ_ETH_CMD_HOSTFCMODE(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
+
+#define S_FW_EQ_ETH_CMD_CPRIO		19
+#define M_FW_EQ_ETH_CMD_CPRIO		0x1
+#define V_FW_EQ_ETH_CMD_CPRIO(x)	((x) << S_FW_EQ_ETH_CMD_CPRIO)
+#define G_FW_EQ_ETH_CMD_CPRIO(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO)
+#define F_FW_EQ_ETH_CMD_CPRIO	V_FW_EQ_ETH_CMD_CPRIO(1U)
+
+#define S_FW_EQ_ETH_CMD_ONCHIP		18
+#define M_FW_EQ_ETH_CMD_ONCHIP		0x1
+#define V_FW_EQ_ETH_CMD_ONCHIP(x)	((x) << S_FW_EQ_ETH_CMD_ONCHIP)
+#define G_FW_EQ_ETH_CMD_ONCHIP(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP)
+#define F_FW_EQ_ETH_CMD_ONCHIP	V_FW_EQ_ETH_CMD_ONCHIP(1U)
+
+#define S_FW_EQ_ETH_CMD_PCIECHN		16
+#define M_FW_EQ_ETH_CMD_PCIECHN		0x3
+#define V_FW_EQ_ETH_CMD_PCIECHN(x)	((x) << S_FW_EQ_ETH_CMD_PCIECHN)
+#define G_FW_EQ_ETH_CMD_PCIECHN(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
+
+#define S_FW_EQ_ETH_CMD_IQID	0
+#define M_FW_EQ_ETH_CMD_IQID	0xffff
+#define V_FW_EQ_ETH_CMD_IQID(x)	((x) << S_FW_EQ_ETH_CMD_IQID)
+#define G_FW_EQ_ETH_CMD_IQID(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
+
+#define S_FW_EQ_ETH_CMD_DCAEN		31
+#define M_FW_EQ_ETH_CMD_DCAEN		0x1
+#define V_FW_EQ_ETH_CMD_DCAEN(x)	((x) << S_FW_EQ_ETH_CMD_DCAEN)
+#define G_FW_EQ_ETH_CMD_DCAEN(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN)
+#define F_FW_EQ_ETH_CMD_DCAEN	V_FW_EQ_ETH_CMD_DCAEN(1U)
+
+#define S_FW_EQ_ETH_CMD_DCACPU		26
+#define M_FW_EQ_ETH_CMD_DCACPU		0x1f
+#define V_FW_EQ_ETH_CMD_DCACPU(x)	((x) << S_FW_EQ_ETH_CMD_DCACPU)
+#define G_FW_EQ_ETH_CMD_DCACPU(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU)
+
+#define S_FW_EQ_ETH_CMD_FBMIN		23
+#define M_FW_EQ_ETH_CMD_FBMIN		0x7
+#define V_FW_EQ_ETH_CMD_FBMIN(x)	((x) << S_FW_EQ_ETH_CMD_FBMIN)
+#define G_FW_EQ_ETH_CMD_FBMIN(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
+
+#define S_FW_EQ_ETH_CMD_FBMAX		20
+#define M_FW_EQ_ETH_CMD_FBMAX		0x7
+#define V_FW_EQ_ETH_CMD_FBMAX(x)	((x) << S_FW_EQ_ETH_CMD_FBMAX)
+#define G_FW_EQ_ETH_CMD_FBMAX(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
+
+#define S_FW_EQ_ETH_CMD_CIDXFTHRESHO	19
+#define M_FW_EQ_ETH_CMD_CIDXFTHRESHO	0x1
+#define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x)	((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO)
+#define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO)
+#define F_FW_EQ_ETH_CMD_CIDXFTHRESHO	V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U)
+
+#define S_FW_EQ_ETH_CMD_CIDXFTHRESH	16
+#define M_FW_EQ_ETH_CMD_CIDXFTHRESH	0x7
+#define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x)	((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
+#define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
+
+#define S_FW_EQ_ETH_CMD_EQSIZE		0
+#define M_FW_EQ_ETH_CMD_EQSIZE		0xffff
+#define V_FW_EQ_ETH_CMD_EQSIZE(x)	((x) << S_FW_EQ_ETH_CMD_EQSIZE)
+#define G_FW_EQ_ETH_CMD_EQSIZE(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
+
+#define S_FW_EQ_ETH_CMD_VIID	16
+#define M_FW_EQ_ETH_CMD_VIID	0xfff
+#define V_FW_EQ_ETH_CMD_VIID(x)	((x) << S_FW_EQ_ETH_CMD_VIID)
+#define G_FW_EQ_ETH_CMD_VIID(x)	\
+    (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
+
+struct fw_eq_ctrl_cmd {
+	__be32 op_to_vfn;
+	__be32 alloc_to_len16;
+	__be32 cmpliqid_eqid;
+	__be32 physeqid_pkd;
+	__be32 fetchszm_to_iqid;
+	__be32 dcaen_to_eqsize;
+	__be64 eqaddr;
+};
+
+#define S_FW_EQ_CTRL_CMD_PFN	8
+#define M_FW_EQ_CTRL_CMD_PFN	0x7
+#define V_FW_EQ_CTRL_CMD_PFN(x)	((x) << S_FW_EQ_CTRL_CMD_PFN)
+#define G_FW_EQ_CTRL_CMD_PFN(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN)
+
+#define S_FW_EQ_CTRL_CMD_VFN	0
+#define M_FW_EQ_CTRL_CMD_VFN	0xff
+#define V_FW_EQ_CTRL_CMD_VFN(x)	((x) << S_FW_EQ_CTRL_CMD_VFN)
+#define G_FW_EQ_CTRL_CMD_VFN(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN)
+
+#define S_FW_EQ_CTRL_CMD_ALLOC		31
+#define M_FW_EQ_CTRL_CMD_ALLOC		0x1
+#define V_FW_EQ_CTRL_CMD_ALLOC(x)	((x) << S_FW_EQ_CTRL_CMD_ALLOC)
+#define G_FW_EQ_CTRL_CMD_ALLOC(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC)
+#define F_FW_EQ_CTRL_CMD_ALLOC	V_FW_EQ_CTRL_CMD_ALLOC(1U)
+
+#define S_FW_EQ_CTRL_CMD_FREE		30
+#define M_FW_EQ_CTRL_CMD_FREE		0x1
+#define V_FW_EQ_CTRL_CMD_FREE(x)	((x) << S_FW_EQ_CTRL_CMD_FREE)
+#define G_FW_EQ_CTRL_CMD_FREE(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE)
+#define F_FW_EQ_CTRL_CMD_FREE	V_FW_EQ_CTRL_CMD_FREE(1U)
+
+#define S_FW_EQ_CTRL_CMD_MODIFY		29
+#define M_FW_EQ_CTRL_CMD_MODIFY		0x1
+#define V_FW_EQ_CTRL_CMD_MODIFY(x)	((x) << S_FW_EQ_CTRL_CMD_MODIFY)
+#define G_FW_EQ_CTRL_CMD_MODIFY(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY)
+#define F_FW_EQ_CTRL_CMD_MODIFY	V_FW_EQ_CTRL_CMD_MODIFY(1U)
+
+#define S_FW_EQ_CTRL_CMD_EQSTART	28
+#define M_FW_EQ_CTRL_CMD_EQSTART	0x1
+#define V_FW_EQ_CTRL_CMD_EQSTART(x)	((x) << S_FW_EQ_CTRL_CMD_EQSTART)
+#define G_FW_EQ_CTRL_CMD_EQSTART(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART)
+#define F_FW_EQ_CTRL_CMD_EQSTART	V_FW_EQ_CTRL_CMD_EQSTART(1U)
+
+#define S_FW_EQ_CTRL_CMD_EQSTOP		27
+#define M_FW_EQ_CTRL_CMD_EQSTOP		0x1
+#define V_FW_EQ_CTRL_CMD_EQSTOP(x)	((x) << S_FW_EQ_CTRL_CMD_EQSTOP)
+#define G_FW_EQ_CTRL_CMD_EQSTOP(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP)
+#define F_FW_EQ_CTRL_CMD_EQSTOP	V_FW_EQ_CTRL_CMD_EQSTOP(1U)
+
+#define S_FW_EQ_CTRL_CMD_CMPLIQID	20
+#define M_FW_EQ_CTRL_CMD_CMPLIQID	0xfff
+#define V_FW_EQ_CTRL_CMD_CMPLIQID(x)	((x) << S_FW_EQ_CTRL_CMD_CMPLIQID)
+#define G_FW_EQ_CTRL_CMD_CMPLIQID(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID)
+
+#define S_FW_EQ_CTRL_CMD_EQID		0
+#define M_FW_EQ_CTRL_CMD_EQID		0xfffff
+#define V_FW_EQ_CTRL_CMD_EQID(x)	((x) << S_FW_EQ_CTRL_CMD_EQID)
+#define G_FW_EQ_CTRL_CMD_EQID(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID)
+
+#define S_FW_EQ_CTRL_CMD_PHYSEQID	0
+#define M_FW_EQ_CTRL_CMD_PHYSEQID	0xfffff
+#define V_FW_EQ_CTRL_CMD_PHYSEQID(x)	((x) << S_FW_EQ_CTRL_CMD_PHYSEQID)
+#define G_FW_EQ_CTRL_CMD_PHYSEQID(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID)
+
+#define S_FW_EQ_CTRL_CMD_FETCHSZM	26
+#define M_FW_EQ_CTRL_CMD_FETCHSZM	0x1
+#define V_FW_EQ_CTRL_CMD_FETCHSZM(x)	((x) << S_FW_EQ_CTRL_CMD_FETCHSZM)
+#define G_FW_EQ_CTRL_CMD_FETCHSZM(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM)
+#define F_FW_EQ_CTRL_CMD_FETCHSZM	V_FW_EQ_CTRL_CMD_FETCHSZM(1U)
+
+#define S_FW_EQ_CTRL_CMD_STATUSPGNS	25
+#define M_FW_EQ_CTRL_CMD_STATUSPGNS	0x1
+#define V_FW_EQ_CTRL_CMD_STATUSPGNS(x)	((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS)
+#define G_FW_EQ_CTRL_CMD_STATUSPGNS(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS)
+#define F_FW_EQ_CTRL_CMD_STATUSPGNS	V_FW_EQ_CTRL_CMD_STATUSPGNS(1U)
+
+#define S_FW_EQ_CTRL_CMD_STATUSPGRO	24
+#define M_FW_EQ_CTRL_CMD_STATUSPGRO	0x1
+#define V_FW_EQ_CTRL_CMD_STATUSPGRO(x)	((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO)
+#define G_FW_EQ_CTRL_CMD_STATUSPGRO(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO)
+#define F_FW_EQ_CTRL_CMD_STATUSPGRO	V_FW_EQ_CTRL_CMD_STATUSPGRO(1U)
+
+#define S_FW_EQ_CTRL_CMD_FETCHNS	23
+#define M_FW_EQ_CTRL_CMD_FETCHNS	0x1
+#define V_FW_EQ_CTRL_CMD_FETCHNS(x)	((x) << S_FW_EQ_CTRL_CMD_FETCHNS)
+#define G_FW_EQ_CTRL_CMD_FETCHNS(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS)
+#define F_FW_EQ_CTRL_CMD_FETCHNS	V_FW_EQ_CTRL_CMD_FETCHNS(1U)
+
+#define S_FW_EQ_CTRL_CMD_FETCHRO	22
+#define M_FW_EQ_CTRL_CMD_FETCHRO	0x1
+#define V_FW_EQ_CTRL_CMD_FETCHRO(x)	((x) << S_FW_EQ_CTRL_CMD_FETCHRO)
+#define G_FW_EQ_CTRL_CMD_FETCHRO(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO)
+#define F_FW_EQ_CTRL_CMD_FETCHRO	V_FW_EQ_CTRL_CMD_FETCHRO(1U)
+
+#define S_FW_EQ_CTRL_CMD_HOSTFCMODE	20
+#define M_FW_EQ_CTRL_CMD_HOSTFCMODE	0x3
+#define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x)	((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE)
+#define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE)
+
+#define S_FW_EQ_CTRL_CMD_CPRIO		19
+#define M_FW_EQ_CTRL_CMD_CPRIO		0x1
+#define V_FW_EQ_CTRL_CMD_CPRIO(x)	((x) << S_FW_EQ_CTRL_CMD_CPRIO)
+#define G_FW_EQ_CTRL_CMD_CPRIO(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO)
+#define F_FW_EQ_CTRL_CMD_CPRIO	V_FW_EQ_CTRL_CMD_CPRIO(1U)
+
+#define S_FW_EQ_CTRL_CMD_ONCHIP		18
+#define M_FW_EQ_CTRL_CMD_ONCHIP		0x1
+#define V_FW_EQ_CTRL_CMD_ONCHIP(x)	((x) << S_FW_EQ_CTRL_CMD_ONCHIP)
+#define G_FW_EQ_CTRL_CMD_ONCHIP(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP)
+#define F_FW_EQ_CTRL_CMD_ONCHIP	V_FW_EQ_CTRL_CMD_ONCHIP(1U)
+
+#define S_FW_EQ_CTRL_CMD_PCIECHN	16
+#define M_FW_EQ_CTRL_CMD_PCIECHN	0x3
+#define V_FW_EQ_CTRL_CMD_PCIECHN(x)	((x) << S_FW_EQ_CTRL_CMD_PCIECHN)
+#define G_FW_EQ_CTRL_CMD_PCIECHN(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN)
+
+#define S_FW_EQ_CTRL_CMD_IQID		0
+#define M_FW_EQ_CTRL_CMD_IQID		0xffff
+#define V_FW_EQ_CTRL_CMD_IQID(x)	((x) << S_FW_EQ_CTRL_CMD_IQID)
+#define G_FW_EQ_CTRL_CMD_IQID(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID)
+
+#define S_FW_EQ_CTRL_CMD_DCAEN		31
+#define M_FW_EQ_CTRL_CMD_DCAEN		0x1
+#define V_FW_EQ_CTRL_CMD_DCAEN(x)	((x) << S_FW_EQ_CTRL_CMD_DCAEN)
+#define G_FW_EQ_CTRL_CMD_DCAEN(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN)
+#define F_FW_EQ_CTRL_CMD_DCAEN	V_FW_EQ_CTRL_CMD_DCAEN(1U)
+
+#define S_FW_EQ_CTRL_CMD_DCACPU		26
+#define M_FW_EQ_CTRL_CMD_DCACPU		0x1f
+#define V_FW_EQ_CTRL_CMD_DCACPU(x)	((x) << S_FW_EQ_CTRL_CMD_DCACPU)
+#define G_FW_EQ_CTRL_CMD_DCACPU(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU)
+
+#define S_FW_EQ_CTRL_CMD_FBMIN		23
+#define M_FW_EQ_CTRL_CMD_FBMIN		0x7
+#define V_FW_EQ_CTRL_CMD_FBMIN(x)	((x) << S_FW_EQ_CTRL_CMD_FBMIN)
+#define G_FW_EQ_CTRL_CMD_FBMIN(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN)
+
+#define S_FW_EQ_CTRL_CMD_FBMAX		20
+#define M_FW_EQ_CTRL_CMD_FBMAX		0x7
+#define V_FW_EQ_CTRL_CMD_FBMAX(x)	((x) << S_FW_EQ_CTRL_CMD_FBMAX)
+#define G_FW_EQ_CTRL_CMD_FBMAX(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX)
+
+#define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO		19
+#define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO		0x1
+#define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x)	\
+    ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO)
+#define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO)
+#define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO	V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U)
+
+#define S_FW_EQ_CTRL_CMD_CIDXFTHRESH	16
+#define M_FW_EQ_CTRL_CMD_CIDXFTHRESH	0x7
+#define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x)	((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH)
+#define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH)
+
+#define S_FW_EQ_CTRL_CMD_EQSIZE		0
+#define M_FW_EQ_CTRL_CMD_EQSIZE		0xffff
+#define V_FW_EQ_CTRL_CMD_EQSIZE(x)	((x) << S_FW_EQ_CTRL_CMD_EQSIZE)
+#define G_FW_EQ_CTRL_CMD_EQSIZE(x)	\
+    (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE)
+
+struct fw_eq_ofld_cmd {
+	__be32 op_to_vfn;
+	__be32 alloc_to_len16;
+	__be32 eqid_pkd;
+	__be32 physeqid_pkd;
+	__be32 fetchszm_to_iqid;
+	__be32 dcaen_to_eqsize;
+	__be64 eqaddr;
+};
+
+#define S_FW_EQ_OFLD_CMD_PFN	8
+#define M_FW_EQ_OFLD_CMD_PFN	0x7
+#define V_FW_EQ_OFLD_CMD_PFN(x)	((x) << S_FW_EQ_OFLD_CMD_PFN)
+#define G_FW_EQ_OFLD_CMD_PFN(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN)
+
+#define S_FW_EQ_OFLD_CMD_VFN	0
+#define M_FW_EQ_OFLD_CMD_VFN	0xff
+#define V_FW_EQ_OFLD_CMD_VFN(x)	((x) << S_FW_EQ_OFLD_CMD_VFN)
+#define G_FW_EQ_OFLD_CMD_VFN(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN)
+
+#define S_FW_EQ_OFLD_CMD_ALLOC		31
+#define M_FW_EQ_OFLD_CMD_ALLOC		0x1
+#define V_FW_EQ_OFLD_CMD_ALLOC(x)	((x) << S_FW_EQ_OFLD_CMD_ALLOC)
+#define G_FW_EQ_OFLD_CMD_ALLOC(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC)
+#define F_FW_EQ_OFLD_CMD_ALLOC	V_FW_EQ_OFLD_CMD_ALLOC(1U)
+
+#define S_FW_EQ_OFLD_CMD_FREE		30
+#define M_FW_EQ_OFLD_CMD_FREE		0x1
+#define V_FW_EQ_OFLD_CMD_FREE(x)	((x) << S_FW_EQ_OFLD_CMD_FREE)
+#define G_FW_EQ_OFLD_CMD_FREE(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE)
+#define F_FW_EQ_OFLD_CMD_FREE	V_FW_EQ_OFLD_CMD_FREE(1U)
+
+#define S_FW_EQ_OFLD_CMD_MODIFY		29
+#define M_FW_EQ_OFLD_CMD_MODIFY		0x1
+#define V_FW_EQ_OFLD_CMD_MODIFY(x)	((x) << S_FW_EQ_OFLD_CMD_MODIFY)
+#define G_FW_EQ_OFLD_CMD_MODIFY(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY)
+#define F_FW_EQ_OFLD_CMD_MODIFY	V_FW_EQ_OFLD_CMD_MODIFY(1U)
+
+#define S_FW_EQ_OFLD_CMD_EQSTART	28
+#define M_FW_EQ_OFLD_CMD_EQSTART	0x1
+#define V_FW_EQ_OFLD_CMD_EQSTART(x)	((x) << S_FW_EQ_OFLD_CMD_EQSTART)
+#define G_FW_EQ_OFLD_CMD_EQSTART(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART)
+#define F_FW_EQ_OFLD_CMD_EQSTART	V_FW_EQ_OFLD_CMD_EQSTART(1U)
+
+#define S_FW_EQ_OFLD_CMD_EQSTOP		27
+#define M_FW_EQ_OFLD_CMD_EQSTOP		0x1
+#define V_FW_EQ_OFLD_CMD_EQSTOP(x)	((x) << S_FW_EQ_OFLD_CMD_EQSTOP)
+#define G_FW_EQ_OFLD_CMD_EQSTOP(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP)
+#define F_FW_EQ_OFLD_CMD_EQSTOP	V_FW_EQ_OFLD_CMD_EQSTOP(1U)
+
+#define S_FW_EQ_OFLD_CMD_EQID		0
+#define M_FW_EQ_OFLD_CMD_EQID		0xfffff
+#define V_FW_EQ_OFLD_CMD_EQID(x)	((x) << S_FW_EQ_OFLD_CMD_EQID)
+#define G_FW_EQ_OFLD_CMD_EQID(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID)
+
+#define S_FW_EQ_OFLD_CMD_PHYSEQID	0
+#define M_FW_EQ_OFLD_CMD_PHYSEQID	0xfffff
+#define V_FW_EQ_OFLD_CMD_PHYSEQID(x)	((x) << S_FW_EQ_OFLD_CMD_PHYSEQID)
+#define G_FW_EQ_OFLD_CMD_PHYSEQID(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID)
+
+#define S_FW_EQ_OFLD_CMD_FETCHSZM	26
+#define M_FW_EQ_OFLD_CMD_FETCHSZM	0x1
+#define V_FW_EQ_OFLD_CMD_FETCHSZM(x)	((x) << S_FW_EQ_OFLD_CMD_FETCHSZM)
+#define G_FW_EQ_OFLD_CMD_FETCHSZM(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM)
+#define F_FW_EQ_OFLD_CMD_FETCHSZM	V_FW_EQ_OFLD_CMD_FETCHSZM(1U)
+
+#define S_FW_EQ_OFLD_CMD_STATUSPGNS	25
+#define M_FW_EQ_OFLD_CMD_STATUSPGNS	0x1
+#define V_FW_EQ_OFLD_CMD_STATUSPGNS(x)	((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS)
+#define G_FW_EQ_OFLD_CMD_STATUSPGNS(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS)
+#define F_FW_EQ_OFLD_CMD_STATUSPGNS	V_FW_EQ_OFLD_CMD_STATUSPGNS(1U)
+
+#define S_FW_EQ_OFLD_CMD_STATUSPGRO	24
+#define M_FW_EQ_OFLD_CMD_STATUSPGRO	0x1
+#define V_FW_EQ_OFLD_CMD_STATUSPGRO(x)	((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO)
+#define G_FW_EQ_OFLD_CMD_STATUSPGRO(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO)
+#define F_FW_EQ_OFLD_CMD_STATUSPGRO	V_FW_EQ_OFLD_CMD_STATUSPGRO(1U)
+
+#define S_FW_EQ_OFLD_CMD_FETCHNS	23
+#define M_FW_EQ_OFLD_CMD_FETCHNS	0x1
+#define V_FW_EQ_OFLD_CMD_FETCHNS(x)	((x) << S_FW_EQ_OFLD_CMD_FETCHNS)
+#define G_FW_EQ_OFLD_CMD_FETCHNS(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS)
+#define F_FW_EQ_OFLD_CMD_FETCHNS	V_FW_EQ_OFLD_CMD_FETCHNS(1U)
+
+#define S_FW_EQ_OFLD_CMD_FETCHRO	22
+#define M_FW_EQ_OFLD_CMD_FETCHRO	0x1
+#define V_FW_EQ_OFLD_CMD_FETCHRO(x)	((x) << S_FW_EQ_OFLD_CMD_FETCHRO)
+#define G_FW_EQ_OFLD_CMD_FETCHRO(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO)
+#define F_FW_EQ_OFLD_CMD_FETCHRO	V_FW_EQ_OFLD_CMD_FETCHRO(1U)
+
+#define S_FW_EQ_OFLD_CMD_HOSTFCMODE	20
+#define M_FW_EQ_OFLD_CMD_HOSTFCMODE	0x3
+#define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x)	((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE)
+#define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE)
+
+#define S_FW_EQ_OFLD_CMD_CPRIO		19
+#define M_FW_EQ_OFLD_CMD_CPRIO		0x1
+#define V_FW_EQ_OFLD_CMD_CPRIO(x)	((x) << S_FW_EQ_OFLD_CMD_CPRIO)
+#define G_FW_EQ_OFLD_CMD_CPRIO(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO)
+#define F_FW_EQ_OFLD_CMD_CPRIO	V_FW_EQ_OFLD_CMD_CPRIO(1U)
+
+#define S_FW_EQ_OFLD_CMD_ONCHIP		18
+#define M_FW_EQ_OFLD_CMD_ONCHIP		0x1
+#define V_FW_EQ_OFLD_CMD_ONCHIP(x)	((x) << S_FW_EQ_OFLD_CMD_ONCHIP)
+#define G_FW_EQ_OFLD_CMD_ONCHIP(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP)
+#define F_FW_EQ_OFLD_CMD_ONCHIP	V_FW_EQ_OFLD_CMD_ONCHIP(1U)
+
+#define S_FW_EQ_OFLD_CMD_PCIECHN	16
+#define M_FW_EQ_OFLD_CMD_PCIECHN	0x3
+#define V_FW_EQ_OFLD_CMD_PCIECHN(x)	((x) << S_FW_EQ_OFLD_CMD_PCIECHN)
+#define G_FW_EQ_OFLD_CMD_PCIECHN(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN)
+
+#define S_FW_EQ_OFLD_CMD_IQID		0
+#define M_FW_EQ_OFLD_CMD_IQID		0xffff
+#define V_FW_EQ_OFLD_CMD_IQID(x)	((x) << S_FW_EQ_OFLD_CMD_IQID)
+#define G_FW_EQ_OFLD_CMD_IQID(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID)
+
+#define S_FW_EQ_OFLD_CMD_DCAEN		31
+#define M_FW_EQ_OFLD_CMD_DCAEN		0x1
+#define V_FW_EQ_OFLD_CMD_DCAEN(x)	((x) << S_FW_EQ_OFLD_CMD_DCAEN)
+#define G_FW_EQ_OFLD_CMD_DCAEN(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN)
+#define F_FW_EQ_OFLD_CMD_DCAEN	V_FW_EQ_OFLD_CMD_DCAEN(1U)
+
+#define S_FW_EQ_OFLD_CMD_DCACPU		26
+#define M_FW_EQ_OFLD_CMD_DCACPU		0x1f
+#define V_FW_EQ_OFLD_CMD_DCACPU(x)	((x) << S_FW_EQ_OFLD_CMD_DCACPU)
+#define G_FW_EQ_OFLD_CMD_DCACPU(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU)
+
+#define S_FW_EQ_OFLD_CMD_FBMIN		23
+#define M_FW_EQ_OFLD_CMD_FBMIN		0x7
+#define V_FW_EQ_OFLD_CMD_FBMIN(x)	((x) << S_FW_EQ_OFLD_CMD_FBMIN)
+#define G_FW_EQ_OFLD_CMD_FBMIN(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN)
+
+#define S_FW_EQ_OFLD_CMD_FBMAX		20
+#define M_FW_EQ_OFLD_CMD_FBMAX		0x7
+#define V_FW_EQ_OFLD_CMD_FBMAX(x)	((x) << S_FW_EQ_OFLD_CMD_FBMAX)
+#define G_FW_EQ_OFLD_CMD_FBMAX(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX)
+
+#define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO		19
+#define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO		0x1
+#define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x)	\
+    ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO)
+#define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO)
+#define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO	V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U)
+
+#define S_FW_EQ_OFLD_CMD_CIDXFTHRESH	16
+#define M_FW_EQ_OFLD_CMD_CIDXFTHRESH	0x7
+#define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x)	((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH)
+#define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH)
+
+#define S_FW_EQ_OFLD_CMD_EQSIZE		0
+#define M_FW_EQ_OFLD_CMD_EQSIZE		0xffff
+#define V_FW_EQ_OFLD_CMD_EQSIZE(x)	((x) << S_FW_EQ_OFLD_CMD_EQSIZE)
+#define G_FW_EQ_OFLD_CMD_EQSIZE(x)	\
+    (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE)
+
+/* Macros for VIID parsing:
+   VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */
+#define S_FW_VIID_PFN		8
+#define M_FW_VIID_PFN		0x7
+#define V_FW_VIID_PFN(x)	((x) << S_FW_VIID_PFN)
+#define G_FW_VIID_PFN(x)	(((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN)
+
+#define S_FW_VIID_VIVLD		7
+#define M_FW_VIID_VIVLD		0x1
+#define V_FW_VIID_VIVLD(x)	((x) << S_FW_VIID_VIVLD)
+#define G_FW_VIID_VIVLD(x)	(((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD)
+
+#define S_FW_VIID_VIN		0
+#define M_FW_VIID_VIN		0x7F
+#define V_FW_VIID_VIN(x)	((x) << S_FW_VIID_VIN)
+#define G_FW_VIID_VIN(x)	(((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN)
+
+enum fw_vi_func {
+	FW_VI_FUNC_ETH,
+	FW_VI_FUNC_OFLD,
+	FW_VI_FUNC_IWARP,
+	FW_VI_FUNC_OPENISCSI,
+	FW_VI_FUNC_OPENFCOE,
+	FW_VI_FUNC_FOISCSI,
+	FW_VI_FUNC_FOFCOE,
+	FW_VI_FUNC_FW,
+};
+
+struct fw_vi_cmd {
+	__be32 op_to_vfn;
+	__be32 alloc_to_len16;
+	__be16 type_to_viid;
+	__u8   mac[6];
+	__u8   portid_pkd;
+	__u8   nmac;
+	__u8   nmac0[6];
+	__be16 norss_rsssize;
+	__u8   nmac1[6];
+	__be16 idsiiq_pkd;
+	__u8   nmac2[6];
+	__be16 idseiq_pkd;
+	__u8   nmac3[6];
+	__be64 r9;
+	__be64 r10;
+};
+
+#define S_FW_VI_CMD_PFN		8
+#define M_FW_VI_CMD_PFN		0x7
+#define V_FW_VI_CMD_PFN(x)	((x) << S_FW_VI_CMD_PFN)
+#define G_FW_VI_CMD_PFN(x)	(((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
+
+#define S_FW_VI_CMD_VFN		0
+#define M_FW_VI_CMD_VFN		0xff
+#define V_FW_VI_CMD_VFN(x)	((x) << S_FW_VI_CMD_VFN)
+#define G_FW_VI_CMD_VFN(x)	(((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
+
+#define S_FW_VI_CMD_ALLOC	31
+#define M_FW_VI_CMD_ALLOC	0x1
+#define V_FW_VI_CMD_ALLOC(x)	((x) << S_FW_VI_CMD_ALLOC)
+#define G_FW_VI_CMD_ALLOC(x)	\
+    (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
+#define F_FW_VI_CMD_ALLOC	V_FW_VI_CMD_ALLOC(1U)
+
+#define S_FW_VI_CMD_FREE	30
+#define M_FW_VI_CMD_FREE	0x1
+#define V_FW_VI_CMD_FREE(x)	((x) << S_FW_VI_CMD_FREE)
+#define G_FW_VI_CMD_FREE(x)	(((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
+#define F_FW_VI_CMD_FREE	V_FW_VI_CMD_FREE(1U)
+
+#define S_FW_VI_CMD_TYPE	15
+#define M_FW_VI_CMD_TYPE	0x1
+#define V_FW_VI_CMD_TYPE(x)	((x) << S_FW_VI_CMD_TYPE)
+#define G_FW_VI_CMD_TYPE(x)	(((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
+#define F_FW_VI_CMD_TYPE	V_FW_VI_CMD_TYPE(1U)
+
+#define S_FW_VI_CMD_FUNC	12
+#define M_FW_VI_CMD_FUNC	0x7
+#define V_FW_VI_CMD_FUNC(x)	((x) << S_FW_VI_CMD_FUNC)
+#define G_FW_VI_CMD_FUNC(x)	(((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
+
+#define S_FW_VI_CMD_VIID	0
+#define M_FW_VI_CMD_VIID	0xfff
+#define V_FW_VI_CMD_VIID(x)	((x) << S_FW_VI_CMD_VIID)
+#define G_FW_VI_CMD_VIID(x)	(((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
+
+#define S_FW_VI_CMD_PORTID	4
+#define M_FW_VI_CMD_PORTID	0xf
+#define V_FW_VI_CMD_PORTID(x)	((x) << S_FW_VI_CMD_PORTID)
+#define G_FW_VI_CMD_PORTID(x)	\
+    (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
+
+#define S_FW_VI_CMD_NORSS	11
+#define M_FW_VI_CMD_NORSS	0x1
+#define V_FW_VI_CMD_NORSS(x)	((x) << S_FW_VI_CMD_NORSS)
+#define G_FW_VI_CMD_NORSS(x)	\
+    (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS)
+#define F_FW_VI_CMD_NORSS	V_FW_VI_CMD_NORSS(1U)
+
+#define S_FW_VI_CMD_RSSSIZE	0
+#define M_FW_VI_CMD_RSSSIZE	0x7ff
+#define V_FW_VI_CMD_RSSSIZE(x)	((x) << S_FW_VI_CMD_RSSSIZE)
+#define G_FW_VI_CMD_RSSSIZE(x)	\
+    (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
+
+#define S_FW_VI_CMD_IDSIIQ	0
+#define M_FW_VI_CMD_IDSIIQ	0x3ff
+#define V_FW_VI_CMD_IDSIIQ(x)	((x) << S_FW_VI_CMD_IDSIIQ)
+#define G_FW_VI_CMD_IDSIIQ(x)	\
+    (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ)
+
+#define S_FW_VI_CMD_IDSEIQ	0
+#define M_FW_VI_CMD_IDSEIQ	0x3ff
+#define V_FW_VI_CMD_IDSEIQ(x)	((x) << S_FW_VI_CMD_IDSEIQ)
+#define G_FW_VI_CMD_IDSEIQ(x)	\
+    (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ)
+
+/* Special VI_MAC command index ids */
+#define FW_VI_MAC_ADD_MAC		0x3FF
+#define FW_VI_MAC_ADD_PERSIST_MAC	0x3FE
+#define FW_VI_MAC_MAC_BASED_FREE	0x3FD
+
+enum fw_vi_mac_smac {
+	FW_VI_MAC_MPS_TCAM_ENTRY,
+	FW_VI_MAC_MPS_TCAM_ONLY,
+	FW_VI_MAC_SMT_ONLY,
+	FW_VI_MAC_SMT_AND_MPSTCAM
+};
+
+enum fw_vi_mac_result {
+	FW_VI_MAC_R_SUCCESS,
+	FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
+	FW_VI_MAC_R_SMAC_FAIL,
+	FW_VI_MAC_R_F_ACL_CHECK
+};
+
+struct fw_vi_mac_cmd {
+	__be32 op_to_viid;
+	__be32 freemacs_to_len16;
+	union fw_vi_mac {
+		struct fw_vi_mac_exact {
+			__be16 valid_to_idx;
+			__u8   macaddr[6];
+		} exact[7];
+		struct fw_vi_mac_hash {
+			__be64 hashvec;
+		} hash;
+	} u;
+};
+
+#define S_FW_VI_MAC_CMD_VIID	0
+#define M_FW_VI_MAC_CMD_VIID	0xfff
+#define V_FW_VI_MAC_CMD_VIID(x)	((x) << S_FW_VI_MAC_CMD_VIID)
+#define G_FW_VI_MAC_CMD_VIID(x)	\
+    (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
+
+#define S_FW_VI_MAC_CMD_FREEMACS	31
+#define M_FW_VI_MAC_CMD_FREEMACS	0x1
+#define V_FW_VI_MAC_CMD_FREEMACS(x)	((x) << S_FW_VI_MAC_CMD_FREEMACS)
+#define G_FW_VI_MAC_CMD_FREEMACS(x)	\
+    (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS)
+#define F_FW_VI_MAC_CMD_FREEMACS	V_FW_VI_MAC_CMD_FREEMACS(1U)
+
+#define S_FW_VI_MAC_CMD_HASHVECEN	23
+#define M_FW_VI_MAC_CMD_HASHVECEN	0x1
+#define V_FW_VI_MAC_CMD_HASHVECEN(x)	((x) << S_FW_VI_MAC_CMD_HASHVECEN)
+#define G_FW_VI_MAC_CMD_HASHVECEN(x)	\
+    (((x) >> S_FW_VI_MAC_CMD_HASHVECEN) & M_FW_VI_MAC_CMD_HASHVECEN)
+#define F_FW_VI_MAC_CMD_HASHVECEN	V_FW_VI_MAC_CMD_HASHVECEN(1U)
+
+#define S_FW_VI_MAC_CMD_HASHUNIEN	22
+#define M_FW_VI_MAC_CMD_HASHUNIEN	0x1
+#define V_FW_VI_MAC_CMD_HASHUNIEN(x)	((x) << S_FW_VI_MAC_CMD_HASHUNIEN)
+#define G_FW_VI_MAC_CMD_HASHUNIEN(x)	\
+    (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN)
+#define F_FW_VI_MAC_CMD_HASHUNIEN	V_FW_VI_MAC_CMD_HASHUNIEN(1U)
+
+#define S_FW_VI_MAC_CMD_VALID		15
+#define M_FW_VI_MAC_CMD_VALID		0x1
+#define V_FW_VI_MAC_CMD_VALID(x)	((x) << S_FW_VI_MAC_CMD_VALID)
+#define G_FW_VI_MAC_CMD_VALID(x)	\
+    (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
+#define F_FW_VI_MAC_CMD_VALID	V_FW_VI_MAC_CMD_VALID(1U)
+
+#define S_FW_VI_MAC_CMD_PRIO	12
+#define M_FW_VI_MAC_CMD_PRIO	0x7
+#define V_FW_VI_MAC_CMD_PRIO(x)	((x) << S_FW_VI_MAC_CMD_PRIO)
+#define G_FW_VI_MAC_CMD_PRIO(x)	\
+    (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO)
+
+#define S_FW_VI_MAC_CMD_SMAC_RESULT	10
+#define M_FW_VI_MAC_CMD_SMAC_RESULT	0x3
+#define V_FW_VI_MAC_CMD_SMAC_RESULT(x)	((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
+#define G_FW_VI_MAC_CMD_SMAC_RESULT(x)	\
+    (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
+
+#define S_FW_VI_MAC_CMD_IDX	0
+#define M_FW_VI_MAC_CMD_IDX	0x3ff
+#define V_FW_VI_MAC_CMD_IDX(x)	((x) << S_FW_VI_MAC_CMD_IDX)
+#define G_FW_VI_MAC_CMD_IDX(x)	\
+    (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
+
+/* T4 max MTU supported */
+#define T4_MAX_MTU_SUPPORTED	9600
+#define FW_RXMODE_MTU_NO_CHG	65535
+
+struct fw_vi_rxmode_cmd {
+	__be32 op_to_viid;
+	__be32 retval_len16;
+	__be32 mtu_to_vlanexen;
+	__be32 r4_lo;
+};
+
+#define S_FW_VI_RXMODE_CMD_VIID		0
+#define M_FW_VI_RXMODE_CMD_VIID		0xfff
+#define V_FW_VI_RXMODE_CMD_VIID(x)	((x) << S_FW_VI_RXMODE_CMD_VIID)
+#define G_FW_VI_RXMODE_CMD_VIID(x)	\
+    (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
+
+#define S_FW_VI_RXMODE_CMD_MTU		16
+#define M_FW_VI_RXMODE_CMD_MTU		0xffff
+#define V_FW_VI_RXMODE_CMD_MTU(x)	((x) << S_FW_VI_RXMODE_CMD_MTU)
+#define G_FW_VI_RXMODE_CMD_MTU(x)	\
+    (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
+
+#define S_FW_VI_RXMODE_CMD_PROMISCEN	14
+#define M_FW_VI_RXMODE_CMD_PROMISCEN	0x3
+#define V_FW_VI_RXMODE_CMD_PROMISCEN(x)	((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
+#define G_FW_VI_RXMODE_CMD_PROMISCEN(x)	\
+    (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
+
+#define S_FW_VI_RXMODE_CMD_ALLMULTIEN		12
+#define M_FW_VI_RXMODE_CMD_ALLMULTIEN		0x3
+#define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x)	\
+    ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
+#define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x)	\
+    (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
+
+#define S_FW_VI_RXMODE_CMD_BROADCASTEN		10
+#define M_FW_VI_RXMODE_CMD_BROADCASTEN		0x3
+#define V_FW_VI_RXMODE_CMD_BROADCASTEN(x)	\
+    ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
+#define G_FW_VI_RXMODE_CMD_BROADCASTEN(x)	\
+    (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN)
+
+#define S_FW_VI_RXMODE_CMD_VLANEXEN	8
+#define M_FW_VI_RXMODE_CMD_VLANEXEN	0x3
+#define V_FW_VI_RXMODE_CMD_VLANEXEN(x)	((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
+#define G_FW_VI_RXMODE_CMD_VLANEXEN(x)	\
+    (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
+
+struct fw_vi_enable_cmd {
+	__be32 op_to_viid;
+	__be32 ien_to_len16;
+	__be16 blinkdur;
+	__be16 r3;
+	__be32 r4;
+};
+
+#define S_FW_VI_ENABLE_CMD_VIID		0
+#define M_FW_VI_ENABLE_CMD_VIID		0xfff
+#define V_FW_VI_ENABLE_CMD_VIID(x)	((x) << S_FW_VI_ENABLE_CMD_VIID)
+#define G_FW_VI_ENABLE_CMD_VIID(x)	\
+    (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
+
+#define S_FW_VI_ENABLE_CMD_IEN		31
+#define M_FW_VI_ENABLE_CMD_IEN		0x1
+#define V_FW_VI_ENABLE_CMD_IEN(x)	((x) << S_FW_VI_ENABLE_CMD_IEN)
+#define G_FW_VI_ENABLE_CMD_IEN(x)	\
+    (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
+#define F_FW_VI_ENABLE_CMD_IEN	V_FW_VI_ENABLE_CMD_IEN(1U)
+
+#define S_FW_VI_ENABLE_CMD_EEN		30
+#define M_FW_VI_ENABLE_CMD_EEN		0x1
+#define V_FW_VI_ENABLE_CMD_EEN(x)	((x) << S_FW_VI_ENABLE_CMD_EEN)
+#define G_FW_VI_ENABLE_CMD_EEN(x)	\
+    (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
+#define F_FW_VI_ENABLE_CMD_EEN	V_FW_VI_ENABLE_CMD_EEN(1U)
+
+#define S_FW_VI_ENABLE_CMD_LED		29
+#define M_FW_VI_ENABLE_CMD_LED		0x1
+#define V_FW_VI_ENABLE_CMD_LED(x)	((x) << S_FW_VI_ENABLE_CMD_LED)
+#define G_FW_VI_ENABLE_CMD_LED(x)	\
+    (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED)
+#define F_FW_VI_ENABLE_CMD_LED	V_FW_VI_ENABLE_CMD_LED(1U)
+
+#define S_FW_VI_ENABLE_CMD_DCB_INFO	28
+#define M_FW_VI_ENABLE_CMD_DCB_INFO	0x1
+#define V_FW_VI_ENABLE_CMD_DCB_INFO(x)	((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
+#define G_FW_VI_ENABLE_CMD_DCB_INFO(x)	\
+    (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
+#define F_FW_VI_ENABLE_CMD_DCB_INFO	V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
+
+/* VI VF stats offset definitions */
+#define VI_VF_NUM_STATS	16
+enum fw_vi_stats_vf_index {
+	FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
+	FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
+	FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
+	FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
+	FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
+	FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
+	FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
+	FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
+	FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
+	FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
+	FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
+	FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
+	FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
+	FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
+	FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
+	FW_VI_VF_STAT_RX_ERR_FRAMES_IX
+};
+
+/* VI PF stats offset definitions */
+#define VI_PF_NUM_STATS	17
+enum fw_vi_stats_pf_index {
+	FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
+	FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
+	FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
+	FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
+	FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
+	FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
+	FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
+	FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
+	FW_VI_PF_STAT_RX_BYTES_IX,
+	FW_VI_PF_STAT_RX_FRAMES_IX,
+	FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
+	FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
+	FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
+	FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
+	FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
+	FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
+	FW_VI_PF_STAT_RX_ERR_FRAMES_IX
+};
+
+struct fw_vi_stats_cmd {
+	__be32 op_to_viid;
+	__be32 retval_len16;
+	union fw_vi_stats {
+		struct fw_vi_stats_ctl {
+			__be16 nstats_ix;
+			__be16 r6;
+			__be32 r7;
+			__be64 stat0;
+			__be64 stat1;
+			__be64 stat2;
+			__be64 stat3;
+			__be64 stat4;
+			__be64 stat5;
+		} ctl;
+		struct fw_vi_stats_pf {
+			__be64 tx_bcast_bytes;
+			__be64 tx_bcast_frames;
+			__be64 tx_mcast_bytes;
+			__be64 tx_mcast_frames;
+			__be64 tx_ucast_bytes;
+			__be64 tx_ucast_frames;
+			__be64 tx_offload_bytes;
+			__be64 tx_offload_frames;
+			__be64 rx_pf_bytes;
+			__be64 rx_pf_frames;
+			__be64 rx_bcast_bytes;
+			__be64 rx_bcast_frames;
+			__be64 rx_mcast_bytes;
+			__be64 rx_mcast_frames;
+			__be64 rx_ucast_bytes;
+			__be64 rx_ucast_frames;
+			__be64 rx_err_frames;
+		} pf;
+		struct fw_vi_stats_vf {
+			__be64 tx_bcast_bytes;
+			__be64 tx_bcast_frames;
+			__be64 tx_mcast_bytes;
+			__be64 tx_mcast_frames;
+			__be64 tx_ucast_bytes;
+			__be64 tx_ucast_frames;
+			__be64 tx_drop_frames;
+			__be64 tx_offload_bytes;
+			__be64 tx_offload_frames;
+			__be64 rx_bcast_bytes;
+			__be64 rx_bcast_frames;
+			__be64 rx_mcast_bytes;
+			__be64 rx_mcast_frames;
+			__be64 rx_ucast_bytes;
+			__be64 rx_ucast_frames;
+			__be64 rx_err_frames;
+		} vf;
+	} u;
+};
+
+#define S_FW_VI_STATS_CMD_VIID		0
+#define M_FW_VI_STATS_CMD_VIID		0xfff
+#define V_FW_VI_STATS_CMD_VIID(x)	((x) << S_FW_VI_STATS_CMD_VIID)
+#define G_FW_VI_STATS_CMD_VIID(x)	\
+    (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID)
+
+#define S_FW_VI_STATS_CMD_NSTATS	12
+#define M_FW_VI_STATS_CMD_NSTATS	0x7
+#define V_FW_VI_STATS_CMD_NSTATS(x)	((x) << S_FW_VI_STATS_CMD_NSTATS)
+#define G_FW_VI_STATS_CMD_NSTATS(x)	\
+    (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS)
+
+#define S_FW_VI_STATS_CMD_IX	0
+#define M_FW_VI_STATS_CMD_IX	0x1f
+#define V_FW_VI_STATS_CMD_IX(x)	((x) << S_FW_VI_STATS_CMD_IX)
+#define G_FW_VI_STATS_CMD_IX(x)	\
+    (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX)
+
+struct fw_acl_mac_cmd {
+	__be32 op_to_vfn;
+	__be32 en_to_len16;
+	__u8   nmac;
+	__u8   r3[7];
+	__be16 r4;
+	__u8   macaddr0[6];
+	__be16 r5;
+	__u8   macaddr1[6];
+	__be16 r6;
+	__u8   macaddr2[6];
+	__be16 r7;
+	__u8   macaddr3[6];
+};
+
+#define S_FW_ACL_MAC_CMD_PFN	8
+#define M_FW_ACL_MAC_CMD_PFN	0x7
+#define V_FW_ACL_MAC_CMD_PFN(x)	((x) << S_FW_ACL_MAC_CMD_PFN)
+#define G_FW_ACL_MAC_CMD_PFN(x)	\
+    (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN)
+
+#define S_FW_ACL_MAC_CMD_VFN	0
+#define M_FW_ACL_MAC_CMD_VFN	0xff
+#define V_FW_ACL_MAC_CMD_VFN(x)	((x) << S_FW_ACL_MAC_CMD_VFN)
+#define G_FW_ACL_MAC_CMD_VFN(x)	\
+    (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN)
+
+#define S_FW_ACL_MAC_CMD_EN	31
+#define M_FW_ACL_MAC_CMD_EN	0x1
+#define V_FW_ACL_MAC_CMD_EN(x)	((x) << S_FW_ACL_MAC_CMD_EN)
+#define G_FW_ACL_MAC_CMD_EN(x)	\
+    (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN)
+#define F_FW_ACL_MAC_CMD_EN	V_FW_ACL_MAC_CMD_EN(1U)
+
+struct fw_acl_vlan_cmd {
+	__be32 op_to_vfn;
+	__be32 en_to_len16;
+	__u8   nvlan;
+	__u8   dropnovlan_fm;
+	__u8   r3_lo[6];
+	__be16 vlanid[16];
+};
+
+#define S_FW_ACL_VLAN_CMD_PFN		8
+#define M_FW_ACL_VLAN_CMD_PFN		0x7
+#define V_FW_ACL_VLAN_CMD_PFN(x)	((x) << S_FW_ACL_VLAN_CMD_PFN)
+#define G_FW_ACL_VLAN_CMD_PFN(x)	\
+    (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN)
+
+#define S_FW_ACL_VLAN_CMD_VFN		0
+#define M_FW_ACL_VLAN_CMD_VFN		0xff
+#define V_FW_ACL_VLAN_CMD_VFN(x)	((x) << S_FW_ACL_VLAN_CMD_VFN)
+#define G_FW_ACL_VLAN_CMD_VFN(x)	\
+    (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN)
+
+#define S_FW_ACL_VLAN_CMD_EN	31
+#define M_FW_ACL_VLAN_CMD_EN	0x1
+#define V_FW_ACL_VLAN_CMD_EN(x)	((x) << S_FW_ACL_VLAN_CMD_EN)
+#define G_FW_ACL_VLAN_CMD_EN(x)	\
+    (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN)
+#define F_FW_ACL_VLAN_CMD_EN	V_FW_ACL_VLAN_CMD_EN(1U)
+
+#define S_FW_ACL_VLAN_CMD_DROPNOVLAN	7
+#define M_FW_ACL_VLAN_CMD_DROPNOVLAN	0x1
+#define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x)	((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN)
+#define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x)	\
+    (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN)
+#define F_FW_ACL_VLAN_CMD_DROPNOVLAN	V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U)
+
+#define S_FW_ACL_VLAN_CMD_FM	6
+#define M_FW_ACL_VLAN_CMD_FM	0x1
+#define V_FW_ACL_VLAN_CMD_FM(x)	((x) << S_FW_ACL_VLAN_CMD_FM)
+#define G_FW_ACL_VLAN_CMD_FM(x)	\
+    (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM)
+#define F_FW_ACL_VLAN_CMD_FM	V_FW_ACL_VLAN_CMD_FM(1U)
+
+/* port capabilities bitmap */
+enum fw_port_cap {
+	FW_PORT_CAP_SPEED_100M		= 0x0001,
+	FW_PORT_CAP_SPEED_1G		= 0x0002,
+	FW_PORT_CAP_SPEED_2_5G		= 0x0004,
+	FW_PORT_CAP_SPEED_10G		= 0x0008,
+	FW_PORT_CAP_SPEED_40G		= 0x0010,
+	FW_PORT_CAP_SPEED_100G		= 0x0020,
+	FW_PORT_CAP_FC_RX		= 0x0040,
+	FW_PORT_CAP_FC_TX		= 0x0080,
+	FW_PORT_CAP_ANEG		= 0x0100,
+	FW_PORT_CAP_MDIX		= 0x0200,
+	FW_PORT_CAP_MDIAUTO		= 0x0400,
+	FW_PORT_CAP_FEC			= 0x0800,
+	FW_PORT_CAP_TECHKR		= 0x1000,
+	FW_PORT_CAP_TECHKX4		= 0x2000,
+};
+
+#define S_FW_PORT_AUXLINFO_MDI		3
+#define M_FW_PORT_AUXLINFO_MDI		0x3
+#define V_FW_PORT_AUXLINFO_MDI(x)	((x) << S_FW_PORT_AUXLINFO_MDI)
+#define G_FW_PORT_AUXLINFO_MDI(x) \
+    (((x) >> S_FW_PORT_AUXLINFO_MDI) & M_FW_PORT_AUXLINFO_MDI)
+
+#define S_FW_PORT_AUXLINFO_KX4		2
+#define M_FW_PORT_AUXLINFO_KX4		0x1
+#define V_FW_PORT_AUXLINFO_KX4(x)	((x) << S_FW_PORT_AUXLINFO_KX4)
+#define G_FW_PORT_AUXLINFO_KX4(x) \
+    (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4)
+#define F_FW_PORT_AUXLINFO_KX4		V_FW_PORT_AUXLINFO_KX4(1U)
+
+#define S_FW_PORT_AUXLINFO_KR		1
+#define M_FW_PORT_AUXLINFO_KR		0x1
+#define V_FW_PORT_AUXLINFO_KR(x)	((x) << S_FW_PORT_AUXLINFO_KR)
+#define G_FW_PORT_AUXLINFO_KR(x) \
+    (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR)
+#define F_FW_PORT_AUXLINFO_KR		V_FW_PORT_AUXLINFO_KR(1U)
+
+#define S_FW_PORT_AUXLINFO_FEC		0
+#define M_FW_PORT_AUXLINFO_FEC		0x1
+#define V_FW_PORT_AUXLINFO_FEC(x)	((x) << S_FW_PORT_AUXLINFO_FEC)
+#define G_FW_PORT_AUXLINFO_FEC(x) \
+    (((x) >> S_FW_PORT_AUXLINFO_FEC) & M_FW_PORT_AUXLINFO_FEC) 
+#define F_FW_PORT_AUXLINFO_FEC		V_FW_PORT_AUXLINFO_FEC(1U)
+
+#define S_FW_PORT_RCAP_AUX	11
+#define M_FW_PORT_RCAP_AUX	0x7
+#define V_FW_PORT_RCAP_AUX(x)	((x) << S_FW_PORT_RCAP_AUX)
+#define G_FW_PORT_RCAP_AUX(x) \
+    (((x) >> S_FW_PORT_RCAP_AUX) & M_FW_PORT_RCAP_AUX)
+
+#define S_FW_PORT_CAP_SPEED	0
+#define M_FW_PORT_CAP_SPEED	0x3f
+#define V_FW_PORT_CAP_SPEED(x)	((x) << S_FW_PORT_CAP_SPEED)
+#define G_FW_PORT_CAP_SPEED(x) \
+    (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
+
+#define S_FW_PORT_CAP_FC	6
+#define M_FW_PORT_CAP_FC	0x3
+#define V_FW_PORT_CAP_FC(x)	((x) << S_FW_PORT_CAP_FC)
+#define G_FW_PORT_CAP_FC(x) \
+    (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC)
+
+#define S_FW_PORT_CAP_ANEG	8
+#define M_FW_PORT_CAP_ANEG	0x1
+#define V_FW_PORT_CAP_ANEG(x)	((x) << S_FW_PORT_CAP_ANEG)
+#define G_FW_PORT_CAP_ANEG(x) \
+    (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG)
+
+enum fw_port_mdi {
+	FW_PORT_CAP_MDI_UNCHANGED,
+	FW_PORT_CAP_MDI_AUTO,
+	FW_PORT_CAP_MDI_F_STRAIGHT,
+	FW_PORT_CAP_MDI_F_CROSSOVER
+};
+
+#define S_FW_PORT_CAP_MDI 9
+#define M_FW_PORT_CAP_MDI 3
+#define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
+#define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
+
+enum fw_port_action {
+	FW_PORT_ACTION_L1_CFG		= 0x0001,
+	FW_PORT_ACTION_L2_CFG		= 0x0002,
+	FW_PORT_ACTION_GET_PORT_INFO	= 0x0003,
+	FW_PORT_ACTION_L2_PPP_CFG	= 0x0004,
+	FW_PORT_ACTION_L2_DCB_CFG	= 0x0005,
+	FW_PORT_ACTION_DCB_READ_TRANS	= 0x0006,
+	FW_PORT_ACTION_DCB_READ_RECV	= 0x0007,
+	FW_PORT_ACTION_DCB_READ_DET	= 0x0008,
+	FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
+	FW_PORT_ACTION_L1_LOW_PWR_EN	= 0x0011,
+	FW_PORT_ACTION_L2_WOL_MODE_EN	= 0x0012,
+	FW_PORT_ACTION_LPBK_TO_NORMAL	= 0x0020,
+	FW_PORT_ACTION_LPBK_SS_ASIC	= 0x0022,
+	FW_PORT_ACTION_LPBK_WS_ASIC	= 0x0023,
+	FW_PORT_ACTION_LPBK_WS_EXT_PHY	= 0x0025,
+	FW_PORT_ACTION_LPBK_SS_EXT	= 0x0026,
+	FW_PORT_ACTION_DIAGNOSTICS	= 0x0027,
+	FW_PORT_ACTION_LPBK_SS_EXT_PHY	= 0x0028,
+	FW_PORT_ACTION_PHY_RESET	= 0x0040,
+	FW_PORT_ACTION_PMA_RESET	= 0x0041,
+	FW_PORT_ACTION_PCS_RESET	= 0x0042,
+	FW_PORT_ACTION_PHYXS_RESET	= 0x0043,
+	FW_PORT_ACTION_DTEXS_REEST	= 0x0044,
+	FW_PORT_ACTION_AN_RESET		= 0x0045,
+
+};
+
+enum fw_port_l2cfg_ctlbf {
+	FW_PORT_L2_CTLBF_OVLAN0	= 0x01,
+	FW_PORT_L2_CTLBF_OVLAN1	= 0x02,
+	FW_PORT_L2_CTLBF_OVLAN2	= 0x04,
+	FW_PORT_L2_CTLBF_OVLAN3	= 0x08,
+	FW_PORT_L2_CTLBF_IVLAN	= 0x10,
+	FW_PORT_L2_CTLBF_TXIPG	= 0x20,
+	FW_PORT_L2_CTLBF_MTU	= 0x40
+};
+
+enum fw_dcb_app_tlv_sf {
+	FW_DCB_APP_SF_ETHERTYPE,
+	FW_DCB_APP_SF_SOCKET_TCP,
+	FW_DCB_APP_SF_SOCKET_UDP,
+	FW_DCB_APP_SF_SOCKET_ALL,
+};
+
+enum fw_port_dcb_versions {
+	FW_PORT_DCB_VER_CEE1D0,
+	FW_PORT_DCB_VER_CEE1D01,
+	FW_PORT_DCB_VER_IEEE,
+	FW_PORT_DCB_VER_UNKNOWN=7
+};
+
+enum fw_port_dcb_cfg {
+	FW_PORT_DCB_CFG_PG	= 0x01,
+	FW_PORT_DCB_CFG_PFC	= 0x02,
+	FW_PORT_DCB_CFG_APPL	= 0x04
+};
+
+enum fw_port_dcb_cfg_rc {
+	FW_PORT_DCB_CFG_SUCCESS	= 0x0,
+	FW_PORT_DCB_CFG_ERROR	= 0x1
+};
+
+enum fw_port_dcb_type {
+	FW_PORT_DCB_TYPE_PGID		= 0x00,
+	FW_PORT_DCB_TYPE_PGRATE		= 0x01,
+	FW_PORT_DCB_TYPE_PRIORATE	= 0x02,
+	FW_PORT_DCB_TYPE_PFC		= 0x03,
+	FW_PORT_DCB_TYPE_APP_ID		= 0x04,
+	FW_PORT_DCB_TYPE_CONTROL	= 0x05,
+};
+
+enum fw_port_dcb_feature_state {
+	FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
+	FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
+	FW_PORT_DCB_FEATURE_STATE_ERROR	= 0x2,
+	FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
+};
+
+enum fw_port_diag_ops {
+	FW_PORT_DIAGS_TEMP		= 0x00,
+	FW_PORT_DIAGS_TX_POWER		= 0x01,
+	FW_PORT_DIAGS_RX_POWER		= 0x02,
+};
+
+struct fw_port_cmd {
+	__be32 op_to_portid;
+	__be32 action_to_len16;
+	union fw_port {
+		struct fw_port_l1cfg {
+			__be32 rcap;
+			__be32 r;
+		} l1cfg;
+		struct fw_port_l2cfg {
+			__u8   ctlbf;
+			__u8   ovlan3_to_ivlan0;
+			__be16 ivlantype;
+			__be16 txipg_force_pinfo;
+			__be16 mtu;
+			__be16 ovlan0mask;
+			__be16 ovlan0type;
+			__be16 ovlan1mask;
+			__be16 ovlan1type;
+			__be16 ovlan2mask;
+			__be16 ovlan2type;
+			__be16 ovlan3mask;
+			__be16 ovlan3type;
+		} l2cfg;
+		struct fw_port_info {
+			__be32 lstatus_to_modtype;
+			__be16 pcap;
+			__be16 acap;
+			__be16 mtu;
+			__u8   cbllen;
+			__u8   auxlinfo;
+			__u8   dcbxdis_pkd;
+			__u8   r8_lo[3];
+			__be64 r9;
+		} info;
+		struct fw_port_diags {
+			__u8   diagop;
+			__u8   r[3];
+			__be32 diagval;
+		} diags;
+		union fw_port_dcb {
+			struct fw_port_dcb_pgid {
+				__u8   type;
+				__u8   apply_pkd;
+				__u8   r10_lo[2];
+				__be32 pgid;
+				__be64 r11;
+			} pgid;
+			struct fw_port_dcb_pgrate {
+				__u8   type;
+				__u8   apply_pkd;
+				__u8   r10_lo[5];
+				__u8   num_tcs_supported;
+				__u8   pgrate[8];
+			} pgrate;
+			struct fw_port_dcb_priorate {
+				__u8   type;
+				__u8   apply_pkd;
+				__u8   r10_lo[6];
+				__u8   strict_priorate[8];
+			} priorate;
+			struct fw_port_dcb_pfc {
+				__u8   type;
+				__u8   pfcen;
+				__be16 r10[3];
+				__be64 r11;
+			} pfc;
+			struct fw_port_app_priority {
+				__u8   type;
+				__u8   r10[2];
+				__u8   idx;
+				__u8   user_prio_map;
+				__u8   sel_field;
+				__be16 protocolid;
+				__be64 r12;
+			} app_priority;
+			struct fw_port_dcb_control {
+				__u8   type;
+				__u8   all_syncd_pkd;
+				__be16 pfc_state_to_app_state;
+				__be32 r11;
+				__be64 r12;
+			} control;
+		} dcb;
+	} u;
+};
+
+#define S_FW_PORT_CMD_READ	22
+#define M_FW_PORT_CMD_READ	0x1
+#define V_FW_PORT_CMD_READ(x)	((x) << S_FW_PORT_CMD_READ)
+#define G_FW_PORT_CMD_READ(x)	\
+    (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ)
+#define F_FW_PORT_CMD_READ	V_FW_PORT_CMD_READ(1U)
+
+#define S_FW_PORT_CMD_PORTID	0
+#define M_FW_PORT_CMD_PORTID	0xf
+#define V_FW_PORT_CMD_PORTID(x)	((x) << S_FW_PORT_CMD_PORTID)
+#define G_FW_PORT_CMD_PORTID(x)	\
+    (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
+
+#define S_FW_PORT_CMD_ACTION	16
+#define M_FW_PORT_CMD_ACTION	0xffff
+#define V_FW_PORT_CMD_ACTION(x)	((x) << S_FW_PORT_CMD_ACTION)
+#define G_FW_PORT_CMD_ACTION(x)	\
+    (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
+
+#define S_FW_PORT_CMD_OVLAN3	7
+#define M_FW_PORT_CMD_OVLAN3	0x1
+#define V_FW_PORT_CMD_OVLAN3(x)	((x) << S_FW_PORT_CMD_OVLAN3)
+#define G_FW_PORT_CMD_OVLAN3(x)	\
+    (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3)
+#define F_FW_PORT_CMD_OVLAN3	V_FW_PORT_CMD_OVLAN3(1U)
+
+#define S_FW_PORT_CMD_OVLAN2	6
+#define M_FW_PORT_CMD_OVLAN2	0x1
+#define V_FW_PORT_CMD_OVLAN2(x)	((x) << S_FW_PORT_CMD_OVLAN2)
+#define G_FW_PORT_CMD_OVLAN2(x)	\
+    (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2)
+#define F_FW_PORT_CMD_OVLAN2	V_FW_PORT_CMD_OVLAN2(1U)
+
+#define S_FW_PORT_CMD_OVLAN1	5
+#define M_FW_PORT_CMD_OVLAN1	0x1
+#define V_FW_PORT_CMD_OVLAN1(x)	((x) << S_FW_PORT_CMD_OVLAN1)
+#define G_FW_PORT_CMD_OVLAN1(x)	\
+    (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1)
+#define F_FW_PORT_CMD_OVLAN1	V_FW_PORT_CMD_OVLAN1(1U)
+
+#define S_FW_PORT_CMD_OVLAN0	4
+#define M_FW_PORT_CMD_OVLAN0	0x1
+#define V_FW_PORT_CMD_OVLAN0(x)	((x) << S_FW_PORT_CMD_OVLAN0)
+#define G_FW_PORT_CMD_OVLAN0(x)	\
+    (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0)
+#define F_FW_PORT_CMD_OVLAN0	V_FW_PORT_CMD_OVLAN0(1U)
+
+#define S_FW_PORT_CMD_IVLAN0	3
+#define M_FW_PORT_CMD_IVLAN0	0x1
+#define V_FW_PORT_CMD_IVLAN0(x)	((x) << S_FW_PORT_CMD_IVLAN0)
+#define G_FW_PORT_CMD_IVLAN0(x)	\
+    (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0)
+#define F_FW_PORT_CMD_IVLAN0	V_FW_PORT_CMD_IVLAN0(1U)
+
+#define S_FW_PORT_CMD_TXIPG	3
+#define M_FW_PORT_CMD_TXIPG	0x1fff
+#define V_FW_PORT_CMD_TXIPG(x)	((x) << S_FW_PORT_CMD_TXIPG)
+#define G_FW_PORT_CMD_TXIPG(x)	\
+    (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG)
+
+#define S_FW_PORT_CMD_FORCE_PINFO	0
+#define M_FW_PORT_CMD_FORCE_PINFO	0x1
+#define V_FW_PORT_CMD_FORCE_PINFO(x)	((x) << S_FW_PORT_CMD_FORCE_PINFO)
+#define G_FW_PORT_CMD_FORCE_PINFO(x)	\
+    (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO)
+#define F_FW_PORT_CMD_FORCE_PINFO	V_FW_PORT_CMD_FORCE_PINFO(1U)
+
+#define S_FW_PORT_CMD_LSTATUS		31
+#define M_FW_PORT_CMD_LSTATUS		0x1
+#define V_FW_PORT_CMD_LSTATUS(x)	((x) << S_FW_PORT_CMD_LSTATUS)
+#define G_FW_PORT_CMD_LSTATUS(x)	\
+    (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
+#define F_FW_PORT_CMD_LSTATUS	V_FW_PORT_CMD_LSTATUS(1U)
+
+#define S_FW_PORT_CMD_LSPEED	24
+#define M_FW_PORT_CMD_LSPEED	0x3f
+#define V_FW_PORT_CMD_LSPEED(x)	((x) << S_FW_PORT_CMD_LSPEED)
+#define G_FW_PORT_CMD_LSPEED(x)	\
+    (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
+
+#define S_FW_PORT_CMD_TXPAUSE		23
+#define M_FW_PORT_CMD_TXPAUSE		0x1
+#define V_FW_PORT_CMD_TXPAUSE(x)	((x) << S_FW_PORT_CMD_TXPAUSE)
+#define G_FW_PORT_CMD_TXPAUSE(x)	\
+    (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
+#define F_FW_PORT_CMD_TXPAUSE	V_FW_PORT_CMD_TXPAUSE(1U)
+
+#define S_FW_PORT_CMD_RXPAUSE		22
+#define M_FW_PORT_CMD_RXPAUSE		0x1
+#define V_FW_PORT_CMD_RXPAUSE(x)	((x) << S_FW_PORT_CMD_RXPAUSE)
+#define G_FW_PORT_CMD_RXPAUSE(x)	\
+    (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
+#define F_FW_PORT_CMD_RXPAUSE	V_FW_PORT_CMD_RXPAUSE(1U)
+
+#define S_FW_PORT_CMD_MDIOCAP		21
+#define M_FW_PORT_CMD_MDIOCAP		0x1
+#define V_FW_PORT_CMD_MDIOCAP(x)	((x) << S_FW_PORT_CMD_MDIOCAP)
+#define G_FW_PORT_CMD_MDIOCAP(x)	\
+    (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
+#define F_FW_PORT_CMD_MDIOCAP	V_FW_PORT_CMD_MDIOCAP(1U)
+
+#define S_FW_PORT_CMD_MDIOADDR		16
+#define M_FW_PORT_CMD_MDIOADDR		0x1f
+#define V_FW_PORT_CMD_MDIOADDR(x)	((x) << S_FW_PORT_CMD_MDIOADDR)
+#define G_FW_PORT_CMD_MDIOADDR(x)	\
+    (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
+
+#define S_FW_PORT_CMD_LPTXPAUSE		15
+#define M_FW_PORT_CMD_LPTXPAUSE		0x1
+#define V_FW_PORT_CMD_LPTXPAUSE(x)	((x) << S_FW_PORT_CMD_LPTXPAUSE)
+#define G_FW_PORT_CMD_LPTXPAUSE(x)	\
+    (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE)
+#define F_FW_PORT_CMD_LPTXPAUSE	V_FW_PORT_CMD_LPTXPAUSE(1U)
+
+#define S_FW_PORT_CMD_LPRXPAUSE		14
+#define M_FW_PORT_CMD_LPRXPAUSE		0x1
+#define V_FW_PORT_CMD_LPRXPAUSE(x)	((x) << S_FW_PORT_CMD_LPRXPAUSE)
+#define G_FW_PORT_CMD_LPRXPAUSE(x)	\
+    (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE)
+#define F_FW_PORT_CMD_LPRXPAUSE	V_FW_PORT_CMD_LPRXPAUSE(1U)
+
+#define S_FW_PORT_CMD_PTYPE	8
+#define M_FW_PORT_CMD_PTYPE	0x1f
+#define V_FW_PORT_CMD_PTYPE(x)	((x) << S_FW_PORT_CMD_PTYPE)
+#define G_FW_PORT_CMD_PTYPE(x)	\
+    (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
+
+#define S_FW_PORT_CMD_LINKDNRC		5
+#define M_FW_PORT_CMD_LINKDNRC		0x7
+#define V_FW_PORT_CMD_LINKDNRC(x)	((x) << S_FW_PORT_CMD_LINKDNRC)
+#define G_FW_PORT_CMD_LINKDNRC(x)	\
+    (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
+
+#define S_FW_PORT_CMD_MODTYPE		0
+#define M_FW_PORT_CMD_MODTYPE		0x1f
+#define V_FW_PORT_CMD_MODTYPE(x)	((x) << S_FW_PORT_CMD_MODTYPE)
+#define G_FW_PORT_CMD_MODTYPE(x)	\
+    (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
+
+#define S_FW_PORT_CMD_DCBXDIS		7
+#define M_FW_PORT_CMD_DCBXDIS		0x1
+#define V_FW_PORT_CMD_DCBXDIS(x)	((x) << S_FW_PORT_CMD_DCBXDIS)
+#define G_FW_PORT_CMD_DCBXDIS(x)	\
+    (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS)
+#define F_FW_PORT_CMD_DCBXDIS	V_FW_PORT_CMD_DCBXDIS(1U)
+
+#define S_FW_PORT_CMD_APPLY	7
+#define M_FW_PORT_CMD_APPLY	0x1
+#define V_FW_PORT_CMD_APPLY(x)	((x) << S_FW_PORT_CMD_APPLY)
+#define G_FW_PORT_CMD_APPLY(x)	\
+    (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY)
+#define F_FW_PORT_CMD_APPLY	V_FW_PORT_CMD_APPLY(1U)
+
+#define S_FW_PORT_CMD_ALL_SYNCD		7
+#define M_FW_PORT_CMD_ALL_SYNCD		0x1
+#define V_FW_PORT_CMD_ALL_SYNCD(x)	((x) << S_FW_PORT_CMD_ALL_SYNCD)
+#define G_FW_PORT_CMD_ALL_SYNCD(x)	\
+    (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD)
+#define F_FW_PORT_CMD_ALL_SYNCD	V_FW_PORT_CMD_ALL_SYNCD(1U)
+
+#define S_FW_PORT_CMD_PFC_STATE		8
+#define M_FW_PORT_CMD_PFC_STATE		0xf
+#define V_FW_PORT_CMD_PFC_STATE(x)	((x) << S_FW_PORT_CMD_PFC_STATE)
+#define G_FW_PORT_CMD_PFC_STATE(x)	\
+    (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE)
+
+#define S_FW_PORT_CMD_ETS_STATE		4
+#define M_FW_PORT_CMD_ETS_STATE		0xf
+#define V_FW_PORT_CMD_ETS_STATE(x)	((x) << S_FW_PORT_CMD_ETS_STATE)
+#define G_FW_PORT_CMD_ETS_STATE(x)	\
+    (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE)
+
+#define S_FW_PORT_CMD_APP_STATE		0
+#define M_FW_PORT_CMD_APP_STATE		0xf
+#define V_FW_PORT_CMD_APP_STATE(x)	((x) << S_FW_PORT_CMD_APP_STATE)
+#define G_FW_PORT_CMD_APP_STATE(x)	\
+    (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE)
+
+/*
+ *	These are configured into the VPD and hence tools that generate
+ *	VPD may use this enumeration.
+ *	extPHY	#lanes	T4_I2C	extI2C	BP_Eq	BP_ANEG	Speed
+ *
+ *	REMEMBER:
+ *	    Update the Common Code t4_hw.c:t4_get_port_type_description()
+ *	    with any new Firmware Port Technology Types!
+ */
+enum fw_port_type {
+	FW_PORT_TYPE_FIBER_XFI	=  0,	/* Y, 1, N, Y, N, N, 10G */
+	FW_PORT_TYPE_FIBER_XAUI	=  1,	/* Y, 4, N, Y, N, N, 10G */
+	FW_PORT_TYPE_BT_SGMII	=  2,	/* Y, 1, No, No, No, No, 1G/100M */
+	FW_PORT_TYPE_BT_XFI	=  3,	/* Y, 1, No, No, No, No, 10G */
+	FW_PORT_TYPE_BT_XAUI	=  4,	/* Y, 4, No, No, No, No, 10G/1G/100M? */
+	FW_PORT_TYPE_KX4	=  5,	/* No, 4, No, No, Yes, Yes, 10G */
+	FW_PORT_TYPE_CX4	=  6,	/* No, 4, No, No, No, No, 10G */
+	FW_PORT_TYPE_KX		=  7,	/* No, 1, No, No, Yes, No, 1G */
+	FW_PORT_TYPE_KR		=  8,	/* No, 1, No, No, Yes, Yes, 10G */
+	FW_PORT_TYPE_SFP	=  9,	/* No, 1, Yes, No, No, No, 10G */
+	FW_PORT_TYPE_BP_AP	= 10,	/* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
+	FW_PORT_TYPE_BP4_AP	= 11,	/* No, 4, No, No, Yes, Yes, 10G, BP ANGE */
+	FW_PORT_TYPE_QSFP_10G	= 12,	/* No, 1, Yes, No, No, No, 10G */
+	FW_PORT_TYPE_QSFP	= 14,	/* No, 4, Yes, No, No, No, 40G */
+	FW_PORT_TYPE_BP40_BA	= 15,	/* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
+
+	FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE
+};
+
+/* These are read from module's EEPROM and determined once the
+   module is inserted. */
+enum fw_port_module_type {
+	FW_PORT_MOD_TYPE_NA		= 0x0,
+	FW_PORT_MOD_TYPE_LR		= 0x1,
+	FW_PORT_MOD_TYPE_SR		= 0x2,
+	FW_PORT_MOD_TYPE_ER		= 0x3,
+	FW_PORT_MOD_TYPE_TWINAX_PASSIVE	= 0x4,
+	FW_PORT_MOD_TYPE_TWINAX_ACTIVE	= 0x5,
+	FW_PORT_MOD_TYPE_LRM		= 0x6,
+	FW_PORT_MOD_TYPE_ERROR		= M_FW_PORT_CMD_MODTYPE - 3,
+	FW_PORT_MOD_TYPE_UNKNOWN	= M_FW_PORT_CMD_MODTYPE - 2,
+	FW_PORT_MOD_TYPE_NOTSUPPORTED	= M_FW_PORT_CMD_MODTYPE - 1,
+	FW_PORT_MOD_TYPE_NONE		= M_FW_PORT_CMD_MODTYPE
+};
+
+/* used by FW and tools may use this to generate VPD */
+enum fw_port_mod_sub_type {
+	FW_PORT_MOD_SUB_TYPE_NA,
+	FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1,
+	FW_PORT_MOD_SUB_TYPE_TN8022=0x2,
+	FW_PORT_MOD_SUB_TYPE_AQ1202=0x3,
+	FW_PORT_MOD_SUB_TYPE_88x3120=0x4,
+	FW_PORT_MOD_SUB_TYPE_BCM84834=0x5,
+	FW_PORT_MOD_SUB_TYPE_BCM5482=0x6,
+	FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8,
+
+	/*
+	 * The following will never been in the VPD.  They are TWINAX cable
+	 * lengths decoded from SFP+ module i2c PROMs.  These should almost
+	 * certainly go somewhere else ...
+	 */
+	FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9,
+	FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA,
+	FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB,
+	FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC,
+};
+
+/* link down reason codes (3b) */
+enum fw_port_link_dn_rc {
+	FW_PORT_LINK_DN_RC_NONE,
+	FW_PORT_LINK_DN_RC_REMFLT,	/* Remote fault detected */
+	FW_PORT_LINK_DN_ANEG_F,		/* Auto-negotiation fault */
+	FW_PORT_LINK_DN_RESERVED3,
+	FW_PORT_LINK_DN_OVERHEAT,	/* Port overheated */
+	FW_PORT_LINK_DN_UNKNOWN,	/* Unable to determine reason */
+	FW_PORT_LINK_DN_RX_LOS,		/* No RX signal detected */
+	FW_PORT_LINK_DN_RESERVED7
+};
+
+/* port stats */
+#define FW_NUM_PORT_STATS 50
+#define FW_NUM_PORT_TX_STATS 23
+#define FW_NUM_PORT_RX_STATS 27
+
+enum fw_port_stats_tx_index {
+	FW_STAT_TX_PORT_BYTES_IX,
+	FW_STAT_TX_PORT_FRAMES_IX,
+	FW_STAT_TX_PORT_BCAST_IX,
+	FW_STAT_TX_PORT_MCAST_IX,
+	FW_STAT_TX_PORT_UCAST_IX,
+	FW_STAT_TX_PORT_ERROR_IX,
+	FW_STAT_TX_PORT_64B_IX,
+	FW_STAT_TX_PORT_65B_127B_IX,
+	FW_STAT_TX_PORT_128B_255B_IX,
+	FW_STAT_TX_PORT_256B_511B_IX,
+	FW_STAT_TX_PORT_512B_1023B_IX,
+	FW_STAT_TX_PORT_1024B_1518B_IX,
+	FW_STAT_TX_PORT_1519B_MAX_IX,
+	FW_STAT_TX_PORT_DROP_IX,
+	FW_STAT_TX_PORT_PAUSE_IX,
+	FW_STAT_TX_PORT_PPP0_IX,
+	FW_STAT_TX_PORT_PPP1_IX,
+	FW_STAT_TX_PORT_PPP2_IX,
+	FW_STAT_TX_PORT_PPP3_IX,
+	FW_STAT_TX_PORT_PPP4_IX,
+	FW_STAT_TX_PORT_PPP5_IX,
+	FW_STAT_TX_PORT_PPP6_IX,
+	FW_STAT_TX_PORT_PPP7_IX
+};
+
+enum fw_port_stat_rx_index {
+	FW_STAT_RX_PORT_BYTES_IX,
+	FW_STAT_RX_PORT_FRAMES_IX,
+	FW_STAT_RX_PORT_BCAST_IX,
+	FW_STAT_RX_PORT_MCAST_IX,
+	FW_STAT_RX_PORT_UCAST_IX,
+	FW_STAT_RX_PORT_MTU_ERROR_IX,
+	FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
+	FW_STAT_RX_PORT_CRC_ERROR_IX,
+	FW_STAT_RX_PORT_LEN_ERROR_IX,
+	FW_STAT_RX_PORT_SYM_ERROR_IX,
+	FW_STAT_RX_PORT_64B_IX,
+	FW_STAT_RX_PORT_65B_127B_IX,
+	FW_STAT_RX_PORT_128B_255B_IX,
+	FW_STAT_RX_PORT_256B_511B_IX,
+	FW_STAT_RX_PORT_512B_1023B_IX,
+	FW_STAT_RX_PORT_1024B_1518B_IX,
+	FW_STAT_RX_PORT_1519B_MAX_IX,
+	FW_STAT_RX_PORT_PAUSE_IX,
+	FW_STAT_RX_PORT_PPP0_IX,
+	FW_STAT_RX_PORT_PPP1_IX,
+	FW_STAT_RX_PORT_PPP2_IX,
+	FW_STAT_RX_PORT_PPP3_IX,
+	FW_STAT_RX_PORT_PPP4_IX,
+	FW_STAT_RX_PORT_PPP5_IX,
+	FW_STAT_RX_PORT_PPP6_IX,
+	FW_STAT_RX_PORT_PPP7_IX,
+	FW_STAT_RX_PORT_LESS_64B_IX
+};
+
+struct fw_port_stats_cmd {
+	__be32 op_to_portid;
+	__be32 retval_len16;
+	union fw_port_stats {
+		struct fw_port_stats_ctl {
+			__u8   nstats_bg_bm;
+			__u8   tx_ix;
+			__be16 r6;
+			__be32 r7;
+			__be64 stat0;
+			__be64 stat1;
+			__be64 stat2;
+			__be64 stat3;
+			__be64 stat4;
+			__be64 stat5;
+		} ctl;
+		struct fw_port_stats_all {
+			__be64 tx_bytes;
+			__be64 tx_frames;
+			__be64 tx_bcast;
+			__be64 tx_mcast;
+			__be64 tx_ucast;
+			__be64 tx_error;
+			__be64 tx_64b;
+			__be64 tx_65b_127b;
+			__be64 tx_128b_255b;
+			__be64 tx_256b_511b;
+			__be64 tx_512b_1023b;
+			__be64 tx_1024b_1518b;
+			__be64 tx_1519b_max;
+			__be64 tx_drop;
+			__be64 tx_pause;
+			__be64 tx_ppp0;
+			__be64 tx_ppp1;
+			__be64 tx_ppp2;
+			__be64 tx_ppp3;
+			__be64 tx_ppp4;
+			__be64 tx_ppp5;
+			__be64 tx_ppp6;
+			__be64 tx_ppp7;
+			__be64 rx_bytes;
+			__be64 rx_frames;
+			__be64 rx_bcast;
+			__be64 rx_mcast;
+			__be64 rx_ucast;
+			__be64 rx_mtu_error;
+			__be64 rx_mtu_crc_error;
+			__be64 rx_crc_error;
+			__be64 rx_len_error;
+			__be64 rx_sym_error;
+			__be64 rx_64b;
+			__be64 rx_65b_127b;
+			__be64 rx_128b_255b;
+			__be64 rx_256b_511b;
+			__be64 rx_512b_1023b;
+			__be64 rx_1024b_1518b;
+			__be64 rx_1519b_max;
+			__be64 rx_pause;
+			__be64 rx_ppp0;
+			__be64 rx_ppp1;
+			__be64 rx_ppp2;
+			__be64 rx_ppp3;
+			__be64 rx_ppp4;
+			__be64 rx_ppp5;
+			__be64 rx_ppp6;
+			__be64 rx_ppp7;
+			__be64 rx_less_64b;
+			__be64 rx_bg_drop;
+			__be64 rx_bg_trunc;
+		} all;
+	} u;
+};
+
+#define S_FW_PORT_STATS_CMD_NSTATS	4
+#define M_FW_PORT_STATS_CMD_NSTATS	0x7
+#define V_FW_PORT_STATS_CMD_NSTATS(x)	((x) << S_FW_PORT_STATS_CMD_NSTATS)
+#define G_FW_PORT_STATS_CMD_NSTATS(x)	\
+    (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS)
+
+#define S_FW_PORT_STATS_CMD_BG_BM	0
+#define M_FW_PORT_STATS_CMD_BG_BM	0x3
+#define V_FW_PORT_STATS_CMD_BG_BM(x)	((x) << S_FW_PORT_STATS_CMD_BG_BM)
+#define G_FW_PORT_STATS_CMD_BG_BM(x)	\
+    (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM)
+
+#define S_FW_PORT_STATS_CMD_TX		7
+#define M_FW_PORT_STATS_CMD_TX		0x1
+#define V_FW_PORT_STATS_CMD_TX(x)	((x) << S_FW_PORT_STATS_CMD_TX)
+#define G_FW_PORT_STATS_CMD_TX(x)	\
+    (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX)
+#define F_FW_PORT_STATS_CMD_TX	V_FW_PORT_STATS_CMD_TX(1U)
+
+#define S_FW_PORT_STATS_CMD_IX		0
+#define M_FW_PORT_STATS_CMD_IX		0x3f
+#define V_FW_PORT_STATS_CMD_IX(x)	((x) << S_FW_PORT_STATS_CMD_IX)
+#define G_FW_PORT_STATS_CMD_IX(x)	\
+    (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX)
+
+/* port loopback stats */
+#define FW_NUM_LB_STATS 14
+enum fw_port_lb_stats_index {
+	FW_STAT_LB_PORT_BYTES_IX,
+	FW_STAT_LB_PORT_FRAMES_IX,
+	FW_STAT_LB_PORT_BCAST_IX,
+	FW_STAT_LB_PORT_MCAST_IX,
+	FW_STAT_LB_PORT_UCAST_IX,
+	FW_STAT_LB_PORT_ERROR_IX,
+	FW_STAT_LB_PORT_64B_IX,
+	FW_STAT_LB_PORT_65B_127B_IX,
+	FW_STAT_LB_PORT_128B_255B_IX,
+	FW_STAT_LB_PORT_256B_511B_IX,
+	FW_STAT_LB_PORT_512B_1023B_IX,
+	FW_STAT_LB_PORT_1024B_1518B_IX,
+	FW_STAT_LB_PORT_1519B_MAX_IX,
+	FW_STAT_LB_PORT_DROP_FRAMES_IX
+};
+
+struct fw_port_lb_stats_cmd {
+	__be32 op_to_lbport;
+	__be32 retval_len16;
+	union fw_port_lb_stats {
+		struct fw_port_lb_stats_ctl {
+			__u8   nstats_bg_bm;
+			__u8   ix_pkd;
+			__be16 r6;
+			__be32 r7;
+			__be64 stat0;
+			__be64 stat1;
+			__be64 stat2;
+			__be64 stat3;
+			__be64 stat4;
+			__be64 stat5;
+		} ctl;
+		struct fw_port_lb_stats_all {
+			__be64 tx_bytes;
+			__be64 tx_frames;
+			__be64 tx_bcast;
+			__be64 tx_mcast;
+			__be64 tx_ucast;
+			__be64 tx_error;
+			__be64 tx_64b;
+			__be64 tx_65b_127b;
+			__be64 tx_128b_255b;
+			__be64 tx_256b_511b;
+			__be64 tx_512b_1023b;
+			__be64 tx_1024b_1518b;
+			__be64 tx_1519b_max;
+			__be64 rx_lb_drop;
+			__be64 rx_lb_trunc;
+		} all;
+	} u;
+};
+
+#define S_FW_PORT_LB_STATS_CMD_LBPORT		0
+#define M_FW_PORT_LB_STATS_CMD_LBPORT		0xf
+#define V_FW_PORT_LB_STATS_CMD_LBPORT(x)	\
+    ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT)
+#define G_FW_PORT_LB_STATS_CMD_LBPORT(x)	\
+    (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT)
+
+#define S_FW_PORT_LB_STATS_CMD_NSTATS		4
+#define M_FW_PORT_LB_STATS_CMD_NSTATS		0x7
+#define V_FW_PORT_LB_STATS_CMD_NSTATS(x)	\
+    ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS)
+#define G_FW_PORT_LB_STATS_CMD_NSTATS(x)	\
+    (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS)
+
+#define S_FW_PORT_LB_STATS_CMD_BG_BM	0
+#define M_FW_PORT_LB_STATS_CMD_BG_BM	0x3
+#define V_FW_PORT_LB_STATS_CMD_BG_BM(x)	((x) << S_FW_PORT_LB_STATS_CMD_BG_BM)
+#define G_FW_PORT_LB_STATS_CMD_BG_BM(x)	\
+    (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM)
+
+#define S_FW_PORT_LB_STATS_CMD_IX	0
+#define M_FW_PORT_LB_STATS_CMD_IX	0xf
+#define V_FW_PORT_LB_STATS_CMD_IX(x)	((x) << S_FW_PORT_LB_STATS_CMD_IX)
+#define G_FW_PORT_LB_STATS_CMD_IX(x)	\
+    (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX)
+
+/* Trace related defines */
+#define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240
+#define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE  2560
+
+struct fw_port_trace_cmd {
+	__be32 op_to_portid;
+	__be32 retval_len16;
+	__be16 traceen_to_pciech;
+	__be16 qnum;
+	__be32 r5;
+};
+
+#define S_FW_PORT_TRACE_CMD_PORTID	0
+#define M_FW_PORT_TRACE_CMD_PORTID	0xf
+#define V_FW_PORT_TRACE_CMD_PORTID(x)	((x) << S_FW_PORT_TRACE_CMD_PORTID)
+#define G_FW_PORT_TRACE_CMD_PORTID(x)	\
+    (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID)
+
+#define S_FW_PORT_TRACE_CMD_TRACEEN	15
+#define M_FW_PORT_TRACE_CMD_TRACEEN	0x1
+#define V_FW_PORT_TRACE_CMD_TRACEEN(x)	((x) << S_FW_PORT_TRACE_CMD_TRACEEN)
+#define G_FW_PORT_TRACE_CMD_TRACEEN(x)	\
+    (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN)
+#define F_FW_PORT_TRACE_CMD_TRACEEN	V_FW_PORT_TRACE_CMD_TRACEEN(1U)
+
+#define S_FW_PORT_TRACE_CMD_FLTMODE	14
+#define M_FW_PORT_TRACE_CMD_FLTMODE	0x1
+#define V_FW_PORT_TRACE_CMD_FLTMODE(x)	((x) << S_FW_PORT_TRACE_CMD_FLTMODE)
+#define G_FW_PORT_TRACE_CMD_FLTMODE(x)	\
+    (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE)
+#define F_FW_PORT_TRACE_CMD_FLTMODE	V_FW_PORT_TRACE_CMD_FLTMODE(1U)
+
+#define S_FW_PORT_TRACE_CMD_DUPLEN	13
+#define M_FW_PORT_TRACE_CMD_DUPLEN	0x1
+#define V_FW_PORT_TRACE_CMD_DUPLEN(x)	((x) << S_FW_PORT_TRACE_CMD_DUPLEN)
+#define G_FW_PORT_TRACE_CMD_DUPLEN(x)	\
+    (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN)
+#define F_FW_PORT_TRACE_CMD_DUPLEN	V_FW_PORT_TRACE_CMD_DUPLEN(1U)
+
+#define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE		8
+#define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE		0x1f
+#define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x)	\
+    ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE)
+#define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x)	\
+    (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \
+     M_FW_PORT_TRACE_CMD_RUNTFLTSIZE)
+
+#define S_FW_PORT_TRACE_CMD_PCIECH	6
+#define M_FW_PORT_TRACE_CMD_PCIECH	0x3
+#define V_FW_PORT_TRACE_CMD_PCIECH(x)	((x) << S_FW_PORT_TRACE_CMD_PCIECH)
+#define G_FW_PORT_TRACE_CMD_PCIECH(x)	\
+    (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH)
+
+struct fw_port_trace_mmap_cmd {
+	__be32 op_to_portid;
+	__be32 retval_len16;
+	__be32 fid_to_skipoffset;
+	__be32 minpktsize_capturemax;
+	__u8   map[224];
+};
+
+#define S_FW_PORT_TRACE_MMAP_CMD_PORTID		0
+#define M_FW_PORT_TRACE_MMAP_CMD_PORTID		0xf
+#define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x)	\
+    ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID)
+#define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x)	\
+    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \
+     M_FW_PORT_TRACE_MMAP_CMD_PORTID)
+
+#define S_FW_PORT_TRACE_MMAP_CMD_FID	30
+#define M_FW_PORT_TRACE_MMAP_CMD_FID	0x3
+#define V_FW_PORT_TRACE_MMAP_CMD_FID(x)	((x) << S_FW_PORT_TRACE_MMAP_CMD_FID)
+#define G_FW_PORT_TRACE_MMAP_CMD_FID(x)	\
+    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID)
+
+#define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN		29
+#define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN		0x1
+#define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x)	\
+    ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN)
+#define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x)	\
+    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \
+     M_FW_PORT_TRACE_MMAP_CMD_MMAPEN)
+#define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN	V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U)
+
+#define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN	28
+#define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN	0x1
+#define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x)	\
+    ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN)
+#define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x)	\
+    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \
+     M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN)
+#define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN	\
+    V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U)
+
+#define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH	8
+#define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH	0x1f
+#define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x)	\
+    ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH)
+#define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x)	\
+    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \
+     M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH)
+
+#define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET	0
+#define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET	0x1f
+#define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x)	\
+    ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET)
+#define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x)	\
+    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \
+     M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET)
+
+#define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE	18
+#define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE	0x3fff
+#define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x)	\
+    ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE)
+#define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x)	\
+    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \
+     M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE)
+
+#define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX	0
+#define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX	0x3fff
+#define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x)	\
+    ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX)
+#define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x)	\
+    (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \
+     M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX)
+
+struct fw_rss_ind_tbl_cmd {
+	__be32 op_to_viid;
+	__be32 retval_len16;
+	__be16 niqid;
+	__be16 startidx;
+	__be32 r3;
+	__be32 iq0_to_iq2;
+	__be32 iq3_to_iq5;
+	__be32 iq6_to_iq8;
+	__be32 iq9_to_iq11;
+	__be32 iq12_to_iq14;
+	__be32 iq15_to_iq17;
+	__be32 iq18_to_iq20;
+	__be32 iq21_to_iq23;
+	__be32 iq24_to_iq26;
+	__be32 iq27_to_iq29;
+	__be32 iq30_iq31;
+	__be32 r15_lo;
+};
+
+#define S_FW_RSS_IND_TBL_CMD_VIID	0
+#define M_FW_RSS_IND_TBL_CMD_VIID	0xfff
+#define V_FW_RSS_IND_TBL_CMD_VIID(x)	((x) << S_FW_RSS_IND_TBL_CMD_VIID)
+#define G_FW_RSS_IND_TBL_CMD_VIID(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ0	20
+#define M_FW_RSS_IND_TBL_CMD_IQ0	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ0(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
+#define G_FW_RSS_IND_TBL_CMD_IQ0(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ1	10
+#define M_FW_RSS_IND_TBL_CMD_IQ1	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ1(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
+#define G_FW_RSS_IND_TBL_CMD_IQ1(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ2	0
+#define M_FW_RSS_IND_TBL_CMD_IQ2	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ2(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
+#define G_FW_RSS_IND_TBL_CMD_IQ2(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ3	20
+#define M_FW_RSS_IND_TBL_CMD_IQ3	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ3(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ3)
+#define G_FW_RSS_IND_TBL_CMD_IQ3(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ4	10
+#define M_FW_RSS_IND_TBL_CMD_IQ4	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ4(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ4)
+#define G_FW_RSS_IND_TBL_CMD_IQ4(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ5	0
+#define M_FW_RSS_IND_TBL_CMD_IQ5	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ5(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ5)
+#define G_FW_RSS_IND_TBL_CMD_IQ5(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ6	20
+#define M_FW_RSS_IND_TBL_CMD_IQ6	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ6(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ6)
+#define G_FW_RSS_IND_TBL_CMD_IQ6(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ7	10
+#define M_FW_RSS_IND_TBL_CMD_IQ7	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ7(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ7)
+#define G_FW_RSS_IND_TBL_CMD_IQ7(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ8	0
+#define M_FW_RSS_IND_TBL_CMD_IQ8	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ8(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ8)
+#define G_FW_RSS_IND_TBL_CMD_IQ8(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ9	20
+#define M_FW_RSS_IND_TBL_CMD_IQ9	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ9(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ9)
+#define G_FW_RSS_IND_TBL_CMD_IQ9(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ10	10
+#define M_FW_RSS_IND_TBL_CMD_IQ10	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ10(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ10)
+#define G_FW_RSS_IND_TBL_CMD_IQ10(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ11	0
+#define M_FW_RSS_IND_TBL_CMD_IQ11	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ11(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ11)
+#define G_FW_RSS_IND_TBL_CMD_IQ11(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ12	20
+#define M_FW_RSS_IND_TBL_CMD_IQ12	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ12(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ12)
+#define G_FW_RSS_IND_TBL_CMD_IQ12(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ13	10
+#define M_FW_RSS_IND_TBL_CMD_IQ13	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ13(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ13)
+#define G_FW_RSS_IND_TBL_CMD_IQ13(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ14	0
+#define M_FW_RSS_IND_TBL_CMD_IQ14	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ14(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ14)
+#define G_FW_RSS_IND_TBL_CMD_IQ14(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ15	20
+#define M_FW_RSS_IND_TBL_CMD_IQ15	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ15(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ15)
+#define G_FW_RSS_IND_TBL_CMD_IQ15(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ16	10
+#define M_FW_RSS_IND_TBL_CMD_IQ16	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ16(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ16)
+#define G_FW_RSS_IND_TBL_CMD_IQ16(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ17	0
+#define M_FW_RSS_IND_TBL_CMD_IQ17	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ17(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ17)
+#define G_FW_RSS_IND_TBL_CMD_IQ17(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ18	20
+#define M_FW_RSS_IND_TBL_CMD_IQ18	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ18(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ18)
+#define G_FW_RSS_IND_TBL_CMD_IQ18(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ19	10
+#define M_FW_RSS_IND_TBL_CMD_IQ19	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ19(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ19)
+#define G_FW_RSS_IND_TBL_CMD_IQ19(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ20	0
+#define M_FW_RSS_IND_TBL_CMD_IQ20	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ20(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ20)
+#define G_FW_RSS_IND_TBL_CMD_IQ20(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ21	20
+#define M_FW_RSS_IND_TBL_CMD_IQ21	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ21(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ21)
+#define G_FW_RSS_IND_TBL_CMD_IQ21(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ22	10
+#define M_FW_RSS_IND_TBL_CMD_IQ22	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ22(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ22)
+#define G_FW_RSS_IND_TBL_CMD_IQ22(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ23	0
+#define M_FW_RSS_IND_TBL_CMD_IQ23	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ23(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ23)
+#define G_FW_RSS_IND_TBL_CMD_IQ23(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ24	20
+#define M_FW_RSS_IND_TBL_CMD_IQ24	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ24(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ24)
+#define G_FW_RSS_IND_TBL_CMD_IQ24(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ25	10
+#define M_FW_RSS_IND_TBL_CMD_IQ25	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ25(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ25)
+#define G_FW_RSS_IND_TBL_CMD_IQ25(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ26	0
+#define M_FW_RSS_IND_TBL_CMD_IQ26	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ26(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ26)
+#define G_FW_RSS_IND_TBL_CMD_IQ26(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ27	20
+#define M_FW_RSS_IND_TBL_CMD_IQ27	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ27(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ27)
+#define G_FW_RSS_IND_TBL_CMD_IQ27(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ28	10
+#define M_FW_RSS_IND_TBL_CMD_IQ28	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ28(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ28)
+#define G_FW_RSS_IND_TBL_CMD_IQ28(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ29	0
+#define M_FW_RSS_IND_TBL_CMD_IQ29	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ29(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ29)
+#define G_FW_RSS_IND_TBL_CMD_IQ29(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ30	20
+#define M_FW_RSS_IND_TBL_CMD_IQ30	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ30(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ30)
+#define G_FW_RSS_IND_TBL_CMD_IQ30(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30)
+
+#define S_FW_RSS_IND_TBL_CMD_IQ31	10
+#define M_FW_RSS_IND_TBL_CMD_IQ31	0x3ff
+#define V_FW_RSS_IND_TBL_CMD_IQ31(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ31)
+#define G_FW_RSS_IND_TBL_CMD_IQ31(x)	\
+    (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31)
+
+struct fw_rss_glb_config_cmd {
+	__be32 op_to_write;
+	__be32 retval_len16;
+	union fw_rss_glb_config {
+		struct fw_rss_glb_config_manual {
+			__be32 mode_pkd;
+			__be32 r3;
+			__be64 r4;
+			__be64 r5;
+		} manual;
+		struct fw_rss_glb_config_basicvirtual {
+			__be32 mode_pkd;
+			__be32 synmapen_to_hashtoeplitz;
+			__be64 r8;
+			__be64 r9;
+		} basicvirtual;
+	} u;
+};
+
+#define S_FW_RSS_GLB_CONFIG_CMD_MODE	28
+#define M_FW_RSS_GLB_CONFIG_CMD_MODE	0xf
+#define V_FW_RSS_GLB_CONFIG_CMD_MODE(x)	((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE)
+#define G_FW_RSS_GLB_CONFIG_CMD_MODE(x)	\
+    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
+
+#define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL	0
+#define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL	1
+#define FW_RSS_GLB_CONFIG_CMD_MODE_MAX		1
+
+#define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN	8
+#define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN	0x1
+#define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x)	\
+    ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
+#define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x)	\
+    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \
+     M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
+#define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN	\
+    V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
+
+#define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6		7
+#define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6		0x1
+#define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x)	\
+    ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
+#define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x)	\
+    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \
+     M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
+#define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6	\
+    V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
+
+#define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6		6
+#define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6		0x1
+#define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x)	\
+    ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
+#define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x)	\
+    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \
+     M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
+#define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6	\
+    V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
+
+#define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4		5
+#define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4		0x1
+#define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x)	\
+    ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
+#define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x)	\
+    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \
+     M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
+#define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4	\
+    V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
+
+#define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4		4
+#define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4		0x1
+#define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x)	\
+    ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
+#define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x)	\
+    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \
+     M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
+#define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4	\
+    V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
+
+#define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN	3
+#define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN	0x1
+#define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x)	\
+    ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
+#define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x)	\
+    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \
+     M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
+#define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN	\
+    V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
+
+#define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN	2
+#define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN	0x1
+#define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x)	\
+    ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
+#define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x)	\
+    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \
+     M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
+#define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN	\
+    V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
+
+#define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP	1
+#define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP	0x1
+#define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x)	\
+    ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
+#define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x)	\
+    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \
+     M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
+#define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP	\
+    V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
+
+#define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ	0
+#define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ	0x1
+#define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x)	\
+    ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
+#define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x)	\
+    (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \
+     M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
+#define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ	\
+    V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
+
+struct fw_rss_vi_config_cmd {
+	__be32 op_to_viid;
+	__be32 retval_len16;
+	union fw_rss_vi_config {
+		struct fw_rss_vi_config_manual {
+			__be64 r3;
+			__be64 r4;
+			__be64 r5;
+		} manual;
+		struct fw_rss_vi_config_basicvirtual {
+			__be32 r6;
+			__be32 defaultq_to_udpen;
+			__be64 r9;
+			__be64 r10;
+		} basicvirtual;
+	} u;
+};
+
+#define S_FW_RSS_VI_CONFIG_CMD_VIID	0
+#define M_FW_RSS_VI_CONFIG_CMD_VIID	0xfff
+#define V_FW_RSS_VI_CONFIG_CMD_VIID(x)	((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
+#define G_FW_RSS_VI_CONFIG_CMD_VIID(x)	\
+    (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
+
+#define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ		16
+#define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ		0x3ff
+#define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x)	\
+    ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
+#define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x)	\
+    (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
+     M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
+
+#define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN	4
+#define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN	0x1
+#define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x)	\
+    ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
+#define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x)	\
+    (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
+     M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
+#define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN	\
+    V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
+
+#define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN	3
+#define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN	0x1
+#define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x)	\
+    ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
+#define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x)	\
+    (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
+     M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
+#define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN	\
+    V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
+
+#define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN	2
+#define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN	0x1
+#define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x)	\
+    ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
+#define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x)	\
+    (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
+     M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
+#define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN	\
+    V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
+
+#define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN	1
+#define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN	0x1
+#define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x)	\
+    ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
+#define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x)	\
+    (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
+     M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
+#define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN	\
+    V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
+
+#define S_FW_RSS_VI_CONFIG_CMD_UDPEN	0
+#define M_FW_RSS_VI_CONFIG_CMD_UDPEN	0x1
+#define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x)	((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
+#define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x)	\
+    (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
+#define F_FW_RSS_VI_CONFIG_CMD_UDPEN	V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
+
+enum fw_sched_sc {
+	FW_SCHED_SC_CONFIG		= 0,
+	FW_SCHED_SC_PARAMS		= 1,
+};
+
+enum fw_sched_type {
+	FW_SCHED_TYPE_PKTSCHED	        = 0,
+	FW_SCHED_TYPE_STREAMSCHED       = 1,
+};
+
+enum fw_sched_params_level {
+	FW_SCHED_PARAMS_LEVEL_CL_RL	= 0,
+	FW_SCHED_PARAMS_LEVEL_CL_WRR	= 1,
+	FW_SCHED_PARAMS_LEVEL_CH_RL	= 2,
+};
+
+enum fw_sched_params_mode {
+	FW_SCHED_PARAMS_MODE_CLASS	= 0,
+	FW_SCHED_PARAMS_MODE_FLOW	= 1,
+};
+
+enum fw_sched_params_unit {
+	FW_SCHED_PARAMS_UNIT_BITRATE	= 0,
+	FW_SCHED_PARAMS_UNIT_PKTRATE	= 1,
+};
+
+enum fw_sched_params_rate {
+	FW_SCHED_PARAMS_RATE_REL	= 0,
+	FW_SCHED_PARAMS_RATE_ABS	= 1,
+};
+
+struct fw_sched_cmd {
+	__be32 op_to_write;
+	__be32 retval_len16;
+	union fw_sched {
+		struct fw_sched_config {
+			__u8   sc;
+			__u8   type;
+			__u8   minmaxen;
+			__u8   r3[5];
+			__u8   nclasses[4];
+			__be32 r4;
+		} config;
+		struct fw_sched_params {
+			__u8   sc;
+			__u8   type;
+			__u8   level;
+			__u8   mode;
+			__u8   unit;
+			__u8   rate;
+			__u8   ch;
+			__u8   cl;
+			__be32 min;
+			__be32 max;
+			__be16 weight;
+			__be16 pktsize;
+			__be16 burstsize;
+			__be16 r4;
+		} params;
+	} u;
+};
+
+/*
+ *	length of the formatting string
+ */
+#define FW_DEVLOG_FMT_LEN	192
+
+/*
+ *	maximum number of the formatting string parameters
+ */
+#define FW_DEVLOG_FMT_PARAMS_NUM 8
+
+/*
+ *	priority levels
+ */
+enum fw_devlog_level {
+	FW_DEVLOG_LEVEL_EMERG	= 0x0,
+	FW_DEVLOG_LEVEL_CRIT	= 0x1,
+	FW_DEVLOG_LEVEL_ERR	= 0x2,
+	FW_DEVLOG_LEVEL_NOTICE	= 0x3,
+	FW_DEVLOG_LEVEL_INFO	= 0x4,
+	FW_DEVLOG_LEVEL_DEBUG	= 0x5,
+	FW_DEVLOG_LEVEL_MAX	= 0x5,
+};
+
+/*
+ *	facilities that may send a log message
+ */
+enum fw_devlog_facility {
+	FW_DEVLOG_FACILITY_CORE		= 0x00,
+	FW_DEVLOG_FACILITY_CF		= 0x01,
+	FW_DEVLOG_FACILITY_SCHED	= 0x02,
+	FW_DEVLOG_FACILITY_TIMER	= 0x04,
+	FW_DEVLOG_FACILITY_RES		= 0x06,
+	FW_DEVLOG_FACILITY_HW		= 0x08,
+	FW_DEVLOG_FACILITY_FLR		= 0x10,
+	FW_DEVLOG_FACILITY_DMAQ		= 0x12,
+	FW_DEVLOG_FACILITY_PHY		= 0x14,
+	FW_DEVLOG_FACILITY_MAC		= 0x16,
+	FW_DEVLOG_FACILITY_PORT		= 0x18,
+	FW_DEVLOG_FACILITY_VI		= 0x1A,
+	FW_DEVLOG_FACILITY_FILTER	= 0x1C,
+	FW_DEVLOG_FACILITY_ACL		= 0x1E,
+	FW_DEVLOG_FACILITY_TM		= 0x20,
+	FW_DEVLOG_FACILITY_QFC		= 0x22,
+	FW_DEVLOG_FACILITY_DCB		= 0x24,
+	FW_DEVLOG_FACILITY_ETH		= 0x26,
+	FW_DEVLOG_FACILITY_OFLD		= 0x28,
+	FW_DEVLOG_FACILITY_RI		= 0x2A,
+	FW_DEVLOG_FACILITY_ISCSI	= 0x2C,
+	FW_DEVLOG_FACILITY_FCOE		= 0x2E,
+	FW_DEVLOG_FACILITY_FOISCSI	= 0x30,
+	FW_DEVLOG_FACILITY_FOFCOE	= 0x32,
+	FW_DEVLOG_FACILITY_MAX		= 0x32,
+};
+
+/*
+ *	log message format
+ */
+struct fw_devlog_e {
+	__be64	timestamp;
+	__be32	seqno;
+	__be16	reserved1;
+	__u8	level;
+	__u8	facility;
+	__u8	fmt[FW_DEVLOG_FMT_LEN];
+	__be32	params[FW_DEVLOG_FMT_PARAMS_NUM];
+	__be32	reserved3[4];
+};
+
+struct fw_devlog_cmd {
+	__be32 op_to_write;
+	__be32 retval_len16;
+	__u8   level;
+	__u8   r2[7];
+	__be32 memtype_devlog_memaddr16_devlog;
+	__be32 memsize_devlog;
+	__be32 r3[2];
+};
+
+#define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG		28
+#define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG		0xf
+#define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x)	\
+    ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG)
+#define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x)	\
+    (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG)
+
+#define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG	0
+#define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG	0xfffffff
+#define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x)	\
+    ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG)
+#define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x)	\
+    (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \
+     M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG)
+
+enum fw_watchdog_actions {
+	FW_WATCHDOG_ACTION_SHUTDOWN = 0,
+	FW_WATCHDOG_ACTION_FLR = 1,
+	FW_WATCHDOG_ACTION_BYPASS = 2,
+	FW_WATCHDOG_ACTION_TMPCHK = 3,
+
+	FW_WATCHDOG_ACTION_MAX = 4,
+};
+
+#define FW_WATCHDOG_MAX_TIMEOUT_SECS	60
+
+struct fw_watchdog_cmd {
+	__be32 op_to_vfn;
+	__be32 retval_len16;
+	__be32 timeout;
+	__be32 action;
+};
+
+#define S_FW_WATCHDOG_CMD_PFN		8
+#define M_FW_WATCHDOG_CMD_PFN		0x7
+#define V_FW_WATCHDOG_CMD_PFN(x)	((x) << S_FW_WATCHDOG_CMD_PFN)
+#define G_FW_WATCHDOG_CMD_PFN(x)	\
+    (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN)
+
+#define S_FW_WATCHDOG_CMD_VFN		0
+#define M_FW_WATCHDOG_CMD_VFN		0xff
+#define V_FW_WATCHDOG_CMD_VFN(x)	((x) << S_FW_WATCHDOG_CMD_VFN)
+#define G_FW_WATCHDOG_CMD_VFN(x)	\
+    (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN)
+
+struct fw_clip_cmd {
+	__be32 op_to_write;
+	__be32 alloc_to_len16;
+	__be64 ip_hi;
+	__be64 ip_lo;
+	__be32 r4[2];
+};
+
+#define S_FW_CLIP_CMD_ALLOC	31
+#define M_FW_CLIP_CMD_ALLOC	0x1
+#define V_FW_CLIP_CMD_ALLOC(x)	((x) << S_FW_CLIP_CMD_ALLOC)
+#define G_FW_CLIP_CMD_ALLOC(x)	\
+    (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC)
+#define F_FW_CLIP_CMD_ALLOC	V_FW_CLIP_CMD_ALLOC(1U)
+
+#define S_FW_CLIP_CMD_FREE	30
+#define M_FW_CLIP_CMD_FREE	0x1
+#define V_FW_CLIP_CMD_FREE(x)	((x) << S_FW_CLIP_CMD_FREE)
+#define G_FW_CLIP_CMD_FREE(x)	\
+    (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE)
+#define F_FW_CLIP_CMD_FREE	V_FW_CLIP_CMD_FREE(1U)
+
+/******************************************************************************
+ *   F O i S C S I   C O M M A N D s
+ **************************************/
+
+#define	FW_CHNET_IFACE_ADDR_MAX	3
+
+enum fw_chnet_iface_cmd_subop {
+	FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0,
+	
+	FW_CHNET_IFACE_CMD_SUBOP_LINK_UP,
+	FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN,
+	
+	FW_CHNET_IFACE_CMD_SUBOP_MTU_SET,
+	FW_CHNET_IFACE_CMD_SUBOP_MTU_GET,
+
+	FW_CHNET_IFACE_CMD_SUBOP_MAX,
+};
+
+struct fw_chnet_iface_cmd {
+	__be32 op_to_portid;
+	__be32 retval_len16;
+	__u8   subop;
+	__u8   r2[3];
+	__be32 ifid_ifstate;
+	__be16 mtu;
+	__be16 vlanid;
+	__be32 r3;
+	__be16 r4;
+	__u8   mac[6];
+};
+
+#define S_FW_CHNET_IFACE_CMD_PORTID	0
+#define M_FW_CHNET_IFACE_CMD_PORTID	0xf
+#define V_FW_CHNET_IFACE_CMD_PORTID(x)	((x) << S_FW_CHNET_IFACE_CMD_PORTID)
+#define G_FW_CHNET_IFACE_CMD_PORTID(x)	\
+    (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID)
+
+#define S_FW_CHNET_IFACE_CMD_IFID	8
+#define M_FW_CHNET_IFACE_CMD_IFID	0xffffff
+#define V_FW_CHNET_IFACE_CMD_IFID(x)	((x) << S_FW_CHNET_IFACE_CMD_IFID)
+#define G_FW_CHNET_IFACE_CMD_IFID(x)	\
+    (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID)
+
+#define S_FW_CHNET_IFACE_CMD_IFSTATE	0
+#define M_FW_CHNET_IFACE_CMD_IFSTATE	0xff
+#define V_FW_CHNET_IFACE_CMD_IFSTATE(x)	((x) << S_FW_CHNET_IFACE_CMD_IFSTATE)
+#define G_FW_CHNET_IFACE_CMD_IFSTATE(x)	\
+    (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE)
+
+/******************************************************************************
+ *   F O F C O E   C O M M A N D s
+ ************************************/
+
+struct fw_fcoe_res_info_cmd {
+	__be32 op_to_read;
+	__be32 retval_len16;
+	__be16 e_d_tov;
+	__be16 r_a_tov_seq;
+	__be16 r_a_tov_els;
+	__be16 r_r_tov;
+	__be32 max_xchgs;
+	__be32 max_ssns;
+	__be32 used_xchgs;
+	__be32 used_ssns;
+	__be32 max_fcfs;
+	__be32 max_vnps;
+	__be32 used_fcfs;
+	__be32 used_vnps;
+};
+
+struct fw_fcoe_link_cmd {
+	__be32 op_to_portid;
+	__be32 retval_len16;
+	__be32 sub_opcode_fcfi;
+	__u8   r3;
+	__u8   lstatus;
+	__be16 flags;
+	__u8   r4;
+	__u8   set_vlan;
+	__be16 vlan_id;
+	__be32 vnpi_pkd;
+	__be16 r6;
+	__u8   phy_mac[6];
+	__u8   vnport_wwnn[8];
+	__u8   vnport_wwpn[8];
+};
+
+#define S_FW_FCOE_LINK_CMD_PORTID	0
+#define M_FW_FCOE_LINK_CMD_PORTID	0xf
+#define V_FW_FCOE_LINK_CMD_PORTID(x)	((x) << S_FW_FCOE_LINK_CMD_PORTID)
+#define G_FW_FCOE_LINK_CMD_PORTID(x)	\
+    (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID)
+
+#define S_FW_FCOE_LINK_CMD_SUB_OPCODE		24
+#define M_FW_FCOE_LINK_CMD_SUB_OPCODE		0xff
+#define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x)	\
+    ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE)
+#define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x)	\
+    (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE)
+
+#define S_FW_FCOE_LINK_CMD_FCFI		0
+#define M_FW_FCOE_LINK_CMD_FCFI		0xffffff
+#define V_FW_FCOE_LINK_CMD_FCFI(x)	((x) << S_FW_FCOE_LINK_CMD_FCFI)
+#define G_FW_FCOE_LINK_CMD_FCFI(x)	\
+    (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI)
+
+#define S_FW_FCOE_LINK_CMD_VNPI		0
+#define M_FW_FCOE_LINK_CMD_VNPI		0xfffff
+#define V_FW_FCOE_LINK_CMD_VNPI(x)	((x) << S_FW_FCOE_LINK_CMD_VNPI)
+#define G_FW_FCOE_LINK_CMD_VNPI(x)	\
+    (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI)
+
+struct fw_fcoe_vnp_cmd {
+	__be32 op_to_fcfi;
+	__be32 alloc_to_len16;
+	__be32 gen_wwn_to_vnpi;
+	__be32 vf_id;
+	__be16 iqid;
+	__u8   vnport_mac[6];
+	__u8   vnport_wwnn[8];
+	__u8   vnport_wwpn[8];
+	__u8   cmn_srv_parms[16];
+	__u8   clsp_word_0_1[8];
+};
+
+#define S_FW_FCOE_VNP_CMD_FCFI		0
+#define M_FW_FCOE_VNP_CMD_FCFI		0xfffff
+#define V_FW_FCOE_VNP_CMD_FCFI(x)	((x) << S_FW_FCOE_VNP_CMD_FCFI)
+#define G_FW_FCOE_VNP_CMD_FCFI(x)	\
+    (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI)
+
+#define S_FW_FCOE_VNP_CMD_ALLOC		31
+#define M_FW_FCOE_VNP_CMD_ALLOC		0x1
+#define V_FW_FCOE_VNP_CMD_ALLOC(x)	((x) << S_FW_FCOE_VNP_CMD_ALLOC)
+#define G_FW_FCOE_VNP_CMD_ALLOC(x)	\
+    (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC)
+#define F_FW_FCOE_VNP_CMD_ALLOC	V_FW_FCOE_VNP_CMD_ALLOC(1U)
+
+#define S_FW_FCOE_VNP_CMD_FREE		30
+#define M_FW_FCOE_VNP_CMD_FREE		0x1
+#define V_FW_FCOE_VNP_CMD_FREE(x)	((x) << S_FW_FCOE_VNP_CMD_FREE)
+#define G_FW_FCOE_VNP_CMD_FREE(x)	\
+    (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE)
+#define F_FW_FCOE_VNP_CMD_FREE	V_FW_FCOE_VNP_CMD_FREE(1U)
+
+#define S_FW_FCOE_VNP_CMD_MODIFY	29
+#define M_FW_FCOE_VNP_CMD_MODIFY	0x1
+#define V_FW_FCOE_VNP_CMD_MODIFY(x)	((x) << S_FW_FCOE_VNP_CMD_MODIFY)
+#define G_FW_FCOE_VNP_CMD_MODIFY(x)	\
+    (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY)
+#define F_FW_FCOE_VNP_CMD_MODIFY	V_FW_FCOE_VNP_CMD_MODIFY(1U)
+
+#define S_FW_FCOE_VNP_CMD_GEN_WWN	22
+#define M_FW_FCOE_VNP_CMD_GEN_WWN	0x1
+#define V_FW_FCOE_VNP_CMD_GEN_WWN(x)	((x) << S_FW_FCOE_VNP_CMD_GEN_WWN)
+#define G_FW_FCOE_VNP_CMD_GEN_WWN(x)	\
+    (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN)
+#define F_FW_FCOE_VNP_CMD_GEN_WWN	V_FW_FCOE_VNP_CMD_GEN_WWN(1U)
+
+#define S_FW_FCOE_VNP_CMD_PERSIST	21
+#define M_FW_FCOE_VNP_CMD_PERSIST	0x1
+#define V_FW_FCOE_VNP_CMD_PERSIST(x)	((x) << S_FW_FCOE_VNP_CMD_PERSIST)
+#define G_FW_FCOE_VNP_CMD_PERSIST(x)	\
+    (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST)
+#define F_FW_FCOE_VNP_CMD_PERSIST	V_FW_FCOE_VNP_CMD_PERSIST(1U)
+
+#define S_FW_FCOE_VNP_CMD_VFID_EN	20
+#define M_FW_FCOE_VNP_CMD_VFID_EN	0x1
+#define V_FW_FCOE_VNP_CMD_VFID_EN(x)	((x) << S_FW_FCOE_VNP_CMD_VFID_EN)
+#define G_FW_FCOE_VNP_CMD_VFID_EN(x)	\
+    (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN)
+#define F_FW_FCOE_VNP_CMD_VFID_EN	V_FW_FCOE_VNP_CMD_VFID_EN(1U)
+
+#define S_FW_FCOE_VNP_CMD_VNPI		0
+#define M_FW_FCOE_VNP_CMD_VNPI		0xfffff
+#define V_FW_FCOE_VNP_CMD_VNPI(x)	((x) << S_FW_FCOE_VNP_CMD_VNPI)
+#define G_FW_FCOE_VNP_CMD_VNPI(x)	\
+    (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI)
+
+struct fw_fcoe_sparams_cmd {
+	__be32 op_to_portid;
+	__be32 retval_len16;
+	__u8   r3[7];
+	__u8   cos;
+	__u8   lport_wwnn[8];
+	__u8   lport_wwpn[8];
+	__u8   cmn_srv_parms[16];
+	__u8   cls_srv_parms[16];
+};
+
+#define S_FW_FCOE_SPARAMS_CMD_PORTID	0
+#define M_FW_FCOE_SPARAMS_CMD_PORTID	0xf
+#define V_FW_FCOE_SPARAMS_CMD_PORTID(x)	((x) << S_FW_FCOE_SPARAMS_CMD_PORTID)
+#define G_FW_FCOE_SPARAMS_CMD_PORTID(x)	\
+    (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID)
+
+struct fw_fcoe_stats_cmd {
+	__be32 op_to_flowid;
+	__be32 free_to_len16;
+	union fw_fcoe_stats {
+		struct fw_fcoe_stats_ctl {
+			__u8   nstats_port;
+			__u8   port_valid_ix;
+			__be16 r6;
+			__be32 r7;
+			__be64 stat0;
+			__be64 stat1;
+			__be64 stat2;
+			__be64 stat3;
+			__be64 stat4;
+			__be64 stat5;
+		} ctl;
+		struct fw_fcoe_port_stats {
+			__be64 tx_bcast_bytes;
+			__be64 tx_bcast_frames;
+			__be64 tx_mcast_bytes;
+			__be64 tx_mcast_frames;
+			__be64 tx_ucast_bytes;
+			__be64 tx_ucast_frames;
+			__be64 tx_drop_frames;
+			__be64 tx_offload_bytes;
+			__be64 tx_offload_frames;
+			__be64 rx_bcast_bytes;
+			__be64 rx_bcast_frames;
+			__be64 rx_mcast_bytes;
+			__be64 rx_mcast_frames;
+			__be64 rx_ucast_bytes;
+			__be64 rx_ucast_frames;
+			__be64 rx_err_frames;
+		} port_stats;
+		struct fw_fcoe_fcf_stats {
+			__be32 fip_tx_bytes;
+			__be32 fip_tx_fr;
+			__be64 fcf_ka;
+			__be64 mcast_adv_rcvd;
+			__be16 ucast_adv_rcvd;
+			__be16 sol_sent;
+			__be16 vlan_req;
+			__be16 vlan_rpl;
+			__be16 clr_vlink;
+			__be16 link_down;
+			__be16 link_up;
+			__be16 logo;
+			__be16 flogi_req;
+			__be16 flogi_rpl;
+			__be16 fdisc_req;
+			__be16 fdisc_rpl;
+			__be16 fka_prd_chg;
+			__be16 fc_map_chg;
+			__be16 vfid_chg;
+			__u8   no_fka_req;
+			__u8   no_vnp;
+		} fcf_stats;
+		struct fw_fcoe_pcb_stats {
+			__be64 tx_bytes;
+			__be64 tx_frames;
+			__be64 rx_bytes;
+			__be64 rx_frames;
+			__be32 vnp_ka;
+			__be32 unsol_els_rcvd;
+			__be64 unsol_cmd_rcvd;
+			__be16 implicit_logo;
+			__be16 flogi_inv_sparm;
+			__be16 fdisc_inv_sparm;
+			__be16 flogi_rjt;
+			__be16 fdisc_rjt;
+			__be16 no_ssn;
+			__be16 mac_flt_fail;
+			__be16 inv_fr_rcvd;
+		} pcb_stats;
+		struct fw_fcoe_scb_stats {
+			__be64 tx_bytes;
+			__be64 tx_frames;
+			__be64 rx_bytes;
+			__be64 rx_frames;
+			__be32 host_abrt_req;
+			__be32 adap_auto_abrt;
+			__be32 adap_abrt_rsp;
+			__be32 host_ios_req;
+			__be16 ssn_offl_ios;
+			__be16 ssn_not_rdy_ios;
+			__u8   rx_data_ddp_err;
+			__u8   ddp_flt_set_err;
+			__be16 rx_data_fr_err;
+			__u8   bad_st_abrt_req;
+			__u8   no_io_abrt_req;
+			__u8   abort_tmo;
+			__u8   abort_tmo_2;
+			__be32 abort_req;
+			__u8   no_ppod_res_tmo;
+			__u8   bp_tmo;
+			__u8   adap_auto_cls;
+			__u8   no_io_cls_req;
+			__be32 host_cls_req;
+			__be64 unsol_cmd_rcvd;
+			__be32 plogi_req_rcvd;
+			__be32 prli_req_rcvd;
+			__be16 logo_req_rcvd;
+			__be16 prlo_req_rcvd;
+			__be16 plogi_rjt_rcvd;
+			__be16 prli_rjt_rcvd;
+			__be32 adisc_req_rcvd;
+			__be32 rscn_rcvd;
+			__be32 rrq_req_rcvd;
+			__be32 unsol_els_rcvd;
+			__u8   adisc_rjt_rcvd;
+			__u8   scr_rjt;
+			__u8   ct_rjt;
+			__u8   inval_bls_rcvd;
+			__be32 ba_rjt_rcvd;
+		} scb_stats;
+	} u;
+};
+
+#define S_FW_FCOE_STATS_CMD_FLOWID	0
+#define M_FW_FCOE_STATS_CMD_FLOWID	0xfffff
+#define V_FW_FCOE_STATS_CMD_FLOWID(x)	((x) << S_FW_FCOE_STATS_CMD_FLOWID)
+#define G_FW_FCOE_STATS_CMD_FLOWID(x)	\
+    (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID)
+
+#define S_FW_FCOE_STATS_CMD_FREE	30
+#define M_FW_FCOE_STATS_CMD_FREE	0x1
+#define V_FW_FCOE_STATS_CMD_FREE(x)	((x) << S_FW_FCOE_STATS_CMD_FREE)
+#define G_FW_FCOE_STATS_CMD_FREE(x)	\
+    (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE)
+#define F_FW_FCOE_STATS_CMD_FREE	V_FW_FCOE_STATS_CMD_FREE(1U)
+
+#define S_FW_FCOE_STATS_CMD_NSTATS	4
+#define M_FW_FCOE_STATS_CMD_NSTATS	0x7
+#define V_FW_FCOE_STATS_CMD_NSTATS(x)	((x) << S_FW_FCOE_STATS_CMD_NSTATS)
+#define G_FW_FCOE_STATS_CMD_NSTATS(x)	\
+    (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS)
+
+#define S_FW_FCOE_STATS_CMD_PORT	0
+#define M_FW_FCOE_STATS_CMD_PORT	0x3
+#define V_FW_FCOE_STATS_CMD_PORT(x)	((x) << S_FW_FCOE_STATS_CMD_PORT)
+#define G_FW_FCOE_STATS_CMD_PORT(x)	\
+    (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT)
+
+#define S_FW_FCOE_STATS_CMD_PORT_VALID		7
+#define M_FW_FCOE_STATS_CMD_PORT_VALID		0x1
+#define V_FW_FCOE_STATS_CMD_PORT_VALID(x)	\
+    ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID)
+#define G_FW_FCOE_STATS_CMD_PORT_VALID(x)	\
+    (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID)
+#define F_FW_FCOE_STATS_CMD_PORT_VALID	V_FW_FCOE_STATS_CMD_PORT_VALID(1U)
+
+#define S_FW_FCOE_STATS_CMD_IX		0
+#define M_FW_FCOE_STATS_CMD_IX		0x3f
+#define V_FW_FCOE_STATS_CMD_IX(x)	((x) << S_FW_FCOE_STATS_CMD_IX)
+#define G_FW_FCOE_STATS_CMD_IX(x)	\
+    (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX)
+
+struct fw_fcoe_fcf_cmd {
+	__be32 op_to_fcfi;
+	__be32 retval_len16;
+	__be16 priority_pkd;
+	__u8   mac[6];
+	__u8   name_id[8];
+	__u8   fabric[8];
+	__be16 vf_id;
+	__be16 max_fcoe_size;
+	__u8   vlan_id;
+	__u8   fc_map[3];
+	__be32 fka_adv;
+	__be32 r6;
+	__u8   r7_hi;
+	__u8   fpma_to_portid;
+	__u8   spma_mac[6];
+	__be64 r8;
+};
+
+#define S_FW_FCOE_FCF_CMD_FCFI		0
+#define M_FW_FCOE_FCF_CMD_FCFI		0xfffff
+#define V_FW_FCOE_FCF_CMD_FCFI(x)	((x) << S_FW_FCOE_FCF_CMD_FCFI)
+#define G_FW_FCOE_FCF_CMD_FCFI(x)	\
+    (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI)
+
+#define S_FW_FCOE_FCF_CMD_PRIORITY	0
+#define M_FW_FCOE_FCF_CMD_PRIORITY	0xff
+#define V_FW_FCOE_FCF_CMD_PRIORITY(x)	((x) << S_FW_FCOE_FCF_CMD_PRIORITY)
+#define G_FW_FCOE_FCF_CMD_PRIORITY(x)	\
+    (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY)
+
+#define S_FW_FCOE_FCF_CMD_FPMA		6
+#define M_FW_FCOE_FCF_CMD_FPMA		0x1
+#define V_FW_FCOE_FCF_CMD_FPMA(x)	((x) << S_FW_FCOE_FCF_CMD_FPMA)
+#define G_FW_FCOE_FCF_CMD_FPMA(x)	\
+    (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA)
+#define F_FW_FCOE_FCF_CMD_FPMA	V_FW_FCOE_FCF_CMD_FPMA(1U)
+
+#define S_FW_FCOE_FCF_CMD_SPMA		5
+#define M_FW_FCOE_FCF_CMD_SPMA		0x1
+#define V_FW_FCOE_FCF_CMD_SPMA(x)	((x) << S_FW_FCOE_FCF_CMD_SPMA)
+#define G_FW_FCOE_FCF_CMD_SPMA(x)	\
+    (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA)
+#define F_FW_FCOE_FCF_CMD_SPMA	V_FW_FCOE_FCF_CMD_SPMA(1U)
+
+#define S_FW_FCOE_FCF_CMD_LOGIN		4
+#define M_FW_FCOE_FCF_CMD_LOGIN		0x1
+#define V_FW_FCOE_FCF_CMD_LOGIN(x)	((x) << S_FW_FCOE_FCF_CMD_LOGIN)
+#define G_FW_FCOE_FCF_CMD_LOGIN(x)	\
+    (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN)
+#define F_FW_FCOE_FCF_CMD_LOGIN	V_FW_FCOE_FCF_CMD_LOGIN(1U)
+
+#define S_FW_FCOE_FCF_CMD_PORTID	0
+#define M_FW_FCOE_FCF_CMD_PORTID	0xf
+#define V_FW_FCOE_FCF_CMD_PORTID(x)	((x) << S_FW_FCOE_FCF_CMD_PORTID)
+#define G_FW_FCOE_FCF_CMD_PORTID(x)	\
+    (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID)
+
+/******************************************************************************
+ *   E R R O R   a n d   D E B U G   C O M M A N D s
+ ******************************************************/
+
+enum fw_error_type {
+	FW_ERROR_TYPE_EXCEPTION		= 0x0,
+	FW_ERROR_TYPE_HWMODULE		= 0x1,
+	FW_ERROR_TYPE_WR		= 0x2,
+	FW_ERROR_TYPE_ACL		= 0x3,
+};
+
+struct fw_error_cmd {
+	__be32 op_to_type;
+	__be32 len16_pkd;
+	union fw_error {
+		struct fw_error_exception {
+			__be32 info[6];
+		} exception;
+		struct fw_error_hwmodule {
+			__be32 regaddr;
+			__be32 regval;
+		} hwmodule;
+		struct fw_error_wr {
+			__be16 cidx;
+			__be16 pfn_vfn;
+			__be32 eqid;
+			__u8   wrhdr[16];
+		} wr;
+		struct fw_error_acl {
+			__be16 cidx;
+			__be16 pfn_vfn;
+			__be32 eqid;
+			__be16 mv_pkd;
+			__u8   val[6];
+			__be64 r4;
+		} acl;
+	} u;
+};
+
+#define S_FW_ERROR_CMD_FATAL	4
+#define M_FW_ERROR_CMD_FATAL	0x1
+#define V_FW_ERROR_CMD_FATAL(x)	((x) << S_FW_ERROR_CMD_FATAL)
+#define G_FW_ERROR_CMD_FATAL(x)	\
+    (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL)
+#define F_FW_ERROR_CMD_FATAL	V_FW_ERROR_CMD_FATAL(1U)
+
+#define S_FW_ERROR_CMD_TYPE	0
+#define M_FW_ERROR_CMD_TYPE	0xf
+#define V_FW_ERROR_CMD_TYPE(x)	((x) << S_FW_ERROR_CMD_TYPE)
+#define G_FW_ERROR_CMD_TYPE(x)	\
+    (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE)
+
+#define S_FW_ERROR_CMD_PFN	8
+#define M_FW_ERROR_CMD_PFN	0x7
+#define V_FW_ERROR_CMD_PFN(x)	((x) << S_FW_ERROR_CMD_PFN)
+#define G_FW_ERROR_CMD_PFN(x)	\
+    (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)
+
+#define S_FW_ERROR_CMD_VFN	0
+#define M_FW_ERROR_CMD_VFN	0xff
+#define V_FW_ERROR_CMD_VFN(x)	((x) << S_FW_ERROR_CMD_VFN)
+#define G_FW_ERROR_CMD_VFN(x)	\
+    (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)
+
+#define S_FW_ERROR_CMD_PFN	8
+#define M_FW_ERROR_CMD_PFN	0x7
+#define V_FW_ERROR_CMD_PFN(x)	((x) << S_FW_ERROR_CMD_PFN)
+#define G_FW_ERROR_CMD_PFN(x)	\
+    (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)
+
+#define S_FW_ERROR_CMD_VFN	0
+#define M_FW_ERROR_CMD_VFN	0xff
+#define V_FW_ERROR_CMD_VFN(x)	((x) << S_FW_ERROR_CMD_VFN)
+#define G_FW_ERROR_CMD_VFN(x)	\
+    (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)
+
+#define S_FW_ERROR_CMD_MV	15
+#define M_FW_ERROR_CMD_MV	0x1
+#define V_FW_ERROR_CMD_MV(x)	((x) << S_FW_ERROR_CMD_MV)
+#define G_FW_ERROR_CMD_MV(x)	\
+    (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV)
+#define F_FW_ERROR_CMD_MV	V_FW_ERROR_CMD_MV(1U)
+
+struct fw_debug_cmd {
+	__be32 op_type;
+	__be32 len16_pkd;
+	union fw_debug {
+		struct fw_debug_assert {
+			__be32 fcid;
+			__be32 line;
+			__be32 x;
+			__be32 y;
+			__u8   filename_0_7[8];
+			__u8   filename_8_15[8];
+			__be64 r3;
+		} assert;
+		struct fw_debug_prt {
+			__be16 dprtstridx;
+			__be16 r3[3];
+			__be32 dprtstrparam0;
+			__be32 dprtstrparam1;
+			__be32 dprtstrparam2;
+			__be32 dprtstrparam3;
+		} prt;
+	} u;
+};
+
+#define S_FW_DEBUG_CMD_TYPE	0
+#define M_FW_DEBUG_CMD_TYPE	0xff
+#define V_FW_DEBUG_CMD_TYPE(x)	((x) << S_FW_DEBUG_CMD_TYPE)
+#define G_FW_DEBUG_CMD_TYPE(x)	\
+    (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
+
+/******************************************************************************
+ *   P C I E   F W   R E G I S T E R
+ **************************************/
+
+enum pcie_fw_eval {
+	PCIE_FW_EVAL_CRASH		= 0,
+	PCIE_FW_EVAL_PREP		= 1,
+	PCIE_FW_EVAL_CONF		= 2,
+	PCIE_FW_EVAL_INIT		= 3,
+	PCIE_FW_EVAL_UNEXPECTEDEVENT	= 4,
+	PCIE_FW_EVAL_OVERHEAT		= 5,
+	PCIE_FW_EVAL_DEVICESHUTDOWN	= 6,
+};
+
+/**
+ *	Register definitions for the PCIE_FW register which the firmware uses
+ *	to retain status across RESETs.  This register should be considered
+ *	as a READ-ONLY register for Host Software and only to be used to
+ *	track firmware initialization/error state, etc.
+ */
+#define S_PCIE_FW_ERR		31
+#define M_PCIE_FW_ERR		0x1
+#define V_PCIE_FW_ERR(x)	((x) << S_PCIE_FW_ERR)
+#define G_PCIE_FW_ERR(x)	(((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
+#define F_PCIE_FW_ERR		V_PCIE_FW_ERR(1U)
+
+#define S_PCIE_FW_INIT		30
+#define M_PCIE_FW_INIT		0x1
+#define V_PCIE_FW_INIT(x)	((x) << S_PCIE_FW_INIT)
+#define G_PCIE_FW_INIT(x)	(((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
+#define F_PCIE_FW_INIT		V_PCIE_FW_INIT(1U)
+
+#define S_PCIE_FW_HALT          29
+#define M_PCIE_FW_HALT          0x1
+#define V_PCIE_FW_HALT(x)       ((x) << S_PCIE_FW_HALT)
+#define G_PCIE_FW_HALT(x)       (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
+#define F_PCIE_FW_HALT          V_PCIE_FW_HALT(1U)
+
+#define S_PCIE_FW_EVAL		24
+#define M_PCIE_FW_EVAL		0x7
+#define V_PCIE_FW_EVAL(x)	((x) << S_PCIE_FW_EVAL)
+#define G_PCIE_FW_EVAL(x)	(((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
+
+#define S_PCIE_FW_STAGE		21
+#define M_PCIE_FW_STAGE		0x7
+#define V_PCIE_FW_STAGE(x)	((x) << S_PCIE_FW_STAGE)
+#define G_PCIE_FW_STAGE(x)	(((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE)
+
+#define S_PCIE_FW_ASYNCNOT_VLD	20
+#define M_PCIE_FW_ASYNCNOT_VLD	0x1
+#define V_PCIE_FW_ASYNCNOT_VLD(x) \
+    ((x) << S_PCIE_FW_ASYNCNOT_VLD)
+#define G_PCIE_FW_ASYNCNOT_VLD(x) \
+    (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD)
+#define F_PCIE_FW_ASYNCNOT_VLD	V_PCIE_FW_ASYNCNOT_VLD(1U)
+
+#define S_PCIE_FW_ASYNCNOTINT	19
+#define M_PCIE_FW_ASYNCNOTINT	0x1
+#define V_PCIE_FW_ASYNCNOTINT(x) \
+    ((x) << S_PCIE_FW_ASYNCNOTINT)
+#define G_PCIE_FW_ASYNCNOTINT(x) \
+    (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT)
+#define F_PCIE_FW_ASYNCNOTINT	V_PCIE_FW_ASYNCNOTINT(1U)
+
+#define S_PCIE_FW_ASYNCNOT	16
+#define M_PCIE_FW_ASYNCNOT	0x7
+#define V_PCIE_FW_ASYNCNOT(x)	((x) << S_PCIE_FW_ASYNCNOT)
+#define G_PCIE_FW_ASYNCNOT(x)	\
+    (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT)
+
+#define S_PCIE_FW_MASTER_VLD	15
+#define M_PCIE_FW_MASTER_VLD	0x1
+#define V_PCIE_FW_MASTER_VLD(x)	((x) << S_PCIE_FW_MASTER_VLD)
+#define G_PCIE_FW_MASTER_VLD(x)	\
+    (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
+#define F_PCIE_FW_MASTER_VLD	V_PCIE_FW_MASTER_VLD(1U)
+
+#define S_PCIE_FW_MASTER	12
+#define M_PCIE_FW_MASTER	0x7
+#define V_PCIE_FW_MASTER(x)	((x) << S_PCIE_FW_MASTER)
+#define G_PCIE_FW_MASTER(x)	(((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
+
+#define S_PCIE_FW_RESET_VLD		11
+#define M_PCIE_FW_RESET_VLD		0x1
+#define V_PCIE_FW_RESET_VLD(x)	((x) << S_PCIE_FW_RESET_VLD)
+#define G_PCIE_FW_RESET_VLD(x)	\
+    (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD)
+#define F_PCIE_FW_RESET_VLD	V_PCIE_FW_RESET_VLD(1U)
+
+#define S_PCIE_FW_RESET		8
+#define M_PCIE_FW_RESET		0x7
+#define V_PCIE_FW_RESET(x)	((x) << S_PCIE_FW_RESET)
+#define G_PCIE_FW_RESET(x)	\
+    (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET)
+
+#define S_PCIE_FW_REGISTERED	0
+#define M_PCIE_FW_REGISTERED	0xff
+#define V_PCIE_FW_REGISTERED(x)	((x) << S_PCIE_FW_REGISTERED)
+#define G_PCIE_FW_REGISTERED(x)	\
+    (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED)
+
+
+/******************************************************************************
+ *   P C I E   F W   P F 0   R E G I S T E R
+ **********************************************/
+
+/*
+ *	this register is available as 32-bit of persistent storage (accross
+ *	PL_RST based chip-reset) for boot drivers (i.e. firmware and driver
+ *	will not write it)
+ */
+
+
+/******************************************************************************
+ *   B I N A R Y   H E A D E R   F O R M A T
+ **********************************************/
+
+/*
+ *	firmware binary header format
+ */
+struct fw_hdr {
+	__u8	ver;
+	__u8	chip;			/* terminator chip family */
+	__be16	len512;			/* bin length in units of 512-bytes */
+	__be32	fw_ver;			/* firmware version */
+	__be32	tp_microcode_ver;	/* tcp processor microcode version */
+	__u8	intfver_nic;
+	__u8	intfver_vnic;
+	__u8	intfver_ofld;
+	__u8	intfver_ri;
+	__u8	intfver_iscsipdu;
+	__u8	intfver_iscsi;
+	__u8	intfver_fcoepdu;
+	__u8	intfver_fcoe;
+	__u32	reserved2;
+	__u32	reserved3;
+	__u32	magic;			/* runtime or bootstrap fw */
+	__be32	flags;
+	__be32	reserved6[23];
+};
+
+enum fw_hdr_chip {
+	FW_HDR_CHIP_T4,
+	FW_HDR_CHIP_T5
+};
+
+#define S_FW_HDR_FW_VER_MAJOR	24
+#define M_FW_HDR_FW_VER_MAJOR	0xff
+#define V_FW_HDR_FW_VER_MAJOR(x) \
+    ((x) << S_FW_HDR_FW_VER_MAJOR)
+#define G_FW_HDR_FW_VER_MAJOR(x) \
+    (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
+
+#define S_FW_HDR_FW_VER_MINOR	16
+#define M_FW_HDR_FW_VER_MINOR	0xff
+#define V_FW_HDR_FW_VER_MINOR(x) \
+    ((x) << S_FW_HDR_FW_VER_MINOR)
+#define G_FW_HDR_FW_VER_MINOR(x) \
+    (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
+
+#define S_FW_HDR_FW_VER_MICRO	8
+#define M_FW_HDR_FW_VER_MICRO	0xff
+#define V_FW_HDR_FW_VER_MICRO(x) \
+    ((x) << S_FW_HDR_FW_VER_MICRO)
+#define G_FW_HDR_FW_VER_MICRO(x) \
+    (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
+
+#define S_FW_HDR_FW_VER_BUILD	0
+#define M_FW_HDR_FW_VER_BUILD	0xff
+#define V_FW_HDR_FW_VER_BUILD(x) \
+    ((x) << S_FW_HDR_FW_VER_BUILD)
+#define G_FW_HDR_FW_VER_BUILD(x) \
+    (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
+
+enum {
+	/* T4
+	 */
+	FW_HDR_INTFVER_NIC	= 0x00,
+	FW_HDR_INTFVER_VNIC	= 0x00,
+	FW_HDR_INTFVER_OFLD	= 0x00,
+	FW_HDR_INTFVER_RI	= 0x00,
+	FW_HDR_INTFVER_ISCSIPDU	= 0x00,
+	FW_HDR_INTFVER_ISCSI	= 0x00,
+	FW_HDR_INTFVER_FCOEPDU  = 0x00,
+	FW_HDR_INTFVER_FCOE	= 0x00,
+
+	/* T5
+	 */
+	T5FW_HDR_INTFVER_NIC	= 0x00,
+	T5FW_HDR_INTFVER_VNIC	= 0x00,
+	T5FW_HDR_INTFVER_OFLD	= 0x00,
+	T5FW_HDR_INTFVER_RI	= 0x00,
+	T5FW_HDR_INTFVER_ISCSIPDU= 0x00,
+	T5FW_HDR_INTFVER_ISCSI	= 0x00,
+	T5FW_HDR_INTFVER_FCOEPDU= 0x00,
+	T5FW_HDR_INTFVER_FCOE	= 0x00,
+};
+
+enum {
+	FW_HDR_MAGIC_RUNTIME	= 0x00000000,
+	FW_HDR_MAGIC_BOOTSTRAP	= 0x626f6f74,
+};
+
+enum fw_hdr_flags {
+	FW_HDR_FLAGS_RESET_HALT	= 0x00000001,
+};
+
+#endif /* _T4FW_INTERFACE_H_ */
diff --git a/contrib/ofed/libcxgb4/src/verbs.c b/contrib/ofed/libcxgb4/src/verbs.c
new file mode 100644
index 0000000..93d1e49
--- /dev/null
+++ b/contrib/ofed/libcxgb4/src/verbs.c
@@ -0,0 +1,702 @@
+/*
+ * Copyright (c) 2006-2014 Chelsio, Inc. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses.  You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ *     Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *      - Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *
+ *      - Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#if HAVE_CONFIG_H
+#  include <config.h>
+#endif				/* HAVE_CONFIG_H */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <errno.h>
+#include <pthread.h>
+#include <sys/mman.h>
+#include <netinet/in.h>
+#include <inttypes.h>
+#include <assert.h>
+
+#include "libcxgb4.h"
+#include "cxgb4-abi.h"
+
+#define MASKED(x) (void *)((unsigned long)(x) & c4iw_page_mask)
+
+int c4iw_query_device(struct ibv_context *context, struct ibv_device_attr *attr)
+{
+	struct ibv_query_device cmd;
+	uint64_t raw_fw_ver;
+	unsigned major, minor, sub_minor;
+	int ret;
+
+	ret = ibv_cmd_query_device(context, attr, &raw_fw_ver, &cmd,
+				   sizeof cmd);
+	if (ret)
+		return ret;
+
+	major = (raw_fw_ver >> 32) & 0xffff;
+	minor = (raw_fw_ver >> 16) & 0xffff;
+	sub_minor = raw_fw_ver & 0xffff;
+
+	snprintf(attr->fw_ver, sizeof attr->fw_ver,
+		 "%d.%d.%d", major, minor, sub_minor);
+
+	return 0;
+}
+
+int c4iw_query_port(struct ibv_context *context, uint8_t port,
+		    struct ibv_port_attr *attr)
+{
+	struct ibv_query_port cmd;
+
+	return ibv_cmd_query_port(context, port, attr, &cmd, sizeof cmd);
+}
+
+struct ibv_pd *c4iw_alloc_pd(struct ibv_context *context)
+{
+	struct ibv_alloc_pd cmd;
+	struct c4iw_alloc_pd_resp resp;
+	struct c4iw_pd *pd;
+
+	pd = malloc(sizeof *pd);
+	if (!pd)
+		return NULL;
+
+	if (ibv_cmd_alloc_pd(context, &pd->ibv_pd, &cmd, sizeof cmd,
+			     &resp.ibv_resp, sizeof resp)) {
+		free(pd);
+		return NULL;
+	}
+
+	return &pd->ibv_pd;
+}
+
+int c4iw_free_pd(struct ibv_pd *pd)
+{
+	int ret;
+
+	ret = ibv_cmd_dealloc_pd(pd);
+	if (ret)
+		return ret;
+
+	free(pd);
+	return 0;
+}
+
+static struct ibv_mr *__c4iw_reg_mr(struct ibv_pd *pd, void *addr,
+				    size_t length, uint64_t hca_va,
+				    int access)
+{
+	struct c4iw_mr *mhp;
+	struct ibv_reg_mr cmd;
+	struct ibv_reg_mr_resp resp;
+	struct c4iw_dev *dev = to_c4iw_dev(pd->context->device);
+
+	mhp = malloc(sizeof *mhp);
+	if (!mhp)
+		return NULL;
+
+	if (ibv_cmd_reg_mr(pd, addr, length, hca_va,
+			   access, &mhp->ibv_mr, &cmd, sizeof cmd,
+			   &resp, sizeof resp)) {
+		free(mhp);
+		return NULL;
+	}
+
+	mhp->va_fbo = hca_va;
+	mhp->len = length;
+
+	PDBG("%s stag 0x%x va_fbo 0x%" PRIx64 " len %d\n",
+	     __func__, mhp->ibv_mr.rkey, mhp->va_fbo, mhp->len);
+
+	pthread_spin_lock(&dev->lock);
+	dev->mmid2ptr[c4iw_mmid(mhp->ibv_mr.lkey)] = mhp;
+	pthread_spin_unlock(&dev->lock);
+	INC_STAT(mr);
+	return &mhp->ibv_mr;
+}
+
+struct ibv_mr *c4iw_reg_mr(struct ibv_pd *pd, void *addr,
+			   size_t length, int access)
+{
+	PDBG("%s addr %p length %ld\n", __func__, addr, length);
+	return __c4iw_reg_mr(pd, addr, length, (uintptr_t) addr, access);
+}
+
+int c4iw_dereg_mr(struct ibv_mr *mr)
+{
+	int ret;
+	struct c4iw_dev *dev = to_c4iw_dev(mr->pd->context->device);
+
+	ret = ibv_cmd_dereg_mr(mr);
+	if (ret)
+		return ret;
+
+	pthread_spin_lock(&dev->lock);
+	dev->mmid2ptr[c4iw_mmid(mr->lkey)] = NULL;
+	pthread_spin_unlock(&dev->lock);
+
+	free(to_c4iw_mr(mr));
+
+	return 0;
+}
+
+struct ibv_cq *c4iw_create_cq(struct ibv_context *context, int cqe,
+			      struct ibv_comp_channel *channel, int comp_vector)
+{
+	struct ibv_create_cq cmd;
+	struct c4iw_create_cq_resp resp;
+	struct c4iw_cq *chp;
+	struct c4iw_dev *dev = to_c4iw_dev(context->device);
+	int ret;
+
+	chp = calloc(1, sizeof *chp);
+	if (!chp) {
+		return NULL;
+	}
+
+	resp.reserved = 0;
+	ret = ibv_cmd_create_cq(context, cqe, channel, comp_vector,
+				&chp->ibv_cq, &cmd, sizeof cmd,
+				&resp.ibv_resp, sizeof resp);
+	if (ret)
+		goto err1;
+
+	if (resp.reserved)
+		PDBG("%s c4iw_create_cq_resp reserved field modified by kernel\n",
+		     __FUNCTION__);
+
+	pthread_spin_init(&chp->lock, PTHREAD_PROCESS_PRIVATE);
+#ifdef STALL_DETECTION
+	gettimeofday(&chp->time, NULL);
+#endif
+	chp->rhp = dev;
+	chp->cq.qid_mask = resp.qid_mask;
+	chp->cq.cqid = resp.cqid;
+	chp->cq.size = resp.size;
+	chp->cq.memsize = resp.memsize;
+	chp->cq.gen = 1;
+	chp->cq.queue = mmap(NULL, chp->cq.memsize, PROT_READ|PROT_WRITE,
+			     MAP_SHARED, context->cmd_fd, resp.key);
+	if (chp->cq.queue == MAP_FAILED)
+		goto err2;
+
+	chp->cq.ugts = mmap(NULL, c4iw_page_size, PROT_WRITE, MAP_SHARED,
+			   context->cmd_fd, resp.gts_key);
+	if (chp->cq.ugts == MAP_FAILED)
+		goto err3;
+
+	if (dev_is_t5(chp->rhp))
+		chp->cq.ugts += 3;
+	else
+		chp->cq.ugts += 1;
+	chp->cq.sw_queue = calloc(chp->cq.size, sizeof *chp->cq.queue);
+	if (!chp->cq.sw_queue)
+		goto err4;
+
+	PDBG("%s cqid 0x%x key %" PRIx64 " va %p memsize %lu gts_key %"
+	       PRIx64 " va %p qid_mask 0x%x\n",
+	       __func__, chp->cq.cqid, resp.key, chp->cq.queue,
+	       chp->cq.memsize, resp.gts_key, chp->cq.ugts, chp->cq.qid_mask);
+
+	pthread_spin_lock(&dev->lock);
+	dev->cqid2ptr[chp->cq.cqid] = chp;
+	pthread_spin_unlock(&dev->lock);
+	INC_STAT(cq);
+	return &chp->ibv_cq;
+err4:
+	munmap(MASKED(chp->cq.ugts), c4iw_page_size);
+err3:
+	munmap(chp->cq.queue, chp->cq.memsize);
+err2:
+	(void)ibv_cmd_destroy_cq(&chp->ibv_cq);
+err1:
+	free(chp);
+	return NULL;
+}
+
+int c4iw_resize_cq(struct ibv_cq *ibcq, int cqe)
+{
+#if 0
+	int ret;
+
+	struct ibv_resize_cq cmd;
+	struct ibv_resize_cq_resp resp;
+	ret = ibv_cmd_resize_cq(ibcq, cqe, &cmd, sizeof cmd, &resp, sizeof resp);
+	PDBG("%s ret %d\n", __func__, ret);
+	return ret;
+#else
+	return -ENOSYS;
+#endif
+}
+
+int c4iw_destroy_cq(struct ibv_cq *ibcq)
+{
+	int ret;
+	struct c4iw_cq *chp = to_c4iw_cq(ibcq);
+	struct c4iw_dev *dev = to_c4iw_dev(ibcq->context->device);
+
+	chp->cq.error = 1;
+	ret = ibv_cmd_destroy_cq(ibcq);
+	if (ret) {
+		return ret;
+	}
+	munmap(MASKED(chp->cq.ugts), c4iw_page_size);
+	munmap(chp->cq.queue, chp->cq.memsize);
+
+	pthread_spin_lock(&dev->lock);
+	dev->cqid2ptr[chp->cq.cqid] = NULL;
+	pthread_spin_unlock(&dev->lock);
+
+	free(chp->cq.sw_queue);
+	free(chp);
+	return 0;
+}
+
+struct ibv_srq *c4iw_create_srq(struct ibv_pd *pd,
+				struct ibv_srq_init_attr *attr)
+{
+	return NULL;
+}
+
+int c4iw_modify_srq(struct ibv_srq *srq, struct ibv_srq_attr *attr,
+		    int attr_mask)
+{
+	return ENOSYS;
+}
+
+int c4iw_destroy_srq(struct ibv_srq *srq)
+{
+	return ENOSYS;
+}
+
+int c4iw_post_srq_recv(struct ibv_srq *ibsrq, struct ibv_recv_wr *wr,
+		       struct ibv_recv_wr **bad_wr)
+{
+	return ENOSYS;
+}
+
+static struct ibv_qp *create_qp_v0(struct ibv_pd *pd,
+				   struct ibv_qp_init_attr *attr)
+{
+	struct ibv_create_qp cmd;
+	struct c4iw_create_qp_resp_v0 resp;
+	struct c4iw_qp *qhp;
+	struct c4iw_dev *dev = to_c4iw_dev(pd->context->device);
+	int ret;
+	void *dbva;
+
+	PDBG("%s enter qp\n", __func__);
+	qhp = calloc(1, sizeof *qhp);
+	if (!qhp)
+		goto err1;
+
+	ret = ibv_cmd_create_qp(pd, &qhp->ibv_qp, attr, &cmd,
+				sizeof cmd, &resp.ibv_resp, sizeof resp);
+	if (ret)
+		goto err2;
+
+	PDBG("%s sqid 0x%x sq key %" PRIx64 " sq db/gts key %" PRIx64
+	       " rqid 0x%x rq key %" PRIx64 " rq db/gts key %" PRIx64
+	       " qid_mask 0x%x\n",
+		__func__,
+		resp.sqid, resp.sq_key, resp.sq_db_gts_key,
+		resp.rqid, resp.rq_key, resp.rq_db_gts_key, resp.qid_mask);
+
+	qhp->wq.qid_mask = resp.qid_mask;
+	qhp->rhp = dev;
+	qhp->wq.sq.qid = resp.sqid;
+	qhp->wq.sq.size = resp.sq_size;
+	qhp->wq.sq.memsize = resp.sq_memsize;
+	qhp->wq.sq.flags = 0;
+	qhp->wq.rq.msn = 1;
+	qhp->wq.rq.qid = resp.rqid;
+	qhp->wq.rq.size = resp.rq_size;
+	qhp->wq.rq.memsize = resp.rq_memsize;
+	pthread_spin_init(&qhp->lock, PTHREAD_PROCESS_PRIVATE);
+
+	dbva = mmap(NULL, c4iw_page_size, PROT_WRITE, MAP_SHARED,
+		    pd->context->cmd_fd, resp.sq_db_gts_key);
+	if (dbva == MAP_FAILED)
+		goto err3;
+
+	qhp->wq.sq.udb = dbva;
+	qhp->wq.sq.queue = mmap(NULL, qhp->wq.sq.memsize,
+			    PROT_WRITE, MAP_SHARED,
+			    pd->context->cmd_fd, resp.sq_key);
+	if (qhp->wq.sq.queue == MAP_FAILED)
+		goto err4;
+
+	dbva = mmap(NULL, c4iw_page_size, PROT_WRITE, MAP_SHARED,
+		    pd->context->cmd_fd, resp.rq_db_gts_key);
+	if (dbva == MAP_FAILED)
+		goto err5;
+	qhp->wq.rq.udb = dbva;
+	qhp->wq.rq.queue = mmap(NULL, qhp->wq.rq.memsize,
+			    PROT_WRITE, MAP_SHARED,
+			    pd->context->cmd_fd, resp.rq_key);
+	if (qhp->wq.rq.queue == MAP_FAILED)
+		goto err6;
+
+	qhp->wq.sq.sw_sq = calloc(qhp->wq.sq.size, sizeof (struct t4_swsqe));
+	if (!qhp->wq.sq.sw_sq)
+		goto err7;
+
+	qhp->wq.rq.sw_rq = calloc(qhp->wq.rq.size, sizeof (uint64_t));
+	if (!qhp->wq.rq.sw_rq)
+		goto err8;
+
+	PDBG("%s sq dbva %p sq qva %p sq depth %u sq memsize %lu "
+	       " rq dbva %p rq qva %p rq depth %u rq memsize %lu\n",
+	     __func__,
+	     qhp->wq.sq.udb, qhp->wq.sq.queue,
+	     qhp->wq.sq.size, qhp->wq.sq.memsize,
+	     qhp->wq.rq.udb, qhp->wq.rq.queue,
+	     qhp->wq.rq.size, qhp->wq.rq.memsize);
+
+	qhp->sq_sig_all = attr->sq_sig_all;
+
+	pthread_spin_lock(&dev->lock);
+	dev->qpid2ptr[qhp->wq.sq.qid] = qhp;
+	pthread_spin_unlock(&dev->lock);
+	INC_STAT(qp);
+	return &qhp->ibv_qp;
+err8:
+	free(qhp->wq.sq.sw_sq);
+err7:
+	munmap((void *)qhp->wq.rq.queue, qhp->wq.rq.memsize);
+err6:
+	munmap(MASKED(qhp->wq.rq.udb), c4iw_page_size);
+err5:
+	munmap((void *)qhp->wq.sq.queue, qhp->wq.sq.memsize);
+err4:
+	munmap(MASKED(qhp->wq.sq.udb), c4iw_page_size);
+err3:
+	(void)ibv_cmd_destroy_qp(&qhp->ibv_qp);
+err2:
+	free(qhp);
+err1:
+	return NULL;
+}
+
+static struct ibv_qp *create_qp(struct ibv_pd *pd,
+				struct ibv_qp_init_attr *attr)
+{
+	struct ibv_create_qp cmd;
+	struct c4iw_create_qp_resp resp;
+	struct c4iw_qp *qhp;
+	struct c4iw_dev *dev = to_c4iw_dev(pd->context->device);
+	struct c4iw_context *ctx = to_c4iw_context(pd->context);
+	int ret;
+	void *dbva;
+
+	PDBG("%s enter qp\n", __func__);
+	qhp = calloc(1, sizeof *qhp);
+	if (!qhp)
+		goto err1;
+
+	ret = ibv_cmd_create_qp(pd, &qhp->ibv_qp, attr, &cmd,
+				sizeof cmd, &resp.ibv_resp, sizeof resp);
+	if (ret)
+		goto err2;
+
+	PDBG("%s sqid 0x%x sq key %" PRIx64 " sq db/gts key %" PRIx64
+	       " rqid 0x%x rq key %" PRIx64 " rq db/gts key %" PRIx64
+	       " qid_mask 0x%x\n",
+		__func__,
+		resp.sqid, resp.sq_key, resp.sq_db_gts_key,
+		resp.rqid, resp.rq_key, resp.rq_db_gts_key, resp.qid_mask);
+
+	qhp->wq.qid_mask = resp.qid_mask;
+	qhp->rhp = dev;
+	qhp->wq.sq.qid = resp.sqid;
+	qhp->wq.sq.size = resp.sq_size;
+	qhp->wq.sq.memsize = resp.sq_memsize;
+	qhp->wq.sq.flags = resp.flags & C4IW_QPF_ONCHIP ? T4_SQ_ONCHIP : 0;
+	qhp->wq.sq.flush_cidx = -1;
+	qhp->wq.rq.msn = 1;
+	qhp->wq.rq.qid = resp.rqid;
+	qhp->wq.rq.size = resp.rq_size;
+	qhp->wq.rq.memsize = resp.rq_memsize;
+	if (ma_wr && resp.sq_memsize < (resp.sq_size + 1) *
+	    sizeof *qhp->wq.sq.queue + 16*sizeof(__be64) ) {
+		ma_wr = 0;
+		fprintf(stderr, "libcxgb4 warning - downlevel iw_cxgb4 driver. "
+			"MA workaround disabled.\n");
+	}
+	pthread_spin_init(&qhp->lock, PTHREAD_PROCESS_PRIVATE);
+
+	dbva = mmap(NULL, c4iw_page_size, PROT_WRITE, MAP_SHARED,
+		    pd->context->cmd_fd, resp.sq_db_gts_key);
+	if (dbva == MAP_FAILED) {
+		PDBG(" %s mmap for sq db failed\n", __func__);
+		abort();
+		goto err3;
+	}
+	qhp->wq.sq.udb = dbva;
+	if (dev_is_t5(qhp->rhp)) {
+		qhp->wq.sq.udb += (128*(qhp->wq.sq.qid & qhp->wq.qid_mask))/4;
+		qhp->wq.sq.udb += 2;
+	}
+
+	qhp->wq.sq.queue = mmap(NULL, qhp->wq.sq.memsize,
+			    PROT_READ | PROT_WRITE, MAP_SHARED,
+			    pd->context->cmd_fd, resp.sq_key);
+	if (qhp->wq.sq.queue == MAP_FAILED) {
+		PDBG(" %s mmap for sq q failed size is qhp->wq.sq.memsize %zu \n", __func__, qhp->wq.sq.memsize);
+		abort();
+		goto err4;
+	}
+
+	dbva = mmap(NULL, c4iw_page_size, PROT_WRITE, MAP_SHARED,
+		    pd->context->cmd_fd, resp.rq_db_gts_key);
+	if (dbva == MAP_FAILED)
+		goto err5;
+	qhp->wq.rq.udb = dbva;
+	if (dev_is_t5(qhp->rhp)) {
+		qhp->wq.rq.udb += (128*(qhp->wq.rq.qid & qhp->wq.qid_mask))/4;
+		qhp->wq.rq.udb += 2;
+	}
+	qhp->wq.rq.queue = mmap(NULL, qhp->wq.rq.memsize,
+			    PROT_READ | PROT_WRITE, MAP_SHARED,
+			    pd->context->cmd_fd, resp.rq_key);
+	if (qhp->wq.rq.queue == MAP_FAILED)
+		goto err6;
+
+	qhp->wq.sq.sw_sq = calloc(qhp->wq.sq.size, sizeof (struct t4_swsqe));
+	if (!qhp->wq.sq.sw_sq)
+		goto err7;
+
+	qhp->wq.rq.sw_rq = calloc(qhp->wq.rq.size, sizeof (uint64_t));
+	if (!qhp->wq.rq.sw_rq)
+		goto err8;
+
+	if (t4_sq_onchip(&qhp->wq)) {
+		qhp->wq.sq.ma_sync = mmap(NULL, c4iw_page_size, PROT_WRITE,
+					  MAP_SHARED, pd->context->cmd_fd,
+					  resp.ma_sync_key);
+		if (qhp->wq.sq.ma_sync == MAP_FAILED)
+			goto err9;
+		qhp->wq.sq.ma_sync += (A_PCIE_MA_SYNC & (c4iw_page_size - 1));
+	}
+
+	if (ctx->status_page_size) {
+		qhp->wq.db_offp = &ctx->status_page->db_off;
+	} else {
+		qhp->wq.db_offp = 
+			&qhp->wq.rq.queue[qhp->wq.rq.size].status.db_off;
+	}
+
+	PDBG("%s sq dbva %p sq qva %p sq depth %u sq memsize %lu "
+	       " rq dbva %p rq qva %p rq depth %u rq memsize %lu\n",
+	     __func__,
+	     qhp->wq.sq.udb, qhp->wq.sq.queue,
+	     qhp->wq.sq.size, qhp->wq.sq.memsize,
+	     qhp->wq.rq.udb, qhp->wq.rq.queue,
+	     qhp->wq.rq.size, qhp->wq.rq.memsize);
+
+	qhp->sq_sig_all = attr->sq_sig_all;
+
+	pthread_spin_lock(&dev->lock);
+	dev->qpid2ptr[qhp->wq.sq.qid] = qhp;
+	pthread_spin_unlock(&dev->lock);
+	INC_STAT(qp);
+	return &qhp->ibv_qp;
+err9:
+	free(qhp->wq.rq.sw_rq);
+err8:
+	free(qhp->wq.sq.sw_sq);
+err7:
+	munmap((void *)qhp->wq.rq.queue, qhp->wq.rq.memsize);
+err6:
+	munmap(MASKED(qhp->wq.rq.udb), c4iw_page_size);
+err5:
+	munmap((void *)qhp->wq.sq.queue, qhp->wq.sq.memsize);
+err4:
+	munmap(MASKED(qhp->wq.sq.udb), c4iw_page_size);
+err3:
+	(void)ibv_cmd_destroy_qp(&qhp->ibv_qp);
+err2:
+	free(qhp);
+err1:
+	return NULL;
+}
+
+struct ibv_qp *c4iw_create_qp(struct ibv_pd *pd,
+				     struct ibv_qp_init_attr *attr)
+{
+	struct c4iw_dev *dev = to_c4iw_dev(pd->context->device);
+
+	if (dev->abi_version == 0)
+		return create_qp_v0(pd, attr);
+	return create_qp(pd, attr);
+}
+
+static void reset_qp(struct c4iw_qp *qhp)
+{
+	PDBG("%s enter qp %p\n", __func__, qhp);
+	qhp->wq.sq.cidx = 0;
+	qhp->wq.sq.wq_pidx = qhp->wq.sq.pidx = qhp->wq.sq.in_use = 0;
+	qhp->wq.rq.cidx = qhp->wq.rq.pidx = qhp->wq.rq.in_use = 0;
+	qhp->wq.sq.oldest_read = NULL;
+	memset(qhp->wq.sq.queue, 0, qhp->wq.sq.memsize);
+	memset(qhp->wq.rq.queue, 0, qhp->wq.rq.memsize);
+}
+
+int c4iw_modify_qp(struct ibv_qp *ibqp, struct ibv_qp_attr *attr,
+		   int attr_mask)
+{
+	struct ibv_modify_qp cmd;
+	struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
+	int ret;
+
+	PDBG("%s enter qp %p new state %d\n", __func__, ibqp, attr_mask & IBV_QP_STATE ? attr->qp_state : -1);
+	pthread_spin_lock(&qhp->lock);
+	if (t4_wq_in_error(&qhp->wq))
+		c4iw_flush_qp(qhp);
+	ret = ibv_cmd_modify_qp(ibqp, attr, attr_mask, &cmd, sizeof cmd);
+	if (!ret && (attr_mask & IBV_QP_STATE) && attr->qp_state == IBV_QPS_RESET)
+		reset_qp(qhp);
+	pthread_spin_unlock(&qhp->lock);
+	return ret;
+}
+
+int c4iw_destroy_qp(struct ibv_qp *ibqp)
+{
+	int ret;
+	struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
+	struct c4iw_dev *dev = to_c4iw_dev(ibqp->context->device);
+
+	PDBG("%s enter qp %p\n", __func__, ibqp);
+	pthread_spin_lock(&qhp->lock);
+	c4iw_flush_qp(qhp);
+	pthread_spin_unlock(&qhp->lock);
+
+	ret = ibv_cmd_destroy_qp(ibqp);
+	if (ret) {
+		return ret;
+	}
+	if (t4_sq_onchip(&qhp->wq)) {
+		qhp->wq.sq.ma_sync -= (A_PCIE_MA_SYNC & (c4iw_page_size - 1));
+		munmap((void *)qhp->wq.sq.ma_sync, c4iw_page_size);
+	}
+	munmap(MASKED(qhp->wq.sq.udb), c4iw_page_size);
+	munmap(MASKED(qhp->wq.rq.udb), c4iw_page_size);
+	munmap(qhp->wq.sq.queue, qhp->wq.sq.memsize);
+	munmap(qhp->wq.rq.queue, qhp->wq.rq.memsize);
+
+	pthread_spin_lock(&dev->lock);
+	dev->qpid2ptr[qhp->wq.sq.qid] = NULL;
+	pthread_spin_unlock(&dev->lock);
+
+	free(qhp->wq.rq.sw_rq);
+	free(qhp->wq.sq.sw_sq);
+	free(qhp);
+	return 0;
+}
+
+int c4iw_query_qp(struct ibv_qp *ibqp, struct ibv_qp_attr *attr,
+		  int attr_mask, struct ibv_qp_init_attr *init_attr)
+{
+	struct ibv_query_qp cmd;
+	struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
+	int ret;
+
+	pthread_spin_lock(&qhp->lock);
+	if (t4_wq_in_error(&qhp->wq))
+		c4iw_flush_qp(qhp);
+	ret = ibv_cmd_query_qp(ibqp, attr, attr_mask, init_attr, &cmd, sizeof cmd);
+	pthread_spin_unlock(&qhp->lock);
+	return ret;
+}
+
+struct ibv_ah *c4iw_create_ah(struct ibv_pd *pd, struct ibv_ah_attr *attr)
+{
+	return NULL;
+}
+
+int c4iw_destroy_ah(struct ibv_ah *ah)
+{
+	return ENOSYS;
+}
+
+int c4iw_attach_mcast(struct ibv_qp *ibqp, const union ibv_gid *gid,
+		      uint16_t lid)
+{
+	struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
+	int ret;
+
+	pthread_spin_lock(&qhp->lock);
+	if (t4_wq_in_error(&qhp->wq))
+		c4iw_flush_qp(qhp);
+	ret = ibv_cmd_attach_mcast(ibqp, gid, lid);
+	pthread_spin_unlock(&qhp->lock);
+	return ret;
+}
+
+int c4iw_detach_mcast(struct ibv_qp *ibqp, const union ibv_gid *gid,
+		      uint16_t lid)
+{
+	struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
+	int ret;
+
+	pthread_spin_lock(&qhp->lock);
+	if (t4_wq_in_error(&qhp->wq))
+		c4iw_flush_qp(qhp);
+	ret = ibv_cmd_detach_mcast(ibqp, gid, lid);
+	pthread_spin_unlock(&qhp->lock);
+	return ret;
+}
+
+void c4iw_async_event(struct ibv_async_event *event)
+{
+	PDBG("%s type %d obj %p\n", __func__, event->event_type,
+	event->element.cq);
+
+	switch (event->event_type) {
+	case IBV_EVENT_CQ_ERR:
+		break;
+	case IBV_EVENT_QP_FATAL:
+	case IBV_EVENT_QP_REQ_ERR:
+	case IBV_EVENT_QP_ACCESS_ERR:
+	case IBV_EVENT_PATH_MIG_ERR: {
+		struct c4iw_qp *qhp = to_c4iw_qp(event->element.qp);
+		pthread_spin_lock(&qhp->lock);
+		c4iw_flush_qp(qhp);
+		pthread_spin_unlock(&qhp->lock);
+		break;
+	}
+	case IBV_EVENT_SQ_DRAINED:
+	case IBV_EVENT_PATH_MIG:
+	case IBV_EVENT_COMM_EST:
+	case IBV_EVENT_QP_LAST_WQE_REACHED:
+	default:
+		break;
+	}
+}
diff --git a/contrib/ofed/usr.lib/Makefile b/contrib/ofed/usr.lib/Makefile
index a26440b..1bf7168 100644
--- a/contrib/ofed/usr.lib/Makefile
+++ b/contrib/ofed/usr.lib/Makefile
@@ -1,6 +1,6 @@
 .include <bsd.own.mk>
 
 SUBDIR	= libibcommon libibmad libibumad libibverbs libmlx4 libmthca
-SUBDIR	+= libopensm libosmcomp libosmvendor libibcm librdmacm libsdp
+SUBDIR	+= libopensm libosmcomp libosmvendor libibcm librdmacm libsdp libcxgb4
 
 .include <bsd.subdir.mk>
diff --git a/contrib/ofed/usr.lib/libcxgb4/Makefile b/contrib/ofed/usr.lib/libcxgb4/Makefile
new file mode 100644
index 0000000..d4619e7
--- /dev/null
+++ b/contrib/ofed/usr.lib/libcxgb4/Makefile
@@ -0,0 +1,24 @@
+# $FreeBSD$
+
+SHLIBDIR?=	/usr/lib
+
+.include <bsd.own.mk>
+
+CXGB4DIR=	${.CURDIR}/../../libcxgb4
+IBVERBSDIR=	${.CURDIR}/../../libibverbs
+CXGBSRCDIR=	${CXGB4DIR}/src
+
+.PATH: ${CXGBSRCDIR}
+
+LIB=		cxgb4
+SHLIB_MAJOR=	1
+MK_PROFILE=	no
+
+SRCS=	dev.c cq.c qp.c verbs.c
+
+CFLAGS+= -g -DHAVE_CONFIG_H -DDEBUG
+CFLAGS+= -I${.CURDIR} -I${CXGBSRCDIR} -I${IBVERBSDIR}/include 
+
+VERSION_MAP= ${CXGBSRCDIR}/cxgb4.map
+
+.include <bsd.lib.mk>
diff --git a/contrib/ofed/usr.lib/libcxgb4/config.h b/contrib/ofed/usr.lib/libcxgb4/config.h
new file mode 100644
index 0000000..a235013
--- /dev/null
+++ b/contrib/ofed/usr.lib/libcxgb4/config.h
@@ -0,0 +1,4 @@
+#define	HAVE_IBV_DONTFORK_RANGE
+#define	HAVE_IBV_DOFORK_RANGE
+#define	HAVE_IBV_REGISTER_DRIVER
+#define	HAVE_IBV_READ_SYSFS_FILE