diff options
| author | dim <dim@FreeBSD.org> | 2014-03-21 17:53:59 +0000 |
|---|---|---|
| committer | dim <dim@FreeBSD.org> | 2014-03-21 17:53:59 +0000 |
| commit | 9cedb8bb69b89b0f0c529937247a6a80cabdbaec (patch) | |
| tree | c978f0e9ec1ab92dc8123783f30b08a7fd1e2a39 /contrib/llvm/utils | |
| parent | 03fdc2934eb61c44c049a02b02aa974cfdd8a0eb (diff) | |
| download | FreeBSD-src-9cedb8bb69b89b0f0c529937247a6a80cabdbaec.zip FreeBSD-src-9cedb8bb69b89b0f0c529937247a6a80cabdbaec.tar.gz | |
MFC 261991:
Upgrade our copy of llvm/clang to 3.4 release. This version supports
all of the features in the current working draft of the upcoming C++
standard, provisionally named C++1y.
The code generator's performance is greatly increased, and the loop
auto-vectorizer is now enabled at -Os and -O2 in addition to -O3. The
PowerPC backend has made several major improvements to code generation
quality and compile time, and the X86, SPARC, ARM32, Aarch64 and SystemZ
backends have all seen major feature work.
Release notes for llvm and clang can be found here:
<http://llvm.org/releases/3.4/docs/ReleaseNotes.html>
<http://llvm.org/releases/3.4/tools/clang/docs/ReleaseNotes.html>
MFC 262121 (by emaste):
Update lldb for clang/llvm 3.4 import
This commit largely restores the lldb source to the upstream r196259
snapshot with the addition of threaded inferior support and a few bug
fixes.
Specific upstream lldb revisions restored include:
SVN git
181387 779e6ac
181703 7bef4e2
182099 b31044e
182650 f2dcf35
182683 0d91b80
183862 15c1774
183929 99447a6
184177 0b2934b
184948 4dc3761
184954 007e7bc
186990 eebd175
Sponsored by: DARPA, AFRL
MFC 262186 (by emaste):
Fix mismerge in r262121
A break statement was lost in the merge. The error had no functional
impact, but restore it to reduce the diff against upstream.
MFC 262303:
Pull in r197521 from upstream clang trunk (by rdivacky):
Use the integrated assembler by default on FreeBSD/ppc and ppc64.
Requested by: jhibbits
MFC 262611:
Pull in r196874 from upstream llvm trunk:
Fix a crash that occurs when PWD is invalid.
MCJIT needs to be able to run in hostile environments, even when PWD
is invalid. There's no need to crash MCJIT in this case.
The obvious fix is to simply leave MCContext's CompilationDir empty
when PWD can't be determined. This way, MCJIT clients,
and other clients that link with LLVM don't need a valid working directory.
If we do want to guarantee valid CompilationDir, that should be done
only for clients of getCompilationDir(). This is as simple as checking
for an empty string.
The only current use of getCompilationDir is EmitGenDwarfInfo, which
won't conceivably run with an invalid working dir. However, in the
purely hypothetically and untestable case that this happens, the
AT_comp_dir will be omitted from the compilation_unit DIE.
This should help fix assertions occurring with ports-mgmt/tinderbox,
when it is using jails, and sometimes invalidates clang's current
working directory.
Reported by: decke
MFC 262809:
Pull in r203007 from upstream clang trunk:
Don't produce an alias between destructors with different calling conventions.
Fixes pr19007.
(Please note that is an LLVM PR identifier, not a FreeBSD one.)
This should fix Firefox and/or libxul crashes (due to problems with
regparm/stdcall calling conventions) on i386.
Reported by: multiple users on freebsd-current
PR: bin/187103
MFC 263048:
Repair recognition of "CC" as an alias for the C++ compiler, since it
was silently broken by upstream for a Windows-specific use-case.
Apparently some versions of CMake still rely on this archaic feature...
Reported by: rakuco
MFC 263049:
Garbage collect the old way of adding the libstdc++ include directories
in clang's InitHeaderSearch.cpp. This has been superseded by David
Chisnall's commit in r255321.
Moreover, if libc++ is used, the libstdc++ include directories should
not be in the search path at all. These directories are now only used
if you pass -stdlib=libstdc++.
Diffstat (limited to 'contrib/llvm/utils')
34 files changed, 1715 insertions, 798 deletions
diff --git a/contrib/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/contrib/llvm/utils/TableGen/AsmMatcherEmitter.cpp index 218af21..de24cde 100644 --- a/contrib/llvm/utils/TableGen/AsmMatcherEmitter.cpp +++ b/contrib/llvm/utils/TableGen/AsmMatcherEmitter.cpp @@ -97,7 +97,6 @@ //===----------------------------------------------------------------------===// #include "CodeGenTarget.h" -#include "StringToOffsetTable.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/ADT/PointerUnion.h" #include "llvm/ADT/STLExtras.h" @@ -110,10 +109,13 @@ #include "llvm/TableGen/Error.h" #include "llvm/TableGen/Record.h" #include "llvm/TableGen/StringMatcher.h" +#include "llvm/TableGen/StringToOffsetTable.h" #include "llvm/TableGen/TableGenBackend.h" #include <cassert> +#include <cctype> #include <map> #include <set> +#include <sstream> using namespace llvm; static cl::opt<std::string> @@ -124,6 +126,13 @@ namespace { class AsmMatcherInfo; struct SubtargetFeatureInfo; +// Register sets are used as keys in some second-order sets TableGen creates +// when generating its data structures. This means that the order of two +// RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and +// can even affect compiler output (at least seen in diagnostics produced when +// all matches fail). So we use a type that sorts them consistently. +typedef std::set<Record*, LessRecordByID> RegisterSet; + class AsmMatcherEmitter { RecordKeeper &Records; public: @@ -184,7 +193,7 @@ struct ClassInfo { std::string ParserMethod; /// For register classes, the records for all the registers in this class. - std::set<Record*> Registers; + RegisterSet Registers; /// For custom match classes, he diagnostic kind for when the predicate fails. std::string DiagnosticType; @@ -212,11 +221,11 @@ public: if (!isRegisterClass() || !RHS.isRegisterClass()) return false; - std::set<Record*> Tmp; - std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin()); + RegisterSet Tmp; + std::insert_iterator<RegisterSet> II(Tmp, Tmp.begin()); std::set_intersection(Registers.begin(), Registers.end(), RHS.Registers.begin(), RHS.Registers.end(), - II); + II, LessRecordByID()); return !Tmp.empty(); } @@ -429,6 +438,9 @@ struct MatchableInfo { /// function. std::string ConversionFnKind; + /// If this instruction is deprecated in some form. + bool HasDeprecation; + MatchableInfo(const CodeGenInstruction &CGI) : AsmVariantID(0), TheDef(CGI.TheDef), DefRec(&CGI), AsmString(CGI.AsmString) { @@ -612,7 +624,7 @@ public: RegisterClassesTy RegisterClasses; /// Map of Predicate records to their subtarget information. - std::map<Record*, SubtargetFeatureInfo*> SubtargetFeatures; + std::map<Record*, SubtargetFeatureInfo*, LessRecordByID> SubtargetFeatures; /// Map of AsmOperandClass records to their class information. std::map<Record*, ClassInfo*> AsmOperandClasses; @@ -662,7 +674,7 @@ public: /// given operand. SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const { assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!"); - std::map<Record*, SubtargetFeatureInfo*>::const_iterator I = + std::map<Record*, SubtargetFeatureInfo*, LessRecordByID>::const_iterator I = SubtargetFeatures.find(Def); return I == SubtargetFeatures.end() ? 0 : I->second; } @@ -778,6 +790,13 @@ void MatchableInfo::initialize(const AsmMatcherInfo &Info, if (Record *Reg = AsmOperands[i].SingletonReg) SingletonRegisters.insert(Reg); } + + const RecordVal *DepMask = TheDef->getValue("DeprecatedFeatureMask"); + if (!DepMask) + DepMask = TheDef->getValue("ComplexDeprecationPredicate"); + + HasDeprecation = + DepMask ? !DepMask->getValue()->getAsUnquotedString().empty() : false; } /// tokenizeAsmString - Tokenize a simplified assembly string. @@ -836,9 +855,11 @@ void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info) { } case '.': - if (InTok) - AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); - Prev = i; + if (!Info.AsmParser->getValueAsBit("MnemonicContainsDot")) { + if (InTok) + AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); + Prev = i; + } InTok = true; break; @@ -1044,6 +1065,18 @@ AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) { PrintFatalError(Rec->getLoc(), "operand has no match class!"); } +struct LessRegisterSet { + bool operator() (const RegisterSet &LHS, const RegisterSet & RHS) const { + // std::set<T> defines its own compariso "operator<", but it + // performs a lexicographical comparison by T's innate comparison + // for some reason. We don't want non-deterministic pointer + // comparisons so use this instead. + return std::lexicographical_compare(LHS.begin(), LHS.end(), + RHS.begin(), RHS.end(), + LessRecordByID()); + } +}; + void AsmMatcherInfo:: buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) { const std::vector<CodeGenRegister*> &Registers = @@ -1051,33 +1084,35 @@ buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) { ArrayRef<CodeGenRegisterClass*> RegClassList = Target.getRegBank().getRegClasses(); + typedef std::set<RegisterSet, LessRegisterSet> RegisterSetSet; + // The register sets used for matching. - std::set< std::set<Record*> > RegisterSets; + RegisterSetSet RegisterSets; // Gather the defined sets. for (ArrayRef<CodeGenRegisterClass*>::const_iterator it = - RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) - RegisterSets.insert(std::set<Record*>( + RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) + RegisterSets.insert(RegisterSet( (*it)->getOrder().begin(), (*it)->getOrder().end())); // Add any required singleton sets. for (SmallPtrSet<Record*, 16>::iterator it = SingletonRegisters.begin(), ie = SingletonRegisters.end(); it != ie; ++it) { Record *Rec = *it; - RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1)); + RegisterSets.insert(RegisterSet(&Rec, &Rec + 1)); } // Introduce derived sets where necessary (when a register does not determine // a unique register set class), and build the mapping of registers to the set // they should classify to. - std::map<Record*, std::set<Record*> > RegisterMap; + std::map<Record*, RegisterSet> RegisterMap; for (std::vector<CodeGenRegister*>::const_iterator it = Registers.begin(), ie = Registers.end(); it != ie; ++it) { const CodeGenRegister &CGR = **it; // Compute the intersection of all sets containing this register. - std::set<Record*> ContainingSet; + RegisterSet ContainingSet; - for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(), + for (RegisterSetSet::iterator it = RegisterSets.begin(), ie = RegisterSets.end(); it != ie; ++it) { if (!it->count(CGR.TheDef)) continue; @@ -1087,11 +1122,12 @@ buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) { continue; } - std::set<Record*> Tmp; + RegisterSet Tmp; std::swap(Tmp, ContainingSet); - std::insert_iterator< std::set<Record*> > II(ContainingSet, - ContainingSet.begin()); - std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II); + std::insert_iterator<RegisterSet> II(ContainingSet, + ContainingSet.begin()); + std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II, + LessRecordByID()); } if (!ContainingSet.empty()) { @@ -1101,9 +1137,9 @@ buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) { } // Construct the register classes. - std::map<std::set<Record*>, ClassInfo*> RegisterSetClasses; + std::map<RegisterSet, ClassInfo*, LessRegisterSet> RegisterSetClasses; unsigned Index = 0; - for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(), + for (RegisterSetSet::iterator it = RegisterSets.begin(), ie = RegisterSets.end(); it != ie; ++it, ++Index) { ClassInfo *CI = new ClassInfo(); CI->Kind = ClassInfo::RegisterClass0 + Index; @@ -1121,13 +1157,14 @@ buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) { // Find the superclasses; we could compute only the subgroup lattice edges, // but there isn't really a point. - for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(), + for (RegisterSetSet::iterator it = RegisterSets.begin(), ie = RegisterSets.end(); it != ie; ++it) { ClassInfo *CI = RegisterSetClasses[*it]; - for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(), + for (RegisterSetSet::iterator it2 = RegisterSets.begin(), ie2 = RegisterSets.end(); it2 != ie2; ++it2) if (*it != *it2 && - std::includes(it2->begin(), it2->end(), it->begin(), it->end())) + std::includes(it2->begin(), it2->end(), it->begin(), it->end(), + LessRecordByID())) CI->SuperClasses.push_back(RegisterSetClasses[*it2]); } @@ -1139,8 +1176,8 @@ buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) { Record *Def = RC.getDef(); if (!Def) continue; - ClassInfo *CI = RegisterSetClasses[std::set<Record*>(RC.getOrder().begin(), - RC.getOrder().end())]; + ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(), + RC.getOrder().end())]; if (CI->ValueName.empty()) { CI->ClassName = RC.getName(); CI->Name = "MCK_" + RC.getName(); @@ -1152,7 +1189,7 @@ buildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) { } // Populate the map for individual registers. - for (std::map<Record*, std::set<Record*> >::iterator it = RegisterMap.begin(), + for (std::map<Record*, RegisterSet>::iterator it = RegisterMap.begin(), ie = RegisterMap.end(); it != ie; ++it) RegisterClasses[it->first] = RegisterSetClasses[it->second]; @@ -2066,9 +2103,12 @@ static void emitIsSubclass(CodeGenTarget &Target, OS << " if (A == B)\n"; OS << " return true;\n\n"; - OS << " switch (A) {\n"; - OS << " default:\n"; - OS << " return false;\n"; + std::string OStr; + raw_string_ostream SS(OStr); + unsigned Count = 0; + SS << " switch (A) {\n"; + SS << " default:\n"; + SS << " return false;\n"; for (std::vector<ClassInfo*>::iterator it = Infos.begin(), ie = Infos.end(); it != ie; ++it) { ClassInfo &A = **it; @@ -2084,21 +2124,35 @@ static void emitIsSubclass(CodeGenTarget &Target, if (SuperClasses.empty()) continue; + ++Count; - OS << "\n case " << A.Name << ":\n"; + SS << "\n case " << A.Name << ":\n"; if (SuperClasses.size() == 1) { - OS << " return B == " << SuperClasses.back() << ";\n"; + SS << " return B == " << SuperClasses.back().str() << ";\n"; continue; } - OS << " switch (B) {\n"; - OS << " default: return false;\n"; - for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i) - OS << " case " << SuperClasses[i] << ": return true;\n"; - OS << " }\n"; + if (!SuperClasses.empty()) { + SS << " switch (B) {\n"; + SS << " default: return false;\n"; + for (unsigned i = 0, e = SuperClasses.size(); i != e; ++i) + SS << " case " << SuperClasses[i].str() << ": return true;\n"; + SS << " }\n"; + } else { + // No case statement to emit + SS << " return false;\n"; + } } - OS << " }\n"; + SS << " }\n"; + + // If there were case statements emitted into the string stream, write them + // to the output stream, otherwise write the default. + if (Count) + OS << SS.str(); + else + OS << " return false;\n"; + OS << "}\n\n"; } @@ -2159,7 +2213,7 @@ static void emitSubtargetFeatureFlagEnumeration(AsmMatcherInfo &Info, OS << "// Flags for subtarget features that participate in " << "instruction matching.\n"; OS << "enum SubtargetFeatureFlag {\n"; - for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator + for (std::map<Record*, SubtargetFeatureInfo*, LessRecordByID>::const_iterator it = Info.SubtargetFeatures.begin(), ie = Info.SubtargetFeatures.end(); it != ie; ++it) { SubtargetFeatureInfo &SFI = *it->second; @@ -2194,18 +2248,24 @@ static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) { static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) { OS << "// User-level names for subtarget features that participate in\n" << "// instruction matching.\n" - << "static const char *getSubtargetFeatureName(unsigned Val) {\n" - << " switch(Val) {\n"; - for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator - it = Info.SubtargetFeatures.begin(), - ie = Info.SubtargetFeatures.end(); it != ie; ++it) { - SubtargetFeatureInfo &SFI = *it->second; - // FIXME: Totally just a placeholder name to get the algorithm working. - OS << " case " << SFI.getEnumName() << ": return \"" - << SFI.TheDef->getValueAsString("PredicateName") << "\";\n"; + << "static const char *getSubtargetFeatureName(unsigned Val) {\n"; + if (!Info.SubtargetFeatures.empty()) { + OS << " switch(Val) {\n"; + typedef std::map<Record*, SubtargetFeatureInfo*, LessRecordByID> RecFeatMap; + for (RecFeatMap::const_iterator it = Info.SubtargetFeatures.begin(), + ie = Info.SubtargetFeatures.end(); it != ie; ++it) { + SubtargetFeatureInfo &SFI = *it->second; + // FIXME: Totally just a placeholder name to get the algorithm working. + OS << " case " << SFI.getEnumName() << ": return \"" + << SFI.TheDef->getValueAsString("PredicateName") << "\";\n"; + } + OS << " default: return \"(unknown)\";\n"; + OS << " }\n"; + } else { + // Nothing to emit, so skip the switch + OS << " return \"(unknown)\";\n"; } - OS << " default: return \"(unknown)\";\n"; - OS << " }\n}\n\n"; + OS << "}\n\n"; } /// emitComputeAvailableFeatures - Emit the function to compute the list of @@ -2218,7 +2278,7 @@ static void emitComputeAvailableFeatures(AsmMatcherInfo &Info, OS << "unsigned " << Info.Target.getName() << ClassName << "::\n" << "ComputeAvailableFeatures(uint64_t FB) const {\n"; OS << " unsigned Features = 0;\n"; - for (std::map<Record*, SubtargetFeatureInfo*>::const_iterator + for (std::map<Record*, SubtargetFeatureInfo*, LessRecordByID>::const_iterator it = Info.SubtargetFeatures.begin(), ie = Info.SubtargetFeatures.end(); it != ie; ++it) { SubtargetFeatureInfo &SFI = *it->second; @@ -2303,7 +2363,7 @@ static void emitMnemonicAliasVariant(raw_ostream &OS,const AsmMatcherInfo &Info, } if (AliasesFromMnemonic.empty()) return; - + // Process each alias a "from" mnemonic at a time, building the code executed // by the string remapper. std::vector<StringMatcher::StringPair> Cases; @@ -2632,7 +2692,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { << "&Operands);\n"; OS << " void convertToMapAndConstraints(unsigned Kind,\n "; OS << " const SmallVectorImpl<MCParsedAsmOperand*> &Operands);\n"; - OS << " bool mnemonicIsValid(StringRef Mnemonic);\n"; + OS << " bool mnemonicIsValid(StringRef Mnemonic, unsigned VariantID);\n"; OS << " unsigned MatchInstructionImpl(\n"; OS.indent(27); OS << "const SmallVectorImpl<MCParsedAsmOperand*> &Operands,\n" @@ -2717,11 +2777,13 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { size_t MaxNumOperands = 0; unsigned MaxMnemonicIndex = 0; + bool HasDeprecation = false; for (std::vector<MatchableInfo*>::const_iterator it = Info.Matchables.begin(), ie = Info.Matchables.end(); it != ie; ++it) { MatchableInfo &II = **it; MaxNumOperands = std::max(MaxNumOperands, II.AsmOperands.size()); + HasDeprecation |= II.HasDeprecation; // Store a pascal-style length byte in the mnemonic. std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str(); @@ -2754,7 +2816,6 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { << " RequiredFeatures;\n"; OS << " " << getMinimalTypeForRange(Info.Classes.size()) << " Classes[" << MaxNumOperands << "];\n"; - OS << " uint8_t AsmVariantID;\n\n"; OS << " StringRef getMnemonic() const {\n"; OS << " return StringRef(MnemonicTable + Mnemonic + 1,\n"; OS << " MnemonicTable[Mnemonic]);\n"; @@ -2776,51 +2837,67 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { OS << "} // end anonymous namespace.\n\n"; - OS << "static const MatchEntry MatchTable[" - << Info.Matchables.size() << "] = {\n"; + unsigned VariantCount = Target.getAsmParserVariantCount(); + for (unsigned VC = 0; VC != VariantCount; ++VC) { + Record *AsmVariant = Target.getAsmParserVariant(VC); + int AsmVariantNo = AsmVariant->getValueAsInt("Variant"); - for (std::vector<MatchableInfo*>::const_iterator it = - Info.Matchables.begin(), ie = Info.Matchables.end(); - it != ie; ++it) { - MatchableInfo &II = **it; + OS << "static const MatchEntry MatchTable" << VC << "[] = {\n"; - // Store a pascal-style length byte in the mnemonic. - std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str(); - OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false) - << " /* " << II.Mnemonic << " */, " - << Target.getName() << "::" - << II.getResultInst()->TheDef->getName() << ", " - << II.ConversionFnKind << ", "; + for (std::vector<MatchableInfo*>::const_iterator it = + Info.Matchables.begin(), ie = Info.Matchables.end(); + it != ie; ++it) { + MatchableInfo &II = **it; + if (II.AsmVariantID != AsmVariantNo) + continue; - // Write the required features mask. - if (!II.RequiredFeatures.empty()) { - for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) { - if (i) OS << "|"; - OS << II.RequiredFeatures[i]->getEnumName(); - } - } else - OS << "0"; + // Store a pascal-style length byte in the mnemonic. + std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str(); + OS << " { " << StringTable.GetOrAddStringOffset(LenMnemonic, false) + << " /* " << II.Mnemonic << " */, " + << Target.getName() << "::" + << II.getResultInst()->TheDef->getName() << ", " + << II.ConversionFnKind << ", "; + + // Write the required features mask. + if (!II.RequiredFeatures.empty()) { + for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) { + if (i) OS << "|"; + OS << II.RequiredFeatures[i]->getEnumName(); + } + } else + OS << "0"; - OS << ", { "; - for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) { - MatchableInfo::AsmOperand &Op = II.AsmOperands[i]; + OS << ", { "; + for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) { + MatchableInfo::AsmOperand &Op = II.AsmOperands[i]; - if (i) OS << ", "; - OS << Op.Class->Name; + if (i) OS << ", "; + OS << Op.Class->Name; + } + OS << " }, },\n"; } - OS << " }, " << II.AsmVariantID; - OS << "},\n"; - } - OS << "};\n\n"; + OS << "};\n\n"; + } // A method to determine if a mnemonic is in the list. OS << "bool " << Target.getName() << ClassName << "::\n" - << "mnemonicIsValid(StringRef Mnemonic) {\n"; + << "mnemonicIsValid(StringRef Mnemonic, unsigned VariantID) {\n"; + OS << " // Find the appropriate table for this asm variant.\n"; + OS << " const MatchEntry *Start, *End;\n"; + OS << " switch (VariantID) {\n"; + OS << " default: // unreachable\n"; + for (unsigned VC = 0; VC != VariantCount; ++VC) { + Record *AsmVariant = Target.getAsmParserVariant(VC); + int AsmVariantNo = AsmVariant->getValueAsInt("Variant"); + OS << " case " << AsmVariantNo << ": Start = MatchTable" << VC + << "; End = array_endof(MatchTable" << VC << "); break;\n"; + } + OS << " }\n"; OS << " // Search the table.\n"; OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n"; - OS << " std::equal_range(MatchTable, MatchTable+" - << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n"; + OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n"; OS << " return MnemonicRange.first != MnemonicRange.second;\n"; OS << "}\n\n"; @@ -2862,10 +2939,20 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { OS << " ErrorInfo = ~0U;\n"; // Emit code to search the table. + OS << " // Find the appropriate table for this asm variant.\n"; + OS << " const MatchEntry *Start, *End;\n"; + OS << " switch (VariantID) {\n"; + OS << " default: // unreachable\n"; + for (unsigned VC = 0; VC != VariantCount; ++VC) { + Record *AsmVariant = Target.getAsmParserVariant(VC); + int AsmVariantNo = AsmVariant->getValueAsInt("Variant"); + OS << " case " << AsmVariantNo << ": Start = MatchTable" << VC + << "; End = array_endof(MatchTable" << VC << "); break;\n"; + } + OS << " }\n"; OS << " // Search the table.\n"; OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n"; - OS << " std::equal_range(MatchTable, MatchTable+" - << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n"; + OS << " std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n"; OS << " // Return a more specific error code if no mnemonics match.\n"; OS << " if (MnemonicRange.first == MnemonicRange.second)\n"; @@ -2879,7 +2966,6 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { OS << " assert(Mnemonic == it->getMnemonic());\n"; // Emit check that the subclasses match. - OS << " if (VariantID != it->AsmVariantID) continue;\n"; OS << " bool OperandsValid = true;\n"; OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n"; OS << " if (i + 1 >= Operands.size()) {\n"; @@ -2959,6 +3045,14 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { if (!InsnCleanupFn.empty()) OS << " " << InsnCleanupFn << "(Inst);\n"; + if (HasDeprecation) { + OS << " std::string Info;\n"; + OS << " if (MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, STI, Info)) {\n"; + OS << " SMLoc Loc = ((" << Target.getName() << "Operand*)Operands[0])->getStartLoc();\n"; + OS << " Parser.Warning(Loc, Info, None);\n"; + OS << " }\n"; + } + OS << " return Match_Success;\n"; OS << " }\n\n"; diff --git a/contrib/llvm/utils/TableGen/AsmWriterEmitter.cpp b/contrib/llvm/utils/TableGen/AsmWriterEmitter.cpp index ac8d896..a18b6b5 100644 --- a/contrib/llvm/utils/TableGen/AsmWriterEmitter.cpp +++ b/contrib/llvm/utils/TableGen/AsmWriterEmitter.cpp @@ -18,6 +18,7 @@ #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/Twine.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/Format.h" #include "llvm/Support/MathExtras.h" #include "llvm/TableGen/Error.h" #include "llvm/TableGen/Record.h" @@ -31,10 +32,12 @@ using namespace llvm; namespace { class AsmWriterEmitter { RecordKeeper &Records; + CodeGenTarget Target; std::map<const CodeGenInstruction*, AsmWriterInst*> CGIAWIMap; std::vector<const CodeGenInstruction*> NumberedInstructions; + std::vector<AsmWriterInst> Instructions; public: - AsmWriterEmitter(RecordKeeper &R) : Records(R) {} + AsmWriterEmitter(RecordKeeper &R); void run(raw_ostream &o); @@ -272,9 +275,9 @@ static void UnescapeString(std::string &Str) { } /// EmitPrintInstruction - Generate the code for the "printInstruction" method -/// implementation. +/// implementation. Destroys all instances of AsmWriterInst information, by +/// clearing the Instructions vector. void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { - CodeGenTarget Target(Records); Record *AsmWriter = Target.getAsmWriter(); std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); bool isMC = AsmWriter->getValueAsBit("isMCAsmWriter"); @@ -287,27 +290,6 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { << "::printInstruction(const " << MachineInstrClassName << " *MI, raw_ostream &O) {\n"; - std::vector<AsmWriterInst> Instructions; - - for (CodeGenTarget::inst_iterator I = Target.inst_begin(), - E = Target.inst_end(); I != E; ++I) - if (!(*I)->AsmString.empty() && - (*I)->TheDef->getName() != "PHI") - Instructions.push_back( - AsmWriterInst(**I, - AsmWriter->getValueAsInt("Variant"), - AsmWriter->getValueAsInt("FirstOperandColumn"), - AsmWriter->getValueAsInt("OperandSpacing"))); - - // Get the instruction numbering. - NumberedInstructions = Target.getInstructionsByEnumValue(); - - // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not - // all machine instructions are necessarily being printed, so there may be - // target instructions not in this map. - for (unsigned i = 0, e = Instructions.size(); i != e; ++i) - CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i])); - // Build an aggregate string, and build a table of offsets into it. SequenceToOffsetTable<std::string> StringTable; @@ -591,7 +573,6 @@ emitRegisterNameString(raw_ostream &O, StringRef AltName, } void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { - CodeGenTarget Target(Records); Record *AsmWriter = Target.getAsmWriter(); std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); const std::vector<CodeGenRegister*> &Registers = @@ -657,7 +638,10 @@ public: void addCond(const std::string &C) { Conds.push_back(C); } - void addOperand(StringRef Op, unsigned Idx) { OpMap[Op] = Idx; } + void addOperand(StringRef Op, unsigned Idx) { + assert(Idx < 0xFF && "Index too large!"); + OpMap[Op] = Idx; + } unsigned getOpIndex(StringRef Op) { return OpMap[Op]; } bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); } @@ -681,12 +665,35 @@ public: O << ") {\n"; O.indent(6) << "// " << Result << "\n"; - O.indent(6) << "AsmString = \"" << AsmString << "\";\n"; - for (std::map<StringRef, unsigned>::iterator - I = OpMap.begin(), E = OpMap.end(); I != E; ++I) - O.indent(6) << "OpMap.push_back(std::make_pair(\"" << I->first << "\", " - << I->second << "));\n"; + // Directly mangle mapped operands into the string. Each operand is + // identified by a '$' sign followed by a byte identifying the number of the + // operand. We add one to the index to avoid zero bytes. + std::pair<StringRef, StringRef> ASM = StringRef(AsmString).split(' '); + SmallString<128> OutString = ASM.first; + if (!ASM.second.empty()) { + raw_svector_ostream OS(OutString); + OS << ' '; + for (StringRef::iterator I = ASM.second.begin(), E = ASM.second.end(); + I != E;) { + OS << *I; + if (*I == '$') { + StringRef::iterator Start = ++I; + while (I != E && + ((*I >= 'a' && *I <= 'z') || (*I >= 'A' && *I <= 'Z') || + (*I >= '0' && *I <= '9') || *I == '_')) + ++I; + StringRef Name(Start, I - Start); + assert(isOpMapped(Name) && "Unmapped operand!"); + OS << format("\\x%02X", (unsigned char)getOpIndex(Name) + 1); + } else { + ++I; + } + } + } + + // Emit the string. + O.indent(6) << "AsmString = \"" << OutString.str() << "\";\n"; O.indent(6) << "break;\n"; O.indent(4) << '}'; @@ -721,19 +728,6 @@ public: } // end anonymous namespace -static void EmitGetMapOperandNumber(raw_ostream &O) { - O << "static unsigned getMapOperandNumber(" - << "const SmallVectorImpl<std::pair<StringRef, unsigned> > &OpMap,\n"; - O << " StringRef Name) {\n"; - O << " for (SmallVectorImpl<std::pair<StringRef, unsigned> >::" - << "const_iterator\n"; - O << " I = OpMap.begin(), E = OpMap.end(); I != E; ++I)\n"; - O << " if (I->first == Name)\n"; - O << " return I->second;\n"; - O << " llvm_unreachable(\"Operand not in map!\");\n"; - O << "}\n\n"; -} - static unsigned CountNumOperands(StringRef AsmString) { unsigned NumOps = 0; std::pair<StringRef, StringRef> ASM = AsmString.split(' '); @@ -768,7 +762,6 @@ static unsigned CountResultNumOperands(StringRef AsmString) { } void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { - CodeGenTarget Target(Records); Record *AsmWriter = Target.getAsmWriter(); if (!AsmWriter->getValueAsBit("isMCAsmWriter")) @@ -822,7 +815,6 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(LastOpNo); IAP->addCond(Cond); - std::map<StringRef, unsigned> OpMap; bool CantHandle = false; for (unsigned i = 0, e = LastOpNo; i != e; ++i) { @@ -955,11 +947,8 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { return; } - EmitGetMapOperandNumber(O); - O << HeaderO.str(); - O.indent(2) << "StringRef AsmString;\n"; - O.indent(2) << "SmallVector<std::pair<StringRef, unsigned>, 4> OpMap;\n"; + O.indent(2) << "const char *AsmString;\n"; O.indent(2) << "switch (MI->getOpcode()) {\n"; O.indent(2) << "default: return false;\n"; O << CasesO.str(); @@ -967,27 +956,21 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { // Code that prints the alias, replacing the operands with the ones from the // MCInst. - O << " std::pair<StringRef, StringRef> ASM = AsmString.split(' ');\n"; - O << " OS << '\\t' << ASM.first;\n"; + O << " unsigned I = 0;\n"; + O << " while (AsmString[I] != ' ' && AsmString[I] != '\\0')\n"; + O << " ++I;\n"; + O << " OS << '\\t' << StringRef(AsmString, I);\n"; - O << " if (!ASM.second.empty()) {\n"; + O << " if (AsmString[I] != '\\0') {\n"; O << " OS << '\\t';\n"; - O << " for (StringRef::iterator\n"; - O << " I = ASM.second.begin(), E = ASM.second.end(); I != E; ) {\n"; - O << " if (*I == '$') {\n"; - O << " StringRef::iterator Start = ++I;\n"; - O << " while (I != E &&\n"; - O << " ((*I >= 'a' && *I <= 'z') ||\n"; - O << " (*I >= 'A' && *I <= 'Z') ||\n"; - O << " (*I >= '0' && *I <= '9') ||\n"; - O << " *I == '_'))\n"; - O << " ++I;\n"; - O << " StringRef Name(Start, I - Start);\n"; - O << " printOperand(MI, getMapOperandNumber(OpMap, Name), OS);\n"; + O << " do {\n"; + O << " if (AsmString[I] == '$') {\n"; + O << " ++I;\n"; + O << " printOperand(MI, unsigned(AsmString[I++]) - 1, OS);\n"; O << " } else {\n"; - O << " OS << *I++;\n"; + O << " OS << AsmString[I++];\n"; O << " }\n"; - O << " }\n"; + O << " } while (AsmString[I] != '\\0');\n"; O << " }\n\n"; O << " return true;\n"; @@ -996,6 +979,27 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { O << "#endif // PRINT_ALIAS_INSTR\n"; } +AsmWriterEmitter::AsmWriterEmitter(RecordKeeper &R) : Records(R), Target(R) { + Record *AsmWriter = Target.getAsmWriter(); + for (CodeGenTarget::inst_iterator I = Target.inst_begin(), + E = Target.inst_end(); + I != E; ++I) + if (!(*I)->AsmString.empty() && (*I)->TheDef->getName() != "PHI") + Instructions.push_back( + AsmWriterInst(**I, AsmWriter->getValueAsInt("Variant"), + AsmWriter->getValueAsInt("FirstOperandColumn"), + AsmWriter->getValueAsInt("OperandSpacing"))); + + // Get the instruction numbering. + NumberedInstructions = Target.getInstructionsByEnumValue(); + + // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not + // all machine instructions are necessarily being printed, so there may be + // target instructions not in this map. + for (unsigned i = 0, e = Instructions.size(); i != e; ++i) + CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i])); +} + void AsmWriterEmitter::run(raw_ostream &O) { EmitPrintInstruction(O); EmitGetRegisterName(O); diff --git a/contrib/llvm/utils/TableGen/AsmWriterInst.cpp b/contrib/llvm/utils/TableGen/AsmWriterInst.cpp index fe1f756..1c2004f6 100644 --- a/contrib/llvm/utils/TableGen/AsmWriterInst.cpp +++ b/contrib/llvm/utils/TableGen/AsmWriterInst.cpp @@ -32,10 +32,10 @@ std::string AsmWriterOperand::getCode() const { return "O << '" + Str + "'; "; return "O << \"" + Str + "\"; "; } - + if (OperandType == isLiteralStatementOperand) return Str; - + std::string Result = Str + "(MI"; if (MIOpNo != ~0U) Result += ", " + utostr(MIOpNo); @@ -53,12 +53,12 @@ AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, int FirstOperandColumn, int OperandSpacing) { this->CGI = &CGI; - + // This is the number of tabs we've seen if we're doing columnar layout. unsigned CurColumn = 0; - - - // NOTE: Any extensions to this code need to be mirrored in the + + + // NOTE: Any extensions to this code need to be mirrored in the // AsmPrinter::printInlineAsm code that executes as compile time (assuming // that inline asm strings should also get the new feature)! std::string AsmString = CGI.FlattenAsmStringVariants(CGI.AsmString, Variant); @@ -67,7 +67,7 @@ AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, std::string::size_type DollarPos = AsmString.find_first_of("$\\", LastEmitted); if (DollarPos == std::string::npos) DollarPos = AsmString.size(); - + // Emit a constant string fragment. if (DollarPos != LastEmitted) { for (; LastEmitted != DollarPos; ++LastEmitted) @@ -82,7 +82,7 @@ AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, AddLiteralString("\\t"); } else { // We recognize a tab as an operand delimeter. - unsigned DestColumn = FirstOperandColumn + + unsigned DestColumn = FirstOperandColumn + CurColumn++ * OperandSpacing; Operands.push_back( AsmWriterOperand( @@ -112,15 +112,15 @@ AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, AddLiteralString("\\t"); break; } - + // We recognize a tab as an operand delimeter. - unsigned DestColumn = FirstOperandColumn + + unsigned DestColumn = FirstOperandColumn + CurColumn++ * OperandSpacing; Operands.push_back( AsmWriterOperand("O.PadToColumn(" + utostr(DestColumn) + ");\n", AsmWriterOperand::isLiteralStatementOperand)); break; - } else if (std::string("${|}\\").find(AsmString[DollarPos+1]) + } else if (std::string("${|}\\").find(AsmString[DollarPos+1]) != std::string::npos) { AddLiteralString(std::string(1, AsmString[DollarPos+1])); } else { @@ -137,7 +137,7 @@ AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, } else { // Get the name of the variable. std::string::size_type VarEnd = DollarPos+1; - + // handle ${foo}bar as $foo by detecting whether the character following // the dollar sign is a curly brace. If so, advance VarEnd and DollarPos // so the variable name does not contain the leading curly brace. @@ -147,17 +147,17 @@ AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, ++DollarPos; ++VarEnd; } - + while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd])) ++VarEnd; std::string VarName(AsmString.begin()+DollarPos+1, AsmString.begin()+VarEnd); - + // Modifier - Support ${foo:modifier} syntax, where "modifier" is passed // into printOperand. Also support ${:feature}, which is passed into // PrintSpecial. std::string Modifier; - + // In order to avoid starting the next string at the terminating curly // brace, advance the end position past it if we found an opening curly // brace. @@ -165,14 +165,14 @@ AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, if (VarEnd >= AsmString.size()) PrintFatalError("Reached end of string before terminating curly brace in '" + CGI.TheDef->getName() + "'"); - + // Look for a modifier string. if (AsmString[VarEnd] == ':') { ++VarEnd; if (VarEnd >= AsmString.size()) PrintFatalError("Reached end of string before terminating curly brace in '" + CGI.TheDef->getName() + "'"); - + unsigned ModifierStart = VarEnd; while (VarEnd < AsmString.size() && isIdentChar(AsmString[VarEnd])) ++VarEnd; @@ -181,7 +181,7 @@ AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, if (Modifier.empty()) PrintFatalError("Bad operand modifier name in '"+ CGI.TheDef->getName() + "'"); } - + if (AsmString[VarEnd] != '}') PrintFatalError("Variable name beginning with '{' did not end with '}' in '" + CGI.TheDef->getName() + "'"); @@ -190,26 +190,26 @@ AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, if (VarName.empty() && Modifier.empty()) PrintFatalError("Stray '$' in '" + CGI.TheDef->getName() + "' asm string, maybe you want $$?"); - + if (VarName.empty()) { // Just a modifier, pass this into PrintSpecial. - Operands.push_back(AsmWriterOperand("PrintSpecial", - ~0U, - ~0U, + Operands.push_back(AsmWriterOperand("PrintSpecial", + ~0U, + ~0U, Modifier)); } else { // Otherwise, normal operand. unsigned OpNo = CGI.Operands.getOperandNamed(VarName); CGIOperandList::OperandInfo OpInfo = CGI.Operands[OpNo]; - + unsigned MIOp = OpInfo.MIOperandNo; - Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName, + Operands.push_back(AsmWriterOperand(OpInfo.PrinterMethodName, OpNo, MIOp, Modifier)); } LastEmitted = VarEnd; } } - + Operands.push_back(AsmWriterOperand("return;", AsmWriterOperand::isLiteralStatementOperand)); } @@ -220,14 +220,13 @@ AsmWriterInst::AsmWriterInst(const CodeGenInstruction &CGI, /// if the instructions are identical return ~0. unsigned AsmWriterInst::MatchesAllButOneOp(const AsmWriterInst &Other)const{ if (Operands.size() != Other.Operands.size()) return ~1; - + unsigned MismatchOperand = ~0U; for (unsigned i = 0, e = Operands.size(); i != e; ++i) { if (Operands[i] != Other.Operands[i]) { if (MismatchOperand != ~0U) // Already have one mismatch? return ~1U; - else - MismatchOperand = i; + MismatchOperand = i; } } return MismatchOperand; diff --git a/contrib/llvm/utils/TableGen/CodeGenDAGPatterns.cpp b/contrib/llvm/utils/TableGen/CodeGenDAGPatterns.cpp index 8e5bb77..717090a 100644 --- a/contrib/llvm/utils/TableGen/CodeGenDAGPatterns.cpp +++ b/contrib/llvm/utils/TableGen/CodeGenDAGPatterns.cpp @@ -30,16 +30,16 @@ using namespace llvm; //===----------------------------------------------------------------------===// static inline bool isInteger(MVT::SimpleValueType VT) { - return EVT(VT).isInteger(); + return MVT(VT).isInteger(); } static inline bool isFloatingPoint(MVT::SimpleValueType VT) { - return EVT(VT).isFloatingPoint(); + return MVT(VT).isFloatingPoint(); } static inline bool isVector(MVT::SimpleValueType VT) { - return EVT(VT).isVector(); + return MVT(VT).isVector(); } static inline bool isScalar(MVT::SimpleValueType VT) { - return !EVT(VT).isVector(); + return !MVT(VT).isVector(); } EEVT::TypeSet::TypeSet(MVT::SimpleValueType VT, TreePattern &TP) { @@ -385,8 +385,8 @@ bool EEVT::TypeSet::EnforceSmallerThan(EEVT::TypeSet &Other, TreePattern &TP) { // Otherwise, if these are both vector types, either this vector // must have a larger bitsize than the other, or this element type // must be larger than the other. - EVT Type(TypeVec[0]); - EVT OtherType(Other.TypeVec[0]); + MVT Type(TypeVec[0]); + MVT OtherType(Other.TypeVec[0]); if (hasVectorTypes() && Other.hasVectorTypes()) { if (Type.getSizeInBits() >= OtherType.getSizeInBits()) @@ -397,8 +397,7 @@ bool EEVT::TypeSet::EnforceSmallerThan(EEVT::TypeSet &Other, TreePattern &TP) { Other.getName() +"'!"); return false; } - } - else + } else // For scalar types, the bitsize of this type must be larger // than that of the other. if (Type.getSizeInBits() >= OtherType.getSizeInBits()) { @@ -438,7 +437,7 @@ bool EEVT::TypeSet::EnforceSmallerThan(EEVT::TypeSet &Other, TreePattern &TP) { int OtherIntSize = 0; int OtherFPSize = 0; - for (SmallVector<MVT::SimpleValueType, 2>::iterator TVI = + for (SmallVectorImpl<MVT::SimpleValueType>::iterator TVI = Other.TypeVec.begin(); TVI != Other.TypeVec.end(); /* NULL */) { @@ -450,8 +449,7 @@ bool EEVT::TypeSet::EnforceSmallerThan(EEVT::TypeSet &Other, TreePattern &TP) { MadeChange = true; continue; } - } - else if (isFloatingPoint(*TVI)) { + } else if (isFloatingPoint(*TVI)) { ++OtherFPSize; if (*TVI == SmallestFP) { TVI = Other.TypeVec.erase(TVI); @@ -465,8 +463,8 @@ bool EEVT::TypeSet::EnforceSmallerThan(EEVT::TypeSet &Other, TreePattern &TP) { // If this is the only type in the large set, the constraint can never be // satisfied. - if ((Other.hasIntegerTypes() && OtherIntSize == 0) - || (Other.hasFloatingPointTypes() && OtherFPSize == 0)) { + if ((Other.hasIntegerTypes() && OtherIntSize == 0) || + (Other.hasFloatingPointTypes() && OtherFPSize == 0)) { TP.error("Type inference contradiction found, '" + Other.getName() + "' has nothing larger than '" + getName() +"'!"); return false; @@ -496,7 +494,7 @@ bool EEVT::TypeSet::EnforceSmallerThan(EEVT::TypeSet &Other, TreePattern &TP) { int IntSize = 0; int FPSize = 0; - for (SmallVector<MVT::SimpleValueType, 2>::iterator TVI = + for (SmallVectorImpl<MVT::SimpleValueType>::iterator TVI = TypeVec.begin(); TVI != TypeVec.end(); /* NULL */) { @@ -508,8 +506,7 @@ bool EEVT::TypeSet::EnforceSmallerThan(EEVT::TypeSet &Other, TreePattern &TP) { MadeChange = true; continue; } - } - else if (isFloatingPoint(*TVI)) { + } else if (isFloatingPoint(*TVI)) { ++FPSize; if (*TVI == LargestFP) { TVI = TypeVec.erase(TVI); @@ -523,8 +520,8 @@ bool EEVT::TypeSet::EnforceSmallerThan(EEVT::TypeSet &Other, TreePattern &TP) { // If this is the only type in the small set, the constraint can never be // satisfied. - if ((hasIntegerTypes() && IntSize == 0) - || (hasFloatingPointTypes() && FPSize == 0)) { + if ((hasIntegerTypes() && IntSize == 0) || + (hasFloatingPointTypes() && FPSize == 0)) { TP.error("Type inference contradiction found, '" + getName() + "' has nothing smaller than '" + Other.getName()+"'!"); return false; @@ -547,10 +544,10 @@ bool EEVT::TypeSet::EnforceVectorEltTypeIs(EEVT::TypeSet &VTOperand, // If we know the vector type, it forces the scalar to agree. if (isConcrete()) { - EVT IVT = getConcrete(); + MVT IVT = getConcrete(); IVT = IVT.getVectorElementType(); return MadeChange | - VTOperand.MergeInTypeInfo(IVT.getSimpleVT().SimpleTy, TP); + VTOperand.MergeInTypeInfo(IVT.SimpleTy, TP); } // If the scalar type is known, filter out vector types whose element types @@ -565,7 +562,7 @@ bool EEVT::TypeSet::EnforceVectorEltTypeIs(EEVT::TypeSet &VTOperand, // Filter out all the types which don't have the right element type. for (unsigned i = 0; i != TypeVec.size(); ++i) { assert(isVector(TypeVec[i]) && "EnforceVector didn't work"); - if (EVT(TypeVec[i]).getVectorElementType().getSimpleVT().SimpleTy != VT) { + if (MVT(TypeVec[i]).getVectorElementType().SimpleTy != VT) { TypeVec.erase(TypeVec.begin()+i--); MadeChange = true; } @@ -593,16 +590,16 @@ bool EEVT::TypeSet::EnforceVectorSubVectorTypeIs(EEVT::TypeSet &VTOperand, // If we know the vector type, it forces the scalar types to agree. if (isConcrete()) { - EVT IVT = getConcrete(); + MVT IVT = getConcrete(); IVT = IVT.getVectorElementType(); - EEVT::TypeSet EltTypeSet(IVT.getSimpleVT().SimpleTy, TP); + EEVT::TypeSet EltTypeSet(IVT.SimpleTy, TP); MadeChange |= VTOperand.EnforceVectorEltTypeIs(EltTypeSet, TP); } else if (VTOperand.isConcrete()) { - EVT IVT = VTOperand.getConcrete(); + MVT IVT = VTOperand.getConcrete(); IVT = IVT.getVectorElementType(); - EEVT::TypeSet EltTypeSet(IVT.getSimpleVT().SimpleTy, TP); + EEVT::TypeSet EltTypeSet(IVT.SimpleTy, TP); MadeChange |= EnforceVectorEltTypeIs(EltTypeSet, TP); } @@ -1522,7 +1519,7 @@ bool TreePatternNode::ApplyTypeConstraints(TreePattern &TP, bool NotRegisters) { if (VT == MVT::iPTR || VT == MVT::iPTRAny) return MadeChange; - unsigned Size = EVT(VT).getSizeInBits(); + unsigned Size = MVT(VT).getSizeInBits(); // Make sure that the value is representable for this type. if (Size >= 32) return MadeChange; @@ -2678,54 +2675,13 @@ static bool checkOperandClass(CGIOperandList::OperandInfo &OI, return false; } -/// ParseInstructions - Parse all of the instructions, inlining and resolving -/// any fragments involved. This populates the Instructions list with fully -/// resolved instructions. -void CodeGenDAGPatterns::ParseInstructions() { - std::vector<Record*> Instrs = Records.getAllDerivedDefinitions("Instruction"); - - for (unsigned i = 0, e = Instrs.size(); i != e; ++i) { - ListInit *LI = 0; +const DAGInstruction &CodeGenDAGPatterns::parseInstructionPattern( + CodeGenInstruction &CGI, ListInit *Pat, DAGInstMap &DAGInsts) { - if (isa<ListInit>(Instrs[i]->getValueInit("Pattern"))) - LI = Instrs[i]->getValueAsListInit("Pattern"); - - // If there is no pattern, only collect minimal information about the - // instruction for its operand list. We have to assume that there is one - // result, as we have no detailed info. A pattern which references the - // null_frag operator is as-if no pattern were specified. Normally this - // is from a multiclass expansion w/ a SDPatternOperator passed in as - // null_frag. - if (!LI || LI->getSize() == 0 || hasNullFragReference(LI)) { - std::vector<Record*> Results; - std::vector<Record*> Operands; - - CodeGenInstruction &InstInfo = Target.getInstruction(Instrs[i]); - - if (InstInfo.Operands.size() != 0) { - if (InstInfo.Operands.NumDefs == 0) { - // These produce no results - for (unsigned j = 0, e = InstInfo.Operands.size(); j < e; ++j) - Operands.push_back(InstInfo.Operands[j].Rec); - } else { - // Assume the first operand is the result. - Results.push_back(InstInfo.Operands[0].Rec); - - // The rest are inputs. - for (unsigned j = 1, e = InstInfo.Operands.size(); j < e; ++j) - Operands.push_back(InstInfo.Operands[j].Rec); - } - } - - // Create and insert the instruction. - std::vector<Record*> ImpResults; - Instructions.insert(std::make_pair(Instrs[i], - DAGInstruction(0, Results, Operands, ImpResults))); - continue; // no pattern. - } + assert(!DAGInsts.count(CGI.TheDef) && "Instruction already parsed!"); // Parse the instruction. - TreePattern *I = new TreePattern(Instrs[i], LI, true, *this); + TreePattern *I = new TreePattern(CGI.TheDef, Pat, true, *this); // Inline pattern fragments into it. I->InlinePatternFragments(); @@ -2764,7 +2720,6 @@ void CodeGenDAGPatterns::ParseInstructions() { // Parse the operands list from the (ops) list, validating it. assert(I->getArgList().empty() && "Args list should still be empty here!"); - CodeGenInstruction &CGI = Target.getInstruction(Instrs[i]); // Check that all of the results occur first in the list. std::vector<Record*> Results; @@ -2863,18 +2818,71 @@ void CodeGenDAGPatterns::ParseInstructions() { // Create and insert the instruction. // FIXME: InstImpResults should not be part of DAGInstruction. DAGInstruction TheInst(I, Results, Operands, InstImpResults); - Instructions.insert(std::make_pair(I->getRecord(), TheInst)); + DAGInsts.insert(std::make_pair(I->getRecord(), TheInst)); // Use a temporary tree pattern to infer all types and make sure that the // constructed result is correct. This depends on the instruction already - // being inserted into the Instructions map. + // being inserted into the DAGInsts map. TreePattern Temp(I->getRecord(), ResultPattern, false, *this); Temp.InferAllTypes(&I->getNamedNodesMap()); - DAGInstruction &TheInsertedInst = Instructions.find(I->getRecord())->second; + DAGInstruction &TheInsertedInst = DAGInsts.find(I->getRecord())->second; TheInsertedInst.setResultPattern(Temp.getOnlyTree()); - DEBUG(I->dump()); + return TheInsertedInst; + } + +/// ParseInstructions - Parse all of the instructions, inlining and resolving +/// any fragments involved. This populates the Instructions list with fully +/// resolved instructions. +void CodeGenDAGPatterns::ParseInstructions() { + std::vector<Record*> Instrs = Records.getAllDerivedDefinitions("Instruction"); + + for (unsigned i = 0, e = Instrs.size(); i != e; ++i) { + ListInit *LI = 0; + + if (isa<ListInit>(Instrs[i]->getValueInit("Pattern"))) + LI = Instrs[i]->getValueAsListInit("Pattern"); + + // If there is no pattern, only collect minimal information about the + // instruction for its operand list. We have to assume that there is one + // result, as we have no detailed info. A pattern which references the + // null_frag operator is as-if no pattern were specified. Normally this + // is from a multiclass expansion w/ a SDPatternOperator passed in as + // null_frag. + if (!LI || LI->getSize() == 0 || hasNullFragReference(LI)) { + std::vector<Record*> Results; + std::vector<Record*> Operands; + + CodeGenInstruction &InstInfo = Target.getInstruction(Instrs[i]); + + if (InstInfo.Operands.size() != 0) { + if (InstInfo.Operands.NumDefs == 0) { + // These produce no results + for (unsigned j = 0, e = InstInfo.Operands.size(); j < e; ++j) + Operands.push_back(InstInfo.Operands[j].Rec); + } else { + // Assume the first operand is the result. + Results.push_back(InstInfo.Operands[0].Rec); + + // The rest are inputs. + for (unsigned j = 1, e = InstInfo.Operands.size(); j < e; ++j) + Operands.push_back(InstInfo.Operands[j].Rec); + } + } + + // Create and insert the instruction. + std::vector<Record*> ImpResults; + Instructions.insert(std::make_pair(Instrs[i], + DAGInstruction(0, Results, Operands, ImpResults))); + continue; // no pattern. + } + + CodeGenInstruction &CGI = Target.getInstruction(Instrs[i]); + const DAGInstruction &DI = parseInstructionPattern(CGI, LI, Instructions); + + (void)DI; + DEBUG(DI.getPattern()->dump()); } // If we can, convert the instructions to be patterns that are matched! diff --git a/contrib/llvm/utils/TableGen/CodeGenDAGPatterns.h b/contrib/llvm/utils/TableGen/CodeGenDAGPatterns.h index 7c2fa36..6fbdd4f 100644 --- a/contrib/llvm/utils/TableGen/CodeGenDAGPatterns.h +++ b/contrib/llvm/utils/TableGen/CodeGenDAGPatterns.h @@ -778,7 +778,11 @@ public: ptm_iterator ptm_begin() const { return PatternsToMatch.begin(); } ptm_iterator ptm_end() const { return PatternsToMatch.end(); } - + /// Parse the Pattern for an instruction, and insert the result in DAGInsts. + typedef std::map<Record*, DAGInstruction, LessRecordByID> DAGInstMap; + const DAGInstruction &parseInstructionPattern( + CodeGenInstruction &CGI, ListInit *Pattern, + DAGInstMap &DAGInsts); const DAGInstruction &getInstruction(Record *R) const { assert(Instructions.count(R) && "Unknown instruction!"); diff --git a/contrib/llvm/utils/TableGen/CodeGenInstruction.cpp b/contrib/llvm/utils/TableGen/CodeGenInstruction.cpp index 3673204..576388b 100644 --- a/contrib/llvm/utils/TableGen/CodeGenInstruction.cpp +++ b/contrib/llvm/utils/TableGen/CodeGenInstruction.cpp @@ -90,7 +90,7 @@ CGIOperandList::CGIOperandList(Record *R) : TheDef(R) { if (unsigned NumArgs = MIOpInfo->getNumArgs()) NumOps = NumArgs; - if (Rec->isSubClassOf("PredicateOperand")) + if (Rec->isSubClassOf("PredicateOp")) isPredicable = true; else if (Rec->isSubClassOf("OptionalDefOperand")) hasOptionalDef = true; @@ -192,6 +192,7 @@ CGIOperandList::ParseOperandName(const std::string &Op, bool AllowWholeOp) { // Otherwise, didn't find it! PrintFatalError(TheDef->getName() + ": unknown suboperand name in '" + Op + "'"); + return std::make_pair(0U, 0U); } static void ParseConstraint(const std::string &CStr, CGIOperandList &Ops) { @@ -336,6 +337,20 @@ CodeGenInstruction::CodeGenInstruction(Record *R) // Parse the DisableEncoding field. Operands.ProcessDisableEncoding(R->getValueAsString("DisableEncoding")); + + // First check for a ComplexDeprecationPredicate. + if (R->getValue("ComplexDeprecationPredicate")) { + HasComplexDeprecationPredicate = true; + DeprecatedReason = R->getValueAsString("ComplexDeprecationPredicate"); + } else if (RecordVal *Dep = R->getValue("DeprecatedFeatureMask")) { + // Check if we have a Subtarget feature mask. + HasComplexDeprecationPredicate = false; + DeprecatedReason = Dep->getValue()->getAsString(); + } else { + // This instruction isn't deprecated. + HasComplexDeprecationPredicate = false; + DeprecatedReason = ""; + } } /// HasOneImplicitDefWithKnownVT - If the instruction has at least one diff --git a/contrib/llvm/utils/TableGen/CodeGenInstruction.h b/contrib/llvm/utils/TableGen/CodeGenInstruction.h index d1e1153..6004f66 100644 --- a/contrib/llvm/utils/TableGen/CodeGenInstruction.h +++ b/contrib/llvm/utils/TableGen/CodeGenInstruction.h @@ -248,6 +248,9 @@ namespace llvm { bool isCodeGenOnly; bool isPseudo; + std::string DeprecatedReason; + bool HasComplexDeprecationPredicate; + /// Are there any undefined flags? bool hasUndefFlags() const { return mayLoad_Unset || mayStore_Unset || hasSideEffects_Unset; diff --git a/contrib/llvm/utils/TableGen/CodeGenIntrinsics.h b/contrib/llvm/utils/TableGen/CodeGenIntrinsics.h index f0570f9..ababfa4 100644 --- a/contrib/llvm/utils/TableGen/CodeGenIntrinsics.h +++ b/contrib/llvm/utils/TableGen/CodeGenIntrinsics.h @@ -77,7 +77,9 @@ namespace llvm { bool isNoReturn; enum ArgAttribute { - NoCapture + NoCapture, + ReadOnly, + ReadNone }; std::vector<std::pair<unsigned, ArgAttribute> > ArgumentAttributes; diff --git a/contrib/llvm/utils/TableGen/CodeGenMapTable.cpp b/contrib/llvm/utils/TableGen/CodeGenMapTable.cpp index ee32aa1..cb7ec3e 100644 --- a/contrib/llvm/utils/TableGen/CodeGenMapTable.cpp +++ b/contrib/llvm/utils/TableGen/CodeGenMapTable.cpp @@ -240,7 +240,6 @@ public: void MapTableEmitter::buildRowInstrMap() { for (unsigned i = 0, e = InstrDefs.size(); i < e; i++) { - std::vector<Record*> InstrList; Record *CurInstr = InstrDefs[i]; std::vector<Init*> KeyValue; ListInit *RowFields = InstrMapDesc.getRowFields(); diff --git a/contrib/llvm/utils/TableGen/CodeGenRegisters.cpp b/contrib/llvm/utils/TableGen/CodeGenRegisters.cpp index 993b8db..f2eef4f 100644 --- a/contrib/llvm/utils/TableGen/CodeGenRegisters.cpp +++ b/contrib/llvm/utils/TableGen/CodeGenRegisters.cpp @@ -12,6 +12,8 @@ // //===----------------------------------------------------------------------===// +#define DEBUG_TYPE "regalloc-emitter" + #include "CodeGenRegisters.h" #include "CodeGenTarget.h" #include "llvm/ADT/IntEqClasses.h" @@ -19,6 +21,7 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/Twine.h" +#include "llvm/Support/Debug.h" #include "llvm/TableGen/Error.h" using namespace llvm; @@ -28,15 +31,18 @@ using namespace llvm; //===----------------------------------------------------------------------===// CodeGenSubRegIndex::CodeGenSubRegIndex(Record *R, unsigned Enum) - : TheDef(R), EnumValue(Enum), LaneMask(0) { + : TheDef(R), EnumValue(Enum), LaneMask(0), AllSuperRegsCovered(true) { Name = R->getName(); if (R->getValue("Namespace")) Namespace = R->getValueAsString("Namespace"); + Size = R->getValueAsInt("Size"); + Offset = R->getValueAsInt("Offset"); } CodeGenSubRegIndex::CodeGenSubRegIndex(StringRef N, StringRef Nspace, unsigned Enum) - : TheDef(0), Name(N), Namespace(Nspace), EnumValue(Enum), LaneMask(0) { + : TheDef(0), Name(N), Namespace(Nspace), Size(-1), Offset(-1), + EnumValue(Enum), LaneMask(0), AllSuperRegsCovered(true) { } std::string CodeGenSubRegIndex::getQualifiedName() const { @@ -68,7 +74,7 @@ void CodeGenSubRegIndex::updateComponents(CodeGenRegBank &RegBank) { if (!Parts.empty()) { if (Parts.size() < 2) PrintFatalError(TheDef->getLoc(), - "CoveredBySubRegs must have two or more entries"); + "CoveredBySubRegs must have two or more entries"); SmallVector<CodeGenSubRegIndex*, 8> IdxParts; for (unsigned i = 0, e = Parts.size(); i != e; ++i) IdxParts.push_back(RegBank.getSubRegIdx(Parts[i])); @@ -312,6 +318,11 @@ CodeGenRegister::computeSubRegs(CodeGenRegBank &RegBank) { PrintFatalError(Loc, "Register " + getName() + " has itself as a sub-register"); } + + // Compute AllSuperRegsCovered. + if (!CoveredBySubRegs) + SI->first->AllSuperRegsCovered = false; + // Ensure that every sub-register has a unique name. DenseMap<const CodeGenRegister*, CodeGenSubRegIndex*>::iterator Ins = SubReg2Idx.insert(std::make_pair(SI->second, SI->first)).first; @@ -520,55 +531,6 @@ CodeGenRegister::addSubRegsPreOrder(SetVector<const CodeGenRegister*> &OSet, OSet.insert(I->second); } -// Compute overlapping registers. -// -// The standard set is all super-registers and all sub-registers, but the -// target description can add arbitrary overlapping registers via the 'Aliases' -// field. This complicates things, but we can compute overlapping sets using -// the following rules: -// -// 1. The relation overlap(A, B) is reflexive and symmetric but not transitive. -// -// 2. overlap(A, B) implies overlap(A, S) for all S in supers(B). -// -// Alternatively: -// -// overlap(A, B) iff there exists: -// A' in { A, subregs(A) } and B' in { B, subregs(B) } such that: -// A' = B' or A' in aliases(B') or B' in aliases(A'). -// -// Here subregs(A) is the full flattened sub-register set returned by -// A.getSubRegs() while aliases(A) is simply the special 'Aliases' field in the -// description of register A. -// -// This also implies that registers with a common sub-register are considered -// overlapping. This can happen when forming register pairs: -// -// P0 = (R0, R1) -// P1 = (R1, R2) -// P2 = (R2, R3) -// -// In this case, we will infer an overlap between P0 and P1 because of the -// shared sub-register R1. There is no overlap between P0 and P2. -// -void CodeGenRegister::computeOverlaps(CodeGenRegister::Set &Overlaps, - const CodeGenRegBank &RegBank) const { - assert(!RegUnits.empty() && "Compute register units before overlaps."); - - // Register units are assigned such that the overlapping registers are the - // super-registers of the root registers of the register units. - for (unsigned rui = 0, rue = RegUnits.size(); rui != rue; ++rui) { - const RegUnit &RU = RegBank.getRegUnit(RegUnits[rui]); - ArrayRef<const CodeGenRegister*> Roots = RU.getRoots(); - for (unsigned ri = 0, re = Roots.size(); ri != re; ++ri) { - const CodeGenRegister *Root = Roots[ri]; - Overlaps.insert(Root); - ArrayRef<const CodeGenRegister*> Supers = Root->getSuperRegs(); - Overlaps.insert(Supers.begin(), Supers.end()); - } - } -} - // Get the sum of this register's unit weights. unsigned CodeGenRegister::getWeight(const CodeGenRegBank &RegBank) const { unsigned Weight = 0; @@ -851,9 +813,10 @@ static bool testSubClass(const CodeGenRegisterClass *A, /// Register classes with the same registers, spill size, and alignment form a /// clique. They will be ordered alphabetically. /// -static int TopoOrderRC(const void *PA, const void *PB) { - const CodeGenRegisterClass *A = *(const CodeGenRegisterClass* const*)PA; - const CodeGenRegisterClass *B = *(const CodeGenRegisterClass* const*)PB; +static int TopoOrderRC(CodeGenRegisterClass *const *PA, + CodeGenRegisterClass *const *PB) { + const CodeGenRegisterClass *A = *PA; + const CodeGenRegisterClass *B = *PB; if (A == B) return 0; @@ -979,7 +942,7 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) { // Read in the register definitions. std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register"); - std::sort(Regs.begin(), Regs.end(), LessRecord()); + std::sort(Regs.begin(), Regs.end(), LessRecordRegister()); Registers.reserve(Regs.size()); // Assign the enumeration values. for (unsigned i = 0, e = Regs.size(); i != e; ++i) @@ -988,10 +951,16 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) { // Expand tuples and number the new registers. std::vector<Record*> Tups = Records.getAllDerivedDefinitions("RegisterTuples"); + + std::vector<Record*> TupRegsCopy; for (unsigned i = 0, e = Tups.size(); i != e; ++i) { const std::vector<Record*> *TupRegs = Sets.expand(Tups[i]); - for (unsigned j = 0, je = TupRegs->size(); j != je; ++j) - getReg((*TupRegs)[j]); + TupRegsCopy.reserve(TupRegs->size()); + TupRegsCopy.assign(TupRegs->begin(), TupRegs->end()); + std::sort(TupRegsCopy.begin(), TupRegsCopy.end(), LessRecordRegister()); + for (unsigned j = 0, je = TupRegsCopy.size(); j != je; ++j) + getReg((TupRegsCopy)[j]); + TupRegsCopy.clear(); } // Now all the registers are known. Build the object graph of explicit @@ -1123,7 +1092,7 @@ CodeGenRegBank::getCompositeSubRegIndex(CodeGenSubRegIndex *A, } CodeGenSubRegIndex *CodeGenRegBank:: -getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex*, 8> &Parts) { +getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &Parts) { assert(Parts.size() > 1 && "Need two parts to concatenate"); // Look for an existing entry. @@ -1133,11 +1102,24 @@ getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex*, 8> &Parts) { // None exists, synthesize one. std::string Name = Parts.front()->getName(); + // Determine whether all parts are contiguous. + bool isContinuous = true; + unsigned Size = Parts.front()->Size; + unsigned LastOffset = Parts.front()->Offset; + unsigned LastSize = Parts.front()->Size; for (unsigned i = 1, e = Parts.size(); i != e; ++i) { Name += '_'; Name += Parts[i]->getName(); + Size += Parts[i]->Size; + if (Parts[i]->Offset != (LastOffset + LastSize)) + isContinuous = false; + LastOffset = Parts[i]->Offset; + LastSize = Parts[i]->Size; } - return Idx = createSubRegIndex(Name, Parts.front()->getNamespace()); + Idx = createSubRegIndex(Name, Parts.front()->getNamespace()); + Idx->Size = Size; + Idx->Offset = isContinuous ? Parts.front()->Offset : -1; + return Idx; } void CodeGenRegBank::computeComposites() { @@ -1195,6 +1177,8 @@ void CodeGenRegBank::computeComposites() { void CodeGenRegBank::computeSubRegIndexLaneMasks() { // First assign individual bits to all the leaf indices. unsigned Bit = 0; + // Determine mask of lanes that cover their registers. + CoveringLanes = ~0u; for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { CodeGenSubRegIndex *Idx = SubRegIndices[i]; if (Idx->getComposites().empty()) { @@ -1206,7 +1190,12 @@ void CodeGenRegBank::computeSubRegIndexLaneMasks() { // view of lanes beyond the 32nd. // // See also the comment for getSubRegIndexLaneMask(). - if (Bit < 31) ++Bit; + if (Bit < 31) + ++Bit; + else + // Once bit 31 is shared among multiple leafs, the 'lane' it represents + // is no longer covering its registers. + CoveringLanes &= ~(1u << Bit); } else { Idx->LaneMask = 0; } @@ -1216,8 +1205,13 @@ void CodeGenRegBank::computeSubRegIndexLaneMasks() { // by the sub-register graph? This doesn't occur in any known targets. // Inherit lanes from composites. - for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) - SubRegIndices[i]->computeLaneMask(); + for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { + unsigned Mask = SubRegIndices[i]->computeLaneMask(); + // If some super-registers without CoveredBySubRegs use this index, we can + // no longer assume that the lanes are covering their registers. + if (!SubRegIndices[i]->AllSuperRegsCovered) + CoveringLanes &= ~Mask; + } } namespace { @@ -1339,9 +1333,18 @@ static void computeUberWeights(std::vector<UberRegSet> &UberSets, } if (Weight > MaxWeight) MaxWeight = Weight; - - // Update the set weight. - I->Weight = MaxWeight; + if (I->Weight != MaxWeight) { + DEBUG( + dbgs() << "UberSet " << I - UberSets.begin() << " Weight " << MaxWeight; + for (CodeGenRegister::Set::iterator + UnitI = I->Regs.begin(), UnitE = I->Regs.end(); + UnitI != UnitE; ++UnitI) { + dbgs() << " " << (*UnitI)->getName(); + } + dbgs() << "\n"); + // Update the set weight. + I->Weight = MaxWeight; + } // Find singular determinants. for (CodeGenRegister::Set::iterator RegI = I->Regs.begin(), @@ -1468,7 +1471,23 @@ static bool isRegUnitSubSet(const std::vector<unsigned> &RUSubSet, RUSubSet.begin(), RUSubSet.end()); } -// Iteratively prune unit sets. +/// Iteratively prune unit sets. Prune subsets that are close to the superset, +/// but with one or two registers removed. We occasionally have registers like +/// APSR and PC thrown in with the general registers. We also see many +/// special-purpose register subsets, such as tail-call and Thumb +/// encodings. Generating all possible overlapping sets is combinatorial and +/// overkill for modeling pressure. Ideally we could fix this statically in +/// tablegen by (1) having the target define register classes that only include +/// the allocatable registers and marking other classes as non-allocatable and +/// (2) having a way to mark special purpose classes as "don't-care" classes for +/// the purpose of pressure. However, we make an attempt to handle targets that +/// are not nicely defined by merging nearly identical register unit sets +/// statically. This generates smaller tables. Then, dynamically, we adjust the +/// set limit by filtering the reserved registers. +/// +/// Merge sets only if the units have the same weight. For example, on ARM, +/// Q-tuples with ssub index 0 include all S regs but also include D16+. We +/// should not expand the S set to include D regs. void CodeGenRegBank::pruneUnitSets() { assert(RegClassUnitSets.empty() && "this invalidates RegClassUnitSets"); @@ -1482,9 +1501,14 @@ void CodeGenRegBank::pruneUnitSets() { if (SuperIdx == SubIdx) continue; + unsigned UnitWeight = RegUnits[SubSet.Units[0]].Weight; const RegUnitSet &SuperSet = RegUnitSets[SuperIdx]; if (isRegUnitSubSet(SubSet.Units, SuperSet.Units) - && (SubSet.Units.size() + 3 > SuperSet.Units.size())) { + && (SubSet.Units.size() + 3 > SuperSet.Units.size()) + && UnitWeight == RegUnits[SuperSet.Units[0]].Weight + && UnitWeight == RegUnits[SuperSet.Units.back()].Weight) { + DEBUG(dbgs() << "UnitSet " << SubIdx << " subsumed by " << SuperIdx + << "\n"); break; } } @@ -1509,6 +1533,7 @@ void CodeGenRegBank::pruneUnitSets() { // RegisterInfoEmitter will map each RegClass to its RegUnitClass and any // RegUnitSet that is a superset of that RegUnitClass. void CodeGenRegBank::computeRegUnitSets() { + assert(RegUnitSets.empty() && "dirty RegUnitSets"); // Compute a unique RegUnitSet for each RegClass. const ArrayRef<CodeGenRegisterClass*> &RegClasses = getRegClasses(); @@ -1531,9 +1556,32 @@ void CodeGenRegBank::computeRegUnitSets() { RegUnitSets.pop_back(); } + DEBUG(dbgs() << "\nBefore pruning:\n"; + for (unsigned USIdx = 0, USEnd = RegUnitSets.size(); + USIdx < USEnd; ++USIdx) { + dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name + << ":"; + ArrayRef<unsigned> Units = RegUnitSets[USIdx].Units; + for (unsigned i = 0, e = Units.size(); i < e; ++i) + dbgs() << " " << RegUnits[Units[i]].Roots[0]->getName(); + dbgs() << "\n"; + }); + // Iteratively prune unit sets. pruneUnitSets(); + DEBUG(dbgs() << "\nBefore union:\n"; + for (unsigned USIdx = 0, USEnd = RegUnitSets.size(); + USIdx < USEnd; ++USIdx) { + dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name + << ":"; + ArrayRef<unsigned> Units = RegUnitSets[USIdx].Units; + for (unsigned i = 0, e = Units.size(); i < e; ++i) + dbgs() << " " << RegUnits[Units[i]].Roots[0]->getName(); + dbgs() << "\n"; + } + dbgs() << "\nUnion sets:\n"); + // Iterate over all unit sets, including new ones added by this loop. unsigned NumRegUnitSubSets = RegUnitSets.size(); for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) { @@ -1571,12 +1619,31 @@ void CodeGenRegBank::computeRegUnitSets() { findRegUnitSet(RegUnitSets, RegUnitSets.back()); if (SetI != llvm::prior(RegUnitSets.end())) RegUnitSets.pop_back(); + else { + DEBUG(dbgs() << "UnitSet " << RegUnitSets.size()-1 + << " " << RegUnitSets.back().Name << ":"; + ArrayRef<unsigned> Units = RegUnitSets.back().Units; + for (unsigned i = 0, e = Units.size(); i < e; ++i) + dbgs() << " " << RegUnits[Units[i]].Roots[0]->getName(); + dbgs() << "\n";); + } } } // Iteratively prune unit sets after inferring supersets. pruneUnitSets(); + DEBUG(dbgs() << "\n"; + for (unsigned USIdx = 0, USEnd = RegUnitSets.size(); + USIdx < USEnd; ++USIdx) { + dbgs() << "UnitSet " << USIdx << " " << RegUnitSets[USIdx].Name + << ":"; + ArrayRef<unsigned> Units = RegUnitSets[USIdx].Units; + for (unsigned i = 0, e = Units.size(); i < e; ++i) + dbgs() << " " << RegUnits[Units[i]].Roots[0]->getName(); + dbgs() << "\n"; + }); + // For each register class, list the UnitSets that are supersets. RegClassUnitSets.resize(NumRegClasses); for (unsigned RCIdx = 0, RCEnd = NumRegClasses; RCIdx != RCEnd; ++RCIdx) { @@ -1584,19 +1651,27 @@ void CodeGenRegBank::computeRegUnitSets() { continue; // Recompute the sorted list of units in this class. - std::vector<unsigned> RegUnits; - RegClasses[RCIdx]->buildRegUnitSet(RegUnits); + std::vector<unsigned> RCRegUnits; + RegClasses[RCIdx]->buildRegUnitSet(RCRegUnits); // Don't increase pressure for unallocatable regclasses. - if (RegUnits.empty()) + if (RCRegUnits.empty()) continue; + DEBUG(dbgs() << "RC " << RegClasses[RCIdx]->getName() << " Units: \n"; + for (unsigned i = 0, e = RCRegUnits.size(); i < e; ++i) + dbgs() << RegUnits[RCRegUnits[i]].getRoots()[0]->getName() << " "; + dbgs() << "\n UnitSetIDs:"); + // Find all supersets. for (unsigned USIdx = 0, USEnd = RegUnitSets.size(); USIdx != USEnd; ++USIdx) { - if (isRegUnitSubSet(RegUnits, RegUnitSets[USIdx].Units)) + if (isRegUnitSubSet(RCRegUnits, RegUnitSets[USIdx].Units)) { + DEBUG(dbgs() << " " << USIdx); RegClassUnitSets[RCIdx].push_back(USIdx); + } } + DEBUG(dbgs() << "\n"); assert(!RegClassUnitSets[RCIdx].empty() && "missing unit set for regclass"); } @@ -1630,6 +1705,16 @@ void CodeGenRegBank::computeRegUnitSets() { } } +struct LessUnits { + const CodeGenRegBank &RegBank; + LessUnits(const CodeGenRegBank &RB): RegBank(RB) {} + + bool operator()(unsigned ID1, unsigned ID2) { + return RegBank.getRegPressureSet(ID1).Units.size() + < RegBank.getRegPressureSet(ID2).Units.size(); + } +}; + void CodeGenRegBank::computeDerivedInfo() { computeComposites(); computeSubRegIndexLaneMasks(); @@ -1641,6 +1726,21 @@ void CodeGenRegBank::computeDerivedInfo() { // Compute a unique set of RegUnitSets. One for each RegClass and inferred // supersets for the union of overlapping sets. computeRegUnitSets(); + + // Get the weight of each set. + for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) + RegUnitSets[Idx].Weight = getRegUnitSetWeight(RegUnitSets[Idx].Units); + + // Find the order of each set. + RegUnitSetOrder.reserve(RegUnitSets.size()); + for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) + RegUnitSetOrder.push_back(Idx); + + std::stable_sort(RegUnitSetOrder.begin(), RegUnitSetOrder.end(), + LessUnits(*this)); + for (unsigned Idx = 0, EndIdx = RegUnitSets.size(); Idx != EndIdx; ++Idx) { + RegUnitSets[RegUnitSetOrder[Idx]].Order = Idx; + } } // diff --git a/contrib/llvm/utils/TableGen/CodeGenRegisters.h b/contrib/llvm/utils/TableGen/CodeGenRegisters.h index 4f2cc28..37f75b4 100644 --- a/contrib/llvm/utils/TableGen/CodeGenRegisters.h +++ b/contrib/llvm/utils/TableGen/CodeGenRegisters.h @@ -39,9 +39,15 @@ namespace llvm { std::string Namespace; public: + uint16_t Size; + uint16_t Offset; const unsigned EnumValue; unsigned LaneMask; + // Are all super-registers containing this SubRegIndex covered by their + // sub-registers? + bool AllSuperRegsCovered; + CodeGenSubRegIndex(Record *R, unsigned Enum); CodeGenSubRegIndex(StringRef N, StringRef Nspace, unsigned Enum); @@ -75,6 +81,15 @@ namespace llvm { assert(A && B); std::pair<CompMap::iterator, bool> Ins = Composed.insert(std::make_pair(A, B)); + // Synthetic subreg indices that aren't contiguous (for instance ARM + // register tuples) don't have a bit range, so it's OK to let + // B->Offset == -1. For the other cases, accumulate the offset and set + // the size here. Only do so if there is no offset yet though. + if ((Offset != (uint16_t)-1 && A->Offset != (uint16_t)-1) && + (B->Offset == (uint16_t)-1)) { + B->Offset = Offset + A->Offset; + B->Size = A->Size; + } return (Ins.second || Ins.first->second == B) ? 0 : Ins.first->second; } @@ -201,9 +216,6 @@ namespace llvm { // Canonically ordered set. typedef std::set<const CodeGenRegister*, Less> Set; - // Compute the set of registers overlapping this. - void computeOverlaps(Set &Overlaps, const CodeGenRegBank&) const; - private: bool SubRegsComplete; bool SuperRegsComplete; @@ -421,6 +433,10 @@ namespace llvm { std::string Name; std::vector<unsigned> Units; + unsigned Weight; // Cache the sum of all unit weights. + unsigned Order; // Cache the sort key. + + RegUnitSet() : Weight(0), Order(0) {} }; // Base vector for identifying TopoSigs. The contents uniquely identify a @@ -472,6 +488,9 @@ namespace llvm { // already exist for a register class, we create a new entry in this vector. std::vector<std::vector<unsigned> > RegClassUnitSets; + // Give each register unit set an order based on sorting criteria. + std::vector<unsigned> RegUnitSetOrder; + // Add RC to *2RC maps. void addToMaps(CodeGenRegisterClass*); @@ -522,10 +541,10 @@ namespace llvm { // Find or create a sub-register index representing the concatenation of // non-overlapping sibling indices. CodeGenSubRegIndex * - getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex*, 8>&); + getConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8>&); void - addConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex*, 8> &Parts, + addConcatSubRegIndex(const SmallVector<CodeGenSubRegIndex *, 8> &Parts, CodeGenSubRegIndex *Idx) { ConcatIdx.insert(std::make_pair(Parts, Idx)); } @@ -610,6 +629,13 @@ namespace llvm { return Weight; } + unsigned getRegSetIDAt(unsigned Order) const { + return RegUnitSetOrder[Order]; + } + const RegUnitSet &getRegSetAt(unsigned Order) const { + return RegUnitSets[RegUnitSetOrder[Order]]; + } + // Increase a RegUnitWeight. void increaseRegUnitWeight(unsigned RUID, unsigned Inc) { getRegUnit(RUID).Weight += Inc; @@ -619,7 +645,7 @@ namespace llvm { unsigned getNumRegPressureSets() const { return RegUnitSets.size(); } // Get a set of register unit IDs for a given dimension of pressure. - RegUnitSet getRegPressureSet(unsigned Idx) const { + const RegUnitSet &getRegPressureSet(unsigned Idx) const { return RegUnitSets[Idx]; } @@ -649,6 +675,11 @@ namespace llvm { // This is used to compute the mask of call-preserved registers from a list // of callee-saves. BitVector computeCoveredRegisters(ArrayRef<Record*> Regs); + + // Bit mask of lanes that cover their registers. A sub-register index whose + // LaneMask is contained in CoveringLanes will be completely covered by + // another sub-register with the same or larger lane mask. + unsigned CoveringLanes; }; } diff --git a/contrib/llvm/utils/TableGen/CodeGenSchedule.cpp b/contrib/llvm/utils/TableGen/CodeGenSchedule.cpp index 112ff65..dd06433 100644 --- a/contrib/llvm/utils/TableGen/CodeGenSchedule.cpp +++ b/contrib/llvm/utils/TableGen/CodeGenSchedule.cpp @@ -36,10 +36,11 @@ static void dumpIdxVec(const SmallVectorImpl<unsigned> &V) { } #endif +namespace { // (instrs a, b, ...) Evaluate and union all arguments. Identical to AddOp. struct InstrsOp : public SetTheory::Operator { - void apply(SetTheory &ST, DagInit *Expr, SetTheory::RecSet &Elts, - ArrayRef<SMLoc> Loc) { + virtual void apply(SetTheory &ST, DagInit *Expr, SetTheory::RecSet &Elts, + ArrayRef<SMLoc> Loc) { ST.evaluate(Expr->arg_begin(), Expr->arg_end(), Elts, Loc); } }; @@ -84,6 +85,7 @@ struct InstRegexOp : public SetTheory::Operator { DeleteContainerPointers(RegexList); } }; +} // end anonymous namespace /// CodeGenModels ctor interprets machine model records and populates maps. CodeGenSchedModels::CodeGenSchedModels(RecordKeeper &RK, @@ -710,16 +712,35 @@ void CodeGenSchedModels::createInstRWClass(Record *InstRWDef) { ArrayRef<Record*> InstDefs = ClassInstrs[CIdx].second; // If the all instrs in the current class are accounted for, then leave // them mapped to their old class. - if (OldSCIdx && SchedClasses[OldSCIdx].InstRWs.size() == InstDefs.size()) { - assert(SchedClasses[OldSCIdx].ProcIndices[0] == 0 && - "expected a generic SchedClass"); - continue; + if (OldSCIdx) { + const RecVec &RWDefs = SchedClasses[OldSCIdx].InstRWs; + if (!RWDefs.empty()) { + const RecVec *OrigInstDefs = Sets.expand(RWDefs[0]); + unsigned OrigNumInstrs = 0; + for (RecIter I = OrigInstDefs->begin(), E = OrigInstDefs->end(); + I != E; ++I) { + if (InstrClassMap[*I] == OldSCIdx) + ++OrigNumInstrs; + } + if (OrigNumInstrs == InstDefs.size()) { + assert(SchedClasses[OldSCIdx].ProcIndices[0] == 0 && + "expected a generic SchedClass"); + DEBUG(dbgs() << "InstRW: Reuse SC " << OldSCIdx << ":" + << SchedClasses[OldSCIdx].Name << " on " + << InstRWDef->getValueAsDef("SchedModel")->getName() << "\n"); + SchedClasses[OldSCIdx].InstRWs.push_back(InstRWDef); + continue; + } + } } unsigned SCIdx = SchedClasses.size(); SchedClasses.resize(SCIdx+1); CodeGenSchedClass &SC = SchedClasses.back(); SC.Index = SCIdx; SC.Name = createSchedClassName(InstDefs); + DEBUG(dbgs() << "InstRW: New SC " << SCIdx << ":" << SC.Name << " on " + << InstRWDef->getValueAsDef("SchedModel")->getName() << "\n"); + // Preserve ItinDef and Writes/Reads for processors without an InstRW entry. SC.ItinClassDef = SchedClasses[OldSCIdx].ItinClassDef; SC.Writes = SchedClasses[OldSCIdx].Writes; @@ -871,9 +892,10 @@ void CodeGenSchedModels::inferFromItinClass(Record *ItinClassDef, /// Infer classes from per-processor InstReadWrite definitions. void CodeGenSchedModels::inferFromInstRWs(unsigned SCIdx) { - const RecVec &RWDefs = SchedClasses[SCIdx].InstRWs; - for (RecIter RWI = RWDefs.begin(), RWE = RWDefs.end(); RWI != RWE; ++RWI) { - const RecVec *InstDefs = Sets.expand(*RWI); + for (unsigned I = 0, E = SchedClasses[SCIdx].InstRWs.size(); I != E; ++I) { + assert(SchedClasses[SCIdx].InstRWs.size() == E && "InstrRWs was mutated!"); + Record *Rec = SchedClasses[SCIdx].InstRWs[I]; + const RecVec *InstDefs = Sets.expand(Rec); RecIter II = InstDefs->begin(), IE = InstDefs->end(); for (; II != IE; ++II) { if (InstrClassMap[*II] == SCIdx) @@ -884,10 +906,10 @@ void CodeGenSchedModels::inferFromInstRWs(unsigned SCIdx) { if (II == IE) continue; IdxVec Writes, Reads; - findRWs((*RWI)->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads); - unsigned PIdx = getProcModel((*RWI)->getValueAsDef("SchedModel")).Index; + findRWs(Rec->getValueAsListOfDefs("OperandReadWrites"), Writes, Reads); + unsigned PIdx = getProcModel(Rec->getValueAsDef("SchedModel")).Index; IdxVec ProcIndices(1, PIdx); - inferFromRW(Writes, Reads, SCIdx, ProcIndices); + inferFromRW(Writes, Reads, SCIdx, ProcIndices); // May mutate SchedClasses. } } @@ -1082,7 +1104,7 @@ void PredTransitions::getIntersectingVariants( TransVariant &Variant = Variants[VIdx]; // Don't expand variants if the processor models don't intersect. // A zero processor index means any processor. - SmallVector<unsigned, 4> &ProcIndices = TransVec[TransIdx].ProcIndices; + SmallVectorImpl<unsigned> &ProcIndices = TransVec[TransIdx].ProcIndices; if (ProcIndices[0] && Variants[VIdx].ProcIdx) { unsigned Cnt = std::count(ProcIndices.begin(), ProcIndices.end(), Variant.ProcIdx); @@ -1153,6 +1175,8 @@ pushVariant(const TransVariant &VInfo, bool IsRead) { unsigned OperIdx = RWSequences.size()-1; // Make N-1 copies of this transition's last sequence. for (unsigned i = 1, e = SelectedRWs.size(); i != e; ++i) { + // Create a temporary copy the vector could reallocate. + RWSequences.reserve(RWSequences.size() + 1); RWSequences.push_back(RWSequences[OperIdx]); } // Push each of the N elements of the SelectedRWs onto a copy of the last @@ -1454,6 +1478,19 @@ void CodeGenSchedModels::collectProcResources() { Record *ModelDef = (*RAI)->getValueAsDef("SchedModel"); addReadAdvance(*RAI, getProcModel(ModelDef).Index); } + // Add ProcResGroups that are defined within this processor model, which may + // not be directly referenced but may directly specify a buffer size. + RecVec ProcResGroups = Records.getAllDerivedDefinitions("ProcResGroup"); + for (RecIter RI = ProcResGroups.begin(), RE = ProcResGroups.end(); + RI != RE; ++RI) { + if (!(*RI)->getValueInit("SchedModel")->isComplete()) + continue; + CodeGenProcModel &PM = getProcModel((*RI)->getValueAsDef("SchedModel")); + RecIter I = std::find(PM.ProcResourceDefs.begin(), + PM.ProcResourceDefs.end(), *RI); + if (I == PM.ProcResourceDefs.end()) + PM.ProcResourceDefs.push_back(*RI); + } // Finalize each ProcModel by sorting the record arrays. for (unsigned PIdx = 0, PEnd = ProcModels.size(); PIdx != PEnd; ++PIdx) { CodeGenProcModel &PM = ProcModels[PIdx]; diff --git a/contrib/llvm/utils/TableGen/CodeGenSchedule.h b/contrib/llvm/utils/TableGen/CodeGenSchedule.h index 2e0a149..fa964cf 100644 --- a/contrib/llvm/utils/TableGen/CodeGenSchedule.h +++ b/contrib/llvm/utils/TableGen/CodeGenSchedule.h @@ -266,11 +266,14 @@ public: return ProcModels[I->second]; } - const CodeGenProcModel &getProcModel(Record *ModelDef) const { + CodeGenProcModel &getProcModel(Record *ModelDef) { ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef); assert(I != ProcModelMap.end() && "missing machine model"); return ProcModels[I->second]; } + const CodeGenProcModel &getProcModel(Record *ModelDef) const { + return const_cast<CodeGenSchedModels*>(this)->getProcModel(ModelDef); + } // Iterate over the unique processor models. typedef std::vector<CodeGenProcModel>::const_iterator ProcIter; diff --git a/contrib/llvm/utils/TableGen/CodeGenTarget.cpp b/contrib/llvm/utils/TableGen/CodeGenTarget.cpp index 8b292b9..dd17059 100644 --- a/contrib/llvm/utils/TableGen/CodeGenTarget.cpp +++ b/contrib/llvm/utils/TableGen/CodeGenTarget.cpp @@ -75,6 +75,7 @@ std::string llvm::getEnumName(MVT::SimpleValueType T) { case MVT::v16i1: return "MVT::v16i1"; case MVT::v32i1: return "MVT::v32i1"; case MVT::v64i1: return "MVT::v64i1"; + case MVT::v1i8: return "MVT::v1i8"; case MVT::v2i8: return "MVT::v2i8"; case MVT::v4i8: return "MVT::v4i8"; case MVT::v8i8: return "MVT::v8i8"; @@ -98,10 +99,14 @@ std::string llvm::getEnumName(MVT::SimpleValueType T) { case MVT::v8i64: return "MVT::v8i64"; case MVT::v16i64: return "MVT::v16i64"; case MVT::v2f16: return "MVT::v2f16"; + case MVT::v4f16: return "MVT::v4f16"; + case MVT::v8f16: return "MVT::v8f16"; + case MVT::v1f32: return "MVT::v1f32"; case MVT::v2f32: return "MVT::v2f32"; case MVT::v4f32: return "MVT::v4f32"; case MVT::v8f32: return "MVT::v8f32"; case MVT::v16f32: return "MVT::v16f32"; + case MVT::v1f64: return "MVT::v1f64"; case MVT::v2f64: return "MVT::v2f64"; case MVT::v4f64: return "MVT::v4f64"; case MVT::v8f64: return "MVT::v8f64"; @@ -298,7 +303,7 @@ struct SortInstByName { /// target, ordered by their enum value. void CodeGenTarget::ComputeInstrsByEnum() const { // The ordering here must match the ordering in TargetOpcodes.h. - const char *const FixedInstrs[] = { + static const char *const FixedInstrs[] = { "PHI", "INLINEASM", "PROLOG_LABEL", @@ -316,6 +321,8 @@ void CodeGenTarget::ComputeInstrsByEnum() const { "BUNDLE", "LIFETIME_START", "LIFETIME_END", + "STACKMAP", + "PATCHPOINT", 0 }; const DenseMap<const Record*, CodeGenInstruction*> &Insts = getInstructions(); @@ -552,6 +559,12 @@ CodeGenIntrinsic::CodeGenIntrinsic(Record *R) { else if (Property->isSubClassOf("NoCapture")) { unsigned ArgNo = Property->getValueAsInt("ArgNo"); ArgumentAttributes.push_back(std::make_pair(ArgNo, NoCapture)); + } else if (Property->isSubClassOf("ReadOnly")) { + unsigned ArgNo = Property->getValueAsInt("ArgNo"); + ArgumentAttributes.push_back(std::make_pair(ArgNo, ReadOnly)); + } else if (Property->isSubClassOf("ReadNone")) { + unsigned ArgNo = Property->getValueAsInt("ArgNo"); + ArgumentAttributes.push_back(std::make_pair(ArgNo, ReadNone)); } else llvm_unreachable("Unknown property!"); } diff --git a/contrib/llvm/utils/TableGen/DAGISelEmitter.cpp b/contrib/llvm/utils/TableGen/DAGISelEmitter.cpp index b47dd71..a76ea32 100644 --- a/contrib/llvm/utils/TableGen/DAGISelEmitter.cpp +++ b/contrib/llvm/utils/TableGen/DAGISelEmitter.cpp @@ -81,15 +81,13 @@ struct PatternSortingPredicate { const TreePatternNode *LHSSrc = LHS->getSrcPattern(); const TreePatternNode *RHSSrc = RHS->getSrcPattern(); - if (LHSSrc->getNumTypes() != 0 && RHSSrc->getNumTypes() != 0 && - LHSSrc->getType(0) != RHSSrc->getType(0)) { - MVT::SimpleValueType V1 = LHSSrc->getType(0), V2 = RHSSrc->getType(0); - if (MVT(V1).isVector() != MVT(V2).isVector()) - return MVT(V2).isVector(); - - if (MVT(V1).isFloatingPoint() != MVT(V2).isFloatingPoint()) - return MVT(V2).isFloatingPoint(); - } + MVT LHSVT = (LHSSrc->getNumTypes() != 0 ? LHSSrc->getType(0) : MVT::Other); + MVT RHSVT = (RHSSrc->getNumTypes() != 0 ? RHSSrc->getType(0) : MVT::Other); + if (LHSVT.isVector() != RHSVT.isVector()) + return RHSVT.isVector(); + + if (LHSVT.isFloatingPoint() != RHSVT.isFloatingPoint()) + return RHSVT.isFloatingPoint(); // Otherwise, if the patterns might both match, sort based on complexity, // which means that we prefer to match patterns that cover more nodes in the diff --git a/contrib/llvm/utils/TableGen/DAGISelMatcher.cpp b/contrib/llvm/utils/TableGen/DAGISelMatcher.cpp index d173cf0..5d6a11a 100644 --- a/contrib/llvm/utils/TableGen/DAGISelMatcher.cpp +++ b/contrib/llvm/utils/TableGen/DAGISelMatcher.cpp @@ -63,7 +63,7 @@ bool Matcher::canMoveBefore(const Matcher *Other) const { } } -/// canMoveBefore - Return true if it is safe to move the current matcher +/// canMoveBeforeNode - Return true if it is safe to move the current matcher /// across the specified one. bool Matcher::canMoveBeforeNode(const Matcher *Other) const { // We can move simple predicates before record nodes. @@ -134,6 +134,10 @@ void CheckSameMatcher::printImpl(raw_ostream &OS, unsigned indent) const { OS.indent(indent) << "CheckSame " << MatchNumber << '\n'; } +void CheckChildSameMatcher::printImpl(raw_ostream &OS, unsigned indent) const { + OS.indent(indent) << "CheckChild" << ChildNo << "Same\n"; +} + void CheckPatternPredicateMatcher:: printImpl(raw_ostream &OS, unsigned indent) const { OS.indent(indent) << "CheckPatternPredicate " << Predicate << '\n'; diff --git a/contrib/llvm/utils/TableGen/DAGISelMatcher.h b/contrib/llvm/utils/TableGen/DAGISelMatcher.h index f978188..70031fa 100644 --- a/contrib/llvm/utils/TableGen/DAGISelMatcher.h +++ b/contrib/llvm/utils/TableGen/DAGISelMatcher.h @@ -55,6 +55,7 @@ public: // Predicate checking. CheckSame, // Fail if not same as prev match. + CheckChildSame, // Fail if child not same as prev match. CheckPatternPredicate, CheckPredicate, // Fail if node predicate fails. CheckOpcode, // Fail if not opcode. @@ -122,6 +123,7 @@ public: switch (getKind()) { default: return false; case CheckSame: + case CheckChildSame: case CheckPatternPredicate: case CheckPredicate: case CheckOpcode: @@ -154,7 +156,7 @@ public: /// node. Other must be equal to or before this. bool canMoveBefore(const Matcher *Other) const; - /// canMoveBefore - Return true if it is safe to move the current matcher + /// canMoveBeforeNode - Return true if it is safe to move the current matcher /// across the specified one. bool canMoveBeforeNode(const Matcher *Other) const; @@ -392,6 +394,34 @@ private: virtual unsigned getHashImpl() const { return getMatchNumber(); } }; +/// CheckChildSameMatcher - This checks to see if child node is exactly the same +/// node as the specified match that was recorded with 'Record'. This is used +/// when patterns have the same name in them, like '(mul GPR:$in, GPR:$in)'. +class CheckChildSameMatcher : public Matcher { + unsigned ChildNo; + unsigned MatchNumber; +public: + CheckChildSameMatcher(unsigned childno, unsigned matchnumber) + : Matcher(CheckChildSame), ChildNo(childno), MatchNumber(matchnumber) {} + + unsigned getChildNo() const { return ChildNo; } + unsigned getMatchNumber() const { return MatchNumber; } + + static inline bool classof(const Matcher *N) { + return N->getKind() == CheckChildSame; + } + + virtual bool isSafeToReorderWithPatternPredicate() const { return true; } + +private: + virtual void printImpl(raw_ostream &OS, unsigned indent) const; + virtual bool isEqualImpl(const Matcher *M) const { + return cast<CheckChildSameMatcher>(M)->ChildNo == ChildNo && + cast<CheckChildSameMatcher>(M)->MatchNumber == MatchNumber; + } + virtual unsigned getHashImpl() const { return (MatchNumber << 2) | ChildNo; } +}; + /// CheckPatternPredicateMatcher - This checks the target-specific predicate /// to see if the entire pattern is capable of matching. This predicate does /// not take a node as input. This is used for subtarget feature checks etc. diff --git a/contrib/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/contrib/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp index 93f84ce..04fe0d1 100644 --- a/contrib/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp +++ b/contrib/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp @@ -242,6 +242,12 @@ EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, << cast<CheckSameMatcher>(N)->getMatchNumber() << ",\n"; return 2; + case Matcher::CheckChildSame: + OS << "OPC_CheckChild" + << cast<CheckChildSameMatcher>(N)->getChildNo() << "Same, " + << cast<CheckChildSameMatcher>(N)->getMatchNumber() << ",\n"; + return 2; + case Matcher::CheckPatternPredicate: { StringRef Pred =cast<CheckPatternPredicateMatcher>(N)->getPredicate(); OS << "OPC_CheckPatternPredicate, " << getPatternPredicate(Pred) << ','; @@ -315,10 +321,12 @@ EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, assert(ChildSize != 0 && "Should not have a zero-sized child!"); if (i != 0) { + if (!OmitComments) + OS << "/*" << CurrentIdx << "*/"; OS.PadToColumn(Indent*2); if (!OmitComments) - OS << (isa<SwitchOpcodeMatcher>(N) ? - "/*SwitchOpcode*/ " : "/*SwitchType*/ "); + OS << (isa<SwitchOpcodeMatcher>(N) ? + "/*SwitchOpcode*/ " : "/*SwitchType*/ "); } // Emit the VBR. @@ -340,6 +348,8 @@ EmitMatcher(const Matcher *N, unsigned Indent, unsigned CurrentIdx, } // Emit the final zero to terminate the switch. + if (!OmitComments) + OS << "/*" << CurrentIdx << "*/"; OS.PadToColumn(Indent*2) << "0, "; if (!OmitComments) OS << (isa<SwitchOpcodeMatcher>(N) ? @@ -749,6 +759,7 @@ void MatcherTableEmitter::EmitHistogram(const Matcher *M, case Matcher::MoveChild: OS << "OPC_MoveChild"; break; case Matcher::MoveParent: OS << "OPC_MoveParent"; break; case Matcher::CheckSame: OS << "OPC_CheckSame"; break; + case Matcher::CheckChildSame: OS << "OPC_CheckChildSame"; break; case Matcher::CheckPatternPredicate: OS << "OPC_CheckPatternPredicate"; break; case Matcher::CheckPredicate: OS << "OPC_CheckPredicate"; break; diff --git a/contrib/llvm/utils/TableGen/DAGISelMatcherOpt.cpp b/contrib/llvm/utils/TableGen/DAGISelMatcherOpt.cpp index f996422..82e5d63 100644 --- a/contrib/llvm/utils/TableGen/DAGISelMatcherOpt.cpp +++ b/contrib/llvm/utils/TableGen/DAGISelMatcherOpt.cpp @@ -51,7 +51,11 @@ static void ContractNodes(OwningPtr<Matcher> &MatcherPtr, if (MC->getChildNo() < 8 && // Only have CheckChildType0...7 CT->getResNo() == 0) // CheckChildType checks res #0 New = new CheckChildTypeMatcher(MC->getChildNo(), CT->getType()); - + + if (CheckSameMatcher *CS = dyn_cast<CheckSameMatcher>(MC->getNext())) + if (MC->getChildNo() < 4) // Only have CheckChildSame0...3 + New = new CheckChildSameMatcher(MC->getChildNo(), CS->getMatchNumber()); + if (New) { // Insert the new node. New->setNext(MatcherPtr.take()); diff --git a/contrib/llvm/utils/TableGen/FastISelEmitter.cpp b/contrib/llvm/utils/TableGen/FastISelEmitter.cpp index 8b1e7f9..e35cf0f 100644 --- a/contrib/llvm/utils/TableGen/FastISelEmitter.cpp +++ b/contrib/llvm/utils/TableGen/FastISelEmitter.cpp @@ -46,7 +46,7 @@ class ImmPredicateSet { DenseMap<TreePattern *, unsigned> ImmIDs; std::vector<TreePredicateFn> PredsByName; public: - + unsigned getIDFor(TreePredicateFn Pred) { unsigned &Entry = ImmIDs[Pred.getOrigPatFragRecord()]; if (Entry == 0) { @@ -55,16 +55,16 @@ public: } return Entry-1; } - + const TreePredicateFn &getPredicate(unsigned i) { assert(i < PredsByName.size()); return PredsByName[i]; } - + typedef std::vector<TreePredicateFn>::const_iterator iterator; iterator begin() const { return PredsByName.begin(); } iterator end() const { return PredsByName.end(); } - + }; } // End anonymous namespace @@ -77,9 +77,9 @@ struct OperandsSignature { enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 }; char Repr; public: - + OpKind() : Repr(OK_Invalid) {} - + bool operator<(OpKind RHS) const { return Repr < RHS.Repr; } bool operator==(OpKind RHS) const { return Repr == RHS.Repr; } @@ -90,13 +90,13 @@ struct OperandsSignature { "Too many integer predicates for the 'Repr' char"); OpKind K; K.Repr = OK_Imm+V; return K; } - + bool isReg() const { return Repr == OK_Reg; } bool isFP() const { return Repr == OK_FP; } bool isImm() const { return Repr >= OK_Imm; } - + unsigned getImmCode() const { assert(isImm()); return Repr-OK_Imm; } - + void printManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates, bool StripImmCodes) const { if (isReg()) @@ -111,8 +111,8 @@ struct OperandsSignature { } } }; - - + + SmallVector<OpKind, 3> Operands; bool operator<(const OperandsSignature &O) const { @@ -130,7 +130,7 @@ struct OperandsSignature { return true; return false; } - + /// getWithoutImmCodes - Return a copy of this with any immediate codes forced /// to zero. OperandsSignature getWithoutImmCodes() const { @@ -142,46 +142,47 @@ struct OperandsSignature { Result.Operands.push_back(OpKind::getImm(0)); return Result; } - + void emitImmediatePredicate(raw_ostream &OS, ImmPredicateSet &ImmPredicates) { bool EmittedAnything = false; for (unsigned i = 0, e = Operands.size(); i != e; ++i) { if (!Operands[i].isImm()) continue; - + unsigned Code = Operands[i].getImmCode(); if (Code == 0) continue; - + if (EmittedAnything) OS << " &&\n "; - + TreePredicateFn PredFn = ImmPredicates.getPredicate(Code-1); - + // Emit the type check. OS << "VT == " << getEnumName(PredFn.getOrigPatFragRecord()->getTree(0)->getType(0)) << " && "; - - + + OS << PredFn.getFnName() << "(imm" << i <<')'; EmittedAnything = true; } } - + /// initialize - Examine the given pattern and initialize the contents /// of the Operands array accordingly. Return true if all the operands /// are supported, false otherwise. /// bool initialize(TreePatternNode *InstPatNode, const CodeGenTarget &Target, MVT::SimpleValueType VT, - ImmPredicateSet &ImmediatePredicates) { + ImmPredicateSet &ImmediatePredicates, + const CodeGenRegisterClass *OrigDstRC) { if (InstPatNode->isLeaf()) return false; - + if (InstPatNode->getOperator()->getName() == "imm") { Operands.push_back(OpKind::getImm(0)); return true; } - + if (InstPatNode->getOperator()->getName() == "fpimm") { Operands.push_back(OpKind::getFP()); return true; @@ -210,19 +211,19 @@ struct OperandsSignature { Record *Rec = PredFn.getOrigPatFragRecord()->getRecord(); if (Rec->getValueAsBit("FastIselShouldIgnore")) return false; - + PredNo = ImmediatePredicates.getIDFor(PredFn)+1; } - + // Handle unmatched immediate sizes here. //if (Op->getType(0) != VT) // return false; - + Operands.push_back(OpKind::getImm(PredNo)); continue; } - + // For now, filter out any operand with a predicate. // For now, filter out any operand with multiple values. if (!Op->getPredicateFns().empty() || Op->getNumTypes() != 1) @@ -236,7 +237,7 @@ struct OperandsSignature { // For now, ignore other non-leaf nodes. return false; } - + assert(Op->hasTypeSet(0) && "Type infererence not done?"); // For now, all the operands must have the same type (if they aren't @@ -249,7 +250,7 @@ struct OperandsSignature { if (!OpDI) return false; Record *OpLeafRec = OpDI->getDef(); - + // For now, the only other thing we accept is register operands. const CodeGenRegisterClass *RC = 0; if (OpLeafRec->isSubClassOf("RegisterOperand")) @@ -258,7 +259,9 @@ struct OperandsSignature { RC = &Target.getRegisterClass(OpLeafRec); else if (OpLeafRec->isSubClassOf("Register")) RC = Target.getRegBank().getRegClassForRegister(OpLeafRec); - else + else if (OpLeafRec->isSubClassOf("ValueType")) { + RC = OrigDstRC; + } else return false; // For now, this needs to be a register class of some sort. @@ -372,7 +375,7 @@ class FastISelMap { std::map<OperandsSignature, std::vector<OperandsSignature> > SignaturesWithConstantForms; - + std::string InstNS; ImmPredicateSet ImmediatePredicates; public: @@ -503,7 +506,8 @@ void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) { // Check all the operands. OperandsSignature Operands; - if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates)) + if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates, + DstRC)) continue; std::vector<std::string>* PhysRegInputs = new std::vector<std::string>(); @@ -547,13 +551,13 @@ void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) { SubRegNo, PhysRegInputs }; - + if (SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck)) PrintFatalError(Pattern.getSrcRecord()->getLoc(), "Duplicate record in FastISel table!"); SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo; - + // If any of the operands were immediates with predicates on them, strip // them down to a signature that doesn't have predicates so that we can // associate them with the stripped predicate version. @@ -567,14 +571,14 @@ void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) { void FastISelMap::printImmediatePredicates(raw_ostream &OS) { if (ImmediatePredicates.begin() == ImmediatePredicates.end()) return; - + OS << "\n// FastEmit Immediate Predicate functions.\n"; for (ImmPredicateSet::iterator I = ImmediatePredicates.begin(), E = ImmediatePredicates.end(); I != E; ++I) { OS << "static bool " << I->getFnName() << "(int64_t Imm) {\n"; OS << I->getImmediatePredicateCode() << "\n}\n"; } - + OS << "\n\n"; } @@ -800,11 +804,11 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { OS << ", "; Operands.PrintParameters(OS); OS << ") {\n"; - - // If there are any forms of this signature available that operand on - // constrained forms of the immediate (e.g. 32-bit sext immediate in a + + // If there are any forms of this signature available that operate on + // constrained forms of the immediate (e.g., 32-bit sext immediate in a // 64-bit operand), check them first. - + std::map<OperandsSignature, std::vector<OperandsSignature> >::iterator MI = SignaturesWithConstantForms.find(Operands); if (MI != SignaturesWithConstantForms.end()) { @@ -812,7 +816,7 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { std::sort(MI->second.begin(), MI->second.end()); MI->second.erase(std::unique(MI->second.begin(), MI->second.end()), MI->second.end()); - + // Check each in order it was seen. It would be nice to have a good // relative ordering between them, but we're not going for optimality // here. @@ -827,11 +831,11 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { MI->second[i].PrintArguments(OS); OS << "))\n return Reg;\n\n"; } - + // Done with this, remove it. SignaturesWithConstantForms.erase(MI); } - + OS << " switch (Opcode) {\n"; for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end(); I != E; ++I) { @@ -851,7 +855,7 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { OS << "}\n"; OS << "\n"; } - + // TODO: SignaturesWithConstantForms should be empty here. } diff --git a/contrib/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp b/contrib/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp index 0c3017f..87d18cd 100644 --- a/contrib/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp +++ b/contrib/llvm/utils/TableGen/FixedLenDecoderEmitter.cpp @@ -879,15 +879,20 @@ emitPredicateFunction(formatted_raw_ostream &OS, PredicateSet &Predicates, OS.indent(Indentation) << "static bool checkDecoderPredicate(unsigned Idx, " << "uint64_t Bits) {\n"; Indentation += 2; - OS.indent(Indentation) << "switch (Idx) {\n"; - OS.indent(Indentation) << "default: llvm_unreachable(\"Invalid index!\");\n"; - unsigned Index = 0; - for (PredicateSet::const_iterator I = Predicates.begin(), E = Predicates.end(); - I != E; ++I, ++Index) { - OS.indent(Indentation) << "case " << Index << ":\n"; - OS.indent(Indentation+2) << "return (" << *I << ");\n"; + if (!Predicates.empty()) { + OS.indent(Indentation) << "switch (Idx) {\n"; + OS.indent(Indentation) << "default: llvm_unreachable(\"Invalid index!\");\n"; + unsigned Index = 0; + for (PredicateSet::const_iterator I = Predicates.begin(), E = Predicates.end(); + I != E; ++I, ++Index) { + OS.indent(Indentation) << "case " << Index << ":\n"; + OS.indent(Indentation+2) << "return (" << *I << ");\n"; + } + OS.indent(Indentation) << "}\n"; + } else { + // No case statement to emit + OS.indent(Indentation) << "llvm_unreachable(\"Invalid index!\");\n"; } - OS.indent(Indentation) << "}\n"; Indentation -= 2; OS.indent(Indentation) << "}\n\n"; } @@ -2033,7 +2038,6 @@ void FixedLenDecoderEmitter::run(raw_ostream &o) { } DecoderTableInfo TableInfo; - std::set<unsigned> Sizes; for (std::map<std::pair<std::string, unsigned>, std::vector<unsigned> >::const_iterator I = OpcMap.begin(), E = OpcMap.end(); I != E; ++I) { diff --git a/contrib/llvm/utils/TableGen/InstrInfoEmitter.cpp b/contrib/llvm/utils/TableGen/InstrInfoEmitter.cpp index d6020a8..d3d9cc1 100644 --- a/contrib/llvm/utils/TableGen/InstrInfoEmitter.cpp +++ b/contrib/llvm/utils/TableGen/InstrInfoEmitter.cpp @@ -45,11 +45,26 @@ private: void emitEnums(raw_ostream &OS); typedef std::map<std::vector<std::string>, unsigned> OperandInfoMapTy; + + /// The keys of this map are maps which have OpName enum values as their keys + /// and instruction operand indices as their values. The values of this map + /// are lists of instruction names. + typedef std::map<std::map<unsigned, unsigned>, + std::vector<std::string> > OpNameMapTy; + typedef std::map<std::string, unsigned>::iterator StrUintMapIter; void emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map<std::vector<Record*>, unsigned> &EL, const OperandInfoMapTy &OpInfo, raw_ostream &OS); + void emitOperandTypesEnum(raw_ostream &OS, const CodeGenTarget &Target); + void initOperandMapData( + const std::vector<const CodeGenInstruction *> NumberedInstructions, + const std::string &Namespace, + std::map<std::string, unsigned> &Operands, + OpNameMapTy &OperandMap); + void emitOperandNameMappings(raw_ostream &OS, const CodeGenTarget &Target, + const std::vector<const CodeGenInstruction*> &NumberedInstructions); // Operand information. void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs); @@ -118,8 +133,8 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { Res += "|(1<<MCOI::LookupPtrRegClass)"; // Predicate operands. Check to see if the original unexpanded operand - // was of type PredicateOperand. - if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand")) + // was of type PredicateOp. + if (Inst.Operands[i].Rec->isSubClassOf("PredicateOp")) Res += "|(1<<MCOI::Predicate)"; // Optional def operands. Check to see if the original unexpanded operand @@ -176,6 +191,155 @@ void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS, } } + +/// Initialize data structures for generating operand name mappings. +/// +/// \param Operands [out] A map used to generate the OpName enum with operand +/// names as its keys and operand enum values as its values. +/// \param OperandMap [out] A map for representing the operand name mappings for +/// each instructions. This is used to generate the OperandMap table as +/// well as the getNamedOperandIdx() function. +void InstrInfoEmitter::initOperandMapData( + const std::vector<const CodeGenInstruction *> NumberedInstructions, + const std::string &Namespace, + std::map<std::string, unsigned> &Operands, + OpNameMapTy &OperandMap) { + + unsigned NumOperands = 0; + for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { + const CodeGenInstruction *Inst = NumberedInstructions[i]; + if (!Inst->TheDef->getValueAsBit("UseNamedOperandTable")) { + continue; + } + std::map<unsigned, unsigned> OpList; + for (unsigned j = 0, je = Inst->Operands.size(); j != je; ++j) { + const CGIOperandList::OperandInfo &Info = Inst->Operands[j]; + StrUintMapIter I = Operands.find(Info.Name); + + if (I == Operands.end()) { + I = Operands.insert(Operands.begin(), + std::pair<std::string, unsigned>(Info.Name, NumOperands++)); + } + OpList[I->second] = Info.MIOperandNo; + } + OperandMap[OpList].push_back(Namespace + "::" + Inst->TheDef->getName()); + } +} + +/// Generate a table and function for looking up the indices of operands by +/// name. +/// +/// This code generates: +/// - An enum in the llvm::TargetNamespace::OpName namespace, with one entry +/// for each operand name. +/// - A 2-dimensional table called OperandMap for mapping OpName enum values to +/// operand indices. +/// - A function called getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) +/// for looking up the operand index for an instruction, given a value from +/// OpName enum +void InstrInfoEmitter::emitOperandNameMappings(raw_ostream &OS, + const CodeGenTarget &Target, + const std::vector<const CodeGenInstruction*> &NumberedInstructions) { + + const std::string &Namespace = Target.getInstNamespace(); + std::string OpNameNS = "OpName"; + // Map of operand names to their enumeration value. This will be used to + // generate the OpName enum. + std::map<std::string, unsigned> Operands; + OpNameMapTy OperandMap; + + initOperandMapData(NumberedInstructions, Namespace, Operands, OperandMap); + + OS << "#ifdef GET_INSTRINFO_OPERAND_ENUM\n"; + OS << "#undef GET_INSTRINFO_OPERAND_ENUM\n"; + OS << "namespace llvm {"; + OS << "namespace " << Namespace << " {\n"; + OS << "namespace " << OpNameNS << " { \n"; + OS << "enum {\n"; + for (StrUintMapIter i = Operands.begin(), e = Operands.end(); i != e; ++i) + OS << " " << i->first << " = " << i->second << ",\n"; + + OS << "OPERAND_LAST"; + OS << "\n};\n"; + OS << "} // End namespace OpName\n"; + OS << "} // End namespace " << Namespace << "\n"; + OS << "} // End namespace llvm\n"; + OS << "#endif //GET_INSTRINFO_OPERAND_ENUM\n"; + + OS << "#ifdef GET_INSTRINFO_NAMED_OPS\n"; + OS << "#undef GET_INSTRINFO_NAMED_OPS\n"; + OS << "namespace llvm {"; + OS << "namespace " << Namespace << " {\n"; + OS << "int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx) {\n"; + if (!Operands.empty()) { + OS << " static const int16_t OperandMap [][" << Operands.size() + << "] = {\n"; + for (OpNameMapTy::iterator i = OperandMap.begin(), e = OperandMap.end(); + i != e; ++i) { + const std::map<unsigned, unsigned> &OpList = i->first; + OS << "{"; + + // Emit a row of the OperandMap table + for (unsigned ii = 0, ie = Operands.size(); ii != ie; ++ii) + OS << (OpList.count(ii) == 0 ? -1 : (int)OpList.find(ii)->second) + << ", "; + + OS << "},\n"; + } + OS << "};\n"; + + OS << " switch(Opcode) {\n"; + unsigned TableIndex = 0; + for (OpNameMapTy::iterator i = OperandMap.begin(), e = OperandMap.end(); + i != e; ++i) { + std::vector<std::string> &OpcodeList = i->second; + + for (unsigned ii = 0, ie = OpcodeList.size(); ii != ie; ++ii) + OS << " case " << OpcodeList[ii] << ":\n"; + + OS << " return OperandMap[" << TableIndex++ << "][NamedIdx];\n"; + } + OS << " default: return -1;\n"; + OS << " }\n"; + } else { + // There are no operands, so no need to emit anything + OS << " return -1;\n"; + } + OS << "}\n"; + OS << "} // End namespace " << Namespace << "\n"; + OS << "} // End namespace llvm\n"; + OS << "#endif //GET_INSTRINFO_NAMED_OPS\n"; + +} + +/// Generate an enum for all the operand types for this target, under the +/// llvm::TargetNamespace::OpTypes namespace. +/// Operand types are all definitions derived of the Operand Target.td class. +void InstrInfoEmitter::emitOperandTypesEnum(raw_ostream &OS, + const CodeGenTarget &Target) { + + const std::string &Namespace = Target.getInstNamespace(); + std::vector<Record *> Operands = Records.getAllDerivedDefinitions("Operand"); + + OS << "\n#ifdef GET_INSTRINFO_OPERAND_TYPES_ENUM\n"; + OS << "#undef GET_INSTRINFO_OPERAND_TYPES_ENUM\n"; + OS << "namespace llvm {"; + OS << "namespace " << Namespace << " {\n"; + OS << "namespace OpTypes { \n"; + OS << "enum OperandType {\n"; + + for (unsigned oi = 0, oe = Operands.size(); oi != oe; ++oi) { + if (!Operands[oi]->isAnonymous()) + OS << " " << Operands[oi]->getName() << " = " << oi << ",\n"; + } + + OS << " OPERAND_TYPE_LIST_END" << "\n};\n"; + OS << "} // End namespace OpTypes\n"; + OS << "} // End namespace " << Namespace << "\n"; + OS << "} // End namespace llvm\n"; + OS << "#endif // GET_INSTRINFO_OPERAND_TYPES_ENUM\n"; +} + //===----------------------------------------------------------------------===// // Main Output. //===----------------------------------------------------------------------===// @@ -273,13 +437,14 @@ void InstrInfoEmitter::run(raw_ostream &OS) { OS << "namespace llvm {\n"; OS << "struct " << ClassName << " : public TargetInstrInfo {\n" << " explicit " << ClassName << "(int SO = -1, int DO = -1);\n" + << " virtual ~" << ClassName << "();\n" << "};\n"; OS << "} // End llvm namespace \n"; OS << "#endif // GET_INSTRINFO_HEADER\n\n"; - OS << "\n#ifdef GET_INSTRINFO_CTOR\n"; - OS << "#undef GET_INSTRINFO_CTOR\n"; + OS << "\n#ifdef GET_INSTRINFO_CTOR_DTOR\n"; + OS << "#undef GET_INSTRINFO_CTOR_DTOR\n"; OS << "namespace llvm {\n"; OS << "extern const MCInstrDesc " << TargetName << "Insts[];\n"; @@ -289,10 +454,15 @@ void InstrInfoEmitter::run(raw_ostream &OS) { << " : TargetInstrInfo(SO, DO) {\n" << " InitMCInstrInfo(" << TargetName << "Insts, " << TargetName << "InstrNameIndices, " << TargetName << "InstrNameData, " - << NumberedInstructions.size() << ");\n}\n"; + << NumberedInstructions.size() << ");\n}\n" + << ClassName << "::~" << ClassName << "() {}\n"; OS << "} // End llvm namespace \n"; - OS << "#endif // GET_INSTRINFO_CTOR\n\n"; + OS << "#endif // GET_INSTRINFO_CTOR_DTOR\n\n"; + + emitOperandNameMappings(OS, Target, NumberedInstructions); + + emitOperandTypesEnum(OS, Target); } void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, @@ -377,6 +547,19 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, else OS << "OperandInfo" << OpInfo.find(OperandInfo)->second; + CodeGenTarget &Target = CDP.getTargetInfo(); + if (Inst.HasComplexDeprecationPredicate) + // Emit a function pointer to the complex predicate method. + OS << ",0" + << ",&get" << Inst.DeprecatedReason << "DeprecationInfo"; + else if (!Inst.DeprecatedReason.empty()) + // Emit the Subtarget feature. + OS << "," << Target.getInstNamespace() << "::" << Inst.DeprecatedReason + << ",0"; + else + // Instruction isn't deprecated. + OS << ",0,0"; + OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n"; } @@ -408,7 +591,15 @@ void InstrInfoEmitter::emitEnums(raw_ostream &OS) { << "\t= " << i << ",\n"; } OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n"; - OS << " };\n}\n"; + OS << " };\n"; + OS << "namespace Sched {\n"; + OS << " enum {\n"; + for (unsigned i = 0, e = SchedModels.numInstrSchedClasses(); i != e; ++i) { + OS << " " << SchedModels.getSchedClass(i).Name + << "\t= " << i << ",\n"; + } + OS << " SCHED_LIST_END = " << SchedModels.numInstrSchedClasses() << "\n"; + OS << " };\n}\n}\n"; OS << "} // End llvm namespace \n"; OS << "#endif // GET_INSTRINFO_ENUM\n\n"; diff --git a/contrib/llvm/utils/TableGen/IntrinsicEmitter.cpp b/contrib/llvm/utils/TableGen/IntrinsicEmitter.cpp index df4d847..8f137f8 100644 --- a/contrib/llvm/utils/TableGen/IntrinsicEmitter.cpp +++ b/contrib/llvm/utils/TableGen/IntrinsicEmitter.cpp @@ -84,10 +84,10 @@ void IntrinsicEmitter::run(raw_ostream &OS) { // Emit the function name recognizer. EmitFnNameRecognizer(Ints, OS); - + // Emit the intrinsic declaration generator. EmitGenerator(Ints, OS); - + // Emit the intrinsic parameter attributes. EmitAttributes(Ints, OS); @@ -125,35 +125,53 @@ void IntrinsicEmitter::EmitEnumInfo(const std::vector<CodeGenIntrinsic> &Ints, for (unsigned i = 0, e = Ints.size(); i != e; ++i) { OS << " " << Ints[i].EnumName; OS << ((i != e-1) ? ", " : " "); - OS << std::string(40-Ints[i].EnumName.size(), ' ') + OS << std::string(40-Ints[i].EnumName.size(), ' ') << "// " << Ints[i].Name << "\n"; } OS << "#endif\n\n"; } +struct IntrinsicNameSorter { + IntrinsicNameSorter(const std::vector<CodeGenIntrinsic> &I) + : Ints(I) {} + + // Sort in reverse order of intrinsic name so "abc.def" appears after + // "abd.def.ghi" in the overridden name matcher + bool operator()(unsigned i, unsigned j) { + return Ints[i].Name > Ints[j].Name; + } + +private: + const std::vector<CodeGenIntrinsic> &Ints; +}; + void IntrinsicEmitter:: -EmitFnNameRecognizer(const std::vector<CodeGenIntrinsic> &Ints, +EmitFnNameRecognizer(const std::vector<CodeGenIntrinsic> &Ints, raw_ostream &OS) { // Build a 'first character of function name' -> intrinsic # mapping. std::map<char, std::vector<unsigned> > IntMapping; for (unsigned i = 0, e = Ints.size(); i != e; ++i) IntMapping[Ints[i].Name[5]].push_back(i); - + OS << "// Function name -> enum value recognizer code.\n"; OS << "#ifdef GET_FUNCTION_RECOGNIZER\n"; OS << " StringRef NameR(Name+6, Len-6); // Skip over 'llvm.'\n"; OS << " switch (Name[5]) { // Dispatch on first letter.\n"; OS << " default: break;\n"; + IntrinsicNameSorter Sorter(Ints); // Emit the intrinsic matching stuff by first letter. for (std::map<char, std::vector<unsigned> >::iterator I = IntMapping.begin(), E = IntMapping.end(); I != E; ++I) { OS << " case '" << I->first << "':\n"; std::vector<unsigned> &IntList = I->second; + // Sort intrinsics in reverse order of their names + std::sort(IntList.begin(), IntList.end(), Sorter); + // Emit all the overloaded intrinsics first, build a table of the // non-overloaded ones. std::vector<StringMatcher::StringPair> MatchTable; - + for (unsigned i = 0, e = IntList.size(); i != e; ++i) { unsigned IntNo = IntList[i]; std::string Result = "return " + TargetPrefix + "Intrinsic::" + @@ -170,18 +188,18 @@ EmitFnNameRecognizer(const std::vector<CodeGenIntrinsic> &Ints, OS << " if (NameR.startswith(\"" << TheStr << "\")) " << Result << '\n'; } - + // Emit the matcher logic for the fixed length strings. StringMatcher("NameR", MatchTable, OS).Emit(1); OS << " break; // end of '" << I->first << "' case.\n"; } - + OS << " }\n"; OS << "#endif\n\n"; } void IntrinsicEmitter:: -EmitIntrinsicToNameTable(const std::vector<CodeGenIntrinsic> &Ints, +EmitIntrinsicToNameTable(const std::vector<CodeGenIntrinsic> &Ints, raw_ostream &OS) { OS << "// Intrinsic ID to name table\n"; OS << "#ifdef GET_INTRINSIC_NAME_TABLE\n"; @@ -192,7 +210,7 @@ EmitIntrinsicToNameTable(const std::vector<CodeGenIntrinsic> &Ints, } void IntrinsicEmitter:: -EmitIntrinsicToOverloadTable(const std::vector<CodeGenIntrinsic> &Ints, +EmitIntrinsicToOverloadTable(const std::vector<CodeGenIntrinsic> &Ints, raw_ostream &OS) { OS << "// Intrinsic ID to overload bitset\n"; OS << "#ifdef GET_INTRINSIC_OVERLOAD_TABLE\n"; @@ -242,7 +260,9 @@ enum IIT_Info { IIT_STRUCT5 = 22, IIT_EXTEND_VEC_ARG = 23, IIT_TRUNC_VEC_ARG = 24, - IIT_ANYPTR = 25 + IIT_ANYPTR = 25, + IIT_V1 = 26, + IIT_VARARG = 27 }; @@ -259,7 +279,7 @@ static void EncodeFixedValueType(MVT::SimpleValueType VT, case 64: return Sig.push_back(IIT_I64); } } - + switch (VT) { default: PrintFatalError("unhandled MVT in intrinsic!"); case MVT::f16: return Sig.push_back(IIT_F16); @@ -269,16 +289,18 @@ static void EncodeFixedValueType(MVT::SimpleValueType VT, case MVT::x86mmx: return Sig.push_back(IIT_MMX); // MVT::OtherVT is used to mean the empty struct type here. case MVT::Other: return Sig.push_back(IIT_EMPTYSTRUCT); + // MVT::isVoid is used to represent varargs here. + case MVT::isVoid: return Sig.push_back(IIT_VARARG); } } #ifdef _MSC_VER #pragma optimize("",off) // MSVC 2010 optimizer can't deal with this function. -#endif +#endif static void EncodeFixedType(Record *R, std::vector<unsigned char> &ArgCodes, std::vector<unsigned char> &Sig) { - + if (R->isSubClassOf("LLVMMatchType")) { unsigned Number = R->getValueAsInt("Number"); assert(Number < ArgCodes.size() && "Invalid matching number!"); @@ -290,7 +312,7 @@ static void EncodeFixedType(Record *R, std::vector<unsigned char> &ArgCodes, Sig.push_back(IIT_ARG); return Sig.push_back((Number << 2) | ArgCodes[Number]); } - + MVT::SimpleValueType VT = getValueType(R->getValueAsDef("VT")); unsigned Tmp = 0; @@ -301,17 +323,17 @@ static void EncodeFixedType(Record *R, std::vector<unsigned char> &ArgCodes, case MVT::fAny: ++Tmp; // FALL THROUGH. case MVT::iAny: { // If this is an "any" valuetype, then the type is the type of the next - // type in the list specified to getIntrinsic(). + // type in the list specified to getIntrinsic(). Sig.push_back(IIT_ARG); - + // Figure out what arg # this is consuming, and remember what kind it was. unsigned ArgNo = ArgCodes.size(); ArgCodes.push_back(Tmp); - + // Encode what sort of argument it must be in the low 2 bits of the ArgNo. return Sig.push_back((ArgNo << 2) | Tmp); } - + case MVT::iPTR: { unsigned AddrSpace = 0; if (R->isSubClassOf("LLVMQualPointerType")) { @@ -327,18 +349,19 @@ static void EncodeFixedType(Record *R, std::vector<unsigned char> &ArgCodes, return EncodeFixedType(R->getValueAsDef("ElTy"), ArgCodes, Sig); } } - + if (EVT(VT).isVector()) { EVT VVT = VT; switch (VVT.getVectorNumElements()) { default: PrintFatalError("unhandled vector type width in intrinsic!"); + case 1: Sig.push_back(IIT_V1); break; case 2: Sig.push_back(IIT_V2); break; case 4: Sig.push_back(IIT_V4); break; case 8: Sig.push_back(IIT_V8); break; case 16: Sig.push_back(IIT_V16); break; case 32: Sig.push_back(IIT_V32); break; } - + return EncodeFixedValueType(VVT.getVectorElementType(). getSimpleVT().SimpleTy, Sig); } @@ -355,7 +378,7 @@ static void EncodeFixedType(Record *R, std::vector<unsigned char> &ArgCodes, static void ComputeFixedEncoding(const CodeGenIntrinsic &Int, std::vector<unsigned char> &TypeSig) { std::vector<unsigned char> ArgCodes; - + if (Int.IS.RetVTs.empty()) TypeSig.push_back(IIT_Done); else if (Int.IS.RetVTs.size() == 1 && @@ -370,11 +393,11 @@ static void ComputeFixedEncoding(const CodeGenIntrinsic &Int, case 5: TypeSig.push_back(IIT_STRUCT5); break; default: assert(0 && "Unhandled case in struct"); } - + for (unsigned i = 0, e = Int.IS.RetVTs.size(); i != e; ++i) EncodeFixedType(Int.IS.RetTypeDefs[i], ArgCodes, TypeSig); } - + for (unsigned i = 0, e = Int.IS.ParamTypeDefs.size(); i != e; ++i) EncodeFixedType(Int.IS.ParamTypeDefs[i], ArgCodes, TypeSig); } @@ -383,16 +406,16 @@ static void printIITEntry(raw_ostream &OS, unsigned char X) { OS << (unsigned)X; } -void IntrinsicEmitter::EmitGenerator(const std::vector<CodeGenIntrinsic> &Ints, +void IntrinsicEmitter::EmitGenerator(const std::vector<CodeGenIntrinsic> &Ints, raw_ostream &OS) { // If we can compute a 32-bit fixed encoding for this intrinsic, do so and // capture it in this vector, otherwise store a ~0U. std::vector<unsigned> FixedEncodings; - + SequenceToOffsetTable<std::vector<unsigned char> > LongEncodingTable; - + std::vector<unsigned char> TypeSig; - + // Compute the unique argument type info. for (unsigned i = 0, e = Ints.size(); i != e; ++i) { // Get the signature for the intrinsic. @@ -412,7 +435,7 @@ void IntrinsicEmitter::EmitGenerator(const std::vector<CodeGenIntrinsic> &Ints, } Result = (Result << 4) | TypeSig[e-i-1]; } - + // If this could be encoded into a 31-bit word, return it. if (!Failed && (Result >> 31) == 0) { FixedEncodings.push_back(Result); @@ -423,45 +446,45 @@ void IntrinsicEmitter::EmitGenerator(const std::vector<CodeGenIntrinsic> &Ints, // Otherwise, we're going to unique the sequence into the // LongEncodingTable, and use its offset in the 32-bit table instead. LongEncodingTable.add(TypeSig); - + // This is a placehold that we'll replace after the table is laid out. FixedEncodings.push_back(~0U); } - + LongEncodingTable.layout(); - + OS << "// Global intrinsic function declaration type table.\n"; OS << "#ifdef GET_INTRINSIC_GENERATOR_GLOBAL\n"; OS << "static const unsigned IIT_Table[] = {\n "; - + for (unsigned i = 0, e = FixedEncodings.size(); i != e; ++i) { if ((i & 7) == 7) OS << "\n "; - + // If the entry fit in the table, just emit it. if (FixedEncodings[i] != ~0U) { OS << "0x" << utohexstr(FixedEncodings[i]) << ", "; continue; } - + TypeSig.clear(); ComputeFixedEncoding(Ints[i], TypeSig); - + // Otherwise, emit the offset into the long encoding table. We emit it this // way so that it is easier to read the offset in the .def file. OS << "(1U<<31) | " << LongEncodingTable.get(TypeSig) << ", "; } - + OS << "0\n};\n\n"; - + // Emit the shared table of register lists. OS << "static const unsigned char IIT_LongEncodingTable[] = {\n"; if (!LongEncodingTable.empty()) LongEncodingTable.emit(OS, printIITEntry); OS << " 255\n};\n\n"; - + OS << "#endif\n\n"; // End of GET_INTRINSIC_GENERATOR_GLOBAL } @@ -549,7 +572,6 @@ EmitAttributes(const std::vector<CodeGenIntrinsic> &Ints, raw_ostream &OS) { OS << " AttributeSet AS[" << maxArgAttrs+1 << "];\n"; OS << " unsigned NumAttrs = 0;\n"; OS << " if (id != 0) {\n"; - OS << " SmallVector<Attribute::AttrKind, 8> AttrVec;\n"; OS << " switch(IntrinsicsToAttributesMap[id - "; if (TargetOnly) OS << "Intrinsic::num_intrinsics"; @@ -559,7 +581,7 @@ EmitAttributes(const std::vector<CodeGenIntrinsic> &Ints, raw_ostream &OS) { OS << " default: llvm_unreachable(\"Invalid attribute number\");\n"; for (UniqAttrMapTy::const_iterator I = UniqAttributes.begin(), E = UniqAttributes.end(); I != E; ++I) { - OS << " case " << I->second << ":\n"; + OS << " case " << I->second << ": {\n"; const CodeGenIntrinsic &intrinsic = *(I->first); @@ -572,54 +594,82 @@ EmitAttributes(const std::vector<CodeGenIntrinsic> &Ints, raw_ostream &OS) { while (ai != ae) { unsigned argNo = intrinsic.ArgumentAttributes[ai].first; - OS << " AttrVec.clear();\n"; + OS << " const Attribute::AttrKind AttrParam" << argNo + 1 <<"[]= {"; + bool addComma = false; do { switch (intrinsic.ArgumentAttributes[ai].second) { case CodeGenIntrinsic::NoCapture: - OS << " AttrVec.push_back(Attribute::NoCapture);\n"; + if (addComma) + OS << ","; + OS << "Attribute::NoCapture"; + addComma = true; + break; + case CodeGenIntrinsic::ReadOnly: + if (addComma) + OS << ","; + OS << "Attribute::ReadOnly"; + addComma = true; + break; + case CodeGenIntrinsic::ReadNone: + if (addComma) + OS << ","; + OS << "Attributes::ReadNone"; + addComma = true; break; } ++ai; } while (ai != ae && intrinsic.ArgumentAttributes[ai].first == argNo); - + OS << "};\n"; OS << " AS[" << numAttrs++ << "] = AttributeSet::get(C, " - << argNo+1 << ", AttrVec);\n"; + << argNo+1 << ", AttrParam" << argNo +1 << ");\n"; } } ModRefKind modRef = getModRefKind(intrinsic); if (!intrinsic.canThrow || modRef || intrinsic.isNoReturn) { - OS << " AttrVec.clear();\n"; - - if (!intrinsic.canThrow) - OS << " AttrVec.push_back(Attribute::NoUnwind);\n"; - if (intrinsic.isNoReturn) - OS << " AttrVec.push_back(Attribute::NoReturn);\n"; + OS << " const Attribute::AttrKind Atts[] = {"; + bool addComma = false; + if (!intrinsic.canThrow) { + OS << "Attribute::NoUnwind"; + addComma = true; + } + if (intrinsic.isNoReturn) { + if (addComma) + OS << ","; + OS << "Attribute::NoReturn"; + addComma = true; + } switch (modRef) { case MRK_none: break; case MRK_readonly: - OS << " AttrVec.push_back(Attribute::ReadOnly);\n"; + if (addComma) + OS << ","; + OS << "Attribute::ReadOnly"; break; case MRK_readnone: - OS << " AttrVec.push_back(Attribute::ReadNone);\n"; + if (addComma) + OS << ","; + OS << "Attribute::ReadNone"; break; } + OS << "};\n"; OS << " AS[" << numAttrs++ << "] = AttributeSet::get(C, " - << "AttributeSet::FunctionIndex, AttrVec);\n"; + << "AttributeSet::FunctionIndex, Atts);\n"; } if (numAttrs) { OS << " NumAttrs = " << numAttrs << ";\n"; OS << " break;\n"; + OS << " }\n"; } else { OS << " return AttributeSet();\n"; } } - + OS << " }\n"; OS << " }\n"; OS << " return AttributeSet::get(C, ArrayRef<AttributeSet>(AS, " @@ -668,9 +718,9 @@ EmitModRefBehavior(const std::vector<CodeGenIntrinsic> &Ints, raw_ostream &OS){ static void EmitTargetBuiltins(const std::map<std::string, std::string> &BIM, const std::string &TargetPrefix, raw_ostream &OS) { - + std::vector<StringMatcher::StringPair> Results; - + for (std::map<std::string, std::string>::const_iterator I = BIM.begin(), E = BIM.end(); I != E; ++I) { std::string ResultCode = @@ -681,9 +731,9 @@ static void EmitTargetBuiltins(const std::map<std::string, std::string> &BIM, StringMatcher("BuiltinName", Results, OS).Emit(); } - + void IntrinsicEmitter:: -EmitIntrinsicToGCCBuiltinMap(const std::vector<CodeGenIntrinsic> &Ints, +EmitIntrinsicToGCCBuiltinMap(const std::vector<CodeGenIntrinsic> &Ints, raw_ostream &OS) { typedef std::map<std::string, std::map<std::string, std::string> > BIMTy; BIMTy BuiltinMap; @@ -691,20 +741,20 @@ EmitIntrinsicToGCCBuiltinMap(const std::vector<CodeGenIntrinsic> &Ints, if (!Ints[i].GCCBuiltinName.empty()) { // Get the map for this target prefix. std::map<std::string, std::string> &BIM =BuiltinMap[Ints[i].TargetPrefix]; - + if (!BIM.insert(std::make_pair(Ints[i].GCCBuiltinName, Ints[i].EnumName)).second) PrintFatalError("Intrinsic '" + Ints[i].TheDef->getName() + "': duplicate GCC builtin name!"); } } - + OS << "// Get the LLVM intrinsic that corresponds to a GCC builtin.\n"; OS << "// This is used by the C front-end. The GCC builtin name is passed\n"; OS << "// in as BuiltinName, and a target prefix (e.g. 'ppc') is passed\n"; OS << "// in as TargetPrefix. The result is assigned to 'IntrinsicID'.\n"; OS << "#ifdef GET_LLVM_INTRINSIC_FOR_GCC_BUILTIN\n"; - + if (TargetOnly) { OS << "static " << TargetPrefix << "Intrinsic::ID " << "getIntrinsicForGCCBuiltin(const char " @@ -713,10 +763,10 @@ EmitIntrinsicToGCCBuiltinMap(const std::vector<CodeGenIntrinsic> &Ints, OS << "Intrinsic::ID Intrinsic::getIntrinsicForGCCBuiltin(const char " << "*TargetPrefixStr, const char *BuiltinNameStr) {\n"; } - + OS << " StringRef BuiltinName(BuiltinNameStr);\n"; OS << " StringRef TargetPrefix(TargetPrefixStr);\n\n"; - + // Note: this could emit significantly better code if we cared. for (BIMTy::iterator I = BuiltinMap.begin(), E = BuiltinMap.end();I != E;++I){ OS << " "; diff --git a/contrib/llvm/utils/TableGen/OptParserEmitter.cpp b/contrib/llvm/utils/TableGen/OptParserEmitter.cpp index 0c1f623..9c4daaf 100644 --- a/contrib/llvm/utils/TableGen/OptParserEmitter.cpp +++ b/contrib/llvm/utils/TableGen/OptParserEmitter.cpp @@ -13,18 +13,23 @@ #include "llvm/ADT/Twine.h" #include "llvm/TableGen/Record.h" #include "llvm/TableGen/TableGenBackend.h" +#include <cstring> +#include <cctype> #include <map> using namespace llvm; +// Ordering on Info. The logic should match with the consumer-side function in +// llvm/Option/OptTable.h. static int StrCmpOptionName(const char *A, const char *B) { - char a = *A, b = *B; + const char *X = A, *Y = B; + char a = tolower(*A), b = tolower(*B); while (a == b) { if (a == '\0') - return 0; + return strcmp(A, B); - a = *++A; - b = *++B; + a = tolower(*++X); + b = tolower(*++Y); } if (a == '\0') // A is a prefix of B. @@ -36,9 +41,9 @@ static int StrCmpOptionName(const char *A, const char *B) { return (a < b) ? -1 : 1; } -static int CompareOptionRecords(const void *Av, const void *Bv) { - const Record *A = *(const Record*const*) Av; - const Record *B = *(const Record*const*) Bv; +static int CompareOptionRecords(Record *const *Av, Record *const *Bv) { + const Record *A = *Av; + const Record *B = *Bv; // Sentinel options precede all others and are only ordered by precedence. bool ASent = A->getValueAsDef("Kind")->getValueAsBit("Sentinel"); @@ -50,7 +55,7 @@ static int CompareOptionRecords(const void *Av, const void *Bv) { if (!ASent) if (int Cmp = StrCmpOptionName(A->getValueAsString("Name").c_str(), B->getValueAsString("Name").c_str())) - return Cmp; + return Cmp; if (!ASent) { std::vector<std::string> APrefixes = A->getValueAsListOfStrings("Prefixes"); @@ -74,7 +79,7 @@ static int CompareOptionRecords(const void *Av, const void *Bv) { if (APrec == BPrec && A->getValueAsListOfStrings("Prefixes") == B->getValueAsListOfStrings("Prefixes")) { - PrintError(A->getLoc(), Twine("Option is equivilent to")); + PrintError(A->getLoc(), Twine("Option is equivalent to")); PrintError(B->getLoc(), Twine("Other defined here")); PrintFatalError("Equivalent Options found."); } @@ -178,7 +183,7 @@ void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) { OS << "INVALID"; // The other option arguments (unused for groups). - OS << ", INVALID, 0, 0"; + OS << ", INVALID, 0, 0, 0"; // The option help text. if (!isa<UnsetInit>(R.getValueInit("HelpText"))) { @@ -228,6 +233,21 @@ void EmitOptParser(RecordKeeper &Records, raw_ostream &OS) { else OS << "INVALID"; + // The option alias arguments (if any). + // Emitted as a \0 separated list in a string, e.g. ["foo", "bar"] + // would become "foo\0bar\0". Note that the compiler adds an implicit + // terminating \0 at the end. + OS << ", "; + std::vector<std::string> AliasArgs = R.getValueAsListOfStrings("AliasArgs"); + if (AliasArgs.size() == 0) { + OS << "0"; + } else { + OS << "\""; + for (size_t i = 0, e = AliasArgs.size(); i != e; ++i) + OS << AliasArgs[i] << "\\0"; + OS << "\""; + } + // The option flags. const ListInit *LI = R.getValueAsListInit("Flags"); if (LI->empty()) { diff --git a/contrib/llvm/utils/TableGen/RegisterInfoEmitter.cpp b/contrib/llvm/utils/TableGen/RegisterInfoEmitter.cpp index 1b5d90b..cc08df9 100644 --- a/contrib/llvm/utils/TableGen/RegisterInfoEmitter.cpp +++ b/contrib/llvm/utils/TableGen/RegisterInfoEmitter.cpp @@ -58,8 +58,6 @@ private: void EmitRegMappingTables(raw_ostream &o, const std::vector<CodeGenRegister*> &Regs, bool isCtor); - void EmitRegClasses(raw_ostream &OS, CodeGenTarget &Target); - void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, const std::string &ClassName); void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank, @@ -123,7 +121,7 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, OS << "}\n"; } - const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices(); + const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices(); // If the only definition is the default NoRegAltName, we don't need to // emit anything. if (RegAltNameIndices.size() > 1) { @@ -225,7 +223,7 @@ EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, << "getRegPressureSetName(unsigned Idx) const {\n" << " static const char *PressureNameTable[] = {\n"; for (unsigned i = 0; i < NumSets; ++i ) { - OS << " \"" << RegBank.getRegPressureSet(i).Name << "\",\n"; + OS << " \"" << RegBank.getRegSetAt(i).Name << "\",\n"; } OS << " 0 };\n" << " return PressureNameTable[Idx];\n" @@ -237,9 +235,9 @@ EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, << "getRegPressureSetLimit(unsigned Idx) const {\n" << " static const unsigned PressureLimitTable[] = {\n"; for (unsigned i = 0; i < NumSets; ++i ) { - const RegUnitSet &RegUnits = RegBank.getRegPressureSet(i); - OS << " " << RegBank.getRegUnitSetWeight(RegUnits.Units) - << ", \t// " << i << ": " << RegUnits.Name << "\n"; + const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); + OS << " " << RegUnits.Weight << ", \t// " << i << ": " + << RegUnits.Name << "\n"; } OS << " 0 };\n" << " return PressureLimitTable[Idx];\n" @@ -254,9 +252,15 @@ EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, for (unsigned i = 0, StartIdx = 0, e = NumRCUnitSets; i != e; ++i) { RCSetStarts[i] = StartIdx; ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i); + std::vector<unsigned> PSets; + PSets.reserve(PSetIDs.size()); for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(), PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) { - OS << *PSetI << ", "; + PSets.push_back(RegBank.getRegPressureSet(*PSetI).Order); + } + std::sort(PSets.begin(), PSets.end()); + for (unsigned j = 0, e = PSets.size(); j < e; ++j) { + OS << PSets[j] << ", "; ++StartIdx; } OS << "-1, \t// #" << RCSetStarts[i] << " "; @@ -266,7 +270,7 @@ EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank, OS << "inferred"; for (ArrayRef<unsigned>::iterator PSetI = PSetIDs.begin(), PSetE = PSetIDs.end(); PSetI != PSetE; ++PSetI) { - OS << "~" << RegBank.getRegPressureSet(*PSetI).Name; + OS << "~" << RegBank.getRegSetAt(*PSetI).Name; } } OS << "\n "; @@ -311,7 +315,7 @@ RegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS, const std::vector<CodeGenRegister*> &Regs, bool isCtor) { // Collect all information about dwarf register numbers - typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy; + typedef std::map<Record*, std::vector<int64_t>, LessRecordRegister> DwarfRegNumsMapTy; DwarfRegNumsMapTy DwarfRegNums; // First, just pull all provided information to the map @@ -703,22 +707,22 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); - // The lists of sub-registers, super-registers, and overlaps all go in the - // same array. That allows us to share suffixes. + ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices(); + // The lists of sub-registers and super-registers go in the same array. That + // allows us to share suffixes. typedef std::vector<const CodeGenRegister*> RegVec; // Differentially encoded lists. SequenceToOffsetTable<DiffVec> DiffSeqs; SmallVector<DiffVec, 4> SubRegLists(Regs.size()); SmallVector<DiffVec, 4> SuperRegLists(Regs.size()); - SmallVector<DiffVec, 4> OverlapLists(Regs.size()); SmallVector<DiffVec, 4> RegUnitLists(Regs.size()); SmallVector<unsigned, 4> RegUnitInitScale(Regs.size()); // Keep track of sub-register names as well. These are not differentially // encoded. typedef SmallVector<const CodeGenSubRegIndex*, 4> SubRegIdxVec; - SequenceToOffsetTable<SubRegIdxVec> SubRegIdxSeqs; + SequenceToOffsetTable<SubRegIdxVec, CodeGenSubRegIndex::Less> SubRegIdxSeqs; SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size()); SequenceToOffsetTable<std::string> RegStrings; @@ -747,15 +751,6 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, SuperRegList.begin(), SuperRegList.end()); DiffSeqs.add(SuperRegLists[i]); - // The list of overlaps doesn't need to have any particular order, and Reg - // itself must be omitted. - DiffVec &OverlapList = OverlapLists[i]; - CodeGenRegister::Set OSet; - Reg->computeOverlaps(OSet, RegBank); - OSet.erase(Reg); - diffEncode(OverlapList, Reg->EnumValue, OSet.begin(), OSet.end()); - DiffSeqs.add(OverlapList); - // Differentially encode the register unit list, seeded by register number. // First compute a scale factor that allows more diff-lists to be reused: // @@ -800,6 +795,19 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, SubRegIdxSeqs.emit(OS, printSubRegIndex); OS << "};\n\n"; + // Emit the table of sub-register index sizes. + OS << "extern const MCRegisterInfo::SubRegCoveredBits " + << TargetName << "SubRegIdxRanges[] = {\n"; + OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n"; + for (ArrayRef<CodeGenSubRegIndex*>::const_iterator + SRI = SubRegIndices.begin(), SRE = SubRegIndices.end(); + SRI != SRE; ++SRI) { + OS << " { " << (*SRI)->Offset << ", " + << (*SRI)->Size + << " },\t// " << (*SRI)->getName() << "\n"; + } + OS << "};\n\n"; + // Emit the string table. RegStrings.layout(); OS << "extern const char " << TargetName << "RegStrings[] = {\n"; @@ -808,13 +816,12 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[] = { // Descriptors\n"; - OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0 },\n"; + OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0 },\n"; // Emit the register descriptors now. for (unsigned i = 0, e = Regs.size(); i != e; ++i) { const CodeGenRegister *Reg = Regs[i]; OS << " { " << RegStrings.get(Reg->getName()) << ", " - << DiffSeqs.get(OverlapLists[i]) << ", " << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) << ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", " @@ -897,8 +904,6 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, OS << "};\n\n"; - ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices(); - EmitRegMappingTables(OS, Regs, false); // Emit Reg encoding table @@ -931,6 +936,7 @@ RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, << TargetName << "RegStrings, " << TargetName << "SubRegIdxLists, " << (SubRegIndices.size() + 1) << ",\n" + << TargetName << "SubRegIdxRanges, " << " " << TargetName << "RegEncodingTable);\n\n"; EmitRegMapping(OS, Regs, false); @@ -1084,7 +1090,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, // Compress the sub-reg index lists. typedef std::vector<const CodeGenSubRegIndex*> IdxList; SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size()); - SequenceToOffsetTable<IdxList> SuperRegIdxSeqs; + SequenceToOffsetTable<IdxList, CodeGenSubRegIndex::Less> SuperRegIdxSeqs; BitVector MaskBV(RegisterClasses.size()); for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { @@ -1262,6 +1268,8 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, OS << "extern const char " << TargetName << "RegStrings[];\n"; OS << "extern const uint16_t " << TargetName << "RegUnitRoots[][2];\n"; OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; + OS << "extern const MCRegisterInfo::SubRegCoveredBits " + << TargetName << "SubRegIdxRanges[];\n"; OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; EmitRegMappingTables(OS, Regs, true); @@ -1270,7 +1278,9 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC)\n" << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc" << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n" - << " SubRegIndexNameTable, SubRegIndexLaneMaskTable) {\n" + << " SubRegIndexNameTable, SubRegIndexLaneMaskTable, 0x"; + OS.write_hex(RegBank.CoveringLanes); + OS << ") {\n" << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size()+1 << ", RA, PC,\n " << TargetName << "MCRegisterClasses, " << RegisterClasses.size() << ",\n" @@ -1280,6 +1290,7 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, << " " << TargetName << "RegStrings,\n" << " " << TargetName << "SubRegIdxLists,\n" << " " << SubRegIndices.size() + 1 << ",\n" + << " " << TargetName << "SubRegIdxRanges,\n" << " " << TargetName << "RegEncodingTable);\n\n"; EmitRegMapping(OS, Regs, true); @@ -1303,9 +1314,21 @@ RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, OS << "0 };\n"; // Emit the *_RegMask bit mask of call-preserved registers. + BitVector Covered = RegBank.computeCoveredRegisters(*Regs); + + // Check for an optional OtherPreserved set. + // Add those registers to RegMask, but not to SaveList. + if (DagInit *OPDag = + dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) { + SetTheory::RecSet OPSet; + RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc()); + Covered |= RegBank.computeCoveredRegisters( + ArrayRef<Record*>(OPSet.begin(), OPSet.end())); + } + OS << "static const uint32_t " << CSRSet->getName() << "_RegMask[] = { "; - printBitVectorAsHex(OS, RegBank.computeCoveredRegisters(*Regs), 32); + printBitVectorAsHex(OS, Covered, 32); OS << "};\n"; } OS << "\n\n"; diff --git a/contrib/llvm/utils/TableGen/SequenceToOffsetTable.h b/contrib/llvm/utils/TableGen/SequenceToOffsetTable.h index fcda233..e6ab664 100644 --- a/contrib/llvm/utils/TableGen/SequenceToOffsetTable.h +++ b/contrib/llvm/utils/TableGen/SequenceToOffsetTable.h @@ -21,6 +21,7 @@ #include <cassert> #include <cctype> #include <functional> +#include <map> #include <vector> namespace llvm { diff --git a/contrib/llvm/utils/TableGen/SetTheory.cpp b/contrib/llvm/utils/TableGen/SetTheory.cpp index 3e5c38c..ad3d7c7 100644 --- a/contrib/llvm/utils/TableGen/SetTheory.cpp +++ b/contrib/llvm/utils/TableGen/SetTheory.cpp @@ -27,14 +27,16 @@ typedef SetTheory::RecVec RecVec; // (add a, b, ...) Evaluate and union all arguments. struct AddOp : public SetTheory::Operator { - void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, ArrayRef<SMLoc> Loc) { + virtual void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, + ArrayRef<SMLoc> Loc) { ST.evaluate(Expr->arg_begin(), Expr->arg_end(), Elts, Loc); } }; // (sub Add, Sub, ...) Set difference. struct SubOp : public SetTheory::Operator { - void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, ArrayRef<SMLoc> Loc) { + virtual void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, + ArrayRef<SMLoc> Loc) { if (Expr->arg_size() < 2) PrintFatalError(Loc, "Set difference needs at least two arguments: " + Expr->getAsString()); @@ -49,7 +51,8 @@ struct SubOp : public SetTheory::Operator { // (and S1, S2) Set intersection. struct AndOp : public SetTheory::Operator { - void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, ArrayRef<SMLoc> Loc) { + virtual void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, + ArrayRef<SMLoc> Loc) { if (Expr->arg_size() != 2) PrintFatalError(Loc, "Set intersection requires two arguments: " + Expr->getAsString()); @@ -68,7 +71,8 @@ struct SetIntBinOp : public SetTheory::Operator { RecSet &Set, int64_t N, RecSet &Elts, ArrayRef<SMLoc> Loc) =0; - void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, ArrayRef<SMLoc> Loc) { + virtual void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, + ArrayRef<SMLoc> Loc) { if (Expr->arg_size() != 2) PrintFatalError(Loc, "Operator requires (Op Set, Int) arguments: " + Expr->getAsString()); @@ -84,9 +88,9 @@ struct SetIntBinOp : public SetTheory::Operator { // (shl S, N) Shift left, remove the first N elements. struct ShlOp : public SetIntBinOp { - void apply2(SetTheory &ST, DagInit *Expr, - RecSet &Set, int64_t N, - RecSet &Elts, ArrayRef<SMLoc> Loc) { + virtual void apply2(SetTheory &ST, DagInit *Expr, + RecSet &Set, int64_t N, + RecSet &Elts, ArrayRef<SMLoc> Loc) { if (N < 0) PrintFatalError(Loc, "Positive shift required: " + Expr->getAsString()); @@ -97,9 +101,9 @@ struct ShlOp : public SetIntBinOp { // (trunc S, N) Truncate after the first N elements. struct TruncOp : public SetIntBinOp { - void apply2(SetTheory &ST, DagInit *Expr, - RecSet &Set, int64_t N, - RecSet &Elts, ArrayRef<SMLoc> Loc) { + virtual void apply2(SetTheory &ST, DagInit *Expr, + RecSet &Set, int64_t N, + RecSet &Elts, ArrayRef<SMLoc> Loc) { if (N < 0) PrintFatalError(Loc, "Positive length required: " + Expr->getAsString()); @@ -115,9 +119,9 @@ struct RotOp : public SetIntBinOp { RotOp(bool Rev) : Reverse(Rev) {} - void apply2(SetTheory &ST, DagInit *Expr, - RecSet &Set, int64_t N, - RecSet &Elts, ArrayRef<SMLoc> Loc) { + virtual void apply2(SetTheory &ST, DagInit *Expr, + RecSet &Set, int64_t N, + RecSet &Elts, ArrayRef<SMLoc> Loc) { if (Reverse) N = -N; // N > 0 -> rotate left, N < 0 -> rotate right. @@ -134,9 +138,9 @@ struct RotOp : public SetIntBinOp { // (decimate S, N) Pick every N'th element of S. struct DecimateOp : public SetIntBinOp { - void apply2(SetTheory &ST, DagInit *Expr, - RecSet &Set, int64_t N, - RecSet &Elts, ArrayRef<SMLoc> Loc) { + virtual void apply2(SetTheory &ST, DagInit *Expr, + RecSet &Set, int64_t N, + RecSet &Elts, ArrayRef<SMLoc> Loc) { if (N <= 0) PrintFatalError(Loc, "Positive stride required: " + Expr->getAsString()); @@ -147,7 +151,8 @@ struct DecimateOp : public SetIntBinOp { // (interleave S1, S2, ...) Interleave elements of the arguments. struct InterleaveOp : public SetTheory::Operator { - void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, ArrayRef<SMLoc> Loc) { + virtual void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, + ArrayRef<SMLoc> Loc) { // Evaluate the arguments individually. SmallVector<RecSet, 4> Args(Expr->getNumArgs()); unsigned MaxSize = 0; @@ -165,7 +170,8 @@ struct InterleaveOp : public SetTheory::Operator { // (sequence "Format", From, To) Generate a sequence of records by name. struct SequenceOp : public SetTheory::Operator { - void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, ArrayRef<SMLoc> Loc) { + virtual void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts, + ArrayRef<SMLoc> Loc) { int Step = 1; if (Expr->arg_size() > 4) PrintFatalError(Loc, "Bad args to (sequence \"Format\", From, To): " + @@ -232,15 +238,16 @@ struct FieldExpander : public SetTheory::Expander { FieldExpander(StringRef fn) : FieldName(fn) {} - void expand(SetTheory &ST, Record *Def, RecSet &Elts) { + virtual void expand(SetTheory &ST, Record *Def, RecSet &Elts) { ST.evaluate(Def->getValueInit(FieldName), Elts, Def->getLoc()); } }; } // end anonymous namespace -void SetTheory::Operator::anchor() { } +// Pin the vtables to this file. +void SetTheory::Operator::anchor() {} +void SetTheory::Expander::anchor() {} -void SetTheory::Expander::anchor() { } SetTheory::SetTheory() { addOperator("add", new AddOp); diff --git a/contrib/llvm/utils/TableGen/StringToOffsetTable.h b/contrib/llvm/utils/TableGen/StringToOffsetTable.h deleted file mode 100644 index d94d3a2..0000000 --- a/contrib/llvm/utils/TableGen/StringToOffsetTable.h +++ /dev/null @@ -1,83 +0,0 @@ -//===- StringToOffsetTable.h - Emit a big concatenated string ---*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#ifndef TBLGEN_STRING_TO_OFFSET_TABLE_H -#define TBLGEN_STRING_TO_OFFSET_TABLE_H - -#include "llvm/ADT/SmallString.h" -#include "llvm/ADT/StringExtras.h" -#include "llvm/ADT/StringMap.h" -#include "llvm/Support/raw_ostream.h" -#include <cctype> - -namespace llvm { - -/// StringToOffsetTable - This class uniques a bunch of nul-terminated strings -/// and keeps track of their offset in a massive contiguous string allocation. -/// It can then output this string blob and use indexes into the string to -/// reference each piece. -class StringToOffsetTable { - StringMap<unsigned> StringOffset; - std::string AggregateString; -public: - - unsigned GetOrAddStringOffset(StringRef Str, bool appendZero = true) { - StringMapEntry<unsigned> &Entry = StringOffset.GetOrCreateValue(Str, -1U); - if (Entry.getValue() == -1U) { - // Add the string to the aggregate if this is the first time found. - Entry.setValue(AggregateString.size()); - AggregateString.append(Str.begin(), Str.end()); - if (appendZero) - AggregateString += '\0'; - } - - return Entry.getValue(); - } - - void EmitString(raw_ostream &O) { - // Escape the string. - SmallString<256> Str; - raw_svector_ostream(Str).write_escaped(AggregateString); - AggregateString = Str.str(); - - O << " \""; - unsigned CharsPrinted = 0; - for (unsigned i = 0, e = AggregateString.size(); i != e; ++i) { - if (CharsPrinted > 70) { - O << "\"\n \""; - CharsPrinted = 0; - } - O << AggregateString[i]; - ++CharsPrinted; - - // Print escape sequences all together. - if (AggregateString[i] != '\\') - continue; - - assert(i+1 < AggregateString.size() && "Incomplete escape sequence!"); - if (isdigit(AggregateString[i+1])) { - assert(isdigit(AggregateString[i+2]) && - isdigit(AggregateString[i+3]) && - "Expected 3 digit octal escape!"); - O << AggregateString[++i]; - O << AggregateString[++i]; - O << AggregateString[++i]; - CharsPrinted += 3; - } else { - O << AggregateString[++i]; - ++CharsPrinted; - } - } - O << "\""; - } -}; - -} // end namespace llvm - -#endif diff --git a/contrib/llvm/utils/TableGen/SubtargetEmitter.cpp b/contrib/llvm/utils/TableGen/SubtargetEmitter.cpp index 4918b1b..b9f9d06 100644 --- a/contrib/llvm/utils/TableGen/SubtargetEmitter.cpp +++ b/contrib/llvm/utils/TableGen/SubtargetEmitter.cpp @@ -634,16 +634,11 @@ void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel, Record *SuperDef = 0; unsigned SuperIdx = 0; unsigned NumUnits = 0; - bool IsBuffered = true; + int BufferSize = PRDef->getValueAsInt("BufferSize"); if (PRDef->isSubClassOf("ProcResGroup")) { RecVec ResUnits = PRDef->getValueAsListOfDefs("Resources"); for (RecIter RUI = ResUnits.begin(), RUE = ResUnits.end(); RUI != RUE; ++RUI) { - if (!NumUnits) - IsBuffered = (*RUI)->getValueAsBit("Buffered"); - else if(IsBuffered != (*RUI)->getValueAsBit("Buffered")) - PrintFatalError(PRDef->getLoc(), - "Mixing buffered and unbuffered resources."); NumUnits += (*RUI)->getValueAsInt("NumUnits"); } } @@ -655,7 +650,6 @@ void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel, SuperIdx = ProcModel.getProcResourceIdx(SuperDef); } NumUnits = PRDef->getValueAsInt("NumUnits"); - IsBuffered = PRDef->getValueAsBit("Buffered"); } // Emit the ProcResourceDesc if (i+1 == e) @@ -664,7 +658,7 @@ void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel, if (PRDef->getName().size() < 15) OS.indent(15 - PRDef->getName().size()); OS << NumUnits << ", " << SuperIdx << ", " - << IsBuffered << "}" << Sep << " // #" << i+1; + << BufferSize << "}" << Sep << " // #" << i+1; if (SuperDef) OS << ", Super=" << SuperDef->getName(); OS << "\n"; @@ -1200,11 +1194,15 @@ void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) { OS << "\n"; OS << "static const llvm::MCSchedModel " << PI->ModelName << "(\n"; EmitProcessorProp(OS, PI->ModelDef, "IssueWidth", ','); - EmitProcessorProp(OS, PI->ModelDef, "MinLatency", ','); + EmitProcessorProp(OS, PI->ModelDef, "MicroOpBufferSize", ','); EmitProcessorProp(OS, PI->ModelDef, "LoadLatency", ','); EmitProcessorProp(OS, PI->ModelDef, "HighLatency", ','); - EmitProcessorProp(OS, PI->ModelDef, "ILPWindow", ','); EmitProcessorProp(OS, PI->ModelDef, "MispredictPenalty", ','); + + OS << " " << (bool)(PI->ModelDef ? + PI->ModelDef->getValueAsBit("CompleteModel") : 0) + << ", // " << "CompleteModel\n"; + OS << " " << PI->Index << ", // Processor ID\n"; if (PI->hasInstrSchedModel()) OS << " " << PI->ModelName << "ProcResources" << ",\n" @@ -1340,11 +1338,11 @@ void SubtargetEmitter::EmitSchedModelHelpers(std::string ClassName, for (std::vector<CodeGenSchedTransition>::const_iterator TI = SC.Transitions.begin(), TE = SC.Transitions.end(); TI != TE; ++TI) { - OS << " if ("; if (*PI != 0 && !std::count(TI->ProcIndices.begin(), TI->ProcIndices.end(), *PI)) { continue; } + OS << " if ("; for (RecIter RI = TI->PredTerm.begin(), RE = TI->PredTerm.end(); RI != RE; ++RI) { if (RI != TI->PredTerm.begin()) diff --git a/contrib/llvm/utils/TableGen/TGValueTypes.cpp b/contrib/llvm/utils/TableGen/TGValueTypes.cpp index 3ac71a4..f4893f5 100644 --- a/contrib/llvm/utils/TableGen/TGValueTypes.cpp +++ b/contrib/llvm/utils/TableGen/TGValueTypes.cpp @@ -35,11 +35,15 @@ public: } Type(TypeKind K) : Kind(K) {} virtual unsigned getSizeInBits() const = 0; - virtual ~Type() {} + virtual ~Type(); }; +// Provide out-of-line definition to prevent weak vtable. +Type::~Type() {} + } +namespace { class ExtendedIntegerType : public Type { unsigned BitWidth; public: @@ -48,7 +52,7 @@ public: static bool classof(const Type *T) { return T->getKind() == TK_ExtendedIntegerType; } - unsigned getSizeInBits() const { + virtual unsigned getSizeInBits() const { return getBitWidth(); } unsigned getBitWidth() const { @@ -65,7 +69,7 @@ public: static bool classof(const Type *T) { return T->getKind() == TK_ExtendedVectorType; } - unsigned getSizeInBits() const { + virtual unsigned getSizeInBits() const { return getNumElements() * getElementType().getSizeInBits(); } EVT getElementType() const { @@ -75,6 +79,7 @@ public: return NumElements; } }; +} // end anonymous namespace static std::map<unsigned, const Type *> ExtendedIntegerTypeMap; diff --git a/contrib/llvm/utils/TableGen/X86DisassemblerTables.cpp b/contrib/llvm/utils/TableGen/X86DisassemblerTables.cpp index 40a0c1b..bdb4793 100644 --- a/contrib/llvm/utils/TableGen/X86DisassemblerTables.cpp +++ b/contrib/llvm/utils/TableGen/X86DisassemblerTables.cpp @@ -81,30 +81,146 @@ static inline bool inheritsFrom(InstructionContext child, case IC_64BIT_REXW_OPSIZE: return false; case IC_VEX: - return inheritsFrom(child, IC_VEX_W) || + return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) || + inheritsFrom(child, IC_VEX_W) || (VEX_LIG && inheritsFrom(child, IC_VEX_L)); case IC_VEX_XS: - return inheritsFrom(child, IC_VEX_W_XS) || + return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS)) || + inheritsFrom(child, IC_VEX_W_XS) || (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS)); case IC_VEX_XD: - return inheritsFrom(child, IC_VEX_W_XD) || + return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD)) || + inheritsFrom(child, IC_VEX_W_XD) || (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD)); case IC_VEX_OPSIZE: - return inheritsFrom(child, IC_VEX_W_OPSIZE) || + return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) || + inheritsFrom(child, IC_VEX_W_OPSIZE) || (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE)); case IC_VEX_W: + return VEX_LIG && inheritsFrom(child, IC_VEX_L_W); case IC_VEX_W_XS: + return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS); case IC_VEX_W_XD: + return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD); case IC_VEX_W_OPSIZE: - return false; + return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE); case IC_VEX_L: + return inheritsFrom(child, IC_VEX_L_W); case IC_VEX_L_XS: + return inheritsFrom(child, IC_VEX_L_W_XS); case IC_VEX_L_XD: - return false; + return inheritsFrom(child, IC_VEX_L_W_XD); case IC_VEX_L_OPSIZE: return inheritsFrom(child, IC_VEX_L_W_OPSIZE); + case IC_VEX_L_W: + case IC_VEX_L_W_XS: + case IC_VEX_L_W_XD: case IC_VEX_L_W_OPSIZE: return false; + case IC_EVEX: + return inheritsFrom(child, IC_EVEX_W) || + inheritsFrom(child, IC_EVEX_L_W); + case IC_EVEX_XS: + return inheritsFrom(child, IC_EVEX_W_XS) || + inheritsFrom(child, IC_EVEX_L_W_XS); + case IC_EVEX_XD: + return inheritsFrom(child, IC_EVEX_W_XD) || + inheritsFrom(child, IC_EVEX_L_W_XD); + case IC_EVEX_OPSIZE: + return inheritsFrom(child, IC_EVEX_W_OPSIZE) || + inheritsFrom(child, IC_EVEX_L_W_OPSIZE); + case IC_EVEX_W: + case IC_EVEX_W_XS: + case IC_EVEX_W_XD: + case IC_EVEX_W_OPSIZE: + return false; + case IC_EVEX_L: + case IC_EVEX_L_XS: + case IC_EVEX_L_XD: + case IC_EVEX_L_OPSIZE: + return false; + case IC_EVEX_L_W: + case IC_EVEX_L_W_XS: + case IC_EVEX_L_W_XD: + case IC_EVEX_L_W_OPSIZE: + return false; + case IC_EVEX_L2: + case IC_EVEX_L2_XS: + case IC_EVEX_L2_XD: + case IC_EVEX_L2_OPSIZE: + return false; + case IC_EVEX_L2_W: + case IC_EVEX_L2_W_XS: + case IC_EVEX_L2_W_XD: + case IC_EVEX_L2_W_OPSIZE: + return false; + case IC_EVEX_K: + return inheritsFrom(child, IC_EVEX_W_K) || + inheritsFrom(child, IC_EVEX_L_W_K); + case IC_EVEX_XS_K: + return inheritsFrom(child, IC_EVEX_W_XS_K) || + inheritsFrom(child, IC_EVEX_L_W_XS_K); + case IC_EVEX_XD_K: + return inheritsFrom(child, IC_EVEX_W_XD_K) || + inheritsFrom(child, IC_EVEX_L_W_XD_K); + case IC_EVEX_OPSIZE_K: + return inheritsFrom(child, IC_EVEX_W_OPSIZE_K) || + inheritsFrom(child, IC_EVEX_W_OPSIZE_K); + case IC_EVEX_W_K: + case IC_EVEX_W_XS_K: + case IC_EVEX_W_XD_K: + case IC_EVEX_W_OPSIZE_K: + return false; + case IC_EVEX_L_K: + case IC_EVEX_L_XS_K: + case IC_EVEX_L_XD_K: + case IC_EVEX_L_OPSIZE_K: + return false; + case IC_EVEX_W_KZ: + case IC_EVEX_W_XS_KZ: + case IC_EVEX_W_XD_KZ: + case IC_EVEX_W_OPSIZE_KZ: + return false; + case IC_EVEX_L_KZ: + case IC_EVEX_L_XS_KZ: + case IC_EVEX_L_XD_KZ: + case IC_EVEX_L_OPSIZE_KZ: + return false; + case IC_EVEX_L_W_K: + case IC_EVEX_L_W_XS_K: + case IC_EVEX_L_W_XD_K: + case IC_EVEX_L_W_OPSIZE_K: + case IC_EVEX_L_W_KZ: + case IC_EVEX_L_W_XS_KZ: + case IC_EVEX_L_W_XD_KZ: + case IC_EVEX_L_W_OPSIZE_KZ: + return false; + case IC_EVEX_L2_K: + case IC_EVEX_L2_B: + case IC_EVEX_L2_XS_K: + case IC_EVEX_L2_XD_K: + case IC_EVEX_L2_OPSIZE_K: + case IC_EVEX_L2_OPSIZE_B: + case IC_EVEX_L2_OPSIZE_K_B: + case IC_EVEX_L2_KZ: + case IC_EVEX_L2_XS_KZ: + case IC_EVEX_L2_XD_KZ: + case IC_EVEX_L2_OPSIZE_KZ: + case IC_EVEX_L2_OPSIZE_KZ_B: + return false; + case IC_EVEX_L2_W_K: + case IC_EVEX_L2_W_B: + case IC_EVEX_L2_W_XS_K: + case IC_EVEX_L2_W_XD_K: + case IC_EVEX_L2_W_OPSIZE_K: + case IC_EVEX_L2_W_OPSIZE_B: + case IC_EVEX_L2_W_OPSIZE_K_B: + case IC_EVEX_L2_W_KZ: + case IC_EVEX_L2_W_XS_KZ: + case IC_EVEX_L2_W_XD_KZ: + case IC_EVEX_L2_W_OPSIZE_KZ: + case IC_EVEX_L2_W_OPSIZE_KZ_B: + return false; default: llvm_unreachable("Unknown instruction class"); } @@ -123,10 +239,14 @@ static inline bool outranks(InstructionContext upper, assert(lower < IC_max); #define ENUM_ENTRY(n, r, d) r, +#define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \ + ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d) \ + ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d) static int ranks[IC_max] = { INSTRUCTION_CONTEXTS }; #undef ENUM_ENTRY +#undef ENUM_ENTRY_K_B return (ranks[upper] > ranks[lower]); } @@ -142,8 +262,12 @@ static inline const char* stringForContext(InstructionContext insnContext) { default: llvm_unreachable("Unhandled instruction class"); #define ENUM_ENTRY(n, r, d) case n: return #n; break; +#define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\ + ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\ + ENUM_ENTRY(n##_KZ_B, r, d) INSTRUCTION_CONTEXTS #undef ENUM_ENTRY +#undef ENUM_ENTRY_K_B } } @@ -170,35 +294,6 @@ static inline const char* stringForOperandEncoding(OperandEncoding encoding) { } } -void DisassemblerTables::emitOneID(raw_ostream &o, unsigned &i, InstrUID id, - bool addComma) const { - if (id) - o.indent(i * 2) << format("0x%hx", id); - else - o.indent(i * 2) << 0; - - if (addComma) - o << ", "; - else - o << " "; - - o << "/* "; - o << InstructionSpecifiers[id].name; - o << "*/"; - - o << "\n"; -} - -/// emitEmptyTable - Emits the modRMEmptyTable, which is used as a ID table by -/// all ModR/M decisions for instructions that are invalid for all possible -/// ModR/M byte values. -/// -/// @param o - The output stream on which to emit the table. -/// @param i - The indentation level for that output stream. -static void emitEmptyTable(raw_ostream &o, unsigned &i) { - o.indent(i * 2) << "0x0, /* EmptyTable */\n"; -} - /// getDecisionType - Determines whether a ModRM decision with 255 entries can /// be compacted by eliminating redundant information. /// @@ -298,6 +393,7 @@ DisassemblerTables::~DisassemblerTables() { void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2, unsigned &i1, unsigned &i2, + unsigned &ModRMTableNum, ModRMDecision &decision) const { static uint32_t sTableNumber = 0; static uint32_t sEntryNumber = 1; @@ -316,44 +412,56 @@ void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2, return; } - o1 << "/* Table" << sTableNumber << " */\n"; - i1++; + std::vector<unsigned> ModRMDecision; switch (dt) { default: llvm_unreachable("Unknown decision type"); case MODRM_ONEENTRY: - emitOneID(o1, i1, decision.instructionIDs[0], true); + ModRMDecision.push_back(decision.instructionIDs[0]); break; case MODRM_SPLITRM: - emitOneID(o1, i1, decision.instructionIDs[0x00], true); // mod = 0b00 - emitOneID(o1, i1, decision.instructionIDs[0xc0], true); // mod = 0b11 + ModRMDecision.push_back(decision.instructionIDs[0x00]); + ModRMDecision.push_back(decision.instructionIDs[0xc0]); break; case MODRM_SPLITREG: for (unsigned index = 0; index < 64; index += 8) - emitOneID(o1, i1, decision.instructionIDs[index], true); + ModRMDecision.push_back(decision.instructionIDs[index]); for (unsigned index = 0xc0; index < 256; index += 8) - emitOneID(o1, i1, decision.instructionIDs[index], true); + ModRMDecision.push_back(decision.instructionIDs[index]); break; case MODRM_SPLITMISC: for (unsigned index = 0; index < 64; index += 8) - emitOneID(o1, i1, decision.instructionIDs[index], true); + ModRMDecision.push_back(decision.instructionIDs[index]); for (unsigned index = 0xc0; index < 256; ++index) - emitOneID(o1, i1, decision.instructionIDs[index], true); + ModRMDecision.push_back(decision.instructionIDs[index]); break; case MODRM_FULL: for (unsigned index = 0; index < 256; ++index) - emitOneID(o1, i1, decision.instructionIDs[index], true); + ModRMDecision.push_back(decision.instructionIDs[index]); break; } - i1--; + unsigned &EntryNumber = ModRMTable[ModRMDecision]; + if (EntryNumber == 0) { + EntryNumber = ModRMTableNum; + + ModRMTableNum += ModRMDecision.size(); + o1 << "/* Table" << EntryNumber << " */\n"; + i1++; + for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(), + E = ModRMDecision.end(); I != E; ++I) { + o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* " + << InstructionSpecifiers[*I].name << " */\n"; + } + i1--; + } o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n"; i2++; o2.indent(i2) << stringForDecisionType(dt) << "," << "\n"; - o2.indent(i2) << sEntryNumber << " /* Table" << sTableNumber << " */\n"; + o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n"; i2--; o2.indent(i2) << "}"; @@ -387,6 +495,7 @@ void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2, void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2, unsigned &i1, unsigned &i2, + unsigned &ModRMTableNum, OpcodeDecision &decision) const { o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n"; i2++; @@ -398,7 +507,8 @@ void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2, o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n"; - emitModRMDecision(o1, o2, i1, i2, decision.modRMDecisions[index]); + emitModRMDecision(o1, o2, i1, i2, ModRMTableNum, + decision.modRMDecisions[index]); if (index < 255) o2 << ","; @@ -414,6 +524,7 @@ void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2, void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2, unsigned &i1, unsigned &i2, + unsigned &ModRMTableNum, ContextDecision &decision, const char* name) const { o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n"; @@ -427,7 +538,8 @@ void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2, o2 << " */"; o2 << "\n"; - emitOpcodeDecision(o1, o2, i1, i2, decision.opcodeDecisions[index]); + emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum, + decision.opcodeDecisions[index]); if (index + 1 < IC_max) o2 << ", "; @@ -533,6 +645,12 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const { if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) o << "IC_VEX_L_W_OPSIZE"; + else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD)) + o << "IC_VEX_L_W_XD"; + else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS)) + o << "IC_VEX_L_W_XS"; + else if ((index & ATTR_VEXL) && (index & ATTR_REXW)) + o << "IC_VEX_L_W"; else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE)) o << "IC_VEX_L_OPSIZE"; else if ((index & ATTR_VEXL) && (index & ATTR_XD)) @@ -610,13 +728,17 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const { } void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2, - unsigned &i1, unsigned &i2) const { - emitContextDecision(o1, o2, i1, i2, *Tables[0], ONEBYTE_STR); - emitContextDecision(o1, o2, i1, i2, *Tables[1], TWOBYTE_STR); - emitContextDecision(o1, o2, i1, i2, *Tables[2], THREEBYTE38_STR); - emitContextDecision(o1, o2, i1, i2, *Tables[3], THREEBYTE3A_STR); - emitContextDecision(o1, o2, i1, i2, *Tables[4], THREEBYTEA6_STR); - emitContextDecision(o1, o2, i1, i2, *Tables[5], THREEBYTEA7_STR); + unsigned &i1, unsigned &i2, + unsigned &ModRMTableNum) const { + emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR); + emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR); + emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR); + emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR); + emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], THREEBYTEA6_STR); + emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], THREEBYTEA7_STR); + emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOP8_MAP_STR); + emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[7], XOP9_MAP_STR); + emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[8], XOPA_MAP_STR); } void DisassemblerTables::emit(raw_ostream &o) const { @@ -635,11 +757,17 @@ void DisassemblerTables::emit(raw_ostream &o) const { emitContextTable(o, i2); o << "\n"; + unsigned ModRMTableNum = 0; + o << "static const InstrUID modRMTable[] = {\n"; i1++; - emitEmptyTable(o1, i1); + std::vector<unsigned> EmptyTable(1, 0); + ModRMTable[EmptyTable] = ModRMTableNum; + ModRMTableNum += EmptyTable.size(); + o1 << "/* EmptyTable */\n"; + o1.indent(i1 * 2) << "0x0,\n"; i1--; - emitContextDecisions(o1, o2, i1, i2); + emitContextDecisions(o1, o2, i1, i2, ModRMTableNum); o << o1.str(); o << " 0x0\n"; diff --git a/contrib/llvm/utils/TableGen/X86DisassemblerTables.h b/contrib/llvm/utils/TableGen/X86DisassemblerTables.h index 01aeaaf..bf8b127 100644 --- a/contrib/llvm/utils/TableGen/X86DisassemblerTables.h +++ b/contrib/llvm/utils/TableGen/X86DisassemblerTables.h @@ -20,6 +20,7 @@ #include "X86DisassemblerShared.h" #include "X86ModRMFilters.h" #include "llvm/Support/raw_ostream.h" +#include <map> #include <vector> namespace llvm { @@ -39,7 +40,14 @@ private: /// [3] three-byte opcodes of the form 0f 3a __ /// [4] three-byte opcodes of the form 0f a6 __ /// [5] three-byte opcodes of the form 0f a7 __ - ContextDecision* Tables[6]; + /// [6] XOP8 map opcode + /// [7] XOP9 map opcode + /// [8] XOPA map opcode + ContextDecision* Tables[9]; + + // Table of ModRM encodings. + typedef std::map<std::vector<unsigned>, unsigned> ModRMMapTy; + mutable ModRMMapTy ModRMTable; /// The instruction information table std::vector<InstructionSpecifier> InstructionSpecifiers; @@ -47,22 +55,6 @@ private: /// True if there are primary decode conflicts in the instruction set bool HasConflicts; - /// emitOneID - Emits a table entry for a single instruction entry, at the - /// innermost level of the structure hierarchy. The entry is printed out - /// in the format "nnnn, /* MNEMONIC */" where nnnn is the ID in decimal, - /// the comma is printed if addComma is true, and the menonic is the name - /// of the instruction as listed in the LLVM tables. - /// - /// @param o - The output stream to print the entry on. - /// @param i - The indentation level for o. - /// @param id - The unique ID of the instruction to print. - /// @param addComma - Whether or not to print a comma after the ID. True if - /// additional items will follow. - void emitOneID(raw_ostream &o, - uint32_t &i, - InstrUID id, - bool addComma) const; - /// emitModRMDecision - Emits a table of entries corresponding to a single /// ModR/M decision. Compacts the ModR/M decision if possible. ModR/M /// decisions are printed as: @@ -91,12 +83,11 @@ private: /// @param o2 - The output stream to print the decision structure to. /// @param i1 - The indentation level to use with stream o1. /// @param i2 - The indentation level to use with stream o2. + /// @param ModRMTableNum - next table number for adding to ModRMTable. /// @param decision - The ModR/M decision to emit. This decision has 256 /// entries - emitModRMDecision decides how to compact it. - void emitModRMDecision(raw_ostream &o1, - raw_ostream &o2, - uint32_t &i1, - uint32_t &i2, + void emitModRMDecision(raw_ostream &o1, raw_ostream &o2, + unsigned &i1, unsigned &i2, unsigned &ModRMTableNum, ModRMDecision &decision) const; /// emitOpcodeDecision - Emits an OpcodeDecision and all its subsidiary ModR/M @@ -120,12 +111,11 @@ private: /// @param o2 - The output stream for the decision structure itself. /// @param i1 - The indent level to use with stream o1. /// @param i2 - The indent level to use with stream o2. + /// @param ModRMTableNum - next table number for adding to ModRMTable. /// @param decision - The OpcodeDecision to emit along with its subsidiary /// structures. - void emitOpcodeDecision(raw_ostream &o1, - raw_ostream &o2, - uint32_t &i1, - uint32_t &i2, + void emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2, + unsigned &i1, unsigned &i2, unsigned &ModRMTableNum, OpcodeDecision &decision) const; /// emitContextDecision - Emits a ContextDecision and all its subsidiary @@ -155,15 +145,13 @@ private: /// @param o2 - The output stream to print the decision structure to. /// @param i1 - The indent level to use with stream o1. /// @param i2 - The indent level to use with stream o2. + /// @param ModRMTableNum - next table number for adding to ModRMTable. /// @param decision - The ContextDecision to emit along with its subsidiary /// structures. /// @param name - The name for the ContextDecision. - void emitContextDecision(raw_ostream &o1, - raw_ostream &o2, - uint32_t &i1, - uint32_t &i2, - ContextDecision &decision, - const char* name) const; + void emitContextDecision(raw_ostream &o1, raw_ostream &o2, + unsigned &i1, unsigned &i2, unsigned &ModRMTableNum, + ContextDecision &decision, const char* name) const; /// emitInstructionInfo - Prints the instruction specifier table, which has /// one entry for each instruction, and contains name and operand @@ -194,7 +182,7 @@ private: /// @param o - The output stream to which the instruction table should be /// written. /// @param i - The indent level for use with the stream. - void emitInstructionInfo(raw_ostream &o, uint32_t &i) const; + void emitInstructionInfo(raw_ostream &o, unsigned &i) const; /// emitContextTable - Prints the table that is used to translate from an /// instruction attribute mask to an instruction context. This table is @@ -220,10 +208,10 @@ private: /// @param o2 - The output stream to print the decision structures to. /// @param i1 - The indent level to use with stream o1. /// @param i2 - The indent level to use with stream o2. - void emitContextDecisions(raw_ostream &o1, - raw_ostream &o2, - uint32_t &i1, - uint32_t &i2) const; + /// @param ModRMTableNum - next table number for adding to ModRMTable. + void emitContextDecisions(raw_ostream &o1, raw_ostream &o2, + unsigned &i1, unsigned &i2, + unsigned &ModRMTableNum) const; /// setTableFields - Uses a ModRMFilter to set the appropriate entries in a /// ModRMDecision to refer to a particular instruction ID. diff --git a/contrib/llvm/utils/TableGen/X86RecognizableInstr.cpp b/contrib/llvm/utils/TableGen/X86RecognizableInstr.cpp index 46f2052..708e72d 100644 --- a/contrib/llvm/utils/TableGen/X86RecognizableInstr.cpp +++ b/contrib/llvm/utils/TableGen/X86RecognizableInstr.cpp @@ -79,7 +79,8 @@ namespace X86Local { DC = 7, DD = 8, DE = 9, DF = 10, XD = 11, XS = 12, T8 = 13, P_TA = 14, - A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19 + A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19, + XOP8 = 20, XOP9 = 21, XOPA = 22 }; } @@ -134,6 +135,10 @@ namespace X86Local { #define THREE_BYTE_38_EXTENSION_TABLES \ EXTENSION_TABLE(F3) +#define XOP9_MAP_EXTENSION_TABLES \ + EXTENSION_TABLE(01) \ + EXTENSION_TABLE(02) + using namespace X86Disassembler; /// needsModRMForDecode - Indicates whether a particular instruction requires a @@ -236,6 +241,11 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix"); HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix"); IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); + HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix"); + HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2"); + HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); + HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); + HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); HasLockPrefix = Rec->getValueAsBit("hasLockPrefix"); IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); @@ -295,15 +305,99 @@ void RecognizableInstr::processInstr(DisassemblerTables &tables, recogInstr.emitDecodePath(tables); } +#define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \ + (HasEVEX_K && HasEVEX_B ? n##_K_B : \ + (HasEVEX_KZ ? n##_KZ : \ + (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n))))) + InstructionContext RecognizableInstr::insnContext() const { InstructionContext insnContext; - if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) { + if (HasEVEXPrefix) { + if (HasVEX_LPrefix && HasEVEX_L2Prefix) { + errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n"; + llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled"); + } + // VEX_L & VEX_W + if (HasVEX_LPrefix && HasVEX_WPrefix) { + if (HasOpSizePrefix) + insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); + else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) + insnContext = EVEX_KB(IC_EVEX_L_W_XS); + else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD || + Prefix == X86Local::TAXD) + insnContext = EVEX_KB(IC_EVEX_L_W_XD); + else + insnContext = EVEX_KB(IC_EVEX_L_W); + } else if (HasVEX_LPrefix) { + // VEX_L + if (HasOpSizePrefix) + insnContext = EVEX_KB(IC_EVEX_L_OPSIZE); + else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) + insnContext = EVEX_KB(IC_EVEX_L_XS); + else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD || + Prefix == X86Local::TAXD) + insnContext = EVEX_KB(IC_EVEX_L_XD); + else + insnContext = EVEX_KB(IC_EVEX_L); + } + else if (HasEVEX_L2Prefix && HasVEX_WPrefix) { + // EVEX_L2 & VEX_W + if (HasOpSizePrefix) + insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); + else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) + insnContext = EVEX_KB(IC_EVEX_L2_W_XS); + else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD || + Prefix == X86Local::TAXD) + insnContext = EVEX_KB(IC_EVEX_L2_W_XD); + else + insnContext = EVEX_KB(IC_EVEX_L2_W); + } else if (HasEVEX_L2Prefix) { + // EVEX_L2 + if (HasOpSizePrefix) + insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE); + else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD || + Prefix == X86Local::TAXD) + insnContext = EVEX_KB(IC_EVEX_L2_XD); + else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) + insnContext = EVEX_KB(IC_EVEX_L2_XS); + else + insnContext = EVEX_KB(IC_EVEX_L2); + } + else if (HasVEX_WPrefix) { + // VEX_W + if (HasOpSizePrefix) + insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); + else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) + insnContext = EVEX_KB(IC_EVEX_W_XS); + else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD || + Prefix == X86Local::TAXD) + insnContext = EVEX_KB(IC_EVEX_W_XD); + else + insnContext = EVEX_KB(IC_EVEX_W); + } + // No L, no W + else if (HasOpSizePrefix) + insnContext = EVEX_KB(IC_EVEX_OPSIZE); + else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD || + Prefix == X86Local::TAXD) + insnContext = EVEX_KB(IC_EVEX_XD); + else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) + insnContext = EVEX_KB(IC_EVEX_XS); + else + insnContext = EVEX_KB(IC_EVEX); + /// eof EVEX + } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) { if (HasVEX_LPrefix && HasVEX_WPrefix) { if (HasOpSizePrefix) insnContext = IC_VEX_L_W_OPSIZE; + else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) + insnContext = IC_VEX_L_W_XS; + else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD || + Prefix == X86Local::TAXD) + insnContext = IC_VEX_L_W_XD; else - llvm_unreachable("Don't support VEX.L and VEX.W together"); + insnContext = IC_VEX_L_W; } else if (HasOpSizePrefix && HasVEX_LPrefix) insnContext = IC_VEX_L_OPSIZE; else if (HasOpSizePrefix && HasVEX_WPrefix) @@ -400,7 +494,8 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const { assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions"); if (Form == X86Local::Pseudo || - (IsCodeGenOnly && Name.find("_REV") == Name.npos)) + (IsCodeGenOnly && Name.find("_REV") == Name.npos && + Name.find("INC32") == Name.npos && Name.find("DEC32") == Name.npos)) return FILTER_STRONG; @@ -430,41 +525,24 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const { // Filter out alternate forms of AVX instructions if (Name.find("_alt") != Name.npos || - Name.find("XrYr") != Name.npos || - (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) || + (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos && Name.find("r64r8") == Name.npos) || Name.find("_64mr") != Name.npos || - Name.find("Xrr") != Name.npos || Name.find("rr64") != Name.npos) return FILTER_WEAK; // Special cases. - if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI") - return FILTER_WEAK; - if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI") - return FILTER_WEAK; - - if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos) - return FILTER_WEAK; - if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos) - return FILTER_WEAK; - if (Name.find("Fs") != Name.npos) - return FILTER_WEAK; if (Name == "PUSH64i16" || Name == "MOVPQI2QImr" || Name == "VMOVPQI2QImr" || - Name == "MMX_MOVD64rrv164" || - Name == "MOV64ri64i32" || - Name == "VMASKMOVDQU64" || - Name == "VEXTRACTPSrr64" || - Name == "VMOVQd64rr" || - Name == "VMOVQs64rr") + Name == "VMASKMOVDQU64") return FILTER_WEAK; - if (HasFROperands && Name.find("MOV") != Name.npos && - ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) || - (Name.find("to") != Name.npos))) - return FILTER_STRONG; + // XACQUIRE and XRELEASE reuse REPNE and REP respectively. + // For now, just prefer the REP versions. + if (Name == "XACQUIRE_PREFIX" || + Name == "XRELEASE_PREFIX") + return FILTER_WEAK; return FILTER_NORMAL; } @@ -635,6 +713,9 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { "Unexpected number of operands for MRMDestMemFrm"); HANDLE_OPERAND(memory) + if (HasEVEX_K) + HANDLE_OPERAND(writemaskRegister) + if (HasVEX_4VPrefix) // FIXME: In AVX, the register below becomes the one encoded // in ModRMVEX and the one above the one in the VEX.VVVV field @@ -659,6 +740,9 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { HANDLE_OPERAND(roRegister) + if (HasEVEX_K) + HANDLE_OPERAND(writemaskRegister) + if (HasVEX_4VPrefix) // FIXME: In AVX, the register below becomes the one encoded // in ModRMVEX and the one above the one in the VEX.VVVV field @@ -692,6 +776,9 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { HANDLE_OPERAND(roRegister) + if (HasEVEX_K) + HANDLE_OPERAND(writemaskRegister) + if (HasVEX_4VPrefix) // FIXME: In AVX, the register below becomes the one encoded // in ModRMVEX and the one above the one in the VEX.VVVV field @@ -717,17 +804,20 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { case X86Local::MRM5r: case X86Local::MRM6r: case X86Local::MRM7r: - // Operand 1 is a register operand in the R/M field. - // Operand 2 (optional) is an immediate or relocation. - // Operand 3 (optional) is an immediate. - if (HasVEX_4VPrefix) - assert(numPhysicalOperands <= 3 && - "Unexpected number of operands for MRMnRFrm with VEX_4V"); - else - assert(numPhysicalOperands <= 3 && - "Unexpected number of operands for MRMnRFrm"); + { + // Operand 1 is a register operand in the R/M field. + // Operand 2 (optional) is an immediate or relocation. + // Operand 3 (optional) is an immediate. + unsigned kOp = (HasEVEX_K) ? 1:0; + unsigned Op4v = (HasVEX_4VPrefix) ? 1:0; + if (numPhysicalOperands > 3 + kOp + Op4v) + llvm_unreachable("Unexpected number of operands for MRMnr"); + } if (HasVEX_4VPrefix) HANDLE_OPERAND(vvvvRegister) + + if (HasEVEX_K) + HANDLE_OPERAND(writemaskRegister) HANDLE_OPTIONAL(rmRegister) HANDLE_OPTIONAL(relocation) HANDLE_OPTIONAL(immediate) @@ -740,16 +830,19 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { case X86Local::MRM5m: case X86Local::MRM6m: case X86Local::MRM7m: - // Operand 1 is a memory operand (possibly SIB-extended) - // Operand 2 (optional) is an immediate or relocation. - if (HasVEX_4VPrefix) - assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && - "Unexpected number of operands for MRMnMFrm"); - else - assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && - "Unexpected number of operands for MRMnMFrm"); + { + // Operand 1 is a memory operand (possibly SIB-extended) + // Operand 2 (optional) is an immediate or relocation. + unsigned kOp = (HasEVEX_K) ? 1:0; + unsigned Op4v = (HasVEX_4VPrefix) ? 1:0; + if (numPhysicalOperands < 1 + kOp + Op4v || + numPhysicalOperands > 2 + kOp + Op4v) + llvm_unreachable("Unexpected number of operands for MRMnm"); + } if (HasVEX_4VPrefix) HANDLE_OPERAND(vvvvRegister) + if (HasEVEX_K) + HANDLE_OPERAND(writemaskRegister) HANDLE_OPERAND(memory) HANDLE_OPTIONAL(relocation) break; @@ -801,6 +894,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { uint8_t opcodeToSet = 0; switch (Prefix) { + default: llvm_unreachable("Invalid prefix!"); // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f case X86Local::XD: case X86Local::XS: @@ -914,6 +1008,63 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { filter = new DumbFilter(); opcodeToSet = Opcode; break; + case X86Local::XOP8: + opcodeType = XOP8_MAP; + if (needsModRMForDecode(Form)) + filter = new ModFilter(isRegFormat(Form)); + else + filter = new DumbFilter(); + opcodeToSet = Opcode; + break; + case X86Local::XOP9: + opcodeType = XOP9_MAP; + switch (Opcode) { + default: + if (needsModRMForDecode(Form)) + filter = new ModFilter(isRegFormat(Form)); + else + filter = new DumbFilter(); + break; +#define EXTENSION_TABLE(n) case 0x##n: + XOP9_MAP_EXTENSION_TABLES +#undef EXTENSION_TABLE + switch (Form) { + default: + llvm_unreachable("Unhandled XOP9 extended opcode"); + case X86Local::MRM0r: + case X86Local::MRM1r: + case X86Local::MRM2r: + case X86Local::MRM3r: + case X86Local::MRM4r: + case X86Local::MRM5r: + case X86Local::MRM6r: + case X86Local::MRM7r: + filter = new ExtendedFilter(true, Form - X86Local::MRM0r); + break; + case X86Local::MRM0m: + case X86Local::MRM1m: + case X86Local::MRM2m: + case X86Local::MRM3m: + case X86Local::MRM4m: + case X86Local::MRM5m: + case X86Local::MRM6m: + case X86Local::MRM7m: + filter = new ExtendedFilter(false, Form - X86Local::MRM0m); + break; + MRM_MAPPING + } // switch (Form) + break; + } // switch (Opcode) + opcodeToSet = Opcode; + break; + case X86Local::XOPA: + opcodeType = XOPA_MAP; + if (needsModRMForDecode(Form)) + filter = new ModFilter(isRegFormat(Form)); + else + filter = new DumbFilter(); + opcodeToSet = Opcode; + break; case X86Local::D8: case X86Local::D9: case X86Local::DA: @@ -934,7 +1085,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { opcodeToSet = 0xd8 + (Prefix - X86Local::D8); break; case X86Local::REP: - default: + case 0: opcodeType = ONEBYTE; switch (Opcode) { #define EXTENSION_TABLE(n) case 0x##n: @@ -1065,6 +1216,7 @@ OperandType RecognizableInstr::typeFromString(const std::string &s, TYPE("i32i8imm", TYPE_IMM32) TYPE("u32u8imm", TYPE_IMM32) TYPE("GR32", TYPE_Rv) + TYPE("GR32orGR64", TYPE_R32) TYPE("i64mem", TYPE_Mv) TYPE("i64i32imm", TYPE_IMM64) TYPE("i64i8imm", TYPE_IMM64) @@ -1073,17 +1225,22 @@ OperandType RecognizableInstr::typeFromString(const std::string &s, TYPE("i8imm", TYPE_IMM8) TYPE("GR8", TYPE_R8) TYPE("VR128", TYPE_XMM128) + TYPE("VR128X", TYPE_XMM128) TYPE("f128mem", TYPE_M128) TYPE("f256mem", TYPE_M256) + TYPE("f512mem", TYPE_M512) TYPE("FR64", TYPE_XMM64) + TYPE("FR64X", TYPE_XMM64) TYPE("f64mem", TYPE_M64FP) TYPE("sdmem", TYPE_M64FP) TYPE("FR32", TYPE_XMM32) + TYPE("FR32X", TYPE_XMM32) TYPE("f32mem", TYPE_M32FP) TYPE("ssmem", TYPE_M32FP) TYPE("RST", TYPE_ST) TYPE("i128mem", TYPE_M128) TYPE("i256mem", TYPE_M256) + TYPE("i512mem", TYPE_M512) TYPE("i64i32imm_pcrel", TYPE_REL64) TYPE("i16imm_pcrel", TYPE_REL16) TYPE("i32imm_pcrel", TYPE_REL32) @@ -1110,13 +1267,22 @@ OperandType RecognizableInstr::typeFromString(const std::string &s, TYPE("offset32", TYPE_MOFFS32) TYPE("offset64", TYPE_MOFFS64) TYPE("VR256", TYPE_XMM256) + TYPE("VR256X", TYPE_XMM256) + TYPE("VR512", TYPE_XMM512) + TYPE("VK8", TYPE_VK8) + TYPE("VK8WM", TYPE_VK8) + TYPE("VK16", TYPE_VK16) + TYPE("VK16WM", TYPE_VK16) TYPE("GR16_NOAX", TYPE_Rv) TYPE("GR32_NOAX", TYPE_Rv) TYPE("GR64_NOAX", TYPE_R64) TYPE("vx32mem", TYPE_M32) TYPE("vy32mem", TYPE_M32) + TYPE("vz32mem", TYPE_M32) TYPE("vx64mem", TYPE_M64) TYPE("vy64mem", TYPE_M64) + TYPE("vy64xmem", TYPE_M64) + TYPE("vz64mem", TYPE_M64) errs() << "Unhandled type string " << s << "\n"; llvm_unreachable("Unhandled type string"); } @@ -1143,10 +1309,15 @@ OperandEncoding RecognizableInstr::immediateEncodingFromString ENCODING("i8imm", ENCODING_IB) // This is not a typo. Instructions like BLENDVPD put // register IDs in 8-bit immediates nowadays. - ENCODING("VR256", ENCODING_IB) - ENCODING("VR128", ENCODING_IB) ENCODING("FR32", ENCODING_IB) ENCODING("FR64", ENCODING_IB) + ENCODING("VR128", ENCODING_IB) + ENCODING("VR256", ENCODING_IB) + ENCODING("FR32X", ENCODING_IB) + ENCODING("FR64X", ENCODING_IB) + ENCODING("VR128X", ENCODING_IB) + ENCODING("VR256X", ENCODING_IB) + ENCODING("VR512", ENCODING_IB) errs() << "Unhandled immediate encoding " << s << "\n"; llvm_unreachable("Unhandled immediate encoding"); } @@ -1156,13 +1327,21 @@ OperandEncoding RecognizableInstr::rmRegisterEncodingFromString bool hasOpSizePrefix) { ENCODING("GR16", ENCODING_RM) ENCODING("GR32", ENCODING_RM) + ENCODING("GR32orGR64", ENCODING_RM) ENCODING("GR64", ENCODING_RM) ENCODING("GR8", ENCODING_RM) ENCODING("VR128", ENCODING_RM) + ENCODING("VR128X", ENCODING_RM) ENCODING("FR64", ENCODING_RM) ENCODING("FR32", ENCODING_RM) + ENCODING("FR64X", ENCODING_RM) + ENCODING("FR32X", ENCODING_RM) ENCODING("VR64", ENCODING_RM) ENCODING("VR256", ENCODING_RM) + ENCODING("VR256X", ENCODING_RM) + ENCODING("VR512", ENCODING_RM) + ENCODING("VK8", ENCODING_RM) + ENCODING("VK16", ENCODING_RM) errs() << "Unhandled R/M register encoding " << s << "\n"; llvm_unreachable("Unhandled R/M register encoding"); } @@ -1172,6 +1351,7 @@ OperandEncoding RecognizableInstr::roRegisterEncodingFromString bool hasOpSizePrefix) { ENCODING("GR16", ENCODING_REG) ENCODING("GR32", ENCODING_REG) + ENCODING("GR32orGR64", ENCODING_REG) ENCODING("GR64", ENCODING_REG) ENCODING("GR8", ENCODING_REG) ENCODING("VR128", ENCODING_REG) @@ -1182,6 +1362,15 @@ OperandEncoding RecognizableInstr::roRegisterEncodingFromString ENCODING("DEBUG_REG", ENCODING_REG) ENCODING("CONTROL_REG", ENCODING_REG) ENCODING("VR256", ENCODING_REG) + ENCODING("VR256X", ENCODING_REG) + ENCODING("VR128X", ENCODING_REG) + ENCODING("FR64X", ENCODING_REG) + ENCODING("FR32X", ENCODING_REG) + ENCODING("VR512", ENCODING_REG) + ENCODING("VK8", ENCODING_REG) + ENCODING("VK16", ENCODING_REG) + ENCODING("VK8WM", ENCODING_REG) + ENCODING("VK16WM", ENCODING_REG) errs() << "Unhandled reg/opcode register encoding " << s << "\n"; llvm_unreachable("Unhandled reg/opcode register encoding"); } @@ -1195,10 +1384,26 @@ OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString ENCODING("FR64", ENCODING_VVVV) ENCODING("VR128", ENCODING_VVVV) ENCODING("VR256", ENCODING_VVVV) + ENCODING("FR32X", ENCODING_VVVV) + ENCODING("FR64X", ENCODING_VVVV) + ENCODING("VR128X", ENCODING_VVVV) + ENCODING("VR256X", ENCODING_VVVV) + ENCODING("VR512", ENCODING_VVVV) + ENCODING("VK8", ENCODING_VVVV) + ENCODING("VK16", ENCODING_VVVV) errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; llvm_unreachable("Unhandled VEX.vvvv register encoding"); } +OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString + (const std::string &s, + bool hasOpSizePrefix) { + ENCODING("VK8WM", ENCODING_WRITEMASK) + ENCODING("VK16WM", ENCODING_WRITEMASK) + errs() << "Unhandled mask register encoding " << s << "\n"; + llvm_unreachable("Unhandled mask register encoding"); +} + OperandEncoding RecognizableInstr::memoryEncodingFromString (const std::string &s, bool hasOpSizePrefix) { @@ -1210,10 +1415,12 @@ OperandEncoding RecognizableInstr::memoryEncodingFromString ENCODING("sdmem", ENCODING_RM) ENCODING("f128mem", ENCODING_RM) ENCODING("f256mem", ENCODING_RM) + ENCODING("f512mem", ENCODING_RM) ENCODING("f64mem", ENCODING_RM) ENCODING("f32mem", ENCODING_RM) ENCODING("i128mem", ENCODING_RM) ENCODING("i256mem", ENCODING_RM) + ENCODING("i512mem", ENCODING_RM) ENCODING("f80mem", ENCODING_RM) ENCODING("lea32mem", ENCODING_RM) ENCODING("lea64_32mem", ENCODING_RM) @@ -1224,8 +1431,11 @@ OperandEncoding RecognizableInstr::memoryEncodingFromString ENCODING("opaque512mem", ENCODING_RM) ENCODING("vx32mem", ENCODING_RM) ENCODING("vy32mem", ENCODING_RM) + ENCODING("vz32mem", ENCODING_RM) ENCODING("vx64mem", ENCODING_RM) ENCODING("vy64mem", ENCODING_RM) + ENCODING("vy64xmem", ENCODING_RM) + ENCODING("vz64mem", ENCODING_RM) errs() << "Unhandled memory encoding " << s << "\n"; llvm_unreachable("Unhandled memory encoding"); } diff --git a/contrib/llvm/utils/TableGen/X86RecognizableInstr.h b/contrib/llvm/utils/TableGen/X86RecognizableInstr.h index 9ec36a3..4d4686e 100644 --- a/contrib/llvm/utils/TableGen/X86RecognizableInstr.h +++ b/contrib/llvm/utils/TableGen/X86RecognizableInstr.h @@ -66,6 +66,16 @@ private: bool HasMemOp4Prefix; /// The ignoreVEX_L field from the record bool IgnoresVEX_L; + /// The hasEVEXPrefix field from the record + bool HasEVEXPrefix; + /// The hasEVEX_L2Prefix field from the record + bool HasEVEX_L2Prefix; + /// The hasEVEX_K field from the record + bool HasEVEX_K; + /// The hasEVEX_KZ field from the record + bool HasEVEX_KZ; + /// The hasEVEX_B field from the record + bool HasEVEX_B; /// The hasLockPrefix field from the record bool HasLockPrefix; /// The isCodeGenOnly filed from the record @@ -176,6 +186,8 @@ private: bool hasOpSizePrefix); static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s, bool HasOpSizePrefix); + static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s, + bool HasOpSizePrefix); /// handleOperand - Converts a single operand from the LLVM table format to /// the emitted table format, handling any duplicate operands it encounters |
