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| author | mav <mav@FreeBSD.org> | 2014-09-17 14:06:21 +0000 |
|---|---|---|
| committer | mav <mav@FreeBSD.org> | 2014-09-17 14:06:21 +0000 |
| commit | 0e425be7bbb51e540023cafb50cb3a0de3b8abf9 (patch) | |
| tree | ea47499283999aef711fb42cd91ef108ed09d29b /contrib/llvm/tools/clang/lib/CodeGen/CGCXXABI.cpp | |
| parent | 312a175bdaf969fe82f1472761a6ac1b811db765 (diff) | |
| download | FreeBSD-src-0e425be7bbb51e540023cafb50cb3a0de3b8abf9.zip FreeBSD-src-0e425be7bbb51e540023cafb50cb3a0de3b8abf9.tar.gz | |
MFC r271604, r271616:
Add couple memory barriers to order tdq_cpu_idle and tdq_load accesses.
This change fixes transient performance drops in some of my benchmarks,
vanishing as soon as I am trying to collect any stats from the scheduler.
It looks like reordered access to those variables sometimes caused loss of
IPI_PREEMPT, that delayed thread execution until some later interrupt.
Approved by: re (marius)
Diffstat (limited to 'contrib/llvm/tools/clang/lib/CodeGen/CGCXXABI.cpp')
0 files changed, 0 insertions, 0 deletions
