MFC r263312:

Pull in r196939 from upstream llvm trunk (by Reid Kleckner):

  Reland "Fix miscompile of MS inline assembly with stack realignment"

  This re-lands commit r196876, which was reverted in r196879.

  The tests have been fixed to pass on platforms with a stack alignment
  larger than 4.

  Update to clang side tests will land shortly.

Pull in r196986 from upstream llvm trunk (by Reid Kleckner):

  Revert the backend fatal error from r196939

  The combination of inline asm, stack realignment, and dynamic allocas
  turns out to be too common to reject out of hand.

  ASan inserts empy inline asm fragments and uses aligned allocas.
  Compiling any trivial function containing a dynamic alloca with ASan is
  enough to trigger the check.

  XFAIL the test cases that would be miscompiled and add one that uses the
  relevant functionality.

Pull in r202930 from upstream llvm trunk (by Hans Wennborg):

  Check for dynamic allocas and inline asm that clobbers sp before building
  selection dag (PR19012)

  In X86SelectionDagInfo::EmitTargetCodeForMemcpy we check with MachineFrameInfo
  to make sure that ESI isn't used as a base pointer register before we choose to
  emit rep movs (which clobbers esi).

  The problem is that MachineFrameInfo wouldn't know about dynamic allocas or
  inline asm that clobbers the stack pointer until SelectionDAGBuilder has
  encountered them.

  This patch fixes the problem by checking for such things when building the
  FunctionLoweringInfo.

  Differential Revision: http://llvm-reviews.chandlerc.com/D2954

Together, these commits fix the problem encountered in the devel/emacs
port on the i386 architecture, where a combination of stack realignment,
alloca() and memcpy() could incidentally clobber the %esi register,
leading to segfaults in the temacs build-time utility.

See also: http://llvm.org/PR18171 and http://llvm.org/PR19012

Reported by:	ashish
PR:		ports/183064

MFC r263313:

Pull in r203311 from upstream llvm trunk (by Arnold Schwaighofer):

  ISel: Make VSELECT selection terminate in cases where the condition type has to
  be split and the result type widened.

  When the condition of a vselect has to be split it makes no sense widening the
  vselect and thereby widening the condition. We end up in an endless loop of
  widening (vselect result type) and splitting (condition mask type) doing this.
  Instead, split both the condition and the vselect and widen the result.

  I ran this over the test suite with i686 and mattr=+sse and saw no regressions.

  Fixes PR18036.

With this fix the original problem case from the graphics/rawtherapee
port (posted in http://llvm.org/PR18036 ) now compiles within ~97MB RSS.

Reported by:	mandree

MFC r263320:

Add separate patch files for all the customizations we have currently
applied to our copy of llvm/clang.  These can be applied in alphabetical
order to a pristine llvm/clang 3.4 release source tree, to result in the
same version used in FreeBSD.

This is intended to clearly document all the changes until now, which
mostly consist of cherry pickings from the respective upstream trunks,
plus a number of hand-written FreeBSD-specific ones.  Hopefully those
can eventually be cleaned up and sent upstream too.

1 files changed, 89 insertions, 0 deletions

diff --git a/contrib/llvm/patches/patch-r262582-llvm-r202422-sparc.diff b/contrib/llvm/patches/patch-r262582-llvm-r202422-sparc.diff
new file mode 100644
index 0000000..589dd47
--- /dev/null
+++ b/contrib/llvm/patches/patch-r262582-llvm-r202422-sparc.diff
@@ -0,0 +1,89 @@
+Pull in r202422 from upstream llvm trunk (by Roman Divacky):
+
+  Lower FNEG just like FABS to fneg[ds] and fmov[ds], thus avoiding
+  expensive libcall. Also, Qp_neg is not implemented on at least
+  FreeBSD. This is also what gcc is doing.
+
+Introduced here: http://svn.freebsd.org/changeset/base/262582
+
+Index: lib/Target/Sparc/SparcISelLowering.cpp
+===================================================================
+--- lib/Target/Sparc/SparcISelLowering.cpp
++++ lib/Target/Sparc/SparcISelLowering.cpp
+@@ -2643,24 +2643,16 @@ static SDValue LowerF128Store(SDValue Op, Selectio
+                      &OutChains[0], 2);
+ }
+ 
+-static SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG,
+-                         const SparcTargetLowering &TLI,
+-                         bool is64Bit) {
+-  if (Op.getValueType() == MVT::f64)
+-    return LowerF64Op(Op, DAG, ISD::FNEG);
+-  if (Op.getValueType() == MVT::f128)
+-    return TLI.LowerF128Op(Op, DAG, ((is64Bit) ? "_Qp_neg" : "_Q_neg"), 1);
+-  return Op;
+-}
++static SDValue LowerFNEGorFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
++  assert((Op.getOpcode() == ISD::FNEG || Op.getOpcode() == ISD::FABS) && "invalid");
+ 
+-static SDValue LowerFABS(SDValue Op, SelectionDAG &DAG, bool isV9) {
+   if (Op.getValueType() == MVT::f64)
+-    return LowerF64Op(Op, DAG, ISD::FABS);
++    return LowerF64Op(Op, DAG, Op.getOpcode());
+   if (Op.getValueType() != MVT::f128)
+     return Op;
+ 
+-  // Lower fabs on f128 to fabs on f64
+-  // fabs f128 => fabs f64:sub_even64, fmov f64:sub_odd64
++  // Lower fabs/fneg on f128 to fabs/fneg on f64
++  // fabs/fneg f128 => fabs/fneg f64:sub_even64, fmov f64:sub_odd64
+ 
+   SDLoc dl(Op);
+   SDValue SrcReg128 = Op.getOperand(0);
+@@ -2671,7 +2663,7 @@ static SDValue LowerF128Store(SDValue Op, Selectio
+   if (isV9)
+     Hi64 = DAG.getNode(Op.getOpcode(), dl, MVT::f64, Hi64);
+   else
+-    Hi64 = LowerF64Op(Hi64, DAG, ISD::FABS);
++    Hi64 = LowerF64Op(Hi64, DAG, Op.getOpcode());
+ 
+   SDValue DstReg128 = SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
+                                                  dl, MVT::f128), 0);
+@@ -2792,7 +2784,6 @@ SDValue SparcTargetLowering::
+ LowerOperation(SDValue Op, SelectionDAG &DAG) const {
+ 
+   bool hasHardQuad = Subtarget->hasHardQuad();
+-  bool is64Bit     = Subtarget->is64Bit();
+   bool isV9        = Subtarget->isV9();
+ 
+   switch (Op.getOpcode()) {
+@@ -2835,8 +2826,8 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) cons
+                                        getLibcallName(RTLIB::DIV_F128), 2);
+   case ISD::FSQRT:              return LowerF128Op(Op, DAG,
+                                        getLibcallName(RTLIB::SQRT_F128),1);
+-  case ISD::FNEG:               return LowerFNEG(Op, DAG, *this, is64Bit);
+-  case ISD::FABS:               return LowerFABS(Op, DAG, isV9);
++  case ISD::FABS:
++  case ISD::FNEG:               return LowerFNEGorFABS(Op, DAG, isV9);
+   case ISD::FP_EXTEND:          return LowerF128_FPEXTEND(Op, DAG, *this);
+   case ISD::FP_ROUND:           return LowerF128_FPROUND(Op, DAG, *this);
+   case ISD::ADDC:
+Index: test/CodeGen/SPARC/fp128.ll
+===================================================================
+--- test/CodeGen/SPARC/fp128.ll
++++ test/CodeGen/SPARC/fp128.ll
+@@ -232,3 +232,14 @@ entry:
+   store  i32 %3, i32* %4, align 8
+   ret void
+ }
++
++; SOFT-LABEL:     f128_neg
++; SOFT:           fnegs
++
++define void @f128_neg(fp128* noalias sret %scalar.result, fp128* byval %a) {
++entry:
++  %0 = load fp128* %a, align 8
++  %1 = fsub fp128 0xL00000000000000008000000000000000, %0
++  store fp128 %1, fp128* %scalar.result, align 8
++  ret void
++}