MFC r263312:

Pull in r196939 from upstream llvm trunk (by Reid Kleckner):

  Reland "Fix miscompile of MS inline assembly with stack realignment"

  This re-lands commit r196876, which was reverted in r196879.

  The tests have been fixed to pass on platforms with a stack alignment
  larger than 4.

  Update to clang side tests will land shortly.

Pull in r196986 from upstream llvm trunk (by Reid Kleckner):

  Revert the backend fatal error from r196939

  The combination of inline asm, stack realignment, and dynamic allocas
  turns out to be too common to reject out of hand.

  ASan inserts empy inline asm fragments and uses aligned allocas.
  Compiling any trivial function containing a dynamic alloca with ASan is
  enough to trigger the check.

  XFAIL the test cases that would be miscompiled and add one that uses the
  relevant functionality.

Pull in r202930 from upstream llvm trunk (by Hans Wennborg):

  Check for dynamic allocas and inline asm that clobbers sp before building
  selection dag (PR19012)

  In X86SelectionDagInfo::EmitTargetCodeForMemcpy we check with MachineFrameInfo
  to make sure that ESI isn't used as a base pointer register before we choose to
  emit rep movs (which clobbers esi).

  The problem is that MachineFrameInfo wouldn't know about dynamic allocas or
  inline asm that clobbers the stack pointer until SelectionDAGBuilder has
  encountered them.

  This patch fixes the problem by checking for such things when building the
  FunctionLoweringInfo.

  Differential Revision: http://llvm-reviews.chandlerc.com/D2954

Together, these commits fix the problem encountered in the devel/emacs
port on the i386 architecture, where a combination of stack realignment,
alloca() and memcpy() could incidentally clobber the %esi register,
leading to segfaults in the temacs build-time utility.

See also: http://llvm.org/PR18171 and http://llvm.org/PR19012

Reported by:	ashish
PR:		ports/183064

MFC r263313:

Pull in r203311 from upstream llvm trunk (by Arnold Schwaighofer):

  ISel: Make VSELECT selection terminate in cases where the condition type has to
  be split and the result type widened.

  When the condition of a vselect has to be split it makes no sense widening the
  vselect and thereby widening the condition. We end up in an endless loop of
  widening (vselect result type) and splitting (condition mask type) doing this.
  Instead, split both the condition and the vselect and widen the result.

  I ran this over the test suite with i686 and mattr=+sse and saw no regressions.

  Fixes PR18036.

With this fix the original problem case from the graphics/rawtherapee
port (posted in http://llvm.org/PR18036 ) now compiles within ~97MB RSS.

Reported by:	mandree

MFC r263320:

Add separate patch files for all the customizations we have currently
applied to our copy of llvm/clang.  These can be applied in alphabetical
order to a pristine llvm/clang 3.4 release source tree, to result in the
same version used in FreeBSD.

This is intended to clearly document all the changes until now, which
mostly consist of cherry pickings from the respective upstream trunks,
plus a number of hand-written FreeBSD-specific ones.  Hopefully those
can eventually be cleaned up and sent upstream too.

1 files changed, 460 insertions, 0 deletions

diff --git a/contrib/llvm/patches/patch-r262261-llvm-r198580-sparc.diff b/contrib/llvm/patches/patch-r262261-llvm-r198580-sparc.diff
new file mode 100644
index 0000000..e30cbb2
--- /dev/null
+++ b/contrib/llvm/patches/patch-r262261-llvm-r198580-sparc.diff
@@ -0,0 +1,460 @@
+Pull in r198580 from upstream llvm trunk (by Venkatraman Govindaraju):
+
+  [Sparc] Add ELF Object Writer for Sparc. 
+
+Introduced here: http://svn.freebsd.org/changeset/base/262261
+
+Index: lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
+===================================================================
+--- lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
++++ lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
+@@ -12,6 +12,7 @@
+ //===----------------------------------------------------------------------===//
+ 
+ #define DEBUG_TYPE "mccodeemitter"
++#include "SparcMCExpr.h"
+ #include "SparcMCTargetDesc.h"
+ #include "MCTargetDesc/SparcFixupKinds.h"
+ #include "llvm/MC/MCCodeEmitter.h"
+@@ -92,6 +93,41 @@ getMachineOpValue(const MCInst &MI, const MCOperan
+ 
+   assert(MO.isExpr());
+   const MCExpr *Expr = MO.getExpr();
++  if (const SparcMCExpr *SExpr = dyn_cast<SparcMCExpr>(Expr)) {
++    switch(SExpr->getKind()) {
++    default: assert(0 && "Unhandled sparc expression!"); break;
++    case SparcMCExpr::VK_Sparc_LO:
++      Fixups.push_back(MCFixup::Create(0, Expr,
++                                       (MCFixupKind)Sparc::fixup_sparc_lo10));
++      break;
++    case SparcMCExpr::VK_Sparc_HI:
++      Fixups.push_back(MCFixup::Create(0, Expr,
++                                       (MCFixupKind)Sparc::fixup_sparc_hi22));
++      break;
++    case SparcMCExpr::VK_Sparc_H44:
++      Fixups.push_back(MCFixup::Create(0, Expr,
++                                       (MCFixupKind)Sparc::fixup_sparc_h44));
++      break;
++    case SparcMCExpr::VK_Sparc_M44:
++      Fixups.push_back(MCFixup::Create(0, Expr,
++                                       (MCFixupKind)Sparc::fixup_sparc_m44));
++      break;
++    case SparcMCExpr::VK_Sparc_L44:
++      Fixups.push_back(MCFixup::Create(0, Expr,
++                                       (MCFixupKind)Sparc::fixup_sparc_l44));
++      break;
++    case SparcMCExpr::VK_Sparc_HH:
++      Fixups.push_back(MCFixup::Create(0, Expr,
++                                       (MCFixupKind)Sparc::fixup_sparc_hh));
++      break;
++    case SparcMCExpr::VK_Sparc_HM:
++      Fixups.push_back(MCFixup::Create(0, Expr,
++                                       (MCFixupKind)Sparc::fixup_sparc_hm));
++      break;
++    }
++    return 0;
++  }
++
+   int64_t Res;
+   if (Expr->EvaluateAsAbsolute(Res))
+     return Res;
+Index: lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
+===================================================================
+--- lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
++++ lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
+@@ -89,6 +89,14 @@ static MCCodeGenInfo *createSparcV9MCCodeGenInfo(S
+   return X;
+ }
+ 
++static MCStreamer *createMCStreamer(const Target &T, StringRef TT,
++                                    MCContext &Context, MCAsmBackend &MAB,
++                                    raw_ostream &OS, MCCodeEmitter *Emitter,
++                                    bool RelaxAll, bool NoExecStack) {
++  SparcTargetELFStreamer *S = new SparcTargetELFStreamer();
++  return createELFStreamer(Context, S, MAB, OS, Emitter, RelaxAll, NoExecStack);
++}
++
+ static MCStreamer *
+ createMCAsmStreamer(MCContext &Ctx, formatted_raw_ostream &OS,
+                     bool isVerboseAsm, bool useLoc, bool useCFI,
+@@ -148,6 +156,13 @@ extern "C" void LLVMInitializeSparcTargetMC() {
+   TargetRegistry::RegisterMCAsmBackend(TheSparcV9Target,
+                                        createSparcAsmBackend);
+ 
++  // Register the object streamer.
++  TargetRegistry::RegisterMCObjectStreamer(TheSparcTarget,
++                                           createMCStreamer);
++  TargetRegistry::RegisterMCObjectStreamer(TheSparcV9Target,
++                                           createMCStreamer);
++
++  // Register the asm streamer.
+   TargetRegistry::RegisterAsmStreamer(TheSparcTarget,
+                                       createMCAsmStreamer);
+   TargetRegistry::RegisterAsmStreamer(TheSparcV9Target,
+Index: lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
+===================================================================
+--- lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
++++ lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
+@@ -10,6 +10,7 @@
+ #include "llvm/MC/MCAsmBackend.h"
+ #include "MCTargetDesc/SparcMCTargetDesc.h"
+ #include "MCTargetDesc/SparcFixupKinds.h"
++#include "llvm/MC/MCELFObjectWriter.h"
+ #include "llvm/MC/MCFixupKindInfo.h"
+ #include "llvm/MC/MCObjectWriter.h"
+ #include "llvm/Support/TargetRegistry.h"
+@@ -16,11 +17,43 @@
+ 
+ using namespace llvm;
+ 
++static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
++  switch (Kind) {
++  default:
++    llvm_unreachable("Unknown fixup kind!");
++  case FK_Data_1:
++  case FK_Data_2:
++  case FK_Data_4:
++  case FK_Data_8:
++    return Value;
++  case Sparc::fixup_sparc_call30:
++    return Value & 0x3fffffff;
++  case Sparc::fixup_sparc_br22:
++    return Value & 0x3fffff;
++  case Sparc::fixup_sparc_br19:
++    return Value & 0x1ffff;
++  case Sparc::fixup_sparc_hi22:
++    return (Value >> 10) & 0x3fffff;
++  case Sparc::fixup_sparc_lo10:
++    return Value & 0x3ff;
++  case Sparc::fixup_sparc_h44:
++    return (Value >> 22) & 0x3fffff;
++  case Sparc::fixup_sparc_m44:
++    return (Value >> 12) & 0x3ff;
++  case Sparc::fixup_sparc_l44:
++    return Value & 0xfff;
++  case Sparc::fixup_sparc_hh:
++    return (Value >> 42) & 0x3fffff;
++  case Sparc::fixup_sparc_hm:
++    return (Value >>32) & 0x3ff;
++  }
++}
++
+ namespace {
+   class SparcAsmBackend : public MCAsmBackend {
+-
++    const Target &TheTarget;
+   public:
+-    SparcAsmBackend(const Target &T) : MCAsmBackend() {}
++    SparcAsmBackend(const Target &T) : MCAsmBackend(), TheTarget(T) {}
+ 
+     unsigned getNumFixupKinds() const {
+       return Sparc::NumTargetFixupKinds;
+@@ -31,7 +64,14 @@ namespace {
+         // name                    offset bits  flags
+         { "fixup_sparc_call30",     0,     30,  MCFixupKindInfo::FKF_IsPCRel },
+         { "fixup_sparc_br22",       0,     22,  MCFixupKindInfo::FKF_IsPCRel },
+-        { "fixup_sparc_br19",       0,     19,  MCFixupKindInfo::FKF_IsPCRel }
++        { "fixup_sparc_br19",       0,     19,  MCFixupKindInfo::FKF_IsPCRel },
++        { "fixup_sparc_hi22",       0,     22,  0 },
++        { "fixup_sparc_lo10",       0,     10,  0 },
++        { "fixup_sparc_h44",        0,     22,  0 },
++        { "fixup_sparc_m44",        0,     10,  0 },
++        { "fixup_sparc_l44",        0,     12,  0 },
++        { "fixup_sparc_hh",         0,     21,  0 },
++        { "fixup_sparc_hm",         0,     10,  0 },
+       };
+ 
+       if (Kind < FirstTargetFixupKind)
+@@ -68,21 +108,38 @@ namespace {
+         OW->Write8(0);
+       return true;
+     }
++
++    bool is64Bit() const {
++      StringRef name = TheTarget.getName();
++      return name == "sparcv9";
++    }
+   };
+ 
+   class ELFSparcAsmBackend : public SparcAsmBackend {
++    Triple::OSType OSType;
+   public:
+     ELFSparcAsmBackend(const Target &T, Triple::OSType OSType) :
+-      SparcAsmBackend(T) { }
++      SparcAsmBackend(T), OSType(OSType) { }
+ 
+     void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
+                     uint64_t Value) const {
+-      assert(0 && "applyFixup not implemented yet");
++
++      Value = adjustFixupValue(Fixup.getKind(), Value);
++      if (!Value) return;           // Doesn't change encoding.
++
++      unsigned Offset = Fixup.getOffset();
++
++      // For each byte of the fragment that the fixup touches, mask in the bits
++      // from the fixup value. The Value has been "split up" into the
++      // appropriate bitfields above.
++      for (unsigned i = 0; i != 4; ++i)
++        Data[Offset + i] |= uint8_t((Value >> ((4 - i - 1)*8)) & 0xff);
++
+     }
+ 
+     MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
+-      assert(0 && "Object Writer not implemented yet");
+-      return 0;
++      uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(OSType);
++      return createSparcELFObjectWriter(OS, is64Bit(), OSABI);
+     }
+ 
+     virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
+Index: lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h
+===================================================================
+--- lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h
++++ lib/Target/Sparc/MCTargetDesc/SparcFixupKinds.h
+@@ -22,10 +22,32 @@ namespace llvm {
+       /// branches
+       fixup_sparc_br22,
+ 
+-      /// fixup_sparc_br22 - 22-bit PC relative relocation for
++      /// fixup_sparc_br19 - 19-bit PC relative relocation for
+       /// branches on icc/xcc
+       fixup_sparc_br19,
+ 
++      /// fixup_sparc_hi22  - 22-bit fixup corresponding to %hi(foo)
++      /// for sethi
++      fixup_sparc_hi22,
++
++      /// fixup_sparc_lo10  - 10-bit fixup corresponding to %lo(foo)
++      fixup_sparc_lo10,
++
++      /// fixup_sparc_h44  - 22-bit fixup corresponding to %h44(foo)
++      fixup_sparc_h44,
++
++      /// fixup_sparc_m44  - 10-bit fixup corresponding to %m44(foo)
++      fixup_sparc_m44,
++
++      /// fixup_sparc_l44  - 12-bit fixup corresponding to %l44(foo)
++      fixup_sparc_l44,
++
++      /// fixup_sparc_hh  -  22-bit fixup corresponding to %hh(foo)
++      fixup_sparc_hh,
++
++      /// fixup_sparc_hm  -  10-bit fixup corresponding to %hm(foo)
++      fixup_sparc_hm,
++
+       // Marker
+       LastTargetFixupKind,
+       NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind
+Index: lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
+===================================================================
+--- lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
++++ lib/Target/Sparc/MCTargetDesc/SparcELFObjectWriter.cpp
+@@ -0,0 +1,86 @@
++//===-- SparcELFObjectWriter.cpp - Sparc ELF Writer -----------------------===//
++//
++//                     The LLVM Compiler Infrastructure
++//
++// This file is distributed under the University of Illinois Open Source
++// License. See LICENSE.TXT for details.
++//
++//===----------------------------------------------------------------------===//
++
++#include "MCTargetDesc/SparcMCTargetDesc.h"
++#include "MCTargetDesc/SparcFixupKinds.h"
++#include "llvm/ADT/STLExtras.h"
++#include "llvm/MC/MCELFObjectWriter.h"
++#include "llvm/MC/MCExpr.h"
++#include "llvm/MC/MCValue.h"
++#include "llvm/Support/ErrorHandling.h"
++
++using namespace llvm;
++
++namespace {
++  class SparcELFObjectWriter : public MCELFObjectTargetWriter {
++  public:
++    SparcELFObjectWriter(bool Is64Bit, uint8_t OSABI)
++      : MCELFObjectTargetWriter(Is64Bit, OSABI,
++                                Is64Bit ?  ELF::EM_SPARCV9 : ELF::EM_SPARC,
++                                /*HasRelocationAddend*/ true) {}
++
++    virtual ~SparcELFObjectWriter() {}
++  protected:
++    virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
++                                  bool IsPCRel, bool IsRelocWithSymbol,
++                                  int64_t Addend) const;
++
++  };
++}
++
++
++unsigned SparcELFObjectWriter::GetRelocType(const MCValue &Target,
++                                            const MCFixup &Fixup,
++                                            bool IsPCRel,
++                                            bool IsRelocWithSymbol,
++                                            int64_t Addend) const {
++  if (IsPCRel) {
++    switch((unsigned)Fixup.getKind()) {
++    default:
++      llvm_unreachable("Unimplemented fixup -> relocation");
++    case FK_Data_1:                  return ELF::R_SPARC_DISP8;
++    case FK_Data_2:                  return ELF::R_SPARC_DISP16;
++    case FK_Data_4:                  return ELF::R_SPARC_DISP32;
++    case FK_Data_8:                  return ELF::R_SPARC_DISP64;
++    case Sparc::fixup_sparc_call30:  return ELF::R_SPARC_WDISP30;
++    case Sparc::fixup_sparc_br22:    return ELF::R_SPARC_WDISP22;
++    case Sparc::fixup_sparc_br19:    return ELF::R_SPARC_WDISP19;
++    }
++  }
++
++  switch((unsigned)Fixup.getKind()) {
++  default:
++    llvm_unreachable("Unimplemented fixup -> relocation");
++  case FK_Data_1:                return ELF::R_SPARC_8;
++  case FK_Data_2:                return ((Fixup.getOffset() % 2)
++                                         ? ELF::R_SPARC_UA16
++                                         : ELF::R_SPARC_16);
++  case FK_Data_4:                return ((Fixup.getOffset() % 4)
++                                         ? ELF::R_SPARC_UA32
++                                         : ELF::R_SPARC_32);
++  case FK_Data_8:                return ((Fixup.getOffset() % 8)
++                                         ? ELF::R_SPARC_UA64
++                                         : ELF::R_SPARC_64);
++  case Sparc::fixup_sparc_hi22:  return ELF::R_SPARC_HI22;
++  case Sparc::fixup_sparc_lo10:  return ELF::R_SPARC_LO10;
++  case Sparc::fixup_sparc_h44:   return ELF::R_SPARC_H44;
++  case Sparc::fixup_sparc_m44:   return ELF::R_SPARC_M44;
++  case Sparc::fixup_sparc_l44:   return ELF::R_SPARC_L44;
++  case Sparc::fixup_sparc_hh:    return ELF::R_SPARC_HH22;
++  case Sparc::fixup_sparc_hm:    return ELF::R_SPARC_HM10;
++  }
++  return ELF::R_SPARC_NONE;
++}
++
++MCObjectWriter *llvm::createSparcELFObjectWriter(raw_ostream &OS,
++                                                 bool Is64Bit,
++                                                 uint8_t OSABI) {
++  MCELFObjectTargetWriter *MOTW = new SparcELFObjectWriter(Is64Bit, OSABI);
++  return createELFObjectWriter(MOTW, OS,  /*IsLittleEndian=*/false);
++}
+Index: lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h
+===================================================================
+--- lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h
++++ lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h
+@@ -14,15 +14,19 @@
+ #ifndef SPARCMCTARGETDESC_H
+ #define SPARCMCTARGETDESC_H
+ 
++#include "llvm/Support/DataTypes.h"
++
+ namespace llvm {
+ class MCAsmBackend;
+ class MCCodeEmitter;
+ class MCContext;
+ class MCInstrInfo;
++class MCObjectWriter;
+ class MCRegisterInfo;
+ class MCSubtargetInfo;
+ class Target;
+ class StringRef;
++class raw_ostream;
+ 
+ extern Target TheSparcTarget;
+ extern Target TheSparcV9Target;
+@@ -35,7 +39,9 @@ MCAsmBackend *createSparcAsmBackend(const Target &
+                                     const MCRegisterInfo &MRI,
+                                     StringRef TT,
+                                     StringRef CPU);
+-
++MCObjectWriter *createSparcELFObjectWriter(raw_ostream &OS,
++                                           bool Is64Bit,
++                                           uint8_t OSABI);
+ } // End llvm namespace
+ 
+ // Defines symbolic names for Sparc registers.  This defines a mapping from
+Index: lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp
+===================================================================
+--- lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp
++++ lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp
+@@ -70,15 +70,67 @@ void SparcMCExpr::PrintImpl(raw_ostream &OS) const
+ bool
+ SparcMCExpr::EvaluateAsRelocatableImpl(MCValue &Res,
+                                          const MCAsmLayout *Layout) const {
+-  assert(0 && "FIXME: Implement SparcMCExpr::EvaluateAsRelocatableImpl");
+   return getSubExpr()->EvaluateAsRelocatable(Res, *Layout);
+ }
+ 
++static void fixELFSymbolsInTLSFixupsImpl(const MCExpr *Expr, MCAssembler &Asm) {
++  assert(0 && "Implement fixELFSymbolsInTLSFixupsImpl!");
++}
+ 
+ void SparcMCExpr::fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {
+-  assert(0 && "FIXME: Implement SparcMCExpr::fixELFSymbolsInTLSFixups");
++  switch(getKind()) {
++  default: return;
++  case VK_Sparc_TLS_GD_HI22:
++  case VK_Sparc_TLS_GD_LO10:
++  case VK_Sparc_TLS_GD_ADD:
++  case VK_Sparc_TLS_GD_CALL:
++  case VK_Sparc_TLS_LDM_HI22:
++  case VK_Sparc_TLS_LDM_LO10:
++  case VK_Sparc_TLS_LDM_ADD:
++  case VK_Sparc_TLS_LDM_CALL:
++  case VK_Sparc_TLS_LDO_HIX22:
++  case VK_Sparc_TLS_LDO_LOX10:
++  case VK_Sparc_TLS_LDO_ADD:
++  case VK_Sparc_TLS_IE_HI22:
++  case VK_Sparc_TLS_IE_LO10:
++  case VK_Sparc_TLS_IE_LD:
++  case VK_Sparc_TLS_IE_LDX:
++  case VK_Sparc_TLS_IE_ADD:
++  case VK_Sparc_TLS_LE_HIX22:
++  case VK_Sparc_TLS_LE_LOX10: break;
++  }
++  fixELFSymbolsInTLSFixupsImpl(getSubExpr(), Asm);
+ }
+ 
++// FIXME: This basically copies MCObjectStreamer::AddValueSymbols. Perhaps
++// that method should be made public?
++// FIXME: really do above: now that at least three other backends are using it.
++static void AddValueSymbolsImpl(const MCExpr *Value, MCAssembler *Asm) {
++  switch (Value->getKind()) {
++  case MCExpr::Target:
++    llvm_unreachable("Can't handle nested target expr!");
++    break;
++
++  case MCExpr::Constant:
++    break;
++
++  case MCExpr::Binary: {
++    const MCBinaryExpr *BE = cast<MCBinaryExpr>(Value);
++    AddValueSymbolsImpl(BE->getLHS(), Asm);
++    AddValueSymbolsImpl(BE->getRHS(), Asm);
++    break;
++  }
++
++  case MCExpr::SymbolRef:
++    Asm->getOrCreateSymbolData(cast<MCSymbolRefExpr>(Value)->getSymbol());
++    break;
++
++  case MCExpr::Unary:
++    AddValueSymbolsImpl(cast<MCUnaryExpr>(Value)->getSubExpr(), Asm);
++    break;
++  }
++}
++
+ void SparcMCExpr::AddValueSymbols(MCAssembler *Asm) const {
+-  assert(0 && "FIXME: Implement SparcMCExpr::AddValueSymbols");
++  AddValueSymbolsImpl(getSubExpr(), Asm);
+ }
+Index: lib/Target/Sparc/MCTargetDesc/CMakeLists.txt
+===================================================================
+--- lib/Target/Sparc/MCTargetDesc/CMakeLists.txt
++++ lib/Target/Sparc/MCTargetDesc/CMakeLists.txt
+@@ -1,5 +1,6 @@
+ add_llvm_library(LLVMSparcDesc
+   SparcAsmBackend.cpp
++  SparcELFObjectWriter.cpp
+   SparcMCAsmInfo.cpp
+   SparcMCCodeEmitter.cpp
+   SparcMCTargetDesc.cpp