diff options
| author | dim <dim@FreeBSD.org> | 2017-04-02 17:24:58 +0000 |
|---|---|---|
| committer | dim <dim@FreeBSD.org> | 2017-04-02 17:24:58 +0000 |
| commit | 60b571e49a90d38697b3aca23020d9da42fc7d7f (patch) | |
| tree | 99351324c24d6cb146b6285b6caffa4d26fce188 /contrib/llvm/lib/Target/Mips | |
| parent | bea1b22c7a9bce1dfdd73e6e5b65bc4752215180 (diff) | |
| download | FreeBSD-src-60b571e49a90d38697b3aca23020d9da42fc7d7f.zip FreeBSD-src-60b571e49a90d38697b3aca23020d9da42fc7d7f.tar.gz | |
Update clang, llvm, lld, lldb, compiler-rt and libc++ to 4.0.0 release:
MFC r309142 (by emaste):
Add WITH_LLD_AS_LD build knob
If set it installs LLD as /usr/bin/ld. LLD (as of version 3.9) is not
capable of linking the world and kernel, but can self-host and link many
substantial applications. GNU ld continues to be used for the world and
kernel build, regardless of how this knob is set.
It is on by default for arm64, and off for all other CPU architectures.
Sponsored by: The FreeBSD Foundation
MFC r310840:
Reapply 310775, now it also builds correctly if lldb is disabled:
Move llvm-objdump from CLANG_EXTRAS to installed by default
We currently install three tools from binutils 2.17.50: as, ld, and
objdump. Work is underway to migrate to a permissively-licensed
tool-chain, with one goal being the retirement of binutils 2.17.50.
LLVM's llvm-objdump is intended to be compatible with GNU objdump
although it is currently missing some options and may have formatting
differences. Enable it by default for testing and further investigation.
It may later be changed to install as /usr/bin/objdump, it becomes a
fully viable replacement.
Reviewed by: emaste
Differential Revision: https://reviews.freebsd.org/D8879
MFC r312855 (by emaste):
Rename LLD_AS_LD to LLD_IS_LD, for consistency with CLANG_IS_CC
Reported by: Dan McGregor <dan.mcgregor usask.ca>
MFC r313559 | glebius | 2017-02-10 18:34:48 +0100 (Fri, 10 Feb 2017) | 5 lines
Don't check struct rtentry on FreeBSD, it is an internal kernel structure.
On other systems it may be API structure for SIOCADDRT/SIOCDELRT.
Reviewed by: emaste, dim
MFC r314152 (by jkim):
Remove an assembler flag, which is redundant since r309124. The upstream
took care of it by introducing a macro NO_EXEC_STACK_DIRECTIVE.
http://llvm.org/viewvc/llvm-project?rev=273500&view=rev
Reviewed by: dim
MFC r314564:
Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ to
4.0.0 (branches/release_40 296509). The release will follow soon.
Please note that from 3.5.0 onwards, clang, llvm and lldb require C++11
support to build; see UPDATING for more information.
Also note that as of 4.0.0, lld should be able to link the base system
on amd64 and aarch64. See the WITH_LLD_IS_LLD setting in src.conf(5).
Though please be aware that this is work in progress.
Release notes for llvm, clang and lld will be available here:
<http://releases.llvm.org/4.0.0/docs/ReleaseNotes.html>
<http://releases.llvm.org/4.0.0/tools/clang/docs/ReleaseNotes.html>
<http://releases.llvm.org/4.0.0/tools/lld/docs/ReleaseNotes.html>
Thanks to Ed Maste, Jan Beich, Antoine Brodin and Eric Fiselier for
their help.
Relnotes: yes
Exp-run: antoine
PR: 215969, 216008
MFC r314708:
For now, revert r287232 from upstream llvm trunk (by Daniil Fukalov):
[SCEV] limit recursion depth of CompareSCEVComplexity
Summary:
CompareSCEVComplexity goes too deep (50+ on a quite a big unrolled
loop) and runs almost infinite time.
Added cache of "equal" SCEV pairs to earlier cutoff of further
estimation. Recursion depth limit was also introduced as a parameter.
Reviewers: sanjoy
Subscribers: mzolotukhin, tstellarAMD, llvm-commits
Differential Revision: https://reviews.llvm.org/D26389
This commit is the cause of excessive compile times on skein_block.c
(and possibly other files) during kernel builds on amd64.
We never saw the problematic behavior described in this upstream commit,
so for now it is better to revert it. An upstream bug has been filed
here: https://bugs.llvm.org/show_bug.cgi?id=32142
Reported by: mjg
MFC r314795:
Reapply r287232 from upstream llvm trunk (by Daniil Fukalov):
[SCEV] limit recursion depth of CompareSCEVComplexity
Summary:
CompareSCEVComplexity goes too deep (50+ on a quite a big unrolled
loop) and runs almost infinite time.
Added cache of "equal" SCEV pairs to earlier cutoff of further
estimation. Recursion depth limit was also introduced as a parameter.
Reviewers: sanjoy
Subscribers: mzolotukhin, tstellarAMD, llvm-commits
Differential Revision: https://reviews.llvm.org/D26389
Pull in r296992 from upstream llvm trunk (by Sanjoy Das):
[SCEV] Decrease the recursion threshold for CompareValueComplexity
Fixes PR32142.
r287232 accidentally increased the recursion threshold for
CompareValueComplexity from 2 to 32. This change reverses that
change by introducing a separate flag for CompareValueComplexity's
threshold.
The latter revision fixes the excessive compile times for skein_block.c.
MFC r314907 | mmel | 2017-03-08 12:40:27 +0100 (Wed, 08 Mar 2017) | 7 lines
Unbreak ARMv6 world.
The new compiler_rt library imported with clang 4.0.0 have several fatal
issues (non-functional __udivsi3 for example) with ARM specific instrict
functions. As temporary workaround, until upstream solve these problems,
disable all thumb[1][2] related feature.
MFC r315016:
Update clang, llvm, lld, lldb, compiler-rt and libc++ to 4.0.0 release.
We were already very close to the last release candidate, so this is a
pretty minor update.
Relnotes: yes
MFC r316005:
Revert r314907, and pull in r298713 from upstream compiler-rt trunk (by
Weiming Zhao):
builtins: Select correct code fragments when compiling for Thumb1/Thum2/ARM ISA.
Summary:
Value of __ARM_ARCH_ISA_THUMB isn't based on the actual compilation
mode (-mthumb, -marm), it reflect's capability of given CPU.
Due to this:
- use __tbumb__ and __thumb2__ insteand of __ARM_ARCH_ISA_THUMB
- use '.thumb' directive consistently in all affected files
- decorate all thumb functions using
DEFINE_COMPILERRT_THUMB_FUNCTION()
---------
Note: This patch doesn't fix broken Thumb1 variant of __udivsi3 !
Reviewers: weimingz, rengolin, compnerd
Subscribers: aemerson, dim
Differential Revision: https://reviews.llvm.org/D30938
Discussed with: mmel
Diffstat (limited to 'contrib/llvm/lib/Target/Mips')
68 files changed, 5261 insertions, 1528 deletions
diff --git a/contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp b/contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp index b51d020..d054578 100644 --- a/contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ b/contrib/llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -13,6 +13,7 @@ #include "MipsRegisterInfo.h" #include "MipsTargetObjectFile.h" #include "MipsTargetStreamer.h" +#include "MCTargetDesc/MipsBaseInfo.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/MC/MCContext.h" @@ -129,6 +130,9 @@ class MipsAsmParser : public MCTargetAsmParser { #define GET_ASSEMBLER_HEADER #include "MipsGenAsmMatcher.inc" + unsigned + checkEarlyTargetMatchPredicate(MCInst &Inst, + const OperandVector &Operands) override; unsigned checkTargetMatchPredicate(MCInst &Inst) override; bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, @@ -230,7 +234,10 @@ class MipsAsmParser : public MCTargetAsmParser { bool expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI); - bool expandUlw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + bool expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); + + bool expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI); bool expandRotation(MCInst &Inst, SMLoc IDLoc, @@ -245,13 +252,19 @@ class MipsAsmParser : public MCTargetAsmParser { bool expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI); + bool expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI, bool IsLoad); + + bool expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); + + bool expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); + bool reportParseError(Twine ErrorMsg); bool reportParseError(SMLoc Loc, Twine ErrorMsg); bool parseMemOffset(const MCExpr *&Res, bool isParenExpr); - bool parseRelocOperand(const MCExpr *&Res); - - const MCExpr *evaluateRelocExpr(const MCExpr *Expr, StringRef RelocStr); bool isEvaluated(const MCExpr *Expr); bool parseSetMips0Directive(); @@ -292,6 +305,10 @@ class MipsAsmParser : public MCTargetAsmParser { bool parseDataDirective(unsigned Size, SMLoc L); bool parseDirectiveGpWord(); bool parseDirectiveGpDWord(); + bool parseDirectiveDtpRelWord(); + bool parseDirectiveDtpRelDWord(); + bool parseDirectiveTpRelWord(); + bool parseDirectiveTpRelDWord(); bool parseDirectiveModule(); bool parseDirectiveModuleFP(); bool parseFpABIValue(MipsABIFlagsSection::FpABIKind &FpABI, @@ -395,6 +412,9 @@ public: Match_RequiresDifferentSrcAndDst = FIRST_TARGET_MATCH_RESULT_TY, Match_RequiresDifferentOperands, Match_RequiresNoZeroRegister, + Match_RequiresSameSrcAndDst, + Match_NoFCCRegisterForCurrentISA, + Match_NonZeroOperandForSync, #define GET_OPERAND_DIAGNOSTIC_TYPES #include "MipsGenAsmMatcher.inc" #undef GET_OPERAND_DIAGNOSTIC_TYPES @@ -548,6 +568,64 @@ public: void warnIfNoMacro(SMLoc Loc); bool isLittle() const { return IsLittleEndian; } + + const MCExpr *createTargetUnaryExpr(const MCExpr *E, + AsmToken::TokenKind OperatorToken, + MCContext &Ctx) override { + switch(OperatorToken) { + default: + llvm_unreachable("Unknown token"); + return nullptr; + case AsmToken::PercentCall16: + return MipsMCExpr::create(MipsMCExpr::MEK_GOT_CALL, E, Ctx); + case AsmToken::PercentCall_Hi: + return MipsMCExpr::create(MipsMCExpr::MEK_CALL_HI16, E, Ctx); + case AsmToken::PercentCall_Lo: + return MipsMCExpr::create(MipsMCExpr::MEK_CALL_LO16, E, Ctx); + case AsmToken::PercentDtprel_Hi: + return MipsMCExpr::create(MipsMCExpr::MEK_DTPREL_HI, E, Ctx); + case AsmToken::PercentDtprel_Lo: + return MipsMCExpr::create(MipsMCExpr::MEK_DTPREL_LO, E, Ctx); + case AsmToken::PercentGot: + return MipsMCExpr::create(MipsMCExpr::MEK_GOT, E, Ctx); + case AsmToken::PercentGot_Disp: + return MipsMCExpr::create(MipsMCExpr::MEK_GOT_DISP, E, Ctx); + case AsmToken::PercentGot_Hi: + return MipsMCExpr::create(MipsMCExpr::MEK_GOT_HI16, E, Ctx); + case AsmToken::PercentGot_Lo: + return MipsMCExpr::create(MipsMCExpr::MEK_GOT_LO16, E, Ctx); + case AsmToken::PercentGot_Ofst: + return MipsMCExpr::create(MipsMCExpr::MEK_GOT_OFST, E, Ctx); + case AsmToken::PercentGot_Page: + return MipsMCExpr::create(MipsMCExpr::MEK_GOT_PAGE, E, Ctx); + case AsmToken::PercentGottprel: + return MipsMCExpr::create(MipsMCExpr::MEK_GOTTPREL, E, Ctx); + case AsmToken::PercentGp_Rel: + return MipsMCExpr::create(MipsMCExpr::MEK_GPREL, E, Ctx); + case AsmToken::PercentHi: + return MipsMCExpr::create(MipsMCExpr::MEK_HI, E, Ctx); + case AsmToken::PercentHigher: + return MipsMCExpr::create(MipsMCExpr::MEK_HIGHER, E, Ctx); + case AsmToken::PercentHighest: + return MipsMCExpr::create(MipsMCExpr::MEK_HIGHEST, E, Ctx); + case AsmToken::PercentLo: + return MipsMCExpr::create(MipsMCExpr::MEK_LO, E, Ctx); + case AsmToken::PercentNeg: + return MipsMCExpr::create(MipsMCExpr::MEK_NEG, E, Ctx); + case AsmToken::PercentPcrel_Hi: + return MipsMCExpr::create(MipsMCExpr::MEK_PCREL_HI16, E, Ctx); + case AsmToken::PercentPcrel_Lo: + return MipsMCExpr::create(MipsMCExpr::MEK_PCREL_LO16, E, Ctx); + case AsmToken::PercentTlsgd: + return MipsMCExpr::create(MipsMCExpr::MEK_TLSGD, E, Ctx); + case AsmToken::PercentTlsldm: + return MipsMCExpr::create(MipsMCExpr::MEK_TLSLDM, E, Ctx); + case AsmToken::PercentTprel_Hi: + return MipsMCExpr::create(MipsMCExpr::MEK_TPREL_HI, E, Ctx); + case AsmToken::PercentTprel_Lo: + return MipsMCExpr::create(MipsMCExpr::MEK_TPREL_LO, E, Ctx); + } + } }; } @@ -605,6 +683,7 @@ private: struct RegIdxOp { unsigned Index; /// Index into the register class RegKind Kind; /// Bitfield of the kinds it could possibly be + struct Token Tok; /// The input token this operand originated from. const MCRegisterInfo *RegInfo; }; @@ -632,7 +711,8 @@ private: SMLoc StartLoc, EndLoc; /// Internal constructor for register kinds - static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, RegKind RegKind, + static std::unique_ptr<MipsOperand> CreateReg(unsigned Index, StringRef Str, + RegKind RegKind, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) { @@ -640,6 +720,8 @@ private: Op->RegIdx.Index = Index; Op->RegIdx.RegInfo = RegInfo; Op->RegIdx.Kind = RegKind; + Op->RegIdx.Tok.Data = Str.data(); + Op->RegIdx.Tok.Length = Str.size(); Op->StartLoc = S; Op->EndLoc = E; return Op; @@ -856,9 +938,11 @@ public: assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::createReg(getFGR32Reg())); // FIXME: We ought to do this for -integrated-as without -via-file-asm too. + // FIXME: This should propagate failure up to parseStatement. if (!AsmParser.useOddSPReg() && RegIdx.Index & 1) - AsmParser.Error(StartLoc, "-mno-odd-spreg prohibits the use of odd FPU " - "registers"); + AsmParser.getParser().printError( + StartLoc, "-mno-odd-spreg prohibits the use of odd FPU " + "registers"); } void addFGRH32AsmRegOperands(MCInst &Inst, unsigned N) const { @@ -925,7 +1009,7 @@ public: void addConstantUImmOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); uint64_t Imm = getConstantImm() - Offset; - Imm &= (1 << Bits) - 1; + Imm &= (1ULL << Bits) - 1; Imm += Offset; Imm += AdjustOffset; Inst.addOperand(MCOperand::createImm(Imm)); @@ -1023,7 +1107,8 @@ public: bool isRegIdx() const { return Kind == k_RegisterIndex; } bool isImm() const override { return Kind == k_Immediate; } bool isConstantImm() const { - return isImm() && isa<MCConstantExpr>(getImm()); + int64_t Res; + return isImm() && getImm()->evaluateAsAbsolute(Res); } bool isConstantImmz() const { return isConstantImm() && getConstantImm() == 0; @@ -1099,8 +1184,14 @@ public: } template <unsigned Bits, unsigned ShiftLeftAmount> bool isScaledSImm() const { - return isConstantImm() && - isShiftedInt<Bits, ShiftLeftAmount>(getConstantImm()); + if (isConstantImm() && isShiftedInt<Bits, ShiftLeftAmount>(getConstantImm())) + return true; + // Operand can also be a symbol or symbol plus offset in case of relocations. + if (Kind != k_Immediate) + return false; + MCValue Res; + bool Success = getImm()->evaluateAsRelocatable(Res, nullptr, nullptr); + return Success && isShiftedInt<Bits, ShiftLeftAmount>(Res.getConstant()); } bool isRegList16() const { if (!isRegList()) @@ -1188,7 +1279,9 @@ public: int64_t getConstantImm() const { const MCExpr *Val = getImm(); - return static_cast<const MCConstantExpr *>(Val)->getValue(); + int64_t Value = 0; + (void)Val->evaluateAsAbsolute(Value); + return Value; } MipsOperand *getMemBase() const { @@ -1228,66 +1321,66 @@ public: /// Create a numeric register (e.g. $1). The exact register remains /// unresolved until an instruction successfully matches static std::unique_ptr<MipsOperand> - createNumericReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, - SMLoc E, MipsAsmParser &Parser) { + createNumericReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, + SMLoc S, SMLoc E, MipsAsmParser &Parser) { DEBUG(dbgs() << "createNumericReg(" << Index << ", ...)\n"); - return CreateReg(Index, RegKind_Numeric, RegInfo, S, E, Parser); + return CreateReg(Index, Str, RegKind_Numeric, RegInfo, S, E, Parser); } /// Create a register that is definitely a GPR. /// This is typically only used for named registers such as $gp. static std::unique_ptr<MipsOperand> - createGPRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, - MipsAsmParser &Parser) { - return CreateReg(Index, RegKind_GPR, RegInfo, S, E, Parser); + createGPRReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, + SMLoc S, SMLoc E, MipsAsmParser &Parser) { + return CreateReg(Index, Str, RegKind_GPR, RegInfo, S, E, Parser); } /// Create a register that is definitely a FGR. /// This is typically only used for named registers such as $f0. static std::unique_ptr<MipsOperand> - createFGRReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, - MipsAsmParser &Parser) { - return CreateReg(Index, RegKind_FGR, RegInfo, S, E, Parser); + createFGRReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, + SMLoc S, SMLoc E, MipsAsmParser &Parser) { + return CreateReg(Index, Str, RegKind_FGR, RegInfo, S, E, Parser); } /// Create a register that is definitely a HWReg. /// This is typically only used for named registers such as $hwr_cpunum. static std::unique_ptr<MipsOperand> - createHWRegsReg(unsigned Index, const MCRegisterInfo *RegInfo, + createHWRegsReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, MipsAsmParser &Parser) { - return CreateReg(Index, RegKind_HWRegs, RegInfo, S, E, Parser); + return CreateReg(Index, Str, RegKind_HWRegs, RegInfo, S, E, Parser); } /// Create a register that is definitely an FCC. /// This is typically only used for named registers such as $fcc0. static std::unique_ptr<MipsOperand> - createFCCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, - MipsAsmParser &Parser) { - return CreateReg(Index, RegKind_FCC, RegInfo, S, E, Parser); + createFCCReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, + SMLoc S, SMLoc E, MipsAsmParser &Parser) { + return CreateReg(Index, Str, RegKind_FCC, RegInfo, S, E, Parser); } /// Create a register that is definitely an ACC. /// This is typically only used for named registers such as $ac0. static std::unique_ptr<MipsOperand> - createACCReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, SMLoc E, - MipsAsmParser &Parser) { - return CreateReg(Index, RegKind_ACC, RegInfo, S, E, Parser); + createACCReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, + SMLoc S, SMLoc E, MipsAsmParser &Parser) { + return CreateReg(Index, Str, RegKind_ACC, RegInfo, S, E, Parser); } /// Create a register that is definitely an MSA128. /// This is typically only used for named registers such as $w0. static std::unique_ptr<MipsOperand> - createMSA128Reg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, - SMLoc E, MipsAsmParser &Parser) { - return CreateReg(Index, RegKind_MSA128, RegInfo, S, E, Parser); + createMSA128Reg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, + SMLoc S, SMLoc E, MipsAsmParser &Parser) { + return CreateReg(Index, Str, RegKind_MSA128, RegInfo, S, E, Parser); } /// Create a register that is definitely an MSACtrl. /// This is typically only used for named registers such as $msaaccess. static std::unique_ptr<MipsOperand> - createMSACtrlReg(unsigned Index, const MCRegisterInfo *RegInfo, SMLoc S, - SMLoc E, MipsAsmParser &Parser) { - return CreateReg(Index, RegKind_MSACtrl, RegInfo, S, E, Parser); + createMSACtrlReg(unsigned Index, StringRef Str, const MCRegisterInfo *RegInfo, + SMLoc S, SMLoc E, MipsAsmParser &Parser) { + return CreateReg(Index, Str, RegKind_MSACtrl, RegInfo, S, E, Parser); } static std::unique_ptr<MipsOperand> @@ -1369,8 +1462,6 @@ public: bool isFCCAsmReg() const { if (!(isRegIdx() && RegIdx.Kind & RegKind_FCC)) return false; - if (!AsmParser.hasEightFccRegisters()) - return RegIdx.Index == 0; return RegIdx.Index <= 7; } bool isACCAsmReg() const { @@ -1428,10 +1519,11 @@ public: OS << ">"; break; case k_RegisterIndex: - OS << "RegIdx<" << RegIdx.Index << ":" << RegIdx.Kind << ">"; + OS << "RegIdx<" << RegIdx.Index << ":" << RegIdx.Kind << ", " + << StringRef(RegIdx.Tok.Data, RegIdx.Tok.Length) << ">"; break; case k_Token: - OS << Tok.Data; + OS << getToken(); break; case k_RegList: OS << "RegList< "; @@ -1444,6 +1536,22 @@ public: break; } } + + bool isValidForTie(const MipsOperand &Other) const { + if (Kind != Other.Kind) + return false; + + switch (Kind) { + default: + llvm_unreachable("Unexpected kind"); + return false; + case k_RegisterIndex: { + StringRef Token(RegIdx.Tok.Data, RegIdx.Tok.Length); + StringRef OtherToken(Other.RegIdx.Tok.Data, Other.RegIdx.Tok.Length); + return Token == OtherToken; + } + } + } }; // class MipsOperand } // namespace @@ -1526,7 +1634,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, case Mips::BBIT1: case Mips::BBIT132: assert(hasCnMips() && "instruction only valid for octeon cpus"); - // Fall through + LLVM_FALLTHROUGH; case Mips::BEQ: case Mips::BNE: @@ -1572,6 +1680,45 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, 1LL << (inMicroMipsMode() ? 1 : 2))) return Error(IDLoc, "branch to misaligned address"); break; + case Mips::BGEC: case Mips::BGEC_MMR6: + case Mips::BLTC: case Mips::BLTC_MMR6: + case Mips::BGEUC: case Mips::BGEUC_MMR6: + case Mips::BLTUC: case Mips::BLTUC_MMR6: + case Mips::BEQC: case Mips::BEQC_MMR6: + case Mips::BNEC: case Mips::BNEC_MMR6: + assert(MCID.getNumOperands() == 3 && "unexpected number of operands"); + Offset = Inst.getOperand(2); + if (!Offset.isImm()) + break; // We'll deal with this situation later on when applying fixups. + if (!isIntN(18, Offset.getImm())) + return Error(IDLoc, "branch target out of range"); + if (OffsetToAlignment(Offset.getImm(), 1LL << 2)) + return Error(IDLoc, "branch to misaligned address"); + break; + case Mips::BLEZC: case Mips::BLEZC_MMR6: + case Mips::BGEZC: case Mips::BGEZC_MMR6: + case Mips::BGTZC: case Mips::BGTZC_MMR6: + case Mips::BLTZC: case Mips::BLTZC_MMR6: + assert(MCID.getNumOperands() == 2 && "unexpected number of operands"); + Offset = Inst.getOperand(1); + if (!Offset.isImm()) + break; // We'll deal with this situation later on when applying fixups. + if (!isIntN(18, Offset.getImm())) + return Error(IDLoc, "branch target out of range"); + if (OffsetToAlignment(Offset.getImm(), 1LL << 2)) + return Error(IDLoc, "branch to misaligned address"); + break; + case Mips::BEQZC: case Mips::BEQZC_MMR6: + case Mips::BNEZC: case Mips::BNEZC_MMR6: + assert(MCID.getNumOperands() == 2 && "unexpected number of operands"); + Offset = Inst.getOperand(1); + if (!Offset.isImm()) + break; // We'll deal with this situation later on when applying fixups. + if (!isIntN(23, Offset.getImm())) + return Error(IDLoc, "branch target out of range"); + if (OffsetToAlignment(Offset.getImm(), 1LL << 2)) + return Error(IDLoc, "branch to misaligned address"); + break; case Mips::BEQZ16_MM: case Mips::BEQZC16_MMR6: case Mips::BNEZ16_MM: @@ -1638,6 +1785,17 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, } } + // For PIC code convert unconditional jump to unconditional branch. + if ((Inst.getOpcode() == Mips::J || Inst.getOpcode() == Mips::J_MM) && + inPicMode()) { + MCInst BInst; + BInst.setOpcode(inMicroMipsMode() ? Mips::BEQ_MM : Mips::BEQ); + BInst.addOperand(MCOperand::createReg(Mips::ZERO)); + BInst.addOperand(MCOperand::createReg(Mips::ZERO)); + BInst.addOperand(Inst.getOperand(0)); + Inst = BInst; + } + // This expansion is not in a function called by tryExpandInstruction() // because the pseudo-instruction doesn't have a distinct opcode. if ((Inst.getOpcode() == Mips::JAL || Inst.getOpcode() == Mips::JAL_MM) && @@ -1658,7 +1816,8 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, // FIXME: Add support for label+offset operands (currently causes an error). // FIXME: Add support for forward-declared local symbols. // FIXME: Add expansion for when the LargeGOT option is enabled. - if (JalSym->isInSection() || JalSym->isTemporary()) { + if (JalSym->isInSection() || JalSym->isTemporary() || + (JalSym->isELF() && cast<MCSymbolELF>(JalSym)->getBinding() == ELF::STB_LOCAL)) { if (isABI_O32()) { // If it's a local symbol and the O32 ABI is being used, we expand to: // lw $25, 0($gp) @@ -1716,7 +1875,8 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, ExpandedJalSym = true; } - if (MCID.mayLoad() || MCID.mayStore()) { + bool IsPCRelativeLoad = (MCID.TSFlags & MipsII::IsPCRelativeLoad) != 0; + if ((MCID.mayLoad() || MCID.mayStore()) && !IsPCRelativeLoad) { // Check the offset of memory operand, if it is a symbol // reference or immediate we may have to expand instructions. for (unsigned i = 0; i < MCID.getNumOperands(); i++) { @@ -1729,7 +1889,7 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, if (MemOffset < -32768 || MemOffset > 32767) { // Offset can't exceed 16bit value. expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad(), true); - return false; + return getParser().hasPendingError(); } } else if (Op.isExpr()) { const MCExpr *Expr = Op.getExpr(); @@ -1739,11 +1899,11 @@ bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, if (SR->getKind() == MCSymbolRefExpr::VK_None) { // Expand symbol. expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad(), false); - return false; + return getParser().hasPendingError(); } } else if (!isEvaluated(Expr)) { expandMemInst(Inst, IDLoc, Out, STI, MCID.mayLoad(), false); - return false; + return getParser().hasPendingError(); } } } @@ -2034,8 +2194,11 @@ MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, return expandUlh(Inst, true, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::Ulhu: return expandUlh(Inst, false, IDLoc, Out, STI) ? MER_Fail : MER_Success; + case Mips::Ush: + return expandUsh(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::Ulw: - return expandUlw(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; + case Mips::Usw: + return expandUxw(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::NORImm: return expandAliasImmediate(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::ADDi: @@ -2077,6 +2240,16 @@ MipsAsmParser::tryExpandInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, return expandDRotationImm(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; case Mips::ABSMacro: return expandAbs(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; + case Mips::LDMacro: + case Mips::SDMacro: + return expandLoadStoreDMacro(Inst, IDLoc, Out, STI, + Inst.getOpcode() == Mips::LDMacro) + ? MER_Fail + : MER_Success; + case Mips::SEQMacro: + return expandSeq(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; + case Mips::SEQIMacro: + return expandSeqI(Inst, IDLoc, Out, STI) ? MER_Fail : MER_Success; } } @@ -2335,6 +2508,7 @@ bool MipsAsmParser::expandLoadAddress(unsigned DstReg, unsigned BaseReg, Error(IDLoc, "la used to load 64-bit address"); // Continue as if we had 'dla' instead. Is32BitAddress = false; + return true; } // dla requires 64-bit addresses. @@ -2561,9 +2735,9 @@ bool MipsAsmParser::expandUncondBranchMMPseudo(MCInst &Inst, SMLoc IDLoc, Inst.setOpcode(hasMips32r6() ? Mips::BC16_MMR6 : Mips::B16_MM); } else { if (!isInt<17>(Offset.getImm())) - Error(IDLoc, "branch target out of range"); + return Error(IDLoc, "branch target out of range"); if (OffsetToAlignment(Offset.getImm(), 1LL << 1)) - Error(IDLoc, "branch to misaligned address"); + return Error(IDLoc, "branch to misaligned address"); Inst.clear(); Inst.setOpcode(Mips::BEQ_MM); Inst.addOperand(MCOperand::createReg(Mips::ZERO)); @@ -3168,146 +3342,158 @@ bool MipsAsmParser::expandTrunc(MCInst &Inst, bool IsDouble, bool Is64FPU, bool MipsAsmParser::expandUlh(MCInst &Inst, bool Signed, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { - MipsTargetStreamer &TOut = getTargetStreamer(); - if (hasMips32r6() || hasMips64r6()) { - Error(IDLoc, "instruction not supported on mips32r6 or mips64r6"); - return false; + return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6"); } - warnIfNoMacro(IDLoc); - const MCOperand &DstRegOp = Inst.getOperand(0); assert(DstRegOp.isReg() && "expected register operand kind"); - const MCOperand &SrcRegOp = Inst.getOperand(1); assert(SrcRegOp.isReg() && "expected register operand kind"); - const MCOperand &OffsetImmOp = Inst.getOperand(2); assert(OffsetImmOp.isImm() && "expected immediate operand kind"); + MipsTargetStreamer &TOut = getTargetStreamer(); unsigned DstReg = DstRegOp.getReg(); unsigned SrcReg = SrcRegOp.getReg(); int64_t OffsetValue = OffsetImmOp.getImm(); // NOTE: We always need AT for ULHU, as it is always used as the source // register for one of the LBu's. + warnIfNoMacro(IDLoc); unsigned ATReg = getATReg(IDLoc); if (!ATReg) return true; - // When the value of offset+1 does not fit in 16 bits, we have to load the - // offset in AT, (D)ADDu the original source register (if there was one), and - // then use AT as the source register for the 2 generated LBu's. - bool LoadedOffsetInAT = false; - if (!isInt<16>(OffsetValue + 1) || !isInt<16>(OffsetValue)) { - LoadedOffsetInAT = true; - - if (loadImmediate(OffsetValue, ATReg, Mips::NoRegister, !ABI.ArePtrs64bit(), - true, IDLoc, Out, STI)) + bool IsLargeOffset = !(isInt<16>(OffsetValue + 1) && isInt<16>(OffsetValue)); + if (IsLargeOffset) { + if (loadImmediate(OffsetValue, ATReg, SrcReg, !ABI.ArePtrs64bit(), true, + IDLoc, Out, STI)) return true; - - // NOTE: We do this (D)ADDu here instead of doing it in loadImmediate() - // because it will make our output more similar to GAS'. For example, - // generating an "ori $1, $zero, 32768" followed by an "addu $1, $1, $9", - // instead of just an "ori $1, $9, 32768". - // NOTE: If there is no source register specified in the ULHU, the parser - // will interpret it as $0. - if (SrcReg != Mips::ZERO && SrcReg != Mips::ZERO_64) - TOut.emitAddu(ATReg, ATReg, SrcReg, ABI.ArePtrs64bit(), STI); } - unsigned FirstLbuDstReg = LoadedOffsetInAT ? DstReg : ATReg; - unsigned SecondLbuDstReg = LoadedOffsetInAT ? ATReg : DstReg; - unsigned LbuSrcReg = LoadedOffsetInAT ? ATReg : SrcReg; + int64_t FirstOffset = IsLargeOffset ? 0 : OffsetValue; + int64_t SecondOffset = IsLargeOffset ? 1 : (OffsetValue + 1); + if (isLittle()) + std::swap(FirstOffset, SecondOffset); - int64_t FirstLbuOffset = 0, SecondLbuOffset = 0; - if (isLittle()) { - FirstLbuOffset = LoadedOffsetInAT ? 1 : (OffsetValue + 1); - SecondLbuOffset = LoadedOffsetInAT ? 0 : OffsetValue; - } else { - FirstLbuOffset = LoadedOffsetInAT ? 0 : OffsetValue; - SecondLbuOffset = LoadedOffsetInAT ? 1 : (OffsetValue + 1); - } + unsigned FirstLbuDstReg = IsLargeOffset ? DstReg : ATReg; + unsigned SecondLbuDstReg = IsLargeOffset ? ATReg : DstReg; - unsigned SllReg = LoadedOffsetInAT ? DstReg : ATReg; + unsigned LbuSrcReg = IsLargeOffset ? ATReg : SrcReg; + unsigned SllReg = IsLargeOffset ? DstReg : ATReg; TOut.emitRRI(Signed ? Mips::LB : Mips::LBu, FirstLbuDstReg, LbuSrcReg, - FirstLbuOffset, IDLoc, STI); - - TOut.emitRRI(Mips::LBu, SecondLbuDstReg, LbuSrcReg, SecondLbuOffset, IDLoc, - STI); - + FirstOffset, IDLoc, STI); + TOut.emitRRI(Mips::LBu, SecondLbuDstReg, LbuSrcReg, SecondOffset, IDLoc, STI); TOut.emitRRI(Mips::SLL, SllReg, SllReg, 8, IDLoc, STI); - TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI); return false; } -bool MipsAsmParser::expandUlw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, +bool MipsAsmParser::expandUsh(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, const MCSubtargetInfo *STI) { + if (hasMips32r6() || hasMips64r6()) { + return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6"); + } + + const MCOperand &DstRegOp = Inst.getOperand(0); + assert(DstRegOp.isReg() && "expected register operand kind"); + const MCOperand &SrcRegOp = Inst.getOperand(1); + assert(SrcRegOp.isReg() && "expected register operand kind"); + const MCOperand &OffsetImmOp = Inst.getOperand(2); + assert(OffsetImmOp.isImm() && "expected immediate operand kind"); + MipsTargetStreamer &TOut = getTargetStreamer(); + unsigned DstReg = DstRegOp.getReg(); + unsigned SrcReg = SrcRegOp.getReg(); + int64_t OffsetValue = OffsetImmOp.getImm(); + warnIfNoMacro(IDLoc); + unsigned ATReg = getATReg(IDLoc); + if (!ATReg) + return true; + + bool IsLargeOffset = !(isInt<16>(OffsetValue + 1) && isInt<16>(OffsetValue)); + if (IsLargeOffset) { + if (loadImmediate(OffsetValue, ATReg, SrcReg, !ABI.ArePtrs64bit(), true, + IDLoc, Out, STI)) + return true; + } + + int64_t FirstOffset = IsLargeOffset ? 1 : (OffsetValue + 1); + int64_t SecondOffset = IsLargeOffset ? 0 : OffsetValue; + if (isLittle()) + std::swap(FirstOffset, SecondOffset); + + if (IsLargeOffset) { + TOut.emitRRI(Mips::SB, DstReg, ATReg, FirstOffset, IDLoc, STI); + TOut.emitRRI(Mips::SRL, DstReg, DstReg, 8, IDLoc, STI); + TOut.emitRRI(Mips::SB, DstReg, ATReg, SecondOffset, IDLoc, STI); + TOut.emitRRI(Mips::LBu, ATReg, ATReg, 0, IDLoc, STI); + TOut.emitRRI(Mips::SLL, DstReg, DstReg, 8, IDLoc, STI); + TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI); + } else { + TOut.emitRRI(Mips::SB, DstReg, SrcReg, FirstOffset, IDLoc, STI); + TOut.emitRRI(Mips::SRL, ATReg, DstReg, 8, IDLoc, STI); + TOut.emitRRI(Mips::SB, ATReg, SrcReg, SecondOffset, IDLoc, STI); + } + + return false; +} + +bool MipsAsmParser::expandUxw(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI) { if (hasMips32r6() || hasMips64r6()) { - Error(IDLoc, "instruction not supported on mips32r6 or mips64r6"); - return false; + return Error(IDLoc, "instruction not supported on mips32r6 or mips64r6"); } const MCOperand &DstRegOp = Inst.getOperand(0); assert(DstRegOp.isReg() && "expected register operand kind"); - const MCOperand &SrcRegOp = Inst.getOperand(1); assert(SrcRegOp.isReg() && "expected register operand kind"); - const MCOperand &OffsetImmOp = Inst.getOperand(2); assert(OffsetImmOp.isImm() && "expected immediate operand kind"); + MipsTargetStreamer &TOut = getTargetStreamer(); + unsigned DstReg = DstRegOp.getReg(); unsigned SrcReg = SrcRegOp.getReg(); int64_t OffsetValue = OffsetImmOp.getImm(); - unsigned ATReg = 0; - - // When the value of offset+3 does not fit in 16 bits, we have to load the - // offset in AT, (D)ADDu the original source register (if there was one), and - // then use AT as the source register for the generated LWL and LWR. - bool LoadedOffsetInAT = false; - if (!isInt<16>(OffsetValue + 3) || !isInt<16>(OffsetValue)) { - ATReg = getATReg(IDLoc); - if (!ATReg) - return true; - LoadedOffsetInAT = true; + // Compute left/right load/store offsets. + bool IsLargeOffset = !(isInt<16>(OffsetValue + 3) && isInt<16>(OffsetValue)); + int64_t LxlOffset = IsLargeOffset ? 0 : OffsetValue; + int64_t LxrOffset = IsLargeOffset ? 3 : (OffsetValue + 3); + if (isLittle()) + std::swap(LxlOffset, LxrOffset); + + bool IsLoadInst = (Inst.getOpcode() == Mips::Ulw); + bool DoMove = IsLoadInst && (SrcReg == DstReg) && !IsLargeOffset; + unsigned TmpReg = SrcReg; + if (IsLargeOffset || DoMove) { warnIfNoMacro(IDLoc); - - if (loadImmediate(OffsetValue, ATReg, Mips::NoRegister, !ABI.ArePtrs64bit(), - true, IDLoc, Out, STI)) + TmpReg = getATReg(IDLoc); + if (!TmpReg) return true; + } - // NOTE: We do this (D)ADDu here instead of doing it in loadImmediate() - // because it will make our output more similar to GAS'. For example, - // generating an "ori $1, $zero, 32768" followed by an "addu $1, $1, $9", - // instead of just an "ori $1, $9, 32768". - // NOTE: If there is no source register specified in the ULW, the parser - // will interpret it as $0. - if (SrcReg != Mips::ZERO && SrcReg != Mips::ZERO_64) - TOut.emitAddu(ATReg, ATReg, SrcReg, ABI.ArePtrs64bit(), STI); - } - - unsigned FinalSrcReg = LoadedOffsetInAT ? ATReg : SrcReg; - int64_t LeftLoadOffset = 0, RightLoadOffset = 0; - if (isLittle()) { - LeftLoadOffset = LoadedOffsetInAT ? 3 : (OffsetValue + 3); - RightLoadOffset = LoadedOffsetInAT ? 0 : OffsetValue; - } else { - LeftLoadOffset = LoadedOffsetInAT ? 0 : OffsetValue; - RightLoadOffset = LoadedOffsetInAT ? 3 : (OffsetValue + 3); + if (IsLargeOffset) { + if (loadImmediate(OffsetValue, TmpReg, SrcReg, !ABI.ArePtrs64bit(), true, + IDLoc, Out, STI)) + return true; } - TOut.emitRRI(Mips::LWL, DstRegOp.getReg(), FinalSrcReg, LeftLoadOffset, IDLoc, - STI); + if (DoMove) + std::swap(DstReg, TmpReg); - TOut.emitRRI(Mips::LWR, DstRegOp.getReg(), FinalSrcReg, RightLoadOffset, - IDLoc, STI); + unsigned XWL = IsLoadInst ? Mips::LWL : Mips::SWL; + unsigned XWR = IsLoadInst ? Mips::LWR : Mips::SWR; + TOut.emitRRI(XWL, DstReg, TmpReg, LxlOffset, IDLoc, STI); + TOut.emitRRI(XWR, DstReg, TmpReg, LxrOffset, IDLoc, STI); + + if (DoMove) + TOut.emitRRR(Mips::OR, TmpReg, DstReg, Mips::ZERO, IDLoc, STI); return false; } @@ -3685,8 +3871,198 @@ bool MipsAsmParser::expandAbs(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, return false; } +static unsigned nextReg(unsigned Reg) { + switch (Reg) { + case Mips::ZERO: return Mips::AT; + case Mips::AT: return Mips::V0; + case Mips::V0: return Mips::V1; + case Mips::V1: return Mips::A0; + case Mips::A0: return Mips::A1; + case Mips::A1: return Mips::A2; + case Mips::A2: return Mips::A3; + case Mips::A3: return Mips::T0; + case Mips::T0: return Mips::T1; + case Mips::T1: return Mips::T2; + case Mips::T2: return Mips::T3; + case Mips::T3: return Mips::T4; + case Mips::T4: return Mips::T5; + case Mips::T5: return Mips::T6; + case Mips::T6: return Mips::T7; + case Mips::T7: return Mips::S0; + case Mips::S0: return Mips::S1; + case Mips::S1: return Mips::S2; + case Mips::S2: return Mips::S3; + case Mips::S3: return Mips::S4; + case Mips::S4: return Mips::S5; + case Mips::S5: return Mips::S6; + case Mips::S6: return Mips::S7; + case Mips::S7: return Mips::T8; + case Mips::T8: return Mips::T9; + case Mips::T9: return Mips::K0; + case Mips::K0: return Mips::K1; + case Mips::K1: return Mips::GP; + case Mips::GP: return Mips::SP; + case Mips::SP: return Mips::FP; + case Mips::FP: return Mips::RA; + case Mips::RA: return Mips::ZERO; + default: return 0; + } + +} + +// Expand 'ld $<reg> offset($reg2)' to 'lw $<reg>, offset($reg2); +// lw $<reg+1>>, offset+4($reg2)' +// or expand 'sd $<reg> offset($reg2)' to 'sw $<reg>, offset($reg2); +// sw $<reg+1>>, offset+4($reg2)' +// for O32. +bool MipsAsmParser::expandLoadStoreDMacro(MCInst &Inst, SMLoc IDLoc, + MCStreamer &Out, + const MCSubtargetInfo *STI, + bool IsLoad) { + if (!isABI_O32()) + return true; + + warnIfNoMacro(IDLoc); + + MipsTargetStreamer &TOut = getTargetStreamer(); + unsigned Opcode = IsLoad ? Mips::LW : Mips::SW; + unsigned FirstReg = Inst.getOperand(0).getReg(); + unsigned SecondReg = nextReg(FirstReg); + unsigned BaseReg = Inst.getOperand(1).getReg(); + if (!SecondReg) + return true; + + warnIfRegIndexIsAT(FirstReg, IDLoc); + + assert(Inst.getOperand(2).isImm() && + "Offset for load macro is not immediate!"); + + MCOperand &FirstOffset = Inst.getOperand(2); + signed NextOffset = FirstOffset.getImm() + 4; + MCOperand SecondOffset = MCOperand::createImm(NextOffset); + + if (!isInt<16>(FirstOffset.getImm()) || !isInt<16>(NextOffset)) + return true; + + // For loads, clobber the base register with the second load instead of the + // first if the BaseReg == FirstReg. + if (FirstReg != BaseReg || !IsLoad) { + TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI); + TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI); + } else { + TOut.emitRRX(Opcode, SecondReg, BaseReg, SecondOffset, IDLoc, STI); + TOut.emitRRX(Opcode, FirstReg, BaseReg, FirstOffset, IDLoc, STI); + } + + return false; +} + +bool MipsAsmParser::expandSeq(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI) { + + warnIfNoMacro(IDLoc); + MipsTargetStreamer &TOut = getTargetStreamer(); + + if (Inst.getOperand(1).getReg() != Mips::ZERO && + Inst.getOperand(2).getReg() != Mips::ZERO) { + TOut.emitRRR(Mips::XOR, Inst.getOperand(0).getReg(), + Inst.getOperand(1).getReg(), Inst.getOperand(2).getReg(), + IDLoc, STI); + TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(), + Inst.getOperand(0).getReg(), 1, IDLoc, STI); + return false; + } + + unsigned Reg = 0; + if (Inst.getOperand(1).getReg() == Mips::ZERO) { + Reg = Inst.getOperand(2).getReg(); + } else { + Reg = Inst.getOperand(1).getReg(); + } + TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(), Reg, 1, IDLoc, STI); + return false; +} + +bool MipsAsmParser::expandSeqI(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI) { + + warnIfNoMacro(IDLoc); + MipsTargetStreamer &TOut = getTargetStreamer(); + + unsigned Opc; + int64_t Imm = Inst.getOperand(2).getImm(); + unsigned Reg = Inst.getOperand(1).getReg(); + + if (Imm == 0) { + TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(), + Inst.getOperand(1).getReg(), 1, IDLoc, STI); + return false; + } else { + + if (Reg == Mips::ZERO) { + Warning(IDLoc, "comparison is always false"); + TOut.emitRRR(isGP64bit() ? Mips::DADDu : Mips::ADDu, + Inst.getOperand(0).getReg(), Reg, Reg, IDLoc, STI); + return false; + } + + if (Imm > -0x8000 && Imm < 0) { + Imm = -Imm; + Opc = isGP64bit() ? Mips::DADDiu : Mips::ADDiu; + } else { + Opc = Mips::XORi; + } + } + if (!isUInt<16>(Imm)) { + unsigned ATReg = getATReg(IDLoc); + if (!ATReg) + return true; + + if (loadImmediate(Imm, ATReg, Mips::NoRegister, true, isGP64bit(), IDLoc, + Out, STI)) + return true; + + TOut.emitRRR(Mips::XOR, Inst.getOperand(0).getReg(), + Inst.getOperand(1).getReg(), ATReg, IDLoc, STI); + TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(), + Inst.getOperand(0).getReg(), 1, IDLoc, STI); + return false; + } + + TOut.emitRRI(Opc, Inst.getOperand(0).getReg(), Inst.getOperand(1).getReg(), + Imm, IDLoc, STI); + TOut.emitRRI(Mips::SLTiu, Inst.getOperand(0).getReg(), + Inst.getOperand(0).getReg(), 1, IDLoc, STI); + return false; +} + +unsigned +MipsAsmParser::checkEarlyTargetMatchPredicate(MCInst &Inst, + const OperandVector &Operands) { + switch (Inst.getOpcode()) { + default: + return Match_Success; + case Mips::DATI: + case Mips::DAHI: + case Mips::DATI_MM64R6: + case Mips::DAHI_MM64R6: + if (static_cast<MipsOperand &>(*Operands[1]) + .isValidForTie(static_cast<MipsOperand &>(*Operands[2]))) + return Match_Success; + return Match_RequiresSameSrcAndDst; + } +} + unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) { switch (Inst.getOpcode()) { + // As described by the MIPSR6 spec, daui must not use the zero operand for + // its source operand. + case Mips::DAUI: + case Mips::DAUI_MM64R6: + if (Inst.getOperand(1).getReg() == Mips::ZERO || + Inst.getOperand(1).getReg() == Mips::ZERO_64) + return Match_RequiresNoZeroRegister; + return Match_Success; // As described by the Mips32r2 spec, the registers Rd and Rs for // jalr.hb must be different. // It also applies for registers Rt and Rs of microMIPSr6 jalrc.hb instruction @@ -3702,6 +4078,10 @@ unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) { if (Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) return Match_RequiresDifferentSrcAndDst; return Match_Success; + case Mips::SYNC: + if (Inst.getOperand(0).getImm() != 0 && !hasMips32()) + return Match_NonZeroOperandForSync; + return Match_Success; // As described the MIPSR6 spec, the compact branches that compare registers // must: // a) Not use the zero register. @@ -3714,31 +4094,52 @@ unsigned MipsAsmParser::checkTargetMatchPredicate(MCInst &Inst) { // The compact branches that branch iff the signed addition of two registers // would overflow must have rs >= rt. That can be handled like beqc/bnec with // operand swapping. They do not have restriction of using the zero register. - case Mips::BLEZC: - case Mips::BGEZC: - case Mips::BGTZC: - case Mips::BLTZC: - case Mips::BEQZC: - case Mips::BNEZC: - if (Inst.getOperand(0).getReg() == Mips::ZERO) + case Mips::BLEZC: case Mips::BLEZC_MMR6: + case Mips::BGEZC: case Mips::BGEZC_MMR6: + case Mips::BGTZC: case Mips::BGTZC_MMR6: + case Mips::BLTZC: case Mips::BLTZC_MMR6: + case Mips::BEQZC: case Mips::BEQZC_MMR6: + case Mips::BNEZC: case Mips::BNEZC_MMR6: + case Mips::BLEZC64: + case Mips::BGEZC64: + case Mips::BGTZC64: + case Mips::BLTZC64: + case Mips::BEQZC64: + case Mips::BNEZC64: + if (Inst.getOperand(0).getReg() == Mips::ZERO || + Inst.getOperand(0).getReg() == Mips::ZERO_64) return Match_RequiresNoZeroRegister; return Match_Success; - case Mips::BGEC: - case Mips::BLTC: - case Mips::BGEUC: - case Mips::BLTUC: - case Mips::BEQC: - case Mips::BNEC: - if (Inst.getOperand(0).getReg() == Mips::ZERO) + case Mips::BGEC: case Mips::BGEC_MMR6: + case Mips::BLTC: case Mips::BLTC_MMR6: + case Mips::BGEUC: case Mips::BGEUC_MMR6: + case Mips::BLTUC: case Mips::BLTUC_MMR6: + case Mips::BEQC: case Mips::BEQC_MMR6: + case Mips::BNEC: case Mips::BNEC_MMR6: + case Mips::BGEC64: + case Mips::BLTC64: + case Mips::BGEUC64: + case Mips::BLTUC64: + case Mips::BEQC64: + case Mips::BNEC64: + if (Inst.getOperand(0).getReg() == Mips::ZERO || + Inst.getOperand(0).getReg() == Mips::ZERO_64) return Match_RequiresNoZeroRegister; - if (Inst.getOperand(1).getReg() == Mips::ZERO) + if (Inst.getOperand(1).getReg() == Mips::ZERO || + Inst.getOperand(1).getReg() == Mips::ZERO_64) return Match_RequiresNoZeroRegister; if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) return Match_RequiresDifferentOperands; return Match_Success; - default: - return Match_Success; } + + uint64_t TSFlags = getInstDesc(Inst.getOpcode()).TSFlags; + if ((TSFlags & MipsII::HasFCCRegOperand) && + (Inst.getOperand(0).getReg() != Mips::FCC0) && !hasEightFccRegisters()) + return Match_NoFCCRegisterForCurrentISA; + + return Match_Success; + } static SMLoc RefineErrorLoc(const SMLoc Loc, const OperandVector &Operands, @@ -3784,6 +4185,8 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, return Error(ErrorLoc, "invalid operand for instruction"); } + case Match_NonZeroOperandForSync: + return Error(IDLoc, "s-type must be zero or unspecified for pre-MIPS32 ISAs"); case Match_MnemonicFail: return Error(IDLoc, "invalid instruction"); case Match_RequiresDifferentSrcAndDst: @@ -3792,6 +4195,11 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, return Error(IDLoc, "registers must be different"); case Match_RequiresNoZeroRegister: return Error(IDLoc, "invalid operand ($zero) for instruction"); + case Match_RequiresSameSrcAndDst: + return Error(IDLoc, "source and destination must match"); + case Match_NoFCCRegisterForCurrentISA: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "non-zero fcc register doesn't exist in current ISA level"); case Match_Immz: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected '0'"); case Match_UImm1_0: @@ -3876,6 +4284,9 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_SImm16_Relaxed: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 16-bit signed immediate"); + case Match_SImm19_Lsl2: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected both 19-bit signed immediate and multiple of 4"); case Match_UImm20_0: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 20-bit unsigned immediate"); @@ -3886,6 +4297,9 @@ bool MipsAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, case Match_SImm32_Relaxed: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected 32-bit signed immediate"); + case Match_UImm32_Coerced: + return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), + "expected 32-bit immediate"); case Match_MemSImm9: return Error(RefineErrorLoc(IDLoc, Operands, ErrorInfo), "expected memory with 9-bit signed offset"); @@ -4131,9 +4545,6 @@ bool MipsAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { DEBUG(dbgs() << ".. Generic Parser\n"); switch (getLexer().getKind()) { - default: - Error(Parser.getTok().getLoc(), "unexpected token in operand"); - return true; case AsmToken::Dollar: { // Parse the register. SMLoc S = Parser.getTok().getLoc(); @@ -4160,72 +4571,23 @@ bool MipsAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { Operands.push_back(MipsOperand::CreateImm(Res, S, E, *this)); return false; } - // Else drop to expression parsing. - case AsmToken::LParen: - case AsmToken::Minus: - case AsmToken::Plus: - case AsmToken::Integer: - case AsmToken::Tilde: - case AsmToken::String: { - DEBUG(dbgs() << ".. generic integer\n"); - OperandMatchResultTy ResTy = parseImm(Operands); - return ResTy != MatchOperand_Success; - } - case AsmToken::Percent: { - // It is a symbol reference or constant expression. - const MCExpr *IdVal; + default: { + DEBUG(dbgs() << ".. generic integer expression\n"); + + const MCExpr *Expr; SMLoc S = Parser.getTok().getLoc(); // Start location of the operand. - if (parseRelocOperand(IdVal)) + if (getParser().parseExpression(Expr)) return true; SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); - Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this)); + Operands.push_back(MipsOperand::CreateImm(Expr, S, E, *this)); return false; - } // case AsmToken::Percent + } } // switch(getLexer().getKind()) return true; } -const MCExpr *MipsAsmParser::evaluateRelocExpr(const MCExpr *Expr, - StringRef RelocStr) { - if (RelocStr == "hi(%neg(%gp_rel") - return MipsMCExpr::createGpOff(MipsMCExpr::MEK_HI, Expr, getContext()); - else if (RelocStr == "lo(%neg(%gp_rel") - return MipsMCExpr::createGpOff(MipsMCExpr::MEK_LO, Expr, getContext()); - - MipsMCExpr::MipsExprKind Kind = - StringSwitch<MipsMCExpr::MipsExprKind>(RelocStr) - .Case("call16", MipsMCExpr::MEK_GOT_CALL) - .Case("call_hi", MipsMCExpr::MEK_CALL_HI16) - .Case("call_lo", MipsMCExpr::MEK_CALL_LO16) - .Case("dtprel_hi", MipsMCExpr::MEK_DTPREL_HI) - .Case("dtprel_lo", MipsMCExpr::MEK_DTPREL_LO) - .Case("got", MipsMCExpr::MEK_GOT) - .Case("got_disp", MipsMCExpr::MEK_GOT_DISP) - .Case("got_hi", MipsMCExpr::MEK_GOT_HI16) - .Case("got_lo", MipsMCExpr::MEK_GOT_LO16) - .Case("got_ofst", MipsMCExpr::MEK_GOT_OFST) - .Case("got_page", MipsMCExpr::MEK_GOT_PAGE) - .Case("gottprel", MipsMCExpr::MEK_GOTTPREL) - .Case("gp_rel", MipsMCExpr::MEK_GPREL) - .Case("hi", MipsMCExpr::MEK_HI) - .Case("higher", MipsMCExpr::MEK_HIGHER) - .Case("highest", MipsMCExpr::MEK_HIGHEST) - .Case("lo", MipsMCExpr::MEK_LO) - .Case("neg", MipsMCExpr::MEK_NEG) - .Case("pcrel_hi", MipsMCExpr::MEK_PCREL_HI16) - .Case("pcrel_lo", MipsMCExpr::MEK_PCREL_LO16) - .Case("tlsgd", MipsMCExpr::MEK_TLSGD) - .Case("tlsldm", MipsMCExpr::MEK_TLSLDM) - .Case("tprel_hi", MipsMCExpr::MEK_TPREL_HI) - .Case("tprel_lo", MipsMCExpr::MEK_TPREL_LO) - .Default(MipsMCExpr::MEK_None); - - assert(Kind != MipsMCExpr::MEK_None); - return MipsMCExpr::create(Kind, Expr, getContext()); -} - bool MipsAsmParser::isEvaluated(const MCExpr *Expr) { switch (Expr->getKind()) { @@ -4247,49 +4609,6 @@ bool MipsAsmParser::isEvaluated(const MCExpr *Expr) { return false; } -bool MipsAsmParser::parseRelocOperand(const MCExpr *&Res) { - MCAsmParser &Parser = getParser(); - Parser.Lex(); // Eat the % token. - const AsmToken &Tok = Parser.getTok(); // Get next token, operation. - if (Tok.isNot(AsmToken::Identifier)) - return true; - - std::string Str = Tok.getIdentifier(); - - Parser.Lex(); // Eat the identifier. - // Now make an expression from the rest of the operand. - const MCExpr *IdVal; - SMLoc EndLoc; - - if (getLexer().getKind() == AsmToken::LParen) { - while (1) { - Parser.Lex(); // Eat the '(' token. - if (getLexer().getKind() == AsmToken::Percent) { - Parser.Lex(); // Eat the % token. - const AsmToken &nextTok = Parser.getTok(); - if (nextTok.isNot(AsmToken::Identifier)) - return true; - Str += "(%"; - Str += nextTok.getIdentifier(); - Parser.Lex(); // Eat the identifier. - if (getLexer().getKind() != AsmToken::LParen) - return true; - } else - break; - } - if (getParser().parseParenExpression(IdVal, EndLoc)) - return true; - - while (getLexer().getKind() == AsmToken::RParen) - Parser.Lex(); // Eat the ')' token. - - } else - return true; // Parenthesis must follow the relocation operand. - - Res = evaluateRelocExpr(IdVal, Str); - return false; -} - bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands; @@ -4317,45 +4636,21 @@ bool MipsAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, } bool MipsAsmParser::parseMemOffset(const MCExpr *&Res, bool isParenExpr) { - MCAsmParser &Parser = getParser(); SMLoc S; - bool Result = true; - unsigned NumOfLParen = 0; - - while (getLexer().getKind() == AsmToken::LParen) { - Parser.Lex(); - ++NumOfLParen; - } - switch (getLexer().getKind()) { - default: - return true; - case AsmToken::Identifier: - case AsmToken::LParen: - case AsmToken::Integer: - case AsmToken::Minus: - case AsmToken::Plus: - if (isParenExpr) - Result = getParser().parseParenExprOfDepth(NumOfLParen, Res, S); - else - Result = (getParser().parseExpression(Res)); - while (getLexer().getKind() == AsmToken::RParen) - Parser.Lex(); - break; - case AsmToken::Percent: - Result = parseRelocOperand(Res); - } - return Result; + if (isParenExpr) + return getParser().parseParenExprOfDepth(0, Res, S); + return getParser().parseExpression(Res); } -MipsAsmParser::OperandMatchResultTy +OperandMatchResultTy MipsAsmParser::parseMemOperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); DEBUG(dbgs() << "parseMemOperand\n"); const MCExpr *IdVal = nullptr; SMLoc S; bool isParenExpr = false; - MipsAsmParser::OperandMatchResultTy Res = MatchOperand_NoMatch; + OperandMatchResultTy Res = MatchOperand_NoMatch; // First operand is the offset. S = Parser.getTok().getLoc(); @@ -4383,14 +4678,66 @@ MipsAsmParser::parseMemOperand(OperandVector &Operands) { // Zero register assumed, add a memory operand with ZERO as its base. // "Base" will be managed by k_Memory. - auto Base = MipsOperand::createGPRReg(0, getContext().getRegisterInfo(), - S, E, *this); + auto Base = MipsOperand::createGPRReg( + 0, "0", getContext().getRegisterInfo(), S, E, *this); Operands.push_back( MipsOperand::CreateMem(std::move(Base), IdVal, S, E, *this)); return MatchOperand_Success; } - Error(Parser.getTok().getLoc(), "'(' expected"); - return MatchOperand_ParseFail; + MCBinaryExpr::Opcode Opcode; + // GAS and LLVM treat comparison operators different. GAS will generate -1 + // or 0, while LLVM will generate 0 or 1. Since a comparsion operator is + // highly unlikely to be found in a memory offset expression, we don't + // handle them. + switch (Tok.getKind()) { + case AsmToken::Plus: + Opcode = MCBinaryExpr::Add; + Parser.Lex(); + break; + case AsmToken::Minus: + Opcode = MCBinaryExpr::Sub; + Parser.Lex(); + break; + case AsmToken::Star: + Opcode = MCBinaryExpr::Mul; + Parser.Lex(); + break; + case AsmToken::Pipe: + Opcode = MCBinaryExpr::Or; + Parser.Lex(); + break; + case AsmToken::Amp: + Opcode = MCBinaryExpr::And; + Parser.Lex(); + break; + case AsmToken::LessLess: + Opcode = MCBinaryExpr::Shl; + Parser.Lex(); + break; + case AsmToken::GreaterGreater: + Opcode = MCBinaryExpr::LShr; + Parser.Lex(); + break; + case AsmToken::Caret: + Opcode = MCBinaryExpr::Xor; + Parser.Lex(); + break; + case AsmToken::Slash: + Opcode = MCBinaryExpr::Div; + Parser.Lex(); + break; + case AsmToken::Percent: + Opcode = MCBinaryExpr::Mod; + Parser.Lex(); + break; + default: + Error(Parser.getTok().getLoc(), "'(' or expression expected"); + return MatchOperand_ParseFail; + } + const MCExpr * NextExpr; + if (getParser().parseExpression(NextExpr)) + return MatchOperand_ParseFail; + IdVal = MCBinaryExpr::create(Opcode, IdVal, NextExpr, getContext()); } Parser.Lex(); // Eat the '(' token. @@ -4460,63 +4807,70 @@ bool MipsAsmParser::searchSymbolAlias(OperandVector &Operands) { return false; } -MipsAsmParser::OperandMatchResultTy +OperandMatchResultTy MipsAsmParser::matchAnyRegisterNameWithoutDollar(OperandVector &Operands, StringRef Identifier, SMLoc S) { int Index = matchCPURegisterName(Identifier); if (Index != -1) { Operands.push_back(MipsOperand::createGPRReg( - Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this)); + Index, Identifier, getContext().getRegisterInfo(), S, + getLexer().getLoc(), *this)); return MatchOperand_Success; } Index = matchHWRegsRegisterName(Identifier); if (Index != -1) { Operands.push_back(MipsOperand::createHWRegsReg( - Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this)); + Index, Identifier, getContext().getRegisterInfo(), S, + getLexer().getLoc(), *this)); return MatchOperand_Success; } Index = matchFPURegisterName(Identifier); if (Index != -1) { Operands.push_back(MipsOperand::createFGRReg( - Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this)); + Index, Identifier, getContext().getRegisterInfo(), S, + getLexer().getLoc(), *this)); return MatchOperand_Success; } Index = matchFCCRegisterName(Identifier); if (Index != -1) { Operands.push_back(MipsOperand::createFCCReg( - Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this)); + Index, Identifier, getContext().getRegisterInfo(), S, + getLexer().getLoc(), *this)); return MatchOperand_Success; } Index = matchACRegisterName(Identifier); if (Index != -1) { Operands.push_back(MipsOperand::createACCReg( - Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this)); + Index, Identifier, getContext().getRegisterInfo(), S, + getLexer().getLoc(), *this)); return MatchOperand_Success; } Index = matchMSA128RegisterName(Identifier); if (Index != -1) { Operands.push_back(MipsOperand::createMSA128Reg( - Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this)); + Index, Identifier, getContext().getRegisterInfo(), S, + getLexer().getLoc(), *this)); return MatchOperand_Success; } Index = matchMSA128CtrlRegisterName(Identifier); if (Index != -1) { Operands.push_back(MipsOperand::createMSACtrlReg( - Index, getContext().getRegisterInfo(), S, getLexer().getLoc(), *this)); + Index, Identifier, getContext().getRegisterInfo(), S, + getLexer().getLoc(), *this)); return MatchOperand_Success; } return MatchOperand_NoMatch; } -MipsAsmParser::OperandMatchResultTy +OperandMatchResultTy MipsAsmParser::matchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S) { MCAsmParser &Parser = getParser(); auto Token = Parser.getLexer().peekTok(false); @@ -4530,8 +4884,8 @@ MipsAsmParser::matchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S) { } else if (Token.is(AsmToken::Integer)) { DEBUG(dbgs() << ".. integer\n"); Operands.push_back(MipsOperand::createNumericReg( - Token.getIntVal(), getContext().getRegisterInfo(), S, Token.getLoc(), - *this)); + Token.getIntVal(), Token.getString(), getContext().getRegisterInfo(), S, + Token.getLoc(), *this)); return MatchOperand_Success; } @@ -4540,7 +4894,7 @@ MipsAsmParser::matchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S) { return MatchOperand_NoMatch; } -MipsAsmParser::OperandMatchResultTy +OperandMatchResultTy MipsAsmParser::parseAnyRegister(OperandVector &Operands) { MCAsmParser &Parser = getParser(); DEBUG(dbgs() << "parseAnyRegister\n"); @@ -4568,48 +4922,19 @@ MipsAsmParser::parseAnyRegister(OperandVector &Operands) { return ResTy; } -MipsAsmParser::OperandMatchResultTy -MipsAsmParser::parseImm(OperandVector &Operands) { - MCAsmParser &Parser = getParser(); - switch (getLexer().getKind()) { - default: - return MatchOperand_NoMatch; - case AsmToken::LParen: - case AsmToken::Minus: - case AsmToken::Plus: - case AsmToken::Integer: - case AsmToken::Tilde: - case AsmToken::String: - break; - } - - const MCExpr *IdVal; - SMLoc S = Parser.getTok().getLoc(); - if (getParser().parseExpression(IdVal)) - return MatchOperand_ParseFail; - - SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); - Operands.push_back(MipsOperand::CreateImm(IdVal, S, E, *this)); - return MatchOperand_Success; -} - -MipsAsmParser::OperandMatchResultTy +OperandMatchResultTy MipsAsmParser::parseJumpTarget(OperandVector &Operands) { MCAsmParser &Parser = getParser(); DEBUG(dbgs() << "parseJumpTarget\n"); SMLoc S = getLexer().getLoc(); - // Integers and expressions are acceptable - OperandMatchResultTy ResTy = parseImm(Operands); - if (ResTy != MatchOperand_NoMatch) - return ResTy; - // Registers are a valid target and have priority over symbols. - ResTy = parseAnyRegister(Operands); + OperandMatchResultTy ResTy = parseAnyRegister(Operands); if (ResTy != MatchOperand_NoMatch) return ResTy; + // Integers and expressions are acceptable const MCExpr *Expr = nullptr; if (Parser.parseExpression(Expr)) { // We have no way of knowing if a symbol was consumed so we must ParseFail @@ -4620,7 +4945,7 @@ MipsAsmParser::parseJumpTarget(OperandVector &Operands) { return MatchOperand_Success; } -MipsAsmParser::OperandMatchResultTy +OperandMatchResultTy MipsAsmParser::parseInvNum(OperandVector &Operands) { MCAsmParser &Parser = getParser(); const MCExpr *IdVal; @@ -4639,7 +4964,7 @@ MipsAsmParser::parseInvNum(OperandVector &Operands) { return MatchOperand_Success; } -MipsAsmParser::OperandMatchResultTy +OperandMatchResultTy MipsAsmParser::parseRegisterList(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SmallVector<unsigned, 10> Regs; @@ -4725,7 +5050,7 @@ MipsAsmParser::parseRegisterList(OperandVector &Operands) { return MatchOperand_Success; } -MipsAsmParser::OperandMatchResultTy +OperandMatchResultTy MipsAsmParser::parseRegisterPair(OperandVector &Operands) { MCAsmParser &Parser = getParser(); @@ -4741,7 +5066,7 @@ MipsAsmParser::parseRegisterPair(OperandVector &Operands) { return MatchOperand_Success; } -MipsAsmParser::OperandMatchResultTy +OperandMatchResultTy MipsAsmParser::parseMovePRegPair(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> TmpOperands; @@ -4793,12 +5118,10 @@ bool MipsAsmParser::parseParenSuffix(StringRef Name, OperandVector &Operands) { Parser.Lex(); if (parseOperand(Operands, Name)) { SMLoc Loc = getLexer().getLoc(); - Parser.eatToEndOfStatement(); return Error(Loc, "unexpected token in argument list"); } if (Parser.getTok().isNot(AsmToken::RParen)) { SMLoc Loc = getLexer().getLoc(); - Parser.eatToEndOfStatement(); return Error(Loc, "unexpected token, expected ')'"); } Operands.push_back( @@ -4823,12 +5146,10 @@ bool MipsAsmParser::parseBracketSuffix(StringRef Name, Parser.Lex(); if (parseOperand(Operands, Name)) { SMLoc Loc = getLexer().getLoc(); - Parser.eatToEndOfStatement(); return Error(Loc, "unexpected token in argument list"); } if (Parser.getTok().isNot(AsmToken::RBrac)) { SMLoc Loc = getLexer().getLoc(); - Parser.eatToEndOfStatement(); return Error(Loc, "unexpected token, expected ']'"); } Operands.push_back( @@ -4848,7 +5169,6 @@ bool MipsAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, // Check if we have valid mnemonic if (!mnemonicIsValid(Name, 0)) { - Parser.eatToEndOfStatement(); return Error(NameLoc, "unknown instruction"); } // First operand in MCInst is instruction mnemonic. @@ -4859,7 +5179,6 @@ bool MipsAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, // Read the first operand. if (parseOperand(Operands, Name)) { SMLoc Loc = getLexer().getLoc(); - Parser.eatToEndOfStatement(); return Error(Loc, "unexpected token in argument list"); } if (getLexer().is(AsmToken::LBrac) && parseBracketSuffix(Name, Operands)) @@ -4871,7 +5190,6 @@ bool MipsAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, // Parse and remember the operand. if (parseOperand(Operands, Name)) { SMLoc Loc = getLexer().getLoc(); - Parser.eatToEndOfStatement(); return Error(Loc, "unexpected token in argument list"); } // Parse bracket and parenthesis suffixes before we iterate @@ -4885,7 +5203,6 @@ bool MipsAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, } if (getLexer().isNot(AsmToken::EndOfStatement)) { SMLoc Loc = getLexer().getLoc(); - Parser.eatToEndOfStatement(); return Error(Loc, "unexpected token in argument list"); } Parser.Lex(); // Consume the EndOfStatement. @@ -4895,9 +5212,7 @@ bool MipsAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, // FIXME: Given that these have the same name, these should both be // consistent on affecting the Parser. bool MipsAsmParser::reportParseError(Twine ErrorMsg) { - MCAsmParser &Parser = getParser(); SMLoc Loc = getLexer().getLoc(); - Parser.eatToEndOfStatement(); return Error(Loc, ErrorMsg); } @@ -5398,7 +5713,6 @@ bool MipsAsmParser::eatComma(StringRef ErrorStr) { MCAsmParser &Parser = getParser(); if (getLexer().isNot(AsmToken::Comma)) { SMLoc Loc = getLexer().getLoc(); - Parser.eatToEndOfStatement(); return Error(Loc, ErrorStr); } @@ -5507,7 +5821,6 @@ bool MipsAsmParser::parseDirectiveCPSetup() { MipsOperand &FuncRegOpnd = static_cast<MipsOperand &>(*TmpReg[0]); if (!FuncRegOpnd.isGPRAsmReg()) { reportParseError(FuncRegOpnd.getStartLoc(), "invalid register"); - Parser.eatToEndOfStatement(); return false; } @@ -5526,7 +5839,6 @@ bool MipsAsmParser::parseDirectiveCPSetup() { if (Parser.parseExpression(OffsetExpr) || !OffsetExpr->evaluateAsAbsolute(OffsetVal)) { reportParseError(ExprLoc, "expected save register or stack offset"); - Parser.eatToEndOfStatement(); return false; } @@ -5536,7 +5848,6 @@ bool MipsAsmParser::parseDirectiveCPSetup() { MipsOperand &SaveOpnd = static_cast<MipsOperand &>(*TmpReg[0]); if (!SaveOpnd.isGPRAsmReg()) { reportParseError(SaveOpnd.getStartLoc(), "invalid register"); - Parser.eatToEndOfStatement(); return false; } Save = SaveOpnd.getGPR32Reg(); @@ -5740,7 +6051,79 @@ bool MipsAsmParser::parseDirectiveGpDWord() { getParser().getStreamer().EmitGPRel64Value(Value); if (getLexer().isNot(AsmToken::EndOfStatement)) - return Error(getLexer().getLoc(), + return Error(getLexer().getLoc(), + "unexpected token, expected end of statement"); + Parser.Lex(); // Eat EndOfStatement token. + return false; +} + +/// parseDirectiveDtpRelWord +/// ::= .dtprelword tls_sym +bool MipsAsmParser::parseDirectiveDtpRelWord() { + MCAsmParser &Parser = getParser(); + const MCExpr *Value; + // EmitDTPRel32Value requires an expression, so we are using base class + // method to evaluate the expression. + if (getParser().parseExpression(Value)) + return true; + getParser().getStreamer().EmitDTPRel32Value(Value); + + if (getLexer().isNot(AsmToken::EndOfStatement)) + return Error(getLexer().getLoc(), + "unexpected token, expected end of statement"); + Parser.Lex(); // Eat EndOfStatement token. + return false; +} + +/// parseDirectiveDtpRelDWord +/// ::= .dtpreldword tls_sym +bool MipsAsmParser::parseDirectiveDtpRelDWord() { + MCAsmParser &Parser = getParser(); + const MCExpr *Value; + // EmitDTPRel64Value requires an expression, so we are using base class + // method to evaluate the expression. + if (getParser().parseExpression(Value)) + return true; + getParser().getStreamer().EmitDTPRel64Value(Value); + + if (getLexer().isNot(AsmToken::EndOfStatement)) + return Error(getLexer().getLoc(), + "unexpected token, expected end of statement"); + Parser.Lex(); // Eat EndOfStatement token. + return false; +} + +/// parseDirectiveTpRelWord +/// ::= .tprelword tls_sym +bool MipsAsmParser::parseDirectiveTpRelWord() { + MCAsmParser &Parser = getParser(); + const MCExpr *Value; + // EmitTPRel32Value requires an expression, so we are using base class + // method to evaluate the expression. + if (getParser().parseExpression(Value)) + return true; + getParser().getStreamer().EmitTPRel32Value(Value); + + if (getLexer().isNot(AsmToken::EndOfStatement)) + return Error(getLexer().getLoc(), + "unexpected token, expected end of statement"); + Parser.Lex(); // Eat EndOfStatement token. + return false; +} + +/// parseDirectiveTpRelDWord +/// ::= .tpreldword tls_sym +bool MipsAsmParser::parseDirectiveTpRelDWord() { + MCAsmParser &Parser = getParser(); + const MCExpr *Value; + // EmitTPRel64Value requires an expression, so we are using base class + // method to evaluate the expression. + if (getParser().parseExpression(Value)) + return true; + getParser().getStreamer().EmitTPRel64Value(Value); + + if (getLexer().isNot(AsmToken::EndOfStatement)) + return Error(getLexer().getLoc(), "unexpected token, expected end of statement"); Parser.Lex(); // Eat EndOfStatement token. return false; @@ -5752,9 +6135,8 @@ bool MipsAsmParser::parseDirectiveOption() { AsmToken Tok = Parser.getTok(); // At the moment only identifiers are supported. if (Tok.isNot(AsmToken::Identifier)) { - Error(Parser.getTok().getLoc(), "unexpected token, expected identifier"); - Parser.eatToEndOfStatement(); - return false; + return Error(Parser.getTok().getLoc(), + "unexpected token, expected identifier"); } StringRef Option = Tok.getIdentifier(); @@ -5766,9 +6148,8 @@ bool MipsAsmParser::parseDirectiveOption() { getTargetStreamer().emitDirectiveOptionPic0(); Parser.Lex(); if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { - Error(Parser.getTok().getLoc(), - "unexpected token, expected end of statement"); - Parser.eatToEndOfStatement(); + return Error(Parser.getTok().getLoc(), + "unexpected token, expected end of statement"); } return false; } @@ -5780,9 +6161,8 @@ bool MipsAsmParser::parseDirectiveOption() { getTargetStreamer().emitDirectiveOptionPic2(); Parser.Lex(); if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { - Error(Parser.getTok().getLoc(), - "unexpected token, expected end of statement"); - Parser.eatToEndOfStatement(); + return Error(Parser.getTok().getLoc(), + "unexpected token, expected end of statement"); } return false; } @@ -5873,8 +6253,7 @@ bool MipsAsmParser::parseDirectiveModule() { return false; // parseDirectiveModule has finished successfully. } else if (Option == "nooddspreg") { if (!isABI_O32()) { - Error(L, "'.module nooddspreg' requires the O32 ABI"); - return false; + return Error(L, "'.module nooddspreg' requires the O32 ABI"); } setModuleFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg"); @@ -6295,6 +6674,26 @@ bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) { return false; } + if (IDVal == ".dtprelword") { + parseDirectiveDtpRelWord(); + return false; + } + + if (IDVal == ".dtpreldword") { + parseDirectiveDtpRelDWord(); + return false; + } + + if (IDVal == ".tprelword") { + parseDirectiveTpRelWord(); + return false; + } + + if (IDVal == ".tpreldword") { + parseDirectiveTpRelDWord(); + return false; + } + if (IDVal == ".word") { parseDataDirective(4, DirectiveID.getLoc()); return false; @@ -6315,8 +6714,6 @@ bool MipsAsmParser::ParseDirective(AsmToken DirectiveID) { if (Parser.getTok().isNot(AsmToken::EndOfStatement)) { Error(Parser.getTok().getLoc(), "unexpected token, expected end of statement"); - // Clear line - Parser.eatToEndOfStatement(); } return false; } @@ -6367,10 +6764,10 @@ bool MipsAsmParser::parseInternalDirectiveReallowModule() { } extern "C" void LLVMInitializeMipsAsmParser() { - RegisterMCAsmParser<MipsAsmParser> X(TheMipsTarget); - RegisterMCAsmParser<MipsAsmParser> Y(TheMipselTarget); - RegisterMCAsmParser<MipsAsmParser> A(TheMips64Target); - RegisterMCAsmParser<MipsAsmParser> B(TheMips64elTarget); + RegisterMCAsmParser<MipsAsmParser> X(getTheMipsTarget()); + RegisterMCAsmParser<MipsAsmParser> Y(getTheMipselTarget()); + RegisterMCAsmParser<MipsAsmParser> A(getTheMips64Target()); + RegisterMCAsmParser<MipsAsmParser> B(getTheMips64elTarget()); } #define GET_REGISTER_MATCHER diff --git a/contrib/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/contrib/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp index aebb4ef..f80efb1 100644 --- a/contrib/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ b/contrib/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -439,6 +439,22 @@ static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder); template <typename InsnType> +static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, + const void *Decoder); + +template <typename InsnType> +static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, + const void *Decoder); + +template <typename InsnType> +static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, + const void *Decoder); + +template <typename InsnType> +static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, + const void *Decoder); + +template <typename InsnType> static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder); @@ -460,6 +476,16 @@ DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, template <typename InsnType> static DecodeStatus +DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, + const void *Decoder); + +template <typename InsnType> +static DecodeStatus +DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, + const void *Decoder); + +template <typename InsnType> +static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder); @@ -501,8 +527,10 @@ static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned Insn, const void *Decoder); namespace llvm { -extern Target TheMipselTarget, TheMipsTarget, TheMips64Target, - TheMips64elTarget; +Target &getTheMipselTarget(); +Target &getTheMipsTarget(); +Target &getTheMips64Target(); +Target &getTheMips64elTarget(); } static MCDisassembler *createMipsDisassembler( @@ -521,13 +549,13 @@ static MCDisassembler *createMipselDisassembler( extern "C" void LLVMInitializeMipsDisassembler() { // Register the disassembler. - TargetRegistry::RegisterMCDisassembler(TheMipsTarget, + TargetRegistry::RegisterMCDisassembler(getTheMipsTarget(), createMipsDisassembler); - TargetRegistry::RegisterMCDisassembler(TheMipselTarget, + TargetRegistry::RegisterMCDisassembler(getTheMipselTarget(), createMipselDisassembler); - TargetRegistry::RegisterMCDisassembler(TheMips64Target, + TargetRegistry::RegisterMCDisassembler(getTheMips64Target(), createMipsDisassembler); - TargetRegistry::RegisterMCDisassembler(TheMips64elTarget, + TargetRegistry::RegisterMCDisassembler(getTheMips64elTarget(), createMipselDisassembler); } @@ -586,6 +614,34 @@ static DecodeStatus DecodeINSVE_DF(MCInst &MI, InsnType insn, uint64_t Address, } template <typename InsnType> +static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address, + const void *Decoder) { + InsnType Rs = fieldFromInstruction(insn, 16, 5); + InsnType Imm = fieldFromInstruction(insn, 0, 16); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, + Rs))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, + Rs))); + MI.addOperand(MCOperand::createImm(Imm)); + + return MCDisassembler::Success; +} + +template <typename InsnType> +static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address, + const void *Decoder) { + InsnType Rs = fieldFromInstruction(insn, 21, 5); + InsnType Imm = fieldFromInstruction(insn, 0, 16); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, + Rs))); + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, + Rs))); + MI.addOperand(MCOperand::createImm(Imm)); + + return MCDisassembler::Success; +} + +template <typename InsnType> static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) { @@ -630,7 +686,7 @@ static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, const void *Decoder) { InsnType Rt = fieldFromInstruction(insn, 21, 5); InsnType Rs = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; + int64_t Imm = 0; if (Rs >= Rt) { MI.setOpcode(Mips::BOVC_MMR6); @@ -638,16 +694,19 @@ static DecodeStatus DecodePOP35GroupBranchMMR6(MCInst &MI, InsnType insn, Rt))); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; } else if (Rs != 0 && Rs < Rt) { MI.setOpcode(Mips::BEQC_MMR6); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; } else { MI.setOpcode(Mips::BEQZALC_MMR6); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; } MI.addOperand(MCOperand::createImm(Imm)); @@ -700,7 +759,7 @@ static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, const void *Decoder) { InsnType Rt = fieldFromInstruction(insn, 21, 5); InsnType Rs = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; + int64_t Imm = 0; if (Rs >= Rt) { MI.setOpcode(Mips::BNVC_MMR6); @@ -708,16 +767,19 @@ static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, Rt))); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; } else if (Rs != 0 && Rs < Rt) { MI.setOpcode(Mips::BNEC_MMR6); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; } else { MI.setOpcode(Mips::BNEZALC_MMR6); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; } MI.addOperand(MCOperand::createImm(Imm)); @@ -726,6 +788,84 @@ static DecodeStatus DecodePOP37GroupBranchMMR6(MCInst &MI, InsnType insn, } template <typename InsnType> +static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, + uint64_t Address, + const void *Decoder) { + // We have: + // 0b110101 ttttt sssss iiiiiiiiiiiiiiii + // Invalid if rt == 0 + // BGTZC_MMR6 if rs == 0 && rt != 0 + // BLTZC_MMR6 if rs == rt && rt != 0 + // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 + + InsnType Rt = fieldFromInstruction(insn, 21, 5); + InsnType Rs = fieldFromInstruction(insn, 16, 5); + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + bool HasRs = false; + + if (Rt == 0) + return MCDisassembler::Fail; + else if (Rs == 0) + MI.setOpcode(Mips::BGTZC_MMR6); + else if (Rs == Rt) + MI.setOpcode(Mips::BLTZC_MMR6); + else { + MI.setOpcode(Mips::BLTC_MMR6); + HasRs = true; + } + + if (HasRs) + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, + Rs))); + + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, + Rt))); + + MI.addOperand(MCOperand::createImm(Imm)); + + return MCDisassembler::Success; +} + +template <typename InsnType> +static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, + uint64_t Address, + const void *Decoder) { + // We have: + // 0b111101 ttttt sssss iiiiiiiiiiiiiiii + // Invalid if rt == 0 + // BLEZC_MMR6 if rs == 0 && rt != 0 + // BGEZC_MMR6 if rs == rt && rt != 0 + // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 + + InsnType Rt = fieldFromInstruction(insn, 21, 5); + InsnType Rs = fieldFromInstruction(insn, 16, 5); + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + bool HasRs = false; + + if (Rt == 0) + return MCDisassembler::Fail; + else if (Rs == 0) + MI.setOpcode(Mips::BLEZC_MMR6); + else if (Rs == Rt) + MI.setOpcode(Mips::BGEZC_MMR6); + else { + HasRs = true; + MI.setOpcode(Mips::BGEC_MMR6); + } + + if (HasRs) + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, + Rs))); + + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, + Rt))); + + MI.addOperand(MCOperand::createImm(Imm)); + + return MCDisassembler::Success; +} + +template <typename InsnType> static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder) { @@ -904,7 +1044,7 @@ static DecodeStatus DecodeBlezGroupBranch(MCInst &MI, InsnType insn, } /// Read two bytes from the ArrayRef and return 16 bit halfword sorted -/// according to the given endianess. +/// according to the given endianness. static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian) { @@ -924,7 +1064,7 @@ static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address, } /// Read four bytes from the ArrayRef and return 32 bit word sorted -/// according to the given endianess +/// according to the given endianness. static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address, uint64_t &Size, uint32_t &Insn, bool IsBigEndian, bool IsMicroMips) { @@ -1662,7 +1802,7 @@ static DecodeStatus DecodeMemMMImm12(MCInst &Inst, break; case Mips::SC_MM: Inst.addOperand(MCOperand::createReg(Reg)); - // fallthrough + LLVM_FALLTHROUGH; default: Inst.addOperand(MCOperand::createReg(Reg)); if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM || @@ -2008,7 +2148,7 @@ static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) { - int32_t BranchOffset = SignExtend32<21>(Offset) << 1; + int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; Inst.addOperand(MCOperand::createImm(BranchOffset)); return MCDisassembler::Success; @@ -2046,7 +2186,7 @@ static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset, uint64_t Address, const void *Decoder) { - int32_t BranchOffset = SignExtend32<16>(Offset) * 2; + int32_t BranchOffset = SignExtend32<16>(Offset) * 2 + 4; Inst.addOperand(MCOperand::createImm(BranchOffset)); return MCDisassembler::Success; } @@ -2285,7 +2425,7 @@ static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, InsnType Rt = fieldFromInstruction(insn, 21, 5); InsnType Rs = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; + InsnType Imm = 0; bool HasRs = false; bool HasRt = false; @@ -2294,15 +2434,18 @@ static DecodeStatus DecodeBgtzGroupBranchMMR6(MCInst &MI, InsnType insn, else if (Rs == 0) { MI.setOpcode(Mips::BGTZALC_MMR6); HasRt = true; + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; } else if (Rs == Rt) { MI.setOpcode(Mips::BLTZALC_MMR6); HasRs = true; + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; } else { MI.setOpcode(Mips::BLTUC_MMR6); HasRs = true; HasRt = true; + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; } if (HasRs) @@ -2324,25 +2467,30 @@ static DecodeStatus DecodeBlezGroupBranchMMR6(MCInst &MI, InsnType insn, const void *Decoder) { // We have: // 0b000110 ttttt sssss iiiiiiiiiiiiiiii - // Invalid if rs == 0 + // Invalid if rt == 0 // BLEZALC_MMR6 if rs == 0 && rt != 0 // BGEZALC_MMR6 if rs == rt && rt != 0 // BGEUC_MMR6 if rs != rt && rs != 0 && rt != 0 InsnType Rt = fieldFromInstruction(insn, 21, 5); InsnType Rs = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; + InsnType Imm = 0; bool HasRs = false; if (Rt == 0) return MCDisassembler::Fail; - else if (Rs == 0) + else if (Rs == 0) { MI.setOpcode(Mips::BLEZALC_MMR6); - else if (Rs == Rt) + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; + } + else if (Rs == Rt) { MI.setOpcode(Mips::BGEZALC_MMR6); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2 + 4; + } else { HasRs = true; MI.setOpcode(Mips::BGEUC_MMR6); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; } if (HasRs) diff --git a/contrib/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp b/contrib/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp index 0fd593f..49c42fd 100644 --- a/contrib/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp +++ b/contrib/llvm/lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp @@ -236,6 +236,7 @@ bool MipsInstPrinter::printAlias(const MCInst &MI, raw_ostream &OS) { // beq $r0, $zero, $L2 => beqz $r0, $L2 return isReg<Mips::ZERO_64>(MI, 1) && printAlias("beqz", MI, 0, 2, OS); case Mips::BNE: + case Mips::BNE_MM: // bne $r0, $zero, $L2 => bnez $r0, $L2 return isReg<Mips::ZERO>(MI, 1) && printAlias("bnez", MI, 0, 2, OS); case Mips::BNE64: diff --git a/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp b/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp index 3cf632e..498ea6f 100644 --- a/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp +++ b/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp @@ -51,12 +51,11 @@ MipsABIInfo MipsABIInfo::computeTargetABI(const Triple &TT, StringRef CPU, const MCTargetOptions &Options) { if (Options.getABIName().startswith("o32")) return MipsABIInfo::O32(); - else if (Options.getABIName().startswith("n32")) + if (Options.getABIName().startswith("n32")) return MipsABIInfo::N32(); - else if (Options.getABIName().startswith("n64")) + if (Options.getABIName().startswith("n64")) return MipsABIInfo::N64(); - else if (!Options.getABIName().empty()) - llvm_unreachable("Unknown ABI option for MIPS"); + assert(Options.getABIName().empty() && "Unknown ABI option for MIPS"); if (TT.getArch() == Triple::mips64 || TT.getArch() == Triple::mips64el) return MipsABIInfo::N64(); diff --git a/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp b/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp index 8292d6b..38b11f7 100644 --- a/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp +++ b/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp @@ -59,9 +59,15 @@ static unsigned adjustFixupValue(const MCFixup &Fixup, uint64_t Value, case Mips::fixup_MIPS_PCLO16: Value &= 0xffff; break; + case FK_DTPRel_4: + case FK_DTPRel_8: + case FK_TPRel_4: + case FK_TPRel_8: case FK_GPRel_4: case FK_Data_4: case FK_Data_8: + case Mips::fixup_Mips_SUB: + case Mips::fixup_MICROMIPS_SUB: break; case Mips::fixup_Mips_PC16: // The displacement is then divided by 4 to give us an 18 bit @@ -361,7 +367,9 @@ getFixupKindInfo(MCFixupKind Kind) const { { "fixup_MICROMIPS_TLS_DTPREL_HI16", 0, 16, 0 }, { "fixup_MICROMIPS_TLS_DTPREL_LO16", 0, 16, 0 }, { "fixup_MICROMIPS_TLS_TPREL_HI16", 0, 16, 0 }, - { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 } + { "fixup_MICROMIPS_TLS_TPREL_LO16", 0, 16, 0 }, + { "fixup_Mips_SUB", 0, 64, 0 }, + { "fixup_MICROMIPS_SUB", 0, 64, 0 } }; const static MCFixupKindInfo BigEndianInfos[Mips::NumTargetFixupKinds] = { @@ -430,7 +438,9 @@ getFixupKindInfo(MCFixupKind Kind) const { { "fixup_MICROMIPS_TLS_DTPREL_HI16", 16, 16, 0 }, { "fixup_MICROMIPS_TLS_DTPREL_LO16", 16, 16, 0 }, { "fixup_MICROMIPS_TLS_TPREL_HI16", 16, 16, 0 }, - { "fixup_MICROMIPS_TLS_TPREL_LO16", 16, 16, 0 } + { "fixup_MICROMIPS_TLS_TPREL_LO16", 16, 16, 0 }, + { "fixup_Mips_SUB", 0, 64, 0 }, + { "fixup_MICROMIPS_SUB", 0, 64, 0 } }; if (Kind < FirstTargetFixupKind) @@ -482,27 +492,31 @@ void MipsAsmBackend::processFixupValue(const MCAssembler &Asm, // MCAsmBackend MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU) { + const Triple &TT, StringRef CPU, + const MCTargetOptions &Options) { return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ false); } MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU) { + const Triple &TT, StringRef CPU, + const MCTargetOptions &Options) { return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false, /*Is64Bit*/ false); } MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU) { + const Triple &TT, StringRef CPU, + const MCTargetOptions &Options) { return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true); } MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU) { + const Triple &TT, StringRef CPU, + const MCTargetOptions &Options) { return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false, /*Is64Bit*/ true); } diff --git a/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h b/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h index 2bcff88..a90db23 100644 --- a/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h +++ b/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h @@ -120,7 +120,12 @@ namespace MipsII { /// IsCTI - Instruction is a Control Transfer Instruction. IsCTI = 1 << 4, /// HasForbiddenSlot - Instruction has a forbidden slot. - HasForbiddenSlot = 1 << 5 + HasForbiddenSlot = 1 << 5, + /// IsPCRelativeLoad - A Load instruction with implicit source register + /// ($pc) with explicit offset and destination register + IsPCRelativeLoad = 1 << 6, + /// HasFCCRegOperand - Instruction uses an $fcc<x> register. + HasFCCRegOperand = 1 << 7 }; } diff --git a/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp b/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp index 20c5f36..b2efd72 100644 --- a/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp +++ b/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsELFObjectWriter.cpp @@ -270,6 +270,14 @@ unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx, case Mips::fixup_Mips_64: case FK_Data_8: return ELF::R_MIPS_64; + case FK_DTPRel_4: + return ELF::R_MIPS_TLS_DTPREL32; + case FK_DTPRel_8: + return ELF::R_MIPS_TLS_DTPREL64; + case FK_TPRel_4: + return ELF::R_MIPS_TLS_TPREL32; + case FK_TPRel_8: + return ELF::R_MIPS_TLS_TPREL64; case FK_GPRel_4: if (isN64()) { unsigned Type = (unsigned)ELF::R_MIPS_NONE; @@ -329,6 +337,8 @@ unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx, return ELF::R_MIPS_HIGHER; case Mips::fixup_Mips_HIGHEST: return ELF::R_MIPS_HIGHEST; + case Mips::fixup_Mips_SUB: + return ELF::R_MIPS_SUB; case Mips::fixup_Mips_GOT_HI16: return ELF::R_MIPS_GOT_HI16; case Mips::fixup_Mips_GOT_LO16: @@ -365,6 +375,8 @@ unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx, return ELF::R_MICROMIPS_TLS_TPREL_HI16; case Mips::fixup_MICROMIPS_TLS_TPREL_LO16: return ELF::R_MICROMIPS_TLS_TPREL_LO16; + case Mips::fixup_MICROMIPS_SUB: + return ELF::R_MICROMIPS_SUB; } llvm_unreachable("invalid fixup kind!"); @@ -407,6 +419,13 @@ unsigned MipsELFObjectWriter::getRelocType(MCContext &Ctx, /// always match using the expressions from the source. void MipsELFObjectWriter::sortRelocs(const MCAssembler &Asm, std::vector<ELFRelocationEntry> &Relocs) { + + // We do not need to sort the relocation table for RELA relocations which + // N32/N64 uses as the relocation addend contains the value we require, + // rather than it being split across a pair of relocations. + if (hasRelocationAddend()) + return; + if (Relocs.size() < 2) return; @@ -527,7 +546,7 @@ bool MipsELFObjectWriter::needsRelocateWithSymbol(const MCSymbol &Sym, case ELF::R_MIPS_GPREL32: if (cast<MCSymbolELF>(Sym).getOther() & ELF::STO_MIPS_MICROMIPS) return true; - // fallthrough + LLVM_FALLTHROUGH; case ELF::R_MIPS_26: case ELF::R_MIPS_64: case ELF::R_MIPS_GPREL16: diff --git a/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h b/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h index b4d8e94..1492962 100644 --- a/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h +++ b/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsFixupKinds.h @@ -209,6 +209,10 @@ namespace Mips { // resulting in - R_MICROMIPS_TLS_TPREL_LO16 fixup_MICROMIPS_TLS_TPREL_LO16, + // resulting in - R_MIPS_SUB/R_MICROMIPS_SUB + fixup_Mips_SUB, + fixup_MICROMIPS_SUB, + // Marker LastTargetFixupKind, NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind diff --git a/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp b/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp index 1ce8f07..a44a35f 100644 --- a/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp +++ b/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsMCAsmInfo.cpp @@ -45,13 +45,22 @@ MipsMCAsmInfo::MipsMCAsmInfo(const Triple &TheTriple) { ZeroDirective = "\t.space\t"; GPRel32Directive = "\t.gpword\t"; GPRel64Directive = "\t.gpdword\t"; + DTPRel32Directive = "\t.dtprelword\t"; + DTPRel64Directive = "\t.dtpreldword\t"; + TPRel32Directive = "\t.tprelword\t"; + TPRel64Directive = "\t.tpreldword\t"; UseAssignmentForEHBegin = true; SupportsDebugInformation = true; ExceptionsType = ExceptionHandling::DwarfCFI; DwarfRegNumForCFI = true; + HasMipsExpressions = true; // Enable IAS by default for O32. if (TheTriple.getArch() == Triple::mips || TheTriple.getArch() == Triple::mipsel) UseIntegratedAssembler = true; + + // Enable IAS by default for Debian mips64/mips64el. + if (TheTriple.getEnvironment() == Triple::GNUABI64) + UseIntegratedAssembler = true; } diff --git a/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp b/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp index 401c7d4..0614316 100644 --- a/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ b/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -129,7 +129,8 @@ void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const { unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0); unsigned Reg1 = Ctx.getRegisterInfo()->getEncodingValue(RegOp1); - if (Inst.getOpcode() == Mips::BNEC || Inst.getOpcode() == Mips::BEQC) { + if (Inst.getOpcode() == Mips::BNEC || Inst.getOpcode() == Mips::BEQC || + Inst.getOpcode() == Mips::BNEC64 || Inst.getOpcode() == Mips::BEQC64) { assert(Reg0 != Reg1 && "Instruction has bad operands ($rs == $rt)!"); if (Reg0 < Reg1) return; @@ -141,7 +142,7 @@ void MipsMCCodeEmitter::LowerCompactBranch(MCInst& Inst) const { if (Reg1 >= Reg0) return; } else - llvm_unreachable("Cannot rewrite unknown branch!"); + llvm_unreachable("Cannot rewrite unknown branch!"); Inst.getOperand(0).setReg(RegOp1); Inst.getOperand(1).setReg(RegOp0); @@ -210,6 +211,8 @@ encodeInstruction(const MCInst &MI, raw_ostream &OS, // Compact branches, enforce encoding restrictions. case Mips::BEQC: case Mips::BNEC: + case Mips::BEQC64: + case Mips::BNEC64: case Mips::BOVC: case Mips::BOVC_MMR6: case Mips::BNVC: @@ -332,6 +335,30 @@ getBranchTargetOpValueMMR6(const MCInst &MI, unsigned OpNo, return 0; } +/// getBranchTargetOpValueLsl2MMR6 - Return binary encoding of the branch +/// target operand. If the machine operand requires relocation, +/// record the relocation and return zero. +unsigned MipsMCCodeEmitter:: +getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const { + + const MCOperand &MO = MI.getOperand(OpNo); + + // If the destination is an immediate, divide by 4. + if (MO.isImm()) + return MO.getImm() >> 2; + + assert(MO.isExpr() && + "getBranchTargetOpValueLsl2MMR6 expects only expressions or immediates"); + + const MCExpr *FixupExpression = MCBinaryExpr::createAdd( + MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx); + Fixups.push_back(MCFixup::create(0, FixupExpression, + MCFixupKind(Mips::fixup_Mips_PC16))); + return 0; +} + /// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch /// target operand. If the machine operand requires relocation, /// record the relocation and return zero. @@ -432,8 +459,8 @@ getBranchTarget21OpValueMM(const MCInst &MI, unsigned OpNo, const MCOperand &MO = MI.getOperand(OpNo); - // If the destination is an immediate, divide by 2. - if (MO.isImm()) return MO.getImm() >> 1; + // If the destination is an immediate, divide by 4. + if (MO.isImm()) return MO.getImm() >> 2; assert(MO.isExpr() && "getBranchTarget21OpValueMM expects only expressions or immediates"); @@ -634,7 +661,6 @@ getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups, Mips::Fixups FixupKind = Mips::Fixups(0); switch (MipsExpr->getKind()) { - case MipsMCExpr::MEK_NEG: case MipsMCExpr::MEK_None: case MipsMCExpr::MEK_Special: llvm_unreachable("Unhandled fixup kind!"); @@ -732,6 +758,10 @@ getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups, FixupKind = isMicroMips(STI) ? Mips::fixup_MICROMIPS_TLS_TPREL_LO16 : Mips::fixup_Mips_TPREL_LO; break; + case MipsMCExpr::MEK_NEG: + FixupKind = + isMicroMips(STI) ? Mips::fixup_MICROMIPS_SUB : Mips::fixup_Mips_SUB; + break; } Fixups.push_back(MCFixup::create(0, MipsExpr, MCFixupKind(FixupKind))); return 0; diff --git a/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h b/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h index 0f4dfe1..2d041dc 100644 --- a/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h +++ b/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h @@ -116,6 +116,13 @@ public: SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const; + // getBranchTargetOpValueLsl2MMR6 - Return binary encoding of the branch + // target operand. If the machine operand requires relocation, + // record the relocation and return zero. + unsigned getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo, + SmallVectorImpl<MCFixup> &Fixups, + const MCSubtargetInfo &STI) const; + // getBranchTarget7OpValue - Return binary encoding of the microMIPS branch // target operand. If the machine operand requires relocation, // record the relocation and return zero. diff --git a/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp b/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp index a055739..56fe185 100644 --- a/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp +++ b/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp @@ -149,8 +149,8 @@ static MCInstrAnalysis *createMipsMCInstrAnalysis(const MCInstrInfo *Info) { } extern "C" void LLVMInitializeMipsTargetMC() { - for (Target *T : {&TheMipsTarget, &TheMipselTarget, &TheMips64Target, - &TheMips64elTarget}) { + for (Target *T : {&getTheMipsTarget(), &getTheMipselTarget(), + &getTheMips64Target(), &getTheMips64elTarget()}) { // Register the MC asm info. RegisterMCAsmInfoFn X(*T, createMipsMCAsmInfo); @@ -183,20 +183,19 @@ extern "C" void LLVMInitializeMipsTargetMC() { } // Register the MC Code Emitter - for (Target *T : {&TheMipsTarget, &TheMips64Target}) + for (Target *T : {&getTheMipsTarget(), &getTheMips64Target()}) TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEB); - for (Target *T : {&TheMipselTarget, &TheMips64elTarget}) + for (Target *T : {&getTheMipselTarget(), &getTheMips64elTarget()}) TargetRegistry::RegisterMCCodeEmitter(*T, createMipsMCCodeEmitterEL); // Register the asm backend. - TargetRegistry::RegisterMCAsmBackend(TheMipsTarget, + TargetRegistry::RegisterMCAsmBackend(getTheMipsTarget(), createMipsAsmBackendEB32); - TargetRegistry::RegisterMCAsmBackend(TheMipselTarget, + TargetRegistry::RegisterMCAsmBackend(getTheMipselTarget(), createMipsAsmBackendEL32); - TargetRegistry::RegisterMCAsmBackend(TheMips64Target, + TargetRegistry::RegisterMCAsmBackend(getTheMips64Target(), createMipsAsmBackendEB64); - TargetRegistry::RegisterMCAsmBackend(TheMips64elTarget, + TargetRegistry::RegisterMCAsmBackend(getTheMips64elTarget(), createMipsAsmBackendEL64); - } diff --git a/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h b/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h index 4069d7d..b28681f 100644 --- a/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h +++ b/contrib/llvm/lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h @@ -24,16 +24,17 @@ class MCInstrInfo; class MCObjectWriter; class MCRegisterInfo; class MCSubtargetInfo; +class MCTargetOptions; class StringRef; class Target; class Triple; class raw_ostream; class raw_pwrite_stream; -extern Target TheMipsTarget; -extern Target TheMipselTarget; -extern Target TheMips64Target; -extern Target TheMips64elTarget; +Target &getTheMipsTarget(); +Target &getTheMipselTarget(); +Target &getTheMips64Target(); +Target &getTheMips64elTarget(); MCCodeEmitter *createMipsMCCodeEmitterEB(const MCInstrInfo &MCII, const MCRegisterInfo &MRI, @@ -44,16 +45,20 @@ MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII, MCAsmBackend *createMipsAsmBackendEB32(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); + const Triple &TT, StringRef CPU, + const MCTargetOptions &Options); MCAsmBackend *createMipsAsmBackendEL32(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); + const Triple &TT, StringRef CPU, + const MCTargetOptions &Options); MCAsmBackend *createMipsAsmBackendEB64(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); + const Triple &TT, StringRef CPU, + const MCTargetOptions &Options); MCAsmBackend *createMipsAsmBackendEL64(const Target &T, const MCRegisterInfo &MRI, - const Triple &TT, StringRef CPU); + const Triple &TT, StringRef CPU, + const MCTargetOptions &Options); MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, bool IsLittleEndian, bool Is64Bit); diff --git a/contrib/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td b/contrib/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td index 2b636cf..fd04f80 100644 --- a/contrib/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ b/contrib/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -32,6 +32,15 @@ def brtargetr6 : Operand<OtherVT> { let ParserMatchClass = MipsJumpTargetAsmOperand; } +def brtarget_lsl2_mm : Operand<OtherVT> { + let EncoderMethod = "getBranchTargetOpValueLsl2MMR6"; + let OperandType = "OPERAND_PCREL"; + // Instructions that use this operand have their decoder method + // set with DecodeDisambiguates + let DecoderMethod = ""; + let ParserMatchClass = MipsJumpTargetAsmOperand; +} + //===----------------------------------------------------------------------===// // // Instruction Encodings @@ -56,16 +65,28 @@ class BITSWAP_MMR6_ENC : POOL32A_BITSWAP_FM_MMR6<0b101100>; class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">; class BEQZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"beqzc", 0b100000>; class BNEZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"bnezc", 0b101000>; -class BGEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgec", 0b111001>; +class BGEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgec", 0b111101>, + DecodeDisambiguates<"POP75GroupBranchMMR6">; class BGEUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgeuc", 0b110000>, DecodeDisambiguates<"BlezGroupBranchMMR6">; -class BLTC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltc", 0b110001>; +class BLTC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltc", 0b110101>, + DecodeDisambiguates<"POP65GroupBranchMMR6">; class BLTUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltuc", 0b111000>, DecodeDisambiguates<"BgtzGroupBranchMMR6">; class BEQC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"beqc", 0b011101>; class BNEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bnec", 0b011111>; -class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"beqzalc", 0b011101>; -class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bnezalc", 0b011111>; +class BLTZC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bltzc", 0b110101>, + DecodeDisambiguates<"POP65GroupBranchMMR6">; +class BLEZC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"blezc", 0b111101>, + DecodeDisambiguates<"POP75GroupBranchMMR6">; +class BGEZC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bgezc", 0b111101>, + DecodeDisambiguates<"POP75GroupBranchMMR6">; +class BGTZC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bgtzc", 0b110101>, + DecodeDisambiguates<"POP65GroupBranchMMR6">; +class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"beqzalc", 0b011101>, + DecodeDisambiguates<"POP35GroupBranchMMR6">; +class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bnezalc", 0b011111>, + DecodeDisambiguates<"POP37GroupBranchMMR6">; class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bgtzalc", 0b111000>, MMDecodeDisambiguatedBy<"BgtzGroupBranchMMR6">; class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bltzalc", 0b111000>, @@ -165,8 +186,6 @@ class TRUNC_W_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.s", 0, 0b10101100>; class TRUNC_W_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"trunc.w.d", 1, 0b10101100>; class SQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.s", 0, 0b00101000>; class SQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"sqrt.d", 1, 0b00101000>; -class RSQRT_S_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.s", 0, 0b00001000>; -class RSQRT_D_MMR6_ENC : POOL32F_MATH_FM_MMR6<"rsqrt.d", 1, 0b00001000>; class SB_MMR6_ENC : SB32_SH32_STORE_FM_MMR6<0b000110>; class SBE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b100>; class SCE_MMR6_ENC : POOL32C_STORE_EVA_FM_MMR6<0b110>; @@ -177,8 +196,6 @@ class LWE_MMR6_ENC : LOAD_WORD_EVA_FM_MMR6<0b111>; class LW_MMR6_ENC : LOAD_WORD_FM_MMR6; class LUI_MMR6_ENC : LOAD_UPPER_IMM_FM_MMR6; class JALRC_HB_MMR6_ENC : POOL32A_JALRC_FM_MMR6<"jalrc.hb", 0b0001111100>; -class RECIP_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.s", 0, 0b01001000>; -class RECIP_D_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"recip.d", 1, 0b01001000>; class RINT_S_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.s", 0>; class RINT_D_MMR6_ENC : POOL32F_RINT_FM_MMR6<"rint.d", 1>; class ROUND_L_S_MMR6_ENC : POOL32F_RECIP_ROUND_FM_MMR6<"round.l.s", 0, @@ -230,6 +247,49 @@ class SDC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"sdc2", 0b1010>; class LWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"lwc2", 0b0000>; class SWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"swc2", 0b1000>; +/// Floating Point Instructions +class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>; +class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>; +class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>; +class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>; +class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>; +class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>; +class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>; +class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>; +class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>; +class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>; +class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>; +class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>; +class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>; +class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>; +class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>; +class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>; +class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>; +class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>; +class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>; +class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>; +class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>; +class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>; +class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>; +class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>; + +class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>; +class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>; +class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>; +class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>; +class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>; +class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>; +class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>; +class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>; +class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>; +class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>; + +//===----------------------------------------------------------------------===// +// +// Instruction Descriptions +// +//===----------------------------------------------------------------------===// + class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, RegisterOperand GPROpnd> : BRANCH_DESC_BASE { @@ -237,6 +297,7 @@ class CMP_CBR_RT_Z_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, dag OutOperandList = (outs); string AsmString = !strconcat(instr_asm, "\t$rt, $offset"); list<Register> Defs = [AT]; + InstrItinClass Itinerary = II_BCCZC; } class BEQZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"beqzalc", brtarget_mm, @@ -269,91 +330,59 @@ class BNEZALC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bnezalc", brtarget_mm, list<Register> Defs = [RA]; } +class BLTZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzc", brtarget_lsl2_mm, + GPR32Opnd>; +class BLEZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezc", brtarget_lsl2_mm, + GPR32Opnd>; +class BGEZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezc", brtarget_lsl2_mm, + GPR32Opnd>; +class BGTZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzc", brtarget_lsl2_mm, + GPR32Opnd>; + class CMP_CBR_2R_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, RegisterOperand GPROpnd> : BRANCH_DESC_BASE { dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset); dag OutOperandList = (outs); string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $offset"); list<Register> Defs = [AT]; + InstrItinClass Itinerary = II_BCCC; } -class BGEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgec", brtarget_mm, +class BGEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgec", brtarget_lsl2_mm, GPR32Opnd>; -class BGEUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgeuc", brtarget_mm, +class BGEUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgeuc", brtarget_lsl2_mm, GPR32Opnd>; -class BLTC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltc", brtarget_mm, +class BLTC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltc", brtarget_lsl2_mm, GPR32Opnd>; -class BLTUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltuc", brtarget_mm, +class BLTUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltuc", brtarget_lsl2_mm, GPR32Opnd>; -class BEQC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"beqc", brtarget_mm, +class BEQC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"beqc", brtarget_lsl2_mm, GPR32Opnd>; -class BNEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bnec", brtarget_mm, +class BNEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bnec", brtarget_lsl2_mm, GPR32Opnd>; -/// Floating Point Instructions -class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>; -class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>; -class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>; -class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>; -class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>; -class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>; -class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>; -class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>; -class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>; -class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>; -class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>; -class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>; -class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>; -class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>; -class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>; -class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>; -class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>; -class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>; -class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>; -class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>; -class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>; -class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>; -class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>; -class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>; - -class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>; -class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>; -class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>; -class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>; -class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>; -class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>; -class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>; -class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>; -class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>; -class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>; - -//===----------------------------------------------------------------------===// -// -// Instruction Descriptions -// -//===----------------------------------------------------------------------===// - -class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>; +class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd, 1, II_ADD>; class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>; -class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>; +class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU>; class MUL_MMR6_DESC : ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>; class MUH_MMR6_DESC : ArithLogicR<"muh", GPR32Opnd, 1, II_MUH, mulhs>; class MULU_MMR6_DESC : ArithLogicR<"mulu", GPR32Opnd, 1, II_MULU>; class MUHU_MMR6_DESC : ArithLogicR<"muhu", GPR32Opnd, 1, II_MUHU, mulhu>; -class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd> +class BC_MMR6_DESC_BASE<string instr_asm, DAGOperand opnd, InstrItinClass Itin> : BRANCH_DESC_BASE, MMR6Arch<instr_asm> { dag InOperandList = (ins opnd:$offset); dag OutOperandList = (outs); string AsmString = !strconcat(instr_asm, "\t$offset"); bit isBarrier = 1; + InstrItinClass Itinerary = Itin; } -class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26_mm> { +class BALC_MMR6_DESC : BC_MMR6_DESC_BASE<"balc", brtarget26_mm, II_BALC> { bit isCall = 1; list<Register> Defs = [RA]; } -class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm>; +class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"bc", brtarget26_mm, II_BC>; class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset), !strconcat("bc16", "\t$offset"), [], @@ -377,8 +406,8 @@ class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm> class BEQZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"beqzc16">; class BNEZC16_MMR6_DESC : BEQZC_BNEZC_MM16R6_DESC_BASE<"bnezc16">; -class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd>; -class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd>; +class SUB_MMR6_DESC : ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>; +class SUBU_MMR6_DESC : ArithLogicR<"subu", GPR32Opnd, 0,II_SUBU>; class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> : MMR6Arch<instr_asm> { @@ -386,6 +415,7 @@ class BITSWAP_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> dag InOperandList = (ins GPROpnd:$rt); string AsmString = !strconcat(instr_asm, "\t$rd, $rt"); list<dag> Pattern = []; + InstrItinClass Itinerary = II_BITSWAP; } class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>; @@ -393,63 +423,74 @@ class BITSWAP_MMR6_DESC : BITSWAP_MMR6_DESC_BASE<"bitswap", GPR32Opnd>; class BRK_MMR6_DESC : BRK_FT<"break">; class CACHE_HINT_MMR6_DESC<string instr_asm, Operand MemOpnd, - RegisterOperand GPROpnd> : MMR6Arch<instr_asm> { + RegisterOperand GPROpnd, InstrItinClass Itin> + : MMR6Arch<instr_asm> { dag OutOperandList = (outs); dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint); string AsmString = !strconcat(instr_asm, "\t$hint, $addr"); list<dag> Pattern = []; string DecoderMethod = "DecodeCacheOpMM"; + InstrItinClass Itinerary = Itin; } -class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd>; -class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd>; +class CACHE_MMR6_DESC : CACHE_HINT_MMR6_DESC<"cache", mem_mm_12, GPR32Opnd, + II_CACHE>; +class PREF_MMR6_DESC : CACHE_HINT_MMR6_DESC<"pref", mem_mm_12, GPR32Opnd, + II_PREF>; class PREFE_CACHEE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd, - RegisterOperand GPROpnd> : - CACHE_HINT_MMR6_DESC<instr_asm, MemOpnd, - GPROpnd> { + RegisterOperand GPROpnd, InstrItinClass Itin> + : CACHE_HINT_MMR6_DESC<instr_asm, MemOpnd, GPROpnd, Itin> { string DecoderMethod = "DecodePrefeOpMM"; } -class PREFE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"prefe", mem_mm_9, GPR32Opnd>; -class CACHEE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"cachee", mem_mm_9, GPR32Opnd>; +class PREFE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"prefe", mem_mm_9, + GPR32Opnd, II_PREFE>; +class CACHEE_MMR6_DESC : PREFE_CACHEE_MMR6_DESC_BASE<"cachee", mem_mm_9, + GPR32Opnd, II_CACHEE>; class LB_LBU_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd, - RegisterOperand GPROpnd> : MMR6Arch<instr_asm> { + RegisterOperand GPROpnd, InstrItinClass Itin> + : MMR6Arch<instr_asm> { dag OutOperandList = (outs GPROpnd:$rt); dag InOperandList = (ins MemOpnd:$addr); string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); string DecoderMethod = "DecodeLoadByte15"; bit mayLoad = 1; + InstrItinClass Itinerary = Itin; } -class LB_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lb", mem_mm_16, GPR32Opnd>; -class LBU_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lbu", mem_mm_16, GPR32Opnd>; +class LB_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lb", mem_mm_16, GPR32Opnd, II_LB>; +class LBU_MMR6_DESC : LB_LBU_MMR6_DESC_BASE<"lbu", mem_mm_16, GPR32Opnd, + II_LBU>; class LBE_LBUE_MMR6_DESC_BASE<string instr_asm, Operand MemOpnd, - RegisterOperand GPROpnd> - : LB_LBU_MMR6_DESC_BASE<instr_asm, MemOpnd, GPROpnd> { + RegisterOperand GPROpnd, InstrItinClass Itin> + : LB_LBU_MMR6_DESC_BASE<instr_asm, MemOpnd, GPROpnd, Itin> { let DecoderMethod = "DecodeLoadByte9"; } -class LBE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbe", mem_mm_9, GPR32Opnd>; -class LBUE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbue", mem_mm_9, GPR32Opnd>; +class LBE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbe", mem_mm_9, GPR32Opnd, + II_LBE>; +class LBUE_MMR6_DESC : LBE_LBUE_MMR6_DESC_BASE<"lbue", mem_mm_9, GPR32Opnd, + II_LBUE>; -class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> - : MMR6Arch<instr_asm> { +class CLO_CLZ_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, + InstrItinClass Itin> : MMR6Arch<instr_asm> { dag OutOperandList = (outs GPROpnd:$rt); dag InOperandList = (ins GPROpnd:$rs); string AsmString = !strconcat(instr_asm, "\t$rt, $rs"); + InstrItinClass Itinerary = Itin; } -class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd>; -class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd>; +class CLO_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clo", GPR32Opnd, II_CLO>; +class CLZ_MMR6_DESC : CLO_CLZ_MMR6_DESC_BASE<"clz", GPR32Opnd, II_CLZ>; -class EHB_MMR6_DESC : Barrier<"ehb">; -class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd>; -class DI_MMR6_DESC : DEI_FT<"di", GPR32Opnd>; +class EHB_MMR6_DESC : Barrier<"ehb", II_EHB>; +class EI_MMR6_DESC : DEI_FT<"ei", GPR32Opnd, II_EI>; +class DI_MMR6_DESC : DEI_FT<"di", GPR32Opnd, II_DI>; -class ERET_MMR6_DESC : ER_FT<"eret">; -class DERET_MMR6_DESC : ER_FT<"deret">; -class ERETNC_MMR6_DESC : ER_FT<"eretnc">; +class ERET_MMR6_DESC : ER_FT<"eret", II_ERET>; +class DERET_MMR6_DESC : ER_FT<"deret", II_DERET>; +class ERETNC_MMR6_DESC : ER_FT<"eretnc", II_ERETNC>; class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO> : MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), @@ -462,23 +503,25 @@ class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO> class JALRC16_MMR6_DESC : JALRC16_MMR6_DESC_BASE<"jalr", GPR32Opnd>; class JMP_MMR6_IDX_COMPACT_DESC_BASE<string opstr, DAGOperand opnd, - RegisterOperand GPROpnd> + RegisterOperand GPROpnd, + InstrItinClass Itin> : MMR6Arch<opstr> { dag InOperandList = (ins GPROpnd:$rt, opnd:$offset); string AsmString = !strconcat(opstr, "\t$rt, $offset"); list<dag> Pattern = []; bit isTerminator = 1; bit hasDelaySlot = 0; + InstrItinClass Itinerary = Itin; } class JIALC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jialc", calloffset16, - GPR32Opnd> { + GPR32Opnd, II_JIALC> { bit isCall = 1; list<Register> Defs = [RA]; } class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, - GPR32Opnd> { + GPR32Opnd, II_JIC> { bit isBarrier = 1; list<Register> Defs = [AT]; } @@ -505,65 +548,76 @@ class JRCADDIUSP_MMR6_DESC } class ALIGN_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, - Operand ImmOpnd> : MMR6Arch<instr_asm> { + Operand ImmOpnd, InstrItinClass Itin> + : MMR6Arch<instr_asm> { dag OutOperandList = (outs GPROpnd:$rd); dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp); string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp"); list<dag> Pattern = []; + InstrItinClass Itinerary = Itin; } -class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2>; +class ALIGN_MMR6_DESC : ALIGN_MMR6_DESC_BASE<"align", GPR32Opnd, uimm2, + II_ALIGN>; -class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> - : MMR6Arch<instr_asm> { +class AUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, + InstrItinClass Itin> : MMR6Arch<instr_asm> { dag OutOperandList = (outs GPROpnd:$rt); - dag InOperandList = (ins GPROpnd:$rs, simm16:$imm); + dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm); string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm"); list<dag> Pattern = []; + InstrItinClass Itinerary = Itin; } -class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd>; +class AUI_MMR6_DESC : AUI_MMR6_DESC_BASE<"aui", GPR32Opnd, II_AUI>; class SEB_MMR6_DESC : SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>; class SEH_MMR6_DESC : SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>; -class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> - : MMR6Arch<instr_asm> { +class ALUIPC_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, + InstrItinClass Itin> : MMR6Arch<instr_asm> { dag OutOperandList = (outs GPROpnd:$rt); dag InOperandList = (ins simm16:$imm); string AsmString = !strconcat(instr_asm, "\t$rt, $imm"); list<dag> Pattern = []; + InstrItinClass Itinerary = Itin; } -class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd>; -class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd>; +class ALUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"aluipc", GPR32Opnd, II_ALUIPC>; +class AUIPC_MMR6_DESC : ALUIPC_MMR6_DESC_BASE<"auipc", GPR32Opnd, II_AUIPC>; class LSA_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, - Operand ImmOpnd> : MMR6Arch<instr_asm> { + Operand ImmOpnd, InstrItinClass Itin> + : MMR6Arch<instr_asm> { dag OutOperandList = (outs GPROpnd:$rd); dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$imm2); string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $rd, $imm2"); list<dag> Pattern = []; + InstrItinClass Itinerary = Itin; } -class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1>; +class LSA_MMR6_DESC : LSA_MMR6_DESC_BASE<"lsa", GPR32Opnd, uimm2_plus1, II_LSA>; class PCREL_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, - Operand ImmOpnd> : MMR6Arch<instr_asm> { + Operand ImmOpnd, InstrItinClass Itin> + : MMR6Arch<instr_asm> { dag OutOperandList = (outs GPROpnd:$rt); dag InOperandList = (ins ImmOpnd:$imm); string AsmString = !strconcat(instr_asm, "\t$rt, $imm"); list<dag> Pattern = []; + InstrItinClass Itinerary = Itin; } -class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, simm19_lsl2>; -class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2>; +class ADDIUPC_MMR6_DESC : PCREL_MMR6_DESC_BASE<"addiupc", GPR32Opnd, + simm19_lsl2, II_ADDIUPC>; +class LWPC_MMR6_DESC: PCREL_MMR6_DESC_BASE<"lwpc", GPR32Opnd, simm19_lsl2, + II_LWPC>; class LWP_MMR6_DESC : MMR6Arch<"lwp"> { dag OutOperandList = (outs regpair:$rd); dag InOperandList = (ins mem_simm12:$addr); string AsmString = !strconcat("lwp", "\t$rd, $addr"); list<dag> Pattern = []; - InstrItinClass Itin = NoItinerary; + InstrItinClass Itinerary = II_LWP; ComplexPattern Addr = addr; Format f = FrmI; string BaseOpcode = "lwp"; @@ -576,7 +630,7 @@ class SWP_MMR6_DESC : MMR6Arch<"swp"> { dag InOperandList = (ins regpair:$rd, mem_simm12:$addr); string AsmString = !strconcat("swp", "\t$rd, $addr"); list<dag> Pattern = []; - InstrItinClass Itin = NoItinerary; + InstrItinClass Itinerary = II_SWP; ComplexPattern Addr = addr; Format f = FrmI; string BaseOpcode = "swp"; @@ -584,17 +638,20 @@ class SWP_MMR6_DESC : MMR6Arch<"swp"> { bit mayStore = 1; } -class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> - : MMR6Arch<instr_asm> { +class SELEQNE_Z_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, + InstrItinClass Itin> : MMR6Arch<instr_asm> { dag OutOperandList = (outs GPROpnd:$rd); dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); list<dag> Pattern = []; + InstrItinClass Itinerary = Itin; } -class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd>; -class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd>; -class PAUSE_MMR6_DESC : Barrier<"pause">; +class SELEQZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"seleqz", GPR32Opnd, + II_SELCCZ>; +class SELNEZ_MMR6_DESC : SELEQNE_Z_MMR6_DESC_BASE<"selnez", GPR32Opnd, + II_SELCCZ>; +class PAUSE_MMR6_DESC : Barrier<"pause", II_PAUSE>; class RDHWR_MMR6_DESC : MMR6Arch<"rdhwr">, MipsR6Inst { dag OutOperandList = (outs GPR32Opnd:$rt); dag InOperandList = (ins HWRegsOpnd:$rs, uimm3:$sel); @@ -605,10 +662,14 @@ class RDHWR_MMR6_DESC : MMR6Arch<"rdhwr">, MipsR6Inst { } class WAIT_MMR6_DESC : WaitMM<"wait">; -class SSNOP_MMR6_DESC : Barrier<"ssnop">; +// FIXME: ssnop should not be defined for R6. Per MD000582 microMIPS32 6.03: +// Assemblers targeting specifically Release 6 should reject the SSNOP +// instruction with an error. +class SSNOP_MMR6_DESC : Barrier<"ssnop", II_SSNOP>; class SLL_MMR6_DESC : shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>; class DIVMOD_MMR6_DESC_BASE<string opstr, RegisterOperand GPROpnd, + InstrItinClass Itin, SDPatternOperator OpNode=null_frag> : MipsR6Inst { dag OutOperandList = (outs GPROpnd:$rd); @@ -619,15 +680,16 @@ class DIVMOD_MMR6_DESC_BASE<string opstr, RegisterOperand GPROpnd, Format f = FrmR; let isCommutable = 0; let isReMaterializable = 1; + InstrItinClass Itinerary = Itin; // This instruction doesn't trap division by zero itself. We must insert // teq instructions as well. bit usesCustomInserter = 1; } -class DIV_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"div", GPR32Opnd, sdiv>; -class DIVU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"divu", GPR32Opnd, udiv>; -class MOD_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"mod", GPR32Opnd, srem>; -class MODU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"modu", GPR32Opnd, urem>; +class DIV_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"div", GPR32Opnd, II_DIV, sdiv>; +class DIVU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"divu", GPR32Opnd, II_DIVU, udiv>; +class MOD_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"mod", GPR32Opnd, II_MOD, srem>; +class MODU_MMR6_DESC : DIVMOD_MMR6_DESC_BASE<"modu", GPR32Opnd, II_MODU, urem>; class AND_MMR6_DESC : ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>; class ANDI_MMR6_DESC : ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI>; class NOR_MMR6_DESC : LogicNOR<"nor", GPR32Opnd>; @@ -641,19 +703,21 @@ class XORI_MMR6_DESC : ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>; class SWE_MMR6_DESC_BASE<string opstr, DAGOperand RO, DAGOperand MO, - SDPatternOperator OpNode = null_frag, InstrItinClass Itin = NoItinerary, + SDPatternOperator OpNode = null_frag, ComplexPattern Addr = addr> : InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"), [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> { let DecoderMethod = "DecodeMem"; let mayStore = 1; } -class SW_MMR6_DESC : Store<"sw", GPR32Opnd>; -class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9>; +class SW_MMR6_DESC : Store<"sw", GPR32Opnd> { + InstrItinClass Itinerary = II_SW; +} +class SWE_MMR6_DESC : SWE_MMR6_DESC_BASE<"swe", GPR32Opnd, mem_simm9, II_SWE>; -class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> - : MMR6Arch<instr_asm> { +class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO, + InstrItinClass Itin> : MMR6Arch<instr_asm> { dag InOperandList = (ins RO:$rs); dag OutOperandList = (outs RO:$rt); string AsmString = !strconcat(instr_asm, "\t$rt, $rs"); @@ -661,18 +725,21 @@ class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> Format f = FrmR; string BaseOpcode = instr_asm; bit hasSideEffects = 0; + InstrItinClass Itinerary = Itin; } -class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd>; -class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd>; +class WRPGPR_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wrpgpr", GPR32Opnd, + II_WRPGPR>; +class WSBH_MMR6_DESC : WRPGPR_WSBH_MMR6_DESC_BASE<"wsbh", GPR32Opnd, II_WSBH>; class MTC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC, - RegisterOperand SrcRC> { + RegisterOperand SrcRC, InstrItinClass Itin> { dag InOperandList = (ins SrcRC:$rt, uimm3:$sel); dag OutOperandList = (outs DstRC:$rs); string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel"); list<dag> Pattern = []; Format f = FrmFR; string BaseOpcode = opstr; + InstrItinClass Itinerary = Itin; } class MTC1_MMR6_DESC_BASE< string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, @@ -701,34 +768,42 @@ class MTC1_64_MMR6_DESC_BASE< let Constraints = "$fs = $fs_in"; } class MTC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC, - RegisterOperand SrcRC> { + RegisterOperand SrcRC, InstrItinClass Itin> { dag InOperandList = (ins SrcRC:$rt); dag OutOperandList = (outs DstRC:$impl); string AsmString = !strconcat(opstr, "\t$rt, $impl"); list<dag> Pattern = []; Format f = FrmFR; string BaseOpcode = opstr; + InstrItinClass Itinerary = Itin; } -class MTC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mtc0", COP0Opnd, GPR32Opnd>; +class MTC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mtc0", COP0Opnd, GPR32Opnd, + II_MTC0>; class MTC1_MMR6_DESC : MTC1_MMR6_DESC_BASE<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, bitconvert>, HARDFLOAT; -class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd>; -class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd>; -class MTHC1_D32_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", AFGR64Opnd, GPR32Opnd>, +class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd, + II_MTC2>; +class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd, + II_MTHC0>; +class MTHC1_D32_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", AFGR64Opnd, + GPR32Opnd, II_MTC1>, HARDFLOAT, FGR_32; -class MTHC1_D64_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", FGR64Opnd, GPR32Opnd>, +class MTHC1_D64_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", FGR64Opnd, + GPR32Opnd, II_MTC1>, HARDFLOAT, FGR_64; -class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd>; +class MTHC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mthc2", COP2Opnd, GPR32Opnd, + II_MTC2>; class MFC0_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC, - RegisterOperand SrcRC> { + RegisterOperand SrcRC, InstrItinClass Itin> { dag InOperandList = (ins SrcRC:$rs, uimm3:$sel); dag OutOperandList = (outs DstRC:$rt); string AsmString = !strconcat(opstr, "\t$rt, $rs, $sel"); list<dag> Pattern = []; Format f = FrmFR; string BaseOpcode = opstr; + InstrItinClass Itinerary = Itin; } class MFC1_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC, @@ -743,24 +818,29 @@ class MFC1_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC, string BaseOpcode = opstr; } class MFC2_MMR6_DESC_BASE<string opstr, RegisterOperand DstRC, - RegisterOperand SrcRC> { + RegisterOperand SrcRC, InstrItinClass Itin> { dag InOperandList = (ins SrcRC:$impl); dag OutOperandList = (outs DstRC:$rt); string AsmString = !strconcat(opstr, "\t$rt, $impl"); list<dag> Pattern = []; Format f = FrmFR; string BaseOpcode = opstr; + InstrItinClass Itinerary = Itin; } -class MFC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfc0", GPR32Opnd, COP0Opnd>; +class MFC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfc0", GPR32Opnd, COP0Opnd, + II_MFC0>; class MFC1_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, bitconvert>, HARDFLOAT; -class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd>; -class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd>; +class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd, + II_MFC2>; +class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd, + II_MFHC0>; class MFHC1_D32_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, HARDFLOAT, FGR_32; class MFHC1_D64_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, FGR64Opnd, II_MFHC1>, HARDFLOAT, FGR_64; -class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd>; +class MFHC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfhc2", GPR32Opnd, COP2Opnd, + II_MFC2>; class LDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 { dag InOperandList = (ins mem_mm_16:$addr); @@ -786,33 +866,33 @@ class SDC1_D64_MMR6_DESC : MipsR6Inst, HARDFLOAT, FGR_64 { let DecoderMethod = "DecodeFMemMMR2"; } -class LDC2_LWC2_MMR6_DESC_BASE<string opstr> { +class LDC2_LWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> { dag OutOperandList = (outs COP2Opnd:$rt); dag InOperandList = (ins mem_mm_11:$addr); string AsmString = !strconcat(opstr, "\t$rt, $addr"); list<dag> Pattern = [(set COP2Opnd:$rt, (load addrimm11:$addr))]; Format f = FrmFI; - InstrItinClass Itinerary = NoItinerary; + InstrItinClass Itinerary = itin; string BaseOpcode = opstr; bit mayLoad = 1; string DecoderMethod = "DecodeFMemCop2MMR6"; } -class LDC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"ldc2">; -class LWC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"lwc2">; +class LDC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"ldc2", II_LDC2>; +class LWC2_MMR6_DESC : LDC2_LWC2_MMR6_DESC_BASE<"lwc2", II_LWC2>; -class SDC2_SWC2_MMR6_DESC_BASE<string opstr> { +class SDC2_SWC2_MMR6_DESC_BASE<string opstr, InstrItinClass itin> { dag OutOperandList = (outs); dag InOperandList = (ins COP2Opnd:$rt, mem_mm_11:$addr); string AsmString = !strconcat(opstr, "\t$rt, $addr"); list<dag> Pattern = [(store COP2Opnd:$rt, addrimm11:$addr)]; Format f = FrmFI; - InstrItinClass Itinerary = NoItinerary; + InstrItinClass Itinerary = itin; string BaseOpcode = opstr; bit mayStore = 1; string DecoderMethod = "DecodeFMemCop2MMR6"; } -class SDC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"sdc2">; -class SWC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"swc2">; +class SDC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"sdc2", II_SDC2>; +class SWC2_MMR6_DESC : SDC2_SWC2_MMR6_DESC_BASE<"swc2", II_SWC2>; /// Floating Point Instructions class FARITH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RC, @@ -841,10 +921,14 @@ class FDIV_S_MMR6_DESC : FARITH_MMR6_DESC_BASE<"div.s", FGR32Opnd, II_DIV_S, 0, fdiv>; class FDIV_D_MMR6_DESC : FARITH_MMR6_DESC_BASE<"div.d", AFGR64Opnd, II_DIV_D, 0, fdiv>; -class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd>, HARDFLOAT; -class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd>, HARDFLOAT; -class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd>, HARDFLOAT; -class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd>, HARDFLOAT; +class MADDF_S_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.s", FGR32Opnd, + II_MADDF_S>, HARDFLOAT; +class MADDF_D_MMR6_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd, + II_MADDF_D>, HARDFLOAT; +class MSUBF_S_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd, + II_MSUBF_S>, HARDFLOAT; +class MSUBF_D_MMR6_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd, + II_MSUBF_D>, HARDFLOAT; class FMOV_FNEG_MMR6_DESC_BASE<string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC, InstrItinClass Itin, @@ -866,15 +950,23 @@ class FNEG_S_MMR6_DESC class FNEG_D_MMR6_DESC : FMOV_FNEG_MMR6_DESC_BASE<"neg.d", AFGR64Opnd, AFGR64Opnd, II_NEG, fneg>; -class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>, HARDFLOAT; -class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>, HARDFLOAT; -class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>, HARDFLOAT; -class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>, HARDFLOAT; - -class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>, HARDFLOAT; -class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>, HARDFLOAT; -class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>, HARDFLOAT; -class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>, HARDFLOAT; +class MAX_S_MMR6_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>, + HARDFLOAT; +class MAX_D_MMR6_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd, II_MAX_D>, + HARDFLOAT; +class MIN_S_MMR6_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd, II_MIN_S>, + HARDFLOAT; +class MIN_D_MMR6_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd, II_MIN_D>, + HARDFLOAT; + +class MAXA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd, II_MAXA_S>, + HARDFLOAT; +class MAXA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd, II_MAXA_D>, + HARDFLOAT; +class MINA_S_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd, II_MINA_S>, + HARDFLOAT; +class MINA_D_MMR6_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd, II_MINA_D>, + HARDFLOAT; class CVT_MMR6_DESC_BASE< string instr_asm, RegisterOperand DstRC, RegisterOperand SrcRC, @@ -910,70 +1002,70 @@ class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd, II_CVT>, FGR_64; multiclass CMP_CC_MMR6<bits<6> format, string Typestr, - RegisterOperand FGROpnd> { + RegisterOperand FGROpnd, InstrItinClass Itin> { def CMP_AF_#NAME : R6MMR6Rel, POOL32F_CMP_FM< !strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>, - CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT, + CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd, Itin>, HARDFLOAT, ISA_MICROMIPS32R6; def CMP_UN_#NAME : R6MMR6Rel, POOL32F_CMP_FM< !strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>, - CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>, HARDFLOAT, + CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, Itin, setuo>, HARDFLOAT, ISA_MICROMIPS32R6; def CMP_EQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM< !strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>, - CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>, HARDFLOAT, + CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, Itin, setoeq>, HARDFLOAT, ISA_MICROMIPS32R6; def CMP_UEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM< !strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>, - CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>, HARDFLOAT, + CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, Itin, setueq>, HARDFLOAT, ISA_MICROMIPS32R6; def CMP_LT_#NAME : R6MMR6Rel, POOL32F_CMP_FM< !strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>, - CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, setolt>, HARDFLOAT, + CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, Itin, setolt>, HARDFLOAT, ISA_MICROMIPS32R6; def CMP_ULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM< !strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>, - CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>, HARDFLOAT, + CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, Itin, setult>, HARDFLOAT, ISA_MICROMIPS32R6; def CMP_LE_#NAME : R6MMR6Rel, POOL32F_CMP_FM< !strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>, - CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, setole>, HARDFLOAT, + CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, Itin, setole>, HARDFLOAT, ISA_MICROMIPS32R6; def CMP_ULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM< !strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>, - CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>, HARDFLOAT, + CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, Itin, setule>, HARDFLOAT, ISA_MICROMIPS32R6; def CMP_SAF_#NAME : R6MMR6Rel, POOL32F_CMP_FM< !strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>, - CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT, + CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd, Itin>, HARDFLOAT, ISA_MICROMIPS32R6; def CMP_SUN_#NAME : R6MMR6Rel, POOL32F_CMP_FM< !strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>, - CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT, + CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd, Itin>, HARDFLOAT, ISA_MICROMIPS32R6; def CMP_SEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM< !strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>, - CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT, + CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd, Itin>, HARDFLOAT, ISA_MICROMIPS32R6; def CMP_SUEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM< !strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>, - CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT, + CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd, Itin>, HARDFLOAT, ISA_MICROMIPS32R6; def CMP_SLT_#NAME : R6MMR6Rel, POOL32F_CMP_FM< !strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>, - CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT, + CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd, Itin>, HARDFLOAT, ISA_MICROMIPS32R6; def CMP_SULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM< !strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>, - CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT, + CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd, Itin>, HARDFLOAT, ISA_MICROMIPS32R6; def CMP_SLE_#NAME : R6MMR6Rel, POOL32F_CMP_FM< !strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>, - CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT, + CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd, Itin>, HARDFLOAT, ISA_MICROMIPS32R6; def CMP_SULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM< !strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>, - CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT, + CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd, Itin>, HARDFLOAT, ISA_MICROMIPS32R6; } @@ -1022,14 +1114,6 @@ class SQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.s", FGR32Opnd, FGR32Opnd, II_SQRT_S, fsqrt>; class SQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"sqrt.d", AFGR64Opnd, AFGR64Opnd, II_SQRT_D, fsqrt>; -class RSQRT_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.s", FGR32Opnd, - FGR32Opnd, II_TRUNC>; -class RSQRT_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"rsqrt.d", FGR32Opnd, - AFGR64Opnd, II_TRUNC>; -class RECIP_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"recip.s", FGR32Opnd, - FGR32Opnd, II_ROUND>; -class RECIP_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"recip.d", FGR32Opnd, FGR32Opnd, - II_ROUND>; class ROUND_L_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>; class ROUND_L_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.l.d", FGR64Opnd, @@ -1039,49 +1123,63 @@ class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.s", FGR32Opnd, class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd, FGR64Opnd, II_ROUND>; -class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>; -class SEL_D_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd> { +class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, II_SEL_S>; +class SEL_D_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd, II_SEL_D> { // We must insert a SUBREG_TO_REG around $fd_in bit usesCustomInserter = 1; } -class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>; -class SELEQZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>; -class SELNEZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>; -class SELNEZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>; -class RINT_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>; -class RINT_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>; -class CLASS_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>; -class CLASS_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>; - -class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO> +class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd, + II_SELCCZ_S>; +class SELEQZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd, + II_SELCCZ_D>; +class SELNEZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd, + II_SELCCZ_S>; +class SELNEZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd, + II_SELCCZ_D>; +class RINT_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd, + II_RINT_S>; +class RINT_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd, + II_RINT_S>; +class CLASS_S_MMR6_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd, + II_CLASS_S>; +class CLASS_D_MMR6_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd, + II_CLASS_S>; + +class STORE_MMR6_DESC_BASE<string opstr, DAGOperand RO, + InstrItinClass Itin> : Store<opstr, RO>, MMR6Arch<opstr> { let DecoderMethod = "DecodeMemMMImm16"; + InstrItinClass Itinerary = Itin; } -class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd>; +class SB_MMR6_DESC : STORE_MMR6_DESC_BASE<"sb", GPR32Opnd, II_SB>; -class STORE_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> +class STORE_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO, + InstrItinClass Itin> : MMR6Arch<instr_asm>, MipsR6Inst { dag OutOperandList = (outs); dag InOperandList = (ins RO:$rt, mem_simm9:$addr); string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); string DecoderMethod = "DecodeStoreEvaOpMM"; bit mayStore = 1; + InstrItinClass Itinerary = Itin; } -class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd>; -class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd>; -class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd>; -class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd>; -class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO> : - MMR6Arch<instr_asm>, MipsR6Inst { +class SBE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sbe", GPR32Opnd, II_SBE>; +class SCE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"sce", GPR32Opnd, II_SCE>; +class SH_MMR6_DESC : STORE_MMR6_DESC_BASE<"sh", GPR32Opnd, II_SH>; +class SHE_MMR6_DESC : STORE_EVA_MMR6_DESC_BASE<"she", GPR32Opnd, II_SHE>; +class LOAD_WORD_EVA_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO, + InstrItinClass Itin> + : MMR6Arch<instr_asm>, MipsR6Inst { dag OutOperandList = (outs RO:$rt); dag InOperandList = (ins mem_simm9:$addr); string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); string DecoderMethod = "DecodeMemMMImm9"; bit mayLoad = 1; + InstrItinClass Itinerary = Itin; } -class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd>; -class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd>; +class LLE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lle", GPR32Opnd, II_LLE>; +class LWE_MMR6_DESC : LOAD_WORD_EVA_MMR6_DESC_BASE<"lwe", GPR32Opnd, II_LWE>; class ADDU16_MMR6_DESC : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>, MMR6Arch<"addu16"> { int AddedComplexity = 1; @@ -1103,13 +1201,13 @@ class SLL16_MMR6_DESC : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>, MMR6Arch<"sll16">; class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>, MMR6Arch<"srl16">; -class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16">, MMR6Arch<"break16">, +class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16", II_BREAK>, MMR6Arch<"break16">, MicroMipsR6Inst16; class LI16_MMR6_DESC : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>, MMR6Arch<"li16">, MicroMipsR6Inst16, IsAsCheapAsAMove; class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">, MicroMipsR6Inst16; -class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16">, MMR6Arch<"sdbbp16">, +class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, MMR6Arch<"sdbbp16">, MicroMipsR6Inst16; class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>, MMR6Arch<"subu16">, MicroMipsR6Inst16 { @@ -1147,7 +1245,7 @@ class SYNC_MMR6_DESC : MMR6Arch<"sync">, MipsR6Inst { dag InOperandList = (ins uimm5:$stype); string AsmString = !strconcat("sync", "\t$stype"); list<dag> Pattern = [(MipsSync immZExt5:$stype)]; - InstrItinClass Itinerary = NoItinerary; + InstrItinClass Itinerary = II_SYNC; bit HasSideEffects = 1; } @@ -1159,6 +1257,7 @@ class RDPGPR_MMR6_DESC : MMR6Arch<"rdpgpr">, MipsR6Inst { dag OutOperandList = (outs GPR32Opnd:$rt); dag InOperandList = (ins GPR32Opnd:$rd); string AsmString = !strconcat("rdpgpr", "\t$rt, $rd"); + InstrItinClass Itinerary = II_RDPGPR; } class SDBBP_MMR6_DESC : MipsR6Inst { @@ -1166,27 +1265,26 @@ class SDBBP_MMR6_DESC : MipsR6Inst { dag InOperandList = (ins uimm20:$code_); string AsmString = !strconcat("sdbbp", "\t$code_"); list<dag> Pattern = []; + InstrItinClass Itinerary = II_SDBBP; } class LWM16_MMR6_DESC : MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr), !strconcat("lwm16", "\t$rt, $addr"), [], - NoItinerary, FrmI>, + II_LWM, FrmI>, MMR6Arch<"lwm16">, MicroMipsR6Inst16 { let DecoderMethod = "DecodeMemMMReglistImm4Lsl2"; let mayLoad = 1; - InstrItinClass Itin = NoItinerary; ComplexPattern Addr = addr; } class SWM16_MMR6_DESC : MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr), !strconcat("swm16", "\t$rt, $addr"), [], - NoItinerary, FrmI>, + II_SWM, FrmI>, MMR6Arch<"swm16">, MicroMipsR6Inst16 { let DecoderMethod = "DecodeMemMMReglistImm4Lsl2"; let mayStore = 1; - InstrItinClass Itin = NoItinerary; ComplexPattern Addr = addr; } @@ -1219,31 +1317,34 @@ class JALRC_HB_MMR6_DESC { dag InOperandList = (ins GPR32Opnd:$rs); string AsmString = !strconcat("jalrc.hb", "\t$rt, $rs"); list<dag> Pattern = []; - InstrItinClass Itinerary = NoItinerary; + InstrItinClass Itinerary = II_JALR_HB; Format Form = FrmJ; bit isIndirectBranch = 1; bit hasDelaySlot = 0; } -class TLBINV_MMR6_DESC_BASE<string opstr> { +class TLBINV_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> { dag OutOperandList = (outs); dag InOperandList = (ins); string AsmString = opstr; list<dag> Pattern = []; + InstrItinClass Itinerary = Itin; } -class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv">; -class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf">; +class TLBINV_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinv", II_TLBINV>; +class TLBINVF_MMR6_DESC : TLBINV_MMR6_DESC_BASE<"tlbinvf", II_TLBINVF>; -class DVPEVP_MMR6_DESC_BASE<string opstr> { - dag OutOperandList = (outs); - dag InOperandList = (ins GPR32Opnd:$rs); +class DVPEVP_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> { + dag OutOperandList = (outs GPR32Opnd:$rs); + dag InOperandList = (ins); string AsmString = !strconcat(opstr, "\t$rs"); list<dag> Pattern = []; + InstrItinClass Itinerary = Itin; + bit hasUnModeledSideEffects = 1; } -class DVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"dvp">; -class EVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"evp">; +class DVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"dvp", II_DVP>; +class EVP_MMR6_DESC : DVPEVP_MMR6_DESC_BASE<"evp", II_EVP>; class BEQZC_MMR6_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21_mm, GPR32Opnd>, @@ -1262,15 +1363,17 @@ class BRANCH_COP1_MMR6_DESC_BASE<string opstr> : class BC1EQZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1eqzc">; class BC1NEZC_MMR6_DESC : BRANCH_COP1_MMR6_DESC_BASE<"bc1nezc">; -class BRANCH_COP2_MMR6_DESC_BASE<string opstr> : BRANCH_DESC_BASE { +class BRANCH_COP2_MMR6_DESC_BASE<string opstr, InstrItinClass Itin> + : BRANCH_DESC_BASE { dag InOperandList = (ins COP2Opnd:$rt, brtarget_mm:$offset); dag OutOperandList = (outs); string AsmString = !strconcat(opstr, "\t$rt, $offset"); list<Register> Defs = [AT]; + InstrItinClass Itinerary = Itin; } -class BC2EQZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2eqzc">; -class BC2NEZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2nezc">; +class BC2EQZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2eqzc", II_BC2CCZ>; +class BC2NEZC_MMR6_DESC : BRANCH_COP2_MMR6_DESC_BASE<"bc2nezc", II_BC2CCZ>; class EXT_MMR6_DESC { dag OutOperandList = (outs GPR32Opnd:$rt); @@ -1314,6 +1417,7 @@ class BOVC_BNVC_MMR6_DESC_BASE<string instr_asm, Operand opnd, dag OutOperandList = (outs); string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $offset"); list<Register> Defs = [AT]; + InstrItinClass Itinerary = II_BCCC; } class BOVC_MMR6_DESC : BOVC_BNVC_MMR6_DESC_BASE<"bovc", brtargetr6, GPR32Opnd>; @@ -1517,8 +1621,8 @@ def CVT_S_W_MMR6 : StdMMR6Rel, CVT_S_W_MMR6_ENC, CVT_S_W_MMR6_DESC, ISA_MICROMIPS32R6; def CVT_S_L_MMR6 : StdMMR6Rel, CVT_S_L_MMR6_ENC, CVT_S_L_MMR6_DESC, ISA_MICROMIPS32R6; -defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd>; -defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd>; +defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd, II_CMP_CC_S>; +defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd, II_CMP_CC_D>; def ABS_S_MMR6 : StdMMR6Rel, ABS_S_MMR6_ENC, ABS_S_MMR6_DESC, ISA_MICROMIPS32R6; def ABS_D_MMR6 : StdMMR6Rel, ABS_D_MMR6_ENC, ABS_D_MMR6_DESC, ISA_MICROMIPS32R6; def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC, @@ -1549,10 +1653,6 @@ def SQRT_S_MMR6 : StdMMR6Rel, SQRT_S_MMR6_ENC, SQRT_S_MMR6_DESC, ISA_MICROMIPS32R6; def SQRT_D_MMR6 : StdMMR6Rel, SQRT_D_MMR6_ENC, SQRT_D_MMR6_DESC, ISA_MICROMIPS32R6; -def RSQRT_S_MMR6 : StdMMR6Rel, RSQRT_S_MMR6_ENC, RSQRT_S_MMR6_DESC, - ISA_MICROMIPS32R6; -def RSQRT_D_MMR6 : StdMMR6Rel, RSQRT_D_MMR6_ENC, RSQRT_D_MMR6_DESC, - ISA_MICROMIPS32R6; def SB_MMR6 : StdMMR6Rel, SB_MMR6_DESC, SB_MMR6_ENC, ISA_MICROMIPS32R6; def SBE_MMR6 : StdMMR6Rel, SBE_MMR6_DESC, SBE_MMR6_ENC, ISA_MICROMIPS32R6; def SCE_MMR6 : StdMMR6Rel, SCE_MMR6_DESC, SCE_MMR6_ENC, ISA_MICROMIPS32R6; @@ -1593,9 +1693,6 @@ def JALRC_HB_MMR6 : R6MMR6Rel, JALRC_HB_MMR6_ENC, JALRC_HB_MMR6_DESC, def EXT_MMR6 : StdMMR6Rel, EXT_MMR6_ENC, EXT_MMR6_DESC, ISA_MICROMIPS32R6; def INS_MMR6 : StdMMR6Rel, INS_MMR6_ENC, INS_MMR6_DESC, ISA_MICROMIPS32R6; def JALRC_MMR6 : R6MMR6Rel, JALRC_MMR6_ENC, JALRC_MMR6_DESC, ISA_MICROMIPS32R6; -def RECIP_S_MMR6 : StdMMR6Rel, RECIP_S_MMR6_ENC, RECIP_S_MMR6_DESC, - ISA_MICROMIPS32R6; -def RECIP_D_MMR6 : StdMMR6Rel, RECIP_D_MMR6_ENC, RECIP_D_MMR6_DESC, ISA_MICROMIPS32R6; def RINT_S_MMR6 : StdMMR6Rel, RINT_S_MMR6_ENC, RINT_S_MMR6_DESC, ISA_MICROMIPS32R6; def RINT_D_MMR6 : StdMMR6Rel, RINT_D_MMR6_ENC, RINT_D_MMR6_DESC, ISA_MICROMIPS32R6; @@ -1661,6 +1758,10 @@ def BEQC_MMR6 : R6MMR6Rel, BEQC_MMR6_ENC, BEQC_MMR6_DESC, ISA_MICROMIPS32R6, DecodeDisambiguates<"POP35GroupBranchMMR6">; def BNEC_MMR6 : R6MMR6Rel, BNEC_MMR6_ENC, BNEC_MMR6_DESC, ISA_MICROMIPS32R6, DecodeDisambiguates<"POP37GroupBranchMMR6">; +def BLTZC_MMR6 : R6MMR6Rel, BLTZC_MMR6_ENC, BLTZC_MMR6_DESC, ISA_MICROMIPS32R6; +def BLEZC_MMR6 : R6MMR6Rel, BLEZC_MMR6_ENC, BLEZC_MMR6_DESC, ISA_MICROMIPS32R6; +def BGEZC_MMR6 : R6MMR6Rel, BGEZC_MMR6_ENC, BGEZC_MMR6_DESC, ISA_MICROMIPS32R6; +def BGTZC_MMR6 : R6MMR6Rel, BGTZC_MMR6_ENC, BGTZC_MMR6_DESC, ISA_MICROMIPS32R6; def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC, ISA_MICROMIPS32R6; def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC, @@ -1727,6 +1828,10 @@ def : MipsInstAlias<"xor $rs, $imm", def : MipsInstAlias<"not $rt, $rs", (NOR_MMR6 GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>, ISA_MICROMIPS32R6; +def : MipsInstAlias<"seh $rd", (SEH_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, + ISA_MICROMIPS32R6; +def : MipsInstAlias<"seb $rd", (SEB_MMR6 GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, + ISA_MICROMIPS32R6; //===----------------------------------------------------------------------===// // @@ -1772,3 +1877,5 @@ let AddedComplexity = 41 in { def : LoadRegImmPat<LDC1_D64_MMR6, f64, load>, FGR_64, ISA_MICROMIPS32R6; def : StoreRegImmPat<SDC1_D64_MMR6, f64>, FGR_64, ISA_MICROMIPS32R6; } + +def TAILCALL_MMR6 : TailCall<BC_MMR6, brtarget26_mm>, ISA_MICROMIPS32R6; diff --git a/contrib/llvm/lib/Target/Mips/MicroMips64r6InstrFormats.td b/contrib/llvm/lib/Target/Mips/MicroMips64r6InstrFormats.td index 4add305..26062bf 100644 --- a/contrib/llvm/lib/Target/Mips/MicroMips64r6InstrFormats.td +++ b/contrib/llvm/lib/Target/Mips/MicroMips64r6InstrFormats.td @@ -219,3 +219,49 @@ class POOL32S_3R_FM_MMR6<string instr_asm, bits<9> funct> let Inst{10-9} = 0b00; let Inst{8-0} = funct; } + +class POOL32S_DBITSWAP_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm>, + MipsR6Inst { + bits<5> rt; + bits<5> rd; + + bits<32> Inst; + + let Inst{31-26} = 0b010110; + let Inst{25-21} = rt; + let Inst{20-16} = rd; + let Inst{15-12} = 0b0000; + let Inst{11-6} = 0b101100; + let Inst{5-0} = 0b111100; +} + +class POOL32S_3RSA_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm>, + MipsR6Inst { + bits<5> rt; + bits<5> rs; + bits<5> rd; + bits<2> sa; + + bits<32> Inst; + + let Inst{31-26} = 0b010110; + let Inst{25-21} = rt; + let Inst{20-16} = rs; + let Inst{15-11} = rd; + let Inst{10-9} = sa; + let Inst{8-6} = 0b100; + let Inst{5-0} = 0b000100; +} + +class PCREL_1ROFFSET19_FM_MMR6<string instr_asm> : MMR6Arch<instr_asm>, + MipsR6Inst { + bits<5> rt; + bits<19> offset; + + bits<32> Inst; + + let Inst{31-26} = 0b011110; + let Inst{25-21} = rt; + let Inst{20-19} = 0b10; + let Inst{18-0} = offset; +} diff --git a/contrib/llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td b/contrib/llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td index 87c41de..05aad51 100644 --- a/contrib/llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td +++ b/contrib/llvm/lib/Target/Mips/MicroMips64r6InstrInfo.td @@ -67,6 +67,9 @@ class SD_MM64R6_ENC : LD_SD_32_2R_OFFSET16_FM_MMR6<"sd", 0b110110>; class DSRL_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsrl", 0b001000000>; class DSRL32_MM64R6_ENC : POOL32S_2RSA5B0_FM_MMR6<"dsrl32", 0b001001000>; class DSRLV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"dsrlv", 0b001010000>; +class DBITSWAP_MM64R6_ENC : POOL32S_DBITSWAP_FM_MMR6<"dbitswap">; +class DLSA_MM64R6_ENC : POOL32S_3RSA_FM_MMR6<"dlsa">; +class LWUPC_MM64R6_ENC : PCREL_1ROFFSET19_FM_MMR6<"lwupc">; //===----------------------------------------------------------------------===// // @@ -74,24 +77,28 @@ class DSRLV_MM64R6_ENC : POOL32S_3R_FM_MMR6<"dsrlv", 0b001010000>; // //===----------------------------------------------------------------------===// -class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> +class DAUI_MMR6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, + InstrItinClass Itin> : MMR6Arch<instr_asm>, MipsR6Inst { dag OutOperandList = (outs GPROpnd:$rt); - dag InOperandList = (ins GPROpnd:$rs, simm16:$imm); + dag InOperandList = (ins GPROpnd:$rs, uimm16:$imm); string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm"); list<dag> Pattern = []; + InstrItinClass Itinerary = Itin; } -class DAUI_MMR6_DESC : DAUI_MMR6_DESC_BASE<"daui", GPR64Opnd>; +class DAUI_MMR6_DESC : DAUI_MMR6_DESC_BASE<"daui", GPR64Opnd, II_DAUI>; -class DAHI_DATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> +class DAHI_DATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, + InstrItinClass Itin> : MMR6Arch<instr_asm>, MipsR6Inst { dag OutOperandList = (outs GPROpnd:$rs); - dag InOperandList = (ins GPROpnd:$rt, simm16:$imm); - string AsmString = !strconcat(instr_asm, "\t$rt, $imm"); + dag InOperandList = (ins GPROpnd:$rt, uimm16:$imm); + string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $imm"); string Constraints = "$rs = $rt"; + InstrItinClass Itinerary = Itin; } -class DAHI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dahi", GPR64Opnd>; -class DATI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dati", GPR64Opnd>; +class DAHI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dahi", GPR64Opnd, II_DAHI>; +class DATI_MMR6_DESC : DAHI_DATI_DESC_BASE<"dati", GPR64Opnd, II_DATI>; class EXTBITS_DESC_BASE<string instr_asm, RegisterOperand RO, Operand PosOpnd, Operand SizeOpnd, SDPatternOperator Op = null_frag> @@ -115,26 +122,33 @@ class DEXTU_MMR6_DESC : EXTBITS_DESC_BASE<"dextu", GPR64Opnd, uimm5_plus32, uimm5_plus1, MipsExt>; class DALIGN_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, - Operand ImmOpnd> : MMR6Arch<instr_asm>, MipsR6Inst { + Operand ImmOpnd, InstrItinClass itin> + : MMR6Arch<instr_asm>, MipsR6Inst { dag OutOperandList = (outs GPROpnd:$rd); dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, ImmOpnd:$bp); string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $bp"); list<dag> Pattern = []; + InstrItinClass Itinerary = itin; } -class DALIGN_MMR6_DESC : DALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3>; +class DALIGN_MMR6_DESC : DALIGN_DESC_BASE<"dalign", GPR64Opnd, uimm3, + II_DALIGN>; -class DDIV_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddiv", GPR64Opnd, sdiv>; -class DMOD_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmod", GPR64Opnd, srem>; -class DDIVU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddivu", GPR64Opnd, udiv>; -class DMODU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmodu", GPR64Opnd, urem>; +class DDIV_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddiv", GPR64Opnd, II_DDIV, + sdiv>; +class DMOD_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmod", GPR64Opnd, II_DMOD, + srem>; +class DDIVU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"ddivu", GPR64Opnd, II_DDIVU, + udiv>; +class DMODU_MM64R6_DESC : DIVMOD_MMR6_DESC_BASE<"dmodu", GPR64Opnd, II_DMODU, + urem>; class DCLO_MM64R6_DESC { dag OutOperandList = (outs GPR64Opnd:$rt); dag InOperandList = (ins GPR64Opnd:$rs); string AsmString = !strconcat("dclo", "\t$rt, $rs"); list<dag> Pattern = [(set GPR64Opnd:$rt, (ctlz (not GPR64Opnd:$rs)))]; - InstrItinClass Itinerary = II_CLO; + InstrItinClass Itinerary = II_DCLO; Format Form = FrmR; string BaseOpcode = "dclo"; } @@ -144,7 +158,7 @@ class DCLZ_MM64R6_DESC { dag InOperandList = (ins GPR64Opnd:$rs); string AsmString = !strconcat("dclz", "\t$rt, $rs"); list<dag> Pattern = [(set GPR64Opnd:$rt, (ctlz GPR64Opnd:$rs))]; - InstrItinClass Itinerary = II_CLZ; + InstrItinClass Itinerary = II_DCLZ; Format Form = FrmR; string BaseOpcode = "dclz"; } @@ -154,16 +168,18 @@ class DINSU_MM64R6_DESC : InsBase<"dinsu", GPR64Opnd, uimm5_plus32, class DINSM_MM64R6_DESC : InsBase<"dinsm", GPR64Opnd, uimm5, uimm_range_2_64>; class DINS_MM64R6_DESC : InsBase<"dins", GPR64Opnd, uimm5, uimm5_inssize_plus1, MipsIns>; -class DMTC0_MM64R6_DESC : MTC0_MMR6_DESC_BASE<"dmtc0", COP0Opnd, GPR64Opnd>; +class DMTC0_MM64R6_DESC : MTC0_MMR6_DESC_BASE<"dmtc0", COP0Opnd, GPR64Opnd, + II_DMTC0>; class DMTC1_MM64R6_DESC : MTC1_MMR6_DESC_BASE<"dmtc1", FGR64Opnd, GPR64Opnd, II_DMTC1, bitconvert>; -class DMTC2_MM64R6_DESC : MTC2_MMR6_DESC_BASE<"dmtc2", COP2Opnd, GPR64Opnd>; - -class DMFC0_MM64R6_DESC : MFC0_MMR6_DESC_BASE<"dmfc0", GPR64Opnd, COP0Opnd>; +class DMTC2_MM64R6_DESC : MTC2_MMR6_DESC_BASE<"dmtc2", COP2Opnd, GPR64Opnd, + II_DMTC2>; +class DMFC0_MM64R6_DESC : MFC0_MMR6_DESC_BASE<"dmfc0", GPR64Opnd, COP0Opnd, + II_DMFC0>; class DMFC1_MM64R6_DESC : MFC1_MMR6_DESC_BASE<"dmfc1", GPR64Opnd, FGR64Opnd, II_DMFC1, bitconvert>; -class DMFC2_MM64R6_DESC : MFC2_MMR6_DESC_BASE<"dmfc2", GPR64Opnd, COP2Opnd>; - +class DMFC2_MM64R6_DESC : MFC2_MMR6_DESC_BASE<"dmfc2", GPR64Opnd, COP2Opnd, + II_DMFC2>; class DADD_MM64R6_DESC : ArithLogicR<"dadd", GPR64Opnd, 1, II_DADD>; class DADDIU_MM64R6_DESC : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU, immSExt16, add>, @@ -188,7 +204,8 @@ class DSUB_DESC_BASE<string instr_asm, RegisterOperand RO, class DSUB_MM64R6_DESC : DSUB_DESC_BASE<"dsub", GPR64Opnd, II_DSUB>; class DSUBU_MM64R6_DESC : DSUB_DESC_BASE<"dsubu", GPR64Opnd, II_DSUBU, sub>; -class LDPC_MM64R6_DESC : PCREL_MMR6_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3>; +class LDPC_MM64R6_DESC : PCREL_MMR6_DESC_BASE<"ldpc", GPR64Opnd, simm18_lsl3, + II_LDPC>; class MUL_MM64R6_DESC_BASE<string opstr, RegisterOperand GPROpnd, InstrItinClass Itin = NoItinerary, @@ -207,19 +224,20 @@ class DMULU_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmulu", GPR64Opnd, II_DMULU>; class DMUHU_MM64R6_DESC : MUL_MM64R6_DESC_BASE<"dmuhu", GPR64Opnd, II_DMUHU, mulhu>; -class DSBH_DSHD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> { +class DSBH_DSHD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, + InstrItinClass Itin> { dag OutOperandList = (outs GPROpnd:$rt); dag InOperandList = (ins GPROpnd:$rs); string AsmString = !strconcat(instr_asm, "\t$rt, $rs"); bit hasSideEffects = 0; list<dag> Pattern = []; - InstrItinClass Itinerary = NoItinerary; + InstrItinClass Itinerary = Itin; Format Form = FrmR; string BaseOpcode = instr_asm; } -class DSBH_MM64R6_DESC : DSBH_DSHD_DESC_BASE<"dsbh", GPR64Opnd>; -class DSHD_MM64R6_DESC : DSBH_DSHD_DESC_BASE<"dshd", GPR64Opnd>; +class DSBH_MM64R6_DESC : DSBH_DSHD_DESC_BASE<"dsbh", GPR64Opnd, II_DSBH>; +class DSHD_MM64R6_DESC : DSBH_DSHD_DESC_BASE<"dshd", GPR64Opnd, II_DSHD>; class SHIFT_ROTATE_IMM_MM64R6<string instr_asm, Operand ImmOpnd, InstrItinClass itin, @@ -308,6 +326,32 @@ class SD_MM64R6_DESC { string DecoderMethod = "DecodeMemMMImm16"; } +class DBITSWAP_MM64R6_DESC { + dag OutOperandList = (outs GPR64Opnd:$rd); + dag InOperandList = (ins GPR64Opnd:$rt); + string AsmString = !strconcat("dbitswap", "\t$rd, $rt"); + list<dag> Pattern = []; + InstrItinClass Itinerary = II_DBITSWAP; +} + +class DLSA_MM64R6_DESC { + dag OutOperandList = (outs GPR64Opnd:$rd); + dag InOperandList = (ins GPR64Opnd:$rt, GPR64Opnd:$rs, uimm2_plus1:$sa); + string AsmString = "dlsa\t$rt, $rs, $rd, $sa"; + list<dag> Pattern = []; + InstrItinClass Itinerary = II_DLSA; +} + +class LWUPC_MM64R6_DESC { + dag OutOperandList = (outs GPR64Opnd:$rt); + dag InOperandList = (ins simm19_lsl2:$offset); + string AsmString = "lwupc\t$rt, $offset"; + list<dag> Pattern = []; + InstrItinClass Itinerary = II_LWUPC; + bit mayLoad = 1; + bit IsPCRelativeLoad = 1; +} + //===----------------------------------------------------------------------===// // // Instruction Definitions @@ -316,8 +360,10 @@ class SD_MM64R6_DESC { let DecoderNamespace = "MicroMipsR6" in { def DAUI_MM64R6 : StdMMR6Rel, DAUI_MMR6_DESC, DAUI_MMR6_ENC, ISA_MICROMIPS64R6; - def DAHI_MM64R6 : StdMMR6Rel, DAHI_MMR6_DESC, DAHI_MMR6_ENC, ISA_MICROMIPS64R6; - def DATI_MM64R6 : StdMMR6Rel, DATI_MMR6_DESC, DATI_MMR6_ENC, ISA_MICROMIPS64R6; + let DecoderMethod = "DecodeDAHIDATIMMR6" in { + def DAHI_MM64R6 : StdMMR6Rel, DAHI_MMR6_DESC, DAHI_MMR6_ENC, ISA_MICROMIPS64R6; + def DATI_MM64R6 : StdMMR6Rel, DATI_MMR6_DESC, DATI_MMR6_ENC, ISA_MICROMIPS64R6; + } def DEXT_MM64R6 : StdMMR6Rel, DEXT_MMR6_DESC, DEXT_MMR6_ENC, ISA_MICROMIPS64R6; def DEXTM_MM64R6 : StdMMR6Rel, DEXTM_MMR6_DESC, DEXTM_MMR6_ENC, @@ -412,8 +458,17 @@ let DecoderNamespace = "MicroMipsR6" in { ISA_MICROMIPS64R6; def DSRLV_MM64R6 : StdMMR6Rel, DSRLV_MM64R6_ENC, DSRLV_MM64R6_DESC, ISA_MICROMIPS64R6; + def DBITSWAP_MM64R6 : R6MMR6Rel, DBITSWAP_MM64R6_ENC, DBITSWAP_MM64R6_DESC, + ISA_MICROMIPS64R6; + def DLSA_MM64R6 : R6MMR6Rel, DLSA_MM64R6_ENC, DLSA_MM64R6_DESC, + ISA_MICROMIPS64R6; + def LWUPC_MM64R6 : R6MMR6Rel, LWUPC_MM64R6_ENC, LWUPC_MM64R6_DESC, + ISA_MICROMIPS64R6; } +let AdditionalPredicates = [InMicroMips] in +defm : MaterializeImms<i64, ZERO_64, DADDIU_MM64R6, LUi64, ORi64>; + //===----------------------------------------------------------------------===// // // Arbitrary patterns that map to one or more instructions @@ -503,11 +558,11 @@ def : MipsInstAlias<"dneg $rt, $rs", (DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>, ISA_MICROMIPS64R6; def : MipsInstAlias<"dneg $rt", - (DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>, + (DSUB_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>, ISA_MICROMIPS64R6; def : MipsInstAlias<"dnegu $rt, $rs", (DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>, ISA_MICROMIPS64R6; def : MipsInstAlias<"dnegu $rt", - (DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>, + (DSUBU_MM64R6 GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>, ISA_MICROMIPS64R6; diff --git a/contrib/llvm/lib/Target/Mips/MicroMipsInstrFPU.td b/contrib/llvm/lib/Target/Mips/MicroMipsInstrFPU.td index 7b0e00b..5600f71 100644 --- a/contrib/llvm/lib/Target/Mips/MicroMipsInstrFPU.td +++ b/contrib/llvm/lib/Target/Mips/MicroMipsInstrFPU.td @@ -27,9 +27,20 @@ def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM_MM<0x188>, INSN_MIPS5_32R2_NOT_32R6_64R6; def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, - CEQS_FM_MM<0>; + CEQS_FM_MM<0> { + // FIXME: This is a required to work around the fact that these instructions + // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the + // fcc register set is used directly. + bits<3> fcc = 0; +} + def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, - CEQS_FM_MM<1>; + CEQS_FM_MM<1> { + // FIXME: This is a required to work around the fact that these instructions + // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the + // fcc register set is used directly. + bits<3> fcc = 0; +} def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>, BC1F_FM_MM<0x1c>, ISA_MIPS1_NOT_32R6_64R6; @@ -99,11 +110,6 @@ def MOVT_D32_MM : MMRel, CMov_F_F_FT<"movt.d", AFGR64Opnd, II_MOVT_D, MipsCMovFP_T>, CMov_F_F_FM_MM<0x60, 1>; def MOVF_D32_MM : MMRel, CMov_F_F_FT<"movf.d", AFGR64Opnd, II_MOVF_D, MipsCMovFP_F>, CMov_F_F_FM_MM<0x20, 1>; - -def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, - MFC1_FM_MM<0x40>; -def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, - MFC1_FM_MM<0x60>; def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, bitconvert>, MFC1_FM_MM<0x80>; def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, @@ -141,6 +147,22 @@ let AdditionalPredicates = [InMicroMips] in { MFC1_FM_MM<0xe0>, ISA_MIPS32R2, FGR_32; def MFHC1_MM : MMRel, MFC1_FT<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, MFC1_FM_MM<0xc0>, ISA_MIPS32R2, FGR_32; + let DecoderNamespace = "MicroMips" in { + def CFC1_MM : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, + MFC1_FM_MM<0x40>; + def CTC1_MM : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, + MFC1_FM_MM<0x60>; + def RECIP_S_MM : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, + II_RECIP_S>, + ROUND_W_FM_MM<0b0, 0b01001000>; + def RECIP_D_MM : MMRel, ABSS_FT<"recip.d", AFGR64Opnd, AFGR64Opnd, + II_RECIP_D>, ROUND_W_FM_MM<0b1, 0b01001000>; + def RSQRT_S_MM : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, + II_RECIP_S>, + ROUND_W_FM_MM<0b0, 0b00001000>; + def RSQRT_D_MM : MMRel, ABSS_FT<"rsqrt.d", AFGR64Opnd, AFGR64Opnd, + II_RECIP_D>, ROUND_W_FM_MM<0b1, 0b00001000>; + } let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeFMemMMR2" in { def LDC1_MM : MMRel, LW_FT<"ldc1", AFGR64Opnd, mem_mm_16, II_LDC1, load>, LW_FM_MM<0x2f>, FGR_32 { @@ -153,6 +175,98 @@ let AdditionalPredicates = [InMicroMips] in { def SWC1_MM : MMRel, SW_FT<"swc1", FGR32Opnd, mem_mm_16, II_SWC1, store>, LW_FM_MM<0x26>; } + + multiclass C_COND_MM<string TypeStr, RegisterOperand RC, bits<2> fmt, + InstrItinClass itin> { + def C_F_#NAME#_MM : MMRel, C_COND_FT<"f", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 0> { + let BaseOpcode = "c.f."#NAME; + let isCommutable = 1; + } + def C_UN_#NAME#_MM : MMRel, C_COND_FT<"un", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 1> { + let BaseOpcode = "c.un."#NAME; + let isCommutable = 1; + } + def C_EQ_#NAME#_MM : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 2> { + let BaseOpcode = "c.eq."#NAME; + let isCommutable = 1; + } + def C_UEQ_#NAME#_MM : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 3> { + let BaseOpcode = "c.ueq."#NAME; + let isCommutable = 1; + } + def C_OLT_#NAME#_MM : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 4> { + let BaseOpcode = "c.olt."#NAME; + } + def C_ULT_#NAME#_MM : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 5> { + let BaseOpcode = "c.ult."#NAME; + } + def C_OLE_#NAME#_MM : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 6> { + let BaseOpcode = "c.ole."#NAME; + } + def C_ULE_#NAME#_MM : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 7> { + let BaseOpcode = "c.ule."#NAME; + } + def C_SF_#NAME#_MM : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 8> { + let BaseOpcode = "c.sf."#NAME; + let isCommutable = 1; + } + def C_NGLE_#NAME#_MM : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 9> { + let BaseOpcode = "c.ngle."#NAME; + } + def C_SEQ_#NAME#_MM : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 10> { + let BaseOpcode = "c.seq."#NAME; + let isCommutable = 1; + } + def C_NGL_#NAME#_MM : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 11> { + let BaseOpcode = "c.ngl."#NAME; + } + def C_LT_#NAME#_MM : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 12> { + let BaseOpcode = "c.lt."#NAME; + } + def C_NGE_#NAME#_MM : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 13> { + let BaseOpcode = "c.nge."#NAME; + } + def C_LE_#NAME#_MM : MMRel, C_COND_FT<"le", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 14> { + let BaseOpcode = "c.le."#NAME; + } + def C_NGT_#NAME#_MM : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>, + C_COND_FM_MM<fmt, 15> { + let BaseOpcode = "c.ngt."#NAME; + } + } + + defm S : C_COND_MM<"s", FGR32Opnd, 0b00, II_C_CC_S>, + ISA_MIPS1_NOT_32R6_64R6; + defm D32 : C_COND_MM<"d", AFGR64Opnd, 0b01, II_C_CC_D>, + ISA_MIPS1_NOT_32R6_64R6, FGR_32; + let DecoderNamespace = "Mips64" in + defm D64 : C_COND_MM<"d", FGR64Opnd, 0b01, II_C_CC_D>, + ISA_MIPS1_NOT_32R6_64R6, FGR_64; + + defm S_MM : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT, + ISA_MIPS1_NOT_32R6_64R6; + defm D32_MM : C_COND_ALIASES<"d", AFGR64Opnd>, HARDFLOAT, + ISA_MIPS1_NOT_32R6_64R6, FGR_32; + defm D64_MM : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT, + ISA_MIPS1_NOT_32R6_64R6, FGR_64; + + defm : BC1_ALIASES<BC1T_MM, "bc1t", BC1F_MM, "bc1f">, + ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT; } //===----------------------------------------------------------------------===// diff --git a/contrib/llvm/lib/Target/Mips/MicroMipsInstrFormats.td b/contrib/llvm/lib/Target/Mips/MicroMipsInstrFormats.td index 79ef648..7749768 100644 --- a/contrib/llvm/lib/Target/Mips/MicroMipsInstrFormats.td +++ b/contrib/llvm/lib/Target/Mips/MicroMipsInstrFormats.td @@ -599,6 +599,17 @@ class SYNC_FM_MM : MMArch { let Inst{5-0} = 0x3c; } +class SYNCI_FM_MM : MMArch { + bits<5> rs; + bits<16> offset; + bits<32> Inst; + + let Inst{31-26} = 0b010000; + let Inst{25-21} = 0b10000; + let Inst{20-16} = rs; + let Inst{15-0} = offset; +} + class BRK_FM_MM : MMArch { bits<10> code_1; bits<10> code_2; @@ -755,6 +766,7 @@ class SWXC1_FM_MM<bits<9> funct> : MMArch { class CEQS_FM_MM<bits<2> fmt> : MMArch { bits<5> fs; bits<5> ft; + bits<3> fcc; bits<4> cond; bits<32> Inst; @@ -762,13 +774,17 @@ class CEQS_FM_MM<bits<2> fmt> : MMArch { let Inst{31-26} = 0x15; let Inst{25-21} = ft; let Inst{20-16} = fs; - let Inst{15-13} = 0x0; // cc + let Inst{15-13} = fcc; let Inst{12} = 0; let Inst{11-10} = fmt; let Inst{9-6} = cond; let Inst{5-0} = 0x3c; } +class C_COND_FM_MM<bits <2> fmt, bits<4> c> : CEQS_FM_MM<fmt> { + let cond = c; +} + class BC1F_FM_MM<bits<5> tf> : MMArch { bits<16> offset; @@ -1023,3 +1039,16 @@ class ADDIUPC_FM_MM { let Inst{25-23} = rs; let Inst{22-0} = imm; } + +class POOL32A_CFTC2_FM_MM<bits<10> funct> : MMArch { + bits<5> rt; + bits<5> impl; + + bits<32> Inst; + + let Inst{31-26} = 0b000000; + let Inst{25-21} = rt; + let Inst{20-16} = impl; + let Inst{15-6} = funct; + let Inst{5-0} = 0b111100; +} diff --git a/contrib/llvm/lib/Target/Mips/MicroMipsInstrInfo.td b/contrib/llvm/lib/Target/Mips/MicroMipsInstrInfo.td index f27370f..c0de9e7 100644 --- a/contrib/llvm/lib/Target/Mips/MicroMipsInstrInfo.td +++ b/contrib/llvm/lib/Target/Mips/MicroMipsInstrInfo.td @@ -194,20 +194,20 @@ class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op, let canFoldAsLoad = 1 in class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO, - Operand MemOpnd> : + Operand MemOpnd, InstrItinClass Itin> : InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src), !strconcat(opstr, "\t$rt, $addr"), [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))], - NoItinerary, FrmI> { + Itin, FrmI> { let DecoderMethod = "DecodeMemMMImm12"; string Constraints = "$src = $rt"; } class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO, - Operand MemOpnd>: + Operand MemOpnd, InstrItinClass Itin>: InstSE<(outs), (ins RO:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"), - [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> { + [(OpNode RO:$rt, addrimm12:$addr)], Itin, FrmI> { let DecoderMethod = "DecodeMemMMImm12"; } @@ -248,39 +248,37 @@ def regpair : Operand<i32> { let MIOperandInfo = (ops ptr_rc, ptr_rc); } -class StorePairMM<string opstr, InstrItinClass Itin = NoItinerary, - ComplexPattern Addr = addr> : - InstSE<(outs), (ins regpair:$rt, mem_simm12:$addr), - !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> { +class StorePairMM<string opstr, ComplexPattern Addr = addr> + : InstSE<(outs), (ins regpair:$rt, mem_simm12:$addr), + !strconcat(opstr, "\t$rt, $addr"), [], II_SWP, FrmI, opstr> { let DecoderMethod = "DecodeMemMMImm12"; let mayStore = 1; } -class LoadPairMM<string opstr, InstrItinClass Itin = NoItinerary, - ComplexPattern Addr = addr> : - InstSE<(outs regpair:$rt), (ins mem_simm12:$addr), - !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> { +class LoadPairMM<string opstr, ComplexPattern Addr = addr> + : InstSE<(outs regpair:$rt), (ins mem_simm12:$addr), + !strconcat(opstr, "\t$rt, $addr"), [], II_LWP, FrmI, opstr> { let DecoderMethod = "DecodeMemMMImm12"; let mayLoad = 1; } class LLBaseMM<string opstr, RegisterOperand RO> : InstSE<(outs RO:$rt), (ins mem_mm_12:$addr), - !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { + !strconcat(opstr, "\t$rt, $addr"), [], II_LL, FrmI> { let DecoderMethod = "DecodeMemMMImm12"; let mayLoad = 1; } class LLEBaseMM<string opstr, RegisterOperand RO> : InstSE<(outs RO:$rt), (ins mem_simm9:$addr), - !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { + !strconcat(opstr, "\t$rt, $addr"), [], II_LLE, FrmI> { let DecoderMethod = "DecodeMemMMImm9"; let mayLoad = 1; } class SCBaseMM<string opstr, RegisterOperand RO> : InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr), - !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { + !strconcat(opstr, "\t$rt, $addr"), [], II_SC, FrmI> { let DecoderMethod = "DecodeMemMMImm12"; let mayStore = 1; let Constraints = "$rt = $dst"; @@ -288,7 +286,7 @@ class SCBaseMM<string opstr, RegisterOperand RO> : class SCEBaseMM<string opstr, RegisterOperand RO> : InstSE<(outs RO:$dst), (ins RO:$rt, mem_simm9:$addr), - !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { + !strconcat(opstr, "\t$rt, $addr"), [], II_SCE, FrmI> { let DecoderMethod = "DecodeMemMMImm9"; let mayStore = 1; let Constraints = "$rt = $dst"; @@ -331,7 +329,7 @@ class LogicRMM16<string opstr, RegisterOperand RO, class NotMM16<string opstr, RegisterOperand RO> : MicroMipsInst16<(outs RO:$rt), (ins RO:$rs), !strconcat(opstr, "\t$rt, $rs"), - [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>; + [(set RO:$rt, (not RO:$rs))], II_NOT, FrmR>; class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO, InstrItinClass Itin = NoItinerary> : @@ -385,23 +383,23 @@ class LoadGPMM16<string opstr, DAGOperand RO, InstrItinClass Itin, class AddImmUR2<string opstr, RegisterOperand RO> : MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm), !strconcat(opstr, "\t$rd, $rs, $imm"), - [], NoItinerary, FrmR> { + [], II_ADDIU, FrmR> { let isCommutable = 1; } class AddImmUS5<string opstr, RegisterOperand RO> : MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm), - !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> { + !strconcat(opstr, "\t$rd, $imm"), [], II_ADDIU, FrmR> { let Constraints = "$rd = $dst"; } class AddImmUR1SP<string opstr, RegisterOperand RO> : MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm), - !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR>; + !strconcat(opstr, "\t$rd, $imm"), [], II_ADDIU, FrmR>; class AddImmUSP<string opstr> : MicroMipsInst16<(outs), (ins simm9_addiusp:$imm), - !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>; + !strconcat(opstr, "\t$imm"), [], II_ADDIU, FrmI>; class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> : MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), @@ -410,17 +408,15 @@ class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> : let hasSideEffects = 0; } -class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0, - InstrItinClass Itin = NoItinerary> : - MicroMipsInst16<(outs RO:$rd), (ins RO:$rs), - !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> { - let isCommutable = isComm; +class MoveMM16<string opstr, RegisterOperand RO> + : MicroMipsInst16<(outs RO:$rd), (ins RO:$rs), + !strconcat(opstr, "\t$rd, $rs"), [], II_MOVE, FrmR> { let isReMaterializable = 1; } class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO> : MicroMipsInst16<(outs RO:$rd), (ins Od:$imm), - !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmI> { + !strconcat(opstr, "\t$rd, $imm"), [], II_LI, FrmI> { let isReMaterializable = 1; } @@ -472,10 +468,10 @@ class JumpRegCMM16<string opstr, RegisterOperand RO> : } // Break16 and Sdbbp16 -class BrkSdbbp16MM<string opstr> : +class BrkSdbbp16MM<string opstr, InstrItinClass Itin> : MicroMipsInst16<(outs), (ins uimm4:$code_), !strconcat(opstr, "\t$code_"), - [], NoItinerary, FrmOther>; + [], Itin, FrmOther>; class CBranchZeroMM<string opstr, DAGOperand opnd, RegisterOperand RO> : MicroMipsInst16<(outs), (ins RO:$rs, opnd:$offset), @@ -505,18 +501,17 @@ let isCall = 1, hasDelaySlot = 1, Defs = [RA] in { } class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO, - InstrItinClass Itin = NoItinerary, SDPatternOperator OpNode = null_frag> : InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index), - !strconcat(opstr, "\t$rd, ${index}(${base})"), [], Itin, FrmFI>; + !strconcat(opstr, "\t$rd, ${index}(${base})"), [], II_LWXS, FrmFI>; class PrefetchIndexed<string opstr> : InstSE<(outs), (ins PtrRC:$base, PtrRC:$index, uimm5:$hint), - !strconcat(opstr, "\t$hint, ${index}(${base})"), [], NoItinerary, FrmOther>; + !strconcat(opstr, "\t$hint, ${index}(${base})"), [], II_PREF, FrmOther>; class AddImmUPC<string opstr, RegisterOperand RO> : InstSE<(outs RO:$rs), (ins simm23_lsl2:$imm), - !strconcat(opstr, "\t$rs, $imm"), [], NoItinerary, FrmR>; + !strconcat(opstr, "\t$rs, $imm"), [], II_ADDIU, FrmR>; /// A list of registers used by load/store multiple instructions. def RegListAsmOperand : AsmOperandClass { @@ -650,40 +645,50 @@ def BEQZ16_MM : CBranchZeroMM<"beqz16", brtarget7_mm, GPRMM16Opnd>, def BNEZ16_MM : CBranchZeroMM<"bnez16", brtarget7_mm, GPRMM16Opnd>, BEQNEZ_FM_MM16<0x2b>; def B16_MM : UncondBranchMM16<"b16">, B16_FM; -def BREAK16_MM : BrkSdbbp16MM<"break16">, BRKSDBBP16_FM_MM<0x28>, +def BREAK16_MM : BrkSdbbp16MM<"break16", II_BREAK>, BRKSDBBP16_FM_MM<0x28>, ISA_MICROMIPS_NOT_32R6_64R6; -def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16">, BRKSDBBP16_FM_MM<0x2C>, +def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, BRKSDBBP16_FM_MM<0x2C>, ISA_MICROMIPS_NOT_32R6_64R6; let DecoderNamespace = "MicroMips" in { /// Load and Store Instructions - multiple - def SWM16_MM : StoreMultMM16<"swm16">, LWM_FM_MM16<0x5>, + def SWM16_MM : StoreMultMM16<"swm16", II_SWM>, LWM_FM_MM16<0x5>, ISA_MICROMIPS32_NOT_MIPS32R6; - def LWM16_MM : LoadMultMM16<"lwm16">, LWM_FM_MM16<0x4>, + def LWM16_MM : LoadMultMM16<"lwm16", II_LWM>, LWM_FM_MM16<0x4>, ISA_MICROMIPS32_NOT_MIPS32R6; + let AdditionalPredicates = [InMicroMips] in { + def CFC2_MM : InstSE<(outs GPR32Opnd:$rt), (ins COP2Opnd:$impl), + "cfc2\t$rt, $impl", [], II_CFC2, FrmFR, "cfc2">, + POOL32A_CFTC2_FM_MM<0b1100110100>; + def CTC2_MM : InstSE<(outs COP2Opnd:$impl), (ins GPR32Opnd:$rt), + "ctc2\t$rt, $impl", [], II_CTC2, FrmFR, "ctc2">, + POOL32A_CFTC2_FM_MM<0b1101110100>; + } } class WaitMM<string opstr> : InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [], - NoItinerary, FrmOther, opstr>; + II_WAIT, FrmOther, opstr>; -let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { +let DecoderNamespace = "MicroMips", Predicates = [InMicroMips, NotMips32r6, + NotMips64r6] in { /// Compact Branch Instructions def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>, COMPACT_BRANCH_FM_MM<0x7>; def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>, COMPACT_BRANCH_FM_MM<0x5>; - +} +let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { /// Arithmetic Instructions (ALU Immediate) - def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>, + def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU>, ADDI_FM_MM<0xc>; - def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, + def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd, II_ADDI>, ADDI_FM_MM<0x4>; def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, SLTI_FM_MM<0x24>; def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, SLTI_FM_MM<0x2c>; - def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>, + def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI>, ADDI_FM_MM<0x34>; def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>, ADDI_FM_MM<0x14>; @@ -699,9 +704,12 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { ADD_FM_MM<0, 0x150>; def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, ADD_FM_MM<0, 0x1d0>; - def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>; - def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>; - def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>; + def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL>, + ADD_FM_MM<0, 0x210>; + def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>, + ADD_FM_MM<0, 0x110>; + def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>, + ADD_FM_MM<0, 0x190>; def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>; def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM_MM<0, 0x390>; @@ -750,60 +758,69 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { /// Load and Store Instructions - aligned let DecoderMethod = "DecodeMemMMImm16" in { - def LB_MM : LoadMemory<"lb", GPR32Opnd, mem_mm_16>, MMRel, LW_FM_MM<0x7>; - def LBu_MM : LoadMemory<"lbu", GPR32Opnd, mem_mm_16>, MMRel, LW_FM_MM<0x5>; + def LB_MM : LoadMemory<"lb", GPR32Opnd, mem_mm_16, null_frag, II_LB>, + MMRel, LW_FM_MM<0x7>; + def LBu_MM : LoadMemory<"lbu", GPR32Opnd, mem_mm_16, null_frag, II_LBU>, + MMRel, LW_FM_MM<0x5>; def LH_MM : LoadMemory<"lh", GPR32Opnd, mem_simm16, sextloadi16, II_LH, addrDefault>, MMRel, LW_FM_MM<0xf>; def LHu_MM : LoadMemory<"lhu", GPR32Opnd, mem_simm16, zextloadi16, II_LHU>, MMRel, LW_FM_MM<0xd>; - def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>; - def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>; - def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>; - def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>; + def LW_MM : Load<"lw", GPR32Opnd, null_frag, II_LW>, MMRel, LW_FM_MM<0x3f>; + def SB_MM : Store<"sb", GPR32Opnd, null_frag, II_SB>, MMRel, + LW_FM_MM<0x6>; + def SH_MM : Store<"sh", GPR32Opnd, null_frag, II_SH>, MMRel, + LW_FM_MM<0xe>; + def SW_MM : Store<"sw", GPR32Opnd, null_frag, II_SW>, MMRel, + LW_FM_MM<0x3e>; } let DecoderMethod = "DecodeMemMMImm9" in { - def LBE_MM : Load<"lbe", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>; - def LBuE_MM : Load<"lbue", GPR32Opnd>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>; - def LHE_MM : LoadMemory<"lhe", GPR32Opnd, mem_simm9>, + def LBE_MM : Load<"lbe", GPR32Opnd, null_frag, II_LBE>, + POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>; + def LBuE_MM : Load<"lbue", GPR32Opnd, null_frag, II_LBUE>, + POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>; + def LHE_MM : LoadMemory<"lhe", GPR32Opnd, mem_simm9, null_frag, II_LHE>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x5>; - def LHuE_MM : LoadMemory<"lhue", GPR32Opnd, mem_simm9>, + def LHuE_MM : LoadMemory<"lhue", GPR32Opnd, mem_simm9, null_frag, II_LHUE>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x1>; - def LWE_MM : LoadMemory<"lwe", GPR32Opnd, mem_simm9>, + def LWE_MM : LoadMemory<"lwe", GPR32Opnd, mem_simm9, null_frag, II_LWE>, POOL32C_LHUE_FM_MM<0x18, 0x6, 0x7>; - def SBE_MM : StoreMemory<"sbe", GPR32Opnd, mem_simm9>, + def SBE_MM : StoreMemory<"sbe", GPR32Opnd, mem_simm9, null_frag, II_SBE>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x4>; - def SHE_MM : StoreMemory<"she", GPR32Opnd, mem_simm9>, + def SHE_MM : StoreMemory<"she", GPR32Opnd, mem_simm9, null_frag, II_SHE>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x5>; - def SWE_MM : StoreMemory<"swe", GPR32Opnd, mem_simm9>, + def SWE_MM : StoreMemory<"swe", GPR32Opnd, mem_simm9, null_frag, II_SWE>, POOL32C_LHUE_FM_MM<0x18, 0xa, 0x7>; } def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>; /// Load and Store Instructions - unaligned - def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>, + def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12, II_LWL>, LWL_FM_MM<0x0>; - def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>, + def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12, II_LWR>, LWL_FM_MM<0x1>; - def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>, + def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12, II_SWL>, LWL_FM_MM<0x8>; - def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>, + def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12, II_SWR>, LWL_FM_MM<0x9>; let DecoderMethod = "DecodeMemMMImm9" in { - def LWLE_MM : LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_9>, - POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>; - def LWRE_MM : LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_9>, - POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>; - def SWLE_MM : StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_9>, + def LWLE_MM : LoadLeftRightMM<"lwle", MipsLWL, GPR32Opnd, mem_mm_9, + II_LWLE>, POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x2>; + def LWRE_MM : LoadLeftRightMM<"lwre", MipsLWR, GPR32Opnd, mem_mm_9, + II_LWRE>, POOL32C_STEVA_LDEVA_FM_MM<0x6, 0x3>; + def SWLE_MM : StoreLeftRightMM<"swle", MipsSWL, GPR32Opnd, mem_mm_9, + II_SWLE>, POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x0>; - def SWRE_MM : StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_9>, + def SWRE_MM : StoreLeftRightMM<"swre", MipsSWR, GPR32Opnd, mem_mm_9, + II_SWRE>, POOL32C_STEVA_LDEVA_FM_MM<0xa, 0x1>, ISA_MIPS1_NOT_32R6_64R6; } /// Load and Store Instructions - multiple - def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>; - def LWM32_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>; + def SWM32_MM : StoreMultMM<"swm32", II_SWM>, LWM_FM_MM<0xd>; + def LWM32_MM : LoadMultMM<"lwm32", II_LWM>, LWM_FM_MM<0x5>; /// Load and Store Pair Instructions def SWP_MM : StorePairMM<"swp">, LWM_FM_MM<0x9>; @@ -849,9 +866,9 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>; /// Count Leading - def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>, + def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM_MM<0x16c>, ISA_MIPS32; - def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>, + def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM_MM<0x12c>, ISA_MIPS32; /// Sign Ext In Register Instructions. @@ -910,30 +927,35 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { /// Control Instructions def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM; + def SYNCI_MM : MMRel, SYNCI_FT<"synci">, SYNCI_FM_MM; def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM; - def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10>, SYS_FM_MM; + def SYSCALL_MM : MMRel, SYS_FT<"syscall", uimm10, II_SYSCALL>, SYS_FM_MM; def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM; - def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>; - def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>; - def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>, + def ERET_MM : MMRel, ER_FT<"eret", II_ERET>, ER_FM_MM<0x3cd>; + def DERET_MM : MMRel, ER_FT<"deret", II_DERET>, ER_FM_MM<0x38d>; + def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd, II_EI>, EI_FM_MM<0x15d>, ISA_MIPS32R2; - def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>, + def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd, II_DI>, EI_FM_MM<0x11d>, ISA_MIPS32R2; /// Trap Instructions - def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm4>, TEQ_FM_MM<0x0>; - def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm4>, TEQ_FM_MM<0x08>; - def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm4>, TEQ_FM_MM<0x10>; - def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm4>, TEQ_FM_MM<0x20>; - def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm4>, TEQ_FM_MM<0x28>; - def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm4>, TEQ_FM_MM<0x30>; - - def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>; - def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>; - def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>; - def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>; - def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>; - def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>; + def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm4, II_TEQ>, TEQ_FM_MM<0x0>; + def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd, uimm4, II_TGE>, TEQ_FM_MM<0x08>; + def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd, uimm4, II_TGEU>, + TEQ_FM_MM<0x10>; + def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd, uimm4, II_TLT>, TEQ_FM_MM<0x20>; + def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd, uimm4, II_TLTU>, + TEQ_FM_MM<0x28>; + def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd, uimm4, II_TNE>, TEQ_FM_MM<0x30>; + + def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd, II_TEQI>, TEQI_FM_MM<0x0e>; + def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd, II_TGEI>, TEQI_FM_MM<0x09>; + def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd, II_TGEIU>, + TEQI_FM_MM<0x0b>; + def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd, II_TLTI>, TEQI_FM_MM<0x08>; + def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd, II_TTLTIU>, + TEQI_FM_MM<0x0a>; + def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd, II_TNEI>, TEQI_FM_MM<0x0c>; /// Load-linked, Store-conditional def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>; @@ -943,32 +965,34 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { def SCE_MM : SCEBaseMM<"sce", GPR32Opnd>, LLE_FM_MM<0xA>; let DecoderMethod = "DecodeCacheOpMM" in { - def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12>, + def CACHE_MM : MMRel, CacheOp<"cache", mem_mm_12, II_CACHE>, CACHE_PREF_FM_MM<0x08, 0x6>; - def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12>, + def PREF_MM : MMRel, CacheOp<"pref", mem_mm_12, II_PREF>, CACHE_PREF_FM_MM<0x18, 0x2>; } let DecoderMethod = "DecodePrefeOpMM" in { - def PREFE_MM : MMRel, CacheOp<"prefe", mem_mm_9>, + def PREFE_MM : MMRel, CacheOp<"prefe", mem_mm_9, II_PREFE>, CACHE_PREFE_FM_MM<0x18, 0x2>; - def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9>, + def CACHEE_MM : MMRel, CacheOp<"cachee", mem_mm_9, II_CACHEE>, CACHE_PREFE_FM_MM<0x18, 0x3>; } - def SSNOP_MM : MMRel, Barrier<"ssnop">, BARRIER_FM_MM<0x1>; - def EHB_MM : MMRel, Barrier<"ehb">, BARRIER_FM_MM<0x3>; - def PAUSE_MM : MMRel, Barrier<"pause">, BARRIER_FM_MM<0x5>; + def SSNOP_MM : MMRel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM_MM<0x1>; + def EHB_MM : MMRel, Barrier<"ehb", II_EHB>, BARRIER_FM_MM<0x3>; + def PAUSE_MM : MMRel, Barrier<"pause", II_PAUSE>, BARRIER_FM_MM<0x5>; - def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>; - def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>; - def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>; - def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>; + def TLBP_MM : MMRel, TLB<"tlbp", II_TLBP>, COP0_TLB_FM_MM<0x0d>; + def TLBR_MM : MMRel, TLB<"tlbr", II_TLBR>, COP0_TLB_FM_MM<0x4d>; + def TLBWI_MM : MMRel, TLB<"tlbwi", II_TLBWI>, COP0_TLB_FM_MM<0x8d>; + def TLBWR_MM : MMRel, TLB<"tlbwr", II_TLBWR>, COP0_TLB_FM_MM<0xcd>; - def SDBBP_MM : MMRel, SYS_FT<"sdbbp", uimm10>, SDBBP_FM_MM; + def SDBBP_MM : MMRel, SYS_FT<"sdbbp", uimm10, II_SDBBP>, SDBBP_FM_MM; def PREFX_MM : PrefetchIndexed<"prefx">, POOL32F_PREFX_FM_MM<0x15, 0x1A0>; } +def TAILCALL_MM : TailCall<J_MM, jmptarget_mm>, ISA_MIPS1_NOT_32R6_64R6; + let DecoderNamespace = "MicroMips" in { def RDHWR_MM : MMRel, R6MMR6Rel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM_MM, ISA_MICROMIPS32_NOT_MIPS32R6; @@ -981,6 +1005,12 @@ let DecoderNamespace = "MicroMips" in { // MicroMips arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// +def : MipsPat<(i32 immLi16:$imm), + (LI16_MM immLi16:$imm)>; + +let AdditionalPredicates = [InMicroMips] in +defm : MaterializeImms<i32, ZERO, ADDiu_MM, LUi_MM, ORi_MM>; + let Predicates = [InMicroMips] in { def : MipsPat<(i32 immLi16:$imm), (LI16_MM immLi16:$imm)>; @@ -1036,6 +1066,11 @@ let Predicates = [InMicroMips] in { (LW_MM addr:$addr)>; def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), (SUBu_MM GPR32:$lhs, GPR32:$rhs)>; + + def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), + (TAILCALL_MM tglobaladdr:$dst)>, ISA_MIPS1_NOT_32R6_64R6; + def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), + (TAILCALL_MM texternalsym:$dst)>, ISA_MIPS1_NOT_32R6_64R6; } let AddedComplexity = 40 in { @@ -1047,6 +1082,15 @@ def : MipsPat<(atomic_load_16 addr:$a), def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_MM addr:$src)>; +defm : BrcondPats<GPR32, BEQ_MM, BEQ_MM, BNE_MM, SLT_MM, SLTu_MM, SLTi_MM, + SLTiu_MM, ZERO>; + +defm : SeteqPats<GPR32, SLTiu_MM, XOR_MM, SLTu_MM, ZERO>; +defm : SetlePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>; +defm : SetgtPats<GPR32, SLT_MM, SLTu_MM>; +defm : SetgePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>; +defm : SetgeImmPats<GPR32, XORi_MM, SLTi_MM, SLTiu_MM>; + //===----------------------------------------------------------------------===// // MicroMips instruction aliases //===----------------------------------------------------------------------===// @@ -1080,6 +1124,24 @@ let Predicates = [InMicroMips] in { (TLTU_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; def : MipsInstAlias<"tne $rs, $rt", (TNE_MM GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>; + def : MipsInstAlias< + "sgt $rd, $rs, $rt", + (SLT_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; + def : MipsInstAlias< + "sgt $rs, $rt", + (SLT_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; + def : MipsInstAlias< + "sgtu $rd, $rs, $rt", + (SLTu_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; + def : MipsInstAlias< + "sgtu $rs, $rt", + (SLTu_MM GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; + def : MipsInstAlias<"slt $rs, $rt, $imm", + (SLTi_MM GPR32Opnd:$rs, GPR32Opnd:$rt, + simm32_relaxed:$imm), 0>; + def : MipsInstAlias<"sltu $rs, $rt, $imm", + (SLTiu_MM GPR32Opnd:$rs, GPR32Opnd:$rt, + simm32_relaxed:$imm), 0>; def : MipsInstAlias<"sll $rd, $rt, $rs", (SLLV_MM GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; def : MipsInstAlias<"sra $rd, $rt, $rs", @@ -1115,4 +1177,14 @@ let Predicates = [InMicroMips] in { (XORi_MM GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>; def : MipsInstAlias<"not $rt, $rs", (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; + def : MipsInstAlias<"not $rt", + (NOR_MM GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>; + def : MipsInstAlias<"bnez $rs,$offset", + (BNE_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; + def : MipsInstAlias<"beqz $rs,$offset", + (BEQ_MM GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>; + def : MipsInstAlias<"seh $rd", (SEH_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, + ISA_MIPS32R2_NOT_32R6_64R6; + def : MipsInstAlias<"seb $rd", (SEB_MM GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, + ISA_MIPS32R2_NOT_32R6_64R6; } diff --git a/contrib/llvm/lib/Target/Mips/Mips.td b/contrib/llvm/lib/Target/Mips/Mips.td index ea3fa0a..670272d 100644 --- a/contrib/llvm/lib/Target/Mips/Mips.td +++ b/contrib/llvm/lib/Target/Mips/Mips.td @@ -57,6 +57,10 @@ include "MipsSchedule.td" include "MipsInstrInfo.td" include "MipsCallingConv.td" +// Avoid forward declaration issues. +include "MipsScheduleP5600.td" +include "MipsScheduleGeneric.td" + def MipsInstrInfo : InstrInfo; //===----------------------------------------------------------------------===// @@ -188,7 +192,7 @@ def ImplP5600 : SubtargetFeature<"p5600", "ProcImpl", "The P5600 Processor", [FeatureMips32r5]>; class Proc<string Name, list<SubtargetFeature> Features> - : Processor<Name, MipsGenericItineraries, Features>; + : ProcessorModel<Name, MipsGenericModel, Features>; def : Proc<"mips1", [FeatureMips1]>; def : Proc<"mips2", [FeatureMips2]>; diff --git a/contrib/llvm/lib/Target/Mips/Mips16FrameLowering.cpp b/contrib/llvm/lib/Target/Mips/Mips16FrameLowering.cpp index e937ffa..e7ceca9 100644 --- a/contrib/llvm/lib/Target/Mips/Mips16FrameLowering.cpp +++ b/contrib/llvm/lib/Target/Mips/Mips16FrameLowering.cpp @@ -34,7 +34,7 @@ Mips16FrameLowering::Mips16FrameLowering(const MipsSubtarget &STI) void Mips16FrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const { assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported"); - MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineFrameInfo &MFI = MF.getFrameInfo(); const Mips16InstrInfo &TII = *static_cast<const Mips16InstrInfo *>(STI.getInstrInfo()); MachineBasicBlock::iterator MBBI = MBB.begin(); @@ -43,10 +43,10 @@ void Mips16FrameLowering::emitPrologue(MachineFunction &MF, // to determine the end of the prologue. DebugLoc dl; - uint64_t StackSize = MFI->getStackSize(); + uint64_t StackSize = MFI.getStackSize(); // No need to allocate space on the stack. - if (StackSize == 0 && !MFI->adjustsStack()) return; + if (StackSize == 0 && !MFI.adjustsStack()) return; MachineModuleInfo &MMI = MF.getMMI(); const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); @@ -56,22 +56,22 @@ void Mips16FrameLowering::emitPrologue(MachineFunction &MF, TII.makeFrame(Mips::SP, StackSize, MBB, MBBI); // emit ".cfi_def_cfa_offset StackSize" - unsigned CFIIndex = MMI.addFrameInst( + unsigned CFIIndex = MF.addFrameInst( MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); - const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); + const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); if (CSI.size()) { - const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); + const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(), E = CSI.end(); I != E; ++I) { - int64_t Offset = MFI->getObjectOffset(I->getFrameIdx()); + int64_t Offset = MFI.getObjectOffset(I->getFrameIdx()); unsigned Reg = I->getReg(); unsigned DReg = MRI->getDwarfRegNum(Reg, true); - unsigned CFIIndex = MMI.addFrameInst( + unsigned CFIIndex = MF.addFrameInst( MCCFIInstruction::createOffset(nullptr, DReg, Offset)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); @@ -86,11 +86,11 @@ void Mips16FrameLowering::emitPrologue(MachineFunction &MF, void Mips16FrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); - MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineFrameInfo &MFI = MF.getFrameInfo(); const Mips16InstrInfo &TII = *static_cast<const Mips16InstrInfo *>(STI.getInstrInfo()); DebugLoc dl = MBBI->getDebugLoc(); - uint64_t StackSize = MFI->getStackSize(); + uint64_t StackSize = MFI.getStackSize(); if (!StackSize) return; @@ -120,12 +120,12 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB, for (unsigned i = 0, e = CSI.size(); i != e; ++i) { // Add the callee-saved register as live-in. Do not add if the register is // RA and return address is taken, because it has already been added in - // method MipsTargetLowering::LowerRETURNADDR. + // method MipsTargetLowering::lowerRETURNADDR. // It's killed at the spill, unless the register is RA and return address // is taken. unsigned Reg = CSI[i].getReg(); bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA) - && MF->getFrameInfo()->isReturnAddressTaken(); + && MF->getFrameInfo().isReturnAddressTaken(); if (!IsRAAndRetAddrIsTaken) EntryBlock->addLiveIn(Reg); } @@ -149,10 +149,10 @@ bool Mips16FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, bool Mips16FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); + const MachineFrameInfo &MFI = MF.getFrameInfo(); // Reserve call frame if the size of the maximum call frame fits into 15-bit // immediate field and there are no variable sized objects on the stack. - return isInt<15>(MFI->getMaxCallFrameSize()) && !MFI->hasVarSizedObjects(); + return isInt<15>(MFI.getMaxCallFrameSize()) && !MFI.hasVarSizedObjects(); } void Mips16FrameLowering::determineCalleeSaves(MachineFunction &MF, diff --git a/contrib/llvm/lib/Target/Mips/Mips16HardFloat.cpp b/contrib/llvm/lib/Target/Mips/Mips16HardFloat.cpp index d2d1c65..191006d 100644 --- a/contrib/llvm/lib/Target/Mips/Mips16HardFloat.cpp +++ b/contrib/llvm/lib/Target/Mips/Mips16HardFloat.cpp @@ -30,9 +30,7 @@ namespace { Mips16HardFloat(MipsTargetMachine &TM_) : ModulePass(ID), TM(TM_) {} - const char *getPassName() const override { - return "MIPS16 Hard Float Pass"; - } + StringRef getPassName() const override { return "MIPS16 Hard Float Pass"; } bool runOnModule(Module &M) override; diff --git a/contrib/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp b/contrib/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp index 0405291..ce193b1 100644 --- a/contrib/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp +++ b/contrib/llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp @@ -80,9 +80,10 @@ void Mips16DAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) { V1 = RegInfo.createVirtualRegister(RC); V2 = RegInfo.createVirtualRegister(RC); - BuildMI(MBB, I, DL, TII.get(Mips::GotPrologue16), V0) - .addReg(V1, RegState::Define) - .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI) + + BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0) + .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI); + BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1) .addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO); BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16); diff --git a/contrib/llvm/lib/Target/Mips/Mips16InstrInfo.cpp b/contrib/llvm/lib/Target/Mips/Mips16InstrInfo.cpp index daa1355..35ef317 100644 --- a/contrib/llvm/lib/Target/Mips/Mips16InstrInfo.cpp +++ b/contrib/llvm/lib/Target/Mips/Mips16InstrInfo.cpp @@ -172,7 +172,7 @@ static void addSaveRestoreRegs(MachineInstrBuilder &MIB, for (unsigned i = 0, e = CSI.size(); i != e; ++i) { // Add the callee-saved register as live-in. Do not add if the register is // RA and return address is taken, because it has already been added in - // method MipsTargetLowering::LowerRETURNADDR. + // method MipsTargetLowering::lowerRETURNADDR. // It's killed at the spill, unless the register is RA and return address // is taken. unsigned Reg = CSI[e-i-1].getReg(); @@ -196,13 +196,13 @@ void Mips16InstrInfo::makeFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock::iterator I) const { DebugLoc DL; MachineFunction &MF = *MBB.getParent(); - MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineFrameInfo &MFI = MF.getFrameInfo(); const BitVector Reserved = RI.getReservedRegs(MF); bool SaveS2 = Reserved[Mips::S2]; MachineInstrBuilder MIB; unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16; MIB = BuildMI(MBB, I, DL, get(Opc)); - const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); + const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); addSaveRestoreRegs(MIB, CSI); if (SaveS2) MIB.addReg(Mips::S2); @@ -226,7 +226,7 @@ void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize, MachineBasicBlock::iterator I) const { DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); MachineFunction *MF = MBB.getParent(); - MachineFrameInfo *MFI = MF->getFrameInfo(); + MachineFrameInfo &MFI = MF->getFrameInfo(); const BitVector Reserved = RI.getReservedRegs(*MF); bool SaveS2 = Reserved[Mips::S2]; MachineInstrBuilder MIB; @@ -245,7 +245,7 @@ void Mips16InstrInfo::restoreFrame(unsigned SP, int64_t FrameSize, adjustStackPtrBig(SP, Remainder, MBB, I, Mips::A0, Mips::A1); } MIB = BuildMI(MBB, I, DL, get(Opc)); - const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); + const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); addSaveRestoreRegs(MIB, CSI, RegState::Define); if (SaveS2) MIB.addReg(Mips::S2, RegState::Define); @@ -510,8 +510,8 @@ unsigned Mips16InstrInfo::getInlineAsmLength(const char *Str, Length += MAI.getMaxInstLength(); atInsnStart = false; } - if (atInsnStart && strncmp(Str, MAI.getCommentString(), - strlen(MAI.getCommentString())) == 0) + if (atInsnStart && strncmp(Str, MAI.getCommentString().data(), + MAI.getCommentString().size()) == 0) atInsnStart = false; } diff --git a/contrib/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp b/contrib/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp index b034c26..44771cb 100644 --- a/contrib/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp +++ b/contrib/llvm/lib/Target/Mips/Mips16RegisterInfo.cpp @@ -79,9 +79,9 @@ void Mips16RegisterInfo::eliminateFI(MachineBasicBlock::iterator II, int64_t SPOffset) const { MachineInstr &MI = *II; MachineFunction &MF = *MI.getParent()->getParent(); - MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineFrameInfo &MFI = MF.getFrameInfo(); - const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); + const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); int MinCSFI = 0; int MaxCSFI = -1; diff --git a/contrib/llvm/lib/Target/Mips/Mips32r6InstrFormats.td b/contrib/llvm/lib/Target/Mips/Mips32r6InstrFormats.td index a20c683..516caa3 100644 --- a/contrib/llvm/lib/Target/Mips/Mips32r6InstrFormats.td +++ b/contrib/llvm/lib/Target/Mips/Mips32r6InstrFormats.td @@ -45,6 +45,7 @@ class MipsR6Inst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, class OPGROUP<bits<6> Val> { bits<6> Value = Val; } +def OPGROUP_COP0 : OPGROUP<0b010000>; def OPGROUP_COP1 : OPGROUP<0b010001>; def OPGROUP_COP2 : OPGROUP<0b010010>; def OPGROUP_ADDI : OPGROUP<0b001000>; @@ -201,6 +202,21 @@ class BAL_FM : MipsR6Inst { let Inst{15-0} = offset; } +class COP0_EVP_DVP_FM<bits<1> sc> : MipsR6Inst { + bits<5> rt; + + bits<32> Inst; + + let Inst{31-26} = OPGROUP_COP0.Value; + let Inst{25-21} = 0b01011; + let Inst{20-16} = rt; + let Inst{15-11} = 0b00000; + let Inst{10-6} = 0b00000; + let Inst{5} = sc; + let Inst{4-3} = 0b00; + let Inst{2-0} = 0b100; +} + class COP1_2R_FM<bits<6> funct, FIELD_FMT Format> : MipsR6Inst { bits<5> fs; bits<5> fd; diff --git a/contrib/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/contrib/llvm/lib/Target/Mips/Mips32r6InstrInfo.td index f552f8d..1b4d73b 100644 --- a/contrib/llvm/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/contrib/llvm/lib/Target/Mips/Mips32r6InstrInfo.td @@ -98,6 +98,9 @@ class BC1NEZ_ENC : COP1_BCCZ_FM<OPCODE5_BC1NEZ>; class BC2EQZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2EQZ>; class BC2NEZ_ENC : COP2_BCCZ_FM<OPCODE5_BC2NEZ>; +class DVP_ENC : COP0_EVP_DVP_FM<0b1>; +class EVP_ENC : COP0_EVP_DVP_FM<0b0>; + class JIALC_ENC : JMP_IDX_COMPACT_FM<0b111110>; class JIC_ENC : JMP_IDX_COMPACT_FM<0b110110>; class JR_HB_R6_ENC : JR_HB_R6_FM<OPCODE6_JALR>; @@ -177,90 +180,98 @@ class SDBBP_R6_ENC : SPECIAL_SDBBP_FM; class CMP_CONDN_DESC_BASE<string CondStr, string Typestr, RegisterOperand FGROpnd, + InstrItinClass Itin, SDPatternOperator Op = null_frag> { dag OutOperandList = (outs FGRCCOpnd:$fd); dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft); string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft"); list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))]; bit isCTI = 1; + InstrItinClass Itinerary = Itin; } multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr, - RegisterOperand FGROpnd>{ + RegisterOperand FGROpnd, InstrItinClass Itin>{ let AdditionalPredicates = [NotInMicroMips] in { def CMP_F_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_AF>, - CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, + CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd, Itin>, MipsR6Arch<!strconcat("cmp.af.", Typestr)>, ISA_MIPS32R6, HARDFLOAT; def CMP_UN_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>, - CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, setuo>, + CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, Itin, setuo>, MipsR6Arch<!strconcat("cmp.un.", Typestr)>, ISA_MIPS32R6, HARDFLOAT; def CMP_EQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>, - CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, setoeq>, + CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, Itin, + setoeq>, MipsR6Arch<!strconcat("cmp.eq.", Typestr)>, ISA_MIPS32R6, HARDFLOAT; def CMP_UEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UEQ>, - CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, setueq>, + CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, Itin, + setueq>, MipsR6Arch<!strconcat("cmp.ueq.", Typestr)>, ISA_MIPS32R6, HARDFLOAT; def CMP_LT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>, - CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, setolt>, + CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, Itin, + setolt>, MipsR6Arch<!strconcat("cmp.lt.", Typestr)>, ISA_MIPS32R6, HARDFLOAT; def CMP_ULT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULT>, - CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, setult>, + CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, Itin, + setult>, MipsR6Arch<!strconcat("cmp.ult.", Typestr)>, ISA_MIPS32R6, HARDFLOAT; def CMP_LE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>, - CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, setole>, + CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, Itin, + setole>, MipsR6Arch<!strconcat("cmp.le.", Typestr)>, ISA_MIPS32R6, HARDFLOAT; def CMP_ULE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_ULE>, - CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, setule>, + CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, Itin, + setule>, MipsR6Arch<!strconcat("cmp.ule.", Typestr)>, ISA_MIPS32R6, HARDFLOAT; def CMP_SAF_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SAF>, - CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, + CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd, Itin>, MipsR6Arch<!strconcat("cmp.saf.", Typestr)>, ISA_MIPS32R6, HARDFLOAT; def CMP_SUN_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SUN>, - CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, + CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd, Itin>, MipsR6Arch<!strconcat("cmp.sun.", Typestr)>, ISA_MIPS32R6, HARDFLOAT; def CMP_SEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SEQ>, - CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, + CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd, Itin>, MipsR6Arch<!strconcat("cmp.seq.", Typestr)>, ISA_MIPS32R6, HARDFLOAT; def CMP_SUEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SUEQ>, - CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, + CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd, Itin>, MipsR6Arch<!strconcat("cmp.sueq.", Typestr)>, ISA_MIPS32R6, HARDFLOAT; def CMP_SLT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SLT>, - CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, + CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd, Itin>, MipsR6Arch<!strconcat("cmp.slt.", Typestr)>, ISA_MIPS32R6, HARDFLOAT; def CMP_SULT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SULT>, - CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, + CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd, Itin>, MipsR6Arch<!strconcat("cmp.sult.", Typestr)>, ISA_MIPS32R6, HARDFLOAT; def CMP_SLE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SLE>, - CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, + CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd, Itin>, MipsR6Arch<!strconcat("cmp.sle.", Typestr)>, ISA_MIPS32R6, HARDFLOAT; def CMP_SULE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_SULE>, - CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, + CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd, Itin>, MipsR6Arch<!strconcat("cmp.sule.", Typestr)>, ISA_MIPS32R6, HARDFLOAT; } @@ -316,7 +327,7 @@ class AUI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, InstrItinClass itin = NoItinerary> : MipsR6Arch<instr_asm> { dag OutOperandList = (outs GPROpnd:$rs); - dag InOperandList = (ins GPROpnd:$rt, simm16:$imm); + dag InOperandList = (ins GPROpnd:$rt, uimm16:$imm); string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm"); list<dag> Pattern = []; InstrItinClass Itinerary = itin; @@ -426,6 +437,7 @@ class COP2_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE { string AsmString = instr_asm; bit hasDelaySlot = 1; bit isCTI = 1; + InstrItinClass Itinerary = II_BC2CCZ; } class BC2EQZ_DESC : COP2_BCCZ_DESC_BASE<"bc2eqz $ct, $offset">; @@ -468,6 +480,7 @@ class JR_HB_R6_DESC : JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> { bit isTerminator=1; bit isBarrier=1; bit isCTI = 1; + InstrItinClass Itinerary = II_JR_HB; } class BITSWAP_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, @@ -496,6 +509,19 @@ class DIVMOD_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, bit usesCustomInserter = 1; } +class DVPEVP_DESC_BASE<string instr_asm, InstrItinClass Itin> + : MipsR6Arch<instr_asm> { + dag OutOperandList = (outs GPR32Opnd:$rt); + dag InOperandList = (ins); + string AsmString = !strconcat(instr_asm, "\t$rt"); + list<dag> Pattern = []; + InstrItinClass Itinerary = Itin; + bit hasUnModeledSideEffects = 1; +} + +class DVP_DESC : DVPEVP_DESC_BASE<"dvp", II_DVP>; +class EVP_DESC : DVPEVP_DESC_BASE<"evp", II_EVP>; + class DIV_DESC : DIVMOD_DESC_BASE<"div", GPR32Opnd, II_DIV, sdiv>; class DIVU_DESC : DIVMOD_DESC_BASE<"divu", GPR32Opnd, II_DIVU, udiv>; class MOD_DESC : DIVMOD_DESC_BASE<"mod", GPR32Opnd, II_MOD, srem>; @@ -540,7 +566,8 @@ class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd, II_MUHU, mulhu>; class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, II_MUL, mul>; class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd, II_MULU>; -class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { +class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd, + InstrItinClass itin> { dag OutOperandList = (outs FGROpnd:$fd); dag InOperandList = (ins FGRCCOpnd:$fd_in, FGROpnd:$fs, FGROpnd:$ft); string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); @@ -548,13 +575,16 @@ class COP1_SEL_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { FGROpnd:$ft, FGROpnd:$fs))]; string Constraints = "$fd_in = $fd"; + InstrItinClass Itinerary = itin; } -class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd>, MipsR6Arch<"sel.d"> { +class SEL_D_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd, II_SEL_D>, + MipsR6Arch<"sel.d"> { // We must insert a SUBREG_TO_REG around $fd_in bit usesCustomInserter = 1; } -class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>, MipsR6Arch<"sel.s">; +class SEL_S_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, II_SEL_S>, + MipsR6Arch<"sel.s">; class SELEQNE_Z_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> : MipsR6Arch<instr_asm> { @@ -583,86 +613,98 @@ class MADDF_D_DESC : COP1_4R_DESC_BASE<"maddf.d", FGR64Opnd, II_MADDF_D>; class MSUBF_S_DESC : COP1_4R_DESC_BASE<"msubf.s", FGR32Opnd, II_MSUBF_S>; class MSUBF_D_DESC : COP1_4R_DESC_BASE<"msubf.d", FGR64Opnd, II_MSUBF_D>; -class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { +class MAX_MIN_DESC_BASE<string instr_asm, RegisterOperand FGROpnd, + InstrItinClass itin> { dag OutOperandList = (outs FGROpnd:$fd); dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft); string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); list<dag> Pattern = []; + InstrItinClass Itinerary = itin; } -class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd>; -class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd>; -class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd>; -class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd>; +class MAX_S_DESC : MAX_MIN_DESC_BASE<"max.s", FGR32Opnd, II_MAX_S>; +class MAX_D_DESC : MAX_MIN_DESC_BASE<"max.d", FGR64Opnd, II_MAX_D>; +class MIN_S_DESC : MAX_MIN_DESC_BASE<"min.s", FGR32Opnd, II_MIN_S>; +class MIN_D_DESC : MAX_MIN_DESC_BASE<"min.d", FGR64Opnd, II_MIN_D>; -class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd>; -class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd>; -class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd>; -class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd>; +class MAXA_S_DESC : MAX_MIN_DESC_BASE<"maxa.s", FGR32Opnd, II_MAX_S>; +class MAXA_D_DESC : MAX_MIN_DESC_BASE<"maxa.d", FGR64Opnd, II_MAX_D>; +class MINA_S_DESC : MAX_MIN_DESC_BASE<"mina.s", FGR32Opnd, II_MIN_D>; +class MINA_D_DESC : MAX_MIN_DESC_BASE<"mina.d", FGR64Opnd, II_MIN_S>; -class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { +class SELEQNEZ_DESC_BASE<string instr_asm, RegisterOperand FGROpnd, + InstrItinClass itin> { dag OutOperandList = (outs FGROpnd:$fd); dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft); string AsmString = !strconcat(instr_asm, "\t$fd, $fs, $ft"); list<dag> Pattern = []; + InstrItinClass Itinerary = itin; } -class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>, +class SELEQZ_S_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd, II_SELCCZ_S>, MipsR6Arch<"seleqz.s">; -class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>, +class SELEQZ_D_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd, II_SELCCZ_D>, MipsR6Arch<"seleqz.d">; -class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd>, +class SELNEZ_S_DESC : SELEQNEZ_DESC_BASE<"selnez.s", FGR32Opnd, II_SELCCZ_S>, MipsR6Arch<"selnez.s">; -class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd>, +class SELNEZ_D_DESC : SELEQNEZ_DESC_BASE<"selnez.d", FGR64Opnd, II_SELCCZ_D>, MipsR6Arch<"selnez.d">; -class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd> { +class CLASS_RINT_DESC_BASE<string instr_asm, RegisterOperand FGROpnd, + InstrItinClass itin> { dag OutOperandList = (outs FGROpnd:$fd); dag InOperandList = (ins FGROpnd:$fs); string AsmString = !strconcat(instr_asm, "\t$fd, $fs"); list<dag> Pattern = []; + InstrItinClass Itinerary = itin; } -class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd>; -class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd>; -class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd>; -class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd>; +class RINT_S_DESC : CLASS_RINT_DESC_BASE<"rint.s", FGR32Opnd, II_RINT_S>; +class RINT_D_DESC : CLASS_RINT_DESC_BASE<"rint.d", FGR64Opnd, II_RINT_D>; +class CLASS_S_DESC : CLASS_RINT_DESC_BASE<"class.s", FGR32Opnd, II_CLASS_S>; +class CLASS_D_DESC : CLASS_RINT_DESC_BASE<"class.d", FGR64Opnd, II_CLASS_D>; class CACHE_HINT_DESC<string instr_asm, Operand MemOpnd, - RegisterOperand GPROpnd> : MipsR6Arch<instr_asm> { + RegisterOperand GPROpnd, InstrItinClass itin> + : MipsR6Arch<instr_asm> { dag OutOperandList = (outs); dag InOperandList = (ins MemOpnd:$addr, uimm5:$hint); string AsmString = !strconcat(instr_asm, "\t$hint, $addr"); list<dag> Pattern = []; string DecoderMethod = "DecodeCacheeOp_CacheOpR6"; + InstrItinClass Itinerary = itin; } -class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd>; -class PREF_DESC : CACHE_HINT_DESC<"pref", mem_simm9, GPR32Opnd>; +class CACHE_DESC : CACHE_HINT_DESC<"cache", mem_simm9, GPR32Opnd, II_CACHE>; +class PREF_DESC : CACHE_HINT_DESC<"pref", mem_simm9, GPR32Opnd, II_PREF>; -class COP2LD_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> { +class COP2LD_DESC_BASE<string instr_asm, RegisterOperand COPOpnd, + InstrItinClass itin> { dag OutOperandList = (outs COPOpnd:$rt); dag InOperandList = (ins mem_simm11:$addr); string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); list<dag> Pattern = []; bit mayLoad = 1; string DecoderMethod = "DecodeFMemCop2R6"; + InstrItinClass Itinerary = itin; } -class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd>; -class LWC2_R6_DESC : COP2LD_DESC_BASE<"lwc2", COP2Opnd>; +class LDC2_R6_DESC : COP2LD_DESC_BASE<"ldc2", COP2Opnd, II_LDC2>; +class LWC2_R6_DESC : COP2LD_DESC_BASE<"lwc2", COP2Opnd, II_LWC2>; -class COP2ST_DESC_BASE<string instr_asm, RegisterOperand COPOpnd> { +class COP2ST_DESC_BASE<string instr_asm, RegisterOperand COPOpnd, + InstrItinClass itin> { dag OutOperandList = (outs); dag InOperandList = (ins COPOpnd:$rt, mem_simm11:$addr); string AsmString = !strconcat(instr_asm, "\t$rt, $addr"); list<dag> Pattern = []; bit mayStore = 1; string DecoderMethod = "DecodeFMemCop2R6"; + InstrItinClass Itinerary = itin; } -class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd>; -class SWC2_R6_DESC : COP2ST_DESC_BASE<"swc2", COP2Opnd>; +class SDC2_R6_DESC : COP2ST_DESC_BASE<"sdc2", COP2Opnd, II_SDC2>; +class SWC2_R6_DESC : COP2ST_DESC_BASE<"swc2", COP2Opnd, II_SWC2>; class LSA_R6_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, Operand ImmOpnd, InstrItinClass itin> @@ -732,6 +774,7 @@ class SDBBP_R6_DESC { string AsmString = "sdbbp\t$code_"; list<dag> Pattern = []; bit isCTI = 1; + InstrItinClass Itinerary = II_SDBBP; } //===----------------------------------------------------------------------===// @@ -754,26 +797,28 @@ let AdditionalPredicates = [NotInMicroMips] in { def BC2NEZ : BC2NEZ_ENC, BC2NEZ_DESC, ISA_MIPS32R6; } def BC : R6MMR6Rel, BC_ENC, BC_DESC, ISA_MIPS32R6; -def BEQC : R6MMR6Rel, BEQC_ENC, BEQC_DESC, ISA_MIPS32R6; -def BEQZALC : R6MMR6Rel, BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6; -def BEQZC : R6MMR6Rel, BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6; -def BGEC : R6MMR6Rel, BGEC_ENC, BGEC_DESC, ISA_MIPS32R6; -def BGEUC : R6MMR6Rel, BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6; -def BGEZALC : R6MMR6Rel, BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6; -def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6; -def BGTZALC : R6MMR6Rel, BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6; -def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6; +let AdditionalPredicates = [NotInMicroMips] in { + def BEQC : R6MMR6Rel, BEQC_ENC, BEQC_DESC, ISA_MIPS32R6; + def BEQZALC : R6MMR6Rel, BEQZALC_ENC, BEQZALC_DESC, ISA_MIPS32R6; + def BEQZC : R6MMR6Rel, BEQZC_ENC, BEQZC_DESC, ISA_MIPS32R6; + def BGEC : R6MMR6Rel, BGEC_ENC, BGEC_DESC, ISA_MIPS32R6; + def BGEUC : R6MMR6Rel, BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6; + def BGEZALC : R6MMR6Rel, BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6; + def BGEZC : R6MMR6Rel, BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6; + def BGTZALC : R6MMR6Rel, BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6; + def BGTZC : R6MMR6Rel, BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6; +} def BITSWAP : R6MMR6Rel, BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6; -def BLEZALC : R6MMR6Rel, BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6; -def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6; -def BLTC : R6MMR6Rel, BLTC_ENC, BLTC_DESC, ISA_MIPS32R6; -def BLTUC : R6MMR6Rel, BLTUC_ENC, BLTUC_DESC, ISA_MIPS32R6; -def BLTZALC : R6MMR6Rel, BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6; -def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6; -def BNEC : R6MMR6Rel, BNEC_ENC, BNEC_DESC, ISA_MIPS32R6; -def BNEZALC : R6MMR6Rel, BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6; -def BNEZC : R6MMR6Rel, BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6; let AdditionalPredicates = [NotInMicroMips] in { + def BLEZALC : R6MMR6Rel, BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6; + def BLEZC : R6MMR6Rel, BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6; + def BLTC : R6MMR6Rel, BLTC_ENC, BLTC_DESC, ISA_MIPS32R6; + def BLTUC : R6MMR6Rel, BLTUC_ENC, BLTUC_DESC, ISA_MIPS32R6; + def BLTZALC : R6MMR6Rel, BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6; + def BLTZC : R6MMR6Rel, BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6; + def BNEC : R6MMR6Rel, BNEC_ENC, BNEC_DESC, ISA_MIPS32R6; + def BNEZALC : R6MMR6Rel, BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6; + def BNEZC : R6MMR6Rel, BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6; def BNVC : R6MMR6Rel, BNVC_ENC, BNVC_DESC, ISA_MIPS32R6; def BOVC : R6MMR6Rel, BOVC_ENC, BOVC_DESC, ISA_MIPS32R6; } @@ -784,12 +829,16 @@ let AdditionalPredicates = [NotInMicroMips] in { } def CLO_R6 : R6MMR6Rel, CLO_R6_ENC, CLO_R6_DESC, ISA_MIPS32R6; def CLZ_R6 : R6MMR6Rel, CLZ_R6_ENC, CLZ_R6_DESC, ISA_MIPS32R6; -defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd>; -defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd>; +defm S : CMP_CC_M<FIELD_CMP_FORMAT_S, "s", FGR32Opnd, II_CMP_CC_S>; +defm D : CMP_CC_M<FIELD_CMP_FORMAT_D, "d", FGR64Opnd, II_CMP_CC_D>; let AdditionalPredicates = [NotInMicroMips] in { def DIV : R6MMR6Rel, DIV_ENC, DIV_DESC, ISA_MIPS32R6; def DIVU : R6MMR6Rel, DIVU_ENC, DIVU_DESC, ISA_MIPS32R6; } + +def DVP : R6MMR6Rel, DVP_ENC, DVP_DESC, ISA_MIPS32R6; +def EVP : R6MMR6Rel, EVP_ENC, EVP_DESC, ISA_MIPS32R6; + def JIALC : R6MMR6Rel, JIALC_ENC, JIALC_DESC, ISA_MIPS32R6; def JIC : R6MMR6Rel, JIC_ENC, JIC_DESC, ISA_MIPS32R6; def JR_HB_R6 : JR_HB_R6_ENC, JR_HB_R6_DESC, ISA_MIPS32R6; @@ -802,8 +851,8 @@ let AdditionalPredicates = [NotInMicroMips] in { def LWC2_R6 : LWC2_R6_ENC, LWC2_R6_DESC, ISA_MIPS32R6; } def LWPC : R6MMR6Rel, LWPC_ENC, LWPC_DESC, ISA_MIPS32R6; -def LWUPC : LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6; let AdditionalPredicates = [NotInMicroMips] in { + def LWUPC : R6MMR6Rel, LWUPC_ENC, LWUPC_DESC, ISA_MIPS32R6; def MADDF_S : MADDF_S_ENC, MADDF_S_DESC, ISA_MIPS32R6, HARDFLOAT; def MADDF_D : MADDF_D_ENC, MADDF_D_DESC, ISA_MIPS32R6, HARDFLOAT; def MAXA_D : MAXA_D_ENC, MAXA_D_DESC, ISA_MIPS32R6, HARDFLOAT; @@ -855,6 +904,9 @@ let AdditionalPredicates = [NotInMicroMips] in { // //===----------------------------------------------------------------------===// +def : MipsInstAlias<"dvp", (DVP ZERO), 0>, ISA_MIPS32R6; +def : MipsInstAlias<"evp", (EVP ZERO), 0>, ISA_MIPS32R6; + let AdditionalPredicates = [NotInMicroMips] in { def : MipsInstAlias<"sdbbp", (SDBBP_R6 0)>, ISA_MIPS32R6; def : MipsInstAlias<"jr $rs", (JALR ZERO, GPR32Opnd:$rs), 1>, ISA_MIPS32R6, GPR_32; diff --git a/contrib/llvm/lib/Target/Mips/Mips64InstrInfo.td b/contrib/llvm/lib/Target/Mips/Mips64InstrInfo.td index 88cfec5..521e22f 100644 --- a/contrib/llvm/lib/Target/Mips/Mips64InstrInfo.td +++ b/contrib/llvm/lib/Target/Mips/Mips64InstrInfo.td @@ -15,11 +15,6 @@ // Mips Operand, Complex Patterns and Transformations Definitions. //===----------------------------------------------------------------------===// -// Transformation Function - get Imm - 32. -def Subtract32 : SDNodeXForm<imm, [{ - return getImm(N, (unsigned)N->getZExtValue() - 32); -}]>; - // shamt must fit in 6 bits. def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; @@ -228,22 +223,24 @@ def LL64 : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, PTR_64, ISA_MIPS2_NOT_32R6_64R6; def SC64 : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, PTR_64, ISA_MIPS2_NOT_32R6_64R6; +def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>, PTR_64; } +def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM; + /// Jump and Branch Instructions let isCodeGenOnly = 1 in { - def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>; def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>; def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>; def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>; def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>; def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>; def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>; - def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM; def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>; - def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>; } +def TAILCALLREG64 : TailCallReg<GPR64Opnd>; + def PseudoReturn64 : PseudoReturnBase<GPR64Opnd>; def PseudoIndirectBranch64 : PseudoIndirectBranchBase<GPR64Opnd>; @@ -293,14 +290,16 @@ def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>, /// Count Leading let AdditionalPredicates = [NotInMicroMips] in { - def DCLZ : StdMMR6Rel, CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>, - ISA_MIPS64_NOT_64R6; - def DCLO : StdMMR6Rel, CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>, - ISA_MIPS64_NOT_64R6; + def DCLZ : StdMMR6Rel, CountLeading0<"dclz", GPR64Opnd, II_DCLZ>, + CLO_FM<0x24>, ISA_MIPS64_NOT_64R6; + def DCLO : StdMMR6Rel, CountLeading1<"dclo", GPR64Opnd, II_DCLO>, + CLO_FM<0x25>, ISA_MIPS64_NOT_64R6; /// Double Word Swap Bytes/HalfWords - def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>, ISA_MIPS64R2; - def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>, ISA_MIPS64R2; + def DSBH : SubwordSwap<"dsbh", GPR64Opnd, II_DSBH>, SEB_FM<2, 0x24>, + ISA_MIPS64R2; + def DSHD : SubwordSwap<"dshd", GPR64Opnd, II_DSHD>, SEB_FM<5, 0x24>, + ISA_MIPS64R2; } def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>; @@ -357,11 +356,12 @@ class Count1s<string opstr, RegisterOperand RO>: let TwoOperandAliasConstraint = "$rd = $rs"; } -class ExtsCins<string opstr, SDPatternOperator Op = null_frag>: +class ExtsCins<string opstr, InstrItinClass itin, + SDPatternOperator Op = null_frag>: InstSE<(outs GPR64Opnd:$rt), (ins GPR64Opnd:$rs, uimm5:$pos, uimm5:$lenm1), !strconcat(opstr, " $rt, $rs, $pos, $lenm1"), [(set GPR64Opnd:$rt, (Op GPR64Opnd:$rs, imm:$pos, imm:$lenm1))], - NoItinerary, FrmR, opstr> { + itin, FrmR, opstr> { let TwoOperandAliasConstraint = "$rt = $rs"; } @@ -395,9 +395,9 @@ class CBranchBitNum<string opstr, DAGOperand opnd, PatFrag cond_op, let Defs = [AT]; } -class MFC2OP<string asmstr, RegisterOperand RO> : +class MFC2OP<string asmstr, RegisterOperand RO, InstrItinClass itin> : InstSE<(outs RO:$rt, uimm16:$imm16), (ins), - !strconcat(asmstr, "\t$rt, $imm16"), [], NoItinerary, FrmFR>; + !strconcat(asmstr, "\t$rt, $imm16"), [], itin, FrmFR>; // Unsigned Byte Add def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>, @@ -425,12 +425,12 @@ def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>, } // Extract a signed bit field /+32 -def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>, ASE_CNMIPS; -def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>, ASE_CNMIPS; +def EXTS : ExtsCins<"exts", II_EXT>, EXTS_FM<0x3a>, ASE_CNMIPS; +def EXTS32: ExtsCins<"exts32", II_EXT>, EXTS_FM<0x3b>, ASE_CNMIPS; // Clear and insert a bit field /+32 -def CINS : ExtsCins<"cins">, EXTS_FM<0x32>, ASE_CNMIPS; -def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>, ASE_CNMIPS; +def CINS : ExtsCins<"cins", II_INS>, EXTS_FM<0x32>, ASE_CNMIPS; +def CINS32: ExtsCins<"cins32", II_INS>, EXTS_FM<0x33>, ASE_CNMIPS; // Move to multiplier/product register def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>, @@ -472,8 +472,10 @@ def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x0f>, } // Move between CPU and coprocessor registers -def DMFC2_OCTEON : MFC2OP<"dmfc2", GPR64Opnd>, MFC2OP_FM<0x12, 1>, ASE_CNMIPS; -def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd>, MFC2OP_FM<0x12, 5>, ASE_CNMIPS; +def DMFC2_OCTEON : MFC2OP<"dmfc2", GPR64Opnd, II_DMFC2>, MFC2OP_FM<0x12, 1>, + ASE_CNMIPS; +def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd, II_DMTC2>, MFC2OP_FM<0x12, 5>, + ASE_CNMIPS; } } @@ -494,6 +496,16 @@ def DMTC2 : MTC3OP<"dmtc2", COP2Opnd, GPR64Opnd, II_DMTC2>, MFC3OP_FM<0x12, 5>, // Arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// +// Materialize i64 constants. +defm : MaterializeImms<i64, ZERO_64, DADDiu, LUi64, ORi64>; + +def : MipsPat<(i64 immZExt32Low16Zero:$imm), + (DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16)>; + +def : MipsPat<(i64 immZExt32:$imm), + (ORi64 (DSLL (ORi64 ZERO_64, (HI16 imm:$imm)), 16), + (LO16 imm:$imm))>; + // extended loads def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; @@ -537,21 +549,21 @@ let AdditionalPredicates = [NotInMicroMips] in { def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>; } -defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, +defm : BrcondPats<GPR64, BEQ64, BEQ, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, ZERO_64>; - def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst), (BLEZ64 i64:$lhs, bb:$dst)>; def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst), (BGEZ64 i64:$lhs, bb:$dst)>; // setcc patterns -defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>; -defm : SetlePats<GPR64, SLT64, SLTu64>; -defm : SetgtPats<GPR64, SLT64, SLTu64>; -defm : SetgePats<GPR64, SLT64, SLTu64>; -defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>; - +let AdditionalPredicates = [NotInMicroMips] in { + defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>; + defm : SetlePats<GPR64, XORi, SLT64, SLTu64>; + defm : SetgtPats<GPR64, SLT64, SLTu64>; + defm : SetgePats<GPR64, XORi, SLT64, SLTu64>; + defm : SetgeImmPats<GPR64, XORi, SLTi64, SLTiu64>; +} // truncate def : MipsPat<(trunc (assertsext GPR64:$src)), (EXTRACT_SUBREG GPR64:$src, sub_32)>; @@ -658,11 +670,14 @@ let AdditionalPredicates = [NotInMicroMips] in { (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>, ISA_MIPS3; def : MipsInstAlias<"dneg $rt", - (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 0>, + (DSUB GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>, ISA_MIPS3; def : MipsInstAlias<"dnegu $rt, $rs", (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rs), 1>, ISA_MIPS3; + def : MipsInstAlias<"dnegu $rt", + (DSUBu GPR64Opnd:$rt, ZERO_64, GPR64Opnd:$rt), 1>, + ISA_MIPS3; } def : MipsInstAlias<"dsubi $rs, $rt, $imm", (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, diff --git a/contrib/llvm/lib/Target/Mips/Mips64r6InstrInfo.td b/contrib/llvm/lib/Target/Mips/Mips64r6InstrInfo.td index 64effbe..dabf4e0 100644 --- a/contrib/llvm/lib/Target/Mips/Mips64r6InstrInfo.td +++ b/contrib/llvm/lib/Target/Mips/Mips64r6InstrInfo.td @@ -48,8 +48,8 @@ class SCD_R6_ENC : SPECIAL3_LL_SC_FM<OPCODE6_SCD>; class AHI_ATI_DESC_BASE<string instr_asm, RegisterOperand GPROpnd, InstrItinClass itin> { dag OutOperandList = (outs GPROpnd:$rs); - dag InOperandList = (ins GPROpnd:$rt, simm16_relaxed:$imm); - string AsmString = !strconcat(instr_asm, "\t$rt, $imm"); + dag InOperandList = (ins GPROpnd:$rt, uimm16_altrelaxed:$imm); + string AsmString = !strconcat(instr_asm, "\t$rs, $rt, $imm"); string Constraints = "$rs = $rt"; InstrItinClass Itinerary = itin; } @@ -76,13 +76,27 @@ class SCD_R6_DESC : SC_R6_DESC_BASE<"scd", GPR64Opnd, II_SCD>; class SELEQZ64_DESC : SELEQNE_Z_DESC_BASE<"seleqz", GPR64Opnd>; class SELNEZ64_DESC : SELEQNE_Z_DESC_BASE<"selnez", GPR64Opnd>; +class BGEC64_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR64Opnd>; +class BGEUC64_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR64Opnd>; +class BEQC64_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR64Opnd>; +class BNEC64_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR64Opnd>; +class BLTC64_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR64Opnd>; +class BLTUC64_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR64Opnd>; +class BLTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR64Opnd>; +class BGEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR64Opnd>; +class BLEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR64Opnd>; +class BGTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR64Opnd>; +class BEQZC64_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR64Opnd>; +class BNEZC64_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR64Opnd>; + class JIALC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jialc", calloffset16, - GPR64Opnd> { + GPR64Opnd, II_JIALC> { bit isCall = 1; list<Register> Defs = [RA]; } -class JIC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR64Opnd> { +class JIC64_DESC : JMP_IDX_COMPACT_DESC_BASE<"jic", jmpoffset16, GPR64Opnd, + II_JIC> { bit isBarrier = 1; bit isTerminator = 1; list<Register> Defs = [AT]; @@ -97,22 +111,20 @@ class SC64_R6_DESC : SC_R6_DESC_BASE<"sc", GPR32Opnd, II_SC>; //===----------------------------------------------------------------------===// let AdditionalPredicates = [NotInMicroMips] in { - def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6; - def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6; + let DecoderMethod = "DecodeDAHIDATI" in { + def DATI : DATI_ENC, DATI_DESC, ISA_MIPS64R6; + def DAHI : DAHI_ENC, DAHI_DESC, ISA_MIPS64R6; + } def DAUI : DAUI_ENC, DAUI_DESC, ISA_MIPS64R6; def DALIGN : DALIGN_ENC, DALIGN_DESC, ISA_MIPS64R6; -} -def DBITSWAP : DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6; -let AdditionalPredicates = [NotInMicroMips] in { + def DBITSWAP : R6MMR6Rel, DBITSWAP_ENC, DBITSWAP_DESC, ISA_MIPS64R6; def DCLO_R6 : R6MMR6Rel, DCLO_R6_ENC, DCLO_R6_DESC, ISA_MIPS64R6; def DCLZ_R6 : R6MMR6Rel, DCLZ_R6_ENC, DCLZ_R6_DESC, ISA_MIPS64R6; def DDIV : DDIV_ENC, DDIV_DESC, ISA_MIPS64R6; def DDIVU : DDIVU_ENC, DDIVU_DESC, ISA_MIPS64R6; def DMOD : DMOD_ENC, DMOD_DESC, ISA_MIPS64R6; def DMODU : DMODU_ENC, DMODU_DESC, ISA_MIPS64R6; -} -def DLSA_R6 : DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6; -let AdditionalPredicates = [NotInMicroMips] in { + def DLSA_R6 : R6MMR6Rel, DLSA_R6_ENC, DLSA_R6_DESC, ISA_MIPS64R6; def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6; def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6; def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6; @@ -130,10 +142,28 @@ let AdditionalPredicates = [NotInMicroMips], def LL64_R6 : LL_R6_ENC, LL64_R6_DESC, PTR_64, ISA_MIPS64R6; def SC64_R6 : SC_R6_ENC, SC64_R6_DESC, PTR_64, ISA_MIPS64R6; } -let isCodeGenOnly = 1 in { -def JIALC64 : JIALC_ENC, JIALC64_DESC, ISA_MIPS64R6; -def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6; + +let DecoderNamespace = "Mips32r6_64r6_GP64" in { +// Jump and Branch Instructions +def JIALC64 : JIALC_ENC, JIALC64_DESC, ISA_MIPS64R6, GPR_64; +def JIC64 : JIC_ENC, JIC64_DESC, ISA_MIPS64R6, GPR_64; + +def BEQC64 : BEQC_ENC, BEQC64_DESC, ISA_MIPS64R6, GPR_64; +def BEQZC64 : BEQZC_ENC, BEQZC64_DESC, ISA_MIPS64R6, GPR_64; +def BGEC64 : BGEC_ENC, BGEC64_DESC, ISA_MIPS64R6, GPR_64; +def BGEUC64 : BGEUC_ENC, BGEUC64_DESC, ISA_MIPS64R6, GPR_64; +def BGTZC64 : BGTZC_ENC, BGTZC64_DESC, ISA_MIPS64R6, GPR_64; +def BLEZC64 : BLEZC_ENC, BLEZC64_DESC, ISA_MIPS64R6, GPR_64; +def BLTC64 : BLTC_ENC, BLTC64_DESC, ISA_MIPS64R6, GPR_64; +def BLTUC64 : BLTUC_ENC, BLTUC64_DESC, ISA_MIPS64R6, GPR_64; +def BNEC64 : BNEC_ENC, BNEC64_DESC, ISA_MIPS64R6, GPR_64; +def BNEZC64 : BNEZC_ENC, BNEZC64_DESC, ISA_MIPS64R6, GPR_64; } +let DecoderNamespace = "Mips32r6_64r6_BranchZero" in { +def BLTZC64 : BLTZC_ENC, BLTZC64_DESC, ISA_MIPS64R6, GPR_64; +def BGEZC64 : BGEZC_ENC, BGEZC64_DESC, ISA_MIPS64R6, GPR_64; +} + //===----------------------------------------------------------------------===// // // Instruction Aliases diff --git a/contrib/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/contrib/llvm/lib/Target/Mips/MipsAsmPrinter.cpp index 3686c2f..04d6529 100644 --- a/contrib/llvm/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsAsmPrinter.cpp @@ -60,10 +60,6 @@ MipsTargetStreamer &MipsAsmPrinter::getTargetStreamer() const { bool MipsAsmPrinter::runOnMachineFunction(MachineFunction &MF) { Subtarget = &MF.getSubtarget<MipsSubtarget>(); - // Initialize TargetLoweringObjectFile. - const_cast<TargetLoweringObjectFile &>(getObjFileLowering()) - .Initialize(OutContext, TM); - MipsFI = MF.getInfo<MipsFunctionInfo>(); if (Subtarget->inMips16Mode()) for (std::map< @@ -98,6 +94,7 @@ bool MipsAsmPrinter::lowerOperand(const MachineOperand &MO, MCOperand &MCOp) { void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer, const MachineInstr *MI) { bool HasLinkReg = false; + bool InMicroMipsMode = Subtarget->inMicroMipsMode(); MCInst TmpInst0; if (Subtarget->hasMips64r6()) { @@ -106,8 +103,12 @@ void MipsAsmPrinter::emitPseudoIndirectBranch(MCStreamer &OutStreamer, HasLinkReg = true; } else if (Subtarget->hasMips32r6()) { // MIPS32r6 should use (JALR ZERO, $rs) - TmpInst0.setOpcode(Mips::JALR); - HasLinkReg = true; + if (InMicroMipsMode) + TmpInst0.setOpcode(Mips::JRC16_MMR6); + else { + TmpInst0.setOpcode(Mips::JALR); + HasLinkReg = true; + } } else if (Subtarget->inMicroMipsMode()) // microMIPS should use (JR_MM $rs) TmpInst0.setOpcode(Mips::JR_MM); @@ -185,7 +186,9 @@ void MipsAsmPrinter::EmitInstruction(const MachineInstr *MI) { if (I->getOpcode() == Mips::PseudoReturn || I->getOpcode() == Mips::PseudoReturn64 || I->getOpcode() == Mips::PseudoIndirectBranch || - I->getOpcode() == Mips::PseudoIndirectBranch64) { + I->getOpcode() == Mips::PseudoIndirectBranch64 || + I->getOpcode() == Mips::TAILCALLREG || + I->getOpcode() == Mips::TAILCALLREG64) { emitPseudoIndirectBranch(*OutStreamer, &*I); continue; } @@ -250,9 +253,9 @@ void MipsAsmPrinter::printSavedRegsBitmask() { int CPUTopSavedRegOff, FPUTopSavedRegOff; // Set the CPU and FPU Bitmasks - const MachineFrameInfo *MFI = MF->getFrameInfo(); + const MachineFrameInfo &MFI = MF->getFrameInfo(); const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo(); - const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); + const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); // size of stack area to which FP callee-saved regs are saved. unsigned CPURegSize = Mips::GPR32RegClass.getSize(); unsigned FGR32RegSize = Mips::FGR32RegClass.getSize(); @@ -302,7 +305,7 @@ void MipsAsmPrinter::emitFrameDirective() { unsigned stackReg = RI.getFrameRegister(*MF); unsigned returnReg = RI.getRARegister(); - unsigned stackSize = MF->getFrameInfo()->getStackSize(); + unsigned stackSize = MF->getFrameInfo().getStackSize(); getTargetStreamer().emitFrame(stackReg, stackSize, returnReg); } @@ -497,7 +500,7 @@ bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, unsigned RegOp = OpNum; if (!Subtarget->isGP64bit()){ - // Endianess reverses which register holds the high or low value + // Endianness reverses which register holds the high or low value // between M and L. switch(ExtraCode[0]) { case 'M': @@ -1034,6 +1037,22 @@ void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI, // TODO: implement } +// Emit .dtprelword or .dtpreldword directive +// and value for debug thread local expression. +void MipsAsmPrinter::EmitDebugValue(const MCExpr *Value, + unsigned Size) const { + switch (Size) { + case 4: + OutStreamer->EmitDTPRel32Value(Value); + break; + case 8: + OutStreamer->EmitDTPRel64Value(Value); + break; + default: + llvm_unreachable("Unexpected size of expression value."); + } +} + // Align all targets of indirect branches on bundle size. Used only if target // is NaCl. void MipsAsmPrinter::NaClAlignIndirectJumpTargets(MachineFunction &MF) { @@ -1063,8 +1082,8 @@ bool MipsAsmPrinter::isLongBranchPseudo(int Opcode) const { // Force static initialization. extern "C" void LLVMInitializeMipsAsmPrinter() { - RegisterAsmPrinter<MipsAsmPrinter> X(TheMipsTarget); - RegisterAsmPrinter<MipsAsmPrinter> Y(TheMipselTarget); - RegisterAsmPrinter<MipsAsmPrinter> A(TheMips64Target); - RegisterAsmPrinter<MipsAsmPrinter> B(TheMips64elTarget); + RegisterAsmPrinter<MipsAsmPrinter> X(getTheMipsTarget()); + RegisterAsmPrinter<MipsAsmPrinter> Y(getTheMipselTarget()); + RegisterAsmPrinter<MipsAsmPrinter> A(getTheMips64Target()); + RegisterAsmPrinter<MipsAsmPrinter> B(getTheMips64elTarget()); } diff --git a/contrib/llvm/lib/Target/Mips/MipsAsmPrinter.h b/contrib/llvm/lib/Target/Mips/MipsAsmPrinter.h index f30141f..c5cf524 100644 --- a/contrib/llvm/lib/Target/Mips/MipsAsmPrinter.h +++ b/contrib/llvm/lib/Target/Mips/MipsAsmPrinter.h @@ -103,9 +103,7 @@ public: : AsmPrinter(TM, std::move(Streamer)), MCP(nullptr), InConstantPool(false), MCInstLowering(*this) {} - const char *getPassName() const override { - return "Mips Assembly Printer"; - } + StringRef getPassName() const override { return "Mips Assembly Printer"; } bool runOnMachineFunction(MachineFunction &MF) override; @@ -142,6 +140,7 @@ public: void EmitStartOfAsmFile(Module &M) override; void EmitEndOfAsmFile(Module &M) override; void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS); + void EmitDebugValue(const MCExpr *Value, unsigned Size) const override; }; } diff --git a/contrib/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp b/contrib/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp index 1ea48e0..08b8ed3 100644 --- a/contrib/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsConstantIslandPass.cpp @@ -356,15 +356,13 @@ namespace { : MachineFunctionPass(ID), STI(nullptr), MF(nullptr), MCP(nullptr), PrescannedForConstants(false) {} - const char *getPassName() const override { - return "Mips Constant Islands"; - } + StringRef getPassName() const override { return "Mips Constant Islands"; } bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } void doInitialPlacement(std::vector<MachineInstr*> &CPEMIs); @@ -801,7 +799,7 @@ void MipsConstantIslands::computeBlockSize(MachineBasicBlock *MBB) { BBI.Size = 0; for (const MachineInstr &MI : *MBB) - BBI.Size += TII->GetInstSizeInBytes(MI); + BBI.Size += TII->getInstSizeInBytes(MI); } /// getOffsetOf - Return the current offset of the specified machine instruction @@ -818,7 +816,7 @@ unsigned MipsConstantIslands::getOffsetOf(MachineInstr *MI) const { // Sum instructions before MI in MBB. for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) { assert(I != MBB->end() && "Didn't find MI in its own basic block?"); - Offset += TII->GetInstSizeInBytes(*I); + Offset += TII->getInstSizeInBytes(*I); } return Offset; } @@ -1297,12 +1295,11 @@ void MipsConstantIslands::createNewWater(unsigned CPUserIndex, unsigned CPUIndex = CPUserIndex+1; unsigned NumCPUsers = CPUsers.size(); //MachineInstr *LastIT = 0; - for (unsigned Offset = UserOffset + TII->GetInstSizeInBytes(*UserMI); + for (unsigned Offset = UserOffset + TII->getInstSizeInBytes(*UserMI); Offset < BaseInsertOffset; - Offset += TII->GetInstSizeInBytes(*MI), MI = std::next(MI)) { + Offset += TII->getInstSizeInBytes(*MI), MI = std::next(MI)) { assert(MI != UserMBB->end() && "Fell off end of block"); - if (CPUIndex < NumCPUsers && - CPUsers[CPUIndex].MI == static_cast<MachineInstr *>(MI)) { + if (CPUIndex < NumCPUsers && CPUsers[CPUIndex].MI == MI) { CPUser &U = CPUsers[CPUIndex]; if (!isOffsetInRange(Offset, EndInsertOffset, U)) { // Shift intertion point by one unit of alignment so it is within reach. @@ -1374,7 +1371,7 @@ bool MipsConstantIslands::handleConstantPoolUser(unsigned CPUserIndex) { // it. Check for this so it will be removed from the WaterList. // Also remove any entry from NewWaterList. MachineBasicBlock *WaterBB = &*--NewMBB->getIterator(); - IP = std::find(WaterList.begin(), WaterList.end(), WaterBB); + IP = find(WaterList, WaterBB); if (IP != WaterList.end()) NewWaterList.erase(WaterBB); @@ -1622,7 +1619,7 @@ MipsConstantIslands::fixupConditionalBr(ImmBranch &Br) { splitBlockBeforeInstr(*MI); // No need for the branch to the next block. We're adding an unconditional // branch to the destination. - int delta = TII->GetInstSizeInBytes(MBB->back()); + int delta = TII->getInstSizeInBytes(MBB->back()); BBInfo[MBB->getNumber()].Size -= delta; MBB->back().eraseFromParent(); // BBInfo[SplitBB].Offset is wrong temporarily, fixed below @@ -1644,14 +1641,14 @@ MipsConstantIslands::fixupConditionalBr(ImmBranch &Br) { .addMBB(NextBB); } Br.MI = &MBB->back(); - BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back()); + BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back()); BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB); - BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back()); + BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back()); unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr); ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr)); // Remove the old conditional branch. It may or may not still be in MBB. - BBInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(*MI); + BBInfo[MI->getParent()->getNumber()].Size -= TII->getInstSizeInBytes(*MI); MI->eraseFromParent(); adjustBBOffsetsAfter(MBB); return true; diff --git a/contrib/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp b/contrib/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp index b5ba770..c821084 100644 --- a/contrib/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp @@ -79,8 +79,7 @@ static cl::opt<CompactBranchPolicy> MipsCompactBranchPolicy( cl::values( clEnumValN(CB_Never, "never", "Do not use compact branches if possible."), clEnumValN(CB_Optimal, "optimal", "Use compact branches where appropiate (default)."), - clEnumValN(CB_Always, "always", "Always use compact branches if possible."), - clEnumValEnd + clEnumValN(CB_Always, "always", "Always use compact branches if possible.") ) ); @@ -192,9 +191,7 @@ namespace { Filler(TargetMachine &tm) : MachineFunctionPass(ID), TM(tm) { } - const char *getPassName() const override { - return "Mips Delay Slot Filler"; - } + StringRef getPassName() const override { return "Mips Delay Slot Filler"; } bool runOnMachineFunction(MachineFunction &F) override { bool Changed = false; @@ -213,7 +210,7 @@ namespace { MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } void getAnalysisUsage(AnalysisUsage &AU) const override { @@ -242,7 +239,7 @@ namespace { /// This function searches in the backward direction for an instruction that /// can be moved to the delay slot. Returns true on success. - bool searchBackward(MachineBasicBlock &MBB, Iter Slot) const; + bool searchBackward(MachineBasicBlock &MBB, MachineInstr &Slot) const; /// This function searches MBB in the forward direction for an instruction /// that can be moved to the delay slot. Returns true on success. @@ -543,6 +540,9 @@ Iter Filler::replaceWithCompactBranch(MachineBasicBlock &MBB, Iter Branch, // For given opcode returns opcode of corresponding instruction with short // delay slot. +// For the pseudo TAILCALL*_MM instrunctions return the short delay slot +// form. Unfortunately, TAILCALL<->b16 is denied as b16 has a limited range +// that is too short to make use of for tail calls. static int getEquivalentCallShort(int Opcode) { switch (Opcode) { case Mips::BGEZAL: @@ -555,6 +555,10 @@ static int getEquivalentCallShort(int Opcode) { return Mips::JALRS_MM; case Mips::JALR16_MM: return Mips::JALRS16_MM; + case Mips::TAILCALL_MM: + llvm_unreachable("Attempting to shorten the TAILCALL_MM pseudo!"); + case Mips::TAILCALLREG: + return Mips::JR16_MM; default: llvm_unreachable("Unexpected call instruction for microMIPS."); } @@ -587,7 +591,7 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { if (MipsCompactBranchPolicy.getValue() != CB_Always || !TII->getEquivalentCompactForm(I)) { - if (searchBackward(MBB, I)) { + if (searchBackward(MBB, *I)) { Filled = true; } else if (I->isTerminator()) { if (searchSuccBBs(MBB, I)) { @@ -602,10 +606,16 @@ bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) { // Get instruction with delay slot. MachineBasicBlock::instr_iterator DSI = I.getInstrIterator(); - if (InMicroMipsMode && TII->GetInstSizeInBytes(*std::next(DSI)) == 2 && + if (InMicroMipsMode && TII->getInstSizeInBytes(*std::next(DSI)) == 2 && DSI->isCall()) { // If instruction in delay slot is 16b change opcode to // corresponding instruction with short delay slot. + + // TODO: Implement an instruction mapping table of 16bit opcodes to + // 32bit opcodes so that an instruction can be expanded. This would + // save 16 bits as a TAILCALL_MM pseudo requires a fullsized nop. + // TODO: Permit b16 when branching backwards to the the same function + // if it is in range. DSI->setDesc(TII->get(getEquivalentCallShort(DSI->getOpcode()))); } continue; @@ -646,8 +656,6 @@ template<typename IterTy> bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End, RegDefsUses &RegDU, InspectMemInstr& IM, Iter Slot, IterTy &Filler) const { - bool IsReverseIter = std::is_convertible<IterTy, ReverseIter>::value; - for (IterTy I = Begin; I != End;) { IterTy CurrI = I; ++I; @@ -664,12 +672,6 @@ bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End, if (CurrI->isKill()) { CurrI->eraseFromParent(); - - // This special case is needed for reverse iterators, because when we - // erase an instruction, the iterators are updated to point to the next - // instruction. - if (IsReverseIter && I != End) - I = CurrI; continue; } @@ -692,9 +694,14 @@ bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End, bool InMicroMipsMode = STI.inMicroMipsMode(); const MipsInstrInfo *TII = STI.getInstrInfo(); unsigned Opcode = (*Slot).getOpcode(); - if (InMicroMipsMode && TII->GetInstSizeInBytes(*CurrI) == 2 && + // This is complicated by the tail call optimization. For non-PIC code + // there is only a 32bit sized unconditional branch which can be assumed + // to be able to reach the target. b16 only has a range of +/- 1 KB. + // It's entirely possible that the target function is reachable with b16 + // but we don't have enough information to make that decision. + if (InMicroMipsMode && TII->getInstSizeInBytes(*CurrI) == 2 && (Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch || - Opcode == Mips::PseudoReturn)) + Opcode == Mips::PseudoReturn || Opcode == Mips::TAILCALL)) continue; Filler = CurrI; @@ -704,23 +711,24 @@ bool Filler::searchRange(MachineBasicBlock &MBB, IterTy Begin, IterTy End, return false; } -bool Filler::searchBackward(MachineBasicBlock &MBB, Iter Slot) const { +bool Filler::searchBackward(MachineBasicBlock &MBB, MachineInstr &Slot) const { if (DisableBackwardSearch) return false; auto *Fn = MBB.getParent(); RegDefsUses RegDU(*Fn->getSubtarget().getRegisterInfo()); - MemDefsUses MemDU(Fn->getDataLayout(), Fn->getFrameInfo()); + MemDefsUses MemDU(Fn->getDataLayout(), &Fn->getFrameInfo()); ReverseIter Filler; - RegDU.init(*Slot); + RegDU.init(Slot); - if (!searchRange(MBB, ReverseIter(Slot), MBB.rend(), RegDU, MemDU, Slot, + MachineBasicBlock::iterator SlotI = Slot; + if (!searchRange(MBB, ++SlotI.getReverse(), MBB.rend(), RegDU, MemDU, Slot, Filler)) return false; - MBB.splice(std::next(Slot), &MBB, std::next(Filler).base()); - MIBundleBuilder(MBB, Slot, std::next(Slot, 2)); + MBB.splice(std::next(SlotI), &MBB, Filler.getReverse()); + MIBundleBuilder(MBB, SlotI, std::next(SlotI, 2)); ++UsefulSlots; return true; } @@ -776,8 +784,8 @@ bool Filler::searchSuccBBs(MachineBasicBlock &MBB, Iter Slot) const { if (HasMultipleSuccs) { IM.reset(new LoadFromStackOrConst()); } else { - const MachineFrameInfo *MFI = Fn->getFrameInfo(); - IM.reset(new MemDefsUses(Fn->getDataLayout(), MFI)); + const MachineFrameInfo &MFI = Fn->getFrameInfo(); + IM.reset(new MemDefsUses(Fn->getDataLayout(), &MFI)); } if (!searchRange(MBB, SuccBB->begin(), SuccBB->end(), RegDU, *IM, Slot, diff --git a/contrib/llvm/lib/Target/Mips/MipsEVAInstrFormats.td b/contrib/llvm/lib/Target/Mips/MipsEVAInstrFormats.td index 11e191a..8c30248 100644 --- a/contrib/llvm/lib/Target/Mips/MipsEVAInstrFormats.td +++ b/contrib/llvm/lib/Target/Mips/MipsEVAInstrFormats.td @@ -50,7 +50,7 @@ def OPCODE6_TLBINVF : OPCODE6<0b000100>; def OPCODE6_CACHEE : OPCODE6<0b011011>; def OPCODE6_PREFE : OPCODE6<0b100011>; -def OPGROUP_COP0 : OPGROUP<0b010000>; +def OPGROUP_COP0_TLB : OPGROUP<0b010000>; //===----------------------------------------------------------------------===// // @@ -77,7 +77,7 @@ class SPECIAL3_EVA_LOAD_STORE_FM<OPCODE6 Operation> : MipsEVAInst { class TLB_FM<OPCODE6 Operation> : MipsEVAInst { bits<32> Inst; - let Inst{31-26} = OPGROUP_COP0.Value; + let Inst{31-26} = OPGROUP_COP0_TLB.Value; let Inst{25} = 1; // CO let Inst{24-6} = 0; let Inst{5-0} = Operation.Value; diff --git a/contrib/llvm/lib/Target/Mips/MipsFastISel.cpp b/contrib/llvm/lib/Target/Mips/MipsFastISel.cpp index 19c201d..a44192f 100644 --- a/contrib/llvm/lib/Target/Mips/MipsFastISel.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsFastISel.cpp @@ -31,6 +31,9 @@ #include "llvm/IR/GlobalVariable.h" #include "llvm/MC/MCSymbol.h" #include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Support/Debug.h" + +#define DEBUG_TYPE "mips-fastisel" using namespace llvm; @@ -95,10 +98,10 @@ class MipsFastISel final : public FastISel { // Convenience variables to avoid some queries. LLVMContext *Context; + bool fastLowerArguments() override; bool fastLowerCall(CallLoweringInfo &CLI) override; bool fastLowerIntrinsicCall(const IntrinsicInst *II) override; - bool TargetSupported; bool UnsupportedFPMode; // To allow fast-isel to proceed and just not handle // floating point but not reject doing fast-isel in other // situations @@ -195,6 +198,9 @@ private: bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs, unsigned &NumBytes); bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes); + const MipsABIInfo &getABI() const { + return static_cast<const MipsTargetMachine &>(TM).getABI(); + } public: // Backend specific FastISel code. @@ -205,12 +211,7 @@ public: TII(*Subtarget->getInstrInfo()), TLI(*Subtarget->getTargetLowering()) { MFI = funcInfo.MF->getInfo<MipsFunctionInfo>(); Context = &funcInfo.Fn->getContext(); - bool ISASupported = !Subtarget->hasMips32r6() && - !Subtarget->inMicroMipsMode() && Subtarget->hasMips32(); - TargetSupported = - ISASupported && TM.isPositionIndependent() && - (static_cast<const MipsTargetMachine &>(TM).getABI().IsO32()); - UnsupportedFPMode = Subtarget->isFP64bit(); + UnsupportedFPMode = Subtarget->isFP64bit() || Subtarget->useSoftFloat(); } unsigned fastMaterializeAlloca(const AllocaInst *AI) override; @@ -285,9 +286,6 @@ unsigned MipsFastISel::emitLogicalOp(unsigned ISDOpc, MVT RetVT, } unsigned MipsFastISel::fastMaterializeAlloca(const AllocaInst *AI) { - if (!TargetSupported) - return 0; - assert(TLI.getValueType(DL, AI->getType(), true) == MVT::i32 && "Alloca should always return a pointer."); @@ -398,9 +396,6 @@ unsigned MipsFastISel::materializeExternalCallSym(MCSymbol *Sym) { // Materialize a constant into a register, and return the register // number (or zero if we failed to handle it). unsigned MipsFastISel::fastMaterializeConstant(const Constant *C) { - if (!TargetSupported) - return 0; - EVT CEVT = TLI.getValueType(DL, C->getType(), true); // Only handle simple types. @@ -443,14 +438,14 @@ bool MipsFastISel::computeAddress(const Value *Obj, Address &Addr) { } case Instruction::GetElementPtr: { Address SavedAddr = Addr; - uint64_t TmpOffset = Addr.getOffset(); + int64_t TmpOffset = Addr.getOffset(); // Iterate through the GEP folding the constants into offsets where // we can. gep_type_iterator GTI = gep_type_begin(U); for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); i != e; ++i, ++GTI) { const Value *Op = *i; - if (StructType *STy = dyn_cast<StructType>(*GTI)) { + if (StructType *STy = GTI.getStructTypeOrNull()) { const StructLayout *SL = DL.getStructLayout(STy); unsigned Idx = cast<ConstantInt>(Op)->getZExtValue(); TmpOffset += SL->getElementOffset(Idx); @@ -703,8 +698,8 @@ bool MipsFastISel::emitCmp(unsigned ResultReg, const CmpInst *CI) { unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass); emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0); emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); - emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg( - Mips::FCC0, RegState::ImplicitDefine); + emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg) + .addReg(RightReg); emitInst(CondMovOpc, ResultReg) .addReg(RegWithOne) .addReg(Mips::FCC0) @@ -761,8 +756,8 @@ bool MipsFastISel::emitLoad(MVT VT, unsigned &ResultReg, Address &Addr, if (Addr.isFIBase()) { unsigned FI = Addr.getFI(); unsigned Align = 4; - unsigned Offset = Addr.getOffset(); - MachineFrameInfo &MFI = *MF->getFrameInfo(); + int64_t Offset = Addr.getOffset(); + MachineFrameInfo &MFI = MF->getFrameInfo(); MachineMemOperand *MMO = MF->getMachineMemOperand( MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOLoad, MFI.getObjectSize(FI), Align); @@ -812,8 +807,8 @@ bool MipsFastISel::emitStore(MVT VT, unsigned SrcReg, Address &Addr, if (Addr.isFIBase()) { unsigned FI = Addr.getFI(); unsigned Align = 4; - unsigned Offset = Addr.getOffset(); - MachineFrameInfo &MFI = *MF->getFrameInfo(); + int64_t Offset = Addr.getOffset(); + MachineFrameInfo &MFI = MF->getFrameInfo(); MachineMemOperand *MMO = MF->getMachineMemOperand( MachinePointerInfo::getFixedStack(*MF, FI), MachineMemOperand::MOStore, MFI.getObjectSize(FI), Align); @@ -970,9 +965,13 @@ bool MipsFastISel::selectFPExt(const Instruction *I) { bool MipsFastISel::selectSelect(const Instruction *I) { assert(isa<SelectInst>(I) && "Expected a select instruction."); + DEBUG(dbgs() << "selectSelect\n"); + MVT VT; - if (!isTypeSupported(I->getType(), VT)) + if (!isTypeSupported(I->getType(), VT) || UnsupportedFPMode) { + DEBUG(dbgs() << ".. .. gave up (!isTypeSupported || UnsupportedFPMode)\n"); return false; + } unsigned CondMovOpc; const TargetRegisterClass *RC; @@ -1249,10 +1248,191 @@ bool MipsFastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT, return true; } -bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) { - if (!TargetSupported) +bool MipsFastISel::fastLowerArguments() { + DEBUG(dbgs() << "fastLowerArguments\n"); + + if (!FuncInfo.CanLowerReturn) { + DEBUG(dbgs() << ".. gave up (!CanLowerReturn)\n"); return false; + } + + const Function *F = FuncInfo.Fn; + if (F->isVarArg()) { + DEBUG(dbgs() << ".. gave up (varargs)\n"); + return false; + } + + CallingConv::ID CC = F->getCallingConv(); + if (CC != CallingConv::C) { + DEBUG(dbgs() << ".. gave up (calling convention is not C)\n"); + return false; + } + + const ArrayRef<MCPhysReg> GPR32ArgRegs = {Mips::A0, Mips::A1, Mips::A2, + Mips::A3}; + const ArrayRef<MCPhysReg> FGR32ArgRegs = {Mips::F12, Mips::F14}; + const ArrayRef<MCPhysReg> AFGR64ArgRegs = {Mips::D6, Mips::D7}; + ArrayRef<MCPhysReg>::iterator NextGPR32 = GPR32ArgRegs.begin(); + ArrayRef<MCPhysReg>::iterator NextFGR32 = FGR32ArgRegs.begin(); + ArrayRef<MCPhysReg>::iterator NextAFGR64 = AFGR64ArgRegs.begin(); + + struct AllocatedReg { + const TargetRegisterClass *RC; + unsigned Reg; + AllocatedReg(const TargetRegisterClass *RC, unsigned Reg) + : RC(RC), Reg(Reg) {} + }; + + // Only handle simple cases. i.e. All arguments are directly mapped to + // registers of the appropriate type. + SmallVector<AllocatedReg, 4> Allocation; + unsigned Idx = 1; + for (const auto &FormalArg : F->args()) { + if (F->getAttributes().hasAttribute(Idx, Attribute::InReg) || + F->getAttributes().hasAttribute(Idx, Attribute::StructRet) || + F->getAttributes().hasAttribute(Idx, Attribute::ByVal)) { + DEBUG(dbgs() << ".. gave up (inreg, structret, byval)\n"); + return false; + } + + Type *ArgTy = FormalArg.getType(); + if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy()) { + DEBUG(dbgs() << ".. gave up (struct, array, or vector)\n"); + return false; + } + + EVT ArgVT = TLI.getValueType(DL, ArgTy); + DEBUG(dbgs() << ".. " << (Idx - 1) << ": " << ArgVT.getEVTString() << "\n"); + if (!ArgVT.isSimple()) { + DEBUG(dbgs() << ".. .. gave up (not a simple type)\n"); + return false; + } + + switch (ArgVT.getSimpleVT().SimpleTy) { + case MVT::i1: + case MVT::i8: + case MVT::i16: + if (!F->getAttributes().hasAttribute(Idx, Attribute::SExt) && + !F->getAttributes().hasAttribute(Idx, Attribute::ZExt)) { + // It must be any extend, this shouldn't happen for clang-generated IR + // so just fall back on SelectionDAG. + DEBUG(dbgs() << ".. .. gave up (i8/i16 arg is not extended)\n"); + return false; + } + + if (NextGPR32 == GPR32ArgRegs.end()) { + DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n"); + return false; + } + + DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n"); + Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++); + + // Allocating any GPR32 prohibits further use of floating point arguments. + NextFGR32 = FGR32ArgRegs.end(); + NextAFGR64 = AFGR64ArgRegs.end(); + break; + + case MVT::i32: + if (F->getAttributes().hasAttribute(Idx, Attribute::ZExt)) { + // The O32 ABI does not permit a zero-extended i32. + DEBUG(dbgs() << ".. .. gave up (i32 arg is zero extended)\n"); + return false; + } + if (NextGPR32 == GPR32ArgRegs.end()) { + DEBUG(dbgs() << ".. .. gave up (ran out of GPR32 arguments)\n"); + return false; + } + + DEBUG(dbgs() << ".. .. GPR32(" << *NextGPR32 << ")\n"); + Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++); + + // Allocating any GPR32 prohibits further use of floating point arguments. + NextFGR32 = FGR32ArgRegs.end(); + NextAFGR64 = AFGR64ArgRegs.end(); + break; + + case MVT::f32: + if (UnsupportedFPMode) { + DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n"); + return false; + } + if (NextFGR32 == FGR32ArgRegs.end()) { + DEBUG(dbgs() << ".. .. gave up (ran out of FGR32 arguments)\n"); + return false; + } + DEBUG(dbgs() << ".. .. FGR32(" << *NextFGR32 << ")\n"); + Allocation.emplace_back(&Mips::FGR32RegClass, *NextFGR32++); + // Allocating an FGR32 also allocates the super-register AFGR64, and + // ABI rules require us to skip the corresponding GPR32. + if (NextGPR32 != GPR32ArgRegs.end()) + NextGPR32++; + if (NextAFGR64 != AFGR64ArgRegs.end()) + NextAFGR64++; + break; + + case MVT::f64: + if (UnsupportedFPMode) { + DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode)\n"); + return false; + } + if (NextAFGR64 == AFGR64ArgRegs.end()) { + DEBUG(dbgs() << ".. .. gave up (ran out of AFGR64 arguments)\n"); + return false; + } + DEBUG(dbgs() << ".. .. AFGR64(" << *NextAFGR64 << ")\n"); + Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++); + // Allocating an FGR32 also allocates the super-register AFGR64, and + // ABI rules require us to skip the corresponding GPR32 pair. + if (NextGPR32 != GPR32ArgRegs.end()) + NextGPR32++; + if (NextGPR32 != GPR32ArgRegs.end()) + NextGPR32++; + if (NextFGR32 != FGR32ArgRegs.end()) + NextFGR32++; + break; + + default: + DEBUG(dbgs() << ".. .. gave up (unknown type)\n"); + return false; + } + + ++Idx; + } + + Idx = 0; + for (const auto &FormalArg : F->args()) { + unsigned SrcReg = Allocation[Idx].Reg; + unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, Allocation[Idx].RC); + // FIXME: Unfortunately it's necessary to emit a copy from the livein copy. + // Without this, EmitLiveInCopies may eliminate the livein if its only + // use is a bitcast (which isn't turned into an instruction). + unsigned ResultReg = createResultReg(Allocation[Idx].RC); + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, + TII.get(TargetOpcode::COPY), ResultReg) + .addReg(DstReg, getKillRegState(true)); + updateValueMap(&FormalArg, ResultReg); + ++Idx; + } + + // Calculate the size of the incoming arguments area. + // We currently reject all the cases where this would be non-zero. + unsigned IncomingArgSizeInBytes = 0; + + // Account for the reserved argument area on ABI's that have one (O32). + // It seems strange to do this on the caller side but it's necessary in + // SelectionDAG's implementation. + IncomingArgSizeInBytes = std::min(getABI().GetCalleeAllocdArgSizeInBytes(CC), + IncomingArgSizeInBytes); + + MF->getInfo<MipsFunctionInfo>()->setFormalArgInfo(IncomingArgSizeInBytes, + false); + + return true; +} + +bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) { CallingConv::ID CC = CLI.CallConv; bool IsTailCall = CLI.IsTailCall; bool IsVarArg = CLI.IsVarArg; @@ -1337,9 +1517,6 @@ bool MipsFastISel::fastLowerCall(CallLoweringInfo &CLI) { } bool MipsFastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) { - if (!TargetSupported) - return false; - switch (II->getIntrinsicID()) { default: return false; @@ -1435,6 +1612,8 @@ bool MipsFastISel::selectRet(const Instruction *I) { const Function &F = *I->getParent()->getParent(); const ReturnInst *Ret = cast<ReturnInst>(I); + DEBUG(dbgs() << "selectRet\n"); + if (!FuncInfo.CanLowerReturn) return false; @@ -1495,6 +1674,12 @@ bool MipsFastISel::selectRet(const Instruction *I) { if (RVVT == MVT::f128) return false; + // Do not handle FGR64 returns for now. + if (RVVT == MVT::f64 && UnsupportedFPMode) { + DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode\n"); + return false; + } + MVT DestVT = VA.getValVT(); // Special handling for extended integers. if (RVVT != DestVT) { @@ -1778,8 +1963,6 @@ bool MipsFastISel::selectShift(const Instruction *I) { } bool MipsFastISel::fastSelectInstruction(const Instruction *I) { - if (!TargetSupported) - return false; switch (I->getOpcode()) { default: break; diff --git a/contrib/llvm/lib/Target/Mips/MipsFrameLowering.cpp b/contrib/llvm/lib/Target/Mips/MipsFrameLowering.cpp index fe6f332..b2cf039 100644 --- a/contrib/llvm/lib/Target/Mips/MipsFrameLowering.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsFrameLowering.cpp @@ -92,30 +92,30 @@ const MipsFrameLowering *MipsFrameLowering::create(const MipsSubtarget &ST) { // if it needs dynamic stack realignment, if frame pointer elimination is // disabled, or if the frame address is taken. bool MipsFrameLowering::hasFP(const MachineFunction &MF) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); + const MachineFrameInfo &MFI = MF.getFrameInfo(); const TargetRegisterInfo *TRI = STI.getRegisterInfo(); return MF.getTarget().Options.DisableFramePointerElim(MF) || - MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken() || + MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken() || TRI->needsStackRealignment(MF); } bool MipsFrameLowering::hasBP(const MachineFunction &MF) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); + const MachineFrameInfo &MFI = MF.getFrameInfo(); const TargetRegisterInfo *TRI = STI.getRegisterInfo(); - return MFI->hasVarSizedObjects() && TRI->needsStackRealignment(MF); + return MFI.hasVarSizedObjects() && TRI->needsStackRealignment(MF); } uint64_t MipsFrameLowering::estimateStackSize(const MachineFunction &MF) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); + const MachineFrameInfo &MFI = MF.getFrameInfo(); const TargetRegisterInfo &TRI = *STI.getRegisterInfo(); int64_t Offset = 0; // Iterate over fixed sized objects. - for (int I = MFI->getObjectIndexBegin(); I != 0; ++I) - Offset = std::max(Offset, -MFI->getObjectOffset(I)); + for (int I = MFI.getObjectIndexBegin(); I != 0; ++I) + Offset = std::max(Offset, -MFI.getObjectOffset(I)); // Conservatively assume all callee-saved registers will be saved. for (const MCPhysReg *R = TRI.getCalleeSavedRegs(&MF); *R; ++R) { @@ -123,19 +123,19 @@ uint64_t MipsFrameLowering::estimateStackSize(const MachineFunction &MF) const { Offset = alignTo(Offset + Size, Size); } - unsigned MaxAlign = MFI->getMaxAlignment(); + unsigned MaxAlign = MFI.getMaxAlignment(); // Check that MaxAlign is not zero if there is a stack object that is not a // callee-saved spill. - assert(!MFI->getObjectIndexEnd() || MaxAlign); + assert(!MFI.getObjectIndexEnd() || MaxAlign); // Iterate over other objects. - for (unsigned I = 0, E = MFI->getObjectIndexEnd(); I != E; ++I) - Offset = alignTo(Offset + MFI->getObjectSize(I), MaxAlign); + for (unsigned I = 0, E = MFI.getObjectIndexEnd(); I != E; ++I) + Offset = alignTo(Offset + MFI.getObjectSize(I), MaxAlign); // Call frame. - if (MFI->adjustsStack() && hasReservedCallFrame(MF)) - Offset = alignTo(Offset + MFI->getMaxCallFrameSize(), + if (MFI.adjustsStack() && hasReservedCallFrame(MF)) + Offset = alignTo(Offset + MFI.getMaxCallFrameSize(), std::max(MaxAlign, getStackAlignment())); return alignTo(Offset, getStackAlignment()); diff --git a/contrib/llvm/lib/Target/Mips/MipsHazardSchedule.cpp b/contrib/llvm/lib/Target/Mips/MipsHazardSchedule.cpp index 10022ba..31b8612 100644 --- a/contrib/llvm/lib/Target/Mips/MipsHazardSchedule.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsHazardSchedule.cpp @@ -7,10 +7,10 @@ // //===----------------------------------------------------------------------===// /// \file -/// This pass is used to workaround certain pipeline hazards. For now, this covers -/// compact branch hazards. In future this pass can be extended to other pipeline -/// hazards, such as various MIPS1 hazards, processor errata that require -/// instruction reorganization, etc. +/// This pass is used to workaround certain pipeline hazards. For now, this +/// covers compact branch hazards. In future this pass can be extended to other +/// pipeline hazards, such as various MIPS1 hazards, processor errata that +/// require instruction reorganization, etc. /// /// This pass has to run after the delay slot filler as that pass can introduce /// pipeline hazards, hence the existing hazard recognizer is not suitable. @@ -18,8 +18,8 @@ /// Hazards handled: forbidden slots for MIPSR6. /// /// A forbidden slot hazard occurs when a compact branch instruction is executed -/// and the adjacent instruction in memory is a control transfer instruction such -/// as a branch or jump, ERET, ERETNC, DERET, WAIT and PAUSE. +/// and the adjacent instruction in memory is a control transfer instruction +/// such as a branch or jump, ERET, ERETNC, DERET, WAIT and PAUSE. /// /// For example: /// @@ -70,13 +70,13 @@ class MipsHazardSchedule : public MachineFunctionPass { public: MipsHazardSchedule() : MachineFunctionPass(ID) {} - const char *getPassName() const override { return "Mips Hazard Schedule"; } + StringRef getPassName() const override { return "Mips Hazard Schedule"; } bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: @@ -91,20 +91,43 @@ FunctionPass *llvm::createMipsHazardSchedule() { return new MipsHazardSchedule(); } -// Find the next real instruction from the current position. -static Iter getNextMachineInstr(Iter Position) { +// Find the next real instruction from the current position in current basic +// block. +static Iter getNextMachineInstrInBB(Iter Position) { Iter I = Position, E = Position->getParent()->end(); - I = std::find_if_not(I, E, [](const Iter &Insn) { return Insn->isTransient(); }); - assert(I != E); + I = std::find_if_not(I, E, + [](const Iter &Insn) { return Insn->isTransient(); }); + return I; } +// Find the next real instruction from the current position, looking through +// basic block boundaries. +static Iter getNextMachineInstr(Iter Position, MachineBasicBlock *Parent) { + if (Position == Parent->end()) { + MachineBasicBlock *Succ = Parent->getNextNode(); + if (Succ != nullptr && Parent->isSuccessor(Succ)) { + Position = Succ->begin(); + Parent = Succ; + } else { + llvm_unreachable( + "Should have identified the end of the function earlier!"); + } + } + + Iter Instr = getNextMachineInstrInBB(Position); + if (Instr == Parent->end()) { + return getNextMachineInstr(Instr, Parent); + } + return Instr; +} + bool MipsHazardSchedule::runOnMachineFunction(MachineFunction &MF) { const MipsSubtarget *STI = &static_cast<const MipsSubtarget &>(MF.getSubtarget()); - // Forbidden slot hazards are only defined for MIPSR6. + // Forbidden slot hazards are only defined for MIPSR6 but not microMIPSR6. if (!STI->hasMips32r6() || STI->inMicroMipsMode()) return false; @@ -118,27 +141,17 @@ bool MipsHazardSchedule::runOnMachineFunction(MachineFunction &MF) { if (!TII->HasForbiddenSlot(*I)) continue; - bool InsertNop = false; - // Next instruction in the basic block. - if (std::next(I) != FI->end() && - !TII->SafeInForbiddenSlot(*getNextMachineInstr(std::next(I)))) { - InsertNop = true; - } else { - // Next instruction in the physical successor basic block. - for (auto *Succ : FI->successors()) { - if (FI->isLayoutSuccessor(Succ) && - getNextMachineInstr(Succ->begin()) != Succ->end() && - !TII->SafeInForbiddenSlot(*getNextMachineInstr(Succ->begin()))) { - InsertNop = true; - break; - } - } + Iter Inst; + bool LastInstInFunction = + std::next(I) == FI->end() && std::next(FI) == MF.end(); + if (!LastInstInFunction) { + Inst = getNextMachineInstr(std::next(I), &*FI); } - if (InsertNop) { + if (LastInstInFunction || !TII->SafeInForbiddenSlot(*Inst)) { Changed = true; - MIBundleBuilder(&*I).append( - BuildMI(MF, I->getDebugLoc(), TII->get(Mips::NOP))); + MIBundleBuilder(&*I) + .append(BuildMI(MF, I->getDebugLoc(), TII->get(Mips::NOP))); NumInsertedNops++; } } diff --git a/contrib/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp b/contrib/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp index 83763a6..0e1173f 100644 --- a/contrib/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -108,8 +108,26 @@ bool MipsDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base, return false; } -bool MipsDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base, - SDValue &Offset) const { +bool MipsDAGToDAGISel::selectIntAddrSImm10(SDValue Addr, SDValue &Base, + SDValue &Offset) const { + llvm_unreachable("Unimplemented function."); + return false; +} + +bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base, + SDValue &Offset) const { + llvm_unreachable("Unimplemented function."); + return false; +} + +bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base, + SDValue &Offset) const { + llvm_unreachable("Unimplemented function."); + return false; +} + +bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base, + SDValue &Offset) const { llvm_unreachable("Unimplemented function."); return false; } diff --git a/contrib/llvm/lib/Target/Mips/MipsISelDAGToDAG.h b/contrib/llvm/lib/Target/Mips/MipsISelDAGToDAG.h index 289832a..20bdd4a 100644 --- a/contrib/llvm/lib/Target/Mips/MipsISelDAGToDAG.h +++ b/contrib/llvm/lib/Target/Mips/MipsISelDAGToDAG.h @@ -35,7 +35,7 @@ public: : SelectionDAGISel(TM, OL), Subtarget(nullptr) {} // Pass Name - const char *getPassName() const override { + StringRef getPassName() const override { return "MIPS DAG->DAG Pattern Instruction Selection"; } @@ -78,8 +78,17 @@ private: SDValue &Offset) const; /// Match addr+simm10 and addr - virtual bool selectIntAddrMSA(SDValue Addr, SDValue &Base, - SDValue &Offset) const; + virtual bool selectIntAddrSImm10(SDValue Addr, SDValue &Base, + SDValue &Offset) const; + + virtual bool selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base, + SDValue &Offset) const; + + virtual bool selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base, + SDValue &Offset) const; + + virtual bool selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base, + SDValue &Offset) const; virtual bool selectAddr16(SDValue Addr, SDValue &Base, SDValue &Offset); virtual bool selectAddr16SP(SDValue Addr, SDValue &Base, SDValue &Offset); diff --git a/contrib/llvm/lib/Target/Mips/MipsISelLowering.cpp b/contrib/llvm/lib/Target/Mips/MipsISelLowering.cpp index d63a62a..9c511bd 100644 --- a/contrib/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -268,7 +268,7 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); // Mips Custom Operations - setOperationAction(ISD::BR_JT, MVT::Other, Custom); + setOperationAction(ISD::BR_JT, MVT::Other, Expand); setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); setOperationAction(ISD::BlockAddress, MVT::i32, Custom); setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); @@ -426,6 +426,13 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, setTargetDAGCombine(ISD::ADD); setTargetDAGCombine(ISD::AssertZext); + if (ABI.IsO32()) { + // These libcalls are not available in 32-bit. + setLibcallName(RTLIB::SHL_I128, nullptr); + setLibcallName(RTLIB::SRL_I128, nullptr); + setLibcallName(RTLIB::SRA_I128, nullptr); + } + setMinFunctionAlignment(Subtarget.isGP64bit() ? 3 : 2); // The arguments on the stack are defined in terms of 4-byte slots on O32 @@ -451,9 +458,19 @@ const MipsTargetLowering *MipsTargetLowering::create(const MipsTargetMachine &TM FastISel * MipsTargetLowering::createFastISel(FunctionLoweringInfo &funcInfo, const TargetLibraryInfo *libInfo) const { - if (!funcInfo.MF->getTarget().Options.EnableFastISel) - return TargetLowering::createFastISel(funcInfo, libInfo); - return Mips::createFastISel(funcInfo, libInfo); + const MipsTargetMachine &TM = + static_cast<const MipsTargetMachine &>(funcInfo.MF->getTarget()); + + // We support only the standard encoding [MIPS32,MIPS32R5] ISAs. + bool UseFastISel = TM.Options.EnableFastISel && Subtarget.hasMips32() && + !Subtarget.hasMips32r6() && !Subtarget.inMips16Mode() && + !Subtarget.inMicroMipsMode(); + + // Disable if we don't generate PIC or the ABI isn't O32. + if (!TM.isPositionIndependent() || !TM.getABI().IsO32()) + UseFastISel = false; + + return UseFastISel ? Mips::createFastISel(funcInfo, libInfo) : nullptr; } EVT MipsTargetLowering::getSetCCResultType(const DataLayout &, LLVMContext &, @@ -893,7 +910,6 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch (Op.getOpcode()) { - case ISD::BR_JT: return lowerBR_JT(Op, DAG); case ISD::BRCOND: return lowerBRCOND(Op, DAG); case ISD::ConstantPool: return lowerConstantPool(Op, DAG); case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); @@ -1659,40 +1675,6 @@ MachineBasicBlock *MipsTargetLowering::emitSEL_D(MachineInstr &MI, return BB; } -//===----------------------------------------------------------------------===// -// Misc Lower Operation implementation -//===----------------------------------------------------------------------===// -SDValue MipsTargetLowering::lowerBR_JT(SDValue Op, SelectionDAG &DAG) const { - SDValue Chain = Op.getOperand(0); - SDValue Table = Op.getOperand(1); - SDValue Index = Op.getOperand(2); - SDLoc DL(Op); - auto &TD = DAG.getDataLayout(); - EVT PTy = getPointerTy(TD); - unsigned EntrySize = - DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD); - - Index = DAG.getNode(ISD::MUL, DL, PTy, Index, - DAG.getConstant(EntrySize, DL, PTy)); - SDValue Addr = DAG.getNode(ISD::ADD, DL, PTy, Index, Table); - - EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); - Addr = DAG.getExtLoad( - ISD::SEXTLOAD, DL, PTy, Chain, Addr, - MachinePointerInfo::getJumpTable(DAG.getMachineFunction()), MemVT); - Chain = Addr.getValue(1); - - if (isPositionIndependent() || ABI.IsN64()) { - // For PIC, the sequence is: - // BRIND(load(Jumptable + index) + RelocBase) - // RelocBase can be JumpTable, GOT or some sort of global base. - Addr = DAG.getNode(ISD::ADD, DL, PTy, Addr, - getPICJumpTableRelocBase(Table, DAG)); - } - - return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr); -} - SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { // The first operand is the chain, the second is the condition, the third is // the block to branch to if the condition is true. @@ -1755,7 +1737,8 @@ SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, const MipsTargetObjectFile *TLOF = static_cast<const MipsTargetObjectFile *>( getTargetMachine().getObjFileLowering()); - if (TLOF->IsGlobalInSmallSection(GV, getTargetMachine())) + const GlobalObject *GO = GV->getBaseObject(); + if (GO && TLOF->IsGlobalInSmallSection(GO, getTargetMachine())) // %gp_rel relocation return getAddrGPRel(N, SDLoc(N), Ty, DAG); @@ -2099,8 +2082,8 @@ lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && "Frame address can only be determined for current frame."); - MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); - MFI->setFrameAddressIsTaken(true); + MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); + MFI.setFrameAddressIsTaken(true); EVT VT = Op.getValueType(); SDLoc DL(Op); SDValue FrameAddr = DAG.getCopyFromReg( @@ -2118,10 +2101,10 @@ SDValue MipsTargetLowering::lowerRETURNADDR(SDValue Op, "Return address can be determined only for current frame."); MachineFunction &MF = DAG.getMachineFunction(); - MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineFrameInfo &MFI = MF.getFrameInfo(); MVT VT = Op.getSimpleValueType(); unsigned RA = ABI.IsN64() ? Mips::RA_64 : Mips::RA; - MFI->setReturnAddressIsTaken(true); + MFI.setReturnAddressIsTaken(true); // Return RA, which contains the return address. Mark it an implicit live-in. unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); @@ -2398,9 +2381,9 @@ SDValue MipsTargetLowering::lowerEH_DWARF_CFA(SDValue Op, // Return a fixed StackObject with offset 0 which points to the old stack // pointer. - MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); + MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); EVT ValTy = Op->getValueType(0); - int FI = MFI->CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); + int FI = MFI.CreateFixedObject(Op.getValueSizeInBits() / 8, 0, false); return DAG.getFrameIndex(FI, ValTy); } @@ -2563,8 +2546,8 @@ SDValue MipsTargetLowering::passArgOnStack(SDValue StackPtr, unsigned Offset, return DAG.getStore(Chain, DL, Arg, PtrOff, MachinePointerInfo()); } - MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); - int FI = MFI->CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); + MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); + int FI = MFI.CreateFixedObject(Arg.getValueSizeInBits() / 8, Offset, false); SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); return DAG.getStore(Chain, DL, Arg, FIN, MachinePointerInfo(), /* Alignment = */ 0, MachineMemOperand::MOVolatile); @@ -2647,7 +2630,7 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, bool IsVarArg = CLI.IsVarArg; MachineFunction &MF = DAG.getMachineFunction(); - MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineFrameInfo &MFI = MF.getFrameInfo(); const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); bool IsPIC = isPositionIndependent(); @@ -2667,11 +2650,20 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, // Get a count of how many bytes are to be pushed on the stack. unsigned NextStackOffset = CCInfo.getNextStackOffset(); - // Check if it's really possible to do a tail call. - if (IsTailCall) + // Check if it's really possible to do a tail call. Restrict it to functions + // that are part of this compilation unit. + bool InternalLinkage = false; + if (IsTailCall) { IsTailCall = isEligibleForTailCallOptimization( CCInfo, NextStackOffset, *MF.getInfo<MipsFunctionInfo>()); - + if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { + InternalLinkage = G->getGlobal()->hasInternalLinkage(); + IsTailCall &= (InternalLinkage || G->getGlobal()->hasLocalLinkage() || + G->getGlobal()->hasPrivateLinkage() || + G->getGlobal()->hasHiddenVisibility() || + G->getGlobal()->hasProtectedVisibility()); + } + } if (!IsTailCall && CLI.CS && CLI.CS->isMustTailCall()) report_fatal_error("failed to perform tail call elimination on a call " "site marked musttail"); @@ -2754,19 +2746,19 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, break; case CCValAssign::SExtUpper: UseUpperBits = true; - // Fallthrough + LLVM_FALLTHROUGH; case CCValAssign::SExt: Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, LocVT, Arg); break; case CCValAssign::ZExtUpper: UseUpperBits = true; - // Fallthrough + LLVM_FALLTHROUGH; case CCValAssign::ZExt: Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, LocVT, Arg); break; case CCValAssign::AExtUpper: UseUpperBits = true; - // Fallthrough + LLVM_FALLTHROUGH; case CCValAssign::AExt: Arg = DAG.getNode(ISD::ANY_EXTEND, DL, LocVT, Arg); break; @@ -2806,9 +2798,9 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, // node so that legalize doesn't hack it. bool IsPICCall = (ABI.IsN64() || IsPIC); // true if calls are translated to // jalr $25 - bool GlobalOrExternal = false, InternalLinkage = false, IsCallReloc = false; SDValue CalleeLo; EVT Ty = Callee.getValueType(); + bool GlobalOrExternal = false, IsCallReloc = false; if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { if (IsPICCall) { @@ -2859,8 +2851,10 @@ MipsTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, InternalLinkage, IsCallReloc, CLI, Callee, Chain); - if (IsTailCall) + if (IsTailCall) { + MF.getFrameInfo().setHasTailCall(); return DAG.getNode(MipsISD::TailCall, DL, MVT::Other, Ops); + } Chain = DAG.getNode(MipsISD::JmpLink, DL, NodeTys, Ops); SDValue InFlag = Chain.getValue(1); @@ -3006,7 +3000,7 @@ SDValue MipsTargetLowering::LowerFormalArguments( const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { MachineFunction &MF = DAG.getMachineFunction(); - MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineFrameInfo &MFI = MF.getFrameInfo(); MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); MipsFI->setVarArgsFrameIndex(0); @@ -3105,8 +3099,8 @@ SDValue MipsTargetLowering::LowerFormalArguments( assert(VA.isMemLoc()); // The stack pointer offset is relative to the caller stack frame. - int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8, - VA.getLocMemOffset(), true); + int FI = MFI.CreateFixedObject(LocVT.getSizeInBits() / 8, + VA.getLocMemOffset(), true); // Create load nodes to retrieve arguments from the stack SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); @@ -3224,19 +3218,19 @@ MipsTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, break; case CCValAssign::AExtUpper: UseUpperBits = true; - // Fallthrough + LLVM_FALLTHROUGH; case CCValAssign::AExt: Val = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Val); break; case CCValAssign::ZExtUpper: UseUpperBits = true; - // Fallthrough + LLVM_FALLTHROUGH; case CCValAssign::ZExt: Val = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Val); break; case CCValAssign::SExtUpper: UseUpperBits = true; - // Fallthrough + LLVM_FALLTHROUGH; case CCValAssign::SExt: Val = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Val); break; @@ -3706,7 +3700,7 @@ void MipsTargetLowering::copyByValRegs( unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, MipsCCState &State) const { MachineFunction &MF = DAG.getMachineFunction(); - MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineFrameInfo &MFI = MF.getFrameInfo(); unsigned GPRSizeInBytes = Subtarget.getGPRSizeInBytes(); unsigned NumRegs = LastReg - FirstReg; unsigned RegAreaSize = NumRegs * GPRSizeInBytes; @@ -3723,7 +3717,7 @@ void MipsTargetLowering::copyByValRegs( // Create frame object. EVT PtrTy = getPointerTy(DAG.getDataLayout()); - int FI = MFI->CreateFixedObject(FrameObjSize, FrameObjOffset, true); + int FI = MFI.CreateFixedObject(FrameObjSize, FrameObjOffset, true); SDValue FIN = DAG.getFrameIndex(FI, PtrTy); InVals.push_back(FIN); @@ -3751,7 +3745,7 @@ void MipsTargetLowering::passByValArg( SDValue Chain, const SDLoc &DL, std::deque<std::pair<unsigned, SDValue>> &RegsToPass, SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, - MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, + MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, const CCValAssign &VA) const { unsigned ByValSizeInBytes = Flags.getByValSize(); @@ -3853,7 +3847,7 @@ void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, MVT RegTy = MVT::getIntegerVT(RegSizeInBytes * 8); const TargetRegisterClass *RC = getRegClassFor(RegTy); MachineFunction &MF = DAG.getMachineFunction(); - MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineFrameInfo &MFI = MF.getFrameInfo(); MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); // Offset of the first variable argument from stack pointer. @@ -3869,7 +3863,7 @@ void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, // Record the frame index of the first variable argument // which is a value necessary to VASTART. - int FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true); + int FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); MipsFI->setVarArgsFrameIndex(FI); // Copy the integer registers that have not been used for argument passing @@ -3880,7 +3874,7 @@ void MipsTargetLowering::writeVarArgRegs(std::vector<SDValue> &OutChains, ++I, VaArgOffset += RegSizeInBytes) { unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegTy); - FI = MFI->CreateFixedObject(RegSizeInBytes, VaArgOffset, true); + FI = MFI.CreateFixedObject(RegSizeInBytes, VaArgOffset, true); SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout())); SDValue Store = DAG.getStore(Chain, DL, ArgValue, PtrOff, MachinePointerInfo()); diff --git a/contrib/llvm/lib/Target/Mips/MipsISelLowering.h b/contrib/llvm/lib/Target/Mips/MipsISelLowering.h index 2ded118..cddf090 100644 --- a/contrib/llvm/lib/Target/Mips/MipsISelLowering.h +++ b/contrib/llvm/lib/Target/Mips/MipsISelLowering.h @@ -296,6 +296,10 @@ namespace llvm { return SrcAS < 256 && DestAS < 256; } + bool isJumpTableRelative() const override { + return getTargetMachine().isPositionIndependent() || ABI.IsN64(); + } + protected: SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const; @@ -426,7 +430,6 @@ namespace llvm { TargetLowering::CallLoweringInfo &CLI) const; // Lower Operand specifics - SDValue lowerBR_JT(SDValue Op, SelectionDAG &DAG) const; SDValue lowerBRCOND(SDValue Op, SelectionDAG &DAG) const; SDValue lowerConstantPool(SDValue Op, SelectionDAG &DAG) const; SDValue lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; @@ -471,7 +474,7 @@ namespace llvm { void passByValArg(SDValue Chain, const SDLoc &DL, std::deque<std::pair<unsigned, SDValue>> &RegsToPass, SmallVectorImpl<SDValue> &MemOpChains, SDValue StackPtr, - MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, + MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, unsigned LastReg, const ISD::ArgFlagsTy &Flags, bool isLittle, const CCValAssign &VA) const; diff --git a/contrib/llvm/lib/Target/Mips/MipsInstrFPU.td b/contrib/llvm/lib/Target/Mips/MipsInstrFPU.td index 87b02bd..df42d56 100644 --- a/contrib/llvm/lib/Target/Mips/MipsInstrFPU.td +++ b/contrib/llvm/lib/Target/Mips/MipsInstrFPU.td @@ -219,6 +219,7 @@ class BC1F_FT<string opstr, DAGOperand opnd, InstrItinClass Itin, let isTerminator = 1; let hasDelaySlot = DelaySlot; let Defs = [AT]; + let hasFCCRegOperand = 1; } class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin, @@ -229,41 +230,106 @@ class CEQS_FT<string typestr, RegisterClass RC, InstrItinClass Itin, !strconcat("c.$cond.", typestr)>, HARDFLOAT { let Defs = [FCC0]; let isCodeGenOnly = 1; + let hasFCCRegOperand = 1; } + +// Note: MIPS-IV introduced $fcc1-$fcc7 and renamed FCSR31[23] $fcc0. Rather +// duplicating the instruction definition for MIPS1 - MIPS3, we expand +// c.cond.ft if necessary, and reject it after constructing the +// instruction if the ISA doesn't support it. class C_COND_FT<string CondStr, string Typestr, RegisterOperand RC, InstrItinClass itin> : - InstSE<(outs), (ins RC:$fs, RC:$ft), - !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], itin, - FrmFR>, HARDFLOAT; + InstSE<(outs FCCRegsOpnd:$fcc), (ins RC:$fs, RC:$ft), + !strconcat("c.", CondStr, ".", Typestr, "\t$fcc, $fs, $ft"), [], itin, + FrmFR>, HARDFLOAT { + let isCompare = 1; + let hasFCCRegOperand = 1; +} + multiclass C_COND_M<string TypeStr, RegisterOperand RC, bits<5> fmt, InstrItinClass itin> { - def C_F_#NAME : C_COND_FT<"f", TypeStr, RC, itin>, C_COND_FM<fmt, 0>; - def C_UN_#NAME : C_COND_FT<"un", TypeStr, RC, itin>, C_COND_FM<fmt, 1>; - def C_EQ_#NAME : C_COND_FT<"eq", TypeStr, RC, itin>, C_COND_FM<fmt, 2>; - def C_UEQ_#NAME : C_COND_FT<"ueq", TypeStr, RC, itin>, C_COND_FM<fmt, 3>; - def C_OLT_#NAME : C_COND_FT<"olt", TypeStr, RC, itin>, C_COND_FM<fmt, 4>; - def C_ULT_#NAME : C_COND_FT<"ult", TypeStr, RC, itin>, C_COND_FM<fmt, 5>; - def C_OLE_#NAME : C_COND_FT<"ole", TypeStr, RC, itin>, C_COND_FM<fmt, 6>; - def C_ULE_#NAME : C_COND_FT<"ule", TypeStr, RC, itin>, C_COND_FM<fmt, 7>; - def C_SF_#NAME : C_COND_FT<"sf", TypeStr, RC, itin>, C_COND_FM<fmt, 8>; - def C_NGLE_#NAME : C_COND_FT<"ngle", TypeStr, RC, itin>, C_COND_FM<fmt, 9>; - def C_SEQ_#NAME : C_COND_FT<"seq", TypeStr, RC, itin>, C_COND_FM<fmt, 10>; - def C_NGL_#NAME : C_COND_FT<"ngl", TypeStr, RC, itin>, C_COND_FM<fmt, 11>; - def C_LT_#NAME : C_COND_FT<"lt", TypeStr, RC, itin>, C_COND_FM<fmt, 12>; - def C_NGE_#NAME : C_COND_FT<"nge", TypeStr, RC, itin>, C_COND_FM<fmt, 13>; - def C_LE_#NAME : C_COND_FT<"le", TypeStr, RC, itin>, C_COND_FM<fmt, 14>; - def C_NGT_#NAME : C_COND_FT<"ngt", TypeStr, RC, itin>, C_COND_FM<fmt, 15>; + def C_F_#NAME : MMRel, C_COND_FT<"f", TypeStr, RC, itin>, + C_COND_FM<fmt, 0> { + let BaseOpcode = "c.f."#NAME; + let isCommutable = 1; + } + def C_UN_#NAME : MMRel, C_COND_FT<"un", TypeStr, RC, itin>, + C_COND_FM<fmt, 1> { + let BaseOpcode = "c.un."#NAME; + let isCommutable = 1; + } + def C_EQ_#NAME : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>, + C_COND_FM<fmt, 2> { + let BaseOpcode = "c.eq."#NAME; + let isCommutable = 1; + } + def C_UEQ_#NAME : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>, + C_COND_FM<fmt, 3> { + let BaseOpcode = "c.ueq."#NAME; + let isCommutable = 1; + } + def C_OLT_#NAME : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>, + C_COND_FM<fmt, 4> { + let BaseOpcode = "c.olt."#NAME; + } + def C_ULT_#NAME : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>, + C_COND_FM<fmt, 5> { + let BaseOpcode = "c.ult."#NAME; + } + def C_OLE_#NAME : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>, + C_COND_FM<fmt, 6> { + let BaseOpcode = "c.ole."#NAME; + } + def C_ULE_#NAME : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>, + C_COND_FM<fmt, 7> { + let BaseOpcode = "c.ule."#NAME; + } + def C_SF_#NAME : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>, + C_COND_FM<fmt, 8> { + let BaseOpcode = "c.sf."#NAME; + let isCommutable = 1; + } + def C_NGLE_#NAME : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>, + C_COND_FM<fmt, 9> { + let BaseOpcode = "c.ngle."#NAME; + } + def C_SEQ_#NAME : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>, + C_COND_FM<fmt, 10> { + let BaseOpcode = "c.seq."#NAME; + let isCommutable = 1; + } + def C_NGL_#NAME : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>, + C_COND_FM<fmt, 11> { + let BaseOpcode = "c.ngl."#NAME; + } + def C_LT_#NAME : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>, + C_COND_FM<fmt, 12> { + let BaseOpcode = "c.lt."#NAME; + } + def C_NGE_#NAME : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>, + C_COND_FM<fmt, 13> { + let BaseOpcode = "c.nge."#NAME; + } + def C_LE_#NAME : MMRel, C_COND_FT<"le", TypeStr, RC, itin>, + C_COND_FM<fmt, 14> { + let BaseOpcode = "c.le."#NAME; + } + def C_NGT_#NAME : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>, + C_COND_FM<fmt, 15> { + let BaseOpcode = "c.ngt."#NAME; + } } +let AdditionalPredicates = [NotInMicroMips] in { defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6; defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, FGR_32; let DecoderNamespace = "Mips64" in defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, FGR_64; - +} //===----------------------------------------------------------------------===// // Floating Point Instructions //===----------------------------------------------------------------------===// @@ -284,6 +350,16 @@ defm CEIL_W : ROUND_M<"ceil.w.d", II_CEIL>, ABSS_FM<0xe, 17>, ISA_MIPS2; defm FLOOR_W : ROUND_M<"floor.w.d", II_FLOOR>, ABSS_FM<0xf, 17>, ISA_MIPS2; defm CVT_W : ROUND_M<"cvt.w.d", II_CVT>, ABSS_FM<0x24, 17>; +let AdditionalPredicates = [NotInMicroMips] in { + def RECIP_S : MMRel, ABSS_FT<"recip.s", FGR32Opnd, FGR32Opnd, II_RECIP_S>, + ABSS_FM<0b010101, 0x10>, INSN_MIPS4_32R2; + def RECIP_D : MMRel, ABSS_FT<"recip.d", FGR64Opnd, FGR64Opnd, II_RECIP_D>, + ABSS_FM<0b010101, 0x11>, INSN_MIPS4_32R2; + def RSQRT_S : MMRel, ABSS_FT<"rsqrt.s", FGR32Opnd, FGR32Opnd, II_RSQRT_S>, + ABSS_FM<0b010110, 0x10>, INSN_MIPS4_32R2; + def RSQRT_D : MMRel, ABSS_FT<"rsqrt.d", FGR64Opnd, FGR64Opnd, II_RSQRT_D>, + ABSS_FM<0b010110, 0x11>, INSN_MIPS4_32R2; +} let DecoderNamespace = "Mips64" in { let AdditionalPredicates = [NotInMicroMips] in { def ROUND_L_S : ABSS_FT<"round.l.s", FGR64Opnd, FGR32Opnd, II_ROUND>, @@ -361,8 +437,10 @@ defm FSQRT : ABSS_M<"sqrt.d", II_SQRT_D, fsqrt>, ABSS_FM<0x4, 17>, ISA_MIPS2; // regardless of register aliasing. /// Move Control Registers From/To CPU Registers -def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>; -def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>; +let AdditionalPredicates = [NotInMicroMips] in { + def CFC1 : MMRel, MFC1_FT<"cfc1", GPR32Opnd, CCROpnd, II_CFC1>, MFC1_FM<2>; + def CTC1 : MMRel, MTC1_FT<"ctc1", CCROpnd, GPR32Opnd, II_CTC1>, MFC1_FM<6>; +} def MFC1 : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, II_MFC1, bitconvert>, MFC1_FM<0>; def MTC1 : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, II_MTC1, @@ -537,13 +615,29 @@ def BC1TL : MMRel, BC1F_FT<"bc1tl", brtarget, II_BC1TL, MIPS_BRANCH_T, 0>, /// Floating Point Compare let AdditionalPredicates = [NotInMicroMips] in { def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>, - ISA_MIPS1_NOT_32R6_64R6; + ISA_MIPS1_NOT_32R6_64R6 { + + // FIXME: This is a required to work around the fact that these instructions + // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the + // fcc register set is used directly. + bits<3> fcc = 0; + } def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, - ISA_MIPS1_NOT_32R6_64R6, FGR_32; + ISA_MIPS1_NOT_32R6_64R6, FGR_32 { + // FIXME: This is a required to work around the fact that these instructions + // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the + // fcc register set is used directly. + bits<3> fcc = 0; + } } let DecoderNamespace = "Mips64" in def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, - ISA_MIPS1_NOT_32R6_64R6, FGR_64; + ISA_MIPS1_NOT_32R6_64R6, FGR_64 { + // FIXME: This is a required to work around the fact that thiese instructions + // only use $fcc0. Ideally, MipsFPCmp nodes could be removed and the + // fcc register set is used directly. + bits<3> fcc = 0; +} //===----------------------------------------------------------------------===// // Floating Point Pseudo-Instructions @@ -590,15 +684,99 @@ def PseudoTRUNC_W_D : MipsAsmPseudoInst<(outs FGR32Opnd:$fd), //===----------------------------------------------------------------------===// // InstAliases. //===----------------------------------------------------------------------===// -def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>, - ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT; -def : MipsInstAlias<"bc1tl $offset", (BC1TL FCC0, brtarget:$offset)>, - ISA_MIPS2_NOT_32R6_64R6, HARDFLOAT; -def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>, - ISA_MIPS1_NOT_32R6_64R6, HARDFLOAT; -def : MipsInstAlias<"bc1fl $offset", (BC1FL FCC0, brtarget:$offset)>, - ISA_MIPS2_NOT_32R6_64R6, HARDFLOAT; +def : MipsInstAlias + <"s.s $fd, $addr", (SWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>, + ISA_MIPS2, HARDFLOAT; +def : MipsInstAlias + <"s.d $fd, $addr", (SDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>, + FGR_32, ISA_MIPS2, HARDFLOAT; +def : MipsInstAlias + <"s.d $fd, $addr", (SDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>, + FGR_64, ISA_MIPS2, HARDFLOAT; + +def : MipsInstAlias + <"l.s $fd, $addr", (LWC1 FGR32Opnd:$fd, mem_simm16:$addr), 0>, + ISA_MIPS2, HARDFLOAT; +def : MipsInstAlias + <"l.d $fd, $addr", (LDC1 AFGR64Opnd:$fd, mem_simm16:$addr), 0>, + FGR_32, ISA_MIPS2, HARDFLOAT; +def : MipsInstAlias + <"l.d $fd, $addr", (LDC164 FGR64Opnd:$fd, mem_simm16:$addr), 0>, + FGR_64, ISA_MIPS2, HARDFLOAT; + +multiclass C_COND_ALIASES<string TypeStr, RegisterOperand RC> { + def : MipsInstAlias<!strconcat("c.f.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_F_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.un.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_UN_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.eq.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_EQ_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.ueq.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_UEQ_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.olt.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_OLT_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.ult.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_ULT_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.ole.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_OLE_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.ule.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_ULE_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.sf.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_SF_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.ngle.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_NGLE_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.seq.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_SEQ_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.ngl.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_NGL_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.lt.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_LT_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.nge.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_NGE_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.le.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_LE_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; + def : MipsInstAlias<!strconcat("c.ngt.", TypeStr, " $fs, $ft"), + (!cast<Instruction>("C_NGT_"#NAME) FCC0, + RC:$fs, RC:$ft), 1>; +} + +multiclass BC1_ALIASES<Instruction BCTrue, string BCTrueString, + Instruction BCFalse, string BCFalseString> { + def : MipsInstAlias<!strconcat(BCTrueString, " $offset"), + (BCTrue FCC0, brtarget:$offset), 1>; + + def : MipsInstAlias<!strconcat(BCFalseString, " $offset"), + (BCFalse FCC0, brtarget:$offset), 1>; +} +let AdditionalPredicates = [NotInMicroMips] in { + defm S : C_COND_ALIASES<"s", FGR32Opnd>, HARDFLOAT, + ISA_MIPS1_NOT_32R6_64R6; + defm D32 : C_COND_ALIASES<"d", AFGR64Opnd>, HARDFLOAT, + ISA_MIPS1_NOT_32R6_64R6, FGR_32; + defm D64 : C_COND_ALIASES<"d", FGR64Opnd>, HARDFLOAT, + ISA_MIPS1_NOT_32R6_64R6, FGR_64; + + defm : BC1_ALIASES<BC1T, "bc1t", BC1F, "bc1f">, ISA_MIPS1_NOT_32R6_64R6, + HARDFLOAT; + defm : BC1_ALIASES<BC1TL, "bc1tl", BC1FL, "bc1fl">, ISA_MIPS2_NOT_32R6_64R6, + HARDFLOAT; +} //===----------------------------------------------------------------------===// // Floating Point Patterns //===----------------------------------------------------------------------===// @@ -614,9 +792,9 @@ def : MipsPat<(f64 (sint_to_fp GPR32Opnd:$src)), (PseudoCVT_D32_W GPR32Opnd:$src)>, FGR_32; def : MipsPat<(MipsTruncIntFP AFGR64Opnd:$src), (TRUNC_W_D32 AFGR64Opnd:$src)>, FGR_32; -def : MipsPat<(f32 (fround AFGR64Opnd:$src)), +def : MipsPat<(f32 (fpround AFGR64Opnd:$src)), (CVT_S_D32 AFGR64Opnd:$src)>, FGR_32; -def : MipsPat<(f64 (fextend FGR32Opnd:$src)), +def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), (CVT_D32_S FGR32Opnd:$src)>, FGR_32; def : MipsPat<(f64 fpimm0), (DMTC1 ZERO_64)>, FGR_64; @@ -636,9 +814,9 @@ def : MipsPat<(MipsTruncIntFP FGR32Opnd:$src), def : MipsPat<(MipsTruncIntFP FGR64Opnd:$src), (TRUNC_L_D64 FGR64Opnd:$src)>, FGR_64; -def : MipsPat<(f32 (fround FGR64Opnd:$src)), +def : MipsPat<(f32 (fpround FGR64Opnd:$src)), (CVT_S_D64 FGR64Opnd:$src)>, FGR_64; -def : MipsPat<(f64 (fextend FGR32Opnd:$src)), +def : MipsPat<(f64 (fpextend FGR32Opnd:$src)), (CVT_D64_S FGR32Opnd:$src)>, FGR_64; // Patterns for loads/stores with a reg+imm operand. diff --git a/contrib/llvm/lib/Target/Mips/MipsInstrFormats.td b/contrib/llvm/lib/Target/Mips/MipsInstrFormats.td index 0bbb49b..817d9b4 100644 --- a/contrib/llvm/lib/Target/Mips/MipsInstrFormats.td +++ b/contrib/llvm/lib/Target/Mips/MipsInstrFormats.td @@ -98,11 +98,18 @@ class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern, bit isCTI = 0; // Any form of Control Transfer Instruction. // Required for MIPSR6 bit hasForbiddenSlot = 0; // Instruction has a forbidden slot. + bit IsPCRelativeLoad = 0; // Load instruction with implicit source register + // ($pc) and with explicit offset and destination + // register + bit hasFCCRegOperand = 0; // Instruction uses $fcc<X> register and is + // present in MIPS-I to MIPS-III. - // TSFlags layout should be kept in sync with MipsInstrInfo.h. + // TSFlags layout should be kept in sync with MCTargetDesc/MipsBaseInfo.h. let TSFlags{3-0} = FormBits; let TSFlags{4} = isCTI; let TSFlags{5} = hasForbiddenSlot; + let TSFlags{6} = IsPCRelativeLoad; + let TSFlags{7} = hasFCCRegOperand; let DecoderNamespace = "Mips"; @@ -825,6 +832,7 @@ class BC1F_FM<bit nd, bit tf> : StdArch { class CEQS_FM<bits<5> fmt> : StdArch { bits<5> fs; bits<5> ft; + bits<3> fcc; bits<4> cond; bits<32> Inst; @@ -833,7 +841,7 @@ class CEQS_FM<bits<5> fmt> : StdArch { let Inst{25-21} = fmt; let Inst{20-16} = ft; let Inst{15-11} = fs; - let Inst{10-8} = 0; // cc + let Inst{10-8} = fcc; let Inst{7-4} = 0x3; let Inst{3-0} = cond; } diff --git a/contrib/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/contrib/llvm/lib/Target/Mips/MipsInstrInfo.cpp index 800d834..19af191 100644 --- a/contrib/llvm/lib/Target/Mips/MipsInstrInfo.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsInstrInfo.cpp @@ -58,7 +58,7 @@ MachineMemOperand * MipsInstrInfo::GetMemOperand(MachineBasicBlock &MBB, int FI, MachineMemOperand::Flags Flags) const { MachineFunction &MF = *MBB.getParent(); - MachineFrameInfo &MFI = *MF.getFrameInfo(); + MachineFrameInfo &MFI = MF.getFrameInfo(); unsigned Align = MFI.getObjectAlignment(FI); return MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI), @@ -113,13 +113,15 @@ void MipsInstrInfo::BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MIB.addMBB(TBB); } -unsigned MipsInstrInfo::InsertBranch(MachineBasicBlock &MBB, +unsigned MipsInstrInfo::insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, - const DebugLoc &DL) const { + const DebugLoc &DL, + int *BytesAdded) const { // Shouldn't be a fall through. - assert(TBB && "InsertBranch must not be told to insert a fallthrough"); + assert(TBB && "insertBranch must not be told to insert a fallthrough"); + assert(!BytesAdded && "code size not handled"); // # of condition operands: // Unconditional branches: 0 @@ -145,16 +147,21 @@ unsigned MipsInstrInfo::InsertBranch(MachineBasicBlock &MBB, return 1; } -unsigned MipsInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { +unsigned MipsInstrInfo::removeBranch(MachineBasicBlock &MBB, + int *BytesRemoved) const { + assert(!BytesRemoved && "code size not handled"); + MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); - MachineBasicBlock::reverse_iterator FirstBr; unsigned removed; // Skip all the debug instructions. while (I != REnd && I->isDebugValue()) ++I; - FirstBr = I; + if (I == REnd) + return 0; + + MachineBasicBlock::iterator FirstBr = ++I.getReverse(); // Up to 2 branches are removed. // Note that indirect branches are not removed. @@ -162,14 +169,14 @@ unsigned MipsInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { if (!getAnalyzableBrOpc(I->getOpcode())) break; - MBB.erase(I.base(), FirstBr.base()); + MBB.erase((--I).getReverse(), FirstBr); return removed; } -/// ReverseBranchCondition - Return the inverse opcode of the +/// reverseBranchCondition - Return the inverse opcode of the /// specified Branch instruction. -bool MipsInstrInfo::ReverseBranchCondition( +bool MipsInstrInfo::reverseBranchCondition( SmallVectorImpl<MachineOperand> &Cond) const { assert( (Cond.size() && Cond.size() <= 3) && "Invalid Mips branch condition!"); @@ -269,7 +276,9 @@ unsigned MipsInstrInfo::getEquivalentCompactForm( if (Subtarget.inMicroMipsMode()) { switch (Opcode) { case Mips::BNE: + case Mips::BNE_MM: case Mips::BEQ: + case Mips::BEQ_MM: // microMIPS has NE,EQ branches that do not have delay slots provided one // of the operands is zero. if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg()) @@ -280,6 +289,7 @@ unsigned MipsInstrInfo::getEquivalentCompactForm( case Mips::JR: case Mips::PseudoReturn: case Mips::PseudoIndirectBranch: + case Mips::TAILCALLREG: canUseShortMicroMipsCTI = true; break; } @@ -302,12 +312,14 @@ unsigned MipsInstrInfo::getEquivalentCompactForm( case Mips::BAL: return Mips::BALC; case Mips::BEQ: + case Mips::BEQ_MM: if (canUseShortMicroMipsCTI) return Mips::BEQZC_MM; else if (I->getOperand(0).getReg() == I->getOperand(1).getReg()) return 0; return Mips::BEQC; case Mips::BNE: + case Mips::BNE_MM: if (canUseShortMicroMipsCTI) return Mips::BNEZC_MM; else if (I->getOperand(0).getReg() == I->getOperand(1).getReg()) @@ -337,11 +349,28 @@ unsigned MipsInstrInfo::getEquivalentCompactForm( return Mips::BLTUC; case Mips::BLTZ: return Mips::BLTZC; + case Mips::BEQ64: + if (I->getOperand(0).getReg() == I->getOperand(1).getReg()) + return 0; + return Mips::BEQC64; + case Mips::BNE64: + if (I->getOperand(0).getReg() == I->getOperand(1).getReg()) + return 0; + return Mips::BNEC64; + case Mips::BGTZ64: + return Mips::BGTZC64; + case Mips::BGEZ64: + return Mips::BGEZC64; + case Mips::BLTZ64: + return Mips::BLTZC64; + case Mips::BLEZ64: + return Mips::BLEZC64; // For MIPSR6, the instruction 'jic' can be used for these cases. Some // tools will accept 'jrc reg' as an alias for 'jic 0, $reg'. case Mips::JR: case Mips::PseudoReturn: case Mips::PseudoIndirectBranch: + case Mips::TAILCALLREG: if (canUseShortMicroMipsCTI) return Mips::JRC16_MM; return Mips::JIC; @@ -350,6 +379,7 @@ unsigned MipsInstrInfo::getEquivalentCompactForm( case Mips::JR64: case Mips::PseudoReturn64: case Mips::PseudoIndirectBranch64: + case Mips::TAILCALLREG64: return Mips::JIC64; case Mips::JALR64Pseudo: return Mips::JIALC64; @@ -378,7 +408,7 @@ bool MipsInstrInfo::HasForbiddenSlot(const MachineInstr &MI) const { } /// Return the number of bytes of code the specified instruction may be. -unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const { +unsigned MipsInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { switch (MI.getOpcode()) { default: return MI.getDesc().getSize(); @@ -399,17 +429,22 @@ MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, MachineBasicBlock::iterator I) const { MachineInstrBuilder MIB; - // Certain branches have two forms: e.g beq $1, $zero, dst vs beqz $1, dest + // Certain branches have two forms: e.g beq $1, $zero, dest vs beqz $1, dest // Pick the zero form of the branch for readable assembly and for greater // branch distance in non-microMIPS mode. + // Additional MIPSR6 does not permit the use of register $zero for compact + // branches. // FIXME: Certain atomic sequences on mips64 generate 32bit references to // Mips::ZERO, which is incorrect. This test should be updated to use // Subtarget.getABI().GetZeroReg() when those atomic sequences and others // are fixed. - bool BranchWithZeroOperand = - (I->isBranch() && !I->isPseudo() && I->getOperand(1).isReg() && - (I->getOperand(1).getReg() == Mips::ZERO || - I->getOperand(1).getReg() == Mips::ZERO_64)); + int ZeroOperandPosition = -1; + bool BranchWithZeroOperand = false; + if (I->isBranch() && !I->isPseudo()) { + auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo(); + ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, false, TRI); + BranchWithZeroOperand = ZeroOperandPosition != -1; + } if (BranchWithZeroOperand) { switch (NewOpc) { @@ -425,6 +460,12 @@ MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, case Mips::BLTC: NewOpc = Mips::BLTZC; break; + case Mips::BEQC64: + NewOpc = Mips::BEQZC64; + break; + case Mips::BNEC64: + NewOpc = Mips::BNEZC64; + break; } } @@ -446,17 +487,11 @@ MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, MIB.addImm(0); - } else if (BranchWithZeroOperand) { - // For MIPSR6 and microMIPS branches with an explicit zero operand, copy - // everything after the zero. - MIB.addOperand(I->getOperand(0)); - - for (unsigned J = 2, E = I->getDesc().getNumOperands(); J < E; ++J) { - MIB.addOperand(I->getOperand(J)); - } } else { - // All other cases copy all other operands. for (unsigned J = 0, E = I->getDesc().getNumOperands(); J < E; ++J) { + if (BranchWithZeroOperand && (unsigned)ZeroOperandPosition == J) + continue; + MIB.addOperand(I->getOperand(J)); } } diff --git a/contrib/llvm/lib/Target/Mips/MipsInstrInfo.h b/contrib/llvm/lib/Target/Mips/MipsInstrInfo.h index 2e55012..347b918 100644 --- a/contrib/llvm/lib/Target/Mips/MipsInstrInfo.h +++ b/contrib/llvm/lib/Target/Mips/MipsInstrInfo.h @@ -55,14 +55,16 @@ public: SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override; - unsigned RemoveBranch(MachineBasicBlock &MBB) const override; + unsigned removeBranch(MachineBasicBlock &MBB, + int *BytesRemoved = nullptr) const override; - unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, + unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, - const DebugLoc &DL) const override; + const DebugLoc &DL, + int *BytesAdded = nullptr) const override; bool - ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; + reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; BranchType analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, @@ -92,7 +94,7 @@ public: virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0; /// Return the number of bytes of code the specified instruction may be. - unsigned GetInstSizeInBytes(const MachineInstr &MI) const; + unsigned getInstSizeInBytes(const MachineInstr &MI) const override; void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, diff --git a/contrib/llvm/lib/Target/Mips/MipsInstrInfo.td b/contrib/llvm/lib/Target/Mips/MipsInstrInfo.td index 296f6e9..5bc4833 100644 --- a/contrib/llvm/lib/Target/Mips/MipsInstrInfo.td +++ b/contrib/llvm/lib/Target/Mips/MipsInstrInfo.td @@ -157,6 +157,8 @@ def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">, AssemblerPredicate<"FeatureMips3_32r2">; def HasMips3 : Predicate<"Subtarget->hasMips3()">, AssemblerPredicate<"FeatureMips3">; +def NotMips3 : Predicate<"!Subtarget->hasMips3()">, + AssemblerPredicate<"!FeatureMips3">; def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">, AssemblerPredicate<"FeatureMips4_32">; def NotMips4_32 : Predicate<"!Subtarget->hasMips4_32()">, @@ -201,6 +203,8 @@ def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">, AssemblerPredicate<"FeatureMips16">; def HasCnMips : Predicate<"Subtarget->hasCnMips()">, AssemblerPredicate<"FeatureCnMips">; +def NotCnMips : Predicate<"!Subtarget->hasCnMips()">, + AssemblerPredicate<"!FeatureCnMips">; def RelocNotPIC : Predicate<"!TM.isPositionIndependent()">; def RelocPIC : Predicate<"TM.isPositionIndependent()">; def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">; @@ -242,6 +246,9 @@ class PTR_64 { list<Predicate> PTRPredicates = [IsPTR64bit]; } // subtractive predicate will hopefully keep us under the 32 predicate // limit long enough to develop an alternative way to handle P1||P2 // predicates. +class ISA_MIPS1_NOT_MIPS3 { + list<Predicate> InsnPredicates = [NotMips3]; +} class ISA_MIPS1_NOT_4_32 { list<Predicate> InsnPredicates = [NotMips4_32]; } @@ -300,6 +307,9 @@ class INSN_MIPS3_32_NOT_32R6_64R6 { // The portions of MIPS-III that were also added to MIPS32 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; } +// The portions of MIPS-IV that were also added to MIPS32. +class INSN_MIPS4_32 { list <Predicate> InsnPredicates = [HasMips4_32]; } + // The portions of MIPS-IV that were also added to MIPS32 but were removed in // MIPS32r6 and MIPS64r6. class INSN_MIPS4_32_NOT_32R6_64R6 { @@ -312,6 +322,11 @@ class INSN_MIPS4_32R2_NOT_32R6_64R6 { list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6]; } +// The portions of MIPS-IV that were also added to MIPS32r2. +class INSN_MIPS4_32R2 { + list<Predicate> InsnPredicates = [HasMips4_32r2]; +} + // The portions of MIPS-V that were also added to MIPS32r2 but were removed in // MIPS32r6 and MIPS64r6. class INSN_MIPS5_32R2_NOT_32R6_64R6 { @@ -322,6 +337,10 @@ class ASE_CNMIPS { list<Predicate> InsnPredicates = [HasCnMips]; } +class NOT_ASE_CNMIPS { + list<Predicate> InsnPredicates = [NotCnMips]; +} + class ASE_MIPS64_CNMIPS { list<Predicate> InsnPredicates = [HasMips64, HasCnMips]; } @@ -413,6 +432,15 @@ class ConstantSImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = [], let DiagnosticType = "SImm" # Bits # "_" # Offset; } +class SimmLslAsmOperandClass<int Bits, list<AsmOperandClass> Supers = [], + int Shift = 0> : AsmOperandClass { + let Name = "Simm" # Bits # "_Lsl" # Shift; + let RenderMethod = "addImmOperands"; + let PredicateMethod = "isScaledSImm<" # Bits # ", " # Shift # ">"; + let SuperClasses = Supers; + let DiagnosticType = "SImm" # Bits # "_Lsl" # Shift; +} + class ConstantUImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = [], int Offset = 0> : AsmOperandClass { let Name = "ConstantUImm" # Bits # "_" # Offset; @@ -450,6 +478,16 @@ class UImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []> let DiagnosticType = "UImm" # Bits; } +// Generic case - only to support certain assembly pseudo instructions. +class UImmAnyAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []> + : AsmOperandClass { + let Name = "ImmAny"; + let RenderMethod = "addConstantUImmOperands<32>"; + let PredicateMethod = "isSImm<" # Bits # ">"; + let SuperClasses = Supers; + let DiagnosticType = "ImmAny"; +} + // AsmOperandClasses require a strict ordering which is difficult to manage // as a hierarchy. Instead, we use a linear ordering and impose an order that // is in some places arbitrary. @@ -473,8 +511,13 @@ class UImmAsmOperandClass<int Bits, list<AsmOperandClass> Supers = []> // uimm5 < uimm5_64, and uimm5 < vsplat_uimm5 // This is entirely arbitrary. We need an ordering and what we pick is // unimportant since only one is possible for a given mnemonic. + +def UImm32CoercedAsmOperandClass : UImmAnyAsmOperandClass<33, []> { + let Name = "UImm32_Coerced"; + let DiagnosticType = "UImm32_Coerced"; +} def SImm32RelaxedAsmOperandClass - : SImmAsmOperandClass<32, []> { + : SImmAsmOperandClass<32, [UImm32CoercedAsmOperandClass]> { let Name = "SImm32_Relaxed"; let PredicateMethod = "isAnyImm<32>"; let DiagnosticType = "SImm32_Relaxed"; @@ -485,12 +528,29 @@ def ConstantUImm26AsmOperandClass : ConstantUImmAsmOperandClass<26, [SImm32AsmOperandClass]>; def ConstantUImm20AsmOperandClass : ConstantUImmAsmOperandClass<20, [ConstantUImm26AsmOperandClass]>; +def ConstantSImm19Lsl2AsmOperandClass : AsmOperandClass { + let Name = "SImm19Lsl2"; + let RenderMethod = "addImmOperands"; + let PredicateMethod = "isScaledSImm<19, 2>"; + let SuperClasses = [ConstantUImm20AsmOperandClass]; + let DiagnosticType = "SImm19_Lsl2"; +} def UImm16RelaxedAsmOperandClass : UImmAsmOperandClass<16, [ConstantUImm20AsmOperandClass]> { let Name = "UImm16_Relaxed"; let PredicateMethod = "isAnyImm<16>"; let DiagnosticType = "UImm16_Relaxed"; } +// Similar to the relaxed classes which take an SImm and render it as +// an UImm, this takes a UImm and renders it as an SImm. +def UImm16AltRelaxedAsmOperandClass + : SImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]> { + let Name = "UImm16_AltRelaxed"; + let PredicateMethod = "isUImm<16>"; + let DiagnosticType = "UImm16_AltRelaxed"; +} +// FIXME: One of these should probably have UImm16AsmOperandClass as the +// superclass instead of UImm16RelaxedasmOPerandClass. def UImm16AsmOperandClass : UImmAsmOperandClass<16, [UImm16RelaxedAsmOperandClass]>; def SImm16RelaxedAsmOperandClass @@ -611,6 +671,9 @@ def ConstantImmzAsmOperandClass : AsmOperandClass { let DiagnosticType = "Immz"; } +def Simm19Lsl2AsmOperand + : SimmLslAsmOperandClass<19, [], 2>; + def MipsJumpTargetAsmOperand : AsmOperandClass { let Name = "JumpTarget"; let ParserMethod = "parseJumpTarget"; @@ -645,7 +708,7 @@ def imm64: Operand<i64>; def simm19_lsl2 : Operand<i32> { let EncoderMethod = "getSimm19Lsl2Encoding"; let DecoderMethod = "DecodeSimm19Lsl2"; - let ParserMatchClass = MipsJumpTargetAsmOperand; + let ParserMatchClass = Simm19Lsl2AsmOperand; } def simm18_lsl3 : Operand<i32> { @@ -766,6 +829,11 @@ def uimm16_64_relaxed : Operand<i64> { !cast<AsmOperandClass>("UImm16RelaxedAsmOperandClass"); } +def uimm16_altrelaxed : Operand<i32> { + let PrintMethod = "printUImm<16>"; + let ParserMatchClass = + !cast<AsmOperandClass>("UImm16AltRelaxedAsmOperandClass"); +} // Like uimm5 but reports a less confusing error for 32-63 when // an instruction alias permits that. def uimm5_report_uimm6 : Operand<i32> { @@ -845,6 +913,10 @@ def simm16_64 : Operand<i64> { let ParserMatchClass = !cast<AsmOperandClass>("SImm16AsmOperandClass"); } +// like simm32 but coerces simm32 to uimm32. +def uimm32_coerced : Operand<i32> { + let ParserMatchClass = !cast<AsmOperandClass>("UImm32CoercedAsmOperandClass"); +} // Like simm32 but coerces uimm32 to simm32. def simm32_relaxed : Operand<i32> { let DecoderMethod = "DecodeSImmWithOffsetAndScale<32>"; @@ -1033,10 +1105,6 @@ def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>; // e.g. addi, andi def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>; -// Node immediate fits as 15-bit sign extended on target immediate. -// e.g. addi, andi -def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>; - // Node immediate fits as 7-bit zero extended on target immediate. def immZExt7 : PatLeaf<(imm), [{ return isUInt<7>(N->getZExtValue()); }]>; @@ -1052,11 +1120,23 @@ def immZExt16 : PatLeaf<(imm), [{ }], LO16>; // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared). -def immLow16Zero : PatLeaf<(imm), [{ +def immSExt32Low16Zero : PatLeaf<(imm), [{ int64_t Val = N->getSExtValue(); return isInt<32>(Val) && !(Val & 0xffff); }]>; +// Zero-extended 32-bit unsigned int with lower 16-bit cleared. +def immZExt32Low16Zero : PatLeaf<(imm), [{ + uint64_t Val = N->getZExtValue(); + return isUInt<32>(Val) && !(Val & 0xffff); +}]>; + +// Note immediate fits as a 32 bit signed extended on target immediate. +def immSExt32 : PatLeaf<(imm), [{ return isInt<32>(N->getSExtValue()); }]>; + +// Note immediate fits as a 32 bit zero extended on target immediate. +def immZExt32 : PatLeaf<(imm), [{ return isUInt<32>(N->getZExtValue()); }]>; + // shamt field must fit in 5 bits. def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>; @@ -1086,7 +1166,13 @@ def addrRegImm : def addrDefault : ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>; -def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>; +def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrSImm10", [frameindex]>; +def addrimm10lsl1 : ComplexPattern<iPTR, 2, "selectIntAddrSImm10Lsl1", + [frameindex]>; +def addrimm10lsl2 : ComplexPattern<iPTR, 2, "selectIntAddrSImm10Lsl2", + [frameindex]>; +def addrimm10lsl3 : ComplexPattern<iPTR, 2, "selectIntAddrSImm10Lsl3", + [frameindex]>; //===----------------------------------------------------------------------===// // Instructions specific format @@ -1352,14 +1438,12 @@ let isCall=1, hasDelaySlot=1, isCTI=1, Defs = [RA] in { let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1, hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT] in { - class TailCall<Instruction JumpInst> : + class TailCall<Instruction JumpInst, DAGOperand Opnd> : PseudoSE<(outs), (ins calltarget:$target), [], II_J>, - PseudoInstExpansion<(JumpInst jmptarget:$target)>; + PseudoInstExpansion<(JumpInst Opnd:$target)>; - class TailCallReg<RegisterOperand RO, Instruction JRInst, - RegisterOperand ResRO = RO> : - PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>, - PseudoInstExpansion<(JRInst ResRO:$rs)>; + class TailCallReg<RegisterOperand RO> : + MipsPseudo<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>; } class BAL_BR_Pseudo<Instruction RealInst> : @@ -1686,33 +1770,35 @@ let AdditionalPredicates = [NotInMicroMips] in { } def ADDi : MMRel, ArithLogicI<"addi", simm16_relaxed, GPR32Opnd, II_ADDI>, ADDI_FM<0x8>, ISA_MIPS1_NOT_32R6_64R6; -def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, - SLTI_FM<0xa>; -def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, - SLTI_FM<0xb>; +let AdditionalPredicates = [NotInMicroMips] in { + def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, + SLTI_FM<0xa>; + def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, + SLTI_FM<0xb>; +} def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16_relaxed>, LUI_FM; let AdditionalPredicates = [NotInMicroMips] in { -/// Arithmetic Instructions (3-Operand, R-Type) -def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>, - ADD_FM<0, 0x21>; -def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, - ADD_FM<0, 0x23>; + /// Arithmetic Instructions (3-Operand, R-Type) + def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>, + ADD_FM<0, 0x21>; + def SUBu : MMRel, StdMMR6Rel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>, + ADD_FM<0, 0x23>; } let Defs = [HI0, LO0] in def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>, ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6; def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd, 1, II_ADD>, ADD_FM<0, 0x20>; def SUB : MMRel, StdMMR6Rel, ArithLogicR<"sub", GPR32Opnd, 0, II_SUB>, ADD_FM<0, 0x22>; -def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; -def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; let AdditionalPredicates = [NotInMicroMips] in { -def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>, - ADD_FM<0, 0x24>; -def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>, - ADD_FM<0, 0x25>; -def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, - ADD_FM<0, 0x26>; -def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; + def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>; + def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>; + def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>, + ADD_FM<0, 0x24>; + def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>, + ADD_FM<0, 0x25>; + def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, + ADD_FM<0, 0x26>; + def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>; } /// Shift Instructions @@ -1794,11 +1880,10 @@ let DecoderNamespace = "COP3_" in { def SDC3 : SW_FT3<"sdc3", COP3Opnd, II_SDC3, store>, LW_FM<0x3f>, ISA_MIPS2; } -} -def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, - ISA_MIPS32; -def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2; + def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS2; + def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2; +} let AdditionalPredicates = [NotInMicroMips] in { def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd, uimm10, II_TEQ>, TEQ_FM<0x34>, ISA_MIPS2; @@ -1898,8 +1983,12 @@ def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>, def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd, 0>, BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6; def BAL_BR : BAL_BR_Pseudo<BGEZAL>; -def TAILCALL : TailCall<J>; -def TAILCALL_R : TailCallReg<GPR32Opnd, JR>; + +let Predicates = [NotInMicroMips] in { + def TAILCALL : TailCall<J, jmptarget>; +} + +def TAILCALLREG : TailCallReg<GPR32Opnd>; // Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA. @@ -2177,6 +2266,21 @@ def : MipsInstAlias<"dror $rd, $imm", def ABSMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs), "abs\t$rd, $rs">; +def SEQMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), + (ins GPR32Opnd:$rs, GPR32Opnd:$rt), + "seq $rd, $rs, $rt">, NOT_ASE_CNMIPS; + +def : MipsInstAlias<"seq $rd, $rs", + (SEQMacro GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rs), 0>, + NOT_ASE_CNMIPS; + +def SEQIMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), + (ins GPR32Opnd:$rs, simm32_relaxed:$imm), + "seq $rd, $rs, $imm">, NOT_ASE_CNMIPS; + +def : MipsInstAlias<"seq $rd, $imm", + (SEQIMacro GPR32Opnd:$rd, GPR32Opnd:$rd, simm32:$imm), 0>, + NOT_ASE_CNMIPS; //===----------------------------------------------------------------------===// // Instruction aliases //===----------------------------------------------------------------------===// @@ -2219,17 +2323,31 @@ def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>; def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32; def : MipsInstAlias<"neg $rt, $rs", (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; -def : MipsInstAlias<"negu $rt", - (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>; +def : MipsInstAlias<"neg $rt", + (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>; def : MipsInstAlias<"negu $rt, $rs", (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>; -def : MipsInstAlias< +def : MipsInstAlias<"negu $rt", + (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 1>; +let AdditionalPredicates = [NotInMicroMips] in { + def : MipsInstAlias< + "sgt $rd, $rs, $rt", + (SLT GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; + def : MipsInstAlias< + "sgt $rs, $rt", + (SLT GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; + def : MipsInstAlias< + "sgtu $rd, $rs, $rt", + (SLTu GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; + def : MipsInstAlias< + "sgtu $$rs, $rt", + (SLTu GPR32Opnd:$rs, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; + def : MipsInstAlias< "slt $rs, $rt, $imm", (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>; -def : MipsInstAlias< + def : MipsInstAlias< "sltu $rt, $rs, $imm", (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm32_relaxed:$imm), 0>; -let AdditionalPredicates = [NotInMicroMips] in { def : MipsInstAlias< "and $rs, $rt, $imm", (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm32_relaxed:$imm), 0>; @@ -2251,6 +2369,9 @@ let AdditionalPredicates = [NotInMicroMips] in { def : MipsInstAlias< "not $rt, $rs", (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>; + def : MipsInstAlias< + "not $rt", + (NOR GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>; def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>; } def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>; @@ -2310,6 +2431,16 @@ let AdditionalPredicates = [NotInMicroMips] in { (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; def : MipsInstAlias<"srl $rd, $rt, $rs", (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>; + def : MipsInstAlias<"sll $rd, $rt", + (SLLV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>; + def : MipsInstAlias<"sra $rd, $rt", + (SRAV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>; + def : MipsInstAlias<"srl $rd, $rt", + (SRLV GPR32Opnd:$rd, GPR32Opnd:$rd, GPR32Opnd:$rt), 0>; + def : MipsInstAlias<"seh $rd", (SEH GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, + ISA_MIPS32R2; + def : MipsInstAlias<"seb $rd", (SEB GPR32Opnd:$rd, GPR32Opnd:$rd), 0>, + ISA_MIPS32R2; } def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6; def : MipsInstAlias<"sync", @@ -2318,11 +2449,12 @@ def : MipsInstAlias<"sync", // Assembler Pseudo Instructions //===----------------------------------------------------------------------===// -// We use i32imm on li/la to defer range checking to the assembler. +// We use uimm32_coerced to accept a 33 bit signed number that is rendered into +// a 32 bit number. class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> : MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32), !strconcat(instr_asm, "\t$rt, $imm32")> ; -def LoadImm32 : LoadImmediate32<"li", i32imm, GPR32Opnd>; +def LoadImm32 : LoadImmediate32<"li", uimm32_coerced, GPR32Opnd>; class LoadAddressFromReg32<string instr_asm, Operand MemOpnd, RegisterOperand RO> : @@ -2441,6 +2573,18 @@ def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), "ulw\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6; +def Ush : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), + "ush\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6; + +def Usw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr), + "usw\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6; + +def LDMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), + (ins mem_simm16:$addr), "ld $rt, $addr">, + ISA_MIPS1_NOT_MIPS3; +def SDMacro : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), + (ins mem_simm16:$addr), "sd $rt, $addr">, + ISA_MIPS1_NOT_MIPS3; //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// @@ -2452,19 +2596,24 @@ class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> : class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> : MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>; +// Materialize constants. +multiclass MaterializeImms<ValueType VT, Register ZEROReg, + Instruction ADDiuOp, Instruction LUiOp, + Instruction ORiOp> { + // Small immediates -let AdditionalPredicates = [NotInMicroMips] in { -def : MipsPat<(i32 immSExt16:$in), - (ADDiu ZERO, imm:$in)>; -def : MipsPat<(i32 immZExt16:$in), - (ORi ZERO, imm:$in)>; -} -def : MipsPat<(i32 immLow16Zero:$in), - (LUi (HI16 imm:$in))>; +def : MipsPat<(VT immSExt16:$imm), (ADDiuOp ZEROReg, imm:$imm)>; +def : MipsPat<(VT immZExt16:$imm), (ORiOp ZEROReg, imm:$imm)>; + +// Bits 32-16 set, sign/zero extended. +def : MipsPat<(VT immSExt32Low16Zero:$imm), (LUiOp (HI16 imm:$imm))>; // Arbitrary immediates -def : MipsPat<(i32 imm:$imm), - (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>; +def : MipsPat<(VT immSExt32:$imm), (ORiOp (LUiOp (HI16 imm:$imm)), (LO16 imm:$imm))>; +} + +let AdditionalPredicates = [NotInMicroMips] in + defm : MaterializeImms<i32, ZERO, ADDiu, LUi, ORi>; // Carry MipsPatterns let AdditionalPredicates = [NotInMicroMips] in { @@ -2558,38 +2707,39 @@ let AdditionalPredicates = [NotInMicroMips] in { def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; // brcond patterns -multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp, - Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp, - Instruction SLTiuOp, Register ZEROReg> { +multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BEQOp1, + Instruction BNEOp, Instruction SLTOp, Instruction SLTuOp, + Instruction SLTiOp, Instruction SLTiuOp, + Register ZEROReg> { def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst), (BNEOp RC:$lhs, ZEROReg, bb:$dst)>; def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst), (BEQOp RC:$lhs, ZEROReg, bb:$dst)>; def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), - (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; + (BEQOp1 (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), - (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; + (BEQOp1 (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>; def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst), - (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; + (BEQOp1 (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst), - (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; + (BEQOp1 (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>; def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), - (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; + (BEQOp1 (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst), - (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; + (BEQOp1 (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>; def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), - (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; + (BEQOp1 (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), - (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; + (BEQOp1 (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>; def : MipsPat<(brcond RC:$cond, bb:$dst), (BNEOp RC:$cond, ZEROReg, bb:$dst)>; } - -defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; - +let AdditionalPredicates = [NotInMicroMips] in { + defm : BrcondPats<GPR32, BEQ, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>; +} def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst), (BLEZ i32:$lhs, bb:$dst)>; def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst), @@ -2608,11 +2758,12 @@ multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp, (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>; } -multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { +multiclass SetlePats<RegisterClass RC, Instruction XORiOp, Instruction SLTOp, + Instruction SLTuOp> { def : MipsPat<(setle RC:$lhs, RC:$rhs), - (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>; + (XORiOp (SLTOp RC:$rhs, RC:$lhs), 1)>; def : MipsPat<(setule RC:$lhs, RC:$rhs), - (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>; + (XORiOp (SLTuOp RC:$rhs, RC:$lhs), 1)>; } multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { @@ -2622,26 +2773,29 @@ multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { (SLTuOp RC:$rhs, RC:$lhs)>; } -multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { +multiclass SetgePats<RegisterClass RC, Instruction XORiOp, Instruction SLTOp, + Instruction SLTuOp> { def : MipsPat<(setge RC:$lhs, RC:$rhs), - (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>; + (XORiOp (SLTOp RC:$lhs, RC:$rhs), 1)>; def : MipsPat<(setuge RC:$lhs, RC:$rhs), - (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>; + (XORiOp (SLTuOp RC:$lhs, RC:$rhs), 1)>; } -multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp, - Instruction SLTiuOp> { +multiclass SetgeImmPats<RegisterClass RC, Instruction XORiOp, + Instruction SLTiOp, Instruction SLTiuOp> { def : MipsPat<(setge RC:$lhs, immSExt16:$rhs), - (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; + (XORiOp (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>; def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs), - (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; + (XORiOp (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>; } -defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>; -defm : SetlePats<GPR32, SLT, SLTu>; -defm : SetgtPats<GPR32, SLT, SLTu>; -defm : SetgePats<GPR32, SLT, SLTu>; -defm : SetgeImmPats<GPR32, SLTi, SLTiu>; +let AdditionalPredicates = [NotInMicroMips] in { + defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>; + defm : SetlePats<GPR32, XORi, SLT, SLTu>; + defm : SetgtPats<GPR32, SLT, SLTu>; + defm : SetgePats<GPR32, XORi, SLT, SLTu>; + defm : SetgeImmPats<GPR32, XORi, SLTi, SLTiu>; +} // bswap pattern def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>; diff --git a/contrib/llvm/lib/Target/Mips/MipsLongBranch.cpp b/contrib/llvm/lib/Target/Mips/MipsLongBranch.cpp index e721312..1087d0e 100644 --- a/contrib/llvm/lib/Target/Mips/MipsLongBranch.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsLongBranch.cpp @@ -66,15 +66,13 @@ namespace { : MachineFunctionPass(ID), TM(tm), IsPIC(TM.isPositionIndependent()), ABI(static_cast<const MipsTargetMachine &>(TM).getABI()) {} - const char *getPassName() const override { - return "Mips Long Branch"; - } + StringRef getPassName() const override { return "Mips Long Branch"; } bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: @@ -157,7 +155,7 @@ void MipsLongBranch::splitMBB(MachineBasicBlock *MBB) { MBB->addSuccessor(Tgt); MF->insert(std::next(MachineFunction::iterator(MBB)), NewMBB); - NewMBB->splice(NewMBB->end(), MBB, (++LastBr).base(), MBB->end()); + NewMBB->splice(NewMBB->end(), MBB, LastBr.getReverse(), MBB->end()); } // Fill MBBInfos. @@ -179,7 +177,7 @@ void MipsLongBranch::initMBBInfo() { // Compute size of MBB. for (MachineBasicBlock::instr_iterator MI = MBB->instr_begin(); MI != MBB->instr_end(); ++MI) - MBBInfos[I].Size += TII->GetInstSizeInBytes(*MI); + MBBInfos[I].Size += TII->getInstSizeInBytes(*MI); // Search for MBB's branch instruction. ReverseIter End = MBB->rend(); @@ -187,7 +185,7 @@ void MipsLongBranch::initMBBInfo() { if ((Br != End) && !Br->isIndirectBranch() && (Br->isConditionalBranch() || (Br->isUnconditionalBranch() && IsPIC))) - MBBInfos[I].Br = &*(++Br).base(); + MBBInfos[I].Br = &*Br; } } diff --git a/contrib/llvm/lib/Target/Mips/MipsMSAInstrInfo.td b/contrib/llvm/lib/Target/Mips/MipsMSAInstrInfo.td index deb4345..8b04fcb 100644 --- a/contrib/llvm/lib/Target/Mips/MipsMSAInstrInfo.td +++ b/contrib/llvm/lib/Target/Mips/MipsMSAInstrInfo.td @@ -389,10 +389,6 @@ def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt), def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt), (fmul node:$ws, (fexp2 node:$wt))>; -// Immediates -def immSExt5 : ImmLeaf<i32, [{return isInt<5>(Imm);}]>; -def immSExt10: ImmLeaf<i32, [{return isInt<10>(Imm);}]>; - // Instruction encoding. class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>; class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>; @@ -2308,9 +2304,12 @@ class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, } class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd, mem_simm10>; -class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd, mem_simm10_lsl1>; -class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd, mem_simm10_lsl2>; -class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd, mem_simm10_lsl3>; +class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd, + mem_simm10_lsl1, addrimm10lsl1>; +class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd, + mem_simm10_lsl2, addrimm10lsl2>; +class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd, + mem_simm10_lsl3, addrimm10lsl3>; class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>; class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>; @@ -2641,9 +2640,12 @@ class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode, } class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd, mem_simm10>; -class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd, mem_simm10_lsl1>; -class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd, mem_simm10_lsl2>; -class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd, mem_simm10_lsl3>; +class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd, + mem_simm10_lsl1, addrimm10lsl1>; +class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd, + mem_simm10_lsl2, addrimm10lsl2>; +class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd, + mem_simm10_lsl3, addrimm10lsl3>; class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b, MSA128BOpnd>; @@ -3523,16 +3525,16 @@ class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> : def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx), (COPY_S_W MSA128W:$ws, immZExt4:$idx)>; -def : MSAPat<(v8f16 (load addrimm10:$addr)), (LD_H addrimm10:$addr)>; -def : MSAPat<(v4f32 (load addrimm10:$addr)), (LD_W addrimm10:$addr)>; -def : MSAPat<(v2f64 (load addrimm10:$addr)), (LD_D addrimm10:$addr)>; +def : MSAPat<(v8f16 (load addrimm10lsl1:$addr)), (LD_H addrimm10lsl1:$addr)>; +def : MSAPat<(v4f32 (load addrimm10lsl2:$addr)), (LD_W addrimm10lsl2:$addr)>; +def : MSAPat<(v2f64 (load addrimm10lsl3:$addr)), (LD_D addrimm10lsl3:$addr)>; -def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10:$addr), - (ST_H MSA128H:$ws, addrimm10:$addr)>; -def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10:$addr), - (ST_W MSA128W:$ws, addrimm10:$addr)>; -def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10:$addr), - (ST_D MSA128D:$ws, addrimm10:$addr)>; +def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10lsl1:$addr), + (ST_H MSA128H:$ws, addrimm10lsl1:$addr)>; +def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10lsl2:$addr), + (ST_W MSA128W:$ws, addrimm10lsl2:$addr)>; +def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10lsl3:$addr), + (ST_D MSA128D:$ws, addrimm10lsl3:$addr)>; class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD, RegisterOperand ROWS = ROWD, @@ -3729,6 +3731,56 @@ def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64, def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8, MSA128B, NoItinerary>; +// Pseudoes used to implement transparent fp16 support. + +let Predicates = [HasMSA] in { + def ST_F16 : MipsPseudo<(outs), (ins MSA128F16:$ws, mem_simm10:$addr), + [(store (f16 MSA128F16:$ws), (addrimm10:$addr))]> { + let usesCustomInserter = 1; + } + + def LD_F16 : MipsPseudo<(outs MSA128F16:$ws), (ins mem_simm10:$addr), + [(set MSA128F16:$ws, (f16 (load addrimm10:$addr)))]> { + let usesCustomInserter = 1; + } + + def MSA_FP_EXTEND_W_PSEUDO : MipsPseudo<(outs FGR32Opnd:$fd), + (ins MSA128F16:$ws), + [(set FGR32Opnd:$fd, + (f32 (fpextend MSA128F16:$ws)))]> { + let usesCustomInserter = 1; + } + + def MSA_FP_ROUND_W_PSEUDO : MipsPseudo<(outs MSA128F16:$wd), + (ins FGR32Opnd:$fs), + [(set MSA128F16:$wd, + (f16 (fpround FGR32Opnd:$fs)))]> { + let usesCustomInserter = 1; + } + + def MSA_FP_EXTEND_D_PSEUDO : MipsPseudo<(outs FGR64Opnd:$fd), + (ins MSA128F16:$ws), + [(set FGR64Opnd:$fd, + (f64 (fpextend MSA128F16:$ws)))]> { + let usesCustomInserter = 1; + } + + def MSA_FP_ROUND_D_PSEUDO : MipsPseudo<(outs MSA128F16:$wd), + (ins FGR64Opnd:$fs), + [(set MSA128F16:$wd, + (f16 (fpround FGR64Opnd:$fs)))]> { + let usesCustomInserter = 1; + } + + def : MipsPat<(MipsTruncIntFP MSA128F16:$ws), + (TRUNC_W_D64 (MSA_FP_EXTEND_D_PSEUDO MSA128F16:$ws))>; + + def : MipsPat<(MipsFPCmp MSA128F16:$ws, MSA128F16:$wt, imm:$cond), + (FCMP_S32 (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$ws), + (MSA_FP_EXTEND_W_PSEUDO MSA128F16:$wt), imm:$cond)>, + ISA_MIPS1_NOT_32R6_64R6; +} + // Vector extraction with fixed index. // // Extracting 32-bit values on MSA32 should always use COPY_S_W rather than diff --git a/contrib/llvm/lib/Target/Mips/MipsMachineFunction.cpp b/contrib/llvm/lib/Target/Mips/MipsMachineFunction.cpp index f81e64e..d0609b1 100644 --- a/contrib/llvm/lib/Target/Mips/MipsMachineFunction.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsMachineFunction.cpp @@ -60,7 +60,7 @@ void MipsFunctionInfo::createEhDataRegsFI() { ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; - EhDataRegFI[I] = MF.getFrameInfo()->CreateStackObject(RC->getSize(), + EhDataRegFI[I] = MF.getFrameInfo().CreateStackObject(RC->getSize(), RC->getAlignment(), false); } } @@ -68,12 +68,12 @@ void MipsFunctionInfo::createEhDataRegsFI() { void MipsFunctionInfo::createISRRegFI() { // ISRs require spill slots for Status & ErrorPC Coprocessor 0 registers. // The current implementation only supports Mips32r2+ not Mips64rX. Status - // is always 32 bits, ErrorPC is 32 or 64 bits dependant on architecture, + // is always 32 bits, ErrorPC is 32 or 64 bits dependent on architecture, // however Mips32r2+ is the supported architecture. const TargetRegisterClass *RC = &Mips::GPR32RegClass; for (int I = 0; I < 2; ++I) - ISRDataRegFI[I] = MF.getFrameInfo()->CreateStackObject( + ISRDataRegFI[I] = MF.getFrameInfo().CreateStackObject( RC->getSize(), RC->getAlignment(), false); } @@ -95,7 +95,7 @@ MachinePointerInfo MipsFunctionInfo::callPtrInfo(const GlobalValue *GV) { int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) { if (MoveF64ViaSpillFI == -1) { - MoveF64ViaSpillFI = MF.getFrameInfo()->CreateStackObject( + MoveF64ViaSpillFI = MF.getFrameInfo().CreateStackObject( RC->getSize(), RC->getAlignment(), false); } return MoveF64ViaSpillFI; diff --git a/contrib/llvm/lib/Target/Mips/MipsModuleISelDAGToDAG.cpp b/contrib/llvm/lib/Target/Mips/MipsModuleISelDAGToDAG.cpp index b18a673..cf85eb3 100644 --- a/contrib/llvm/lib/Target/Mips/MipsModuleISelDAGToDAG.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsModuleISelDAGToDAG.cpp @@ -26,7 +26,7 @@ namespace { : MachineFunctionPass(ID), TM(TM_) {} // Pass Name - const char *getPassName() const override { + StringRef getPassName() const override { return "MIPS DAG->DAG Pattern Instruction Selection"; } diff --git a/contrib/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp b/contrib/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp index 7c940ee..f33857f 100644 --- a/contrib/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsOptimizePICCall.cpp @@ -61,7 +61,7 @@ class OptimizePICCall : public MachineFunctionPass { public: OptimizePICCall(TargetMachine &tm) : MachineFunctionPass(ID) {} - const char *getPassName() const override { return "Mips OptimizePICCall"; } + StringRef getPassName() const override { return "Mips OptimizePICCall"; } bool runOnMachineFunction(MachineFunction &F) override; diff --git a/contrib/llvm/lib/Target/Mips/MipsOs16.cpp b/contrib/llvm/lib/Target/Mips/MipsOs16.cpp index 8136907..51ac562 100644 --- a/contrib/llvm/lib/Target/Mips/MipsOs16.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsOs16.cpp @@ -35,9 +35,7 @@ namespace { MipsOs16() : ModulePass(ID) {} - const char *getPassName() const override { - return "MIPS Os16 Optimization"; - } + StringRef getPassName() const override { return "MIPS Os16 Optimization"; } bool runOnModule(Module &M) override; }; diff --git a/contrib/llvm/lib/Target/Mips/MipsRegisterInfo.cpp b/contrib/llvm/lib/Target/Mips/MipsRegisterInfo.cpp index 860cf9c..65be350 100644 --- a/contrib/llvm/lib/Target/Mips/MipsRegisterInfo.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsRegisterInfo.cpp @@ -206,7 +206,7 @@ getReservedRegs(const MachineFunction &MF) const { // allocate variable-sized objects at runtime. This should test the // same conditions as MipsFrameLowering::hasBP(). if (needsStackRealignment(MF) && - MF.getFrameInfo()->hasVarSizedObjects()) { + MF.getFrameInfo().hasVarSizedObjects()) { Reserved.set(Mips::S7); Reserved.set(Mips::S7_64); } @@ -281,8 +281,8 @@ eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, errs() << "<--------->\n" << MI); int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); - uint64_t stackSize = MF.getFrameInfo()->getStackSize(); - int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex); + uint64_t stackSize = MF.getFrameInfo().getStackSize(); + int64_t spOffset = MF.getFrameInfo().getObjectOffset(FrameIndex); DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n" << "spOffset : " << spOffset << "\n" diff --git a/contrib/llvm/lib/Target/Mips/MipsRegisterInfo.td b/contrib/llvm/lib/Target/Mips/MipsRegisterInfo.td index cfce7c8..8c82239 100644 --- a/contrib/llvm/lib/Target/Mips/MipsRegisterInfo.td +++ b/contrib/llvm/lib/Target/Mips/MipsRegisterInfo.td @@ -400,6 +400,8 @@ def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>, // This class allows us to represent this in codegen patterns. def FGRCC : RegisterClass<"Mips", [i32], 32, (sequence "F%u", 0, 31)>; +def MSA128F16 : RegisterClass<"Mips", [f16], 128, (sequence "W%u", 0, 31)>; + def MSA128B: RegisterClass<"Mips", [v16i8], 128, (sequence "W%u", 0, 31)>; def MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128, @@ -646,6 +648,10 @@ def COP3Opnd : RegisterOperand<COP3> { let ParserMatchClass = COP3AsmOperand; } +def MSA128F16Opnd : RegisterOperand<MSA128F16> { + let ParserMatchClass = MSA128AsmOperand; +} + def MSA128BOpnd : RegisterOperand<MSA128B> { let ParserMatchClass = MSA128AsmOperand; } diff --git a/contrib/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp b/contrib/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp index a7ddd77..4996d07 100644 --- a/contrib/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp @@ -374,7 +374,7 @@ MipsSEFrameLowering::MipsSEFrameLowering(const MipsSubtarget &STI) void MipsSEFrameLowering::emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const { assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported"); - MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineFrameInfo &MFI = MF.getFrameInfo(); MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); const MipsSEInstrInfo &TII = @@ -396,10 +396,10 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF, &Mips::GPR64RegClass : &Mips::GPR32RegClass; // First, compute final stack size. - uint64_t StackSize = MFI->getStackSize(); + uint64_t StackSize = MFI.getStackSize(); // No need to allocate space on the stack. - if (StackSize == 0 && !MFI->adjustsStack()) return; + if (StackSize == 0 && !MFI.adjustsStack()) return; MachineModuleInfo &MMI = MF.getMMI(); const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); @@ -409,7 +409,7 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF, TII.adjustStackPtr(SP, -StackSize, MBB, MBBI); // emit ".cfi_def_cfa_offset StackSize" - unsigned CFIIndex = MMI.addFrameInst( + unsigned CFIIndex = MF.addFrameInst( MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); @@ -417,7 +417,7 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF, if (MF.getFunction()->hasFnAttribute("interrupt")) emitInterruptPrologueStub(MF, MBB); - const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); + const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); if (CSI.size()) { // Find the instruction past the last instruction that saves a callee-saved @@ -429,7 +429,7 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF, // directives. for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(), E = CSI.end(); I != E; ++I) { - int64_t Offset = MFI->getObjectOffset(I->getFrameIdx()); + int64_t Offset = MFI.getObjectOffset(I->getFrameIdx()); unsigned Reg = I->getReg(); // If Reg is a double precision register, emit two cfa_offsets, @@ -443,12 +443,12 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF, if (!STI.isLittle()) std::swap(Reg0, Reg1); - unsigned CFIIndex = MMI.addFrameInst( + unsigned CFIIndex = MF.addFrameInst( MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); - CFIIndex = MMI.addFrameInst( + CFIIndex = MF.addFrameInst( MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); @@ -459,18 +459,18 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF, if (!STI.isLittle()) std::swap(Reg0, Reg1); - unsigned CFIIndex = MMI.addFrameInst( + unsigned CFIIndex = MF.addFrameInst( MCCFIInstruction::createOffset(nullptr, Reg0, Offset)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); - CFIIndex = MMI.addFrameInst( + CFIIndex = MF.addFrameInst( MCCFIInstruction::createOffset(nullptr, Reg1, Offset + 4)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); } else { // Reg is either in GPR32 or FGR32. - unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset( + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset( nullptr, MRI->getDwarfRegNum(Reg, 1), Offset)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); @@ -489,9 +489,9 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF, // Emit .cfi_offset directives for eh data registers. for (int I = 0; I < 4; ++I) { - int64_t Offset = MFI->getObjectOffset(MipsFI->getEhDataRegFI(I)); + int64_t Offset = MFI.getObjectOffset(MipsFI->getEhDataRegFI(I)); unsigned Reg = MRI->getDwarfRegNum(ABI.GetEhDataReg(I), true); - unsigned CFIIndex = MMI.addFrameInst( + unsigned CFIIndex = MF.addFrameInst( MCCFIInstruction::createOffset(nullptr, Reg, Offset)); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); @@ -505,7 +505,7 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF, .setMIFlag(MachineInstr::FrameSetup); // emit ".cfi_def_cfa_register $fp" - unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createDefCfaRegister( + unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaRegister( nullptr, MRI->getDwarfRegNum(FP, true))); BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) .addCFIIndex(CFIIndex); @@ -514,9 +514,9 @@ void MipsSEFrameLowering::emitPrologue(MachineFunction &MF, // addiu $Reg, $zero, -MaxAlignment // andi $sp, $sp, $Reg unsigned VR = MF.getRegInfo().createVirtualRegister(RC); - assert(isInt<16>(MFI->getMaxAlignment()) && + assert(isInt<16>(MFI.getMaxAlignment()) && "Function's alignment size requirement is not supported."); - int MaxAlign = -(int)MFI->getMaxAlignment(); + int MaxAlign = -(int)MFI.getMaxAlignment(); BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO) .addImm(MaxAlign); BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR); @@ -664,7 +664,7 @@ void MipsSEFrameLowering::emitInterruptPrologueStub( void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); - MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineFrameInfo &MFI = MF.getFrameInfo(); MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); const MipsSEInstrInfo &TII = @@ -684,7 +684,7 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF, // Find the first instruction that restores a callee-saved register. MachineBasicBlock::iterator I = MBBI; - for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i) + for (unsigned i = 0; i < MFI.getCalleeSavedInfo().size(); ++i) --I; // Insert instruction "move $sp, $fp" at this location. @@ -697,7 +697,7 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF, // Find first instruction that restores a callee-saved register. MachineBasicBlock::iterator I = MBBI; - for (unsigned i = 0; i < MFI->getCalleeSavedInfo().size(); ++i) + for (unsigned i = 0; i < MFI.getCalleeSavedInfo().size(); ++i) --I; // Insert instructions that restore eh data registers. @@ -711,7 +711,7 @@ void MipsSEFrameLowering::emitEpilogue(MachineFunction &MF, emitInterruptEpilogueStub(MF, MBB); // Get the number of bytes from FrameInfo - uint64_t StackSize = MFI->getStackSize(); + uint64_t StackSize = MFI.getStackSize(); if (!StackSize) return; @@ -754,16 +754,16 @@ void MipsSEFrameLowering::emitInterruptEpilogueStub( int MipsSEFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); + const MachineFrameInfo &MFI = MF.getFrameInfo(); MipsABIInfo ABI = STI.getABI(); - if (MFI->isFixedObjectIndex(FI)) + if (MFI.isFixedObjectIndex(FI)) FrameReg = hasFP(MF) ? ABI.GetFramePtr() : ABI.GetStackPtr(); else FrameReg = hasBP(MF) ? ABI.GetBasePtr() : ABI.GetStackPtr(); - return MFI->getObjectOffset(FI) + MFI->getStackSize() - - getOffsetOfLocalArea() + MFI->getOffsetAdjustment(); + return MFI.getObjectOffset(FI) + MFI.getStackSize() - + getOffsetOfLocalArea() + MFI.getOffsetAdjustment(); } bool MipsSEFrameLowering:: @@ -778,12 +778,12 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB, for (unsigned i = 0, e = CSI.size(); i != e; ++i) { // Add the callee-saved register as live-in. Do not add if the register is // RA and return address is taken, because it has already been added in - // method MipsTargetLowering::LowerRETURNADDR. + // method MipsTargetLowering::lowerRETURNADDR. // It's killed at the spill, unless the register is RA and return address // is taken. unsigned Reg = CSI[i].getReg(); bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA || Reg == Mips::RA_64) - && MF->getFrameInfo()->isReturnAddressTaken(); + && MF->getFrameInfo().isReturnAddressTaken(); if (!IsRAAndRetAddrIsTaken) EntryBlock->addLiveIn(Reg); @@ -819,14 +819,14 @@ spillCalleeSavedRegisters(MachineBasicBlock &MBB, bool MipsSEFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); + const MachineFrameInfo &MFI = MF.getFrameInfo(); // Reserve call frame if the size of the maximum call frame fits into 16-bit // immediate field and there are no variable sized objects on the stack. // Make sure the second register scavenger spill slot can be accessed with one // instruction. - return isInt<16>(MFI->getMaxCallFrameSize() + getStackAlignment()) && - !MFI->hasVarSizedObjects(); + return isInt<16>(MFI.getMaxCallFrameSize() + getStackAlignment()) && + !MFI.hasVarSizedObjects(); } /// Mark \p Reg and all registers aliasing it in the bitset. @@ -868,7 +868,7 @@ void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF, // mips64, it should be 64-bit, otherwise it should be 32-bt. const TargetRegisterClass *RC = STI.hasMips64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; - int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(), + int FI = MF.getFrameInfo().CreateStackObject(RC->getSize(), RC->getAlignment(), false); RS->addScavengingFrameIndex(FI); } @@ -882,7 +882,7 @@ void MipsSEFrameLowering::determineCalleeSaves(MachineFunction &MF, const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; - int FI = MF.getFrameInfo()->CreateStackObject(RC->getSize(), + int FI = MF.getFrameInfo().CreateStackObject(RC->getSize(), RC->getAlignment(), false); RS->addScavengingFrameIndex(FI); } diff --git a/contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp index d9528da..92d3c00 100644 --- a/contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp @@ -28,6 +28,7 @@ #include "llvm/IR/Instructions.h" #include "llvm/IR/Intrinsics.h" #include "llvm/IR/Type.h" +#include "llvm/IR/Dominators.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" @@ -43,6 +44,11 @@ bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) { return MipsDAGToDAGISel::runOnMachineFunction(MF); } +void MipsSEDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequired<DominatorTreeWrapperPass>(); + SelectionDAGISel::getAnalysisUsage(AU); +} + void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI, MachineFunction &MF) { MachineInstrBuilder MIB(MF, &MI); @@ -293,20 +299,25 @@ bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base, } /// Match frameindex+offset and frameindex|offset -bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, - SDValue &Offset, - unsigned OffsetBits) const { +bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset( + SDValue Addr, SDValue &Base, SDValue &Offset, unsigned OffsetBits, + unsigned ShiftAmount = 0) const { if (CurDAG->isBaseWithConstantOffset(Addr)) { ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)); - if (isIntN(OffsetBits, CN->getSExtValue())) { + if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) { EVT ValTy = Addr.getValueType(); // If the first operand is a FI, get the TargetFI Node - if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode> - (Addr.getOperand(0))) + if (FrameIndexSDNode *FIN = + dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); - else + else { Base = Addr.getOperand(0); + // If base is a FI, additional offset calculation is done in + // eliminateFrameIndex, otherwise we need to check the alignment + if (OffsetToAlignment(CN->getZExtValue(), 1ull << ShiftAmount) != 0) + return false; + } Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr), ValTy); @@ -392,17 +403,6 @@ bool MipsSEDAGToDAGISel::selectAddrRegImm9(SDValue Addr, SDValue &Base, return false; } -bool MipsSEDAGToDAGISel::selectAddrRegImm10(SDValue Addr, SDValue &Base, - SDValue &Offset) const { - if (selectAddrFrameIndex(Addr, Base, Offset)) - return true; - - if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10)) - return true; - - return false; -} - /// Used on microMIPS LWC2, LDC2, SWC2 and SDC2 instructions (11-bit offset) bool MipsSEDAGToDAGISel::selectAddrRegImm11(SDValue Addr, SDValue &Base, SDValue &Offset) const { @@ -478,15 +478,49 @@ bool MipsSEDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base, return selectAddrDefault(Addr, Base, Offset); } -bool MipsSEDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base, - SDValue &Offset) const { - if (selectAddrRegImm10(Addr, Base, Offset)) +bool MipsSEDAGToDAGISel::selectIntAddrSImm10(SDValue Addr, SDValue &Base, + SDValue &Offset) const { + + if (selectAddrFrameIndex(Addr, Base, Offset)) return true; - if (selectAddrDefault(Addr, Base, Offset)) + if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10)) return true; - return false; + return selectAddrDefault(Addr, Base, Offset); +} + +bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base, + SDValue &Offset) const { + if (selectAddrFrameIndex(Addr, Base, Offset)) + return true; + + if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 1)) + return true; + + return selectAddrDefault(Addr, Base, Offset); +} + +bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base, + SDValue &Offset) const { + if (selectAddrFrameIndex(Addr, Base, Offset)) + return true; + + if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 2)) + return true; + + return selectAddrDefault(Addr, Base, Offset); +} + +bool MipsSEDAGToDAGISel::selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base, + SDValue &Offset) const { + if (selectAddrFrameIndex(Addr, Base, Offset)) + return true; + + if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10, 3)) + return true; + + return selectAddrDefault(Addr, Base, Offset); } // Select constant vector splats. @@ -771,13 +805,13 @@ bool MipsSEDAGToDAGISel::trySelect(SDNode *Node) { case ISD::Constant: { const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node); + int64_t Imm = CN->getSExtValue(); unsigned Size = CN->getValueSizeInBits(0); - if (Size == 32) + if (isInt<32>(Imm)) break; MipsAnalyzeImmediate AnalyzeImm; - int64_t Imm = CN->getSExtValue(); const MipsAnalyzeImmediate::InstSeq &Seq = AnalyzeImm.Analyze(Imm, Size, false); diff --git a/contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h b/contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h index 0f08b72..f89a350 100644 --- a/contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h +++ b/contrib/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h @@ -28,6 +28,8 @@ private: bool runOnMachineFunction(MachineFunction &MF) override; + void getAnalysisUsage(AnalysisUsage &AU) const override; + void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI, MachineFunction &MF); @@ -44,7 +46,8 @@ private: bool selectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset) const; bool selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset, - unsigned OffsetBits) const; + unsigned OffsetBits, + unsigned ShiftAmount) const; bool selectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset) const override; @@ -58,9 +61,6 @@ private: bool selectAddrRegImm9(SDValue Addr, SDValue &Base, SDValue &Offset) const; - bool selectAddrRegImm10(SDValue Addr, SDValue &Base, - SDValue &Offset) const; - bool selectAddrRegImm11(SDValue Addr, SDValue &Base, SDValue &Offset) const; @@ -82,8 +82,17 @@ private: bool selectIntAddrLSL2MM(SDValue Addr, SDValue &Base, SDValue &Offset) const override; - bool selectIntAddrMSA(SDValue Addr, SDValue &Base, - SDValue &Offset) const override; + bool selectIntAddrSImm10(SDValue Addr, SDValue &Base, + SDValue &Offset) const override; + + bool selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base, + SDValue &Offset) const override; + + bool selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base, + SDValue &Offset) const override; + + bool selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base, + SDValue &Offset) const override; /// \brief Select constant vector splats. bool selectVSplat(SDNode *N, APInt &Imm, diff --git a/contrib/llvm/lib/Target/Mips/MipsSEISelLowering.cpp b/contrib/llvm/lib/Target/Mips/MipsSEISelLowering.cpp index 80c000d..f28e8b3 100644 --- a/contrib/llvm/lib/Target/Mips/MipsSEISelLowering.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsSEISelLowering.cpp @@ -14,11 +14,13 @@ #include "MipsMachineFunction.h" #include "MipsRegisterInfo.h" #include "MipsTargetMachine.h" +#include "llvm/ADT/APInt.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/IR/Intrinsics.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetInstrInfo.h" @@ -27,8 +29,8 @@ using namespace llvm; #define DEBUG_TYPE "mips-isel" static cl::opt<bool> -EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden, - cl::desc("MIPS: Enable tail calls."), cl::init(false)); +UseMipsTailCalls("mips-tail-calls", cl::Hidden, + cl::desc("MIPS: permit tail calls."), cl::init(false)); static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), cl::desc("Expand double precision loads and " @@ -92,6 +94,44 @@ MipsSETargetLowering::MipsSETargetLowering(const MipsTargetMachine &TM, addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass); addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass); + // f16 is a storage-only type, always promote it to f32. + addRegisterClass(MVT::f16, &Mips::MSA128HRegClass); + setOperationAction(ISD::SETCC, MVT::f16, Promote); + setOperationAction(ISD::BR_CC, MVT::f16, Promote); + setOperationAction(ISD::SELECT_CC, MVT::f16, Promote); + setOperationAction(ISD::SELECT, MVT::f16, Promote); + setOperationAction(ISD::FADD, MVT::f16, Promote); + setOperationAction(ISD::FSUB, MVT::f16, Promote); + setOperationAction(ISD::FMUL, MVT::f16, Promote); + setOperationAction(ISD::FDIV, MVT::f16, Promote); + setOperationAction(ISD::FREM, MVT::f16, Promote); + setOperationAction(ISD::FMA, MVT::f16, Promote); + setOperationAction(ISD::FNEG, MVT::f16, Promote); + setOperationAction(ISD::FABS, MVT::f16, Promote); + setOperationAction(ISD::FCEIL, MVT::f16, Promote); + setOperationAction(ISD::FCOPYSIGN, MVT::f16, Promote); + setOperationAction(ISD::FCOS, MVT::f16, Promote); + setOperationAction(ISD::FP_EXTEND, MVT::f16, Promote); + setOperationAction(ISD::FFLOOR, MVT::f16, Promote); + setOperationAction(ISD::FNEARBYINT, MVT::f16, Promote); + setOperationAction(ISD::FPOW, MVT::f16, Promote); + setOperationAction(ISD::FPOWI, MVT::f16, Promote); + setOperationAction(ISD::FRINT, MVT::f16, Promote); + setOperationAction(ISD::FSIN, MVT::f16, Promote); + setOperationAction(ISD::FSINCOS, MVT::f16, Promote); + setOperationAction(ISD::FSQRT, MVT::f16, Promote); + setOperationAction(ISD::FEXP, MVT::f16, Promote); + setOperationAction(ISD::FEXP2, MVT::f16, Promote); + setOperationAction(ISD::FLOG, MVT::f16, Promote); + setOperationAction(ISD::FLOG2, MVT::f16, Promote); + setOperationAction(ISD::FLOG10, MVT::f16, Promote); + setOperationAction(ISD::FROUND, MVT::f16, Promote); + setOperationAction(ISD::FTRUNC, MVT::f16, Promote); + setOperationAction(ISD::FMINNUM, MVT::f16, Promote); + setOperationAction(ISD::FMAXNUM, MVT::f16, Promote); + setOperationAction(ISD::FMINNAN, MVT::f16, Promote); + setOperationAction(ISD::FMAXNAN, MVT::f16, Promote); + setTargetDAGCombine(ISD::AND); setTargetDAGCombine(ISD::OR); setTargetDAGCombine(ISD::SRA); @@ -852,7 +892,7 @@ static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, APInt SplatValue, SplatUndef; unsigned SplatBitSize; bool HasAnyUndefs; - unsigned EltSize = Ty.getVectorElementType().getSizeInBits(); + unsigned EltSize = Ty.getScalarSizeInBits(); BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); if (!Subtarget.hasDSP()) @@ -1172,13 +1212,25 @@ MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, return emitFEXP2_W_1(MI, BB); case Mips::FEXP2_D_1_PSEUDO: return emitFEXP2_D_1(MI, BB); + case Mips::ST_F16: + return emitST_F16_PSEUDO(MI, BB); + case Mips::LD_F16: + return emitLD_F16_PSEUDO(MI, BB); + case Mips::MSA_FP_EXTEND_W_PSEUDO: + return emitFPEXTEND_PSEUDO(MI, BB, false); + case Mips::MSA_FP_ROUND_W_PSEUDO: + return emitFPROUND_PSEUDO(MI, BB, false); + case Mips::MSA_FP_EXTEND_D_PSEUDO: + return emitFPEXTEND_PSEUDO(MI, BB, true); + case Mips::MSA_FP_ROUND_D_PSEUDO: + return emitFPROUND_PSEUDO(MI, BB, true); } } bool MipsSETargetLowering::isEligibleForTailCallOptimization( const CCState &CCInfo, unsigned NextStackOffset, const MipsFunctionInfo &FI) const { - if (!EnableMipsTailCalls) + if (!UseMipsTailCalls) return false; // Exception has to be cleared with eret. @@ -1406,9 +1458,12 @@ static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) { return Result; } -static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) { - return DAG.getConstant(Op->getConstantOperandVal(ImmOp), SDLoc(Op), - Op->getValueType(0)); +static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG, + bool IsSigned = false) { + return DAG.getConstant( + APInt(Op->getValueType(0).getScalarType().getSizeInBits(), + Op->getConstantOperandVal(ImmOp), IsSigned), + SDLoc(Op), Op->getValueType(0)); } static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue, @@ -1504,7 +1559,7 @@ static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG) { static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) { SDLoc DL(Op); EVT ResTy = Op->getValueType(0); - APInt BitImm = APInt(ResTy.getVectorElementType().getSizeInBits(), 1) + APInt BitImm = APInt(ResTy.getScalarSizeInBits(), 1) << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue(); SDValue BitMask = DAG.getConstant(~BitImm, DL, ResTy); @@ -1514,8 +1569,8 @@ static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) { SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { SDLoc DL(Op); - - switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) { + unsigned Intrinsic = cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue(); + switch (Intrinsic) { default: return SDValue(); case Intrinsic::mips_shilo: @@ -1585,6 +1640,8 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, // binsli_x(IfClear, IfSet, nbits) -> (vselect LBitsMask, IfSet, IfClear) EVT VecTy = Op->getValueType(0); EVT EltTy = VecTy.getVectorElementType(); + if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits()) + report_fatal_error("Immediate out of range"); APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(), Op->getConstantOperandVal(3)); return DAG.getNode(ISD::VSELECT, DL, VecTy, @@ -1598,6 +1655,8 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, // binsri_x(IfClear, IfSet, nbits) -> (vselect RBitsMask, IfSet, IfClear) EVT VecTy = Op->getValueType(0); EVT EltTy = VecTy.getVectorElementType(); + if (Op->getConstantOperandVal(3) >= EltTy.getSizeInBits()) + report_fatal_error("Immediate out of range"); APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(), Op->getConstantOperandVal(3)); return DAG.getNode(ISD::VSELECT, DL, VecTy, @@ -1691,7 +1750,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_ceqi_w: case Intrinsic::mips_ceqi_d: return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), - lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ); + lowerMSASplatImm(Op, 2, DAG, true), ISD::SETEQ); case Intrinsic::mips_cle_s_b: case Intrinsic::mips_cle_s_h: case Intrinsic::mips_cle_s_w: @@ -1703,7 +1762,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_clei_s_w: case Intrinsic::mips_clei_s_d: return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), - lowerMSASplatImm(Op, 2, DAG), ISD::SETLE); + lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLE); case Intrinsic::mips_cle_u_b: case Intrinsic::mips_cle_u_h: case Intrinsic::mips_cle_u_w: @@ -1727,7 +1786,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_clti_s_w: case Intrinsic::mips_clti_s_d: return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), - lowerMSASplatImm(Op, 2, DAG), ISD::SETLT); + lowerMSASplatImm(Op, 2, DAG, true), ISD::SETLT); case Intrinsic::mips_clt_u_b: case Intrinsic::mips_clt_u_h: case Intrinsic::mips_clt_u_w: @@ -1940,15 +1999,28 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_insve_b: case Intrinsic::mips_insve_h: case Intrinsic::mips_insve_w: - case Intrinsic::mips_insve_d: + case Intrinsic::mips_insve_d: { + // Report an error for out of range values. + int64_t Max; + switch (Intrinsic) { + case Intrinsic::mips_insve_b: Max = 15; break; + case Intrinsic::mips_insve_h: Max = 7; break; + case Intrinsic::mips_insve_w: Max = 3; break; + case Intrinsic::mips_insve_d: Max = 1; break; + default: llvm_unreachable("Unmatched intrinsic"); + } + int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue(); + if (Value < 0 || Value > Max) + report_fatal_error("Immediate out of range"); return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0), Op->getOperand(1), Op->getOperand(2), Op->getOperand(3), DAG.getConstant(0, DL, MVT::i32)); + } case Intrinsic::mips_ldi_b: case Intrinsic::mips_ldi_h: case Intrinsic::mips_ldi_w: case Intrinsic::mips_ldi_d: - return lowerMSASplatImm(Op, 1, DAG); + return lowerMSASplatImm(Op, 1, DAG, true); case Intrinsic::mips_lsa: case Intrinsic::mips_dlsa: { EVT ResTy = Op->getValueType(0); @@ -1982,7 +2054,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_maxi_s_w: case Intrinsic::mips_maxi_s_d: return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0), - Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true)); case Intrinsic::mips_maxi_u_b: case Intrinsic::mips_maxi_u_h: case Intrinsic::mips_maxi_u_w: @@ -2006,7 +2078,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_mini_s_w: case Intrinsic::mips_mini_s_d: return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0), - Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG, true)); case Intrinsic::mips_mini_u_b: case Intrinsic::mips_mini_u_h: case Intrinsic::mips_mini_u_w: @@ -2079,11 +2151,59 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_pcnt_w: case Intrinsic::mips_pcnt_d: return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1)); + case Intrinsic::mips_sat_s_b: + case Intrinsic::mips_sat_s_h: + case Intrinsic::mips_sat_s_w: + case Intrinsic::mips_sat_s_d: + case Intrinsic::mips_sat_u_b: + case Intrinsic::mips_sat_u_h: + case Intrinsic::mips_sat_u_w: + case Intrinsic::mips_sat_u_d: { + // Report an error for out of range values. + int64_t Max; + switch (Intrinsic) { + case Intrinsic::mips_sat_s_b: + case Intrinsic::mips_sat_u_b: Max = 7; break; + case Intrinsic::mips_sat_s_h: + case Intrinsic::mips_sat_u_h: Max = 15; break; + case Intrinsic::mips_sat_s_w: + case Intrinsic::mips_sat_u_w: Max = 31; break; + case Intrinsic::mips_sat_s_d: + case Intrinsic::mips_sat_u_d: Max = 63; break; + default: llvm_unreachable("Unmatched intrinsic"); + } + int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue(); + if (Value < 0 || Value > Max) + report_fatal_error("Immediate out of range"); + return SDValue(); + } case Intrinsic::mips_shf_b: case Intrinsic::mips_shf_h: - case Intrinsic::mips_shf_w: + case Intrinsic::mips_shf_w: { + int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue(); + if (Value < 0 || Value > 255) + report_fatal_error("Immediate out of range"); return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0), Op->getOperand(2), Op->getOperand(1)); + } + case Intrinsic::mips_sldi_b: + case Intrinsic::mips_sldi_h: + case Intrinsic::mips_sldi_w: + case Intrinsic::mips_sldi_d: { + // Report an error for out of range values. + int64_t Max; + switch (Intrinsic) { + case Intrinsic::mips_sldi_b: Max = 15; break; + case Intrinsic::mips_sldi_h: Max = 7; break; + case Intrinsic::mips_sldi_w: Max = 3; break; + case Intrinsic::mips_sldi_d: Max = 1; break; + default: llvm_unreachable("Unmatched intrinsic"); + } + int64_t Value = cast<ConstantSDNode>(Op->getOperand(3))->getSExtValue(); + if (Value < 0 || Value > Max) + report_fatal_error("Immediate out of range"); + return SDValue(); + } case Intrinsic::mips_sll_b: case Intrinsic::mips_sll_h: case Intrinsic::mips_sll_w: @@ -2126,6 +2246,24 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_srai_d: return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_srari_b: + case Intrinsic::mips_srari_h: + case Intrinsic::mips_srari_w: + case Intrinsic::mips_srari_d: { + // Report an error for out of range values. + int64_t Max; + switch (Intrinsic) { + case Intrinsic::mips_srari_b: Max = 7; break; + case Intrinsic::mips_srari_h: Max = 15; break; + case Intrinsic::mips_srari_w: Max = 31; break; + case Intrinsic::mips_srari_d: Max = 63; break; + default: llvm_unreachable("Unmatched intrinsic"); + } + int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue(); + if (Value < 0 || Value > Max) + report_fatal_error("Immediate out of range"); + return SDValue(); + } case Intrinsic::mips_srl_b: case Intrinsic::mips_srl_h: case Intrinsic::mips_srl_w: @@ -2138,6 +2276,24 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, case Intrinsic::mips_srli_d: return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); + case Intrinsic::mips_srlri_b: + case Intrinsic::mips_srlri_h: + case Intrinsic::mips_srlri_w: + case Intrinsic::mips_srlri_d: { + // Report an error for out of range values. + int64_t Max; + switch (Intrinsic) { + case Intrinsic::mips_srlri_b: Max = 7; break; + case Intrinsic::mips_srlri_h: Max = 15; break; + case Intrinsic::mips_srlri_w: Max = 31; break; + case Intrinsic::mips_srlri_d: Max = 63; break; + default: llvm_unreachable("Unmatched intrinsic"); + } + int64_t Value = cast<ConstantSDNode>(Op->getOperand(2))->getSExtValue(); + if (Value < 0 || Value > Max) + report_fatal_error("Immediate out of range"); + return SDValue(); + } case Intrinsic::mips_subv_b: case Intrinsic::mips_subv_h: case Intrinsic::mips_subv_w: @@ -2169,7 +2325,8 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, } } -static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) { +static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, + const MipsSubtarget &Subtarget) { SDLoc DL(Op); SDValue ChainIn = Op->getOperand(0); SDValue Address = Op->getOperand(2); @@ -2177,6 +2334,12 @@ static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) { EVT ResTy = Op->getValueType(0); EVT PtrTy = Address->getValueType(0); + // For N64 addresses have the underlying type MVT::i64. This intrinsic + // however takes an i32 signed constant offset. The actual type of the + // intrinsic is a scaled signed i10. + if (Subtarget.isABI_N64()) + Offset = DAG.getNode(ISD::SIGN_EXTEND, DL, PtrTy, Offset); + Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset); return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), /* Alignment = */ 16); @@ -2232,11 +2395,12 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op, case Intrinsic::mips_ld_h: case Intrinsic::mips_ld_w: case Intrinsic::mips_ld_d: - return lowerMSALoadIntr(Op, DAG, Intr); + return lowerMSALoadIntr(Op, DAG, Intr, Subtarget); } } -static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) { +static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr, + const MipsSubtarget &Subtarget) { SDLoc DL(Op); SDValue ChainIn = Op->getOperand(0); SDValue Value = Op->getOperand(2); @@ -2244,6 +2408,12 @@ static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) { SDValue Offset = Op->getOperand(4); EVT PtrTy = Address->getValueType(0); + // For N64 addresses have the underlying type MVT::i64. This intrinsic + // however takes an i32 signed constant offset. The actual type of the + // intrinsic is a scaled signed i10. + if (Subtarget.isABI_N64()) + Offset = DAG.getNode(ISD::SIGN_EXTEND, DL, PtrTy, Offset); + Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset); return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), @@ -2260,7 +2430,7 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op, case Intrinsic::mips_st_h: case Intrinsic::mips_st_w: case Intrinsic::mips_st_d: - return lowerMSAStoreIntr(Op, DAG, Intr); + return lowerMSAStoreIntr(Op, DAG, Intr, Subtarget); } } @@ -3327,8 +3497,12 @@ MipsSETargetLowering::emitFILL_FW(MachineInstr &MI, DebugLoc DL = MI.getDebugLoc(); unsigned Wd = MI.getOperand(0).getReg(); unsigned Fs = MI.getOperand(1).getReg(); - unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); - unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); + unsigned Wt1 = RegInfo.createVirtualRegister( + Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass + : &Mips::MSA128WEvensRegClass); + unsigned Wt2 = RegInfo.createVirtualRegister( + Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass + : &Mips::MSA128WEvensRegClass); BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1); BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2) @@ -3372,6 +3546,304 @@ MipsSETargetLowering::emitFILL_FD(MachineInstr &MI, return BB; } +// Emit the ST_F16_PSEDUO instruction to store a f16 value from an MSA +// register. +// +// STF16 MSA128F16:$wd, mem_simm10:$addr +// => +// copy_u.h $rtemp,$wd[0] +// sh $rtemp, $addr +// +// Safety: We can't use st.h & co as they would over write the memory after +// the destination. It would require half floats be allocated 16 bytes(!) of +// space. +MachineBasicBlock * +MipsSETargetLowering::emitST_F16_PSEUDO(MachineInstr &MI, + MachineBasicBlock *BB) const { + + const TargetInstrInfo *TII = Subtarget.getInstrInfo(); + MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); + DebugLoc DL = MI.getDebugLoc(); + unsigned Ws = MI.getOperand(0).getReg(); + unsigned Rt = MI.getOperand(1).getReg(); + const MachineMemOperand &MMO = **MI.memoperands_begin(); + unsigned Imm = MMO.getOffset(); + + // Caution: A load via the GOT can expand to a GPR32 operand, a load via + // spill and reload can expand as a GPR64 operand. Examine the + // operand in detail and default to ABI. + const TargetRegisterClass *RC = + MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg()) + : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass + : &Mips::GPR64RegClass); + const bool UsingMips32 = RC == &Mips::GPR32RegClass; + unsigned Rs = RegInfo.createVirtualRegister(RC); + + BuildMI(*BB, MI, DL, TII->get(Mips::COPY_U_H), Rs).addReg(Ws).addImm(0); + BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::SH : Mips::SH64)) + .addReg(Rs) + .addReg(Rt) + .addImm(Imm) + .addMemOperand(BB->getParent()->getMachineMemOperand( + &MMO, MMO.getOffset(), MMO.getSize())); + + MI.eraseFromParent(); + return BB; +} + +// Emit the LD_F16_PSEDUO instruction to load a f16 value into an MSA register. +// +// LD_F16 MSA128F16:$wd, mem_simm10:$addr +// => +// lh $rtemp, $addr +// fill.h $wd, $rtemp +// +// Safety: We can't use ld.h & co as they over-read from the source. +// Additionally, if the address is not modulo 16, 2 cases can occur: +// a) Segmentation fault as the load instruction reads from a memory page +// memory it's not supposed to. +// b) The load crosses an implementation specific boundary, requiring OS +// intervention. +// +MachineBasicBlock * +MipsSETargetLowering::emitLD_F16_PSEUDO(MachineInstr &MI, + MachineBasicBlock *BB) const { + + const TargetInstrInfo *TII = Subtarget.getInstrInfo(); + MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); + DebugLoc DL = MI.getDebugLoc(); + unsigned Wd = MI.getOperand(0).getReg(); + + // Caution: A load via the GOT can expand to a GPR32 operand, a load via + // spill and reload can expand as a GPR64 operand. Examine the + // operand in detail and default to ABI. + const TargetRegisterClass *RC = + MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg()) + : (Subtarget.isABI_O32() ? &Mips::GPR32RegClass + : &Mips::GPR64RegClass); + + const bool UsingMips32 = RC == &Mips::GPR32RegClass; + unsigned Rt = RegInfo.createVirtualRegister(RC); + + MachineInstrBuilder MIB = + BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt); + for (unsigned i = 1; i < MI.getNumOperands(); i++) + MIB.addOperand(MI.getOperand(i)); + + BuildMI(*BB, MI, DL, TII->get(Mips::FILL_H), Wd).addReg(Rt); + + MI.eraseFromParent(); + return BB; +} + +// Emit the FPROUND_PSEUDO instruction. +// +// Round an FGR64Opnd, FGR32Opnd to an f16. +// +// Safety: Cycle the operand through the GPRs so the result always ends up +// the correct MSA register. +// +// FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fs +// / FGR64Opnd:$Fs and MSA128F16:$Wd to the same physical register +// (which they can be, as the MSA registers are defined to alias the +// FPU's 64 bit and 32 bit registers) the result can be accessed using +// the correct register class. That requires operands be tie-able across +// register classes which have a sub/super register class relationship. +// +// For FPG32Opnd: +// +// FPROUND MSA128F16:$wd, FGR32Opnd:$fs +// => +// mfc1 $rtemp, $fs +// fill.w $rtemp, $wtemp +// fexdo.w $wd, $wtemp, $wtemp +// +// For FPG64Opnd on mips32r2+: +// +// FPROUND MSA128F16:$wd, FGR64Opnd:$fs +// => +// mfc1 $rtemp, $fs +// fill.w $rtemp, $wtemp +// mfhc1 $rtemp2, $fs +// insert.w $wtemp[1], $rtemp2 +// insert.w $wtemp[3], $rtemp2 +// fexdo.w $wtemp2, $wtemp, $wtemp +// fexdo.h $wd, $temp2, $temp2 +// +// For FGR64Opnd on mips64r2+: +// +// FPROUND MSA128F16:$wd, FGR64Opnd:$fs +// => +// dmfc1 $rtemp, $fs +// fill.d $rtemp, $wtemp +// fexdo.w $wtemp2, $wtemp, $wtemp +// fexdo.h $wd, $wtemp2, $wtemp2 +// +// Safety note: As $wtemp is UNDEF, we may provoke a spurious exception if the +// undef bits are "just right" and the exception enable bits are +// set. By using fill.w to replicate $fs into all elements over +// insert.w for one element, we avoid that potiential case. If +// fexdo.[hw] causes an exception in, the exception is valid and it +// occurs for all elements. +// +MachineBasicBlock * +MipsSETargetLowering::emitFPROUND_PSEUDO(MachineInstr &MI, + MachineBasicBlock *BB, + bool IsFGR64) const { + + // Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous + // here. It's technically doable to support MIPS32 here, but the ISA forbids + // it. + assert(Subtarget.hasMSA() && Subtarget.hasMips32r2()); + + bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64; + + const TargetInstrInfo *TII = Subtarget.getInstrInfo(); + DebugLoc DL = MI.getDebugLoc(); + unsigned Wd = MI.getOperand(0).getReg(); + unsigned Fs = MI.getOperand(1).getReg(); + + MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); + unsigned Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); + const TargetRegisterClass *GPRRC = + IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; + unsigned MFC1Opc = IsFGR64onMips64 ? Mips::DMFC1 : Mips::MFC1; + unsigned FILLOpc = IsFGR64onMips64 ? Mips::FILL_D : Mips::FILL_W; + + // Perform the register class copy as mentioned above. + unsigned Rtemp = RegInfo.createVirtualRegister(GPRRC); + BuildMI(*BB, MI, DL, TII->get(MFC1Opc), Rtemp).addReg(Fs); + BuildMI(*BB, MI, DL, TII->get(FILLOpc), Wtemp).addReg(Rtemp); + unsigned WPHI = Wtemp; + + if (!Subtarget.hasMips64() && IsFGR64) { + unsigned Rtemp2 = RegInfo.createVirtualRegister(GPRRC); + BuildMI(*BB, MI, DL, TII->get(Mips::MFHC1_D64), Rtemp2).addReg(Fs); + unsigned Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); + unsigned Wtemp3 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); + BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp2) + .addReg(Wtemp) + .addReg(Rtemp2) + .addImm(1); + BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp3) + .addReg(Wtemp2) + .addReg(Rtemp2) + .addImm(3); + WPHI = Wtemp3; + } + + if (IsFGR64) { + unsigned Wtemp2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); + BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_W), Wtemp2) + .addReg(WPHI) + .addReg(WPHI); + WPHI = Wtemp2; + } + + BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_H), Wd).addReg(WPHI).addReg(WPHI); + + MI.eraseFromParent(); + return BB; +} + +// Emit the FPEXTEND_PSEUDO instruction. +// +// Expand an f16 to either a FGR32Opnd or FGR64Opnd. +// +// Safety: Cycle the result through the GPRs so the result always ends up +// the correct floating point register. +// +// FIXME: This copying is strictly unnecessary. If we could tie FGR32Opnd:$Fd +// / FGR64Opnd:$Fd and MSA128F16:$Ws to the same physical register +// (which they can be, as the MSA registers are defined to alias the +// FPU's 64 bit and 32 bit registers) the result can be accessed using +// the correct register class. That requires operands be tie-able across +// register classes which have a sub/super register class relationship. I +// haven't checked. +// +// For FGR32Opnd: +// +// FPEXTEND FGR32Opnd:$fd, MSA128F16:$ws +// => +// fexupr.w $wtemp, $ws +// copy_s.w $rtemp, $ws[0] +// mtc1 $rtemp, $fd +// +// For FGR64Opnd on Mips64: +// +// FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws +// => +// fexupr.w $wtemp, $ws +// fexupr.d $wtemp2, $wtemp +// copy_s.d $rtemp, $wtemp2s[0] +// dmtc1 $rtemp, $fd +// +// For FGR64Opnd on Mips32: +// +// FPEXTEND FGR64Opnd:$fd, MSA128F16:$ws +// => +// fexupr.w $wtemp, $ws +// fexupr.d $wtemp2, $wtemp +// copy_s.w $rtemp, $wtemp2[0] +// mtc1 $rtemp, $ftemp +// copy_s.w $rtemp2, $wtemp2[1] +// $fd = mthc1 $rtemp2, $ftemp +// +MachineBasicBlock * +MipsSETargetLowering::emitFPEXTEND_PSEUDO(MachineInstr &MI, + MachineBasicBlock *BB, + bool IsFGR64) const { + + // Strictly speaking, we need MIPS32R5 to support MSA. We'll be generous + // here. It's technically doable to support MIPS32 here, but the ISA forbids + // it. + assert(Subtarget.hasMSA() && Subtarget.hasMips32r2()); + + bool IsFGR64onMips64 = Subtarget.hasMips64() && IsFGR64; + bool IsFGR64onMips32 = !Subtarget.hasMips64() && IsFGR64; + + const TargetInstrInfo *TII = Subtarget.getInstrInfo(); + DebugLoc DL = MI.getDebugLoc(); + unsigned Fd = MI.getOperand(0).getReg(); + unsigned Ws = MI.getOperand(1).getReg(); + + MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); + const TargetRegisterClass *GPRRC = + IsFGR64onMips64 ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; + unsigned MTC1Opc = IsFGR64onMips64 ? Mips::DMTC1 : Mips::MTC1; + unsigned COPYOpc = IsFGR64onMips64 ? Mips::COPY_S_D : Mips::COPY_S_W; + + unsigned Wtemp = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); + unsigned WPHI = Wtemp; + + BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_W), Wtemp).addReg(Ws); + if (IsFGR64) { + WPHI = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); + BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_D), WPHI).addReg(Wtemp); + } + + // Perform the safety regclass copy mentioned above. + unsigned Rtemp = RegInfo.createVirtualRegister(GPRRC); + unsigned FPRPHI = IsFGR64onMips32 + ? RegInfo.createVirtualRegister(&Mips::FGR64RegClass) + : Fd; + BuildMI(*BB, MI, DL, TII->get(COPYOpc), Rtemp).addReg(WPHI).addImm(0); + BuildMI(*BB, MI, DL, TII->get(MTC1Opc), FPRPHI).addReg(Rtemp); + + if (IsFGR64onMips32) { + unsigned Rtemp2 = RegInfo.createVirtualRegister(GPRRC); + BuildMI(*BB, MI, DL, TII->get(Mips::COPY_S_W), Rtemp2) + .addReg(WPHI) + .addImm(1); + BuildMI(*BB, MI, DL, TII->get(Mips::MTHC1_D64), Fd) + .addReg(FPRPHI) + .addReg(Rtemp2); + } + + MI.eraseFromParent(); + return BB; +} + // Emit the FEXP2_W_1 pseudo instructions. // // fexp2_w_1_pseudo $wd, $wt diff --git a/contrib/llvm/lib/Target/Mips/MipsSEISelLowering.h b/contrib/llvm/lib/Target/Mips/MipsSEISelLowering.h index 5415466..0abb9b3 100644 --- a/contrib/llvm/lib/Target/Mips/MipsSEISelLowering.h +++ b/contrib/llvm/lib/Target/Mips/MipsSEISelLowering.h @@ -111,6 +111,20 @@ namespace llvm { /// \brief Emit the FEXP2_D_1 pseudo instructions. MachineBasicBlock *emitFEXP2_D_1(MachineInstr &MI, MachineBasicBlock *BB) const; + /// \brief Emit the FILL_FW pseudo instruction + MachineBasicBlock *emitLD_F16_PSEUDO(MachineInstr &MI, + MachineBasicBlock *BB) const; + /// \brief Emit the FILL_FD pseudo instruction + MachineBasicBlock *emitST_F16_PSEUDO(MachineInstr &MI, + MachineBasicBlock *BB) const; + /// \brief Emit the FEXP2_W_1 pseudo instructions. + MachineBasicBlock *emitFPEXTEND_PSEUDO(MachineInstr &MI, + MachineBasicBlock *BB, + bool IsFGR64) const; + /// \brief Emit the FEXP2_D_1 pseudo instructions. + MachineBasicBlock *emitFPROUND_PSEUDO(MachineInstr &MI, + MachineBasicBlock *BBi, + bool IsFGR64) const; }; } diff --git a/contrib/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/contrib/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp index 29107b2..ea703d0 100644 --- a/contrib/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp @@ -408,7 +408,9 @@ unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const { switch (Opc) { default: llvm_unreachable("Illegal opcode!"); case Mips::BEQ: return Mips::BNE; + case Mips::BEQ_MM: return Mips::BNE_MM; case Mips::BNE: return Mips::BEQ; + case Mips::BNE_MM: return Mips::BEQ_MM; case Mips::BGTZ: return Mips::BLEZ; case Mips::BGEZ: return Mips::BLTZ; case Mips::BLTZ: return Mips::BGEZ; @@ -431,6 +433,18 @@ unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const { case Mips::BGEZC: return Mips::BLTZC; case Mips::BLTZC: return Mips::BGEZC; case Mips::BLEZC: return Mips::BGTZC; + case Mips::BEQZC64: return Mips::BNEZC64; + case Mips::BNEZC64: return Mips::BEQZC64; + case Mips::BEQC64: return Mips::BNEC64; + case Mips::BNEC64: return Mips::BEQC64; + case Mips::BGEC64: return Mips::BLTC64; + case Mips::BGEUC64: return Mips::BLTUC64; + case Mips::BLTC64: return Mips::BGEC64; + case Mips::BLTUC64: return Mips::BGEUC64; + case Mips::BGTZC64: return Mips::BLEZC64; + case Mips::BGEZC64: return Mips::BLTZC64; + case Mips::BLTZC64: return Mips::BGEZC64; + case Mips::BLEZC64: return Mips::BGTZC64; } } @@ -506,17 +520,22 @@ unsigned MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB, } unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const { - return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ || - Opc == Mips::BGEZ || Opc == Mips::BLTZ || Opc == Mips::BLEZ || - Opc == Mips::BEQ64 || Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || - Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || - Opc == Mips::BC1T || Opc == Mips::BC1F || Opc == Mips::B || - Opc == Mips::J || Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM || - Opc == Mips::BEQC || Opc == Mips::BNEC || Opc == Mips::BLTC || - Opc == Mips::BGEC || Opc == Mips::BLTUC || Opc == Mips::BGEUC || - Opc == Mips::BGTZC || Opc == Mips::BLEZC || Opc == Mips::BGEZC || - Opc == Mips::BLTZC || Opc == Mips::BEQZC || Opc == Mips::BNEZC || - Opc == Mips::BC) ? Opc : 0; + return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE || + Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ || + Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 || + Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 || + Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T || + Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J || + Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || + Opc == Mips::BNEC || Opc == Mips::BLTC || Opc == Mips::BGEC || + Opc == Mips::BLTUC || Opc == Mips::BGEUC || Opc == Mips::BGTZC || + Opc == Mips::BLEZC || Opc == Mips::BGEZC || Opc == Mips::BLTZC || + Opc == Mips::BEQZC || Opc == Mips::BNEZC || Opc == Mips::BEQZC64 || + Opc == Mips::BNEZC64 || Opc == Mips::BEQC64 || Opc == Mips::BNEC64 || + Opc == Mips::BGEC64 || Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 || + Opc == Mips::BLTUC64 || Opc == Mips::BGTZC64 || + Opc == Mips::BGEZC64 || Opc == Mips::BLTZC64 || + Opc == Mips::BLEZC64 || Opc == Mips::BC) ? Opc : 0; } void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB, diff --git a/contrib/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp b/contrib/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp index e3431cd..86bd241 100644 --- a/contrib/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsSERegisterInfo.cpp @@ -149,7 +149,7 @@ void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II, int64_t SPOffset) const { MachineInstr &MI = *II; MachineFunction &MF = *MI.getParent()->getParent(); - MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineFrameInfo &MFI = MF.getFrameInfo(); MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); MipsABIInfo ABI = @@ -157,7 +157,7 @@ void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II, const MipsRegisterInfo *RegInfo = static_cast<const MipsRegisterInfo *>(MF.getSubtarget().getRegisterInfo()); - const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); + const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo(); int MinCSFI = 0; int MaxCSFI = -1; @@ -182,9 +182,9 @@ void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II, IsISRRegFI) FrameReg = ABI.GetStackPtr(); else if (RegInfo->needsStackRealignment(MF)) { - if (MFI->hasVarSizedObjects() && !MFI->isFixedObjectIndex(FrameIndex)) + if (MFI.hasVarSizedObjects() && !MFI.isFixedObjectIndex(FrameIndex)) FrameReg = ABI.GetBasePtr(); - else if (MFI->isFixedObjectIndex(FrameIndex)) + else if (MFI.isFixedObjectIndex(FrameIndex)) FrameReg = getFrameRegister(MF); else FrameReg = ABI.GetStackPtr(); diff --git a/contrib/llvm/lib/Target/Mips/MipsSchedule.td b/contrib/llvm/lib/Target/Mips/MipsSchedule.td index 738b6c4..c0de59b 100644 --- a/contrib/llvm/lib/Target/Mips/MipsSchedule.td +++ b/contrib/llvm/lib/Target/Mips/MipsSchedule.td @@ -44,6 +44,7 @@ def II_BC1FL : InstrItinClass; def II_BC1T : InstrItinClass; def II_BC1TL : InstrItinClass; def II_BC1CCZ : InstrItinClass; +def II_BC2CCZ : InstrItinClass; def II_BCC : InstrItinClass; // beq and bne def II_BCCZ : InstrItinClass; // b[gl][et]z def II_BCCC : InstrItinClass; // b<cc>c @@ -53,12 +54,18 @@ def II_BCCZC : InstrItinClass; // beqzc, bnezc def II_BITSWAP : InstrItinClass; def II_CEIL : InstrItinClass; def II_CFC1 : InstrItinClass; +def II_CFC2 : InstrItinClass; def II_CLO : InstrItinClass; def II_CLZ : InstrItinClass; def II_CTC1 : InstrItinClass; +def II_CTC2 : InstrItinClass; def II_CVT : InstrItinClass; def II_C_CC_D : InstrItinClass; // Any c.<cc>.d instruction def II_C_CC_S : InstrItinClass; // Any c.<cc>.s instruction +def II_CMP_CC_D : InstrItinClass; // Any cmp.<cc>.d instruction +def II_CMP_CC_S : InstrItinClass; // Any cmp.<cc>.s instruction +def II_CLASS_D : InstrItinClass; +def II_CLASS_S : InstrItinClass; def II_DADDIU : InstrItinClass; def II_DADDU : InstrItinClass; def II_DADDI : InstrItinClass; @@ -172,6 +179,7 @@ def II_LHE : InstrItinClass; def II_LHU : InstrItinClass; def II_LHUE : InstrItinClass; def II_LL : InstrItinClass; +def II_LI : InstrItinClass; def II_LLD : InstrItinClass; def II_LUI : InstrItinClass; def II_LUXC1 : InstrItinClass; @@ -180,14 +188,17 @@ def II_LWE : InstrItinClass; def II_LWC1 : InstrItinClass; def II_LWC2 : InstrItinClass; def II_LWC3 : InstrItinClass; +def II_LWM : InstrItinClass; def II_LWL : InstrItinClass; def II_LWLE : InstrItinClass; def II_LWPC : InstrItinClass; +def II_LWP : InstrItinClass; def II_LWR : InstrItinClass; def II_LWRE : InstrItinClass; def II_LWU : InstrItinClass; def II_LWUPC : InstrItinClass; def II_LWXC1 : InstrItinClass; +def II_LWXS : InstrItinClass; def II_LSA : InstrItinClass; def II_DLSA : InstrItinClass; def II_MADD : InstrItinClass; @@ -196,13 +207,23 @@ def II_MADD_D : InstrItinClass; def II_MADD_S : InstrItinClass; def II_MADDF_D : InstrItinClass; def II_MADDF_S : InstrItinClass; +def II_MAX_D : InstrItinClass; +def II_MAX_S : InstrItinClass; +def II_MAXA_D : InstrItinClass; +def II_MAXA_S : InstrItinClass; +def II_MIN_D : InstrItinClass; +def II_MIN_S : InstrItinClass; +def II_MINA_D : InstrItinClass; +def II_MINA_S : InstrItinClass; def II_MFC0 : InstrItinClass; +def II_MFHC0 : InstrItinClass; def II_MFC1 : InstrItinClass; def II_MFHC1 : InstrItinClass; def II_MFC2 : InstrItinClass; def II_MFHI_MFLO : InstrItinClass; // mfhi and mflo def II_MOD : InstrItinClass; def II_MODU : InstrItinClass; +def II_MOVE : InstrItinClass; def II_MOVF : InstrItinClass; def II_MOVF_D : InstrItinClass; def II_MOVF_S : InstrItinClass; @@ -224,6 +245,7 @@ def II_MSUB_S : InstrItinClass; def II_MSUBF_D : InstrItinClass; def II_MSUBF_S : InstrItinClass; def II_MTC0 : InstrItinClass; +def II_MTHC0 : InstrItinClass; def II_MTC1 : InstrItinClass; def II_MTHC1 : InstrItinClass; def II_MTC2 : InstrItinClass; @@ -242,14 +264,21 @@ def II_NMADD_S : InstrItinClass; def II_NMSUB_D : InstrItinClass; def II_NMSUB_S : InstrItinClass; def II_NOR : InstrItinClass; +def II_NOT : InstrItinClass; def II_OR : InstrItinClass; def II_ORI : InstrItinClass; def II_POP : InstrItinClass; def II_RDHWR : InstrItinClass; def II_RESTORE : InstrItinClass; +def II_RECIP_S : InstrItinClass; +def II_RECIP_D : InstrItinClass; +def II_RINT_S : InstrItinClass; +def II_RINT_D : InstrItinClass; def II_ROTR : InstrItinClass; def II_ROTRV : InstrItinClass; def II_ROUND : InstrItinClass; +def II_RSQRT_S : InstrItinClass; +def II_RSQRT_D : InstrItinClass; def II_SAVE : InstrItinClass; def II_SC : InstrItinClass; def II_SCD : InstrItinClass; @@ -265,6 +294,8 @@ def II_SDXC1 : InstrItinClass; def II_SEB : InstrItinClass; def II_SEH : InstrItinClass; def II_SELCCZ : InstrItinClass; +def II_SELCCZ_D : InstrItinClass; +def II_SELCCZ_S : InstrItinClass; def II_SEQ_SNE : InstrItinClass; // seq and sne def II_SEQI_SNEI : InstrItinClass; // seqi and snei def II_SH : InstrItinClass; @@ -275,6 +306,8 @@ def II_SLTI_SLTIU : InstrItinClass; // slti and sltiu def II_SLT_SLTU : InstrItinClass; // slt and sltu def II_SQRT_D : InstrItinClass; def II_SQRT_S : InstrItinClass; +def II_SEL_D : InstrItinClass; +def II_SEL_S : InstrItinClass; def II_SRA : InstrItinClass; def II_SRAV : InstrItinClass; def II_SRL : InstrItinClass; @@ -291,6 +324,8 @@ def II_SWC2 : InstrItinClass; def II_SWC3 : InstrItinClass; def II_SWL : InstrItinClass; def II_SWLE : InstrItinClass; +def II_SWM : InstrItinClass; +def II_SWP : InstrItinClass; def II_SWR : InstrItinClass; def II_SWRE : InstrItinClass; def II_SWXC1 : InstrItinClass; @@ -306,6 +341,10 @@ def II_LLE : InstrItinClass; def II_SCE : InstrItinClass; def II_TLBINV : InstrItinClass; def II_TLBINVF : InstrItinClass; +def II_WRPGPR : InstrItinClass; +def II_RDPGPR : InstrItinClass; +def II_DVP : InstrItinClass; +def II_EVP : InstrItinClass; //===----------------------------------------------------------------------===// // Mips Generic instruction itineraries. @@ -368,6 +407,7 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData<II_EXT , [InstrStage<1, [ALU]>]>, InstrItinData<II_INS , [InstrStage<1, [ALU]>]>, InstrItinData<II_LUI , [InstrStage<1, [ALU]>]>, + InstrItinData<II_MOVE , [InstrStage<1, [ALU]>]>, InstrItinData<II_MOVF , [InstrStage<1, [ALU]>]>, InstrItinData<II_MOVN , [InstrStage<1, [ALU]>]>, InstrItinData<II_MOVN_S , [InstrStage<1, [ALU]>]>, @@ -375,6 +415,7 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData<II_MOVT , [InstrStage<1, [ALU]>]>, InstrItinData<II_MOVZ , [InstrStage<1, [ALU]>]>, InstrItinData<II_NOR , [InstrStage<1, [ALU]>]>, + InstrItinData<II_NOT , [InstrStage<1, [ALU]>]>, InstrItinData<II_OR , [InstrStage<1, [ALU]>]>, InstrItinData<II_POP , [InstrStage<1, [ALU]>]>, InstrItinData<II_RDHWR , [InstrStage<1, [ALU]>]>, @@ -392,6 +433,8 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData<II_LHU , [InstrStage<3, [ALU]>]>, InstrItinData<II_LHUE , [InstrStage<3, [ALU]>]>, InstrItinData<II_LW , [InstrStage<3, [ALU]>]>, + InstrItinData<II_LWM , [InstrStage<3, [ALU]>]>, + InstrItinData<II_LWP , [InstrStage<3, [ALU]>]>, InstrItinData<II_LWPC , [InstrStage<3, [ALU]>]>, InstrItinData<II_LWL , [InstrStage<3, [ALU]>]>, InstrItinData<II_LWLE , [InstrStage<3, [ALU]>]>, @@ -402,6 +445,7 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData<II_LDL , [InstrStage<3, [ALU]>]>, InstrItinData<II_LDR , [InstrStage<3, [ALU]>]>, InstrItinData<II_LDPC , [InstrStage<3, [ALU]>]>, + InstrItinData<II_LI , [InstrStage<1, [ALU]>]>, InstrItinData<II_LL , [InstrStage<3, [ALU]>]>, InstrItinData<II_LLD , [InstrStage<3, [ALU]>]>, InstrItinData<II_RESTORE , [InstrStage<3, [ALU]>]>, @@ -409,15 +453,18 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData<II_SH , [InstrStage<1, [ALU]>]>, InstrItinData<II_SHE , [InstrStage<1, [ALU]>]>, InstrItinData<II_SW , [InstrStage<1, [ALU]>]>, + InstrItinData<II_SWM , [InstrStage<1, [ALU]>]>, InstrItinData<II_SWL , [InstrStage<1, [ALU]>]>, InstrItinData<II_SWR , [InstrStage<1, [ALU]>]>, + InstrItinData<II_SWP , [InstrStage<1, [ALU]>]>, InstrItinData<II_SDL , [InstrStage<1, [ALU]>]>, InstrItinData<II_SDR , [InstrStage<1, [ALU]>]>, InstrItinData<II_SD , [InstrStage<1, [ALU]>]>, InstrItinData<II_SC , [InstrStage<1, [ALU]>]>, InstrItinData<II_SCD , [InstrStage<1, [ALU]>]>, InstrItinData<II_SAVE , [InstrStage<1, [ALU]>]>, - InstrItinData<II_SELCCZ , [InstrStage<1, [ALU]>]>, + InstrItinData<II_SELCCZ_S , [InstrStage<1, [ALU]>]>, + InstrItinData<II_SELCCZ_D , [InstrStage<1, [ALU]>]>, InstrItinData<II_SEQ_SNE , [InstrStage<1, [ALU]>]>, InstrItinData<II_SEQI_SNEI , [InstrStage<1, [ALU]>]>, InstrItinData<II_SLTI_SLTIU , [InstrStage<1, [ALU]>]>, @@ -431,12 +478,15 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData<II_BC1T , [InstrStage<1, [ALU]>]>, InstrItinData<II_BC1TL , [InstrStage<1, [ALU]>]>, InstrItinData<II_BC1CCZ , [InstrStage<1, [ALU]>]>, + InstrItinData<II_BC2CCZ , [InstrStage<1, [ALU]>]>, InstrItinData<II_BCC , [InstrStage<1, [ALU]>]>, InstrItinData<II_BCCC , [InstrStage<1, [ALU]>]>, InstrItinData<II_BCCZ , [InstrStage<1, [ALU]>]>, InstrItinData<II_BCCZAL , [InstrStage<1, [ALU]>]>, InstrItinData<II_BCCZALS , [InstrStage<1, [ALU]>]>, InstrItinData<II_BCCZC , [InstrStage<1, [ALU]>]>, + InstrItinData<II_CLASS_D , [InstrStage<1, [ALU]>]>, + InstrItinData<II_CLASS_S , [InstrStage<1, [ALU]>]>, InstrItinData<II_IndirectBranchPseudo, [InstrStage<1, [ALU]>]>, InstrItinData<II_J , [InstrStage<1, [ALU]>]>, InstrItinData<II_JAL , [InstrStage<1, [ALU]>]>, @@ -493,6 +543,14 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData<II_MADD , [InstrStage<17, [IMULDIV]>]>, InstrItinData<II_MADDU , [InstrStage<17, [IMULDIV]>]>, InstrItinData<II_MFHI_MFLO , [InstrStage<1, [IMULDIV]>]>, + InstrItinData<II_MAX_D , [InstrStage<4, [ALU]>]>, + InstrItinData<II_MAX_S , [InstrStage<4, [ALU]>]>, + InstrItinData<II_MAXA_D , [InstrStage<4, [ALU]>]>, + InstrItinData<II_MAXA_S , [InstrStage<4, [ALU]>]>, + InstrItinData<II_MIN_S , [InstrStage<4, [ALU]>]>, + InstrItinData<II_MIN_D , [InstrStage<4, [ALU]>]>, + InstrItinData<II_MINA_S , [InstrStage<4, [ALU]>]>, + InstrItinData<II_MINA_D , [InstrStage<4, [ALU]>]>, InstrItinData<II_MOD , [InstrStage<38, [IMULDIV]>]>, InstrItinData<II_MODU , [InstrStage<38, [IMULDIV]>]>, InstrItinData<II_MSUB , [InstrStage<17, [IMULDIV]>]>, @@ -521,6 +579,8 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData<II_MOV_S , [InstrStage<2, [ALU]>]>, InstrItinData<II_CFC1 , [InstrStage<2, [ALU]>]>, InstrItinData<II_CTC1 , [InstrStage<2, [ALU]>]>, + InstrItinData<II_CFC2 , [InstrStage<2, [ALU]>]>, + InstrItinData<II_CTC2 , [InstrStage<2, [ALU]>]>, InstrItinData<II_MOVF_D , [InstrStage<2, [ALU]>]>, InstrItinData<II_MOVF_S , [InstrStage<2, [ALU]>]>, InstrItinData<II_MOVT_D , [InstrStage<2, [ALU]>]>, @@ -529,6 +589,8 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData<II_MOVZ_S , [InstrStage<2, [ALU]>]>, InstrItinData<II_C_CC_S , [InstrStage<3, [ALU]>]>, InstrItinData<II_C_CC_D , [InstrStage<3, [ALU]>]>, + InstrItinData<II_CMP_CC_S , [InstrStage<3, [ALU]>]>, + InstrItinData<II_CMP_CC_D , [InstrStage<3, [ALU]>]>, InstrItinData<II_ADD_D , [InstrStage<4, [ALU]>]>, InstrItinData<II_ADD_S , [InstrStage<4, [ALU]>]>, InstrItinData<II_SUB_D , [InstrStage<4, [ALU]>]>, @@ -549,8 +611,16 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData<II_NMSUB_D , [InstrStage<8, [ALU]>]>, InstrItinData<II_DIV_S , [InstrStage<23, [ALU]>]>, InstrItinData<II_DIV_D , [InstrStage<36, [ALU]>]>, + InstrItinData<II_RECIP_D , [InstrStage<25, [ALU]>]>, + InstrItinData<II_RECIP_S , [InstrStage<13, [ALU]>]>, + InstrItinData<II_RSQRT_D , [InstrStage<29, [ALU]>]>, + InstrItinData<II_RSQRT_S , [InstrStage<14, [ALU]>]>, + InstrItinData<II_RINT_D , [InstrStage<1, [ALU]>]>, + InstrItinData<II_RINT_S , [InstrStage<1, [ALU]>]>, InstrItinData<II_SQRT_S , [InstrStage<54, [ALU]>]>, InstrItinData<II_SQRT_D , [InstrStage<12, [ALU]>]>, + InstrItinData<II_SEL_D , [InstrStage<1, [ALU]>]>, + InstrItinData<II_SEL_S , [InstrStage<1, [ALU]>]>, InstrItinData<II_WSBH , [InstrStage<1, [ALU]>]>, InstrItinData<II_LSA , [InstrStage<1, [ALU]>]>, InstrItinData<II_DLSA , [InstrStage<1, [ALU]>]>, @@ -563,6 +633,7 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData<II_LDXC1 , [InstrStage<3, [ALU]>]>, InstrItinData<II_LWXC1 , [InstrStage<3, [ALU]>]>, InstrItinData<II_LUXC1 , [InstrStage<3, [ALU]>]>, + InstrItinData<II_LWXS , [InstrStage<3, [ALU]>]>, InstrItinData<II_SDC1 , [InstrStage<1, [ALU]>]>, InstrItinData<II_SDC2 , [InstrStage<1, [ALU]>]>, InstrItinData<II_SDC3 , [InstrStage<1, [ALU]>]>, @@ -579,9 +650,11 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData<II_DMTC1 , [InstrStage<2, [ALU]>]>, InstrItinData<II_DMTC2 , [InstrStage<2, [ALU]>]>, InstrItinData<II_MFC0 , [InstrStage<2, [ALU]>]>, + InstrItinData<II_MFHC0 , [InstrStage<2, [ALU]>]>, InstrItinData<II_MFC1 , [InstrStage<2, [ALU]>]>, InstrItinData<II_MFC2 , [InstrStage<2, [ALU]>]>, InstrItinData<II_MTC0 , [InstrStage<2, [ALU]>]>, + InstrItinData<II_MTHC0 , [InstrStage<2, [ALU]>]>, InstrItinData<II_MTC1 , [InstrStage<2, [ALU]>]>, InstrItinData<II_MTC2 , [InstrStage<2, [ALU]>]>, InstrItinData<II_MFHC1 , [InstrStage<2, [ALU]>]>, @@ -593,7 +666,9 @@ def MipsGenericItineraries : ProcessorItineraries<[ALU, IMULDIV], [], [ InstrItinData<II_TLBINV , [InstrStage<1, [ALU]>]>, InstrItinData<II_TLBINVF , [InstrStage<1, [ALU]>]>, InstrItinData<II_LLE , [InstrStage<3, [ALU]>]>, - InstrItinData<II_SCE , [InstrStage<1, [ALU]>]> + InstrItinData<II_SCE , [InstrStage<1, [ALU]>]>, + InstrItinData<II_WRPGPR , [InstrStage<1, [ALU]>]>, + InstrItinData<II_RDPGPR , [InstrStage<1, [ALU]>]>, + InstrItinData<II_DVP , [InstrStage<1, [ALU]>]>, + InstrItinData<II_EVP , [InstrStage<1, [ALU]>]> ]>; - -include "MipsScheduleP5600.td" diff --git a/contrib/llvm/lib/Target/Mips/MipsScheduleGeneric.td b/contrib/llvm/lib/Target/Mips/MipsScheduleGeneric.td new file mode 100644 index 0000000..15a0401 --- /dev/null +++ b/contrib/llvm/lib/Target/Mips/MipsScheduleGeneric.td @@ -0,0 +1,1048 @@ +//=- MipsScheduleGeneric.td - Generic Scheduling Definitions -*- tablegen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the interAptiv processor in a manner of speaking. It +// describes a hypothetical version of the in-order MIPS32R2 interAptiv with all +// branches of the MIPS ISAs, ASEs and ISA variants. The itinerary lists are +// broken down into per ISA lists, so that this file can be used to rapidly +// develop new schedule models. +// +//===----------------------------------------------------------------------===// +def MipsGenericModel : SchedMachineModel { + int IssueWidth = 1; + int MicroOpBufferSize = 0; + + // These figures assume an L1 hit. + int LoadLatency = 2; + int MispredictPenalty = 4; + + int HighLatency = 37; + list<Predicate> UnsupportedFeatures = []; + + let CompleteModel = 1; + let PostRAScheduler = 1; +} + +let SchedModel = MipsGenericModel in { + +// ALU Pipeline +// ============ + +def GenericALU : ProcResource<1> { let BufferSize = 1; } +def GenericIssueALU : ProcResource<1> { let Super = GenericALU; } + +def GenericWriteALU : SchedWriteRes<[GenericIssueALU]>; + +// and, lui, nor, or, slti, sltiu, sub, subu, xor +// add, addi, addiu, addu, andi, ori, rotr, se[bh], sllv?, sr[al]v?, slt, sltu, +// xori +def : ItinRW<[GenericWriteALU], [II_ADD, II_ADDU, II_ADDI, II_ADDIU, II_ANDI, + II_AND, II_ANDI, II_CLO, II_CLZ, II_EXT, + II_INS, II_LUI, II_MULT, II_MULTU, II_NOR, + II_ORI, II_OR, II_ROTR, II_ROTRV, II_SEB, + II_SEH, II_SLTI_SLTIU, II_SLT_SLTU, II_SLL, + II_SRA, II_SRL, II_SLLV, II_SRAV, II_SRLV, + II_SSNOP, II_SUB, II_SUBU, II_WSBH, II_XOR, + II_XORI]>; + +def : InstRW<[GenericWriteALU], (instrs COPY)>; + +def GenericMDU : ProcResource<1> { let BufferSize = 1; } +def GenericIssueMDU : ProcResource<1> { let Super = GenericALU; } +def GenericIssueDIV : ProcResource<1> { let Super = GenericMDU; } +def GenericWriteHILO : SchedWriteRes<[GenericIssueMDU]>; +def GenericWriteALULong : SchedWriteRes<[GenericIssueALU]> { let Latency = 5; } +def GenericWriteMove : SchedWriteRes<[GenericIssueALU]> { let Latency = 2; } + +def : ItinRW<[GenericWriteHILO], [II_MADD, II_MADDU, II_MSUB, II_MSUBU]>; + +def GenericWriteMDUtoGPR : SchedWriteRes<[GenericIssueMDU]> { + let Latency = 5; +} + +def : ItinRW<[GenericWriteMDUtoGPR], [II_MUL]>; + +def GenericWriteDIV : SchedWriteRes<[GenericIssueDIV]> { + // Estimated worst case + let Latency = 33; + let ResourceCycles = [1, 33]; +} +def GenericWriteDIVU : SchedWriteRes<[GenericIssueDIV]> { + // Estimated worst case + let Latency = 31; + let ResourceCycles = [1, 31]; +} + +def : ItinRW<[GenericWriteDIV], [II_DIV]>; + +def : ItinRW<[GenericWriteDIVU], [II_DIVU]>; + +// MIPS64 +// ====== + +def : ItinRW<[GenericWriteALU], [II_DADDIU, II_DADDU, II_DADDI, II_DADD, + II_DCLO, II_DCLZ, II_DROTR, II_DROTR32, + II_DROTRV, II_DSBH, II_DSHD, II_DSLL, + II_DSLL32, II_DSLLV, II_DSRA, II_DSRA32, + II_DSRAV, II_DSRL, II_DSRL32, II_DSRLV, + II_DSUBU, II_DSUB]>; + +def : ItinRW<[GenericWriteDIV], [II_DDIV]>; + +def : ItinRW<[GenericWriteDIVU], [II_DDIVU]>; + +def : ItinRW<[GenericWriteMDUtoGPR], [II_DMUL]>; + +def : ItinRW<[GenericWriteHILO], [II_DMULU, II_DMULT, II_DMULTU]>; + +// MIPS16e +// ======= + +def : ItinRW<[GenericWriteALU], [IIM16Alu, IIPseudo]>; + +// microMIPS +// ========= + +def : ItinRW<[GenericWriteALU], [II_MOVE, II_LI, II_NOT]>; + +// MIPSR6 +// ====== + +def GenericWriteMul : SchedWriteRes<[GenericIssueMDU]> { let Latency = 4; } +def : ItinRW<[GenericWriteMul], [II_MUH, II_MUHU, II_MULU]>; + +def : ItinRW<[GenericWriteDIV], [II_MOD, II_MODU]>; + +def : ItinRW<[GenericWriteALU], [II_ADDIUPC, II_ALIGN, II_ALUIPC, II_AUI, + II_AUIPC, II_BITSWAP, II_LSA, II_SELCCZ]>; + +// MIPS64R6 +// ======== + +def : ItinRW<[GenericWriteALU], [II_DALIGN, II_DAHI, II_DATI, II_DAUI, + II_DBITSWAP, II_DLSA]>; + +def : ItinRW<[GenericWriteMDUtoGPR], [II_DMUH, II_DMUHU]>; +def : ItinRW<[GenericWriteDIV], [II_DMOD, II_DMODU]>; + +// clo, clz, di, mfhi, mflo +def : ItinRW<[GenericWriteALULong], [II_MFHI_MFLO]>; +def : ItinRW<[GenericWriteALU], [II_MOVN, II_MOVZ]>; +def : ItinRW<[GenericWriteMove], [II_MTHI_MTLO, II_RDHWR]>; + + +// CTISTD Pipeline +// --------------- + +def GenericIssueCTISTD : ProcResource<1> { let Super = GenericALU; } + +def GenericLDST : ProcResource<1> { let BufferSize = 1; } +def GenericIssueLDST : ProcResource<1> { let Super = GenericLDST; } + +def GenericWriteJump : SchedWriteRes<[GenericIssueCTISTD]>; +def GenericWriteJumpAndLink : SchedWriteRes<[GenericIssueCTISTD]> { + let Latency = 2; +} + +// b, beq, beql, bg[et]z, bl[et]z, bne, bnel, j, syscall, jal, bltzal, jalx, +// jalr, jr.hb, jr, jalr.hb, jarlc, jialc +def : ItinRW<[GenericWriteJump], [II_B, II_BCC, II_BCCZ, II_BCCZAL, II_J, + II_JR, II_JR_HB, II_ERET, II_ERETNC, + II_DERET]>; + +def : ItinRW<[GenericWriteJumpAndLink], [II_JAL, II_JALR, II_JALR_HB, + II_BC2CCZ]>; + +def : ItinRW<[GenericWriteJump], [II_JRC, II_JRADDIUSP]>; + +def : ItinRW<[GenericWriteJumpAndLink], [II_BCCZALS, II_JALS, II_JALRS]>; + +// MIPSR6 +// ====== + +def : ItinRW<[GenericWriteJumpAndLink], [II_BALC, II_JALRC, II_JIALC]>; + +def : ItinRW<[GenericWriteJump], [II_JIC, II_BC, II_BCCC, II_BCCZC]>; + + +def GenericWriteTrap : SchedWriteRes<[GenericIssueCTISTD]>; + +def : ItinRW<[GenericWriteTrap], [II_BREAK, II_SYSCALL, II_TEQ, II_TEQI, + II_TGE, II_TGEI, II_TGEIU, II_TGEU, II_TNE, + II_TNEI, II_TLT, II_TLTI, II_TLTU, II_TTLTIU, + II_TRAP, II_SDBBP]>; + +// COP0 Pipeline +// ============= + +def GenericCOP0 : ProcResource<1> { let BufferSize = 1; } + +def GenericIssueCOP0 : ProcResource<1> { let Super = GenericCOP0; } +def GenericWriteCOP0TLB : SchedWriteRes<[GenericIssueCOP0]> { let Latency = 4; } +def GenericWriteCOP0 : SchedWriteRes<[GenericIssueCOP0]> { let Latency = 3; } +def GenericReadCOP0 : SchedWriteRes<[GenericIssueCOP0]> { let Latency = 2; } +def GnereicReadWritePGPR : SchedWriteRes<[GenericIssueCOP0]>; + +def : ItinRW<[GenericWriteCOP0TLB], [II_TLBP, II_TLBR, II_TLBWI, II_TLBWR]>; +def : ItinRW<[GenericWriteCOP0TLB], [II_TLBINV, II_TLBINVF]>; + +def : ItinRW<[GenericReadCOP0], [II_MFC0]>; +def : ItinRW<[GenericWriteCOP0], [II_MTC0]>; + +def : ItinRW<[GenericWriteCOP0], [II_EVP, II_DVP]>; + +// MIPSR5 +// ====== +def : ItinRW<[GenericReadCOP0], [II_MFHC0]>; +def : ItinRW<[GenericWriteCOP0], [II_MTHC0]>; + +// MIPS64 +// ====== + +def : ItinRW<[GenericReadCOP0], [II_DMFC0]>; +def : ItinRW<[GenericWriteCOP0], [II_DMTC0]>; + +def : ItinRW<[GenericWriteCOP0], [II_RDPGPR, II_WRPGPR]>; + +def : ItinRW<[GenericWriteCOP0], [II_DI, II_EI]>; + +def : ItinRW<[GenericWriteCOP0], [II_EHB, II_PAUSE, II_WAIT]>; + +def GenericCOP2 : ProcResource<1> { let BufferSize = 1; } +def GenericWriteCOPOther : SchedWriteRes<[GenericCOP2]>; + +def : ItinRW<[GenericWriteCOPOther], [II_MFC2, II_MTC2, II_DMFC2, II_DMTC2]>; + +// LDST Pipeline +// ------------- + +def GenericWriteLoad : SchedWriteRes<[GenericIssueLDST]> { + let Latency = 2; +} + +def GenericWritePref : SchedWriteRes<[GenericIssueLDST]>; +def GenericWriteSync : SchedWriteRes<[GenericIssueLDST]>; +def GenericWriteCache : SchedWriteRes<[GenericIssueLDST]> { let Latency = 5; } + +def GenericWriteStore : SchedWriteRes<[GenericIssueLDST]>; +def GenericWriteStoreSC : SchedWriteRes<[GenericIssueLDST]> { let Latency = 2; } + +def GenericWriteGPRFromBypass : SchedWriteRes<[GenericIssueLDST]> { + let Latency = 2; +} + +def GenericWriteStoreFromOtherUnits : SchedWriteRes<[GenericIssueLDST]>; +def GenericWriteLoadToOtherUnits : SchedWriteRes<[GenericIssueLDST]> { + let Latency = 0; +} + +// l[bhw], l[bh]u, ll +def : ItinRW<[GenericWriteLoad], [II_LB, II_LBU, II_LH, II_LHU, II_LW, II_LL, + II_LWC2, II_LWC3, II_LDC2, II_LDC3]>; + +// lw[lr] +def : ItinRW<[GenericWriteLoad], [II_LWL, II_LWR]>; + +// MIPS64 loads +def : ItinRW<[GenericWriteLoad], [II_LD, II_LLD, II_LWU]>; + +// ld[lr] +def : ItinRW<[GenericWriteLoad], [II_LDL, II_LDR]>; + +// MIPS32 EVA +def : ItinRW<[GenericWriteLoad], [II_LBE, II_LBUE, II_LHE, II_LHUE, II_LWE, + II_LLE]>; + +def : ItinRW<[GenericWriteLoad], [II_LWLE, II_LWRE]>; + +// MIPS32R6 and MIPS16e +// ==================== + +def : ItinRW<[GenericWriteLoad], [II_LWPC]>; + +// MIPS64R6 +// ==================== + +def : ItinRW<[GenericWriteLoad], [II_LWUPC, II_LDPC]>; + + +// s[bhw], sc, s[dw]c[23] +def : ItinRW<[GenericWriteStore], [II_SB, II_SH, II_SW, II_SWC2, II_SWC3, + II_SDC2, II_SDC3]>; + +def : ItinRW<[GenericWriteStoreSC], [II_SC]>; + +// PreMIPSR6 sw[lr] +def : ItinRW<[GenericWriteStore], [II_SWL, II_SWR]>; + +// EVA ASE stores +def : ItinRW<[GenericWriteStore], [II_SBE, II_SHE, II_SWE, II_SCE]>; + +def : ItinRW<[GenericWriteStore], [II_SWLE, II_SWRE]>; + +// MIPS64 +// ====== + +def : ItinRW<[GenericWriteStore], [II_SD, II_SCD]>; + +// PreMIPSR6 stores +// ================ + +def : ItinRW<[GenericWriteStore], [II_SDL, II_SDR]>; + +// MIPS16e +// ======= + +def : ItinRW<[GenericWriteLoad], [II_RESTORE]>; + +def : ItinRW<[GenericWriteStore], [II_SAVE]>; + +// microMIPS +// ========= + +def : ItinRW<[GenericWriteLoad], [II_LWM, II_LWP, II_LWXS]>; + +def : ItinRW<[GenericWriteStore], [II_SWM, II_SWP]>; + +// pref +def : ItinRW<[GenericWritePref], [II_PREF]>; + +def : ItinRW<[GenericWritePref], [II_PREFE]>; + +// cache +def : ItinRW<[GenericWriteCache], [II_CACHE]>; + +def : ItinRW<[GenericWriteCache], [II_CACHEE]>; + +// sync +def : ItinRW<[GenericWriteSync], [II_SYNC]>; + +def : ItinRW<[GenericWriteSync], [II_SYNCI]>; + +// FPU Pipelines +// ============= + +def GenericFPQ : ProcResource<1> { let BufferSize = 1; } +def GenericIssueFPUS : ProcResource<1> { let Super = GenericFPQ; } +def GenericIssueFPUL : ProcResource<1> { let Super = GenericFPQ; } +def GenericIssueFPULoad : ProcResource<1> { let Super = GenericFPQ; } +def GenericIssueFPUStore : ProcResource<1> { let Super = GenericFPQ; } +def GenericIssueFPUMove : ProcResource<1> { let Super = GenericFPQ; } +def GenericFPUDivSqrt : ProcResource<1> { let Super = GenericFPQ; } + +// The floating point compare of the 24k series including interAptiv has a +// listed latency of 1-2. Using the higher latency here. + +def GenericWriteFPUCmp : SchedWriteRes<[GenericIssueFPUS]> { let Latency = 2; } +def GenericWriteFPUS : SchedWriteRes<[GenericIssueFPUS]> { let Latency = 4; } +def GenericWriteFPUL : SchedWriteRes<[GenericIssueFPUL]> { let Latency = 5; } +def GenericWriteFPUStore : SchedWriteRes<[GenericIssueFPUStore]> { let + Latency = 1; +} +def GenericWriteFPULoad : SchedWriteRes<[GenericIssueFPULoad]> { + let Latency = 2; +} +def GenericWriteFPUMoveFP : SchedWriteRes<[GenericIssueFPUMove]> { + let Latency = 4; +} +def GenericWriteFPUMoveGPRFPU : SchedWriteRes<[GenericIssueFPUMove]> { + let Latency = 2; +} +def GenericWriteFPUDivS : SchedWriteRes<[GenericFPUDivSqrt]> { + let Latency = 17; + let ResourceCycles = [ 14 ]; +} +def GenericWriteFPUDivD : SchedWriteRes<[GenericFPUDivSqrt]> { + let Latency = 32; + let ResourceCycles = [ 29 ]; +} +def GenericWriteFPURcpS : SchedWriteRes<[GenericFPUDivSqrt]> { + let Latency = 13; + let ResourceCycles = [ 10 ]; +} +def GenericWriteFPURcpD : SchedWriteRes<[GenericFPUDivSqrt]> { + let Latency = 25; + let ResourceCycles = [ 21 ]; +} +def GenericWriteFPURsqrtS : SchedWriteRes<[GenericFPUDivSqrt]> { + let Latency = 17; + let ResourceCycles = [ 14 ]; +} +def GenericWriteFPURsqrtD : SchedWriteRes<[GenericFPUDivSqrt]> { + let Latency = 32; + let ResourceCycles = [ 29 ]; +} +def GenericWriteFPUSqrtS : SchedWriteRes<[GenericFPUDivSqrt]> { + let Latency = 17; + let ResourceCycles = [ 14 ]; +} +def GenericWriteFPUSqrtD : SchedWriteRes<[GenericFPUDivSqrt]> { + let Latency = 29; + let ResourceCycles = [ 29 ]; +} + +// Floating point compare and branch +// --------------------------------- +// +// c.<cc>.[ds], bc1[tf], bc1[tf]l +def : ItinRW<[GenericWriteFPUCmp], [II_C_CC_D, II_C_CC_S, II_BC1F, II_BC1T, + II_BC1FL, II_BC1TL]>; + +def : ItinRW<[GenericWriteFPUCmp], [II_CMP_CC_D, II_CMP_CC_S]>; + +// Short Pipe +// ---------- +// +// abs.[ds], abs.ps, add.[ds], neg.[ds], neg.ps, madd.s, msub.s, nmadd,s +// nmsub.s, sub.[ds], mul.s + +def : ItinRW<[GenericWriteFPUS], [II_ABS, II_ADD_D, II_ADD_S, II_MADD_S, + II_MSUB_S, II_MUL_S, II_NEG, II_NMADD_S, + II_NMSUB_S, II_SUB_S, II_SUB_D]>; +// mov[tf].[ds] + +def : ItinRW<[GenericWriteFPUS], [II_MOVF_S, II_MOVF_D, II_MOVT_S, II_MOVT_D]>; + +// MIPSR6 +// ------ +// +// sel(eq|ne).[ds], max.[ds], maxa.[ds], min.[ds], mina.[ds], class.[ds] +def : ItinRW<[GenericWriteFPUS], [II_SELCCZ_S, II_SELCCZ_D, II_MAX_S, + II_MAX_D, II_MAXA_S, II_MAXA_D, II_MIN_S, + II_MIN_D, II_MINA_S, II_MINA_D, II_CLASS_S, + II_CLASS_D]>; + +// Long Pipe +// ---------- +// +// nmadd.d, nmsub.d, mul.[ds], mul.ps, ceil.[wl].[sd], cvt.d.[sw], cvt.s.[dw], +// cvt.w.[sd], cvt.[sw].ps, trunc.w.[ds], trunc.w.ps, floor.[ds], +// round.[lw].[ds], floor.[lw].ds + +// madd.d, msub.dm mul.d, mul.ps, nmadd.d, nmsub.d, ceil.[wl].[sd], cvt.d.[sw], +// cvt.s.[dw], cvt.w.[sd], cvt.[sw].ps, round.[lw].[ds], floor.[lw].ds, +// trunc.w.[ds], trunc.w.ps, +def : ItinRW<[GenericWriteFPUL], [II_MADD_D, II_MSUB_D, II_MUL_D, II_NMADD_D, + II_NMSUB_D, II_CEIL, II_CVT, + II_FLOOR, II_ROUND, II_TRUNC]>; + +// div.[ds], div.ps +def : ItinRW<[GenericWriteFPUDivS], [II_DIV_S]>; +def : ItinRW<[GenericWriteFPUDivD], [II_DIV_D]>; + +// sqrt.[ds], sqrt.ps +def : ItinRW<[GenericWriteFPUSqrtS], [II_SQRT_S]>; +def : ItinRW<[GenericWriteFPUSqrtD], [II_SQRT_D]>; + +// rsqrt.[ds], recip.[ds] +def : ItinRW<[GenericWriteFPURcpS], [II_RECIP_S, II_RSQRT_S]>; +def : ItinRW<[GenericWriteFPURcpD], [II_RECIP_D, II_RSQRT_D]>; + +// MIPSR6 +// ====== +// +// rint.[ds] +def : ItinRW<[GenericWriteFPUL], [II_RINT_S, II_RINT_D]>; + +// Load Pipe +// --------- + +// ctc1, mtc1, mthc1, cfc1, mfc1, mfhc1 +def : ItinRW<[GenericWriteFPUMoveGPRFPU], [II_CFC1, II_CTC1, II_MFC1, II_MFHC1, + II_MTC1, II_MTHC1]>; + +// swc1, swxc1 +def : ItinRW<[GenericWriteFPUStore], [II_SDC1, II_SDXC1, II_SUXC1, II_SWC1, + II_SWXC1]>; + +// movn.[ds], movz.[ds] +def : ItinRW<[GenericWriteFPUMoveFP], [II_MOV_D, II_MOV_S, II_MOVF, II_MOVT, + II_MOVN_D, II_MOVN_S, II_MOVZ_D, + II_MOVZ_S]>; + +// l[dw]x?c1 +def : ItinRW<[GenericWriteFPULoad], [II_LDC1, II_LDXC1, II_LUXC1, II_LWC1, + II_LWXC1]>; + +// MIPS64 +// ====== + +def : ItinRW<[GenericWriteFPUMoveGPRFPU], [II_DMFC1, II_DMTC1]>; + +// MIPSR6 +// ====== + +def : ItinRW<[GenericWriteFPUS], [II_MADDF_S, II_MSUBF_S]>; + +def : ItinRW<[GenericWriteFPUS], [II_MADDF_D, II_MSUBF_D]>; + +def : ItinRW<[GenericWriteFPUCmp], [II_BC1CCZ, II_SEL_D, II_SEL_S]>; + +// Cavium Networks MIPS (cnMIPS) - Octeon, HasCnMips +// ================================================= + +def : ItinRW<[GenericWriteALU], [II_SEQ_SNE, II_SEQI_SNEI, II_POP, II_BADDU, + II_BBIT]>; + +// MIPS DSP ASE, HasDSP +// ==================== + +def GenericDSP : ProcResource<1> { let BufferSize = 1; } +def GenericDSPShort : SchedWriteRes<[GenericDSP]> { let Latency = 2; } +def GenericDSPLong : SchedWriteRes<[GenericDSP]> { let Latency = 6; } +def GenericDSPBypass : SchedWriteRes<[GenericDSP]> { let Latency = 1; } +def GenericDSPMTHILO : SchedWriteRes<[GenericDSP]> { let Latency = 5; } +def GenericDSPLoad : SchedWriteRes<[GenericDSP]> { let Latency = 4; } +def GenericDSPMTHLIP : SchedWriteRes<[GenericDSP]> { let Latency = 5; } + +def : InstRW<[GenericDSPLong], (instregex "^EXTRV_RS_W$")>; +def : InstRW<[GenericDSPLong], (instregex "^EXTRV_R_W$")>; +def : InstRW<[GenericDSPLong], (instregex "^EXTRV_S_H$")>; +def : InstRW<[GenericDSPLong], (instregex "^EXTRV_W$")>; +def : InstRW<[GenericDSPLong], (instregex "^EXTR_RS_W$")>; +def : InstRW<[GenericDSPLong], (instregex "^EXTR_R_W$")>; +def : InstRW<[GenericDSPLong], (instregex "^EXTR_S_H$")>; +def : InstRW<[GenericDSPLong], (instregex "^EXTR_W$")>; +def : InstRW<[GenericDSPLong], (instregex "^INSV$")>; + +def : InstRW<[GenericDSPMTHLIP], (instregex "^MTHLIP$")>; +def : InstRW<[GenericDSPMTHILO], (instregex "^MTHI_DSP$")>; +def : InstRW<[GenericDSPMTHILO], (instregex "^MTLO_DSP$")>; + +def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_W$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDQ_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDQ_S_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDQ_S_W$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDSC$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDU_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDU_S_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDWC$")>; +def : InstRW<[GenericDSPShort], (instregex "^BITREV$")>; +def : InstRW<[GenericDSPShort], (instregex "^BPOSGE32$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMPGU_EQ_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMPGU_LE_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMPGU_LT_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMPU_EQ_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMPU_LE_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMPU_LT_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMP_EQ_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMP_LE_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMP_LT_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPAQ_SA_L_W$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPAQ_S_W_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPAU_H_QBL$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPAU_H_QBR$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPSQ_SA_L_W$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPSQ_S_W_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPSU_H_QBL$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPSU_H_QBR$")>; +def : InstRW<[GenericDSPShort], (instregex "^EXTPDPV$")>; +def : InstRW<[GenericDSPShort], (instregex "^EXTPDP$")>; +def : InstRW<[GenericDSPShort], (instregex "^EXTPV$")>; +def : InstRW<[GenericDSPShort], (instregex "^EXTP$")>; +def : InstRW<[GenericDSPShort], (instregex "^LBUX$")>; +def : InstRW<[GenericDSPShort], (instregex "^LHX$")>; +def : InstRW<[GenericDSPShort], (instregex "^LWX$")>; +def : InstRW<[GenericDSPShort], (instregex "^MADDU_DSP$")>; +def : InstRW<[GenericDSPShort], (instregex "^MADD_DSP$")>; +def : InstRW<[GenericDSPShort], (instregex "^MAQ_SA_W_PHL$")>; +def : InstRW<[GenericDSPShort], (instregex "^MAQ_SA_W_PHR$")>; +def : InstRW<[GenericDSPShort], (instregex "^MAQ_S_W_PHL$")>; +def : InstRW<[GenericDSPShort], (instregex "^MAQ_S_W_PHR$")>; +def : InstRW<[GenericDSPShort], (instregex "^MFHI_DSP$")>; +def : InstRW<[GenericDSPShort], (instregex "^MFLO_DSP$")>; +def : InstRW<[GenericDSPShort], (instregex "^MODSUB$")>; +def : InstRW<[GenericDSPShort], (instregex "^MSUBU_DSP$")>; +def : InstRW<[GenericDSPShort], (instregex "^MSUB_DSP$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULEQ_S_W_PHL$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULEQ_S_W_PHR$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULEU_S_PH_QBL$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULEU_S_PH_QBR$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULQ_RS_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULSAQ_S_W_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULTU_DSP$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULT_DSP$")>; +def : InstRW<[GenericDSPShort], (instregex "^PACKRL_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^PICK_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^PICK_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBLA$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBL$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBRA$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBR$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECEQ_W_PHL$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECEQ_W_PHR$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBLA$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBL$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBRA$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBR$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECRQU_S_QB_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_PH_W$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_QB_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_RS_PH_W$")>; +def : InstRW<[GenericDSPShort], (instregex "^RADDU_W_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^RDDSP$")>; +def : InstRW<[GenericDSPShort], (instregex "^REPLV_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^REPLV_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^REPL_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^REPL_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHILOV$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHILO$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHLLV_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHLLV_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHLLV_S_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHLLV_S_W$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHLL_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHLL_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHLL_S_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHLL_S_W$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRAV_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_W$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRA_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_W$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRLV_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRL_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBQ_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBQ_S_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBQ_S_W$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBU_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBU_S_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^WRDSP$")>; + +// MIPS DSP R2 - hasDSP, HasDSPR2, InMicroMips +// =========================================== + +def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDQH_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDQH_R_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDQH_R_W$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDQH_W$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDUH_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDUH_R_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDU_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDU_S_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^APPEND$")>; +def : InstRW<[GenericDSPShort], (instregex "^BALIGN$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_EQ_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_LE_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_LT_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPA_W_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPAQX_SA_W_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPAQX_S_W_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPAX_W_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPS_W_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPSQX_S_W_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPSQX_SA_W_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPSX_W_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^MUL_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^MUL_S_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULQ_RS_W$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULQ_S_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULQ_S_W$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULSA_W_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECR_QB_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECR_SRA_PH_W$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECR_SRA_R_PH_W$")>; +def : InstRW<[GenericDSPShort], (instregex "^PREPEND$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRA_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRAV_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRL_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRLV_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBQH_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBQH_R_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBQH_W$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBQH_R_W$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBU_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBU_S_PH$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBUH_QB$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBUH_R_QB$")>; + +// microMIPS DSP R1 - HasDSP, InMicroMips +// ====================================== + +def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_W_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDQ_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDQ_S_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDQ_S_W_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDSC_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDU_QB_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDU_S_QB_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDWC_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^BITREV_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^BPOSGE32_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMPGU_EQ_QB_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMPGU_LE_QB_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMPGU_LT_QB_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMPU_EQ_QB_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMPU_LE_QB_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMPU_LT_QB_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMP_EQ_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMP_LE_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMP_LT_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPAQ_SA_L_W_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPAQ_S_W_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPAU_H_QBL_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPAU_H_QBR_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPSQ_SA_L_W_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPSQ_S_W_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPSU_H_QBL_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPSU_H_QBR_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^EXTPDPV_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^EXTPDP_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^EXTPV_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^EXTP_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^EXTRV_RS_W_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^EXTRV_R_W_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^EXTRV_S_H_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^EXTRV_W_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^EXTR_RS_W_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^EXTR_R_W_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^EXTR_S_H_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^EXTR_W_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^INSV_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^LBUX_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^LHX_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^LWX_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MADDU_DSP_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MADD_DSP_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MAQ_SA_W_PHL_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MAQ_SA_W_PHR_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MAQ_S_W_PHL_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MAQ_S_W_PHR_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MFHI_DSP_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MFLO_DSP_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MODSUB_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MOVEP_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MOVN_I_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MOVZ_I_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MSUBU_DSP_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MSUB_DSP_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MTHI_DSP_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MTHLIP_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MTLO_DSP_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULEQ_S_W_PHL_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULEQ_S_W_PHR_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULEU_S_PH_QBL_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULEU_S_PH_QBR_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULQ_RS_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULSAQ_S_W_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULTU_DSP_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULT_DSP_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^PACKRL_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^PICK_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^PICK_QB_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBLA_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBL_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBRA_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECEQU_PH_QBR_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECEQ_W_PHL_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECEQ_W_PHR_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBLA_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBL_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBRA_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECEU_PH_QBR_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECRQU_S_QB_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_PH_W_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_QB_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECRQ_RS_PH_W_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^RADDU_W_QB_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^RDDSP_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^REPLV_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^REPLV_QB_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^REPL_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^REPL_QB_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHILOV_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHILO_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHLLV_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHLLV_QB_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHLLV_S_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHLLV_S_W_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHLL_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHLL_QB_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHLL_S_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHLL_S_W_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRAV_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_W_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRA_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_W_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRLV_QB_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRL_QB_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBQ_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBQ_S_PH_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBQ_S_W_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBU_QB_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBU_S_QB_MM$")>; +def : InstRW<[GenericDSPShort], (instregex "^WRDSP_MM$")>; + + +// microMIPS DSP R2 - hasDSP, HasDSPR2, InMicroMips +// ================================================ + +def : InstRW<[GenericDSPShort], (instregex "^ABSQ_S_QB_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDQH_PH_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDQH_R_PH_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDQH_R_W_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDQH_W_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDUH_QB_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDUH_R_QB_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDU_PH_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^ADDU_S_PH_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^APPEND_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^BALIGN_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_EQ_QB_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_LE_QB_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^CMPGDU_LT_QB_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPA_W_PH_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPAQX_SA_W_PH_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPAQX_S_W_PH_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPAX_W_PH_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPS_W_PH_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPSQX_S_W_PH_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPSQX_SA_W_PH_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^DPSX_W_PH_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^MUL_PH_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^MUL_S_PH_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULQ_RS_W_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULQ_S_PH_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULQ_S_W_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^MULSA_W_PH_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECR_QB_PH_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECR_SRA_PH_W_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^PRECR_SRA_R_PH_W_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^PREPEND_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRA_QB_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRA_R_QB_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRAV_QB_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRAV_R_QB_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRL_PH_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^SHRLV_PH_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBQH_PH_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBQH_R_PH_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBQH_W_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBQH_R_W_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBU_PH_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBU_S_PH_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBUH_QB_MMR2$")>; +def : InstRW<[GenericDSPShort], (instregex "^SUBUH_R_QB_MMR2$")>; + +// microMIPS DSP R3 - hasDSP, hasDSPR2, hasDSPR3, InMicroMips +// ========================================================== + +def : InstRW<[GenericDSPShort], (instregex "^BPOSGE32C_MMR3$")>; + +// MIPS MSA ASE - hasMSA +// ===================== + +def GenericWriteMSAShortLogic : SchedWriteRes<[GenericIssueFPUS]>; +def GenericWriteMSAShortInt : SchedWriteRes<[GenericIssueFPUS]> { +let Latency = 2; +} +def GenericWriteMoveOtherUnitsToFPU : SchedWriteRes<[GenericIssueFPUS]>; +def GenericWriteMSAOther3 : SchedWriteRes<[GenericIssueFPUS]> { +let Latency = 3; +} +def GenericWriteMSALongInt : SchedWriteRes<[GenericIssueFPUS]> { +let Latency = 5; +} +def GenericWriteFPUDivI : SchedWriteRes<[GenericFPQ]> { + let Latency = 33; + let ResourceCycles = [ 33 ]; +} + +// FPUS is also used in moves from floating point and MSA registers to general +// purpose registers. +def GenericWriteMoveFPUSToOtherUnits : SchedWriteRes<[GenericIssueFPUS]> { + let Latency = 0; +} + +// FPUL is also used in moves from floating point and MSA registers to general +// purpose registers. +def GenericWriteMoveFPULToOtherUnits : SchedWriteRes<[GenericIssueFPUL]>; + + +// adds_a.[bhwd], adds_[asu].[bhwd], addvi?.[bhwd], asub_[us].[bhwd], +// aver?_[us].[bhwd] +def : InstRW<[GenericWriteMSAShortInt], (instregex "^ADD_A_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortInt], (instregex "^ADDS_[ASU]_[BHWD]$")>; + +// TODO: ADDVI_[BHW] might be 1 cycle latency rather than 2. Need to confirm it. +// add.[bhwd], addvi.[bhwd], asub_[us].[bhwd], ave.[bhwd], aver.[bhwd] +def : InstRW<[GenericWriteMSAShortInt], (instregex "^ADDVI?_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortInt], (instregex "^ASUB_[US].[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortInt], (instregex "^AVER?_[US].[BHWD]$")>; + +// and.v, andi.b, move.v, ldi.[bhwd], xor.v, nor.v, xori.b, nori.b +def : InstRW<[GenericWriteMSAShortLogic], (instregex "^MOVE_V$")>; +def : InstRW<[GenericWriteMSAShortLogic], (instregex "^LDI_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)_V$")>; +def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)I_B$")>; +def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)I_B$")>; + +// vshf.[bhwd], binsl.[bhwd], binsr.[bhwd], insert.[bhwd], sld?.[bhwd], +// bset.[bhwd], bclr.[bhwd], bneg.[bhwd], bsel_v, bseli_b +def : InstRW<[GenericWriteMSAShortInt], (instregex "^VSHF_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BINSL|BINSLI)_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BINSR|BINSRI)_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortInt], (instregex "^INSERT_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortInt], (instregex "^(SLD|SLDI)_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BSET|BSETI)_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BCLR|BCLRI)_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BNEG|BNEGI)_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortInt], (instregex "^(BSEL_V|BSELI_B)$")>; +def : InstRW<[GenericWriteMSAShortInt], (instregex "^BMN*Z.*$")>; + +// pcnt.[bhwd], sat_s.[bhwd], sat_u.bhwd] +def : InstRW<[GenericWriteMSAOther3], (instregex "^PCNT_[BHWD]$")>; +def : InstRW<[GenericWriteMSAOther3], (instregex "^SAT_(S|U)_[BHWD]$")>; + +// bnz.[bhwdv], cfcmsa, ctcmsa +def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(BNZ|BZ)_[BHWDV]$")>; +def : InstRW<[GenericWriteMSAShortLogic], (instregex "^C(F|T)CMSA$")>; + +// shf.[bhw], fill[bhwd], splat?.[bhwd] +def : InstRW<[GenericWriteMSAShortInt], (instregex "^SHF_[BHW]$")>; +def : InstRW<[GenericWriteMSAShortInt], (instregex "^FILL_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortInt], (instregex "^(SPLAT|SPLATI)_[BHWD]$")>; + +// pcnt.[bhwd], sat_s.[bhwd], sat_u.bhwd] +def : InstRW<[GenericWriteMSAOther3], (instregex "^PCNT_[BHWD]$")>; +def : InstRW<[GenericWriteMSAOther3], (instregex "^SAT_(S|U)_[BHWD]$")>; + +// fexp2_w, fexp2_d +def : InstRW<[GenericWriteFPUS], (instregex "^FEXP2_(W|D)$")>; + +// compare, converts, round to int, floating point truncate. +def : InstRW<[GenericWriteFPUS], (instregex "^(CLT|CLTI)_(S|U)_[BHWD]$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^(CLE|CLEI)_(S|U)_[BHWD]$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^(CEQ|CEQI)_[BHWD]$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^CMP_UN_(S|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^CMP_UEQ_(S|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^CMP_EQ_(S|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^CMP_LT_(S|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^CMP_ULT_(S|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^CMP_LE_(S|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^CMP_ULE_(S|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FS(AF|EQ|LT|LE|NE|OR)_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FSUEQ_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FSULE_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FSULT_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FSUNE_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FSUN_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FCAF_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FCEQ_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FCLE_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FCLT_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FCNE_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FCOR_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FCUEQ_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FCULE_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FCULT_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FCUNE_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FCUN_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FABS_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FFINT_(U|S)_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FFQL_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FFQR_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FTINT_(U|S)_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FRINT_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FTQ_(H|W)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FTRUNC_(U|S)_(W|D)$")>; + +// fexdo.[hw], fexupl.[wd], fexupr.[wd] +def : InstRW<[GenericWriteFPUS], (instregex "^FEXDO_(H|W)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FEXUPL_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FEXUPR_(W|D)$")>; + +// fclass.[wd], fmax.[wd], fmax_a.[wd], fmin.[wd], fmin_a.[wd], flog2.[wd] +def : InstRW<[GenericWriteFPUS], (instregex "^FCLASS_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FMAX_A_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FMAX_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FMIN_A_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FMIN_(W|D)$")>; +def : InstRW<[GenericWriteFPUS], (instregex "^FLOG2_(W|D)$")>; + +// interleave right/left, interleave even/odd, insert +def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(ILVR|ILVL)_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(ILVEV|ILVOD)_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortLogic], (instregex "^INSVE_[BHWD]$")>; + +// subs_?.[bhwd], subsus_?.[bhwd], subsuu_?.[bhwd], subvi.[bhwd], subv.[bhwd], +def : InstRW<[GenericWriteMSAShortInt], (instregex "^SUBS_(S|U)_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortInt], (instregex "^SUBSUS_(S|U)_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortInt], (instregex "^SUBSUU_(S|U)_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortInt], (instregex "^SUBVI_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortInt], (instregex "^SUBV_[BHWD]$")>; + +// mod_[su].[bhwd], div_[su].[bhwd] +def : InstRW<[GenericWriteFPUDivI], (instregex "^MOD_(S|U)_[BHWD]$")>; +def : InstRW<[GenericWriteFPUDivI], (instregex "^DIV_(S|U)_[BHWD]$")>; + +// hadd_[su].[bhwd], hsub_[su].[bhwd], max_[sua].[bhwd], min_[sua].[bhwd], +// maxi_[su].[bhwd], mini_[su].[bhwd], sra?.[bhwd], srar?.[bhwd], srlr.[bhwd], +// sll?.[bhwd], pckev.[bhwd], pckod.[bhwd], nloc.[bhwd], nlzc.[bhwd], +// insve.[bhwd] +def : InstRW<[GenericWriteMSAShortLogic], (instregex "^HADD_(S|U)_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortLogic], (instregex "^HSUB_(S|U)_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(MAX|MIN)_S_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(MAX|MIN)_U_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(MAX|MIN)_A_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortLogic], + (instregex "^(MAXI|MINI)_(S|U)_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SRA|SRAI)_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SRL|SRLI)_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SRAR|SRARI)_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SRLR|SRLRI)_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(SLL|SLLI)_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(PCKEV|PCKOD)_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortLogic], (instregex "^(NLOC|NLZC)_[BHWD]$")>; +def : InstRW<[GenericWriteMSAShortLogic], (instregex "^INSVE_[BHWD]$")>; + +// dpadd_?.[bhwd], dpsub_?.[bhwd], dotp_?.[bhwd], msubv.[bhwd], maddv.[bhwd] +// mulv.[bhwd]. +def : InstRW<[GenericWriteMSALongInt], (instregex "^DPADD_(S|U)_[HWD]$")>; +def : InstRW<[GenericWriteMSALongInt], (instregex "^DPSUB_(S|U)_[HWD]$")>; +def : InstRW<[GenericWriteMSALongInt], (instregex "^DOTP_(S|U)_[HWD]$")>; +def : InstRW<[GenericWriteMSALongInt], (instregex "^MSUBV_[BHWD]$")>; +def : InstRW<[GenericWriteMSALongInt], (instregex "^MADDV_[BHWD]$")>; +def : InstRW<[GenericWriteMSALongInt], (instregex "^MULV_[BHWD]$")>; + +// madd?.q.[hw], msub?.q.[hw], mul?.q.[hw] +def : InstRW<[GenericWriteMSALongInt], (instregex "^MADDR_Q_[HW]$")>; +def : InstRW<[GenericWriteMSALongInt], (instregex "^MADD_Q_[HW]$")>; +def : InstRW<[GenericWriteMSALongInt], (instregex "^MSUBR_Q_[HW]$")>; +def : InstRW<[GenericWriteMSALongInt], (instregex "^MSUB_Q_[HW]$")>; +def : InstRW<[GenericWriteMSALongInt], (instregex "^MULR_Q_[HW]$")>; +def : InstRW<[GenericWriteMSALongInt], (instregex "^MUL_Q_[HW]$")>; + +// fadd.[dw], fmadd.[dw], fmul.[dw], frcp.[dw], frsqrt.[dw], fsqrt.[dw] +// fsub.[dw], fdiv.[dw] +def : InstRW<[GenericWriteFPUL], (instregex "^FADD_[DW]$")>; +def : InstRW<[GenericWriteFPUL], (instregex "^FMADD_[DW]$")>; +def : InstRW<[GenericWriteFPUL], (instregex "^FMSUB_[DW]$")>; +def : InstRW<[GenericWriteFPUL], (instregex "^FMUL_[DW]$")>; +def : InstRW<[GenericWriteFPUL], (instregex "^FRCP_[DW]$")>; +def : InstRW<[GenericWriteFPUL], (instregex "^FRSQRT_[DW]$")>; +def : InstRW<[GenericWriteFPUL], (instregex "^FSQRT_[DW]$")>; +def : InstRW<[GenericWriteFPUL], (instregex "^FSUB_[DW]$")>; +def : InstRW<[GenericWriteFPUL], (instregex "^FDIV_[DW]$")>; + +// copy.[su]_[bhwd] +def : InstRW<[GenericWriteFPUMoveGPRFPU], (instregex "^COPY_U_[BHW]$")>; +def : InstRW<[GenericWriteFPUMoveGPRFPU], (instregex "^COPY_S_[BHWD]$")>; + +def : InstRW<[GenericWriteFPUStore], (instregex "^ST_[BHWD]$")>; +def : InstRW<[GenericWriteFPULoad], (instregex "^LD_[BHWD]$")>; +} diff --git a/contrib/llvm/lib/Target/Mips/MipsScheduleP5600.td b/contrib/llvm/lib/Target/Mips/MipsScheduleP5600.td index cee4287..882a241 100644 --- a/contrib/llvm/lib/Target/Mips/MipsScheduleP5600.td +++ b/contrib/llvm/lib/Target/Mips/MipsScheduleP5600.td @@ -13,7 +13,14 @@ def MipsP5600Model : SchedMachineModel { int LoadLatency = 4; int MispredictPenalty = 8; // TODO: Estimated - let CompleteModel = 0; + let CompleteModel = 1; + + list<Predicate> UnsupportedFeatures = [HasMips32r6, HasMips64r6, + HasMips64, HasMips64r2, HasCnMips, + InMicroMips, InMips16Mode, + HasMicroMips32r6, HasMicroMips64r6, + HasDSP, HasDSPR2]; + } let SchedModel = MipsP5600Model in { @@ -31,7 +38,8 @@ def P5600WriteALU : SchedWriteRes<[P5600IssueALU]>; // and, lui, nor, or, slti, sltiu, sub, subu, xor def : ItinRW<[P5600WriteALU], - [II_AND, II_LUI, II_NOR, II_OR, II_SLTI_SLTIU, II_SUBU, II_XOR]>; + [II_AND, II_LUI, II_NOR, II_OR, II_SLTI_SLTIU, II_SUB, II_SUBU, + II_XOR]>; // AGQ Pipelines // ============= @@ -53,11 +61,22 @@ def P5600WriteJumpAndLink : SchedWriteRes<[P5600IssueCTISTD, P5600CTISTD]> { let Latency = 2; } -// b, beq, beql, bg[et]z, bl[et]z, bne, bnel, j, syscall, jal, bltzal, jalx, +// b, beq, beql, bg[et]z, bl[et]z, bne, bnel, j, syscall, jal, bltzal, // jalr, jr.hb, jr -def : ItinRW<[P5600WriteJump], [II_B, II_BCC, II_BCCZ, II_BCCZAL, II_J, II_JR]>; -def : ItinRW<[P5600WriteJumpAndLink], [II_JAL, II_JALR]>; +def : ItinRW<[P5600WriteJump], [II_B, II_BCC, II_BCCZ, II_BCCZAL, II_J, II_JR, + II_JR_HB, II_DERET, II_ERET, II_ERETNC, + II_SYSCALL, II_BREAK, II_SDBBP, II_SSNOP, + II_TEQ, II_TEQI, II_TGE, II_TGEI, II_TGEIU, + II_TGEU, II_TLT, II_TLTI, II_TLTU, II_TNE, + II_TNEI, II_TRAP, II_TTLTIU, II_WAIT, + II_PAUSE]>; + +def : ItinRW<[P5600WriteJumpAndLink], [II_JAL, II_JALR, II_JALR_HB]>; +def P5600COP0 : SchedWriteRes<[P5600IssueCTISTD, P5600CTISTD]>; + +def : ItinRW<[P5600COP0], [II_TLBINV, II_TLBINVF, II_TLBP, II_TLBR, II_TLBWI, + II_TLBWR, II_MFC0, II_MTC0]>; // LDST Pipeline // ------------- @@ -69,7 +88,7 @@ def P5600WriteLoadShifted : SchedWriteRes<[P5600IssueLDST, P5600CTISTD]> { let Latency = 4; } -def P5600WritePref : SchedWriteRes<[P5600IssueLDST]>; +def P5600WriteCache : SchedWriteRes<[P5600IssueLDST]>; def P5600WriteStore : SchedWriteRes<[P5600IssueLDST, P5600CTISTD]> { // FIXME: This is a bit pessimistic. P5600CTISTD is only used during cycle 2 @@ -87,21 +106,21 @@ def P5600WriteLoadToOtherUnits : SchedWriteRes<[P5600IssueLDST]> { } // l[bhw], l[bh]u, ll -def : ItinRW<[P5600WriteLoad], [II_LB, II_LBU, II_LH, II_LHU, II_LW, II_LWU]>; +def : ItinRW<[P5600WriteLoad], [II_LB, II_LBE, II_LBU, II_LBUE, II_LH, II_LHE, + II_LHU, II_LHUE, II_LW, II_LWE, II_LL, II_LLE, + II_LWPC]>; // lw[lr] -def : ItinRW<[P5600WriteLoadShifted], [II_LWL, II_LWR]>; +def : ItinRW<[P5600WriteLoadShifted], [II_LWL, II_LWLE, II_LWR, II_LWRE]>; // s[bhw], sw[lr] -def : ItinRW<[P5600WriteStore], [II_SB, II_SH, II_SW, II_SWL, II_SWR]>; - -// pref -// (this instruction does not exist in the backend yet) -def : ItinRW<[P5600WritePref], []>; +def : ItinRW<[P5600WriteStore], [II_SB, II_SBE, II_SH, II_SHE, II_SW, II_SWE, + II_SWL, II_SWLE, II_SWR, II_SWRE, II_SC, + II_SCE]>; -// sc -// (this instruction does not exist in the backend yet) -def : ItinRW<[P5600WriteStore], []>; +// pref, cache, sync, synci +def : ItinRW<[P5600WriteCache], [II_PREF, II_PREFE, II_CACHE, II_CACHEE, + II_SYNC, II_SYNCI]>; // LDST is also used in moves from general purpose registers to floating point // and MSA. @@ -134,11 +153,11 @@ def P5600WriteAL2MAdd: SchedWriteRes<[P5600IssueAL2, P5600CTISTD]> { let Latency = 5; } -// clo, clz, di, mfhi, mflo -def : ItinRW<[P5600WriteAL2], [II_CLO, II_CLZ, II_MFHI_MFLO]>; +// clo, clz, di, ei, mfhi, mflo +def : ItinRW<[P5600WriteAL2], [II_CLO, II_CLZ, II_DI, II_EI, II_MFHI_MFLO]>; // ehb, rdhwr, rdpgpr, wrpgpr, wsbh -def : ItinRW<[P5600WriteAL2ShadowMov], [II_RDHWR]>; +def : ItinRW<[P5600WriteAL2ShadowMov], [II_EHB, II_RDHWR, II_WSBH]>; // mov[nz] def : ItinRW<[P5600WriteAL2CondMov], [II_MOVN, II_MOVZ]>; @@ -156,8 +175,7 @@ def : ItinRW<[P5600WriteAL2MAdd], [II_MADD, II_MADDU, II_MSUB, II_MSUBU, II_MTHI_MTLO]>; // ext, ins -def : ItinRW<[P5600WriteAL2BitExt], - [II_EXT, II_INS]>; +def : ItinRW<[P5600WriteAL2BitExt], [II_EXT, II_INS]>; // Either ALU or AL2 Pipelines // --------------------------- @@ -176,9 +194,10 @@ def P5600WriteEitherALU : SchedWriteVariant< // add, addi, addiu, addu, andi, ori, rotr, se[bh], sllv?, sr[al]v?, slt, sltu, // xori def : ItinRW<[P5600WriteEitherALU], - [II_ADDI, II_ADDIU, II_ANDI, II_ORI, II_ROTR, II_SEB, II_SEH, + [II_ADD, II_ADDI, II_ADDIU, II_ANDI, II_ORI, II_ROTR, II_SEB, II_SEH, II_SLT_SLTU, II_SLL, II_SRA, II_SRL, II_XORI, II_ADDU, II_SLLV, - II_SRAV, II_SRLV]>; + II_SRAV, II_SRLV, II_LSA]>; +def : InstRW<[], (instrs COPY)>; // FPU Pipelines // ============= @@ -193,6 +212,11 @@ def P5600FPUDivSqrt : ProcResource<2>; def P5600WriteFPUS : SchedWriteRes<[P5600IssueFPUS]>; def P5600WriteFPUL : SchedWriteRes<[P5600IssueFPUL]> { let Latency = 4; } def P5600WriteFPUL_MADDSUB : SchedWriteRes<[P5600IssueFPUL]> { let Latency = 6; } +def P5600WriteFPUDivI : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> { + // Best/Common/Worst case = 7 / 23 / 27 + let Latency = 23; // Using common case + let ResourceCycles = [ 1, 23 ]; +} def P5600WriteFPUDivS : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> { // Best/Common/Worst case = 7 / 23 / 27 let Latency = 23; // Using common case @@ -236,6 +260,29 @@ def P5600WriteFPUSqrtD : SchedWriteRes<[P5600IssueFPUL, P5600FPUDivSqrt]> { def P5600WriteMSAShortLogic : SchedWriteRes<[P5600IssueFPUS]>; def P5600WriteMSAShortInt : SchedWriteRes<[P5600IssueFPUS]> { let Latency = 2; } def P5600WriteMoveOtherUnitsToFPU : SchedWriteRes<[P5600IssueFPUS]>; +def P5600WriteMSAOther3 : SchedWriteRes<[P5600IssueFPUS]> { let Latency = 3; } +def P5600WriteMSALongInt : SchedWriteRes<[P5600IssueFPUS]> { let Latency = 5; } + +// vshf.[bhwd], binsl.[bhwd], binsr.[bhwd], insert.[bhwd], sld?.[bhwd], +// bset.[bhwd], bclr.[bhwd], bneg.[bhwd], bsel_v, bseli_b +def : InstRW<[P5600WriteMSAShortInt], (instregex "^VSHF_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BINSL|BINSLI)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BINSR|BINSRI)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^INSERT_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^(SLD|SLDI)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BSET|BSETI)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BCLR|BCLRI)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BNEG|BNEGI)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BSEL_V|BSELI_B)$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^BMN*Z.*$")>; + +// pcnt.[bhwd], sat_s.[bhwd], sat_u.bhwd] +def : InstRW<[P5600WriteMSAOther3], (instregex "^PCNT_[BHWD]$")>; +def : InstRW<[P5600WriteMSAOther3], (instregex "^SAT_(S|U)_[BHWD]$")>; + +// bnz.[bhwdv], cfcmsa, ctcmsa +def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(BNZ|BZ)_[BHWDV]$")>; +def : InstRW<[P5600WriteMSAShortLogic], (instregex "^C(F|T)CMSA$")>; // FPUS is also used in moves from floating point and MSA registers to general // purpose registers. @@ -257,13 +304,16 @@ def : ItinRW<[P5600WriteFPUS], [II_ABS, II_MOVF_D, II_MOVF_S, II_MOVT_D, II_MOVT_S, II_MOV_D, II_MOV_S, II_NEG]>; // adds_a.[bhwd], adds_[asu].[bhwd], addvi?.[bhwd], asub_[us].[bhwd], -// aver?_[us].[bhwd] +// aver?_[us].[bhwd], shf.[bhw], fill[bhwd], splat?.[bhwd] def : InstRW<[P5600WriteMSAShortInt], (instregex "^ADD_A_[BHWD]$")>; def : InstRW<[P5600WriteMSAShortInt], (instregex "^ADDS_[ASU]_[BHWD]$")>; // TODO: ADDVI_[BHW] might be 1 cycle latency rather than 2. Need to confirm it. def : InstRW<[P5600WriteMSAShortInt], (instregex "^ADDVI?_[BHWD]$")>; def : InstRW<[P5600WriteMSAShortInt], (instregex "^ASUB_[US].[BHWD]$")>; def : InstRW<[P5600WriteMSAShortInt], (instregex "^AVER?_[US].[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^SHF_[BHW]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^FILL_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^(SPLAT|SPLATI)_[BHWD]$")>; // and.v, andi.b, move.v, ldi.[bhwd] def : InstRW<[P5600WriteMSAShortLogic], (instregex "^MOVE_V$")>; @@ -271,6 +321,111 @@ def : InstRW<[P5600WriteMSAShortLogic], (instregex "^LDI_[BHWD]$")>; def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)_V$")>; def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(AND|OR|[XN]OR)I_B$")>; +// vshf.[bhwd], binsl.[bhwd], binsr.[bhwd], insert.[bhwd], sld?.[bhwd], +// bset.[bhwd], bclr.[bhwd], bneg.[bhwd], bsel_v, bseli_b +def : InstRW<[P5600WriteMSAShortInt], (instregex "^VSHF_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BINSL|BINSLI)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BINSR|BINSRI)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^INSERT_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^(SLD|SLDI)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BSET|BSETI)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BCLR|BCLRI)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BNEG|BNEGI)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^(BSEL_V|BSELI_B)$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^BMN*Z.*$")>; + +// pcnt.[bhwd], sat_s.[bhwd], sat_u.bhwd] +def : InstRW<[P5600WriteMSAOther3], (instregex "^PCNT_[BHWD]$")>; +def : InstRW<[P5600WriteMSAOther3], (instregex "^SAT_(S|U)_[BHWD]$")>; + +// fexp2_w, fexp2_d +def : InstRW<[P5600WriteFPUS], (instregex "^FEXP2_(W|D)$")>; + +// compare, converts, round to int, floating point truncate. +def : InstRW<[P5600WriteFPUS], (instregex "^(CLT|CLTI)_(S|U)_[BHWD]$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^(CLE|CLEI)_(S|U)_[BHWD]$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^(CEQ|CEQI)_[BHWD]$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^CMP_UN_(S|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^CMP_UEQ_(S|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^CMP_EQ_(S|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^CMP_LT_(S|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^CMP_ULT_(S|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^CMP_LE_(S|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^CMP_ULE_(S|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FS(AF|EQ|LT|LE|NE|OR)_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FSUEQ_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FSULE_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FSULT_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FSUNE_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FSUN_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FCAF_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FCEQ_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FCLE_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FCLT_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FCNE_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FCOR_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FCUEQ_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FCULE_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FCULT_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FCUNE_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FCUN_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FABS_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FFINT_(U|S)_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FFQL_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FFQR_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FTINT_(U|S)_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FRINT_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FTQ_(H|W)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FTRUNC_(U|S)_(W|D)$")>; + +// fexdo.[hw], fexupl.[wd], fexupr.[wd] +def : InstRW<[P5600WriteFPUS], (instregex "^FEXDO_(H|W)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FEXUPL_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FEXUPR_(W|D)$")>; + +// fclass.[wd], fmax.[wd], fmax_a.[wd], fmin.[wd], fmin_a.[wd], flog2.[wd] +def : InstRW<[P5600WriteFPUS], (instregex "^FCLASS_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FMAX_A_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FMAX_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FMIN_A_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FMIN_(W|D)$")>; +def : InstRW<[P5600WriteFPUS], (instregex "^FLOG2_(W|D)$")>; + +// interleave right/left, interleave even/odd, insert +def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(ILVR|ILVL)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(ILVEV|ILVOD)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortLogic], (instregex "^INSVE_[BHWD]$")>; + +// subs_?.[bhwd], subsus_?.[bhwd], subsuu_?.[bhwd], subvi.[bhwd], subv.[bhwd], +def : InstRW<[P5600WriteMSAShortInt], (instregex "^SUBS_(S|U)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^SUBSUS_(S|U)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^SUBSUU_(S|U)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^SUBVI_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortInt], (instregex "^SUBV_[BHWD]$")>; + +// mod_[su].[bhwd], div_[su].[bhwd] +def : InstRW<[P5600WriteFPUDivI], (instregex "^MOD_(S|U)_[BHWD]$")>; +def : InstRW<[P5600WriteFPUDivI], (instregex "^DIV_(S|U)_[BHWD]$")>; + +// hadd_[su].[bhwd], hsub_[su].[bhwd], max_[sua].[bhwd], min_[sua].[bhwd], +// maxi_[su].[bhwd], mini_[su].[bhwd], sra?.[bhwd], srar?.[bhwd], srlr.[bhwd], +// sll?.[bhwd], pckev.[bhwd], pckod.[bhwd], nloc.[bhwd], nlzc.[bhwd], +// insve.[bhwd] +def : InstRW<[P5600WriteMSAShortLogic], (instregex "^HADD_(S|U)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortLogic], (instregex "^HSUB_(S|U)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(MAX|MIN)_S_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(MAX|MIN)_U_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(MAX|MIN)_A_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(MAXI|MINI)_(S|U)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SRA|SRAI)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SRL|SRLI)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SRAR|SRARI)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SRLR|SRLRI)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(SLL|SLLI)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(PCKEV|PCKOD)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(NLOC|NLZC)_[BHWD]$")>; +def : InstRW<[P5600WriteMSAShortLogic], (instregex "^INSVE_[BHWD]$")>; + // Long Pipe // ---------- // @@ -289,6 +444,41 @@ def : ItinRW<[P5600WriteFPUDivD], [II_DIV_D]>; def : ItinRW<[P5600WriteFPUSqrtS], [II_SQRT_S]>; def : ItinRW<[P5600WriteFPUSqrtD], [II_SQRT_D]>; +// frcp.[wd], frsqrt.[wd] +def : InstRW<[P5600WriteFPURsqrtD], (instregex "^FRCP_(W|D)$")>; +def : InstRW<[P5600WriteFPURsqrtD], (instregex "^FRSQRT_(W|D)$")>; + +def : ItinRW<[P5600WriteFPURsqrtD], [II_RECIP_D, II_RSQRT_D]>; +def : ItinRW<[P5600WriteFPURsqrtS], [II_RECIP_S, II_RSQRT_S]>; + +// fmadd.[wd], fmsubb.[wd], fdiv.[wd], fsqrt.[wd], fmul.[wd], fadd.[wd], +// fsub.[wd] +def : InstRW<[P5600WriteFPUL_MADDSUB], (instregex "^FMADD_(W|D)$")>; +def : InstRW<[P5600WriteFPUL_MADDSUB], (instregex "^FMSUB_(W|D)$")>; +def : InstRW<[P5600WriteFPUDivS], (instregex "^FDIV_W$")>; +def : InstRW<[P5600WriteFPUDivD], (instregex "^FDIV_D$")>; +def : InstRW<[P5600WriteFPUSqrtS], (instregex "^FSQRT_W$")>; +def : InstRW<[P5600WriteFPUSqrtD], (instregex "^FSQRT_D$")>; +def : InstRW<[P5600WriteFPUL], (instregex "^FMUL_(W|D)$")>; +def : InstRW<[P5600WriteFPUL], (instregex "^FADD_(W|D)$")>; +def : InstRW<[P5600WriteFPUL], (instregex "^FSUB_(W|D)$")>; + +// dpadd_?.[bhwd], dpsub_?.[bhwd], dotp_?.[bhwd], msubv.[bhwd], maddv.[bhwd] +// mulv.[bhwd]. +def : InstRW<[P5600WriteMSALongInt], (instregex "^DPADD_(S|U)_[HWD]$")>; +def : InstRW<[P5600WriteMSALongInt], (instregex "^DPSUB_(S|U)_[HWD]$")>; +def : InstRW<[P5600WriteMSALongInt], (instregex "^DOTP_(S|U)_[HWD]$")>; +def : InstRW<[P5600WriteMSALongInt], (instregex "^MSUBV_[BHWD]$")>; +def : InstRW<[P5600WriteMSALongInt], (instregex "^MADDV_[BHWD]$")>; +def : InstRW<[P5600WriteMSALongInt], (instregex "^MULV_[BHWD]$")>; + +def : InstRW<[P5600WriteMSALongInt], (instregex "^MADDR_Q_[HW]$")>; +def : InstRW<[P5600WriteMSALongInt], (instregex "^MADD_Q_[HW]$")>; +def : InstRW<[P5600WriteMSALongInt], (instregex "^MSUBR_Q_[HW]$")>; +def : InstRW<[P5600WriteMSALongInt], (instregex "^MSUB_Q_[HW]$")>; +def : InstRW<[P5600WriteMSALongInt], (instregex "^MULR_Q_[HW]$")>; +def : InstRW<[P5600WriteMSALongInt], (instregex "^MUL_Q_[HW]$")>; + // madd.[ds], msub.[ds], nmadd.[ds], nmsub.[ds], // Operand 0 is read on cycle 5. All other operands are read on operand 0. def : ItinRW<[SchedReadAdvance<5>, P5600WriteFPUL_MADDSUB], @@ -348,19 +538,24 @@ def P5600WriteLoadFPU : WriteSequence<[P5600WriteLoadToOtherUnits, // ctc1, mtc1, mthc1 def : ItinRW<[P5600WriteMoveGPRToFPU], [II_CTC1, II_MTC1, II_MTHC1]>; +// copy.[su]_[bhwd] +def : InstRW<[P5600WriteMoveFPUToGPR], (instregex "^COPY_U_[BHW]$")>; +def : InstRW<[P5600WriteMoveFPUToGPR], (instregex "^COPY_S_[BHWD]$")>; + // bc1[ft], cfc1, mfc1, mfhc1, movf, movt def : ItinRW<[P5600WriteMoveFPUToGPR], - [II_BC1F, II_BC1T, II_CFC1, II_MFC1, II_MFHC1, II_MOVF, II_MOVT]>; + [II_BC1F, II_BC1FL, II_BC1T, II_BC1TL, II_CFC1, II_MFC1, II_MFHC1, II_MOVF, II_MOVT]>; // swc1, swxc1, st.[bhwd] -def : ItinRW<[P5600WriteStoreFPUS], [II_SWC1, II_SWXC1]>; +def : ItinRW<[P5600WriteStoreFPUS], [II_SDC1, II_SDXC1, II_SUXC1, II_SWC1, + II_SWXC1]>; def : InstRW<[P5600WriteStoreFPUS], (instregex "^ST_[BHWD]$")>; // movn.[ds], movz.[ds] def : ItinRW<[P5600WriteStoreFPUL], [II_MOVN_D, II_MOVN_S, II_MOVZ_D, II_MOVZ_S]>; // l[dw]x?c1, ld.[bhwd] -def : ItinRW<[P5600WriteLoadFPU], [II_LDC1, II_LDXC1, II_LWC1, II_LWXC1]>; +def : ItinRW<[P5600WriteLoadFPU], [II_LDC1, II_LDXC1, II_LWC1, II_LWXC1, II_LUXC1]>; def : InstRW<[P5600WriteLoadFPU], (instregex "LD_[BHWD]")>; // Unsupported Instructions @@ -370,11 +565,10 @@ def : InstRW<[P5600WriteLoadFPU], (instregex "LD_[BHWD]")>; // II_DADDIU, II_DADDU, II_DMFC1, II_DMTC1, II_DMULT, II_DMULTU, II_DROTR, // II_DROTR32, II_DROTRV, II_DDIV, II_DSLL, II_DSLL32, II_DSLLV, II_DSRA, // II_DSRA32, II_DSRAV, II_DSRL, II_DSRL32, II_DSRLV, II_DSUBU, II_DDIVU, -// II_JALRC, II_LD, II_LD[LR], II_LUXC1, II_RESTORE, II_SAVE, II_SD, II_SDC1, -// II_SDL, II_SDR, II_SDXC1 +// II_JALRC, II_LD, II_LD[LR], II_RESTORE, II_SAVE, II_SD, II_SDC1, II_SD[LR] // // The following instructions are never valid on P5600. -// addq.ph, rdhwr, repl.ph, repl.qb, subq.ph, subu_s.qb +// addq.ph, repl.ph, repl.qb, subq.ph, subu_s.qb // // Guesswork // ========= diff --git a/contrib/llvm/lib/Target/Mips/MipsTargetMachine.cpp b/contrib/llvm/lib/Target/Mips/MipsTargetMachine.cpp index 80641ed..bb48188 100644 --- a/contrib/llvm/lib/Target/Mips/MipsTargetMachine.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsTargetMachine.cpp @@ -39,10 +39,10 @@ using namespace llvm; extern "C" void LLVMInitializeMipsTarget() { // Register the target. - RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget); - RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget); - RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target); - RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget); + RegisterTargetMachine<MipsebTargetMachine> X(getTheMipsTarget()); + RegisterTargetMachine<MipselTargetMachine> Y(getTheMipselTarget()); + RegisterTargetMachine<MipsebTargetMachine> A(getTheMips64Target()); + RegisterTargetMachine<MipselTargetMachine> B(getTheMips64elTarget()); } static std::string computeDataLayout(const Triple &TT, StringRef CPU, @@ -208,7 +208,6 @@ public: void addIRPasses() override; bool addInstSelector() override; - void addMachineSSAOptimization() override; void addPreEmitPass() override; void addPreRegAlloc() override; @@ -237,14 +236,8 @@ bool MipsPassConfig::addInstSelector() { return false; } -void MipsPassConfig::addMachineSSAOptimization() { - addPass(createMipsOptimizePICCallPass(getMipsTargetMachine())); - TargetPassConfig::addMachineSSAOptimization(); -} - void MipsPassConfig::addPreRegAlloc() { - if (getOptLevel() == CodeGenOpt::None) - addPass(createMipsOptimizePICCallPass(getMipsTargetMachine())); + addPass(createMipsOptimizePICCallPass(getMipsTargetMachine())); } TargetIRAnalysis MipsTargetMachine::getTargetIRAnalysis() { diff --git a/contrib/llvm/lib/Target/Mips/MipsTargetObjectFile.cpp b/contrib/llvm/lib/Target/Mips/MipsTargetObjectFile.cpp index 3bd4567..c5d6a05 100644 --- a/contrib/llvm/lib/Target/Mips/MipsTargetObjectFile.cpp +++ b/contrib/llvm/lib/Target/Mips/MipsTargetObjectFile.cpp @@ -61,23 +61,23 @@ static bool IsInSmallSection(uint64_t Size) { /// Return true if this global address should be placed into small data/bss /// section. -bool MipsTargetObjectFile:: -IsGlobalInSmallSection(const GlobalValue *GV, const TargetMachine &TM) const { +bool MipsTargetObjectFile::IsGlobalInSmallSection( + const GlobalObject *GO, const TargetMachine &TM) const { // We first check the case where global is a declaration, because finding // section kind using getKindForGlobal() is only allowed for global // definitions. - if (GV->isDeclaration() || GV->hasAvailableExternallyLinkage()) - return IsGlobalInSmallSectionImpl(GV, TM); + if (GO->isDeclaration() || GO->hasAvailableExternallyLinkage()) + return IsGlobalInSmallSectionImpl(GO, TM); - return IsGlobalInSmallSection(GV, TM, getKindForGlobal(GV, TM)); + return IsGlobalInSmallSection(GO, TM, getKindForGlobal(GO, TM)); } /// Return true if this global address should be placed into small data/bss /// section. bool MipsTargetObjectFile:: -IsGlobalInSmallSection(const GlobalValue *GV, const TargetMachine &TM, +IsGlobalInSmallSection(const GlobalObject *GO, const TargetMachine &TM, SectionKind Kind) const { - return (IsGlobalInSmallSectionImpl(GV, TM) && + return (IsGlobalInSmallSectionImpl(GO, TM) && (Kind.isData() || Kind.isBSS() || Kind.isCommon())); } @@ -85,7 +85,7 @@ IsGlobalInSmallSection(const GlobalValue *GV, const TargetMachine &TM, /// section. This method does all the work, except for checking the section /// kind. bool MipsTargetObjectFile:: -IsGlobalInSmallSectionImpl(const GlobalValue *GV, +IsGlobalInSmallSectionImpl(const GlobalObject *GO, const TargetMachine &TM) const { const MipsSubtarget &Subtarget = *static_cast<const MipsTargetMachine &>(TM).getSubtargetImpl(); @@ -95,39 +95,37 @@ IsGlobalInSmallSectionImpl(const GlobalValue *GV, return false; // Only global variables, not functions. - const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GV); + const GlobalVariable *GVA = dyn_cast<GlobalVariable>(GO); if (!GVA) return false; // Enforce -mlocal-sdata. - if (!LocalSData && GV->hasLocalLinkage()) + if (!LocalSData && GVA->hasLocalLinkage()) return false; // Enforce -mextern-sdata. - if (!ExternSData && ((GV->hasExternalLinkage() && GV->isDeclaration()) || - GV->hasCommonLinkage())) + if (!ExternSData && ((GVA->hasExternalLinkage() && GVA->isDeclaration()) || + GVA->hasCommonLinkage())) return false; - Type *Ty = GV->getValueType(); + Type *Ty = GVA->getValueType(); return IsInSmallSection( - GV->getParent()->getDataLayout().getTypeAllocSize(Ty)); + GVA->getParent()->getDataLayout().getTypeAllocSize(Ty)); } -MCSection * -MipsTargetObjectFile::SelectSectionForGlobal(const GlobalValue *GV, - SectionKind Kind, Mangler &Mang, - const TargetMachine &TM) const { +MCSection *MipsTargetObjectFile::SelectSectionForGlobal( + const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const { // TODO: Could also support "weak" symbols as well with ".gnu.linkonce.s.*" // sections? // Handle Small Section classification here. - if (Kind.isBSS() && IsGlobalInSmallSection(GV, TM, Kind)) + if (Kind.isBSS() && IsGlobalInSmallSection(GO, TM, Kind)) return SmallBSSSection; - if (Kind.isData() && IsGlobalInSmallSection(GV, TM, Kind)) + if (Kind.isData() && IsGlobalInSmallSection(GO, TM, Kind)) return SmallDataSection; // Otherwise, we work the same as ELF. - return TargetLoweringObjectFileELF::SelectSectionForGlobal(GV, Kind, Mang,TM); + return TargetLoweringObjectFileELF::SelectSectionForGlobal(GO, Kind, TM); } /// Return true if this constant should be placed into small data section. @@ -150,3 +148,11 @@ MCSection *MipsTargetObjectFile::getSectionForConstant(const DataLayout &DL, // Otherwise, we work the same as ELF. return TargetLoweringObjectFileELF::getSectionForConstant(DL, Kind, C, Align); } + +const MCExpr * +MipsTargetObjectFile::getDebugThreadLocalSymbol(const MCSymbol *Sym) const { + const MCExpr *Expr = + MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); + return MCBinaryExpr::createAdd( + Expr, MCConstantExpr::create(0x8000, getContext()), getContext()); +} diff --git a/contrib/llvm/lib/Target/Mips/MipsTargetObjectFile.h b/contrib/llvm/lib/Target/Mips/MipsTargetObjectFile.h index 9840769..a37ec15 100644 --- a/contrib/llvm/lib/Target/Mips/MipsTargetObjectFile.h +++ b/contrib/llvm/lib/Target/Mips/MipsTargetObjectFile.h @@ -18,21 +18,21 @@ class MipsTargetMachine; MCSection *SmallDataSection; MCSection *SmallBSSSection; const MipsTargetMachine *TM; + + bool IsGlobalInSmallSection(const GlobalObject *GO, const TargetMachine &TM, + SectionKind Kind) const; + bool IsGlobalInSmallSectionImpl(const GlobalObject *GO, + const TargetMachine &TM) const; public: void Initialize(MCContext &Ctx, const TargetMachine &TM) override; /// Return true if this global address should be placed into small data/bss /// section. - bool IsGlobalInSmallSection(const GlobalValue *GV, const TargetMachine &TM, - SectionKind Kind) const; - bool IsGlobalInSmallSection(const GlobalValue *GV, + bool IsGlobalInSmallSection(const GlobalObject *GO, const TargetMachine &TM) const; - bool IsGlobalInSmallSectionImpl(const GlobalValue *GV, - const TargetMachine &TM) const; - MCSection *SelectSectionForGlobal(const GlobalValue *GV, SectionKind Kind, - Mangler &Mang, + MCSection *SelectSectionForGlobal(const GlobalObject *GO, SectionKind Kind, const TargetMachine &TM) const override; /// Return true if this constant should be placed into small data section. @@ -42,6 +42,8 @@ class MipsTargetMachine; MCSection *getSectionForConstant(const DataLayout &DL, SectionKind Kind, const Constant *C, unsigned &Align) const override; + /// Describe a TLS variable address within debug info. + const MCExpr *getDebugThreadLocalSymbol(const MCSymbol *Sym) const override; }; } // end namespace llvm diff --git a/contrib/llvm/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp b/contrib/llvm/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp index 6a65943..4c1edfa 100644 --- a/contrib/llvm/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp +++ b/contrib/llvm/lib/Target/Mips/TargetInfo/MipsTargetInfo.cpp @@ -12,20 +12,37 @@ #include "llvm/Support/TargetRegistry.h" using namespace llvm; -Target llvm::TheMipsTarget, llvm::TheMipselTarget; -Target llvm::TheMips64Target, llvm::TheMips64elTarget; +Target &llvm::getTheMipsTarget() { + static Target TheMipsTarget; + return TheMipsTarget; +} +Target &llvm::getTheMipselTarget() { + static Target TheMipselTarget; + return TheMipselTarget; +} +Target &llvm::getTheMips64Target() { + static Target TheMips64Target; + return TheMips64Target; +} +Target &llvm::getTheMips64elTarget() { + static Target TheMips64elTarget; + return TheMips64elTarget; +} extern "C" void LLVMInitializeMipsTargetInfo() { RegisterTarget<Triple::mips, - /*HasJIT=*/true> X(TheMipsTarget, "mips", "Mips"); + /*HasJIT=*/true> + X(getTheMipsTarget(), "mips", "Mips"); RegisterTarget<Triple::mipsel, - /*HasJIT=*/true> Y(TheMipselTarget, "mipsel", "Mipsel"); + /*HasJIT=*/true> + Y(getTheMipselTarget(), "mipsel", "Mipsel"); RegisterTarget<Triple::mips64, - /*HasJIT=*/true> A(TheMips64Target, "mips64", "Mips64 [experimental]"); + /*HasJIT=*/true> + A(getTheMips64Target(), "mips64", "Mips64 [experimental]"); RegisterTarget<Triple::mips64el, - /*HasJIT=*/true> B(TheMips64elTarget, - "mips64el", "Mips64el [experimental]"); + /*HasJIT=*/true> + B(getTheMips64elTarget(), "mips64el", "Mips64el [experimental]"); } |
