Pull in r227089 from upstream llvm trunk (by Vasileios Kalintiris):

  [mips] Enable arithmetic and binary operations for the i128 data type.

  Summary:
  This patch adds support for some operations that were missing from
  128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these
  changes we can support the __int128_t and __uint128_t data types
  from C/C++.

  Depends on D7125

  Reviewers: dsanders

  Subscribers: llvm-commits

  Differential Revision: http://reviews.llvm.org/D7143

This fixes "error in backend" messages, when compiling parts of
compiler-rt using 128-bit integer types for mips64.

Reported by:	sbruno
PR:		197259

1 files changed, 4 insertions, 0 deletions

diff --git a/contrib/llvm/lib/Target/Mips/MipsSEISelLowering.cpp b/contrib/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
index 29aac2e..3f865af 100644
--- a/contrib/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
+++ b/contrib/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
@@ -122,6 +122,8 @@ MipsSETargetLowering::MipsSETargetLowering(const MipsTargetMachine &TM,
     setOperationAction(ISD::MUL,              MVT::i64, Custom);
 
   if (Subtarget.isGP64bit()) {
+    setOperationAction(ISD::SMUL_LOHI,        MVT::i64, Custom);
+    setOperationAction(ISD::UMUL_LOHI,        MVT::i64, Custom);
     setOperationAction(ISD::MULHS,            MVT::i64, Custom);
     setOperationAction(ISD::MULHU,            MVT::i64, Custom);
     setOperationAction(ISD::SDIVREM,          MVT::i64, Custom);
@@ -200,6 +202,8 @@ MipsSETargetLowering::MipsSETargetLowering(const MipsTargetMachine &TM,
   if (Subtarget.hasMips64r6()) {
     // MIPS64r6 replaces the accumulator-based multiplies with a three register
     // instruction
+    setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
+    setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
     setOperationAction(ISD::MUL, MVT::i64, Legal);
     setOperationAction(ISD::MULHS, MVT::i64, Legal);
     setOperationAction(ISD::MULHU, MVT::i64, Legal);