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author | dim <dim@FreeBSD.org> | 2015-05-27 20:26:41 +0000 |
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committer | dim <dim@FreeBSD.org> | 2015-05-27 20:26:41 +0000 |
commit | 5ef8fd3549d38e883a31881636be3dc2a275de20 (patch) | |
tree | bd13a22d9db57ccf3eddbc07b32c18109521d050 /contrib/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp | |
parent | 77794ebe2d5718eb502c93ec32f8ccae4d8a0b7b (diff) | |
parent | 782067d0278612ee75d024b9b135c221c327e9e8 (diff) | |
download | FreeBSD-src-5ef8fd3549d38e883a31881636be3dc2a275de20.zip FreeBSD-src-5ef8fd3549d38e883a31881636be3dc2a275de20.tar.gz |
Merge llvm trunk r238337 from ^/vendor/llvm/dist, resolve conflicts, and
preserve our customizations, where necessary.
Diffstat (limited to 'contrib/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp')
-rw-r--r-- | contrib/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp index 3f5d6d8..535d1f9 100644 --- a/contrib/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp +++ b/contrib/llvm/lib/Target/Hexagon/HexagonMCInstLower.cpp @@ -15,7 +15,6 @@ #include "Hexagon.h" #include "HexagonAsmPrinter.h" #include "HexagonMachineFunctionInfo.h" -#include "MCTargetDesc/HexagonMCInst.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/IR/Constants.h" #include "llvm/IR/Mangler.h" @@ -35,11 +34,11 @@ static MCOperand GetSymbolRef(const MachineOperand& MO, const MCSymbol* Symbol, ME = MCBinaryExpr::CreateAdd(ME, MCConstantExpr::Create(MO.getOffset(), MC), MC); - return (MCOperand::CreateExpr(ME)); + return (MCOperand::createExpr(ME)); } // Create an MCInst from a MachineInstr -void llvm::HexagonLowerToMC(const MachineInstr* MI, HexagonMCInst& MCI, +void llvm::HexagonLowerToMC(MachineInstr const* MI, MCInst& MCI, HexagonAsmPrinter& AP) { MCI.setOpcode(MI->getOpcode()); @@ -54,20 +53,20 @@ void llvm::HexagonLowerToMC(const MachineInstr* MI, HexagonMCInst& MCI, case MachineOperand::MO_Register: // Ignore all implicit register operands. if (MO.isImplicit()) continue; - MCO = MCOperand::CreateReg(MO.getReg()); + MCO = MCOperand::createReg(MO.getReg()); break; case MachineOperand::MO_FPImmediate: { APFloat Val = MO.getFPImm()->getValueAPF(); // FP immediates are used only when setting GPRs, so they may be dealt // with like regular immediates from this point on. - MCO = MCOperand::CreateImm(*Val.bitcastToAPInt().getRawData()); + MCO = MCOperand::createImm(*Val.bitcastToAPInt().getRawData()); break; } case MachineOperand::MO_Immediate: - MCO = MCOperand::CreateImm(MO.getImm()); + MCO = MCOperand::createImm(MO.getImm()); break; case MachineOperand::MO_MachineBasicBlock: - MCO = MCOperand::CreateExpr + MCO = MCOperand::createExpr (MCSymbolRefExpr::Create(MO.getMBB()->getSymbol(), AP.OutContext)); break; |