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authordim <dim@FreeBSD.org>2011-06-12 18:01:31 +0000
committerdim <dim@FreeBSD.org>2011-06-12 18:01:31 +0000
commitd4c7939beafe09c033866ebd290e274af0cc826d (patch)
treea9b264321873e7d25e69b8671c9f705ebc6d30ee /contrib/llvm/lib/CodeGen/AllocationOrder.h
parentb164882ef981a8ed5c085469231831e221fa1323 (diff)
parentece02cd5829cea836e9365b0845a8ef042d17b0a (diff)
downloadFreeBSD-src-d4c7939beafe09c033866ebd290e274af0cc826d.zip
FreeBSD-src-d4c7939beafe09c033866ebd290e274af0cc826d.tar.gz
Upgrade our copy of llvm/clang to r132879, from upstream's trunk.
Diffstat (limited to 'contrib/llvm/lib/CodeGen/AllocationOrder.h')
-rw-r--r--contrib/llvm/lib/CodeGen/AllocationOrder.h25
1 files changed, 21 insertions, 4 deletions
diff --git a/contrib/llvm/lib/CodeGen/AllocationOrder.h b/contrib/llvm/lib/CodeGen/AllocationOrder.h
index 61fd8f8..d1e48a1 100644
--- a/contrib/llvm/lib/CodeGen/AllocationOrder.h
+++ b/contrib/llvm/lib/CodeGen/AllocationOrder.h
@@ -19,15 +19,16 @@
namespace llvm {
-class BitVector;
+class RegisterClassInfo;
class VirtRegMap;
class AllocationOrder {
const unsigned *Begin;
const unsigned *End;
const unsigned *Pos;
- const BitVector &Reserved;
+ const RegisterClassInfo &RCI;
unsigned Hint;
+ bool OwnedBegin;
public:
/// AllocationOrder - Create a new AllocationOrder for VirtReg.
@@ -37,12 +38,28 @@ public:
/// TargetRegisterInfo::getReservedRegs().
AllocationOrder(unsigned VirtReg,
const VirtRegMap &VRM,
- const BitVector &ReservedRegs);
+ const RegisterClassInfo &RegClassInfo);
+
+ ~AllocationOrder();
/// next - Return the next physical register in the allocation order, or 0.
/// It is safe to call next again after it returned 0.
/// It will keep returning 0 until rewind() is called.
- unsigned next();
+ unsigned next() {
+ // First take the hint.
+ if (!Pos) {
+ Pos = Begin;
+ if (Hint)
+ return Hint;
+ }
+ // Then look at the order from TRI.
+ while (Pos != End) {
+ unsigned Reg = *Pos++;
+ if (Reg != Hint)
+ return Reg;
+ }
+ return 0;
+ }
/// rewind - Start over from the beginning.
void rewind() { Pos = 0; }
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