Add/improve mips64r2, Octeon, n32 and n64 support in the toolchain.

o) Add TARGET_ABI to the MIPS toolchain build process.  This sets the default
   ABI to one of o32, n32 or n64.  If it is not set, o32 is assumed as that is
   the current default.
o) Set the default GCC cpu type to any specified TARGET_CPUTYPE.  This is
   necessary to have a working "cc" if e.g. mips64 is specified, as binutils
   will refuse to link objects using different ISAs in some cases.
o) Add support for n32 and n64 ABIs to binutils and GCC.
o) Add additional required libgcc2 stubs for n32 and n64.
o) Add support for the "mips64r2" architecture to GCC.  Add the "octeon"
o) When static linking, wrap default libraries in --start-group and
   --end-group.  This is required for static linking to work on n64 with the
   interdependencies between libraries there.  This is what other OSes that
   support n64 seem to do, as well.
o) Fix our GCC spec to define __mips64 for 64-bit targets, not __mips64__, the
   former being what libgcc, etc., check and the latter seemingly being a
   misspelling of a hand merge from a Linux spec.
o) When no TARGET_CPUTYPE is specified at build time, make GCC take the default
   ISA from the ABI.  Our old defaults were too liberal and assumed that 64-bit
   ABIs should default to the MIPS64 ISA and that 32-bit ABIs should default to
   the MIPS32 ISA, when we are supporting or will support some systems based on
   earlier 32-bit and 64-bit ISAs, most notably MIPS-III.
o) Merge a new opcode file (and support code) from a later version of binutils
   and add flags and code necessary to support Octeon-specific instructions.
   This should also make merging opcodes for other modern architectures easier.

Reviewed by:	imp

12 files changed, 271 insertions, 23 deletions

diff --git a/contrib/gcc/config/fixdfdi.c b/contrib/gcc/config/fixdfdi.c
new file mode 100644
index 0000000..9b49228
--- /dev/null
+++ b/contrib/gcc/config/fixdfdi.c
@@ -0,0 +1,28 @@
+/* Public domain.  */
+typedef unsigned int USItype __attribute__ ((mode (SI)));
+typedef int DItype __attribute__ ((mode (DI)));
+typedef unsigned int UDItype __attribute__ ((mode (DI)));
+typedef float DFtype __attribute__ ((mode (DF)));
+
+DItype __fixdfdi (DFtype);
+
+/* This version is needed to prevent recursion; fixunsdfdi in libgcc
+   calls fixdfdi, which in turn calls calls fixunsdfdi.  */
+
+static DItype
+local_fixunsdfdi (DFtype a)
+{
+  USItype hi, lo;
+
+  hi = a / (((UDItype) 1) << (sizeof (USItype) * 8));
+  lo = a - ((DFtype) hi) * (((UDItype) 1) << (sizeof (USItype) * 8));
+  return ((UDItype) hi << (sizeof (USItype) * 8)) | lo;
+}
+
+DItype
+__fixdfdi (DFtype a)
+{
+  if (a < 0)
+    return - local_fixunsdfdi (-a);
+  return local_fixunsdfdi (a);
+}
diff --git a/contrib/gcc/config/fixsfdi.c b/contrib/gcc/config/fixsfdi.c
new file mode 100644
index 0000000..58b3cfc
--- /dev/null
+++ b/contrib/gcc/config/fixsfdi.c
@@ -0,0 +1,30 @@
+/* Public domain.  */
+typedef unsigned int USItype __attribute__ ((mode (SI)));
+typedef int DItype __attribute__ ((mode (DI)));
+typedef unsigned int UDItype __attribute__ ((mode (DI)));
+typedef float SFtype __attribute__ ((mode (SF)));
+typedef float DFtype __attribute__ ((mode (DF)));
+
+DItype __fixsfdi (SFtype);
+
+/* This version is needed to prevent recursion; fixunssfdi in libgcc
+   calls fixsfdi, which in turn calls calls fixunssfdi.  */
+
+static DItype
+local_fixunssfdi (SFtype original_a)
+{
+  DFtype a = original_a;
+  USItype hi, lo;
+
+  hi = a / (((UDItype) 1) << (sizeof (USItype) * 8));
+  lo = a - ((DFtype) hi) * (((UDItype) 1) << (sizeof (USItype) * 8));
+  return ((UDItype) hi << (sizeof (USItype) * 8)) | lo;
+}
+
+DItype
+__fixsfdi (SFtype a)
+{
+  if (a < 0)
+    return - local_fixunssfdi (-a);
+  return local_fixunssfdi (a);
+}
diff --git a/contrib/gcc/config/fixunsdfsi.c b/contrib/gcc/config/fixunsdfsi.c
new file mode 100644
index 0000000..fe7a4f8
--- /dev/null
+++ b/contrib/gcc/config/fixunsdfsi.c
@@ -0,0 +1,18 @@
+/* Public domain.  */
+typedef unsigned int USItype __attribute__ ((mode (SI)));
+typedef int SItype __attribute__ ((mode (SI)));
+typedef float SFtype __attribute__ ((mode (SF)));
+typedef float DFtype __attribute__ ((mode (DF)));
+
+USItype __fixunsdfsi (DFtype);
+
+#define SItype_MIN \
+  (- ((SItype) (((USItype) 1 << ((sizeof (SItype) * 8) - 1)) - 1)) - 1)
+
+USItype
+__fixunsdfsi (DFtype a)
+{
+  if (a >= - (DFtype) SItype_MIN)
+    return (SItype) (a + SItype_MIN) - SItype_MIN;
+  return (SItype) a;
+}
diff --git a/contrib/gcc/config/fixunssfsi.c b/contrib/gcc/config/fixunssfsi.c
new file mode 100644
index 0000000..f318749
--- /dev/null
+++ b/contrib/gcc/config/fixunssfsi.c
@@ -0,0 +1,17 @@
+/* Public domain.  */
+typedef unsigned int USItype __attribute__ ((mode (SI)));
+typedef int SItype __attribute__ ((mode (SI)));
+typedef float SFtype __attribute__ ((mode (SF)));
+
+USItype __fixunssfsi (SFtype);
+
+#define SItype_MIN \
+  (- ((SItype) (((USItype) 1 << ((sizeof (SItype) * 8) - 1)) - 1)) - 1)
+
+USItype
+__fixunssfsi (SFtype a)
+{
+  if (a >= - (SFtype) SItype_MIN)
+    return (SItype) (a + SItype_MIN) - SItype_MIN;
+  return (SItype) a;
+}
diff --git a/contrib/gcc/config/floatdidf.c b/contrib/gcc/config/floatdidf.c
new file mode 100644
index 0000000..45bd0fd
--- /dev/null
+++ b/contrib/gcc/config/floatdidf.c
@@ -0,0 +1,17 @@
+/* Public domain.  */
+typedef int SItype __attribute__ ((mode (SI)));
+typedef unsigned int USItype __attribute__ ((mode (SI)));
+typedef int DItype __attribute__ ((mode (DI)));
+typedef float DFtype __attribute__ ((mode (DF)));
+
+DFtype __floatdidf (DItype);
+
+DFtype
+__floatdidf (DItype u)
+{
+  /* When the word size is small, we never get any rounding error.  */
+  DFtype f = (SItype) (u >> (sizeof (SItype) * 8));
+  f *= 0x1p32f;
+  f += (USItype) u;
+  return f;
+}
diff --git a/contrib/gcc/config/floatdisf.c b/contrib/gcc/config/floatdisf.c
new file mode 100644
index 0000000..b306044
--- /dev/null
+++ b/contrib/gcc/config/floatdisf.c
@@ -0,0 +1,38 @@
+/* Public domain.  */
+typedef int DItype __attribute__ ((mode (DI)));
+typedef unsigned int UDItype __attribute__ ((mode (DI)));
+typedef int SItype __attribute__ ((mode (SI)));
+typedef unsigned int USItype __attribute__ ((mode (SI)));
+typedef float SFtype __attribute__ ((mode (SF)));
+typedef float DFtype __attribute__ ((mode (DF)));
+
+SFtype __floatdisf (DItype);
+
+SFtype
+__floatdisf (DItype u)
+{
+  /* Protect against double-rounding error.
+     Represent any low-order bits, that might be truncated by a bit that
+     won't be lost.  The bit can go in anywhere below the rounding position
+     of SFtype.  A fixed mask and bit position handles all usual
+     configurations.  */
+  if (53 < (sizeof (DItype) * 8)
+      && 53 > ((sizeof (DItype) * 8) - 53 + 24))
+    {
+      if (!(- ((DItype) 1 << 53) < u
+	    && u < ((DItype) 1 << 53)))
+	{
+	  if ((UDItype) u & (((UDItype) 1 << (sizeof (DItype) * 8 - 53)) - 1))
+	    {
+	      u &= ~ (((UDItype) 1 << (sizeof (DItype) * 8 - 53)) - 1);
+	      u |= (UDItype) 1 << (sizeof (DItype) * 8 - 53);
+	    }
+	}
+    }
+  /* Do the calculation in a wider type so that we don't lose any of
+     the precision of the high word while multiplying it.  */
+  DFtype f = (SItype) (u >> (sizeof (SItype) * 8));
+  f *= 0x1p32f;
+  f += (USItype) u;
+  return (SFtype) f;
+}
diff --git a/contrib/gcc/config/floatundidf.c b/contrib/gcc/config/floatundidf.c
new file mode 100644
index 0000000..0b11b0f
--- /dev/null
+++ b/contrib/gcc/config/floatundidf.c
@@ -0,0 +1,16 @@
+/* Public domain.  */
+typedef unsigned int USItype __attribute__ ((mode (SI)));
+typedef unsigned int UDItype __attribute__ ((mode (DI)));
+typedef float DFtype __attribute__ ((mode (DF)));
+
+DFtype __floatundidf (UDItype);
+
+DFtype
+__floatundidf (UDItype u)
+{
+  /* When the word size is small, we never get any rounding error.  */
+  DFtype f = (USItype) (u >> (sizeof (USItype) * 8));
+  f *= 0x1p32f;
+  f += (USItype) u;
+  return f;
+}
diff --git a/contrib/gcc/config/floatundisf.c b/contrib/gcc/config/floatundisf.c
new file mode 100644
index 0000000..c813f0d
--- /dev/null
+++ b/contrib/gcc/config/floatundisf.c
@@ -0,0 +1,36 @@
+/* Public domain.  */
+typedef int DItype __attribute__ ((mode (DI)));
+typedef unsigned int UDItype __attribute__ ((mode (DI)));
+typedef unsigned int USItype __attribute__ ((mode (SI)));
+typedef float SFtype __attribute__ ((mode (SF)));
+typedef float DFtype __attribute__ ((mode (DF)));
+
+SFtype __floatundisf (UDItype);
+
+SFtype
+__floatundisf (UDItype u)
+{
+  /* Protect against double-rounding error.
+     Represent any low-order bits, that might be truncated by a bit that
+     won't be lost.  The bit can go in anywhere below the rounding position
+     of SFTYPE.  A fixed mask and bit position handles all usual
+     configurations.  */
+  if (53 < (sizeof (DItype) * 8)
+      && 53 > ((sizeof (DItype) * 8) - 53 + 24))
+    {
+      if (u >= ((UDItype) 1 << 53))
+	{
+	  if ((UDItype) u & (((UDItype) 1 << (sizeof (DItype) * 8 - 53)) - 1))
+	    {
+	      u &= ~ (((UDItype) 1 << (sizeof (DItype) * 8 - 53)) - 1);
+	      u |= (UDItype) 1 << (sizeof (DItype) * 8 - 53);
+	    }
+	}
+    }
+  /* Do the calculation in a wider type so that we don't lose any of
+     the precision of the high word while multiplying it.  */
+  DFtype f = (USItype) (u >> (sizeof (USItype) * 8));
+  f *= 0x1p32f;
+  f += (USItype) u;
+  return (SFtype) f;
+}
diff --git a/contrib/gcc/config/mips/freebsd.h b/contrib/gcc/config/mips/freebsd.h
index 35159ab..d2ecd65 100644
--- a/contrib/gcc/config/mips/freebsd.h
+++ b/contrib/gcc/config/mips/freebsd.h
@@ -75,7 +75,10 @@ Boston, MA 02110-1301, USA.  */
     %{mabi=o64:-melf64%{EB:b}%{EL:l}tsmip_fbsd} \
     %(fbsd_link_spec)"
 
-    
+#undef	LINK_GCC_C_SEQUENCE_SPEC
+#define LINK_GCC_C_SEQUENCE_SPEC \
+  "%{static:--start-group} %G %L %{static:--end-group}%{!static:%G}"
+
 /* Reset our STARTFILE_SPEC which was properly set in config/freebsd.h
    but trashed by config/mips/elf.h.  */
 #undef  STARTFILE_SPEC
@@ -124,7 +127,7 @@ Boston, MA 02110-1301, USA.  */
       builtin_define ("__mips__");				\
 								\
       if (TARGET_64BIT)						\
-	builtin_define ("__mips64__");				\
+	builtin_define ("__mips64");				\
 								\
       if (TARGET_FLOAT64)					\
 	builtin_define ("__mips_fpr=64");			\
@@ -228,13 +231,13 @@ Boston, MA 02110-1301, USA.  */
           builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64");        \
 	  builtin_define ("__mips_isa_rev=1");			\
 	}							\
-/*      else if (ISA_MIPS64R2)					\
+      else if (ISA_MIPS64R2)					\
 	{							\
 	  builtin_define ("__mips=64");				\
           builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64");        \
 	  builtin_define ("__mips_isa_rev=2");			\
 	}							\
-*/								\
+	    							\
       if (TARGET_HARD_FLOAT)					\
 	builtin_define ("__mips_hard_float");			\
       else if (TARGET_SOFT_FLOAT)				\
@@ -255,27 +258,37 @@ Boston, MA 02110-1301, USA.  */
   while (0)
 
 /* Default ABI and ISA */
+/*
+ * XXX/juli
+ * Shouldn't this also be dependent on !mips*?
+ */
+#ifdef MIPS_CPU_STRING_DEFAULT
+#define DRIVER_SELF_ISA_SPEC	"%{!march=*: -march=" MIPS_CPU_STRING_DEFAULT "}"
+#else
+#define	DRIVER_SELF_ISA_SPEC	"%{!march=*: -march=from-abi}"
+#endif
+
 #undef DRIVER_SELF_SPECS
 #if MIPS_ABI_DEFAULT == ABI_N32
 #define DRIVER_SELF_SPECS \
 	"%{!EB:%{!EL:%(endian_spec)}}", \
-	"%{!march=*: -march=mips64}",   \
-	"%{!mabi=*: -mabi=n32}"
+	"%{!mabi=*: -mabi=n32}", \
+	DRIVER_SELF_ISA_SPEC
 #elif MIPS_ABI_DEFAULT == ABI_64
 #define DRIVER_SELF_SPECS \
 	"%{!EB:%{!EL:%(endian_spec)}}", \
-	"%{!march=*: -march=mips64}",   \
-	"%{!mabi=*: -mabi=64}"
+	"%{!mabi=*: -mabi=64}", \
+	DRIVER_SELF_ISA_SPEC
 #elif MIPS_ABI_DEFAULT == ABI_O64
 #define DRIVER_SELF_SPECS \
 	"%{!EB:%{!EL:%(endian_spec)}}", \
-	"%{!march=*: -march=mips64}",   \
-	"%{!mabi=*: -mabi=o64}"
+	"%{!mabi=*: -mabi=o64}", \
+	DRIVER_SELF_ISA_SPEC
 #else /* default to o32 */
 #define DRIVER_SELF_SPECS \
 	"%{!EB:%{!EL:%(endian_spec)}}", \
-	"%{!march=*: -march=mips32}",   \
-	"%{!mabi=*: -mabi=32}"
+	"%{!mabi=*: -mabi=32}", \
+	DRIVER_SELF_ISA_SPEC
 #endif
 
 #if 0
diff --git a/contrib/gcc/config/mips/mips.c b/contrib/gcc/config/mips/mips.c
index 05498c2..e9f7c97 100644
--- a/contrib/gcc/config/mips/mips.c
+++ b/contrib/gcc/config/mips/mips.c
@@ -713,6 +713,7 @@ const struct mips_cpu_info mips_cpu_info_table[] = {
   { "mips32", PROCESSOR_4KC, 32 },
   { "mips32r2", PROCESSOR_M4K, 33 },
   { "mips64", PROCESSOR_5KC, 64 },
+  { "mips64r2", PROCESSOR_5KC, 65 },
 
   /* MIPS I */
   { "r3000", PROCESSOR_R3000, 1 },
@@ -762,6 +763,9 @@ const struct mips_cpu_info mips_cpu_info_table[] = {
   { "sb1a", PROCESSOR_SB1A, 64 },
   { "sr71000", PROCESSOR_SR71000, 64 },
 
+  /* MIPS64R2 */
+  { "octeon", PROCESSOR_OCTEON, 65 },
+
   /* End marker */
   { 0, 0, 0 }
 };
@@ -4829,7 +4833,7 @@ override_options (void)
 	 issue those instructions unless instructed to do so by
 	 -mbranch-likely.  */
       if (ISA_HAS_BRANCHLIKELY
-	  && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64)
+	  && !(ISA_MIPS32 || ISA_MIPS32R2 || ISA_MIPS64 || ISA_MIPS64R2)
 	  && !(TUNE_MIPS5500 || TUNE_SB1))
 	target_flags |= MASK_BRANCHLIKELY;
       else
@@ -9943,6 +9947,7 @@ mips_issue_rate (void)
     case PROCESSOR_R5500:
     case PROCESSOR_R7000:
     case PROCESSOR_R9000:
+    case PROCESSOR_OCTEON:
       return 2;
 
     case PROCESSOR_SB1:
diff --git a/contrib/gcc/config/mips/mips.h b/contrib/gcc/config/mips/mips.h
index ba77d86..1ba1402 100644
--- a/contrib/gcc/config/mips/mips.h
+++ b/contrib/gcc/config/mips/mips.h
@@ -41,6 +41,7 @@ enum processor_type {
   PROCESSOR_24K,
   PROCESSOR_24KX,
   PROCESSOR_M4K,
+  PROCESSOR_OCTEON,
   PROCESSOR_R3900,
   PROCESSOR_R6000,
   PROCESSOR_R4000,
@@ -199,6 +200,7 @@ extern const struct mips_rtx_cost_data *mips_cost;
 #define ISA_MIPS32		    (mips_isa == 32)
 #define ISA_MIPS32R2		    (mips_isa == 33)
 #define ISA_MIPS64                  (mips_isa == 64)
+#define	ISA_MIPS64R2		    (mips_isa == 65)
 
 /* Architecture target defines.  */
 #define TARGET_MIPS3900             (mips_arch == PROCESSOR_R3900)
@@ -212,6 +214,7 @@ extern const struct mips_rtx_cost_data *mips_cost;
 #define TARGET_SB1                  (mips_arch == PROCESSOR_SB1		\
 				     || mips_arch == PROCESSOR_SB1A)
 #define TARGET_SR71K                (mips_arch == PROCESSOR_SR71000)
+#define TARGET_OCTEON               (mips_arch == PROCESSOR_OCTEON)
 
 /* Scheduling target defines.  */
 #define TUNE_MIPS3000               (mips_tune == PROCESSOR_R3000)
@@ -227,6 +230,7 @@ extern const struct mips_rtx_cost_data *mips_cost;
 #define TUNE_MIPS9000               (mips_tune == PROCESSOR_R9000)
 #define TUNE_SB1                    (mips_tune == PROCESSOR_SB1		\
 				     || mips_tune == PROCESSOR_SB1A)
+#define TUNE_OCTEON                 (mips_tune == PROCESSOR_OCTEON)
 
 /* True if the pre-reload scheduler should try to create chains of
    multiply-add or multiply-subtract instructions.  For example,
@@ -380,6 +384,12 @@ extern const struct mips_rtx_cost_data *mips_cost;
 	  builtin_define ("__mips_isa_rev=1");			\
 	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64");	\
 	}							\
+      else if (ISA_MIPS64R2)					\
+	{							\
+	  builtin_define ("__mips=64");				\
+	  builtin_define ("__mips_isa_rev=2");			\
+	  builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64");	\
+	}							\
 								\
       if (TARGET_HARD_FLOAT)					\
 	builtin_define ("__mips_hard_float");			\
@@ -501,7 +511,11 @@ extern const struct mips_rtx_cost_data *mips_cost;
 #              if MIPS_ISA_DEFAULT == 64
 #                define MULTILIB_ISA_DEFAULT "mips64"
 #              else
-#                define MULTILIB_ISA_DEFAULT "mips1"
+#                if MIPS_ISA_DEFAULT == 65
+#                  define MULTILIB_ISA_DEFAULT "mips64r2"
+#                else
+#                  define MULTILIB_ISA_DEFAULT "mips1"
+#                endif
 #              endif
 #            endif
 #          endif
@@ -562,7 +576,8 @@ extern const struct mips_rtx_cost_data *mips_cost;
 				  || TARGET_MAD				\
                                   || ISA_MIPS32	                        \
                                   || ISA_MIPS32R2                       \
-                                  || ISA_MIPS64)                        \
+                                  || ISA_MIPS64                         \
+                                  || ISA_MIPS64R2)                      \
                                  && !TARGET_MIPS16)
 
 /* Generate three-operand multiply instructions for DImode.  */
@@ -584,7 +599,8 @@ extern const struct mips_rtx_cost_data *mips_cost;
 /* ISA has instructions for managing 64 bit fp and gp regs (e.g. mips3).  */
 #define ISA_HAS_64BIT_REGS	(ISA_MIPS3				\
 				 || ISA_MIPS4				\
-                                 || ISA_MIPS64)
+                                 || ISA_MIPS64				\
+				 || ISA_MIPS64R2)
 
 /* ISA has branch likely instructions (e.g. mips2).  */
 /* Disable branchlikely for tx39 until compare rewrite.  They haven't
@@ -595,7 +611,8 @@ extern const struct mips_rtx_cost_data *mips_cost;
 #define ISA_HAS_CONDMOVE        ((ISA_MIPS4				\
 				  || ISA_MIPS32	                        \
 				  || ISA_MIPS32R2                       \
-				  || ISA_MIPS64)			\
+				  || ISA_MIPS64				\
+				  || ISA_MIPS64R2)			\
                                  && !TARGET_MIPS5500                    \
 				 && !TARGET_MIPS16)
 
@@ -604,13 +621,15 @@ extern const struct mips_rtx_cost_data *mips_cost;
 #define ISA_HAS_8CC		(ISA_MIPS4				\
                          	 || ISA_MIPS32	                        \
                          	 || ISA_MIPS32R2                        \
-				 || ISA_MIPS64)
+				 || ISA_MIPS64				\
+				 || ISA_MIPS64R2)
 
 /* This is a catch all for other mips4 instructions: indexed load, the
    FP madd and msub instructions, and the FP recip and recip sqrt
    instructions.  */
 #define ISA_HAS_FP4             ((ISA_MIPS4				\
-				  || ISA_MIPS64)       			\
+				  || ISA_MIPS64				\
+				  || ISA_MIPS64R2)     			\
  				 && !TARGET_MIPS16)
 
 /* ISA has conditional trap instructions.  */
@@ -621,11 +640,13 @@ extern const struct mips_rtx_cost_data *mips_cost;
 #define ISA_HAS_MADD_MSUB       ((ISA_MIPS32				\
 				  || ISA_MIPS32R2			\
 				  || ISA_MIPS64				\
+				  || ISA_MIPS64R2			\
 				  ) && !TARGET_MIPS16)
 
 /* ISA has floating-point nmadd and nmsub instructions.  */
 #define ISA_HAS_NMADD_NMSUB	((ISA_MIPS4				\
-				  || ISA_MIPS64)       			\
+				  || ISA_MIPS64				\
+				  || ISA_MIPS64R2)			\
                                  && (!TARGET_MIPS5400 || TARGET_MAD)    \
 				 && ! TARGET_MIPS16)
 
@@ -633,11 +654,13 @@ extern const struct mips_rtx_cost_data *mips_cost;
 #define ISA_HAS_CLZ_CLO         ((ISA_MIPS32				\
                                   || ISA_MIPS32R2			\
                                   || ISA_MIPS64				\
+                                  || ISA_MIPS64R2			\
                                  ) && !TARGET_MIPS16)
 
 /* ISA has double-word count leading zeroes/ones instruction (not
    implemented).  */
 #define ISA_HAS_DCLZ_DCLO       (ISA_MIPS64				\
+				 || ISA_MIPS64R2			\
 				 && !TARGET_MIPS16)
 
 /* ISA has three operand multiply instructions that put
@@ -677,6 +700,7 @@ extern const struct mips_rtx_cost_data *mips_cost;
 /* ISA has 32-bit rotate right instruction.  */
 #define ISA_HAS_ROTR_SI         (!TARGET_MIPS16                         \
                                  && (ISA_MIPS32R2                       \
+                                     || ISA_MIPS64R2                    \
                                      || TARGET_MIPS5400                 \
                                      || TARGET_MIPS5500                 \
                                      || TARGET_SR71K                    \
@@ -694,7 +718,8 @@ extern const struct mips_rtx_cost_data *mips_cost;
 #define ISA_HAS_PREFETCH	((ISA_MIPS4				\
 				  || ISA_MIPS32				\
 				  || ISA_MIPS32R2			\
-				  || ISA_MIPS64)	       		\
+				  || ISA_MIPS64		       		\
+				  || ISA_MIPS64R2)	       		\
 				 && !TARGET_MIPS16)
 
 /* ISA has data indexed prefetch instructions.  This controls use of
@@ -702,7 +727,8 @@ extern const struct mips_rtx_cost_data *mips_cost;
    (prefx is a cop1x instruction, so can only be used if FP is
    enabled.)  */
 #define ISA_HAS_PREFETCHX       ((ISA_MIPS4				\
-				  || ISA_MIPS64)       			\
+				  || ISA_MIPS64				\
+				  || ISA_MIPS64R2)			\
  				 && !TARGET_MIPS16)
 
 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
@@ -713,11 +739,13 @@ extern const struct mips_rtx_cost_data *mips_cost;
 /* ISA includes the MIPS32r2 seb and seh instructions.  */
 #define ISA_HAS_SEB_SEH         (!TARGET_MIPS16                        \
                                  && (ISA_MIPS32R2                      \
+				     || ISA_MIPS64R2			\
                                      ))
 
 /* ISA includes the MIPS32/64 rev 2 ext and ins instructions.  */
 #define ISA_HAS_EXT_INS         (!TARGET_MIPS16                        \
                                  && (ISA_MIPS32R2                      \
+				     || ISA_MIPS64R2		       \
                                      ))
 
 /* True if the result of a load is not available to the next instruction.
@@ -748,6 +776,7 @@ extern const struct mips_rtx_cost_data *mips_cost;
 #define ISA_HAS_HILO_INTERLOCKS	(ISA_MIPS32				\
 				 || ISA_MIPS32R2			\
 				 || ISA_MIPS64				\
+				 || ISA_MIPS64R2			\
 				 || TARGET_MIPS5500)
 
 /* Add -G xx support.  */
diff --git a/contrib/gcc/config/mips/mips.md b/contrib/gcc/config/mips/mips.md
index 969d22f..b3716a0 100644
--- a/contrib/gcc/config/mips/mips.md
+++ b/contrib/gcc/config/mips/mips.md
@@ -1041,7 +1041,8 @@
       || TARGET_MIPS9000
       || ISA_MIPS32
       || ISA_MIPS32R2
-      || ISA_MIPS64)
+      || ISA_MIPS64
+      || ISA_MIPS64R2)
     return "mul\t%0,%1,%2";
   return "mult\t%0,%1,%2";
 }