diff options
| author | kan <kan@FreeBSD.org> | 2007-05-19 02:26:26 +0000 |
|---|---|---|
| committer | kan <kan@FreeBSD.org> | 2007-05-19 02:26:26 +0000 |
| commit | 5d74891d60e041222feaa0134e422675ce862aa4 (patch) | |
| tree | fdff62d4f2c29a3b20099b8faa355eb3a37483ac /contrib/gcc | |
| parent | 671dcce5dd5486893031d298bacd5eab489cbf4c (diff) | |
| download | FreeBSD-src-5d74891d60e041222feaa0134e422675ce862aa4.zip FreeBSD-src-5d74891d60e041222feaa0134e422675ce862aa4.tar.gz | |
Merge local FreeBSD changes for -mno-align-long-strings.
Diffstat (limited to 'contrib/gcc')
| -rw-r--r-- | contrib/gcc/config/i386/i386.c | 10987 |
1 files changed, 7025 insertions, 3962 deletions
diff --git a/contrib/gcc/config/i386/i386.c b/contrib/gcc/config/i386/i386.c index 0360ff1..b965e8d 100644 --- a/contrib/gcc/config/i386/i386.c +++ b/contrib/gcc/config/i386/i386.c @@ -1,6 +1,6 @@ /* Subroutines used for code generation on IA-32. Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, - 2002, 2003, 2004 Free Software Foundation, Inc. + 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. This file is part of GCC. @@ -16,13 +16,11 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with GCC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - +the Free Software Foundation, 51 Franklin Street, Fifth Floor, +Boston, MA 02110-1301, USA. */ /* $FreeBSD$ */ - #include "config.h" #include "system.h" #include "coretypes.h" @@ -36,6 +34,7 @@ Boston, MA 02111-1307, USA. */ #include "insn-config.h" #include "conditions.h" #include "output.h" +#include "insn-codes.h" #include "insn-attr.h" #include "flags.h" #include "except.h" @@ -50,6 +49,9 @@ Boston, MA 02111-1307, USA. */ #include "target-def.h" #include "langhooks.h" #include "cgraph.h" +#include "tree-gimple.h" +#include "dwarf2.h" +#include "tm-constrs.h" #ifndef CHECK_STACK_LIMIT #define CHECK_STACK_LIMIT (-1) @@ -64,17 +66,28 @@ Boston, MA 02111-1307, USA. */ : 4) /* Processor costs (relative to an add) */ +/* We assume COSTS_N_INSNS is defined as (N)*4 and an addition is 2 bytes. */ +#define COSTS_N_BYTES(N) ((N) * 2) + static const -struct processor_costs size_cost = { /* costs for tunning for size */ - 2, /* cost of an add instruction */ - 3, /* cost of a lea instruction */ - 2, /* variable shift costs */ - 3, /* constant shift costs */ - {3, 3, 3, 3, 5}, /* cost of starting a multiply */ +struct processor_costs size_cost = { /* costs for tuning for size */ + COSTS_N_BYTES (2), /* cost of an add instruction */ + COSTS_N_BYTES (3), /* cost of a lea instruction */ + COSTS_N_BYTES (2), /* variable shift costs */ + COSTS_N_BYTES (3), /* constant shift costs */ + {COSTS_N_BYTES (3), /* cost of starting multiply for QI */ + COSTS_N_BYTES (3), /* HI */ + COSTS_N_BYTES (3), /* SI */ + COSTS_N_BYTES (3), /* DI */ + COSTS_N_BYTES (5)}, /* other */ 0, /* cost of multiply per each bit set */ - {3, 3, 3, 3, 5}, /* cost of a divide/mod */ - 3, /* cost of movsx */ - 3, /* cost of movzx */ + {COSTS_N_BYTES (3), /* cost of a divide/mod for QI */ + COSTS_N_BYTES (3), /* HI */ + COSTS_N_BYTES (3), /* SI */ + COSTS_N_BYTES (3), /* DI */ + COSTS_N_BYTES (5)}, /* other */ + COSTS_N_BYTES (3), /* cost of movsx */ + COSTS_N_BYTES (3), /* cost of movzx */ 0, /* "large" insn */ 2, /* MOVE_RATIO */ 2, /* cost for loading QImode using movzbl */ @@ -85,7 +98,8 @@ struct processor_costs size_cost = { /* costs for tunning for size */ 2, /* cost of reg,reg fld/fst */ {2, 2, 2}, /* cost of loading fp registers in SFmode, DFmode and XFmode */ - {2, 2, 2}, /* cost of loading integer registers */ + {2, 2, 2}, /* cost of storing fp registers + in SFmode, DFmode and XFmode */ 3, /* cost of moving MMX register */ {3, 3}, /* cost of loading MMX registers in SImode and DImode */ @@ -99,27 +113,35 @@ struct processor_costs size_cost = { /* costs for tunning for size */ 3, /* MMX or SSE register to integer */ 0, /* size of prefetch block */ 0, /* number of parallel prefetches */ - 1, /* Branch cost */ - 2, /* cost of FADD and FSUB insns. */ - 2, /* cost of FMUL instruction. */ - 2, /* cost of FDIV instruction. */ - 2, /* cost of FABS instruction. */ - 2, /* cost of FCHS instruction. */ - 2, /* cost of FSQRT instruction. */ + 2, /* Branch cost */ + COSTS_N_BYTES (2), /* cost of FADD and FSUB insns. */ + COSTS_N_BYTES (2), /* cost of FMUL instruction. */ + COSTS_N_BYTES (2), /* cost of FDIV instruction. */ + COSTS_N_BYTES (2), /* cost of FABS instruction. */ + COSTS_N_BYTES (2), /* cost of FCHS instruction. */ + COSTS_N_BYTES (2), /* cost of FSQRT instruction. */ }; /* Processor costs (relative to an add) */ static const struct processor_costs i386_cost = { /* 386 specific costs */ - 1, /* cost of an add instruction */ - 1, /* cost of a lea instruction */ - 3, /* variable shift costs */ - 2, /* constant shift costs */ - {6, 6, 6, 6, 6}, /* cost of starting a multiply */ - 1, /* cost of multiply per each bit set */ - {23, 23, 23, 23, 23}, /* cost of a divide/mod */ - 3, /* cost of movsx */ - 2, /* cost of movzx */ + COSTS_N_INSNS (1), /* cost of an add instruction */ + COSTS_N_INSNS (1), /* cost of a lea instruction */ + COSTS_N_INSNS (3), /* variable shift costs */ + COSTS_N_INSNS (2), /* constant shift costs */ + {COSTS_N_INSNS (6), /* cost of starting multiply for QI */ + COSTS_N_INSNS (6), /* HI */ + COSTS_N_INSNS (6), /* SI */ + COSTS_N_INSNS (6), /* DI */ + COSTS_N_INSNS (6)}, /* other */ + COSTS_N_INSNS (1), /* cost of multiply per each bit set */ + {COSTS_N_INSNS (23), /* cost of a divide/mod for QI */ + COSTS_N_INSNS (23), /* HI */ + COSTS_N_INSNS (23), /* SI */ + COSTS_N_INSNS (23), /* DI */ + COSTS_N_INSNS (23)}, /* other */ + COSTS_N_INSNS (3), /* cost of movsx */ + COSTS_N_INSNS (2), /* cost of movzx */ 15, /* "large" insn */ 3, /* MOVE_RATIO */ 4, /* cost for loading QImode using movzbl */ @@ -130,7 +152,8 @@ struct processor_costs i386_cost = { /* 386 specific costs */ 2, /* cost of reg,reg fld/fst */ {8, 8, 8}, /* cost of loading fp registers in SFmode, DFmode and XFmode */ - {8, 8, 8}, /* cost of loading integer registers */ + {8, 8, 8}, /* cost of storing fp registers + in SFmode, DFmode and XFmode */ 2, /* cost of moving MMX register */ {4, 8}, /* cost of loading MMX registers in SImode and DImode */ @@ -145,25 +168,33 @@ struct processor_costs i386_cost = { /* 386 specific costs */ 0, /* size of prefetch block */ 0, /* number of parallel prefetches */ 1, /* Branch cost */ - 23, /* cost of FADD and FSUB insns. */ - 27, /* cost of FMUL instruction. */ - 88, /* cost of FDIV instruction. */ - 22, /* cost of FABS instruction. */ - 24, /* cost of FCHS instruction. */ - 122, /* cost of FSQRT instruction. */ + COSTS_N_INSNS (23), /* cost of FADD and FSUB insns. */ + COSTS_N_INSNS (27), /* cost of FMUL instruction. */ + COSTS_N_INSNS (88), /* cost of FDIV instruction. */ + COSTS_N_INSNS (22), /* cost of FABS instruction. */ + COSTS_N_INSNS (24), /* cost of FCHS instruction. */ + COSTS_N_INSNS (122), /* cost of FSQRT instruction. */ }; static const struct processor_costs i486_cost = { /* 486 specific costs */ - 1, /* cost of an add instruction */ - 1, /* cost of a lea instruction */ - 3, /* variable shift costs */ - 2, /* constant shift costs */ - {12, 12, 12, 12, 12}, /* cost of starting a multiply */ + COSTS_N_INSNS (1), /* cost of an add instruction */ + COSTS_N_INSNS (1), /* cost of a lea instruction */ + COSTS_N_INSNS (3), /* variable shift costs */ + COSTS_N_INSNS (2), /* constant shift costs */ + {COSTS_N_INSNS (12), /* cost of starting multiply for QI */ + COSTS_N_INSNS (12), /* HI */ + COSTS_N_INSNS (12), /* SI */ + COSTS_N_INSNS (12), /* DI */ + COSTS_N_INSNS (12)}, /* other */ 1, /* cost of multiply per each bit set */ - {40, 40, 40, 40, 40}, /* cost of a divide/mod */ - 3, /* cost of movsx */ - 2, /* cost of movzx */ + {COSTS_N_INSNS (40), /* cost of a divide/mod for QI */ + COSTS_N_INSNS (40), /* HI */ + COSTS_N_INSNS (40), /* SI */ + COSTS_N_INSNS (40), /* DI */ + COSTS_N_INSNS (40)}, /* other */ + COSTS_N_INSNS (3), /* cost of movsx */ + COSTS_N_INSNS (2), /* cost of movzx */ 15, /* "large" insn */ 3, /* MOVE_RATIO */ 4, /* cost for loading QImode using movzbl */ @@ -174,7 +205,8 @@ struct processor_costs i486_cost = { /* 486 specific costs */ 2, /* cost of reg,reg fld/fst */ {8, 8, 8}, /* cost of loading fp registers in SFmode, DFmode and XFmode */ - {8, 8, 8}, /* cost of loading integer registers */ + {8, 8, 8}, /* cost of storing fp registers + in SFmode, DFmode and XFmode */ 2, /* cost of moving MMX register */ {4, 8}, /* cost of loading MMX registers in SImode and DImode */ @@ -189,25 +221,33 @@ struct processor_costs i486_cost = { /* 486 specific costs */ 0, /* size of prefetch block */ 0, /* number of parallel prefetches */ 1, /* Branch cost */ - 8, /* cost of FADD and FSUB insns. */ - 16, /* cost of FMUL instruction. */ - 73, /* cost of FDIV instruction. */ - 3, /* cost of FABS instruction. */ - 3, /* cost of FCHS instruction. */ - 83, /* cost of FSQRT instruction. */ + COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */ + COSTS_N_INSNS (16), /* cost of FMUL instruction. */ + COSTS_N_INSNS (73), /* cost of FDIV instruction. */ + COSTS_N_INSNS (3), /* cost of FABS instruction. */ + COSTS_N_INSNS (3), /* cost of FCHS instruction. */ + COSTS_N_INSNS (83), /* cost of FSQRT instruction. */ }; static const struct processor_costs pentium_cost = { - 1, /* cost of an add instruction */ - 1, /* cost of a lea instruction */ - 4, /* variable shift costs */ - 1, /* constant shift costs */ - {11, 11, 11, 11, 11}, /* cost of starting a multiply */ + COSTS_N_INSNS (1), /* cost of an add instruction */ + COSTS_N_INSNS (1), /* cost of a lea instruction */ + COSTS_N_INSNS (4), /* variable shift costs */ + COSTS_N_INSNS (1), /* constant shift costs */ + {COSTS_N_INSNS (11), /* cost of starting multiply for QI */ + COSTS_N_INSNS (11), /* HI */ + COSTS_N_INSNS (11), /* SI */ + COSTS_N_INSNS (11), /* DI */ + COSTS_N_INSNS (11)}, /* other */ 0, /* cost of multiply per each bit set */ - {25, 25, 25, 25, 25}, /* cost of a divide/mod */ - 3, /* cost of movsx */ - 2, /* cost of movzx */ + {COSTS_N_INSNS (25), /* cost of a divide/mod for QI */ + COSTS_N_INSNS (25), /* HI */ + COSTS_N_INSNS (25), /* SI */ + COSTS_N_INSNS (25), /* DI */ + COSTS_N_INSNS (25)}, /* other */ + COSTS_N_INSNS (3), /* cost of movsx */ + COSTS_N_INSNS (2), /* cost of movzx */ 8, /* "large" insn */ 6, /* MOVE_RATIO */ 6, /* cost for loading QImode using movzbl */ @@ -218,7 +258,8 @@ struct processor_costs pentium_cost = { 2, /* cost of reg,reg fld/fst */ {2, 2, 6}, /* cost of loading fp registers in SFmode, DFmode and XFmode */ - {4, 4, 6}, /* cost of loading integer registers */ + {4, 4, 6}, /* cost of storing fp registers + in SFmode, DFmode and XFmode */ 8, /* cost of moving MMX register */ {8, 8}, /* cost of loading MMX registers in SImode and DImode */ @@ -233,25 +274,33 @@ struct processor_costs pentium_cost = { 0, /* size of prefetch block */ 0, /* number of parallel prefetches */ 2, /* Branch cost */ - 3, /* cost of FADD and FSUB insns. */ - 3, /* cost of FMUL instruction. */ - 39, /* cost of FDIV instruction. */ - 1, /* cost of FABS instruction. */ - 1, /* cost of FCHS instruction. */ - 70, /* cost of FSQRT instruction. */ + COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */ + COSTS_N_INSNS (3), /* cost of FMUL instruction. */ + COSTS_N_INSNS (39), /* cost of FDIV instruction. */ + COSTS_N_INSNS (1), /* cost of FABS instruction. */ + COSTS_N_INSNS (1), /* cost of FCHS instruction. */ + COSTS_N_INSNS (70), /* cost of FSQRT instruction. */ }; static const struct processor_costs pentiumpro_cost = { - 1, /* cost of an add instruction */ - 1, /* cost of a lea instruction */ - 1, /* variable shift costs */ - 1, /* constant shift costs */ - {4, 4, 4, 4, 4}, /* cost of starting a multiply */ + COSTS_N_INSNS (1), /* cost of an add instruction */ + COSTS_N_INSNS (1), /* cost of a lea instruction */ + COSTS_N_INSNS (1), /* variable shift costs */ + COSTS_N_INSNS (1), /* constant shift costs */ + {COSTS_N_INSNS (4), /* cost of starting multiply for QI */ + COSTS_N_INSNS (4), /* HI */ + COSTS_N_INSNS (4), /* SI */ + COSTS_N_INSNS (4), /* DI */ + COSTS_N_INSNS (4)}, /* other */ 0, /* cost of multiply per each bit set */ - {17, 17, 17, 17, 17}, /* cost of a divide/mod */ - 1, /* cost of movsx */ - 1, /* cost of movzx */ + {COSTS_N_INSNS (17), /* cost of a divide/mod for QI */ + COSTS_N_INSNS (17), /* HI */ + COSTS_N_INSNS (17), /* SI */ + COSTS_N_INSNS (17), /* DI */ + COSTS_N_INSNS (17)}, /* other */ + COSTS_N_INSNS (1), /* cost of movsx */ + COSTS_N_INSNS (1), /* cost of movzx */ 8, /* "large" insn */ 6, /* MOVE_RATIO */ 2, /* cost for loading QImode using movzbl */ @@ -262,7 +311,8 @@ struct processor_costs pentiumpro_cost = { 2, /* cost of reg,reg fld/fst */ {2, 2, 6}, /* cost of loading fp registers in SFmode, DFmode and XFmode */ - {4, 4, 6}, /* cost of loading integer registers */ + {4, 4, 6}, /* cost of storing fp registers + in SFmode, DFmode and XFmode */ 2, /* cost of moving MMX register */ {2, 2}, /* cost of loading MMX registers in SImode and DImode */ @@ -277,25 +327,33 @@ struct processor_costs pentiumpro_cost = { 32, /* size of prefetch block */ 6, /* number of parallel prefetches */ 2, /* Branch cost */ - 3, /* cost of FADD and FSUB insns. */ - 5, /* cost of FMUL instruction. */ - 56, /* cost of FDIV instruction. */ - 2, /* cost of FABS instruction. */ - 2, /* cost of FCHS instruction. */ - 56, /* cost of FSQRT instruction. */ + COSTS_N_INSNS (3), /* cost of FADD and FSUB insns. */ + COSTS_N_INSNS (5), /* cost of FMUL instruction. */ + COSTS_N_INSNS (56), /* cost of FDIV instruction. */ + COSTS_N_INSNS (2), /* cost of FABS instruction. */ + COSTS_N_INSNS (2), /* cost of FCHS instruction. */ + COSTS_N_INSNS (56), /* cost of FSQRT instruction. */ }; static const struct processor_costs k6_cost = { - 1, /* cost of an add instruction */ - 2, /* cost of a lea instruction */ - 1, /* variable shift costs */ - 1, /* constant shift costs */ - {3, 3, 3, 3, 3}, /* cost of starting a multiply */ + COSTS_N_INSNS (1), /* cost of an add instruction */ + COSTS_N_INSNS (2), /* cost of a lea instruction */ + COSTS_N_INSNS (1), /* variable shift costs */ + COSTS_N_INSNS (1), /* constant shift costs */ + {COSTS_N_INSNS (3), /* cost of starting multiply for QI */ + COSTS_N_INSNS (3), /* HI */ + COSTS_N_INSNS (3), /* SI */ + COSTS_N_INSNS (3), /* DI */ + COSTS_N_INSNS (3)}, /* other */ 0, /* cost of multiply per each bit set */ - {18, 18, 18, 18, 18}, /* cost of a divide/mod */ - 2, /* cost of movsx */ - 2, /* cost of movzx */ + {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */ + COSTS_N_INSNS (18), /* HI */ + COSTS_N_INSNS (18), /* SI */ + COSTS_N_INSNS (18), /* DI */ + COSTS_N_INSNS (18)}, /* other */ + COSTS_N_INSNS (2), /* cost of movsx */ + COSTS_N_INSNS (2), /* cost of movzx */ 8, /* "large" insn */ 4, /* MOVE_RATIO */ 3, /* cost for loading QImode using movzbl */ @@ -306,7 +364,8 @@ struct processor_costs k6_cost = { 4, /* cost of reg,reg fld/fst */ {6, 6, 6}, /* cost of loading fp registers in SFmode, DFmode and XFmode */ - {4, 4, 4}, /* cost of loading integer registers */ + {4, 4, 4}, /* cost of storing fp registers + in SFmode, DFmode and XFmode */ 2, /* cost of moving MMX register */ {2, 2}, /* cost of loading MMX registers in SImode and DImode */ @@ -321,25 +380,33 @@ struct processor_costs k6_cost = { 32, /* size of prefetch block */ 1, /* number of parallel prefetches */ 1, /* Branch cost */ - 2, /* cost of FADD and FSUB insns. */ - 2, /* cost of FMUL instruction. */ - 56, /* cost of FDIV instruction. */ - 2, /* cost of FABS instruction. */ - 2, /* cost of FCHS instruction. */ - 56, /* cost of FSQRT instruction. */ + COSTS_N_INSNS (2), /* cost of FADD and FSUB insns. */ + COSTS_N_INSNS (2), /* cost of FMUL instruction. */ + COSTS_N_INSNS (56), /* cost of FDIV instruction. */ + COSTS_N_INSNS (2), /* cost of FABS instruction. */ + COSTS_N_INSNS (2), /* cost of FCHS instruction. */ + COSTS_N_INSNS (56), /* cost of FSQRT instruction. */ }; static const struct processor_costs athlon_cost = { - 1, /* cost of an add instruction */ - 2, /* cost of a lea instruction */ - 1, /* variable shift costs */ - 1, /* constant shift costs */ - {5, 5, 5, 5, 5}, /* cost of starting a multiply */ + COSTS_N_INSNS (1), /* cost of an add instruction */ + COSTS_N_INSNS (2), /* cost of a lea instruction */ + COSTS_N_INSNS (1), /* variable shift costs */ + COSTS_N_INSNS (1), /* constant shift costs */ + {COSTS_N_INSNS (5), /* cost of starting multiply for QI */ + COSTS_N_INSNS (5), /* HI */ + COSTS_N_INSNS (5), /* SI */ + COSTS_N_INSNS (5), /* DI */ + COSTS_N_INSNS (5)}, /* other */ 0, /* cost of multiply per each bit set */ - {18, 26, 42, 74, 74}, /* cost of a divide/mod */ - 1, /* cost of movsx */ - 1, /* cost of movzx */ + {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */ + COSTS_N_INSNS (26), /* HI */ + COSTS_N_INSNS (42), /* SI */ + COSTS_N_INSNS (74), /* DI */ + COSTS_N_INSNS (74)}, /* other */ + COSTS_N_INSNS (1), /* cost of movsx */ + COSTS_N_INSNS (1), /* cost of movzx */ 8, /* "large" insn */ 9, /* MOVE_RATIO */ 4, /* cost for loading QImode using movzbl */ @@ -350,7 +417,8 @@ struct processor_costs athlon_cost = { 4, /* cost of reg,reg fld/fst */ {4, 4, 12}, /* cost of loading fp registers in SFmode, DFmode and XFmode */ - {6, 6, 8}, /* cost of loading integer registers */ + {6, 6, 8}, /* cost of storing fp registers + in SFmode, DFmode and XFmode */ 2, /* cost of moving MMX register */ {4, 4}, /* cost of loading MMX registers in SImode and DImode */ @@ -364,26 +432,34 @@ struct processor_costs athlon_cost = { 5, /* MMX or SSE register to integer */ 64, /* size of prefetch block */ 6, /* number of parallel prefetches */ - 2, /* Branch cost */ - 4, /* cost of FADD and FSUB insns. */ - 4, /* cost of FMUL instruction. */ - 24, /* cost of FDIV instruction. */ - 2, /* cost of FABS instruction. */ - 2, /* cost of FCHS instruction. */ - 35, /* cost of FSQRT instruction. */ + 5, /* Branch cost */ + COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */ + COSTS_N_INSNS (4), /* cost of FMUL instruction. */ + COSTS_N_INSNS (24), /* cost of FDIV instruction. */ + COSTS_N_INSNS (2), /* cost of FABS instruction. */ + COSTS_N_INSNS (2), /* cost of FCHS instruction. */ + COSTS_N_INSNS (35), /* cost of FSQRT instruction. */ }; static const struct processor_costs k8_cost = { - 1, /* cost of an add instruction */ - 2, /* cost of a lea instruction */ - 1, /* variable shift costs */ - 1, /* constant shift costs */ - {3, 4, 3, 4, 5}, /* cost of starting a multiply */ + COSTS_N_INSNS (1), /* cost of an add instruction */ + COSTS_N_INSNS (2), /* cost of a lea instruction */ + COSTS_N_INSNS (1), /* variable shift costs */ + COSTS_N_INSNS (1), /* constant shift costs */ + {COSTS_N_INSNS (3), /* cost of starting multiply for QI */ + COSTS_N_INSNS (4), /* HI */ + COSTS_N_INSNS (3), /* SI */ + COSTS_N_INSNS (4), /* DI */ + COSTS_N_INSNS (5)}, /* other */ 0, /* cost of multiply per each bit set */ - {18, 26, 42, 74, 74}, /* cost of a divide/mod */ - 1, /* cost of movsx */ - 1, /* cost of movzx */ + {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */ + COSTS_N_INSNS (26), /* HI */ + COSTS_N_INSNS (42), /* SI */ + COSTS_N_INSNS (74), /* DI */ + COSTS_N_INSNS (74)}, /* other */ + COSTS_N_INSNS (1), /* cost of movsx */ + COSTS_N_INSNS (1), /* cost of movzx */ 8, /* "large" insn */ 9, /* MOVE_RATIO */ 4, /* cost for loading QImode using movzbl */ @@ -394,7 +470,8 @@ struct processor_costs k8_cost = { 4, /* cost of reg,reg fld/fst */ {4, 4, 12}, /* cost of loading fp registers in SFmode, DFmode and XFmode */ - {6, 6, 8}, /* cost of loading integer registers */ + {6, 6, 8}, /* cost of storing fp registers + in SFmode, DFmode and XFmode */ 2, /* cost of moving MMX register */ {3, 3}, /* cost of loading MMX registers in SImode and DImode */ @@ -408,26 +485,34 @@ struct processor_costs k8_cost = { 5, /* MMX or SSE register to integer */ 64, /* size of prefetch block */ 6, /* number of parallel prefetches */ - 2, /* Branch cost */ - 4, /* cost of FADD and FSUB insns. */ - 4, /* cost of FMUL instruction. */ - 19, /* cost of FDIV instruction. */ - 2, /* cost of FABS instruction. */ - 2, /* cost of FCHS instruction. */ - 35, /* cost of FSQRT instruction. */ + 5, /* Branch cost */ + COSTS_N_INSNS (4), /* cost of FADD and FSUB insns. */ + COSTS_N_INSNS (4), /* cost of FMUL instruction. */ + COSTS_N_INSNS (19), /* cost of FDIV instruction. */ + COSTS_N_INSNS (2), /* cost of FABS instruction. */ + COSTS_N_INSNS (2), /* cost of FCHS instruction. */ + COSTS_N_INSNS (35), /* cost of FSQRT instruction. */ }; static const struct processor_costs pentium4_cost = { - 1, /* cost of an add instruction */ - 1, /* cost of a lea instruction */ - 4, /* variable shift costs */ - 4, /* constant shift costs */ - {15, 15, 15, 15, 15}, /* cost of starting a multiply */ + COSTS_N_INSNS (1), /* cost of an add instruction */ + COSTS_N_INSNS (3), /* cost of a lea instruction */ + COSTS_N_INSNS (4), /* variable shift costs */ + COSTS_N_INSNS (4), /* constant shift costs */ + {COSTS_N_INSNS (15), /* cost of starting multiply for QI */ + COSTS_N_INSNS (15), /* HI */ + COSTS_N_INSNS (15), /* SI */ + COSTS_N_INSNS (15), /* DI */ + COSTS_N_INSNS (15)}, /* other */ 0, /* cost of multiply per each bit set */ - {56, 56, 56, 56, 56}, /* cost of a divide/mod */ - 1, /* cost of movsx */ - 1, /* cost of movzx */ + {COSTS_N_INSNS (56), /* cost of a divide/mod for QI */ + COSTS_N_INSNS (56), /* HI */ + COSTS_N_INSNS (56), /* SI */ + COSTS_N_INSNS (56), /* DI */ + COSTS_N_INSNS (56)}, /* other */ + COSTS_N_INSNS (1), /* cost of movsx */ + COSTS_N_INSNS (1), /* cost of movzx */ 16, /* "large" insn */ 6, /* MOVE_RATIO */ 2, /* cost for loading QImode using movzbl */ @@ -438,7 +523,8 @@ struct processor_costs pentium4_cost = { 2, /* cost of reg,reg fld/fst */ {2, 2, 6}, /* cost of loading fp registers in SFmode, DFmode and XFmode */ - {4, 4, 6}, /* cost of loading integer registers */ + {4, 4, 6}, /* cost of storing fp registers + in SFmode, DFmode and XFmode */ 2, /* cost of moving MMX register */ {2, 2}, /* cost of loading MMX registers in SImode and DImode */ @@ -453,12 +539,179 @@ struct processor_costs pentium4_cost = { 64, /* size of prefetch block */ 6, /* number of parallel prefetches */ 2, /* Branch cost */ - 5, /* cost of FADD and FSUB insns. */ - 7, /* cost of FMUL instruction. */ - 43, /* cost of FDIV instruction. */ - 2, /* cost of FABS instruction. */ - 2, /* cost of FCHS instruction. */ - 43, /* cost of FSQRT instruction. */ + COSTS_N_INSNS (5), /* cost of FADD and FSUB insns. */ + COSTS_N_INSNS (7), /* cost of FMUL instruction. */ + COSTS_N_INSNS (43), /* cost of FDIV instruction. */ + COSTS_N_INSNS (2), /* cost of FABS instruction. */ + COSTS_N_INSNS (2), /* cost of FCHS instruction. */ + COSTS_N_INSNS (43), /* cost of FSQRT instruction. */ +}; + +static const +struct processor_costs nocona_cost = { + COSTS_N_INSNS (1), /* cost of an add instruction */ + COSTS_N_INSNS (1), /* cost of a lea instruction */ + COSTS_N_INSNS (1), /* variable shift costs */ + COSTS_N_INSNS (1), /* constant shift costs */ + {COSTS_N_INSNS (10), /* cost of starting multiply for QI */ + COSTS_N_INSNS (10), /* HI */ + COSTS_N_INSNS (10), /* SI */ + COSTS_N_INSNS (10), /* DI */ + COSTS_N_INSNS (10)}, /* other */ + 0, /* cost of multiply per each bit set */ + {COSTS_N_INSNS (66), /* cost of a divide/mod for QI */ + COSTS_N_INSNS (66), /* HI */ + COSTS_N_INSNS (66), /* SI */ + COSTS_N_INSNS (66), /* DI */ + COSTS_N_INSNS (66)}, /* other */ + COSTS_N_INSNS (1), /* cost of movsx */ + COSTS_N_INSNS (1), /* cost of movzx */ + 16, /* "large" insn */ + 17, /* MOVE_RATIO */ + 4, /* cost for loading QImode using movzbl */ + {4, 4, 4}, /* cost of loading integer registers + in QImode, HImode and SImode. + Relative to reg-reg move (2). */ + {4, 4, 4}, /* cost of storing integer registers */ + 3, /* cost of reg,reg fld/fst */ + {12, 12, 12}, /* cost of loading fp registers + in SFmode, DFmode and XFmode */ + {4, 4, 4}, /* cost of storing fp registers + in SFmode, DFmode and XFmode */ + 6, /* cost of moving MMX register */ + {12, 12}, /* cost of loading MMX registers + in SImode and DImode */ + {12, 12}, /* cost of storing MMX registers + in SImode and DImode */ + 6, /* cost of moving SSE register */ + {12, 12, 12}, /* cost of loading SSE registers + in SImode, DImode and TImode */ + {12, 12, 12}, /* cost of storing SSE registers + in SImode, DImode and TImode */ + 8, /* MMX or SSE register to integer */ + 128, /* size of prefetch block */ + 8, /* number of parallel prefetches */ + 1, /* Branch cost */ + COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */ + COSTS_N_INSNS (8), /* cost of FMUL instruction. */ + COSTS_N_INSNS (40), /* cost of FDIV instruction. */ + COSTS_N_INSNS (3), /* cost of FABS instruction. */ + COSTS_N_INSNS (3), /* cost of FCHS instruction. */ + COSTS_N_INSNS (44), /* cost of FSQRT instruction. */ +}; + +/* Generic64 should produce code tuned for Nocona and K8. */ +static const +struct processor_costs generic64_cost = { + COSTS_N_INSNS (1), /* cost of an add instruction */ + /* On all chips taken into consideration lea is 2 cycles and more. With + this cost however our current implementation of synth_mult results in + use of unnecessary temporary registers causing regression on several + SPECfp benchmarks. */ + COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */ + COSTS_N_INSNS (1), /* variable shift costs */ + COSTS_N_INSNS (1), /* constant shift costs */ + {COSTS_N_INSNS (3), /* cost of starting multiply for QI */ + COSTS_N_INSNS (4), /* HI */ + COSTS_N_INSNS (3), /* SI */ + COSTS_N_INSNS (4), /* DI */ + COSTS_N_INSNS (2)}, /* other */ + 0, /* cost of multiply per each bit set */ + {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */ + COSTS_N_INSNS (26), /* HI */ + COSTS_N_INSNS (42), /* SI */ + COSTS_N_INSNS (74), /* DI */ + COSTS_N_INSNS (74)}, /* other */ + COSTS_N_INSNS (1), /* cost of movsx */ + COSTS_N_INSNS (1), /* cost of movzx */ + 8, /* "large" insn */ + 17, /* MOVE_RATIO */ + 4, /* cost for loading QImode using movzbl */ + {4, 4, 4}, /* cost of loading integer registers + in QImode, HImode and SImode. + Relative to reg-reg move (2). */ + {4, 4, 4}, /* cost of storing integer registers */ + 4, /* cost of reg,reg fld/fst */ + {12, 12, 12}, /* cost of loading fp registers + in SFmode, DFmode and XFmode */ + {6, 6, 8}, /* cost of storing fp registers + in SFmode, DFmode and XFmode */ + 2, /* cost of moving MMX register */ + {8, 8}, /* cost of loading MMX registers + in SImode and DImode */ + {8, 8}, /* cost of storing MMX registers + in SImode and DImode */ + 2, /* cost of moving SSE register */ + {8, 8, 8}, /* cost of loading SSE registers + in SImode, DImode and TImode */ + {8, 8, 8}, /* cost of storing SSE registers + in SImode, DImode and TImode */ + 5, /* MMX or SSE register to integer */ + 64, /* size of prefetch block */ + 6, /* number of parallel prefetches */ + /* Benchmarks shows large regressions on K8 sixtrack benchmark when this value + is increased to perhaps more appropriate value of 5. */ + 3, /* Branch cost */ + COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */ + COSTS_N_INSNS (8), /* cost of FMUL instruction. */ + COSTS_N_INSNS (20), /* cost of FDIV instruction. */ + COSTS_N_INSNS (8), /* cost of FABS instruction. */ + COSTS_N_INSNS (8), /* cost of FCHS instruction. */ + COSTS_N_INSNS (40), /* cost of FSQRT instruction. */ +}; + +/* Generic32 should produce code tuned for Athlon, PPro, Pentium4, Nocona and K8. */ +static const +struct processor_costs generic32_cost = { + COSTS_N_INSNS (1), /* cost of an add instruction */ + COSTS_N_INSNS (1) + 1, /* cost of a lea instruction */ + COSTS_N_INSNS (1), /* variable shift costs */ + COSTS_N_INSNS (1), /* constant shift costs */ + {COSTS_N_INSNS (3), /* cost of starting multiply for QI */ + COSTS_N_INSNS (4), /* HI */ + COSTS_N_INSNS (3), /* SI */ + COSTS_N_INSNS (4), /* DI */ + COSTS_N_INSNS (2)}, /* other */ + 0, /* cost of multiply per each bit set */ + {COSTS_N_INSNS (18), /* cost of a divide/mod for QI */ + COSTS_N_INSNS (26), /* HI */ + COSTS_N_INSNS (42), /* SI */ + COSTS_N_INSNS (74), /* DI */ + COSTS_N_INSNS (74)}, /* other */ + COSTS_N_INSNS (1), /* cost of movsx */ + COSTS_N_INSNS (1), /* cost of movzx */ + 8, /* "large" insn */ + 17, /* MOVE_RATIO */ + 4, /* cost for loading QImode using movzbl */ + {4, 4, 4}, /* cost of loading integer registers + in QImode, HImode and SImode. + Relative to reg-reg move (2). */ + {4, 4, 4}, /* cost of storing integer registers */ + 4, /* cost of reg,reg fld/fst */ + {12, 12, 12}, /* cost of loading fp registers + in SFmode, DFmode and XFmode */ + {6, 6, 8}, /* cost of storing fp registers + in SFmode, DFmode and XFmode */ + 2, /* cost of moving MMX register */ + {8, 8}, /* cost of loading MMX registers + in SImode and DImode */ + {8, 8}, /* cost of storing MMX registers + in SImode and DImode */ + 2, /* cost of moving SSE register */ + {8, 8, 8}, /* cost of loading SSE registers + in SImode, DImode and TImode */ + {8, 8, 8}, /* cost of storing SSE registers + in SImode, DImode and TImode */ + 5, /* MMX or SSE register to integer */ + 64, /* size of prefetch block */ + 6, /* number of parallel prefetches */ + 3, /* Branch cost */ + COSTS_N_INSNS (8), /* cost of FADD and FSUB insns. */ + COSTS_N_INSNS (8), /* cost of FMUL instruction. */ + COSTS_N_INSNS (20), /* cost of FDIV instruction. */ + COSTS_N_INSNS (8), /* cost of FABS instruction. */ + COSTS_N_INSNS (8), /* cost of FCHS instruction. */ + COSTS_N_INSNS (40), /* cost of FSQRT instruction. */ }; const struct processor_costs *ix86_cost = &pentium_cost; @@ -473,68 +726,112 @@ const struct processor_costs *ix86_cost = &pentium_cost; #define m_PENT4 (1<<PROCESSOR_PENTIUM4) #define m_K8 (1<<PROCESSOR_K8) #define m_ATHLON_K8 (m_K8 | m_ATHLON) - -const int x86_use_leave = m_386 | m_K6 | m_ATHLON_K8; -const int x86_push_memory = m_386 | m_K6 | m_ATHLON_K8 | m_PENT4; +#define m_NOCONA (1<<PROCESSOR_NOCONA) +#define m_GENERIC32 (1<<PROCESSOR_GENERIC32) +#define m_GENERIC64 (1<<PROCESSOR_GENERIC64) +#define m_GENERIC (m_GENERIC32 | m_GENERIC64) + +/* Generic instruction choice should be common subset of supported CPUs + (PPro/PENT4/NOCONA/Athlon/K8). */ + +/* Leave is not affecting Nocona SPEC2000 results negatively, so enabling for + Generic64 seems like good code size tradeoff. We can't enable it for 32bit + generic because it is not working well with PPro base chips. */ +const int x86_use_leave = m_386 | m_K6 | m_ATHLON_K8 | m_GENERIC64; +const int x86_push_memory = m_386 | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC; const int x86_zero_extend_with_and = m_486 | m_PENT; -const int x86_movx = m_ATHLON_K8 | m_PPRO | m_PENT4 /* m_386 | m_K6 */; +const int x86_movx = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_GENERIC /* m_386 | m_K6 */; const int x86_double_with_add = ~m_386; const int x86_use_bit_test = m_386; -const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON_K8 | m_K6; -const int x86_cmove = m_PPRO | m_ATHLON_K8 | m_PENT4; +const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON_K8 | m_K6 | m_GENERIC; +const int x86_cmove = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA; const int x86_3dnow_a = m_ATHLON_K8; -const int x86_deep_branch = m_PPRO | m_K6 | m_ATHLON_K8 | m_PENT4; -const int x86_branch_hints = m_PENT4; -const int x86_use_sahf = m_PPRO | m_K6 | m_PENT4; +const int x86_deep_branch = m_PPRO | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC; +/* Branch hints were put in P4 based on simulation result. But + after P4 was made, no performance benefit was observed with + branch hints. It also increases the code size. As the result, + icc never generates branch hints. */ +const int x86_branch_hints = 0; +const int x86_use_sahf = m_PPRO | m_K6 | m_PENT4 | m_NOCONA | m_GENERIC32; /*m_GENERIC | m_ATHLON_K8 ? */ +/* We probably ought to watch for partial register stalls on Generic32 + compilation setting as well. However in current implementation the + partial register stalls are not eliminated very well - they can + be introduced via subregs synthesized by combine and can happen + in caller/callee saving sequences. + Because this option pays back little on PPro based chips and is in conflict + with partial reg. dependencies used by Athlon/P4 based chips, it is better + to leave it off for generic32 for now. */ const int x86_partial_reg_stall = m_PPRO; -const int x86_use_loop = m_K6; -const int x86_use_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT); +const int x86_partial_flag_reg_stall = m_GENERIC; +const int x86_use_himode_fiop = m_386 | m_486 | m_K6; +const int x86_use_simode_fiop = ~(m_PPRO | m_ATHLON_K8 | m_PENT | m_GENERIC); const int x86_use_mov0 = m_K6; -const int x86_use_cltd = ~(m_PENT | m_K6); +const int x86_use_cltd = ~(m_PENT | m_K6 | m_GENERIC); const int x86_read_modify_write = ~m_PENT; const int x86_read_modify = ~(m_PENT | m_PPRO); const int x86_split_long_moves = m_PPRO; -const int x86_promote_QImode = m_K6 | m_PENT | m_386 | m_486 | m_ATHLON_K8; +const int x86_promote_QImode = m_K6 | m_PENT | m_386 | m_486 | m_ATHLON_K8 | m_GENERIC; /* m_PENT4 ? */ const int x86_fast_prefix = ~(m_PENT | m_486 | m_386); -const int x86_single_stringop = m_386 | m_PENT4; +const int x86_single_stringop = m_386 | m_PENT4 | m_NOCONA; const int x86_qimode_math = ~(0); const int x86_promote_qi_regs = 0; +/* On PPro this flag is meant to avoid partial register stalls. Just like + the x86_partial_reg_stall this option might be considered for Generic32 + if our scheme for avoiding partial stalls was more effective. */ const int x86_himode_math = ~(m_PPRO); const int x86_promote_hi_regs = m_PPRO; -const int x86_sub_esp_4 = m_ATHLON_K8 | m_PPRO | m_PENT4; -const int x86_sub_esp_8 = m_ATHLON_K8 | m_PPRO | m_386 | m_486 | m_PENT4; -const int x86_add_esp_4 = m_ATHLON_K8 | m_K6 | m_PENT4; -const int x86_add_esp_8 = m_ATHLON_K8 | m_PPRO | m_K6 | m_386 | m_486 | m_PENT4; -const int x86_integer_DFmode_moves = ~(m_ATHLON_K8 | m_PENT4 | m_PPRO); -const int x86_partial_reg_dependency = m_ATHLON_K8 | m_PENT4; -const int x86_memory_mismatch_stall = m_ATHLON_K8 | m_PENT4; -const int x86_accumulate_outgoing_args = m_ATHLON_K8 | m_PENT4 | m_PPRO; -const int x86_prologue_using_move = m_ATHLON_K8 | m_PENT4 | m_PPRO; -const int x86_epilogue_using_move = m_ATHLON_K8 | m_PENT4 | m_PPRO; -const int x86_decompose_lea = m_PENT4; +const int x86_sub_esp_4 = m_ATHLON_K8 | m_PPRO | m_PENT4 | m_NOCONA | m_GENERIC; +const int x86_sub_esp_8 = m_ATHLON_K8 | m_PPRO | m_386 | m_486 | m_PENT4 | m_NOCONA | m_GENERIC; +const int x86_add_esp_4 = m_ATHLON_K8 | m_K6 | m_PENT4 | m_NOCONA | m_GENERIC; +const int x86_add_esp_8 = m_ATHLON_K8 | m_PPRO | m_K6 | m_386 | m_486 | m_PENT4 | m_NOCONA | m_GENERIC; +const int x86_integer_DFmode_moves = ~(m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC); +const int x86_partial_reg_dependency = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC; +const int x86_memory_mismatch_stall = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC; +const int x86_accumulate_outgoing_args = m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC; +const int x86_prologue_using_move = m_ATHLON_K8 | m_PPRO | m_GENERIC; +const int x86_epilogue_using_move = m_ATHLON_K8 | m_PPRO | m_GENERIC; const int x86_shift1 = ~m_486; -const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PENT4; -const int x86_sse_partial_reg_dependency = m_PENT4 | m_PPRO; -/* Set for machines where the type and dependencies are resolved on SSE register - parts instead of whole registers, so we may maintain just lower part of - scalar values in proper format leaving the upper part undefined. */ -const int x86_sse_partial_regs = m_ATHLON_K8; -/* Athlon optimizes partial-register FPS special case, thus avoiding the - need for extra instructions beforehand */ -const int x86_sse_partial_regs_for_cvtsd2ss = 0; +const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC; +/* In Generic model we have an conflict here in between PPro/Pentium4 based chips + that thread 128bit SSE registers as single units versus K8 based chips that + divide SSE registers to two 64bit halves. + x86_sse_partial_reg_dependency promote all store destinations to be 128bit + to allow register renaming on 128bit SSE units, but usually results in one + extra microop on 64bit SSE units. Experimental results shows that disabling + this option on P4 brings over 20% SPECfp regression, while enabling it on + K8 brings roughly 2.4% regression that can be partly masked by careful scheduling + of moves. */ +const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC; +/* Set for machines where the type and dependencies are resolved on SSE + register parts instead of whole registers, so we may maintain just + lower part of scalar values in proper format leaving the upper part + undefined. */ +const int x86_sse_split_regs = m_ATHLON_K8; const int x86_sse_typeless_stores = m_ATHLON_K8; -const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4; +const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4 | m_NOCONA; const int x86_use_ffreep = m_ATHLON_K8; const int x86_rep_movl_optimal = m_386 | m_PENT | m_PPRO | m_K6; - -/* ??? HACK! The following is a lie. SSE can hold e.g. SImode, and - indeed *must* be able to hold SImode so that SSE2 shifts are able - to work right. But this can result in some mighty surprising - register allocation when building kernels. Turning this off should - make us less likely to all-of-the-sudden select an SSE register. */ -const int x86_inter_unit_moves = 0; /* ~(m_ATHLON_K8) */ - -const int x86_ext_80387_constants = m_K6 | m_ATHLON | m_PENT4 | m_PPRO; +const int x86_use_incdec = ~(m_PENT4 | m_NOCONA | m_GENERIC); + +/* ??? Allowing interunit moves makes it all too easy for the compiler to put + integer data in xmm registers. Which results in pretty abysmal code. */ +const int x86_inter_unit_moves = 0 /* ~(m_ATHLON_K8) */; + +const int x86_ext_80387_constants = m_K6 | m_ATHLON | m_PENT4 | m_NOCONA | m_PPRO | m_GENERIC32; +/* Some CPU cores are not able to predict more than 4 branch instructions in + the 16 byte window. */ +const int x86_four_jump_limit = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC; +const int x86_schedule = m_PPRO | m_ATHLON_K8 | m_K6 | m_PENT | m_GENERIC; +const int x86_use_bt = m_ATHLON_K8; +/* Compare and exchange was added for 80486. */ +const int x86_cmpxchg = ~m_386; +/* Compare and exchange 8 bytes was added for pentium. */ +const int x86_cmpxchg8b = ~(m_386 | m_486); +/* Compare and exchange 16 bytes was added for nocona. */ +const int x86_cmpxchg16b = m_NOCONA; +/* Exchange and add was added for 80486. */ +const int x86_xadd = ~m_386; +const int x86_pad_returns = m_ATHLON_K8 | m_GENERIC; /* In case the average insn count for single function invocation is lower than this constant, emit fast (but longer) prologue and @@ -678,8 +975,8 @@ int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] = rtx ix86_compare_op0 = NULL_RTX; rtx ix86_compare_op1 = NULL_RTX; +rtx ix86_compare_emitted = NULL_RTX; -#define MAX_386_STACK_LOCALS 3 /* Size of the register save area. */ #define X86_64_VARARGS_SIZE (REGPARM_MAX * UNITS_PER_WORD + SSE_REGPARM_MAX * 16) @@ -733,17 +1030,11 @@ struct ix86_frame bool save_regs_using_mov; }; -/* Used to enable/disable debugging features. */ -const char *ix86_debug_arg_string, *ix86_debug_addr_string; -/* Code model option as passed by user. */ -const char *ix86_cmodel_string; -/* Parsed value. */ +/* Code model option. */ enum cmodel ix86_cmodel; /* Asm dialect. */ -const char *ix86_asm_string; enum asm_dialect ix86_asm_dialect = ASM_ATT; -/* TLS dialext. */ -const char *ix86_tls_dialect_string; +/* TLS dialects. */ enum tls_dialect ix86_tls_dialect = TLS_DIALECT_GNU; /* Which unit we are generating floating point math for. */ @@ -754,53 +1045,37 @@ enum processor_type ix86_tune; /* Which instruction set architecture to use. */ enum processor_type ix86_arch; -/* Strings to hold which cpu and instruction set architecture to use. */ -const char *ix86_tune_string; /* for -mtune=<xxx> */ -const char *ix86_arch_string; /* for -march=<xxx> */ -const char *ix86_fpmath_string; /* for -mfpmath=<xxx> */ - -/* # of registers to use to pass arguments. */ -const char *ix86_regparm_string; - /* true if sse prefetch instruction is not NOOP. */ int x86_prefetch_sse; /* ix86_regparm_string as a number */ -int ix86_regparm; - -/* Alignment to use for loops and jumps: */ +static int ix86_regparm; -/* Power of two alignment for loops. */ -const char *ix86_align_loops_string; - -/* Power of two alignment for non-loop jumps. */ -const char *ix86_align_jumps_string; - -/* Power of two alignment for stack boundary in bytes. */ -const char *ix86_preferred_stack_boundary_string; +/* -mstackrealign option */ +extern int ix86_force_align_arg_pointer; +static const char ix86_force_align_arg_pointer_string[] = "force_align_arg_pointer"; /* Preferred alignment for stack boundary in bits. */ -int ix86_preferred_stack_boundary; +unsigned int ix86_preferred_stack_boundary; /* Values 1-5: see jump.c */ int ix86_branch_cost; -const char *ix86_branch_cost_string; -/* Power of two alignment for functions. */ -const char *ix86_align_funcs_string; +/* Variables which are this size or smaller are put in the data/bss + or ldata/lbss sections. */ + +int ix86_section_threshold = 65536; /* Prefix built by ASM_GENERATE_INTERNAL_LABEL. */ -static char internal_label_prefix[16]; -static int internal_label_prefix_len; +char internal_label_prefix[16]; +int internal_label_prefix_len; -static int local_symbolic_operand (rtx, enum machine_mode); -static int tls_symbolic_operand_1 (rtx, enum tls_model); +static bool ix86_handle_option (size_t, const char *, int); static void output_pic_addr_const (FILE *, rtx, int); static void put_condition_code (enum rtx_code, enum machine_mode, int, int, FILE *); static const char *get_some_local_dynamic_name (void); static int get_some_local_dynamic_name_1 (rtx *, void *); -static rtx maybe_get_pool_constant (rtx); static rtx ix86_expand_int_compare (enum rtx_code, rtx, rtx); static enum rtx_code ix86_prepare_fp_compare_args (enum rtx_code, rtx *, rtx *); @@ -811,12 +1086,8 @@ static rtx get_thread_pointer (int); static rtx legitimize_tls_address (rtx, enum tls_model, int); static void get_pc_thunk_name (char [32], unsigned int); static rtx gen_push (rtx); -static int memory_address_length (rtx addr); -static int ix86_flags_dependant (rtx, rtx, enum attr_type); -static int ix86_agi_dependant (rtx, rtx, enum attr_type); -static enum attr_ppro_uops ix86_safe_ppro_uops (rtx); -static void ix86_dump_ppro_packet (FILE *); -static void ix86_reorder_insn (rtx *, rtx *); +static int ix86_flags_dependent (rtx, rtx, enum attr_type); +static int ix86_agi_dependent (rtx, rtx, enum attr_type); static struct machine_function * ix86_init_machine_status (void); static int ix86_split_to_parts (rtx, rtx *, enum machine_mode); static int ix86_nsaved_regs (void); @@ -824,17 +1095,12 @@ static void ix86_emit_save_regs (void); static void ix86_emit_save_regs_using_mov (rtx, HOST_WIDE_INT); static void ix86_emit_restore_regs_using_mov (rtx, HOST_WIDE_INT, int); static void ix86_output_function_epilogue (FILE *, HOST_WIDE_INT); -static void ix86_sched_reorder_ppro (rtx *, rtx *); static HOST_WIDE_INT ix86_GOT_alias_set (void); static void ix86_adjust_counter (rtx, HOST_WIDE_INT); static rtx ix86_expand_aligntest (rtx, int); static void ix86_expand_strlensi_unroll_1 (rtx, rtx, rtx); static int ix86_issue_rate (void); static int ix86_adjust_cost (rtx, rtx, rtx, int); -static void ix86_sched_init (FILE *, int, int); -static int ix86_sched_reorder (FILE *, int, rtx *, int *, int); -static int ix86_variable_issue (FILE *, int, rtx, int); -static int ia32_use_dfa_pipeline_interface (void); static int ia32_multipass_dfa_lookahead (void); static void ix86_init_mmx_sse_builtins (void); static rtx x86_this_parameter (tree); @@ -845,19 +1111,18 @@ static void x86_file_start (void); static void ix86_reorg (void); static bool ix86_expand_carry_flag_compare (enum rtx_code, rtx, rtx, rtx*); static tree ix86_build_builtin_va_list (void); +static void ix86_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode, + tree, int *, int); +static tree ix86_gimplify_va_arg (tree, tree, tree *, tree *); +static bool ix86_scalar_mode_supported_p (enum machine_mode); +static bool ix86_vector_mode_supported_p (enum machine_mode); -struct ix86_address -{ - rtx base, index, disp; - HOST_WIDE_INT scale; - enum ix86_address_seg { SEG_DEFAULT, SEG_FS, SEG_GS } seg; -}; - -static int ix86_decompose_address (rtx, struct ix86_address *); static int ix86_address_cost (rtx); static bool ix86_cannot_force_const_mem (rtx); static rtx ix86_delegitimize_address (rtx); +static void i386_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; + struct builtin_description; static rtx ix86_expand_sse_comi (const struct builtin_description *, tree, rtx); @@ -868,9 +1133,6 @@ static rtx ix86_expand_unop_builtin (enum insn_code, tree, rtx, int); static rtx ix86_expand_binop_builtin (enum insn_code, tree, rtx); static rtx ix86_expand_store_builtin (enum insn_code, tree); static rtx safe_vector_operand (rtx, enum machine_mode); -static enum rtx_code ix86_fp_compare_code_to_integer (enum rtx_code); -static void ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *, - enum rtx_code *, enum rtx_code *); static rtx ix86_expand_fp_compare (enum rtx_code, rtx, rtx, rtx, rtx *, rtx *); static int ix86_fp_comparison_arithmetics_cost (enum rtx_code code); static int ix86_fp_comparison_fcomi_cost (enum rtx_code code); @@ -883,20 +1145,29 @@ static int ix86_comp_type_attributes (tree, tree); static int ix86_function_regparm (tree, tree); const struct attribute_spec ix86_attribute_table[]; static bool ix86_function_ok_for_sibcall (tree, tree); -static tree ix86_handle_cdecl_attribute (tree *, tree, tree, int, bool *); -static tree ix86_handle_regparm_attribute (tree *, tree, tree, int, bool *); -static int ix86_value_regno (enum machine_mode); +static tree ix86_handle_cconv_attribute (tree *, tree, tree, int, bool *); +static int ix86_value_regno (enum machine_mode, tree, tree); static bool contains_128bit_aligned_vector_p (tree); +static rtx ix86_struct_value_rtx (tree, int); static bool ix86_ms_bitfield_layout_p (tree); static tree ix86_handle_struct_attribute (tree *, tree, tree, int, bool *); static int extended_reg_mentioned_1 (rtx *, void *); static bool ix86_rtx_costs (rtx, int, int, int *); static int min_insn_size (rtx); -static void k8_avoid_jump_misspredicts (void); - -#if defined (DO_GLOBAL_CTORS_BODY) && defined (HAS_INIT_SECTION) -static void ix86_svr3_asm_out_constructor (rtx, int); -#endif +static tree ix86_md_asm_clobbers (tree outputs, tree inputs, tree clobbers); +static bool ix86_must_pass_in_stack (enum machine_mode mode, tree type); +static bool ix86_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode, + tree, bool); +static void ix86_init_builtins (void); +static rtx ix86_expand_builtin (tree, rtx, rtx, enum machine_mode, int); +static const char *ix86_mangle_fundamental_type (tree); +static tree ix86_stack_protect_fail (void); +static rtx ix86_internal_arg_pointer (void); +static void ix86_dwarf_handle_frame_unspec (const char *, rtx, int); + +/* This function is only used on Solaris. */ +static void i386_solaris_elf_named_section (const char *, unsigned int, tree) + ATTRIBUTE_UNUSED; /* Register class used for passing given 64bit part of the argument. These represent classes as documented by the PS ABI, with the exception @@ -917,29 +1188,31 @@ enum x86_64_reg_class X86_64_SSEUP_CLASS, X86_64_X87_CLASS, X86_64_X87UP_CLASS, + X86_64_COMPLEX_X87_CLASS, X86_64_MEMORY_CLASS }; -static const char * const x86_64_reg_class_name[] = - {"no", "integer", "integerSI", "sse", "sseSF", "sseDF", "sseup", "x87", "x87up", "no"}; +static const char * const x86_64_reg_class_name[] = { + "no", "integer", "integerSI", "sse", "sseSF", "sseDF", + "sseup", "x87", "x87up", "cplx87", "no" +}; #define MAX_CLASSES 4 -static int classify_argument (enum machine_mode, tree, - enum x86_64_reg_class [MAX_CLASSES], int); -static int examine_argument (enum machine_mode, tree, int, int *, int *); -static rtx construct_container (enum machine_mode, tree, int, int, int, - const int *, int); -static enum x86_64_reg_class merge_classes (enum x86_64_reg_class, - enum x86_64_reg_class); /* Table of constants used by fldpi, fldln2, etc.... */ static REAL_VALUE_TYPE ext_80387_constants_table [5]; static bool ext_80387_constants_init = 0; static void init_ext_80387_constants (void); +static bool ix86_in_large_data_p (tree) ATTRIBUTE_UNUSED; +static void ix86_encode_section_info (tree, rtx, int) ATTRIBUTE_UNUSED; +static void x86_64_elf_unique_section (tree decl, int reloc) ATTRIBUTE_UNUSED; +static section *x86_64_elf_select_section (tree decl, int reloc, + unsigned HOST_WIDE_INT align) + ATTRIBUTE_UNUSED; /* Initialize the GCC target structure. */ #undef TARGET_ATTRIBUTE_TABLE #define TARGET_ATTRIBUTE_TABLE ix86_attribute_table -#ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES +#if TARGET_DLLIMPORT_DECL_ATTRIBUTES # undef TARGET_MERGE_DECL_ATTRIBUTES # define TARGET_MERGE_DECL_ATTRIBUTES merge_dllimport_decl_attributes #endif @@ -949,13 +1222,19 @@ static void init_ext_80387_constants (void); #undef TARGET_INIT_BUILTINS #define TARGET_INIT_BUILTINS ix86_init_builtins - #undef TARGET_EXPAND_BUILTIN #define TARGET_EXPAND_BUILTIN ix86_expand_builtin #undef TARGET_ASM_FUNCTION_EPILOGUE #define TARGET_ASM_FUNCTION_EPILOGUE ix86_output_function_epilogue +#undef TARGET_ENCODE_SECTION_INFO +#ifndef SUBTARGET_ENCODE_SECTION_INFO +#define TARGET_ENCODE_SECTION_INFO ix86_encode_section_info +#else +#define TARGET_ENCODE_SECTION_INFO SUBTARGET_ENCODE_SECTION_INFO +#endif + #undef TARGET_ASM_OPEN_PAREN #define TARGET_ASM_OPEN_PAREN "" #undef TARGET_ASM_CLOSE_PAREN @@ -981,15 +1260,6 @@ static void init_ext_80387_constants (void); #define TARGET_SCHED_ADJUST_COST ix86_adjust_cost #undef TARGET_SCHED_ISSUE_RATE #define TARGET_SCHED_ISSUE_RATE ix86_issue_rate -#undef TARGET_SCHED_VARIABLE_ISSUE -#define TARGET_SCHED_VARIABLE_ISSUE ix86_variable_issue -#undef TARGET_SCHED_INIT -#define TARGET_SCHED_INIT ix86_sched_init -#undef TARGET_SCHED_REORDER -#define TARGET_SCHED_REORDER ix86_sched_reorder -#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE -#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE \ - ia32_use_dfa_pipeline_interface #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \ ia32_multipass_dfa_lookahead @@ -1003,6 +1273,8 @@ static void init_ext_80387_constants (void); #endif #undef TARGET_CANNOT_FORCE_CONST_MEM #define TARGET_CANNOT_FORCE_CONST_MEM ix86_cannot_force_const_mem +#undef TARGET_USE_BLOCKS_FOR_CONSTANT_P +#define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_rtx_true #undef TARGET_DELEGITIMIZE_ADDRESS #define TARGET_DELEGITIMIZE_ADDRESS ix86_delegitimize_address @@ -1010,6 +1282,11 @@ static void init_ext_80387_constants (void); #undef TARGET_MS_BITFIELD_LAYOUT_P #define TARGET_MS_BITFIELD_LAYOUT_P ix86_ms_bitfield_layout_p +#if TARGET_MACHO +#undef TARGET_BINDS_LOCAL_P +#define TARGET_BINDS_LOCAL_P darwin_binds_local_p +#endif + #undef TARGET_ASM_OUTPUT_MI_THUNK #define TARGET_ASM_OUTPUT_MI_THUNK x86_output_mi_thunk #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK @@ -1018,6 +1295,16 @@ static void init_ext_80387_constants (void); #undef TARGET_ASM_FILE_START #define TARGET_ASM_FILE_START x86_file_start +#undef TARGET_DEFAULT_TARGET_FLAGS +#define TARGET_DEFAULT_TARGET_FLAGS \ + (TARGET_DEFAULT \ + | TARGET_64BIT_DEFAULT \ + | TARGET_SUBTARGET_DEFAULT \ + | TARGET_TLS_DIRECT_SEG_REFS_DEFAULT) + +#undef TARGET_HANDLE_OPTION +#define TARGET_HANDLE_OPTION ix86_handle_option + #undef TARGET_RTX_COSTS #define TARGET_RTX_COSTS ix86_rtx_costs #undef TARGET_ADDRESS_COST @@ -1034,7 +1321,54 @@ static void init_ext_80387_constants (void); #undef TARGET_BUILD_BUILTIN_VA_LIST #define TARGET_BUILD_BUILTIN_VA_LIST ix86_build_builtin_va_list +#undef TARGET_MD_ASM_CLOBBERS +#define TARGET_MD_ASM_CLOBBERS ix86_md_asm_clobbers + +#undef TARGET_PROMOTE_PROTOTYPES +#define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true +#undef TARGET_STRUCT_VALUE_RTX +#define TARGET_STRUCT_VALUE_RTX ix86_struct_value_rtx +#undef TARGET_SETUP_INCOMING_VARARGS +#define TARGET_SETUP_INCOMING_VARARGS ix86_setup_incoming_varargs +#undef TARGET_MUST_PASS_IN_STACK +#define TARGET_MUST_PASS_IN_STACK ix86_must_pass_in_stack +#undef TARGET_PASS_BY_REFERENCE +#define TARGET_PASS_BY_REFERENCE ix86_pass_by_reference +#undef TARGET_INTERNAL_ARG_POINTER +#define TARGET_INTERNAL_ARG_POINTER ix86_internal_arg_pointer +#undef TARGET_DWARF_HANDLE_FRAME_UNSPEC +#define TARGET_DWARF_HANDLE_FRAME_UNSPEC ix86_dwarf_handle_frame_unspec + +#undef TARGET_GIMPLIFY_VA_ARG_EXPR +#define TARGET_GIMPLIFY_VA_ARG_EXPR ix86_gimplify_va_arg + +#undef TARGET_SCALAR_MODE_SUPPORTED_P +#define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p + +#undef TARGET_VECTOR_MODE_SUPPORTED_P +#define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p + +#ifdef HAVE_AS_TLS +#undef TARGET_ASM_OUTPUT_DWARF_DTPREL +#define TARGET_ASM_OUTPUT_DWARF_DTPREL i386_output_dwarf_dtprel +#endif + +#ifdef SUBTARGET_INSERT_ATTRIBUTES +#undef TARGET_INSERT_ATTRIBUTES +#define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES +#endif + +#undef TARGET_MANGLE_FUNDAMENTAL_TYPE +#define TARGET_MANGLE_FUNDAMENTAL_TYPE ix86_mangle_fundamental_type + +#undef TARGET_STACK_PROTECT_FAIL +#define TARGET_STACK_PROTECT_FAIL ix86_stack_protect_fail + +#undef TARGET_FUNCTION_VALUE +#define TARGET_FUNCTION_VALUE ix86_function_value + struct gcc_target targetm = TARGET_INITIALIZER; + /* The svr4 ABI for the i386 says that records and unions are returned in memory. */ @@ -1042,6 +1376,50 @@ struct gcc_target targetm = TARGET_INITIALIZER; #define DEFAULT_PCC_STRUCT_RETURN 1 #endif +/* Implement TARGET_HANDLE_OPTION. */ + +static bool +ix86_handle_option (size_t code, const char *arg ATTRIBUTE_UNUSED, int value) +{ + switch (code) + { + case OPT_m3dnow: + if (!value) + { + target_flags &= ~MASK_3DNOW_A; + target_flags_explicit |= MASK_3DNOW_A; + } + return true; + + case OPT_mmmx: + if (!value) + { + target_flags &= ~(MASK_3DNOW | MASK_3DNOW_A); + target_flags_explicit |= MASK_3DNOW | MASK_3DNOW_A; + } + return true; + + case OPT_msse: + if (!value) + { + target_flags &= ~(MASK_SSE2 | MASK_SSE3); + target_flags_explicit |= MASK_SSE2 | MASK_SSE3; + } + return true; + + case OPT_msse2: + if (!value) + { + target_flags &= ~MASK_SSE3; + target_flags_explicit |= MASK_SSE3; + } + return true; + + default: + return true; + } +} + /* Sometimes certain combinations of command options do not make sense on a particular target machine. You can define a macro `OVERRIDE_OPTIONS' to take account of this. This macro, if @@ -1055,6 +1433,8 @@ void override_options (void) { int i; + int ix86_tune_defaulted = 0; + /* Comes from final.c -- no real reason to change it. */ #define MAX_CODE_ALIGN 16 @@ -1078,7 +1458,10 @@ override_options (void) {&k6_cost, 0, 0, 32, 7, 32, 7, 32}, {&athlon_cost, 0, 0, 16, 7, 16, 7, 16}, {&pentium4_cost, 0, 0, 0, 0, 0, 0, 0}, - {&k8_cost, 0, 0, 16, 7, 16, 7, 16} + {&k8_cost, 0, 0, 16, 7, 16, 7, 16}, + {&nocona_cost, 0, 0, 0, 0, 0, 0, 0}, + {&generic32_cost, 0, 0, 16, 7, 16, 7, 16}, + {&generic64_cost, 0, 0, 16, 7, 16, 7, 16} }; static const char * const cpu_names[] = TARGET_CPU_DEFAULT_NAMES; @@ -1119,10 +1502,10 @@ override_options (void) | PTA_MMX | PTA_PREFETCH_SSE}, {"pentium4m", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2 | PTA_MMX | PTA_PREFETCH_SSE}, - {"prescott", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2 | PTA_SSE3 + {"prescott", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 + | PTA_MMX | PTA_PREFETCH_SSE}, + {"nocona", PROCESSOR_NOCONA, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT | PTA_MMX | PTA_PREFETCH_SSE}, - {"nocona", PROCESSOR_PENTIUM4, PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_64BIT - | PTA_MMX | PTA_PREFETCH_SSE}, {"k6", PROCESSOR_K6, PTA_MMX}, {"k6-2", PROCESSOR_K6, PTA_MMX | PTA_3DNOW}, {"k6-3", PROCESSOR_K6, PTA_MMX | PTA_3DNOW}, @@ -1146,16 +1529,31 @@ override_options (void) | PTA_3DNOW_A | PTA_SSE | PTA_SSE2}, {"athlon-fx", PROCESSOR_K8, PTA_MMX | PTA_PREFETCH_SSE | PTA_3DNOW | PTA_64BIT | PTA_3DNOW_A | PTA_SSE | PTA_SSE2}, + {"generic32", PROCESSOR_GENERIC32, 0 /* flags are only used for -march switch. */ }, + {"generic64", PROCESSOR_GENERIC64, PTA_64BIT /* flags are only used for -march switch. */ }, }; int const pta_size = ARRAY_SIZE (processor_alias_table); +#ifdef SUBTARGET_OVERRIDE_OPTIONS + SUBTARGET_OVERRIDE_OPTIONS; +#endif + +#ifdef SUBSUBTARGET_OVERRIDE_OPTIONS + SUBSUBTARGET_OVERRIDE_OPTIONS; +#endif + + /* -fPIC is the default for x86_64. */ + if (TARGET_MACHO && TARGET_64BIT) + flag_pic = 2; + /* Set the default values for switches whose default depends on TARGET_64BIT in case they weren't overwritten by command line options. */ if (TARGET_64BIT) { + /* Mach-O doesn't support omitting the frame pointer for now. */ if (flag_omit_frame_pointer == 2) - flag_omit_frame_pointer = 1; + flag_omit_frame_pointer = (TARGET_MACHO ? 0 : 1); if (flag_asynchronous_unwind_tables == 2) flag_asynchronous_unwind_tables = 1; if (flag_pcc_struct_return == 2) @@ -1171,29 +1569,69 @@ override_options (void) flag_pcc_struct_return = DEFAULT_PCC_STRUCT_RETURN; } -#ifdef SUBTARGET_OVERRIDE_OPTIONS - SUBTARGET_OVERRIDE_OPTIONS; -#endif + /* Need to check -mtune=generic first. */ + if (ix86_tune_string) + { + if (!strcmp (ix86_tune_string, "generic") + || !strcmp (ix86_tune_string, "i686") + /* As special support for cross compilers we read -mtune=native + as -mtune=generic. With native compilers we won't see the + -mtune=native, as it was changed by the driver. */ + || !strcmp (ix86_tune_string, "native")) + { + if (TARGET_64BIT) + ix86_tune_string = "generic64"; + else + ix86_tune_string = "generic32"; + } + else if (!strncmp (ix86_tune_string, "generic", 7)) + error ("bad value (%s) for -mtune= switch", ix86_tune_string); + } + else + { + if (ix86_arch_string) + ix86_tune_string = ix86_arch_string; + if (!ix86_tune_string) + { + ix86_tune_string = cpu_names [TARGET_CPU_DEFAULT]; + ix86_tune_defaulted = 1; + } + + /* ix86_tune_string is set to ix86_arch_string or defaulted. We + need to use a sensible tune option. */ + if (!strcmp (ix86_tune_string, "generic") + || !strcmp (ix86_tune_string, "x86-64") + || !strcmp (ix86_tune_string, "i686")) + { + if (TARGET_64BIT) + ix86_tune_string = "generic64"; + else + ix86_tune_string = "generic32"; + } + } + if (!strcmp (ix86_tune_string, "x86-64")) + warning (OPT_Wdeprecated, "-mtune=x86-64 is deprecated. Use -mtune=k8 or " + "-mtune=generic instead as appropriate."); - if (!ix86_tune_string && ix86_arch_string) - ix86_tune_string = ix86_arch_string; - if (!ix86_tune_string) - ix86_tune_string = cpu_names [TARGET_CPU_DEFAULT]; if (!ix86_arch_string) ix86_arch_string = TARGET_64BIT ? "x86-64" : "i386"; + if (!strcmp (ix86_arch_string, "generic")) + error ("generic CPU can be used only for -mtune= switch"); + if (!strncmp (ix86_arch_string, "generic", 7)) + error ("bad value (%s) for -march= switch", ix86_arch_string); if (ix86_cmodel_string != 0) { if (!strcmp (ix86_cmodel_string, "small")) ix86_cmodel = flag_pic ? CM_SMALL_PIC : CM_SMALL; + else if (!strcmp (ix86_cmodel_string, "medium")) + ix86_cmodel = flag_pic ? CM_MEDIUM_PIC : CM_MEDIUM; else if (flag_pic) sorry ("code model %s not supported in PIC mode", ix86_cmodel_string); else if (!strcmp (ix86_cmodel_string, "32")) ix86_cmodel = CM_32; else if (!strcmp (ix86_cmodel_string, "kernel") && !flag_pic) ix86_cmodel = CM_KERNEL; - else if (!strcmp (ix86_cmodel_string, "medium") && !flag_pic) - ix86_cmodel = CM_MEDIUM; else if (!strcmp (ix86_cmodel_string, "large") && !flag_pic) ix86_cmodel = CM_LARGE; else @@ -1207,7 +1645,8 @@ override_options (void) } if (ix86_asm_string != 0) { - if (!strcmp (ix86_asm_string, "intel")) + if (! TARGET_MACHO + && !strcmp (ix86_asm_string, "intel")) ix86_asm_dialect = ASM_INTEL; else if (!strcmp (ix86_asm_string, "att")) ix86_asm_dialect = ASM_ATT; @@ -1215,10 +1654,10 @@ override_options (void) error ("bad value (%s) for -masm= switch", ix86_asm_string); } if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32)) - error ("code model `%s' not supported in the %s bit mode", + error ("code model %qs not supported in the %s bit mode", ix86_cmodel_string, TARGET_64BIT ? "64" : "32"); if (ix86_cmodel == CM_LARGE) - sorry ("code model `large' not supported yet"); + sorry ("code model %<large%> not supported yet"); if ((TARGET_64BIT != 0) != ((target_flags & MASK_64BIT) != 0)) sorry ("%i-bit mode not compiled in", (target_flags & MASK_64BIT) ? 64 : 32); @@ -1250,7 +1689,8 @@ override_options (void) if (processor_alias_table[i].flags & PTA_PREFETCH_SSE) x86_prefetch_sse = true; if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT)) - error ("CPU you selected does not support x86-64 instruction set"); + error ("CPU you selected does not support x86-64 " + "instruction set"); break; } @@ -1262,9 +1702,21 @@ override_options (void) { ix86_tune = processor_alias_table[i].processor; if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT)) - error ("CPU you selected does not support x86-64 instruction set"); - - /* Intel CPUs have always interpreted SSE prefetch instructions as + { + if (ix86_tune_defaulted) + { + ix86_tune_string = "x86-64"; + for (i = 0; i < pta_size; i++) + if (! strcmp (ix86_tune_string, + processor_alias_table[i].name)) + break; + ix86_tune = processor_alias_table[i].processor; + } + else + error ("CPU you selected does not support x86-64 " + "instruction set"); + } + /* Intel CPUs have always interpreted SSE prefetch instructions as NOPs; so, we can enable SSE prefetch instructions even when -mtune (rather than -march) points us to a processor that has them. However, the VIA C3 gives a SIGILL, so we only do that for i686 and @@ -1304,7 +1756,7 @@ override_options (void) Remove this code in GCC 3.2 or later. */ if (ix86_align_loops_string) { - warning ("-malign-loops is obsolete, use -falign-loops"); + warning (0, "-malign-loops is obsolete, use -falign-loops"); if (align_loops == 0) { i = atoi (ix86_align_loops_string); @@ -1317,7 +1769,7 @@ override_options (void) if (ix86_align_jumps_string) { - warning ("-malign-jumps is obsolete, use -falign-jumps"); + warning (0, "-malign-jumps is obsolete, use -falign-jumps"); if (align_jumps == 0) { i = atoi (ix86_align_jumps_string); @@ -1330,7 +1782,7 @@ override_options (void) if (ix86_align_funcs_string) { - warning ("-malign-functions is obsolete, use -falign-functions"); + warning (0, "-malign-functions is obsolete, use -falign-functions"); if (align_functions == 0) { i = atoi (ix86_align_funcs_string); @@ -1357,25 +1809,8 @@ override_options (void) align_functions = processor_target_table[ix86_tune].align_func; } - /* Validate -mpreferred-stack-boundary= value, or provide default. - The default of 128 bits is for Pentium III's SSE __m128, but we - don't want additional code to keep the stack aligned when - optimizing for code size. */ - ix86_preferred_stack_boundary = (optimize_size - ? TARGET_64BIT ? 128 : 32 - : 128); - if (ix86_preferred_stack_boundary_string) - { - i = atoi (ix86_preferred_stack_boundary_string); - if (i < (TARGET_64BIT ? 4 : 2) || i > 12) - error ("-mpreferred-stack-boundary=%d is not between %d and 12", i, - TARGET_64BIT ? 4 : 2); - else - ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT; - } - /* Validate -mbranch-cost= value, or provide default. */ - ix86_branch_cost = processor_target_table[ix86_tune].cost->branch_cost; + ix86_branch_cost = ix86_cost->branch_cost; if (ix86_branch_cost_string) { i = atoi (ix86_branch_cost_string); @@ -1384,11 +1819,21 @@ override_options (void) else ix86_branch_cost = i; } + if (ix86_section_threshold_string) + { + i = atoi (ix86_section_threshold_string); + if (i < 0) + error ("-mlarge-data-threshold=%d is negative", i); + else + ix86_section_threshold = i; + } if (ix86_tls_dialect_string) { if (strcmp (ix86_tls_dialect_string, "gnu") == 0) ix86_tls_dialect = TLS_DIALECT_GNU; + else if (strcmp (ix86_tls_dialect_string, "gnu2") == 0) + ix86_tls_dialect = TLS_DIALECT_GNU2; else if (strcmp (ix86_tls_dialect_string, "sun") == 0) ix86_tls_dialect = TLS_DIALECT_SUN; else @@ -1397,12 +1842,14 @@ override_options (void) } /* Keep nonleaf frame pointers. */ - if (TARGET_OMIT_LEAF_FRAME_POINTER) + if (flag_omit_frame_pointer) + target_flags &= ~MASK_OMIT_LEAF_FRAME_POINTER; + else if (TARGET_OMIT_LEAF_FRAME_POINTER) flag_omit_frame_pointer = 1; /* If we're doing fast math, we don't care about comparison order wrt NaNs. This lets us use a shorter comparison sequence. */ - if (flag_unsafe_math_optimizations) + if (flag_finite_math_only) target_flags &= ~MASK_IEEE_FP; /* If the architecture always has an FPU, turn off NO_FANCY_MATH_387, @@ -1410,6 +1857,11 @@ override_options (void) if (x86_arch_always_fancy_math_387 & (1 << ix86_arch)) target_flags &= ~MASK_NO_FANCY_MATH_387; + /* Likewise, if the target doesn't have a 387, or we've specified + software floating point, don't use 387 inline intrinsics. */ + if (!TARGET_80387) + target_flags |= MASK_NO_FANCY_MATH_387; + /* Turn on SSE2 builtins for -msse3. */ if (TARGET_SSE3) target_flags |= MASK_SSE2; @@ -1418,25 +1870,61 @@ override_options (void) if (TARGET_SSE2) target_flags |= MASK_SSE; + /* Turn on MMX builtins for -msse. */ + if (TARGET_SSE) + { + target_flags |= MASK_MMX & ~target_flags_explicit; + x86_prefetch_sse = true; + } + + /* Turn on MMX builtins for 3Dnow. */ + if (TARGET_3DNOW) + target_flags |= MASK_MMX; + if (TARGET_64BIT) { if (TARGET_ALIGN_DOUBLE) error ("-malign-double makes no sense in the 64bit mode"); if (TARGET_RTD) error ("-mrtd calling convention not supported in the 64bit mode"); - /* Enable by default the SSE and MMX builtins. */ - target_flags |= (MASK_SSE2 | MASK_SSE | MASK_MMX | MASK_128BIT_LONG_DOUBLE); - ix86_fpmath = FPMATH_SSE; + + /* Enable by default the SSE and MMX builtins. Do allow the user to + explicitly disable any of these. In particular, disabling SSE and + MMX for kernel code is extremely useful. */ + target_flags + |= ((MASK_SSE2 | MASK_SSE | MASK_MMX | MASK_128BIT_LONG_DOUBLE) + & ~target_flags_explicit); } else { - ix86_fpmath = FPMATH_387; /* i386 ABI does not specify red zone. It still makes sense to use it when programmer takes care to stack from being destroyed. */ if (!(target_flags_explicit & MASK_NO_RED_ZONE)) target_flags |= MASK_NO_RED_ZONE; } + /* Validate -mpreferred-stack-boundary= value, or provide default. + The default of 128 bits is for Pentium III's SSE __m128. We can't + change it because of optimize_size. Otherwise, we can't mix object + files compiled with -Os and -On. */ + ix86_preferred_stack_boundary = 128; + if (ix86_preferred_stack_boundary_string) + { + i = atoi (ix86_preferred_stack_boundary_string); + if (i < (TARGET_64BIT ? 4 : 2) || i > 12) + error ("-mpreferred-stack-boundary=%d is not between %d and 12", i, + TARGET_64BIT ? 4 : 2); + else + ix86_preferred_stack_boundary = (1 << i) * BITS_PER_UNIT; + } + + /* Accept -msseregparm only if at least SSE support is enabled. */ + if (TARGET_SSEREGPARM + && ! TARGET_SSE) + error ("-msseregparm used without SSE enabled"); + + ix86_fpmath = TARGET_FPMATH_DEFAULT; + if (ix86_fpmath_string != 0) { if (! strcmp (ix86_fpmath_string, "387")) @@ -1445,7 +1933,7 @@ override_options (void) { if (!TARGET_SSE) { - warning ("SSE instruction set disabled, using 387 arithmetics"); + warning (0, "SSE instruction set disabled, using 387 arithmetics"); ix86_fpmath = FPMATH_387; } else @@ -1456,12 +1944,12 @@ override_options (void) { if (!TARGET_SSE) { - warning ("SSE instruction set disabled, using 387 arithmetics"); + warning (0, "SSE instruction set disabled, using 387 arithmetics"); ix86_fpmath = FPMATH_387; } else if (!TARGET_80387) { - warning ("387 instruction set disabled, using SSE arithmetics"); + warning (0, "387 instruction set disabled, using SSE arithmetics"); ix86_fpmath = FPMATH_SSE; } else @@ -1471,28 +1959,30 @@ override_options (void) error ("bad value (%s) for -mfpmath= switch", ix86_fpmath_string); } - /* It makes no sense to ask for just SSE builtins, so MMX is also turned - on by -msse. */ - if (TARGET_SSE) - { - target_flags |= MASK_MMX; - x86_prefetch_sse = true; - } + /* If the i387 is disabled, then do not return values in it. */ + if (!TARGET_80387) + target_flags &= ~MASK_FLOAT_RETURNS; - /* If it has 3DNow! it also has MMX so MMX is also turned on by -m3dnow */ - if (TARGET_3DNOW) - { - target_flags |= MASK_MMX; - /* If we are targeting the Athlon architecture, enable the 3Dnow/MMX - extensions it adds. */ - if (x86_3dnow_a & (1 << ix86_arch)) - target_flags |= MASK_3DNOW_A; - } if ((x86_accumulate_outgoing_args & TUNEMASK) && !(target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS) && !optimize_size) target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS; + /* ??? Unwind info is not correct around the CFG unless either a frame + pointer is present or M_A_O_A is set. Fixing this requires rewriting + unwind info generation to be aware of the CFG and propagating states + around edges. */ + if ((flag_unwind_tables || flag_asynchronous_unwind_tables + || flag_exceptions || flag_non_call_exceptions) + && flag_omit_frame_pointer + && !(target_flags & MASK_ACCUMULATE_OUTGOING_ARGS)) + { + if (target_flags_explicit & MASK_ACCUMULATE_OUTGOING_ARGS) + warning (0, "unwind tables currently require either a frame pointer " + "or -maccumulate-outgoing-args for correctness"); + target_flags |= MASK_ACCUMULATE_OUTGOING_ARGS; + } + /* Figure out what ASM_GENERATE_INTERNAL_LABEL builds as a prefix. */ { char *p; @@ -1501,7 +1991,190 @@ override_options (void) internal_label_prefix_len = p - internal_label_prefix; *p = '\0'; } + + /* When scheduling description is not available, disable scheduler pass + so it won't slow down the compilation and make x87 code slower. */ + if (!TARGET_SCHEDULE) + flag_schedule_insns_after_reload = flag_schedule_insns = 0; +} + +/* switch to the appropriate section for output of DECL. + DECL is either a `VAR_DECL' node or a constant of some sort. + RELOC indicates whether forming the initial value of DECL requires + link-time relocations. */ + +static section * +x86_64_elf_select_section (tree decl, int reloc, + unsigned HOST_WIDE_INT align) +{ + if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC) + && ix86_in_large_data_p (decl)) + { + const char *sname = NULL; + unsigned int flags = SECTION_WRITE; + switch (categorize_decl_for_section (decl, reloc)) + { + case SECCAT_DATA: + sname = ".ldata"; + break; + case SECCAT_DATA_REL: + sname = ".ldata.rel"; + break; + case SECCAT_DATA_REL_LOCAL: + sname = ".ldata.rel.local"; + break; + case SECCAT_DATA_REL_RO: + sname = ".ldata.rel.ro"; + break; + case SECCAT_DATA_REL_RO_LOCAL: + sname = ".ldata.rel.ro.local"; + break; + case SECCAT_BSS: + sname = ".lbss"; + flags |= SECTION_BSS; + break; + case SECCAT_RODATA: + case SECCAT_RODATA_MERGE_STR: + case SECCAT_RODATA_MERGE_STR_INIT: + case SECCAT_RODATA_MERGE_CONST: + sname = ".lrodata"; + flags = 0; + break; + case SECCAT_SRODATA: + case SECCAT_SDATA: + case SECCAT_SBSS: + gcc_unreachable (); + case SECCAT_TEXT: + case SECCAT_TDATA: + case SECCAT_TBSS: + /* We don't split these for medium model. Place them into + default sections and hope for best. */ + break; + } + if (sname) + { + /* We might get called with string constants, but get_named_section + doesn't like them as they are not DECLs. Also, we need to set + flags in that case. */ + if (!DECL_P (decl)) + return get_section (sname, flags, NULL); + return get_named_section (decl, sname, reloc); + } + } + return default_elf_select_section (decl, reloc, align); +} + +/* Build up a unique section name, expressed as a + STRING_CST node, and assign it to DECL_SECTION_NAME (decl). + RELOC indicates whether the initial value of EXP requires + link-time relocations. */ + +static void +x86_64_elf_unique_section (tree decl, int reloc) +{ + if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC) + && ix86_in_large_data_p (decl)) + { + const char *prefix = NULL; + /* We only need to use .gnu.linkonce if we don't have COMDAT groups. */ + bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP; + + switch (categorize_decl_for_section (decl, reloc)) + { + case SECCAT_DATA: + case SECCAT_DATA_REL: + case SECCAT_DATA_REL_LOCAL: + case SECCAT_DATA_REL_RO: + case SECCAT_DATA_REL_RO_LOCAL: + prefix = one_only ? ".gnu.linkonce.ld." : ".ldata."; + break; + case SECCAT_BSS: + prefix = one_only ? ".gnu.linkonce.lb." : ".lbss."; + break; + case SECCAT_RODATA: + case SECCAT_RODATA_MERGE_STR: + case SECCAT_RODATA_MERGE_STR_INIT: + case SECCAT_RODATA_MERGE_CONST: + prefix = one_only ? ".gnu.linkonce.lr." : ".lrodata."; + break; + case SECCAT_SRODATA: + case SECCAT_SDATA: + case SECCAT_SBSS: + gcc_unreachable (); + case SECCAT_TEXT: + case SECCAT_TDATA: + case SECCAT_TBSS: + /* We don't split these for medium model. Place them into + default sections and hope for best. */ + break; + } + if (prefix) + { + const char *name; + size_t nlen, plen; + char *string; + plen = strlen (prefix); + + name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); + name = targetm.strip_name_encoding (name); + nlen = strlen (name); + + string = alloca (nlen + plen + 1); + memcpy (string, prefix, plen); + memcpy (string + plen, name, nlen + 1); + + DECL_SECTION_NAME (decl) = build_string (nlen + plen, string); + return; + } + } + default_unique_section (decl, reloc); +} + +#ifdef COMMON_ASM_OP +/* This says how to output assembler code to declare an + uninitialized external linkage data object. + + For medium model x86-64 we need to use .largecomm opcode for + large objects. */ +void +x86_elf_aligned_common (FILE *file, + const char *name, unsigned HOST_WIDE_INT size, + int align) +{ + if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC) + && size > (unsigned int)ix86_section_threshold) + fprintf (file, ".largecomm\t"); + else + fprintf (file, "%s", COMMON_ASM_OP); + assemble_name (file, name); + fprintf (file, ","HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", + size, align / BITS_PER_UNIT); +} + +/* Utility function for targets to use in implementing + ASM_OUTPUT_ALIGNED_BSS. */ + +void +x86_output_aligned_bss (FILE *file, tree decl ATTRIBUTE_UNUSED, + const char *name, unsigned HOST_WIDE_INT size, + int align) +{ + if ((ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_MEDIUM_PIC) + && size > (unsigned int)ix86_section_threshold) + switch_to_section (get_named_section (decl, ".lbss", 0)); + else + switch_to_section (bss_section); + ASM_OUTPUT_ALIGN (file, floor_log2 (align / BITS_PER_UNIT)); +#ifdef ASM_DECLARE_OBJECT_NAME + last_assemble_variable_decl = decl; + ASM_DECLARE_OBJECT_NAME (file, name, decl); +#else + /* Standard thing is just output label for the object. */ + ASM_OUTPUT_LABEL (file, name); +#endif /* ASM_DECLARE_OBJECT_NAME */ + ASM_OUTPUT_SKIP (file, size ? size : 1); } +#endif void optimization_options (int level, int size ATTRIBUTE_UNUSED) @@ -1513,6 +2186,11 @@ optimization_options (int level, int size ATTRIBUTE_UNUSED) flag_schedule_insns = 0; #endif + if (TARGET_MACHO) + /* The Darwin libraries never set errno, so we might as well + avoid calling them when that's the only reason we would. */ + flag_errno_math = 0; + /* The default values of these switches depend on the TARGET_64BIT that is not known at this moment. Mark these values with 2 and let user the to override these. In case there is no command line option @@ -1521,6 +2199,9 @@ optimization_options (int level, int size ATTRIBUTE_UNUSED) flag_omit_frame_pointer = 2; flag_pcc_struct_return = 2; flag_asynchronous_unwind_tables = 2; +#ifdef SUBTARGET_OPTIMIZATION_OPTIONS + SUBTARGET_OPTIMIZATION_OPTIONS; +#endif } /* Table of valid machine attributes. */ @@ -1529,22 +2210,31 @@ const struct attribute_spec ix86_attribute_table[] = /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ /* Stdcall attribute says callee is responsible for popping arguments if they are not variable. */ - { "stdcall", 0, 0, false, true, true, ix86_handle_cdecl_attribute }, + { "stdcall", 0, 0, false, true, true, ix86_handle_cconv_attribute }, /* Fastcall attribute says callee is responsible for popping arguments if they are not variable. */ - { "fastcall", 0, 0, false, true, true, ix86_handle_cdecl_attribute }, + { "fastcall", 0, 0, false, true, true, ix86_handle_cconv_attribute }, /* Cdecl attribute says the callee is a normal C declaration */ - { "cdecl", 0, 0, false, true, true, ix86_handle_cdecl_attribute }, + { "cdecl", 0, 0, false, true, true, ix86_handle_cconv_attribute }, /* Regparm attribute specifies how many integer arguments are to be passed in registers. */ - { "regparm", 1, 1, false, true, true, ix86_handle_regparm_attribute }, -#ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES - { "dllimport", 0, 0, false, false, false, ix86_handle_dll_attribute }, - { "dllexport", 0, 0, false, false, false, ix86_handle_dll_attribute }, + { "regparm", 1, 1, false, true, true, ix86_handle_cconv_attribute }, + /* Sseregparm attribute says we are using x86_64 calling conventions + for FP arguments. */ + { "sseregparm", 0, 0, false, true, true, ix86_handle_cconv_attribute }, + /* force_align_arg_pointer says this function realigns the stack at entry. */ + { (const char *)&ix86_force_align_arg_pointer_string, 0, 0, + false, true, true, ix86_handle_cconv_attribute }, +#if TARGET_DLLIMPORT_DECL_ATTRIBUTES + { "dllimport", 0, 0, false, false, false, handle_dll_attribute }, + { "dllexport", 0, 0, false, false, false, handle_dll_attribute }, { "shared", 0, 0, true, false, false, ix86_handle_shared_attribute }, #endif { "ms_struct", 0, 0, false, false, false, ix86_handle_struct_attribute }, { "gcc_struct", 0, 0, false, false, false, ix86_handle_struct_attribute }, +#ifdef SUBTARGET_ATTRIBUTE_TABLE + SUBTARGET_ATTRIBUTE_TABLE, +#endif { NULL, 0, 0, false, false, false, NULL } }; @@ -1555,19 +2245,44 @@ const struct attribute_spec ix86_attribute_table[] = static bool ix86_function_ok_for_sibcall (tree decl, tree exp) { + tree func; + rtx a, b; + /* If we are generating position-independent code, we cannot sibcall optimize any indirect call, or a direct call to a global function, as the PLT requires %ebx be live. */ - if (!TARGET_64BIT && flag_pic && (!decl || TREE_PUBLIC (decl))) + if (!TARGET_64BIT && flag_pic && (!decl || !targetm.binds_local_p (decl))) return false; - /* If we are returning floats on the 80387 register stack, we cannot + if (decl) + func = decl; + else + { + func = TREE_TYPE (TREE_OPERAND (exp, 0)); + if (POINTER_TYPE_P (func)) + func = TREE_TYPE (func); + } + + /* Check that the return value locations are the same. Like + if we are returning floats on the 80387 register stack, we cannot make a sibcall from a function that doesn't return a float to a function that does or, conversely, from a function that does return a float to a function that doesn't; the necessary stack adjustment - would not be executed. */ - if (STACK_REG_P (ix86_function_value (TREE_TYPE (exp))) - != STACK_REG_P (ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl))))) + would not be executed. This is also the place we notice + differences in the return value ABI. Note that it is ok for one + of the functions to have void return type as long as the return + value of the other is passed in a register. */ + a = ix86_function_value (TREE_TYPE (exp), func, false); + b = ix86_function_value (TREE_TYPE (DECL_RESULT (cfun->decl)), + cfun->decl, false); + if (STACK_REG_P (a) || STACK_REG_P (b)) + { + if (!rtx_equal_p (a, b)) + return false; + } + else if (VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl)))) + ; + else if (!rtx_equal_p (a, b)) return false; /* If this call is indirect, we'll need to be able to use a call-clobbered @@ -1590,96 +2305,134 @@ ix86_function_ok_for_sibcall (tree decl, tree exp) } } +#if TARGET_DLLIMPORT_DECL_ATTRIBUTES + /* Dllimport'd functions are also called indirectly. */ + if (decl && DECL_DLLIMPORT_P (decl) + && ix86_function_regparm (TREE_TYPE (decl), NULL) >= 3) + return false; +#endif + + /* If we forced aligned the stack, then sibcalling would unalign the + stack, which may break the called function. */ + if (cfun->machine->force_align_arg_pointer) + return false; + /* Otherwise okay. That also includes certain types of indirect calls. */ return true; } -/* Handle a "cdecl", "stdcall", or "fastcall" attribute; +/* Handle "cdecl", "stdcall", "fastcall", "regparm" and "sseregparm" + calling convention attributes; arguments as in struct attribute_spec.handler. */ -static tree -ix86_handle_cdecl_attribute (tree *node, tree name, - tree args ATTRIBUTE_UNUSED, - int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) -{ - if (TREE_CODE (*node) != FUNCTION_TYPE - && TREE_CODE (*node) != METHOD_TYPE - && TREE_CODE (*node) != FIELD_DECL - && TREE_CODE (*node) != TYPE_DECL) - { - warning ("`%s' attribute only applies to functions", - IDENTIFIER_POINTER (name)); - *no_add_attrs = true; - } - else - { - if (is_attribute_p ("fastcall", name)) - { - if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node))) - { - error ("fastcall and stdcall attributes are not compatible"); - } - else if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node))) - { - error ("fastcall and regparm attributes are not compatible"); - } - } - else if (is_attribute_p ("stdcall", name)) - { - if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node))) - { - error ("fastcall and stdcall attributes are not compatible"); - } - } - } - - if (TARGET_64BIT) - { - warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name)); - *no_add_attrs = true; - } - return NULL_TREE; -} - -/* Handle a "regparm" attribute; - arguments as in struct attribute_spec.handler. */ static tree -ix86_handle_regparm_attribute (tree *node, tree name, tree args, - int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) +ix86_handle_cconv_attribute (tree *node, tree name, + tree args, + int flags ATTRIBUTE_UNUSED, + bool *no_add_attrs) { if (TREE_CODE (*node) != FUNCTION_TYPE && TREE_CODE (*node) != METHOD_TYPE && TREE_CODE (*node) != FIELD_DECL && TREE_CODE (*node) != TYPE_DECL) { - warning ("`%s' attribute only applies to functions", + warning (OPT_Wattributes, "%qs attribute only applies to functions", IDENTIFIER_POINTER (name)); *no_add_attrs = true; + return NULL_TREE; } - else + + /* Can combine regparm with all attributes but fastcall. */ + if (is_attribute_p ("regparm", name)) { tree cst; + if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node))) + { + error ("fastcall and regparm attributes are not compatible"); + } + cst = TREE_VALUE (args); if (TREE_CODE (cst) != INTEGER_CST) { - warning ("`%s' attribute requires an integer constant argument", + warning (OPT_Wattributes, + "%qs attribute requires an integer constant argument", IDENTIFIER_POINTER (name)); *no_add_attrs = true; } else if (compare_tree_int (cst, REGPARM_MAX) > 0) { - warning ("argument to `%s' attribute larger than %d", + warning (OPT_Wattributes, "argument to %qs attribute larger than %d", IDENTIFIER_POINTER (name), REGPARM_MAX); *no_add_attrs = true; } - if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node))) + if (!TARGET_64BIT + && lookup_attribute (ix86_force_align_arg_pointer_string, + TYPE_ATTRIBUTES (*node)) + && compare_tree_int (cst, REGPARM_MAX-1)) { + error ("%s functions limited to %d register parameters", + ix86_force_align_arg_pointer_string, REGPARM_MAX-1); + } + + return NULL_TREE; + } + + if (TARGET_64BIT) + { + warning (OPT_Wattributes, "%qs attribute ignored", + IDENTIFIER_POINTER (name)); + *no_add_attrs = true; + return NULL_TREE; + } + + /* Can combine fastcall with stdcall (redundant) and sseregparm. */ + if (is_attribute_p ("fastcall", name)) + { + if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node))) + { + error ("fastcall and cdecl attributes are not compatible"); + } + if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node))) + { + error ("fastcall and stdcall attributes are not compatible"); + } + if (lookup_attribute ("regparm", TYPE_ATTRIBUTES (*node))) + { error ("fastcall and regparm attributes are not compatible"); } } + /* Can combine stdcall with fastcall (redundant), regparm and + sseregparm. */ + else if (is_attribute_p ("stdcall", name)) + { + if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (*node))) + { + error ("stdcall and cdecl attributes are not compatible"); + } + if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node))) + { + error ("stdcall and fastcall attributes are not compatible"); + } + } + + /* Can combine cdecl with regparm and sseregparm. */ + else if (is_attribute_p ("cdecl", name)) + { + if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (*node))) + { + error ("stdcall and cdecl attributes are not compatible"); + } + if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (*node))) + { + error ("fastcall and cdecl attributes are not compatible"); + } + } + + /* Can combine sseregparm with all attributes. */ + return NULL_TREE; } @@ -1696,22 +2449,27 @@ ix86_comp_type_attributes (tree type1, tree type2) if (TREE_CODE (type1) != FUNCTION_TYPE) return 1; - /* Check for mismatched fastcall types */ - if (!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1)) - != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2))) + /* Check for mismatched fastcall/regparm types. */ + if ((!lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type1)) + != !lookup_attribute ("fastcall", TYPE_ATTRIBUTES (type2))) + || (ix86_function_regparm (type1, NULL) + != ix86_function_regparm (type2, NULL))) + return 0; + + /* Check for mismatched sseregparm types. */ + if (!lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type1)) + != !lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type2))) return 0; /* Check for mismatched return types (cdecl vs stdcall). */ if (!lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type1)) != !lookup_attribute (rtdstr, TYPE_ATTRIBUTES (type2))) return 0; - if (ix86_function_regparm (type1, NULL) - != ix86_function_regparm (type2, NULL)) - return 0; + return 1; } -/* Return the regparm value for a fuctio with the indicated TYPE and DECL. +/* Return the regparm value for a function with the indicated TYPE and DECL. DECL may be NULL when calling function indirectly or considering a libcall. */ @@ -1744,19 +2502,91 @@ ix86_function_regparm (tree type, tree decl) struct cgraph_local_info *i = cgraph_local_info (decl); if (i && i->local) { + int local_regparm, globals = 0, regno; + + /* Make sure no regparm register is taken by a global register + variable. */ + for (local_regparm = 0; local_regparm < 3; local_regparm++) + if (global_regs[local_regparm]) + break; /* We can't use regparm(3) for nested functions as these use static chain pointer in third argument. */ - if (DECL_CONTEXT (decl) && !DECL_NO_STATIC_CHAIN (decl)) - regparm = 2; - else - regparm = 3; + if (local_regparm == 3 + && decl_function_context (decl) + && !DECL_NO_STATIC_CHAIN (decl)) + local_regparm = 2; + /* If the function realigns its stackpointer, the + prologue will clobber %ecx. If we've already + generated code for the callee, the callee + DECL_STRUCT_FUNCTION is gone, so we fall back to + scanning the attributes for the self-realigning + property. */ + if ((DECL_STRUCT_FUNCTION (decl) + && DECL_STRUCT_FUNCTION (decl)->machine->force_align_arg_pointer) + || (!DECL_STRUCT_FUNCTION (decl) + && lookup_attribute (ix86_force_align_arg_pointer_string, + TYPE_ATTRIBUTES (TREE_TYPE (decl))))) + local_regparm = 2; + /* Each global register variable increases register preassure, + so the more global reg vars there are, the smaller regparm + optimization use, unless requested by the user explicitly. */ + for (regno = 0; regno < 6; regno++) + if (global_regs[regno]) + globals++; + local_regparm + = globals < local_regparm ? local_regparm - globals : 0; + + if (local_regparm > regparm) + regparm = local_regparm; } } } return regparm; } -/* Return true if EAX is live at the start of the function. Used by +/* Return 1 or 2, if we can pass up to SSE_REGPARM_MAX SFmode (1) and + DFmode (2) arguments in SSE registers for a function with the + indicated TYPE and DECL. DECL may be NULL when calling function + indirectly or considering a libcall. Otherwise return 0. */ + +static int +ix86_function_sseregparm (tree type, tree decl) +{ + /* Use SSE registers to pass SFmode and DFmode arguments if requested + by the sseregparm attribute. */ + if (TARGET_SSEREGPARM + || (type + && lookup_attribute ("sseregparm", TYPE_ATTRIBUTES (type)))) + { + if (!TARGET_SSE) + { + if (decl) + error ("Calling %qD with attribute sseregparm without " + "SSE/SSE2 enabled", decl); + else + error ("Calling %qT with attribute sseregparm without " + "SSE/SSE2 enabled", type); + return 0; + } + + return 2; + } + + /* For local functions, pass up to SSE_REGPARM_MAX SFmode + (and DFmode for SSE2) arguments in SSE registers, + even for 32-bit targets. */ + if (!TARGET_64BIT && decl + && TARGET_SSE_MATH && flag_unit_at_a_time && !profile_flag) + { + struct cgraph_local_info *i = cgraph_local_info (decl); + if (i && i->local) + return TARGET_SSE2 ? 2 : 1; + } + + return 0; +} + +/* Return true if EAX is live at the start of the function. Used by ix86_expand_prologue to determine if we need special help before calling allocate_stack_worker. */ @@ -1769,7 +2599,7 @@ ix86_eax_live_at_start_p (void) to correct at this point. This gives false positives for broken functions that might use uninitialized data that happens to be allocated in eax, but who cares? */ - return REGNO_REG_SET_P (ENTRY_BLOCK_PTR->global_live_at_end, 0); + return REGNO_REG_SET_P (ENTRY_BLOCK_PTR->il.rtl->global_live_at_end, 0); } /* Value is the number of bytes of arguments automatically @@ -1812,7 +2642,8 @@ ix86_return_pops_args (tree fundecl, tree funtype, int size) /* Lose any fake structure return argument if it is passed on the stack. */ if (aggregate_value_p (TREE_TYPE (funtype), fundecl) - && !TARGET_64BIT) + && !TARGET_64BIT + && !KEEP_AGGREGATE_RETURN_POINTER) { int nregs = ix86_function_regparm (funtype, fundecl); @@ -1831,10 +2662,29 @@ ix86_function_arg_regno_p (int regno) { int i; if (!TARGET_64BIT) - return (regno < REGPARM_MAX - || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno])); - if (SSE_REGNO_P (regno) && TARGET_SSE) - return true; + { + if (TARGET_MACHO) + return (regno < REGPARM_MAX + || (TARGET_SSE && SSE_REGNO_P (regno) && !fixed_regs[regno])); + else + return (regno < REGPARM_MAX + || (TARGET_MMX && MMX_REGNO_P (regno) + && (regno < FIRST_MMX_REG + MMX_REGPARM_MAX)) + || (TARGET_SSE && SSE_REGNO_P (regno) + && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX))); + } + + if (TARGET_MACHO) + { + if (SSE_REGNO_P (regno) && TARGET_SSE) + return true; + } + else + { + if (TARGET_SSE && SSE_REGNO_P (regno) + && (regno < FIRST_SSE_REG + SSE_REGPARM_MAX)) + return true; + } /* RAX is used as hidden argument to va_arg functions. */ if (!regno) return true; @@ -1844,6 +2694,21 @@ ix86_function_arg_regno_p (int regno) return false; } +/* Return if we do not know how to pass TYPE solely in registers. */ + +static bool +ix86_must_pass_in_stack (enum machine_mode mode, tree type) +{ + if (must_pass_in_stack_var_size_or_pad (mode, type)) + return true; + + /* For 32-bit, we want TImode aggregates to go on the stack. But watch out! + The layout_type routine is crafty and tries to trick us into passing + currently unsupported vector types on the stack by using TImode. */ + return (!TARGET_64BIT && mode == TImode + && type && TREE_CODE (type) != VECTOR_TYPE); +} + /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE. For a library call, FNTYPE is 0. */ @@ -1874,17 +2739,17 @@ init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */ *cum = zero_cum; /* Set up the number of registers to use for passing arguments. */ - if (fntype) - cum->nregs = ix86_function_regparm (fntype, fndecl); - else - cum->nregs = ix86_regparm; - cum->sse_nregs = SSE_REGPARM_MAX; - cum->mmx_nregs = MMX_REGPARM_MAX; + cum->nregs = ix86_regparm; + if (TARGET_SSE) + cum->sse_nregs = SSE_REGPARM_MAX; + if (TARGET_MMX) + cum->mmx_nregs = MMX_REGPARM_MAX; cum->warn_sse = true; cum->warn_mmx = true; cum->maybe_vaarg = false; - /* Use ecx and edx registers if function has fastcall attribute */ + /* Use ecx and edx registers if function has fastcall attribute, + else look for regparm information. */ if (fntype && !TARGET_64BIT) { if (lookup_attribute ("fastcall", TYPE_ATTRIBUTES (fntype))) @@ -1892,15 +2757,20 @@ init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */ cum->nregs = 2; cum->fastcall = 1; } + else + cum->nregs = ix86_function_regparm (fntype, fndecl); } + /* Set up the number of SSE registers used for passing SFmode + and DFmode arguments. Warn for mismatching ABI. */ + cum->float_in_sse = ix86_function_sseregparm (fntype, fndecl); /* Determine if this function has variable arguments. This is indicated by the last argument being 'void_type_mode' if there are no variable arguments. If there are variable arguments, then - we won't pass anything in registers */ + we won't pass anything in registers in 32-bit mode. */ - if (cum->nregs || !TARGET_MMX || !TARGET_SSE) + if (cum->nregs || cum->mmx_nregs || cum->sse_nregs) { for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0; param != 0; param = next_param) @@ -1916,6 +2786,7 @@ init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */ cum->warn_sse = 0; cum->warn_mmx = 0; cum->fastcall = 0; + cum->float_in_sse = 0; } cum->maybe_vaarg = true; } @@ -1923,7 +2794,7 @@ init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */ } if ((!fntype && !libname) || (fntype && !TYPE_ARG_TYPES (fntype))) - cum->maybe_vaarg = 1; + cum->maybe_vaarg = true; if (TARGET_DEBUG_ARG) fprintf (stderr, ", nregs=%d )\n", cum->nregs); @@ -1931,6 +2802,71 @@ init_cumulative_args (CUMULATIVE_ARGS *cum, /* Argument info to initialize */ return; } +/* Return the "natural" mode for TYPE. In most cases, this is just TYPE_MODE. + But in the case of vector types, it is some vector mode. + + When we have only some of our vector isa extensions enabled, then there + are some modes for which vector_mode_supported_p is false. For these + modes, the generic vector support in gcc will choose some non-vector mode + in order to implement the type. By computing the natural mode, we'll + select the proper ABI location for the operand and not depend on whatever + the middle-end decides to do with these vector types. */ + +static enum machine_mode +type_natural_mode (tree type) +{ + enum machine_mode mode = TYPE_MODE (type); + + if (TREE_CODE (type) == VECTOR_TYPE && !VECTOR_MODE_P (mode)) + { + HOST_WIDE_INT size = int_size_in_bytes (type); + if ((size == 8 || size == 16) + /* ??? Generic code allows us to create width 1 vectors. Ignore. */ + && TYPE_VECTOR_SUBPARTS (type) > 1) + { + enum machine_mode innermode = TYPE_MODE (TREE_TYPE (type)); + + if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE) + mode = MIN_MODE_VECTOR_FLOAT; + else + mode = MIN_MODE_VECTOR_INT; + + /* Get the mode which has this inner mode and number of units. */ + for (; mode != VOIDmode; mode = GET_MODE_WIDER_MODE (mode)) + if (GET_MODE_NUNITS (mode) == TYPE_VECTOR_SUBPARTS (type) + && GET_MODE_INNER (mode) == innermode) + return mode; + + gcc_unreachable (); + } + } + + return mode; +} + +/* We want to pass a value in REGNO whose "natural" mode is MODE. However, + this may not agree with the mode that the type system has chosen for the + register, which is ORIG_MODE. If ORIG_MODE is not BLKmode, then we can + go ahead and use it. Otherwise we have to build a PARALLEL instead. */ + +static rtx +gen_reg_or_parallel (enum machine_mode mode, enum machine_mode orig_mode, + unsigned int regno) +{ + rtx tmp; + + if (orig_mode != BLKmode) + tmp = gen_rtx_REG (orig_mode, regno); + else + { + tmp = gen_rtx_REG (mode, regno); + tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx); + tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp)); + } + + return tmp; +} + /* x86-64 register passing implementation. See x86-64 ABI for details. Goal of this code is to classify each 8bytes of incoming argument by the register class and assign registers accordingly. */ @@ -1964,9 +2900,14 @@ merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2) || class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS) return X86_64_INTEGER_CLASS; - /* Rule #5: If one of the classes is X87 or X87UP class, MEMORY is used. */ - if (class1 == X86_64_X87_CLASS || class1 == X86_64_X87UP_CLASS - || class2 == X86_64_X87_CLASS || class2 == X86_64_X87UP_CLASS) + /* Rule #5: If one of the classes is X87, X87UP, or COMPLEX_X87 class, + MEMORY is used. */ + if (class1 == X86_64_X87_CLASS + || class1 == X86_64_X87UP_CLASS + || class1 == X86_64_COMPLEX_X87_CLASS + || class2 == X86_64_X87_CLASS + || class2 == X86_64_X87UP_CLASS + || class2 == X86_64_COMPLEX_X87_CLASS) return X86_64_MEMORY_CLASS; /* Rule #6: Otherwise class SSE is used. */ @@ -1998,7 +2939,7 @@ classify_argument (enum machine_mode mode, tree type, return 0; if (mode != VOIDmode - && MUST_PASS_IN_STACK (mode, type)) + && targetm.calls.must_pass_in_stack (mode, type)) return 0; if (type && AGGREGATE_TYPE_P (type)) @@ -2023,21 +2964,21 @@ classify_argument (enum machine_mode mode, tree type, } /* Classify each field of record and merge classes. */ - if (TREE_CODE (type) == RECORD_TYPE) + switch (TREE_CODE (type)) { + case RECORD_TYPE: /* For classes first merge in the field of the subclasses. */ - if (TYPE_BINFO (type) != NULL && TYPE_BINFO_BASETYPES (type) != NULL) + if (TYPE_BINFO (type)) { - tree bases = TYPE_BINFO_BASETYPES (type); - int n_bases = TREE_VEC_LENGTH (bases); - int i; + tree binfo, base_binfo; + int basenum; - for (i = 0; i < n_bases; ++i) + for (binfo = TYPE_BINFO (type), basenum = 0; + BINFO_BASE_ITERATE (binfo, basenum, base_binfo); basenum++) { - tree binfo = TREE_VEC_ELT (bases, i); int num; - int offset = tree_low_cst (BINFO_OFFSET (binfo), 0) * 8; - tree type = BINFO_TYPE (binfo); + int offset = tree_low_cst (BINFO_OFFSET (base_binfo), 0) * 8; + tree type = BINFO_TYPE (base_binfo); num = classify_argument (TYPE_MODE (type), type, subclasses, @@ -2059,13 +3000,16 @@ classify_argument (enum machine_mode mode, tree type, { int num; + if (TREE_TYPE (field) == error_mark_node) + continue; + /* Bitfields are always classified as integer. Handle them early, since later code would consider them to be misaligned integers. */ if (DECL_BIT_FIELD (field)) { - for (i = int_bit_position (field) / 8 / 8; - i < (int_bit_position (field) + for (i = (int_bit_position (field) + (bit_offset % 64)) / 8 / 8; + i < ((int_bit_position (field) + (bit_offset % 64)) + tree_low_cst (DECL_SIZE (field), 0) + 63) / 8 / 8; i++) classes[i] = @@ -2090,61 +3034,45 @@ classify_argument (enum machine_mode mode, tree type, } } } - } - /* Arrays are handled as small records. */ - else if (TREE_CODE (type) == ARRAY_TYPE) - { - int num; - num = classify_argument (TYPE_MODE (TREE_TYPE (type)), - TREE_TYPE (type), subclasses, bit_offset); - if (!num) - return 0; + break; - /* The partial classes are now full classes. */ - if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4) - subclasses[0] = X86_64_SSE_CLASS; - if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4) - subclasses[0] = X86_64_INTEGER_CLASS; + case ARRAY_TYPE: + /* Arrays are handled as small records. */ + { + int num; + num = classify_argument (TYPE_MODE (TREE_TYPE (type)), + TREE_TYPE (type), subclasses, bit_offset); + if (!num) + return 0; - for (i = 0; i < words; i++) - classes[i] = subclasses[i % num]; - } - /* Unions are similar to RECORD_TYPE but offset is always 0. */ - else if (TREE_CODE (type) == UNION_TYPE - || TREE_CODE (type) == QUAL_UNION_TYPE) - { - /* For classes first merge in the field of the subclasses. */ - if (TYPE_BINFO (type) != NULL && TYPE_BINFO_BASETYPES (type) != NULL) - { - tree bases = TYPE_BINFO_BASETYPES (type); - int n_bases = TREE_VEC_LENGTH (bases); - int i; + /* The partial classes are now full classes. */ + if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4) + subclasses[0] = X86_64_SSE_CLASS; + if (subclasses[0] == X86_64_INTEGERSI_CLASS && bytes != 4) + subclasses[0] = X86_64_INTEGER_CLASS; - for (i = 0; i < n_bases; ++i) - { - tree binfo = TREE_VEC_ELT (bases, i); - int num; - int offset = tree_low_cst (BINFO_OFFSET (binfo), 0) * 8; - tree type = BINFO_TYPE (binfo); + for (i = 0; i < words; i++) + classes[i] = subclasses[i % num]; - num = classify_argument (TYPE_MODE (type), - type, subclasses, - (offset + (bit_offset % 64)) % 256); - if (!num) - return 0; - for (i = 0; i < num; i++) - { - int pos = (offset + (bit_offset % 64)) / 8 / 8; - classes[i + pos] = - merge_classes (subclasses[i], classes[i + pos]); - } - } - } + break; + } + case UNION_TYPE: + case QUAL_UNION_TYPE: + /* Unions are similar to RECORD_TYPE but offset is always 0. + */ + + /* Unions are not derived. */ + gcc_assert (!TYPE_BINFO (type) + || !BINFO_N_BASE_BINFOS (TYPE_BINFO (type))); for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) { if (TREE_CODE (field) == FIELD_DECL) { int num; + + if (TREE_TYPE (field) == error_mark_node) + continue; + num = classify_argument (TYPE_MODE (TREE_TYPE (field)), TREE_TYPE (field), subclasses, bit_offset); @@ -2154,34 +3082,11 @@ classify_argument (enum machine_mode mode, tree type, classes[i] = merge_classes (subclasses[i], classes[i]); } } + break; + + default: + gcc_unreachable (); } - else if (TREE_CODE (type) == SET_TYPE) - { - if (bytes <= 4) - { - classes[0] = X86_64_INTEGERSI_CLASS; - return 1; - } - else if (bytes <= 8) - { - classes[0] = X86_64_INTEGER_CLASS; - return 1; - } - else if (bytes <= 12) - { - classes[0] = X86_64_INTEGER_CLASS; - classes[1] = X86_64_INTEGERSI_CLASS; - return 2; - } - else - { - classes[0] = X86_64_INTEGER_CLASS; - classes[1] = X86_64_INTEGER_CLASS; - return 2; - } - } - else - abort (); /* Final merger cleanup. */ for (i = 0; i < words; i++) @@ -2222,9 +3127,22 @@ classify_argument (enum machine_mode mode, tree type, return 0; } + /* for V1xx modes, just use the base mode */ + if (VECTOR_MODE_P (mode) + && GET_MODE_SIZE (GET_MODE_INNER (mode)) == bytes) + mode = GET_MODE_INNER (mode); + /* Classification of atomic types. */ switch (mode) { + case SDmode: + case DDmode: + classes[0] = X86_64_SSE_CLASS; + return 1; + case TDmode: + classes[0] = X86_64_SSE_CLASS; + classes[1] = X86_64_SSEUP_CLASS; + return 2; case DImode: case SImode: case HImode: @@ -2242,9 +3160,7 @@ classify_argument (enum machine_mode mode, tree type, classes[0] = classes[1] = X86_64_INTEGER_CLASS; return 2; case CTImode: - classes[0] = classes[1] = X86_64_INTEGER_CLASS; - classes[2] = classes[3] = X86_64_INTEGER_CLASS; - return 4; + return 0; case SFmode: if (!(bit_offset % 64)) classes[0] = X86_64_SSESF_CLASS; @@ -2259,21 +3175,22 @@ classify_argument (enum machine_mode mode, tree type, classes[1] = X86_64_X87UP_CLASS; return 2; case TFmode: - case TCmode: - return 0; - case XCmode: - classes[0] = X86_64_X87_CLASS; - classes[1] = X86_64_X87UP_CLASS; - classes[2] = X86_64_X87_CLASS; - classes[3] = X86_64_X87UP_CLASS; - return 4; + classes[0] = X86_64_SSE_CLASS; + classes[1] = X86_64_SSEUP_CLASS; + return 2; + case SCmode: + classes[0] = X86_64_SSE_CLASS; + return 1; case DCmode: classes[0] = X86_64_SSEDF_CLASS; classes[1] = X86_64_SSEDF_CLASS; return 2; - case SCmode: - classes[0] = X86_64_SSE_CLASS; + case XCmode: + classes[0] = X86_64_COMPLEX_X87_CLASS; return 1; + case TCmode: + /* This modes is larger than 16 bytes. */ + return 0; case V4SFmode: case V4SImode: case V16QImode: @@ -2287,12 +3204,25 @@ classify_argument (enum machine_mode mode, tree type, case V2SImode: case V4HImode: case V8QImode: - return 0; + classes[0] = X86_64_SSE_CLASS; + return 1; case BLKmode: case VOIDmode: return 0; default: - abort (); + gcc_assert (VECTOR_MODE_P (mode)); + + if (bytes > 16) + return 0; + + gcc_assert (GET_MODE_CLASS (GET_MODE_INNER (mode)) == MODE_INT); + + if (bit_offset + GET_MODE_BITSIZE (mode) <= 32) + classes[0] = X86_64_INTEGERSI_CLASS; + else + classes[0] = X86_64_INTEGER_CLASS; + classes[1] = X86_64_INTEGER_CLASS; + return 1 + (bytes > 8); } } @@ -2329,18 +3259,27 @@ examine_argument (enum machine_mode mode, tree type, int in_return, if (!in_return) return 0; break; + case X86_64_COMPLEX_X87_CLASS: + return in_return ? 2 : 0; case X86_64_MEMORY_CLASS: - abort (); + gcc_unreachable (); } return 1; } + /* Construct container for the argument used by GCC interface. See FUNCTION_ARG for the detailed description. */ + static rtx -construct_container (enum machine_mode mode, tree type, int in_return, - int nintregs, int nsseregs, const int * intreg, - int sse_regno) +construct_container (enum machine_mode mode, enum machine_mode orig_mode, + tree type, int in_return, int nintregs, int nsseregs, + const int *intreg, int sse_regno) { + /* The following variables hold the static issued_error state. */ + static bool issued_sse_arg_error; + static bool issued_sse_ret_error; + static bool issued_x87_ret_error; + enum machine_mode tmpmode; int bytes = (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode); @@ -2369,11 +3308,48 @@ construct_container (enum machine_mode mode, tree type, int in_return, } if (!n) return NULL; - if (!examine_argument (mode, type, in_return, &needed_intregs, &needed_sseregs)) + if (!examine_argument (mode, type, in_return, &needed_intregs, + &needed_sseregs)) return NULL; if (needed_intregs > nintregs || needed_sseregs > nsseregs) return NULL; + /* We allowed the user to turn off SSE for kernel mode. Don't crash if + some less clueful developer tries to use floating-point anyway. */ + if (needed_sseregs && !TARGET_SSE) + { + if (in_return) + { + if (!issued_sse_ret_error) + { + error ("SSE register return with SSE disabled"); + issued_sse_ret_error = true; + } + } + else if (!issued_sse_arg_error) + { + error ("SSE register argument with SSE disabled"); + issued_sse_arg_error = true; + } + return NULL; + } + + /* Likewise, error if the ABI requires us to return values in the + x87 registers and the user specified -mno-80387. */ + if (!TARGET_80387 && in_return) + for (i = 0; i < n; i++) + if (class[i] == X86_64_X87_CLASS + || class[i] == X86_64_X87UP_CLASS + || class[i] == X86_64_COMPLEX_X87_CLASS) + { + if (!issued_x87_ret_error) + { + error ("x87 register return with x87 disabled"); + issued_x87_ret_error = true; + } + return NULL; + } + /* First construct simple cases. Avoid SCmode, since we want to use single register to pass this type. */ if (n == 1 && mode != SCmode) @@ -2385,14 +3361,15 @@ construct_container (enum machine_mode mode, tree type, int in_return, case X86_64_SSE_CLASS: case X86_64_SSESF_CLASS: case X86_64_SSEDF_CLASS: - return gen_rtx_REG (mode, SSE_REGNO (sse_regno)); + return gen_reg_or_parallel (mode, orig_mode, SSE_REGNO (sse_regno)); case X86_64_X87_CLASS: + case X86_64_COMPLEX_X87_CLASS: return gen_rtx_REG (mode, FIRST_STACK_REG); case X86_64_NO_CLASS: /* Zero sized array, struct or class. */ return NULL; default: - abort (); + gcc_unreachable (); } if (n == 2 && class[0] == X86_64_SSE_CLASS && class[1] == X86_64_SSEUP_CLASS && mode != BLKmode) @@ -2405,11 +3382,6 @@ construct_container (enum machine_mode mode, tree type, int in_return, && (mode == CDImode || mode == TImode || mode == TFmode) && intreg[0] + 1 == intreg[1]) return gen_rtx_REG (mode, intreg[0]); - if (n == 4 - && class[0] == X86_64_X87_CLASS && class[1] == X86_64_X87UP_CLASS - && class[2] == X86_64_X87_CLASS && class[3] == X86_64_X87UP_CLASS - && mode != BLKmode) - return gen_rtx_REG (XCmode, FIRST_STACK_REG); /* Otherwise figure out the entries of the PARALLEL. */ for (i = 0; i < n; i++) @@ -2463,9 +3435,14 @@ construct_container (enum machine_mode mode, tree type, int in_return, sse_regno++; break; default: - abort (); + gcc_unreachable (); } } + + /* Empty aligned struct, union or class. */ + if (nexps == 0) + return NULL; + ret = gen_rtx_PARALLEL (mode, rtvec_alloc (nexps)); for (i = 0; i < nexps; i++) XVECEXP (ret, 0, i) = exp [i]; @@ -2477,19 +3454,22 @@ construct_container (enum machine_mode mode, tree type, int in_return, (TYPE is null for libcalls where that information may not be available.) */ void -function_arg_advance (CUMULATIVE_ARGS *cum, /* current arg information */ - enum machine_mode mode, /* current arg mode */ - tree type, /* type of the argument or 0 if lib support */ - int named) /* whether or not the argument was named */ +function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode, + tree type, int named) { int bytes = (mode == BLKmode) ? int_size_in_bytes (type) : (int) GET_MODE_SIZE (mode); int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; + if (type) + mode = type_natural_mode (type); + if (TARGET_DEBUG_ARG) - fprintf (stderr, - "function_adv (sz=%d, wds=%2d, nregs=%d, ssenregs=%d, mode=%s, named=%d)\n\n", - words, cum->words, cum->nregs, cum->sse_nregs, GET_MODE_NAME (mode), named); + fprintf (stderr, "function_adv (sz=%d, wds=%2d, nregs=%d, ssenregs=%d, " + "mode=%s, named=%d)\n\n", + words, cum->words, cum->nregs, cum->sse_nregs, + GET_MODE_NAME (mode), named); + if (TARGET_64BIT) { int int_nregs, sse_nregs; @@ -2507,32 +3487,20 @@ function_arg_advance (CUMULATIVE_ARGS *cum, /* current arg information */ } else { - if (TARGET_SSE && SSE_REG_MODE_P (mode) - && (!type || !AGGREGATE_TYPE_P (type))) - { - cum->sse_words += words; - cum->sse_nregs -= 1; - cum->sse_regno += 1; - if (cum->sse_nregs <= 0) - { - cum->sse_nregs = 0; - cum->sse_regno = 0; - } - } - else if (TARGET_MMX && MMX_REG_MODE_P (mode) - && (!type || !AGGREGATE_TYPE_P (type))) - { - cum->mmx_words += words; - cum->mmx_nregs -= 1; - cum->mmx_regno += 1; - if (cum->mmx_nregs <= 0) - { - cum->mmx_nregs = 0; - cum->mmx_regno = 0; - } - } - else + switch (mode) { + default: + break; + + case BLKmode: + if (bytes < 0) + break; + /* FALLTHRU */ + + case DImode: + case SImode: + case HImode: + case QImode: cum->words += words; cum->nregs -= words; cum->regno += words; @@ -2542,37 +3510,54 @@ function_arg_advance (CUMULATIVE_ARGS *cum, /* current arg information */ cum->nregs = 0; cum->regno = 0; } - } - } - return; -} - -/* A subroutine of function_arg. We want to pass a parameter whose nominal - type is MODE in REGNO. We try to minimize ABI variation, so MODE may not - actually be valid for REGNO with the current ISA. In this case, ALT_MODE - is used instead. It must be the same size as MODE, and must be known to - be valid for REGNO. Finally, ORIG_MODE is the original mode of the - parameter, as seen by the type system. This may be different from MODE - when we're mucking with things minimizing ABI variations. + break; - Returns a REG or a PARALLEL as appropriate. */ + case DFmode: + if (cum->float_in_sse < 2) + break; + case SFmode: + if (cum->float_in_sse < 1) + break; + /* FALLTHRU */ -static rtx -gen_reg_or_parallel (enum machine_mode mode, enum machine_mode alt_mode, - enum machine_mode orig_mode, unsigned int regno) -{ - rtx tmp; + case TImode: + case V16QImode: + case V8HImode: + case V4SImode: + case V2DImode: + case V4SFmode: + case V2DFmode: + if (!type || !AGGREGATE_TYPE_P (type)) + { + cum->sse_words += words; + cum->sse_nregs -= 1; + cum->sse_regno += 1; + if (cum->sse_nregs <= 0) + { + cum->sse_nregs = 0; + cum->sse_regno = 0; + } + } + break; - if (HARD_REGNO_MODE_OK (regno, mode)) - tmp = gen_rtx_REG (mode, regno); - else - { - tmp = gen_rtx_REG (alt_mode, regno); - tmp = gen_rtx_EXPR_LIST (VOIDmode, tmp, const0_rtx); - tmp = gen_rtx_PARALLEL (orig_mode, gen_rtvec (1, tmp)); + case V8QImode: + case V4HImode: + case V2SImode: + case V2SFmode: + if (!type || !AGGREGATE_TYPE_P (type)) + { + cum->mmx_words += words; + cum->mmx_nregs -= 1; + cum->mmx_regno += 1; + if (cum->mmx_nregs <= 0) + { + cum->mmx_nregs = 0; + cum->mmx_regno = 0; + } + } + break; + } } - - return tmp; } /* Define where to put the arguments to a function. @@ -2599,6 +3584,11 @@ function_arg (CUMULATIVE_ARGS *cum, enum machine_mode orig_mode, int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; static bool warnedsse, warnedmmx; + /* To simplify the code below, represent vector types with a vector mode + even if MMX/SSE are not active. */ + if (type && TREE_CODE (type) == VECTOR_TYPE) + mode = type_natural_mode (type); + /* Handle a hidden AL argument containing number of registers for varargs x86-64 functions. For i386 ABI just return constm1_rtx to avoid any AL settings. */ @@ -2614,7 +3604,8 @@ function_arg (CUMULATIVE_ARGS *cum, enum machine_mode orig_mode, return constm1_rtx; } if (TARGET_64BIT) - ret = construct_container (mode, type, 0, cum->nregs, cum->sse_nregs, + ret = construct_container (mode, orig_mode, type, 0, cum->nregs, + cum->sse_nregs, &x86_64_int_parameter_registers [cum->regno], cum->sse_regno); else @@ -2650,6 +3641,13 @@ function_arg (CUMULATIVE_ARGS *cum, enum machine_mode orig_mode, ret = gen_rtx_REG (mode, regno); } break; + case DFmode: + if (cum->float_in_sse < 2) + break; + case SFmode: + if (cum->float_in_sse < 1) + break; + /* FALLTHRU */ case TImode: case V16QImode: case V8HImode: @@ -2659,14 +3657,14 @@ function_arg (CUMULATIVE_ARGS *cum, enum machine_mode orig_mode, case V2DFmode: if (!type || !AGGREGATE_TYPE_P (type)) { - if (!TARGET_SSE && !warnedmmx && cum->warn_sse) + if (!TARGET_SSE && !warnedsse && cum->warn_sse) { warnedsse = true; - warning ("SSE vector argument without SSE enabled " + warning (0, "SSE vector argument without SSE enabled " "changes the ABI"); } if (cum->sse_nregs) - ret = gen_reg_or_parallel (mode, TImode, orig_mode, + ret = gen_reg_or_parallel (mode, orig_mode, cum->sse_regno + FIRST_SSE_REG); } break; @@ -2679,11 +3677,11 @@ function_arg (CUMULATIVE_ARGS *cum, enum machine_mode orig_mode, if (!TARGET_MMX && !warnedmmx && cum->warn_mmx) { warnedmmx = true; - warning ("MMX vector argument without MMX enabled " + warning (0, "MMX vector argument without MMX enabled " "changes the ABI"); } if (cum->mmx_nregs) - ret = gen_reg_or_parallel (mode, DImode, orig_mode, + ret = gen_reg_or_parallel (mode, orig_mode, cum->mmx_regno + FIRST_MMX_REG); } break; @@ -2712,10 +3710,10 @@ function_arg (CUMULATIVE_ARGS *cum, enum machine_mode orig_mode, the argument itself. The pointer is passed in whatever way is appropriate for passing a pointer to that type. */ -int -function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, - enum machine_mode mode ATTRIBUTE_UNUSED, - tree type, int named ATTRIBUTE_UNUSED) +static bool +ix86_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, + enum machine_mode mode ATTRIBUTE_UNUSED, + tree type, bool named ATTRIBUTE_UNUSED) { if (!TARGET_64BIT) return 0; @@ -2731,7 +3729,7 @@ function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, } /* Return true when TYPE should be 128bit aligned for 32bit argument passing - ABI */ + ABI. Only called if TARGET_SSE. */ static bool contains_128bit_aligned_vector_p (tree type) { @@ -2745,44 +3743,44 @@ contains_128bit_aligned_vector_p (tree type) if (AGGREGATE_TYPE_P (type)) { /* Walk the aggregates recursively. */ - if (TREE_CODE (type) == RECORD_TYPE - || TREE_CODE (type) == UNION_TYPE - || TREE_CODE (type) == QUAL_UNION_TYPE) + switch (TREE_CODE (type)) { - tree field; - - if (TYPE_BINFO (type) != NULL - && TYPE_BINFO_BASETYPES (type) != NULL) - { - tree bases = TYPE_BINFO_BASETYPES (type); - int n_bases = TREE_VEC_LENGTH (bases); - int i; + case RECORD_TYPE: + case UNION_TYPE: + case QUAL_UNION_TYPE: + { + tree field; - for (i = 0; i < n_bases; ++i) - { - tree binfo = TREE_VEC_ELT (bases, i); - tree type = BINFO_TYPE (binfo); + if (TYPE_BINFO (type)) + { + tree binfo, base_binfo; + int i; - if (contains_128bit_aligned_vector_p (type)) + for (binfo = TYPE_BINFO (type), i = 0; + BINFO_BASE_ITERATE (binfo, i, base_binfo); i++) + if (contains_128bit_aligned_vector_p + (BINFO_TYPE (base_binfo))) return true; - } - } - /* And now merge the fields of structure. */ - for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) - { - if (TREE_CODE (field) == FIELD_DECL - && contains_128bit_aligned_vector_p (TREE_TYPE (field))) - return true; - } - } - /* Just for use if some languages passes arrays by value. */ - else if (TREE_CODE (type) == ARRAY_TYPE) - { + } + /* And now merge the fields of structure. */ + for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field)) + { + if (TREE_CODE (field) == FIELD_DECL + && contains_128bit_aligned_vector_p (TREE_TYPE (field))) + return true; + } + break; + } + + case ARRAY_TYPE: + /* Just for use if some languages passes arrays by value. */ if (contains_128bit_aligned_vector_p (TREE_TYPE (type))) return true; + break; + + default: + gcc_unreachable (); } - else - abort (); } return false; } @@ -2809,7 +3807,9 @@ ix86_function_arg_boundary (enum machine_mode mode, tree type) The handling here differs from field_alignment. ICC aligns MMX arguments to 4 byte boundaries, while structure fields are aligned to 8 byte boundaries. */ - if (!type) + if (!TARGET_SSE) + align = PARM_BOUNDARY; + else if (!type) { if (!SSE_REG_MODE_P (mode)) align = PARM_BOUNDARY; @@ -2829,15 +3829,31 @@ ix86_function_arg_boundary (enum machine_mode mode, tree type) bool ix86_function_value_regno_p (int regno) { - if (!TARGET_64BIT) + if (TARGET_MACHO) { - return ((regno) == 0 - || ((regno) == FIRST_FLOAT_REG && TARGET_FLOAT_RETURNS_IN_80387) - || ((regno) == FIRST_SSE_REG && TARGET_SSE)); + if (!TARGET_64BIT) + { + return ((regno) == 0 + || ((regno) == FIRST_FLOAT_REG && TARGET_FLOAT_RETURNS_IN_80387) + || ((regno) == FIRST_SSE_REG && TARGET_SSE)); + } + return ((regno) == 0 || (regno) == FIRST_FLOAT_REG + || ((regno) == FIRST_SSE_REG && TARGET_SSE) + || ((regno) == FIRST_FLOAT_REG && TARGET_FLOAT_RETURNS_IN_80387)); + } + else + { + if (regno == 0 + || (regno == FIRST_FLOAT_REG && TARGET_FLOAT_RETURNS_IN_80387) + || (regno == FIRST_SSE_REG && TARGET_SSE)) + return true; + + if (!TARGET_64BIT + && (regno == FIRST_MMX_REG && TARGET_MMX)) + return true; + + return false; } - return ((regno) == 0 || (regno) == FIRST_FLOAT_REG - || ((regno) == FIRST_SSE_REG && TARGET_SSE) - || ((regno) == FIRST_FLOAT_REG && TARGET_FLOAT_RETURNS_IN_80387)); } /* Define how to find the value returned by a function. @@ -2845,30 +3861,40 @@ ix86_function_value_regno_p (int regno) If the precise function being called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. */ rtx -ix86_function_value (tree valtype) +ix86_function_value (tree valtype, tree fntype_or_decl, + bool outgoing ATTRIBUTE_UNUSED) { + enum machine_mode natmode = type_natural_mode (valtype); + if (TARGET_64BIT) { - rtx ret = construct_container (TYPE_MODE (valtype), valtype, 1, - REGPARM_MAX, SSE_REGPARM_MAX, + rtx ret = construct_container (natmode, TYPE_MODE (valtype), valtype, + 1, REGPARM_MAX, SSE_REGPARM_MAX, x86_64_int_return_registers, 0); - /* For zero sized structures, construct_container return NULL, but we need - to keep rest of compiler happy by returning meaningful value. */ + /* For zero sized structures, construct_container return NULL, but we + need to keep rest of compiler happy by returning meaningful value. */ if (!ret) ret = gen_rtx_REG (TYPE_MODE (valtype), 0); return ret; } else - return gen_rtx_REG (TYPE_MODE (valtype), - ix86_value_regno (TYPE_MODE (valtype))); + { + tree fn = NULL_TREE, fntype; + if (fntype_or_decl + && DECL_P (fntype_or_decl)) + fn = fntype_or_decl; + fntype = fn ? TREE_TYPE (fn) : fntype_or_decl; + return gen_rtx_REG (TYPE_MODE (valtype), + ix86_value_regno (natmode, fn, fntype)); + } } -/* Return false iff type is returned in memory. */ +/* Return true iff type is returned in memory. */ int ix86_return_in_memory (tree type) { int needed_intregs, needed_sseregs, size; - enum machine_mode mode = TYPE_MODE (type); + enum machine_mode mode = type_natural_mode (type); if (TARGET_64BIT) return !examine_argument (mode, type, 1, &needed_intregs, &needed_sseregs); @@ -2887,42 +3913,73 @@ ix86_return_in_memory (tree type) if (size < 8) return 0; - /* MMX/3dNow values are returned on the stack, since we've - got to EMMS/FEMMS before returning. */ + /* MMX/3dNow values are returned in MM0, + except when it doesn't exits. */ if (size == 8) - return 1; + return (TARGET_MMX ? 0 : 1); - /* SSE values are returned in XMM0. */ - /* ??? Except when it doesn't exist? We have a choice of - either (1) being abi incompatible with a -march switch, - or (2) generating an error here. Given no good solution, - I think the safest thing is one warning. The user won't - be able to use -Werror, but.... */ + /* SSE values are returned in XMM0, except when it doesn't exist. */ if (size == 16) - { - static bool warned; - - if (TARGET_SSE) - return 0; - - if (!warned) - { - warned = true; - warning ("SSE vector return without SSE enabled " - "changes the ABI"); - } - return 1; - } + return (TARGET_SSE ? 0 : 1); } if (mode == XFmode) return 0; + if (mode == TDmode) + return 1; + if (size > 12) return 1; return 0; } +/* When returning SSE vector types, we have a choice of either + (1) being abi incompatible with a -march switch, or + (2) generating an error. + Given no good solution, I think the safest thing is one warning. + The user won't be able to use -Werror, but.... + + Choose the STRUCT_VALUE_RTX hook because that's (at present) only + called in response to actually generating a caller or callee that + uses such a type. As opposed to RETURN_IN_MEMORY, which is called + via aggregate_value_p for general type probing from tree-ssa. */ + +static rtx +ix86_struct_value_rtx (tree type, int incoming ATTRIBUTE_UNUSED) +{ + static bool warnedsse, warnedmmx; + + if (type) + { + /* Look at the return type of the function, not the function type. */ + enum machine_mode mode = TYPE_MODE (TREE_TYPE (type)); + + if (!TARGET_SSE && !warnedsse) + { + if (mode == TImode + || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16)) + { + warnedsse = true; + warning (0, "SSE vector return without SSE enabled " + "changes the ABI"); + } + } + + if (!TARGET_MMX && !warnedmmx) + { + if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8) + { + warnedmmx = true; + warning (0, "MMX vector return without MMX enabled " + "changes the ABI"); + } + } + } + + return NULL; +} + /* Define how to find the value returned by a library function assuming the value has mode MODE. */ rtx @@ -2936,11 +3993,14 @@ ix86_libcall_value (enum machine_mode mode) case SCmode: case DFmode: case DCmode: + case TFmode: + case SDmode: + case DDmode: + case TDmode: return gen_rtx_REG (mode, FIRST_SSE_REG); case XFmode: case XCmode: return gen_rtx_REG (mode, FIRST_FLOAT_REG); - case TFmode: case TCmode: return NULL; default: @@ -2948,23 +4008,48 @@ ix86_libcall_value (enum machine_mode mode) } } else - return gen_rtx_REG (mode, ix86_value_regno (mode)); + return gen_rtx_REG (mode, ix86_value_regno (mode, NULL, NULL)); } /* Given a mode, return the register to use for a return value. */ static int -ix86_value_regno (enum machine_mode mode) +ix86_value_regno (enum machine_mode mode, tree func, tree fntype) { - /* Floating point return values in %st(0). */ - if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_FLOAT_RETURNS_IN_80387) - return FIRST_FLOAT_REG; + gcc_assert (!TARGET_64BIT); + + /* 8-byte vector modes in %mm0. See ix86_return_in_memory for where + we normally prevent this case when mmx is not available. However + some ABIs may require the result to be returned like DImode. */ + if (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 8) + return TARGET_MMX ? FIRST_MMX_REG : 0; + /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where - we prevent this case when sse is not available. */ + we prevent this case when sse is not available. However some ABIs + may require the result to be returned like integer TImode. */ if (mode == TImode || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16)) - return FIRST_SSE_REG; - /* Everything else in %eax. */ - return 0; + return TARGET_SSE ? FIRST_SSE_REG : 0; + + /* Decimal floating point values can go in %eax, unlike other float modes. */ + if (DECIMAL_FLOAT_MODE_P (mode)) + return 0; + + /* Most things go in %eax, except (unless -mno-fp-ret-in-387) fp values. */ + if (!SCALAR_FLOAT_MODE_P (mode) || !TARGET_FLOAT_RETURNS_IN_80387) + return 0; + + /* Floating point return values in %st(0), except for local functions when + SSE math is enabled or for functions with sseregparm attribute. */ + if ((func || fntype) + && (mode == SFmode || mode == DFmode)) + { + int sse_level = ix86_function_sseregparm (fntype, func); + if ((sse_level >= 1 && mode == SFmode) + || (sse_level == 2 && mode == DFmode)) + return FIRST_SSE_REG; + } + + return FIRST_FLOAT_REG; } /* Create the va_list data type. */ @@ -2990,6 +4075,9 @@ ix86_build_builtin_va_list (void) f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"), ptr_type_node); + va_list_gpr_counter_field = f_gpr; + va_list_fpr_counter_field = f_fpr; + DECL_FIELD_CONTEXT (f_gpr) = record; DECL_FIELD_CONTEXT (f_fpr) = record; DECL_FIELD_CONTEXT (f_ovf) = record; @@ -3008,21 +4096,9 @@ ix86_build_builtin_va_list (void) return build_array_type (record, build_index_type (size_zero_node)); } -/* Perform any needed actions needed for a function that is receiving a - variable number of arguments. - - CUM is as above. - - MODE and TYPE are the mode and type of the current parameter. +/* Worker function for TARGET_SETUP_INCOMING_VARARGS. */ - PRETEND_SIZE is a variable that should be set to the amount of stack - that must be pushed by the prolog to pretend that our caller pushed - it. - - Normally, this macro will push all remaining incoming registers on the - stack and set PRETEND_SIZE to the length of the registers pushed. */ - -void +static void ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type, int *pretend_size ATTRIBUTE_UNUSED, int no_rtl) @@ -3041,6 +4117,9 @@ ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, if (!TARGET_64BIT) return; + if (! cfun->va_list_gpr_size && ! cfun->va_list_fpr_size) + return; + /* Indicate to allocate space on the stack for varargs save area. */ ix86_save_varrargs_registers = 1; @@ -3062,16 +4141,20 @@ ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, set = get_varargs_alias_set (); - for (i = next_cum.regno; i < ix86_regparm; i++) + for (i = next_cum.regno; + i < ix86_regparm + && i < next_cum.regno + cfun->va_list_gpr_size / UNITS_PER_WORD; + i++) { mem = gen_rtx_MEM (Pmode, plus_constant (save_area, i * UNITS_PER_WORD)); + MEM_NOTRAP_P (mem) = 1; set_mem_alias_set (mem, set); emit_move_insn (mem, gen_rtx_REG (Pmode, x86_64_int_parameter_registers[i])); } - if (next_cum.sse_nregs) + if (next_cum.sse_nregs && cfun->va_list_fpr_size) { /* Now emit code to save SSE registers. The AX parameter contains number of SSE parameter registers used to call this function. We use @@ -3108,6 +4191,7 @@ ix86_setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode, plus_constant (save_area, 8 * REGPARM_MAX + 127))); mem = gen_rtx_MEM (BLKmode, plus_constant (tmp_reg, -127)); + MEM_NOTRAP_P (mem) = 1; set_mem_alias_set (mem, set); set_mem_align (mem, BITS_PER_WORD); @@ -3126,6 +4210,7 @@ ix86_va_start (tree valist, rtx nextarg) HOST_WIDE_INT words, n_gpr, n_fpr; tree f_gpr, f_fpr, f_ovf, f_sav; tree gpr, fpr, ovf, sav, t; + tree type; /* Only 64bit target needs something special. */ if (!TARGET_64BIT) @@ -3140,10 +4225,10 @@ ix86_va_start (tree valist, rtx nextarg) f_sav = TREE_CHAIN (f_ovf); valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); - gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); - fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); - ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); - sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); + gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); + fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); + ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); + sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); /* Count number of gp and fp argument registers used. */ words = current_function_args_info.words; @@ -3154,96 +4239,106 @@ ix86_va_start (tree valist, rtx nextarg) fprintf (stderr, "va_start: words = %d, n_gpr = %d, n_fpr = %d\n", (int) words, (int) n_gpr, (int) n_fpr); - t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, - build_int_2 (n_gpr * 8, 0)); - TREE_SIDE_EFFECTS (t) = 1; - expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); + if (cfun->va_list_gpr_size) + { + type = TREE_TYPE (gpr); + t = build2 (MODIFY_EXPR, type, gpr, + build_int_cst (type, n_gpr * 8)); + TREE_SIDE_EFFECTS (t) = 1; + expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); + } - t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, - build_int_2 (n_fpr * 16 + 8*REGPARM_MAX, 0)); - TREE_SIDE_EFFECTS (t) = 1; - expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); + if (cfun->va_list_fpr_size) + { + type = TREE_TYPE (fpr); + t = build2 (MODIFY_EXPR, type, fpr, + build_int_cst (type, n_fpr * 16 + 8*REGPARM_MAX)); + TREE_SIDE_EFFECTS (t) = 1; + expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); + } /* Find the overflow area. */ - t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx); + type = TREE_TYPE (ovf); + t = make_tree (type, virtual_incoming_args_rtx); if (words != 0) - t = build (PLUS_EXPR, TREE_TYPE (ovf), t, - build_int_2 (words * UNITS_PER_WORD, 0)); - t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); + t = build2 (PLUS_EXPR, type, t, + build_int_cst (type, words * UNITS_PER_WORD)); + t = build2 (MODIFY_EXPR, type, ovf, t); TREE_SIDE_EFFECTS (t) = 1; expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); - /* Find the register save area. - Prologue of the function save it right above stack frame. */ - t = make_tree (TREE_TYPE (sav), frame_pointer_rtx); - t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t); - TREE_SIDE_EFFECTS (t) = 1; - expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); + if (cfun->va_list_gpr_size || cfun->va_list_fpr_size) + { + /* Find the register save area. + Prologue of the function save it right above stack frame. */ + type = TREE_TYPE (sav); + t = make_tree (type, frame_pointer_rtx); + t = build2 (MODIFY_EXPR, type, sav, t); + TREE_SIDE_EFFECTS (t) = 1; + expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); + } } /* Implement va_arg. */ -rtx -ix86_va_arg (tree valist, tree type) + +tree +ix86_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p) { static const int intreg[6] = { 0, 1, 2, 3, 4, 5 }; tree f_gpr, f_fpr, f_ovf, f_sav; tree gpr, fpr, ovf, sav, t; int size, rsize; - rtx lab_false, lab_over = NULL_RTX; - rtx addr_rtx, r; + tree lab_false, lab_over = NULL_TREE; + tree addr, t2; rtx container; int indirect_p = 0; + tree ptrtype; + enum machine_mode nat_mode; /* Only 64bit target needs something special. */ if (!TARGET_64BIT) - { - return std_expand_builtin_va_arg (valist, type); - } + return std_gimplify_va_arg_expr (valist, type, pre_p, post_p); f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); f_fpr = TREE_CHAIN (f_gpr); f_ovf = TREE_CHAIN (f_fpr); f_sav = TREE_CHAIN (f_ovf); - valist = build1 (INDIRECT_REF, TREE_TYPE (TREE_TYPE (valist)), valist); - gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr); - fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr); - ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf); - sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav); + valist = build_va_arg_indirect_ref (valist); + gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE); + fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE); + ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE); + sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE); + indirect_p = pass_by_reference (NULL, TYPE_MODE (type), type, false); + if (indirect_p) + type = build_pointer_type (type); size = int_size_in_bytes (type); - if (size == -1) - { - /* Passed by reference. */ - indirect_p = 1; - type = build_pointer_type (type); - size = int_size_in_bytes (type); - } rsize = (size + UNITS_PER_WORD - 1) / UNITS_PER_WORD; - container = construct_container (TYPE_MODE (type), type, 0, + nat_mode = type_natural_mode (type); + container = construct_container (nat_mode, TYPE_MODE (type), type, 0, REGPARM_MAX, SSE_REGPARM_MAX, intreg, 0); - /* - * Pull the value out of the saved registers ... - */ - addr_rtx = gen_reg_rtx (Pmode); + /* Pull the value out of the saved registers. */ + + addr = create_tmp_var (ptr_type_node, "addr"); + DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set (); if (container) { - rtx int_addr_rtx, sse_addr_rtx; int needed_intregs, needed_sseregs; - int need_temp; + bool need_temp; + tree int_addr, sse_addr; - lab_over = gen_label_rtx (); - lab_false = gen_label_rtx (); + lab_false = create_artificial_label (); + lab_over = create_artificial_label (); - examine_argument (TYPE_MODE (type), type, 0, - &needed_intregs, &needed_sseregs); + examine_argument (nat_mode, type, 0, &needed_intregs, &needed_sseregs); - - need_temp = ((needed_intregs && TYPE_ALIGN (type) > 64) - || TYPE_ALIGN (type) > 128); + need_temp = (!REG_P (container) + && ((needed_intregs && TYPE_ALIGN (type) > 64) + || TYPE_ALIGN (type) > 128)); /* In case we are passing structure, verify that it is consecutive block on the register save area. If not we need to do moves. */ @@ -3277,230 +4372,161 @@ ix86_va_arg (tree valist, tree type) } if (!need_temp) { - int_addr_rtx = addr_rtx; - sse_addr_rtx = addr_rtx; + int_addr = addr; + sse_addr = addr; } else { - int_addr_rtx = gen_reg_rtx (Pmode); - sse_addr_rtx = gen_reg_rtx (Pmode); + int_addr = create_tmp_var (ptr_type_node, "int_addr"); + DECL_POINTER_ALIAS_SET (int_addr) = get_varargs_alias_set (); + sse_addr = create_tmp_var (ptr_type_node, "sse_addr"); + DECL_POINTER_ALIAS_SET (sse_addr) = get_varargs_alias_set (); } + /* First ensure that we fit completely in registers. */ if (needed_intregs) { - emit_cmp_and_jump_insns (expand_expr - (gpr, NULL_RTX, SImode, EXPAND_NORMAL), - GEN_INT ((REGPARM_MAX - needed_intregs + - 1) * 8), GE, const1_rtx, SImode, - 1, lab_false); + t = build_int_cst (TREE_TYPE (gpr), + (REGPARM_MAX - needed_intregs + 1) * 8); + t = build2 (GE_EXPR, boolean_type_node, gpr, t); + t2 = build1 (GOTO_EXPR, void_type_node, lab_false); + t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE); + gimplify_and_add (t, pre_p); } if (needed_sseregs) { - emit_cmp_and_jump_insns (expand_expr - (fpr, NULL_RTX, SImode, EXPAND_NORMAL), - GEN_INT ((SSE_REGPARM_MAX - - needed_sseregs + 1) * 16 + - REGPARM_MAX * 8), GE, const1_rtx, - SImode, 1, lab_false); + t = build_int_cst (TREE_TYPE (fpr), + (SSE_REGPARM_MAX - needed_sseregs + 1) * 16 + + REGPARM_MAX * 8); + t = build2 (GE_EXPR, boolean_type_node, fpr, t); + t2 = build1 (GOTO_EXPR, void_type_node, lab_false); + t = build3 (COND_EXPR, void_type_node, t, t2, NULL_TREE); + gimplify_and_add (t, pre_p); } /* Compute index to start of area used for integer regs. */ if (needed_intregs) { - t = build (PLUS_EXPR, ptr_type_node, sav, gpr); - r = expand_expr (t, int_addr_rtx, Pmode, EXPAND_NORMAL); - if (r != int_addr_rtx) - emit_move_insn (int_addr_rtx, r); + /* int_addr = gpr + sav; */ + t = fold_convert (ptr_type_node, gpr); + t = build2 (PLUS_EXPR, ptr_type_node, sav, t); + t = build2 (MODIFY_EXPR, void_type_node, int_addr, t); + gimplify_and_add (t, pre_p); } if (needed_sseregs) { - t = build (PLUS_EXPR, ptr_type_node, sav, fpr); - r = expand_expr (t, sse_addr_rtx, Pmode, EXPAND_NORMAL); - if (r != sse_addr_rtx) - emit_move_insn (sse_addr_rtx, r); + /* sse_addr = fpr + sav; */ + t = fold_convert (ptr_type_node, fpr); + t = build2 (PLUS_EXPR, ptr_type_node, sav, t); + t = build2 (MODIFY_EXPR, void_type_node, sse_addr, t); + gimplify_and_add (t, pre_p); } if (need_temp) { int i; - rtx mem; - rtx x; + tree temp = create_tmp_var (type, "va_arg_tmp"); - /* Never use the memory itself, as it has the alias set. */ - x = XEXP (assign_temp (type, 0, 1, 0), 0); - mem = gen_rtx_MEM (BLKmode, x); - force_operand (x, addr_rtx); - set_mem_alias_set (mem, get_varargs_alias_set ()); - set_mem_align (mem, BITS_PER_UNIT); + /* addr = &temp; */ + t = build1 (ADDR_EXPR, build_pointer_type (type), temp); + t = build2 (MODIFY_EXPR, void_type_node, addr, t); + gimplify_and_add (t, pre_p); for (i = 0; i < XVECLEN (container, 0); i++) { rtx slot = XVECEXP (container, 0, i); rtx reg = XEXP (slot, 0); enum machine_mode mode = GET_MODE (reg); - rtx src_addr; - rtx src_mem; + tree piece_type = lang_hooks.types.type_for_mode (mode, 1); + tree addr_type = build_pointer_type (piece_type); + tree src_addr, src; int src_offset; - rtx dest_mem; + tree dest_addr, dest; if (SSE_REGNO_P (REGNO (reg))) { - src_addr = sse_addr_rtx; + src_addr = sse_addr; src_offset = (REGNO (reg) - FIRST_SSE_REG) * 16; } else { - src_addr = int_addr_rtx; + src_addr = int_addr; src_offset = REGNO (reg) * 8; } - src_mem = gen_rtx_MEM (mode, src_addr); - set_mem_alias_set (src_mem, get_varargs_alias_set ()); - src_mem = adjust_address (src_mem, mode, src_offset); - dest_mem = adjust_address (mem, mode, INTVAL (XEXP (slot, 1))); - emit_move_insn (dest_mem, src_mem); + src_addr = fold_convert (addr_type, src_addr); + src_addr = fold (build2 (PLUS_EXPR, addr_type, src_addr, + size_int (src_offset))); + src = build_va_arg_indirect_ref (src_addr); + + dest_addr = fold_convert (addr_type, addr); + dest_addr = fold (build2 (PLUS_EXPR, addr_type, dest_addr, + size_int (INTVAL (XEXP (slot, 1))))); + dest = build_va_arg_indirect_ref (dest_addr); + + t = build2 (MODIFY_EXPR, void_type_node, dest, src); + gimplify_and_add (t, pre_p); } } if (needed_intregs) { - t = - build (PLUS_EXPR, TREE_TYPE (gpr), gpr, - build_int_2 (needed_intregs * 8, 0)); - t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t); - TREE_SIDE_EFFECTS (t) = 1; - expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); + t = build2 (PLUS_EXPR, TREE_TYPE (gpr), gpr, + build_int_cst (TREE_TYPE (gpr), needed_intregs * 8)); + t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr, t); + gimplify_and_add (t, pre_p); } if (needed_sseregs) { - t = - build (PLUS_EXPR, TREE_TYPE (fpr), fpr, - build_int_2 (needed_sseregs * 16, 0)); - t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr, t); - TREE_SIDE_EFFECTS (t) = 1; - expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); + t = build2 (PLUS_EXPR, TREE_TYPE (fpr), fpr, + build_int_cst (TREE_TYPE (fpr), needed_sseregs * 16)); + t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr, t); + gimplify_and_add (t, pre_p); } - emit_jump_insn (gen_jump (lab_over)); - emit_barrier (); - emit_label (lab_false); + t = build1 (GOTO_EXPR, void_type_node, lab_over); + gimplify_and_add (t, pre_p); + + t = build1 (LABEL_EXPR, void_type_node, lab_false); + append_to_statement_list (t, pre_p); } /* ... otherwise out of the overflow area. */ /* Care for on-stack alignment if needed. */ - if (FUNCTION_ARG_BOUNDARY (VOIDmode, type) <= 64) + if (FUNCTION_ARG_BOUNDARY (VOIDmode, type) <= 64 + || integer_zerop (TYPE_SIZE (type))) t = ovf; else { HOST_WIDE_INT align = FUNCTION_ARG_BOUNDARY (VOIDmode, type) / 8; - t = build (PLUS_EXPR, TREE_TYPE (ovf), ovf, build_int_2 (align - 1, 0)); - t = build (BIT_AND_EXPR, TREE_TYPE (t), t, build_int_2 (-align, -1)); + t = build2 (PLUS_EXPR, TREE_TYPE (ovf), ovf, + build_int_cst (TREE_TYPE (ovf), align - 1)); + t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, + build_int_cst (TREE_TYPE (t), -align)); } - t = save_expr (t); + gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue); - r = expand_expr (t, addr_rtx, Pmode, EXPAND_NORMAL); - if (r != addr_rtx) - emit_move_insn (addr_rtx, r); + t2 = build2 (MODIFY_EXPR, void_type_node, addr, t); + gimplify_and_add (t2, pre_p); - t = - build (PLUS_EXPR, TREE_TYPE (t), t, - build_int_2 (rsize * UNITS_PER_WORD, 0)); - t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); - TREE_SIDE_EFFECTS (t) = 1; - expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); + t = build2 (PLUS_EXPR, TREE_TYPE (t), t, + build_int_cst (TREE_TYPE (t), rsize * UNITS_PER_WORD)); + t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t); + gimplify_and_add (t, pre_p); if (container) - emit_label (lab_over); - - if (indirect_p) { - r = gen_rtx_MEM (Pmode, addr_rtx); - set_mem_alias_set (r, get_varargs_alias_set ()); - emit_move_insn (addr_rtx, r); + t = build1 (LABEL_EXPR, void_type_node, lab_over); + append_to_statement_list (t, pre_p); } - return addr_rtx; -} - -/* Return nonzero if OP is either a i387 or SSE fp register. */ -int -any_fp_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - return ANY_FP_REG_P (op); -} - -/* Return nonzero if OP is an i387 fp register. */ -int -fp_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - return FP_REG_P (op); -} - -/* Return nonzero if OP is a non-fp register_operand. */ -int -register_and_not_any_fp_reg_operand (rtx op, enum machine_mode mode) -{ - return register_operand (op, mode) && !ANY_FP_REG_P (op); -} - -/* Return nonzero if OP is a register operand other than an - i387 fp register. */ -int -register_and_not_fp_reg_operand (rtx op, enum machine_mode mode) -{ - return register_operand (op, mode) && !FP_REG_P (op); -} - -/* Return nonzero if OP is general operand representable on x86_64. */ - -int -x86_64_general_operand (rtx op, enum machine_mode mode) -{ - if (!TARGET_64BIT) - return general_operand (op, mode); - if (nonimmediate_operand (op, mode)) - return 1; - return x86_64_sign_extended_value (op); -} - -/* Return nonzero if OP is general operand representable on x86_64 - as either sign extended or zero extended constant. */ - -int -x86_64_szext_general_operand (rtx op, enum machine_mode mode) -{ - if (!TARGET_64BIT) - return general_operand (op, mode); - if (nonimmediate_operand (op, mode)) - return 1; - return x86_64_sign_extended_value (op) || x86_64_zero_extended_value (op); -} - -/* Return nonzero if OP is nonmemory operand representable on x86_64. */ - -int -x86_64_nonmemory_operand (rtx op, enum machine_mode mode) -{ - if (!TARGET_64BIT) - return nonmemory_operand (op, mode); - if (register_operand (op, mode)) - return 1; - return x86_64_sign_extended_value (op); -} - -/* Return nonzero if OP is nonmemory operand acceptable by movabs patterns. */ + ptrtype = build_pointer_type (type); + addr = fold_convert (ptrtype, addr); -int -x86_64_movabs_operand (rtx op, enum machine_mode mode) -{ - if (!TARGET_64BIT || !flag_pic) - return nonmemory_operand (op, mode); - if (register_operand (op, mode) || x86_64_sign_extended_value (op)) - return 1; - if (CONSTANT_P (op) && !symbolic_reference_mentioned_p (op)) - return 1; - return 0; + if (indirect_p) + addr = build_va_arg_indirect_ref (addr); + return build_va_arg_indirect_ref (addr); } - + /* Return nonzero if OPNUM's MEM should be matched in movabs* patterns. */ @@ -3512,859 +4538,13 @@ ix86_check_movabs (rtx insn, int opnum) set = PATTERN (insn); if (GET_CODE (set) == PARALLEL) set = XVECEXP (set, 0, 0); - if (GET_CODE (set) != SET) - abort (); + gcc_assert (GET_CODE (set) == SET); mem = XEXP (set, opnum); while (GET_CODE (mem) == SUBREG) mem = SUBREG_REG (mem); - if (GET_CODE (mem) != MEM) - abort (); + gcc_assert (GET_CODE (mem) == MEM); return (volatile_ok || !MEM_VOLATILE_P (mem)); } - -/* Return nonzero if OP is nonmemory operand representable on x86_64. */ - -int -x86_64_szext_nonmemory_operand (rtx op, enum machine_mode mode) -{ - if (!TARGET_64BIT) - return nonmemory_operand (op, mode); - if (register_operand (op, mode)) - return 1; - return x86_64_sign_extended_value (op) || x86_64_zero_extended_value (op); -} - -/* Return nonzero if OP is immediate operand representable on x86_64. */ - -int -x86_64_immediate_operand (rtx op, enum machine_mode mode) -{ - if (!TARGET_64BIT) - return immediate_operand (op, mode); - return x86_64_sign_extended_value (op); -} - -/* Return nonzero if OP is immediate operand representable on x86_64. */ - -int -x86_64_zext_immediate_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - return x86_64_zero_extended_value (op); -} - -/* Return nonzero if OP is CONST_INT >= 1 and <= 31 (a valid operand - for shift & compare patterns, as shifting by 0 does not change flags), - else return zero. */ - -int -const_int_1_31_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 1 && INTVAL (op) <= 31); -} - -/* Returns 1 if OP is either a symbol reference or a sum of a symbol - reference and a constant. */ - -int -symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - switch (GET_CODE (op)) - { - case SYMBOL_REF: - case LABEL_REF: - return 1; - - case CONST: - op = XEXP (op, 0); - if (GET_CODE (op) == SYMBOL_REF - || GET_CODE (op) == LABEL_REF - || (GET_CODE (op) == UNSPEC - && (XINT (op, 1) == UNSPEC_GOT - || XINT (op, 1) == UNSPEC_GOTOFF - || XINT (op, 1) == UNSPEC_GOTPCREL))) - return 1; - if (GET_CODE (op) != PLUS - || GET_CODE (XEXP (op, 1)) != CONST_INT) - return 0; - - op = XEXP (op, 0); - if (GET_CODE (op) == SYMBOL_REF - || GET_CODE (op) == LABEL_REF) - return 1; - /* Only @GOTOFF gets offsets. */ - if (GET_CODE (op) != UNSPEC - || XINT (op, 1) != UNSPEC_GOTOFF) - return 0; - - op = XVECEXP (op, 0, 0); - if (GET_CODE (op) == SYMBOL_REF - || GET_CODE (op) == LABEL_REF) - return 1; - return 0; - - default: - return 0; - } -} - -/* Return true if the operand contains a @GOT or @GOTOFF reference. */ - -int -pic_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - if (GET_CODE (op) != CONST) - return 0; - op = XEXP (op, 0); - if (TARGET_64BIT) - { - if (GET_CODE (op) == UNSPEC - && XINT (op, 1) == UNSPEC_GOTPCREL) - return 1; - if (GET_CODE (op) == PLUS - && GET_CODE (XEXP (op, 0)) == UNSPEC - && XINT (XEXP (op, 0), 1) == UNSPEC_GOTPCREL) - return 1; - } - else - { - if (GET_CODE (op) == UNSPEC) - return 1; - if (GET_CODE (op) != PLUS - || GET_CODE (XEXP (op, 1)) != CONST_INT) - return 0; - op = XEXP (op, 0); - if (GET_CODE (op) == UNSPEC) - return 1; - } - return 0; -} - -/* Return true if OP is a symbolic operand that resolves locally. */ - -static int -local_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - if (GET_CODE (op) == CONST - && GET_CODE (XEXP (op, 0)) == PLUS - && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT) - op = XEXP (XEXP (op, 0), 0); - - if (GET_CODE (op) == LABEL_REF) - return 1; - - if (GET_CODE (op) != SYMBOL_REF) - return 0; - - if (SYMBOL_REF_LOCAL_P (op)) - return 1; - - /* There is, however, a not insubstantial body of code in the rest of - the compiler that assumes it can just stick the results of - ASM_GENERATE_INTERNAL_LABEL in a symbol_ref and have done. */ - /* ??? This is a hack. Should update the body of the compiler to - always create a DECL an invoke targetm.encode_section_info. */ - if (strncmp (XSTR (op, 0), internal_label_prefix, - internal_label_prefix_len) == 0) - return 1; - - return 0; -} - -/* Test for various thread-local symbols. */ - -int -tls_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - if (GET_CODE (op) != SYMBOL_REF) - return 0; - return SYMBOL_REF_TLS_MODEL (op); -} - -static inline int -tls_symbolic_operand_1 (rtx op, enum tls_model kind) -{ - if (GET_CODE (op) != SYMBOL_REF) - return 0; - return SYMBOL_REF_TLS_MODEL (op) == kind; -} - -int -global_dynamic_symbolic_operand (rtx op, - enum machine_mode mode ATTRIBUTE_UNUSED) -{ - return tls_symbolic_operand_1 (op, TLS_MODEL_GLOBAL_DYNAMIC); -} - -int -local_dynamic_symbolic_operand (rtx op, - enum machine_mode mode ATTRIBUTE_UNUSED) -{ - return tls_symbolic_operand_1 (op, TLS_MODEL_LOCAL_DYNAMIC); -} - -int -initial_exec_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - return tls_symbolic_operand_1 (op, TLS_MODEL_INITIAL_EXEC); -} - -int -local_exec_symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - return tls_symbolic_operand_1 (op, TLS_MODEL_LOCAL_EXEC); -} - -/* Test for a valid operand for a call instruction. Don't allow the - arg pointer register or virtual regs since they may decay into - reg + const, which the patterns can't handle. */ - -int -call_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - /* Disallow indirect through a virtual register. This leads to - compiler aborts when trying to eliminate them. */ - if (GET_CODE (op) == REG - && (op == arg_pointer_rtx - || op == frame_pointer_rtx - || (REGNO (op) >= FIRST_PSEUDO_REGISTER - && REGNO (op) <= LAST_VIRTUAL_REGISTER))) - return 0; - - /* Disallow `call 1234'. Due to varying assembler lameness this - gets either rejected or translated to `call .+1234'. */ - if (GET_CODE (op) == CONST_INT) - return 0; - - /* Explicitly allow SYMBOL_REF even if pic. */ - if (GET_CODE (op) == SYMBOL_REF) - return 1; - - /* Otherwise we can allow any general_operand in the address. */ - return general_operand (op, Pmode); -} - -/* Test for a valid operand for a call instruction. Don't allow the - arg pointer register or virtual regs since they may decay into - reg + const, which the patterns can't handle. */ - -int -sibcall_insn_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - /* Disallow indirect through a virtual register. This leads to - compiler aborts when trying to eliminate them. */ - if (GET_CODE (op) == REG - && (op == arg_pointer_rtx - || op == frame_pointer_rtx - || (REGNO (op) >= FIRST_PSEUDO_REGISTER - && REGNO (op) <= LAST_VIRTUAL_REGISTER))) - return 0; - - /* Explicitly allow SYMBOL_REF even if pic. */ - if (GET_CODE (op) == SYMBOL_REF) - return 1; - - /* Otherwise we can only allow register operands. */ - return register_operand (op, Pmode); -} - -int -constant_call_address_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - if (GET_CODE (op) == CONST - && GET_CODE (XEXP (op, 0)) == PLUS - && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT) - op = XEXP (XEXP (op, 0), 0); - return GET_CODE (op) == SYMBOL_REF; -} - -/* Match exactly zero and one. */ - -int -const0_operand (rtx op, enum machine_mode mode) -{ - return op == CONST0_RTX (mode); -} - -int -const1_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - return op == const1_rtx; -} - -/* Match 2, 4, or 8. Used for leal multiplicands. */ - -int -const248_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - return (GET_CODE (op) == CONST_INT - && (INTVAL (op) == 2 || INTVAL (op) == 4 || INTVAL (op) == 8)); -} - -int -const_0_to_3_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 4); -} - -int -const_0_to_7_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 8); -} - -int -const_0_to_15_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 16); -} - -int -const_0_to_255_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 0 && INTVAL (op) < 256); -} - - -/* True if this is a constant appropriate for an increment or decrement. */ - -int -incdec_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - /* On Pentium4, the inc and dec operations causes extra dependency on flag - registers, since carry flag is not set. */ - if (TARGET_PENTIUM4 && !optimize_size) - return 0; - return op == const1_rtx || op == constm1_rtx; -} - -/* Return nonzero if OP is acceptable as operand of DImode shift - expander. */ - -int -shiftdi_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - if (TARGET_64BIT) - return nonimmediate_operand (op, mode); - else - return register_operand (op, mode); -} - -/* Return false if this is the stack pointer, or any other fake - register eliminable to the stack pointer. Otherwise, this is - a register operand. - - This is used to prevent esp from being used as an index reg. - Which would only happen in pathological cases. */ - -int -reg_no_sp_operand (rtx op, enum machine_mode mode) -{ - rtx t = op; - if (GET_CODE (t) == SUBREG) - t = SUBREG_REG (t); - if (t == stack_pointer_rtx || t == arg_pointer_rtx || t == frame_pointer_rtx) - return 0; - - return register_operand (op, mode); -} - -int -mmx_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - return MMX_REG_P (op); -} - -/* Return false if this is any eliminable register. Otherwise - general_operand. */ - -int -general_no_elim_operand (rtx op, enum machine_mode mode) -{ - rtx t = op; - if (GET_CODE (t) == SUBREG) - t = SUBREG_REG (t); - if (t == arg_pointer_rtx || t == frame_pointer_rtx - || t == virtual_incoming_args_rtx || t == virtual_stack_vars_rtx - || t == virtual_stack_dynamic_rtx) - return 0; - if (REG_P (t) - && REGNO (t) >= FIRST_VIRTUAL_REGISTER - && REGNO (t) <= LAST_VIRTUAL_REGISTER) - return 0; - - return general_operand (op, mode); -} - -/* Return false if this is any eliminable register. Otherwise - register_operand or const_int. */ - -int -nonmemory_no_elim_operand (rtx op, enum machine_mode mode) -{ - rtx t = op; - if (GET_CODE (t) == SUBREG) - t = SUBREG_REG (t); - if (t == arg_pointer_rtx || t == frame_pointer_rtx - || t == virtual_incoming_args_rtx || t == virtual_stack_vars_rtx - || t == virtual_stack_dynamic_rtx) - return 0; - - return GET_CODE (op) == CONST_INT || register_operand (op, mode); -} - -/* Return false if this is any eliminable register or stack register, - otherwise work like register_operand. */ - -int -index_register_operand (rtx op, enum machine_mode mode) -{ - rtx t = op; - if (GET_CODE (t) == SUBREG) - t = SUBREG_REG (t); - if (!REG_P (t)) - return 0; - if (t == arg_pointer_rtx - || t == frame_pointer_rtx - || t == virtual_incoming_args_rtx - || t == virtual_stack_vars_rtx - || t == virtual_stack_dynamic_rtx - || REGNO (t) == STACK_POINTER_REGNUM) - return 0; - - return general_operand (op, mode); -} - -/* Return true if op is a Q_REGS class register. */ - -int -q_regs_operand (rtx op, enum machine_mode mode) -{ - if (mode != VOIDmode && GET_MODE (op) != mode) - return 0; - if (GET_CODE (op) == SUBREG) - op = SUBREG_REG (op); - return ANY_QI_REG_P (op); -} - -/* Return true if op is an flags register. */ - -int -flags_reg_operand (rtx op, enum machine_mode mode) -{ - if (mode != VOIDmode && GET_MODE (op) != mode) - return 0; - return REG_P (op) && REGNO (op) == FLAGS_REG && GET_MODE (op) != VOIDmode; -} - -/* Return true if op is a NON_Q_REGS class register. */ - -int -non_q_regs_operand (rtx op, enum machine_mode mode) -{ - if (mode != VOIDmode && GET_MODE (op) != mode) - return 0; - if (GET_CODE (op) == SUBREG) - op = SUBREG_REG (op); - return NON_QI_REG_P (op); -} - -int -zero_extended_scalar_load_operand (rtx op, - enum machine_mode mode ATTRIBUTE_UNUSED) -{ - unsigned n_elts; - if (GET_CODE (op) != MEM) - return 0; - op = maybe_get_pool_constant (op); - if (!op) - return 0; - if (GET_CODE (op) != CONST_VECTOR) - return 0; - n_elts = - (GET_MODE_SIZE (GET_MODE (op)) / - GET_MODE_SIZE (GET_MODE_INNER (GET_MODE (op)))); - for (n_elts--; n_elts > 0; n_elts--) - { - rtx elt = CONST_VECTOR_ELT (op, n_elts); - if (elt != CONST0_RTX (GET_MODE_INNER (GET_MODE (op)))) - return 0; - } - return 1; -} - -/* Return 1 when OP is operand acceptable for standard SSE move. */ -int -vector_move_operand (rtx op, enum machine_mode mode) -{ - if (nonimmediate_operand (op, mode)) - return 1; - if (GET_MODE (op) != mode && mode != VOIDmode) - return 0; - return (op == CONST0_RTX (GET_MODE (op))); -} - -/* Return true if op if a valid address, and does not contain - a segment override. */ - -int -no_seg_address_operand (rtx op, enum machine_mode mode) -{ - struct ix86_address parts; - - if (! address_operand (op, mode)) - return 0; - - if (! ix86_decompose_address (op, &parts)) - abort (); - - return parts.seg == SEG_DEFAULT; -} - -/* Return 1 if OP is a comparison that can be used in the CMPSS/CMPPS - insns. */ -int -sse_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - enum rtx_code code = GET_CODE (op); - switch (code) - { - /* Operations supported directly. */ - case EQ: - case LT: - case LE: - case UNORDERED: - case NE: - case UNGE: - case UNGT: - case ORDERED: - return 1; - /* These are equivalent to ones above in non-IEEE comparisons. */ - case UNEQ: - case UNLT: - case UNLE: - case LTGT: - case GE: - case GT: - return !TARGET_IEEE_FP; - default: - return 0; - } -} -/* Return 1 if OP is a valid comparison operator in valid mode. */ -int -ix86_comparison_operator (rtx op, enum machine_mode mode) -{ - enum machine_mode inmode; - enum rtx_code code = GET_CODE (op); - if (mode != VOIDmode && GET_MODE (op) != mode) - return 0; - if (GET_RTX_CLASS (code) != '<') - return 0; - inmode = GET_MODE (XEXP (op, 0)); - - if (inmode == CCFPmode || inmode == CCFPUmode) - { - enum rtx_code second_code, bypass_code; - ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code); - return (bypass_code == NIL && second_code == NIL); - } - switch (code) - { - case EQ: case NE: - return 1; - case LT: case GE: - if (inmode == CCmode || inmode == CCGCmode - || inmode == CCGOCmode || inmode == CCNOmode) - return 1; - return 0; - case LTU: case GTU: case LEU: case ORDERED: case UNORDERED: case GEU: - if (inmode == CCmode) - return 1; - return 0; - case GT: case LE: - if (inmode == CCmode || inmode == CCGCmode || inmode == CCNOmode) - return 1; - return 0; - default: - return 0; - } -} - -/* Return 1 if OP is a valid comparison operator testing carry flag - to be set. */ -int -ix86_carry_flag_operator (rtx op, enum machine_mode mode) -{ - enum machine_mode inmode; - enum rtx_code code = GET_CODE (op); - - if (mode != VOIDmode && GET_MODE (op) != mode) - return 0; - if (GET_RTX_CLASS (code) != '<') - return 0; - inmode = GET_MODE (XEXP (op, 0)); - if (GET_CODE (XEXP (op, 0)) != REG - || REGNO (XEXP (op, 0)) != 17 - || XEXP (op, 1) != const0_rtx) - return 0; - - if (inmode == CCFPmode || inmode == CCFPUmode) - { - enum rtx_code second_code, bypass_code; - - ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code); - if (bypass_code != NIL || second_code != NIL) - return 0; - code = ix86_fp_compare_code_to_integer (code); - } - else if (inmode != CCmode) - return 0; - return code == LTU; -} - -/* Return 1 if OP is a comparison operator that can be issued by fcmov. */ - -int -fcmov_comparison_operator (rtx op, enum machine_mode mode) -{ - enum machine_mode inmode; - enum rtx_code code = GET_CODE (op); - - if (mode != VOIDmode && GET_MODE (op) != mode) - return 0; - if (GET_RTX_CLASS (code) != '<') - return 0; - inmode = GET_MODE (XEXP (op, 0)); - if (inmode == CCFPmode || inmode == CCFPUmode) - { - enum rtx_code second_code, bypass_code; - - ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code); - if (bypass_code != NIL || second_code != NIL) - return 0; - code = ix86_fp_compare_code_to_integer (code); - } - /* i387 supports just limited amount of conditional codes. */ - switch (code) - { - case LTU: case GTU: case LEU: case GEU: - if (inmode == CCmode || inmode == CCFPmode || inmode == CCFPUmode) - return 1; - return 0; - case ORDERED: case UNORDERED: - case EQ: case NE: - return 1; - default: - return 0; - } -} - -/* Return 1 if OP is a binary operator that can be promoted to wider mode. */ - -int -promotable_binary_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - switch (GET_CODE (op)) - { - case MULT: - /* Modern CPUs have same latency for HImode and SImode multiply, - but 386 and 486 do HImode multiply faster. */ - return ix86_tune > PROCESSOR_I486; - case PLUS: - case AND: - case IOR: - case XOR: - case ASHIFT: - return 1; - default: - return 0; - } -} - -/* Nearly general operand, but accept any const_double, since we wish - to be able to drop them into memory rather than have them get pulled - into registers. */ - -int -cmp_fp_expander_operand (rtx op, enum machine_mode mode) -{ - if (mode != VOIDmode && mode != GET_MODE (op)) - return 0; - if (GET_CODE (op) == CONST_DOUBLE) - return 1; - return general_operand (op, mode); -} - -/* Match an SI or HImode register for a zero_extract. */ - -int -ext_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - int regno; - if ((!TARGET_64BIT || GET_MODE (op) != DImode) - && GET_MODE (op) != SImode && GET_MODE (op) != HImode) - return 0; - - if (!register_operand (op, VOIDmode)) - return 0; - - /* Be careful to accept only registers having upper parts. */ - regno = REG_P (op) ? REGNO (op) : REGNO (SUBREG_REG (op)); - return (regno > LAST_VIRTUAL_REGISTER || regno < 4); -} - -/* Return 1 if this is a valid binary floating-point operation. - OP is the expression matched, and MODE is its mode. */ - -int -binary_fp_operator (rtx op, enum machine_mode mode) -{ - if (mode != VOIDmode && mode != GET_MODE (op)) - return 0; - - switch (GET_CODE (op)) - { - case PLUS: - case MINUS: - case MULT: - case DIV: - return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT; - - default: - return 0; - } -} - -int -mult_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - return GET_CODE (op) == MULT; -} - -int -div_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - return GET_CODE (op) == DIV; -} - -int -arith_or_logical_operator (rtx op, enum machine_mode mode) -{ - return ((mode == VOIDmode || GET_MODE (op) == mode) - && (GET_RTX_CLASS (GET_CODE (op)) == 'c' - || GET_RTX_CLASS (GET_CODE (op)) == '2')); -} - -/* Returns 1 if OP is memory operand with a displacement. */ - -int -memory_displacement_operand (rtx op, enum machine_mode mode) -{ - struct ix86_address parts; - - if (! memory_operand (op, mode)) - return 0; - - if (! ix86_decompose_address (XEXP (op, 0), &parts)) - abort (); - - return parts.disp != NULL_RTX; -} - -/* To avoid problems when jump re-emits comparisons like testqi_ext_ccno_0, - re-recognize the operand to avoid a copy_to_mode_reg that will fail. - - ??? It seems likely that this will only work because cmpsi is an - expander, and no actual insns use this. */ - -int -cmpsi_operand (rtx op, enum machine_mode mode) -{ - if (nonimmediate_operand (op, mode)) - return 1; - - if (GET_CODE (op) == AND - && GET_MODE (op) == SImode - && GET_CODE (XEXP (op, 0)) == ZERO_EXTRACT - && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT - && GET_CODE (XEXP (XEXP (op, 0), 2)) == CONST_INT - && INTVAL (XEXP (XEXP (op, 0), 1)) == 8 - && INTVAL (XEXP (XEXP (op, 0), 2)) == 8 - && GET_CODE (XEXP (op, 1)) == CONST_INT) - return 1; - - return 0; -} - -/* Returns 1 if OP is memory operand that can not be represented by the - modRM array. */ - -int -long_memory_operand (rtx op, enum machine_mode mode) -{ - if (! memory_operand (op, mode)) - return 0; - - return memory_address_length (op) != 0; -} - -/* Return nonzero if the rtx is known aligned. */ - -int -aligned_operand (rtx op, enum machine_mode mode) -{ - struct ix86_address parts; - - if (!general_operand (op, mode)) - return 0; - - /* Registers and immediate operands are always "aligned". */ - if (GET_CODE (op) != MEM) - return 1; - - /* Don't even try to do any aligned optimizations with volatiles. */ - if (MEM_VOLATILE_P (op)) - return 0; - - op = XEXP (op, 0); - - /* Pushes and pops are only valid on the stack pointer. */ - if (GET_CODE (op) == PRE_DEC - || GET_CODE (op) == POST_INC) - return 1; - - /* Decode the address. */ - if (! ix86_decompose_address (op, &parts)) - abort (); - - /* Look for some component that isn't known to be aligned. */ - if (parts.index) - { - if (parts.scale < 4 - && REGNO_POINTER_ALIGN (REGNO (parts.index)) < 32) - return 0; - } - if (parts.base) - { - if (REGNO_POINTER_ALIGN (REGNO (parts.base)) < 32) - return 0; - } - if (parts.disp) - { - if (GET_CODE (parts.disp) != CONST_INT - || (INTVAL (parts.disp) & 3) != 0) - return 0; - } - - /* Didn't find one -- this must be an aligned address. */ - return 1; -} - -int -compare_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) -{ - return GET_CODE (op) == COMPARE; -} /* Initialize the table of extra 80387 mathematical constants. */ @@ -4406,10 +4586,10 @@ standard_80387_constant_p (rtx x) if (x == CONST1_RTX (GET_MODE (x))) return 2; - /* For XFmode constants, try to find a special 80387 instruction on - those CPUs that benefit from them. */ + /* For XFmode constants, try to find a special 80387 instruction when + optimizing for size or on those CPUs that benefit from them. */ if (GET_MODE (x) == XFmode - && x86_ext_80387_constants & TUNEMASK) + && (optimize_size || x86_ext_80387_constants & TUNEMASK)) { REAL_VALUE_TYPE r; int i; @@ -4448,8 +4628,9 @@ standard_80387_constant_opcode (rtx x) return "fldl2t"; case 7: return "fldpi"; + default: + gcc_unreachable (); } - abort (); } /* Return the CONST_DOUBLE representing the 80387 constant that is @@ -4475,21 +4656,67 @@ standard_80387_constant_rtx (int idx) break; default: - abort (); + gcc_unreachable (); } return CONST_DOUBLE_FROM_REAL_VALUE (ext_80387_constants_table[i], XFmode); } +/* Return 1 if mode is a valid mode for sse. */ +static int +standard_sse_mode_p (enum machine_mode mode) +{ + switch (mode) + { + case V16QImode: + case V8HImode: + case V4SImode: + case V2DImode: + case V4SFmode: + case V2DFmode: + return 1; + + default: + return 0; + } +} + /* Return 1 if X is FP constant we can load to SSE register w/o using memory. */ int standard_sse_constant_p (rtx x) { - if (x == const0_rtx) + enum machine_mode mode = GET_MODE (x); + + if (x == const0_rtx || x == CONST0_RTX (GET_MODE (x))) return 1; - return (x == CONST0_RTX (GET_MODE (x))); + if (vector_all_ones_operand (x, mode) + && standard_sse_mode_p (mode)) + return TARGET_SSE2 ? 2 : -1; + + return 0; +} + +/* Return the opcode of the special instruction to be used to load + the constant X. */ + +const char * +standard_sse_constant_opcode (rtx insn, rtx x) +{ + switch (standard_sse_constant_p (x)) + { + case 1: + if (get_attr_mode (insn) == MODE_V4SF) + return "xorps\t%0, %0"; + else if (get_attr_mode (insn) == MODE_V2DF) + return "xorpd\t%0, %0"; + else + return "pxor\t%0, %0"; + case 2: + return "pcmpeqd\t%0, %0"; + } + gcc_unreachable (); } /* Returns 1 if OP contains a symbol reference */ @@ -4526,24 +4753,13 @@ symbolic_reference_mentioned_p (rtx op) body of a function. Do this only if the epilogue is simple, needing a couple of insns. Prior to reloading, we can't tell how many registers must be saved, so return 0 then. Return 0 if there is no frame - marker to de-allocate. - - If NON_SAVING_SETJMP is defined and true, then it is not possible - for the epilogue to be simple, so return 0. This is a special case - since NON_SAVING_SETJMP will not cause regs_ever_live to change - until final, but jump_optimize may need to know sooner if a - `return' is OK. */ + marker to de-allocate. */ int ix86_can_use_return_insn_p (void) { struct ix86_frame frame; -#ifdef NON_SAVING_SETJMP - if (NON_SAVING_SETJMP && current_function_calls_setjmp) - return 0; -#endif - if (! reload_completed || frame_pointer_needed) return 0; @@ -4557,196 +4773,6 @@ ix86_can_use_return_insn_p (void) return frame.to_allocate == 0 && frame.nregs == 0; } -/* Return 1 if VALUE can be stored in the sign extended immediate field. */ -int -x86_64_sign_extended_value (rtx value) -{ - switch (GET_CODE (value)) - { - /* CONST_DOUBLES never match, since HOST_BITS_PER_WIDE_INT is known - to be at least 32 and this all acceptable constants are - represented as CONST_INT. */ - case CONST_INT: - if (HOST_BITS_PER_WIDE_INT == 32) - return 1; - else - { - HOST_WIDE_INT val = trunc_int_for_mode (INTVAL (value), DImode); - return trunc_int_for_mode (val, SImode) == val; - } - break; - - /* For certain code models, the symbolic references are known to fit. - in CM_SMALL_PIC model we know it fits if it is local to the shared - library. Don't count TLS SYMBOL_REFs here, since they should fit - only if inside of UNSPEC handled below. */ - case SYMBOL_REF: - /* TLS symbols are not constant. */ - if (tls_symbolic_operand (value, Pmode)) - return false; - return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_KERNEL); - - /* For certain code models, the code is near as well. */ - case LABEL_REF: - return (ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM - || ix86_cmodel == CM_KERNEL); - - /* We also may accept the offsetted memory references in certain special - cases. */ - case CONST: - if (GET_CODE (XEXP (value, 0)) == UNSPEC) - switch (XINT (XEXP (value, 0), 1)) - { - case UNSPEC_GOTPCREL: - case UNSPEC_DTPOFF: - case UNSPEC_GOTNTPOFF: - case UNSPEC_NTPOFF: - return 1; - default: - break; - } - if (GET_CODE (XEXP (value, 0)) == PLUS) - { - rtx op1 = XEXP (XEXP (value, 0), 0); - rtx op2 = XEXP (XEXP (value, 0), 1); - HOST_WIDE_INT offset; - - if (ix86_cmodel == CM_LARGE) - return 0; - if (GET_CODE (op2) != CONST_INT) - return 0; - offset = trunc_int_for_mode (INTVAL (op2), DImode); - switch (GET_CODE (op1)) - { - case SYMBOL_REF: - /* For CM_SMALL assume that latest object is 16MB before - end of 31bits boundary. We may also accept pretty - large negative constants knowing that all objects are - in the positive half of address space. */ - if (ix86_cmodel == CM_SMALL - && offset < 16*1024*1024 - && trunc_int_for_mode (offset, SImode) == offset) - return 1; - /* For CM_KERNEL we know that all object resist in the - negative half of 32bits address space. We may not - accept negative offsets, since they may be just off - and we may accept pretty large positive ones. */ - if (ix86_cmodel == CM_KERNEL - && offset > 0 - && trunc_int_for_mode (offset, SImode) == offset) - return 1; - break; - case LABEL_REF: - /* These conditions are similar to SYMBOL_REF ones, just the - constraints for code models differ. */ - if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM) - && offset < 16*1024*1024 - && trunc_int_for_mode (offset, SImode) == offset) - return 1; - if (ix86_cmodel == CM_KERNEL - && offset > 0 - && trunc_int_for_mode (offset, SImode) == offset) - return 1; - break; - case UNSPEC: - switch (XINT (op1, 1)) - { - case UNSPEC_DTPOFF: - case UNSPEC_NTPOFF: - if (offset > 0 - && trunc_int_for_mode (offset, SImode) == offset) - return 1; - } - break; - default: - return 0; - } - } - return 0; - default: - return 0; - } -} - -/* Return 1 if VALUE can be stored in the zero extended immediate field. */ -int -x86_64_zero_extended_value (rtx value) -{ - switch (GET_CODE (value)) - { - case CONST_DOUBLE: - if (HOST_BITS_PER_WIDE_INT == 32) - return (GET_MODE (value) == VOIDmode - && !CONST_DOUBLE_HIGH (value)); - else - return 0; - case CONST_INT: - if (HOST_BITS_PER_WIDE_INT == 32) - return INTVAL (value) >= 0; - else - return !(INTVAL (value) & ~(HOST_WIDE_INT) 0xffffffff); - break; - - /* For certain code models, the symbolic references are known to fit. */ - case SYMBOL_REF: - /* TLS symbols are not constant. */ - if (tls_symbolic_operand (value, Pmode)) - return false; - return ix86_cmodel == CM_SMALL; - - /* For certain code models, the code is near as well. */ - case LABEL_REF: - return ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM; - - /* We also may accept the offsetted memory references in certain special - cases. */ - case CONST: - if (GET_CODE (XEXP (value, 0)) == PLUS) - { - rtx op1 = XEXP (XEXP (value, 0), 0); - rtx op2 = XEXP (XEXP (value, 0), 1); - - if (ix86_cmodel == CM_LARGE) - return 0; - switch (GET_CODE (op1)) - { - case SYMBOL_REF: - return 0; - /* For small code model we may accept pretty large positive - offsets, since one bit is available for free. Negative - offsets are limited by the size of NULL pointer area - specified by the ABI. */ - if (ix86_cmodel == CM_SMALL - && GET_CODE (op2) == CONST_INT - && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000 - && (trunc_int_for_mode (INTVAL (op2), SImode) - == INTVAL (op2))) - return 1; - /* ??? For the kernel, we may accept adjustment of - -0x10000000, since we know that it will just convert - negative address space to positive, but perhaps this - is not worthwhile. */ - break; - case LABEL_REF: - /* These conditions are similar to SYMBOL_REF ones, just the - constraints for code models differ. */ - if ((ix86_cmodel == CM_SMALL || ix86_cmodel == CM_MEDIUM) - && GET_CODE (op2) == CONST_INT - && trunc_int_for_mode (INTVAL (op2), DImode) > -0x10000 - && (trunc_int_for_mode (INTVAL (op2), SImode) - == INTVAL (op2))) - return 1; - break; - default: - return 0; - } - } - return 0; - default: - return 0; - } -} - /* Value should be nonzero if functions must have frame pointers. Zero means the frame pointer need not be set up (and parms may be accessed via the stack pointer) in functions that seem suitable. */ @@ -4768,7 +4794,8 @@ ix86_frame_pointer_required (void) the frame pointer by default. Turn it back on now if we've not got a leaf function. */ if (TARGET_OMIT_LEAF_FRAME_POINTER - && (!current_function_is_leaf)) + && (!current_function_is_leaf + || ix86_current_function_calls_tls_descriptor)) return 1; if (current_function_profile) @@ -4785,7 +4812,7 @@ ix86_setup_frame_addresses (void) cfun->machine->accesses_prev_frame = 1; } -#if defined(HAVE_GAS_HIDDEN) && defined(SUPPORTS_ONE_ONLY) +#if (defined(HAVE_GAS_HIDDEN) && (SUPPORTS_ONE_ONLY - 0)) || TARGET_MACHO # define USE_HIDDEN_LINKONCE 1 #else # define USE_HIDDEN_LINKONCE 0 @@ -4799,6 +4826,8 @@ static int pic_labels_used; static void get_pc_thunk_name (char name[32], unsigned int regno) { + gcc_assert (!TARGET_64BIT); + if (USE_HIDDEN_LINKONCE) sprintf (name, "__i686.get_pc_thunk.%s", reg_names[regno]); else @@ -4824,6 +4853,19 @@ ix86_file_end (void) get_pc_thunk_name (name, regno); +#if TARGET_MACHO + if (TARGET_MACHO) + { + switch_to_section (darwin_sections[text_coal_section]); + fputs ("\t.weak_definition\t", asm_out_file); + assemble_name (asm_out_file, name); + fputs ("\n\t.private_extern\t", asm_out_file); + assemble_name (asm_out_file, name); + fputs ("\n", asm_out_file); + ASM_OUTPUT_LABEL (asm_out_file, name); + } + else +#endif if (USE_HIDDEN_LINKONCE) { tree decl; @@ -4835,7 +4877,7 @@ ix86_file_end (void) DECL_ONE_ONLY (decl) = 1; (*targetm.asm_out.unique_section) (decl, 0); - named_section (decl, NULL, 0); + switch_to_section (get_named_section (decl, NULL, 0)); (*targetm.asm_out.globalize_label) (asm_out_file, name); fputs ("\t.hidden\t", asm_out_file); @@ -4845,7 +4887,7 @@ ix86_file_end (void) } else { - text_section (); + switch_to_section (text_section); ASM_OUTPUT_LABEL (asm_out_file, name); } @@ -4862,7 +4904,7 @@ ix86_file_end (void) /* Emit code for the SET_GOT patterns. */ const char * -output_set_got (rtx dest) +output_set_got (rtx dest, rtx label ATTRIBUTE_UNUSED) { rtx xops[3]; @@ -4871,7 +4913,7 @@ output_set_got (rtx dest) if (! TARGET_DEEP_BRANCH_PREDICTION || !flag_pic) { - xops[2] = gen_rtx_LABEL_REF (Pmode, gen_label_rtx ()); + xops[2] = gen_rtx_LABEL_REF (Pmode, label ? label : gen_label_rtx ()); if (!flag_pic) output_asm_insn ("mov{l}\t{%2, %0|%0, %2}", xops); @@ -4879,10 +4921,12 @@ output_set_got (rtx dest) output_asm_insn ("call\t%a2", xops); #if TARGET_MACHO - /* Output the "canonical" label name ("Lxx$pb") here too. This - is what will be referred to by the Mach-O PIC subsystem. */ - ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ()); + /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This + is what will be referenced by the Mach-O PIC subsystem. */ + if (!label) + ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ()); #endif + (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (XEXP (xops[2], 0))); @@ -4898,11 +4942,23 @@ output_set_got (rtx dest) xops[2] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name)); xops[2] = gen_rtx_MEM (QImode, xops[2]); output_asm_insn ("call\t%X2", xops); + /* Output the Mach-O "canonical" label name ("Lxx$pb") here too. This + is what will be referenced by the Mach-O PIC subsystem. */ +#if TARGET_MACHO + if (!label) + ASM_OUTPUT_LABEL (asm_out_file, machopic_function_base_name ()); + else + targetm.asm_out.internal_label (asm_out_file, "L", + CODE_LABEL_NUMBER (label)); +#endif } + if (TARGET_MACHO) + return ""; + if (!flag_pic || TARGET_DEEP_BRANCH_PREDICTION) output_asm_insn ("add{l}\t{%1, %0|%0, %1}", xops); - else if (!TARGET_MACHO) + else output_asm_insn ("add{l}\t{%1+[.-%a2], %0|%0, %1+(.-%a2)}", xops); return ""; @@ -4926,7 +4982,8 @@ gen_push (rtx arg) static unsigned int ix86_select_alt_pic_regnum (void) { - if (current_function_is_leaf && !current_function_profile) + if (current_function_is_leaf && !current_function_profile + && !ix86_current_function_calls_tls_descriptor) { int i; for (i = 2; i >= 0; --i) @@ -4966,6 +5023,10 @@ ix86_save_reg (unsigned int regno, int maybe_eh_return) } } + if (cfun->machine->force_align_arg_pointer + && regno == REGNO (cfun->machine->force_align_arg_pointer)) + return 1; + return (regs_ever_live[regno] && !call_used_regs[regno] && !fixed_regs[regno] @@ -5002,14 +5063,13 @@ ix86_initial_elimination_offset (int from, int to) return frame.hard_frame_pointer_offset - frame.frame_pointer_offset; else { - if (to != STACK_POINTER_REGNUM) - abort (); - else if (from == ARG_POINTER_REGNUM) + gcc_assert (to == STACK_POINTER_REGNUM); + + if (from == ARG_POINTER_REGNUM) return frame.stack_pointer_offset; - else if (from != FRAME_POINTER_REGNUM) - abort (); - else - return frame.stack_pointer_offset - frame.frame_pointer_offset; + + gcc_assert (from == FRAME_POINTER_REGNUM); + return frame.stack_pointer_offset - frame.frame_pointer_offset; } } @@ -5019,17 +5079,20 @@ static void ix86_compute_frame_layout (struct ix86_frame *frame) { HOST_WIDE_INT total_size; - int stack_alignment_needed = cfun->stack_alignment_needed / BITS_PER_UNIT; + unsigned int stack_alignment_needed; HOST_WIDE_INT offset; - int preferred_alignment = cfun->preferred_stack_boundary / BITS_PER_UNIT; + unsigned int preferred_alignment; HOST_WIDE_INT size = get_frame_size (); frame->nregs = ix86_nsaved_regs (); total_size = size; + stack_alignment_needed = cfun->stack_alignment_needed / BITS_PER_UNIT; + preferred_alignment = cfun->preferred_stack_boundary / BITS_PER_UNIT; + /* During reload iteration the amount of registers saved can change. Recompute the value as needed. Do not recompute when amount of registers - didn't change as reload does mutiple calls to the function and does not + didn't change as reload does multiple calls to the function and does not expect the decision to change within single iteration. */ if (!optimize_size && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs) @@ -5073,14 +5136,11 @@ ix86_compute_frame_layout (struct ix86_frame *frame) preferred_alignment, since i386 port is the only using those features that may break easily. */ - if (size && !stack_alignment_needed) - abort (); - if (preferred_alignment < STACK_BOUNDARY / BITS_PER_UNIT) - abort (); - if (preferred_alignment > PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT) - abort (); - if (stack_alignment_needed > PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT) - abort (); + gcc_assert (!size || stack_alignment_needed); + gcc_assert (preferred_alignment >= STACK_BOUNDARY / BITS_PER_UNIT); + gcc_assert (preferred_alignment <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT); + gcc_assert (stack_alignment_needed + <= PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT); if (stack_alignment_needed < STACK_BOUNDARY / BITS_PER_UNIT) stack_alignment_needed = STACK_BOUNDARY / BITS_PER_UNIT; @@ -5114,7 +5174,8 @@ ix86_compute_frame_layout (struct ix86_frame *frame) expander assumes that last current_function_outgoing_args_size of stack frame are unused. */ if (ACCUMULATE_OUTGOING_ARGS - && (!current_function_is_leaf || current_function_calls_alloca)) + && (!current_function_is_leaf || current_function_calls_alloca + || ix86_current_function_calls_tls_descriptor)) { offset += current_function_outgoing_args_size; frame->outgoing_arguments_size = current_function_outgoing_args_size; @@ -5124,7 +5185,8 @@ ix86_compute_frame_layout (struct ix86_frame *frame) /* Align stack boundary. Only needed if we're calling another function or using alloca. */ - if (!current_function_is_leaf || current_function_calls_alloca) + if (!current_function_is_leaf || current_function_calls_alloca + || ix86_current_function_calls_tls_descriptor) frame->padding2 = ((offset + preferred_alignment - 1) & -preferred_alignment) - offset; else @@ -5145,7 +5207,8 @@ ix86_compute_frame_layout (struct ix86_frame *frame) frame->save_regs_using_mov = false; if (TARGET_RED_ZONE && current_function_sp_is_unchanging - && current_function_is_leaf) + && current_function_is_leaf + && !ix86_current_function_calls_tls_descriptor) { frame->red_zone_size = frame->to_allocate; if (frame->save_regs_using_mov) @@ -5178,10 +5241,10 @@ ix86_compute_frame_layout (struct ix86_frame *frame) static void ix86_emit_save_regs (void) { - int regno; + unsigned int regno; rtx insn; - for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno--) + for (regno = FIRST_PSEUDO_REGISTER; regno-- > 0; ) if (ix86_save_reg (regno, true)) { insn = emit_insn (gen_push (gen_rtx_REG (Pmode, regno))); @@ -5194,7 +5257,7 @@ ix86_emit_save_regs (void) static void ix86_emit_save_regs_using_mov (rtx pointer, HOST_WIDE_INT offset) { - int regno; + unsigned int regno; rtx insn; for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) @@ -5230,8 +5293,7 @@ pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style) epilogue and used after the epilogue. ATM indirect sibcall shouldn't be used together with huge frame sizes in one function because of the frame_size check in sibcall.c. */ - if (style == 0) - abort (); + gcc_assert (style); r11 = gen_rtx_REG (DImode, FIRST_REX_INT_REG + 3 /* R11 */); insn = emit_insn (gen_rtx_SET (DImode, r11, offset)); if (style < 0) @@ -5243,6 +5305,64 @@ pro_epilogue_adjust_stack (rtx dest, rtx src, rtx offset, int style) RTX_FRAME_RELATED_P (insn) = 1; } +/* Handle the TARGET_INTERNAL_ARG_POINTER hook. */ + +static rtx +ix86_internal_arg_pointer (void) +{ + bool has_force_align_arg_pointer = + (0 != lookup_attribute (ix86_force_align_arg_pointer_string, + TYPE_ATTRIBUTES (TREE_TYPE (current_function_decl)))); + if ((FORCE_PREFERRED_STACK_BOUNDARY_IN_MAIN + && DECL_NAME (current_function_decl) + && MAIN_NAME_P (DECL_NAME (current_function_decl)) + && DECL_FILE_SCOPE_P (current_function_decl)) + || ix86_force_align_arg_pointer + || has_force_align_arg_pointer) + { + /* Nested functions can't realign the stack due to a register + conflict. */ + if (DECL_CONTEXT (current_function_decl) + && TREE_CODE (DECL_CONTEXT (current_function_decl)) == FUNCTION_DECL) + { + if (ix86_force_align_arg_pointer) + warning (0, "-mstackrealign ignored for nested functions"); + if (has_force_align_arg_pointer) + error ("%s not supported for nested functions", + ix86_force_align_arg_pointer_string); + return virtual_incoming_args_rtx; + } + cfun->machine->force_align_arg_pointer = gen_rtx_REG (Pmode, 2); + return copy_to_reg (cfun->machine->force_align_arg_pointer); + } + else + return virtual_incoming_args_rtx; +} + +/* Handle the TARGET_DWARF_HANDLE_FRAME_UNSPEC hook. + This is called from dwarf2out.c to emit call frame instructions + for frame-related insns containing UNSPECs and UNSPEC_VOLATILEs. */ +static void +ix86_dwarf_handle_frame_unspec (const char *label, rtx pattern, int index) +{ + rtx unspec = SET_SRC (pattern); + gcc_assert (GET_CODE (unspec) == UNSPEC); + + switch (index) + { + case UNSPEC_REG_SAVE: + dwarf2out_reg_save_reg (label, XVECEXP (unspec, 0, 0), + SET_DEST (pattern)); + break; + case UNSPEC_DEF_CFA: + dwarf2out_def_cfa (label, REGNO (SET_DEST (pattern)), + INTVAL (XVECEXP (unspec, 0, 0))); + break; + default: + gcc_unreachable (); + } +} + /* Expand the prologue into a bunch of separate insns. */ void @@ -5255,6 +5375,52 @@ ix86_expand_prologue (void) ix86_compute_frame_layout (&frame); + if (cfun->machine->force_align_arg_pointer) + { + rtx x, y; + + /* Grab the argument pointer. */ + x = plus_constant (stack_pointer_rtx, 4); + y = cfun->machine->force_align_arg_pointer; + insn = emit_insn (gen_rtx_SET (VOIDmode, y, x)); + RTX_FRAME_RELATED_P (insn) = 1; + + /* The unwind info consists of two parts: install the fafp as the cfa, + and record the fafp as the "save register" of the stack pointer. + The later is there in order that the unwinder can see where it + should restore the stack pointer across the and insn. */ + x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, const0_rtx), UNSPEC_DEF_CFA); + x = gen_rtx_SET (VOIDmode, y, x); + RTX_FRAME_RELATED_P (x) = 1; + y = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, stack_pointer_rtx), + UNSPEC_REG_SAVE); + y = gen_rtx_SET (VOIDmode, cfun->machine->force_align_arg_pointer, y); + RTX_FRAME_RELATED_P (y) = 1; + x = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, x, y)); + x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL); + REG_NOTES (insn) = x; + + /* Align the stack. */ + emit_insn (gen_andsi3 (stack_pointer_rtx, stack_pointer_rtx, + GEN_INT (-16))); + + /* And here we cheat like madmen with the unwind info. We force the + cfa register back to sp+4, which is exactly what it was at the + start of the function. Re-pushing the return address results in + the return at the same spot relative to the cfa, and thus is + correct wrt the unwind info. */ + x = cfun->machine->force_align_arg_pointer; + x = gen_frame_mem (Pmode, plus_constant (x, -4)); + insn = emit_insn (gen_push (x)); + RTX_FRAME_RELATED_P (insn) = 1; + + x = GEN_INT (4); + x = gen_rtx_UNSPEC (VOIDmode, gen_rtvec (1, x), UNSPEC_DEF_CFA); + x = gen_rtx_SET (VOIDmode, stack_pointer_rtx, x); + x = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, x, NULL); + REG_NOTES (insn) = x; + } + /* Note: AT&T enter does NOT have reversed args. Enter is probably slower on all targets. Also sdb doesn't like it. */ @@ -5291,9 +5457,9 @@ ix86_expand_prologue (void) /* Only valid for Win32. */ rtx eax = gen_rtx_REG (SImode, 0); bool eax_live = ix86_eax_live_at_start_p (); + rtx t; - if (TARGET_64BIT) - abort (); + gcc_assert (!TARGET_64BIT); if (eax_live) { @@ -5301,15 +5467,24 @@ ix86_expand_prologue (void) allocate -= 4; } - insn = emit_move_insn (eax, GEN_INT (allocate)); - RTX_FRAME_RELATED_P (insn) = 1; + emit_move_insn (eax, GEN_INT (allocate)); insn = emit_insn (gen_allocate_stack_worker (eax)); RTX_FRAME_RELATED_P (insn) = 1; + t = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-allocate)); + t = gen_rtx_SET (VOIDmode, stack_pointer_rtx, t); + REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, + t, REG_NOTES (insn)); if (eax_live) { - rtx t = plus_constant (stack_pointer_rtx, allocate); + if (frame_pointer_needed) + t = plus_constant (hard_frame_pointer_rtx, + allocate + - frame.to_allocate + - frame.nregs * UNITS_PER_WORD); + else + t = plus_constant (stack_pointer_rtx, allocate); emit_move_insn (eax, gen_rtx_MEM (SImode, t)); } } @@ -5338,7 +5513,10 @@ ix86_expand_prologue (void) if (pic_reg_used) { - insn = emit_insn (gen_set_got (pic_offset_table_rtx)); + if (TARGET_64BIT) + insn = emit_insn (gen_set_got_rex64 (pic_offset_table_rtx)); + else + insn = emit_insn (gen_set_got (pic_offset_table_rtx)); /* Even with accurate pre-reload life analysis, we can wind up deleting all references to the pic register after reload. @@ -5490,8 +5668,7 @@ ix86_expand_epilogue (int style) pop the registers. */ if (!sp_valid) { - if (!frame_pointer_needed) - abort (); + gcc_assert (frame_pointer_needed); pro_epilogue_adjust_stack (stack_pointer_rtx, hard_frame_pointer_rtx, GEN_INT (offset), style); @@ -5521,6 +5698,13 @@ ix86_expand_epilogue (int style) } } + if (cfun->machine->force_align_arg_pointer) + { + emit_insn (gen_addsi3 (stack_pointer_rtx, + cfun->machine->force_align_arg_pointer, + GEN_INT (-4))); + } + /* Sibcall epilogues don't want a return instruction. */ if (style == 0) return; @@ -5538,8 +5722,7 @@ ix86_expand_epilogue (int style) rtx ecx = gen_rtx_REG (SImode, 2); /* There is no "pascal" calling convention in 64bit ABI. */ - if (TARGET_64BIT) - abort (); + gcc_assert (!TARGET_64BIT); emit_insn (gen_popsi1 (ecx)); emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, popc)); @@ -5560,6 +5743,23 @@ ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, { if (pic_offset_table_rtx) REGNO (pic_offset_table_rtx) = REAL_PIC_OFFSET_TABLE_REGNUM; +#if TARGET_MACHO + /* Mach-O doesn't support labels at the end of objects, so if + it looks like we might want one, insert a NOP. */ + { + rtx insn = get_last_insn (); + while (insn + && NOTE_P (insn) + && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL) + insn = PREV_INSN (insn); + if (insn + && (LABEL_P (insn) + || (NOTE_P (insn) + && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL))) + fputs ("\tnop\n", file); + } +#endif + } /* Extract the parts of an RTL expression that is a valid memory address @@ -5567,12 +5767,11 @@ ix86_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, grossly off. Return -1 if the address contains ASHIFT, so it is not strictly valid, but still used for computing length of lea instruction. */ -static int +int ix86_decompose_address (rtx addr, struct ix86_address *out) { - rtx base = NULL_RTX; - rtx index = NULL_RTX; - rtx disp = NULL_RTX; + rtx base = NULL_RTX, index = NULL_RTX, disp = NULL_RTX; + rtx base_reg, index_reg; HOST_WIDE_INT scale = 1; rtx scale_rtx = NULL_RTX; int retval = 1; @@ -5674,34 +5873,37 @@ ix86_decompose_address (rtx addr, struct ix86_address *out) scale = INTVAL (scale_rtx); } + base_reg = base && GET_CODE (base) == SUBREG ? SUBREG_REG (base) : base; + index_reg = index && GET_CODE (index) == SUBREG ? SUBREG_REG (index) : index; + /* Allow arg pointer and stack pointer as index if there is not scaling. */ - if (base && index && scale == 1 - && (index == arg_pointer_rtx - || index == frame_pointer_rtx - || (REG_P (index) && REGNO (index) == STACK_POINTER_REGNUM))) + if (base_reg && index_reg && scale == 1 + && (index_reg == arg_pointer_rtx + || index_reg == frame_pointer_rtx + || (REG_P (index_reg) && REGNO (index_reg) == STACK_POINTER_REGNUM))) { - rtx tmp = base; - base = index; - index = tmp; + rtx tmp; + tmp = base, base = index, index = tmp; + tmp = base_reg, base_reg = index_reg, index_reg = tmp; } /* Special case: %ebp cannot be encoded as a base without a displacement. */ - if ((base == hard_frame_pointer_rtx - || base == frame_pointer_rtx - || base == arg_pointer_rtx) && !disp) + if ((base_reg == hard_frame_pointer_rtx + || base_reg == frame_pointer_rtx + || base_reg == arg_pointer_rtx) && !disp) disp = const0_rtx; /* Special case: on K6, [%esi] makes the instruction vector decoded. Avoid this by transforming to [%esi+0]. */ if (ix86_tune == PROCESSOR_K6 && !optimize_size - && base && !index && !disp - && REG_P (base) - && REGNO_REG_CLASS (REGNO (base)) == SIREG) + && base_reg && !index_reg && !disp + && REG_P (base_reg) + && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG) disp = const0_rtx; /* Special case: encode reg+reg instead of reg*2. */ if (!base && index && scale && scale == 2) - base = index, scale = 1; + base = index, base_reg = index_reg, scale = 1; /* Special case: scaling cannot be encoded without base or displacement. */ if (!base && !disp && index && scale != 1) @@ -5726,9 +5928,14 @@ ix86_address_cost (rtx x) { struct ix86_address parts; int cost = 1; + int ok = ix86_decompose_address (x, &parts); + + gcc_assert (ok); - if (!ix86_decompose_address (x, &parts)) - abort (); + if (parts.base && GET_CODE (parts.base) == SUBREG) + parts.base = SUBREG_REG (parts.base); + if (parts.index && GET_CODE (parts.index) == SUBREG) + parts.index = SUBREG_REG (parts.index); /* More complex memory references are better. */ if (parts.disp && parts.disp != const0_rtx) @@ -5814,6 +6021,28 @@ ix86_find_base_term (rtx x) return term; } + +/* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O as + this is used for to form addresses to local data when -fPIC is in + use. */ + +static bool +darwin_local_data_pic (rtx disp) +{ + if (GET_CODE (disp) == MINUS) + { + if (GET_CODE (XEXP (disp, 0)) == LABEL_REF + || GET_CODE (XEXP (disp, 0)) == SYMBOL_REF) + if (GET_CODE (XEXP (disp, 1)) == SYMBOL_REF) + { + const char *sym_name = XSTR (XEXP (disp, 1), 0); + if (! strcmp (sym_name, "<pic base>")) + return true; + } + } + + return false; +} /* Determine if a given RTX is a valid constant. We already know this satisfies CONSTANT_P. */ @@ -5833,30 +6062,53 @@ legitimate_constant_p (rtx x) x = XEXP (x, 0); } + if (TARGET_MACHO && darwin_local_data_pic (x)) + return true; + /* Only some unspecs are valid as "constants". */ if (GET_CODE (x) == UNSPEC) switch (XINT (x, 1)) { + case UNSPEC_GOTOFF: + return TARGET_64BIT; case UNSPEC_TPOFF: case UNSPEC_NTPOFF: - return local_exec_symbolic_operand (XVECEXP (x, 0, 0), Pmode); + x = XVECEXP (x, 0, 0); + return (GET_CODE (x) == SYMBOL_REF + && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC); case UNSPEC_DTPOFF: - return local_dynamic_symbolic_operand (XVECEXP (x, 0, 0), Pmode); + x = XVECEXP (x, 0, 0); + return (GET_CODE (x) == SYMBOL_REF + && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC); default: return false; } /* We must have drilled down to a symbol. */ - if (!symbolic_operand (x, Pmode)) + if (GET_CODE (x) == LABEL_REF) + return true; + if (GET_CODE (x) != SYMBOL_REF) return false; /* FALLTHRU */ case SYMBOL_REF: /* TLS symbols are never valid. */ - if (tls_symbolic_operand (x, Pmode)) + if (SYMBOL_REF_TLS_MODEL (x)) return false; break; + case CONST_DOUBLE: + if (GET_MODE (x) == TImode + && x != CONST0_RTX (TImode) + && !TARGET_64BIT) + return false; + break; + + case CONST_VECTOR: + if (x == CONST0_RTX (GET_MODE (x))) + return true; + return false; + default: break; } @@ -5872,6 +6124,17 @@ legitimate_constant_p (rtx x) static bool ix86_cannot_force_const_mem (rtx x) { + /* We can always put integral constants and vectors in memory. */ + switch (GET_CODE (x)) + { + case CONST_INT: + case CONST_DOUBLE: + case CONST_VECTOR: + return false; + + default: + break; + } return !legitimate_constant_p (x); } @@ -5896,13 +6159,20 @@ legitimate_pic_operand_p (rtx x) { case CONST: inner = XEXP (x, 0); + if (GET_CODE (inner) == PLUS + && GET_CODE (XEXP (inner, 1)) == CONST_INT) + inner = XEXP (inner, 0); /* Only some unspecs are valid as "constants". */ if (GET_CODE (inner) == UNSPEC) switch (XINT (inner, 1)) { + case UNSPEC_GOTOFF: + return TARGET_64BIT; case UNSPEC_TPOFF: - return local_exec_symbolic_operand (XVECEXP (inner, 0, 0), Pmode); + x = XVECEXP (inner, 0, 0); + return (GET_CODE (x) == SYMBOL_REF + && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC); default: return false; } @@ -5929,32 +6199,38 @@ legitimate_pic_address_disp_p (rtx disp) when they are not dynamic symbols. */ if (TARGET_64BIT) { - /* TLS references should always be enclosed in UNSPEC. */ - if (tls_symbolic_operand (disp, GET_MODE (disp))) - return 0; - if (GET_CODE (disp) == SYMBOL_REF - && ix86_cmodel == CM_SMALL_PIC - && SYMBOL_REF_LOCAL_P (disp)) - return 1; - if (GET_CODE (disp) == LABEL_REF) - return 1; - if (GET_CODE (disp) == CONST - && GET_CODE (XEXP (disp, 0)) == PLUS) + rtx op0 = disp, op1; + + switch (GET_CODE (disp)) { - rtx op0 = XEXP (XEXP (disp, 0), 0); - rtx op1 = XEXP (XEXP (disp, 0), 1); + case LABEL_REF: + return true; + case CONST: + if (GET_CODE (XEXP (disp, 0)) != PLUS) + break; + op0 = XEXP (XEXP (disp, 0), 0); + op1 = XEXP (XEXP (disp, 0), 1); + if (GET_CODE (op1) != CONST_INT + || INTVAL (op1) >= 16*1024*1024 + || INTVAL (op1) < -16*1024*1024) + break; + if (GET_CODE (op0) == LABEL_REF) + return true; + if (GET_CODE (op0) != SYMBOL_REF) + break; + /* FALLTHRU */ + + case SYMBOL_REF: /* TLS references should always be enclosed in UNSPEC. */ - if (tls_symbolic_operand (op0, GET_MODE (op0))) - return 0; - if (((GET_CODE (op0) == SYMBOL_REF - && ix86_cmodel == CM_SMALL_PIC - && SYMBOL_REF_LOCAL_P (op0)) - || GET_CODE (op0) == LABEL_REF) - && GET_CODE (op1) == CONST_INT - && INTVAL (op1) < 16*1024*1024 - && INTVAL (op1) >= -16*1024*1024) - return 1; + if (SYMBOL_REF_TLS_MODEL (op0)) + return false; + if (!SYMBOL_REF_FAR_ADDR_P (op0) && SYMBOL_REF_LOCAL_P (op0)) + return true; + break; + + default: + break; } } if (GET_CODE (disp) != CONST) @@ -5966,7 +6242,8 @@ legitimate_pic_address_disp_p (rtx disp) /* We are unsafe to allow PLUS expressions. This limit allowed distance of GOT tables. We should not need these anyway. */ if (GET_CODE (disp) != UNSPEC - || XINT (disp, 1) != UNSPEC_GOTPCREL) + || (XINT (disp, 1) != UNSPEC_GOTPCREL + && XINT (disp, 1) != UNSPEC_GOTOFF)) return 0; if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF @@ -5984,18 +6261,8 @@ legitimate_pic_address_disp_p (rtx disp) saw_plus = true; } - /* Allow {LABEL | SYMBOL}_REF - SYMBOL_REF-FOR-PICBASE for Mach-O. */ - if (TARGET_MACHO && GET_CODE (disp) == MINUS) - { - if (GET_CODE (XEXP (disp, 0)) == LABEL_REF - || GET_CODE (XEXP (disp, 0)) == SYMBOL_REF) - if (GET_CODE (XEXP (disp, 1)) == SYMBOL_REF) - { - const char *sym_name = XSTR (XEXP (disp, 1), 0); - if (! strcmp (sym_name, "<pic base>")) - return 1; - } - } + if (TARGET_MACHO && darwin_local_data_pic (disp)) + return 1; if (GET_CODE (disp) != UNSPEC) return 0; @@ -6007,8 +6274,12 @@ legitimate_pic_address_disp_p (rtx disp) return false; return GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF; case UNSPEC_GOTOFF: - if (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF - || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF) + /* Refuse GOTOFF in 64bit mode since it is always 64bit when used. + While ABI specify also 32bit relocation but we don't produce it in + small PIC model at all. */ + if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF + || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF) + && !TARGET_64BIT) return local_symbolic_operand (XVECEXP (disp, 0, 0), Pmode); return false; case UNSPEC_GOTTPOFF: @@ -6016,11 +6287,17 @@ legitimate_pic_address_disp_p (rtx disp) case UNSPEC_INDNTPOFF: if (saw_plus) return false; - return initial_exec_symbolic_operand (XVECEXP (disp, 0, 0), Pmode); + disp = XVECEXP (disp, 0, 0); + return (GET_CODE (disp) == SYMBOL_REF + && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC); case UNSPEC_NTPOFF: - return local_exec_symbolic_operand (XVECEXP (disp, 0, 0), Pmode); + disp = XVECEXP (disp, 0, 0); + return (GET_CODE (disp) == SYMBOL_REF + && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC); case UNSPEC_DTPOFF: - return local_dynamic_symbolic_operand (XVECEXP (disp, 0, 0), Pmode); + disp = XVECEXP (disp, 0, 0); + return (GET_CODE (disp) == SYMBOL_REF + && SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC); } return 0; @@ -6064,15 +6341,23 @@ legitimate_address_p (enum machine_mode mode, rtx addr, int strict) /* Validate base register. - Don't allow SUBREG's here, it can lead to spill failures when the base - is one word out of a two word structure, which is represented internally - as a DImode int. */ + Don't allow SUBREG's that span more than a word here. It can lead to spill + failures when the base is one word out of a two word structure, which is + represented internally as a DImode int. */ if (base) { + rtx reg; reason_rtx = base; - if (GET_CODE (base) != REG) + if (REG_P (base)) + reg = base; + else if (GET_CODE (base) == SUBREG + && REG_P (SUBREG_REG (base)) + && GET_MODE_SIZE (GET_MODE (SUBREG_REG (base))) + <= UNITS_PER_WORD) + reg = SUBREG_REG (base); + else { reason = "base is not a register"; goto report_error; @@ -6084,8 +6369,8 @@ legitimate_address_p (enum machine_mode mode, rtx addr, int strict) goto report_error; } - if ((strict && ! REG_OK_FOR_BASE_STRICT_P (base)) - || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (base))) + if ((strict && ! REG_OK_FOR_BASE_STRICT_P (reg)) + || (! strict && ! REG_OK_FOR_BASE_NONSTRICT_P (reg))) { reason = "base is not valid"; goto report_error; @@ -6094,15 +6379,21 @@ legitimate_address_p (enum machine_mode mode, rtx addr, int strict) /* Validate index register. - Don't allow SUBREG's here, it can lead to spill failures when the index - is one word out of a two word structure, which is represented internally - as a DImode int. */ + Don't allow SUBREG's that span more than a word here -- same as above. */ if (index) { + rtx reg; reason_rtx = index; - if (GET_CODE (index) != REG) + if (REG_P (index)) + reg = index; + else if (GET_CODE (index) == SUBREG + && REG_P (SUBREG_REG (index)) + && GET_MODE_SIZE (GET_MODE (SUBREG_REG (index))) + <= UNITS_PER_WORD) + reg = SUBREG_REG (index); + else { reason = "index is not a register"; goto report_error; @@ -6114,8 +6405,8 @@ legitimate_address_p (enum machine_mode mode, rtx addr, int strict) goto report_error; } - if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (index)) - || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (index))) + if ((strict && ! REG_OK_FOR_INDEX_STRICT_P (reg)) + || (! strict && ! REG_OK_FOR_INDEX_NONSTRICT_P (reg))) { reason = "index is not valid"; goto report_error; @@ -6148,11 +6439,19 @@ legitimate_address_p (enum machine_mode mode, rtx addr, int strict) && GET_CODE (XEXP (disp, 0)) == UNSPEC) switch (XINT (XEXP (disp, 0), 1)) { + /* Refuse GOTOFF and GOT in 64bit mode since it is always 64bit when + used. While ABI specify also 32bit relocations, we don't produce + them at all and use IP relative instead. */ case UNSPEC_GOT: case UNSPEC_GOTOFF: + gcc_assert (flag_pic); + if (!TARGET_64BIT) + goto is_legitimate_pic; + reason = "64bit address unspec"; + goto report_error; + case UNSPEC_GOTPCREL: - if (!flag_pic) - abort (); + gcc_assert (flag_pic); goto is_legitimate_pic; case UNSPEC_GOTTPOFF: @@ -6167,12 +6466,16 @@ legitimate_address_p (enum machine_mode mode, rtx addr, int strict) goto report_error; } - else if (flag_pic && (SYMBOLIC_CONST (disp) + else if (SYMBOLIC_CONST (disp) + && (flag_pic + || (TARGET_MACHO #if TARGET_MACHO - && !machopic_operand_p (disp) + && MACHOPIC_INDIRECT + && !machopic_operand_p (disp) #endif - )) + ))) { + is_legitimate_pic: if (TARGET_64BIT && (index || base)) { @@ -6226,7 +6529,8 @@ legitimate_address_p (enum machine_mode mode, rtx addr, int strict) reason = "displacement is not constant"; goto report_error; } - else if (TARGET_64BIT && !x86_64_sign_extended_value (disp)) + else if (TARGET_64BIT + && !x86_64_immediate_operand (disp, VOIDmode)) { reason = "displacement is out of range"; goto report_error; @@ -6247,7 +6551,7 @@ legitimate_address_p (enum machine_mode mode, rtx addr, int strict) return FALSE; } -/* Return an unique alias set for the GOT. */ +/* Return a unique alias set for the GOT. */ static HOST_WIDE_INT ix86_GOT_alias_set (void) @@ -6276,7 +6580,7 @@ ix86_GOT_alias_set (void) GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC reg also appears in the address. */ -rtx +static rtx legitimize_pic_address (rtx orig, rtx reg) { rtx addr = orig; @@ -6284,14 +6588,51 @@ legitimize_pic_address (rtx orig, rtx reg) rtx base; #if TARGET_MACHO - if (reg == 0) - reg = gen_reg_rtx (Pmode); - /* Use the generic Mach-O PIC machinery. */ - return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg); + if (TARGET_MACHO && !TARGET_64BIT) + { + if (reg == 0) + reg = gen_reg_rtx (Pmode); + /* Use the generic Mach-O PIC machinery. */ + return machopic_legitimize_pic_address (orig, GET_MODE (orig), reg); + } #endif if (TARGET_64BIT && legitimate_pic_address_disp_p (addr)) new = addr; + else if (TARGET_64BIT + && ix86_cmodel != CM_SMALL_PIC + && local_symbolic_operand (addr, Pmode)) + { + rtx tmpreg; + /* This symbol may be referenced via a displacement from the PIC + base address (@GOTOFF). */ + + if (reload_in_progress) + regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1; + if (GET_CODE (addr) == CONST) + addr = XEXP (addr, 0); + if (GET_CODE (addr) == PLUS) + { + new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, XEXP (addr, 0)), UNSPEC_GOTOFF); + new = gen_rtx_PLUS (Pmode, new, XEXP (addr, 1)); + } + else + new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTOFF); + new = gen_rtx_CONST (Pmode, new); + if (!reg) + tmpreg = gen_reg_rtx (Pmode); + else + tmpreg = reg; + emit_move_insn (tmpreg, new); + + if (reg != 0) + { + new = expand_simple_binop (Pmode, PLUS, reg, pic_offset_table_rtx, + tmpreg, 1, OPTAB_DIRECT); + new = reg; + } + else new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, tmpreg); + } else if (!TARGET_64BIT && local_symbolic_operand (addr, Pmode)) { /* This symbol may be referenced via a displacement from the PIC @@ -6317,14 +6658,13 @@ legitimize_pic_address (rtx orig, rtx reg) new = reg; } } - else if (GET_CODE (addr) == SYMBOL_REF) + else if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0) { if (TARGET_64BIT) { new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOTPCREL); new = gen_rtx_CONST (Pmode, new); - new = gen_rtx_MEM (Pmode, new); - RTX_UNCHANGING_P (new) = 1; + new = gen_const_mem (Pmode, new); set_mem_alias_set (new, ix86_GOT_alias_set ()); if (reg == 0) @@ -6345,8 +6685,7 @@ legitimize_pic_address (rtx orig, rtx reg) new = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_GOT); new = gen_rtx_CONST (Pmode, new); new = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new); - new = gen_rtx_MEM (Pmode, new); - RTX_UNCHANGING_P (new) = 1; + new = gen_const_mem (Pmode, new); set_mem_alias_set (new, ix86_GOT_alias_set ()); if (reg == 0) @@ -6357,7 +6696,18 @@ legitimize_pic_address (rtx orig, rtx reg) } else { - if (GET_CODE (addr) == CONST) + if (GET_CODE (addr) == CONST_INT + && !x86_64_immediate_operand (addr, VOIDmode)) + { + if (reg) + { + emit_move_insn (reg, addr); + new = reg; + } + else + new = force_reg (Pmode, addr); + } + else if (GET_CODE (addr) == CONST) { addr = XEXP (addr, 0); @@ -6368,8 +6718,7 @@ legitimize_pic_address (rtx orig, rtx reg) || (GET_CODE (addr) == PLUS && GET_CODE (XEXP (addr, 0)) == UNSPEC)) return orig; - if (GET_CODE (addr) != PLUS) - abort (); + gcc_assert (GET_CODE (addr) == PLUS); } if (GET_CODE (addr) == PLUS) { @@ -6400,7 +6749,11 @@ legitimize_pic_address (rtx orig, rtx reg) { if (INTVAL (op1) < -16*1024*1024 || INTVAL (op1) >= 16*1024*1024) - new = gen_rtx_PLUS (Pmode, op0, force_reg (Pmode, op1)); + { + if (!x86_64_immediate_operand (op1, Pmode)) + op1 = force_reg (Pmode, op1); + new = gen_rtx_PLUS (Pmode, force_reg (Pmode, op0), op1); + } } } else @@ -6451,14 +6804,16 @@ get_thread_pointer (int to_reg) static rtx legitimize_tls_address (rtx x, enum tls_model model, int for_mov) { - rtx dest, base, off, pic; + rtx dest, base, off, pic, tp; int type; switch (model) { case TLS_MODEL_GLOBAL_DYNAMIC: dest = gen_reg_rtx (Pmode); - if (TARGET_64BIT) + tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0; + + if (TARGET_64BIT && ! TARGET_GNU2_TLS) { rtx rax = gen_rtx_REG (Pmode, 0), insns; @@ -6469,13 +6824,24 @@ legitimize_tls_address (rtx x, enum tls_model model, int for_mov) emit_libcall_block (insns, dest, rax, x); } + else if (TARGET_64BIT && TARGET_GNU2_TLS) + emit_insn (gen_tls_global_dynamic_64 (dest, x)); else emit_insn (gen_tls_global_dynamic_32 (dest, x)); + + if (TARGET_GNU2_TLS) + { + dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, tp, dest)); + + set_unique_reg_note (get_last_insn (), REG_EQUIV, x); + } break; case TLS_MODEL_LOCAL_DYNAMIC: base = gen_reg_rtx (Pmode); - if (TARGET_64BIT) + tp = TARGET_GNU2_TLS ? get_thread_pointer (1) : 0; + + if (TARGET_64BIT && ! TARGET_GNU2_TLS) { rtx rax = gen_rtx_REG (Pmode, 0), insns, note; @@ -6488,13 +6854,32 @@ legitimize_tls_address (rtx x, enum tls_model model, int for_mov) note = gen_rtx_EXPR_LIST (VOIDmode, ix86_tls_get_addr (), note); emit_libcall_block (insns, base, rax, note); } + else if (TARGET_64BIT && TARGET_GNU2_TLS) + emit_insn (gen_tls_local_dynamic_base_64 (base)); else emit_insn (gen_tls_local_dynamic_base_32 (base)); + if (TARGET_GNU2_TLS) + { + rtx x = ix86_tls_module_base (); + + set_unique_reg_note (get_last_insn (), REG_EQUIV, + gen_rtx_MINUS (Pmode, x, tp)); + } + off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), UNSPEC_DTPOFF); off = gen_rtx_CONST (Pmode, off); - return gen_rtx_PLUS (Pmode, base, off); + dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, off)); + + if (TARGET_GNU2_TLS) + { + dest = force_reg (Pmode, gen_rtx_PLUS (Pmode, dest, tp)); + + set_unique_reg_note (get_last_insn (), REG_EQUIV, x); + } + + break; case TLS_MODEL_INITIAL_EXEC: if (TARGET_64BIT) @@ -6507,9 +6892,9 @@ legitimize_tls_address (rtx x, enum tls_model model, int for_mov) if (reload_in_progress) regs_ever_live[PIC_OFFSET_TABLE_REGNUM] = 1; pic = pic_offset_table_rtx; - type = TARGET_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF; + type = TARGET_ANY_GNU_TLS ? UNSPEC_GOTNTPOFF : UNSPEC_GOTTPOFF; } - else if (!TARGET_GNU_TLS) + else if (!TARGET_ANY_GNU_TLS) { pic = gen_reg_rtx (Pmode); emit_insn (gen_set_got (pic)); @@ -6525,11 +6910,10 @@ legitimize_tls_address (rtx x, enum tls_model model, int for_mov) off = gen_rtx_CONST (Pmode, off); if (pic) off = gen_rtx_PLUS (Pmode, pic, off); - off = gen_rtx_MEM (Pmode, off); - RTX_UNCHANGING_P (off) = 1; + off = gen_const_mem (Pmode, off); set_mem_alias_set (off, ix86_GOT_alias_set ()); - if (TARGET_64BIT || TARGET_GNU_TLS) + if (TARGET_64BIT || TARGET_ANY_GNU_TLS) { base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS); off = force_reg (Pmode, off); @@ -6545,11 +6929,11 @@ legitimize_tls_address (rtx x, enum tls_model model, int for_mov) case TLS_MODEL_LOCAL_EXEC: off = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, x), - (TARGET_64BIT || TARGET_GNU_TLS) + (TARGET_64BIT || TARGET_ANY_GNU_TLS) ? UNSPEC_NTPOFF : UNSPEC_TPOFF); off = gen_rtx_CONST (Pmode, off); - if (TARGET_64BIT || TARGET_GNU_TLS) + if (TARGET_64BIT || TARGET_ANY_GNU_TLS) { base = get_thread_pointer (for_mov || !TARGET_TLS_DIRECT_SEG_REFS); return gen_rtx_PLUS (Pmode, base, off); @@ -6563,7 +6947,7 @@ legitimize_tls_address (rtx x, enum tls_model model, int for_mov) break; default: - abort (); + gcc_unreachable (); } return dest; @@ -6603,9 +6987,17 @@ legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode) debug_rtx (x); } - log = tls_symbolic_operand (x, mode); + log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0; if (log) return legitimize_tls_address (x, log, false); + if (GET_CODE (x) == CONST + && GET_CODE (XEXP (x, 0)) == PLUS + && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF + && (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0)))) + { + rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0), log, false); + return gen_rtx_PLUS (Pmode, t, XEXP (XEXP (x, 0), 1)); + } if (flag_pic && SYMBOLIC_CONST (x)) return legitimize_pic_address (x, 0); @@ -6613,9 +7005,10 @@ legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode) /* Canonicalize shifts by 0, 1, 2, 3 into multiply */ if (GET_CODE (x) == ASHIFT && GET_CODE (XEXP (x, 1)) == CONST_INT - && (log = (unsigned) exact_log2 (INTVAL (XEXP (x, 1)))) < 4) + && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) < 4) { changed = 1; + log = INTVAL (XEXP (x, 1)); x = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (x, 0)), GEN_INT (1 << log)); } @@ -6626,9 +7019,10 @@ legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode) if (GET_CODE (XEXP (x, 0)) == ASHIFT && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT - && (log = (unsigned) exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) < 4) + && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 0), 1)) < 4) { changed = 1; + log = INTVAL (XEXP (XEXP (x, 0), 1)); XEXP (x, 0) = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (XEXP (x, 0), 0)), GEN_INT (1 << log)); @@ -6636,9 +7030,10 @@ legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, enum machine_mode mode) if (GET_CODE (XEXP (x, 1)) == ASHIFT && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT - && (log = (unsigned) exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1)))) < 4) + && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (x, 1), 1)) < 4) { changed = 1; + log = INTVAL (XEXP (XEXP (x, 1), 1)); XEXP (x, 1) = gen_rtx_MULT (Pmode, force_reg (Pmode, XEXP (XEXP (x, 1), 0)), GEN_INT (1 << log)); @@ -6768,14 +7163,28 @@ output_pic_addr_const (FILE *file, rtx x, int code) switch (GET_CODE (x)) { case PC: - if (flag_pic) - putc ('.', file); - else - abort (); + gcc_assert (flag_pic); + putc ('.', file); break; case SYMBOL_REF: - assemble_name (file, XSTR (x, 0)); + if (! TARGET_MACHO || TARGET_64BIT) + output_addr_const (file, x); + else + { + const char *name = XSTR (x, 0); + + /* Mark the decl as referenced so that cgraph will output the function. */ + if (SYMBOL_REF_DECL (x)) + mark_decl_referenced (SYMBOL_REF_DECL (x)); + +#if TARGET_MACHO + if (MACHOPIC_INDIRECT + && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION) + name = machopic_indirection_name (x, /*stub_p=*/true); +#endif + assemble_name (file, name); + } if (!TARGET_MACHO && code == 'P' && ! SYMBOL_REF_LOCAL_P (x)) fputs ("@PLT", file); break; @@ -6823,14 +7232,13 @@ output_pic_addr_const (FILE *file, rtx x, int code) putc ('+', file); output_pic_addr_const (file, XEXP (x, 1), code); } - else if (GET_CODE (XEXP (x, 1)) == CONST_INT) + else { + gcc_assert (GET_CODE (XEXP (x, 1)) == CONST_INT); output_pic_addr_const (file, XEXP (x, 1), code); putc ('+', file); output_pic_addr_const (file, XEXP (x, 0), code); } - else - abort (); break; case MINUS: @@ -6844,8 +7252,7 @@ output_pic_addr_const (FILE *file, rtx x, int code) break; case UNSPEC: - if (XVECLEN (x, 0) != 1) - abort (); + gcc_assert (XVECLEN (x, 0) == 1); output_pic_addr_const (file, XVECEXP (x, 0, 0), code); switch (XINT (x, 1)) { @@ -6894,30 +7301,10 @@ output_pic_addr_const (FILE *file, rtx x, int code) } } -/* This is called from dwarfout.c via ASM_OUTPUT_DWARF_ADDR_CONST. - We need to handle our special PIC relocations. */ - -void -i386_dwarf_output_addr_const (FILE *file, rtx x) -{ -#ifdef ASM_QUAD - fprintf (file, "%s", TARGET_64BIT ? ASM_QUAD : ASM_LONG); -#else - if (TARGET_64BIT) - abort (); - fprintf (file, "%s", ASM_LONG); -#endif - if (flag_pic) - output_pic_addr_const (file, x, '\0'); - else - output_addr_const (file, x); - fputc ('\n', file); -} - -/* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL. +/* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL. We need to emit DTP-relative relocations. */ -void +static void i386_output_dwarf_dtprel (FILE *file, int size, rtx x) { fputs (ASM_LONG, file); @@ -6931,18 +7318,30 @@ i386_output_dwarf_dtprel (FILE *file, int size, rtx x) fputs (", 0", file); break; default: - abort (); + gcc_unreachable (); } } /* In the name of slightly smaller debug output, and to cater to - general assembler losage, recognize PIC+GOTOFF and turn it back - into a direct symbol reference. */ + general assembler lossage, recognize PIC+GOTOFF and turn it back + into a direct symbol reference. + + On Darwin, this is necessary to avoid a crash, because Darwin + has a different PIC label for each routine but the DWARF debugging + information is not associated with any particular routine, so it's + necessary to remove references to the PIC label from RTL stored by + the DWARF output code. */ static rtx ix86_delegitimize_address (rtx orig_x) { - rtx x = orig_x, y; + rtx x = orig_x; + /* reg_addend is NULL or a multiple of some register. */ + rtx reg_addend = NULL_RTX; + /* const_addend is NULL or a const_int. */ + rtx const_addend = NULL_RTX; + /* This is the result, or NULL. */ + rtx result = NULL_RTX; if (GET_CODE (x) == MEM) x = XEXP (x, 0); @@ -6964,51 +7363,52 @@ ix86_delegitimize_address (rtx orig_x) if (GET_CODE (XEXP (x, 0)) == REG && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM) /* %ebx + GOT/GOTOFF */ - y = NULL; + ; else if (GET_CODE (XEXP (x, 0)) == PLUS) { /* %ebx + %reg * scale + GOT/GOTOFF */ - y = XEXP (x, 0); - if (GET_CODE (XEXP (y, 0)) == REG - && REGNO (XEXP (y, 0)) == PIC_OFFSET_TABLE_REGNUM) - y = XEXP (y, 1); - else if (GET_CODE (XEXP (y, 1)) == REG - && REGNO (XEXP (y, 1)) == PIC_OFFSET_TABLE_REGNUM) - y = XEXP (y, 0); + reg_addend = XEXP (x, 0); + if (GET_CODE (XEXP (reg_addend, 0)) == REG + && REGNO (XEXP (reg_addend, 0)) == PIC_OFFSET_TABLE_REGNUM) + reg_addend = XEXP (reg_addend, 1); + else if (GET_CODE (XEXP (reg_addend, 1)) == REG + && REGNO (XEXP (reg_addend, 1)) == PIC_OFFSET_TABLE_REGNUM) + reg_addend = XEXP (reg_addend, 0); else return orig_x; - if (GET_CODE (y) != REG - && GET_CODE (y) != MULT - && GET_CODE (y) != ASHIFT) + if (GET_CODE (reg_addend) != REG + && GET_CODE (reg_addend) != MULT + && GET_CODE (reg_addend) != ASHIFT) return orig_x; } else return orig_x; x = XEXP (XEXP (x, 1), 0); + if (GET_CODE (x) == PLUS + && GET_CODE (XEXP (x, 1)) == CONST_INT) + { + const_addend = XEXP (x, 1); + x = XEXP (x, 0); + } + if (GET_CODE (x) == UNSPEC && ((XINT (x, 1) == UNSPEC_GOT && GET_CODE (orig_x) == MEM) || (XINT (x, 1) == UNSPEC_GOTOFF && GET_CODE (orig_x) != MEM))) - { - if (y) - return gen_rtx_PLUS (Pmode, y, XVECEXP (x, 0, 0)); - return XVECEXP (x, 0, 0); - } + result = XVECEXP (x, 0, 0); - if (GET_CODE (x) == PLUS - && GET_CODE (XEXP (x, 0)) == UNSPEC - && GET_CODE (XEXP (x, 1)) == CONST_INT - && ((XINT (XEXP (x, 0), 1) == UNSPEC_GOT && GET_CODE (orig_x) == MEM) - || (XINT (XEXP (x, 0), 1) == UNSPEC_GOTOFF - && GET_CODE (orig_x) != MEM))) - { - x = gen_rtx_PLUS (VOIDmode, XVECEXP (XEXP (x, 0), 0, 0), XEXP (x, 1)); - if (y) - return gen_rtx_PLUS (Pmode, y, x); - return x; - } + if (TARGET_MACHO && darwin_local_data_pic (x) + && GET_CODE (orig_x) != MEM) + result = XEXP (x, 0); + + if (! result) + return orig_x; - return orig_x; + if (const_addend) + result = gen_rtx_PLUS (Pmode, result, const_addend); + if (reg_addend) + result = gen_rtx_PLUS (Pmode, reg_addend, result); + return result; } static void @@ -7021,8 +7421,7 @@ put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse, { enum rtx_code second_code, bypass_code; ix86_fp_comparison_codes (code, &bypass_code, &code, &second_code); - if (bypass_code != NIL || second_code != NIL) - abort (); + gcc_assert (bypass_code == UNKNOWN && second_code == UNKNOWN); code = ix86_fp_compare_code_to_integer (code); mode = CCmode; } @@ -7038,52 +7437,64 @@ put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse, suffix = "ne"; break; case GT: - if (mode != CCmode && mode != CCNOmode && mode != CCGCmode) - abort (); + gcc_assert (mode == CCmode || mode == CCNOmode || mode == CCGCmode); suffix = "g"; break; case GTU: - /* ??? Use "nbe" instead of "a" for fcmov losage on some assemblers. - Those same assemblers have the same but opposite losage on cmov. */ - if (mode != CCmode) - abort (); + /* ??? Use "nbe" instead of "a" for fcmov lossage on some assemblers. + Those same assemblers have the same but opposite lossage on cmov. */ + gcc_assert (mode == CCmode); suffix = fp ? "nbe" : "a"; break; case LT: - if (mode == CCNOmode || mode == CCGOCmode) - suffix = "s"; - else if (mode == CCmode || mode == CCGCmode) - suffix = "l"; - else - abort (); + switch (mode) + { + case CCNOmode: + case CCGOCmode: + suffix = "s"; + break; + + case CCmode: + case CCGCmode: + suffix = "l"; + break; + + default: + gcc_unreachable (); + } break; case LTU: - if (mode != CCmode) - abort (); + gcc_assert (mode == CCmode); suffix = "b"; break; case GE: - if (mode == CCNOmode || mode == CCGOCmode) - suffix = "ns"; - else if (mode == CCmode || mode == CCGCmode) - suffix = "ge"; - else - abort (); + switch (mode) + { + case CCNOmode: + case CCGOCmode: + suffix = "ns"; + break; + + case CCmode: + case CCGCmode: + suffix = "ge"; + break; + + default: + gcc_unreachable (); + } break; case GEU: /* ??? As above. */ - if (mode != CCmode) - abort (); + gcc_assert (mode == CCmode); suffix = fp ? "nb" : "ae"; break; case LE: - if (mode != CCmode && mode != CCGCmode && mode != CCNOmode) - abort (); + gcc_assert (mode == CCmode || mode == CCGCmode || mode == CCNOmode); suffix = "le"; break; case LEU: - if (mode != CCmode) - abort (); + gcc_assert (mode == CCmode); suffix = "be"; break; case UNORDERED: @@ -7093,7 +7504,7 @@ put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse, suffix = fp ? "nu" : "np"; break; default: - abort (); + gcc_unreachable (); } fputs (suffix, file); } @@ -7103,17 +7514,16 @@ put_condition_code (enum rtx_code code, enum machine_mode mode, int reverse, If CODE is 'b', pretend the mode is QImode. If CODE is 'k', pretend the mode is SImode. If CODE is 'q', pretend the mode is DImode. - If CODE is 'h', pretend the reg is the `high' byte register. + If CODE is 'h', pretend the reg is the 'high' byte register. If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */ void print_reg (rtx x, int code, FILE *file) { - if (REGNO (x) == ARG_POINTER_REGNUM - || REGNO (x) == FRAME_POINTER_REGNUM - || REGNO (x) == FLAGS_REG - || REGNO (x) == FPSR_REG) - abort (); + gcc_assert (REGNO (x) != ARG_POINTER_REGNUM + && REGNO (x) != FRAME_POINTER_REGNUM + && REGNO (x) != FLAGS_REG + && REGNO (x) != FPSR_REG); if (ASSEMBLER_DIALECT == ASM_ATT || USER_LABEL_PREFIX[0] == 0) putc ('%', file); @@ -7137,8 +7547,7 @@ print_reg (rtx x, int code, FILE *file) from the normal registers. */ if (REX_INT_REG_P (x)) { - if (!TARGET_64BIT) - abort (); + gcc_assert (TARGET_64BIT); switch (code) { case 0: @@ -7193,7 +7602,7 @@ print_reg (rtx x, int code, FILE *file) fputs (qi_high_reg_name[REGNO (x)], file); break; default: - abort (); + gcc_unreachable (); } } @@ -7214,7 +7623,7 @@ get_some_local_dynamic_name (void) && for_each_rtx (&PATTERN (insn), get_some_local_dynamic_name_1, 0)) return cfun->machine->some_ld_name; - abort (); + gcc_unreachable (); } static int @@ -7223,7 +7632,7 @@ get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) rtx x = *px; if (GET_CODE (x) == SYMBOL_REF - && local_dynamic_symbolic_operand (x, Pmode)) + && SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC) { cfun->machine->some_ld_name = XSTR (x, 0); return 1; @@ -7257,6 +7666,7 @@ get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED) P -- if PIC, print an @PLT suffix. X -- don't print any sort of PIC '@' suffix for a symbol. & -- print some in-use local-dynamic symbol name. + H -- print a memory address offset by 8; used for sse high-parts */ void @@ -7276,10 +7686,13 @@ print_operand (FILE *file, rtx x, int code) return; case 'A': - if (ASSEMBLER_DIALECT == ASM_ATT) - putc ('*', file); - else if (ASSEMBLER_DIALECT == ASM_INTEL) + switch (ASSEMBLER_DIALECT) { + case ASM_ATT: + putc ('*', file); + break; + + case ASM_INTEL: /* Intel syntax. For absolute addresses, registers should not be surrounded by braces. */ if (GET_CODE (x) != REG) @@ -7289,9 +7702,11 @@ print_operand (FILE *file, rtx x, int code) putc (']', file); return; } + break; + + default: + gcc_unreachable (); } - else - abort (); PRINT_OPERAND (file, x, 0); return; @@ -7376,7 +7791,7 @@ print_operand (FILE *file, rtx x, int code) return; default: - abort (); + gcc_unreachable (); } case 'b': @@ -7434,8 +7849,7 @@ print_operand (FILE *file, rtx x, int code) fputs ("ord", file); break; default: - abort (); - break; + gcc_unreachable (); } return; case 'O': @@ -7449,7 +7863,7 @@ print_operand (FILE *file, rtx x, int code) case SFmode: putc ('l', file); break; case DImode: case DFmode: putc ('q', file); break; - default: abort (); + default: gcc_unreachable (); } putc ('.', file); } @@ -7470,7 +7884,7 @@ print_operand (FILE *file, rtx x, int code) case 'c': /* Check to see if argument to %c is really a constant and not a condition code which needs to be reversed. */ - if (GET_RTX_CLASS (GET_CODE (x)) != '<') + if (!COMPARISON_P (x)) { output_operand_lossage ("operand is neither a constant nor a condition code, invalid operand code 'c'"); return; @@ -7484,6 +7898,13 @@ print_operand (FILE *file, rtx x, int code) #endif put_condition_code (GET_CODE (x), GET_MODE (XEXP (x, 0)), 1, 1, file); return; + + case 'H': + /* It doesn't actually matter what mode we use here, as we're + only going to use this for printing. */ + x = adjust_address_nv (x, DImode, 8); + break; + case '+': { rtx x; @@ -7518,7 +7939,7 @@ print_operand (FILE *file, rtx x, int code) return; } default: - output_operand_lossage ("invalid operand code `%c'", code); + output_operand_lossage ("invalid operand code '%c'", code); } } @@ -7540,7 +7961,7 @@ print_operand (FILE *file, rtx x, int code) case 12: size = "XWORD"; break; case 16: size = "XMMWORD"; break; default: - abort (); + gcc_unreachable (); } /* Check for explicit size override (codes 'b', 'w' and 'k') */ @@ -7599,6 +8020,15 @@ print_operand (FILE *file, rtx x, int code) else { + /* We have patterns that allow zero sets of memory, for instance. + In 64-bit mode, we should probably support all 8-byte vectors, + since we can in fact encode that into an immediate. */ + if (GET_CODE (x) == CONST_VECTOR) + { + gcc_assert (x == CONST0_RTX (GET_MODE (x))); + x = const0_rtx; + } + if (code != 'P') { if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) @@ -7632,9 +8062,9 @@ print_operand_address (FILE *file, rtx addr) struct ix86_address parts; rtx base, index, disp; int scale; + int ok = ix86_decompose_address (addr, &parts); - if (! ix86_decompose_address (addr, &parts)) - abort (); + gcc_assert (ok); base = parts.base; index = parts.index; @@ -7652,7 +8082,7 @@ print_operand_address (FILE *file, rtx addr) fputs ((parts.seg == SEG_FS ? "fs:" : "gs:"), file); break; default: - abort (); + gcc_unreachable (); } if (!base && !index) @@ -7675,16 +8105,17 @@ print_operand_address (FILE *file, rtx addr) output_addr_const (file, disp); /* Use one byte shorter RIP relative addressing for 64bit mode. */ - if (TARGET_64BIT - && ((GET_CODE (disp) == SYMBOL_REF - && ! tls_symbolic_operand (disp, GET_MODE (disp))) - || GET_CODE (disp) == LABEL_REF - || (GET_CODE (disp) == CONST - && GET_CODE (XEXP (disp, 0)) == PLUS - && (GET_CODE (XEXP (XEXP (disp, 0), 0)) == SYMBOL_REF - || GET_CODE (XEXP (XEXP (disp, 0), 0)) == LABEL_REF) - && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT))) - fputs ("(%rip)", file); + if (TARGET_64BIT) + { + if (GET_CODE (disp) == CONST + && GET_CODE (XEXP (disp, 0)) == PLUS + && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT) + disp = XEXP (XEXP (disp, 0), 0); + if (GET_CODE (disp) == LABEL_REF + || (GET_CODE (disp) == SYMBOL_REF + && SYMBOL_REF_TLS_MODEL (disp) == 0)) + fputs ("(%rip)", file); + } } else { @@ -7847,7 +8278,7 @@ split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[]) } } } -/* Split one or more TImode RTL references into pairs of SImode +/* Split one or more TImode RTL references into pairs of DImode references. The RTL can be REG, offsettable MEM, integer constant, or CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to split and "num" is its length. lo_half and hi_half are output arrays @@ -7898,7 +8329,7 @@ output_387_binary_op (rtx insn, rtx *operands) static char buf[30]; const char *p; const char *ssep; - int is_sse = SSE_REG_P (operands[0]) | SSE_REG_P (operands[1]) | SSE_REG_P (operands[2]); + int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]) || SSE_REG_P (operands[2]); #ifdef ENABLE_CHECKING /* Even if we do not want to check the inputs, this documents input @@ -7912,8 +8343,8 @@ output_387_binary_op (rtx insn, rtx *operands) && (STACK_REG_P (operands[1]) || GET_CODE (operands[1]) == MEM))) && (STACK_TOP_P (operands[1]) || STACK_TOP_P (operands[2]))) ; /* ok */ - else if (!is_sse) - abort (); + else + gcc_assert (is_sse); #endif switch (GET_CODE (operands[3])) @@ -7955,7 +8386,7 @@ output_387_binary_op (rtx insn, rtx *operands) break; default: - abort (); + gcc_unreachable (); } if (is_sse) @@ -8090,29 +8521,153 @@ output_387_binary_op (rtx insn, rtx *operands) break; default: - abort (); + gcc_unreachable (); } strcat (buf, p); return buf; } -/* Output code to initialize control word copies used by - trunc?f?i patterns. NORMAL is set to current control word, while ROUND_DOWN - is set to control word rounding downwards. */ +/* Return needed mode for entity in optimize_mode_switching pass. */ + +int +ix86_mode_needed (int entity, rtx insn) +{ + enum attr_i387_cw mode; + + /* The mode UNINITIALIZED is used to store control word after a + function call or ASM pattern. The mode ANY specify that function + has no requirements on the control word and make no changes in the + bits we are interested in. */ + + if (CALL_P (insn) + || (NONJUMP_INSN_P (insn) + && (asm_noperands (PATTERN (insn)) >= 0 + || GET_CODE (PATTERN (insn)) == ASM_INPUT))) + return I387_CW_UNINITIALIZED; + + if (recog_memoized (insn) < 0) + return I387_CW_ANY; + + mode = get_attr_i387_cw (insn); + + switch (entity) + { + case I387_TRUNC: + if (mode == I387_CW_TRUNC) + return mode; + break; + + case I387_FLOOR: + if (mode == I387_CW_FLOOR) + return mode; + break; + + case I387_CEIL: + if (mode == I387_CW_CEIL) + return mode; + break; + + case I387_MASK_PM: + if (mode == I387_CW_MASK_PM) + return mode; + break; + + default: + gcc_unreachable (); + } + + return I387_CW_ANY; +} + +/* Output code to initialize control word copies used by trunc?f?i and + rounding patterns. CURRENT_MODE is set to current control word, + while NEW_MODE is set to new control word. */ + void -emit_i387_cw_initialization (rtx normal, rtx round_down) +emit_i387_cw_initialization (int mode) { + rtx stored_mode = assign_386_stack_local (HImode, SLOT_CW_STORED); + rtx new_mode; + + int slot; + rtx reg = gen_reg_rtx (HImode); - emit_insn (gen_x86_fnstcw_1 (normal)); - emit_move_insn (reg, normal); - if (!TARGET_PARTIAL_REG_STALL && !optimize_size - && !TARGET_64BIT) - emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc))); + emit_insn (gen_x86_fnstcw_1 (stored_mode)); + emit_move_insn (reg, stored_mode); + + if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL || optimize_size) + { + switch (mode) + { + case I387_CW_TRUNC: + /* round toward zero (truncate) */ + emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0c00))); + slot = SLOT_CW_TRUNC; + break; + + case I387_CW_FLOOR: + /* round down toward -oo */ + emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00))); + emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0400))); + slot = SLOT_CW_FLOOR; + break; + + case I387_CW_CEIL: + /* round up toward +oo */ + emit_insn (gen_andhi3 (reg, reg, GEN_INT (~0x0c00))); + emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0800))); + slot = SLOT_CW_CEIL; + break; + + case I387_CW_MASK_PM: + /* mask precision exception for nearbyint() */ + emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020))); + slot = SLOT_CW_MASK_PM; + break; + + default: + gcc_unreachable (); + } + } else - emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0xc00))); - emit_move_insn (round_down, reg); + { + switch (mode) + { + case I387_CW_TRUNC: + /* round toward zero (truncate) */ + emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0xc))); + slot = SLOT_CW_TRUNC; + break; + + case I387_CW_FLOOR: + /* round down toward -oo */ + emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x4))); + slot = SLOT_CW_FLOOR; + break; + + case I387_CW_CEIL: + /* round up toward +oo */ + emit_insn (gen_movsi_insv_1 (reg, GEN_INT (0x8))); + slot = SLOT_CW_CEIL; + break; + + case I387_CW_MASK_PM: + /* mask precision exception for nearbyint() */ + emit_insn (gen_iorhi3 (reg, reg, GEN_INT (0x0020))); + slot = SLOT_CW_MASK_PM; + break; + + default: + gcc_unreachable (); + } + } + + gcc_assert (slot < MAX_386_STACK_LOCALS); + + new_mode = assign_386_stack_local (HImode, slot); + emit_move_insn (new_mode, reg); } /* Output code for INSN to convert a float to a signed int. OPERANDS @@ -8120,50 +8675,87 @@ emit_i387_cw_initialization (rtx normal, rtx round_down) operand may be [SDX]Fmode. */ const char * -output_fix_trunc (rtx insn, rtx *operands) +output_fix_trunc (rtx insn, rtx *operands, int fisttp) { int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; int dimode_p = GET_MODE (operands[0]) == DImode; + int round_mode = get_attr_i387_cw (insn); /* Jump through a hoop or two for DImode, since the hardware has no non-popping instruction. We used to do this a different way, but that was somewhat fragile and broke with post-reload splitters. */ - if (dimode_p && !stack_top_dies) + if ((dimode_p || fisttp) && !stack_top_dies) output_asm_insn ("fld\t%y1", operands); - if (!STACK_TOP_P (operands[1])) - abort (); - - if (GET_CODE (operands[0]) != MEM) - abort (); + gcc_assert (STACK_TOP_P (operands[1])); + gcc_assert (GET_CODE (operands[0]) == MEM); - output_asm_insn ("fldcw\t%3", operands); - if (stack_top_dies || dimode_p) - output_asm_insn ("fistp%z0\t%0", operands); + if (fisttp) + output_asm_insn ("fisttp%z0\t%0", operands); else - output_asm_insn ("fist%z0\t%0", operands); - output_asm_insn ("fldcw\t%2", operands); + { + if (round_mode != I387_CW_ANY) + output_asm_insn ("fldcw\t%3", operands); + if (stack_top_dies || dimode_p) + output_asm_insn ("fistp%z0\t%0", operands); + else + output_asm_insn ("fist%z0\t%0", operands); + if (round_mode != I387_CW_ANY) + output_asm_insn ("fldcw\t%2", operands); + } return ""; } +/* Output code for x87 ffreep insn. The OPNO argument, which may only + have the values zero or one, indicates the ffreep insn's operand + from the OPERANDS array. */ + +static const char * +output_387_ffreep (rtx *operands ATTRIBUTE_UNUSED, int opno) +{ + if (TARGET_USE_FFREEP) +#if HAVE_AS_IX86_FFREEP + return opno ? "ffreep\t%y1" : "ffreep\t%y0"; +#else + switch (REGNO (operands[opno])) + { + case FIRST_STACK_REG + 0: return ".word\t0xc0df"; + case FIRST_STACK_REG + 1: return ".word\t0xc1df"; + case FIRST_STACK_REG + 2: return ".word\t0xc2df"; + case FIRST_STACK_REG + 3: return ".word\t0xc3df"; + case FIRST_STACK_REG + 4: return ".word\t0xc4df"; + case FIRST_STACK_REG + 5: return ".word\t0xc5df"; + case FIRST_STACK_REG + 6: return ".word\t0xc6df"; + case FIRST_STACK_REG + 7: return ".word\t0xc7df"; + } +#endif + + return opno ? "fstp\t%y1" : "fstp\t%y0"; +} + + /* Output code for INSN to compare OPERANDS. EFLAGS_P is 1 when fcomi - should be used and 2 when fnstsw should be used. UNORDERED_P is true - when fucom should be used. */ + should be used. UNORDERED_P is true when fucom should be used. */ const char * output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p) { int stack_top_dies; - rtx cmp_op0 = operands[0]; - rtx cmp_op1 = operands[1]; - int is_sse = SSE_REG_P (operands[0]) | SSE_REG_P (operands[1]); + rtx cmp_op0, cmp_op1; + int is_sse = SSE_REG_P (operands[0]) || SSE_REG_P (operands[1]); - if (eflags_p == 2) + if (eflags_p) + { + cmp_op0 = operands[0]; + cmp_op1 = operands[1]; + } + else { - cmp_op0 = cmp_op1; + cmp_op0 = operands[1]; cmp_op1 = operands[2]; } + if (is_sse) { if (GET_MODE (operands[0]) == SFmode) @@ -8178,11 +8770,21 @@ output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p) return "comisd\t{%1, %0|%0, %1}"; } - if (! STACK_TOP_P (cmp_op0)) - abort (); + gcc_assert (STACK_TOP_P (cmp_op0)); stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + if (cmp_op1 == CONST0_RTX (GET_MODE (cmp_op1))) + { + if (stack_top_dies) + { + output_asm_insn ("ftst\n\tfnstsw\t%0", operands); + return output_387_ffreep (operands, 1); + } + else + return "ftst\n\tfnstsw\t%0"; + } + if (STACK_REG_P (cmp_op1) && stack_top_dies && find_regno_note (insn, REG_DEAD, REGNO (cmp_op1)) @@ -8192,7 +8794,7 @@ output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p) is also a stack register that dies, then this must be a `fcompp' float compare */ - if (eflags_p == 1) + if (eflags_p) { /* There is no double popping fcomi variant. Fortunately, eflags is immune from the fstp's cc clobbering. */ @@ -8200,39 +8802,29 @@ output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p) output_asm_insn ("fucomip\t{%y1, %0|%0, %y1}", operands); else output_asm_insn ("fcomip\t{%y1, %0|%0, %y1}", operands); - return "fstp\t%y0"; + return output_387_ffreep (operands, 0); } else { - if (eflags_p == 2) - { - if (unordered_p) - return "fucompp\n\tfnstsw\t%0"; - else - return "fcompp\n\tfnstsw\t%0"; - } + if (unordered_p) + return "fucompp\n\tfnstsw\t%0"; else - { - if (unordered_p) - return "fucompp"; - else - return "fcompp"; - } + return "fcompp\n\tfnstsw\t%0"; } } else { /* Encoded here as eflags_p | intmode | unordered_p | stack_top_dies. */ - static const char * const alt[24] = + static const char * const alt[16] = { - "fcom%z1\t%y1", - "fcomp%z1\t%y1", - "fucom%z1\t%y1", - "fucomp%z1\t%y1", + "fcom%z2\t%y2\n\tfnstsw\t%0", + "fcomp%z2\t%y2\n\tfnstsw\t%0", + "fucom%z2\t%y2\n\tfnstsw\t%0", + "fucomp%z2\t%y2\n\tfnstsw\t%0", - "ficom%z1\t%y1", - "ficomp%z1\t%y1", + "ficom%z2\t%y2\n\tfnstsw\t%0", + "ficomp%z2\t%y2\n\tfnstsw\t%0", NULL, NULL, @@ -8244,16 +8836,6 @@ output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p) NULL, NULL, NULL, - NULL, - - "fcom%z2\t%y2\n\tfnstsw\t%0", - "fcomp%z2\t%y2\n\tfnstsw\t%0", - "fucom%z2\t%y2\n\tfnstsw\t%0", - "fucomp%z2\t%y2\n\tfnstsw\t%0", - - "ficom%z2\t%y2\n\tfnstsw\t%0", - "ficomp%z2\t%y2\n\tfnstsw\t%0", - NULL, NULL }; @@ -8261,15 +8843,13 @@ output_fp_compare (rtx insn, rtx *operands, int eflags_p, int unordered_p) const char *ret; mask = eflags_p << 3; - mask |= (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT) << 2; + mask |= (GET_MODE_CLASS (GET_MODE (cmp_op1)) == MODE_INT) << 2; mask |= unordered_p << 1; mask |= stack_top_dies; - if (mask >= 24) - abort (); + gcc_assert (mask < 16); ret = alt[mask]; - if (ret == NULL) - abort (); + gcc_assert (ret); return ret; } @@ -8280,14 +8860,12 @@ ix86_output_addr_vec_elt (FILE *file, int value) { const char *directive = ASM_LONG; - if (TARGET_64BIT) - { #ifdef ASM_QUAD - directive = ASM_QUAD; + if (TARGET_64BIT) + directive = ASM_QUAD; #else - abort (); + gcc_assert (!TARGET_64BIT); #endif - } fprintf (file, "%s%s%d\n", directive, LPREFIX, value); } @@ -8322,8 +8900,7 @@ ix86_expand_clear (rtx dest) rtx tmp; /* We play register width games, which are only valid after reload. */ - if (!reload_completed) - abort (); + gcc_assert (reload_completed); /* Avoid HImode and its attendant prefix byte. */ if (GET_MODE_SIZE (GET_MODE (dest)) < 4) @@ -8344,7 +8921,7 @@ ix86_expand_clear (rtx dest) /* X is an unchanging MEM. If it is a constant pool reference, return the constant pool rtx, else NULL. */ -static rtx +rtx maybe_get_pool_constant (rtx x) { x = ix86_delegitimize_address (XEXP (x, 0)); @@ -8365,46 +8942,62 @@ ix86_expand_move (enum machine_mode mode, rtx operands[]) op0 = operands[0]; op1 = operands[1]; - model = tls_symbolic_operand (op1, Pmode); - if (model) + if (GET_CODE (op1) == SYMBOL_REF) { - op1 = legitimize_tls_address (op1, model, true); - op1 = force_operand (op1, op0); - if (op1 == op0) - return; + model = SYMBOL_REF_TLS_MODEL (op1); + if (model) + { + op1 = legitimize_tls_address (op1, model, true); + op1 = force_operand (op1, op0); + if (op1 == op0) + return; + } + } + else if (GET_CODE (op1) == CONST + && GET_CODE (XEXP (op1, 0)) == PLUS + && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SYMBOL_REF) + { + model = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (op1, 0), 0)); + if (model) + { + rtx addend = XEXP (XEXP (op1, 0), 1); + op1 = legitimize_tls_address (XEXP (XEXP (op1, 0), 0), model, true); + op1 = force_operand (op1, NULL); + op1 = expand_simple_binop (Pmode, PLUS, op1, addend, + op0, 1, OPTAB_DIRECT); + if (op1 == op0) + return; + } } if (flag_pic && mode == Pmode && symbolic_operand (op1, Pmode)) { + if (TARGET_MACHO && !TARGET_64BIT) + { #if TARGET_MACHO - if (MACHOPIC_PURE) - { - rtx temp = ((reload_in_progress - || ((op0 && GET_CODE (op0) == REG) - && mode == Pmode)) - ? op0 : gen_reg_rtx (Pmode)); - op1 = machopic_indirect_data_reference (op1, temp); - op1 = machopic_legitimize_pic_address (op1, mode, - temp == op1 ? 0 : temp); - } - else if (MACHOPIC_INDIRECT) - op1 = machopic_indirect_data_reference (op1, 0); - if (op0 == op1) - return; -#else - if (GET_CODE (op0) == MEM) - op1 = force_reg (Pmode, op1); + if (MACHOPIC_PURE) + { + rtx temp = ((reload_in_progress + || ((op0 && GET_CODE (op0) == REG) + && mode == Pmode)) + ? op0 : gen_reg_rtx (Pmode)); + op1 = machopic_indirect_data_reference (op1, temp); + op1 = machopic_legitimize_pic_address (op1, mode, + temp == op1 ? 0 : temp); + } + else if (MACHOPIC_INDIRECT) + op1 = machopic_indirect_data_reference (op1, 0); + if (op0 == op1) + return; +#endif + } else { - rtx temp = op0; - if (GET_CODE (temp) != REG) - temp = gen_reg_rtx (Pmode); - temp = legitimize_pic_address (op1, temp); - if (temp == op0) - return; - op1 = temp; + if (GET_CODE (op0) == MEM) + op1 = force_reg (Pmode, op1); + else + op1 = legitimize_address (op1, op1, Pmode); } -#endif /* TARGET_MACHO */ } else { @@ -8422,7 +9015,7 @@ ix86_expand_move (enum machine_mode mode, rtx operands[]) to get them CSEed. */ if (TARGET_64BIT && mode == DImode && immediate_operand (op1, mode) - && !x86_64_zero_extended_value (op1) + && !x86_64_zext_immediate_operand (op1, VOIDmode) && !register_operand (op0, mode) && optimize && !reload_completed && !reload_in_progress) op1 = copy_to_mode_reg (mode, op1); @@ -8455,45 +9048,186 @@ ix86_expand_move (enum machine_mode mode, rtx operands[]) void ix86_expand_vector_move (enum machine_mode mode, rtx operands[]) { + rtx op0 = operands[0], op1 = operands[1]; + /* Force constants other than zero into memory. We do not know how the instructions used to build constants modify the upper 64 bits of the register, once we have that information we may be able to handle some of them more efficiently. */ if ((reload_in_progress | reload_completed) == 0 - && register_operand (operands[0], mode) - && CONSTANT_P (operands[1]) && operands[1] != CONST0_RTX (mode)) - operands[1] = validize_mem (force_const_mem (mode, operands[1])); + && register_operand (op0, mode) + && CONSTANT_P (op1) + && standard_sse_constant_p (op1) <= 0) + op1 = validize_mem (force_const_mem (mode, op1)); /* Make operand1 a register if it isn't already. */ if (!no_new_pseudos - && !register_operand (operands[0], mode) - && !register_operand (operands[1], mode)) + && !register_operand (op0, mode) + && !register_operand (op1, mode)) { - rtx temp = force_reg (GET_MODE (operands[1]), operands[1]); - emit_move_insn (operands[0], temp); + emit_move_insn (op0, force_reg (GET_MODE (op0), op1)); return; } - emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); + emit_insn (gen_rtx_SET (VOIDmode, op0, op1)); } -/* Attempt to expand a binary operator. Make the expansion closer to the - actual machine, then just general_operand, which will allow 3 separate - memory references (one output, two input) in a single insn. */ +/* Implement the movmisalign patterns for SSE. Non-SSE modes go + straight to ix86_expand_vector_move. */ void -ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode, - rtx operands[]) +ix86_expand_vector_move_misalign (enum machine_mode mode, rtx operands[]) +{ + rtx op0, op1, m; + + op0 = operands[0]; + op1 = operands[1]; + + if (MEM_P (op1)) + { + /* If we're optimizing for size, movups is the smallest. */ + if (optimize_size) + { + op0 = gen_lowpart (V4SFmode, op0); + op1 = gen_lowpart (V4SFmode, op1); + emit_insn (gen_sse_movups (op0, op1)); + return; + } + + /* ??? If we have typed data, then it would appear that using + movdqu is the only way to get unaligned data loaded with + integer type. */ + if (TARGET_SSE2 && GET_MODE_CLASS (mode) == MODE_VECTOR_INT) + { + op0 = gen_lowpart (V16QImode, op0); + op1 = gen_lowpart (V16QImode, op1); + emit_insn (gen_sse2_movdqu (op0, op1)); + return; + } + + if (TARGET_SSE2 && mode == V2DFmode) + { + rtx zero; + + /* When SSE registers are split into halves, we can avoid + writing to the top half twice. */ + if (TARGET_SSE_SPLIT_REGS) + { + emit_insn (gen_rtx_CLOBBER (VOIDmode, op0)); + zero = op0; + } + else + { + /* ??? Not sure about the best option for the Intel chips. + The following would seem to satisfy; the register is + entirely cleared, breaking the dependency chain. We + then store to the upper half, with a dependency depth + of one. A rumor has it that Intel recommends two movsd + followed by an unpacklpd, but this is unconfirmed. And + given that the dependency depth of the unpacklpd would + still be one, I'm not sure why this would be better. */ + zero = CONST0_RTX (V2DFmode); + } + + m = adjust_address (op1, DFmode, 0); + emit_insn (gen_sse2_loadlpd (op0, zero, m)); + m = adjust_address (op1, DFmode, 8); + emit_insn (gen_sse2_loadhpd (op0, op0, m)); + } + else + { + if (TARGET_SSE_PARTIAL_REG_DEPENDENCY) + emit_move_insn (op0, CONST0_RTX (mode)); + else + emit_insn (gen_rtx_CLOBBER (VOIDmode, op0)); + + if (mode != V4SFmode) + op0 = gen_lowpart (V4SFmode, op0); + m = adjust_address (op1, V2SFmode, 0); + emit_insn (gen_sse_loadlps (op0, op0, m)); + m = adjust_address (op1, V2SFmode, 8); + emit_insn (gen_sse_loadhps (op0, op0, m)); + } + } + else if (MEM_P (op0)) + { + /* If we're optimizing for size, movups is the smallest. */ + if (optimize_size) + { + op0 = gen_lowpart (V4SFmode, op0); + op1 = gen_lowpart (V4SFmode, op1); + emit_insn (gen_sse_movups (op0, op1)); + return; + } + + /* ??? Similar to above, only less clear because of quote + typeless stores unquote. */ + if (TARGET_SSE2 && !TARGET_SSE_TYPELESS_STORES + && GET_MODE_CLASS (mode) == MODE_VECTOR_INT) + { + op0 = gen_lowpart (V16QImode, op0); + op1 = gen_lowpart (V16QImode, op1); + emit_insn (gen_sse2_movdqu (op0, op1)); + return; + } + + if (TARGET_SSE2 && mode == V2DFmode) + { + m = adjust_address (op0, DFmode, 0); + emit_insn (gen_sse2_storelpd (m, op1)); + m = adjust_address (op0, DFmode, 8); + emit_insn (gen_sse2_storehpd (m, op1)); + } + else + { + if (mode != V4SFmode) + op1 = gen_lowpart (V4SFmode, op1); + m = adjust_address (op0, V2SFmode, 0); + emit_insn (gen_sse_storelps (m, op1)); + m = adjust_address (op0, V2SFmode, 8); + emit_insn (gen_sse_storehps (m, op1)); + } + } + else + gcc_unreachable (); +} + +/* Expand a push in MODE. This is some mode for which we do not support + proper push instructions, at least from the registers that we expect + the value to live in. */ + +void +ix86_expand_push (enum machine_mode mode, rtx x) +{ + rtx tmp; + + tmp = expand_simple_binop (Pmode, PLUS, stack_pointer_rtx, + GEN_INT (-GET_MODE_SIZE (mode)), + stack_pointer_rtx, 1, OPTAB_DIRECT); + if (tmp != stack_pointer_rtx) + emit_move_insn (stack_pointer_rtx, tmp); + + tmp = gen_rtx_MEM (mode, stack_pointer_rtx); + emit_move_insn (tmp, x); +} + +/* Fix up OPERANDS to satisfy ix86_binary_operator_ok. Return the + destination to use for the operation. If different from the true + destination in operands[0], a copy operation will be required. */ + +rtx +ix86_fixup_binary_operands (enum rtx_code code, enum machine_mode mode, + rtx operands[]) { int matching_memory; - rtx src1, src2, dst, op, clob; + rtx src1, src2, dst; dst = operands[0]; src1 = operands[1]; src2 = operands[2]; /* Recognize <var1> = <value> <op> <var1> for commutative operators */ - if (GET_RTX_CLASS (code) == 'c' + if (GET_RTX_CLASS (code) == RTX_COMM_ARITH && (rtx_equal_p (dst, src2) || immediate_operand (src1, mode))) { @@ -8509,7 +9243,7 @@ ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode, { if (rtx_equal_p (dst, src1)) matching_memory = 1; - else if (GET_RTX_CLASS (code) == 'c' + else if (GET_RTX_CLASS (code) == RTX_COMM_ARITH && rtx_equal_p (dst, src2)) matching_memory = 2; else @@ -8529,29 +9263,47 @@ ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode, or non-matching memory. */ if ((CONSTANT_P (src1) || (!matching_memory && GET_CODE (src1) == MEM)) - && GET_RTX_CLASS (code) != 'c') + && GET_RTX_CLASS (code) != RTX_COMM_ARITH) src1 = force_reg (mode, src1); - /* If optimizing, copy to regs to improve CSE */ - if (optimize && ! no_new_pseudos) - { - if (GET_CODE (dst) == MEM) - dst = gen_reg_rtx (mode); - if (GET_CODE (src1) == MEM) - src1 = force_reg (mode, src1); - if (GET_CODE (src2) == MEM) - src2 = force_reg (mode, src2); - } + src1 = operands[1] = src1; + src2 = operands[2] = src2; + return dst; +} - /* Emit the instruction. */ +/* Similarly, but assume that the destination has already been + set up properly. */ + +void +ix86_fixup_binary_operands_no_copy (enum rtx_code code, + enum machine_mode mode, rtx operands[]) +{ + rtx dst = ix86_fixup_binary_operands (code, mode, operands); + gcc_assert (dst == operands[0]); +} + +/* Attempt to expand a binary operator. Make the expansion closer to the + actual machine, then just general_operand, which will allow 3 separate + memory references (one output, two input) in a single insn. */ + +void +ix86_expand_binary_operator (enum rtx_code code, enum machine_mode mode, + rtx operands[]) +{ + rtx src1, src2, dst, op, clob; + + dst = ix86_fixup_binary_operands (code, mode, operands); + src1 = operands[1]; + src2 = operands[2]; + + /* Emit the instruction. */ op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_ee (code, mode, src1, src2)); if (reload_in_progress) { /* Reload doesn't know about the flags register, and doesn't know that it doesn't want to clobber it. We can only do this with PLUS. */ - if (code != PLUS) - abort (); + gcc_assert (code == PLUS); emit_insn (op); } else @@ -8577,18 +9329,18 @@ ix86_binary_operator_ok (enum rtx_code code, if (GET_CODE (operands[1]) == MEM && GET_CODE (operands[2]) == MEM) return 0; /* If the operation is not commutable, source 1 cannot be a constant. */ - if (CONSTANT_P (operands[1]) && GET_RTX_CLASS (code) != 'c') + if (CONSTANT_P (operands[1]) && GET_RTX_CLASS (code) != RTX_COMM_ARITH) return 0; /* If the destination is memory, we must have a matching source operand. */ if (GET_CODE (operands[0]) == MEM && ! (rtx_equal_p (operands[0], operands[1]) - || (GET_RTX_CLASS (code) == 'c' + || (GET_RTX_CLASS (code) == RTX_COMM_ARITH && rtx_equal_p (operands[0], operands[2])))) return 0; /* If the operation is not commutable and the source 1 is memory, we must have a matching destination. */ if (GET_CODE (operands[1]) == MEM - && GET_RTX_CLASS (code) != 'c' + && GET_RTX_CLASS (code) != RTX_COMM_ARITH && ! rtx_equal_p (operands[0], operands[1])) return 0; return 1; @@ -8611,7 +9363,7 @@ ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode, /* If the destination is memory, and we do not have matching source operands, do things in registers. */ matching_memory = 0; - if (GET_CODE (dst) == MEM) + if (MEM_P (dst)) { if (rtx_equal_p (dst, src)) matching_memory = 1; @@ -8620,18 +9372,9 @@ ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode, } /* When source operand is memory, destination must match. */ - if (!matching_memory && GET_CODE (src) == MEM) + if (MEM_P (src) && !matching_memory) src = force_reg (mode, src); - /* If optimizing, copy to regs to improve CSE */ - if (optimize && ! no_new_pseudos) - { - if (GET_CODE (dst) == MEM) - dst = gen_reg_rtx (mode); - if (GET_CODE (src) == MEM) - src = force_reg (mode, src); - } - /* Emit the instruction. */ op = gen_rtx_SET (VOIDmode, dst, gen_rtx_fmt_e (code, mode, src)); @@ -8639,8 +9382,7 @@ ix86_expand_unary_operator (enum rtx_code code, enum machine_mode mode, { /* Reload doesn't know about the flags register, and doesn't know that it doesn't want to clobber it. */ - if (code != NOT) - abort (); + gcc_assert (code == NOT); emit_insn (op); } else @@ -8670,6 +9412,278 @@ ix86_unary_operator_ok (enum rtx_code code ATTRIBUTE_UNUSED, return TRUE; } +/* A subroutine of ix86_expand_fp_absneg_operator and copysign expanders. + Create a mask for the sign bit in MODE for an SSE register. If VECT is + true, then replicate the mask for all elements of the vector register. + If INVERT is true, then create a mask excluding the sign bit. */ + +rtx +ix86_build_signbit_mask (enum machine_mode mode, bool vect, bool invert) +{ + enum machine_mode vec_mode; + HOST_WIDE_INT hi, lo; + int shift = 63; + rtvec v; + rtx mask; + + /* Find the sign bit, sign extended to 2*HWI. */ + if (mode == SFmode) + lo = 0x80000000, hi = lo < 0; + else if (HOST_BITS_PER_WIDE_INT >= 64) + lo = (HOST_WIDE_INT)1 << shift, hi = -1; + else + lo = 0, hi = (HOST_WIDE_INT)1 << (shift - HOST_BITS_PER_WIDE_INT); + + if (invert) + lo = ~lo, hi = ~hi; + + /* Force this value into the low part of a fp vector constant. */ + mask = immed_double_const (lo, hi, mode == SFmode ? SImode : DImode); + mask = gen_lowpart (mode, mask); + + if (mode == SFmode) + { + if (vect) + v = gen_rtvec (4, mask, mask, mask, mask); + else + v = gen_rtvec (4, mask, CONST0_RTX (SFmode), + CONST0_RTX (SFmode), CONST0_RTX (SFmode)); + vec_mode = V4SFmode; + } + else + { + if (vect) + v = gen_rtvec (2, mask, mask); + else + v = gen_rtvec (2, mask, CONST0_RTX (DFmode)); + vec_mode = V2DFmode; + } + + return force_reg (vec_mode, gen_rtx_CONST_VECTOR (vec_mode, v)); +} + +/* Generate code for floating point ABS or NEG. */ + +void +ix86_expand_fp_absneg_operator (enum rtx_code code, enum machine_mode mode, + rtx operands[]) +{ + rtx mask, set, use, clob, dst, src; + bool matching_memory; + bool use_sse = false; + bool vector_mode = VECTOR_MODE_P (mode); + enum machine_mode elt_mode = mode; + + if (vector_mode) + { + elt_mode = GET_MODE_INNER (mode); + use_sse = true; + } + else if (TARGET_SSE_MATH) + use_sse = SSE_FLOAT_MODE_P (mode); + + /* NEG and ABS performed with SSE use bitwise mask operations. + Create the appropriate mask now. */ + if (use_sse) + mask = ix86_build_signbit_mask (elt_mode, vector_mode, code == ABS); + else + mask = NULL_RTX; + + dst = operands[0]; + src = operands[1]; + + /* If the destination is memory, and we don't have matching source + operands or we're using the x87, do things in registers. */ + matching_memory = false; + if (MEM_P (dst)) + { + if (use_sse && rtx_equal_p (dst, src)) + matching_memory = true; + else + dst = gen_reg_rtx (mode); + } + if (MEM_P (src) && !matching_memory) + src = force_reg (mode, src); + + if (vector_mode) + { + set = gen_rtx_fmt_ee (code == NEG ? XOR : AND, mode, src, mask); + set = gen_rtx_SET (VOIDmode, dst, set); + emit_insn (set); + } + else + { + set = gen_rtx_fmt_e (code, mode, src); + set = gen_rtx_SET (VOIDmode, dst, set); + if (mask) + { + use = gen_rtx_USE (VOIDmode, mask); + clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG)); + emit_insn (gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (3, set, use, clob))); + } + else + emit_insn (set); + } + + if (dst != operands[0]) + emit_move_insn (operands[0], dst); +} + +/* Expand a copysign operation. Special case operand 0 being a constant. */ + +void +ix86_expand_copysign (rtx operands[]) +{ + enum machine_mode mode, vmode; + rtx dest, op0, op1, mask, nmask; + + dest = operands[0]; + op0 = operands[1]; + op1 = operands[2]; + + mode = GET_MODE (dest); + vmode = mode == SFmode ? V4SFmode : V2DFmode; + + if (GET_CODE (op0) == CONST_DOUBLE) + { + rtvec v; + + if (real_isneg (CONST_DOUBLE_REAL_VALUE (op0))) + op0 = simplify_unary_operation (ABS, mode, op0, mode); + + if (op0 == CONST0_RTX (mode)) + op0 = CONST0_RTX (vmode); + else + { + if (mode == SFmode) + v = gen_rtvec (4, op0, CONST0_RTX (SFmode), + CONST0_RTX (SFmode), CONST0_RTX (SFmode)); + else + v = gen_rtvec (2, op0, CONST0_RTX (DFmode)); + op0 = force_reg (vmode, gen_rtx_CONST_VECTOR (vmode, v)); + } + + mask = ix86_build_signbit_mask (mode, 0, 0); + + if (mode == SFmode) + emit_insn (gen_copysignsf3_const (dest, op0, op1, mask)); + else + emit_insn (gen_copysigndf3_const (dest, op0, op1, mask)); + } + else + { + nmask = ix86_build_signbit_mask (mode, 0, 1); + mask = ix86_build_signbit_mask (mode, 0, 0); + + if (mode == SFmode) + emit_insn (gen_copysignsf3_var (dest, NULL, op0, op1, nmask, mask)); + else + emit_insn (gen_copysigndf3_var (dest, NULL, op0, op1, nmask, mask)); + } +} + +/* Deconstruct a copysign operation into bit masks. Operand 0 is known to + be a constant, and so has already been expanded into a vector constant. */ + +void +ix86_split_copysign_const (rtx operands[]) +{ + enum machine_mode mode, vmode; + rtx dest, op0, op1, mask, x; + + dest = operands[0]; + op0 = operands[1]; + op1 = operands[2]; + mask = operands[3]; + + mode = GET_MODE (dest); + vmode = GET_MODE (mask); + + dest = simplify_gen_subreg (vmode, dest, mode, 0); + x = gen_rtx_AND (vmode, dest, mask); + emit_insn (gen_rtx_SET (VOIDmode, dest, x)); + + if (op0 != CONST0_RTX (vmode)) + { + x = gen_rtx_IOR (vmode, dest, op0); + emit_insn (gen_rtx_SET (VOIDmode, dest, x)); + } +} + +/* Deconstruct a copysign operation into bit masks. Operand 0 is variable, + so we have to do two masks. */ + +void +ix86_split_copysign_var (rtx operands[]) +{ + enum machine_mode mode, vmode; + rtx dest, scratch, op0, op1, mask, nmask, x; + + dest = operands[0]; + scratch = operands[1]; + op0 = operands[2]; + op1 = operands[3]; + nmask = operands[4]; + mask = operands[5]; + + mode = GET_MODE (dest); + vmode = GET_MODE (mask); + + if (rtx_equal_p (op0, op1)) + { + /* Shouldn't happen often (it's useless, obviously), but when it does + we'd generate incorrect code if we continue below. */ + emit_move_insn (dest, op0); + return; + } + + if (REG_P (mask) && REGNO (dest) == REGNO (mask)) /* alternative 0 */ + { + gcc_assert (REGNO (op1) == REGNO (scratch)); + + x = gen_rtx_AND (vmode, scratch, mask); + emit_insn (gen_rtx_SET (VOIDmode, scratch, x)); + + dest = mask; + op0 = simplify_gen_subreg (vmode, op0, mode, 0); + x = gen_rtx_NOT (vmode, dest); + x = gen_rtx_AND (vmode, x, op0); + emit_insn (gen_rtx_SET (VOIDmode, dest, x)); + } + else + { + if (REGNO (op1) == REGNO (scratch)) /* alternative 1,3 */ + { + x = gen_rtx_AND (vmode, scratch, mask); + } + else /* alternative 2,4 */ + { + gcc_assert (REGNO (mask) == REGNO (scratch)); + op1 = simplify_gen_subreg (vmode, op1, mode, 0); + x = gen_rtx_AND (vmode, scratch, op1); + } + emit_insn (gen_rtx_SET (VOIDmode, scratch, x)); + + if (REGNO (op0) == REGNO (dest)) /* alternative 1,2 */ + { + dest = simplify_gen_subreg (vmode, op0, mode, 0); + x = gen_rtx_AND (vmode, dest, nmask); + } + else /* alternative 3,4 */ + { + gcc_assert (REGNO (nmask) == REGNO (dest)); + dest = nmask; + op0 = simplify_gen_subreg (vmode, op0, mode, 0); + x = gen_rtx_AND (vmode, dest, op0); + } + emit_insn (gen_rtx_SET (VOIDmode, dest, x)); + } + + x = gen_rtx_IOR (vmode, dest, scratch); + emit_insn (gen_rtx_SET (VOIDmode, dest, x)); +} + /* Return TRUE or FALSE depending on whether the first SET in INSN has source and destination with matching CC modes, and that the CC mode is at least as constrained as REQ_MODE. */ @@ -8683,10 +9697,8 @@ ix86_match_ccmode (rtx insn, enum machine_mode req_mode) set = PATTERN (insn); if (GET_CODE (set) == PARALLEL) set = XVECEXP (set, 0, 0); - if (GET_CODE (set) != SET) - abort (); - if (GET_CODE (SET_SRC (set)) != COMPARE) - abort (); + gcc_assert (GET_CODE (set) == SET); + gcc_assert (GET_CODE (SET_SRC (set)) == COMPARE); set_mode = GET_MODE (SET_DEST (set)); switch (set_mode) @@ -8713,7 +9725,7 @@ ix86_match_ccmode (rtx insn, enum machine_mode req_mode) break; default: - abort (); + gcc_unreachable (); } return (GET_MODE (SET_SRC (set)) == set_mode); @@ -8757,7 +9769,7 @@ ix86_fp_compare_mode (enum rtx_code code ATTRIBUTE_UNUSED) enum machine_mode ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1) { - if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_FLOAT) + if (SCALAR_FLOAT_MODE_P (GET_MODE (op0))) return ix86_fp_compare_mode (code); switch (code) { @@ -8795,7 +9807,7 @@ ix86_cc_mode (enum rtx_code code, rtx op0, rtx op1) case USE: return CCmode; default: - abort (); + gcc_unreachable (); } } @@ -8829,7 +9841,7 @@ ix86_cc_modes_compatible (enum machine_mode m1, enum machine_mode m2) switch (m1) { default: - abort (); + gcc_unreachable (); case CCmode: case CCGCmode: @@ -8878,15 +9890,20 @@ ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1) enum machine_mode fpcmp_mode = ix86_fp_compare_mode (code); rtx op0 = *pop0, op1 = *pop1; enum machine_mode op_mode = GET_MODE (op0); - int is_sse = SSE_REG_P (op0) | SSE_REG_P (op1); + int is_sse = TARGET_SSE_MATH && SSE_FLOAT_MODE_P (op_mode); /* All of the unordered compare instructions only work on registers. - The same is true of the XFmode compare instructions. The same is - true of the fcomi compare instructions. */ + The same is true of the fcomi compare instructions. The XFmode + compare instructions require registers except when comparing + against zero or when converting operand 1 from fixed point to + floating point. */ if (!is_sse && (fpcmp_mode == CCFPUmode - || op_mode == XFmode + || (op_mode == XFmode + && ! (standard_80387_constant_p (op0) == 1 + || standard_80387_constant_p (op1) == 1) + && GET_CODE (op1) != FLOAT) || ix86_use_fcomi_compare (code))) { op0 = force_reg (op_mode, op0); @@ -8913,10 +9930,16 @@ ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1) if (CONSTANT_P (op1)) { - if (standard_80387_constant_p (op1)) - op1 = force_reg (op_mode, op1); - else + int tmp = standard_80387_constant_p (op1); + if (tmp == 0) op1 = validize_mem (force_const_mem (op_mode, op1)); + else if (tmp == 1) + { + if (TARGET_CMOVE) + op1 = force_reg (op_mode, op1); + } + else + op1 = force_reg (op_mode, op1); } } @@ -8940,7 +9963,8 @@ ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1) /* Convert comparison codes we use to represent FP comparison to integer code that will result in proper branch. Return UNKNOWN if no such code is available. */ -static enum rtx_code + +enum rtx_code ix86_fp_compare_code_to_integer (enum rtx_code code) { switch (code) @@ -8973,16 +9997,17 @@ ix86_fp_compare_code_to_integer (enum rtx_code code) /* Split comparison code CODE into comparisons we can do using branch instructions. BYPASS_CODE is comparison code for branch that will branch around FIRST_CODE and SECOND_CODE. If some of branches - is not required, set value to NIL. + is not required, set value to UNKNOWN. We never require more than two branches. */ -static void + +void ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code, enum rtx_code *first_code, enum rtx_code *second_code) { *first_code = code; - *bypass_code = NIL; - *second_code = NIL; + *bypass_code = UNKNOWN; + *second_code = UNKNOWN; /* The fcomi comparison sets flags as follows: @@ -9028,12 +10053,12 @@ ix86_fp_comparison_codes (enum rtx_code code, enum rtx_code *bypass_code, *second_code = UNORDERED; break; default: - abort (); + gcc_unreachable (); } if (!TARGET_IEEE_FP) { - *second_code = NIL; - *bypass_code = NIL; + *second_code = UNKNOWN; + *bypass_code = UNKNOWN; } } @@ -9070,7 +10095,7 @@ ix86_fp_comparison_arithmetics_cost (enum rtx_code code) return 6; break; default: - abort (); + gcc_unreachable (); } } @@ -9085,7 +10110,7 @@ ix86_fp_comparison_fcomi_cost (enum rtx_code code) if (!TARGET_CMOVE) return 1024; ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code); - return (bypass_code != NIL || second_code != NIL) + 2; + return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 2; } /* Return cost of comparison done using sahf operation. @@ -9099,7 +10124,7 @@ ix86_fp_comparison_sahf_cost (enum rtx_code code) if (!TARGET_USE_SAHF && !optimize_size) return 1024; ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code); - return (bypass_code != NIL || second_code != NIL) + 3; + return (bypass_code != UNKNOWN || second_code != UNKNOWN) + 3; } /* Compute cost of the comparison done using any method. @@ -9143,8 +10168,8 @@ ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch, ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code); /* Do fcomi/sahf based test when profitable. */ - if ((bypass_code == NIL || bypass_test) - && (second_code == NIL || second_test) + if ((bypass_code == UNKNOWN || bypass_test) + && (second_code == UNKNOWN || second_test) && ix86_fp_comparison_arithmetics_cost (code) > cost) { if (TARGET_CMOVE) @@ -9167,11 +10192,11 @@ ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch, /* The FP codes work out to act like unsigned. */ intcmp_mode = fpcmp_mode; code = first_code; - if (bypass_code != NIL) + if (bypass_code != UNKNOWN) *bypass_test = gen_rtx_fmt_ee (bypass_code, VOIDmode, gen_rtx_REG (intcmp_mode, FLAGS_REG), const0_rtx); - if (second_code != NIL) + if (second_code != UNKNOWN) *second_test = gen_rtx_fmt_ee (second_code, VOIDmode, gen_rtx_REG (intcmp_mode, FLAGS_REG), const0_rtx); @@ -9297,7 +10322,7 @@ ix86_expand_fp_compare (enum rtx_code code, rtx op0, rtx op1, rtx scratch, break; default: - abort (); + gcc_unreachable (); } } @@ -9320,7 +10345,12 @@ ix86_expand_compare (enum rtx_code code, rtx *second_test, rtx *bypass_test) if (bypass_test) *bypass_test = NULL_RTX; - if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_FLOAT) + if (ix86_compare_emitted) + { + ret = gen_rtx_fmt_ee (code, VOIDmode, ix86_compare_emitted, const0_rtx); + ix86_compare_emitted = NULL_RTX; + } + else if (SCALAR_FLOAT_MODE_P (GET_MODE (op0))) ret = ix86_expand_fp_compare (code, op0, op1, NULL_RTX, second_test, bypass_test); else @@ -9337,7 +10367,7 @@ ix86_fp_jump_nontrivial_p (enum rtx_code code) if (!TARGET_CMOVE) return true; ix86_fp_comparison_codes (code, &bypass_code, &first_code, &second_code); - return bypass_code != NIL || second_code != NIL; + return bypass_code != UNKNOWN || second_code != UNKNOWN; } void @@ -9345,6 +10375,12 @@ ix86_expand_branch (enum rtx_code code, rtx label) { rtx tmp; + /* If we have emitted a compare insn, go straight to simple. + ix86_expand_compare won't emit anything if ix86_compare_emitted + is non NULL. */ + if (ix86_compare_emitted) + goto simple; + switch (GET_MODE (ix86_compare_op0)) { case QImode: @@ -9374,12 +10410,12 @@ ix86_expand_branch (enum rtx_code code, rtx label) /* Check whether we will use the natural sequence with one jump. If so, we can expand jump early. Otherwise delay expansion by creating compound insn to not confuse optimizers. */ - if (bypass_code == NIL && second_code == NIL + if (bypass_code == UNKNOWN && second_code == UNKNOWN && TARGET_CMOVE) { ix86_split_fp_branch (code, ix86_compare_op0, ix86_compare_op1, gen_rtx_LABEL_REF (VOIDmode, label), - pc_rtx, NULL_RTX); + pc_rtx, NULL_RTX, NULL_RTX); } else { @@ -9409,10 +10445,12 @@ ix86_expand_branch (enum rtx_code code, rtx label) case DImode: if (TARGET_64BIT) goto simple; + case TImode: /* Expand DImode branch into multiple compare+branch. */ { rtx lo[2], hi[2], label2; enum rtx_code code1, code2, code3; + enum machine_mode submode; if (CONSTANT_P (ix86_compare_op0) && ! CONSTANT_P (ix86_compare_op1)) { @@ -9421,8 +10459,18 @@ ix86_expand_branch (enum rtx_code code, rtx label) ix86_compare_op1 = tmp; code = swap_condition (code); } - split_di (&ix86_compare_op0, 1, lo+0, hi+0); - split_di (&ix86_compare_op1, 1, lo+1, hi+1); + if (GET_MODE (ix86_compare_op0) == DImode) + { + split_di (&ix86_compare_op0, 1, lo+0, hi+0); + split_di (&ix86_compare_op1, 1, lo+1, hi+1); + submode = SImode; + } + else + { + split_ti (&ix86_compare_op0, 1, lo+0, hi+0); + split_ti (&ix86_compare_op1, 1, lo+1, hi+1); + submode = DImode; + } /* When comparing for equality, we can use (hi0^hi1)|(lo0^lo1) to avoid two branches. This costs one extra insn, so disable when @@ -9436,15 +10484,15 @@ ix86_expand_branch (enum rtx_code code, rtx label) xor1 = hi[0]; if (hi[1] != const0_rtx) - xor1 = expand_binop (SImode, xor_optab, xor1, hi[1], + xor1 = expand_binop (submode, xor_optab, xor1, hi[1], NULL_RTX, 0, OPTAB_WIDEN); xor0 = lo[0]; if (lo[1] != const0_rtx) - xor0 = expand_binop (SImode, xor_optab, xor0, lo[1], + xor0 = expand_binop (submode, xor_optab, xor0, lo[1], NULL_RTX, 0, OPTAB_WIDEN); - tmp = expand_binop (SImode, ior_optab, xor1, xor0, + tmp = expand_binop (submode, ior_optab, xor1, xor0, NULL_RTX, 0, OPTAB_WIDEN); ix86_compare_op0 = tmp; @@ -9487,11 +10535,11 @@ ix86_expand_branch (enum rtx_code code, rtx label) case LEU: code1 = LTU; code2 = GTU; break; case GEU: code1 = GTU; code2 = LTU; break; - case EQ: code1 = NIL; code2 = NE; break; - case NE: code2 = NIL; break; + case EQ: code1 = UNKNOWN; code2 = NE; break; + case NE: code2 = UNKNOWN; break; default: - abort (); + gcc_unreachable (); } /* @@ -9505,29 +10553,29 @@ ix86_expand_branch (enum rtx_code code, rtx label) ix86_compare_op0 = hi[0]; ix86_compare_op1 = hi[1]; - if (code1 != NIL) + if (code1 != UNKNOWN) ix86_expand_branch (code1, label); - if (code2 != NIL) + if (code2 != UNKNOWN) ix86_expand_branch (code2, label2); ix86_compare_op0 = lo[0]; ix86_compare_op1 = lo[1]; ix86_expand_branch (code3, label); - if (code2 != NIL) + if (code2 != UNKNOWN) emit_label (label2); return; } default: - abort (); + gcc_unreachable (); } } /* Split branch based on floating point condition. */ void ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2, - rtx target1, rtx target2, rtx tmp) + rtx target1, rtx target2, rtx tmp, rtx pushed) { rtx second, bypass; rtx label = NULL_RTX; @@ -9546,6 +10594,10 @@ ix86_split_fp_branch (enum rtx_code code, rtx op1, rtx op2, condition = ix86_expand_fp_compare (code, op1, op2, tmp, &second, &bypass); + /* Remove pushed operand from stack. */ + if (pushed) + ix86_free_from_memory (GET_MODE (pushed)); + if (split_branch_probability >= 0) { /* Distribute the probabilities across the jumps. @@ -9608,12 +10660,10 @@ ix86_expand_setcc (enum rtx_code code, rtx dest) rtx ret, tmp, tmpreg, equiv; rtx second_test, bypass_test; - if (GET_MODE (ix86_compare_op0) == DImode - && !TARGET_64BIT) + if (GET_MODE (ix86_compare_op0) == (TARGET_64BIT ? TImode : DImode)) return 0; /* FAIL */ - if (GET_MODE (dest) != QImode) - abort (); + gcc_assert (GET_MODE (dest) == QImode); ret = ix86_expand_compare (code, &second_test, &bypass_test); PUT_MODE (ret, QImode); @@ -9629,8 +10679,7 @@ ix86_expand_setcc (enum rtx_code code, rtx dest) rtx tmp2 = gen_reg_rtx (QImode); if (bypass_test) { - if (second_test) - abort (); + gcc_assert (!second_test); test = bypass_test; bypass = 1; PUT_CODE (test, reverse_condition_maybe_unordered (GET_CODE (test))); @@ -9645,10 +10694,13 @@ ix86_expand_setcc (enum rtx_code code, rtx dest) } /* Attach a REG_EQUAL note describing the comparison result. */ - equiv = simplify_gen_relational (code, QImode, - GET_MODE (ix86_compare_op0), - ix86_compare_op0, ix86_compare_op1); - set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv); + if (ix86_compare_op0 && ix86_compare_op1) + { + equiv = simplify_gen_relational (code, QImode, + GET_MODE (ix86_compare_op0), + ix86_compare_op0, ix86_compare_op1); + set_unique_reg_note (get_last_insn (), REG_EQUAL, equiv); + } return 1; /* DONE */ } @@ -9661,9 +10713,9 @@ ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop) enum machine_mode mode = GET_MODE (op0) != VOIDmode ? GET_MODE (op0) : GET_MODE (op1); - /* Do not handle DImode compares that go trought special path. Also we can't + /* Do not handle DImode compares that go through special path. Also we can't deal with FP compares yet. This is possible to add. */ - if ((mode == DImode && !TARGET_64BIT)) + if (mode == (TARGET_64BIT ? TImode : DImode)) return false; if (FLOAT_MODE_P (mode)) { @@ -9775,8 +10827,7 @@ ix86_expand_carry_flag_compare (enum rtx_code code, rtx op0, rtx op1, rtx *pop) ix86_compare_op0 = op0; ix86_compare_op1 = op1; *pop = ix86_expand_compare (code, NULL, NULL); - if (GET_CODE (*pop) != LTU && GET_CODE (*pop) != GEU) - abort (); + gcc_assert (GET_CODE (*pop) == LTU || GET_CODE (*pop) == GEU); return true; } @@ -9804,7 +10855,7 @@ ix86_expand_int_movcc (rtx operands[]) HImode insns, we'd be swallowed in word prefix ops. */ if ((mode != HImode || TARGET_FAST_PREFIX) - && (mode != DImode || TARGET_64BIT) + && (mode != (TARGET_64BIT ? TImode : DImode)) && GET_CODE (operands[2]) == CONST_INT && GET_CODE (operands[3]) == CONST_INT) { @@ -9979,7 +11030,7 @@ ix86_expand_int_movcc (rtx operands[]) } } - compare_code = NIL; + compare_code = UNKNOWN; if (GET_MODE_CLASS (GET_MODE (ix86_compare_op0)) == MODE_INT && GET_CODE (ix86_compare_op1) == CONST_INT) { @@ -9996,7 +11047,7 @@ ix86_expand_int_movcc (rtx operands[]) } /* Optimize dest = (op0 < 0) ? -1 : cf. */ - if (compare_code != NIL + if (compare_code != UNKNOWN && GET_MODE (ix86_compare_op0) == GET_MODE (out) && (cf == -1 || ct == -1)) { @@ -10037,7 +11088,8 @@ ix86_expand_int_movcc (rtx operands[]) if ((diff == 1 || diff == 2 || diff == 4 || diff == 8 || diff == 3 || diff == 5 || diff == 9) && ((mode != QImode && mode != HImode) || !TARGET_PARTIAL_REG_STALL) - && (mode != DImode || x86_64_sign_extended_value (GEN_INT (cf)))) + && (mode != DImode + || x86_64_immediate_operand (GEN_INT (cf), VOIDmode))) { /* * xorl dest,dest @@ -10123,12 +11175,12 @@ ix86_expand_int_movcc (rtx operands[]) else { code = reverse_condition (code); - if (compare_code != NIL) + if (compare_code != UNKNOWN) compare_code = reverse_condition (compare_code); } } - if (compare_code != NIL) + if (compare_code != UNKNOWN) { /* notl op1 (if needed) sarl $31, op1 @@ -10291,121 +11343,233 @@ ix86_expand_int_movcc (rtx operands[]) return 1; /* DONE */ } -int -ix86_expand_fp_movcc (rtx operands[]) +/* Swap, force into registers, or otherwise massage the two operands + to an sse comparison with a mask result. Thus we differ a bit from + ix86_prepare_fp_compare_args which expects to produce a flags result. + + The DEST operand exists to help determine whether to commute commutative + operators. The POP0/POP1 operands are updated in place. The new + comparison code is returned, or UNKNOWN if not implementable. */ + +static enum rtx_code +ix86_prepare_sse_fp_compare_args (rtx dest, enum rtx_code code, + rtx *pop0, rtx *pop1) { - enum rtx_code code; rtx tmp; - rtx compare_op, second_test, bypass_test; - - /* For SF/DFmode conditional moves based on comparisons - in same mode, we may want to use SSE min/max instructions. */ - if (((TARGET_SSE_MATH && GET_MODE (operands[0]) == SFmode) - || (TARGET_SSE2 && TARGET_SSE_MATH && GET_MODE (operands[0]) == DFmode)) - && GET_MODE (ix86_compare_op0) == GET_MODE (operands[0]) - /* The SSE comparisons does not support the LTGT/UNEQ pair. */ - && (!TARGET_IEEE_FP - || (GET_CODE (operands[1]) != LTGT && GET_CODE (operands[1]) != UNEQ)) - /* We may be called from the post-reload splitter. */ - && (!REG_P (operands[0]) - || SSE_REG_P (operands[0]) - || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)) - { - rtx op0 = ix86_compare_op0, op1 = ix86_compare_op1; - code = GET_CODE (operands[1]); - - /* See if we have (cross) match between comparison operands and - conditional move operands. */ - if (rtx_equal_p (operands[2], op1)) - { - rtx tmp = op0; - op0 = op1; - op1 = tmp; - code = reverse_condition_maybe_unordered (code); - } - if (rtx_equal_p (operands[2], op0) && rtx_equal_p (operands[3], op1)) - { - /* Check for min operation. */ - if (code == LT || code == UNLE) - { - if (code == UNLE) - { - rtx tmp = op0; - op0 = op1; - op1 = tmp; - } - operands[0] = force_reg (GET_MODE (operands[0]), operands[0]); - if (memory_operand (op0, VOIDmode)) - op0 = force_reg (GET_MODE (operands[0]), op0); - if (GET_MODE (operands[0]) == SFmode) - emit_insn (gen_minsf3 (operands[0], op0, op1)); - else - emit_insn (gen_mindf3 (operands[0], op0, op1)); - return 1; - } - /* Check for max operation. */ - if (code == GT || code == UNGE) - { - if (code == UNGE) - { - rtx tmp = op0; - op0 = op1; - op1 = tmp; - } - operands[0] = force_reg (GET_MODE (operands[0]), operands[0]); - if (memory_operand (op0, VOIDmode)) - op0 = force_reg (GET_MODE (operands[0]), op0); - if (GET_MODE (operands[0]) == SFmode) - emit_insn (gen_maxsf3 (operands[0], op0, op1)); - else - emit_insn (gen_maxdf3 (operands[0], op0, op1)); - return 1; - } - } - /* Manage condition to be sse_comparison_operator. In case we are - in non-ieee mode, try to canonicalize the destination operand - to be first in the comparison - this helps reload to avoid extra - moves. */ - if (!sse_comparison_operator (operands[1], VOIDmode) - || (rtx_equal_p (operands[0], ix86_compare_op1) && !TARGET_IEEE_FP)) - { - rtx tmp = ix86_compare_op0; - ix86_compare_op0 = ix86_compare_op1; - ix86_compare_op1 = tmp; - operands[1] = gen_rtx_fmt_ee (swap_condition (GET_CODE (operands[1])), - VOIDmode, ix86_compare_op0, - ix86_compare_op1); - } - /* Similarly try to manage result to be first operand of conditional - move. We also don't support the NE comparison on SSE, so try to - avoid it. */ - if ((rtx_equal_p (operands[0], operands[3]) - && (!TARGET_IEEE_FP || GET_CODE (operands[1]) != EQ)) - || (GET_CODE (operands[1]) == NE && TARGET_IEEE_FP)) - { - rtx tmp = operands[2]; - operands[2] = operands[3]; - operands[3] = tmp; - operands[1] = gen_rtx_fmt_ee (reverse_condition_maybe_unordered - (GET_CODE (operands[1])), - VOIDmode, ix86_compare_op0, - ix86_compare_op1); - } - if (GET_MODE (operands[0]) == SFmode) - emit_insn (gen_sse_movsfcc (operands[0], operands[1], - operands[2], operands[3], - ix86_compare_op0, ix86_compare_op1)); + + switch (code) + { + case LTGT: + case UNEQ: + /* We have no LTGT as an operator. We could implement it with + NE & ORDERED, but this requires an extra temporary. It's + not clear that it's worth it. */ + return UNKNOWN; + + case LT: + case LE: + case UNGT: + case UNGE: + /* These are supported directly. */ + break; + + case EQ: + case NE: + case UNORDERED: + case ORDERED: + /* For commutative operators, try to canonicalize the destination + operand to be first in the comparison - this helps reload to + avoid extra moves. */ + if (!dest || !rtx_equal_p (dest, *pop1)) + break; + /* FALLTHRU */ + + case GE: + case GT: + case UNLE: + case UNLT: + /* These are not supported directly. Swap the comparison operands + to transform into something that is supported. */ + tmp = *pop0; + *pop0 = *pop1; + *pop1 = tmp; + code = swap_condition (code); + break; + + default: + gcc_unreachable (); + } + + return code; +} + +/* Detect conditional moves that exactly match min/max operational + semantics. Note that this is IEEE safe, as long as we don't + interchange the operands. + + Returns FALSE if this conditional move doesn't match a MIN/MAX, + and TRUE if the operation is successful and instructions are emitted. */ + +static bool +ix86_expand_sse_fp_minmax (rtx dest, enum rtx_code code, rtx cmp_op0, + rtx cmp_op1, rtx if_true, rtx if_false) +{ + enum machine_mode mode; + bool is_min; + rtx tmp; + + if (code == LT) + ; + else if (code == UNGE) + { + tmp = if_true; + if_true = if_false; + if_false = tmp; + } + else + return false; + + if (rtx_equal_p (cmp_op0, if_true) && rtx_equal_p (cmp_op1, if_false)) + is_min = true; + else if (rtx_equal_p (cmp_op1, if_true) && rtx_equal_p (cmp_op0, if_false)) + is_min = false; + else + return false; + + mode = GET_MODE (dest); + + /* We want to check HONOR_NANS and HONOR_SIGNED_ZEROS here, + but MODE may be a vector mode and thus not appropriate. */ + if (!flag_finite_math_only || !flag_unsafe_math_optimizations) + { + int u = is_min ? UNSPEC_IEEE_MIN : UNSPEC_IEEE_MAX; + rtvec v; + + if_true = force_reg (mode, if_true); + v = gen_rtvec (2, if_true, if_false); + tmp = gen_rtx_UNSPEC (mode, v, u); + } + else + { + code = is_min ? SMIN : SMAX; + tmp = gen_rtx_fmt_ee (code, mode, if_true, if_false); + } + + emit_insn (gen_rtx_SET (VOIDmode, dest, tmp)); + return true; +} + +/* Expand an sse vector comparison. Return the register with the result. */ + +static rtx +ix86_expand_sse_cmp (rtx dest, enum rtx_code code, rtx cmp_op0, rtx cmp_op1, + rtx op_true, rtx op_false) +{ + enum machine_mode mode = GET_MODE (dest); + rtx x; + + cmp_op0 = force_reg (mode, cmp_op0); + if (!nonimmediate_operand (cmp_op1, mode)) + cmp_op1 = force_reg (mode, cmp_op1); + + if (optimize + || reg_overlap_mentioned_p (dest, op_true) + || reg_overlap_mentioned_p (dest, op_false)) + dest = gen_reg_rtx (mode); + + x = gen_rtx_fmt_ee (code, mode, cmp_op0, cmp_op1); + emit_insn (gen_rtx_SET (VOIDmode, dest, x)); + + return dest; +} + +/* Expand DEST = CMP ? OP_TRUE : OP_FALSE into a sequence of logical + operations. This is used for both scalar and vector conditional moves. */ + +static void +ix86_expand_sse_movcc (rtx dest, rtx cmp, rtx op_true, rtx op_false) +{ + enum machine_mode mode = GET_MODE (dest); + rtx t2, t3, x; + + if (op_false == CONST0_RTX (mode)) + { + op_true = force_reg (mode, op_true); + x = gen_rtx_AND (mode, cmp, op_true); + emit_insn (gen_rtx_SET (VOIDmode, dest, x)); + } + else if (op_true == CONST0_RTX (mode)) + { + op_false = force_reg (mode, op_false); + x = gen_rtx_NOT (mode, cmp); + x = gen_rtx_AND (mode, x, op_false); + emit_insn (gen_rtx_SET (VOIDmode, dest, x)); + } + else + { + op_true = force_reg (mode, op_true); + op_false = force_reg (mode, op_false); + + t2 = gen_reg_rtx (mode); + if (optimize) + t3 = gen_reg_rtx (mode); else - emit_insn (gen_sse_movdfcc (operands[0], operands[1], - operands[2], operands[3], - ix86_compare_op0, ix86_compare_op1)); + t3 = dest; + + x = gen_rtx_AND (mode, op_true, cmp); + emit_insn (gen_rtx_SET (VOIDmode, t2, x)); + + x = gen_rtx_NOT (mode, cmp); + x = gen_rtx_AND (mode, x, op_false); + emit_insn (gen_rtx_SET (VOIDmode, t3, x)); + + x = gen_rtx_IOR (mode, t3, t2); + emit_insn (gen_rtx_SET (VOIDmode, dest, x)); + } +} + +/* Expand a floating-point conditional move. Return true if successful. */ + +int +ix86_expand_fp_movcc (rtx operands[]) +{ + enum machine_mode mode = GET_MODE (operands[0]); + enum rtx_code code = GET_CODE (operands[1]); + rtx tmp, compare_op, second_test, bypass_test; + + if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode)) + { + enum machine_mode cmode; + + /* Since we've no cmove for sse registers, don't force bad register + allocation just to gain access to it. Deny movcc when the + comparison mode doesn't match the move mode. */ + cmode = GET_MODE (ix86_compare_op0); + if (cmode == VOIDmode) + cmode = GET_MODE (ix86_compare_op1); + if (cmode != mode) + return 0; + + code = ix86_prepare_sse_fp_compare_args (operands[0], code, + &ix86_compare_op0, + &ix86_compare_op1); + if (code == UNKNOWN) + return 0; + + if (ix86_expand_sse_fp_minmax (operands[0], code, ix86_compare_op0, + ix86_compare_op1, operands[2], + operands[3])) + return 1; + + tmp = ix86_expand_sse_cmp (operands[0], code, ix86_compare_op0, + ix86_compare_op1, operands[2], operands[3]); + ix86_expand_sse_movcc (operands[0], tmp, operands[2], operands[3]); return 1; } /* The floating point conditional move instructions don't directly support conditions resulting from a signed integer comparison. */ - code = GET_CODE (operands[1]); compare_op = ix86_expand_compare (code, &second_test, &bypass_test); /* The floating point conditional move instructions don't directly @@ -10413,8 +11577,7 @@ ix86_expand_fp_movcc (rtx operands[]) if (!fcmov_comparison_operator (compare_op, VOIDmode)) { - if (second_test != NULL || bypass_test != NULL) - abort (); + gcc_assert (!second_test && !bypass_test); tmp = gen_reg_rtx (QImode); ix86_expand_setcc (code, tmp); code = NE; @@ -10424,38 +11587,160 @@ ix86_expand_fp_movcc (rtx operands[]) } if (bypass_test && reg_overlap_mentioned_p (operands[0], operands[3])) { - tmp = gen_reg_rtx (GET_MODE (operands[0])); + tmp = gen_reg_rtx (mode); emit_move_insn (tmp, operands[3]); operands[3] = tmp; } if (second_test && reg_overlap_mentioned_p (operands[0], operands[2])) { - tmp = gen_reg_rtx (GET_MODE (operands[0])); + tmp = gen_reg_rtx (mode); emit_move_insn (tmp, operands[2]); operands[2] = tmp; } emit_insn (gen_rtx_SET (VOIDmode, operands[0], - gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), - compare_op, - operands[2], - operands[3]))); + gen_rtx_IF_THEN_ELSE (mode, compare_op, + operands[2], operands[3]))); if (bypass_test) emit_insn (gen_rtx_SET (VOIDmode, operands[0], - gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), - bypass_test, - operands[3], - operands[0]))); + gen_rtx_IF_THEN_ELSE (mode, bypass_test, + operands[3], operands[0]))); if (second_test) emit_insn (gen_rtx_SET (VOIDmode, operands[0], - gen_rtx_IF_THEN_ELSE (GET_MODE (operands[0]), - second_test, - operands[2], - operands[0]))); + gen_rtx_IF_THEN_ELSE (mode, second_test, + operands[2], operands[0]))); return 1; } +/* Expand a floating-point vector conditional move; a vcond operation + rather than a movcc operation. */ + +bool +ix86_expand_fp_vcond (rtx operands[]) +{ + enum rtx_code code = GET_CODE (operands[3]); + rtx cmp; + + code = ix86_prepare_sse_fp_compare_args (operands[0], code, + &operands[4], &operands[5]); + if (code == UNKNOWN) + return false; + + if (ix86_expand_sse_fp_minmax (operands[0], code, operands[4], + operands[5], operands[1], operands[2])) + return true; + + cmp = ix86_expand_sse_cmp (operands[0], code, operands[4], operands[5], + operands[1], operands[2]); + ix86_expand_sse_movcc (operands[0], cmp, operands[1], operands[2]); + return true; +} + +/* Expand a signed integral vector conditional move. */ + +bool +ix86_expand_int_vcond (rtx operands[]) +{ + enum machine_mode mode = GET_MODE (operands[0]); + enum rtx_code code = GET_CODE (operands[3]); + bool negate = false; + rtx x, cop0, cop1; + + cop0 = operands[4]; + cop1 = operands[5]; + + /* Canonicalize the comparison to EQ, GT, GTU. */ + switch (code) + { + case EQ: + case GT: + case GTU: + break; + + case NE: + case LE: + case LEU: + code = reverse_condition (code); + negate = true; + break; + + case GE: + case GEU: + code = reverse_condition (code); + negate = true; + /* FALLTHRU */ + + case LT: + case LTU: + code = swap_condition (code); + x = cop0, cop0 = cop1, cop1 = x; + break; + + default: + gcc_unreachable (); + } + + /* Unsigned parallel compare is not supported by the hardware. Play some + tricks to turn this into a signed comparison against 0. */ + if (code == GTU) + { + cop0 = force_reg (mode, cop0); + + switch (mode) + { + case V4SImode: + { + rtx t1, t2, mask; + + /* Perform a parallel modulo subtraction. */ + t1 = gen_reg_rtx (mode); + emit_insn (gen_subv4si3 (t1, cop0, cop1)); + + /* Extract the original sign bit of op0. */ + mask = GEN_INT (-0x80000000); + mask = gen_rtx_CONST_VECTOR (mode, + gen_rtvec (4, mask, mask, mask, mask)); + mask = force_reg (mode, mask); + t2 = gen_reg_rtx (mode); + emit_insn (gen_andv4si3 (t2, cop0, mask)); + + /* XOR it back into the result of the subtraction. This results + in the sign bit set iff we saw unsigned underflow. */ + x = gen_reg_rtx (mode); + emit_insn (gen_xorv4si3 (x, t1, t2)); + + code = GT; + } + break; + + case V16QImode: + case V8HImode: + /* Perform a parallel unsigned saturating subtraction. */ + x = gen_reg_rtx (mode); + emit_insn (gen_rtx_SET (VOIDmode, x, + gen_rtx_US_MINUS (mode, cop0, cop1))); + + code = EQ; + negate = !negate; + break; + + default: + gcc_unreachable (); + } + + cop0 = x; + cop1 = CONST0_RTX (mode); + } + + x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1, + operands[1+negate], operands[2-negate]); + + ix86_expand_sse_movcc (operands[0], x, operands[1+negate], + operands[2-negate]); + return true; +} + /* Expand conditional increment or decrement using adb/sbb instructions. The default case using setcc followed by the conditional move can be done by generic code. */ @@ -10513,7 +11798,7 @@ ix86_expand_int_addcc (rtx operands[]) emit_insn (gen_subdi3_carry_rex64 (operands[0], operands[2], val, compare_op)); break; default: - abort (); + gcc_unreachable (); } } else @@ -10533,7 +11818,7 @@ ix86_expand_int_addcc (rtx operands[]) emit_insn (gen_adddi3_carry_rex64 (operands[0], operands[2], val, compare_op)); break; default: - abort (); + gcc_unreachable (); } } return 1; /* DONE */ @@ -10555,14 +11840,12 @@ ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode) else size = (GET_MODE_SIZE (mode) + 4) / 8; - if (GET_CODE (operand) == REG && MMX_REGNO_P (REGNO (operand))) - abort (); - if (size < 2 || size > 3) - abort (); + gcc_assert (GET_CODE (operand) != REG || !MMX_REGNO_P (REGNO (operand))); + gcc_assert (size >= 2 && size <= 3); /* Optimize constant pool reference to immediates. This is used by fp moves, that force all constants to memory to allow combining. */ - if (GET_CODE (operand) == MEM && RTX_UNCHANGING_P (operand)) + if (GET_CODE (operand) == MEM && MEM_READONLY_P (operand)) { rtx tmp = maybe_get_pool_constant (operand); if (tmp) @@ -10572,14 +11855,28 @@ ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode) if (GET_CODE (operand) == MEM && !offsettable_memref_p (operand)) { /* The only non-offsetable memories we handle are pushes. */ - if (! push_operand (operand, VOIDmode)) - abort (); + int ok = push_operand (operand, VOIDmode); + + gcc_assert (ok); operand = copy_rtx (operand); PUT_MODE (operand, Pmode); parts[0] = parts[1] = parts[2] = operand; + return size; } - else if (!TARGET_64BIT) + + if (GET_CODE (operand) == CONST_VECTOR) + { + enum machine_mode imode = int_mode_for_mode (mode); + /* Caution: if we looked through a constant pool memory above, + the operand may actually have a different mode now. That's + ok, since we want to pun this all the way back to an integer. */ + operand = simplify_subreg (imode, operand, GET_MODE (operand), 0); + gcc_assert (operand != NULL); + mode = imode; + } + + if (!TARGET_64BIT) { if (mode == DImode) split_di (&operand, 1, &parts[0], &parts[1]); @@ -10587,8 +11884,7 @@ ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode) { if (REG_P (operand)) { - if (!reload_completed) - abort (); + gcc_assert (reload_completed); parts[0] = gen_rtx_REG (SImode, REGNO (operand) + 0); parts[1] = gen_rtx_REG (SImode, REGNO (operand) + 1); if (size == 3) @@ -10618,13 +11914,13 @@ ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode) REAL_VALUE_TO_TARGET_DOUBLE (r, l); break; default: - abort (); + gcc_unreachable (); } parts[1] = gen_int_mode (l[1], SImode); parts[0] = gen_int_mode (l[0], SImode); } else - abort (); + gcc_unreachable (); } } else @@ -10636,8 +11932,7 @@ ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode) enum machine_mode upper_mode = mode==XFmode ? SImode : DImode; if (REG_P (operand)) { - if (!reload_completed) - abort (); + gcc_assert (reload_completed); parts[0] = gen_rtx_REG (DImode, REGNO (operand) + 0); parts[1] = gen_rtx_REG (upper_mode, REGNO (operand) + 1); } @@ -10677,7 +11972,7 @@ ix86_split_to_parts (rtx operand, rtx *parts, enum machine_mode mode) parts[1] = immed_double_const (l[2], l[3], DImode); } else - abort (); + gcc_unreachable (); } } @@ -10725,9 +12020,9 @@ ix86_split_long_move (rtx operands[]) /* The only non-offsettable memory we handle is push. */ if (push_operand (operands[0], VOIDmode)) push = 1; - else if (GET_CODE (operands[0]) == MEM - && ! offsettable_memref_p (operands[0])) - abort (); + else + gcc_assert (GET_CODE (operands[0]) != MEM + || offsettable_memref_p (operands[0])); nparts = ix86_split_to_parts (operands[1], part[1], GET_MODE (operands[0])); ix86_split_to_parts (operands[0], part[0], GET_MODE (operands[0])); @@ -10808,12 +12103,20 @@ ix86_split_long_move (rtx operands[]) moving of second half of TFmode value. */ if (GET_MODE (part[1][1]) == SImode) { - if (GET_CODE (part[1][1]) == MEM) - part[1][1] = adjust_address (part[1][1], DImode, 0); - else if (REG_P (part[1][1])) - part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1])); - else - abort (); + switch (GET_CODE (part[1][1])) + { + case MEM: + part[1][1] = adjust_address (part[1][1], DImode, 0); + break; + + case REG: + part[1][1] = gen_rtx_REG (DImode, REGNO (part[1][1])); + break; + + default: + gcc_unreachable (); + } + if (GET_MODE (part[1][0]) == SImode) part[1][0] = part[1][1]; } @@ -10868,6 +12171,33 @@ ix86_split_long_move (rtx operands[]) operands[6] = part[1][1]; } } + + /* If optimizing for size, attempt to locally unCSE nonzero constants. */ + if (optimize_size) + { + if (GET_CODE (operands[5]) == CONST_INT + && operands[5] != const0_rtx + && REG_P (operands[2])) + { + if (GET_CODE (operands[6]) == CONST_INT + && INTVAL (operands[6]) == INTVAL (operands[5])) + operands[6] = operands[2]; + + if (nparts == 3 + && GET_CODE (operands[7]) == CONST_INT + && INTVAL (operands[7]) == INTVAL (operands[5])) + operands[7] = operands[2]; + } + + if (nparts == 3 + && GET_CODE (operands[6]) == CONST_INT + && operands[6] != const0_rtx + && REG_P (operands[3]) + && GET_CODE (operands[7]) == CONST_INT + && INTVAL (operands[7]) == INTVAL (operands[6])) + operands[7] = operands[3]; + } + emit_move_insn (operands[2], operands[5]); emit_move_insn (operands[3], operands[6]); if (nparts == 3) @@ -10876,90 +12206,209 @@ ix86_split_long_move (rtx operands[]) return; } +/* Helper function of ix86_split_ashl used to generate an SImode/DImode + left shift by a constant, either using a single shift or + a sequence of add instructions. */ + +static void +ix86_expand_ashl_const (rtx operand, int count, enum machine_mode mode) +{ + if (count == 1) + { + emit_insn ((mode == DImode + ? gen_addsi3 + : gen_adddi3) (operand, operand, operand)); + } + else if (!optimize_size + && count * ix86_cost->add <= ix86_cost->shift_const) + { + int i; + for (i=0; i<count; i++) + { + emit_insn ((mode == DImode + ? gen_addsi3 + : gen_adddi3) (operand, operand, operand)); + } + } + else + emit_insn ((mode == DImode + ? gen_ashlsi3 + : gen_ashldi3) (operand, operand, GEN_INT (count))); +} + void -ix86_split_ashldi (rtx *operands, rtx scratch) +ix86_split_ashl (rtx *operands, rtx scratch, enum machine_mode mode) { rtx low[2], high[2]; int count; + const int single_width = mode == DImode ? 32 : 64; if (GET_CODE (operands[2]) == CONST_INT) { - split_di (operands, 2, low, high); - count = INTVAL (operands[2]) & 63; + (mode == DImode ? split_di : split_ti) (operands, 2, low, high); + count = INTVAL (operands[2]) & (single_width * 2 - 1); - if (count >= 32) + if (count >= single_width) { emit_move_insn (high[0], low[1]); emit_move_insn (low[0], const0_rtx); - if (count > 32) - emit_insn (gen_ashlsi3 (high[0], high[0], GEN_INT (count - 32))); + if (count > single_width) + ix86_expand_ashl_const (high[0], count - single_width, mode); } else { if (!rtx_equal_p (operands[0], operands[1])) emit_move_insn (operands[0], operands[1]); - emit_insn (gen_x86_shld_1 (high[0], low[0], GEN_INT (count))); - emit_insn (gen_ashlsi3 (low[0], low[0], GEN_INT (count))); + emit_insn ((mode == DImode + ? gen_x86_shld_1 + : gen_x86_64_shld) (high[0], low[0], GEN_INT (count))); + ix86_expand_ashl_const (low[0], count, mode); } + return; } - else + + (mode == DImode ? split_di : split_ti) (operands, 1, low, high); + + if (operands[1] == const1_rtx) { - if (!rtx_equal_p (operands[0], operands[1])) - emit_move_insn (operands[0], operands[1]); + /* Assuming we've chosen a QImode capable registers, then 1 << N + can be done with two 32/64-bit shifts, no branches, no cmoves. */ + if (ANY_QI_REG_P (low[0]) && ANY_QI_REG_P (high[0])) + { + rtx s, d, flags = gen_rtx_REG (CCZmode, FLAGS_REG); - split_di (operands, 1, low, high); + ix86_expand_clear (low[0]); + ix86_expand_clear (high[0]); + emit_insn (gen_testqi_ccz_1 (operands[2], GEN_INT (single_width))); - emit_insn (gen_x86_shld_1 (high[0], low[0], operands[2])); - emit_insn (gen_ashlsi3 (low[0], low[0], operands[2])); + d = gen_lowpart (QImode, low[0]); + d = gen_rtx_STRICT_LOW_PART (VOIDmode, d); + s = gen_rtx_EQ (QImode, flags, const0_rtx); + emit_insn (gen_rtx_SET (VOIDmode, d, s)); - if (TARGET_CMOVE && (! no_new_pseudos || scratch)) + d = gen_lowpart (QImode, high[0]); + d = gen_rtx_STRICT_LOW_PART (VOIDmode, d); + s = gen_rtx_NE (QImode, flags, const0_rtx); + emit_insn (gen_rtx_SET (VOIDmode, d, s)); + } + + /* Otherwise, we can get the same results by manually performing + a bit extract operation on bit 5/6, and then performing the two + shifts. The two methods of getting 0/1 into low/high are exactly + the same size. Avoiding the shift in the bit extract case helps + pentium4 a bit; no one else seems to care much either way. */ + else { - if (! no_new_pseudos) - scratch = force_reg (SImode, const0_rtx); - else - emit_move_insn (scratch, const0_rtx); + rtx x; - emit_insn (gen_x86_shift_adj_1 (high[0], low[0], operands[2], - scratch)); + if (TARGET_PARTIAL_REG_STALL && !optimize_size) + x = gen_rtx_ZERO_EXTEND (mode == DImode ? SImode : DImode, operands[2]); + else + x = gen_lowpart (mode == DImode ? SImode : DImode, operands[2]); + emit_insn (gen_rtx_SET (VOIDmode, high[0], x)); + + emit_insn ((mode == DImode + ? gen_lshrsi3 + : gen_lshrdi3) (high[0], high[0], GEN_INT (mode == DImode ? 5 : 6))); + emit_insn ((mode == DImode + ? gen_andsi3 + : gen_anddi3) (high[0], high[0], GEN_INT (1))); + emit_move_insn (low[0], high[0]); + emit_insn ((mode == DImode + ? gen_xorsi3 + : gen_xordi3) (low[0], low[0], GEN_INT (1))); } + + emit_insn ((mode == DImode + ? gen_ashlsi3 + : gen_ashldi3) (low[0], low[0], operands[2])); + emit_insn ((mode == DImode + ? gen_ashlsi3 + : gen_ashldi3) (high[0], high[0], operands[2])); + return; + } + + if (operands[1] == constm1_rtx) + { + /* For -1 << N, we can avoid the shld instruction, because we + know that we're shifting 0...31/63 ones into a -1. */ + emit_move_insn (low[0], constm1_rtx); + if (optimize_size) + emit_move_insn (high[0], low[0]); else - emit_insn (gen_x86_shift_adj_2 (high[0], low[0], operands[2])); + emit_move_insn (high[0], constm1_rtx); + } + else + { + if (!rtx_equal_p (operands[0], operands[1])) + emit_move_insn (operands[0], operands[1]); + + (mode == DImode ? split_di : split_ti) (operands, 1, low, high); + emit_insn ((mode == DImode + ? gen_x86_shld_1 + : gen_x86_64_shld) (high[0], low[0], operands[2])); } + + emit_insn ((mode == DImode ? gen_ashlsi3 : gen_ashldi3) (low[0], low[0], operands[2])); + + if (TARGET_CMOVE && scratch) + { + ix86_expand_clear (scratch); + emit_insn ((mode == DImode + ? gen_x86_shift_adj_1 + : gen_x86_64_shift_adj) (high[0], low[0], operands[2], scratch)); + } + else + emit_insn (gen_x86_shift_adj_2 (high[0], low[0], operands[2])); } void -ix86_split_ashrdi (rtx *operands, rtx scratch) +ix86_split_ashr (rtx *operands, rtx scratch, enum machine_mode mode) { rtx low[2], high[2]; int count; + const int single_width = mode == DImode ? 32 : 64; if (GET_CODE (operands[2]) == CONST_INT) { - split_di (operands, 2, low, high); - count = INTVAL (operands[2]) & 63; + (mode == DImode ? split_di : split_ti) (operands, 2, low, high); + count = INTVAL (operands[2]) & (single_width * 2 - 1); - if (count >= 32) + if (count == single_width * 2 - 1) { - emit_move_insn (low[0], high[1]); + emit_move_insn (high[0], high[1]); + emit_insn ((mode == DImode + ? gen_ashrsi3 + : gen_ashrdi3) (high[0], high[0], + GEN_INT (single_width - 1))); + emit_move_insn (low[0], high[0]); - if (! reload_completed) - emit_insn (gen_ashrsi3 (high[0], low[0], GEN_INT (31))); - else - { - emit_move_insn (high[0], low[0]); - emit_insn (gen_ashrsi3 (high[0], high[0], GEN_INT (31))); - } - - if (count > 32) - emit_insn (gen_ashrsi3 (low[0], low[0], GEN_INT (count - 32))); + } + else if (count >= single_width) + { + emit_move_insn (low[0], high[1]); + emit_move_insn (high[0], low[0]); + emit_insn ((mode == DImode + ? gen_ashrsi3 + : gen_ashrdi3) (high[0], high[0], + GEN_INT (single_width - 1))); + if (count > single_width) + emit_insn ((mode == DImode + ? gen_ashrsi3 + : gen_ashrdi3) (low[0], low[0], + GEN_INT (count - single_width))); } else { if (!rtx_equal_p (operands[0], operands[1])) emit_move_insn (operands[0], operands[1]); - emit_insn (gen_x86_shrd_1 (low[0], high[0], GEN_INT (count))); - emit_insn (gen_ashrsi3 (high[0], high[0], GEN_INT (count))); + emit_insn ((mode == DImode + ? gen_x86_shrd_1 + : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count))); + emit_insn ((mode == DImode + ? gen_ashrsi3 + : gen_ashrdi3) (high[0], high[0], GEN_INT (count))); } } else @@ -10967,19 +12416,26 @@ ix86_split_ashrdi (rtx *operands, rtx scratch) if (!rtx_equal_p (operands[0], operands[1])) emit_move_insn (operands[0], operands[1]); - split_di (operands, 1, low, high); + (mode == DImode ? split_di : split_ti) (operands, 1, low, high); - emit_insn (gen_x86_shrd_1 (low[0], high[0], operands[2])); - emit_insn (gen_ashrsi3 (high[0], high[0], operands[2])); + emit_insn ((mode == DImode + ? gen_x86_shrd_1 + : gen_x86_64_shrd) (low[0], high[0], operands[2])); + emit_insn ((mode == DImode + ? gen_ashrsi3 + : gen_ashrdi3) (high[0], high[0], operands[2])); - if (TARGET_CMOVE && (! no_new_pseudos || scratch)) + if (TARGET_CMOVE && scratch) { - if (! no_new_pseudos) - scratch = gen_reg_rtx (SImode); emit_move_insn (scratch, high[0]); - emit_insn (gen_ashrsi3 (scratch, scratch, GEN_INT (31))); - emit_insn (gen_x86_shift_adj_1 (low[0], high[0], operands[2], - scratch)); + emit_insn ((mode == DImode + ? gen_ashrsi3 + : gen_ashrdi3) (scratch, scratch, + GEN_INT (single_width - 1))); + emit_insn ((mode == DImode + ? gen_x86_shift_adj_1 + : gen_x86_64_shift_adj) (low[0], high[0], operands[2], + scratch)); } else emit_insn (gen_x86_shift_adj_3 (low[0], high[0], operands[2])); @@ -10987,30 +12443,38 @@ ix86_split_ashrdi (rtx *operands, rtx scratch) } void -ix86_split_lshrdi (rtx *operands, rtx scratch) +ix86_split_lshr (rtx *operands, rtx scratch, enum machine_mode mode) { rtx low[2], high[2]; int count; + const int single_width = mode == DImode ? 32 : 64; if (GET_CODE (operands[2]) == CONST_INT) { - split_di (operands, 2, low, high); - count = INTVAL (operands[2]) & 63; + (mode == DImode ? split_di : split_ti) (operands, 2, low, high); + count = INTVAL (operands[2]) & (single_width * 2 - 1); - if (count >= 32) + if (count >= single_width) { emit_move_insn (low[0], high[1]); - emit_move_insn (high[0], const0_rtx); + ix86_expand_clear (high[0]); - if (count > 32) - emit_insn (gen_lshrsi3 (low[0], low[0], GEN_INT (count - 32))); + if (count > single_width) + emit_insn ((mode == DImode + ? gen_lshrsi3 + : gen_lshrdi3) (low[0], low[0], + GEN_INT (count - single_width))); } else { if (!rtx_equal_p (operands[0], operands[1])) emit_move_insn (operands[0], operands[1]); - emit_insn (gen_x86_shrd_1 (low[0], high[0], GEN_INT (count))); - emit_insn (gen_lshrsi3 (high[0], high[0], GEN_INT (count))); + emit_insn ((mode == DImode + ? gen_x86_shrd_1 + : gen_x86_64_shrd) (low[0], high[0], GEN_INT (count))); + emit_insn ((mode == DImode + ? gen_lshrsi3 + : gen_lshrdi3) (high[0], high[0], GEN_INT (count))); } } else @@ -11018,21 +12482,23 @@ ix86_split_lshrdi (rtx *operands, rtx scratch) if (!rtx_equal_p (operands[0], operands[1])) emit_move_insn (operands[0], operands[1]); - split_di (operands, 1, low, high); + (mode == DImode ? split_di : split_ti) (operands, 1, low, high); - emit_insn (gen_x86_shrd_1 (low[0], high[0], operands[2])); - emit_insn (gen_lshrsi3 (high[0], high[0], operands[2])); + emit_insn ((mode == DImode + ? gen_x86_shrd_1 + : gen_x86_64_shrd) (low[0], high[0], operands[2])); + emit_insn ((mode == DImode + ? gen_lshrsi3 + : gen_lshrdi3) (high[0], high[0], operands[2])); /* Heh. By reversing the arguments, we can reuse this pattern. */ - if (TARGET_CMOVE && (! no_new_pseudos || scratch)) + if (TARGET_CMOVE && scratch) { - if (! no_new_pseudos) - scratch = force_reg (SImode, const0_rtx); - else - emit_move_insn (scratch, const0_rtx); - - emit_insn (gen_x86_shift_adj_1 (low[0], high[0], operands[2], - scratch)); + ix86_expand_clear (scratch); + emit_insn ((mode == DImode + ? gen_x86_shift_adj_1 + : gen_x86_64_shift_adj) (low[0], high[0], operands[2], + scratch)); } else emit_insn (gen_x86_shift_adj_2 (low[0], high[0], operands[2])); @@ -11080,9 +12546,9 @@ ix86_zero_extend_to_Pmode (rtx exp) } /* Expand string move (memcpy) operation. Use i386 string operations when - profitable. expand_clrstr contains similar code. */ + profitable. expand_clrmem contains similar code. */ int -ix86_expand_movstr (rtx dst, rtx src, rtx count_exp, rtx align_exp) +ix86_expand_movmem (rtx dst, rtx src, rtx count_exp, rtx align_exp) { rtx srcreg, destreg, countreg, srcexp, destexp; enum machine_mode counter_mode; @@ -11110,14 +12576,14 @@ ix86_expand_movstr (rtx dst, rtx src, rtx count_exp, rtx align_exp) /* Figure out proper mode for counter. For 32bits it is always SImode, for 64bits use SImode when possible, otherwise DImode. Set count to number of bytes copied when known at compile time. */ - if (!TARGET_64BIT || GET_MODE (count_exp) == SImode - || x86_64_zero_extended_value (count_exp)) + if (!TARGET_64BIT + || GET_MODE (count_exp) == SImode + || x86_64_zext_immediate_operand (count_exp, VOIDmode)) counter_mode = SImode; else counter_mode = DImode; - if (counter_mode != SImode && counter_mode != DImode) - abort (); + gcc_assert (counter_mode == SImode || counter_mode == DImode); destreg = copy_to_mode_reg (Pmode, XEXP (dst, 0)); if (destreg != XEXP (dst, 0)) @@ -11127,9 +12593,20 @@ ix86_expand_movstr (rtx dst, rtx src, rtx count_exp, rtx align_exp) src = replace_equiv_address_nv (src, srcreg); /* When optimizing for size emit simple rep ; movsb instruction for - counts not divisible by 4. */ - - if ((!optimize || optimize_size) && (count == 0 || (count & 0x03))) + counts not divisible by 4, except when (movsl;)*(movsw;)?(movsb;)? + sequence is shorter than mov{b,l} $count, %{ecx,cl}; rep; movsb. + Sice of (movsl;)*(movsw;)?(movsb;)? sequence is + count / 4 + (count & 3), the other sequence is either 4 or 7 bytes, + but we don't know whether upper 24 (resp. 56) bits of %ecx will be + known to be zero or not. The rep; movsb sequence causes higher + register pressure though, so take that into account. */ + + if ((!optimize || optimize_size) + && (count == 0 + || ((count & 0x03) + && (!optimize_size + || count > 5 * 4 + || (count & 3) + count / 4 > 6)))) { emit_insn (gen_cld ()); countreg = ix86_zero_extend_to_Pmode (count_exp); @@ -11155,19 +12632,36 @@ ix86_expand_movstr (rtx dst, rtx src, rtx count_exp, rtx align_exp) emit_insn (gen_cld ()); if (count & ~(size - 1)) { - countreg = copy_to_mode_reg (counter_mode, - GEN_INT ((count >> (size == 4 ? 2 : 3)) - & (TARGET_64BIT ? -1 : 0x3fffffff))); - countreg = ix86_zero_extend_to_Pmode (countreg); - - destexp = gen_rtx_ASHIFT (Pmode, countreg, - GEN_INT (size == 4 ? 2 : 3)); - srcexp = gen_rtx_PLUS (Pmode, destexp, srcreg); - destexp = gen_rtx_PLUS (Pmode, destexp, destreg); + if ((TARGET_SINGLE_STRINGOP || optimize_size) && count < 5 * 4) + { + enum machine_mode movs_mode = size == 4 ? SImode : DImode; - emit_insn (gen_rep_mov (destreg, dst, srcreg, src, - countreg, destexp, srcexp)); - offset = count & ~(size - 1); + while (offset < (count & ~(size - 1))) + { + srcmem = adjust_automodify_address_nv (src, movs_mode, + srcreg, offset); + dstmem = adjust_automodify_address_nv (dst, movs_mode, + destreg, offset); + emit_insn (gen_strmov (destreg, dstmem, srcreg, srcmem)); + offset += size; + } + } + else + { + countreg = GEN_INT ((count >> (size == 4 ? 2 : 3)) + & (TARGET_64BIT ? -1 : 0x3fffffff)); + countreg = copy_to_mode_reg (counter_mode, countreg); + countreg = ix86_zero_extend_to_Pmode (countreg); + + destexp = gen_rtx_ASHIFT (Pmode, countreg, + GEN_INT (size == 4 ? 2 : 3)); + srcexp = gen_rtx_PLUS (Pmode, destexp, srcreg); + destexp = gen_rtx_PLUS (Pmode, destexp, destreg); + + emit_insn (gen_rep_mov (destreg, dst, srcreg, src, + countreg, destexp, srcexp)); + offset = count & ~(size - 1); + } } if (size == 8 && (count & 0x04)) { @@ -11359,9 +12853,9 @@ ix86_expand_movstr (rtx dst, rtx src, rtx count_exp, rtx align_exp) } /* Expand string clear operation (bzero). Use i386 string operations when - profitable. expand_movstr contains similar code. */ + profitable. expand_movmem contains similar code. */ int -ix86_expand_clrstr (rtx dst, rtx count_exp, rtx align_exp) +ix86_expand_clrmem (rtx dst, rtx count_exp, rtx align_exp) { rtx destreg, zeroreg, countreg, destexp; enum machine_mode counter_mode; @@ -11388,8 +12882,9 @@ ix86_expand_clrstr (rtx dst, rtx count_exp, rtx align_exp) /* Figure out proper mode for counter. For 32bits it is always SImode, for 64bits use SImode when possible, otherwise DImode. Set count to number of bytes copied when known at compile time. */ - if (!TARGET_64BIT || GET_MODE (count_exp) == SImode - || x86_64_zero_extended_value (count_exp)) + if (!TARGET_64BIT + || GET_MODE (count_exp) == SImode + || x86_64_zext_immediate_operand (count_exp, VOIDmode)) counter_mode = SImode; else counter_mode = DImode; @@ -11398,13 +12893,20 @@ ix86_expand_clrstr (rtx dst, rtx count_exp, rtx align_exp) if (destreg != XEXP (dst, 0)) dst = replace_equiv_address_nv (dst, destreg); - emit_insn (gen_cld ()); /* When optimizing for size emit simple rep ; movsb instruction for - counts not divisible by 4. */ + counts not divisible by 4. The movl $N, %ecx; rep; stosb + sequence is 7 bytes long, so if optimizing for size and count is + small enough that some stosl, stosw and stosb instructions without + rep are shorter, fall back into the next if. */ - if ((!optimize || optimize_size) && (count == 0 || (count & 0x03))) + if ((!optimize || optimize_size) + && (count == 0 + || ((count & 0x03) + && (!optimize_size || (count & 0x03) + (count >> 2) > 7)))) { + emit_insn (gen_cld ()); + countreg = ix86_zero_extend_to_Pmode (count_exp); zeroreg = copy_to_mode_reg (QImode, const0_rtx); destexp = gen_rtx_PLUS (Pmode, destreg, countreg); @@ -11418,17 +12920,54 @@ ix86_expand_clrstr (rtx dst, rtx count_exp, rtx align_exp) int size = TARGET_64BIT && !optimize_size ? 8 : 4; unsigned HOST_WIDE_INT offset = 0; + emit_insn (gen_cld ()); + zeroreg = copy_to_mode_reg (size == 4 ? SImode : DImode, const0_rtx); if (count & ~(size - 1)) { - countreg = copy_to_mode_reg (counter_mode, - GEN_INT ((count >> (size == 4 ? 2 : 3)) - & (TARGET_64BIT ? -1 : 0x3fffffff))); - countreg = ix86_zero_extend_to_Pmode (countreg); - destexp = gen_rtx_ASHIFT (Pmode, countreg, GEN_INT (size == 4 ? 2 : 3)); - destexp = gen_rtx_PLUS (Pmode, destexp, destreg); - emit_insn (gen_rep_stos (destreg, countreg, dst, zeroreg, destexp)); - offset = count & ~(size - 1); + unsigned HOST_WIDE_INT repcount; + unsigned int max_nonrep; + + repcount = count >> (size == 4 ? 2 : 3); + if (!TARGET_64BIT) + repcount &= 0x3fffffff; + + /* movl $N, %ecx; rep; stosl is 7 bytes, while N x stosl is N bytes. + movl $N, %ecx; rep; stosq is 8 bytes, while N x stosq is 2xN + bytes. In both cases the latter seems to be faster for small + values of N. */ + max_nonrep = size == 4 ? 7 : 4; + if (!optimize_size) + switch (ix86_tune) + { + case PROCESSOR_PENTIUM4: + case PROCESSOR_NOCONA: + max_nonrep = 3; + break; + default: + break; + } + + if (repcount <= max_nonrep) + while (repcount-- > 0) + { + rtx mem = adjust_automodify_address_nv (dst, + GET_MODE (zeroreg), + destreg, offset); + emit_insn (gen_strset (destreg, mem, zeroreg)); + offset += size; + } + else + { + countreg = copy_to_mode_reg (counter_mode, GEN_INT (repcount)); + countreg = ix86_zero_extend_to_Pmode (countreg); + destexp = gen_rtx_ASHIFT (Pmode, countreg, + GEN_INT (size == 4 ? 2 : 3)); + destexp = gen_rtx_PLUS (Pmode, destexp, destreg); + emit_insn (gen_rep_stos (destreg, countreg, dst, zeroreg, + destexp)); + offset = count & ~(size - 1); + } } if (size == 8 && (count & 0x04)) { @@ -11704,9 +13243,9 @@ ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx) emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL, Pmode, 1, align_4_label); - emit_cmp_and_jump_insns (align_rtx, GEN_INT (2), EQ, NULL, + emit_cmp_and_jump_insns (align_rtx, const2_rtx, EQ, NULL, Pmode, 1, align_2_label); - emit_cmp_and_jump_insns (align_rtx, GEN_INT (2), GTU, NULL, + emit_cmp_and_jump_insns (align_rtx, const2_rtx, GTU, NULL, Pmode, 1, align_3_label); } else @@ -11714,7 +13253,7 @@ ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx) /* Since the alignment is 2, we have to check 2 or 0 bytes; check if is aligned to 4 - byte. */ - align_rtx = expand_binop (Pmode, and_optab, scratch1, GEN_INT (2), + align_rtx = expand_binop (Pmode, and_optab, scratch1, const2_rtx, NULL_RTX, 0, OPTAB_WIDEN); emit_cmp_and_jump_insns (align_rtx, const0_rtx, EQ, NULL, @@ -11800,7 +13339,7 @@ ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx) tmpreg))); /* Emit lea manually to avoid clobbering of flags. */ emit_insn (gen_rtx_SET (SImode, reg2, - gen_rtx_PLUS (Pmode, out, GEN_INT (2)))); + gen_rtx_PLUS (Pmode, out, const2_rtx))); tmp = gen_rtx_REG (CCNOmode, FLAGS_REG); tmp = gen_rtx_EQ (VOIDmode, tmp, const0_rtx); @@ -11827,9 +13366,9 @@ ix86_expand_strlensi_unroll_1 (rtx out, rtx src, rtx align_rtx) /* Not in the first two. Move two bytes forward. */ emit_insn (gen_lshrsi3 (tmpreg, tmpreg, GEN_INT (16))); if (TARGET_64BIT) - emit_insn (gen_adddi3 (out, out, GEN_INT (2))); + emit_insn (gen_adddi3 (out, out, const2_rtx)); else - emit_insn (gen_addsi3 (out, out, GEN_INT (2))); + emit_insn (gen_addsi3 (out, out, const2_rtx)); emit_label (end_2_label); @@ -11856,18 +13395,23 @@ ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1, if (pop == const0_rtx) pop = NULL; - if (TARGET_64BIT && pop) - abort (); + gcc_assert (!TARGET_64BIT || !pop); + if (TARGET_MACHO && !TARGET_64BIT) + { #if TARGET_MACHO - if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF) - fnaddr = machopic_indirect_call_target (fnaddr); -#else - /* Static functions and indirect calls don't need the pic register. */ - if (! TARGET_64BIT && flag_pic - && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF - && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0))) - use_reg (&use, pic_offset_table_rtx); + if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF) + fnaddr = machopic_indirect_call_target (fnaddr); +#endif + } + else + { + /* Static functions and indirect calls don't need the pic register. */ + if (! TARGET_64BIT && flag_pic + && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF + && ! SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0))) + use_reg (&use, pic_offset_table_rtx); + } if (TARGET_64BIT && INTVAL (callarg2) >= 0) { @@ -11875,7 +13419,6 @@ ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1, emit_move_insn (al, callarg2); use_reg (&use, al); } -#endif /* TARGET_MACHO */ if (! call_insn_operand (XEXP (fnaddr, 0), Pmode)) { @@ -11919,6 +13462,7 @@ ix86_init_machine_status (void) f = ggc_alloc_cleared (sizeof (struct machine_function)); f->use_fast_prologue_epilogue_nregs = -1; + f->tls_descriptor_call_expanded_p = 0; return f; } @@ -11930,12 +13474,11 @@ ix86_init_machine_status (void) which slot to use. */ rtx -assign_386_stack_local (enum machine_mode mode, int n) +assign_386_stack_local (enum machine_mode mode, enum ix86_stack_slot n) { struct stack_local_entry *s; - if (n < 0 || n >= MAX_386_STACK_LOCALS) - abort (); + gcc_assert (n < MAX_386_STACK_LOCALS); for (s = ix86_stack_locals; s; s = s->next) if (s->mode == mode && s->n == n) @@ -11962,23 +13505,43 @@ ix86_tls_get_addr (void) if (!ix86_tls_symbol) { ix86_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, - (TARGET_GNU_TLS && !TARGET_64BIT) + (TARGET_ANY_GNU_TLS + && !TARGET_64BIT) ? "___tls_get_addr" : "__tls_get_addr"); } return ix86_tls_symbol; } + +/* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */ + +static GTY(()) rtx ix86_tls_module_base_symbol; +rtx +ix86_tls_module_base (void) +{ + + if (!ix86_tls_module_base_symbol) + { + ix86_tls_module_base_symbol = gen_rtx_SYMBOL_REF (Pmode, + "_TLS_MODULE_BASE_"); + SYMBOL_REF_FLAGS (ix86_tls_module_base_symbol) + |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT; + } + + return ix86_tls_module_base_symbol; +} /* Calculate the length of the memory address in the instruction encoding. Does not include the one-byte modrm, opcode, or prefix. */ -static int +int memory_address_length (rtx addr) { struct ix86_address parts; rtx base, index, disp; int len; + int ok; if (GET_CODE (addr) == PRE_DEC || GET_CODE (addr) == POST_INC @@ -11986,8 +13549,13 @@ memory_address_length (rtx addr) || GET_CODE (addr) == POST_MODIFY) return 0; - if (! ix86_decompose_address (addr, &parts)) - abort (); + ok = ix86_decompose_address (addr, &parts); + gcc_assert (ok); + + if (parts.base && GET_CODE (parts.base) == SUBREG) + parts.base = SUBREG_REG (parts.base); + if (parts.index && GET_CODE (parts.index) == SUBREG) + parts.index = SUBREG_REG (parts.index); base = parts.base; index = parts.index; @@ -12019,9 +13587,7 @@ memory_address_length (rtx addr) /* Find the length of the displacement constant. */ if (disp) { - if (GET_CODE (disp) == CONST_INT - && CONST_OK_FOR_LETTER_P (INTVAL (disp), 'K') - && base) + if (base && satisfies_constraint_K (disp)) len = 1; else len = 4; @@ -12053,11 +13619,8 @@ ix86_attr_length_immediate_default (rtx insn, int shortform) for (i = recog_data.n_operands - 1; i >= 0; --i) if (CONSTANT_P (recog_data.operand[i])) { - if (len) - abort (); - if (shortform - && GET_CODE (recog_data.operand[i]) == CONST_INT - && CONST_OK_FOR_LETTER_P (INTVAL (recog_data.operand[i]), 'K')) + gcc_assert (!len); + if (shortform && satisfies_constraint_K (recog_data.operand[i])) len = 1; else { @@ -12092,18 +13655,11 @@ ix86_attr_length_address_default (rtx insn) if (get_attr_type (insn) == TYPE_LEA) { rtx set = PATTERN (insn); - if (GET_CODE (set) == SET) - ; - else if (GET_CODE (set) == PARALLEL - && GET_CODE (XVECEXP (set, 0, 0)) == SET) + + if (GET_CODE (set) == PARALLEL) set = XVECEXP (set, 0, 0); - else - { -#ifdef ENABLE_CHECKING - abort (); -#endif - return 0; - } + + gcc_assert (GET_CODE (set) == SET); return memory_address_length (SET_SRC (set)); } @@ -12133,6 +13689,9 @@ ix86_issue_rate (void) case PROCESSOR_PENTIUM4: case PROCESSOR_ATHLON: case PROCESSOR_K8: + case PROCESSOR_NOCONA: + case PROCESSOR_GENERIC32: + case PROCESSOR_GENERIC64: return 3; default: @@ -12144,7 +13703,7 @@ ix86_issue_rate (void) by DEP_INSN and nothing set by DEP_INSN. */ static int -ix86_flags_dependant (rtx insn, rtx dep_insn, enum attr_type insn_type) +ix86_flags_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type) { rtx set, set2; @@ -12189,7 +13748,7 @@ ix86_flags_dependant (rtx insn, rtx dep_insn, enum attr_type insn_type) address with operands set by DEP_INSN. */ static int -ix86_agi_dependant (rtx insn, rtx dep_insn, enum attr_type insn_type) +ix86_agi_dependent (rtx insn, rtx dep_insn, enum attr_type insn_type) { rtx addr; @@ -12197,13 +13756,12 @@ ix86_agi_dependant (rtx insn, rtx dep_insn, enum attr_type insn_type) && TARGET_PENTIUM) { addr = PATTERN (insn); - if (GET_CODE (addr) == SET) - ; - else if (GET_CODE (addr) == PARALLEL - && GET_CODE (XVECEXP (addr, 0, 0)) == SET) + + if (GET_CODE (addr) == PARALLEL) addr = XVECEXP (addr, 0, 0); - else - abort (); + + gcc_assert (GET_CODE (addr) == SET); + addr = SET_SRC (addr); } else @@ -12227,7 +13785,7 @@ static int ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) { enum attr_type insn_type, dep_insn_type; - enum attr_memory memory, dep_memory; + enum attr_memory memory; rtx set, set2; int dep_insn_code_number; @@ -12248,30 +13806,22 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) { case PROCESSOR_PENTIUM: /* Address Generation Interlock adds a cycle of latency. */ - if (ix86_agi_dependant (insn, dep_insn, insn_type)) + if (ix86_agi_dependent (insn, dep_insn, insn_type)) cost += 1; /* ??? Compares pair with jump/setcc. */ - if (ix86_flags_dependant (insn, dep_insn, insn_type)) + if (ix86_flags_dependent (insn, dep_insn, insn_type)) cost = 0; /* Floating point stores require value to be ready one cycle earlier. */ if (insn_type == TYPE_FMOV && get_attr_memory (insn) == MEMORY_STORE - && !ix86_agi_dependant (insn, dep_insn, insn_type)) + && !ix86_agi_dependent (insn, dep_insn, insn_type)) cost += 1; break; case PROCESSOR_PENTIUMPRO: memory = get_attr_memory (insn); - dep_memory = get_attr_memory (dep_insn); - - /* Since we can't represent delayed latencies of load+operation, - increase the cost here for non-imov insns. */ - if (dep_insn_type != TYPE_IMOV - && dep_insn_type != TYPE_FMOV - && (dep_memory == MEMORY_LOAD || dep_memory == MEMORY_BOTH)) - cost += 1; /* INT->FP conversion is expensive. */ if (get_attr_fp_int_src (dep_insn)) @@ -12289,7 +13839,7 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) in parallel with previous instruction in case previous instruction is not needed to compute the address. */ if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH) - && !ix86_agi_dependant (insn, dep_insn, insn_type)) + && !ix86_agi_dependent (insn, dep_insn, insn_type)) { /* Claim moves to take one cycle, as core can issue one load at time and the next load can start cycle later. */ @@ -12303,18 +13853,13 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) case PROCESSOR_K6: memory = get_attr_memory (insn); - dep_memory = get_attr_memory (dep_insn); + /* The esp dependency is resolved before the instruction is really finished. */ if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP) && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP)) return 1; - /* Since we can't represent delayed latencies of load+operation, - increase the cost here for non-imov insns. */ - if (dep_memory == MEMORY_LOAD || dep_memory == MEMORY_BOTH) - cost += (dep_insn_type != TYPE_IMOV) ? 2 : 1; - /* INT->FP conversion is expensive. */ if (get_attr_fp_int_src (dep_insn)) cost += 5; @@ -12323,7 +13868,7 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) in parallel with previous instruction in case previous instruction is not needed to compute the address. */ if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH) - && !ix86_agi_dependant (insn, dep_insn, insn_type)) + && !ix86_agi_dependent (insn, dep_insn, insn_type)) { /* Claim moves to take one cycle, as core can issue one load at time and the next load can start cycle later. */ @@ -12339,14 +13884,15 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) case PROCESSOR_ATHLON: case PROCESSOR_K8: + case PROCESSOR_GENERIC32: + case PROCESSOR_GENERIC64: memory = get_attr_memory (insn); - dep_memory = get_attr_memory (dep_insn); /* Show ability of reorder buffer to hide latency of load by executing in parallel with previous instruction in case previous instruction is not needed to compute the address. */ if ((memory == MEMORY_LOAD || memory == MEMORY_BOTH) - && !ix86_agi_dependant (insn, dep_insn, insn_type)) + && !ix86_agi_dependent (insn, dep_insn, insn_type)) { enum attr_unit unit = get_attr_unit (insn); int loadcost = 3; @@ -12374,248 +13920,6 @@ ix86_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost) return cost; } -static union -{ - struct ppro_sched_data - { - rtx decode[3]; - int issued_this_cycle; - } ppro; -} ix86_sched_data; - -static enum attr_ppro_uops -ix86_safe_ppro_uops (rtx insn) -{ - if (recog_memoized (insn) >= 0) - return get_attr_ppro_uops (insn); - else - return PPRO_UOPS_MANY; -} - -static void -ix86_dump_ppro_packet (FILE *dump) -{ - if (ix86_sched_data.ppro.decode[0]) - { - fprintf (dump, "PPRO packet: %d", - INSN_UID (ix86_sched_data.ppro.decode[0])); - if (ix86_sched_data.ppro.decode[1]) - fprintf (dump, " %d", INSN_UID (ix86_sched_data.ppro.decode[1])); - if (ix86_sched_data.ppro.decode[2]) - fprintf (dump, " %d", INSN_UID (ix86_sched_data.ppro.decode[2])); - fputc ('\n', dump); - } -} - -/* We're beginning a new block. Initialize data structures as necessary. */ - -static void -ix86_sched_init (FILE *dump ATTRIBUTE_UNUSED, - int sched_verbose ATTRIBUTE_UNUSED, - int veclen ATTRIBUTE_UNUSED) -{ - memset (&ix86_sched_data, 0, sizeof (ix86_sched_data)); -} - -/* Shift INSN to SLOT, and shift everything else down. */ - -static void -ix86_reorder_insn (rtx *insnp, rtx *slot) -{ - if (insnp != slot) - { - rtx insn = *insnp; - do - insnp[0] = insnp[1]; - while (++insnp != slot); - *insnp = insn; - } -} - -static void -ix86_sched_reorder_ppro (rtx *ready, rtx *e_ready) -{ - rtx decode[3]; - enum attr_ppro_uops cur_uops; - int issued_this_cycle; - rtx *insnp; - int i; - - /* At this point .ppro.decode contains the state of the three - decoders from last "cycle". That is, those insns that were - actually independent. But here we're scheduling for the - decoder, and we may find things that are decodable in the - same cycle. */ - - memcpy (decode, ix86_sched_data.ppro.decode, sizeof (decode)); - issued_this_cycle = 0; - - insnp = e_ready; - cur_uops = ix86_safe_ppro_uops (*insnp); - - /* If the decoders are empty, and we've a complex insn at the - head of the priority queue, let it issue without complaint. */ - if (decode[0] == NULL) - { - if (cur_uops == PPRO_UOPS_MANY) - { - decode[0] = *insnp; - goto ppro_done; - } - - /* Otherwise, search for a 2-4 uop unsn to issue. */ - while (cur_uops != PPRO_UOPS_FEW) - { - if (insnp == ready) - break; - cur_uops = ix86_safe_ppro_uops (*--insnp); - } - - /* If so, move it to the head of the line. */ - if (cur_uops == PPRO_UOPS_FEW) - ix86_reorder_insn (insnp, e_ready); - - /* Issue the head of the queue. */ - issued_this_cycle = 1; - decode[0] = *e_ready--; - } - - /* Look for simple insns to fill in the other two slots. */ - for (i = 1; i < 3; ++i) - if (decode[i] == NULL) - { - if (ready > e_ready) - goto ppro_done; - - insnp = e_ready; - cur_uops = ix86_safe_ppro_uops (*insnp); - while (cur_uops != PPRO_UOPS_ONE) - { - if (insnp == ready) - break; - cur_uops = ix86_safe_ppro_uops (*--insnp); - } - - /* Found one. Move it to the head of the queue and issue it. */ - if (cur_uops == PPRO_UOPS_ONE) - { - ix86_reorder_insn (insnp, e_ready); - decode[i] = *e_ready--; - issued_this_cycle++; - continue; - } - - /* ??? Didn't find one. Ideally, here we would do a lazy split - of 2-uop insns, issue one and queue the other. */ - } - - ppro_done: - if (issued_this_cycle == 0) - issued_this_cycle = 1; - ix86_sched_data.ppro.issued_this_cycle = issued_this_cycle; -} - -/* We are about to being issuing insns for this clock cycle. - Override the default sort algorithm to better slot instructions. */ -static int -ix86_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, - int sched_verbose ATTRIBUTE_UNUSED, rtx *ready, - int *n_readyp, int clock_var ATTRIBUTE_UNUSED) -{ - int n_ready = *n_readyp; - rtx *e_ready = ready + n_ready - 1; - - /* Make sure to go ahead and initialize key items in - ix86_sched_data if we are not going to bother trying to - reorder the ready queue. */ - if (n_ready < 2) - { - ix86_sched_data.ppro.issued_this_cycle = 1; - goto out; - } - - switch (ix86_tune) - { - default: - break; - - case PROCESSOR_PENTIUMPRO: - ix86_sched_reorder_ppro (ready, e_ready); - break; - } - -out: - return ix86_issue_rate (); -} - -/* We are about to issue INSN. Return the number of insns left on the - ready queue that can be issued this cycle. */ - -static int -ix86_variable_issue (FILE *dump, int sched_verbose, rtx insn, - int can_issue_more) -{ - int i; - switch (ix86_tune) - { - default: - return can_issue_more - 1; - - case PROCESSOR_PENTIUMPRO: - { - enum attr_ppro_uops uops = ix86_safe_ppro_uops (insn); - - if (uops == PPRO_UOPS_MANY) - { - if (sched_verbose) - ix86_dump_ppro_packet (dump); - ix86_sched_data.ppro.decode[0] = insn; - ix86_sched_data.ppro.decode[1] = NULL; - ix86_sched_data.ppro.decode[2] = NULL; - if (sched_verbose) - ix86_dump_ppro_packet (dump); - ix86_sched_data.ppro.decode[0] = NULL; - } - else if (uops == PPRO_UOPS_FEW) - { - if (sched_verbose) - ix86_dump_ppro_packet (dump); - ix86_sched_data.ppro.decode[0] = insn; - ix86_sched_data.ppro.decode[1] = NULL; - ix86_sched_data.ppro.decode[2] = NULL; - } - else - { - for (i = 0; i < 3; ++i) - if (ix86_sched_data.ppro.decode[i] == NULL) - { - ix86_sched_data.ppro.decode[i] = insn; - break; - } - if (i == 3) - abort (); - if (i == 2) - { - if (sched_verbose) - ix86_dump_ppro_packet (dump); - ix86_sched_data.ppro.decode[0] = NULL; - ix86_sched_data.ppro.decode[1] = NULL; - ix86_sched_data.ppro.decode[2] = NULL; - } - } - } - return --ix86_sched_data.ppro.issued_this_cycle; - } -} - -static int -ia32_use_dfa_pipeline_interface (void) -{ - if (TARGET_PENTIUM || TARGET_ATHLON_K8) - return 1; - return 0; -} - /* How many alternative schedules to try. This should be as wide as the scheduling freedom in the DFA, but no wider. Making this value too large results extra work for the scheduler. */ @@ -12625,8 +13929,13 @@ ia32_multipass_dfa_lookahead (void) { if (ix86_tune == PROCESSOR_PENTIUM) return 2; + + if (ix86_tune == PROCESSOR_PENTIUMPRO + || ix86_tune == PROCESSOR_K6) + return 1; + else - return 0; + return 0; } @@ -12647,7 +13956,7 @@ ix86_constant_alignment (tree exp, int align) return 128; } else if (!optimize_size && TREE_CODE (exp) == STRING_CST - && !TARGET_NO_ALIGN_LONG_STRINGS + && !TARGET_NO_ALIGN_LONG_STRINGS && TREE_STRING_LENGTH (exp) >= 31 && align < BITS_PER_WORD) return BITS_PER_WORD; @@ -12662,12 +13971,15 @@ ix86_constant_alignment (tree exp, int align) int ix86_data_alignment (tree type, int align) { + int max_align = optimize_size ? BITS_PER_WORD : 256; + if (AGGREGATE_TYPE_P (type) - && TYPE_SIZE (type) - && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST - && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= 256 - || TREE_INT_CST_HIGH (TYPE_SIZE (type))) && align < 256) - return 256; + && TYPE_SIZE (type) + && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST + && (TREE_INT_CST_LOW (TYPE_SIZE (type)) >= (unsigned) max_align + || TREE_INT_CST_HIGH (TYPE_SIZE (type))) + && align < max_align) + align = max_align; /* x86-64 ABI requires arrays greater than 16 bytes to be aligned to 16byte boundary. */ @@ -12798,7 +14110,7 @@ x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt) /* Try to load address using shorter movl instead of movabs. We may want to support movq for kernel mode, but kernel does not use trampolines at the moment. */ - if (x86_64_zero_extended_value (fnaddr)) + if (x86_64_zext_immediate_operand (fnaddr, VOIDmode)) { fnaddr = copy_to_mode_reg (DImode, fnaddr); emit_move_insn (gen_rtx_MEM (HImode, plus_constant (tramp, offset)), @@ -12827,24 +14139,459 @@ x86_initialize_trampoline (rtx tramp, rtx fnaddr, rtx cxt) emit_move_insn (gen_rtx_MEM (QImode, plus_constant (tramp, offset+2)), gen_int_mode (0xe3, QImode)); offset += 3; - if (offset > TRAMPOLINE_SIZE) - abort (); + gcc_assert (offset <= TRAMPOLINE_SIZE); } #ifdef ENABLE_EXECUTE_STACK - emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), + emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"), LCT_NORMAL, VOIDmode, 1, tramp, Pmode); #endif } -#define def_builtin(MASK, NAME, TYPE, CODE) \ -do { \ - if ((MASK) & target_flags \ - && (!((MASK) & MASK_64BIT) || TARGET_64BIT)) \ - builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \ - NULL, NULL_TREE); \ +/* Codes for all the SSE/MMX builtins. */ +enum ix86_builtins +{ + IX86_BUILTIN_ADDPS, + IX86_BUILTIN_ADDSS, + IX86_BUILTIN_DIVPS, + IX86_BUILTIN_DIVSS, + IX86_BUILTIN_MULPS, + IX86_BUILTIN_MULSS, + IX86_BUILTIN_SUBPS, + IX86_BUILTIN_SUBSS, + + IX86_BUILTIN_CMPEQPS, + IX86_BUILTIN_CMPLTPS, + IX86_BUILTIN_CMPLEPS, + IX86_BUILTIN_CMPGTPS, + IX86_BUILTIN_CMPGEPS, + IX86_BUILTIN_CMPNEQPS, + IX86_BUILTIN_CMPNLTPS, + IX86_BUILTIN_CMPNLEPS, + IX86_BUILTIN_CMPNGTPS, + IX86_BUILTIN_CMPNGEPS, + IX86_BUILTIN_CMPORDPS, + IX86_BUILTIN_CMPUNORDPS, + IX86_BUILTIN_CMPEQSS, + IX86_BUILTIN_CMPLTSS, + IX86_BUILTIN_CMPLESS, + IX86_BUILTIN_CMPNEQSS, + IX86_BUILTIN_CMPNLTSS, + IX86_BUILTIN_CMPNLESS, + IX86_BUILTIN_CMPNGTSS, + IX86_BUILTIN_CMPNGESS, + IX86_BUILTIN_CMPORDSS, + IX86_BUILTIN_CMPUNORDSS, + + IX86_BUILTIN_COMIEQSS, + IX86_BUILTIN_COMILTSS, + IX86_BUILTIN_COMILESS, + IX86_BUILTIN_COMIGTSS, + IX86_BUILTIN_COMIGESS, + IX86_BUILTIN_COMINEQSS, + IX86_BUILTIN_UCOMIEQSS, + IX86_BUILTIN_UCOMILTSS, + IX86_BUILTIN_UCOMILESS, + IX86_BUILTIN_UCOMIGTSS, + IX86_BUILTIN_UCOMIGESS, + IX86_BUILTIN_UCOMINEQSS, + + IX86_BUILTIN_CVTPI2PS, + IX86_BUILTIN_CVTPS2PI, + IX86_BUILTIN_CVTSI2SS, + IX86_BUILTIN_CVTSI642SS, + IX86_BUILTIN_CVTSS2SI, + IX86_BUILTIN_CVTSS2SI64, + IX86_BUILTIN_CVTTPS2PI, + IX86_BUILTIN_CVTTSS2SI, + IX86_BUILTIN_CVTTSS2SI64, + + IX86_BUILTIN_MAXPS, + IX86_BUILTIN_MAXSS, + IX86_BUILTIN_MINPS, + IX86_BUILTIN_MINSS, + + IX86_BUILTIN_LOADUPS, + IX86_BUILTIN_STOREUPS, + IX86_BUILTIN_MOVSS, + + IX86_BUILTIN_MOVHLPS, + IX86_BUILTIN_MOVLHPS, + IX86_BUILTIN_LOADHPS, + IX86_BUILTIN_LOADLPS, + IX86_BUILTIN_STOREHPS, + IX86_BUILTIN_STORELPS, + + IX86_BUILTIN_MASKMOVQ, + IX86_BUILTIN_MOVMSKPS, + IX86_BUILTIN_PMOVMSKB, + + IX86_BUILTIN_MOVNTPS, + IX86_BUILTIN_MOVNTQ, + + IX86_BUILTIN_LOADDQU, + IX86_BUILTIN_STOREDQU, + + IX86_BUILTIN_PACKSSWB, + IX86_BUILTIN_PACKSSDW, + IX86_BUILTIN_PACKUSWB, + + IX86_BUILTIN_PADDB, + IX86_BUILTIN_PADDW, + IX86_BUILTIN_PADDD, + IX86_BUILTIN_PADDQ, + IX86_BUILTIN_PADDSB, + IX86_BUILTIN_PADDSW, + IX86_BUILTIN_PADDUSB, + IX86_BUILTIN_PADDUSW, + IX86_BUILTIN_PSUBB, + IX86_BUILTIN_PSUBW, + IX86_BUILTIN_PSUBD, + IX86_BUILTIN_PSUBQ, + IX86_BUILTIN_PSUBSB, + IX86_BUILTIN_PSUBSW, + IX86_BUILTIN_PSUBUSB, + IX86_BUILTIN_PSUBUSW, + + IX86_BUILTIN_PAND, + IX86_BUILTIN_PANDN, + IX86_BUILTIN_POR, + IX86_BUILTIN_PXOR, + + IX86_BUILTIN_PAVGB, + IX86_BUILTIN_PAVGW, + + IX86_BUILTIN_PCMPEQB, + IX86_BUILTIN_PCMPEQW, + IX86_BUILTIN_PCMPEQD, + IX86_BUILTIN_PCMPGTB, + IX86_BUILTIN_PCMPGTW, + IX86_BUILTIN_PCMPGTD, + + IX86_BUILTIN_PMADDWD, + + IX86_BUILTIN_PMAXSW, + IX86_BUILTIN_PMAXUB, + IX86_BUILTIN_PMINSW, + IX86_BUILTIN_PMINUB, + + IX86_BUILTIN_PMULHUW, + IX86_BUILTIN_PMULHW, + IX86_BUILTIN_PMULLW, + + IX86_BUILTIN_PSADBW, + IX86_BUILTIN_PSHUFW, + + IX86_BUILTIN_PSLLW, + IX86_BUILTIN_PSLLD, + IX86_BUILTIN_PSLLQ, + IX86_BUILTIN_PSRAW, + IX86_BUILTIN_PSRAD, + IX86_BUILTIN_PSRLW, + IX86_BUILTIN_PSRLD, + IX86_BUILTIN_PSRLQ, + IX86_BUILTIN_PSLLWI, + IX86_BUILTIN_PSLLDI, + IX86_BUILTIN_PSLLQI, + IX86_BUILTIN_PSRAWI, + IX86_BUILTIN_PSRADI, + IX86_BUILTIN_PSRLWI, + IX86_BUILTIN_PSRLDI, + IX86_BUILTIN_PSRLQI, + + IX86_BUILTIN_PUNPCKHBW, + IX86_BUILTIN_PUNPCKHWD, + IX86_BUILTIN_PUNPCKHDQ, + IX86_BUILTIN_PUNPCKLBW, + IX86_BUILTIN_PUNPCKLWD, + IX86_BUILTIN_PUNPCKLDQ, + + IX86_BUILTIN_SHUFPS, + + IX86_BUILTIN_RCPPS, + IX86_BUILTIN_RCPSS, + IX86_BUILTIN_RSQRTPS, + IX86_BUILTIN_RSQRTSS, + IX86_BUILTIN_SQRTPS, + IX86_BUILTIN_SQRTSS, + + IX86_BUILTIN_UNPCKHPS, + IX86_BUILTIN_UNPCKLPS, + + IX86_BUILTIN_ANDPS, + IX86_BUILTIN_ANDNPS, + IX86_BUILTIN_ORPS, + IX86_BUILTIN_XORPS, + + IX86_BUILTIN_EMMS, + IX86_BUILTIN_LDMXCSR, + IX86_BUILTIN_STMXCSR, + IX86_BUILTIN_SFENCE, + + /* 3DNow! Original */ + IX86_BUILTIN_FEMMS, + IX86_BUILTIN_PAVGUSB, + IX86_BUILTIN_PF2ID, + IX86_BUILTIN_PFACC, + IX86_BUILTIN_PFADD, + IX86_BUILTIN_PFCMPEQ, + IX86_BUILTIN_PFCMPGE, + IX86_BUILTIN_PFCMPGT, + IX86_BUILTIN_PFMAX, + IX86_BUILTIN_PFMIN, + IX86_BUILTIN_PFMUL, + IX86_BUILTIN_PFRCP, + IX86_BUILTIN_PFRCPIT1, + IX86_BUILTIN_PFRCPIT2, + IX86_BUILTIN_PFRSQIT1, + IX86_BUILTIN_PFRSQRT, + IX86_BUILTIN_PFSUB, + IX86_BUILTIN_PFSUBR, + IX86_BUILTIN_PI2FD, + IX86_BUILTIN_PMULHRW, + + /* 3DNow! Athlon Extensions */ + IX86_BUILTIN_PF2IW, + IX86_BUILTIN_PFNACC, + IX86_BUILTIN_PFPNACC, + IX86_BUILTIN_PI2FW, + IX86_BUILTIN_PSWAPDSI, + IX86_BUILTIN_PSWAPDSF, + + /* SSE2 */ + IX86_BUILTIN_ADDPD, + IX86_BUILTIN_ADDSD, + IX86_BUILTIN_DIVPD, + IX86_BUILTIN_DIVSD, + IX86_BUILTIN_MULPD, + IX86_BUILTIN_MULSD, + IX86_BUILTIN_SUBPD, + IX86_BUILTIN_SUBSD, + + IX86_BUILTIN_CMPEQPD, + IX86_BUILTIN_CMPLTPD, + IX86_BUILTIN_CMPLEPD, + IX86_BUILTIN_CMPGTPD, + IX86_BUILTIN_CMPGEPD, + IX86_BUILTIN_CMPNEQPD, + IX86_BUILTIN_CMPNLTPD, + IX86_BUILTIN_CMPNLEPD, + IX86_BUILTIN_CMPNGTPD, + IX86_BUILTIN_CMPNGEPD, + IX86_BUILTIN_CMPORDPD, + IX86_BUILTIN_CMPUNORDPD, + IX86_BUILTIN_CMPNEPD, + IX86_BUILTIN_CMPEQSD, + IX86_BUILTIN_CMPLTSD, + IX86_BUILTIN_CMPLESD, + IX86_BUILTIN_CMPNEQSD, + IX86_BUILTIN_CMPNLTSD, + IX86_BUILTIN_CMPNLESD, + IX86_BUILTIN_CMPORDSD, + IX86_BUILTIN_CMPUNORDSD, + IX86_BUILTIN_CMPNESD, + + IX86_BUILTIN_COMIEQSD, + IX86_BUILTIN_COMILTSD, + IX86_BUILTIN_COMILESD, + IX86_BUILTIN_COMIGTSD, + IX86_BUILTIN_COMIGESD, + IX86_BUILTIN_COMINEQSD, + IX86_BUILTIN_UCOMIEQSD, + IX86_BUILTIN_UCOMILTSD, + IX86_BUILTIN_UCOMILESD, + IX86_BUILTIN_UCOMIGTSD, + IX86_BUILTIN_UCOMIGESD, + IX86_BUILTIN_UCOMINEQSD, + + IX86_BUILTIN_MAXPD, + IX86_BUILTIN_MAXSD, + IX86_BUILTIN_MINPD, + IX86_BUILTIN_MINSD, + + IX86_BUILTIN_ANDPD, + IX86_BUILTIN_ANDNPD, + IX86_BUILTIN_ORPD, + IX86_BUILTIN_XORPD, + + IX86_BUILTIN_SQRTPD, + IX86_BUILTIN_SQRTSD, + + IX86_BUILTIN_UNPCKHPD, + IX86_BUILTIN_UNPCKLPD, + + IX86_BUILTIN_SHUFPD, + + IX86_BUILTIN_LOADUPD, + IX86_BUILTIN_STOREUPD, + IX86_BUILTIN_MOVSD, + + IX86_BUILTIN_LOADHPD, + IX86_BUILTIN_LOADLPD, + + IX86_BUILTIN_CVTDQ2PD, + IX86_BUILTIN_CVTDQ2PS, + + IX86_BUILTIN_CVTPD2DQ, + IX86_BUILTIN_CVTPD2PI, + IX86_BUILTIN_CVTPD2PS, + IX86_BUILTIN_CVTTPD2DQ, + IX86_BUILTIN_CVTTPD2PI, + + IX86_BUILTIN_CVTPI2PD, + IX86_BUILTIN_CVTSI2SD, + IX86_BUILTIN_CVTSI642SD, + + IX86_BUILTIN_CVTSD2SI, + IX86_BUILTIN_CVTSD2SI64, + IX86_BUILTIN_CVTSD2SS, + IX86_BUILTIN_CVTSS2SD, + IX86_BUILTIN_CVTTSD2SI, + IX86_BUILTIN_CVTTSD2SI64, + + IX86_BUILTIN_CVTPS2DQ, + IX86_BUILTIN_CVTPS2PD, + IX86_BUILTIN_CVTTPS2DQ, + + IX86_BUILTIN_MOVNTI, + IX86_BUILTIN_MOVNTPD, + IX86_BUILTIN_MOVNTDQ, + + /* SSE2 MMX */ + IX86_BUILTIN_MASKMOVDQU, + IX86_BUILTIN_MOVMSKPD, + IX86_BUILTIN_PMOVMSKB128, + + IX86_BUILTIN_PACKSSWB128, + IX86_BUILTIN_PACKSSDW128, + IX86_BUILTIN_PACKUSWB128, + + IX86_BUILTIN_PADDB128, + IX86_BUILTIN_PADDW128, + IX86_BUILTIN_PADDD128, + IX86_BUILTIN_PADDQ128, + IX86_BUILTIN_PADDSB128, + IX86_BUILTIN_PADDSW128, + IX86_BUILTIN_PADDUSB128, + IX86_BUILTIN_PADDUSW128, + IX86_BUILTIN_PSUBB128, + IX86_BUILTIN_PSUBW128, + IX86_BUILTIN_PSUBD128, + IX86_BUILTIN_PSUBQ128, + IX86_BUILTIN_PSUBSB128, + IX86_BUILTIN_PSUBSW128, + IX86_BUILTIN_PSUBUSB128, + IX86_BUILTIN_PSUBUSW128, + + IX86_BUILTIN_PAND128, + IX86_BUILTIN_PANDN128, + IX86_BUILTIN_POR128, + IX86_BUILTIN_PXOR128, + + IX86_BUILTIN_PAVGB128, + IX86_BUILTIN_PAVGW128, + + IX86_BUILTIN_PCMPEQB128, + IX86_BUILTIN_PCMPEQW128, + IX86_BUILTIN_PCMPEQD128, + IX86_BUILTIN_PCMPGTB128, + IX86_BUILTIN_PCMPGTW128, + IX86_BUILTIN_PCMPGTD128, + + IX86_BUILTIN_PMADDWD128, + + IX86_BUILTIN_PMAXSW128, + IX86_BUILTIN_PMAXUB128, + IX86_BUILTIN_PMINSW128, + IX86_BUILTIN_PMINUB128, + + IX86_BUILTIN_PMULUDQ, + IX86_BUILTIN_PMULUDQ128, + IX86_BUILTIN_PMULHUW128, + IX86_BUILTIN_PMULHW128, + IX86_BUILTIN_PMULLW128, + + IX86_BUILTIN_PSADBW128, + IX86_BUILTIN_PSHUFHW, + IX86_BUILTIN_PSHUFLW, + IX86_BUILTIN_PSHUFD, + + IX86_BUILTIN_PSLLW128, + IX86_BUILTIN_PSLLD128, + IX86_BUILTIN_PSLLQ128, + IX86_BUILTIN_PSRAW128, + IX86_BUILTIN_PSRAD128, + IX86_BUILTIN_PSRLW128, + IX86_BUILTIN_PSRLD128, + IX86_BUILTIN_PSRLQ128, + IX86_BUILTIN_PSLLDQI128, + IX86_BUILTIN_PSLLWI128, + IX86_BUILTIN_PSLLDI128, + IX86_BUILTIN_PSLLQI128, + IX86_BUILTIN_PSRAWI128, + IX86_BUILTIN_PSRADI128, + IX86_BUILTIN_PSRLDQI128, + IX86_BUILTIN_PSRLWI128, + IX86_BUILTIN_PSRLDI128, + IX86_BUILTIN_PSRLQI128, + + IX86_BUILTIN_PUNPCKHBW128, + IX86_BUILTIN_PUNPCKHWD128, + IX86_BUILTIN_PUNPCKHDQ128, + IX86_BUILTIN_PUNPCKHQDQ128, + IX86_BUILTIN_PUNPCKLBW128, + IX86_BUILTIN_PUNPCKLWD128, + IX86_BUILTIN_PUNPCKLDQ128, + IX86_BUILTIN_PUNPCKLQDQ128, + + IX86_BUILTIN_CLFLUSH, + IX86_BUILTIN_MFENCE, + IX86_BUILTIN_LFENCE, + + /* Prescott New Instructions. */ + IX86_BUILTIN_ADDSUBPS, + IX86_BUILTIN_HADDPS, + IX86_BUILTIN_HSUBPS, + IX86_BUILTIN_MOVSHDUP, + IX86_BUILTIN_MOVSLDUP, + IX86_BUILTIN_ADDSUBPD, + IX86_BUILTIN_HADDPD, + IX86_BUILTIN_HSUBPD, + IX86_BUILTIN_LDDQU, + + IX86_BUILTIN_MONITOR, + IX86_BUILTIN_MWAIT, + + IX86_BUILTIN_VEC_INIT_V2SI, + IX86_BUILTIN_VEC_INIT_V4HI, + IX86_BUILTIN_VEC_INIT_V8QI, + IX86_BUILTIN_VEC_EXT_V2DF, + IX86_BUILTIN_VEC_EXT_V2DI, + IX86_BUILTIN_VEC_EXT_V4SF, + IX86_BUILTIN_VEC_EXT_V4SI, + IX86_BUILTIN_VEC_EXT_V8HI, + IX86_BUILTIN_VEC_EXT_V2SI, + IX86_BUILTIN_VEC_EXT_V4HI, + IX86_BUILTIN_VEC_SET_V8HI, + IX86_BUILTIN_VEC_SET_V4HI, + + IX86_BUILTIN_MAX +}; + +#define def_builtin(MASK, NAME, TYPE, CODE) \ +do { \ + if ((MASK) & target_flags \ + && (!((MASK) & MASK_64BIT) || TARGET_64BIT)) \ + lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \ + NULL, NULL_TREE); \ } while (0) +/* Bits for builtin_description.flag. */ + +/* Set when we don't support the comparison natively, and should + swap_comparison in order to support it. */ +#define BUILTIN_DESC_SWAP_OPERANDS 1 + struct builtin_description { const unsigned int mask; @@ -12890,41 +14637,49 @@ static const struct builtin_description bdesc_2arg[] = { MASK_SSE, CODE_FOR_subv4sf3, "__builtin_ia32_subps", IX86_BUILTIN_SUBPS, 0, 0 }, { MASK_SSE, CODE_FOR_mulv4sf3, "__builtin_ia32_mulps", IX86_BUILTIN_MULPS, 0, 0 }, { MASK_SSE, CODE_FOR_divv4sf3, "__builtin_ia32_divps", IX86_BUILTIN_DIVPS, 0, 0 }, - { MASK_SSE, CODE_FOR_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, 0, 0 }, - { MASK_SSE, CODE_FOR_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, 0, 0 }, - { MASK_SSE, CODE_FOR_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, 0, 0 }, - { MASK_SSE, CODE_FOR_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, 0, 0 }, - - { MASK_SSE, CODE_FOR_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, 0 }, - { MASK_SSE, CODE_FOR_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, 0 }, - { MASK_SSE, CODE_FOR_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, 0 }, - { MASK_SSE, CODE_FOR_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, 1 }, - { MASK_SSE, CODE_FOR_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, 1 }, - { MASK_SSE, CODE_FOR_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, 0 }, - { MASK_SSE, CODE_FOR_maskncmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, EQ, 0 }, - { MASK_SSE, CODE_FOR_maskncmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, LT, 0 }, - { MASK_SSE, CODE_FOR_maskncmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, LE, 0 }, - { MASK_SSE, CODE_FOR_maskncmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, LT, 1 }, - { MASK_SSE, CODE_FOR_maskncmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, LE, 1 }, - { MASK_SSE, CODE_FOR_maskncmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, UNORDERED, 0 }, - { MASK_SSE, CODE_FOR_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, 0 }, - { MASK_SSE, CODE_FOR_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, 0 }, - { MASK_SSE, CODE_FOR_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, 0 }, - { MASK_SSE, CODE_FOR_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, 0 }, - { MASK_SSE, CODE_FOR_vmmaskncmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, EQ, 0 }, - { MASK_SSE, CODE_FOR_vmmaskncmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, LT, 0 }, - { MASK_SSE, CODE_FOR_vmmaskncmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, LE, 0 }, - { MASK_SSE, CODE_FOR_vmmaskncmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, UNORDERED, 0 }, + { MASK_SSE, CODE_FOR_sse_vmaddv4sf3, "__builtin_ia32_addss", IX86_BUILTIN_ADDSS, 0, 0 }, + { MASK_SSE, CODE_FOR_sse_vmsubv4sf3, "__builtin_ia32_subss", IX86_BUILTIN_SUBSS, 0, 0 }, + { MASK_SSE, CODE_FOR_sse_vmmulv4sf3, "__builtin_ia32_mulss", IX86_BUILTIN_MULSS, 0, 0 }, + { MASK_SSE, CODE_FOR_sse_vmdivv4sf3, "__builtin_ia32_divss", IX86_BUILTIN_DIVSS, 0, 0 }, + + { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpeqps", IX86_BUILTIN_CMPEQPS, EQ, 0 }, + { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpltps", IX86_BUILTIN_CMPLTPS, LT, 0 }, + { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpleps", IX86_BUILTIN_CMPLEPS, LE, 0 }, + { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgtps", IX86_BUILTIN_CMPGTPS, LT, + BUILTIN_DESC_SWAP_OPERANDS }, + { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpgeps", IX86_BUILTIN_CMPGEPS, LE, + BUILTIN_DESC_SWAP_OPERANDS }, + { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpunordps", IX86_BUILTIN_CMPUNORDPS, UNORDERED, 0 }, + { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpneqps", IX86_BUILTIN_CMPNEQPS, NE, 0 }, + { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnltps", IX86_BUILTIN_CMPNLTPS, UNGE, 0 }, + { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpnleps", IX86_BUILTIN_CMPNLEPS, UNGT, 0 }, + { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngtps", IX86_BUILTIN_CMPNGTPS, UNGE, + BUILTIN_DESC_SWAP_OPERANDS }, + { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpngeps", IX86_BUILTIN_CMPNGEPS, UNGT, + BUILTIN_DESC_SWAP_OPERANDS }, + { MASK_SSE, CODE_FOR_sse_maskcmpv4sf3, "__builtin_ia32_cmpordps", IX86_BUILTIN_CMPORDPS, ORDERED, 0 }, + { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpeqss", IX86_BUILTIN_CMPEQSS, EQ, 0 }, + { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpltss", IX86_BUILTIN_CMPLTSS, LT, 0 }, + { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpless", IX86_BUILTIN_CMPLESS, LE, 0 }, + { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpunordss", IX86_BUILTIN_CMPUNORDSS, UNORDERED, 0 }, + { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpneqss", IX86_BUILTIN_CMPNEQSS, NE, 0 }, + { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnltss", IX86_BUILTIN_CMPNLTSS, UNGE, 0 }, + { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpnless", IX86_BUILTIN_CMPNLESS, UNGT, 0 }, + { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngtss", IX86_BUILTIN_CMPNGTSS, UNGE, + BUILTIN_DESC_SWAP_OPERANDS }, + { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpngess", IX86_BUILTIN_CMPNGESS, UNGT, + BUILTIN_DESC_SWAP_OPERANDS }, + { MASK_SSE, CODE_FOR_sse_vmmaskcmpv4sf3, "__builtin_ia32_cmpordss", IX86_BUILTIN_CMPORDSS, ORDERED, 0 }, { MASK_SSE, CODE_FOR_sminv4sf3, "__builtin_ia32_minps", IX86_BUILTIN_MINPS, 0, 0 }, { MASK_SSE, CODE_FOR_smaxv4sf3, "__builtin_ia32_maxps", IX86_BUILTIN_MAXPS, 0, 0 }, - { MASK_SSE, CODE_FOR_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, 0, 0 }, - { MASK_SSE, CODE_FOR_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, 0, 0 }, + { MASK_SSE, CODE_FOR_sse_vmsminv4sf3, "__builtin_ia32_minss", IX86_BUILTIN_MINSS, 0, 0 }, + { MASK_SSE, CODE_FOR_sse_vmsmaxv4sf3, "__builtin_ia32_maxss", IX86_BUILTIN_MAXSS, 0, 0 }, - { MASK_SSE, CODE_FOR_sse_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, 0, 0 }, + { MASK_SSE, CODE_FOR_andv4sf3, "__builtin_ia32_andps", IX86_BUILTIN_ANDPS, 0, 0 }, { MASK_SSE, CODE_FOR_sse_nandv4sf3, "__builtin_ia32_andnps", IX86_BUILTIN_ANDNPS, 0, 0 }, - { MASK_SSE, CODE_FOR_sse_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, 0, 0 }, - { MASK_SSE, CODE_FOR_sse_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, 0, 0 }, + { MASK_SSE, CODE_FOR_iorv4sf3, "__builtin_ia32_orps", IX86_BUILTIN_ORPS, 0, 0 }, + { MASK_SSE, CODE_FOR_xorv4sf3, "__builtin_ia32_xorps", IX86_BUILTIN_XORPS, 0, 0 }, { MASK_SSE, CODE_FOR_sse_movss, "__builtin_ia32_movss", IX86_BUILTIN_MOVSS, 0, 0 }, { MASK_SSE, CODE_FOR_sse_movhlps, "__builtin_ia32_movhlps", IX86_BUILTIN_MOVHLPS, 0, 0 }, @@ -12933,47 +14688,47 @@ static const struct builtin_description bdesc_2arg[] = { MASK_SSE, CODE_FOR_sse_unpcklps, "__builtin_ia32_unpcklps", IX86_BUILTIN_UNPCKLPS, 0, 0 }, /* MMX */ - { MASK_MMX, CODE_FOR_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, 0, 0 }, - { MASK_MMX, CODE_FOR_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, 0, 0 }, - { MASK_MMX, CODE_FOR_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, 0, 0 }, - { MASK_MMX, CODE_FOR_mmx_adddi3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, 0, 0 }, - { MASK_MMX, CODE_FOR_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, 0, 0 }, - { MASK_MMX, CODE_FOR_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, 0, 0 }, - { MASK_MMX, CODE_FOR_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, 0, 0 }, - { MASK_MMX, CODE_FOR_mmx_subdi3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, 0, 0 }, - - { MASK_MMX, CODE_FOR_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, 0, 0 }, - { MASK_MMX, CODE_FOR_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, 0, 0 }, - { MASK_MMX, CODE_FOR_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, 0, 0 }, - { MASK_MMX, CODE_FOR_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, 0, 0 }, - { MASK_MMX, CODE_FOR_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, 0, 0 }, - { MASK_MMX, CODE_FOR_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, 0, 0 }, - { MASK_MMX, CODE_FOR_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, 0, 0 }, - { MASK_MMX, CODE_FOR_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, 0, 0 }, - - { MASK_MMX, CODE_FOR_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, 0, 0 }, - { MASK_MMX, CODE_FOR_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, 0, 0 }, - { MASK_SSE | MASK_3DNOW_A, CODE_FOR_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, 0, 0 }, - - { MASK_MMX, CODE_FOR_mmx_anddi3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, 0, 0 }, - { MASK_MMX, CODE_FOR_mmx_nanddi3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, 0, 0 }, - { MASK_MMX, CODE_FOR_mmx_iordi3, "__builtin_ia32_por", IX86_BUILTIN_POR, 0, 0 }, - { MASK_MMX, CODE_FOR_mmx_xordi3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_addv4hi3, "__builtin_ia32_paddw", IX86_BUILTIN_PADDW, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_addv2si3, "__builtin_ia32_paddd", IX86_BUILTIN_PADDD, 0, 0 }, + { MASK_SSE2, CODE_FOR_mmx_adddi3, "__builtin_ia32_paddq", IX86_BUILTIN_PADDQ, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_subv8qi3, "__builtin_ia32_psubb", IX86_BUILTIN_PSUBB, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_subv4hi3, "__builtin_ia32_psubw", IX86_BUILTIN_PSUBW, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_subv2si3, "__builtin_ia32_psubd", IX86_BUILTIN_PSUBD, 0, 0 }, + { MASK_SSE2, CODE_FOR_mmx_subdi3, "__builtin_ia32_psubq", IX86_BUILTIN_PSUBQ, 0, 0 }, + + { MASK_MMX, CODE_FOR_mmx_ssaddv8qi3, "__builtin_ia32_paddsb", IX86_BUILTIN_PADDSB, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_ssaddv4hi3, "__builtin_ia32_paddsw", IX86_BUILTIN_PADDSW, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_sssubv8qi3, "__builtin_ia32_psubsb", IX86_BUILTIN_PSUBSB, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_sssubv4hi3, "__builtin_ia32_psubsw", IX86_BUILTIN_PSUBSW, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_usaddv8qi3, "__builtin_ia32_paddusb", IX86_BUILTIN_PADDUSB, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_usaddv4hi3, "__builtin_ia32_paddusw", IX86_BUILTIN_PADDUSW, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_ussubv8qi3, "__builtin_ia32_psubusb", IX86_BUILTIN_PSUBUSB, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_ussubv4hi3, "__builtin_ia32_psubusw", IX86_BUILTIN_PSUBUSW, 0, 0 }, + + { MASK_MMX, CODE_FOR_mmx_mulv4hi3, "__builtin_ia32_pmullw", IX86_BUILTIN_PMULLW, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_smulv4hi3_highpart, "__builtin_ia32_pmulhw", IX86_BUILTIN_PMULHW, 0, 0 }, + { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_umulv4hi3_highpart, "__builtin_ia32_pmulhuw", IX86_BUILTIN_PMULHUW, 0, 0 }, + + { MASK_MMX, CODE_FOR_mmx_andv2si3, "__builtin_ia32_pand", IX86_BUILTIN_PAND, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_nandv2si3, "__builtin_ia32_pandn", IX86_BUILTIN_PANDN, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_iorv2si3, "__builtin_ia32_por", IX86_BUILTIN_POR, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_xorv2si3, "__builtin_ia32_pxor", IX86_BUILTIN_PXOR, 0, 0 }, { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uavgv8qi3, "__builtin_ia32_pavgb", IX86_BUILTIN_PAVGB, 0, 0 }, { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uavgv4hi3, "__builtin_ia32_pavgw", IX86_BUILTIN_PAVGW, 0, 0 }, - { MASK_MMX, CODE_FOR_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, 0, 0 }, - { MASK_MMX, CODE_FOR_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, 0, 0 }, - { MASK_MMX, CODE_FOR_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, 0, 0 }, - { MASK_MMX, CODE_FOR_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, 0, 0 }, - { MASK_MMX, CODE_FOR_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, 0, 0 }, - { MASK_MMX, CODE_FOR_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_eqv8qi3, "__builtin_ia32_pcmpeqb", IX86_BUILTIN_PCMPEQB, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_eqv4hi3, "__builtin_ia32_pcmpeqw", IX86_BUILTIN_PCMPEQW, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_eqv2si3, "__builtin_ia32_pcmpeqd", IX86_BUILTIN_PCMPEQD, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_gtv8qi3, "__builtin_ia32_pcmpgtb", IX86_BUILTIN_PCMPGTB, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_gtv4hi3, "__builtin_ia32_pcmpgtw", IX86_BUILTIN_PCMPGTW, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_gtv2si3, "__builtin_ia32_pcmpgtd", IX86_BUILTIN_PCMPGTD, 0, 0 }, - { MASK_SSE | MASK_3DNOW_A, CODE_FOR_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, 0, 0 }, - { MASK_SSE | MASK_3DNOW_A, CODE_FOR_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, 0, 0 }, - { MASK_SSE | MASK_3DNOW_A, CODE_FOR_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, 0, 0 }, - { MASK_SSE | MASK_3DNOW_A, CODE_FOR_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, 0, 0 }, + { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_umaxv8qi3, "__builtin_ia32_pmaxub", IX86_BUILTIN_PMAXUB, 0, 0 }, + { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_smaxv4hi3, "__builtin_ia32_pmaxsw", IX86_BUILTIN_PMAXSW, 0, 0 }, + { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_uminv8qi3, "__builtin_ia32_pminub", IX86_BUILTIN_PMINUB, 0, 0 }, + { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_sminv4hi3, "__builtin_ia32_pminsw", IX86_BUILTIN_PMINSW, 0, 0 }, { MASK_MMX, CODE_FOR_mmx_punpckhbw, "__builtin_ia32_punpckhbw", IX86_BUILTIN_PUNPCKHBW, 0, 0 }, { MASK_MMX, CODE_FOR_mmx_punpckhwd, "__builtin_ia32_punpckhwd", IX86_BUILTIN_PUNPCKHWD, 0, 0 }, @@ -12987,28 +14742,28 @@ static const struct builtin_description bdesc_2arg[] = { MASK_MMX, CODE_FOR_mmx_packssdw, 0, IX86_BUILTIN_PACKSSDW, 0, 0 }, { MASK_MMX, CODE_FOR_mmx_packuswb, 0, IX86_BUILTIN_PACKUSWB, 0, 0 }, - { MASK_SSE, CODE_FOR_cvtpi2ps, 0, IX86_BUILTIN_CVTPI2PS, 0, 0 }, - { MASK_SSE, CODE_FOR_cvtsi2ss, 0, IX86_BUILTIN_CVTSI2SS, 0, 0 }, - { MASK_SSE | MASK_64BIT, CODE_FOR_cvtsi2ssq, 0, IX86_BUILTIN_CVTSI642SS, 0, 0 }, + { MASK_SSE, CODE_FOR_sse_cvtpi2ps, 0, IX86_BUILTIN_CVTPI2PS, 0, 0 }, + { MASK_SSE, CODE_FOR_sse_cvtsi2ss, 0, IX86_BUILTIN_CVTSI2SS, 0, 0 }, + { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvtsi2ssq, 0, IX86_BUILTIN_CVTSI642SS, 0, 0 }, - { MASK_MMX, CODE_FOR_ashlv4hi3, 0, IX86_BUILTIN_PSLLW, 0, 0 }, - { MASK_MMX, CODE_FOR_ashlv4hi3, 0, IX86_BUILTIN_PSLLWI, 0, 0 }, - { MASK_MMX, CODE_FOR_ashlv2si3, 0, IX86_BUILTIN_PSLLD, 0, 0 }, - { MASK_MMX, CODE_FOR_ashlv2si3, 0, IX86_BUILTIN_PSLLDI, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_ashlv4hi3, 0, IX86_BUILTIN_PSLLW, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_ashlv4hi3, 0, IX86_BUILTIN_PSLLWI, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_ashlv2si3, 0, IX86_BUILTIN_PSLLD, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_ashlv2si3, 0, IX86_BUILTIN_PSLLDI, 0, 0 }, { MASK_MMX, CODE_FOR_mmx_ashldi3, 0, IX86_BUILTIN_PSLLQ, 0, 0 }, { MASK_MMX, CODE_FOR_mmx_ashldi3, 0, IX86_BUILTIN_PSLLQI, 0, 0 }, - { MASK_MMX, CODE_FOR_lshrv4hi3, 0, IX86_BUILTIN_PSRLW, 0, 0 }, - { MASK_MMX, CODE_FOR_lshrv4hi3, 0, IX86_BUILTIN_PSRLWI, 0, 0 }, - { MASK_MMX, CODE_FOR_lshrv2si3, 0, IX86_BUILTIN_PSRLD, 0, 0 }, - { MASK_MMX, CODE_FOR_lshrv2si3, 0, IX86_BUILTIN_PSRLDI, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_lshrv4hi3, 0, IX86_BUILTIN_PSRLW, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_lshrv4hi3, 0, IX86_BUILTIN_PSRLWI, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_lshrv2si3, 0, IX86_BUILTIN_PSRLD, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_lshrv2si3, 0, IX86_BUILTIN_PSRLDI, 0, 0 }, { MASK_MMX, CODE_FOR_mmx_lshrdi3, 0, IX86_BUILTIN_PSRLQ, 0, 0 }, { MASK_MMX, CODE_FOR_mmx_lshrdi3, 0, IX86_BUILTIN_PSRLQI, 0, 0 }, - { MASK_MMX, CODE_FOR_ashrv4hi3, 0, IX86_BUILTIN_PSRAW, 0, 0 }, - { MASK_MMX, CODE_FOR_ashrv4hi3, 0, IX86_BUILTIN_PSRAWI, 0, 0 }, - { MASK_MMX, CODE_FOR_ashrv2si3, 0, IX86_BUILTIN_PSRAD, 0, 0 }, - { MASK_MMX, CODE_FOR_ashrv2si3, 0, IX86_BUILTIN_PSRADI, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_ashrv4hi3, 0, IX86_BUILTIN_PSRAW, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_ashrv4hi3, 0, IX86_BUILTIN_PSRAWI, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_ashrv2si3, 0, IX86_BUILTIN_PSRAD, 0, 0 }, + { MASK_MMX, CODE_FOR_mmx_ashrv2si3, 0, IX86_BUILTIN_PSRADI, 0, 0 }, { MASK_SSE | MASK_3DNOW_A, CODE_FOR_mmx_psadbw, 0, IX86_BUILTIN_PSADBW, 0, 0 }, { MASK_MMX, CODE_FOR_mmx_pmaddwd, 0, IX86_BUILTIN_PMADDWD, 0, 0 }, @@ -13018,41 +14773,45 @@ static const struct builtin_description bdesc_2arg[] = { MASK_SSE2, CODE_FOR_subv2df3, "__builtin_ia32_subpd", IX86_BUILTIN_SUBPD, 0, 0 }, { MASK_SSE2, CODE_FOR_mulv2df3, "__builtin_ia32_mulpd", IX86_BUILTIN_MULPD, 0, 0 }, { MASK_SSE2, CODE_FOR_divv2df3, "__builtin_ia32_divpd", IX86_BUILTIN_DIVPD, 0, 0 }, - { MASK_SSE2, CODE_FOR_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, 0, 0 }, - { MASK_SSE2, CODE_FOR_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, 0, 0 }, - { MASK_SSE2, CODE_FOR_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, 0, 0 }, - { MASK_SSE2, CODE_FOR_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, 0, 0 }, - - { MASK_SSE2, CODE_FOR_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, 0 }, - { MASK_SSE2, CODE_FOR_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, 0 }, - { MASK_SSE2, CODE_FOR_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, 0 }, - { MASK_SSE2, CODE_FOR_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, 1 }, - { MASK_SSE2, CODE_FOR_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, 1 }, - { MASK_SSE2, CODE_FOR_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, 0 }, - { MASK_SSE2, CODE_FOR_maskncmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, EQ, 0 }, - { MASK_SSE2, CODE_FOR_maskncmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, LT, 0 }, - { MASK_SSE2, CODE_FOR_maskncmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, LE, 0 }, - { MASK_SSE2, CODE_FOR_maskncmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, LT, 1 }, - { MASK_SSE2, CODE_FOR_maskncmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, LE, 1 }, - { MASK_SSE2, CODE_FOR_maskncmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, UNORDERED, 0 }, - { MASK_SSE2, CODE_FOR_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, 0 }, - { MASK_SSE2, CODE_FOR_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, 0 }, - { MASK_SSE2, CODE_FOR_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, 0 }, - { MASK_SSE2, CODE_FOR_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, 0 }, - { MASK_SSE2, CODE_FOR_vmmaskncmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, EQ, 0 }, - { MASK_SSE2, CODE_FOR_vmmaskncmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, LT, 0 }, - { MASK_SSE2, CODE_FOR_vmmaskncmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, LE, 0 }, - { MASK_SSE2, CODE_FOR_vmmaskncmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, UNORDERED, 0 }, + { MASK_SSE2, CODE_FOR_sse2_vmaddv2df3, "__builtin_ia32_addsd", IX86_BUILTIN_ADDSD, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_vmsubv2df3, "__builtin_ia32_subsd", IX86_BUILTIN_SUBSD, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_vmmulv2df3, "__builtin_ia32_mulsd", IX86_BUILTIN_MULSD, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_vmdivv2df3, "__builtin_ia32_divsd", IX86_BUILTIN_DIVSD, 0, 0 }, + + { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpeqpd", IX86_BUILTIN_CMPEQPD, EQ, 0 }, + { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpltpd", IX86_BUILTIN_CMPLTPD, LT, 0 }, + { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmplepd", IX86_BUILTIN_CMPLEPD, LE, 0 }, + { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgtpd", IX86_BUILTIN_CMPGTPD, LT, + BUILTIN_DESC_SWAP_OPERANDS }, + { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpgepd", IX86_BUILTIN_CMPGEPD, LE, + BUILTIN_DESC_SWAP_OPERANDS }, + { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpunordpd", IX86_BUILTIN_CMPUNORDPD, UNORDERED, 0 }, + { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpneqpd", IX86_BUILTIN_CMPNEQPD, NE, 0 }, + { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnltpd", IX86_BUILTIN_CMPNLTPD, UNGE, 0 }, + { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpnlepd", IX86_BUILTIN_CMPNLEPD, UNGT, 0 }, + { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngtpd", IX86_BUILTIN_CMPNGTPD, UNGE, + BUILTIN_DESC_SWAP_OPERANDS }, + { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpngepd", IX86_BUILTIN_CMPNGEPD, UNGT, + BUILTIN_DESC_SWAP_OPERANDS }, + { MASK_SSE2, CODE_FOR_sse2_maskcmpv2df3, "__builtin_ia32_cmpordpd", IX86_BUILTIN_CMPORDPD, ORDERED, 0 }, + { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpeqsd", IX86_BUILTIN_CMPEQSD, EQ, 0 }, + { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpltsd", IX86_BUILTIN_CMPLTSD, LT, 0 }, + { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmplesd", IX86_BUILTIN_CMPLESD, LE, 0 }, + { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpunordsd", IX86_BUILTIN_CMPUNORDSD, UNORDERED, 0 }, + { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpneqsd", IX86_BUILTIN_CMPNEQSD, NE, 0 }, + { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnltsd", IX86_BUILTIN_CMPNLTSD, UNGE, 0 }, + { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpnlesd", IX86_BUILTIN_CMPNLESD, UNGT, 0 }, + { MASK_SSE2, CODE_FOR_sse2_vmmaskcmpv2df3, "__builtin_ia32_cmpordsd", IX86_BUILTIN_CMPORDSD, ORDERED, 0 }, { MASK_SSE2, CODE_FOR_sminv2df3, "__builtin_ia32_minpd", IX86_BUILTIN_MINPD, 0, 0 }, { MASK_SSE2, CODE_FOR_smaxv2df3, "__builtin_ia32_maxpd", IX86_BUILTIN_MAXPD, 0, 0 }, - { MASK_SSE2, CODE_FOR_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, 0, 0 }, - { MASK_SSE2, CODE_FOR_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_vmsminv2df3, "__builtin_ia32_minsd", IX86_BUILTIN_MINSD, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_vmsmaxv2df3, "__builtin_ia32_maxsd", IX86_BUILTIN_MAXSD, 0, 0 }, - { MASK_SSE2, CODE_FOR_sse2_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, 0, 0 }, + { MASK_SSE2, CODE_FOR_andv2df3, "__builtin_ia32_andpd", IX86_BUILTIN_ANDPD, 0, 0 }, { MASK_SSE2, CODE_FOR_sse2_nandv2df3, "__builtin_ia32_andnpd", IX86_BUILTIN_ANDNPD, 0, 0 }, - { MASK_SSE2, CODE_FOR_sse2_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, 0, 0 }, - { MASK_SSE2, CODE_FOR_sse2_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, 0, 0 }, + { MASK_SSE2, CODE_FOR_iorv2df3, "__builtin_ia32_orpd", IX86_BUILTIN_ORPD, 0, 0 }, + { MASK_SSE2, CODE_FOR_xorv2df3, "__builtin_ia32_xorpd", IX86_BUILTIN_XORPD, 0, 0 }, { MASK_SSE2, CODE_FOR_sse2_movsd, "__builtin_ia32_movsd", IX86_BUILTIN_MOVSD, 0, 0 }, { MASK_SSE2, CODE_FOR_sse2_unpckhpd, "__builtin_ia32_unpckhpd", IX86_BUILTIN_UNPCKHPD, 0, 0 }, @@ -13068,34 +14827,32 @@ static const struct builtin_description bdesc_2arg[] = { MASK_SSE2, CODE_FOR_subv4si3, "__builtin_ia32_psubd128", IX86_BUILTIN_PSUBD128, 0, 0 }, { MASK_SSE2, CODE_FOR_subv2di3, "__builtin_ia32_psubq128", IX86_BUILTIN_PSUBQ128, 0, 0 }, - { MASK_MMX, CODE_FOR_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, 0, 0 }, - { MASK_MMX, CODE_FOR_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, 0, 0 }, - { MASK_MMX, CODE_FOR_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, 0, 0 }, - { MASK_MMX, CODE_FOR_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, 0, 0 }, - { MASK_MMX, CODE_FOR_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, 0, 0 }, - { MASK_MMX, CODE_FOR_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, 0, 0 }, - { MASK_MMX, CODE_FOR_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, 0, 0 }, - { MASK_MMX, CODE_FOR_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, 0, 0 }, + { MASK_MMX, CODE_FOR_sse2_ssaddv16qi3, "__builtin_ia32_paddsb128", IX86_BUILTIN_PADDSB128, 0, 0 }, + { MASK_MMX, CODE_FOR_sse2_ssaddv8hi3, "__builtin_ia32_paddsw128", IX86_BUILTIN_PADDSW128, 0, 0 }, + { MASK_MMX, CODE_FOR_sse2_sssubv16qi3, "__builtin_ia32_psubsb128", IX86_BUILTIN_PSUBSB128, 0, 0 }, + { MASK_MMX, CODE_FOR_sse2_sssubv8hi3, "__builtin_ia32_psubsw128", IX86_BUILTIN_PSUBSW128, 0, 0 }, + { MASK_MMX, CODE_FOR_sse2_usaddv16qi3, "__builtin_ia32_paddusb128", IX86_BUILTIN_PADDUSB128, 0, 0 }, + { MASK_MMX, CODE_FOR_sse2_usaddv8hi3, "__builtin_ia32_paddusw128", IX86_BUILTIN_PADDUSW128, 0, 0 }, + { MASK_MMX, CODE_FOR_sse2_ussubv16qi3, "__builtin_ia32_psubusb128", IX86_BUILTIN_PSUBUSB128, 0, 0 }, + { MASK_MMX, CODE_FOR_sse2_ussubv8hi3, "__builtin_ia32_psubusw128", IX86_BUILTIN_PSUBUSW128, 0, 0 }, { MASK_SSE2, CODE_FOR_mulv8hi3, "__builtin_ia32_pmullw128", IX86_BUILTIN_PMULLW128, 0, 0 }, - { MASK_SSE2, CODE_FOR_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, 0, 0 }, - { MASK_SSE2, CODE_FOR_sse2_umulsidi3, "__builtin_ia32_pmuludq", IX86_BUILTIN_PMULUDQ, 0, 0 }, - { MASK_SSE2, CODE_FOR_sse2_umulv2siv2di3, "__builtin_ia32_pmuludq128", IX86_BUILTIN_PMULUDQ128, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_smulv8hi3_highpart, "__builtin_ia32_pmulhw128", IX86_BUILTIN_PMULHW128, 0, 0 }, - { MASK_SSE2, CODE_FOR_sse2_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, 0, 0 }, + { MASK_SSE2, CODE_FOR_andv2di3, "__builtin_ia32_pand128", IX86_BUILTIN_PAND128, 0, 0 }, { MASK_SSE2, CODE_FOR_sse2_nandv2di3, "__builtin_ia32_pandn128", IX86_BUILTIN_PANDN128, 0, 0 }, - { MASK_SSE2, CODE_FOR_sse2_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, 0, 0 }, - { MASK_SSE2, CODE_FOR_sse2_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, 0, 0 }, + { MASK_SSE2, CODE_FOR_iorv2di3, "__builtin_ia32_por128", IX86_BUILTIN_POR128, 0, 0 }, + { MASK_SSE2, CODE_FOR_xorv2di3, "__builtin_ia32_pxor128", IX86_BUILTIN_PXOR128, 0, 0 }, { MASK_SSE2, CODE_FOR_sse2_uavgv16qi3, "__builtin_ia32_pavgb128", IX86_BUILTIN_PAVGB128, 0, 0 }, { MASK_SSE2, CODE_FOR_sse2_uavgv8hi3, "__builtin_ia32_pavgw128", IX86_BUILTIN_PAVGW128, 0, 0 }, - { MASK_SSE2, CODE_FOR_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, 0, 0 }, - { MASK_SSE2, CODE_FOR_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, 0, 0 }, - { MASK_SSE2, CODE_FOR_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, 0, 0 }, - { MASK_SSE2, CODE_FOR_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, 0, 0 }, - { MASK_SSE2, CODE_FOR_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, 0, 0 }, - { MASK_SSE2, CODE_FOR_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_eqv16qi3, "__builtin_ia32_pcmpeqb128", IX86_BUILTIN_PCMPEQB128, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_eqv8hi3, "__builtin_ia32_pcmpeqw128", IX86_BUILTIN_PCMPEQW128, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_eqv4si3, "__builtin_ia32_pcmpeqd128", IX86_BUILTIN_PCMPEQD128, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_gtv16qi3, "__builtin_ia32_pcmpgtb128", IX86_BUILTIN_PCMPGTB128, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_gtv8hi3, "__builtin_ia32_pcmpgtw128", IX86_BUILTIN_PCMPGTW128, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_gtv4si3, "__builtin_ia32_pcmpgtd128", IX86_BUILTIN_PCMPGTD128, 0, 0 }, { MASK_SSE2, CODE_FOR_umaxv16qi3, "__builtin_ia32_pmaxub128", IX86_BUILTIN_PMAXUB128, 0, 0 }, { MASK_SSE2, CODE_FOR_smaxv8hi3, "__builtin_ia32_pmaxsw128", IX86_BUILTIN_PMAXSW128, 0, 0 }, @@ -13115,42 +14872,37 @@ static const struct builtin_description bdesc_2arg[] = { MASK_SSE2, CODE_FOR_sse2_packssdw, "__builtin_ia32_packssdw128", IX86_BUILTIN_PACKSSDW128, 0, 0 }, { MASK_SSE2, CODE_FOR_sse2_packuswb, "__builtin_ia32_packuswb128", IX86_BUILTIN_PACKUSWB128, 0, 0 }, - { MASK_SSE2, CODE_FOR_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_umulv8hi3_highpart, "__builtin_ia32_pmulhuw128", IX86_BUILTIN_PMULHUW128, 0, 0 }, { MASK_SSE2, CODE_FOR_sse2_psadbw, 0, IX86_BUILTIN_PSADBW128, 0, 0 }, - { MASK_SSE2, CODE_FOR_ashlv8hi3_ti, 0, IX86_BUILTIN_PSLLW128, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_umulsidi3, 0, IX86_BUILTIN_PMULUDQ, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_umulv2siv2di3, 0, IX86_BUILTIN_PMULUDQ128, 0, 0 }, + { MASK_SSE2, CODE_FOR_ashlv8hi3, 0, IX86_BUILTIN_PSLLWI128, 0, 0 }, - { MASK_SSE2, CODE_FOR_ashlv4si3_ti, 0, IX86_BUILTIN_PSLLD128, 0, 0 }, { MASK_SSE2, CODE_FOR_ashlv4si3, 0, IX86_BUILTIN_PSLLDI128, 0, 0 }, - { MASK_SSE2, CODE_FOR_ashlv2di3_ti, 0, IX86_BUILTIN_PSLLQ128, 0, 0 }, { MASK_SSE2, CODE_FOR_ashlv2di3, 0, IX86_BUILTIN_PSLLQI128, 0, 0 }, - { MASK_SSE2, CODE_FOR_lshrv8hi3_ti, 0, IX86_BUILTIN_PSRLW128, 0, 0 }, { MASK_SSE2, CODE_FOR_lshrv8hi3, 0, IX86_BUILTIN_PSRLWI128, 0, 0 }, - { MASK_SSE2, CODE_FOR_lshrv4si3_ti, 0, IX86_BUILTIN_PSRLD128, 0, 0 }, { MASK_SSE2, CODE_FOR_lshrv4si3, 0, IX86_BUILTIN_PSRLDI128, 0, 0 }, - { MASK_SSE2, CODE_FOR_lshrv2di3_ti, 0, IX86_BUILTIN_PSRLQ128, 0, 0 }, { MASK_SSE2, CODE_FOR_lshrv2di3, 0, IX86_BUILTIN_PSRLQI128, 0, 0 }, - { MASK_SSE2, CODE_FOR_ashrv8hi3_ti, 0, IX86_BUILTIN_PSRAW128, 0, 0 }, { MASK_SSE2, CODE_FOR_ashrv8hi3, 0, IX86_BUILTIN_PSRAWI128, 0, 0 }, - { MASK_SSE2, CODE_FOR_ashrv4si3_ti, 0, IX86_BUILTIN_PSRAD128, 0, 0 }, { MASK_SSE2, CODE_FOR_ashrv4si3, 0, IX86_BUILTIN_PSRADI128, 0, 0 }, { MASK_SSE2, CODE_FOR_sse2_pmaddwd, 0, IX86_BUILTIN_PMADDWD128, 0, 0 }, - { MASK_SSE2, CODE_FOR_cvtsi2sd, 0, IX86_BUILTIN_CVTSI2SD, 0, 0 }, - { MASK_SSE2 | MASK_64BIT, CODE_FOR_cvtsi2sdq, 0, IX86_BUILTIN_CVTSI642SD, 0, 0 }, - { MASK_SSE2, CODE_FOR_cvtsd2ss, 0, IX86_BUILTIN_CVTSD2SS, 0, 0 }, - { MASK_SSE2, CODE_FOR_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_cvtsi2sd, 0, IX86_BUILTIN_CVTSI2SD, 0, 0 }, + { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvtsi2sdq, 0, IX86_BUILTIN_CVTSI642SD, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_cvtsd2ss, 0, IX86_BUILTIN_CVTSD2SS, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_cvtss2sd, 0, IX86_BUILTIN_CVTSS2SD, 0, 0 }, /* SSE3 MMX */ - { MASK_SSE3, CODE_FOR_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, 0, 0 }, - { MASK_SSE3, CODE_FOR_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, 0, 0 }, - { MASK_SSE3, CODE_FOR_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, 0, 0 }, - { MASK_SSE3, CODE_FOR_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, 0, 0 }, - { MASK_SSE3, CODE_FOR_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, 0, 0 }, - { MASK_SSE3, CODE_FOR_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, 0, 0 } + { MASK_SSE3, CODE_FOR_sse3_addsubv4sf3, "__builtin_ia32_addsubps", IX86_BUILTIN_ADDSUBPS, 0, 0 }, + { MASK_SSE3, CODE_FOR_sse3_addsubv2df3, "__builtin_ia32_addsubpd", IX86_BUILTIN_ADDSUBPD, 0, 0 }, + { MASK_SSE3, CODE_FOR_sse3_haddv4sf3, "__builtin_ia32_haddps", IX86_BUILTIN_HADDPS, 0, 0 }, + { MASK_SSE3, CODE_FOR_sse3_haddv2df3, "__builtin_ia32_haddpd", IX86_BUILTIN_HADDPD, 0, 0 }, + { MASK_SSE3, CODE_FOR_sse3_hsubv4sf3, "__builtin_ia32_hsubps", IX86_BUILTIN_HSUBPS, 0, 0 }, + { MASK_SSE3, CODE_FOR_sse3_hsubv2df3, "__builtin_ia32_hsubpd", IX86_BUILTIN_HSUBPD, 0, 0 } }; static const struct builtin_description bdesc_1arg[] = @@ -13159,52 +14911,47 @@ static const struct builtin_description bdesc_1arg[] = { MASK_SSE, CODE_FOR_sse_movmskps, 0, IX86_BUILTIN_MOVMSKPS, 0, 0 }, { MASK_SSE, CODE_FOR_sqrtv4sf2, 0, IX86_BUILTIN_SQRTPS, 0, 0 }, - { MASK_SSE, CODE_FOR_rsqrtv4sf2, 0, IX86_BUILTIN_RSQRTPS, 0, 0 }, - { MASK_SSE, CODE_FOR_rcpv4sf2, 0, IX86_BUILTIN_RCPPS, 0, 0 }, + { MASK_SSE, CODE_FOR_sse_rsqrtv4sf2, 0, IX86_BUILTIN_RSQRTPS, 0, 0 }, + { MASK_SSE, CODE_FOR_sse_rcpv4sf2, 0, IX86_BUILTIN_RCPPS, 0, 0 }, - { MASK_SSE, CODE_FOR_cvtps2pi, 0, IX86_BUILTIN_CVTPS2PI, 0, 0 }, - { MASK_SSE, CODE_FOR_cvtss2si, 0, IX86_BUILTIN_CVTSS2SI, 0, 0 }, - { MASK_SSE | MASK_64BIT, CODE_FOR_cvtss2siq, 0, IX86_BUILTIN_CVTSS2SI64, 0, 0 }, - { MASK_SSE, CODE_FOR_cvttps2pi, 0, IX86_BUILTIN_CVTTPS2PI, 0, 0 }, - { MASK_SSE, CODE_FOR_cvttss2si, 0, IX86_BUILTIN_CVTTSS2SI, 0, 0 }, - { MASK_SSE | MASK_64BIT, CODE_FOR_cvttss2siq, 0, IX86_BUILTIN_CVTTSS2SI64, 0, 0 }, + { MASK_SSE, CODE_FOR_sse_cvtps2pi, 0, IX86_BUILTIN_CVTPS2PI, 0, 0 }, + { MASK_SSE, CODE_FOR_sse_cvtss2si, 0, IX86_BUILTIN_CVTSS2SI, 0, 0 }, + { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvtss2siq, 0, IX86_BUILTIN_CVTSS2SI64, 0, 0 }, + { MASK_SSE, CODE_FOR_sse_cvttps2pi, 0, IX86_BUILTIN_CVTTPS2PI, 0, 0 }, + { MASK_SSE, CODE_FOR_sse_cvttss2si, 0, IX86_BUILTIN_CVTTSS2SI, 0, 0 }, + { MASK_SSE | MASK_64BIT, CODE_FOR_sse_cvttss2siq, 0, IX86_BUILTIN_CVTTSS2SI64, 0, 0 }, { MASK_SSE2, CODE_FOR_sse2_pmovmskb, 0, IX86_BUILTIN_PMOVMSKB128, 0, 0 }, { MASK_SSE2, CODE_FOR_sse2_movmskpd, 0, IX86_BUILTIN_MOVMSKPD, 0, 0 }, - { MASK_SSE2, CODE_FOR_sse2_movq2dq, 0, IX86_BUILTIN_MOVQ2DQ, 0, 0 }, - { MASK_SSE2, CODE_FOR_sse2_movdq2q, 0, IX86_BUILTIN_MOVDQ2Q, 0, 0 }, { MASK_SSE2, CODE_FOR_sqrtv2df2, 0, IX86_BUILTIN_SQRTPD, 0, 0 }, - { MASK_SSE2, CODE_FOR_cvtdq2pd, 0, IX86_BUILTIN_CVTDQ2PD, 0, 0 }, - { MASK_SSE2, CODE_FOR_cvtdq2ps, 0, IX86_BUILTIN_CVTDQ2PS, 0, 0 }, - - { MASK_SSE2, CODE_FOR_cvtpd2dq, 0, IX86_BUILTIN_CVTPD2DQ, 0, 0 }, - { MASK_SSE2, CODE_FOR_cvtpd2pi, 0, IX86_BUILTIN_CVTPD2PI, 0, 0 }, - { MASK_SSE2, CODE_FOR_cvtpd2ps, 0, IX86_BUILTIN_CVTPD2PS, 0, 0 }, - { MASK_SSE2, CODE_FOR_cvttpd2dq, 0, IX86_BUILTIN_CVTTPD2DQ, 0, 0 }, - { MASK_SSE2, CODE_FOR_cvttpd2pi, 0, IX86_BUILTIN_CVTTPD2PI, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_cvtdq2pd, 0, IX86_BUILTIN_CVTDQ2PD, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_cvtdq2ps, 0, IX86_BUILTIN_CVTDQ2PS, 0, 0 }, - { MASK_SSE2, CODE_FOR_cvtpi2pd, 0, IX86_BUILTIN_CVTPI2PD, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_cvtpd2dq, 0, IX86_BUILTIN_CVTPD2DQ, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_cvtpd2pi, 0, IX86_BUILTIN_CVTPD2PI, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_cvtpd2ps, 0, IX86_BUILTIN_CVTPD2PS, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_cvttpd2dq, 0, IX86_BUILTIN_CVTTPD2DQ, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_cvttpd2pi, 0, IX86_BUILTIN_CVTTPD2PI, 0, 0 }, - { MASK_SSE2, CODE_FOR_cvtsd2si, 0, IX86_BUILTIN_CVTSD2SI, 0, 0 }, - { MASK_SSE2, CODE_FOR_cvttsd2si, 0, IX86_BUILTIN_CVTTSD2SI, 0, 0 }, - { MASK_SSE2 | MASK_64BIT, CODE_FOR_cvtsd2siq, 0, IX86_BUILTIN_CVTSD2SI64, 0, 0 }, - { MASK_SSE2 | MASK_64BIT, CODE_FOR_cvttsd2siq, 0, IX86_BUILTIN_CVTTSD2SI64, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_cvtpi2pd, 0, IX86_BUILTIN_CVTPI2PD, 0, 0 }, - { MASK_SSE2, CODE_FOR_cvtps2dq, 0, IX86_BUILTIN_CVTPS2DQ, 0, 0 }, - { MASK_SSE2, CODE_FOR_cvtps2pd, 0, IX86_BUILTIN_CVTPS2PD, 0, 0 }, - { MASK_SSE2, CODE_FOR_cvttps2dq, 0, IX86_BUILTIN_CVTTPS2DQ, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_cvtsd2si, 0, IX86_BUILTIN_CVTSD2SI, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_cvttsd2si, 0, IX86_BUILTIN_CVTTSD2SI, 0, 0 }, + { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvtsd2siq, 0, IX86_BUILTIN_CVTSD2SI64, 0, 0 }, + { MASK_SSE2 | MASK_64BIT, CODE_FOR_sse2_cvttsd2siq, 0, IX86_BUILTIN_CVTTSD2SI64, 0, 0 }, - { MASK_SSE2, CODE_FOR_sse2_movq, 0, IX86_BUILTIN_MOVQ, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_cvtps2dq, 0, IX86_BUILTIN_CVTPS2DQ, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_cvtps2pd, 0, IX86_BUILTIN_CVTPS2PD, 0, 0 }, + { MASK_SSE2, CODE_FOR_sse2_cvttps2dq, 0, IX86_BUILTIN_CVTTPS2DQ, 0, 0 }, /* SSE3 */ - { MASK_SSE3, CODE_FOR_movshdup, 0, IX86_BUILTIN_MOVSHDUP, 0, 0 }, - { MASK_SSE3, CODE_FOR_movsldup, 0, IX86_BUILTIN_MOVSLDUP, 0, 0 }, - { MASK_SSE3, CODE_FOR_movddup, 0, IX86_BUILTIN_MOVDDUP, 0, 0 } + { MASK_SSE3, CODE_FOR_sse3_movshdup, 0, IX86_BUILTIN_MOVSHDUP, 0, 0 }, + { MASK_SSE3, CODE_FOR_sse3_movsldup, 0, IX86_BUILTIN_MOVSLDUP, 0, 0 }, }; -void +static void ix86_init_builtins (void) { if (TARGET_MMX) @@ -13220,6 +14967,18 @@ ix86_init_mmx_sse_builtins (void) const struct builtin_description * d; size_t i; + tree V16QI_type_node = build_vector_type_for_mode (intQI_type_node, V16QImode); + tree V2SI_type_node = build_vector_type_for_mode (intSI_type_node, V2SImode); + tree V2SF_type_node = build_vector_type_for_mode (float_type_node, V2SFmode); + tree V2DI_type_node + = build_vector_type_for_mode (long_long_integer_type_node, V2DImode); + tree V2DF_type_node = build_vector_type_for_mode (double_type_node, V2DFmode); + tree V4SF_type_node = build_vector_type_for_mode (float_type_node, V4SFmode); + tree V4SI_type_node = build_vector_type_for_mode (intSI_type_node, V4SImode); + tree V4HI_type_node = build_vector_type_for_mode (intHI_type_node, V4HImode); + tree V8QI_type_node = build_vector_type_for_mode (intQI_type_node, V8QImode); + tree V8HI_type_node = build_vector_type_for_mode (intHI_type_node, V8HImode); + tree pchar_type_node = build_pointer_type (char_type_node); tree pcchar_type_node = build_pointer_type ( build_type_variant (char_type_node, 1, 0)); @@ -13256,13 +15015,7 @@ ix86_init_mmx_sse_builtins (void) tree v4sf_ftype_v4sf_v2si = build_function_type_list (V4SF_type_node, V4SF_type_node, V2SI_type_node, NULL_TREE); - tree int_ftype_v4hi_int - = build_function_type_list (integer_type_node, - V4HI_type_node, integer_type_node, NULL_TREE); - tree v4hi_ftype_v4hi_int_int - = build_function_type_list (V4HI_type_node, V4HI_type_node, - integer_type_node, integer_type_node, - NULL_TREE); + /* Miscellaneous. */ tree v8qi_ftype_v4hi_v4hi = build_function_type_list (V8QI_type_node, @@ -13301,10 +15054,6 @@ ix86_init_mmx_sse_builtins (void) NULL_TREE); tree unsigned_ftype_void = build_function_type (unsigned_type_node, void_list_node); - tree di_ftype_void - = build_function_type (long_long_unsigned_type_node, void_list_node); - tree v4sf_ftype_void - = build_function_type (V4SF_type_node, void_list_node); tree v2si_ftype_v4sf = build_function_type_list (V2SI_type_node, V4SF_type_node, NULL_TREE); /* Loads/stores. */ @@ -13368,8 +15117,6 @@ ix86_init_mmx_sse_builtins (void) = build_function_type_list (V2SI_type_node, V2SF_type_node, V2SF_type_node, NULL_TREE); tree pint_type_node = build_pointer_type (integer_type_node); - tree pcint_type_node = build_pointer_type ( - build_type_variant (integer_type_node, 1, 0)); tree pdouble_type_node = build_pointer_type (double_type_node); tree pcdouble_type_node = build_pointer_type ( build_type_variant (double_type_node, 1, 0)); @@ -13377,21 +15124,8 @@ ix86_init_mmx_sse_builtins (void) = build_function_type_list (integer_type_node, V2DF_type_node, V2DF_type_node, NULL_TREE); - tree ti_ftype_void - = build_function_type (intTI_type_node, void_list_node); - tree v2di_ftype_void - = build_function_type (V2DI_type_node, void_list_node); - tree ti_ftype_ti_ti - = build_function_type_list (intTI_type_node, - intTI_type_node, intTI_type_node, NULL_TREE); tree void_ftype_pcvoid = build_function_type_list (void_type_node, const_ptr_type_node, NULL_TREE); - tree v2di_ftype_di - = build_function_type_list (V2DI_type_node, - long_long_unsigned_type_node, NULL_TREE); - tree di_ftype_v2di - = build_function_type_list (long_long_unsigned_type_node, - V2DI_type_node, NULL_TREE); tree v4sf_ftype_v4si = build_function_type_list (V4SF_type_node, V4SI_type_node, NULL_TREE); tree v4si_ftype_v4sf @@ -13431,12 +15165,9 @@ ix86_init_mmx_sse_builtins (void) V2DF_type_node, V2DF_type_node, integer_type_node, NULL_TREE); - tree v2df_ftype_v2df_pv2si + tree v2df_ftype_v2df_pcdouble = build_function_type_list (V2DF_type_node, - V2DF_type_node, pv2si_type_node, NULL_TREE); - tree void_ftype_pv2si_v2df - = build_function_type_list (void_type_node, - pv2si_type_node, V2DF_type_node, NULL_TREE); + V2DF_type_node, pcdouble_type_node, NULL_TREE); tree void_ftype_pdouble_v2df = build_function_type_list (void_type_node, pdouble_type_node, V2DF_type_node, NULL_TREE); @@ -13469,18 +15200,6 @@ ix86_init_mmx_sse_builtins (void) V2DF_type_node, V2DF_type_node, NULL_TREE); tree v2df_ftype_v2df = build_function_type_list (V2DF_type_node, V2DF_type_node, NULL_TREE); - tree v2df_ftype_double - = build_function_type_list (V2DF_type_node, double_type_node, NULL_TREE); - tree v2df_ftype_double_double - = build_function_type_list (V2DF_type_node, - double_type_node, double_type_node, NULL_TREE); - tree int_ftype_v8hi_int - = build_function_type_list (integer_type_node, - V8HI_type_node, integer_type_node, NULL_TREE); - tree v8hi_ftype_v8hi_int_int - = build_function_type_list (V8HI_type_node, - V8HI_type_node, integer_type_node, - integer_type_node, NULL_TREE); tree v2di_ftype_v2di_int = build_function_type_list (V2DI_type_node, V2DI_type_node, integer_type_node, NULL_TREE); @@ -13490,21 +15209,21 @@ ix86_init_mmx_sse_builtins (void) tree v8hi_ftype_v8hi_int = build_function_type_list (V8HI_type_node, V8HI_type_node, integer_type_node, NULL_TREE); - tree v8hi_ftype_v8hi_v2di - = build_function_type_list (V8HI_type_node, - V8HI_type_node, V2DI_type_node, NULL_TREE); - tree v4si_ftype_v4si_v2di - = build_function_type_list (V4SI_type_node, - V4SI_type_node, V2DI_type_node, NULL_TREE); tree v4si_ftype_v8hi_v8hi = build_function_type_list (V4SI_type_node, V8HI_type_node, V8HI_type_node, NULL_TREE); tree di_ftype_v8qi_v8qi = build_function_type_list (long_long_unsigned_type_node, V8QI_type_node, V8QI_type_node, NULL_TREE); + tree di_ftype_v2si_v2si + = build_function_type_list (long_long_unsigned_type_node, + V2SI_type_node, V2SI_type_node, NULL_TREE); tree v2di_ftype_v16qi_v16qi = build_function_type_list (V2DI_type_node, V16QI_type_node, V16QI_type_node, NULL_TREE); + tree v2di_ftype_v4si_v4si + = build_function_type_list (V2DI_type_node, + V4SI_type_node, V4SI_type_node, NULL_TREE); tree int_ftype_v16qi = build_function_type_list (integer_type_node, V16QI_type_node, NULL_TREE); tree v16qi_ftype_pcchar @@ -13512,16 +15231,10 @@ ix86_init_mmx_sse_builtins (void) tree void_ftype_pchar_v16qi = build_function_type_list (void_type_node, pchar_type_node, V16QI_type_node, NULL_TREE); - tree v4si_ftype_pcint - = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE); - tree void_ftype_pcint_v4si - = build_function_type_list (void_type_node, - pcint_type_node, V4SI_type_node, NULL_TREE); - tree v2di_ftype_v2di - = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE); tree float80_type; tree float128_type; + tree ftype; /* The __float80 type. */ if (TYPE_MODE (long_double_type_node) == XFmode) @@ -13531,15 +15244,18 @@ ix86_init_mmx_sse_builtins (void) { /* The __float80 type. */ float80_type = make_node (REAL_TYPE); - TYPE_PRECISION (float80_type) = 96; + TYPE_PRECISION (float80_type) = 80; layout_type (float80_type); (*lang_hooks.types.register_builtin_type) (float80_type, "__float80"); } - float128_type = make_node (REAL_TYPE); - TYPE_PRECISION (float128_type) = 128; - layout_type (float128_type); - (*lang_hooks.types.register_builtin_type) (float128_type, "__float128"); + if (TARGET_64BIT) + { + float128_type = make_node (REAL_TYPE); + TYPE_PRECISION (float128_type) = 128; + layout_type (float128_type); + (*lang_hooks.types.register_builtin_type) (float128_type, "__float128"); + } /* Add all builtins that are more or less simple operations on two operands. */ @@ -13571,9 +15287,6 @@ ix86_init_mmx_sse_builtins (void) case V2DFmode: type = v2df_ftype_v2df_v2df; break; - case TImode: - type = ti_ftype_ti_ti; - break; case V4SFmode: type = v4sf_ftype_v4sf_v4sf; break; @@ -13591,27 +15304,22 @@ ix86_init_mmx_sse_builtins (void) break; default: - abort (); + gcc_unreachable (); } /* Override for comparisons. */ - if (d->icode == CODE_FOR_maskcmpv4sf3 - || d->icode == CODE_FOR_maskncmpv4sf3 - || d->icode == CODE_FOR_vmmaskcmpv4sf3 - || d->icode == CODE_FOR_vmmaskncmpv4sf3) + if (d->icode == CODE_FOR_sse_maskcmpv4sf3 + || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3) type = v4si_ftype_v4sf_v4sf; - if (d->icode == CODE_FOR_maskcmpv2df3 - || d->icode == CODE_FOR_maskncmpv2df3 - || d->icode == CODE_FOR_vmmaskcmpv2df3 - || d->icode == CODE_FOR_vmmaskncmpv2df3) + if (d->icode == CODE_FOR_sse2_maskcmpv2df3 + || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3) type = v2di_ftype_v2df_v2df; def_builtin (d->mask, d->name, type, d->code); } /* Add the remaining MMX insns with somewhat more complicated types. */ - def_builtin (MASK_MMX, "__builtin_ia32_mmx_zero", di_ftype_void, IX86_BUILTIN_MMX_ZERO); def_builtin (MASK_MMX, "__builtin_ia32_emms", void_ftype_void, IX86_BUILTIN_EMMS); def_builtin (MASK_MMX, "__builtin_ia32_psllw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSLLW); def_builtin (MASK_MMX, "__builtin_ia32_pslld", v2si_ftype_v2si_di, IX86_BUILTIN_PSLLD); @@ -13624,7 +15332,7 @@ ix86_init_mmx_sse_builtins (void) def_builtin (MASK_MMX, "__builtin_ia32_psraw", v4hi_ftype_v4hi_di, IX86_BUILTIN_PSRAW); def_builtin (MASK_MMX, "__builtin_ia32_psrad", v2si_ftype_v2si_di, IX86_BUILTIN_PSRAD); - def_builtin (MASK_MMX, "__builtin_ia32_pshufw", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSHUFW); + def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_pshufw", v4hi_ftype_v4hi_int, IX86_BUILTIN_PSHUFW); def_builtin (MASK_MMX, "__builtin_ia32_pmaddwd", v2si_ftype_v4hi_v4hi, IX86_BUILTIN_PMADDWD); /* comi/ucomi insns. */ @@ -13650,17 +15358,10 @@ ix86_init_mmx_sse_builtins (void) def_builtin (MASK_SSE, "__builtin_ia32_cvttss2si", int_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI); def_builtin (MASK_SSE | MASK_64BIT, "__builtin_ia32_cvttss2si64", int64_ftype_v4sf, IX86_BUILTIN_CVTTSS2SI64); - def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_pextrw", int_ftype_v4hi_int, IX86_BUILTIN_PEXTRW); - def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_pinsrw", v4hi_ftype_v4hi_int_int, IX86_BUILTIN_PINSRW); - def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_maskmovq", void_ftype_v8qi_v8qi_pchar, IX86_BUILTIN_MASKMOVQ); - def_builtin (MASK_SSE, "__builtin_ia32_loadaps", v4sf_ftype_pcfloat, IX86_BUILTIN_LOADAPS); def_builtin (MASK_SSE, "__builtin_ia32_loadups", v4sf_ftype_pcfloat, IX86_BUILTIN_LOADUPS); - def_builtin (MASK_SSE, "__builtin_ia32_loadss", v4sf_ftype_pcfloat, IX86_BUILTIN_LOADSS); - def_builtin (MASK_SSE, "__builtin_ia32_storeaps", void_ftype_pfloat_v4sf, IX86_BUILTIN_STOREAPS); def_builtin (MASK_SSE, "__builtin_ia32_storeups", void_ftype_pfloat_v4sf, IX86_BUILTIN_STOREUPS); - def_builtin (MASK_SSE, "__builtin_ia32_storess", void_ftype_pfloat_v4sf, IX86_BUILTIN_STORESS); def_builtin (MASK_SSE, "__builtin_ia32_loadhps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADHPS); def_builtin (MASK_SSE, "__builtin_ia32_loadlps", v4sf_ftype_v4sf_pv2si, IX86_BUILTIN_LOADLPS); @@ -13715,27 +15416,14 @@ ix86_init_mmx_sse_builtins (void) def_builtin (MASK_3DNOW_A, "__builtin_ia32_pswapdsf", v2sf_ftype_v2sf, IX86_BUILTIN_PSWAPDSF); def_builtin (MASK_3DNOW_A, "__builtin_ia32_pswapdsi", v2si_ftype_v2si, IX86_BUILTIN_PSWAPDSI); - def_builtin (MASK_SSE, "__builtin_ia32_setzerops", v4sf_ftype_void, IX86_BUILTIN_SSE_ZERO); - /* SSE2 */ - def_builtin (MASK_SSE2, "__builtin_ia32_pextrw128", int_ftype_v8hi_int, IX86_BUILTIN_PEXTRW128); - def_builtin (MASK_SSE2, "__builtin_ia32_pinsrw128", v8hi_ftype_v8hi_int_int, IX86_BUILTIN_PINSRW128); - def_builtin (MASK_SSE2, "__builtin_ia32_maskmovdqu", void_ftype_v16qi_v16qi_pchar, IX86_BUILTIN_MASKMOVDQU); - def_builtin (MASK_SSE2, "__builtin_ia32_movq2dq", v2di_ftype_di, IX86_BUILTIN_MOVQ2DQ); - def_builtin (MASK_SSE2, "__builtin_ia32_movdq2q", di_ftype_v2di, IX86_BUILTIN_MOVDQ2Q); - def_builtin (MASK_SSE2, "__builtin_ia32_loadapd", v2df_ftype_pcdouble, IX86_BUILTIN_LOADAPD); def_builtin (MASK_SSE2, "__builtin_ia32_loadupd", v2df_ftype_pcdouble, IX86_BUILTIN_LOADUPD); - def_builtin (MASK_SSE2, "__builtin_ia32_loadsd", v2df_ftype_pcdouble, IX86_BUILTIN_LOADSD); - def_builtin (MASK_SSE2, "__builtin_ia32_storeapd", void_ftype_pdouble_v2df, IX86_BUILTIN_STOREAPD); def_builtin (MASK_SSE2, "__builtin_ia32_storeupd", void_ftype_pdouble_v2df, IX86_BUILTIN_STOREUPD); - def_builtin (MASK_SSE2, "__builtin_ia32_storesd", void_ftype_pdouble_v2df, IX86_BUILTIN_STORESD); - def_builtin (MASK_SSE2, "__builtin_ia32_loadhpd", v2df_ftype_v2df_pv2si, IX86_BUILTIN_LOADHPD); - def_builtin (MASK_SSE2, "__builtin_ia32_loadlpd", v2df_ftype_v2df_pv2si, IX86_BUILTIN_LOADLPD); - def_builtin (MASK_SSE2, "__builtin_ia32_storehpd", void_ftype_pv2si_v2df, IX86_BUILTIN_STOREHPD); - def_builtin (MASK_SSE2, "__builtin_ia32_storelpd", void_ftype_pv2si_v2df, IX86_BUILTIN_STORELPD); + def_builtin (MASK_SSE2, "__builtin_ia32_loadhpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADHPD); + def_builtin (MASK_SSE2, "__builtin_ia32_loadlpd", v2df_ftype_v2df_pcdouble, IX86_BUILTIN_LOADLPD); def_builtin (MASK_SSE2, "__builtin_ia32_movmskpd", int_ftype_v2df, IX86_BUILTIN_MOVMSKPD); def_builtin (MASK_SSE2, "__builtin_ia32_pmovmskb128", int_ftype_v16qi, IX86_BUILTIN_PMOVMSKB128); @@ -13778,38 +15466,26 @@ ix86_init_mmx_sse_builtins (void) def_builtin (MASK_SSE2, "__builtin_ia32_cvtsd2ss", v4sf_ftype_v4sf_v2df, IX86_BUILTIN_CVTSD2SS); def_builtin (MASK_SSE2, "__builtin_ia32_cvtss2sd", v2df_ftype_v2df_v4sf, IX86_BUILTIN_CVTSS2SD); - def_builtin (MASK_SSE2, "__builtin_ia32_setpd1", v2df_ftype_double, IX86_BUILTIN_SETPD1); - def_builtin (MASK_SSE2, "__builtin_ia32_setpd", v2df_ftype_double_double, IX86_BUILTIN_SETPD); - def_builtin (MASK_SSE2, "__builtin_ia32_setzeropd", ti_ftype_void, IX86_BUILTIN_CLRPD); - def_builtin (MASK_SSE2, "__builtin_ia32_loadpd1", v2df_ftype_pcdouble, IX86_BUILTIN_LOADPD1); - def_builtin (MASK_SSE2, "__builtin_ia32_loadrpd", v2df_ftype_pcdouble, IX86_BUILTIN_LOADRPD); - def_builtin (MASK_SSE2, "__builtin_ia32_storepd1", void_ftype_pdouble_v2df, IX86_BUILTIN_STOREPD1); - def_builtin (MASK_SSE2, "__builtin_ia32_storerpd", void_ftype_pdouble_v2df, IX86_BUILTIN_STORERPD); - def_builtin (MASK_SSE2, "__builtin_ia32_clflush", void_ftype_pcvoid, IX86_BUILTIN_CLFLUSH); def_builtin (MASK_SSE2, "__builtin_ia32_lfence", void_ftype_void, IX86_BUILTIN_LFENCE); def_builtin (MASK_SSE2, "__builtin_ia32_mfence", void_ftype_void, IX86_BUILTIN_MFENCE); - def_builtin (MASK_SSE2, "__builtin_ia32_loaddqa", v16qi_ftype_pcchar, IX86_BUILTIN_LOADDQA); def_builtin (MASK_SSE2, "__builtin_ia32_loaddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LOADDQU); - def_builtin (MASK_SSE2, "__builtin_ia32_loadd", v4si_ftype_pcint, IX86_BUILTIN_LOADD); - def_builtin (MASK_SSE2, "__builtin_ia32_storedqa", void_ftype_pchar_v16qi, IX86_BUILTIN_STOREDQA); def_builtin (MASK_SSE2, "__builtin_ia32_storedqu", void_ftype_pchar_v16qi, IX86_BUILTIN_STOREDQU); - def_builtin (MASK_SSE2, "__builtin_ia32_stored", void_ftype_pcint_v4si, IX86_BUILTIN_STORED); - def_builtin (MASK_SSE2, "__builtin_ia32_movq", v2di_ftype_v2di, IX86_BUILTIN_MOVQ); - def_builtin (MASK_SSE, "__builtin_ia32_setzero128", v2di_ftype_void, IX86_BUILTIN_CLRTI); + def_builtin (MASK_SSE2, "__builtin_ia32_pmuludq", di_ftype_v2si_v2si, IX86_BUILTIN_PMULUDQ); + def_builtin (MASK_SSE2, "__builtin_ia32_pmuludq128", v2di_ftype_v4si_v4si, IX86_BUILTIN_PMULUDQ128); - def_builtin (MASK_SSE2, "__builtin_ia32_psllw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSLLW128); - def_builtin (MASK_SSE2, "__builtin_ia32_pslld128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSLLD128); + def_builtin (MASK_SSE2, "__builtin_ia32_psllw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSLLW128); + def_builtin (MASK_SSE2, "__builtin_ia32_pslld128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSLLD128); def_builtin (MASK_SSE2, "__builtin_ia32_psllq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSLLQ128); - def_builtin (MASK_SSE2, "__builtin_ia32_psrlw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSRLW128); - def_builtin (MASK_SSE2, "__builtin_ia32_psrld128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSRLD128); + def_builtin (MASK_SSE2, "__builtin_ia32_psrlw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSRLW128); + def_builtin (MASK_SSE2, "__builtin_ia32_psrld128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSRLD128); def_builtin (MASK_SSE2, "__builtin_ia32_psrlq128", v2di_ftype_v2di_v2di, IX86_BUILTIN_PSRLQ128); - def_builtin (MASK_SSE2, "__builtin_ia32_psraw128", v8hi_ftype_v8hi_v2di, IX86_BUILTIN_PSRAW128); - def_builtin (MASK_SSE2, "__builtin_ia32_psrad128", v4si_ftype_v4si_v2di, IX86_BUILTIN_PSRAD128); + def_builtin (MASK_SSE2, "__builtin_ia32_psraw128", v8hi_ftype_v8hi_v8hi, IX86_BUILTIN_PSRAW128); + def_builtin (MASK_SSE2, "__builtin_ia32_psrad128", v4si_ftype_v4si_v4si, IX86_BUILTIN_PSRAD128); def_builtin (MASK_SSE2, "__builtin_ia32_pslldqi128", v2di_ftype_v2di_int, IX86_BUILTIN_PSLLDQI128); def_builtin (MASK_SSE2, "__builtin_ia32_psllwi128", v8hi_ftype_v8hi_int, IX86_BUILTIN_PSLLWI128); @@ -13841,10 +15517,77 @@ ix86_init_mmx_sse_builtins (void) IX86_BUILTIN_MOVSLDUP); def_builtin (MASK_SSE3, "__builtin_ia32_lddqu", v16qi_ftype_pcchar, IX86_BUILTIN_LDDQU); - def_builtin (MASK_SSE3, "__builtin_ia32_loadddup", - v2df_ftype_pcdouble, IX86_BUILTIN_LOADDDUP); - def_builtin (MASK_SSE3, "__builtin_ia32_movddup", - v2df_ftype_v2df, IX86_BUILTIN_MOVDDUP); + + /* Access to the vec_init patterns. */ + ftype = build_function_type_list (V2SI_type_node, integer_type_node, + integer_type_node, NULL_TREE); + def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v2si", + ftype, IX86_BUILTIN_VEC_INIT_V2SI); + + ftype = build_function_type_list (V4HI_type_node, short_integer_type_node, + short_integer_type_node, + short_integer_type_node, + short_integer_type_node, NULL_TREE); + def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v4hi", + ftype, IX86_BUILTIN_VEC_INIT_V4HI); + + ftype = build_function_type_list (V8QI_type_node, char_type_node, + char_type_node, char_type_node, + char_type_node, char_type_node, + char_type_node, char_type_node, + char_type_node, NULL_TREE); + def_builtin (MASK_MMX, "__builtin_ia32_vec_init_v8qi", + ftype, IX86_BUILTIN_VEC_INIT_V8QI); + + /* Access to the vec_extract patterns. */ + ftype = build_function_type_list (double_type_node, V2DF_type_node, + integer_type_node, NULL_TREE); + def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v2df", + ftype, IX86_BUILTIN_VEC_EXT_V2DF); + + ftype = build_function_type_list (long_long_integer_type_node, + V2DI_type_node, integer_type_node, + NULL_TREE); + def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v2di", + ftype, IX86_BUILTIN_VEC_EXT_V2DI); + + ftype = build_function_type_list (float_type_node, V4SF_type_node, + integer_type_node, NULL_TREE); + def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v4sf", + ftype, IX86_BUILTIN_VEC_EXT_V4SF); + + ftype = build_function_type_list (intSI_type_node, V4SI_type_node, + integer_type_node, NULL_TREE); + def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v4si", + ftype, IX86_BUILTIN_VEC_EXT_V4SI); + + ftype = build_function_type_list (intHI_type_node, V8HI_type_node, + integer_type_node, NULL_TREE); + def_builtin (MASK_SSE, "__builtin_ia32_vec_ext_v8hi", + ftype, IX86_BUILTIN_VEC_EXT_V8HI); + + ftype = build_function_type_list (intHI_type_node, V4HI_type_node, + integer_type_node, NULL_TREE); + def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_vec_ext_v4hi", + ftype, IX86_BUILTIN_VEC_EXT_V4HI); + + ftype = build_function_type_list (intSI_type_node, V2SI_type_node, + integer_type_node, NULL_TREE); + def_builtin (MASK_MMX, "__builtin_ia32_vec_ext_v2si", + ftype, IX86_BUILTIN_VEC_EXT_V2SI); + + /* Access to the vec_set patterns. */ + ftype = build_function_type_list (V8HI_type_node, V8HI_type_node, + intHI_type_node, + integer_type_node, NULL_TREE); + def_builtin (MASK_SSE, "__builtin_ia32_vec_set_v8hi", + ftype, IX86_BUILTIN_VEC_SET_V8HI); + + ftype = build_function_type_list (V4HI_type_node, V4HI_type_node, + intHI_type_node, + integer_type_node, NULL_TREE); + def_builtin (MASK_SSE | MASK_3DNOW_A, "__builtin_ia32_vec_set_v4hi", + ftype, IX86_BUILTIN_VEC_SET_V4HI); } /* Errors in the source file can cause expand_expr to return const0_rtx @@ -13853,17 +15596,8 @@ ix86_init_mmx_sse_builtins (void) static rtx safe_vector_operand (rtx x, enum machine_mode mode) { - if (x != const0_rtx) - return x; - x = gen_reg_rtx (mode); - - if (VALID_MMX_REG_MODE (mode) || VALID_MMX_REG_MODE_3DNOW (mode)) - emit_insn (gen_mmx_clrdi (mode == DImode ? x - : gen_rtx_SUBREG (DImode, x, 0))); - else - emit_insn (gen_sse_clrv4sf (mode == V4SFmode ? x - : gen_rtx_SUBREG (V4SFmode, x, 0), - CONST0_RTX (V4SFmode))); + if (x == const0_rtx) + x = CONST0_RTX (mode); return x; } @@ -13872,11 +15606,11 @@ safe_vector_operand (rtx x, enum machine_mode mode) static rtx ix86_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target) { - rtx pat; + rtx pat, xops[3]; tree arg0 = TREE_VALUE (arglist); tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); - rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + rtx op0 = expand_normal (arg0); + rtx op1 = expand_normal (arg1); enum machine_mode tmode = insn_data[icode].operand[0].mode; enum machine_mode mode0 = insn_data[icode].operand[1].mode; enum machine_mode mode1 = insn_data[icode].operand[2].mode; @@ -13886,7 +15620,7 @@ ix86_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target) if (VECTOR_MODE_P (mode1)) op1 = safe_vector_operand (op1, mode1); - if (! target + if (optimize || !target || GET_MODE (target) != tmode || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) target = gen_reg_rtx (tmode); @@ -13898,22 +15632,35 @@ ix86_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target) op1 = gen_lowpart (TImode, x); } - /* In case the insn wants input operands in modes different from - the result, abort. */ - if ((GET_MODE (op0) != mode0 && GET_MODE (op0) != VOIDmode) - || (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)) - abort (); + /* The insn must want input operands in the same modes as the + result. */ + gcc_assert ((GET_MODE (op0) == mode0 || GET_MODE (op0) == VOIDmode) + && (GET_MODE (op1) == mode1 || GET_MODE (op1) == VOIDmode)); - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) + if (!(*insn_data[icode].operand[1].predicate) (op0, mode0)) op0 = copy_to_mode_reg (mode0, op0); - if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) + if (!(*insn_data[icode].operand[2].predicate) (op1, mode1)) op1 = copy_to_mode_reg (mode1, op1); - /* In the commutative cases, both op0 and op1 are nonimmediate_operand, - yet one of the two must not be a memory. This is normally enforced - by expanders, but we didn't bother to create one here. */ - if (GET_CODE (op0) == MEM && GET_CODE (op1) == MEM) - op0 = copy_to_mode_reg (mode0, op0); + /* ??? Using ix86_fixup_binary_operands is problematic when + we've got mismatched modes. Fake it. */ + + xops[0] = target; + xops[1] = op0; + xops[2] = op1; + + if (tmode == mode0 && tmode == mode1) + { + target = ix86_fixup_binary_operands (UNKNOWN, tmode, xops); + op0 = xops[1]; + op1 = xops[2]; + } + else if (optimize || !ix86_binary_operator_ok (UNKNOWN, tmode, xops)) + { + op0 = force_reg (mode0, op0); + op1 = force_reg (mode1, op1); + target = gen_reg_rtx (tmode); + } pat = GEN_FCN (icode) (target, op0, op1); if (! pat) @@ -13930,8 +15677,8 @@ ix86_expand_store_builtin (enum insn_code icode, tree arglist) rtx pat; tree arg0 = TREE_VALUE (arglist); tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); - rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + rtx op0 = expand_normal (arg0); + rtx op1 = expand_normal (arg1); enum machine_mode mode0 = insn_data[icode].operand[0].mode; enum machine_mode mode1 = insn_data[icode].operand[1].mode; @@ -13955,13 +15702,12 @@ ix86_expand_unop_builtin (enum insn_code icode, tree arglist, { rtx pat; tree arg0 = TREE_VALUE (arglist); - rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); + rtx op0 = expand_normal (arg0); enum machine_mode tmode = insn_data[icode].operand[0].mode; enum machine_mode mode0 = insn_data[icode].operand[1].mode; - if (! target + if (optimize || !target || GET_MODE (target) != tmode - || (do_load && GET_CODE (target) == MEM) || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) target = gen_reg_rtx (tmode); if (do_load) @@ -13971,7 +15717,8 @@ ix86_expand_unop_builtin (enum insn_code icode, tree arglist, if (VECTOR_MODE_P (mode0)) op0 = safe_vector_operand (op0, mode0); - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) + if ((optimize && !register_operand (op0, mode0)) + || ! (*insn_data[icode].operand[1].predicate) (op0, mode0)) op0 = copy_to_mode_reg (mode0, op0); } @@ -13990,11 +15737,11 @@ ix86_expand_unop1_builtin (enum insn_code icode, tree arglist, rtx target) { rtx pat; tree arg0 = TREE_VALUE (arglist); - rtx op1, op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); + rtx op1, op0 = expand_normal (arg0); enum machine_mode tmode = insn_data[icode].operand[0].mode; enum machine_mode mode0 = insn_data[icode].operand[1].mode; - if (! target + if (optimize || !target || GET_MODE (target) != tmode || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) target = gen_reg_rtx (tmode); @@ -14002,7 +15749,8 @@ ix86_expand_unop1_builtin (enum insn_code icode, tree arglist, rtx target) if (VECTOR_MODE_P (mode0)) op0 = safe_vector_operand (op0, mode0); - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) + if ((optimize && !register_operand (op0, mode0)) + || ! (*insn_data[icode].operand[1].predicate) (op0, mode0)) op0 = copy_to_mode_reg (mode0, op0); op1 = op0; @@ -14025,8 +15773,8 @@ ix86_expand_sse_compare (const struct builtin_description *d, tree arglist, rtx pat; tree arg0 = TREE_VALUE (arglist); tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); - rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + rtx op0 = expand_normal (arg0); + rtx op1 = expand_normal (arg1); rtx op2; enum machine_mode tmode = insn_data[d->icode].operand[0].mode; enum machine_mode mode0 = insn_data[d->icode].operand[1].mode; @@ -14040,7 +15788,7 @@ ix86_expand_sse_compare (const struct builtin_description *d, tree arglist, /* Swap operands if we have a comparison that isn't available in hardware. */ - if (d->flag) + if (d->flag & BUILTIN_DESC_SWAP_OPERANDS) { rtx tmp = gen_reg_rtx (mode1); emit_move_insn (tmp, op1); @@ -14048,14 +15796,16 @@ ix86_expand_sse_compare (const struct builtin_description *d, tree arglist, op0 = tmp; } - if (! target + if (optimize || !target || GET_MODE (target) != tmode || ! (*insn_data[d->icode].operand[0].predicate) (target, tmode)) target = gen_reg_rtx (tmode); - if (! (*insn_data[d->icode].operand[1].predicate) (op0, mode0)) + if ((optimize && !register_operand (op0, mode0)) + || ! (*insn_data[d->icode].operand[1].predicate) (op0, mode0)) op0 = copy_to_mode_reg (mode0, op0); - if (! (*insn_data[d->icode].operand[2].predicate) (op1, mode1)) + if ((optimize && !register_operand (op1, mode1)) + || ! (*insn_data[d->icode].operand[2].predicate) (op1, mode1)) op1 = copy_to_mode_reg (mode1, op1); op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1); @@ -14075,8 +15825,8 @@ ix86_expand_sse_comi (const struct builtin_description *d, tree arglist, rtx pat; tree arg0 = TREE_VALUE (arglist); tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); - rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + rtx op0 = expand_normal (arg0); + rtx op1 = expand_normal (arg1); rtx op2; enum machine_mode mode0 = insn_data[d->icode].operand[0].mode; enum machine_mode mode1 = insn_data[d->icode].operand[1].mode; @@ -14089,7 +15839,7 @@ ix86_expand_sse_comi (const struct builtin_description *d, tree arglist, /* Swap operands if we have a comparison that isn't available in hardware. */ - if (d->flag) + if (d->flag & BUILTIN_DESC_SWAP_OPERANDS) { rtx tmp = op1; op1 = op0; @@ -14100,9 +15850,11 @@ ix86_expand_sse_comi (const struct builtin_description *d, tree arglist, emit_move_insn (target, const0_rtx); target = gen_rtx_SUBREG (QImode, target, 0); - if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0)) + if ((optimize && !register_operand (op0, mode0)) + || !(*insn_data[d->icode].operand[0].predicate) (op0, mode0)) op0 = copy_to_mode_reg (mode0, op0); - if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1)) + if ((optimize && !register_operand (op1, mode1)) + || !(*insn_data[d->icode].operand[1].predicate) (op1, mode1)) op1 = copy_to_mode_reg (mode1, op1); op2 = gen_rtx_fmt_ee (comparison, mode0, op0, op1); @@ -14119,13 +15871,136 @@ ix86_expand_sse_comi (const struct builtin_description *d, tree arglist, return SUBREG_REG (target); } +/* Return the integer constant in ARG. Constrain it to be in the range + of the subparts of VEC_TYPE; issue an error if not. */ + +static int +get_element_number (tree vec_type, tree arg) +{ + unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1; + + if (!host_integerp (arg, 1) + || (elt = tree_low_cst (arg, 1), elt > max)) + { + error ("selector must be an integer constant in the range 0..%wi", max); + return 0; + } + + return elt; +} + +/* A subroutine of ix86_expand_builtin. These builtins are a wrapper around + ix86_expand_vector_init. We DO have language-level syntax for this, in + the form of (type){ init-list }. Except that since we can't place emms + instructions from inside the compiler, we can't allow the use of MMX + registers unless the user explicitly asks for it. So we do *not* define + vec_set/vec_extract/vec_init patterns for MMX modes in mmx.md. Instead + we have builtins invoked by mmintrin.h that gives us license to emit + these sorts of instructions. */ + +static rtx +ix86_expand_vec_init_builtin (tree type, tree arglist, rtx target) +{ + enum machine_mode tmode = TYPE_MODE (type); + enum machine_mode inner_mode = GET_MODE_INNER (tmode); + int i, n_elt = GET_MODE_NUNITS (tmode); + rtvec v = rtvec_alloc (n_elt); + + gcc_assert (VECTOR_MODE_P (tmode)); + + for (i = 0; i < n_elt; ++i, arglist = TREE_CHAIN (arglist)) + { + rtx x = expand_normal (TREE_VALUE (arglist)); + RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x); + } + + gcc_assert (arglist == NULL); + + if (!target || !register_operand (target, tmode)) + target = gen_reg_rtx (tmode); + + ix86_expand_vector_init (true, target, gen_rtx_PARALLEL (tmode, v)); + return target; +} + +/* A subroutine of ix86_expand_builtin. These builtins are a wrapper around + ix86_expand_vector_extract. They would be redundant (for non-MMX) if we + had a language-level syntax for referencing vector elements. */ + +static rtx +ix86_expand_vec_ext_builtin (tree arglist, rtx target) +{ + enum machine_mode tmode, mode0; + tree arg0, arg1; + int elt; + rtx op0; + + arg0 = TREE_VALUE (arglist); + arg1 = TREE_VALUE (TREE_CHAIN (arglist)); + + op0 = expand_normal (arg0); + elt = get_element_number (TREE_TYPE (arg0), arg1); + + tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0))); + mode0 = TYPE_MODE (TREE_TYPE (arg0)); + gcc_assert (VECTOR_MODE_P (mode0)); + + op0 = force_reg (mode0, op0); + + if (optimize || !target || !register_operand (target, tmode)) + target = gen_reg_rtx (tmode); + + ix86_expand_vector_extract (true, target, op0, elt); + + return target; +} + +/* A subroutine of ix86_expand_builtin. These builtins are a wrapper around + ix86_expand_vector_set. They would be redundant (for non-MMX) if we had + a language-level syntax for referencing vector elements. */ + +static rtx +ix86_expand_vec_set_builtin (tree arglist) +{ + enum machine_mode tmode, mode1; + tree arg0, arg1, arg2; + int elt; + rtx op0, op1, target; + + arg0 = TREE_VALUE (arglist); + arg1 = TREE_VALUE (TREE_CHAIN (arglist)); + arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); + + tmode = TYPE_MODE (TREE_TYPE (arg0)); + mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0))); + gcc_assert (VECTOR_MODE_P (tmode)); + + op0 = expand_expr (arg0, NULL_RTX, tmode, 0); + op1 = expand_expr (arg1, NULL_RTX, mode1, 0); + elt = get_element_number (TREE_TYPE (arg0), arg2); + + if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode) + op1 = convert_modes (mode1, GET_MODE (op1), op1, true); + + op0 = force_reg (tmode, op0); + op1 = force_reg (mode1, op1); + + /* OP0 is the source of these builtin functions and shouldn't be + modified. Create a copy, use it and return it as target. */ + target = gen_reg_rtx (tmode); + emit_move_insn (target, op0); + ix86_expand_vector_set (true, target, op1, elt); + + return target; +} + /* Expand an expression EXP that calls a built-in function, with result going to TARGET if that's convenient (and in mode MODE if that's convenient). SUBTARGET may be used as the target for computing one of EXP's operands. IGNORE is nonzero if the value is to be ignored. */ -rtx +static rtx ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, enum machine_mode mode ATTRIBUTE_UNUSED, int ignore ATTRIBUTE_UNUSED) @@ -14143,97 +16018,32 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, switch (fcode) { case IX86_BUILTIN_EMMS: - emit_insn (gen_emms ()); + emit_insn (gen_mmx_emms ()); return 0; case IX86_BUILTIN_SFENCE: - emit_insn (gen_sfence ()); + emit_insn (gen_sse_sfence ()); return 0; - case IX86_BUILTIN_PEXTRW: - case IX86_BUILTIN_PEXTRW128: - icode = (fcode == IX86_BUILTIN_PEXTRW - ? CODE_FOR_mmx_pextrw - : CODE_FOR_sse2_pextrw); - arg0 = TREE_VALUE (arglist); - arg1 = TREE_VALUE (TREE_CHAIN (arglist)); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); - tmode = insn_data[icode].operand[0].mode; - mode0 = insn_data[icode].operand[1].mode; - mode1 = insn_data[icode].operand[2].mode; - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) - { - error ("selector must be an integer constant in the range 0..%i", - fcode == IX86_BUILTIN_PEXTRW ? 3:7); - return gen_reg_rtx (tmode); - } - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - pat = GEN_FCN (icode) (target, op0, op1); - if (! pat) - return 0; - emit_insn (pat); - return target; - - case IX86_BUILTIN_PINSRW: - case IX86_BUILTIN_PINSRW128: - icode = (fcode == IX86_BUILTIN_PINSRW - ? CODE_FOR_mmx_pinsrw - : CODE_FOR_sse2_pinsrw); - arg0 = TREE_VALUE (arglist); - arg1 = TREE_VALUE (TREE_CHAIN (arglist)); - arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); - op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); - tmode = insn_data[icode].operand[0].mode; - mode0 = insn_data[icode].operand[1].mode; - mode1 = insn_data[icode].operand[2].mode; - mode2 = insn_data[icode].operand[3].mode; - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); - if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) - { - error ("selector must be an integer constant in the range 0..%i", - fcode == IX86_BUILTIN_PINSRW ? 15:255); - return const0_rtx; - } - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - pat = GEN_FCN (icode) (target, op0, op1, op2); - if (! pat) - return 0; - emit_insn (pat); - return target; - case IX86_BUILTIN_MASKMOVQ: case IX86_BUILTIN_MASKMOVDQU: icode = (fcode == IX86_BUILTIN_MASKMOVQ - ? (TARGET_64BIT ? CODE_FOR_mmx_maskmovq_rex : CODE_FOR_mmx_maskmovq) - : (TARGET_64BIT ? CODE_FOR_sse2_maskmovdqu_rex64 - : CODE_FOR_sse2_maskmovdqu)); + ? CODE_FOR_mmx_maskmovq + : CODE_FOR_sse2_maskmovdqu); /* Note the arg order is different from the operand order. */ arg1 = TREE_VALUE (arglist); arg2 = TREE_VALUE (TREE_CHAIN (arglist)); arg0 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); - op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); + op0 = expand_normal (arg0); + op1 = expand_normal (arg1); + op2 = expand_normal (arg2); mode0 = insn_data[icode].operand[0].mode; mode1 = insn_data[icode].operand[1].mode; mode2 = insn_data[icode].operand[2].mode; + op0 = force_reg (Pmode, op0); + op0 = gen_rtx_MEM (mode1, op0); + if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) op0 = copy_to_mode_reg (mode0, op0); if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) @@ -14247,52 +16057,39 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, return 0; case IX86_BUILTIN_SQRTSS: - return ix86_expand_unop1_builtin (CODE_FOR_vmsqrtv4sf2, arglist, target); + return ix86_expand_unop1_builtin (CODE_FOR_sse_vmsqrtv4sf2, arglist, target); case IX86_BUILTIN_RSQRTSS: - return ix86_expand_unop1_builtin (CODE_FOR_vmrsqrtv4sf2, arglist, target); + return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrsqrtv4sf2, arglist, target); case IX86_BUILTIN_RCPSS: - return ix86_expand_unop1_builtin (CODE_FOR_vmrcpv4sf2, arglist, target); - - case IX86_BUILTIN_LOADAPS: - return ix86_expand_unop_builtin (CODE_FOR_sse_movaps, arglist, target, 1); + return ix86_expand_unop1_builtin (CODE_FOR_sse_vmrcpv4sf2, arglist, target); case IX86_BUILTIN_LOADUPS: return ix86_expand_unop_builtin (CODE_FOR_sse_movups, arglist, target, 1); - case IX86_BUILTIN_STOREAPS: - return ix86_expand_store_builtin (CODE_FOR_sse_movaps, arglist); - case IX86_BUILTIN_STOREUPS: return ix86_expand_store_builtin (CODE_FOR_sse_movups, arglist); - case IX86_BUILTIN_LOADSS: - return ix86_expand_unop_builtin (CODE_FOR_sse_loadss, arglist, target, 1); - - case IX86_BUILTIN_STORESS: - return ix86_expand_store_builtin (CODE_FOR_sse_storess, arglist); - case IX86_BUILTIN_LOADHPS: case IX86_BUILTIN_LOADLPS: case IX86_BUILTIN_LOADHPD: case IX86_BUILTIN_LOADLPD: - icode = (fcode == IX86_BUILTIN_LOADHPS ? CODE_FOR_sse_movhps - : fcode == IX86_BUILTIN_LOADLPS ? CODE_FOR_sse_movlps - : fcode == IX86_BUILTIN_LOADHPD ? CODE_FOR_sse2_movhpd - : CODE_FOR_sse2_movsd); + icode = (fcode == IX86_BUILTIN_LOADHPS ? CODE_FOR_sse_loadhps + : fcode == IX86_BUILTIN_LOADLPS ? CODE_FOR_sse_loadlps + : fcode == IX86_BUILTIN_LOADHPD ? CODE_FOR_sse2_loadhpd + : CODE_FOR_sse2_loadlpd); arg0 = TREE_VALUE (arglist); arg1 = TREE_VALUE (TREE_CHAIN (arglist)); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + op0 = expand_normal (arg0); + op1 = expand_normal (arg1); tmode = insn_data[icode].operand[0].mode; mode0 = insn_data[icode].operand[1].mode; mode1 = insn_data[icode].operand[2].mode; - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); + op0 = force_reg (mode0, op0); op1 = gen_rtx_MEM (mode1, copy_to_mode_reg (Pmode, op1)); - if (target == 0 + if (optimize || target == 0 || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) + || !register_operand (target, tmode)) target = gen_reg_rtx (tmode); pat = GEN_FCN (icode) (target, op0, op1); if (! pat) @@ -14302,28 +16099,23 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, case IX86_BUILTIN_STOREHPS: case IX86_BUILTIN_STORELPS: - case IX86_BUILTIN_STOREHPD: - case IX86_BUILTIN_STORELPD: - icode = (fcode == IX86_BUILTIN_STOREHPS ? CODE_FOR_sse_movhps - : fcode == IX86_BUILTIN_STORELPS ? CODE_FOR_sse_movlps - : fcode == IX86_BUILTIN_STOREHPD ? CODE_FOR_sse2_movhpd - : CODE_FOR_sse2_movsd); + icode = (fcode == IX86_BUILTIN_STOREHPS ? CODE_FOR_sse_storehps + : CODE_FOR_sse_storelps); arg0 = TREE_VALUE (arglist); arg1 = TREE_VALUE (TREE_CHAIN (arglist)); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); - mode0 = insn_data[icode].operand[1].mode; - mode1 = insn_data[icode].operand[2].mode; + op0 = expand_normal (arg0); + op1 = expand_normal (arg1); + mode0 = insn_data[icode].operand[0].mode; + mode1 = insn_data[icode].operand[1].mode; op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); - if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); + op1 = force_reg (mode1, op1); - pat = GEN_FCN (icode) (op0, op0, op1); + pat = GEN_FCN (icode) (op0, op1); if (! pat) return 0; emit_insn (pat); - return 0; + return const0_rtx; case IX86_BUILTIN_MOVNTPS: return ix86_expand_store_builtin (CODE_FOR_sse_movntv4sf, arglist); @@ -14331,15 +16123,15 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, return ix86_expand_store_builtin (CODE_FOR_sse_movntdi, arglist); case IX86_BUILTIN_LDMXCSR: - op0 = expand_expr (TREE_VALUE (arglist), NULL_RTX, VOIDmode, 0); - target = assign_386_stack_local (SImode, 0); + op0 = expand_normal (TREE_VALUE (arglist)); + target = assign_386_stack_local (SImode, SLOT_TEMP); emit_move_insn (target, op0); - emit_insn (gen_ldmxcsr (target)); + emit_insn (gen_sse_ldmxcsr (target)); return 0; case IX86_BUILTIN_STMXCSR: - target = assign_386_stack_local (SImode, 0); - emit_insn (gen_stmxcsr (target)); + target = assign_386_stack_local (SImode, SLOT_TEMP); + emit_insn (gen_sse_stmxcsr (target)); return copy_to_mode_reg (SImode, target); case IX86_BUILTIN_SHUFPS: @@ -14350,9 +16142,9 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, arg0 = TREE_VALUE (arglist); arg1 = TREE_VALUE (TREE_CHAIN (arglist)); arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); - op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); + op0 = expand_normal (arg0); + op1 = expand_normal (arg1); + op2 = expand_normal (arg2); tmode = insn_data[icode].operand[0].mode; mode0 = insn_data[icode].operand[1].mode; mode1 = insn_data[icode].operand[2].mode; @@ -14360,7 +16152,8 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) op0 = copy_to_mode_reg (mode0, op0); - if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) + if ((optimize && !register_operand (op1, mode1)) + || !(*insn_data[icode].operand[2].predicate) (op1, mode1)) op1 = copy_to_mode_reg (mode1, op1); if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) { @@ -14368,7 +16161,7 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, error ("mask must be an immediate"); return gen_reg_rtx (tmode); } - if (target == 0 + if (optimize || target == 0 || GET_MODE (target) != tmode || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) target = gen_reg_rtx (tmode); @@ -14388,8 +16181,8 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, : CODE_FOR_mmx_pshufw); arg0 = TREE_VALUE (arglist); arg1 = TREE_VALUE (TREE_CHAIN (arglist)); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + op0 = expand_normal (arg0); + op1 = expand_normal (arg1); tmode = insn_data[icode].operand[0].mode; mode1 = insn_data[icode].operand[1].mode; mode2 = insn_data[icode].operand[2].mode; @@ -14412,14 +16205,111 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, emit_insn (pat); return target; + case IX86_BUILTIN_PSLLWI128: + icode = CODE_FOR_ashlv8hi3; + goto do_pshifti; + case IX86_BUILTIN_PSLLDI128: + icode = CODE_FOR_ashlv4si3; + goto do_pshifti; + case IX86_BUILTIN_PSLLQI128: + icode = CODE_FOR_ashlv2di3; + goto do_pshifti; + case IX86_BUILTIN_PSRAWI128: + icode = CODE_FOR_ashrv8hi3; + goto do_pshifti; + case IX86_BUILTIN_PSRADI128: + icode = CODE_FOR_ashrv4si3; + goto do_pshifti; + case IX86_BUILTIN_PSRLWI128: + icode = CODE_FOR_lshrv8hi3; + goto do_pshifti; + case IX86_BUILTIN_PSRLDI128: + icode = CODE_FOR_lshrv4si3; + goto do_pshifti; + case IX86_BUILTIN_PSRLQI128: + icode = CODE_FOR_lshrv2di3; + goto do_pshifti; + do_pshifti: + arg0 = TREE_VALUE (arglist); + arg1 = TREE_VALUE (TREE_CHAIN (arglist)); + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + + if (GET_CODE (op1) != CONST_INT) + { + error ("shift must be an immediate"); + return const0_rtx; + } + if (INTVAL (op1) < 0 || INTVAL (op1) > 255) + op1 = GEN_INT (255); + + tmode = insn_data[icode].operand[0].mode; + mode1 = insn_data[icode].operand[1].mode; + if (! (*insn_data[icode].operand[1].predicate) (op0, mode1)) + op0 = copy_to_reg (op0); + + target = gen_reg_rtx (tmode); + pat = GEN_FCN (icode) (target, op0, op1); + if (!pat) + return 0; + emit_insn (pat); + return target; + + case IX86_BUILTIN_PSLLW128: + icode = CODE_FOR_ashlv8hi3; + goto do_pshift; + case IX86_BUILTIN_PSLLD128: + icode = CODE_FOR_ashlv4si3; + goto do_pshift; + case IX86_BUILTIN_PSLLQ128: + icode = CODE_FOR_ashlv2di3; + goto do_pshift; + case IX86_BUILTIN_PSRAW128: + icode = CODE_FOR_ashrv8hi3; + goto do_pshift; + case IX86_BUILTIN_PSRAD128: + icode = CODE_FOR_ashrv4si3; + goto do_pshift; + case IX86_BUILTIN_PSRLW128: + icode = CODE_FOR_lshrv8hi3; + goto do_pshift; + case IX86_BUILTIN_PSRLD128: + icode = CODE_FOR_lshrv4si3; + goto do_pshift; + case IX86_BUILTIN_PSRLQ128: + icode = CODE_FOR_lshrv2di3; + goto do_pshift; + do_pshift: + arg0 = TREE_VALUE (arglist); + arg1 = TREE_VALUE (TREE_CHAIN (arglist)); + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + + tmode = insn_data[icode].operand[0].mode; + mode1 = insn_data[icode].operand[1].mode; + + if (! (*insn_data[icode].operand[1].predicate) (op0, mode1)) + op0 = copy_to_reg (op0); + + op1 = simplify_gen_subreg (TImode, op1, GET_MODE (op1), 0); + if (! (*insn_data[icode].operand[2].predicate) (op1, TImode)) + op1 = copy_to_reg (op1); + + target = gen_reg_rtx (tmode); + pat = GEN_FCN (icode) (target, op0, op1); + if (!pat) + return 0; + emit_insn (pat); + return target; + case IX86_BUILTIN_PSLLDQI128: case IX86_BUILTIN_PSRLDQI128: - icode = ( fcode == IX86_BUILTIN_PSLLDQI128 ? CODE_FOR_sse2_ashlti3 + icode = (fcode == IX86_BUILTIN_PSLLDQI128 ? CODE_FOR_sse2_ashlti3 : CODE_FOR_sse2_lshrti3); arg0 = TREE_VALUE (arglist); arg1 = TREE_VALUE (TREE_CHAIN (arglist)); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + op0 = expand_normal (arg0); + op1 = expand_normal (arg1); tmode = insn_data[icode].operand[0].mode; mode1 = insn_data[icode].operand[1].mode; mode2 = insn_data[icode].operand[2].mode; @@ -14435,169 +16325,99 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, return const0_rtx; } target = gen_reg_rtx (V2DImode); - pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, V2DImode, 0), op0, op1); + pat = GEN_FCN (icode) (simplify_gen_subreg (tmode, target, V2DImode, 0), + op0, op1); if (! pat) return 0; emit_insn (pat); return target; case IX86_BUILTIN_FEMMS: - emit_insn (gen_femms ()); + emit_insn (gen_mmx_femms ()); return NULL_RTX; case IX86_BUILTIN_PAVGUSB: - return ix86_expand_binop_builtin (CODE_FOR_pavgusb, arglist, target); + return ix86_expand_binop_builtin (CODE_FOR_mmx_uavgv8qi3, arglist, target); case IX86_BUILTIN_PF2ID: - return ix86_expand_unop_builtin (CODE_FOR_pf2id, arglist, target, 0); + return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2id, arglist, target, 0); case IX86_BUILTIN_PFACC: - return ix86_expand_binop_builtin (CODE_FOR_pfacc, arglist, target); + return ix86_expand_binop_builtin (CODE_FOR_mmx_haddv2sf3, arglist, target); case IX86_BUILTIN_PFADD: - return ix86_expand_binop_builtin (CODE_FOR_addv2sf3, arglist, target); + return ix86_expand_binop_builtin (CODE_FOR_mmx_addv2sf3, arglist, target); case IX86_BUILTIN_PFCMPEQ: - return ix86_expand_binop_builtin (CODE_FOR_eqv2sf3, arglist, target); + return ix86_expand_binop_builtin (CODE_FOR_mmx_eqv2sf3, arglist, target); case IX86_BUILTIN_PFCMPGE: - return ix86_expand_binop_builtin (CODE_FOR_gev2sf3, arglist, target); + return ix86_expand_binop_builtin (CODE_FOR_mmx_gev2sf3, arglist, target); case IX86_BUILTIN_PFCMPGT: - return ix86_expand_binop_builtin (CODE_FOR_gtv2sf3, arglist, target); + return ix86_expand_binop_builtin (CODE_FOR_mmx_gtv2sf3, arglist, target); case IX86_BUILTIN_PFMAX: - return ix86_expand_binop_builtin (CODE_FOR_pfmaxv2sf3, arglist, target); + return ix86_expand_binop_builtin (CODE_FOR_mmx_smaxv2sf3, arglist, target); case IX86_BUILTIN_PFMIN: - return ix86_expand_binop_builtin (CODE_FOR_pfminv2sf3, arglist, target); + return ix86_expand_binop_builtin (CODE_FOR_mmx_sminv2sf3, arglist, target); case IX86_BUILTIN_PFMUL: - return ix86_expand_binop_builtin (CODE_FOR_mulv2sf3, arglist, target); + return ix86_expand_binop_builtin (CODE_FOR_mmx_mulv2sf3, arglist, target); case IX86_BUILTIN_PFRCP: - return ix86_expand_unop_builtin (CODE_FOR_pfrcpv2sf2, arglist, target, 0); + return ix86_expand_unop_builtin (CODE_FOR_mmx_rcpv2sf2, arglist, target, 0); case IX86_BUILTIN_PFRCPIT1: - return ix86_expand_binop_builtin (CODE_FOR_pfrcpit1v2sf3, arglist, target); + return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit1v2sf3, arglist, target); case IX86_BUILTIN_PFRCPIT2: - return ix86_expand_binop_builtin (CODE_FOR_pfrcpit2v2sf3, arglist, target); + return ix86_expand_binop_builtin (CODE_FOR_mmx_rcpit2v2sf3, arglist, target); case IX86_BUILTIN_PFRSQIT1: - return ix86_expand_binop_builtin (CODE_FOR_pfrsqit1v2sf3, arglist, target); + return ix86_expand_binop_builtin (CODE_FOR_mmx_rsqit1v2sf3, arglist, target); case IX86_BUILTIN_PFRSQRT: - return ix86_expand_unop_builtin (CODE_FOR_pfrsqrtv2sf2, arglist, target, 0); + return ix86_expand_unop_builtin (CODE_FOR_mmx_rsqrtv2sf2, arglist, target, 0); case IX86_BUILTIN_PFSUB: - return ix86_expand_binop_builtin (CODE_FOR_subv2sf3, arglist, target); + return ix86_expand_binop_builtin (CODE_FOR_mmx_subv2sf3, arglist, target); case IX86_BUILTIN_PFSUBR: - return ix86_expand_binop_builtin (CODE_FOR_subrv2sf3, arglist, target); + return ix86_expand_binop_builtin (CODE_FOR_mmx_subrv2sf3, arglist, target); case IX86_BUILTIN_PI2FD: - return ix86_expand_unop_builtin (CODE_FOR_floatv2si2, arglist, target, 0); + return ix86_expand_unop_builtin (CODE_FOR_mmx_floatv2si2, arglist, target, 0); case IX86_BUILTIN_PMULHRW: - return ix86_expand_binop_builtin (CODE_FOR_pmulhrwv4hi3, arglist, target); + return ix86_expand_binop_builtin (CODE_FOR_mmx_pmulhrwv4hi3, arglist, target); case IX86_BUILTIN_PF2IW: - return ix86_expand_unop_builtin (CODE_FOR_pf2iw, arglist, target, 0); + return ix86_expand_unop_builtin (CODE_FOR_mmx_pf2iw, arglist, target, 0); case IX86_BUILTIN_PFNACC: - return ix86_expand_binop_builtin (CODE_FOR_pfnacc, arglist, target); + return ix86_expand_binop_builtin (CODE_FOR_mmx_hsubv2sf3, arglist, target); case IX86_BUILTIN_PFPNACC: - return ix86_expand_binop_builtin (CODE_FOR_pfpnacc, arglist, target); + return ix86_expand_binop_builtin (CODE_FOR_mmx_addsubv2sf3, arglist, target); case IX86_BUILTIN_PI2FW: - return ix86_expand_unop_builtin (CODE_FOR_pi2fw, arglist, target, 0); + return ix86_expand_unop_builtin (CODE_FOR_mmx_pi2fw, arglist, target, 0); case IX86_BUILTIN_PSWAPDSI: - return ix86_expand_unop_builtin (CODE_FOR_pswapdv2si2, arglist, target, 0); + return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2si2, arglist, target, 0); case IX86_BUILTIN_PSWAPDSF: - return ix86_expand_unop_builtin (CODE_FOR_pswapdv2sf2, arglist, target, 0); - - case IX86_BUILTIN_SSE_ZERO: - target = gen_reg_rtx (V4SFmode); - emit_insn (gen_sse_clrv4sf (target, CONST0_RTX (V4SFmode))); - return target; - - case IX86_BUILTIN_MMX_ZERO: - target = gen_reg_rtx (DImode); - emit_insn (gen_mmx_clrdi (target)); - return target; - - case IX86_BUILTIN_CLRTI: - target = gen_reg_rtx (V2DImode); - emit_insn (gen_sse2_clrti (simplify_gen_subreg (TImode, target, V2DImode, 0))); - return target; - + return ix86_expand_unop_builtin (CODE_FOR_mmx_pswapdv2sf2, arglist, target, 0); case IX86_BUILTIN_SQRTSD: - return ix86_expand_unop1_builtin (CODE_FOR_vmsqrtv2df2, arglist, target); - case IX86_BUILTIN_LOADAPD: - return ix86_expand_unop_builtin (CODE_FOR_sse2_movapd, arglist, target, 1); + return ix86_expand_unop1_builtin (CODE_FOR_sse2_vmsqrtv2df2, arglist, target); case IX86_BUILTIN_LOADUPD: return ix86_expand_unop_builtin (CODE_FOR_sse2_movupd, arglist, target, 1); - - case IX86_BUILTIN_STOREAPD: - return ix86_expand_store_builtin (CODE_FOR_sse2_movapd, arglist); case IX86_BUILTIN_STOREUPD: return ix86_expand_store_builtin (CODE_FOR_sse2_movupd, arglist); - case IX86_BUILTIN_LOADSD: - return ix86_expand_unop_builtin (CODE_FOR_sse2_loadsd, arglist, target, 1); - - case IX86_BUILTIN_STORESD: - return ix86_expand_store_builtin (CODE_FOR_sse2_storesd, arglist); - - case IX86_BUILTIN_SETPD1: - target = assign_386_stack_local (DFmode, 0); - arg0 = TREE_VALUE (arglist); - emit_move_insn (adjust_address (target, DFmode, 0), - expand_expr (arg0, NULL_RTX, VOIDmode, 0)); - op0 = gen_reg_rtx (V2DFmode); - emit_insn (gen_sse2_loadsd (op0, adjust_address (target, V2DFmode, 0))); - emit_insn (gen_sse2_shufpd (op0, op0, op0, GEN_INT (0))); - return op0; - - case IX86_BUILTIN_SETPD: - target = assign_386_stack_local (V2DFmode, 0); - arg0 = TREE_VALUE (arglist); - arg1 = TREE_VALUE (TREE_CHAIN (arglist)); - emit_move_insn (adjust_address (target, DFmode, 0), - expand_expr (arg0, NULL_RTX, VOIDmode, 0)); - emit_move_insn (adjust_address (target, DFmode, 8), - expand_expr (arg1, NULL_RTX, VOIDmode, 0)); - op0 = gen_reg_rtx (V2DFmode); - emit_insn (gen_sse2_movapd (op0, target)); - return op0; - - case IX86_BUILTIN_LOADRPD: - target = ix86_expand_unop_builtin (CODE_FOR_sse2_movapd, arglist, - gen_reg_rtx (V2DFmode), 1); - emit_insn (gen_sse2_shufpd (target, target, target, GEN_INT (1))); - return target; - - case IX86_BUILTIN_LOADPD1: - target = ix86_expand_unop_builtin (CODE_FOR_sse2_loadsd, arglist, - gen_reg_rtx (V2DFmode), 1); - emit_insn (gen_sse2_shufpd (target, target, target, const0_rtx)); - return target; - - case IX86_BUILTIN_STOREPD1: - return ix86_expand_store_builtin (CODE_FOR_sse2_movapd, arglist); - case IX86_BUILTIN_STORERPD: - return ix86_expand_store_builtin (CODE_FOR_sse2_movapd, arglist); - - case IX86_BUILTIN_CLRPD: - target = gen_reg_rtx (V2DFmode); - emit_insn (gen_sse_clrv2df (target)); - return target; - case IX86_BUILTIN_MFENCE: emit_insn (gen_sse2_mfence ()); return 0; @@ -14607,7 +16427,7 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, case IX86_BUILTIN_CLFLUSH: arg0 = TREE_VALUE (arglist); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); + op0 = expand_normal (arg0); icode = CODE_FOR_sse2_clflush; if (! (*insn_data[icode].operand[0].predicate) (op0, Pmode)) op0 = copy_to_mode_reg (Pmode, op0); @@ -14622,54 +16442,63 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, case IX86_BUILTIN_MOVNTI: return ix86_expand_store_builtin (CODE_FOR_sse2_movntsi, arglist); - case IX86_BUILTIN_LOADDQA: - return ix86_expand_unop_builtin (CODE_FOR_sse2_movdqa, arglist, target, 1); case IX86_BUILTIN_LOADDQU: return ix86_expand_unop_builtin (CODE_FOR_sse2_movdqu, arglist, target, 1); - case IX86_BUILTIN_LOADD: - return ix86_expand_unop_builtin (CODE_FOR_sse2_loadd, arglist, target, 1); - - case IX86_BUILTIN_STOREDQA: - return ix86_expand_store_builtin (CODE_FOR_sse2_movdqa, arglist); case IX86_BUILTIN_STOREDQU: return ix86_expand_store_builtin (CODE_FOR_sse2_movdqu, arglist); - case IX86_BUILTIN_STORED: - return ix86_expand_store_builtin (CODE_FOR_sse2_stored, arglist); case IX86_BUILTIN_MONITOR: arg0 = TREE_VALUE (arglist); arg1 = TREE_VALUE (TREE_CHAIN (arglist)); arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); - op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); + op0 = expand_normal (arg0); + op1 = expand_normal (arg1); + op2 = expand_normal (arg2); if (!REG_P (op0)) - op0 = copy_to_mode_reg (SImode, op0); + op0 = copy_to_mode_reg (Pmode, op0); if (!REG_P (op1)) op1 = copy_to_mode_reg (SImode, op1); if (!REG_P (op2)) op2 = copy_to_mode_reg (SImode, op2); - emit_insn (gen_monitor (op0, op1, op2)); + if (!TARGET_64BIT) + emit_insn (gen_sse3_monitor (op0, op1, op2)); + else + emit_insn (gen_sse3_monitor64 (op0, op1, op2)); return 0; case IX86_BUILTIN_MWAIT: arg0 = TREE_VALUE (arglist); arg1 = TREE_VALUE (TREE_CHAIN (arglist)); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + op0 = expand_normal (arg0); + op1 = expand_normal (arg1); if (!REG_P (op0)) op0 = copy_to_mode_reg (SImode, op0); if (!REG_P (op1)) op1 = copy_to_mode_reg (SImode, op1); - emit_insn (gen_mwait (op0, op1)); + emit_insn (gen_sse3_mwait (op0, op1)); return 0; - case IX86_BUILTIN_LOADDDUP: - return ix86_expand_unop_builtin (CODE_FOR_loadddup, arglist, target, 1); - case IX86_BUILTIN_LDDQU: - return ix86_expand_unop_builtin (CODE_FOR_lddqu, arglist, target, - 1); + return ix86_expand_unop_builtin (CODE_FOR_sse3_lddqu, arglist, + target, 1); + + case IX86_BUILTIN_VEC_INIT_V2SI: + case IX86_BUILTIN_VEC_INIT_V4HI: + case IX86_BUILTIN_VEC_INIT_V8QI: + return ix86_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target); + + case IX86_BUILTIN_VEC_EXT_V2DF: + case IX86_BUILTIN_VEC_EXT_V2DI: + case IX86_BUILTIN_VEC_EXT_V4SF: + case IX86_BUILTIN_VEC_EXT_V4SI: + case IX86_BUILTIN_VEC_EXT_V8HI: + case IX86_BUILTIN_VEC_EXT_V2SI: + case IX86_BUILTIN_VEC_EXT_V4HI: + return ix86_expand_vec_ext_builtin (arglist, target); + + case IX86_BUILTIN_VEC_SET_V8HI: + case IX86_BUILTIN_VEC_SET_V4HI: + return ix86_expand_vec_set_builtin (arglist); default: break; @@ -14679,14 +16508,10 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, if (d->code == fcode) { /* Compares are treated specially. */ - if (d->icode == CODE_FOR_maskcmpv4sf3 - || d->icode == CODE_FOR_vmmaskcmpv4sf3 - || d->icode == CODE_FOR_maskncmpv4sf3 - || d->icode == CODE_FOR_vmmaskncmpv4sf3 - || d->icode == CODE_FOR_maskcmpv2df3 - || d->icode == CODE_FOR_vmmaskcmpv2df3 - || d->icode == CODE_FOR_maskncmpv2df3 - || d->icode == CODE_FOR_vmmaskncmpv2df3) + if (d->icode == CODE_FOR_sse_maskcmpv4sf3 + || d->icode == CODE_FOR_sse_vmmaskcmpv4sf3 + || d->icode == CODE_FOR_sse2_maskcmpv2df3 + || d->icode == CODE_FOR_sse2_vmmaskcmpv2df3) return ix86_expand_sse_compare (d, arglist, target); return ix86_expand_binop_builtin (d->icode, arglist, target); @@ -14700,8 +16525,7 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, if (d->code == fcode) return ix86_expand_sse_comi (d, arglist, target); - /* @@@ Should really do something sensible here. */ - return 0; + gcc_unreachable (); } /* Store OPERAND to the memory after reload is completed. This means @@ -14710,8 +16534,8 @@ rtx ix86_force_to_memory (enum machine_mode mode, rtx operand) { rtx result; - if (!reload_completed) - abort (); + + gcc_assert (reload_completed); if (TARGET_RED_ZONE) { result = gen_rtx_MEM (mode, @@ -14737,7 +16561,7 @@ ix86_force_to_memory (enum machine_mode mode, rtx operand) operand)); break; default: - abort (); + gcc_unreachable (); } result = gen_rtx_MEM (mode, stack_pointer_rtx); } @@ -14764,9 +16588,8 @@ ix86_force_to_memory (enum machine_mode mode, rtx operand) } break; case HImode: - /* It is better to store HImodes as SImodes. */ - if (!TARGET_PARTIAL_REG_STALL) - operand = gen_lowpart (SImode, operand); + /* Store HImodes as SImodes. */ + operand = gen_lowpart (SImode, operand); /* FALLTHRU */ case SImode: emit_insn ( @@ -14777,7 +16600,7 @@ ix86_force_to_memory (enum machine_mode mode, rtx operand) operand)); break; default: - abort (); + gcc_unreachable (); } result = gen_rtx_MEM (mode, stack_pointer_rtx); } @@ -14794,8 +16617,6 @@ ix86_free_from_memory (enum machine_mode mode) if (mode == DImode || TARGET_64BIT) size = 8; - else if (mode == HImode && TARGET_PARTIAL_REG_STALL) - size = 2; else size = 4; /* Use LEA to deallocate stack space. In peephole2 it will be converted @@ -14813,34 +16634,99 @@ ix86_free_from_memory (enum machine_mode mode) enum reg_class ix86_preferred_reload_class (rtx x, enum reg_class class) { - if (GET_CODE (x) == CONST_VECTOR && x != CONST0_RTX (GET_MODE (x))) + enum machine_mode mode = GET_MODE (x); + + /* We're only allowed to return a subclass of CLASS. Many of the + following checks fail for NO_REGS, so eliminate that early. */ + if (class == NO_REGS) return NO_REGS; + + /* All classes can load zeros. */ + if (x == CONST0_RTX (mode)) + return class; + + /* Force constants into memory if we are loading a (nonzero) constant into + an MMX or SSE register. This is because there are no MMX/SSE instructions + to load from a constant. */ + if (CONSTANT_P (x) + && (MAYBE_MMX_CLASS_P (class) || MAYBE_SSE_CLASS_P (class))) + return NO_REGS; + + /* Prefer SSE regs only, if we can use them for math. */ + if (TARGET_SSE_MATH && !TARGET_MIX_SSE_I387 && SSE_FLOAT_MODE_P (mode)) + return SSE_CLASS_P (class) ? class : NO_REGS; + + /* Floating-point constants need more complex checks. */ if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != VOIDmode) { - /* SSE can't load any constant directly yet. */ - if (SSE_CLASS_P (class)) - return NO_REGS; - /* Floats can load 0 and 1. */ - if (MAYBE_FLOAT_CLASS_P (class) && standard_80387_constant_p (x)) + /* General regs can load everything. */ + if (reg_class_subset_p (class, GENERAL_REGS)) + return class; + + /* Floats can load 0 and 1 plus some others. Note that we eliminated + zero above. We only want to wind up preferring 80387 registers if + we plan on doing computation with them. */ + if (TARGET_80387 + && standard_80387_constant_p (x)) { - /* Limit class to non-SSE. Use GENERAL_REGS if possible. */ - if (MAYBE_SSE_CLASS_P (class)) - return (reg_class_subset_p (class, GENERAL_REGS) - ? GENERAL_REGS : FLOAT_REGS); - else + /* Limit class to non-sse. */ + if (class == FLOAT_SSE_REGS) + return FLOAT_REGS; + if (class == FP_TOP_SSE_REGS) + return FP_TOP_REG; + if (class == FP_SECOND_SSE_REGS) + return FP_SECOND_REG; + if (class == FLOAT_INT_REGS || class == FLOAT_REGS) return class; } - /* General regs can load everything. */ - if (reg_class_subset_p (class, GENERAL_REGS)) - return GENERAL_REGS; - /* In case we haven't resolved FLOAT or SSE yet, give up. */ - if (MAYBE_FLOAT_CLASS_P (class) || MAYBE_SSE_CLASS_P (class)) - return NO_REGS; + + return NO_REGS; } - if (MAYBE_MMX_CLASS_P (class) && CONSTANT_P (x)) - return NO_REGS; - if (GET_MODE (x) == QImode && ! reg_class_subset_p (class, Q_REGS)) - return Q_REGS; + + /* Generally when we see PLUS here, it's the function invariant + (plus soft-fp const_int). Which can only be computed into general + regs. */ + if (GET_CODE (x) == PLUS) + return reg_class_subset_p (class, GENERAL_REGS) ? class : NO_REGS; + + /* QImode constants are easy to load, but non-constant QImode data + must go into Q_REGS. */ + if (GET_MODE (x) == QImode && !CONSTANT_P (x)) + { + if (reg_class_subset_p (class, Q_REGS)) + return class; + if (reg_class_subset_p (Q_REGS, class)) + return Q_REGS; + return NO_REGS; + } + + return class; +} + +/* Discourage putting floating-point values in SSE registers unless + SSE math is being used, and likewise for the 387 registers. */ +enum reg_class +ix86_preferred_output_reload_class (rtx x, enum reg_class class) +{ + enum machine_mode mode = GET_MODE (x); + + /* Restrict the output reload class to the register bank that we are doing + math on. If we would like not to return a subset of CLASS, reject this + alternative: if reload cannot do this, it will still use its choice. */ + mode = GET_MODE (x); + if (TARGET_SSE_MATH && SSE_FLOAT_MODE_P (mode)) + return MAYBE_SSE_CLASS_P (class) ? SSE_REGS : NO_REGS; + + if (TARGET_80387 && SCALAR_FLOAT_MODE_P (mode)) + { + if (class == FP_TOP_SSE_REGS) + return FP_TOP_REG; + else if (class == FP_SECOND_SSE_REGS) + return FP_SECOND_REG; + else + return FLOAT_CLASS_P (class) ? class : NO_REGS; + } + return class; } @@ -14854,6 +16740,7 @@ ix86_preferred_reload_class (rtx x, enum reg_class class) When STRICT is false, we are being called from REGISTER_MOVE_COST, so do not enforce these sanity checks. */ + int ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2, enum machine_mode mode, int strict) @@ -14865,23 +16752,86 @@ ix86_secondary_memory_needed (enum reg_class class1, enum reg_class class2, || MAYBE_MMX_CLASS_P (class1) != MMX_CLASS_P (class1) || MAYBE_MMX_CLASS_P (class2) != MMX_CLASS_P (class2)) { - if (strict) - abort (); - else - return 1; + gcc_assert (!strict); + return true; + } + + if (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2)) + return true; + + /* ??? This is a lie. We do have moves between mmx/general, and for + mmx/sse2. But by saying we need secondary memory we discourage the + register allocator from using the mmx registers unless needed. */ + if (MMX_CLASS_P (class1) != MMX_CLASS_P (class2)) + return true; + + if (SSE_CLASS_P (class1) != SSE_CLASS_P (class2)) + { + /* SSE1 doesn't have any direct moves from other classes. */ + if (!TARGET_SSE2) + return true; + + /* If the target says that inter-unit moves are more expensive + than moving through memory, then don't generate them. */ + if (!TARGET_INTER_UNIT_MOVES && !optimize_size) + return true; + + /* Between SSE and general, we have moves no larger than word size. */ + if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) + return true; + + /* ??? For the cost of one register reformat penalty, we could use + the same instructions to move SFmode and DFmode data, but the + relevant move patterns don't support those alternatives. */ + if (mode == SFmode || mode == DFmode) + return true; + } + + return false; +} + +/* Return true if the registers in CLASS cannot represent the change from + modes FROM to TO. */ + +bool +ix86_cannot_change_mode_class (enum machine_mode from, enum machine_mode to, + enum reg_class class) +{ + if (from == to) + return false; + + /* x87 registers can't do subreg at all, as all values are reformatted + to extended precision. */ + if (MAYBE_FLOAT_CLASS_P (class)) + return true; + + if (MAYBE_SSE_CLASS_P (class) || MAYBE_MMX_CLASS_P (class)) + { + /* Vector registers do not support QI or HImode loads. If we don't + disallow a change to these modes, reload will assume it's ok to + drop the subreg from (subreg:SI (reg:HI 100) 0). This affects + the vec_dupv4hi pattern. */ + if (GET_MODE_SIZE (from) < 4) + return true; + + /* Vector registers do not support subreg with nonzero offsets, which + are otherwise valid for integer registers. Since we can't see + whether we have a nonzero offset from here, prohibit all + nonparadoxical subregs changing size. */ + if (GET_MODE_SIZE (to) < GET_MODE_SIZE (from)) + return true; } - return (FLOAT_CLASS_P (class1) != FLOAT_CLASS_P (class2) - || ((SSE_CLASS_P (class1) != SSE_CLASS_P (class2) - || MMX_CLASS_P (class1) != MMX_CLASS_P (class2)) - && ((mode != SImode && (mode != DImode || !TARGET_64BIT)) - || (!TARGET_INTER_UNIT_MOVES && !optimize_size)))); + + return false; } + /* Return the cost of moving data from a register in class CLASS1 to one in class CLASS2. It is not required that the cost always equal 2 when FROM is the same as TO; on some machines it is expensive to move between registers if they are not general registers. */ + int ix86_register_move_cost (enum machine_mode mode, enum reg_class class1, enum reg_class class2) @@ -14928,7 +16878,8 @@ ix86_register_move_cost (enum machine_mode mode, enum reg_class class1, } /* Return 1 if hard register REGNO can hold a value of machine-mode MODE. */ -int + +bool ix86_hard_regno_mode_ok (int regno, enum machine_mode mode) { /* Flags and only flags can only hold CCmode values. */ @@ -14942,15 +16893,9 @@ ix86_hard_regno_mode_ok (int regno, enum machine_mode mode) return VALID_FP_MODE_P (mode); if (SSE_REGNO_P (regno)) { - /* HACK! We didn't change all of the constraints for SSE1 for the - scalar modes on the branch. Fortunately, they're not required - for ABI compatibility. */ - if (!TARGET_SSE2 && !VECTOR_MODE_P (mode)) - return VALID_SSE_REG_MODE (mode); - /* We implement the move patterns for all vector modes into and - out of SSE registers, even when no operation instructions - are available. */ + out of SSE registers, even when no operation instructions + are available. */ return (VALID_SSE_REG_MODE (mode) || VALID_SSE2_REG_MODE (mode) || VALID_MMX_REG_MODE (mode) @@ -14959,20 +16904,98 @@ ix86_hard_regno_mode_ok (int regno, enum machine_mode mode) if (MMX_REGNO_P (regno)) { /* We implement the move patterns for 3DNOW modes even in MMX mode, - so if the register is available at all, then we can move data of - the given mode into or out of it. */ + so if the register is available at all, then we can move data of + the given mode into or out of it. */ return (VALID_MMX_REG_MODE (mode) || VALID_MMX_REG_MODE_3DNOW (mode)); } - /* We handle both integer and floats in the general purpose registers. - In future we should be able to handle vector modes as well. */ - if (!VALID_INT_MODE_P (mode) && !VALID_FP_MODE_P (mode)) - return 0; - /* Take care for QImode values - they can be in non-QI regs, but then - they do cause partial register stalls. */ - if (regno < 4 || mode != QImode || TARGET_64BIT) + + if (mode == QImode) + { + /* Take care for QImode values - they can be in non-QI regs, + but then they do cause partial register stalls. */ + if (regno < 4 || TARGET_64BIT) + return 1; + if (!TARGET_PARTIAL_REG_STALL) + return 1; + return reload_in_progress || reload_completed; + } + /* We handle both integer and floats in the general purpose registers. */ + else if (VALID_INT_MODE_P (mode)) + return 1; + else if (VALID_FP_MODE_P (mode)) return 1; - return reload_in_progress || reload_completed || !TARGET_PARTIAL_REG_STALL; + /* Lots of MMX code casts 8 byte vector modes to DImode. If we then go + on to use that value in smaller contexts, this can easily force a + pseudo to be allocated to GENERAL_REGS. Since this is no worse than + supporting DImode, allow it. */ + else if (VALID_MMX_REG_MODE_3DNOW (mode) || VALID_MMX_REG_MODE (mode)) + return 1; + + return 0; +} + +/* A subroutine of ix86_modes_tieable_p. Return true if MODE is a + tieable integer mode. */ + +static bool +ix86_tieable_integer_mode_p (enum machine_mode mode) +{ + switch (mode) + { + case HImode: + case SImode: + return true; + + case QImode: + return TARGET_64BIT || !TARGET_PARTIAL_REG_STALL; + + case DImode: + return TARGET_64BIT; + + default: + return false; + } +} + +/* Return true if MODE1 is accessible in a register that can hold MODE2 + without copying. That is, all register classes that can hold MODE2 + can also hold MODE1. */ + +bool +ix86_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2) +{ + if (mode1 == mode2) + return true; + + if (ix86_tieable_integer_mode_p (mode1) + && ix86_tieable_integer_mode_p (mode2)) + return true; + + /* MODE2 being XFmode implies fp stack or general regs, which means we + can tie any smaller floating point modes to it. Note that we do not + tie this with TFmode. */ + if (mode2 == XFmode) + return mode1 == SFmode || mode1 == DFmode; + + /* MODE2 being DFmode implies fp stack, general or sse regs, which means + that we can tie it with SFmode. */ + if (mode2 == DFmode) + return mode1 == SFmode; + + /* If MODE2 is only appropriate for an SSE register, then tie with + any other mode acceptable to SSE registers. */ + if (GET_MODE_SIZE (mode2) >= 8 + && ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2)) + return ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1); + + /* If MODE2 is appropriate for an MMX (or SSE) register, then tie + with any other mode acceptable to MMX registers. */ + if (GET_MODE_SIZE (mode2) == 8 + && ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode2)) + return ix86_hard_regno_mode_ok (FIRST_MMX_REG, mode1); + + return false; } /* Return the cost of moving data of mode M between a @@ -15080,9 +17103,9 @@ ix86_rtx_costs (rtx x, int code, int outer_code, int *total) case CONST: case LABEL_REF: case SYMBOL_REF: - if (TARGET_64BIT && !x86_64_sign_extended_value (x)) + if (TARGET_64BIT && !x86_64_immediate_operand (x, VOIDmode)) *total = 3; - else if (TARGET_64BIT && !x86_64_zero_extended_value (x)) + else if (TARGET_64BIT && !x86_64_zext_immediate_operand (x, VOIDmode)) *total = 2; else if (flag_pic && SYMBOLIC_CONST (x) && (!TARGET_64BIT @@ -15124,13 +17147,13 @@ ix86_rtx_costs (rtx x, int code, int outer_code, int *total) && GET_MODE (XEXP (x, 0)) == SImode) *total = 1; else if (TARGET_ZERO_EXTEND_WITH_AND) - *total = COSTS_N_INSNS (ix86_cost->add); + *total = ix86_cost->add; else - *total = COSTS_N_INSNS (ix86_cost->movzx); + *total = ix86_cost->movzx; return false; case SIGN_EXTEND: - *total = COSTS_N_INSNS (ix86_cost->movsx); + *total = ix86_cost->movsx; return false; case ASHIFT: @@ -15140,14 +17163,13 @@ ix86_rtx_costs (rtx x, int code, int outer_code, int *total) HOST_WIDE_INT value = INTVAL (XEXP (x, 1)); if (value == 1) { - *total = COSTS_N_INSNS (ix86_cost->add); + *total = ix86_cost->add; return false; } if ((value == 2 || value == 3) - && !TARGET_DECOMPOSE_LEA && ix86_cost->lea <= ix86_cost->shift_const) { - *total = COSTS_N_INSNS (ix86_cost->lea); + *total = ix86_cost->lea; return false; } } @@ -15162,64 +17184,92 @@ ix86_rtx_costs (rtx x, int code, int outer_code, int *total) if (GET_CODE (XEXP (x, 1)) == CONST_INT) { if (INTVAL (XEXP (x, 1)) > 32) - *total = COSTS_N_INSNS(ix86_cost->shift_const + 2); + *total = ix86_cost->shift_const + COSTS_N_INSNS (2); else - *total = COSTS_N_INSNS(ix86_cost->shift_const * 2); + *total = ix86_cost->shift_const * 2; } else { if (GET_CODE (XEXP (x, 1)) == AND) - *total = COSTS_N_INSNS(ix86_cost->shift_var * 2); + *total = ix86_cost->shift_var * 2; else - *total = COSTS_N_INSNS(ix86_cost->shift_var * 6 + 2); + *total = ix86_cost->shift_var * 6 + COSTS_N_INSNS (2); } } else { if (GET_CODE (XEXP (x, 1)) == CONST_INT) - *total = COSTS_N_INSNS (ix86_cost->shift_const); + *total = ix86_cost->shift_const; else - *total = COSTS_N_INSNS (ix86_cost->shift_var); + *total = ix86_cost->shift_var; } return false; case MULT: if (FLOAT_MODE_P (mode)) - *total = COSTS_N_INSNS (ix86_cost->fmul); - else if (GET_CODE (XEXP (x, 1)) == CONST_INT) { - unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1)); - int nbits; - - for (nbits = 0; value != 0; value >>= 1) - nbits++; - - *total = COSTS_N_INSNS (ix86_cost->mult_init[MODE_INDEX (mode)] - + nbits * ix86_cost->mult_bit); + *total = ix86_cost->fmul; + return false; } else { - /* This is arbitrary */ - *total = COSTS_N_INSNS (ix86_cost->mult_init[MODE_INDEX (mode)] - + 7 * ix86_cost->mult_bit); + rtx op0 = XEXP (x, 0); + rtx op1 = XEXP (x, 1); + int nbits; + if (GET_CODE (XEXP (x, 1)) == CONST_INT) + { + unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1)); + for (nbits = 0; value != 0; value &= value - 1) + nbits++; + } + else + /* This is arbitrary. */ + nbits = 7; + + /* Compute costs correctly for widening multiplication. */ + if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op1) == ZERO_EXTEND) + && GET_MODE_SIZE (GET_MODE (XEXP (op0, 0))) * 2 + == GET_MODE_SIZE (mode)) + { + int is_mulwiden = 0; + enum machine_mode inner_mode = GET_MODE (op0); + + if (GET_CODE (op0) == GET_CODE (op1)) + is_mulwiden = 1, op1 = XEXP (op1, 0); + else if (GET_CODE (op1) == CONST_INT) + { + if (GET_CODE (op0) == SIGN_EXTEND) + is_mulwiden = trunc_int_for_mode (INTVAL (op1), inner_mode) + == INTVAL (op1); + else + is_mulwiden = !(INTVAL (op1) & ~GET_MODE_MASK (inner_mode)); + } + + if (is_mulwiden) + op0 = XEXP (op0, 0), mode = GET_MODE (op0); + } + + *total = (ix86_cost->mult_init[MODE_INDEX (mode)] + + nbits * ix86_cost->mult_bit + + rtx_cost (op0, outer_code) + rtx_cost (op1, outer_code)); + + return true; } - return false; case DIV: case UDIV: case MOD: case UMOD: if (FLOAT_MODE_P (mode)) - *total = COSTS_N_INSNS (ix86_cost->fdiv); + *total = ix86_cost->fdiv; else - *total = COSTS_N_INSNS (ix86_cost->divide[MODE_INDEX (mode)]); + *total = ix86_cost->divide[MODE_INDEX (mode)]; return false; case PLUS: if (FLOAT_MODE_P (mode)) - *total = COSTS_N_INSNS (ix86_cost->fadd); - else if (!TARGET_DECOMPOSE_LEA - && GET_MODE_CLASS (mode) == MODE_INT + *total = ix86_cost->fadd; + else if (GET_MODE_CLASS (mode) == MODE_INT && GET_MODE_BITSIZE (mode) <= GET_MODE_BITSIZE (Pmode)) { if (GET_CODE (XEXP (x, 0)) == PLUS @@ -15230,7 +17280,7 @@ ix86_rtx_costs (rtx x, int code, int outer_code, int *total) HOST_WIDE_INT val = INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)); if (val == 2 || val == 4 || val == 8) { - *total = COSTS_N_INSNS (ix86_cost->lea); + *total = ix86_cost->lea; *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code); *total += rtx_cost (XEXP (XEXP (XEXP (x, 0), 0), 0), outer_code); @@ -15244,7 +17294,7 @@ ix86_rtx_costs (rtx x, int code, int outer_code, int *total) HOST_WIDE_INT val = INTVAL (XEXP (XEXP (x, 0), 1)); if (val == 2 || val == 4 || val == 8) { - *total = COSTS_N_INSNS (ix86_cost->lea); + *total = ix86_cost->lea; *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code); *total += rtx_cost (XEXP (x, 1), outer_code); return true; @@ -15252,7 +17302,7 @@ ix86_rtx_costs (rtx x, int code, int outer_code, int *total) } else if (GET_CODE (XEXP (x, 0)) == PLUS) { - *total = COSTS_N_INSNS (ix86_cost->lea); + *total = ix86_cost->lea; *total += rtx_cost (XEXP (XEXP (x, 0), 0), outer_code); *total += rtx_cost (XEXP (XEXP (x, 0), 1), outer_code); *total += rtx_cost (XEXP (x, 1), outer_code); @@ -15264,7 +17314,7 @@ ix86_rtx_costs (rtx x, int code, int outer_code, int *total) case MINUS: if (FLOAT_MODE_P (mode)) { - *total = COSTS_N_INSNS (ix86_cost->fadd); + *total = ix86_cost->fadd; return false; } /* FALLTHRU */ @@ -15274,7 +17324,7 @@ ix86_rtx_costs (rtx x, int code, int outer_code, int *total) case XOR: if (!TARGET_64BIT && mode == DImode) { - *total = (COSTS_N_INSNS (ix86_cost->add) * 2 + *total = (ix86_cost->add * 2 + (rtx_cost (XEXP (x, 0), outer_code) << (GET_MODE (XEXP (x, 0)) != DImode)) + (rtx_cost (XEXP (x, 1), outer_code) @@ -15286,33 +17336,63 @@ ix86_rtx_costs (rtx x, int code, int outer_code, int *total) case NEG: if (FLOAT_MODE_P (mode)) { - *total = COSTS_N_INSNS (ix86_cost->fchs); + *total = ix86_cost->fchs; return false; } /* FALLTHRU */ case NOT: if (!TARGET_64BIT && mode == DImode) - *total = COSTS_N_INSNS (ix86_cost->add * 2); + *total = ix86_cost->add * 2; else - *total = COSTS_N_INSNS (ix86_cost->add); + *total = ix86_cost->add; + return false; + + case COMPARE: + if (GET_CODE (XEXP (x, 0)) == ZERO_EXTRACT + && XEXP (XEXP (x, 0), 1) == const1_rtx + && GET_CODE (XEXP (XEXP (x, 0), 2)) == CONST_INT + && XEXP (x, 1) == const0_rtx) + { + /* This kind of construct is implemented using test[bwl]. + Treat it as if we had an AND. */ + *total = (ix86_cost->add + + rtx_cost (XEXP (XEXP (x, 0), 0), outer_code) + + rtx_cost (const1_rtx, outer_code)); + return true; + } return false; case FLOAT_EXTEND: if (!TARGET_SSE_MATH || mode == XFmode || (mode == DFmode && !TARGET_SSE2)) - *total = 0; + /* For standard 80387 constants, raise the cost to prevent + compress_float_constant() to generate load from memory. */ + switch (standard_80387_constant_p (XEXP (x, 0))) + { + case -1: + case 0: + *total = 0; + break; + case 1: /* 0.0 */ + *total = 1; + break; + default: + *total = (x86_ext_80387_constants & TUNEMASK + || optimize_size + ? 1 : 0); + } return false; case ABS: if (FLOAT_MODE_P (mode)) - *total = COSTS_N_INSNS (ix86_cost->fabs); + *total = ix86_cost->fabs; return false; case SQRT: if (FLOAT_MODE_P (mode)) - *total = COSTS_N_INSNS (ix86_cost->fsqrt); + *total = ix86_cost->fsqrt; return false; case UNSPEC: @@ -15325,17 +17405,6 @@ ix86_rtx_costs (rtx x, int code, int outer_code, int *total) } } -#if defined (DO_GLOBAL_CTORS_BODY) && defined (HAS_INIT_SECTION) -static void -ix86_svr3_asm_out_constructor (rtx symbol, int priority ATTRIBUTE_UNUSED) -{ - init_section (); - fputs ("\tpushl $", asm_out_file); - assemble_name (asm_out_file, XSTR (symbol, 0)); - fputc ('\n', asm_out_file); -} -#endif - #if TARGET_MACHO static int current_machopic_label_num; @@ -15350,6 +17419,9 @@ machopic_output_stub (FILE *file, const char *symb, const char *stub) char *binder_name, *symbol_name, lazy_ptr_name[32]; int label = ++current_machopic_label_num; + /* For 64-bit we shouldn't get here. */ + gcc_assert (!TARGET_64BIT); + /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ symb = (*targetm.strip_name_encoding) (symb); @@ -15364,39 +17436,46 @@ machopic_output_stub (FILE *file, const char *symb, const char *stub) sprintf (lazy_ptr_name, "L%d$lz", label); if (MACHOPIC_PURE) - machopic_picsymbol_stub_section (); + switch_to_section (darwin_sections[machopic_picsymbol_stub_section]); else - machopic_symbol_stub_section (); + switch_to_section (darwin_sections[machopic_symbol_stub_section]); fprintf (file, "%s:\n", stub); fprintf (file, "\t.indirect_symbol %s\n", symbol_name); if (MACHOPIC_PURE) { - fprintf (file, "\tcall LPC$%d\nLPC$%d:\tpopl %%eax\n", label, label); - fprintf (file, "\tmovl %s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label); - fprintf (file, "\tjmp %%edx\n"); + fprintf (file, "\tcall\tLPC$%d\nLPC$%d:\tpopl\t%%eax\n", label, label); + fprintf (file, "\tmovl\t%s-LPC$%d(%%eax),%%edx\n", lazy_ptr_name, label); + fprintf (file, "\tjmp\t*%%edx\n"); } else - fprintf (file, "\tjmp *%s\n", lazy_ptr_name); + fprintf (file, "\tjmp\t*%s\n", lazy_ptr_name); fprintf (file, "%s:\n", binder_name); if (MACHOPIC_PURE) { - fprintf (file, "\tlea %s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label); - fprintf (file, "\tpushl %%eax\n"); + fprintf (file, "\tlea\t%s-LPC$%d(%%eax),%%eax\n", lazy_ptr_name, label); + fprintf (file, "\tpushl\t%%eax\n"); } else - fprintf (file, "\t pushl $%s\n", lazy_ptr_name); + fprintf (file, "\tpushl\t$%s\n", lazy_ptr_name); - fprintf (file, "\tjmp dyld_stub_binding_helper\n"); + fprintf (file, "\tjmp\tdyld_stub_binding_helper\n"); - machopic_lazy_symbol_ptr_section (); + switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]); fprintf (file, "%s:\n", lazy_ptr_name); fprintf (file, "\t.indirect_symbol %s\n", symbol_name); fprintf (file, "\t.long %s\n", binder_name); } + +void +darwin_x86_file_end (void) +{ + darwin_file_end (); + ix86_file_end (); +} #endif /* TARGET_MACHO */ /* Order the registers for register allocator. */ @@ -15443,10 +17522,6 @@ x86_order_regs_for_local_alloc (void) reg_alloc_order [pos++] = 0; } -#ifndef TARGET_USE_MS_BITFIELD_LAYOUT -#define TARGET_USE_MS_BITFIELD_LAYOUT 0 -#endif - /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in struct attribute_spec.handler. */ static tree @@ -15466,7 +17541,8 @@ ix86_handle_struct_attribute (tree *node, tree name, if (!(type && (TREE_CODE (*type) == RECORD_TYPE || TREE_CODE (*type) == UNION_TYPE))) { - warning ("`%s' attribute ignored", IDENTIFIER_POINTER (name)); + warning (OPT_Wattributes, "%qs attribute ignored", + IDENTIFIER_POINTER (name)); *no_add_attrs = true; } @@ -15475,7 +17551,7 @@ ix86_handle_struct_attribute (tree *node, tree name, || ((is_attribute_p ("gcc_struct", name) && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type))))) { - warning ("`%s' incompatible attribute ignored", + warning (OPT_Wattributes, "%qs incompatible attribute ignored", IDENTIFIER_POINTER (name)); *no_add_attrs = true; } @@ -15486,7 +17562,7 @@ ix86_handle_struct_attribute (tree *node, tree name, static bool ix86_ms_bitfield_layout_p (tree record_type) { - return (TARGET_USE_MS_BITFIELD_LAYOUT && + return (TARGET_MS_BITFIELD_LAYOUT && !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type))) || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type)); } @@ -15676,8 +17752,10 @@ x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED, #if TARGET_MACHO if (TARGET_MACHO) { - const char *ip = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (function)); - tmp = gen_rtx_SYMBOL_REF (Pmode, machopic_stub_name (ip)); + rtx sym_ref = XEXP (DECL_RTL (function), 0); + tmp = (gen_rtx_SYMBOL_REF + (Pmode, + machopic_indirection_name (sym_ref, /*stub_p=*/true))); tmp = gen_rtx_MEM (QImode, tmp); xops[0] = tmp; output_asm_insn ("jmp\t%0", xops); @@ -15686,7 +17764,7 @@ x86_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED, #endif /* TARGET_MACHO */ { tmp = gen_rtx_REG (SImode, 2 /* ECX */); - output_set_got (tmp); + output_set_got (tmp, NULL_RTX); xops[1] = tmp; output_asm_insn ("mov{l}\t{%0@GOT(%1), %1|%1, %0@GOT[%1]}", xops); @@ -15699,6 +17777,9 @@ static void x86_file_start (void) { default_file_start (); +#if TARGET_MACHO + darwin_file_start (); +#endif if (X86_FILE_START_VERSION_DIRECTIVE) fputs ("\t.version\t\"01.01\"\n", asm_out_file); if (X86_FILE_START_FLTUSED) @@ -15812,7 +17893,7 @@ min_insn_size (rtx insn) window. */ static void -k8_avoid_jump_misspredicts (void) +ix86_avoid_jump_misspredicts (void) { rtx insn, start = get_insns (); int nbytes = 0, njumps = 0; @@ -15832,8 +17913,8 @@ k8_avoid_jump_misspredicts (void) { nbytes += min_insn_size (insn); - if (rtl_dump_file) - fprintf(rtl_dump_file, "Insn %i estimated to %i bytes\n", + if (dump_file) + fprintf(dump_file, "Insn %i estimated to %i bytes\n", INSN_UID (insn), min_insn_size (insn)); if ((GET_CODE (insn) == JUMP_INSN && GET_CODE (PATTERN (insn)) != ADDR_VEC @@ -15855,75 +17936,85 @@ k8_avoid_jump_misspredicts (void) isjump = 0; nbytes -= min_insn_size (start); } - if (njumps < 0) - abort (); - if (rtl_dump_file) - fprintf(rtl_dump_file, "Interval %i to %i has %i bytes\n", + gcc_assert (njumps >= 0); + if (dump_file) + fprintf (dump_file, "Interval %i to %i has %i bytes\n", INSN_UID (start), INSN_UID (insn), nbytes); if (njumps == 3 && isjump && nbytes < 16) { int padsize = 15 - nbytes + min_insn_size (insn); - if (rtl_dump_file) - fprintf (rtl_dump_file, "Padding insn %i by %i bytes!\n", INSN_UID (insn), padsize); + if (dump_file) + fprintf (dump_file, "Padding insn %i by %i bytes!\n", + INSN_UID (insn), padsize); emit_insn_before (gen_align (GEN_INT (padsize)), insn); } } } -/* Implement machine specific optimizations. - At the moment we implement single transformation: AMD Athlon works faster +/* AMD Athlon works faster when RET is not destination of conditional jump or directly preceded by other jump instruction. We avoid the penalty by inserting NOP just before the RET instructions in such cases. */ static void -ix86_reorg (void) +ix86_pad_returns (void) { edge e; + edge_iterator ei; - if (!TARGET_ATHLON_K8 || !optimize || optimize_size) - return; - for (e = EXIT_BLOCK_PTR->pred; e; e = e->pred_next) - { - basic_block bb = e->src; - rtx ret = BB_END (bb); - rtx prev; - bool replace = false; - - if (GET_CODE (ret) != JUMP_INSN || GET_CODE (PATTERN (ret)) != RETURN - || !maybe_hot_bb_p (bb)) - continue; - for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev)) - if (active_insn_p (prev) || GET_CODE (prev) == CODE_LABEL) - break; - if (prev && GET_CODE (prev) == CODE_LABEL) - { - edge e; - for (e = bb->pred; e; e = e->pred_next) - if (EDGE_FREQUENCY (e) && e->src->index >= 0 - && !(e->flags & EDGE_FALLTHRU)) + FOR_EACH_EDGE (e, ei, EXIT_BLOCK_PTR->preds) + { + basic_block bb = e->src; + rtx ret = BB_END (bb); + rtx prev; + bool replace = false; + + if (GET_CODE (ret) != JUMP_INSN || GET_CODE (PATTERN (ret)) != RETURN + || !maybe_hot_bb_p (bb)) + continue; + for (prev = PREV_INSN (ret); prev; prev = PREV_INSN (prev)) + if (active_insn_p (prev) || GET_CODE (prev) == CODE_LABEL) + break; + if (prev && GET_CODE (prev) == CODE_LABEL) + { + edge e; + edge_iterator ei; + + FOR_EACH_EDGE (e, ei, bb->preds) + if (EDGE_FREQUENCY (e) && e->src->index >= 0 + && !(e->flags & EDGE_FALLTHRU)) + replace = true; + } + if (!replace) + { + prev = prev_active_insn (ret); + if (prev + && ((GET_CODE (prev) == JUMP_INSN && any_condjump_p (prev)) + || GET_CODE (prev) == CALL_INSN)) replace = true; - } - if (!replace) - { - prev = prev_active_insn (ret); - if (prev - && ((GET_CODE (prev) == JUMP_INSN && any_condjump_p (prev)) - || GET_CODE (prev) == CALL_INSN)) - replace = true; - /* Empty functions get branch mispredict even when the jump destination - is not visible to us. */ - if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED) - replace = true; - } - if (replace) - { - emit_insn_before (gen_return_internal_long (), ret); - delete_insn (ret); - } - } - k8_avoid_jump_misspredicts (); + /* Empty functions get branch mispredict even when the jump destination + is not visible to us. */ + if (!prev && cfun->function_frequency > FUNCTION_FREQUENCY_UNLIKELY_EXECUTED) + replace = true; + } + if (replace) + { + emit_insn_before (gen_return_internal_long (), ret); + delete_insn (ret); + } + } +} + +/* Implement machine specific optimizations. We implement padding of returns + for K8 CPUs and pass to avoid 4 jumps in the single 16 byte window. */ +static void +ix86_reorg (void) +{ + if (TARGET_PAD_RETURNS && optimize && !optimize_size) + ix86_pad_returns (); + if (TARGET_FOUR_JUMP_LIMIT && optimize && !optimize_size) + ix86_avoid_jump_misspredicts (); } /* Return nonzero when QImode register that must be represented via REX prefix @@ -15970,9 +18061,7 @@ x86_emit_floatuns (rtx operands[2]) enum machine_mode mode, inmode; inmode = GET_MODE (operands[1]); - if (inmode != SImode - && inmode != DImode) - abort (); + gcc_assert (inmode == SImode || inmode == DImode); out = operands[0]; in = force_reg (inmode, operands[1]); @@ -15998,102 +18087,1076 @@ x86_emit_floatuns (rtx operands[2]) emit_label (donelab); } + +/* A subroutine of ix86_expand_vector_init. Store into TARGET a vector + with all elements equal to VAR. Return true if successful. */ -/* Return if we do not know how to pass TYPE solely in registers. */ -bool -ix86_must_pass_in_stack (enum machine_mode mode, tree type) +static bool +ix86_expand_vector_init_duplicate (bool mmx_ok, enum machine_mode mode, + rtx target, rtx val) +{ + enum machine_mode smode, wsmode, wvmode; + rtx x; + + switch (mode) + { + case V2SImode: + case V2SFmode: + if (!mmx_ok) + return false; + /* FALLTHRU */ + + case V2DFmode: + case V2DImode: + case V4SFmode: + case V4SImode: + val = force_reg (GET_MODE_INNER (mode), val); + x = gen_rtx_VEC_DUPLICATE (mode, val); + emit_insn (gen_rtx_SET (VOIDmode, target, x)); + return true; + + case V4HImode: + if (!mmx_ok) + return false; + if (TARGET_SSE || TARGET_3DNOW_A) + { + val = gen_lowpart (SImode, val); + x = gen_rtx_TRUNCATE (HImode, val); + x = gen_rtx_VEC_DUPLICATE (mode, x); + emit_insn (gen_rtx_SET (VOIDmode, target, x)); + return true; + } + else + { + smode = HImode; + wsmode = SImode; + wvmode = V2SImode; + goto widen; + } + + case V8QImode: + if (!mmx_ok) + return false; + smode = QImode; + wsmode = HImode; + wvmode = V4HImode; + goto widen; + case V8HImode: + if (TARGET_SSE2) + { + rtx tmp1, tmp2; + /* Extend HImode to SImode using a paradoxical SUBREG. */ + tmp1 = gen_reg_rtx (SImode); + emit_move_insn (tmp1, gen_lowpart (SImode, val)); + /* Insert the SImode value as low element of V4SImode vector. */ + tmp2 = gen_reg_rtx (V4SImode); + tmp1 = gen_rtx_VEC_MERGE (V4SImode, + gen_rtx_VEC_DUPLICATE (V4SImode, tmp1), + CONST0_RTX (V4SImode), + const1_rtx); + emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1)); + /* Cast the V4SImode vector back to a V8HImode vector. */ + tmp1 = gen_reg_rtx (V8HImode); + emit_move_insn (tmp1, gen_lowpart (V8HImode, tmp2)); + /* Duplicate the low short through the whole low SImode word. */ + emit_insn (gen_sse2_punpcklwd (tmp1, tmp1, tmp1)); + /* Cast the V8HImode vector back to a V4SImode vector. */ + tmp2 = gen_reg_rtx (V4SImode); + emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1)); + /* Replicate the low element of the V4SImode vector. */ + emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx)); + /* Cast the V2SImode back to V8HImode, and store in target. */ + emit_move_insn (target, gen_lowpart (V8HImode, tmp2)); + return true; + } + smode = HImode; + wsmode = SImode; + wvmode = V4SImode; + goto widen; + case V16QImode: + if (TARGET_SSE2) + { + rtx tmp1, tmp2; + /* Extend QImode to SImode using a paradoxical SUBREG. */ + tmp1 = gen_reg_rtx (SImode); + emit_move_insn (tmp1, gen_lowpart (SImode, val)); + /* Insert the SImode value as low element of V4SImode vector. */ + tmp2 = gen_reg_rtx (V4SImode); + tmp1 = gen_rtx_VEC_MERGE (V4SImode, + gen_rtx_VEC_DUPLICATE (V4SImode, tmp1), + CONST0_RTX (V4SImode), + const1_rtx); + emit_insn (gen_rtx_SET (VOIDmode, tmp2, tmp1)); + /* Cast the V4SImode vector back to a V16QImode vector. */ + tmp1 = gen_reg_rtx (V16QImode); + emit_move_insn (tmp1, gen_lowpart (V16QImode, tmp2)); + /* Duplicate the low byte through the whole low SImode word. */ + emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1)); + emit_insn (gen_sse2_punpcklbw (tmp1, tmp1, tmp1)); + /* Cast the V16QImode vector back to a V4SImode vector. */ + tmp2 = gen_reg_rtx (V4SImode); + emit_move_insn (tmp2, gen_lowpart (V4SImode, tmp1)); + /* Replicate the low element of the V4SImode vector. */ + emit_insn (gen_sse2_pshufd (tmp2, tmp2, const0_rtx)); + /* Cast the V2SImode back to V16QImode, and store in target. */ + emit_move_insn (target, gen_lowpart (V16QImode, tmp2)); + return true; + } + smode = QImode; + wsmode = HImode; + wvmode = V8HImode; + goto widen; + widen: + /* Replicate the value once into the next wider mode and recurse. */ + val = convert_modes (wsmode, smode, val, true); + x = expand_simple_binop (wsmode, ASHIFT, val, + GEN_INT (GET_MODE_BITSIZE (smode)), + NULL_RTX, 1, OPTAB_LIB_WIDEN); + val = expand_simple_binop (wsmode, IOR, val, x, x, 1, OPTAB_LIB_WIDEN); + + x = gen_reg_rtx (wvmode); + if (!ix86_expand_vector_init_duplicate (mmx_ok, wvmode, x, val)) + gcc_unreachable (); + emit_move_insn (target, gen_lowpart (mode, x)); + return true; + + default: + return false; + } +} + +/* A subroutine of ix86_expand_vector_init. Store into TARGET a vector + whose ONE_VAR element is VAR, and other elements are zero. Return true + if successful. */ + +static bool +ix86_expand_vector_init_one_nonzero (bool mmx_ok, enum machine_mode mode, + rtx target, rtx var, int one_var) { - if (default_must_pass_in_stack (mode, type)) - return true; - return (!TARGET_64BIT && type && mode == TImode); + enum machine_mode vsimode; + rtx new_target; + rtx x, tmp; + + switch (mode) + { + case V2SFmode: + case V2SImode: + if (!mmx_ok) + return false; + /* FALLTHRU */ + + case V2DFmode: + case V2DImode: + if (one_var != 0) + return false; + var = force_reg (GET_MODE_INNER (mode), var); + x = gen_rtx_VEC_CONCAT (mode, var, CONST0_RTX (GET_MODE_INNER (mode))); + emit_insn (gen_rtx_SET (VOIDmode, target, x)); + return true; + + case V4SFmode: + case V4SImode: + if (!REG_P (target) || REGNO (target) < FIRST_PSEUDO_REGISTER) + new_target = gen_reg_rtx (mode); + else + new_target = target; + var = force_reg (GET_MODE_INNER (mode), var); + x = gen_rtx_VEC_DUPLICATE (mode, var); + x = gen_rtx_VEC_MERGE (mode, x, CONST0_RTX (mode), const1_rtx); + emit_insn (gen_rtx_SET (VOIDmode, new_target, x)); + if (one_var != 0) + { + /* We need to shuffle the value to the correct position, so + create a new pseudo to store the intermediate result. */ + + /* With SSE2, we can use the integer shuffle insns. */ + if (mode != V4SFmode && TARGET_SSE2) + { + emit_insn (gen_sse2_pshufd_1 (new_target, new_target, + GEN_INT (1), + GEN_INT (one_var == 1 ? 0 : 1), + GEN_INT (one_var == 2 ? 0 : 1), + GEN_INT (one_var == 3 ? 0 : 1))); + if (target != new_target) + emit_move_insn (target, new_target); + return true; + } + + /* Otherwise convert the intermediate result to V4SFmode and + use the SSE1 shuffle instructions. */ + if (mode != V4SFmode) + { + tmp = gen_reg_rtx (V4SFmode); + emit_move_insn (tmp, gen_lowpart (V4SFmode, new_target)); + } + else + tmp = new_target; + + emit_insn (gen_sse_shufps_1 (tmp, tmp, tmp, + GEN_INT (1), + GEN_INT (one_var == 1 ? 0 : 1), + GEN_INT (one_var == 2 ? 0+4 : 1+4), + GEN_INT (one_var == 3 ? 0+4 : 1+4))); + + if (mode != V4SFmode) + emit_move_insn (target, gen_lowpart (V4SImode, tmp)); + else if (tmp != target) + emit_move_insn (target, tmp); + } + else if (target != new_target) + emit_move_insn (target, new_target); + return true; + + case V8HImode: + case V16QImode: + vsimode = V4SImode; + goto widen; + case V4HImode: + case V8QImode: + if (!mmx_ok) + return false; + vsimode = V2SImode; + goto widen; + widen: + if (one_var != 0) + return false; + + /* Zero extend the variable element to SImode and recurse. */ + var = convert_modes (SImode, GET_MODE_INNER (mode), var, true); + + x = gen_reg_rtx (vsimode); + if (!ix86_expand_vector_init_one_nonzero (mmx_ok, vsimode, x, + var, one_var)) + gcc_unreachable (); + + emit_move_insn (target, gen_lowpart (mode, x)); + return true; + + default: + return false; + } } -/* Initialize vector TARGET via VALS. */ +/* A subroutine of ix86_expand_vector_init. Store into TARGET a vector + consisting of the values in VALS. It is known that all elements + except ONE_VAR are constants. Return true if successful. */ + +static bool +ix86_expand_vector_init_one_var (bool mmx_ok, enum machine_mode mode, + rtx target, rtx vals, int one_var) +{ + rtx var = XVECEXP (vals, 0, one_var); + enum machine_mode wmode; + rtx const_vec, x; + + const_vec = copy_rtx (vals); + XVECEXP (const_vec, 0, one_var) = CONST0_RTX (GET_MODE_INNER (mode)); + const_vec = gen_rtx_CONST_VECTOR (mode, XVEC (const_vec, 0)); + + switch (mode) + { + case V2DFmode: + case V2DImode: + case V2SFmode: + case V2SImode: + /* For the two element vectors, it's just as easy to use + the general case. */ + return false; + + case V4SFmode: + case V4SImode: + case V8HImode: + case V4HImode: + break; + + case V16QImode: + wmode = V8HImode; + goto widen; + case V8QImode: + wmode = V4HImode; + goto widen; + widen: + /* There's no way to set one QImode entry easily. Combine + the variable value with its adjacent constant value, and + promote to an HImode set. */ + x = XVECEXP (vals, 0, one_var ^ 1); + if (one_var & 1) + { + var = convert_modes (HImode, QImode, var, true); + var = expand_simple_binop (HImode, ASHIFT, var, GEN_INT (8), + NULL_RTX, 1, OPTAB_LIB_WIDEN); + x = GEN_INT (INTVAL (x) & 0xff); + } + else + { + var = convert_modes (HImode, QImode, var, true); + x = gen_int_mode (INTVAL (x) << 8, HImode); + } + if (x != const0_rtx) + var = expand_simple_binop (HImode, IOR, var, x, var, + 1, OPTAB_LIB_WIDEN); + + x = gen_reg_rtx (wmode); + emit_move_insn (x, gen_lowpart (wmode, const_vec)); + ix86_expand_vector_set (mmx_ok, x, var, one_var >> 1); + + emit_move_insn (target, gen_lowpart (mode, x)); + return true; + + default: + return false; + } + + emit_move_insn (target, const_vec); + ix86_expand_vector_set (mmx_ok, target, var, one_var); + return true; +} + +/* A subroutine of ix86_expand_vector_init. Handle the most general case: + all values variable, and none identical. */ + +static void +ix86_expand_vector_init_general (bool mmx_ok, enum machine_mode mode, + rtx target, rtx vals) +{ + enum machine_mode half_mode = GET_MODE_INNER (mode); + rtx op0 = NULL, op1 = NULL; + bool use_vec_concat = false; + + switch (mode) + { + case V2SFmode: + case V2SImode: + if (!mmx_ok && !TARGET_SSE) + break; + /* FALLTHRU */ + + case V2DFmode: + case V2DImode: + /* For the two element vectors, we always implement VEC_CONCAT. */ + op0 = XVECEXP (vals, 0, 0); + op1 = XVECEXP (vals, 0, 1); + use_vec_concat = true; + break; + + case V4SFmode: + half_mode = V2SFmode; + goto half; + case V4SImode: + half_mode = V2SImode; + goto half; + half: + { + rtvec v; + + /* For V4SF and V4SI, we implement a concat of two V2 vectors. + Recurse to load the two halves. */ + + op0 = gen_reg_rtx (half_mode); + v = gen_rtvec (2, XVECEXP (vals, 0, 0), XVECEXP (vals, 0, 1)); + ix86_expand_vector_init (false, op0, gen_rtx_PARALLEL (half_mode, v)); + + op1 = gen_reg_rtx (half_mode); + v = gen_rtvec (2, XVECEXP (vals, 0, 2), XVECEXP (vals, 0, 3)); + ix86_expand_vector_init (false, op1, gen_rtx_PARALLEL (half_mode, v)); + + use_vec_concat = true; + } + break; + + case V8HImode: + case V16QImode: + case V4HImode: + case V8QImode: + break; + + default: + gcc_unreachable (); + } + + if (use_vec_concat) + { + if (!register_operand (op0, half_mode)) + op0 = force_reg (half_mode, op0); + if (!register_operand (op1, half_mode)) + op1 = force_reg (half_mode, op1); + + emit_insn (gen_rtx_SET (VOIDmode, target, + gen_rtx_VEC_CONCAT (mode, op0, op1))); + } + else + { + int i, j, n_elts, n_words, n_elt_per_word; + enum machine_mode inner_mode; + rtx words[4], shift; + + inner_mode = GET_MODE_INNER (mode); + n_elts = GET_MODE_NUNITS (mode); + n_words = GET_MODE_SIZE (mode) / UNITS_PER_WORD; + n_elt_per_word = n_elts / n_words; + shift = GEN_INT (GET_MODE_BITSIZE (inner_mode)); + + for (i = 0; i < n_words; ++i) + { + rtx word = NULL_RTX; + + for (j = 0; j < n_elt_per_word; ++j) + { + rtx elt = XVECEXP (vals, 0, (i+1)*n_elt_per_word - j - 1); + elt = convert_modes (word_mode, inner_mode, elt, true); + + if (j == 0) + word = elt; + else + { + word = expand_simple_binop (word_mode, ASHIFT, word, shift, + word, 1, OPTAB_LIB_WIDEN); + word = expand_simple_binop (word_mode, IOR, word, elt, + word, 1, OPTAB_LIB_WIDEN); + } + } + + words[i] = word; + } + + if (n_words == 1) + emit_move_insn (target, gen_lowpart (mode, words[0])); + else if (n_words == 2) + { + rtx tmp = gen_reg_rtx (mode); + emit_insn (gen_rtx_CLOBBER (VOIDmode, tmp)); + emit_move_insn (gen_lowpart (word_mode, tmp), words[0]); + emit_move_insn (gen_highpart (word_mode, tmp), words[1]); + emit_move_insn (target, tmp); + } + else if (n_words == 4) + { + rtx tmp = gen_reg_rtx (V4SImode); + vals = gen_rtx_PARALLEL (V4SImode, gen_rtvec_v (4, words)); + ix86_expand_vector_init_general (false, V4SImode, tmp, vals); + emit_move_insn (target, gen_lowpart (mode, tmp)); + } + else + gcc_unreachable (); + } +} + +/* Initialize vector TARGET via VALS. Suppress the use of MMX + instructions unless MMX_OK is true. */ + void -ix86_expand_vector_init (rtx target, rtx vals) +ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals) { enum machine_mode mode = GET_MODE (target); - int elt_size = GET_MODE_SIZE (GET_MODE_INNER (mode)); - int n_elts = (GET_MODE_SIZE (mode) / elt_size); + enum machine_mode inner_mode = GET_MODE_INNER (mode); + int n_elts = GET_MODE_NUNITS (mode); + int n_var = 0, one_var = -1; + bool all_same = true, all_const_zero = true; int i; - - for (i = n_elts - 1; i >= 0; i--) - if (GET_CODE (XVECEXP (vals, 0, i)) != CONST_INT - && GET_CODE (XVECEXP (vals, 0, i)) != CONST_DOUBLE) - break; + rtx x; + + for (i = 0; i < n_elts; ++i) + { + x = XVECEXP (vals, 0, i); + if (!CONSTANT_P (x)) + n_var++, one_var = i; + else if (x != CONST0_RTX (inner_mode)) + all_const_zero = false; + if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0))) + all_same = false; + } - /* Few special cases first... - ... constants are best loaded from constant pool. */ - if (i < 0) + /* Constants are best loaded from the constant pool. */ + if (n_var == 0) { emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0))); return; } - /* ... values where only first field is non-constant are best loaded - from the pool and overwriten via move later. */ - if (!i) + /* If all values are identical, broadcast the value. */ + if (all_same + && ix86_expand_vector_init_duplicate (mmx_ok, mode, target, + XVECEXP (vals, 0, 0))) + return; + + /* Values where only one field is non-constant are best loaded from + the pool and overwritten via move later. */ + if (n_var == 1) { - rtx op = simplify_gen_subreg (mode, XVECEXP (vals, 0, 0), - GET_MODE_INNER (mode), 0); + if (all_const_zero + && ix86_expand_vector_init_one_nonzero (mmx_ok, mode, target, + XVECEXP (vals, 0, one_var), + one_var)) + return; - op = force_reg (mode, op); - XVECEXP (vals, 0, 0) = CONST0_RTX (GET_MODE_INNER (mode)); - emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0))); - switch (GET_MODE (target)) + if (ix86_expand_vector_init_one_var (mmx_ok, mode, target, vals, one_var)) + return; + } + + ix86_expand_vector_init_general (mmx_ok, mode, target, vals); +} + +void +ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt) +{ + enum machine_mode mode = GET_MODE (target); + enum machine_mode inner_mode = GET_MODE_INNER (mode); + bool use_vec_merge = false; + rtx tmp; + + switch (mode) + { + case V2SFmode: + case V2SImode: + if (mmx_ok) { - case V2DFmode: - emit_insn (gen_sse2_movsd (target, target, op)); - break; - case V4SFmode: - emit_insn (gen_sse_movss (target, target, op)); - break; - default: - break; + tmp = gen_reg_rtx (GET_MODE_INNER (mode)); + ix86_expand_vector_extract (true, tmp, target, 1 - elt); + if (elt == 0) + tmp = gen_rtx_VEC_CONCAT (mode, tmp, val); + else + tmp = gen_rtx_VEC_CONCAT (mode, val, tmp); + emit_insn (gen_rtx_SET (VOIDmode, target, tmp)); + return; } + break; + + case V2DFmode: + case V2DImode: + { + rtx op0, op1; + + /* For the two element vectors, we implement a VEC_CONCAT with + the extraction of the other element. */ + + tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (1 - elt))); + tmp = gen_rtx_VEC_SELECT (inner_mode, target, tmp); + + if (elt == 0) + op0 = val, op1 = tmp; + else + op0 = tmp, op1 = val; + + tmp = gen_rtx_VEC_CONCAT (mode, op0, op1); + emit_insn (gen_rtx_SET (VOIDmode, target, tmp)); + } return; + + case V4SFmode: + switch (elt) + { + case 0: + use_vec_merge = true; + break; + + case 1: + /* tmp = target = A B C D */ + tmp = copy_to_reg (target); + /* target = A A B B */ + emit_insn (gen_sse_unpcklps (target, target, target)); + /* target = X A B B */ + ix86_expand_vector_set (false, target, val, 0); + /* target = A X C D */ + emit_insn (gen_sse_shufps_1 (target, target, tmp, + GEN_INT (1), GEN_INT (0), + GEN_INT (2+4), GEN_INT (3+4))); + return; + + case 2: + /* tmp = target = A B C D */ + tmp = copy_to_reg (target); + /* tmp = X B C D */ + ix86_expand_vector_set (false, tmp, val, 0); + /* target = A B X D */ + emit_insn (gen_sse_shufps_1 (target, target, tmp, + GEN_INT (0), GEN_INT (1), + GEN_INT (0+4), GEN_INT (3+4))); + return; + + case 3: + /* tmp = target = A B C D */ + tmp = copy_to_reg (target); + /* tmp = X B C D */ + ix86_expand_vector_set (false, tmp, val, 0); + /* target = A B X D */ + emit_insn (gen_sse_shufps_1 (target, target, tmp, + GEN_INT (0), GEN_INT (1), + GEN_INT (2+4), GEN_INT (0+4))); + return; + + default: + gcc_unreachable (); + } + break; + + case V4SImode: + /* Element 0 handled by vec_merge below. */ + if (elt == 0) + { + use_vec_merge = true; + break; + } + + if (TARGET_SSE2) + { + /* With SSE2, use integer shuffles to swap element 0 and ELT, + store into element 0, then shuffle them back. */ + + rtx order[4]; + + order[0] = GEN_INT (elt); + order[1] = const1_rtx; + order[2] = const2_rtx; + order[3] = GEN_INT (3); + order[elt] = const0_rtx; + + emit_insn (gen_sse2_pshufd_1 (target, target, order[0], + order[1], order[2], order[3])); + + ix86_expand_vector_set (false, target, val, 0); + + emit_insn (gen_sse2_pshufd_1 (target, target, order[0], + order[1], order[2], order[3])); + } + else + { + /* For SSE1, we have to reuse the V4SF code. */ + ix86_expand_vector_set (false, gen_lowpart (V4SFmode, target), + gen_lowpart (SFmode, val), elt); + } + return; + + case V8HImode: + use_vec_merge = TARGET_SSE2; + break; + case V4HImode: + use_vec_merge = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A); + break; + + case V16QImode: + case V8QImode: + default: + break; } - /* And the busy sequence doing rotations. */ - switch (GET_MODE (target)) + if (use_vec_merge) { - case V2DFmode: + tmp = gen_rtx_VEC_DUPLICATE (mode, val); + tmp = gen_rtx_VEC_MERGE (mode, tmp, target, GEN_INT (1 << elt)); + emit_insn (gen_rtx_SET (VOIDmode, target, tmp)); + } + else + { + rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false); + + emit_move_insn (mem, target); + + tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode)); + emit_move_insn (tmp, val); + + emit_move_insn (target, mem); + } +} + +void +ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt) +{ + enum machine_mode mode = GET_MODE (vec); + enum machine_mode inner_mode = GET_MODE_INNER (mode); + bool use_vec_extr = false; + rtx tmp; + + switch (mode) + { + case V2SImode: + case V2SFmode: + if (!mmx_ok) + break; + /* FALLTHRU */ + + case V2DFmode: + case V2DImode: + use_vec_extr = true; + break; + + case V4SFmode: + switch (elt) { - rtx vecop0 = - simplify_gen_subreg (V2DFmode, XVECEXP (vals, 0, 0), DFmode, 0); - rtx vecop1 = - simplify_gen_subreg (V2DFmode, XVECEXP (vals, 0, 1), DFmode, 0); + case 0: + tmp = vec; + break; + + case 1: + case 3: + tmp = gen_reg_rtx (mode); + emit_insn (gen_sse_shufps_1 (tmp, vec, vec, + GEN_INT (elt), GEN_INT (elt), + GEN_INT (elt+4), GEN_INT (elt+4))); + break; + + case 2: + tmp = gen_reg_rtx (mode); + emit_insn (gen_sse_unpckhps (tmp, vec, vec)); + break; - vecop0 = force_reg (V2DFmode, vecop0); - vecop1 = force_reg (V2DFmode, vecop1); - emit_insn (gen_sse2_unpcklpd (target, vecop0, vecop1)); + default: + gcc_unreachable (); } - break; - case V4SFmode: + vec = tmp; + use_vec_extr = true; + elt = 0; + break; + + case V4SImode: + if (TARGET_SSE2) { - rtx vecop0 = - simplify_gen_subreg (V4SFmode, XVECEXP (vals, 0, 0), SFmode, 0); - rtx vecop1 = - simplify_gen_subreg (V4SFmode, XVECEXP (vals, 0, 1), SFmode, 0); - rtx vecop2 = - simplify_gen_subreg (V4SFmode, XVECEXP (vals, 0, 2), SFmode, 0); - rtx vecop3 = - simplify_gen_subreg (V4SFmode, XVECEXP (vals, 0, 3), SFmode, 0); - rtx tmp1 = gen_reg_rtx (V4SFmode); - rtx tmp2 = gen_reg_rtx (V4SFmode); - - vecop0 = force_reg (V4SFmode, vecop0); - vecop1 = force_reg (V4SFmode, vecop1); - vecop2 = force_reg (V4SFmode, vecop2); - vecop3 = force_reg (V4SFmode, vecop3); - emit_insn (gen_sse_unpcklps (tmp1, vecop1, vecop3)); - emit_insn (gen_sse_unpcklps (tmp2, vecop0, vecop2)); - emit_insn (gen_sse_unpcklps (target, tmp2, tmp1)); + switch (elt) + { + case 0: + tmp = vec; + break; + + case 1: + case 3: + tmp = gen_reg_rtx (mode); + emit_insn (gen_sse2_pshufd_1 (tmp, vec, + GEN_INT (elt), GEN_INT (elt), + GEN_INT (elt), GEN_INT (elt))); + break; + + case 2: + tmp = gen_reg_rtx (mode); + emit_insn (gen_sse2_punpckhdq (tmp, vec, vec)); + break; + + default: + gcc_unreachable (); + } + vec = tmp; + use_vec_extr = true; + elt = 0; } - break; - default: - abort (); + else + { + /* For SSE1, we have to reuse the V4SF code. */ + ix86_expand_vector_extract (false, gen_lowpart (SFmode, target), + gen_lowpart (V4SFmode, vec), elt); + return; + } + break; + + case V8HImode: + use_vec_extr = TARGET_SSE2; + break; + case V4HImode: + use_vec_extr = mmx_ok && (TARGET_SSE || TARGET_3DNOW_A); + break; + + case V16QImode: + case V8QImode: + /* ??? Could extract the appropriate HImode element and shift. */ + default: + break; + } + + if (use_vec_extr) + { + tmp = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (1, GEN_INT (elt))); + tmp = gen_rtx_VEC_SELECT (inner_mode, vec, tmp); + + /* Let the rtl optimizers know about the zero extension performed. */ + if (inner_mode == HImode) + { + tmp = gen_rtx_ZERO_EXTEND (SImode, tmp); + target = gen_lowpart (SImode, target); + } + + emit_insn (gen_rtx_SET (VOIDmode, target, tmp)); + } + else + { + rtx mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), false); + + emit_move_insn (mem, vec); + + tmp = adjust_address (mem, inner_mode, elt*GET_MODE_SIZE (inner_mode)); + emit_move_insn (target, tmp); + } +} + +/* Expand a vector reduction on V4SFmode for SSE1. FN is the binary + pattern to reduce; DEST is the destination; IN is the input vector. */ + +void +ix86_expand_reduc_v4sf (rtx (*fn) (rtx, rtx, rtx), rtx dest, rtx in) +{ + rtx tmp1, tmp2, tmp3; + + tmp1 = gen_reg_rtx (V4SFmode); + tmp2 = gen_reg_rtx (V4SFmode); + tmp3 = gen_reg_rtx (V4SFmode); + + emit_insn (gen_sse_movhlps (tmp1, in, in)); + emit_insn (fn (tmp2, tmp1, in)); + + emit_insn (gen_sse_shufps_1 (tmp3, tmp2, tmp2, + GEN_INT (1), GEN_INT (1), + GEN_INT (1+4), GEN_INT (1+4))); + emit_insn (fn (dest, tmp2, tmp3)); +} + +/* Target hook for scalar_mode_supported_p. */ +static bool +ix86_scalar_mode_supported_p (enum machine_mode mode) +{ + if (DECIMAL_FLOAT_MODE_P (mode)) + return true; + else + return default_scalar_mode_supported_p (mode); +} + +/* Implements target hook vector_mode_supported_p. */ +static bool +ix86_vector_mode_supported_p (enum machine_mode mode) +{ + if (TARGET_SSE && VALID_SSE_REG_MODE (mode)) + return true; + if (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode)) + return true; + if (TARGET_MMX && VALID_MMX_REG_MODE (mode)) + return true; + if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode)) + return true; + return false; +} + +/* Worker function for TARGET_MD_ASM_CLOBBERS. + + We do this in the new i386 backend to maintain source compatibility + with the old cc0-based compiler. */ + +static tree +ix86_md_asm_clobbers (tree outputs ATTRIBUTE_UNUSED, + tree inputs ATTRIBUTE_UNUSED, + tree clobbers) +{ + clobbers = tree_cons (NULL_TREE, build_string (5, "flags"), + clobbers); + clobbers = tree_cons (NULL_TREE, build_string (4, "fpsr"), + clobbers); + clobbers = tree_cons (NULL_TREE, build_string (7, "dirflag"), + clobbers); + return clobbers; +} + +/* Return true if this goes in small data/bss. */ + +static bool +ix86_in_large_data_p (tree exp) +{ + if (ix86_cmodel != CM_MEDIUM && ix86_cmodel != CM_MEDIUM_PIC) + return false; + + /* Functions are never large data. */ + if (TREE_CODE (exp) == FUNCTION_DECL) + return false; + + if (TREE_CODE (exp) == VAR_DECL && DECL_SECTION_NAME (exp)) + { + const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (exp)); + if (strcmp (section, ".ldata") == 0 + || strcmp (section, ".lbss") == 0) + return true; + return false; + } + else + { + HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (exp)); + + /* If this is an incomplete type with size 0, then we can't put it + in data because it might be too big when completed. */ + if (!size || size > ix86_section_threshold) + return true; + } + + return false; +} +static void +ix86_encode_section_info (tree decl, rtx rtl, int first) +{ + default_encode_section_info (decl, rtl, first); + + if (TREE_CODE (decl) == VAR_DECL + && (TREE_STATIC (decl) || DECL_EXTERNAL (decl)) + && ix86_in_large_data_p (decl)) + SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= SYMBOL_FLAG_FAR_ADDR; +} + +/* Worker function for REVERSE_CONDITION. */ + +enum rtx_code +ix86_reverse_condition (enum rtx_code code, enum machine_mode mode) +{ + return (mode != CCFPmode && mode != CCFPUmode + ? reverse_condition (code) + : reverse_condition_maybe_unordered (code)); +} + +/* Output code to perform an x87 FP register move, from OPERANDS[1] + to OPERANDS[0]. */ + +const char * +output_387_reg_move (rtx insn, rtx *operands) +{ + if (REG_P (operands[1]) + && find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) + { + if (REGNO (operands[0]) == FIRST_STACK_REG) + return output_387_ffreep (operands, 0); + return "fstp\t%y0"; + } + if (STACK_TOP_P (operands[0])) + return "fld%z1\t%y1"; + return "fst\t%y0"; +} + +/* Output code to perform a conditional jump to LABEL, if C2 flag in + FP status register is set. */ + +void +ix86_emit_fp_unordered_jump (rtx label) +{ + rtx reg = gen_reg_rtx (HImode); + rtx temp; + + emit_insn (gen_x86_fnstsw_1 (reg)); + + if (TARGET_USE_SAHF) + { + emit_insn (gen_x86_sahf_1 (reg)); + + temp = gen_rtx_REG (CCmode, FLAGS_REG); + temp = gen_rtx_UNORDERED (VOIDmode, temp, const0_rtx); + } + else + { + emit_insn (gen_testqi_ext_ccno_0 (reg, GEN_INT (0x04))); + + temp = gen_rtx_REG (CCNOmode, FLAGS_REG); + temp = gen_rtx_NE (VOIDmode, temp, const0_rtx); + } + + temp = gen_rtx_IF_THEN_ELSE (VOIDmode, temp, + gen_rtx_LABEL_REF (VOIDmode, label), + pc_rtx); + temp = gen_rtx_SET (VOIDmode, pc_rtx, temp); + emit_jump_insn (temp); +} + +/* Output code to perform a log1p XFmode calculation. */ + +void ix86_emit_i387_log1p (rtx op0, rtx op1) +{ + rtx label1 = gen_label_rtx (); + rtx label2 = gen_label_rtx (); + + rtx tmp = gen_reg_rtx (XFmode); + rtx tmp2 = gen_reg_rtx (XFmode); + + emit_insn (gen_absxf2 (tmp, op1)); + emit_insn (gen_cmpxf (tmp, + CONST_DOUBLE_FROM_REAL_VALUE ( + REAL_VALUE_ATOF ("0.29289321881345247561810596348408353", XFmode), + XFmode))); + emit_jump_insn (gen_bge (label1)); + + emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */ + emit_insn (gen_fyl2xp1_xf3 (op0, tmp2, op1)); + emit_jump (label2); + + emit_label (label1); + emit_move_insn (tmp, CONST1_RTX (XFmode)); + emit_insn (gen_addxf3 (tmp, op1, tmp)); + emit_move_insn (tmp2, standard_80387_constant_rtx (4)); /* fldln2 */ + emit_insn (gen_fyl2x_xf3 (op0, tmp2, tmp)); + + emit_label (label2); +} + +/* Solaris implementation of TARGET_ASM_NAMED_SECTION. */ + +static void +i386_solaris_elf_named_section (const char *name, unsigned int flags, + tree decl) +{ + /* With Binutils 2.15, the "@unwind" marker must be specified on + every occurrence of the ".eh_frame" section, not just the first + one. */ + if (TARGET_64BIT + && strcmp (name, ".eh_frame") == 0) + { + fprintf (asm_out_file, "\t.section\t%s,\"%s\",@unwind\n", name, + flags & SECTION_WRITE ? "aw" : "a"); + return; + } + default_elf_asm_named_section (name, flags, decl); +} + +/* Return the mangling of TYPE if it is an extended fundamental type. */ + +static const char * +ix86_mangle_fundamental_type (tree type) +{ + switch (TYPE_MODE (type)) + { + case TFmode: + /* __float128 is "g". */ + return "g"; + case XFmode: + /* "long double" or __float80 is "e". */ + return "e"; + default: + return NULL; } } +/* For 32-bit code we can save PIC register setup by using + __stack_chk_fail_local hidden function instead of calling + __stack_chk_fail directly. 64-bit code doesn't need to setup any PIC + register, so it is better to call __stack_chk_fail directly. */ + +static tree +ix86_stack_protect_fail (void) +{ + return TARGET_64BIT + ? default_external_stack_protect_fail () + : default_hidden_stack_protect_fail (); +} + +/* Select a format to encode pointers in exception handling data. CODE + is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is + true if the symbol may be affected by dynamic relocations. + + ??? All x86 object file formats are capable of representing this. + After all, the relocation needed is the same as for the call insn. + Whether or not a particular assembler allows us to enter such, I + guess we'll have to see. */ +int +asm_preferred_eh_data_format (int code, int global) +{ + if (flag_pic) + { + int type = DW_EH_PE_sdata8; + if (!TARGET_64BIT + || ix86_cmodel == CM_SMALL_PIC + || (ix86_cmodel == CM_MEDIUM_PIC && (global || code))) + type = DW_EH_PE_sdata4; + return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type; + } + if (ix86_cmodel == CM_SMALL + || (ix86_cmodel == CM_MEDIUM && code)) + return DW_EH_PE_udata4; + return DW_EH_PE_absptr; +} + #include "gt-i386.h" |
