diff options
author | kan <kan@FreeBSD.org> | 2005-06-03 03:50:42 +0000 |
---|---|---|
committer | kan <kan@FreeBSD.org> | 2005-06-03 03:50:42 +0000 |
commit | f8dd8336e3484d2d7f4887c5583585521dd055d0 (patch) | |
tree | 56d842dca34faa3e40f969e13617dfdbb051d690 /contrib/gcc/config | |
parent | a101babe926f42d1c4b46f430425c21fdcda6f97 (diff) | |
download | FreeBSD-src-f8dd8336e3484d2d7f4887c5583585521dd055d0.zip FreeBSD-src-f8dd8336e3484d2d7f4887c5583585521dd055d0.tar.gz |
Stock files.
Diffstat (limited to 'contrib/gcc/config')
-rw-r--r-- | contrib/gcc/config/alpha/alpha.c | 139 | ||||
-rw-r--r-- | contrib/gcc/config/i386/i386.md | 1068 |
2 files changed, 638 insertions, 569 deletions
diff --git a/contrib/gcc/config/alpha/alpha.c b/contrib/gcc/config/alpha/alpha.c index 0086968..fbaeabe 100644 --- a/contrib/gcc/config/alpha/alpha.c +++ b/contrib/gcc/config/alpha/alpha.c @@ -1947,6 +1947,17 @@ alpha_legitimize_address (rtx x, rtx scratch, } } +/* Primarily this is required for TLS symbols, but given that our move + patterns *ought* to be able to handle any symbol at any time, we + should never be spilling symbolic operands to the constant pool, ever. */ + +static bool +alpha_cannot_force_const_mem (rtx x) +{ + enum rtx_code code = GET_CODE (x); + return code == SYMBOL_REF || code == LABEL_REF || code == CONST; +} + /* We do not allow indirect calls to be optimized into sibling calls, nor can we allow a call to a function with a different GP to be optimized into a sibcall. */ @@ -3186,7 +3197,13 @@ alpha_emit_conditional_branch (enum rtx_code code) /* If the constants doesn't fit into an immediate, but can be generated by lda/ldah, we adjust the argument and compare against zero, so we can use beq/bne directly. */ - else if (GET_CODE (op1) == CONST_INT && (code == EQ || code == NE)) + /* ??? Don't do this when comparing against symbols, otherwise + we'll reduce (&x == 0x1234) to (&x-0x1234 == 0), which will + be declared false out of hand (at least for non-weak). */ + else if (GET_CODE (op1) == CONST_INT + && (code == EQ || code == NE) + && !(symbolic_operand (op0, VOIDmode) + || (GET_CODE (op0) == REG && REG_POINTER (op0)))) { HOST_WIDE_INT v = INTVAL (op1), n = -v; @@ -6786,11 +6803,6 @@ alpha_sa_mask (unsigned long *imaskP, unsigned long *fmaskP) break; imask |= 1UL << regno; } - - /* Glibc likes to use $31 as an unwind stopper for crt0. To - avoid hackery in unwind-dw2.c, we need to actively store a - zero in the prologue of _Unwind_RaiseException et al. */ - imask |= 1UL << 31; } /* If any register spilled, then spill the return address also. */ @@ -7046,6 +7058,48 @@ set_frame_related_p (void) #define FRP(exp) (start_sequence (), exp, set_frame_related_p ()) +/* Generates a store with the proper unwind info attached. VALUE is + stored at BASE_REG+BASE_OFS. If FRAME_BIAS is non-zero, then BASE_REG + contains SP+FRAME_BIAS, and that is the unwind info that should be + generated. If FRAME_REG != VALUE, then VALUE is being stored on + behalf of FRAME_REG, and FRAME_REG should be present in the unwind. */ + +static void +emit_frame_store_1 (rtx value, rtx base_reg, HOST_WIDE_INT frame_bias, + HOST_WIDE_INT base_ofs, rtx frame_reg) +{ + rtx addr, mem, insn; + + addr = plus_constant (base_reg, base_ofs); + mem = gen_rtx_MEM (DImode, addr); + set_mem_alias_set (mem, alpha_sr_alias_set); + + insn = emit_move_insn (mem, value); + RTX_FRAME_RELATED_P (insn) = 1; + + if (frame_bias || value != frame_reg) + { + if (frame_bias) + { + addr = plus_constant (stack_pointer_rtx, frame_bias + base_ofs); + mem = gen_rtx_MEM (DImode, addr); + } + + REG_NOTES (insn) + = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, + gen_rtx_SET (VOIDmode, mem, frame_reg), + REG_NOTES (insn)); + } +} + +static void +emit_frame_store (unsigned int regno, rtx base_reg, + HOST_WIDE_INT frame_bias, HOST_WIDE_INT base_ofs) +{ + rtx reg = gen_rtx_REG (DImode, regno); + emit_frame_store_1 (reg, base_reg, frame_bias, base_ofs, reg); +} + /* Write function prologue. */ /* On vms we have two kinds of functions: @@ -7075,7 +7129,7 @@ alpha_expand_prologue (void) HOST_WIDE_INT frame_size; /* Offset from base reg to register save area. */ HOST_WIDE_INT reg_offset; - rtx sa_reg, mem; + rtx sa_reg; int i; sa_size = alpha_sa_size (); @@ -7225,37 +7279,40 @@ alpha_expand_prologue (void) if (!TARGET_ABI_UNICOSMK) { + HOST_WIDE_INT sa_bias = 0; + /* Cope with very large offsets to the register save area. */ sa_reg = stack_pointer_rtx; if (reg_offset + sa_size > 0x8000) { int low = ((reg_offset & 0xffff) ^ 0x8000) - 0x8000; - HOST_WIDE_INT bias; + rtx sa_bias_rtx; if (low + sa_size <= 0x8000) - bias = reg_offset - low, reg_offset = low; + sa_bias = reg_offset - low, reg_offset = low; else - bias = reg_offset, reg_offset = 0; + sa_bias = reg_offset, reg_offset = 0; sa_reg = gen_rtx_REG (DImode, 24); - FRP (emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx, - GEN_INT (bias)))); + sa_bias_rtx = GEN_INT (sa_bias); + + if (add_operand (sa_bias_rtx, DImode)) + emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx, sa_bias_rtx)); + else + { + emit_move_insn (sa_reg, sa_bias_rtx); + emit_insn (gen_adddi3 (sa_reg, stack_pointer_rtx, sa_reg)); + } } /* Save regs in stack order. Beginning with VMS PV. */ if (TARGET_ABI_OPEN_VMS && alpha_procedure_type == PT_STACK) - { - mem = gen_rtx_MEM (DImode, stack_pointer_rtx); - set_mem_alias_set (mem, alpha_sr_alias_set); - FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_PV))); - } + emit_frame_store (REG_PV, stack_pointer_rtx, 0, 0); /* Save register RA next. */ if (imask & (1UL << REG_RA)) { - mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset)); - set_mem_alias_set (mem, alpha_sr_alias_set); - FRP (emit_move_insn (mem, gen_rtx_REG (DImode, REG_RA))); + emit_frame_store (REG_RA, sa_reg, sa_bias, reg_offset); imask &= ~(1UL << REG_RA); reg_offset += 8; } @@ -7264,36 +7321,14 @@ alpha_expand_prologue (void) for (i = 0; i < 31; i++) if (imask & (1UL << i)) { - mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset)); - set_mem_alias_set (mem, alpha_sr_alias_set); - FRP (emit_move_insn (mem, gen_rtx_REG (DImode, i))); + emit_frame_store (i, sa_reg, sa_bias, reg_offset); reg_offset += 8; } - /* Store a zero if requested for unwinding. */ - if (imask & (1UL << 31)) - { - rtx insn, t; - - mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset)); - set_mem_alias_set (mem, alpha_sr_alias_set); - insn = emit_move_insn (mem, const0_rtx); - - RTX_FRAME_RELATED_P (insn) = 1; - t = gen_rtx_REG (Pmode, 31); - t = gen_rtx_SET (VOIDmode, mem, t); - t = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, t, REG_NOTES (insn)); - REG_NOTES (insn) = t; - - reg_offset += 8; - } - for (i = 0; i < 31; i++) if (fmask & (1UL << i)) { - mem = gen_rtx_MEM (DFmode, plus_constant (sa_reg, reg_offset)); - set_mem_alias_set (mem, alpha_sr_alias_set); - FRP (emit_move_insn (mem, gen_rtx_REG (DFmode, i+32))); + emit_frame_store (i+32, sa_reg, sa_bias, reg_offset); reg_offset += 8; } } @@ -7307,19 +7342,13 @@ alpha_expand_prologue (void) for (i = 9; i < 15; i++) if (imask & (1UL << i)) { - mem = gen_rtx_MEM (DImode, plus_constant(hard_frame_pointer_rtx, - reg_offset)); - set_mem_alias_set (mem, alpha_sr_alias_set); - FRP (emit_move_insn (mem, gen_rtx_REG (DImode, i))); + emit_frame_store (i, hard_frame_pointer_rtx, 0, reg_offset); reg_offset -= 8; } for (i = 2; i < 10; i++) if (fmask & (1UL << i)) { - mem = gen_rtx_MEM (DFmode, plus_constant (hard_frame_pointer_rtx, - reg_offset)); - set_mem_alias_set (mem, alpha_sr_alias_set); - FRP (emit_move_insn (mem, gen_rtx_REG (DFmode, i+32))); + emit_frame_store (i+32, hard_frame_pointer_rtx, 0, reg_offset); reg_offset -= 8; } } @@ -7713,9 +7742,6 @@ alpha_expand_epilogue (void) reg_offset += 8; } - if (imask & (1UL << 31)) - reg_offset += 8; - for (i = 0; i < 31; ++i) if (fmask & (1UL << i)) { @@ -10215,6 +10241,8 @@ alpha_init_libfuncs (void) #define TARGET_FUNCTION_OK_FOR_SIBCALL alpha_function_ok_for_sibcall #undef TARGET_CANNOT_COPY_INSN_P #define TARGET_CANNOT_COPY_INSN_P alpha_cannot_copy_insn_p +#undef TARGET_CANNOT_FORCE_CONST_MEM +#define TARGET_CANNOT_FORCE_CONST_MEM alpha_cannot_force_const_mem #if TARGET_ABI_OSF #undef TARGET_ASM_OUTPUT_MI_THUNK @@ -10257,4 +10285,3 @@ struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-alpha.h" - diff --git a/contrib/gcc/config/i386/i386.md b/contrib/gcc/config/i386/i386.md index a190d23..93d9dcd 100644 --- a/contrib/gcc/config/i386/i386.md +++ b/contrib/gcc/config/i386/i386.md @@ -1261,10 +1261,9 @@ "" "xchg{l}\t%1, %0" [(set_attr "type" "imov") + (set_attr "mode" "SI") (set_attr "pent_pair" "np") (set_attr "athlon_decode" "vector") - (set_attr "mode" "SI") - (set_attr "modrm" "0") (set_attr "ppro_uops" "few")]) (define_expand "movhi" @@ -1377,12 +1376,12 @@ (match_operand:HI 1 "register_operand" "+r")) (set (match_dup 1) (match_dup 0))] - "TARGET_PARTIAL_REG_STALL" - "xchg{w}\t%1, %0" + "!TARGET_PARTIAL_REG_STALL || optimize_size" + "xchg{l}\t%k1, %k0" [(set_attr "type" "imov") + (set_attr "mode" "SI") (set_attr "pent_pair" "np") - (set_attr "mode" "HI") - (set_attr "modrm" "0") + (set_attr "athlon_decode" "vector") (set_attr "ppro_uops" "few")]) (define_insn "*swaphi_2" @@ -1390,12 +1389,12 @@ (match_operand:HI 1 "register_operand" "+r")) (set (match_dup 1) (match_dup 0))] - "! TARGET_PARTIAL_REG_STALL" - "xchg{l}\t%k1, %k0" + "TARGET_PARTIAL_REG_STALL" + "xchg{w}\t%1, %0" [(set_attr "type" "imov") + (set_attr "mode" "HI") (set_attr "pent_pair" "np") - (set_attr "mode" "SI") - (set_attr "modrm" "0") + (set_attr "athlon_decode" "vector") (set_attr "ppro_uops" "few")]) (define_expand "movstricthi" @@ -1543,17 +1542,30 @@ DONE; }) -(define_insn "*swapqi" +(define_insn "*swapqi_1" [(set (match_operand:QI 0 "register_operand" "+r") (match_operand:QI 1 "register_operand" "+r")) (set (match_dup 1) (match_dup 0))] - "" - "xchg{b}\t%1, %0" + "!TARGET_PARTIAL_REG_STALL || optimize_size" + "xchg{l}\t%k1, %k0" [(set_attr "type" "imov") + (set_attr "mode" "SI") (set_attr "pent_pair" "np") + (set_attr "athlon_decode" "vector") + (set_attr "ppro_uops" "few")]) + +(define_insn "*swapqi_2" + [(set (match_operand:QI 0 "register_operand" "+q") + (match_operand:QI 1 "register_operand" "+q")) + (set (match_dup 1) + (match_dup 0))] + "TARGET_PARTIAL_REG_STALL" + "xchg{b}\t%1, %0" + [(set_attr "type" "imov") (set_attr "mode" "QI") - (set_attr "modrm" "0") + (set_attr "pent_pair" "np") + (set_attr "athlon_decode" "vector") (set_attr "ppro_uops" "few")]) (define_expand "movstrictqi" @@ -2108,13 +2120,11 @@ "TARGET_64BIT" "xchg{q}\t%1, %0" [(set_attr "type" "imov") + (set_attr "mode" "DI") (set_attr "pent_pair" "np") (set_attr "athlon_decode" "vector") - (set_attr "mode" "DI") - (set_attr "modrm" "0") (set_attr "ppro_uops" "few")]) - (define_expand "movsf" [(set (match_operand:SF 0 "nonimmediate_operand" "") (match_operand:SF 1 "general_operand" ""))] @@ -6314,9 +6324,13 @@ } } [(set (attr "type") - (if_then_else (match_operand:QI 2 "incdec_operand" "") + (if_then_else (match_operand:QI 1 "incdec_operand" "") (const_string "incdec") (const_string "alu1"))) + (set (attr "memory") + (if_then_else (match_operand 1 "memory_operand" "") + (const_string "load") + (const_string "none"))) (set_attr "mode" "QI")]) (define_insn "*addqi_2" @@ -7872,18 +7886,21 @@ "" "") -(define_insn "*testqi_1" +(define_insn "*testqi_1_maybe_si" [(set (reg 17) - (compare (and:QI (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm,r") - (match_operand:QI 1 "general_operand" "n,n,qn,n")) - (const_int 0)))] - "ix86_match_ccmode (insn, CCNOmode) - && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" + (compare + (and:QI + (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm,r") + (match_operand:QI 1 "general_operand" "n,n,qn,n")) + (const_int 0)))] + "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) + && ix86_match_ccmode (insn, + GET_CODE (operands[1]) == CONST_INT + && INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode)" { if (which_alternative == 3) { - if (GET_CODE (operands[1]) == CONST_INT - && (INTVAL (operands[1]) & 0xffffff00)) + if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) < 0) operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff); return "test{l}\t{%1, %k0|%k0, %1}"; } @@ -7894,6 +7911,21 @@ (set_attr "mode" "QI,QI,QI,SI") (set_attr "pent_pair" "uv,np,uv,np")]) +(define_insn "*testqi_1" + [(set (reg 17) + (compare + (and:QI + (match_operand:QI 0 "nonimmediate_operand" "%!*a,q,qm") + (match_operand:QI 1 "general_operand" "n,n,qn")) + (const_int 0)))] + "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) + && ix86_match_ccmode (insn, CCNOmode)" + "test{b}\t{%1, %0|%0, %1}" + [(set_attr "type" "test") + (set_attr "modrm" "0,1,1") + (set_attr "mode" "QI") + (set_attr "pent_pair" "uv,np,uv")]) + (define_expand "testqi_ext_ccno_0" [(set (reg:CCNO 17) (compare:CCNO @@ -8012,51 +8044,53 @@ "#") (define_split - [(set (reg 17) - (compare (zero_extract - (match_operand 0 "nonimmediate_operand" "") - (match_operand 1 "const_int_operand" "") - (match_operand 2 "const_int_operand" "")) - (const_int 0)))] + [(set (match_operand 0 "flags_reg_operand" "") + (match_operator 1 "compare_operator" + [(zero_extract + (match_operand 2 "nonimmediate_operand" "") + (match_operand 3 "const_int_operand" "") + (match_operand 4 "const_int_operand" "")) + (const_int 0)]))] "ix86_match_ccmode (insn, CCNOmode)" - [(set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))] + [(set (match_dup 0) (match_op_dup 1 [(match_dup 2) (const_int 0)]))] { - HOST_WIDE_INT len = INTVAL (operands[1]); - HOST_WIDE_INT pos = INTVAL (operands[2]); + rtx val = operands[2]; + HOST_WIDE_INT len = INTVAL (operands[3]); + HOST_WIDE_INT pos = INTVAL (operands[4]); HOST_WIDE_INT mask; enum machine_mode mode, submode; - mode = GET_MODE (operands[0]); - if (GET_CODE (operands[0]) == MEM) + mode = GET_MODE (val); + if (GET_CODE (val) == MEM) { /* ??? Combine likes to put non-volatile mem extractions in QImode no matter the size of the test. So find a mode that works. */ - if (! MEM_VOLATILE_P (operands[0])) + if (! MEM_VOLATILE_P (val)) { mode = smallest_mode_for_size (pos + len, MODE_INT); - operands[0] = adjust_address (operands[0], mode, 0); + val = adjust_address (val, mode, 0); } } - else if (GET_CODE (operands[0]) == SUBREG - && (submode = GET_MODE (SUBREG_REG (operands[0])), + else if (GET_CODE (val) == SUBREG + && (submode = GET_MODE (SUBREG_REG (val)), GET_MODE_BITSIZE (mode) > GET_MODE_BITSIZE (submode)) && pos + len <= GET_MODE_BITSIZE (submode)) { /* Narrow a paradoxical subreg to prevent partial register stalls. */ mode = submode; - operands[0] = SUBREG_REG (operands[0]); + val = SUBREG_REG (val); } else if (mode == HImode && pos + len <= 8) { /* Small HImode tests can be converted to QImode. */ mode = QImode; - operands[0] = gen_lowpart (QImode, operands[0]); + val = gen_lowpart (QImode, val); } mask = ((HOST_WIDE_INT)1 << (pos + len)) - 1; mask &= ~(((HOST_WIDE_INT)1 << pos) - 1); - operands[3] = gen_rtx_AND (mode, operands[0], gen_int_mode (mask, mode)); + operands[2] = gen_rtx_AND (mode, val, gen_int_mode (mask, mode)); }) ;; Convert HImode/SImode test instructions with immediate to QImode ones. @@ -8065,46 +8099,44 @@ ;; Do the conversion only post-reload to avoid limiting of the register class ;; to QI regs. (define_split - [(set (reg 17) - (compare - (and (match_operand 0 "register_operand" "") - (match_operand 1 "const_int_operand" "")) - (const_int 0)))] + [(set (match_operand 0 "flags_reg_operand" "") + (match_operator 1 "compare_operator" + [(and (match_operand 2 "register_operand" "") + (match_operand 3 "const_int_operand" "")) + (const_int 0)]))] "reload_completed - && QI_REG_P (operands[0]) + && QI_REG_P (operands[2]) + && GET_MODE (operands[2]) != QImode && ((ix86_match_ccmode (insn, CCZmode) - && !(INTVAL (operands[1]) & ~(255 << 8))) + && !(INTVAL (operands[3]) & ~(255 << 8))) || (ix86_match_ccmode (insn, CCNOmode) - && !(INTVAL (operands[1]) & ~(127 << 8)))) - && GET_MODE (operands[0]) != QImode" - [(set (reg:CCNO 17) - (compare:CCNO - (and:SI (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8)) - (match_dup 1)) - (const_int 0)))] - "operands[0] = gen_lowpart (SImode, operands[0]); - operands[1] = gen_int_mode (INTVAL (operands[1]) >> 8, SImode);") + && !(INTVAL (operands[3]) & ~(127 << 8))))" + [(set (match_dup 0) + (match_op_dup 1 + [(and:SI (zero_extract:SI (match_dup 2) (const_int 8) (const_int 8)) + (match_dup 3)) + (const_int 0)]))] + "operands[2] = gen_lowpart (SImode, operands[2]); + operands[3] = gen_int_mode (INTVAL (operands[3]) >> 8, SImode);") (define_split - [(set (reg 17) - (compare - (and (match_operand 0 "nonimmediate_operand" "") - (match_operand 1 "const_int_operand" "")) - (const_int 0)))] + [(set (match_operand 0 "flags_reg_operand" "") + (match_operator 1 "compare_operator" + [(and (match_operand 2 "nonimmediate_operand" "") + (match_operand 3 "const_int_operand" "")) + (const_int 0)]))] "reload_completed - && (!REG_P (operands[0]) || ANY_QI_REG_P (operands[0])) + && GET_MODE (operands[2]) != QImode + && (!REG_P (operands[2]) || ANY_QI_REG_P (operands[2])) && ((ix86_match_ccmode (insn, CCZmode) - && !(INTVAL (operands[1]) & ~255)) + && !(INTVAL (operands[3]) & ~255)) || (ix86_match_ccmode (insn, CCNOmode) - && !(INTVAL (operands[1]) & ~127))) - && GET_MODE (operands[0]) != QImode" - [(set (reg:CCNO 17) - (compare:CCNO - (and:QI (match_dup 0) - (match_dup 1)) - (const_int 0)))] - "operands[0] = gen_lowpart (QImode, operands[0]); - operands[1] = gen_lowpart (QImode, operands[1]);") + && !(INTVAL (operands[3]) & ~127)))" + [(set (match_dup 0) + (match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3)) + (const_int 0)]))] + "operands[2] = gen_lowpart (QImode, operands[2]); + operands[3] = gen_lowpart (QImode, operands[3]);") ;; %%% This used to optimize known byte-wide and operations to memory, @@ -8381,21 +8413,22 @@ [(set_attr "type" "alu1") (set_attr "mode" "QI")]) -(define_insn "*andqi_2" +(define_insn "*andqi_2_maybe_si" [(set (reg 17) (compare (and:QI - (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") - (match_operand:QI 2 "general_operand" "qim,qi,i")) + (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") + (match_operand:QI 2 "general_operand" "qim,qi,i")) (const_int 0))) (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm,*r") (and:QI (match_dup 1) (match_dup 2)))] - "ix86_match_ccmode (insn, CCNOmode) - && ix86_binary_operator_ok (AND, QImode, operands)" + "ix86_binary_operator_ok (AND, QImode, operands) + && ix86_match_ccmode (insn, + GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) >= 0 ? CCNOmode : CCZmode)" { if (which_alternative == 2) { - if (GET_CODE (operands[2]) == CONST_INT - && (INTVAL (operands[2]) & 0xffffff00)) + if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff); return "and{l}\t{%2, %k0|%k0, %2}"; } @@ -8404,6 +8437,20 @@ [(set_attr "type" "alu") (set_attr "mode" "QI,QI,SI")]) +(define_insn "*andqi_2" + [(set (reg 17) + (compare (and:QI + (match_operand:QI 1 "nonimmediate_operand" "%0,0") + (match_operand:QI 2 "general_operand" "qim,qi")) + (const_int 0))) + (set (match_operand:QI 0 "nonimmediate_operand" "=q,qm") + (and:QI (match_dup 1) (match_dup 2)))] + "ix86_match_ccmode (insn, CCNOmode) + && ix86_binary_operator_ok (AND, QImode, operands)" + "and{b}\t{%2, %0|%0, %2}" + [(set_attr "type" "alu") + (set_attr "mode" "QI")]) + (define_insn "*andqi_2_slp" [(set (reg 17) (compare (and:QI @@ -9567,8 +9614,8 @@ [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") (neg:SF (match_operand:SF 1 "nonimmediate_operand" ""))) (clobber (reg:CC 17))])] - "TARGET_80387" - "if (TARGET_SSE) + "TARGET_80387 || TARGET_SSE_MATH" + "if (TARGET_SSE_MATH) { /* In case operand is in memory, we will not use SSE. */ if (memory_operand (operands[0], VOIDmode) @@ -9641,12 +9688,12 @@ (use (match_operand:V4SF 2 "nonimmediate_operand" "")) (clobber (reg:CC 17))] "reload_completed && SSE_REG_P (operands[0])" - [(set (subreg:TI (match_dup 0) 0) - (xor:TI (match_dup 1) - (match_dup 2)))] + [(set (match_dup 0) + (xor:V4SF (match_dup 1) + (match_dup 2)))] { - operands[1] = simplify_gen_subreg (TImode, operands[1], SFmode, 0); - operands[2] = simplify_gen_subreg (TImode, operands[2], V4SFmode, 0); + operands[0] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0); + operands[1] = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0); if (operands_match_p (operands[0], operands[2])) { rtx tmp; @@ -9664,7 +9711,7 @@ [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f") (neg:SF (match_operand:SF 1 "nonimmediate_operand" "0,0"))) (clobber (reg:CC 17))] - "TARGET_80387 && !TARGET_SSE + "TARGET_80387 && ix86_unary_operator_ok (NEG, SFmode, operands)" "#") @@ -9707,8 +9754,8 @@ [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "") (neg:DF (match_operand:DF 1 "nonimmediate_operand" ""))) (clobber (reg:CC 17))])] - "TARGET_80387" - "if (TARGET_SSE2) + "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)" + "if (TARGET_SSE2 && TARGET_SSE_MATH) { /* In case operand is in memory, we will not use SSE. */ if (memory_operand (operands[0], VOIDmode) @@ -9809,13 +9856,12 @@ (use (match_operand:V2DF 2 "nonimmediate_operand" "")) (clobber (reg:CC 17))] "reload_completed && SSE_REG_P (operands[0])" - [(set (subreg:TI (match_dup 0) 0) - (xor:TI (match_dup 1) - (match_dup 2)))] + [(set (match_dup 0) + (xor:V2DF (match_dup 1) + (match_dup 2)))] { operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0); - operands[1] = simplify_gen_subreg (TImode, operands[1], DFmode, 0); - operands[2] = simplify_gen_subreg (TImode, operands[2], V2DFmode, 0); + operands[1] = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0); /* Avoid possible reformatting on the operands. */ if (TARGET_SSE_PARTIAL_REGS && !optimize_size) emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0])); @@ -9974,8 +10020,8 @@ [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") (neg:SF (match_operand:SF 1 "nonimmediate_operand" ""))) (clobber (reg:CC 17))])] - "TARGET_80387" - "if (TARGET_SSE) + "TARGET_80387 || TARGET_SSE_MATH" + "if (TARGET_SSE_MATH) { /* In case operand is in memory, we will not use SSE. */ if (memory_operand (operands[0], VOIDmode) @@ -10049,12 +10095,12 @@ (use (match_operand:V4SF 2 "nonimmediate_operand" "")) (clobber (reg:CC 17))] "reload_completed && SSE_REG_P (operands[0])" - [(set (subreg:TI (match_dup 0) 0) - (and:TI (match_dup 1) - (match_dup 2)))] + [(set (match_dup 0) + (and:V4SF (match_dup 1) + (match_dup 2)))] { - operands[1] = simplify_gen_subreg (TImode, operands[1], SFmode, 0); - operands[2] = simplify_gen_subreg (TImode, operands[2], V4SFmode, 0); + operands[0] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0); + operands[1] = simplify_gen_subreg (V4SFmode, operands[1], SFmode, 0); if (operands_match_p (operands[0], operands[2])) { rtx tmp; @@ -10071,7 +10117,7 @@ [(set (match_operand:SF 0 "nonimmediate_operand" "=f#r,rm#f") (abs:SF (match_operand:SF 1 "nonimmediate_operand" "0,0"))) (clobber (reg:CC 17))] - "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands) && !TARGET_SSE" + "TARGET_80387 && ix86_unary_operator_ok (ABS, SFmode, operands)" "#") (define_split @@ -10113,8 +10159,8 @@ [(parallel [(set (match_operand:DF 0 "nonimmediate_operand" "") (neg:DF (match_operand:DF 1 "nonimmediate_operand" ""))) (clobber (reg:CC 17))])] - "TARGET_80387" - "if (TARGET_SSE2) + "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)" + "if (TARGET_SSE2 && TARGET_SSE_MATH) { /* In case operand is in memory, we will not use SSE. */ if (memory_operand (operands[0], VOIDmode) @@ -10203,13 +10249,12 @@ (use (match_operand:V2DF 2 "nonimmediate_operand" "")) (clobber (reg:CC 17))] "reload_completed && SSE_REG_P (operands[0])" - [(set (subreg:TI (match_dup 0) 0) - (and:TI (match_dup 1) - (match_dup 2)))] + [(set (match_dup 0) + (and:V2DF (match_dup 1) + (match_dup 2)))] { operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0); - operands[1] = simplify_gen_subreg (TImode, operands[1], DFmode, 0); - operands[2] = simplify_gen_subreg (TImode, operands[2], V2DFmode, 0); + operands[1] = simplify_gen_subreg (V2DFmode, operands[1], DFmode, 0); /* Avoid possible reformatting on the operands. */ if (TARGET_SSE_PARTIAL_REGS && !optimize_size) emit_insn (gen_sse2_unpcklpd (operands[0], operands[0], operands[0])); @@ -10383,17 +10428,19 @@ (set_attr "mode" "DI")]) (define_split - [(set (reg 17) - (compare (not:DI (match_operand:DI 1 "nonimmediate_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "nonimmediate_operand" "") - (not:DI (match_dup 1)))] + [(set (match_operand 0 "flags_reg_operand" "") + (match_operator 2 "compare_operator" + [(not:DI (match_operand:DI 3 "nonimmediate_operand" "")) + (const_int 0)])) + (set (match_operand:DI 1 "nonimmediate_operand" "") + (not:DI (match_dup 3)))] "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)" - [(parallel [(set (reg:CCNO 17) - (compare:CCNO (xor:DI (match_dup 1) (const_int -1)) - (const_int 0))) - (set (match_dup 0) - (xor:DI (match_dup 1) (const_int -1)))])] + [(parallel [(set (match_dup 0) + (match_op_dup 2 + [(xor:DI (match_dup 3) (const_int -1)) + (const_int 0)])) + (set (match_dup 1) + (xor:DI (match_dup 3) (const_int -1)))])] "") (define_expand "one_cmplsi2" @@ -10432,17 +10479,18 @@ (set_attr "mode" "SI")]) (define_split - [(set (reg 17) - (compare (not:SI (match_operand:SI 1 "nonimmediate_operand" "")) - (const_int 0))) - (set (match_operand:SI 0 "nonimmediate_operand" "") - (not:SI (match_dup 1)))] + [(set (match_operand 0 "flags_reg_operand" "") + (match_operator 2 "compare_operator" + [(not:SI (match_operand:SI 3 "nonimmediate_operand" "")) + (const_int 0)])) + (set (match_operand:SI 1 "nonimmediate_operand" "") + (not:SI (match_dup 3)))] "ix86_match_ccmode (insn, CCNOmode)" - [(parallel [(set (reg:CCNO 17) - (compare:CCNO (xor:SI (match_dup 1) (const_int -1)) - (const_int 0))) - (set (match_dup 0) - (xor:SI (match_dup 1) (const_int -1)))])] + [(parallel [(set (match_dup 0) + (match_op_dup 2 [(xor:SI (match_dup 3) (const_int -1)) + (const_int 0)])) + (set (match_dup 1) + (xor:SI (match_dup 3) (const_int -1)))])] "") ;; ??? Currently never generated - xor is used instead. @@ -10459,17 +10507,18 @@ (set_attr "mode" "SI")]) (define_split - [(set (reg 17) - (compare (not:SI (match_operand:SI 1 "register_operand" "")) - (const_int 0))) - (set (match_operand:DI 0 "register_operand" "") - (zero_extend:DI (not:SI (match_dup 1))))] + [(set (match_operand 0 "flags_reg_operand" "") + (match_operator 2 "compare_operator" + [(not:SI (match_operand:SI 3 "register_operand" "")) + (const_int 0)])) + (set (match_operand:DI 1 "register_operand" "") + (zero_extend:DI (not:SI (match_dup 3))))] "ix86_match_ccmode (insn, CCNOmode)" - [(parallel [(set (reg:CCNO 17) - (compare:CCNO (xor:SI (match_dup 1) (const_int -1)) - (const_int 0))) - (set (match_dup 0) - (zero_extend:DI (xor:SI (match_dup 1) (const_int -1))))])] + [(parallel [(set (match_dup 0) + (match_op_dup 2 [(xor:SI (match_dup 3) (const_int -1)) + (const_int 0)])) + (set (match_dup 1) + (zero_extend:DI (xor:SI (match_dup 3) (const_int -1))))])] "") (define_expand "one_cmplhi2" @@ -10499,17 +10548,18 @@ (set_attr "mode" "HI")]) (define_split - [(set (reg 17) - (compare (not:HI (match_operand:HI 1 "nonimmediate_operand" "")) - (const_int 0))) - (set (match_operand:HI 0 "nonimmediate_operand" "") - (not:HI (match_dup 1)))] + [(set (match_operand 0 "flags_reg_operand" "") + (match_operator 2 "compare_operator" + [(not:HI (match_operand:HI 3 "nonimmediate_operand" "")) + (const_int 0)])) + (set (match_operand:HI 1 "nonimmediate_operand" "") + (not:HI (match_dup 3)))] "ix86_match_ccmode (insn, CCNOmode)" - [(parallel [(set (reg:CCNO 17) - (compare:CCNO (xor:HI (match_dup 1) (const_int -1)) - (const_int 0))) - (set (match_dup 0) - (xor:HI (match_dup 1) (const_int -1)))])] + [(parallel [(set (match_dup 0) + (match_op_dup 2 [(xor:HI (match_dup 3) (const_int -1)) + (const_int 0)])) + (set (match_dup 1) + (xor:HI (match_dup 3) (const_int -1)))])] "") ;; %%% Potential partial reg stall on alternative 1. What to do? @@ -10542,17 +10592,18 @@ (set_attr "mode" "QI")]) (define_split - [(set (reg 17) - (compare (not:QI (match_operand:QI 1 "nonimmediate_operand" "")) - (const_int 0))) - (set (match_operand:QI 0 "nonimmediate_operand" "") - (not:QI (match_dup 1)))] + [(set (match_operand 0 "flags_reg_operand" "") + (match_operator 2 "compare_operator" + [(not:QI (match_operand:QI 3 "nonimmediate_operand" "")) + (const_int 0)])) + (set (match_operand:QI 1 "nonimmediate_operand" "") + (not:QI (match_dup 3)))] "ix86_match_ccmode (insn, CCNOmode)" - [(parallel [(set (reg:CCNO 17) - (compare:CCNO (xor:QI (match_dup 1) (const_int -1)) - (const_int 0))) - (set (match_dup 0) - (xor:QI (match_dup 1) (const_int -1)))])] + [(parallel [(set (match_dup 0) + (match_op_dup 2 [(xor:QI (match_dup 3) (const_int -1)) + (const_int 0)])) + (set (match_dup 1) + (xor:QI (match_dup 3) (const_int -1)))])] "") ;; Arithmetic shift instructions @@ -17003,7 +17054,8 @@ (clobber (match_operand 6 "" "")) (clobber (reg:CC 17))] "!SSE_REG_P (operands[0]) && reload_completed - && VALID_SSE_REG_MODE (GET_MODE (operands[0]))" + && (GET_MODE (operands[0]) == SFmode + || (TARGET_SSE2 && GET_MODE (operands[0]) == DFmode))" [(const_int 0)] { ix86_compare_op0 = operands[5]; @@ -17020,22 +17072,60 @@ ;; nand op0, op3 - load op3 to op0 if comparison was false ;; or op2, op0 - get the nonzero one into the result. (define_split - [(set (match_operand 0 "register_operand" "") - (if_then_else (match_operator 1 "sse_comparison_operator" - [(match_operand 4 "register_operand" "") - (match_operand 5 "nonimmediate_operand" "")]) - (match_operand 2 "register_operand" "") - (match_operand 3 "register_operand" ""))) + [(set (match_operand:SF 0 "register_operand" "") + (if_then_else:SF (match_operator 1 "sse_comparison_operator" + [(match_operand:SF 4 "register_operand" "") + (match_operand:SF 5 "nonimmediate_operand" "")]) + (match_operand:SF 2 "register_operand" "") + (match_operand:SF 3 "register_operand" ""))) (clobber (match_operand 6 "" "")) (clobber (reg:CC 17))] "SSE_REG_P (operands[0]) && reload_completed" [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)])) - (set (subreg:TI (match_dup 2) 0) (and:TI (subreg:TI (match_dup 2) 0) - (subreg:TI (match_dup 4) 0))) - (set (subreg:TI (match_dup 4) 0) (and:TI (not:TI (subreg:TI (match_dup 4) 0)) - (subreg:TI (match_dup 3) 0))) - (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0) - (subreg:TI (match_dup 7) 0)))] + (set (match_dup 2) (and:V4SF (match_dup 2) + (match_dup 8))) + (set (match_dup 8) (and:V4SF (not:V4SF (match_dup 8)) + (match_dup 3))) + (set (match_dup 0) (ior:V4SF (match_dup 6) + (match_dup 7)))] +{ + /* If op2 == op3, op3 would be clobbered before it is used. */ + if (operands_match_p (operands[2], operands[3])) + { + emit_move_insn (operands[0], operands[2]); + DONE; + } + + PUT_MODE (operands[1], GET_MODE (operands[0])); + if (operands_match_p (operands[0], operands[4])) + operands[6] = operands[4], operands[7] = operands[2]; + else + operands[6] = operands[2], operands[7] = operands[4]; + operands[0] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0); + operands[2] = simplify_gen_subreg (V4SFmode, operands[2], SFmode, 0); + operands[3] = simplify_gen_subreg (V4SFmode, operands[3], SFmode, 0); + operands[8] = simplify_gen_subreg (V4SFmode, operands[4], SFmode, 0); + operands[6] = simplify_gen_subreg (V4SFmode, operands[6], SFmode, 0); + operands[7] = simplify_gen_subreg (V4SFmode, operands[7], SFmode, 0); +}) + +(define_split + [(set (match_operand:DF 0 "register_operand" "") + (if_then_else:DF (match_operator 1 "sse_comparison_operator" + [(match_operand:DF 4 "register_operand" "") + (match_operand:DF 5 "nonimmediate_operand" "")]) + (match_operand:DF 2 "register_operand" "") + (match_operand:DF 3 "register_operand" ""))) + (clobber (match_operand 6 "" "")) + (clobber (reg:CC 17))] + "SSE_REG_P (operands[0]) && reload_completed" + [(set (match_dup 4) (match_op_dup 1 [(match_dup 4) (match_dup 5)])) + (set (match_dup 2) (and:V2DF (match_dup 2) + (match_dup 8))) + (set (match_dup 8) (and:V2DF (not:V2DF (match_dup 8)) + (match_dup 3))) + (set (match_dup 0) (ior:V2DF (match_dup 6) + (match_dup 7)))] { if (GET_MODE (operands[2]) == DFmode && TARGET_SSE_PARTIAL_REGS && !optimize_size) @@ -17058,6 +17148,12 @@ operands[6] = operands[4], operands[7] = operands[2]; else operands[6] = operands[2], operands[7] = operands[4]; + operands[0] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0); + operands[2] = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0); + operands[3] = simplify_gen_subreg (V2DFmode, operands[3], DFmode, 0); + operands[8] = simplify_gen_subreg (V2DFmode, operands[4], DFmode, 0); + operands[6] = simplify_gen_subreg (V2DFmode, operands[6], DFmode, 0); + operands[7] = simplify_gen_subreg (V2DFmode, operands[7], DFmode, 0); }) ;; Special case of conditional move we can handle effectively. @@ -17144,18 +17240,55 @@ "#") (define_split - [(set (match_operand 0 "register_operand" "") - (if_then_else (match_operator 1 "comparison_operator" - [(match_operand 4 "nonimmediate_operand" "") - (match_operand 5 "nonimmediate_operand" "")]) - (match_operand 2 "nonmemory_operand" "") - (match_operand 3 "nonmemory_operand" "")))] + [(set (match_operand:SF 0 "register_operand" "") + (if_then_else:SF (match_operator 1 "comparison_operator" + [(match_operand:SF 4 "nonimmediate_operand" "") + (match_operand:SF 5 "nonimmediate_operand" "")]) + (match_operand:SF 2 "nonmemory_operand" "") + (match_operand:SF 3 "nonmemory_operand" "")))] "SSE_REG_P (operands[0]) && reload_completed && (const0_operand (operands[2], GET_MODE (operands[0])) || const0_operand (operands[3], GET_MODE (operands[0])))" [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)])) - (set (subreg:TI (match_dup 0) 0) (and:TI (match_dup 6) - (match_dup 7)))] + (set (match_dup 8) (and:V4SF (match_dup 6) (match_dup 7)))] +{ + PUT_MODE (operands[1], GET_MODE (operands[0])); + if (!sse_comparison_operator (operands[1], VOIDmode) + || !rtx_equal_p (operands[0], operands[4])) + { + rtx tmp = operands[5]; + operands[5] = operands[4]; + operands[4] = tmp; + PUT_CODE (operands[1], swap_condition (GET_CODE (operands[1]))); + } + if (!rtx_equal_p (operands[0], operands[4])) + abort (); + operands[8] = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0); + if (const0_operand (operands[2], GET_MODE (operands[2]))) + { + operands[7] = operands[3]; + operands[6] = gen_rtx_NOT (V4SFmode, operands[5]); + } + else + { + operands[7] = operands[2]; + operands[6] = operands[8]; + } + operands[7] = simplify_gen_subreg (V4SFmode, operands[7], SFmode, 0); +}) + +(define_split + [(set (match_operand:DF 0 "register_operand" "") + (if_then_else:DF (match_operator 1 "comparison_operator" + [(match_operand:DF 4 "nonimmediate_operand" "") + (match_operand:DF 5 "nonimmediate_operand" "")]) + (match_operand:DF 2 "nonmemory_operand" "") + (match_operand:DF 3 "nonmemory_operand" "")))] + "SSE_REG_P (operands[0]) && reload_completed + && (const0_operand (operands[2], GET_MODE (operands[0])) + || const0_operand (operands[3], GET_MODE (operands[0])))" + [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)])) + (set (match_dup 8) (and:V2DF (match_dup 6) (match_dup 7)))] { if (TARGET_SSE_PARTIAL_REGS && !optimize_size && GET_MODE (operands[2]) == DFmode) @@ -17182,19 +17315,18 @@ } if (!rtx_equal_p (operands[0], operands[4])) abort (); - if (const0_operand (operands[2], GET_MODE (operands[0]))) + operands[8] = simplify_gen_subreg (V2DFmode, operands[0], DFmode, 0); + if (const0_operand (operands[2], GET_MODE (operands[2]))) { operands[7] = operands[3]; - operands[6] = gen_rtx_NOT (TImode, gen_rtx_SUBREG (TImode, operands[0], - 0)); + operands[6] = gen_rtx_NOT (V2DFmode, operands[8]); } else { operands[7] = operands[2]; - operands[6] = gen_rtx_SUBREG (TImode, operands[0], 0); + operands[6] = operands[8]; } - operands[7] = simplify_gen_subreg (TImode, operands[7], - GET_MODE (operands[7]), 0); + operands[7] = simplify_gen_subreg (V2DFmode, operands[7], DFmode, 0); }) (define_expand "allocate_stack_worker" @@ -17319,52 +17451,56 @@ ; instruction size is unchanged, except in the %eax case for ; which it is increased by one byte, hence the ! optimize_size. (define_split - [(set (reg 17) - (compare (and (match_operand 1 "aligned_operand" "") - (match_operand 2 "const_int_operand" "")) - (const_int 0))) - (set (match_operand 0 "register_operand" "") - (and (match_dup 1) (match_dup 2)))] + [(set (match_operand 0 "flags_reg_operand" "") + (match_operator 2 "compare_operator" + [(and (match_operand 3 "aligned_operand" "") + (match_operand 4 "const_int_operand" "")) + (const_int 0)])) + (set (match_operand 1 "register_operand" "") + (and (match_dup 3) (match_dup 4)))] "! TARGET_PARTIAL_REG_STALL && reload_completed /* Ensure that the operand will remain sign-extended immediate. */ - && ix86_match_ccmode (insn, INTVAL (operands[2]) >= 0 ? CCNOmode : CCZmode) + && ix86_match_ccmode (insn, INTVAL (operands[4]) >= 0 ? CCNOmode : CCZmode) && ! optimize_size - && ((GET_MODE (operands[0]) == HImode && ! TARGET_FAST_PREFIX) - || (GET_MODE (operands[0]) == QImode && TARGET_PROMOTE_QImode))" - [(parallel [(set (reg:CCNO 17) - (compare:CCNO (and:SI (match_dup 1) (match_dup 2)) - (const_int 0))) - (set (match_dup 0) - (and:SI (match_dup 1) (match_dup 2)))])] - "operands[2] - = gen_int_mode (INTVAL (operands[2]) - & GET_MODE_MASK (GET_MODE (operands[0])), - SImode); - operands[0] = gen_lowpart (SImode, operands[0]); - operands[1] = gen_lowpart (SImode, operands[1]);") + && ((GET_MODE (operands[1]) == HImode && ! TARGET_FAST_PREFIX) + || (GET_MODE (operands[1]) == QImode && TARGET_PROMOTE_QImode))" + [(parallel [(set (match_dup 0) + (match_op_dup 2 [(and:SI (match_dup 3) (match_dup 4)) + (const_int 0)])) + (set (match_dup 1) + (and:SI (match_dup 3) (match_dup 4)))])] +{ + operands[4] + = gen_int_mode (INTVAL (operands[4]) + & GET_MODE_MASK (GET_MODE (operands[1])), SImode); + operands[1] = gen_lowpart (SImode, operands[1]); + operands[3] = gen_lowpart (SImode, operands[3]); +}) ; Don't promote the QImode tests, as i386 doesn't have encoding of ; the TEST instruction with 32-bit sign-extended immediate and thus ; the instruction size would at least double, which is not what we ; want even with ! optimize_size. (define_split - [(set (reg 17) - (compare (and (match_operand:HI 0 "aligned_operand" "") - (match_operand:HI 1 "const_int_operand" "")) - (const_int 0)))] + [(set (match_operand 0 "flags_reg_operand" "") + (match_operator 1 "compare_operator" + [(and (match_operand:HI 2 "aligned_operand" "") + (match_operand:HI 3 "const_int_operand" "")) + (const_int 0)]))] "! TARGET_PARTIAL_REG_STALL && reload_completed /* Ensure that the operand will remain sign-extended immediate. */ - && ix86_match_ccmode (insn, INTVAL (operands[1]) >= 0 ? CCNOmode : CCZmode) + && ix86_match_ccmode (insn, INTVAL (operands[3]) >= 0 ? CCNOmode : CCZmode) && ! TARGET_FAST_PREFIX && ! optimize_size" - [(set (reg:CCNO 17) - (compare:CCNO (and:SI (match_dup 0) (match_dup 1)) - (const_int 0)))] - "operands[1] - = gen_int_mode (INTVAL (operands[1]) - & GET_MODE_MASK (GET_MODE (operands[0])), - SImode); - operands[0] = gen_lowpart (SImode, operands[0]);") + [(set (match_dup 0) + (match_op_dup 1 [(and:SI (match_dup 2) (match_dup 3)) + (const_int 0)]))] +{ + operands[3] + = gen_int_mode (INTVAL (operands[3]) + & GET_MODE_MASK (GET_MODE (operands[2])), SImode); + operands[2] = gen_lowpart (SImode, operands[2]); +}) (define_split [(set (match_operand 0 "register_operand" "") @@ -17537,13 +17673,14 @@ ;; Don't compare memory with zero, load and use a test instead. (define_peephole2 - [(set (reg 17) - (compare (match_operand:SI 0 "memory_operand" "") - (const_int 0))) + [(set (match_operand 0 "flags_reg_operand" "") + (match_operator 1 "compare_operator" + [(match_operand:SI 2 "memory_operand" "") + (const_int 0)])) (match_scratch:SI 3 "r")] "ix86_match_ccmode (insn, CCNOmode) && ! optimize_size" - [(set (match_dup 3) (match_dup 0)) - (set (reg:CCNO 17) (compare:CCNO (match_dup 3) (const_int 0)))] + [(set (match_dup 3) (match_dup 2)) + (set (match_dup 0) (match_op_dup 1 [(match_dup 3) (const_int 0)]))] "") ;; NOT is not pairable on Pentium, while XOR is, but one byte longer. @@ -17607,77 +17744,77 @@ ;; versions if we're concerned about partial register stalls. (define_peephole2 - [(set (reg 17) - (compare (and:SI (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "immediate_operand" "")) - (const_int 0)))] + [(set (match_operand 0 "flags_reg_operand" "") + (match_operator 1 "compare_operator" + [(and:SI (match_operand:SI 2 "register_operand" "") + (match_operand:SI 3 "immediate_operand" "")) + (const_int 0)]))] "ix86_match_ccmode (insn, CCNOmode) - && (true_regnum (operands[0]) != 0 - || (GET_CODE (operands[1]) == CONST_INT - && CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'K'))) - && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" + && (true_regnum (operands[2]) != 0 + || (GET_CODE (operands[3]) == CONST_INT + && CONST_OK_FOR_LETTER_P (INTVAL (operands[3]), 'K'))) + && peep2_reg_dead_p (1, operands[2])" [(parallel - [(set (reg:CCNO 17) - (compare:CCNO (and:SI (match_dup 0) - (match_dup 1)) - (const_int 0))) - (set (match_dup 0) - (and:SI (match_dup 0) (match_dup 1)))])] + [(set (match_dup 0) + (match_op_dup 1 [(and:SI (match_dup 2) (match_dup 3)) + (const_int 0)])) + (set (match_dup 2) + (and:SI (match_dup 2) (match_dup 3)))])] "") ;; We don't need to handle HImode case, because it will be promoted to SImode ;; on ! TARGET_PARTIAL_REG_STALL (define_peephole2 - [(set (reg 17) - (compare (and:QI (match_operand:QI 0 "register_operand" "") - (match_operand:QI 1 "immediate_operand" "")) - (const_int 0)))] + [(set (match_operand 0 "flags_reg_operand" "") + (match_operator 1 "compare_operator" + [(and:QI (match_operand:QI 2 "register_operand" "") + (match_operand:QI 3 "immediate_operand" "")) + (const_int 0)]))] "! TARGET_PARTIAL_REG_STALL && ix86_match_ccmode (insn, CCNOmode) - && true_regnum (operands[0]) != 0 - && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" + && true_regnum (operands[2]) != 0 + && peep2_reg_dead_p (1, operands[2])" [(parallel - [(set (reg:CCNO 17) - (compare:CCNO (and:QI (match_dup 0) - (match_dup 1)) - (const_int 0))) - (set (match_dup 0) - (and:QI (match_dup 0) (match_dup 1)))])] + [(set (match_dup 0) + (match_op_dup 1 [(and:QI (match_dup 2) (match_dup 3)) + (const_int 0)])) + (set (match_dup 2) + (and:QI (match_dup 2) (match_dup 3)))])] "") (define_peephole2 - [(set (reg 17) - (compare - (and:SI - (zero_extract:SI - (match_operand 0 "ext_register_operand" "") - (const_int 8) - (const_int 8)) - (match_operand 1 "const_int_operand" "")) - (const_int 0)))] + [(set (match_operand 0 "flags_reg_operand" "") + (match_operator 1 "compare_operator" + [(and:SI + (zero_extract:SI + (match_operand 2 "ext_register_operand" "") + (const_int 8) + (const_int 8)) + (match_operand 3 "const_int_operand" "")) + (const_int 0)]))] "! TARGET_PARTIAL_REG_STALL && ix86_match_ccmode (insn, CCNOmode) - && true_regnum (operands[0]) != 0 - && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" - [(parallel [(set (reg:CCNO 17) - (compare:CCNO - (and:SI - (zero_extract:SI - (match_dup 0) - (const_int 8) - (const_int 8)) - (match_dup 1)) - (const_int 0))) - (set (zero_extract:SI (match_dup 0) + && true_regnum (operands[2]) != 0 + && peep2_reg_dead_p (1, operands[2])" + [(parallel [(set (match_dup 0) + (match_op_dup 1 + [(and:SI + (zero_extract:SI + (match_dup 2) + (const_int 8) + (const_int 8)) + (match_dup 3)) + (const_int 0)])) + (set (zero_extract:SI (match_dup 2) (const_int 8) (const_int 8)) (and:SI (zero_extract:SI - (match_dup 0) + (match_dup 2) (const_int 8) (const_int 8)) - (match_dup 1)))])] + (match_dup 3)))])] "") ;; Don't do logical operations with memory inputs. @@ -17979,66 +18116,20 @@ "") ;; Convert compares with 1 to shorter inc/dec operations when CF is not -;; required and register dies. -(define_peephole2 - [(set (reg 17) - (compare (match_operand:SI 0 "register_operand" "") - (match_operand:SI 1 "incdec_operand" "")))] - "ix86_match_ccmode (insn, CCGCmode) - && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" - [(parallel [(set (reg:CCGC 17) - (compare:CCGC (match_dup 0) - (match_dup 1))) - (clobber (match_dup 0))])] - "") - +;; required and register dies. Similarly for 128 to plus -128. (define_peephole2 - [(set (reg 17) - (compare (match_operand:HI 0 "register_operand" "") - (match_operand:HI 1 "incdec_operand" "")))] - "ix86_match_ccmode (insn, CCGCmode) - && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" - [(parallel [(set (reg:CCGC 17) - (compare:CCGC (match_dup 0) - (match_dup 1))) - (clobber (match_dup 0))])] - "") - -(define_peephole2 - [(set (reg 17) - (compare (match_operand:QI 0 "register_operand" "") - (match_operand:QI 1 "incdec_operand" "")))] - "ix86_match_ccmode (insn, CCGCmode) - && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" - [(parallel [(set (reg:CCGC 17) - (compare:CCGC (match_dup 0) - (match_dup 1))) - (clobber (match_dup 0))])] - "") - -;; Convert compares with 128 to shorter add -128 -(define_peephole2 - [(set (reg 17) - (compare (match_operand:SI 0 "register_operand" "") - (const_int 128)))] - "ix86_match_ccmode (insn, CCGCmode) - && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" - [(parallel [(set (reg:CCGC 17) - (compare:CCGC (match_dup 0) - (const_int 128))) - (clobber (match_dup 0))])] - "") - -(define_peephole2 - [(set (reg 17) - (compare (match_operand:HI 0 "register_operand" "") - (const_int 128)))] - "ix86_match_ccmode (insn, CCGCmode) - && find_regno_note (insn, REG_DEAD, true_regnum (operands[0]))" - [(parallel [(set (reg:CCGC 17) - (compare:CCGC (match_dup 0) - (const_int 128))) - (clobber (match_dup 0))])] + [(set (match_operand 0 "flags_reg_operand" "") + (match_operator 1 "compare_operator" + [(match_operand 2 "register_operand" "") + (match_operand 3 "const_int_operand" "")]))] + "(INTVAL (operands[3]) == -1 + || INTVAL (operands[3]) == 1 + || INTVAL (operands[3]) == 128) + && ix86_match_ccmode (insn, CCGCmode) + && peep2_reg_dead_p (1, operands[2])" + [(parallel [(set (match_dup 0) + (match_op_dup 1 [(match_dup 2) (match_dup 3)])) + (clobber (match_dup 2))])] "") (define_peephole2 @@ -18326,7 +18417,7 @@ { if (constant_call_address_operand (operands[1], QImode)) return "call\t%P1"; - return "call\t%*%1"; + return "call\t%A1"; } [(set_attr "type" "callv")]) @@ -18338,7 +18429,7 @@ { if (constant_call_address_operand (operands[1], QImode)) return "jmp\t%P1"; - return "jmp\t%*%1"; + return "jmp\t%A1"; } [(set_attr "type" "callv")]) @@ -18422,10 +18513,11 @@ ;; Moves for SSE/MMX regs. -(define_insn "movv4sf_internal" +(define_insn "*movv4sf_internal" [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m") (match_operand:V4SF 1 "vector_move_operand" "C,xm,x"))] - "TARGET_SSE" + "TARGET_SSE + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "@ xorps\t%0, %0 movaps\t{%1, %0|%0, %1} @@ -18436,7 +18528,7 @@ (define_split [(set (match_operand:V4SF 0 "register_operand" "") (match_operand:V4SF 1 "zero_extended_scalar_load_operand" ""))] - "TARGET_SSE" + "TARGET_SSE && reload_completed" [(set (match_dup 0) (vec_merge:V4SF (vec_duplicate:V4SF (match_dup 1)) @@ -18447,10 +18539,11 @@ operands[2] = CONST0_RTX (V4SFmode); }) -(define_insn "movv4si_internal" +(define_insn "*movv4si_internal" [(set (match_operand:V4SI 0 "nonimmediate_operand" "=x,x,m") (match_operand:V4SI 1 "vector_move_operand" "C,xm,x"))] - "TARGET_SSE" + "TARGET_SSE + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" { switch (which_alternative) { @@ -18487,10 +18580,11 @@ (const_string "TI"))] (const_string "TI")))]) -(define_insn "movv2di_internal" +(define_insn "*movv2di_internal" [(set (match_operand:V2DI 0 "nonimmediate_operand" "=x,x,m") (match_operand:V2DI 1 "vector_move_operand" "C,xm,x"))] - "TARGET_SSE" + "TARGET_SSE + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" { switch (which_alternative) { @@ -18530,7 +18624,7 @@ (define_split [(set (match_operand:V2DF 0 "register_operand" "") (match_operand:V2DF 1 "zero_extended_scalar_load_operand" ""))] - "TARGET_SSE2" + "TARGET_SSE2 && reload_completed" [(set (match_dup 0) (vec_merge:V2DF (vec_duplicate:V2DF (match_dup 1)) @@ -18541,52 +18635,80 @@ operands[2] = CONST0_RTX (V2DFmode); }) -(define_insn "movv8qi_internal" - [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,y,m") - (match_operand:V8QI 1 "vector_move_operand" "C,ym,y"))] +(define_insn "*movv2si_internal" + [(set (match_operand:V2SI 0 "nonimmediate_operand" + "=y,y ,m,!y,!*Y,*x,?*x,?m") + (match_operand:V2SI 1 "vector_move_operand" + "C ,ym,y,*Y,y ,C ,*xm,*x"))] "TARGET_MMX && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "@ pxor\t%0, %0 movq\t{%1, %0|%0, %1} + movq\t{%1, %0|%0, %1} + movdq2q\t{%1, %0|%0, %1} + movq2dq\t{%1, %0|%0, %1} + pxor\t%0, %0 + movq\t{%1, %0|%0, %1} movq\t{%1, %0|%0, %1}" - [(set_attr "type" "mmxmov") + [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov") (set_attr "mode" "DI")]) -(define_insn "movv4hi_internal" - [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,y,m") - (match_operand:V4HI 1 "vector_move_operand" "C,ym,y"))] +(define_insn "*movv4hi_internal" + [(set (match_operand:V4HI 0 "nonimmediate_operand" + "=y,y ,m,!y,!*Y,*x,?*x,?m") + (match_operand:V4HI 1 "vector_move_operand" + "C ,ym,y,*Y,y ,C ,*xm,*x"))] "TARGET_MMX && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "@ pxor\t%0, %0 movq\t{%1, %0|%0, %1} + movq\t{%1, %0|%0, %1} + movdq2q\t{%1, %0|%0, %1} + movq2dq\t{%1, %0|%0, %1} + pxor\t%0, %0 + movq\t{%1, %0|%0, %1} movq\t{%1, %0|%0, %1}" - [(set_attr "type" "mmxmov") + [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov") (set_attr "mode" "DI")]) -(define_insn "movv2si_internal" - [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,y,m") - (match_operand:V2SI 1 "vector_move_operand" "C,ym,y"))] +(define_insn "*movv8qi_internal" + [(set (match_operand:V8QI 0 "nonimmediate_operand" + "=y,y ,m,!y,!*Y,*x,?*x,?m") + (match_operand:V8QI 1 "vector_move_operand" + "C ,ym,y,*Y,y ,C ,*xm,*x"))] "TARGET_MMX && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "@ pxor\t%0, %0 movq\t{%1, %0|%0, %1} + movq\t{%1, %0|%0, %1} + movdq2q\t{%1, %0|%0, %1} + movq2dq\t{%1, %0|%0, %1} + pxor\t%0, %0 + movq\t{%1, %0|%0, %1} movq\t{%1, %0|%0, %1}" - [(set_attr "type" "mmxcvt") + [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov") (set_attr "mode" "DI")]) -(define_insn "movv2sf_internal" - [(set (match_operand:V2SF 0 "nonimmediate_operand" "=y,y,m") - (match_operand:V2SF 1 "vector_move_operand" "C,ym,y"))] - "TARGET_3DNOW +(define_insn "*movv2sf_internal" + [(set (match_operand:V2SF 0 "nonimmediate_operand" + "=y,y ,m,!y,!*Y,*x,?*x,?m") + (match_operand:V2SF 1 "vector_move_operand" + "C ,ym,y,*Y,y ,C ,*xm,*x"))] + "TARGET_MMX && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" "@ pxor\t%0, %0 movq\t{%1, %0|%0, %1} + movq\t{%1, %0|%0, %1} + movdq2q\t{%1, %0|%0, %1} + movq2dq\t{%1, %0|%0, %1} + xorps\t%0, %0 + movq\t{%1, %0|%0, %1} movq\t{%1, %0|%0, %1}" - [(set_attr "type" "mmxcvt") + [(set_attr "type" "mmxmov,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,ssemov,ssemov") (set_attr "mode" "DI")]) (define_expand "movti" @@ -18606,17 +18728,14 @@ (match_operand:TF 1 "nonimmediate_operand" ""))] "TARGET_64BIT" { - if (TARGET_64BIT) - ix86_expand_move (TFmode, operands); - else - ix86_expand_vector_move (TFmode, operands); + ix86_expand_move (TFmode, operands); DONE; }) -(define_insn "movv2df_internal" +(define_insn "*movv2df_internal" [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m") (match_operand:V2DF 1 "vector_move_operand" "C,xm,x"))] - "TARGET_SSE2 + "TARGET_SSE && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" { switch (which_alternative) @@ -18638,7 +18757,9 @@ } [(set_attr "type" "ssemov") (set (attr "mode") - (cond [(eq_attr "alternative" "0,1") + (cond [(eq (symbol_ref "TARGET_SSE2") (const_int 0)) + (const_string "V4SF") + (eq_attr "alternative" "0,1") (if_then_else (ne (symbol_ref "optimize_size") (const_int 0)) @@ -18654,10 +18775,10 @@ (const_string "V2DF"))] (const_string "V2DF")))]) -(define_insn "movv8hi_internal" +(define_insn "*movv8hi_internal" [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,x,m") (match_operand:V8HI 1 "vector_move_operand" "C,xm,x"))] - "TARGET_SSE2 + "TARGET_SSE && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" { switch (which_alternative) @@ -18695,10 +18816,10 @@ (const_string "TI"))] (const_string "TI")))]) -(define_insn "movv16qi_internal" +(define_insn "*movv16qi_internal" [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,x,m") - (match_operand:V16QI 1 "nonimmediate_operand" "C,xm,x"))] - "TARGET_SSE2 + (match_operand:V16QI 1 "vector_move_operand" "C,xm,x"))] + "TARGET_SSE && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" { switch (which_alternative) @@ -18739,7 +18860,7 @@ (define_expand "movv2df" [(set (match_operand:V2DF 0 "nonimmediate_operand" "") (match_operand:V2DF 1 "nonimmediate_operand" ""))] - "TARGET_SSE2" + "TARGET_SSE" { ix86_expand_vector_move (V2DFmode, operands); DONE; @@ -18748,7 +18869,7 @@ (define_expand "movv8hi" [(set (match_operand:V8HI 0 "nonimmediate_operand" "") (match_operand:V8HI 1 "nonimmediate_operand" ""))] - "TARGET_SSE2" + "TARGET_SSE" { ix86_expand_vector_move (V8HImode, operands); DONE; @@ -18757,7 +18878,7 @@ (define_expand "movv16qi" [(set (match_operand:V16QI 0 "nonimmediate_operand" "") (match_operand:V16QI 1 "nonimmediate_operand" ""))] - "TARGET_SSE2" + "TARGET_SSE" { ix86_expand_vector_move (V16QImode, operands); DONE; @@ -18820,7 +18941,7 @@ (define_expand "movv2sf" [(set (match_operand:V2SF 0 "nonimmediate_operand" "") (match_operand:V2SF 1 "nonimmediate_operand" ""))] - "TARGET_3DNOW" + "TARGET_MMX" { ix86_expand_vector_move (V2SFmode, operands); DONE; @@ -18841,19 +18962,19 @@ (define_insn "*pushv2di" [(set (match_operand:V2DI 0 "push_operand" "=<") (match_operand:V2DI 1 "register_operand" "x"))] - "TARGET_SSE2" + "TARGET_SSE" "#") (define_insn "*pushv8hi" [(set (match_operand:V8HI 0 "push_operand" "=<") (match_operand:V8HI 1 "register_operand" "x"))] - "TARGET_SSE2" + "TARGET_SSE" "#") (define_insn "*pushv16qi" [(set (match_operand:V16QI 0 "push_operand" "=<") (match_operand:V16QI 1 "register_operand" "x"))] - "TARGET_SSE2" + "TARGET_SSE" "#") (define_insn "*pushv4sf" @@ -18865,7 +18986,7 @@ (define_insn "*pushv4si" [(set (match_operand:V4SI 0 "push_operand" "=<") (match_operand:V4SI 1 "register_operand" "x"))] - "TARGET_SSE2" + "TARGET_SSE" "#") (define_insn "*pushv2si" @@ -18889,7 +19010,7 @@ (define_insn "*pushv2sf" [(set (match_operand:V2SF 0 "push_operand" "=<") (match_operand:V2SF 1 "register_operand" "y"))] - "TARGET_3DNOW" + "TARGET_MMX" "#") (define_split @@ -18915,7 +19036,7 @@ operands[3] = GEN_INT (-GET_MODE_SIZE (GET_MODE (operands[0])));") -(define_insn "movti_internal" +(define_insn "*movti_internal" [(set (match_operand:TI 0 "nonimmediate_operand" "=x,x,m") (match_operand:TI 1 "vector_move_operand" "C,xm,x"))] "TARGET_SSE && !TARGET_64BIT @@ -19462,26 +19583,16 @@ ;; of DImode subregs again! ;; SSE1 single precision floating point logical operation (define_expand "sse_andv4sf3" - [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0) - (and:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0) - (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))] + [(set (match_operand:V4SF 0 "register_operand" "") + (and:V4SF (match_operand:V4SF 1 "register_operand" "") + (match_operand:V4SF 2 "nonimmediate_operand" "")))] "TARGET_SSE" "") (define_insn "*sse_andv4sf3" - [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0) - (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0") - (match_operand:TI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE - && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" - "andps\t{%2, %0|%0, %2}" - [(set_attr "type" "sselog") - (set_attr "mode" "V4SF")]) - -(define_insn "*sse_andsf3" - [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) - (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0") - (match_operand:TI 2 "nonimmediate_operand" "xm")))] + [(set (match_operand:V4SF 0 "register_operand" "=x") + (and:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0") + (match_operand:V4SF 2 "nonimmediate_operand" "xm")))] "TARGET_SSE && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "andps\t{%2, %0|%0, %2}" @@ -19489,51 +19600,32 @@ (set_attr "mode" "V4SF")]) (define_expand "sse_nandv4sf3" - [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0) - (and:TI (not:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0)) - (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))] + [(set (match_operand:V4SF 0 "register_operand" "") + (and:V4SF (not:V4SF (match_operand:V4SF 1 "register_operand" "")) + (match_operand:V4SF 2 "nonimmediate_operand" "")))] "TARGET_SSE" "") (define_insn "*sse_nandv4sf3" - [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0) - (and:TI (not:TI (match_operand:TI 1 "register_operand" "0")) - (match_operand:TI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE" - "andnps\t{%2, %0|%0, %2}" - [(set_attr "type" "sselog") - (set_attr "mode" "V4SF")]) - -(define_insn "*sse_nandsf3" - [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) - (and:TI (not:TI (match_operand:TI 1 "register_operand" "0")) - (match_operand:TI 2 "nonimmediate_operand" "xm")))] + [(set (match_operand:V4SF 0 "register_operand" "=x") + (and:V4SF (not:V4SF (match_operand:V4SF 1 "register_operand" "0")) + (match_operand:V4SF 2 "nonimmediate_operand" "xm")))] "TARGET_SSE" "andnps\t{%2, %0|%0, %2}" [(set_attr "type" "sselog") (set_attr "mode" "V4SF")]) (define_expand "sse_iorv4sf3" - [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0) - (ior:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0) - (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))] + [(set (match_operand:V4SF 0 "register_operand" "") + (ior:V4SF (match_operand:V4SF 1 "register_operand" "") + (match_operand:V4SF 2 "nonimmediate_operand" "")))] "TARGET_SSE" "") (define_insn "*sse_iorv4sf3" - [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0) - (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0") - (match_operand:TI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE - && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" - "orps\t{%2, %0|%0, %2}" - [(set_attr "type" "sselog") - (set_attr "mode" "V4SF")]) - -(define_insn "*sse_iorsf3" - [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) - (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0") - (match_operand:TI 2 "nonimmediate_operand" "xm")))] + [(set (match_operand:V4SF 0 "register_operand" "=x") + (ior:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0") + (match_operand:V4SF 2 "nonimmediate_operand" "xm")))] "TARGET_SSE && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "orps\t{%2, %0|%0, %2}" @@ -19541,27 +19633,16 @@ (set_attr "mode" "V4SF")]) (define_expand "sse_xorv4sf3" - [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "") 0) - (xor:TI (subreg:TI (match_operand:V4SF 1 "register_operand" "") 0) - (subreg:TI (match_operand:V4SF 2 "nonimmediate_operand" "") 0)))] - "TARGET_SSE - && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" + [(set (match_operand:V4SF 0 "register_operand" "") + (xor:V4SF (match_operand:V4SF 1 "register_operand" "") + (match_operand:V4SF 2 "nonimmediate_operand" "")))] + "TARGET_SSE" "") (define_insn "*sse_xorv4sf3" - [(set (subreg:TI (match_operand:V4SF 0 "register_operand" "=x") 0) - (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0") - (match_operand:TI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE - && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" - "xorps\t{%2, %0|%0, %2}" - [(set_attr "type" "sselog") - (set_attr "mode" "V4SF")]) - -(define_insn "*sse_xorsf3" - [(set (subreg:TI (match_operand:SF 0 "register_operand" "=x") 0) - (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0") - (match_operand:TI 2 "nonimmediate_operand" "xm")))] + [(set (match_operand:V4SF 0 "register_operand" "=x") + (xor:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "%0") + (match_operand:V4SF 2 "nonimmediate_operand" "xm")))] "TARGET_SSE && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "xorps\t{%2, %0|%0, %2}" @@ -19571,26 +19652,16 @@ ;; SSE2 double precision floating point logical operation (define_expand "sse2_andv2df3" - [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0) - (and:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0) - (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))] + [(set (match_operand:V2DF 0 "register_operand" "") + (and:V2DF (match_operand:V2DF 1 "register_operand" "") + (match_operand:V2DF 2 "nonimmediate_operand" "")))] "TARGET_SSE2" "") (define_insn "*sse2_andv2df3" - [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0) - (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0") - (match_operand:TI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE2 - && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" - "andpd\t{%2, %0|%0, %2}" - [(set_attr "type" "sselog") - (set_attr "mode" "V2DF")]) - -(define_insn "*sse2_andv2df3" - [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0) - (and:TI (match_operand:TI 1 "nonimmediate_operand" "%0") - (match_operand:TI 2 "nonimmediate_operand" "xm")))] + [(set (match_operand:V2DF 0 "register_operand" "=x") + (and:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0") + (match_operand:V2DF 2 "nonimmediate_operand" "xm")))] "TARGET_SSE2 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "andpd\t{%2, %0|%0, %2}" @@ -19598,51 +19669,32 @@ (set_attr "mode" "V2DF")]) (define_expand "sse2_nandv2df3" - [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0) - (and:TI (not:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0)) - (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))] + [(set (match_operand:V2DF 0 "register_operand" "") + (and:V2DF (not:V2DF (match_operand:V2DF 1 "register_operand" "")) + (match_operand:V2DF 2 "nonimmediate_operand" "")))] "TARGET_SSE2" "") (define_insn "*sse2_nandv2df3" - [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0) - (and:TI (not:TI (match_operand:TI 1 "register_operand" "0")) - (match_operand:TI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE2" - "andnpd\t{%2, %0|%0, %2}" - [(set_attr "type" "sselog") - (set_attr "mode" "V2DF")]) - -(define_insn "*sse_nandti3_df" - [(set (subreg:TI (match_operand:DF 0 "register_operand" "=Y") 0) - (and:TI (not:TI (match_operand:TI 1 "register_operand" "0")) - (match_operand:TI 2 "nonimmediate_operand" "Ym")))] + [(set (match_operand:V2DF 0 "register_operand" "=x") + (and:V2DF (not:V2DF (match_operand:V2DF 1 "register_operand" "0")) + (match_operand:V2DF 2 "nonimmediate_operand" "xm")))] "TARGET_SSE2" "andnpd\t{%2, %0|%0, %2}" [(set_attr "type" "sselog") (set_attr "mode" "V2DF")]) (define_expand "sse2_iorv2df3" - [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0) - (ior:TI (subreg:TI (match_operand:V2DF 1 "register_operand" "") 0) - (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))] + [(set (match_operand:V2DF 0 "register_operand" "") + (ior:V2DF (match_operand:V2DF 1 "register_operand" "") + (match_operand:V2DF 2 "nonimmediate_operand" "")))] "TARGET_SSE2" "") (define_insn "*sse2_iorv2df3" - [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0) - (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0") - (match_operand:TI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE2 - && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" - "orpd\t{%2, %0|%0, %2}" - [(set_attr "type" "sselog") - (set_attr "mode" "V2DF")]) - -(define_insn "*sse2_iordf3" - [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0) - (ior:TI (match_operand:TI 1 "nonimmediate_operand" "%0") - (match_operand:TI 2 "nonimmediate_operand" "xm")))] + [(set (match_operand:V2DF 0 "register_operand" "=x") + (ior:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0") + (match_operand:V2DF 2 "nonimmediate_operand" "xm")))] "TARGET_SSE2 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "orpd\t{%2, %0|%0, %2}" @@ -19650,26 +19702,16 @@ (set_attr "mode" "V2DF")]) (define_expand "sse2_xorv2df3" - [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "") 0) - (xor:TI (subreg:TI (match_operand:V2DF 1 "nonimmediate_operand" "") 0) - (subreg:TI (match_operand:V2DF 2 "nonimmediate_operand" "") 0)))] + [(set (match_operand:V2DF 0 "register_operand" "") + (xor:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "") + (match_operand:V2DF 2 "nonimmediate_operand" "")))] "TARGET_SSE2" "") (define_insn "*sse2_xorv2df3" - [(set (subreg:TI (match_operand:V2DF 0 "register_operand" "=x") 0) - (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0") - (match_operand:TI 2 "nonimmediate_operand" "xm")))] - "TARGET_SSE2 - && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" - "xorpd\t{%2, %0|%0, %2}" - [(set_attr "type" "sselog") - (set_attr "mode" "V2DF")]) - -(define_insn "*sse2_xordf3" - [(set (subreg:TI (match_operand:DF 0 "register_operand" "=x") 0) - (xor:TI (match_operand:TI 1 "nonimmediate_operand" "%0") - (match_operand:TI 2 "nonimmediate_operand" "xm")))] + [(set (match_operand:V2DF 0 "register_operand" "=x") + (xor:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "%0") + (match_operand:V2DF 2 "nonimmediate_operand" "xm")))] "TARGET_SSE2 && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)" "xorpd\t{%2, %0|%0, %2}" |