diff options
author | kan <kan@FreeBSD.org> | 2003-11-07 03:05:29 +0000 |
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committer | kan <kan@FreeBSD.org> | 2003-11-07 03:05:29 +0000 |
commit | a084c35ceb956547fd51afa69bbb1ddde34622dc (patch) | |
tree | ff877898269dfc629cdb62275a4c8db7b18b8956 /contrib/gcc/config | |
parent | 1fb226c0cab359db650569c666e4fac31032482f (diff) | |
download | FreeBSD-src-a084c35ceb956547fd51afa69bbb1ddde34622dc.zip FreeBSD-src-a084c35ceb956547fd51afa69bbb1ddde34622dc.tar.gz |
No FreeBSD-local changes in these files.
Diffstat (limited to 'contrib/gcc/config')
-rw-r--r-- | contrib/gcc/config/alpha/alpha.c | 68 | ||||
-rw-r--r-- | contrib/gcc/config/i386/i386.md | 135 |
2 files changed, 181 insertions, 22 deletions
diff --git a/contrib/gcc/config/alpha/alpha.c b/contrib/gcc/config/alpha/alpha.c index 9657e56..42b57e1 100644 --- a/contrib/gcc/config/alpha/alpha.c +++ b/contrib/gcc/config/alpha/alpha.c @@ -2949,12 +2949,8 @@ alpha_expand_mov (mode, operands) compiled at the end of compilation. In the meantime, someone can re-encode-section-info on some symbol changing it e.g. from global to local-not-small. If this happens, we'd have emitted a plain - load rather than a high+losum load and not recognize the insn. - - So if rtl inlining is in effect, we delay the global/not-global - decision until rest_of_compilation by wrapping it in an - UNSPEC_SYMBOL. */ - if (TARGET_EXPLICIT_RELOCS && flag_inline_functions + load rather than a high+losum load and not recognize the insn. */ + if (TARGET_EXPLICIT_RELOCS && rtx_equal_function_value_matters && global_symbolic_operand (operands[1], mode)) { @@ -3336,10 +3332,10 @@ alpha_emit_conditional_branch (code) if (op1 == const0_rtx) cmp_code = NIL, branch_code = code; - /* We want to use cmpcc/bcc when we can, since there is a zero delay - bypass between logicals and br/cmov on EV5. But we don't want to - force valid immediate constants into registers needlessly. */ - else if (GET_CODE (op1) == CONST_INT) + /* If the constants doesn't fit into an immediate, but can + be generated by lda/ldah, we adjust the argument and + compare against zero, so we can use beq/bne directly. */ + else if (GET_CODE (op1) == CONST_INT && (code == EQ || code == NE)) { HOST_WIDE_INT v = INTVAL (op1), n = -v; @@ -6748,14 +6744,21 @@ alpha_sa_mask (imaskP, fmaskP) /* We need to restore these for the handler. */ if (current_function_calls_eh_return) - for (i = 0; ; ++i) - { - unsigned regno = EH_RETURN_DATA_REGNO (i); - if (regno == INVALID_REGNUM) - break; - imask |= 1L << regno; - } - + { + for (i = 0; ; ++i) + { + unsigned regno = EH_RETURN_DATA_REGNO (i); + if (regno == INVALID_REGNUM) + break; + imask |= 1L << regno; + } + + /* Glibc likes to use $31 as an unwind stopper for crt0. To + avoid hackery in unwind-dw2.c, we need to actively store a + zero in the prologue of _Unwind_RaiseException et al. */ + imask |= 1UL << 31; + } + /* If any register spilled, then spill the return address also. */ /* ??? This is required by the Digital stack unwind specification and isn't needed if we're doing Dwarf2 unwinding. */ @@ -7210,7 +7213,7 @@ alpha_expand_prologue () } /* Now save any other registers required to be saved. */ - for (i = 0; i < 32; i++) + for (i = 0; i < 31; i++) if (imask & (1L << i)) { mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset)); @@ -7219,7 +7222,25 @@ alpha_expand_prologue () reg_offset += 8; } - for (i = 0; i < 32; i++) + /* Store a zero if requested for unwinding. */ + if (imask & (1UL << 31)) + { + rtx insn, t; + + mem = gen_rtx_MEM (DImode, plus_constant (sa_reg, reg_offset)); + set_mem_alias_set (mem, alpha_sr_alias_set); + insn = emit_move_insn (mem, const0_rtx); + + RTX_FRAME_RELATED_P (insn) = 1; + t = gen_rtx_REG (Pmode, 31); + t = gen_rtx_SET (VOIDmode, mem, t); + t = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, t, REG_NOTES (insn)); + REG_NOTES (insn) = t; + + reg_offset += 8; + } + + for (i = 0; i < 31; i++) if (fmask & (1L << i)) { mem = gen_rtx_MEM (DFmode, plus_constant (sa_reg, reg_offset)); @@ -7625,7 +7646,7 @@ alpha_expand_epilogue () reg_offset += 8; imask &= ~(1L << REG_RA); - for (i = 0; i < 32; ++i) + for (i = 0; i < 31; ++i) if (imask & (1L << i)) { if (i == HARD_FRAME_POINTER_REGNUM && fp_is_frame_pointer) @@ -7639,7 +7660,10 @@ alpha_expand_epilogue () reg_offset += 8; } - for (i = 0; i < 32; ++i) + if (imask & (1UL << 31)) + reg_offset += 8; + + for (i = 0; i < 31; ++i) if (fmask & (1L << i)) { mem = gen_rtx_MEM (DFmode, plus_constant(sa_reg, reg_offset)); diff --git a/contrib/gcc/config/i386/i386.md b/contrib/gcc/config/i386/i386.md index 1fa2998..e4377a5 100644 --- a/contrib/gcc/config/i386/i386.md +++ b/contrib/gcc/config/i386/i386.md @@ -110,6 +110,13 @@ (UNSPEC_MFENCE 59) (UNSPEC_LFENCE 60) (UNSPEC_PSADBW 61) + (UNSPEC_ADDSUB 71) + (UNSPEC_HADD 72) + (UNSPEC_HSUB 73) + (UNSPEC_MOVSHDUP 74) + (UNSPEC_MOVSLDUP 75) + (UNSPEC_LDQQU 76) + (UNSPEC_MOVDDUP 77) ]) (define_constants @@ -120,6 +127,8 @@ (UNSPECV_STMXCSR 40) (UNSPECV_FEMMS 46) (UNSPECV_CLFLUSH 57) + (UNSPECV_MONITOR 69) + (UNSPECV_MWAIT 70) ]) ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls @@ -22072,3 +22081,129 @@ "lfence" [(set_attr "type" "sse") (set_attr "memory" "unknown")]) + +;; PNI + +(define_insn "mwait" + [(unspec_volatile [(match_operand:SI 0 "register_operand" "a") + (match_operand:SI 1 "register_operand" "c")] + UNSPECV_MWAIT)] + "TARGET_PNI" + "mwait\t%0, %1" + [(set_attr "length" "3")]) + +(define_insn "monitor" + [(unspec_volatile [(match_operand:SI 0 "register_operand" "a") + (match_operand:SI 1 "register_operand" "c") + (match_operand:SI 2 "register_operand" "d")] + UNSPECV_MONITOR)] + "TARGET_PNI" + "monitor\t%0, %1, %2" + [(set_attr "length" "3")]) + +;; PNI arithmetic + +(define_insn "addsubv4sf3" + [(set (match_operand:V4SF 0 "register_operand" "=x") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0") + (match_operand:V4SF 2 "nonimmediate_operand" "xm")] + UNSPEC_ADDSUB))] + "TARGET_PNI" + "addsubps\t{%2, %0|%0, %2}" + [(set_attr "type" "sseadd") + (set_attr "mode" "V4SF")]) + +(define_insn "addsubv2df3" + [(set (match_operand:V2DF 0 "register_operand" "=x") + (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0") + (match_operand:V2DF 2 "nonimmediate_operand" "xm")] + UNSPEC_ADDSUB))] + "TARGET_PNI" + "addsubpd\t{%2, %0|%0, %2}" + [(set_attr "type" "sseadd") + (set_attr "mode" "V2DF")]) + +(define_insn "haddv4sf3" + [(set (match_operand:V4SF 0 "register_operand" "=x") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0") + (match_operand:V4SF 2 "nonimmediate_operand" "xm")] + UNSPEC_HADD))] + "TARGET_PNI" + "haddps\t{%2, %0|%0, %2}" + [(set_attr "type" "sseadd") + (set_attr "mode" "V4SF")]) + +(define_insn "haddv2df3" + [(set (match_operand:V2DF 0 "register_operand" "=x") + (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0") + (match_operand:V2DF 2 "nonimmediate_operand" "xm")] + UNSPEC_HADD))] + "TARGET_PNI" + "haddpd\t{%2, %0|%0, %2}" + [(set_attr "type" "sseadd") + (set_attr "mode" "V2DF")]) + +(define_insn "hsubv4sf3" + [(set (match_operand:V4SF 0 "register_operand" "=x") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "0") + (match_operand:V4SF 2 "nonimmediate_operand" "xm")] + UNSPEC_HSUB))] + "TARGET_PNI" + "hsubps\t{%2, %0|%0, %2}" + [(set_attr "type" "sseadd") + (set_attr "mode" "V4SF")]) + +(define_insn "hsubv2df3" + [(set (match_operand:V2DF 0 "register_operand" "=x") + (unspec:V2DF [(match_operand:V2DF 1 "register_operand" "0") + (match_operand:V2DF 2 "nonimmediate_operand" "xm")] + UNSPEC_HSUB))] + "TARGET_PNI" + "hsubpd\t{%2, %0|%0, %2}" + [(set_attr "type" "sseadd") + (set_attr "mode" "V2DF")]) + +(define_insn "movshdup" + [(set (match_operand:V4SF 0 "register_operand" "=x") + (unspec:V4SF + [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSHDUP))] + "TARGET_PNI" + "movshdup\t{%1, %0|%0, %1}" + [(set_attr "type" "sse") + (set_attr "mode" "V4SF")]) + +(define_insn "movsldup" + [(set (match_operand:V4SF 0 "register_operand" "=x") + (unspec:V4SF + [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_MOVSLDUP))] + "TARGET_PNI" + "movsldup\t{%1, %0|%0, %1}" + [(set_attr "type" "sse") + (set_attr "mode" "V4SF")]) + +(define_insn "lddqu" + [(set (match_operand:V16QI 0 "register_operand" "=x") + (unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "m")] + UNSPEC_LDQQU))] + "TARGET_PNI" + "lddqu\t{%1, %0|%0, %1}" + [(set_attr "type" "ssecvt") + (set_attr "mode" "TI")]) + +(define_insn "loadddup" + [(set (match_operand:V2DF 0 "register_operand" "=x") + (vec_duplicate:V2DF (match_operand:DF 1 "memory_operand" "m")))] + "TARGET_PNI" + "movddup\t{%1, %0|%0, %1}" + [(set_attr "type" "ssecvt") + (set_attr "mode" "DF")]) + +(define_insn "movddup" + [(set (match_operand:V2DF 0 "register_operand" "=x") + (vec_duplicate:V2DF + (vec_select:DF (match_operand:V2DF 1 "register_operand" "x") + (parallel [(const_int 0)]))))] + "TARGET_PNI" + "movddup\t{%1, %0|%0, %1}" + [(set_attr "type" "ssecvt") + (set_attr "mode" "DF")]) |