diff options
| author | kan <kan@FreeBSD.org> | 2003-07-11 03:40:53 +0000 |
|---|---|---|
| committer | kan <kan@FreeBSD.org> | 2003-07-11 03:40:53 +0000 |
| commit | b2a8872fbe1ec1c49094559ac7b78e6ea4ab7180 (patch) | |
| tree | f6b0610f4a17fd26aa234354f050080f789861a4 /contrib/gcc/config/rs6000 | |
| parent | 52e69d78eee5612ac195e0701a5cebe40d1ab0e1 (diff) | |
| download | FreeBSD-src-b2a8872fbe1ec1c49094559ac7b78e6ea4ab7180.zip FreeBSD-src-b2a8872fbe1ec1c49094559ac7b78e6ea4ab7180.tar.gz | |
Gcc 3.3.1-pre as of 2003-07-11.
Diffstat (limited to 'contrib/gcc/config/rs6000')
47 files changed, 12171 insertions, 4684 deletions
diff --git a/contrib/gcc/config/rs6000/aix.h b/contrib/gcc/config/rs6000/aix.h index d8dde5b..505d758 100644 --- a/contrib/gcc/config/rs6000/aix.h +++ b/contrib/gcc/config/rs6000/aix.h @@ -21,14 +21,31 @@ Boston, MA 02111-1307, USA. */ /* Yes! We are AIX! */ #define DEFAULT_ABI ABI_AIX -#undef TARGET_AIX +#undef TARGET_AIX #define TARGET_AIX 1 + +/* AIX always has a TOC. */ +#define TARGET_NO_TOC 0 +#define TARGET_TOC 1 +#define FIXED_R2 1 + +/* AIX allows r13 to be used in 32-bit mode. */ +#define FIXED_R13 0 + +/* AIX does not support Altivec. */ +#undef TARGET_ALTIVEC +#define TARGET_ALTIVEC 0 +#undef TARGET_ALTIVEC_ABI +#define TARGET_ALTIVEC_ABI 0 +#undef TARGET_ALTIVEC_VRSAVE +#define TARGET_ALTIVEC_VRSAVE 0 + /* The AIX linker will discard static constructors in object files before collect has a chance to see them, so scan the object files directly. */ #define COLLECT_EXPORT_LIST /* Handle #pragma weak and #pragma pack. */ -#define HANDLE_SYSV_PRAGMA +#define HANDLE_SYSV_PRAGMA 1 /* This is the only version of nm that collect2 can work with. */ #define REAL_NM_FILE_NAME "/usr/ucb/nm" @@ -41,18 +58,26 @@ Boston, MA 02111-1307, USA. */ #define LINK_LIBGCC_SPECIAL_1 /* Names to predefine in the preprocessor for this target machine. */ -#define CPP_PREDEFINES "-D_IBMR2 -D_POWER -D_AIX -D_AIX32 -D_LONG_LONG \ --Asystem=unix -Asystem=aix -Acpu=rs6000 -Amachine=rs6000" +#define TARGET_OS_CPP_BUILTINS() \ + do \ + { \ + builtin_define ("_IBMR2"); \ + builtin_define ("_POWER"); \ + builtin_define ("_AIX"); \ + builtin_define ("_AIX32"); \ + builtin_define ("_LONG_LONG"); \ + builtin_assert ("system=unix"); \ + builtin_assert ("system=aix"); \ + builtin_assert ("cpu=rs6000"); \ + builtin_assert ("machine=rs6000"); \ + } \ + while (0) /* Define appropriate architecture macros for preprocessor depending on target switches. */ #define CPP_SPEC "%{posix: -D_POSIX_SOURCE}\ - %{ansi: -D_ANSI_C_SOURCE}\ - %(cpp_cpu)" - -#undef CPP_DEFAULT_SPEC -#define CPP_DEFAULT_SPEC "-D_ARCH_PWR" + %{ansi: -D_ANSI_C_SOURCE}" #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "" @@ -121,8 +146,6 @@ Boston, MA 02111-1307, USA. */ ? MAX (MAX ((COMPUTED), (SPECIFIED)), 64) \ : MAX ((COMPUTED), (SPECIFIED))) - - /* Indicate that jump tables go in the text section. */ #define JUMP_TABLES_IN_TEXT_SECTION 1 @@ -176,14 +199,6 @@ Boston, MA 02111-1307, USA. */ } \ } while (0) -/* AIX always has a TOC. */ -#define TARGET_NO_TOC 0 -#define TARGET_TOC 1 - -#define FIXED_R2 1 -/* AIX allows r13 to be used. */ -#define FIXED_R13 0 - /* __throw will restore its own return address to be the same as the return address of the function that the throw is being made to. This is unfortunate, because we want to check the original diff --git a/contrib/gcc/config/rs6000/aix31.h b/contrib/gcc/config/rs6000/aix31.h index 688e588..7379a34 100644 --- a/contrib/gcc/config/rs6000/aix31.h +++ b/contrib/gcc/config/rs6000/aix31.h @@ -29,25 +29,25 @@ Boston, MA 02111-1307, USA. */ where we can't, it gets stripped off. */ #undef ASM_OUTPUT_EXTERNAL -#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \ -{ rtx _symref = XEXP (DECL_RTL (DECL), 0); \ - if ((TREE_CODE (DECL) == VAR_DECL \ - || TREE_CODE (DECL) == FUNCTION_DECL) \ - && (NAME)[strlen (NAME) - 1] != ']') \ - { \ - char *_name = (char *) permalloc (strlen (XSTR (_symref, 0)) + 5); \ - strcpy (_name, XSTR (_symref, 0)); \ - strcat (_name, TREE_CODE (DECL) == FUNCTION_DECL ? "[DS]" : "[RW]"); \ - XSTR (_symref, 0) = _name; \ - } \ - fputs ("\t.extern ", FILE); \ - assemble_name (FILE, XSTR (_symref, 0)); \ - if (TREE_CODE (DECL) == FUNCTION_DECL) \ - { \ - fputs ("\n\t.extern .", FILE); \ - RS6000_OUTPUT_BASENAME (FILE, XSTR (_symref, 0)); \ - } \ - putc ('\n', FILE); \ +#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \ +{ rtx _symref = XEXP (DECL_RTL (DECL), 0); \ + if ((TREE_CODE (DECL) == VAR_DECL \ + || TREE_CODE (DECL) == FUNCTION_DECL) \ + && (NAME)[strlen (NAME) - 1] != ']') \ + { \ + XSTR (_symref, 0) = concat (XSTR (_symref, 0), \ + (TREE_CODE (DECL) == FUNCTION_DECL \ + ? "[DS]" : "[RW]"), \ + NULL); \ + } \ + fputs ("\t.extern ", FILE); \ + assemble_name (FILE, XSTR (_symref, 0)); \ + if (TREE_CODE (DECL) == FUNCTION_DECL) \ + { \ + fputs ("\n\t.extern .", FILE); \ + RS6000_OUTPUT_BASENAME (FILE, XSTR (_symref, 0)); \ + } \ + putc ('\n', FILE); \ } /* Similar, but for libcall. We only have to worry about the function name, @@ -60,8 +60,18 @@ Boston, MA 02111-1307, USA. */ } /* AIX 3.2 defined _AIX32, but older versions do not. */ -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "-D_IBMR2 -D_AIX -Asystem=unix -Asystem=aix -Acpu=rs6000 -Amachine=rs6000" +#undef TARGET_OS_CPP_BUILTINS +#define TARGET_OS_CPP_BUILTINS() \ + do \ + { \ + builtin_define ("_IBMR2"); \ + builtin_define ("_AIX"); \ + builtin_assert ("system=unix"); \ + builtin_assert ("system=aix"); \ + builtin_assert ("cpu=rs6000"); \ + builtin_assert ("machine=rs6000"); \ + } \ + while (0) /* AIX 3.1 uses bit 15 in CROR as the magic nop. */ #undef RS6000_CALL_GLUE diff --git a/contrib/gcc/config/rs6000/aix41.h b/contrib/gcc/config/rs6000/aix41.h index cae1a85..7f23a48 100644 --- a/contrib/gcc/config/rs6000/aix41.h +++ b/contrib/gcc/config/rs6000/aix41.h @@ -33,19 +33,26 @@ Boston, MA 02111-1307, USA. */ #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mcom" -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "-D_IBMR2 -D_POWER -D_AIX -D_AIX32 -D_AIX41 \ --D_LONG_LONG -Asystem=unix -Asystem=aix" +#undef TARGET_OS_CPP_BUILTINS +#define TARGET_OS_CPP_BUILTINS() \ + do \ + { \ + builtin_define ("_IBMR2"); \ + builtin_define ("_POWER"); \ + builtin_define ("_AIX"); \ + builtin_define ("_AIX32"); \ + builtin_define ("_AIX41"); \ + builtin_define ("_LONG_LONG"); \ + builtin_assert ("system=unix"); \ + builtin_assert ("system=aix"); \ + } \ + while (0) #undef CPP_SPEC #define CPP_SPEC "%{posix: -D_POSIX_SOURCE}\ %{ansi: -D_ANSI_C_SOURCE}\ %{mpe: -I/usr/lpp/ppe.poe/include}\ - %{pthread: -D_THREAD_SAFE}\ - %(cpp_cpu)" - -#undef CPP_DEFAULT_SPEC -#define CPP_DEFAULT_SPEC "-D_ARCH_COM" + %{pthread: -D_THREAD_SAFE}" #undef TARGET_DEFAULT #define TARGET_DEFAULT MASK_NEW_MNEMONICS diff --git a/contrib/gcc/config/rs6000/aix43.h b/contrib/gcc/config/rs6000/aix43.h index 8fe9859..bcbfcf2 100644 --- a/contrib/gcc/config/rs6000/aix43.h +++ b/contrib/gcc/config/rs6000/aix43.h @@ -75,6 +75,8 @@ do { \ %{mcpu=common: -mcom} \ %{mcpu=power: -mpwr} \ %{mcpu=power2: -mpwr2} \ +%{mcpu=power3: -m604} \ +%{mcpu=power4: -m604} \ %{mcpu=powerpc: -mppc} \ %{mcpu=rios: -mpwr} \ %{mcpu=rios1: -mpwr} \ @@ -82,8 +84,6 @@ do { \ %{mcpu=rsc: -mpwr} \ %{mcpu=rsc1: -mpwr} \ %{mcpu=rs64a: -mppc} \ -%{mcpu=403: -mppc} \ -%{mcpu=505: -mppc} \ %{mcpu=601: -m601} \ %{mcpu=602: -mppc} \ %{mcpu=603: -m603} \ @@ -91,24 +91,33 @@ do { \ %{mcpu=604: -m604} \ %{mcpu=604e: -m604} \ %{mcpu=620: -mppc} \ -%{mcpu=630: -mppc} \ -%{mcpu=821: -mppc} \ -%{mcpu=860: -mppc}" +%{mcpu=630: -m604}" #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mcom" -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "-D_IBMR2 -D_POWER -D_AIX -D_AIX32 -D_AIX41 -D_AIX43 \ --D_LONG_LONG -Asystem=unix -Asystem=aix" +#undef TARGET_OS_CPP_BUILTINS +#define TARGET_OS_CPP_BUILTINS() \ + do \ + { \ + builtin_define ("_IBMR2"); \ + builtin_define ("_POWER"); \ + builtin_define ("_AIX"); \ + builtin_define ("_AIX32"); \ + builtin_define ("_AIX41"); \ + builtin_define ("_AIX43"); \ + builtin_define ("_LONG_LONG"); \ + builtin_assert ("system=unix"); \ + builtin_assert ("system=aix"); \ + } \ + while (0) #undef CPP_SPEC #define CPP_SPEC "%{posix: -D_POSIX_SOURCE}\ %{ansi: -D_ANSI_C_SOURCE}\ - %{maix64: -D__64BIT__ -D_ARCH_PPC -D__LONG_MAX__=9223372036854775807L}\ + %{maix64: -D__64BIT__}\ %{mpe: -I/usr/lpp/ppe.poe/include}\ - %{pthread: -D_THREAD_SAFE}\ - %(cpp_cpu)" + %{pthread: -D_THREAD_SAFE}" /* The GNU C++ standard library requires that these macros be defined. */ @@ -117,51 +126,16 @@ do { \ "-D_XOPEN_SOURCE=500 \ -D_XOPEN_SOURCE_EXTENDED=1 \ -D_LARGE_FILE_API \ - -D_ALL_SOURCE \ - %{maix64: -D__64BIT__ -D_ARCH_PPC -D__LONG_MAX__=9223372036854775807L}\ - %{mpe: -I/usr/lpp/ppe.poe/include}\ - %{pthread: -D_THREAD_SAFE}\ - %(cpp_cpu)" - -/* Common CPP definitions used by CPP_SPEC among the various targets - for handling -mcpu=xxx switches. */ -#undef CPP_CPU_SPEC -#define CPP_CPU_SPEC \ -"%{!mcpu*: %{!maix64: \ - %{mpower: %{!mpower2: -D_ARCH_PWR}} \ - %{mpower2: -D_ARCH_PWR2} \ - %{mpowerpc*: -D_ARCH_PPC} \ - %{!mpower*: %{!mpowerpc*: %(cpp_default)}}}} \ -%{mcpu=common: -D_ARCH_COM} \ -%{mcpu=power: -D_ARCH_PWR} \ -%{mcpu=power2: -D_ARCH_PWR2} \ -%{mcpu=powerpc: -D_ARCH_PPC} \ -%{mcpu=rios: -D_ARCH_PWR} \ -%{mcpu=rios1: -D_ARCH_PWR} \ -%{mcpu=rios2: -D_ARCH_PWR2} \ -%{mcpu=rsc: -D_ARCH_PWR} \ -%{mcpu=rsc1: -D_ARCH_PWR} \ -%{mcpu=rs64a: -D_ARCH_PPC} \ -%{mcpu=403: -D_ARCH_PPC} \ -%{mcpu=505: -D_ARCH_PPC} \ -%{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR} \ -%{mcpu=602: -D_ARCH_PPC} \ -%{mcpu=603: -D_ARCH_PPC} \ -%{mcpu=603e: -D_ARCH_PPC} \ -%{mcpu=604: -D_ARCH_PPC} \ -%{mcpu=620: -D_ARCH_PPC} \ -%{mcpu=630: -D_ARCH_PPC} \ -%{mcpu=821: -D_ARCH_PPC} \ -%{mcpu=860: -D_ARCH_PPC}" - -#undef CPP_DEFAULT_SPEC -#define CPP_DEFAULT_SPEC "-D_ARCH_COM" + -D_ALL_SOURCE \ + %{maix64: -D__64BIT__} \ + %{mpe: -I/usr/lpp/ppe.poe/include} \ + %{pthread: -D_THREAD_SAFE}" #undef TARGET_DEFAULT #define TARGET_DEFAULT MASK_NEW_MNEMONICS #undef PROCESSOR_DEFAULT -#define PROCESSOR_DEFAULT PROCESSOR_PPC604 +#define PROCESSOR_DEFAULT PROCESSOR_PPC604e /* Define this macro as a C expression for the initializer of an array of string to tell the driver program which options are diff --git a/contrib/gcc/config/rs6000/aix51.h b/contrib/gcc/config/rs6000/aix51.h index 4051dd0..552394e 100644 --- a/contrib/gcc/config/rs6000/aix51.h +++ b/contrib/gcc/config/rs6000/aix51.h @@ -75,6 +75,8 @@ do { \ %{mcpu=common: -mcom} \ %{mcpu=power: -mpwr} \ %{mcpu=power2: -mpwr2} \ +%{mcpu=power3: -m604} \ +%{mcpu=power4: -m604} \ %{mcpu=powerpc: -mppc} \ %{mcpu=rios: -mpwr} \ %{mcpu=rios1: -mpwr} \ @@ -82,8 +84,6 @@ do { \ %{mcpu=rsc: -mpwr} \ %{mcpu=rsc1: -mpwr} \ %{mcpu=rs64a: -mppc} \ -%{mcpu=403: -mppc} \ -%{mcpu=505: -mppc} \ %{mcpu=601: -m601} \ %{mcpu=602: -mppc} \ %{mcpu=603: -m603} \ @@ -91,81 +91,52 @@ do { \ %{mcpu=604: -m604} \ %{mcpu=604e: -m604} \ %{mcpu=620: -mppc} \ -%{mcpu=630: -mppc} \ -%{mcpu=821: -mppc} \ -%{mcpu=860: -mppc}" +%{mcpu=630: -m604}" #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mcom" -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "-D_IBMR2 -D_POWER -D_LONG_LONG \ --D_AIX -D_AIX32 -D_AIX41 -D_AIX43 -D_AIX51 -Asystem=unix -Asystem=aix" +#undef TARGET_OS_CPP_BUILTINS +#define TARGET_OS_CPP_BUILTINS() \ + do \ + { \ + builtin_define ("_IBMR2"); \ + builtin_define ("_POWER"); \ + builtin_define ("_LONG_LONG"); \ + builtin_define ("_AIX"); \ + builtin_define ("_AIX32"); \ + builtin_define ("_AIX41"); \ + builtin_define ("_AIX43"); \ + builtin_define ("_AIX51"); \ + builtin_assert ("system=unix"); \ + builtin_assert ("system=aix"); \ + } \ + while (0) #undef CPP_SPEC -#define CPP_SPEC "%{posix: -D_POSIX_SOURCE}\ - %{ansi: -D_ANSI_C_SOURCE}\ - %{!maix64: -D__WCHAR_TYPE__=short\\ unsigned\\ int}\ - %{maix64: -D__64BIT__ -D_ARCH_PPC -D__LONG_MAX__=9223372036854775807L \ - -D__WCHAR_TYPE__=unsigned\\ int}\ - %{mpe: -I/usr/lpp/ppe.poe/include}\ - %{pthread: -D_THREAD_SAFE}\ - %(cpp_cpu)" +#define CPP_SPEC "%{posix: -D_POSIX_SOURCE} \ + %{ansi: -D_ANSI_C_SOURCE} \ + %{maix64: -D__64BIT__} \ + %{mpe: -I/usr/lpp/ppe.poe/include} \ + %{pthread: -D_THREAD_SAFE}" /* The GNU C++ standard library requires that these macros be defined. */ #undef CPLUSPLUS_CPP_SPEC -#define CPLUSPLUS_CPP_SPEC \ - "-D_XOPEN_SOURCE=500 \ - -D_XOPEN_SOURCE_EXTENDED=1 \ - -D_LARGE_FILE_API \ - -D_ALL_SOURCE \ - %{!maix64: -D__WCHAR_TYPE__=short\\ unsigned\\ int}\ - %{maix64: -D__64BIT__ -D_ARCH_PPC -D__LONG_MAX__=9223372036854775807L \ - -D__WCHAR_TYPE__=unsigned\\ int}\ - %{mpe: -I/usr/lpp/ppe.poe/include}\ - %{pthread: -D_THREAD_SAFE}\ - %(cpp_cpu)" - -/* Common CPP definitions used by CPP_SPEC among the various targets - for handling -mcpu=xxx switches. */ -#undef CPP_CPU_SPEC -#define CPP_CPU_SPEC \ -"%{!mcpu*: %{!maix64: \ - %{mpower: %{!mpower2: -D_ARCH_PWR}} \ - %{mpower2: -D_ARCH_PWR2} \ - %{mpowerpc*: -D_ARCH_PPC} \ - %{!mpower*: %{!mpowerpc*: %(cpp_default)}}}} \ -%{mcpu=common: -D_ARCH_COM} \ -%{mcpu=power: -D_ARCH_PWR} \ -%{mcpu=power2: -D_ARCH_PWR2} \ -%{mcpu=powerpc: -D_ARCH_PPC} \ -%{mcpu=rios: -D_ARCH_PWR} \ -%{mcpu=rios1: -D_ARCH_PWR} \ -%{mcpu=rios2: -D_ARCH_PWR2} \ -%{mcpu=rsc: -D_ARCH_PWR} \ -%{mcpu=rsc1: -D_ARCH_PWR} \ -%{mcpu=rs64a: -D_ARCH_PPC} \ -%{mcpu=403: -D_ARCH_PPC} \ -%{mcpu=505: -D_ARCH_PPC} \ -%{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR} \ -%{mcpu=602: -D_ARCH_PPC} \ -%{mcpu=603: -D_ARCH_PPC} \ -%{mcpu=603e: -D_ARCH_PPC} \ -%{mcpu=604: -D_ARCH_PPC} \ -%{mcpu=620: -D_ARCH_PPC} \ -%{mcpu=630: -D_ARCH_PPC} \ -%{mcpu=821: -D_ARCH_PPC} \ -%{mcpu=860: -D_ARCH_PPC}" - -#undef CPP_DEFAULT_SPEC -#define CPP_DEFAULT_SPEC "-D_ARCH_COM" +#define CPLUSPLUS_CPP_SPEC \ + "-D_XOPEN_SOURCE=500 \ + -D_XOPEN_SOURCE_EXTENDED=1 \ + -D_LARGE_FILE_API \ + -D_ALL_SOURCE \ + %{maix64: -D__64BIT__} \ + %{mpe: -I/usr/lpp/ppe.poe/include} \ + %{pthread: -D_THREAD_SAFE}" #undef TARGET_DEFAULT #define TARGET_DEFAULT MASK_NEW_MNEMONICS #undef PROCESSOR_DEFAULT -#define PROCESSOR_DEFAULT PROCESSOR_PPC604 +#define PROCESSOR_DEFAULT PROCESSOR_PPC604e /* Define this macro as a C expression for the initializer of an array of string to tell the driver program which options are @@ -204,9 +175,6 @@ do { \ #undef PTRDIFF_TYPE #define PTRDIFF_TYPE "long int" -/* __WCHAR_TYPE__ is dynamic, so do not define it statically. */ -#define NO_BUILTIN_WCHAR_TYPE - /* Type used for wchar_t, as a string used in a declaration. */ #undef WCHAR_TYPE #define WCHAR_TYPE (!TARGET_64BIT ? "short unsigned int" : "unsigned int") diff --git a/contrib/gcc/config/rs6000/aix52.h b/contrib/gcc/config/rs6000/aix52.h new file mode 100644 index 0000000..b61cc30 --- /dev/null +++ b/contrib/gcc/config/rs6000/aix52.h @@ -0,0 +1,191 @@ +/* Definitions of target machine for GNU compiler, + for IBM RS/6000 POWER running AIX V5.2. + Copyright (C) 2002 Free Software Foundation, Inc. + Contributed by David Edelsohn (edelsohn@gnu.org). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + + +/* AIX V5 and above support 64-bit executables. */ +#undef SUBSUBTARGET_SWITCHES +#define SUBSUBTARGET_SWITCHES \ + {"aix64", MASK_64BIT | MASK_POWERPC64 | MASK_POWERPC, \ + N_("Compile for 64-bit pointers") }, \ + {"aix32", - (MASK_64BIT | MASK_POWERPC64), \ + N_("Compile for 32-bit pointers") }, \ + {"pe", 0, \ + N_("Support message passing with the Parallel Environment") }, + +/* Sometimes certain combinations of command options do not make sense + on a particular target machine. You can define a macro + `OVERRIDE_OPTIONS' to take account of this. This macro, if + defined, is executed once just after all the command options have + been parsed. + + The macro SUBTARGET_OVERRIDE_OPTIONS is provided for subtargets, to + get control. */ + +#define NON_POWERPC_MASKS (MASK_POWER | MASK_POWER2) +#define SUBTARGET_OVERRIDE_OPTIONS \ +do { \ + if (TARGET_64BIT && (target_flags & NON_POWERPC_MASKS)) \ + { \ + target_flags &= ~NON_POWERPC_MASKS; \ + warning ("-maix64 and POWER architecture are incompatible"); \ + } \ + if (TARGET_64BIT && ! TARGET_POWERPC64) \ + { \ + target_flags |= MASK_POWERPC64; \ + warning ("-maix64 requires PowerPC64 architecture remain enabled"); \ + } \ + if (TARGET_POWERPC64 && ! TARGET_64BIT) \ + { \ + error ("-maix64 required: 64-bit computation with 32-bit addressing not yet supported"); \ + } \ +} while (0); + +#undef ASM_SPEC +#define ASM_SPEC "-u %{maix64:-a64 -mppc64} %(asm_cpu)" + +/* Common ASM definitions used by ASM_SPEC amonst the various targets + for handling -mcpu=xxx switches. */ +#undef ASM_CPU_SPEC +#define ASM_CPU_SPEC \ +"%{!mcpu*: %{!maix64: \ + %{mpowerpc64: -mppc64} \ + %{!mpower64: %(asm_default)}}} \ +%{mcpu=power3: -m604} \ +%{mcpu=power4: -m604} \ +%{mcpu=powerpc: -mppc} \ +%{mcpu=rs64a: -mppc} \ +%{mcpu=603: -m603} \ +%{mcpu=603e: -m603} \ +%{mcpu=604: -m604} \ +%{mcpu=604e: -m604} \ +%{mcpu=620: -mppc} \ +%{mcpu=630: -m604}" + +#undef ASM_DEFAULT_SPEC +#define ASM_DEFAULT_SPEC "-mppc" + +#undef TARGET_OS_CPP_BUILTINS +#define TARGET_OS_CPP_BUILTINS() \ + do \ + { \ + builtin_define ("_IBMR2"); \ + builtin_define ("_POWER"); \ + builtin_define ("_LONG_LONG"); \ + builtin_define ("_AIX"); \ + builtin_define ("_AIX32"); \ + builtin_define ("_AIX41"); \ + builtin_define ("_AIX43"); \ + builtin_define ("_AIX51"); \ + builtin_define ("_AIX52"); \ + builtin_assert ("system=unix"); \ + builtin_assert ("system=aix"); \ + } \ + while (0) + +#undef CPP_SPEC +#define CPP_SPEC "%{posix: -D_POSIX_SOURCE} \ + %{ansi: -D_ANSI_C_SOURCE} \ + %{maix64: -D__64BIT__} \ + %{mpe: -I/usr/lpp/ppe.poe/include} \ + %{pthread: -D_THREAD_SAFE}" + +/* The GNU C++ standard library requires that these macros be + defined. */ +#undef CPLUSPLUS_CPP_SPEC +#define CPLUSPLUS_CPP_SPEC \ + "-D_XOPEN_SOURCE=500 \ + -D_XOPEN_SOURCE_EXTENDED=1 \ + -D_LARGE_FILE_API \ + -D_ALL_SOURCE \ + %{maix64: -D__64BIT__} \ + %{mpe: -I/usr/lpp/ppe.poe/include} \ + %{pthread: -D_THREAD_SAFE}" + +#undef TARGET_DEFAULT +#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS) + +#undef PROCESSOR_DEFAULT +#define PROCESSOR_DEFAULT PROCESSOR_PPC630 +#undef PROCESSOR_DEFAULT64 +#define PROCESSOR_DEFAULT64 PROCESSOR_POWER4 + +#undef TARGET_POWER +#define TARGET_POWER 0 + +/* Define this macro as a C expression for the initializer of an + array of string to tell the driver program which options are + defaults for this target and thus do not need to be handled + specially when using `MULTILIB_OPTIONS'. + + Do not define this macro if `MULTILIB_OPTIONS' is not defined in + the target makefile fragment or if none of the options listed in + `MULTILIB_OPTIONS' are set by default. *Note Target Fragment::. */ + +#undef MULTILIB_DEFAULTS + +#undef LIB_SPEC +#define LIB_SPEC "%{pg:-L/lib/profiled -L/usr/lib/profiled}\ + %{p:-L/lib/profiled -L/usr/lib/profiled}\ + %{!maix64:%{!shared:%{g*:-lg}}}\ + %{mpe:-L/usr/lpp/ppe.poe/lib -lmpi -lvtd}\ + %{pthread:-lpthreads} -lc" + +#undef LINK_SPEC +#define LINK_SPEC "-bpT:0x10000000 -bpD:0x20000000 %{!r:-btextro} -bnodelcsect\ + %{static:-bnso %(link_syscalls) } %{shared:-bM:SRE %{!e:-bnoentry}}\ + %{!maix64:%{!shared:%{g*: %(link_libg) }}} %{maix64:-b64}\ + %{mpe:-binitfini:poe_remote_main}" + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "%{!shared:\ + %{maix64:%{pg:gcrt0_64%O%s}%{!pg:%{p:mcrt0_64%O%s}%{!p:crt0_64%O%s}}}\ + %{!maix64:\ + %{pthread:%{pg:gcrt0_r%O%s}%{!pg:%{p:mcrt0_r%O%s}%{!p:crt0_r%O%s}}}\ + %{!pthread:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}}" + +/* AIX V5 typedefs ptrdiff_t as "long" while earlier releases used "int". */ + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "long int" + +/* Type used for wchar_t, as a string used in a declaration. */ +#undef WCHAR_TYPE +#define WCHAR_TYPE (!TARGET_64BIT ? "short unsigned int" : "unsigned int") + +/* Width of wchar_t in bits. */ +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE (!TARGET_64BIT ? 16 : 32) +#define MAX_WCHAR_TYPE_SIZE 32 + +/* AIX V5 uses PowerPC nop (ori 0,0,0) instruction as call glue for PowerPC + and "cror 31,31,31" for POWER architecture. */ + +#undef RS6000_CALL_GLUE +#define RS6000_CALL_GLUE "{cror 31,31,31|nop}" + +/* AIX 4.2 and above provides initialization and finalization function + support from linker command line. */ +#undef HAS_INIT_SECTION +#define HAS_INIT_SECTION + +#undef LD_INIT_SWITCH +#define LD_INIT_SWITCH "-binitfini" diff --git a/contrib/gcc/config/rs6000/altivec.h b/contrib/gcc/config/rs6000/altivec.h index f1387c0..1e2d8c8 100644 --- a/contrib/gcc/config/rs6000/altivec.h +++ b/contrib/gcc/config/rs6000/altivec.h @@ -1102,43 +1102,43 @@ vec_cmple (vector float a1, vector float a2) inline vector signed char vec_cmplt (vector unsigned char a1, vector unsigned char a2) { - return (vector signed char) __builtin_altivec_vcmpgtub ((vector signed char) a1, (vector signed char) a2); + return (vector signed char) __builtin_altivec_vcmpgtub ((vector signed char) a2, (vector signed char) a1); } inline vector signed char vec_cmplt (vector signed char a1, vector signed char a2) { - return (vector signed char) __builtin_altivec_vcmpgtsb ((vector signed char) a1, (vector signed char) a2); + return (vector signed char) __builtin_altivec_vcmpgtsb ((vector signed char) a2, (vector signed char) a1); } inline vector signed short vec_cmplt (vector unsigned short a1, vector unsigned short a2) { - return (vector signed short) __builtin_altivec_vcmpgtuh ((vector signed short) a1, (vector signed short) a2); + return (vector signed short) __builtin_altivec_vcmpgtuh ((vector signed short) a2, (vector signed short) a1); } inline vector signed short vec_cmplt (vector signed short a1, vector signed short a2) { - return (vector signed short) __builtin_altivec_vcmpgtsh ((vector signed short) a1, (vector signed short) a2); + return (vector signed short) __builtin_altivec_vcmpgtsh ((vector signed short) a2, (vector signed short) a1); } inline vector signed int vec_cmplt (vector unsigned int a1, vector unsigned int a2) { - return (vector signed int) __builtin_altivec_vcmpgtuw ((vector signed int) a1, (vector signed int) a2); + return (vector signed int) __builtin_altivec_vcmpgtuw ((vector signed int) a2, (vector signed int) a1); } inline vector signed int vec_cmplt (vector signed int a1, vector signed int a2) { - return (vector signed int) __builtin_altivec_vcmpgtsw ((vector signed int) a1, (vector signed int) a2); + return (vector signed int) __builtin_altivec_vcmpgtsw ((vector signed int) a2, (vector signed int) a1); } inline vector signed int vec_cmplt (vector float a1, vector float a2) { - return (vector signed int) __builtin_altivec_vcmpgtfp ((vector float) a1, (vector float) a2); + return (vector signed int) __builtin_altivec_vcmpgtfp ((vector float) a2, (vector float) a1); } /* vec_ctf */ @@ -6523,7 +6523,7 @@ __ch (__bin_args_eq (vector unsigned char, (a1), vector unsigned char, (a2)), \ #define vec_cmple(a1, a2) __builtin_altivec_vcmpgefp ((a1), (a2)) -#define vec_cmplt(a1, a2) \ +#define vec_cmplt(a2, a1) \ __ch (__bin_args_eq (vector unsigned char, (a1), vector unsigned char, (a2)), \ ((vector signed char) __builtin_altivec_vcmpgtub ((vector signed char) (a1), (vector signed char) (a2))), \ __ch (__bin_args_eq (vector signed char, (a1), vector signed char, (a2)), \ diff --git a/contrib/gcc/config/rs6000/altivec.md b/contrib/gcc/config/rs6000/altivec.md new file mode 100644 index 0000000..25e4b08 --- /dev/null +++ b/contrib/gcc/config/rs6000/altivec.md @@ -0,0 +1,1915 @@ +;; AltiVec patterns. +;; Copyright (C) 2002 Free Software Foundation, Inc. +;; Contributed by Aldy Hernandez (aldy@quesejoda.com) + +;; This file is part of GNU CC. + +;; GNU CC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. + +;; GNU CC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GNU CC; see the file COPYING. If not, write to +;; the Free Software Foundation, 59 Temple Place - Suite 330, +;; Boston, MA 02111-1307, USA. + +;; Generic LVX load instruction. +(define_insn "altivec_lvx_4si" + [(set (match_operand:V4SI 0 "altivec_register_operand" "=v") + (match_operand:V4SI 1 "memory_operand" "m"))] + "TARGET_ALTIVEC" + "lvx %0,%y1" + [(set_attr "type" "vecload")]) + +(define_insn "altivec_lvx_8hi" + [(set (match_operand:V8HI 0 "altivec_register_operand" "=v") + (match_operand:V8HI 1 "memory_operand" "m"))] + "TARGET_ALTIVEC" + "lvx %0,%y1" + [(set_attr "type" "vecload")]) + +(define_insn "altivec_lvx_16qi" + [(set (match_operand:V16QI 0 "altivec_register_operand" "=v") + (match_operand:V16QI 1 "memory_operand" "m"))] + "TARGET_ALTIVEC" + "lvx %0,%y1" + [(set_attr "type" "vecload")]) + +(define_insn "altivec_lvx_4sf" + [(set (match_operand:V4SF 0 "altivec_register_operand" "=v") + (match_operand:V4SF 1 "memory_operand" "m"))] + "TARGET_ALTIVEC" + "lvx %0,%y1" + [(set_attr "type" "vecload")]) + +;; Generic STVX store instruction. +(define_insn "altivec_stvx_4si" + [(set (match_operand:V4SI 0 "memory_operand" "=m") + (match_operand:V4SI 1 "altivec_register_operand" "v"))] + "TARGET_ALTIVEC" + "stvx %1,%y0" + [(set_attr "type" "vecstore")]) + +(define_insn "altivec_stvx_8hi" + [(set (match_operand:V8HI 0 "memory_operand" "=m") + (match_operand:V8HI 1 "altivec_register_operand" "v"))] + "TARGET_ALTIVEC" + "stvx %1,%y0" + [(set_attr "type" "vecstore")]) + +(define_insn "altivec_stvx_16qi" + [(set (match_operand:V16QI 0 "memory_operand" "=m") + (match_operand:V16QI 1 "altivec_register_operand" "v"))] + "TARGET_ALTIVEC" + "stvx %1,%y0" + [(set_attr "type" "vecstore")]) + +(define_insn "altivec_stvx_4sf" + [(set (match_operand:V4SF 0 "memory_operand" "=m") + (match_operand:V4SF 1 "altivec_register_operand" "v"))] + "TARGET_ALTIVEC" + "stvx %1,%y0" + [(set_attr "type" "vecstore")]) + +;; Vector move instructions. +(define_expand "movv4si" + [(set (match_operand:V4SI 0 "nonimmediate_operand" "") + (match_operand:V4SI 1 "any_operand" ""))] + "TARGET_ALTIVEC" + "{ rs6000_emit_move (operands[0], operands[1], V4SImode); DONE; }") + +(define_insn "*movv4si_internal" + [(set (match_operand:V4SI 0 "nonimmediate_operand" "=m,v,v,o,r,r") + (match_operand:V4SI 1 "input_operand" "v,m,v,r,o,r"))] + "TARGET_ALTIVEC" + "@ + stvx %1,%y0 + lvx %0,%y1 + vor %0,%1,%1 + stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 + lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 + mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" + [(set_attr "type" "altivec") + (set_attr "length" "*,*,*,16,16,16")]) + +(define_expand "movv8hi" + [(set (match_operand:V8HI 0 "nonimmediate_operand" "") + (match_operand:V8HI 1 "any_operand" ""))] + "TARGET_ALTIVEC" + "{ rs6000_emit_move (operands[0], operands[1], V8HImode); DONE; }") + +(define_insn "*movv8hi_internal1" + [(set (match_operand:V8HI 0 "nonimmediate_operand" "=m,v,v,o,r,r") + (match_operand:V8HI 1 "input_operand" "v,m,v,r,o,r"))] + "TARGET_ALTIVEC" + "@ + stvx %1,%y0 + lvx %0,%y1 + vor %0,%1,%1 + stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 + lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 + mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" + [(set_attr "type" "altivec") + (set_attr "length" "*,*,*,16,16,16")]) + +(define_expand "movv16qi" + [(set (match_operand:V16QI 0 "nonimmediate_operand" "") + (match_operand:V16QI 1 "any_operand" ""))] + "TARGET_ALTIVEC" + "{ rs6000_emit_move (operands[0], operands[1], V16QImode); DONE; }") + +(define_insn "*movv16qi_internal1" + [(set (match_operand:V16QI 0 "nonimmediate_operand" "=m,v,v,o,r,r") + (match_operand:V16QI 1 "input_operand" "v,m,v,r,o,r"))] + "TARGET_ALTIVEC" + "@ + stvx %1,%y0 + lvx %0,%y1 + vor %0,%1,%1 + stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 + lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 + mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" + [(set_attr "type" "altivec") + (set_attr "length" "*,*,*,16,16,16")]) + +(define_expand "movv4sf" + [(set (match_operand:V4SF 0 "nonimmediate_operand" "") + (match_operand:V4SF 1 "any_operand" ""))] + "TARGET_ALTIVEC" + "{ rs6000_emit_move (operands[0], operands[1], V4SFmode); DONE; }") + +(define_insn "*movv4sf_internal1" + [(set (match_operand:V4SF 0 "nonimmediate_operand" "=m,v,v,o,r,r") + (match_operand:V4SF 1 "input_operand" "v,m,v,r,o,r"))] + "TARGET_ALTIVEC" + "@ + stvx %1,%y0 + lvx %0,%y1 + vor %0,%1,%1 + stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 + lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 + mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" + [(set_attr "type" "altivec") + (set_attr "length" "*,*,*,16,16,16")]) + +(define_insn "get_vrsave_internal" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(reg:SI 109)] 214))] + "TARGET_ALTIVEC" + "* +{ + if (TARGET_MACHO) + return \"mfspr %0,256\"; + else + return \"mfvrsave %0\"; +}" + [(set_attr "type" "altivec")]) + +(define_insn "*set_vrsave_internal" + [(match_parallel 0 "vrsave_operation" + [(set (reg:SI 109) + (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r") + (reg:SI 109)] 30))])] + "TARGET_ALTIVEC" + "* +{ + if (TARGET_MACHO) + return \"mtspr 256,%1\"; + else + return \"mtvrsave %1\"; +}" + [(set_attr "type" "altivec")]) + +;; Vector clears +(define_insn "*movv4si_const0" + [(set (match_operand:V4SI 0 "altivec_register_operand" "=v") + (match_operand:V4SI 1 "zero_constant" ""))] + "TARGET_ALTIVEC" + "vxor %0,%0,%0" + [(set_attr "type" "vecsimple")]) + +(define_insn "*movv4sf_const0" + [(set (match_operand:V4SF 0 "altivec_register_operand" "=v") + (match_operand:V4SF 1 "zero_constant" ""))] + + "TARGET_ALTIVEC" + "vxor %0,%0,%0" + [(set_attr "type" "vecsimple")]) + +(define_insn "*movv8hi_const0" + [(set (match_operand:V8HI 0 "altivec_register_operand" "=v") + (match_operand:V8HI 1 "zero_constant" ""))] + "TARGET_ALTIVEC" + "vxor %0,%0,%0" + [(set_attr "type" "vecsimple")]) + +(define_insn "*movv16qi_const0" + [(set (match_operand:V16QI 0 "altivec_register_operand" "=v") + (match_operand:V16QI 1 "zero_constant" ""))] + "TARGET_ALTIVEC" + "vxor %0,%0,%0" + [(set_attr "type" "vecsimple")]) + +;; Simple binary operations. + +(define_insn "addv16qi3" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (plus:V16QI (match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vaddubm %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "addv8hi3" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (plus:V8HI (match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vadduhm %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "addv4si3" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (plus:V4SI (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vadduwm %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "addv4sf3" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (plus:V4SF (match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vaddfp %0,%1,%2" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vaddcuw" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 35))] + "TARGET_ALTIVEC" + "vaddcuw %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vaddubs" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] 36)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vaddubs %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vaddsbs" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] 37)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vaddsbs %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vadduhs" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 38)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vadduhs %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vaddshs" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 39)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vaddshs %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vadduws" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 40)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vadduws %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vaddsws" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 41)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vaddsws %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "andv4si3" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (and:V4SI (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vand %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vandc" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (and:V4SI (match_operand:V4SI 1 "register_operand" "v") + (not:V4SI (match_operand:V4SI 2 "register_operand" "v"))))] + "TARGET_ALTIVEC" + "vandc %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vavgub" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] 44))] + "TARGET_ALTIVEC" + "vavgub %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vavgsb" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] 45))] + "TARGET_ALTIVEC" + "vavgsb %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vavguh" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 46))] + "TARGET_ALTIVEC" + "vavguh %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vavgsh" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 47))] + "TARGET_ALTIVEC" + "vavgsh %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vavguw" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 48))] + "TARGET_ALTIVEC" + "vavguw %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vavgsw" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 49))] + "TARGET_ALTIVEC" + "vavgsw %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vcmpbfp" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v")] 50))] + "TARGET_ALTIVEC" + "vcmpbfp %0,%1,%2" + [(set_attr "type" "veccmp")]) + +(define_insn "altivec_vcmpequb" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] 51))] + "TARGET_ALTIVEC" + "vcmpequb %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vcmpequh" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 52))] + "TARGET_ALTIVEC" + "vcmpequh %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vcmpequw" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 53))] + "TARGET_ALTIVEC" + "vcmpequw %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vcmpeqfp" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v")] 54))] + "TARGET_ALTIVEC" + "vcmpeqfp %0,%1,%2" + [(set_attr "type" "veccmp")]) + +(define_insn "altivec_vcmpgefp" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v")] 55))] + "TARGET_ALTIVEC" + "vcmpgefp %0,%1,%2" + [(set_attr "type" "veccmp")]) + +(define_insn "altivec_vcmpgtub" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] 56))] + "TARGET_ALTIVEC" + "vcmpgtub %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vcmpgtsb" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] 57))] + "TARGET_ALTIVEC" + "vcmpgtsb %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vcmpgtuh" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 58))] + "TARGET_ALTIVEC" + "vcmpgtuh %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vcmpgtsh" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 59))] + "TARGET_ALTIVEC" + "vcmpgtsh %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vcmpgtuw" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 60))] + "TARGET_ALTIVEC" + "vcmpgtuw %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vcmpgtsw" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 61))] + "TARGET_ALTIVEC" + "vcmpgtsw %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vcmpgtfp" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v")] 62))] + "TARGET_ALTIVEC" + "vcmpgtfp %0,%1,%2" + [(set_attr "type" "veccmp")]) + +;; Fused multiply add +(define_insn "altivec_vmaddfp" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v")) + (match_operand:V4SF 3 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vmaddfp %0,%1,%2,%3" + [(set_attr "type" "vecfloat")]) + +;; We do multiply as a fused multiply-add with an add of a -0.0 vector. + +(define_expand "mulv4sf3" + [(use (match_operand:V4SF 0 "register_operand" "")) + (use (match_operand:V4SF 1 "register_operand" "")) + (use (match_operand:V4SF 2 "register_operand" ""))] + "TARGET_ALTIVEC && TARGET_FUSED_MADD" + " +{ + rtx neg0; + + /* Generate [-0.0, -0.0, -0.0, -0.0]. */ + neg0 = gen_reg_rtx (V4SFmode); + emit_insn (gen_altivec_vspltisw_v4sf (neg0, GEN_INT (-1))); + emit_insn (gen_altivec_vslw_v4sf (neg0, neg0, neg0)); + + /* Use the multiply-add. */ + emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2], + neg0)); + DONE; +}") + +;; Fused multiply subtract +(define_insn "altivec_vnmsubfp" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v")) + (match_operand:V4SF 3 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vnmsubfp %0,%1,%2,%3" + [(set_attr "type" "vecfloat")]) + + +(define_insn "altivec_vmsumubm" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v") + (match_operand:V4SI 3 "register_operand" "v")] 65))] + "TARGET_ALTIVEC" + "vmsumubm %0, %1, %2, %3" + [(set_attr "type" "veccomplex")]) + +(define_insn "altivec_vmsummbm" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v") + (match_operand:V4SI 3 "register_operand" "v")] 66))] + "TARGET_ALTIVEC" + "vmsumubm %0, %1, %2, %3" + [(set_attr "type" "veccomplex")]) + +(define_insn "altivec_vmsumuhm" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v") + (match_operand:V4SI 3 "register_operand" "v")] 67))] + "TARGET_ALTIVEC" + "vmsumuhm %0, %1, %2, %3" + [(set_attr "type" "veccomplex")]) + +(define_insn "altivec_vmsumshm" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v") + (match_operand:V4SI 3 "register_operand" "v")] 68))] + "TARGET_ALTIVEC" + "vmsumshm %0, %1, %2, %3" + [(set_attr "type" "veccomplex")]) + +(define_insn "altivec_vmsumuhs" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v") + (match_operand:V4SI 3 "register_operand" "v")] 69)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vmsumuhs %0, %1, %2, %3" + [(set_attr "type" "veccomplex")]) + +(define_insn "altivec_vmsumshs" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v") + (match_operand:V4SI 3 "register_operand" "v")] 70)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vmsumshs %0, %1, %2, %3" + [(set_attr "type" "veccomplex")]) + +(define_insn "umaxv16qi3" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (umax:V16QI (match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vmaxub %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "smaxv16qi3" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (smax:V16QI (match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vmaxsb %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "umaxv8hi3" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (umax:V8HI (match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vmaxuh %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "smaxv8hi3" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (smax:V8HI (match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vmaxsh %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "umaxv4si3" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (umax:V4SI (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vmaxuw %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "smaxv4si3" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (smax:V4SI (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vmaxsw %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "smaxv4sf3" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (smax:V4SF (match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vmaxfp %0,%1,%2" + [(set_attr "type" "veccmp")]) + +(define_insn "altivec_vmhaddshs" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v") + (match_operand:V8HI 3 "register_operand" "v")] 71)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vmhaddshs %0, %1, %2, %3" + [(set_attr "type" "veccomplex")]) +(define_insn "altivec_vmhraddshs" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v") + (match_operand:V8HI 3 "register_operand" "v")] 72)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vmhraddshs %0, %1, %2, %3" + [(set_attr "type" "veccomplex")]) +(define_insn "altivec_vmladduhm" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v") + (match_operand:V8HI 3 "register_operand" "v")] 73))] + "TARGET_ALTIVEC" + "vmladduhm %0, %1, %2, %3" + [(set_attr "type" "veccomplex")]) + +(define_insn "altivec_vmrghb" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v") + (parallel [(const_int 8) + (const_int 9) + (const_int 10) + (const_int 11) + (const_int 12) + (const_int 13) + (const_int 14) + (const_int 15) + (const_int 0) + (const_int 1) + (const_int 2) + (const_int 3) + (const_int 4) + (const_int 5) + (const_int 6) + (const_int 7)])) + (match_operand:V16QI 2 "register_operand" "v") + (const_int 255)))] + "TARGET_ALTIVEC" + "vmrghb %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vmrghh" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v") + (parallel [(const_int 4) + (const_int 5) + (const_int 6) + (const_int 7) + (const_int 0) + (const_int 1) + (const_int 2) + (const_int 3)])) + (match_operand:V8HI 2 "register_operand" "v") + (const_int 15)))] + "TARGET_ALTIVEC" + "vmrghh %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vmrghw" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v") + (parallel [(const_int 2) + (const_int 3) + (const_int 0) + (const_int 1)])) + (match_operand:V4SI 2 "register_operand" "v") + (const_int 12)))] + "TARGET_ALTIVEC" + "vmrghw %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vmrglb" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v") + (parallel [(const_int 0) + (const_int 1) + (const_int 2) + (const_int 3) + (const_int 4) + (const_int 5) + (const_int 6) + (const_int 7) + (const_int 8) + (const_int 9) + (const_int 10) + (const_int 11) + (const_int 12) + (const_int 13) + (const_int 14) + (const_int 15)])) + (match_operand:V16QI 1 "register_operand" "v") + (const_int 255)))] + "TARGET_ALTIVEC" + "vmrglb %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vmrglh" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v") + (parallel [(const_int 0) + (const_int 1) + (const_int 2) + (const_int 3) + (const_int 4) + (const_int 5) + (const_int 6) + (const_int 7)])) + (match_operand:V8HI 1 "register_operand" "v") + (const_int 15)))] + "TARGET_ALTIVEC" + "vmrglh %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vmrglw" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v") + (parallel [(const_int 0) + (const_int 1) + (const_int 2) + (const_int 3)])) + (match_operand:V4SI 1 "register_operand" "v") + (const_int 12)))] + "TARGET_ALTIVEC" + "vmrglw %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "uminv16qi3" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (umin:V16QI (match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vminub %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "sminv16qi3" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (smin:V16QI (match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vminsb %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "uminv8hi3" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (umin:V8HI (match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vminuh %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "sminv8hi3" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (smin:V8HI (match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vminsh %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "uminv4si3" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (umin:V4SI (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vminuw %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "sminv4si3" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (smin:V4SI (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vminsw %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "sminv4sf3" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (smin:V4SF (match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vminfp %0,%1,%2" + [(set_attr "type" "veccmp")]) + +(define_insn "altivec_vmuleub" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] 83))] + "TARGET_ALTIVEC" + "vmuleub %0,%1,%2" + [(set_attr "type" "veccomplex")]) + +(define_insn "altivec_vmulesb" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] 84))] + "TARGET_ALTIVEC" + "vmulesb %0,%1,%2" + [(set_attr "type" "veccomplex")]) + +(define_insn "altivec_vmuleuh" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 85))] + "TARGET_ALTIVEC" + "vmuleuh %0,%1,%2" + [(set_attr "type" "veccomplex")]) + +(define_insn "altivec_vmulesh" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 86))] + "TARGET_ALTIVEC" + "vmulesh %0,%1,%2" + [(set_attr "type" "veccomplex")]) + +(define_insn "altivec_vmuloub" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] 87))] + "TARGET_ALTIVEC" + "vmuloub %0,%1,%2" + [(set_attr "type" "veccomplex")]) + +(define_insn "altivec_vmulosb" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] 88))] + "TARGET_ALTIVEC" + "vmulosb %0,%1,%2" + [(set_attr "type" "veccomplex")]) + +(define_insn "altivec_vmulouh" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 89))] + "TARGET_ALTIVEC" + "vmulouh %0,%1,%2" + [(set_attr "type" "veccomplex")]) + +(define_insn "altivec_vmulosh" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 90))] + "TARGET_ALTIVEC" + "vmulosh %0,%1,%2" + [(set_attr "type" "veccomplex")]) + +(define_insn "altivec_vnor" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (not:V4SI (ior:V4SI (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v"))))] + "TARGET_ALTIVEC" + "vnor %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "iorv4si3" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (ior:V4SI (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vor %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vpkuhum" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 93))] + "TARGET_ALTIVEC" + "vpkuhum %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vpkuwum" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 94))] + "TARGET_ALTIVEC" + "vpkuwum %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vpkpx" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 95))] + "TARGET_ALTIVEC" + "vpkpx %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vpkuhss" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 96)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vpkuhss %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vpkshss" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 97)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vpkshss %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vpkuwss" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 98)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vpkuwss %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vpkswss" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 99)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vpkswss %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vpkuhus" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 100)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vpkuhus %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vpkshus" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 101)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vpkshus %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vpkuwus" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 102)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vpkuwus %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vpkswus" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 103)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vpkswus %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vrlb" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] 104))] + "TARGET_ALTIVEC" + "vrlb %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vrlh" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 105))] + "TARGET_ALTIVEC" + "vrlh %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vrlw" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 106))] + "TARGET_ALTIVEC" + "vrlw %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vslb" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] 107))] + "TARGET_ALTIVEC" + "vslb %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vslh" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 108))] + "TARGET_ALTIVEC" + "vslh %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vslw" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 109))] + "TARGET_ALTIVEC" + "vslw %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vslw_v4sf" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v")] 109))] + "TARGET_ALTIVEC" + "vslw %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vsl" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 110))] + "TARGET_ALTIVEC" + "vsl %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vslo" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 111))] + "TARGET_ALTIVEC" + "vslo %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vsrb" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] 112))] + "TARGET_ALTIVEC" + "vsrb %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vsrh" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 113))] + "TARGET_ALTIVEC" + "vsrh %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vsrw" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 114))] + "TARGET_ALTIVEC" + "vsrw %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vsrab" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] 115))] + "TARGET_ALTIVEC" + "vsrab %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vsrah" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 116))] + "TARGET_ALTIVEC" + "vsrah %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vsraw" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 117))] + "TARGET_ALTIVEC" + "vsraw %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vsr" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 118))] + "TARGET_ALTIVEC" + "vsr %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vsro" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 119))] + "TARGET_ALTIVEC" + "vsro %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "subv16qi3" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (minus:V16QI (match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vsububm %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "subv8hi3" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (minus:V8HI (match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vsubuhm %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "subv4si3" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (minus:V4SI (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vsubuwm %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "subv4sf3" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (minus:V4SF (match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vsubfp %0,%1,%2" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vsubcuw" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 124))] + "TARGET_ALTIVEC" + "vsubcuw %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vsububs" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] 125)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vsububs %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vsubsbs" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v")] 126)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vsubsbs %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vsubuhs" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 127)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vsubuhs %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vsubshs" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v")] 128)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vsubshs %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vsubuws" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 129)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vsubuws %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vsubsws" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 130)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vsubsws %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vsum4ubs" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 131)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vsum4ubs %0,%1,%2" + [(set_attr "type" "veccomplex")]) + +(define_insn "altivec_vsum4sbs" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 132)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vsum4sbs %0,%1,%2" + [(set_attr "type" "veccomplex")]) + +(define_insn "altivec_vsum4shs" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 133)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vsum4shs %0,%1,%2" + [(set_attr "type" "veccomplex")]) + +(define_insn "altivec_vsum2sws" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 134)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vsum2sws %0,%1,%2" + [(set_attr "type" "veccomplex")]) + +(define_insn "altivec_vsumsws" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")] 135)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vsumsws %0,%1,%2" + [(set_attr "type" "veccomplex")]) + +(define_insn "xorv4si3" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (xor:V4SI (match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vxor %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vspltb" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:QI 2 "immediate_operand" "i")] 136))] + "TARGET_ALTIVEC" + "vspltb %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vsplth" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:QI 2 "immediate_operand" "i")] 137))] + "TARGET_ALTIVEC" + "vsplth %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vspltw" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:QI 2 "immediate_operand" "i")] 138))] + "TARGET_ALTIVEC" + "vspltw %0,%1,%2" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vspltisb" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:QI 1 "immediate_operand" "i")] 139))] + "TARGET_ALTIVEC" + "vspltisb %0, %1" + [(set_attr "type" "vecsimple")]) + + +(define_insn "altivec_vspltish" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:QI 1 "immediate_operand" "i")] 140))] + "TARGET_ALTIVEC" + "vspltish %0, %1" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vspltisw" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:QI 1 "immediate_operand" "i")] 141))] + "TARGET_ALTIVEC" + "vspltisw %0, %1" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_vspltisw_v4sf" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:QI 1 "immediate_operand" "i")] 142))] + "TARGET_ALTIVEC" + "vspltisw %0, %1" + [(set_attr "type" "vecsimple")]) + +(define_insn "ftruncv4sf2" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))] + "TARGET_ALTIVEC" + "vrfiz %0, %1" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vperm_4si" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v") + (match_operand:V16QI 3 "register_operand" "v")] 144))] + "TARGET_ALTIVEC" + "vperm %0,%1,%2,%3" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vperm_4sf" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v") + (match_operand:V16QI 3 "register_operand" "v")] 145))] + "TARGET_ALTIVEC" + "vperm %0,%1,%2,%3" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vperm_8hi" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v") + (match_operand:V16QI 3 "register_operand" "v")] 146))] + "TARGET_ALTIVEC" + "vperm %0,%1,%2,%3" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vperm_16qi" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v") + (match_operand:V16QI 3 "register_operand" "v")] 147))] + "TARGET_ALTIVEC" + "vperm %0,%1,%2,%3" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vrfip" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 148))] + "TARGET_ALTIVEC" + "vrfip %0, %1" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vrfin" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 149))] + "TARGET_ALTIVEC" + "vrfin %0, %1" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vrfim" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 150))] + "TARGET_ALTIVEC" + "vrfim %0, %1" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vcfux" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:QI 2 "immediate_operand" "i")] 151))] + "TARGET_ALTIVEC" + "vcfux %0, %1, %2" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vcfsx" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:QI 2 "immediate_operand" "i")] 152))] + "TARGET_ALTIVEC" + "vcfsx %0, %1, %2" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vctuxs" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") + (match_operand:QI 2 "immediate_operand" "i")] 153)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vctuxs %0, %1, %2" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vctsxs" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") + (match_operand:QI 2 "immediate_operand" "i")] 154)) + (set (reg:SI 110) (unspec:SI [(const_int 0)] 213))] + "TARGET_ALTIVEC" + "vctsxs %0, %1, %2" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vlogefp" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 155))] + "TARGET_ALTIVEC" + "vlogefp %0, %1" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vexptefp" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 156))] + "TARGET_ALTIVEC" + "vexptefp %0, %1" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vrsqrtefp" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 157))] + "TARGET_ALTIVEC" + "vrsqrtefp %0, %1" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vrefp" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 158))] + "TARGET_ALTIVEC" + "vrefp %0, %1" + [(set_attr "type" "vecfloat")]) + +(define_insn "altivec_vsel_4si" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v") + (match_operand:V4SI 3 "register_operand" "v")] 159))] + "TARGET_ALTIVEC" + "vsel %0,%1,%2,%3" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vsel_4sf" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v") + (match_operand:V4SI 3 "register_operand" "v")] 160))] + "TARGET_ALTIVEC" + "vsel %0,%1,%2,%3" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vsel_8hi" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v") + (match_operand:V8HI 3 "register_operand" "v")] 161))] + "TARGET_ALTIVEC" + "vsel %0,%1,%2,%3" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vsel_16qi" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v") + (match_operand:V16QI 3 "register_operand" "v")] 162))] + "TARGET_ALTIVEC" + "vsel %0,%1,%2,%3" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vsldoi_4si" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v") + (match_operand:QI 3 "immediate_operand" "i")] 163))] + "TARGET_ALTIVEC" + "vsldoi %0, %1, %2, %3" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vsldoi_4sf" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v") + (match_operand:QI 3 "immediate_operand" "i")] 164))] + "TARGET_ALTIVEC" + "vsldoi %0, %1, %2, %3" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vsldoi_8hi" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v") + (match_operand:QI 3 "immediate_operand" "i")] 165))] + "TARGET_ALTIVEC" + "vsldoi %0, %1, %2, %3" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vsldoi_16qi" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v") + (match_operand:QI 3 "immediate_operand" "i")] 166))] + "TARGET_ALTIVEC" + "vsldoi %0, %1, %2, %3" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vupkhsb" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 167))] + "TARGET_ALTIVEC" + "vupkhsb %0, %1" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vupkhpx" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 168))] + "TARGET_ALTIVEC" + "vupkhpx %0, %1" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vupkhsh" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 169))] + "TARGET_ALTIVEC" + "vupkhsh %0, %1" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vupklsb" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 170))] + "TARGET_ALTIVEC" + "vupklsb %0, %1" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vupklpx" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 171))] + "TARGET_ALTIVEC" + "vupklpx %0, %1" + [(set_attr "type" "vecperm")]) + +(define_insn "altivec_vupklsh" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 172))] + "TARGET_ALTIVEC" + "vupklsh %0, %1" + [(set_attr "type" "vecperm")]) + +;; AltiVec predicates. + +(define_expand "cr6_test_for_zero" + [(set (match_operand:SI 0 "register_operand" "=r") + (eq:SI (reg:CC 74) + (const_int 0)))] + "TARGET_ALTIVEC" + "") + +(define_expand "cr6_test_for_zero_reverse" + [(set (match_operand:SI 0 "register_operand" "=r") + (eq:SI (reg:CC 74) + (const_int 0))) + (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))] + "TARGET_ALTIVEC" + "") + +(define_expand "cr6_test_for_lt" + [(set (match_operand:SI 0 "register_operand" "=r") + (lt:SI (reg:CC 74) + (const_int 0)))] + "TARGET_ALTIVEC" + "") + +(define_expand "cr6_test_for_lt_reverse" + [(set (match_operand:SI 0 "register_operand" "=r") + (lt:SI (reg:CC 74) + (const_int 0))) + (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))] + "TARGET_ALTIVEC" + "") + +;; We can get away with generating the opcode on the fly (%3 below) +;; because all the predicates have the same scheduling parameters. + +(define_insn "altivec_predicate_v4si" + [(set (reg:CC 74) + (unspec:CC [(match_operand:V4SI 1 "register_operand" "v") + (match_operand:V4SI 2 "register_operand" "v") + (match_operand 3 "any_operand" "")] 173)) + (clobber (match_scratch:V4SI 0 "=v"))] + "TARGET_ALTIVEC" + "%3 %0,%1,%2" +[(set_attr "type" "veccmp")]) + +(define_insn "altivec_predicate_v4sf" + [(set (reg:CC 74) + (unspec:CC [(match_operand:V4SF 1 "register_operand" "v") + (match_operand:V4SF 2 "register_operand" "v") + (match_operand 3 "any_operand" "")] 174)) + (clobber (match_scratch:V4SF 0 "=v"))] + "TARGET_ALTIVEC" + "%3 %0,%1,%2" +[(set_attr "type" "veccmp")]) + +(define_insn "altivec_predicate_v8hi" + [(set (reg:CC 74) + (unspec:CC [(match_operand:V8HI 1 "register_operand" "v") + (match_operand:V8HI 2 "register_operand" "v") + (match_operand 3 "any_operand" "")] 175)) + (clobber (match_scratch:V8HI 0 "=v"))] + "TARGET_ALTIVEC" + "%3 %0,%1,%2" +[(set_attr "type" "veccmp")]) + +(define_insn "altivec_predicate_v16qi" + [(set (reg:CC 74) + (unspec:CC [(match_operand:V16QI 1 "register_operand" "v") + (match_operand:V16QI 2 "register_operand" "v") + (match_operand 3 "any_operand" "")] 175)) + (clobber (match_scratch:V16QI 0 "=v"))] + "TARGET_ALTIVEC" + "%3 %0,%1,%2" +[(set_attr "type" "veccmp")]) + +(define_insn "altivec_mtvscr" + [(set (reg:SI 110) + (unspec_volatile:SI + [(match_operand:V4SI 0 "register_operand" "v")] 186))] + "TARGET_ALTIVEC" + "mtvscr %0" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_mfvscr" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec_volatile:V8HI [(reg:SI 110)] 187))] + "TARGET_ALTIVEC" + "mfvscr %0" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_dssall" + [(unspec [(const_int 0)] 188)] + "TARGET_ALTIVEC" + "dssall" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_dss" + [(unspec [(match_operand:QI 0 "immediate_operand" "i")] 189)] + "TARGET_ALTIVEC" + "dss %0" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_dst" + [(unspec [(match_operand:SI 0 "register_operand" "b") + (match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "i")] 190)] + "TARGET_ALTIVEC" + "dst %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_dstt" + [(unspec [(match_operand:SI 0 "register_operand" "b") + (match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "i")] 191)] + "TARGET_ALTIVEC" + "dstt %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_dstst" + [(unspec [(match_operand:SI 0 "register_operand" "b") + (match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "i")] 192)] + "TARGET_ALTIVEC" + "dstst %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_dststt" + [(unspec [(match_operand:SI 0 "register_operand" "b") + (match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "i")] 193)] + "TARGET_ALTIVEC" + "dststt %0,%1,%2" + [(set_attr "type" "vecsimple")]) + +(define_insn "altivec_lvsl" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:SI 1 "register_operand" "b") + (match_operand:SI 2 "register_operand" "r")] 194))] + "TARGET_ALTIVEC" + "lvsl %0,%1,%2" + [(set_attr "type" "vecload")]) + +(define_insn "altivec_lvsr" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:SI 1 "register_operand" "b") + (match_operand:SI 2 "register_operand" "r")] 195))] + "TARGET_ALTIVEC" + "lvsr %0,%1,%2" + [(set_attr "type" "vecload")]) + +;; Parallel some of the LVE* and STV*'s with unspecs because some have +;; identical rtl but different instructions-- and gcc gets confused. + +(define_insn "altivec_lvebx" + [(parallel + [(set (match_operand:V16QI 0 "register_operand" "=v") + (mem:V16QI (plus:SI (match_operand:SI 1 "register_operand" "b") + (match_operand:SI 2 "register_operand" "r")))) + (unspec [(const_int 0)] 196)])] + "TARGET_ALTIVEC" + "lvebx %0,%1,%2" + [(set_attr "type" "vecload")]) + +(define_insn "altivec_lvehx" + [(parallel + [(set (match_operand:V8HI 0 "register_operand" "=v") + (mem:V8HI + (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b") + (match_operand:SI 2 "register_operand" "r")) + (const_int -2)))) + (unspec [(const_int 0)] 197)])] + "TARGET_ALTIVEC" + "lvehx %0,%1,%2" + [(set_attr "type" "vecload")]) + +(define_insn "altivec_lvewx" + [(parallel + [(set (match_operand:V4SI 0 "register_operand" "=v") + (mem:V4SI + (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b") + (match_operand:SI 2 "register_operand" "r")) + (const_int -4)))) + (unspec [(const_int 0)] 198)])] + "TARGET_ALTIVEC" + "lvewx %0,%1,%2" + [(set_attr "type" "vecload")]) + +(define_insn "altivec_lvxl" + [(parallel + [(set (match_operand:V4SI 0 "register_operand" "=v") + (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b") + (match_operand:SI 2 "register_operand" "r")))) + (unspec [(const_int 0)] 213)])] + "TARGET_ALTIVEC" + "lvxl %0,%1,%2" + [(set_attr "type" "vecload")]) + +(define_insn "altivec_lvx" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b") + (match_operand:SI 2 "register_operand" "r"))))] + "TARGET_ALTIVEC" + "lvx %0,%1,%2" + [(set_attr "type" "vecload")]) + +(define_insn "altivec_stvx" + [(parallel + [(set (mem:V4SI + (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") + (match_operand:SI 1 "register_operand" "r")) + (const_int -16))) + (match_operand:V4SI 2 "register_operand" "v")) + (unspec [(const_int 0)] 201)])] + "TARGET_ALTIVEC" + "stvx %2,%0,%1" + [(set_attr "type" "vecstore")]) + +(define_insn "altivec_stvxl" + [(parallel + [(set (mem:V4SI + (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") + (match_operand:SI 1 "register_operand" "r")) + (const_int -16))) + (match_operand:V4SI 2 "register_operand" "v")) + (unspec [(const_int 0)] 202)])] + "TARGET_ALTIVEC" + "stvxl %2,%0,%1" + [(set_attr "type" "vecstore")]) + +(define_insn "altivec_stvebx" + [(parallel + [(set (mem:V16QI + (plus:SI (match_operand:SI 0 "register_operand" "b") + (match_operand:SI 1 "register_operand" "r"))) + (match_operand:V16QI 2 "register_operand" "v")) + (unspec [(const_int 0)] 203)])] + "TARGET_ALTIVEC" + "stvebx %2,%0,%1" + [(set_attr "type" "vecstore")]) + +(define_insn "altivec_stvehx" + [(parallel + [(set (mem:V8HI + (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") + (match_operand:SI 1 "register_operand" "r")) + (const_int -2))) + (match_operand:V8HI 2 "register_operand" "v")) + (unspec [(const_int 0)] 204)])] + "TARGET_ALTIVEC" + "stvehx %2,%0,%1" + [(set_attr "type" "vecstore")]) + +(define_insn "altivec_stvewx" + [(parallel + [(set (mem:V4SI + (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") + (match_operand:SI 1 "register_operand" "r")) + (const_int -4))) + (match_operand:V4SI 2 "register_operand" "v")) + (unspec [(const_int 0)] 205)])] + "TARGET_ALTIVEC" + "stvewx %2,%0,%1" + [(set_attr "type" "vecstore")]) + +(define_insn "absv16qi2" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (abs:V16QI (match_operand:V16QI 1 "register_operand" "v"))) + (clobber (match_scratch:V16QI 2 "=&v")) + (clobber (match_scratch:V16QI 3 "=&v"))] + "TARGET_ALTIVEC" + "vspltisb %2,0\;vsububm %3,%2,%1\;vmaxsb %0,%1,%3" + [(set_attr "type" "altivec") + (set_attr "length" "12")]) + +(define_insn "absv8hi2" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (abs:V8HI (match_operand:V8HI 1 "register_operand" "v"))) + (clobber (match_scratch:V8HI 2 "=&v")) + (clobber (match_scratch:V8HI 3 "=&v"))] + "TARGET_ALTIVEC" + "vspltisb %2,0\;vsubuhm %3,%2,%1\;vmaxsh %0,%1,%3" + [(set_attr "type" "altivec") + (set_attr "length" "12")]) + +(define_insn "absv4si2" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (abs:V4SI (match_operand:V4SI 1 "register_operand" "v"))) + (clobber (match_scratch:V4SI 2 "=&v")) + (clobber (match_scratch:V4SI 3 "=&v"))] + "TARGET_ALTIVEC" + "vspltisb %2,0\;vsubuwm %3,%2,%1\;vmaxsw %0,%1,%3" + [(set_attr "type" "altivec") + (set_attr "length" "12")]) + +(define_insn "absv4sf2" + [(set (match_operand:V4SF 0 "register_operand" "=v") + (abs:V4SF (match_operand:V4SF 1 "register_operand" "v"))) + (clobber (match_scratch:V4SF 2 "=&v")) + (clobber (match_scratch:V4SF 3 "=&v"))] + "TARGET_ALTIVEC" + "vspltisw %2, -1\;vslw %3,%2,%2\;vandc %0,%1,%3" + [(set_attr "type" "altivec") + (set_attr "length" "12")]) + +(define_insn "altivec_abss_v16qi" + [(set (match_operand:V16QI 0 "register_operand" "=v") + (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")] 210)) + (clobber (match_scratch:V16QI 2 "=&v")) + (clobber (match_scratch:V16QI 3 "=&v"))] + "TARGET_ALTIVEC" + "vspltisb %2,0\;vsubsbs %3,%2,%1\;vmaxsb %0,%1,%3" + [(set_attr "type" "altivec") + (set_attr "length" "12")]) + +(define_insn "altivec_abss_v8hi" + [(set (match_operand:V8HI 0 "register_operand" "=v") + (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")] 211)) + (clobber (match_scratch:V8HI 2 "=&v")) + (clobber (match_scratch:V8HI 3 "=&v"))] + "TARGET_ALTIVEC" + "vspltisb %2,0\;vsubshs %3,%2,%1\;vmaxsh %0,%1,%3" + [(set_attr "type" "altivec") + (set_attr "length" "12")]) + +(define_insn "altivec_abss_v4si" + [(set (match_operand:V4SI 0 "register_operand" "=v") + (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")] 212)) + (clobber (match_scratch:V4SI 2 "=&v")) + (clobber (match_scratch:V4SI 3 "=&v"))] + "TARGET_ALTIVEC" + "vspltisb %2,0\;vsubsws %3,%2,%1\;vmaxsw %0,%1,%3" + [(set_attr "type" "altivec") + (set_attr "length" "12")]) diff --git a/contrib/gcc/config/rs6000/beos.h b/contrib/gcc/config/rs6000/beos.h index f569c3c..1f788c3 100644 --- a/contrib/gcc/config/rs6000/beos.h +++ b/contrib/gcc/config/rs6000/beos.h @@ -38,15 +38,21 @@ Boston, MA 02111-1307, USA. */ #undef ASM_SPEC #define ASM_SPEC "-u %(asm_cpu)" -#undef CPP_PREDEFINES +#undef TARGET_OS_CPP_BUILTINS /* __POWERPC__ must be defined for some header files */ -#define CPP_PREDEFINES "-D__BEOS__ -D__POWERPC__ -Asystem=beos -Acpu=powerpc -Amachine=powerpc" +#define TARGET_OS_CPP_BUILTINS() \ + do \ + { \ + builtin_define ("__BEOS__"); \ + builtin_define ("__POWERPC__"); \ + builtin_assert ("system=beos"); \ + builtin_assert ("cpu=powerpc"); \ + builtin_assert ("machine=powerpc"); \ + } \ + while (0) #undef CPP_SPEC -#define CPP_SPEC "%{posix: -D_POSIX_SOURCE} %(cpp_cpu)" - -#undef CPP_DEFAULT_SPEC -#define CPP_DEFAULT_SPEC "-D_ARCH_PPC" +#define CPP_SPEC "%{posix: -D_POSIX_SOURCE}" /* This is the easiest way to disable use of gcc's builtin alloca, which in the current BeOS release (DR9) is a problem because of the diff --git a/contrib/gcc/config/rs6000/darwin-tramp.asm b/contrib/gcc/config/rs6000/darwin-tramp.asm index 02c7be6..22ce80a 100644 --- a/contrib/gcc/config/rs6000/darwin-tramp.asm +++ b/contrib/gcc/config/rs6000/darwin-tramp.asm @@ -64,7 +64,7 @@ ___trampoline_setup: bcl 20,31,LCF0 /* load up __trampoline_initial into r7 */ LCF0: mflr r11 - addi r7,r11,ha16(LTRAMP-LCF0) + addis r7,r11,ha16(LTRAMP-LCF0) lwz r7,lo16(LTRAMP-LCF0)(r7) subi r7,r7,4 li r8,trampoline_size /* verify trampoline big enough */ diff --git a/contrib/gcc/config/rs6000/darwin.h b/contrib/gcc/config/rs6000/darwin.h index 81c24e7..b3468f2 100644 --- a/contrib/gcc/config/rs6000/darwin.h +++ b/contrib/gcc/config/rs6000/darwin.h @@ -36,7 +36,7 @@ Boston, MA 02111-1307, USA. */ #define TARGET_NO_TOC 1 /* Handle #pragma weak and #pragma pack. */ -#define HANDLE_SYSV_PRAGMA +#define HANDLE_SYSV_PRAGMA 1 /* The Darwin ABI always includes AltiVec, can't be (validly) turned off. */ @@ -44,12 +44,23 @@ Boston, MA 02111-1307, USA. */ #define SUBTARGET_OVERRIDE_OPTIONS \ rs6000_altivec_abi = 1; -#define CPP_PREDEFINES "-D__ppc__ -D__POWERPC__ -D__NATURAL_ALIGNMENT__ -D__MACH__ -D__BIG_ENDIAN__ -D__APPLE__" +#define TARGET_OS_CPP_BUILTINS() \ + do \ + { \ + builtin_define ("__ppc__"); \ + builtin_define ("__POWERPC__"); \ + builtin_define ("__NATURAL_ALIGNMENT__"); \ + builtin_define ("__MACH__"); \ + builtin_define ("__APPLE__"); \ + } \ + while (0) /* We want -fPIC by default, unless we're using -static to compile for the kernel or some such. */ -#define CC1_SPEC "%{!static:-fPIC}" +#define CC1_SPEC "\ +%{static: %{Zdynamic: %e conflicting code gen style switches are used}}\ +%{!static:-fPIC}" /* Make both r2 and r3 available for allocation. */ #define FIXED_R2 0 @@ -94,20 +105,10 @@ Boston, MA 02111-1307, USA. */ #define RS6000_OUTPUT_BASENAME(FILE, NAME) \ assemble_name (FILE, NAME); -/* Output before instructions. */ -/* This is how to output the definition of a user-level label named NAME, - such as the label on a static function or variable NAME. */ - -#define ASM_OUTPUT_LABEL(FILE,NAME) \ - do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) - -/* This is how to output a command to make the user-level label named NAME - defined for reference from other files. */ - -#undef ASM_GLOBALIZE_LABEL -#define ASM_GLOBALIZE_LABEL(FILE,NAME) \ - do { fputs ("\t.globl ", FILE); \ - RS6000_OUTPUT_BASENAME (FILE, NAME); putc ('\n', FILE);} while (0) +/* Globalizing directive for a label. */ +#undef GLOBAL_ASM_OP +#define GLOBAL_ASM_OP "\t.globl " +#undef TARGET_ASM_GLOBALIZE_LABEL /* This is how to output an internal label prefix. rs6000.c uses this when generating traceback tables. */ @@ -117,14 +118,6 @@ Boston, MA 02111-1307, USA. */ #define ASM_OUTPUT_INTERNAL_LABEL_PREFIX(FILE,PREFIX) \ fprintf (FILE, "%s", PREFIX) -#undef TEXT_SECTION_ASM_OP -#define TEXT_SECTION_ASM_OP ".text" - -/* Output before writable data. */ - -#undef DATA_SECTION_ASM_OP -#define DATA_SECTION_ASM_OP ".data" - /* This says how to output an assembler line to define a global common symbol. */ /* ? */ @@ -134,9 +127,6 @@ Boston, MA 02111-1307, USA. */ RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ fprintf ((FILE), ",%d\n", (SIZE)); } while (0) -#define ASM_OUTPUT_SKIP(FILE,SIZE) \ - fprintf (FILE, "\t.space %d\n", SIZE) - /* Override the standard rs6000 definition. */ #undef ASM_COMMENT_START @@ -148,6 +138,21 @@ Boston, MA 02111-1307, USA. */ #define RESTORE_FP_PREFIX "._restf" #define RESTORE_FP_SUFFIX "" +/* This is how to output an assembler line that says to advance + the location counter to a multiple of 2**LOG bytes using the + "nop" instruction as padding. */ + +#define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \ + do \ + { \ + if ((LOG) < 3) \ + { \ + ASM_OUTPUT_ALIGN (FILE,LOG); \ + } \ + else /* nop == ori r0,r0,0 */ \ + fprintf (FILE, "\t.align32 %d,0x60000000\n", (LOG)); \ + } while (0) + /* Generate insns to call the profiler. */ #define PROFILE_HOOK(LABEL) output_profile_hook (LABEL) @@ -226,7 +231,7 @@ Boston, MA 02111-1307, USA. */ : MAX ((COMPUTED), (SPECIFIED))) /* XXX: Darwin supports neither .quad, or .llong, but it also doesn't - support 64 bit powerpc either, so this just keeps things happy. */ + support 64 bit PowerPC either, so this just keeps things happy. */ #define DOUBLE_INT_ASM_OP "\t.quad\t" /* Get HOST_WIDE_INT and CONST_INT to be 32 bits, for compile time @@ -237,3 +242,6 @@ Boston, MA 02111-1307, USA. */ /* For binary compatibility with 2.95; Darwin C APIs use bool from stdbool.h, which was an int-sized enum in 2.95. */ #define BOOL_TYPE_SIZE INT_TYPE_SIZE + +#undef REGISTER_TARGET_PRAGMAS +#define REGISTER_TARGET_PRAGMAS DARWIN_REGISTER_TARGET_PRAGMAS diff --git a/contrib/gcc/config/rs6000/eabi.asm b/contrib/gcc/config/rs6000/eabi.asm index 0808e9c..058f9b9 100644 --- a/contrib/gcc/config/rs6000/eabi.asm +++ b/contrib/gcc/config/rs6000/eabi.asm @@ -139,7 +139,7 @@ FUNC_START(__eabi) addi 11,11,.LCTOC1@l cmplwi 2,9,0 /* init flag != 0? */ bnelr 2 /* return now, if we've been called already */ - stw 1,.Linit_p@l(10) /* store a non-zero value in the done flag */ + stw 1,.Linit_p@l(10) /* store a nonzero value in the done flag */ #else /* -mrelocatable */ mflr 0 @@ -155,7 +155,7 @@ FUNC_START(__eabi) cmplwi 2,9,0 /* init flag != 0? */ mtlr 0 /* restore in case branch was taken */ bnelr 2 /* return now, if we've been called already */ - stwx 1,10,12 /* store a non-zero value in the done flag */ + stwx 1,10,12 /* store a nonzero value in the done flag */ beq+ 0,.Lsdata /* skip if we don't need to relocate */ /* We need to relocate the .got2 pointers. */ diff --git a/contrib/gcc/config/rs6000/eabi.h b/contrib/gcc/config/rs6000/eabi.h index 88fb6f8..373dd2b 100644 --- a/contrib/gcc/config/rs6000/eabi.h +++ b/contrib/gcc/config/rs6000/eabi.h @@ -31,6 +31,24 @@ Boston, MA 02111-1307, USA. */ #undef TARGET_VERSION #define TARGET_VERSION fprintf (stderr, " (PowerPC Embedded)"); -#undef CPP_PREDEFINES -#define CPP_PREDEFINES \ - "-DPPC -D__embedded__ -Asystem=embedded -Acpu=powerpc -Amachine=powerpc" +#undef TARGET_OS_CPP_BUILTINS +#define TARGET_OS_CPP_BUILTINS() \ + do \ + { \ + builtin_define_std ("PPC"); \ + builtin_define ("__embedded__"); \ + builtin_assert ("system=embedded"); \ + builtin_assert ("cpu=powerpc"); \ + builtin_assert ("machine=powerpc"); \ + } \ + while (0) + +#undef TARGET_SPE_ABI +#undef TARGET_SPE +#undef TARGET_ISEL +#undef TARGET_FPRS + +#define TARGET_SPE_ABI rs6000_spe_abi +#define TARGET_SPE (rs6000_cpu == PROCESSOR_PPC8540) +#define TARGET_ISEL rs6000_isel +#define TARGET_FPRS rs6000_fprs diff --git a/contrib/gcc/config/rs6000/eabiaix.h b/contrib/gcc/config/rs6000/eabiaix.h index 639a335..4e18067 100644 --- a/contrib/gcc/config/rs6000/eabiaix.h +++ b/contrib/gcc/config/rs6000/eabiaix.h @@ -23,9 +23,6 @@ Boston, MA 02111-1307, USA. */ #undef RS6000_ABI_NAME #define RS6000_ABI_NAME "aix" -#undef CPP_SYSV_DEFAULT_SPEC -#define CPP_SYSV_DEFAULT_SPEC "-D_CALL_AIX" - /* Define this macro as a C expression for the initializer of an array of string to tell the driver program which options are defaults for this target and thus do not need to be handled diff --git a/contrib/gcc/config/rs6000/eabisim.h b/contrib/gcc/config/rs6000/eabisim.h index 92e0957..00f710e 100644 --- a/contrib/gcc/config/rs6000/eabisim.h +++ b/contrib/gcc/config/rs6000/eabisim.h @@ -23,9 +23,19 @@ Boston, MA 02111-1307, USA. */ #undef TARGET_VERSION #define TARGET_VERSION fprintf (stderr, " (PowerPC Simulated)"); -#undef CPP_PREDEFINES -#define CPP_PREDEFINES \ - "-DPPC -D__embedded__ -D__simulator__ -Asystem=embedded -Asystem=simulator -Acpu=powerpc -Amachine=powerpc" +#undef TARGET_OS_CPP_BUILTINS +#define TARGET_OS_CPP_BUILTINS() \ + do \ + { \ + builtin_define_std ("PPC"); \ + builtin_define ("__embedded__"); \ + builtin_define ("__simulator__"); \ + builtin_assert ("system=embedded"); \ + builtin_assert ("system=simulator"); \ + builtin_assert ("cpu=powerpc"); \ + builtin_assert ("machine=powerpc"); \ + } \ + while (0) /* Make the simulator the default */ #undef LIB_DEFAULT_SPEC diff --git a/contrib/gcc/config/rs6000/eabispe.h b/contrib/gcc/config/rs6000/eabispe.h new file mode 100644 index 0000000..b0047cd --- /dev/null +++ b/contrib/gcc/config/rs6000/eabispe.h @@ -0,0 +1,51 @@ +/* Core target definitions for GNU compiler + for PowerPC embedded targeted systems with SPE support. + Copyright (C) 2002 Free Software Foundation, Inc. + Contributed by Aldy Hernandez (aldyh@redhat.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#undef TARGET_DEFAULT +#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_EABI) + +#undef TARGET_VERSION +#define TARGET_VERSION fprintf (stderr, " (PowerPC Embedded SPE)"); + +#undef SUBSUBTARGET_OVERRIDE_OPTIONS +#define SUBSUBTARGET_OVERRIDE_OPTIONS \ + rs6000_cpu = PROCESSOR_PPC8540; \ + rs6000_spe_abi = 1; \ + rs6000_fprs = 0; \ + /* See note below. */ \ + /*rs6000_long_double_type_size = 128;*/ \ + rs6000_isel = 1 + +/* + The e500 ABI says that either long doubles are 128 bits, or if + implemented in any other size, the compiler/linker should error out. + We have no emulation libraries for 128 bit long doubles, and I hate + the dozens of failures on the regression suite. So I'm breaking ABI + specifications, until I properly fix the emulation. + + Enable these later. +#undef CPP_LONGDOUBLE_DEFAULT_SPEC +#define CPP_LONGDOUBLE_DEFAULT_SPEC "-D__LONG_DOUBLE_128__=1" +*/ + +#undef ASM_DEFAULT_SPEC +#define ASM_DEFAULT_SPEC "-mppc -mspe -me500" diff --git a/contrib/gcc/config/rs6000/freebsd.h b/contrib/gcc/config/rs6000/freebsd.h index e4b9fc5..699d2ad 100644 --- a/contrib/gcc/config/rs6000/freebsd.h +++ b/contrib/gcc/config/rs6000/freebsd.h @@ -38,6 +38,11 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ #undef LINK_OS_DEFAULT_SPEC #define LINK_OS_DEFAULT_SPEC "%(link_os_freebsd)" +/* XXX: This is wrong for many platforms in sysv4.h. + We should work on getting that defination fixed. */ +#undef LINK_SHLIB_SPEC +#define LINK_SHLIB_SPEC "%{shared:-shared} %{!shared: %{static:-static}}" + /************************[ Target stuff ]***********************************/ @@ -45,12 +50,12 @@ the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ Needs to agree with <machine/ansi.h>. GCC defaults come from c-decl.c, c-common.c, and config/<arch>/<arch>.h. */ +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + /* rs6000.h gets this wrong for FreeBSD. We use the GCC defaults instead. */ #undef WCHAR_TYPE -#undef WCHAR_UNSIGNED -#define WCHAR_UNSIGNED 0 - #undef WCHAR_TYPE_SIZE #define WCHAR_TYPE_SIZE 32 diff --git a/contrib/gcc/config/rs6000/gnu.h b/contrib/gcc/config/rs6000/gnu.h index 32bd906..9aeb696 100644 --- a/contrib/gcc/config/rs6000/gnu.h +++ b/contrib/gcc/config/rs6000/gnu.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, - for powerpc machines running GNU. + for PowerPC machines running GNU. Copyright (C) 2001 Free Software Foundation, Inc. This file is part of GNU CC. diff --git a/contrib/gcc/config/rs6000/linux.h b/contrib/gcc/config/rs6000/linux.h index f5cbd7a..593e961 100644 --- a/contrib/gcc/config/rs6000/linux.h +++ b/contrib/gcc/config/rs6000/linux.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, - for powerpc machines running Linux. - Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003 + for PowerPC machines running Linux. + Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. Contributed by Michael Meissner (meissner@cygnus.com). @@ -21,15 +21,20 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* Don't assume anything about the header files. */ -#define NO_IMPLICIT_EXTERN_C - #undef MD_EXEC_PREFIX #undef MD_STARTFILE_PREFIX -#undef CPP_PREDEFINES -#define CPP_PREDEFINES \ - "-DPPC -D__ELF__ -Dpowerpc -Acpu=powerpc -Amachine=powerpc" +#undef TARGET_OS_CPP_BUILTINS +#define TARGET_OS_CPP_BUILTINS() \ + do \ + { \ + builtin_define_std ("PPC"); \ + builtin_define ("__ELF__"); \ + builtin_define_std ("powerpc"); \ + builtin_assert ("cpu=powerpc"); \ + builtin_assert ("machine=powerpc"); \ + } \ + while (0) #undef CPP_OS_DEFAULT_SPEC #define CPP_OS_DEFAULT_SPEC "%(cpp_os_linux)" @@ -79,7 +84,18 @@ Boston, MA 02111-1307, USA. */ #ifdef IN_LIBGCC2 #include <signal.h> -#include <sys/ucontext.h> + +/* During the 2.5 kernel series the kernel ucontext was changed, but + the new layout is compatible with the old one, so we just define + and use the old one here for simplicity and compatibility. */ + +struct kernel_old_ucontext { + unsigned long uc_flags; + struct ucontext *uc_link; + stack_t uc_stack; + struct sigcontext_struct uc_mcontext; + sigset_t uc_sigmask; +}; enum { SIGNAL_FRAMESIZE = 64 }; #endif @@ -115,7 +131,7 @@ enum { SIGNAL_FRAMESIZE = 64 }; struct siginfo *pinfo; \ void *puc; \ struct siginfo info; \ - struct ucontext uc; \ + struct kernel_old_ucontext uc; \ } *rt_ = (CONTEXT)->cfa; \ sc_ = &rt_->uc.uc_mcontext; \ } \ @@ -139,15 +155,9 @@ enum { SIGNAL_FRAMESIZE = 64 }; (FS)->regs.reg[LINK_REGISTER_REGNUM].loc.offset \ = (long)&(sc_->regs->link) - new_cfa_; \ \ - /* The unwinder expects the IP to point to the following insn, \ - whereas the kernel returns the address of the actual \ - faulting insn. We store NIP+4 in an unused register slot to \ - get the same result for multiple evaluation of the same signal \ - frame. */ \ - sc_->regs->gpr[47] = sc_->regs->nip + 4; \ (FS)->regs.reg[CR0_REGNO].how = REG_SAVED_OFFSET; \ (FS)->regs.reg[CR0_REGNO].loc.offset \ - = (long)&(sc_->regs->gpr[47]) - new_cfa_; \ + = (long)&(sc_->regs->nip) - new_cfa_; \ (FS)->retaddr_column = CR0_REGNO; \ goto SUCCESS; \ } while (0) diff --git a/contrib/gcc/config/rs6000/linux64.h b/contrib/gcc/config/rs6000/linux64.h index ce8f7ac..55065c6 100644 --- a/contrib/gcc/config/rs6000/linux64.h +++ b/contrib/gcc/config/rs6000/linux64.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, - for 64 bit powerpc linux. + for 64 bit PowerPC linux. Copyright (C) 2000, 2001, 2002 Free Software Foundation, Inc. This file is part of GNU CC. @@ -31,8 +31,10 @@ Boston, MA 02111-1307, USA. */ #define TARGET_DEFAULT \ (MASK_POWERPC | MASK_POWERPC64 | MASK_64BIT | MASK_NEW_MNEMONICS) -#undef CPP_DEFAULT_SPEC -#define CPP_DEFAULT_SPEC "-D_ARCH_PPC64" +#undef PROCESSOR_DEFAULT +#define PROCESSOR_DEFAULT PROCESSOR_PPC630 +#undef PROCESSOR_DEFAULT64 +#define PROCESSOR_DEFAULT64 PROCESSOR_PPC630 #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mppc64" @@ -104,18 +106,24 @@ Boston, MA 02111-1307, USA. */ So we have to squirrel it away with this. */ #define SETUP_FRAME_ADDRESSES() rs6000_aix_emit_builtin_unwind_init () -/* Don't assume anything about the header files. */ -#define NO_IMPLICIT_EXTERN_C - +/* Override svr4.h */ #undef MD_EXEC_PREFIX #undef MD_STARTFILE_PREFIX -#undef CPP_PREDEFINES -#define CPP_PREDEFINES \ - "-D_PPC_ -D__PPC__ -D_PPC64_ -D__PPC64__ -D__powerpc__ -D__powerpc64__ \ - -D_PIC_ -D__PIC__ -D_BIG_ENDIAN -D__BIG_ENDIAN__ -D__ELF__ \ - -D__LONG_MAX__=9223372036854775807L \ - -Acpu=powerpc64 -Amachine=powerpc64" +#undef TARGET_OS_CPP_BUILTINS +#define TARGET_OS_CPP_BUILTINS() \ + do \ + { \ + builtin_define ("__PPC__"); \ + builtin_define ("__PPC64__"); \ + builtin_define ("__powerpc__"); \ + builtin_define ("__powerpc64__"); \ + builtin_define ("__PIC__"); \ + builtin_define ("__ELF__"); \ + builtin_assert ("cpu=powerpc64"); \ + builtin_assert ("machine=powerpc64"); \ + } \ + while (0) #undef CPP_OS_DEFAULT_SPEC #define CPP_OS_DEFAULT_SPEC "%(cpp_os_linux)" @@ -145,29 +153,23 @@ Boston, MA 02111-1307, USA. */ #define LINK_OS_DEFAULT_SPEC "%(link_os_linux)" #undef LINK_OS_LINUX_SPEC -#ifndef CROSS_COMPILE -#define LINK_OS_LINUX_SPEC "-m elf64ppc %{!shared: %{!static: \ - %{rdynamic:-export-dynamic} \ - %{!dynamic-linker:-dynamic-linker /lib64/ld.so.1}}}" -#else #define LINK_OS_LINUX_SPEC "-m elf64ppc %{!shared: %{!static: \ %{rdynamic:-export-dynamic} \ - %{!dynamic-linker:-dynamic-linker ld.so.1}}}" + %{!dynamic-linker:-dynamic-linker /lib64/ld64.so.1}}}" + +#ifdef NATIVE_CROSS +#define STARTFILE_PREFIX_SPEC "/usr/local/lib64/ /lib64/ /usr/lib64/" #endif -#ifndef CROSS_COMPILE #undef STARTFILE_LINUX_SPEC #define STARTFILE_LINUX_SPEC "\ -%{!shared: %{pg:/usr/lib64/gcrt1.o%s} %{!pg:%{p:/usr/lib64/gcrt1.o%s} \ - %{!p:/usr/lib64/crt1.o%s}}} /usr/lib64/crti.o%s \ -%{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}" -#endif +%{!shared: %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} %{!p:crt1.o%s}}} crti.o%s \ +%{static:crtbeginT.o%s} \ +%{!static:%{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}}" -#ifndef CROSS_COMPILE #undef ENDFILE_LINUX_SPEC #define ENDFILE_LINUX_SPEC "\ -%{!shared:crtend.o%s} %{shared:crtendS.o%s} /usr/lib64/crtn.o%s" -#endif +%{!shared:crtend.o%s} %{shared:crtendS.o%s} crtn.o%s" #undef TOC_SECTION_ASM_OP #define TOC_SECTION_ASM_OP "\t.section\t\".toc\",\"aw\"" @@ -205,6 +207,18 @@ Boston, MA 02111-1307, USA. */ #undef RS6000_MCOUNT #define RS6000_MCOUNT "_mcount" +#ifdef __powerpc64__ +/* _init and _fini functions are built from bits spread across many + object files, each potentially with a different TOC pointer. For + that reason, place a nop after the call so that the linker can + restore the TOC pointer if a TOC adjusting call stub is needed. */ +#define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ + asm (SECTION_OP "\n" \ +" bl ." #FUNC "\n" \ +" nop\n" \ +" .previous"); +#endif + /* FP save and restore routines. */ #undef SAVE_FP_PREFIX #define SAVE_FP_PREFIX "._savef" @@ -219,17 +233,8 @@ Boston, MA 02111-1307, USA. */ #undef PREFERRED_DEBUGGING_TYPE #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG -/* If we are referencing a function that is static or is known to be - in this file, make the SYMBOL_REF special. We can use this to indicate - that we can branch to this function without emitting a no-op after the - call. Do not set this flag if the function is weakly defined. */ - -#undef ENCODE_SECTION_INFO -#define ENCODE_SECTION_INFO(DECL) \ - if (TREE_CODE (DECL) == FUNCTION_DECL \ - && (TREE_ASM_WRITTEN (DECL) || ! TREE_PUBLIC (DECL)) \ - && ! DECL_WEAK (DECL)) \ - SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; +#undef TARGET_ENCODE_SECTION_INFO +#define TARGET_ENCODE_SECTION_INFO rs6000_xcoff_encode_section_info /* This is how to output a reference to a user-level label named NAME. `assemble_name' uses this. */ @@ -290,7 +295,7 @@ do { \ } \ while (0) -/* Return non-zero if this entry is to be written into the constant +/* Return nonzero if this entry is to be written into the constant pool in a special way. We do so if this is a SYMBOL_REF, LABEL_REF or a CONST containing one of them. If -mfp-in-toc (the default), we also do this for floating-point constants. We actually can only diff --git a/contrib/gcc/config/rs6000/lynx.h b/contrib/gcc/config/rs6000/lynx.h index 5a859ca..7878ef9 100644 --- a/contrib/gcc/config/rs6000/lynx.h +++ b/contrib/gcc/config/rs6000/lynx.h @@ -1,5 +1,5 @@ /* Definitions for Rs6000 running LynxOS. - Copyright (C) 1995, 1996, 2000 Free Software Foundation, Inc. + Copyright (C) 1995, 1996, 2000, 2002 Free Software Foundation, Inc. Contributed by David Henkel-Wallace, Cygnus Support (gumby@cygnus.com) This file is part of GNU CC. @@ -27,9 +27,10 @@ Boston, MA 02111-1307, USA. */ #undef ASM_FILE_START #undef EXTRA_SECTIONS #undef READONLY_DATA_SECTION +#undef READONLY_DATA_SECTION_ASM_OP #undef EXTRA_SECTION_FUNCTIONS -#undef SELECT_RTX_SECTION -#undef SELECT_SECTION +#undef TARGET_ASM_SELECT_RTX_SECTION +#undef TARGET_ASM_SELECT_SECTION #undef USER_LABEL_PREFIX #undef ASM_OUTPUT_LABELREF #undef ASM_OUTPUT_INTERNAL_LABEL @@ -52,8 +53,22 @@ Boston, MA 02111-1307, USA. */ #undef DEFAULT_SIGNED_CHAR #define DEFAULT_SIGNED_CHAR 1 -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "-Acpu=rs6000 -Amachine=rs6000 -Asystem=lynx -Asystem=unix -DLynx -D_IBMR2 -Dunix -Drs6000 -Dlynx -DLYNX" +#undef TARGET_OS_CPP_BUILTINS +#define TARGET_OS_CPP_BUILTINS() \ + do \ + { \ + builtin_assert ("cpu=rs6000"); \ + builtin_assert ("machine=rs6000"); \ + builtin_assert ("system=lynx"); \ + builtin_assert ("system=unix"); \ + builtin_define_std ("Lynx"); \ + builtin_define ("_IBMR2"); \ + builtin_define_std ("unix"); \ + builtin_define_std ("rs6000"); \ + builtin_define_std ("lynx"); \ + builtin_define_std ("LYNX"); \ + } \ + while (0) #undef LINK_SPEC #define LINK_SPEC "-T0x10001000 -H0x1000 -D0x20000000 -btextro -bhalt:4 -bnodelcsect -bnso -bro -bnoglink %{v} %{b*}" diff --git a/contrib/gcc/config/rs6000/mach.h b/contrib/gcc/config/rs6000/mach.h index d4395d5..a246f91 100644 --- a/contrib/gcc/config/rs6000/mach.h +++ b/contrib/gcc/config/rs6000/mach.h @@ -26,8 +26,19 @@ Boston, MA 02111-1307, USA. */ #define TARGET_VERSION fprintf (stderr, " (Mach-RS/6000)"); /* We don't define AIX under MACH; instead we define `unix'. */ -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "-Drios -D_IBMR2 -Dunix -Asystem=unix -Asystem=mach -Acpu=rs6000 -Amachine=rs6000" +#undef TARGET_OS_CPP_BUILTINS +#define TARGET_OS_CPP_BUILTINS() \ + do \ + { \ + builtin_define_std ("rios"); \ + builtin_define ("_IBMR2"); \ + builtin_define_std ("unix"); \ + builtin_assert ("system=unix"); \ + builtin_assert ("system=mach"); \ + builtin_assert ("cpu=rs6000"); \ + builtin_assert ("machine=rs6000"); \ + } \ + while (0) /* Define different binder options for MACH. */ #undef LINK_SPEC diff --git a/contrib/gcc/config/rs6000/netbsd.h b/contrib/gcc/config/rs6000/netbsd.h index d41e576..b473a8a 100644 --- a/contrib/gcc/config/rs6000/netbsd.h +++ b/contrib/gcc/config/rs6000/netbsd.h @@ -1,6 +1,7 @@ /* Definitions of target machine for GNU compiler, for PowerPC NetBSD systems. - Copyright 2001 Free Software Foundation, Inc. + Copyright 2002 Free Software Foundation, Inc. + Contributed by Wasabi Systems, Inc. This file is part of GNU CC. @@ -19,48 +20,74 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* Under NetBSD, the normal location of the various *crt*.o files is - the /usr/lib directory [from config/netbsd.h]. */ +#undef TARGET_OS_CPP_BUILTINS /* FIXME: sysv4.h should not define this! */ +#define TARGET_OS_CPP_BUILTINS() \ + do \ + { \ + NETBSD_OS_CPP_BUILTINS_ELF(); \ + builtin_define ("__powerpc__"); \ + builtin_assert ("cpu=powerpc"); \ + builtin_assert ("machine=powerpc"); \ + } \ + while (0) + +/* Override the default from rs6000.h to avoid conflicts with macros + defined in NetBSD header files. */ + +#undef RS6000_CPU_CPP_ENDIAN_BUILTINS +#define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ + do \ + { \ + if (BYTES_BIG_ENDIAN) \ + { \ + builtin_define ("__BIG_ENDIAN__"); \ + builtin_assert ("machine=bigendian"); \ + } \ + else \ + { \ + builtin_define ("__LITTLE_ENDIAN__"); \ + builtin_assert ("machine=littleendian"); \ + } \ + } \ + while (0) + +/* Make GCC agree with <machine/ansi.h>. */ + +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "int" + +/* Undo the spec mess from sysv4.h, and just define the specs + the way NetBSD systems actually expect. */ + +#undef CPP_SPEC +#define CPP_SPEC NETBSD_CPP_SPEC + +#undef LINK_SPEC +#define LINK_SPEC \ + "%{!msdata=none:%{G*}} %{msdata=none:-G0} \ + %(netbsd_link_spec)" + +#define NETBSD_ENTRY_POINT "_start" + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC NETBSD_STARTFILE_SPEC + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC \ + "crtsavres%O%s %(netbsd_endfile_spec)" + +#undef LIB_SPEC +#define LIB_SPEC NETBSD_LIB_SPEC + +#undef SUBTARGET_EXTRA_SPECS +#define SUBTARGET_EXTRA_SPECS \ + { "netbsd_link_spec", NETBSD_LINK_SPEC_ELF }, \ + { "netbsd_entry_point", NETBSD_ENTRY_POINT }, \ + { "netbsd_endfile_spec", NETBSD_ENDFILE_SPEC }, -#undef STANDARD_STARTFILE_PREFIX -#define STANDARD_STARTFILE_PREFIX "/usr/lib/" - -/* FIXME: Should this macro be treated the same as for the other - spec's? */ -/* NOTE: -dc and -dp are equivalent yet NetBSD's CC passes both both! - NetBSD's CC also passes -O1 but we can skip that. NetBSD explictly - sets ``-e _start'', since LD knows this, skip it. */ - -#undef LINK_SHLIB_SPEC -#define LINK_SHLIB_SPEC "\ -%{shared:-shared} \ -%{!shared: %{static:-dc -dp -static}} \ -%{!shared: %{!static:-dc -dp}} \ -" - -/* Override the defaults. */ -#undef LIB_DEFAULT_SPEC -#define LIB_DEFAULT_SPEC "%(lib_netbsd)" - -#undef STARTFILE_DEFAULT_SPEC -#define STARTFILE_DEFAULT_SPEC "%(startfile_netbsd)" - -#undef ENDFILE_DEFAULT_SPEC -#define ENDFILE_DEFAULT_SPEC "%(endfile_netbsd)" - -#undef LINK_START_DEFAULT_SPEC -#define LINK_START_DEFAULT_SPEC "%(link_start_netbsd)" - -#undef LINK_OS_DEFAULT_SPEC -#define LINK_OS_DEFAULT_SPEC "%(link_os_netbsd)" - -#undef CPP_OS_DEFAULT_SPEC -#define CPP_OS_DEFAULT_SPEC "%(cpp_os_netbsd)" #undef TARGET_VERSION -#define TARGET_VERSION fprintf (stderr, " (PowerPC NetBSD/ELF)"); - -/* Use STABS debugging information by default. DWARF2 makes a mess of - the 1.5.2 linker. */ -#undef PREFERRED_DEBUGGING_TYPE -#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG +#define TARGET_VERSION fprintf (stderr, " (NetBSD/powerpc ELF)"); diff --git a/contrib/gcc/config/rs6000/ppc-asm.h b/contrib/gcc/config/rs6000/ppc-asm.h index 27f3635..2822e18 100644 --- a/contrib/gcc/config/rs6000/ppc-asm.h +++ b/contrib/gcc/config/rs6000/ppc-asm.h @@ -2,7 +2,6 @@ /* Under winnt, 1) gas supports the following as names and 2) in particular defining "toc" breaks the FUNC_START macro as ".toc" becomes ".2" */ -#if !defined(__WINNT__) #define r0 0 #define sp 1 #define toc 2 @@ -77,7 +76,6 @@ #define f29 29 #define f30 30 #define f31 31 -#endif /* * Macros to glue together two tokens. @@ -122,43 +120,6 @@ GLUE(.,name): GLUE(.L,name): \ .size GLUE(.,name),GLUE(.L,name)-GLUE(.,name) -#elif defined(__WINNT__) -#define FUNC_NAME(name) GLUE(..,name) -#define JUMP_TARGET(name) FUNC_NAME(name) -#define FUNC_START(name) \ - .pdata; \ - .align 2; \ - .ualong GLUE(..,name),GLUE(name,.e),0,0,GLUE(..,name); \ - .reldata; \ -name: \ - .ualong GLUE(..,name),.toc; \ - .section .text; \ - .globl name; \ - .globl GLUE(..,name); \ -GLUE(..,name): - -#define FUNC_END(name) \ -GLUE(name,.e): ; \ -GLUE(FE_MOT_RESVD..,name): - -#elif defined(_CALL_NT) -#define FUNC_NAME(name) GLUE(..,name) -#define JUMP_TARGET(name) FUNC_NAME(name) -#define FUNC_START(name) \ - .section DESC_SECTION,"aw"; \ -name: \ - .long GLUE(..,name); \ - .long _GLOBAL_OFFSET_TABLE_; \ - .previous; \ - .type GLUE(..,name),@function; \ - .globl name; \ - .globl GLUE(..,name); \ -GLUE(..,name): - -#define FUNC_END(name) \ -GLUE(.L,name): \ - .size GLUE(..,name),GLUE(.L,name)-GLUE(..,name) - #elif defined (__powerpc64__) #define FUNC_NAME(name) GLUE(.,name) #define JUMP_TARGET(name) FUNC_NAME(name) diff --git a/contrib/gcc/config/rs6000/ppc64-fp.c b/contrib/gcc/config/rs6000/ppc64-fp.c new file mode 100644 index 0000000..3f6d7cd --- /dev/null +++ b/contrib/gcc/config/rs6000/ppc64-fp.c @@ -0,0 +1,146 @@ +/* Functions needed for soft-float on powerpc64-linux, copied from + libgcc2.c with macros expanded to force the use of specific types. + + Copyright (C) 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, + 2000, 2001, 2002, 2003 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify it under +the terms of the GNU General Public License as published by the Free +Software Foundation; either version 2, or (at your option) any later +version. + +In addition to the permissions in the GNU General Public License, the +Free Software Foundation gives you unlimited permission to link the +compiled version of this file into combinations with other programs, +and to distribute those combinations without any restriction coming +from the use of this file. (The General Public License restrictions +do apply in other respects; for example, they cover modification of +the file, and distribution when not linked into a combine +executable.) + +GCC is distributed in the hope that it will be useful, but WITHOUT ANY +WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA +02111-1307, USA. */ + +#if defined(__powerpc64__) +#include "fp-bit.h" + +extern DItype __fixdfdi (DFtype); +extern DItype __fixsfdi (SFtype); +extern USItype __fixunsdfsi (DFtype); +extern USItype __fixunssfsi (SFtype); +extern DFtype __floatdidf (DItype); +extern SFtype __floatdisf (DItype); + +static DItype local_fixunssfdi (SFtype); +static DItype local_fixunsdfdi (DFtype); + +DItype +__fixdfdi (DFtype a) +{ + if (a < 0) + return - local_fixunsdfdi (-a); + return local_fixunsdfdi (a); +} + +DItype +__fixsfdi (SFtype a) +{ + if (a < 0) + return - local_fixunssfdi (-a); + return local_fixunssfdi (a); +} + +USItype +__fixunsdfsi (DFtype a) +{ + if (a >= - (DFtype) (- ((SItype)(((USItype)1 << ((4 * 8) - 1)) - 1)) - 1)) + return (SItype) (a + (- ((SItype)(((USItype)1 << ((4 * 8) - 1)) - 1)) - 1)) + - (- ((SItype)(((USItype)1 << ((4 * 8) - 1)) - 1)) - 1); + return (SItype) a; +} + +USItype +__fixunssfsi (SFtype a) +{ + if (a >= - (SFtype) (- ((SItype)(((USItype)1 << ((4 * 8) - 1)) - 1)) - 1)) + return (SItype) (a + (- ((SItype)(((USItype)1 << ((4 * 8) - 1)) - 1)) - 1)) + - (- ((SItype)(((USItype)1 << ((4 * 8) - 1)) - 1)) - 1); + return (SItype) a; +} + +DFtype +__floatdidf (DItype u) +{ + DFtype d; + + d = (SItype) (u >> (sizeof (SItype) * 8)); + d *= (((UDItype) 1) << ((sizeof (SItype) * 8) / 2)); + d *= (((UDItype) 1) << ((sizeof (SItype) * 8) / 2)); + d += (USItype) (u & ((((UDItype) 1) << (sizeof (SItype) * 8)) - 1)); + + return d; +} + +SFtype +__floatdisf (DItype u) +{ + DFtype f; + + if (53 < (sizeof (DItype) * 8) + && 53 > ((sizeof (DItype) * 8) - 53 + 24)) + { + if (! (- ((DItype) 1 << 53) < u + && u < ((DItype) 1 << 53))) + { + if ((UDItype) u & (((UDItype) 1 << ((sizeof (DItype) * 8) - 53)) - 1)) + { + u &= ~ (((UDItype) 1 << ((sizeof (DItype) * 8) - 53)) - 1); + u |= ((UDItype) 1 << ((sizeof (DItype) * 8) - 53)); + } + } + } + f = (SItype) (u >> (sizeof (SItype) * 8)); + f *= (((UDItype) 1) << ((sizeof (SItype) * 8) / 2)); + f *= (((UDItype) 1) << ((sizeof (SItype) * 8) / 2)); + f += (USItype) (u & ((((UDItype) 1) << (sizeof (SItype) * 8)) - 1)); + + return (SFtype) f; +} + +/* This version is needed to prevent recursion; fixunsdfdi in libgcc + calls fixdfdi, which in turn calls calls fixunsdfdi. */ + +static DItype +local_fixunsdfdi (DFtype a) +{ + USItype hi, lo; + + hi = a / (((UDItype) 1) << (sizeof (SItype) * 8)); + lo = (a - ((DFtype) hi) * (((UDItype) 1) << (sizeof (SItype) * 8))); + return ((UDItype) hi << (sizeof (SItype) * 8)) | lo; +} + +/* This version is needed to prevent recursion; fixunssfdi in libgcc + calls fixsfdi, which in turn calls calls fixunssfdi. */ + +static DItype +local_fixunssfdi (SFtype original_a) +{ + DFtype a = original_a; + USItype hi, lo; + + hi = a / (((UDItype) 1) << (sizeof (SItype) * 8)); + lo = (a - ((DFtype) hi) * (((UDItype) 1) << (sizeof (SItype) * 8))); + return ((UDItype) hi << (sizeof (SItype) * 8)) | lo; +} + +#endif /* __powerpc64__ */ diff --git a/contrib/gcc/config/rs6000/rs6000-c.c b/contrib/gcc/config/rs6000/rs6000-c.c new file mode 100644 index 0000000..03f91ba --- /dev/null +++ b/contrib/gcc/config/rs6000/rs6000-c.c @@ -0,0 +1,128 @@ +/* Subroutines for the C front end on the POWER and PowerPC architectures. + Copyright (C) 2002 + Free Software Foundation, Inc. + + Contributed by Zack Weinberg <zack@codesourcery.com> + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "config.h" +#include "system.h" +#include "cpplib.h" +#include "tree.h" +#include "c-pragma.h" +#include "errors.h" +#include "tm_p.h" + +/* Handle the machine specific pragma longcall. Its syntax is + + # pragma longcall ( TOGGLE ) + + where TOGGLE is either 0 or 1. + + rs6000_default_long_calls is set to the value of TOGGLE, changing + whether or not new function declarations receive a longcall + attribute by default. */ + +#define SYNTAX_ERROR(msgid) do { \ + warning (msgid); \ + warning ("ignoring malformed #pragma longcall"); \ + return; \ +} while (0) + +void +rs6000_pragma_longcall (pfile) + cpp_reader *pfile ATTRIBUTE_UNUSED; +{ + tree x, n; + + /* If we get here, generic code has already scanned the directive + leader and the word "longcall". */ + + if (c_lex (&x) != CPP_OPEN_PAREN) + SYNTAX_ERROR ("missing open paren"); + if (c_lex (&n) != CPP_NUMBER) + SYNTAX_ERROR ("missing number"); + if (c_lex (&x) != CPP_CLOSE_PAREN) + SYNTAX_ERROR ("missing close paren"); + + if (n != integer_zero_node && n != integer_one_node) + SYNTAX_ERROR ("number must be 0 or 1"); + + if (c_lex (&x) != CPP_EOF) + warning ("junk at end of #pragma longcall"); + + rs6000_default_long_calls = (n == integer_one_node); +} + +/* Handle defining many CPP flags based on TARGET_xxx. As a general + policy, rather than trying to guess what flags a user might want a + #define for, it's better to define a flag for everything. */ + +#define builtin_define(TXT) cpp_define (pfile, TXT) +#define builtin_assert(TXT) cpp_assert (pfile, TXT) + +void +rs6000_cpu_cpp_builtins (pfile) + cpp_reader *pfile; +{ + if (TARGET_POWER2) + builtin_define ("_ARCH_PWR2"); + else if (TARGET_POWER) + builtin_define ("_ARCH_PWR"); + if (TARGET_POWERPC) + builtin_define ("_ARCH_PPC"); + if (TARGET_POWERPC64) + builtin_define ("_ARCH_PPC64"); + if (! TARGET_POWER && ! TARGET_POWER2 && ! TARGET_POWERPC) + builtin_define ("_ARCH_COM"); + if (TARGET_ALTIVEC) + builtin_define ("__ALTIVEC__"); + if (TARGET_SPE) + builtin_define ("__SPE__"); + if (TARGET_SOFT_FLOAT) + builtin_define ("_SOFT_FLOAT"); + /* Used by lwarx/stwcx. errata work-around. */ + if (rs6000_cpu == PROCESSOR_PPC405) + builtin_define ("__PPC405__"); + + /* May be overridden by target configuration. */ + RS6000_CPU_CPP_ENDIAN_BUILTINS(); + + if (TARGET_LONG_DOUBLE_128) + builtin_define ("__LONG_DOUBLE_128__"); + + switch (rs6000_current_abi) + { + case ABI_V4: + builtin_define ("_CALL_SYSV"); + break; + case ABI_AIX_NODESC: + builtin_define ("_CALL_AIX"); + break; + case ABI_AIX: + builtin_define ("_CALL_AIXDESC"); + builtin_define ("_CALL_AIX"); + break; + case ABI_DARWIN: + builtin_define ("_CALL_DARWIN"); + break; + default: + break; + } +} diff --git a/contrib/gcc/config/rs6000/rs6000-modes.def b/contrib/gcc/config/rs6000/rs6000-modes.def new file mode 100644 index 0000000..ac4112c --- /dev/null +++ b/contrib/gcc/config/rs6000/rs6000-modes.def @@ -0,0 +1,31 @@ +/* Definitions of target machine for GNU compiler, for IBM RS/6000. + Copyright (C) 2002 Free Software Foundation, Inc. + Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Add any extra modes needed to represent the condition code. + + For the RS/6000, we need separate modes when unsigned (logical) comparisons + are being done and we need a separate mode for floating-point. We also + use a mode for the case when we are comparing the results of two + comparisons, as then only the EQ bit is valid in the register. */ + +CC (CCUNS) +CC (CCFP) +CC (CCEQ) diff --git a/contrib/gcc/config/rs6000/rs6000-protos.h b/contrib/gcc/config/rs6000/rs6000-protos.h index f6024ec..4d6daa5 100644 --- a/contrib/gcc/config/rs6000/rs6000-protos.h +++ b/contrib/gcc/config/rs6000/rs6000-protos.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000. - Copyright (C) 2000, 2001 Free Software Foundation, Inc. + Copyright (C) 2000, 2001, 2002 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GNU CC. @@ -19,13 +19,16 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#ifndef GCC_RS6000_PROTOS_H +#define GCC_RS6000_PROTOS_H + /* Declare functions in rs6000.c */ #ifdef RTX_CODE #ifdef TREE_CODE -extern void init_cumulative_args PARAMS ((CUMULATIVE_ARGS *, tree, rtx, int)); -extern void rs6000_va_start PARAMS ((int, tree, rtx)); +extern void init_cumulative_args PARAMS ((CUMULATIVE_ARGS *, tree, rtx, int, int)); +extern void rs6000_va_start PARAMS ((tree, rtx)); #endif /* TREE_CODE */ extern struct rtx_def *rs6000_got_register PARAMS ((rtx)); @@ -61,8 +64,12 @@ extern int non_add_cint_operand PARAMS ((rtx, enum machine_mode)); extern int non_logical_cint_operand PARAMS ((rtx, enum machine_mode)); extern int logical_operand PARAMS ((rtx, enum machine_mode)); extern int mask_operand PARAMS ((rtx, enum machine_mode)); +extern int mask_operand_wrap PARAMS ((rtx, enum machine_mode)); extern int mask64_operand PARAMS ((rtx, enum machine_mode)); +extern int mask64_2_operand PARAMS ((rtx, enum machine_mode)); +extern void build_mask64_2_operands PARAMS ((rtx, rtx *)); extern int and64_operand PARAMS ((rtx, enum machine_mode)); +extern int and64_2_operand PARAMS ((rtx, enum machine_mode)); extern int and_operand PARAMS ((rtx, enum machine_mode)); extern int count_register_operand PARAMS ((rtx, enum machine_mode)); extern int xer_operand PARAMS ((rtx, enum machine_mode)); @@ -96,6 +103,8 @@ extern int addrs_ok_for_quad_peep PARAMS ((rtx, rtx)); extern enum reg_class secondary_reload_class PARAMS ((enum reg_class, enum machine_mode, rtx)); extern int ccr_bit PARAMS ((rtx, int)); +extern int extract_MB PARAMS ((rtx)); +extern int extract_ME PARAMS ((rtx)); extern void print_operand PARAMS ((FILE *, rtx, int)); extern void print_operand_address PARAMS ((FILE *, rtx)); extern enum rtx_code rs6000_reverse_condition PARAMS ((enum machine_mode, @@ -120,8 +129,6 @@ extern rtx rs6000_legitimize_address PARAMS ((rtx, rtx, enum machine_mode)); extern rtx rs6000_legitimize_reload_address PARAMS ((rtx, enum machine_mode, int, int, int, int *)); extern int rs6000_legitimate_address PARAMS ((enum machine_mode, rtx, int)); -extern void rs6000_select_rtx_section PARAMS ((enum machine_mode, rtx)); - extern rtx rs6000_return_addr PARAMS ((int, rtx)); extern void rs6000_output_symbol_ref PARAMS ((FILE*, rtx)); @@ -144,10 +151,7 @@ extern void setup_incoming_varargs PARAMS ((CUMULATIVE_ARGS *, enum machine_mode, tree, int *, int)); extern struct rtx_def *rs6000_va_arg PARAMS ((tree, tree)); -extern void output_mi_thunk PARAMS ((FILE *, tree, int, tree)); -extern void rs6000_encode_section_info PARAMS ((tree)); -extern void rs6000_select_section PARAMS ((tree, int)); -extern void rs6000_unique_section PARAMS ((tree, int)); +extern int function_ok_for_sibcall PARAMS ((tree)); #ifdef ARGS_SIZE_RTX /* expr.h defines ARGS_SIZE_RTX and `enum direction' */ extern enum direction function_arg_padding PARAMS ((enum machine_mode, tree)); @@ -158,8 +162,6 @@ extern enum direction function_arg_padding PARAMS ((enum machine_mode, tree)); extern void optimization_options PARAMS ((int, int)); extern void rs6000_override_options PARAMS ((const char *)); extern void rs6000_file_start PARAMS ((FILE *, const char *)); -extern struct rtx_def *rs6000_float_const PARAMS ((const char *, - enum machine_mode)); extern int direct_return PARAMS ((void)); extern union tree_node *rs6000_build_va_list PARAMS ((void)); extern int first_reg_to_save PARAMS ((void)); @@ -185,5 +187,18 @@ extern void rs6000_emit_load_toc_table PARAMS ((int)); extern void rs6000_aix_emit_builtin_unwind_init PARAMS ((void)); extern void rs6000_emit_epilogue PARAMS ((int)); extern void debug_stack_info PARAMS ((rs6000_stack_t *)); +extern const char * output_isel PARAMS ((rtx *)); +extern int vrsave_operation PARAMS ((rtx, enum machine_mode)); +extern int rs6000_register_move_cost PARAMS ((enum machine_mode, + enum reg_class, enum reg_class)); +extern int rs6000_memory_move_cost PARAMS ((enum machine_mode, + enum reg_class, int)); + +/* Declare functions in rs6000-c.c */ + +#ifdef GCC_CPPLIB_H +extern void rs6000_pragma_longcall PARAMS ((cpp_reader *)); +extern void rs6000_cpu_cpp_builtins PARAMS ((cpp_reader *)); +#endif -extern void machopic_output_stub PARAMS ((FILE *, const char *, const char *)); +#endif /* rs6000-protos.h */ diff --git a/contrib/gcc/config/rs6000/rs6000.c b/contrib/gcc/config/rs6000/rs6000.c index 89808cc..591f77d 100644 --- a/contrib/gcc/config/rs6000/rs6000.c +++ b/contrib/gcc/config/rs6000/rs6000.c @@ -74,7 +74,25 @@ int rs6000_long_double_type_size; /* Whether -mabi=altivec has appeared */ int rs6000_altivec_abi; -/* Set to non-zero once AIX common-mode calls have been defined. */ +/* Whether VRSAVE instructions should be generated. */ +int rs6000_altivec_vrsave; + +/* String from -mvrsave= option. */ +const char *rs6000_altivec_vrsave_string; + +/* Nonzero if we want SPE ABI extensions. */ +int rs6000_spe_abi; + +/* Whether isel instructions should be generated. */ +int rs6000_isel; + +/* Nonzero if we have FPRs. */ +int rs6000_fprs = 1; + +/* String from -misel=. */ +const char *rs6000_isel_string; + +/* Set to nonzero once AIX common-mode calls have been defined. */ static int common_mode_defined; /* Private copy of original value of flag_pic for ABI_AIX. */ @@ -114,6 +132,14 @@ const char *rs6000_debug_name; int rs6000_debug_stack; /* debug stack applications */ int rs6000_debug_arg; /* debug argument handling */ +const char *rs6000_traceback_name; +static enum { + traceback_default = 0, + traceback_none, + traceback_part, + traceback_full +} rs6000_traceback; + /* Flag to say the TOC is initialized */ int toc_initialized; char toc_label_name[10]; @@ -121,6 +147,24 @@ char toc_label_name[10]; /* Alias set for saves and restores from the rs6000 stack. */ static int rs6000_sr_alias_set; +/* Call distance, overridden by -mlongcall and #pragma longcall(1). + The only place that looks at this is rs6000_set_default_type_attributes; + everywhere else should rely on the presence or absence of a longcall + attribute on the function declaration. */ +int rs6000_default_long_calls; +const char *rs6000_longcall_switch; + +struct builtin_description +{ + /* mask is not const because we're going to alter it below. This + nonsense will go away when we rewrite the -march infrastructure + to give us more target flag bits. */ + unsigned int mask; + const enum insn_code icode; + const char *const name; + const enum rs6000_builtins code; +}; + static void rs6000_add_gc_roots PARAMS ((void)); static int num_insns_constant_wide PARAMS ((HOST_WIDE_INT)); static void validate_condition_mode @@ -129,6 +173,9 @@ static rtx rs6000_generate_compare PARAMS ((enum rtx_code)); static void rs6000_maybe_dead PARAMS ((rtx)); static void rs6000_emit_stack_tie PARAMS ((void)); static void rs6000_frame_related PARAMS ((rtx, rtx, HOST_WIDE_INT, rtx, rtx)); +static void emit_frame_save PARAMS ((rtx, rtx, enum machine_mode, + unsigned int, int, int)); +static rtx gen_frame_mem_offset PARAMS ((enum machine_mode, rtx, int)); static void rs6000_emit_allocate_stack PARAMS ((HOST_WIDE_INT, int)); static unsigned rs6000_hash_constant PARAMS ((rtx)); static unsigned toc_hash_function PARAMS ((const void *)); @@ -136,14 +183,19 @@ static int toc_hash_eq PARAMS ((const void *, const void *)); static int toc_hash_mark_entry PARAMS ((void **, void *)); static void toc_hash_mark_table PARAMS ((void *)); static int constant_pool_expr_1 PARAMS ((rtx, int *, int *)); -static void rs6000_free_machine_status PARAMS ((struct function *)); -static void rs6000_init_machine_status PARAMS ((struct function *)); +static struct machine_function * rs6000_init_machine_status PARAMS ((void)); static bool rs6000_assemble_integer PARAMS ((rtx, unsigned int, int)); +#ifdef HAVE_GAS_HIDDEN +static void rs6000_assemble_visibility PARAMS ((tree, int)); +#endif static int rs6000_ra_ever_killed PARAMS ((void)); static tree rs6000_handle_longcall_attribute PARAMS ((tree *, tree, tree, int, bool *)); const struct attribute_spec rs6000_attribute_table[]; +static void rs6000_set_default_type_attributes PARAMS ((tree)); static void rs6000_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT)); static void rs6000_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT)); +static void rs6000_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT, + HOST_WIDE_INT, tree)); static rtx rs6000_emit_set_long_const PARAMS ((rtx, HOST_WIDE_INT, HOST_WIDE_INT)); #if TARGET_ELF @@ -151,30 +203,64 @@ static unsigned int rs6000_elf_section_type_flags PARAMS ((tree, const char *, int)); static void rs6000_elf_asm_out_constructor PARAMS ((rtx, int)); static void rs6000_elf_asm_out_destructor PARAMS ((rtx, int)); +static void rs6000_elf_select_section PARAMS ((tree, int, + unsigned HOST_WIDE_INT)); +static void rs6000_elf_unique_section PARAMS ((tree, int)); +static void rs6000_elf_select_rtx_section PARAMS ((enum machine_mode, rtx, + unsigned HOST_WIDE_INT)); +static void rs6000_elf_encode_section_info PARAMS ((tree, int)) + ATTRIBUTE_UNUSED; +static const char *rs6000_elf_strip_name_encoding PARAMS ((const char *)); +static bool rs6000_elf_in_small_data_p PARAMS ((tree)); #endif -#ifdef OBJECT_FORMAT_COFF -static void xcoff_asm_named_section PARAMS ((const char *, unsigned int)); +#if TARGET_XCOFF +static void rs6000_xcoff_asm_globalize_label PARAMS ((FILE *, const char *)); +static void rs6000_xcoff_asm_named_section PARAMS ((const char *, unsigned int)); +static void rs6000_xcoff_select_section PARAMS ((tree, int, + unsigned HOST_WIDE_INT)); +static void rs6000_xcoff_unique_section PARAMS ((tree, int)); +static void rs6000_xcoff_select_rtx_section PARAMS ((enum machine_mode, rtx, + unsigned HOST_WIDE_INT)); +static const char * rs6000_xcoff_strip_name_encoding PARAMS ((const char *)); +static unsigned int rs6000_xcoff_section_type_flags PARAMS ((tree, const char *, int)); #endif +static void rs6000_xcoff_encode_section_info PARAMS ((tree, int)) + ATTRIBUTE_UNUSED; static bool rs6000_binds_local_p PARAMS ((tree)); static int rs6000_adjust_cost PARAMS ((rtx, rtx, rtx, int)); static int rs6000_adjust_priority PARAMS ((rtx, int)); static int rs6000_issue_rate PARAMS ((void)); static void rs6000_init_builtins PARAMS ((void)); -static void altivec_init_builtins PARAMS ((void)); +static rtx rs6000_expand_unop_builtin PARAMS ((enum insn_code, tree, rtx)); +static rtx rs6000_expand_binop_builtin PARAMS ((enum insn_code, tree, rtx)); +static rtx rs6000_expand_ternop_builtin PARAMS ((enum insn_code, tree, rtx)); static rtx rs6000_expand_builtin PARAMS ((tree, rtx, rtx, enum machine_mode, int)); -static rtx altivec_expand_builtin PARAMS ((tree, rtx)); -static rtx altivec_expand_unop_builtin PARAMS ((enum insn_code, tree, rtx)); -static rtx altivec_expand_binop_builtin PARAMS ((enum insn_code, tree, rtx)); +static void altivec_init_builtins PARAMS ((void)); +static void rs6000_common_init_builtins PARAMS ((void)); + +static void enable_mask_for_builtins PARAMS ((struct builtin_description *, + int, enum rs6000_builtins, + enum rs6000_builtins)); +static void spe_init_builtins PARAMS ((void)); +static rtx spe_expand_builtin PARAMS ((tree, rtx, bool *)); +static rtx spe_expand_predicate_builtin PARAMS ((enum insn_code, tree, rtx)); +static rtx spe_expand_evsel_builtin PARAMS ((enum insn_code, tree, rtx)); +static int rs6000_emit_int_cmove PARAMS ((rtx, rtx, rtx, rtx)); + +static rtx altivec_expand_builtin PARAMS ((tree, rtx, bool *)); +static rtx altivec_expand_ld_builtin PARAMS ((tree, rtx, bool *)); +static rtx altivec_expand_st_builtin PARAMS ((tree, rtx, bool *)); +static rtx altivec_expand_dst_builtin PARAMS ((tree, rtx, bool *)); static rtx altivec_expand_abs_builtin PARAMS ((enum insn_code, tree, rtx)); static rtx altivec_expand_predicate_builtin PARAMS ((enum insn_code, const char *, tree, rtx)); -static rtx altivec_expand_ternop_builtin PARAMS ((enum insn_code, tree, rtx)); static rtx altivec_expand_stv_builtin PARAMS ((enum insn_code, tree)); static void rs6000_parse_abi_options PARAMS ((void)); +static void rs6000_parse_vrsave_option PARAMS ((void)); +static void rs6000_parse_isel_option PARAMS ((void)); static int first_altivec_reg_to_save PARAMS ((void)); static unsigned int compute_vrsave_mask PARAMS ((void)); static void is_altivec_return_reg PARAMS ((rtx, void *)); -int vrsave_operation PARAMS ((rtx, enum machine_mode)); static rtx generate_set_vrsave PARAMS ((rtx, rs6000_stack_t *, int)); static void altivec_frame_fixup PARAMS ((rtx, rtx, HOST_WIDE_INT)); static int easy_vector_constant PARAMS ((rtx)); @@ -198,7 +284,9 @@ char rs6000_reg_names[][8] = "8", "9", "10", "11", "12", "13", "14", "15", "16", "17", "18", "19", "20", "21", "22", "23", "24", "25", "26", "27", "28", "29", "30", "31", - "vrsave" + "vrsave", "vscr", + /* SPE registers. */ + "spe_acc", "spefscr" }; #ifdef TARGET_REGNAMES @@ -215,22 +303,29 @@ static const char alt_reg_names[][8] = "mq", "lr", "ctr", "ap", "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", "xer", - /* AltiVec registers. */ + /* AltiVec registers. */ "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7", - "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", - "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", - "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", - "vrsave" + "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15", + "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23", + "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31", + "vrsave", "vscr", + /* SPE registers. */ + "spe_acc", "spefscr" }; #endif #ifndef MASK_STRICT_ALIGN #define MASK_STRICT_ALIGN 0 #endif + +/* The VRSAVE bitmask puts bit %v0 as the most significant bit. */ +#define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO)) /* Initialize the GCC target structure. */ #undef TARGET_ATTRIBUTE_TABLE #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table +#undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES +#define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes #undef TARGET_ASM_ALIGNED_DI_OP #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP @@ -238,7 +333,7 @@ static const char alt_reg_names[][8] = /* Default unaligned ops are only provided for ELF. Find the ops needed for non-ELF systems. */ #ifndef OBJECT_FORMAT_ELF -#ifdef OBJECT_FORMAT_COFF +#if TARGET_XCOFF /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on 64-bit targets. */ #undef TARGET_ASM_UNALIGNED_HI_OP @@ -261,16 +356,16 @@ static const char alt_reg_names[][8] = #undef TARGET_ASM_INTEGER #define TARGET_ASM_INTEGER rs6000_assemble_integer +#ifdef HAVE_GAS_HIDDEN +#undef TARGET_ASM_ASSEMBLE_VISIBILITY +#define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility +#endif + #undef TARGET_ASM_FUNCTION_PROLOGUE #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue #undef TARGET_ASM_FUNCTION_EPILOGUE #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue -#if TARGET_ELF -#undef TARGET_SECTION_TYPE_FLAGS -#define TARGET_SECTION_TYPE_FLAGS rs6000_elf_section_type_flags -#endif - #undef TARGET_SCHED_ISSUE_RATE #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate #undef TARGET_SCHED_ADJUST_COST @@ -284,8 +379,18 @@ static const char alt_reg_names[][8] = #undef TARGET_EXPAND_BUILTIN #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin -/* The VRSAVE bitmask puts bit %v0 as the most significant bit. */ -#define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO)) +#undef TARGET_BINDS_LOCAL_P +#define TARGET_BINDS_LOCAL_P rs6000_binds_local_p + +#undef TARGET_ASM_OUTPUT_MI_THUNK +#define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk + +/* ??? Should work everywhere, but ask dje@watson.ibm.com before + enabling for AIX. */ +#if TARGET_OBJECT_FORMAT != OBJECT_XCOFF +#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK +#define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall +#endif struct gcc_target targetm = TARGET_INITIALIZER; @@ -325,6 +430,9 @@ rs6000_override_options (default_cpu) {"power3", PROCESSOR_PPC630, MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, POWER_MASKS | MASK_PPC_GPOPT}, + {"power4", PROCESSOR_POWER4, + MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, + POWER_MASKS | MASK_PPC_GPOPT}, {"powerpc", PROCESSOR_POWERPC, MASK_POWERPC | MASK_NEW_MNEMONICS, POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, @@ -400,6 +508,9 @@ rs6000_override_options (default_cpu) {"7450", PROCESSOR_PPC7450, MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, + {"8540", PROCESSOR_PPC8540, + MASK_POWERPC | MASK_PPC_GFXOPT | MASK_NEW_MNEMONICS, + POWER_MASKS | MASK_PPC_GPOPT | MASK_POWERPC64}, {"801", PROCESSOR_MPCCORE, MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}, @@ -413,7 +524,7 @@ rs6000_override_options (default_cpu) MASK_POWERPC | MASK_SOFT_FLOAT | MASK_NEW_MNEMONICS, POWER_MASKS | POWERPC_OPT_MASKS | MASK_POWERPC64}}; - size_t ptt_size = sizeof (processor_target_table) / sizeof (struct ptt); + const size_t ptt_size = ARRAY_SIZE (processor_target_table); /* Save current -mmultiple/-mno-multiple status. */ int multiple = TARGET_MULTIPLE; @@ -448,10 +559,13 @@ rs6000_override_options (default_cpu) } } - /* If we are optimizing big endian systems for space, use the store - multiple instructions. */ + if (rs6000_cpu == PROCESSOR_PPC8540) + rs6000_isel = 1; + + /* If we are optimizing big endian systems for space, use the load/store + multiple and string instructions. */ if (BYTES_BIG_ENDIAN && optimize_size) - target_flags |= MASK_MULTIPLE; + target_flags |= MASK_MULTIPLE | MASK_STRING; /* If -mmultiple or -mno-multiple was explicitly used, don't override with the processor default */ @@ -492,20 +606,9 @@ rs6000_override_options (default_cpu) flag_pic = 0; } -#ifdef XCOFF_DEBUGGING_INFO - if (flag_function_sections && (write_symbols != NO_DEBUG) - && DEFAULT_ABI == ABI_AIX) - { - warning ("-ffunction-sections disabled on AIX when debugging"); - flag_function_sections = 0; - } - - if (flag_data_sections && (DEFAULT_ABI == ABI_AIX)) - { - warning ("-fdata-sections not supported on AIX"); - flag_data_sections = 0; - } -#endif + /* For Darwin, always silently make -fpic and -fPIC identical. */ + if (flag_pic == 1 && DEFAULT_ABI == ABI_DARWIN) + flag_pic = 2; /* Set debug flags */ if (rs6000_debug_name) @@ -520,6 +623,19 @@ rs6000_override_options (default_cpu) error ("unknown -mdebug-%s switch", rs6000_debug_name); } + if (rs6000_traceback_name) + { + if (! strncmp (rs6000_traceback_name, "full", 4)) + rs6000_traceback = traceback_full; + else if (! strncmp (rs6000_traceback_name, "part", 4)) + rs6000_traceback = traceback_part; + else if (! strncmp (rs6000_traceback_name, "no", 2)) + rs6000_traceback = traceback_none; + else + error ("unknown -mtraceback arg `%s'; expecting `full', `partial' or `none'", + rs6000_traceback_name); + } + /* Set size of long double */ rs6000_long_double_type_size = 64; if (rs6000_long_double_size_string) @@ -536,12 +652,11 @@ rs6000_override_options (default_cpu) /* Handle -mabi= options. */ rs6000_parse_abi_options (); -#ifdef TARGET_REGNAMES - /* If the user desires alternate register names, copy in the - alternate names now. */ - if (TARGET_REGNAMES) - memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); -#endif + /* Handle -mvrsave= option. */ + rs6000_parse_vrsave_option (); + + /* Handle -misel= option. */ + rs6000_parse_isel_option (); #ifdef SUBTARGET_OVERRIDE_OPTIONS SUBTARGET_OVERRIDE_OPTIONS; @@ -550,6 +665,29 @@ rs6000_override_options (default_cpu) SUBSUBTARGET_OVERRIDE_OPTIONS; #endif + /* Handle -m(no-)longcall option. This is a bit of a cheap hack, + using TARGET_OPTIONS to handle a toggle switch, but we're out of + bits in target_flags so TARGET_SWITCHES cannot be used. + Assumption here is that rs6000_longcall_switch points into the + text of the complete option, rather than being a copy, so we can + scan back for the presence or absence of the no- modifier. */ + if (rs6000_longcall_switch) + { + const char *base = rs6000_longcall_switch; + while (base[-1] != 'm') base--; + + if (*rs6000_longcall_switch != '\0') + error ("invalid option `%s'", base); + rs6000_default_long_calls = (base[0] != 'n'); + } + +#ifdef TARGET_REGNAMES + /* If the user desires alternate register names, copy in the + alternate names now. */ + if (TARGET_REGNAMES) + memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names)); +#endif + /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined. If -maix-struct-return or -msvr4-struct-return was explicitly used, don't override with the ABI default. */ @@ -561,6 +699,10 @@ rs6000_override_options (default_cpu) target_flags |= MASK_AIX_STRUCT_RET; } + if (TARGET_LONG_DOUBLE_128 + && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)) + real_format_for_mode[TFmode - QFmode] = &ibm_extended_format; + /* Register global variables with the garbage collector. */ rs6000_add_gc_roots (); @@ -580,7 +722,36 @@ rs6000_override_options (default_cpu) /* Arrange to save and restore machine status around nested functions. */ init_machine_status = rs6000_init_machine_status; - free_machine_status = rs6000_free_machine_status; +} + +/* Handle -misel= option. */ +static void +rs6000_parse_isel_option () +{ + if (rs6000_isel_string == 0) + return; + else if (! strcmp (rs6000_isel_string, "yes")) + rs6000_isel = 1; + else if (! strcmp (rs6000_isel_string, "no")) + rs6000_isel = 0; + else + error ("unknown -misel= option specified: '%s'", + rs6000_isel_string); +} + +/* Handle -mvrsave= options. */ +static void +rs6000_parse_vrsave_option () +{ + /* Generate VRSAVE instructions by default. */ + if (rs6000_altivec_vrsave_string == 0 + || ! strcmp (rs6000_altivec_vrsave_string, "yes")) + rs6000_altivec_vrsave = 1; + else if (! strcmp (rs6000_altivec_vrsave_string, "no")) + rs6000_altivec_vrsave = 0; + else + error ("unknown -mvrsave= option specified: '%s'", + rs6000_altivec_vrsave_string); } /* Handle -mabi= options. */ @@ -593,6 +764,10 @@ rs6000_parse_abi_options () rs6000_altivec_abi = 1; else if (! strcmp (rs6000_abi_string, "no-altivec")) rs6000_altivec_abi = 0; + else if (! strcmp (rs6000_abi_string, "spe")) + rs6000_spe_abi = 1; + else if (! strcmp (rs6000_abi_string, "no-spe")) + rs6000_spe_abi = 0; else error ("unknown ABI specified: '%s'", rs6000_abi_string); } @@ -651,21 +826,8 @@ rs6000_file_start (file, default_cpu) putc ('\n', file); } } - - -/* Create a CONST_DOUBLE from a string. */ - -struct rtx_def * -rs6000_float_const (string, mode) - const char *string; - enum machine_mode mode; -{ - REAL_VALUE_TYPE value; - value = REAL_VALUE_ATOF (string, mode); - return immed_real_const_1 (value, mode); -} -/* Return non-zero if this function is known to have a null epilogue. */ +/* Return nonzero if this function is known to have a null epilogue. */ int direct_return () @@ -936,8 +1098,9 @@ reg_or_add_cint64_operand (op, mode) { return (gpc_reg_operand (op, mode) || (GET_CODE (op) == CONST_INT +#if HOST_BITS_PER_WIDE_INT == 32 && INTVAL (op) < 0x7fff8000 -#if HOST_BITS_PER_WIDE_INT != 32 +#else && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000) < 0x100000000ll) #endif @@ -954,8 +1117,9 @@ reg_or_sub_cint64_operand (op, mode) { return (gpc_reg_operand (op, mode) || (GET_CODE (op) == CONST_INT +#if HOST_BITS_PER_WIDE_INT == 32 && (- INTVAL (op)) < 0x7fff8000 -#if HOST_BITS_PER_WIDE_INT != 32 +#else && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000) < 0x100000000ll) #endif @@ -1037,20 +1201,16 @@ num_insns_constant_wide (value) #if HOST_BITS_PER_WIDE_INT == 64 else if (TARGET_POWERPC64) { - HOST_WIDE_INT low = value & 0xffffffff; - HOST_WIDE_INT high = value >> 32; + HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000; + HOST_WIDE_INT high = value >> 31; - low = (low ^ 0x80000000) - 0x80000000; /* sign extend */ - - if (high == 0 && (low & 0x80000000) == 0) + if (high == 0 || high == -1) return 2; - else if (high == -1 && (low & 0x80000000) != 0) - return 2; + high >>= 1; - else if (! low) + if (low == 0) return num_insns_constant_wide (high) + 1; - else return (num_insns_constant_wide (high) + num_insns_constant_wide (low) + 1); @@ -1151,7 +1311,8 @@ easy_fp_constant (op, mode) return 0; /* Consider all constants with -msoft-float to be easy. */ - if (TARGET_SOFT_FLOAT && mode != DImode) + if ((TARGET_SOFT_FLOAT || !TARGET_FPRS) + && mode != DImode) return 1; /* If we are using V.4 style PIC, consider all constants to be hard. */ @@ -1165,7 +1326,21 @@ easy_fp_constant (op, mode) return 0; #endif - if (mode == DFmode) + if (mode == TFmode) + { + long k[4]; + REAL_VALUE_TYPE rv; + + REAL_VALUE_FROM_CONST_DOUBLE (rv, op); + REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); + + return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 + && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1 + && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1 + && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1); + } + + else if (mode == DFmode) { long k[2]; REAL_VALUE_TYPE rv; @@ -1173,8 +1348,8 @@ easy_fp_constant (op, mode) REAL_VALUE_FROM_CONST_DOUBLE (rv, op); REAL_VALUE_TO_TARGET_DOUBLE (rv, k); - return (num_insns_constant_wide ((HOST_WIDE_INT)k[0]) == 1 - && num_insns_constant_wide ((HOST_WIDE_INT)k[1]) == 1); + return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1 + && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1); } else if (mode == SFmode) @@ -1439,64 +1614,187 @@ mask_operand (op, mode) return c == -lsb; } +/* Return 1 for the PowerPC64 rlwinm corner case. */ + +int +mask_operand_wrap (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + HOST_WIDE_INT c, lsb; + + if (GET_CODE (op) != CONST_INT) + return 0; + + c = INTVAL (op); + + if ((c & 0x80000001) != 0x80000001) + return 0; + + c = ~c; + if (c == 0) + return 0; + + lsb = c & -c; + c = ~c; + c &= -lsb; + lsb = c & -c; + return c == -lsb; +} + /* Return 1 if the operand is a constant that is a PowerPC64 mask. It is if there are no more than one 1->0 or 0->1 transitions. - Reject all ones and all zeros, since these should have been optimized - away and confuse the making of MB and ME. */ + Reject all zeros, since zero should have been optimized away and + confuses the making of MB and ME. */ int mask64_operand (op, mode) rtx op; - enum machine_mode mode; + enum machine_mode mode ATTRIBUTE_UNUSED; { if (GET_CODE (op) == CONST_INT) { HOST_WIDE_INT c, lsb; - /* We don't change the number of transitions by inverting, - so make sure we start with the LS bit zero. */ c = INTVAL (op); - if (c & 1) - c = ~c; - /* Reject all zeros or all ones. */ + /* Reject all zeros. */ if (c == 0) return 0; + /* We don't change the number of transitions by inverting, + so make sure we start with the LS bit zero. */ + if (c & 1) + c = ~c; + /* Find the transition, and check that all bits above are 1's. */ lsb = c & -c; return c == -lsb; } - else if (GET_CODE (op) == CONST_DOUBLE - && (mode == VOIDmode || mode == DImode)) + return 0; +} + +/* Like mask64_operand, but allow up to three transitions. This + predicate is used by insn patterns that generate two rldicl or + rldicr machine insns. */ + +int +mask64_2_operand (op, mode) + rtx op; + enum machine_mode mode ATTRIBUTE_UNUSED; +{ + if (GET_CODE (op) == CONST_INT) { - HOST_WIDE_INT low, high, lsb; + HOST_WIDE_INT c, lsb; - if (HOST_BITS_PER_WIDE_INT < 64) - high = CONST_DOUBLE_HIGH (op); + c = INTVAL (op); - low = CONST_DOUBLE_LOW (op); - if (low & 1) - { - if (HOST_BITS_PER_WIDE_INT < 64) - high = ~high; - low = ~low; - } + /* Disallow all zeros. */ + if (c == 0) + return 0; - if (low == 0) - { - if (HOST_BITS_PER_WIDE_INT >= 64 || high == 0) - return 0; + /* We don't change the number of transitions by inverting, + so make sure we start with the LS bit zero. */ + if (c & 1) + c = ~c; - lsb = high & -high; - return high == -lsb; - } + /* Find the first transition. */ + lsb = c & -c; - lsb = low & -low; - return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0); + /* Invert to look for a second transition. */ + c = ~c; + + /* Erase first transition. */ + c &= -lsb; + + /* Find the second transition. */ + lsb = c & -c; + + /* Invert to look for a third transition. */ + c = ~c; + + /* Erase second transition. */ + c &= -lsb; + + /* Find the third transition (if any). */ + lsb = c & -c; + + /* Match if all the bits above are 1's (or c is zero). */ + return c == -lsb; + } + return 0; +} + +/* Generates shifts and masks for a pair of rldicl or rldicr insns to + implement ANDing by the mask IN. */ +void +build_mask64_2_operands (in, out) + rtx in; + rtx *out; +{ +#if HOST_BITS_PER_WIDE_INT >= 64 + unsigned HOST_WIDE_INT c, lsb, m1, m2; + int shift; + + if (GET_CODE (in) != CONST_INT) + abort (); + + c = INTVAL (in); + if (c & 1) + { + /* Assume c initially something like 0x00fff000000fffff. The idea + is to rotate the word so that the middle ^^^^^^ group of zeros + is at the MS end and can be cleared with an rldicl mask. We then + rotate back and clear off the MS ^^ group of zeros with a + second rldicl. */ + c = ~c; /* c == 0xff000ffffff00000 */ + lsb = c & -c; /* lsb == 0x0000000000100000 */ + m1 = -lsb; /* m1 == 0xfffffffffff00000 */ + c = ~c; /* c == 0x00fff000000fffff */ + c &= -lsb; /* c == 0x00fff00000000000 */ + lsb = c & -c; /* lsb == 0x0000100000000000 */ + c = ~c; /* c == 0xff000fffffffffff */ + c &= -lsb; /* c == 0xff00000000000000 */ + shift = 0; + while ((lsb >>= 1) != 0) + shift++; /* shift == 44 on exit from loop */ + m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */ + m1 = ~m1; /* m1 == 0x000000ffffffffff */ + m2 = ~c; /* m2 == 0x00ffffffffffffff */ } else - return 0; + { + /* Assume c initially something like 0xff000f0000000000. The idea + is to rotate the word so that the ^^^ middle group of zeros + is at the LS end and can be cleared with an rldicr mask. We then + rotate back and clear off the LS group of ^^^^^^^^^^ zeros with + a second rldicr. */ + lsb = c & -c; /* lsb == 0x0000010000000000 */ + m2 = -lsb; /* m2 == 0xffffff0000000000 */ + c = ~c; /* c == 0x00fff0ffffffffff */ + c &= -lsb; /* c == 0x00fff00000000000 */ + lsb = c & -c; /* lsb == 0x0000100000000000 */ + c = ~c; /* c == 0xff000fffffffffff */ + c &= -lsb; /* c == 0xff00000000000000 */ + shift = 0; + while ((lsb >>= 1) != 0) + shift++; /* shift == 44 on exit from loop */ + m1 = ~c; /* m1 == 0x00ffffffffffffff */ + m1 >>= shift; /* m1 == 0x0000000000000fff */ + m1 = ~m1; /* m1 == 0xfffffffffffff000 */ + } + + /* Note that when we only have two 0->1 and 1->0 transitions, one of the + masks will be all 1's. We are guaranteed more than one transition. */ + out[0] = GEN_INT (64 - shift); + out[1] = GEN_INT (m1); + out[2] = GEN_INT (shift); + out[3] = GEN_INT (m2); +#else + (void)in; + (void)out; + abort (); +#endif } /* Return 1 if the operand is either a non-special register or a constant @@ -1513,6 +1811,20 @@ and64_operand (op, mode) return (logical_operand (op, mode) || mask64_operand (op, mode)); } +/* Like the above, but also match constants that can be implemented + with two rldicl or rldicr insns. */ + +int +and64_2_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */ + return gpc_reg_operand (op, mode) || mask64_2_operand (op, mode); + + return logical_operand (op, mode) || mask64_2_operand (op, mode); +} + /* Return 1 if the operand is either a non-special register or a constant that can be used as the operand of an RS/6000 logical AND insn. */ @@ -1562,9 +1874,21 @@ lwa_operand (op, mode) || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0)); } +/* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */ + +int +symbol_ref_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (mode != VOIDmode && GET_MODE (op) != mode) + return 0; + + return (GET_CODE (op) == SYMBOL_REF); +} + /* Return 1 if the operand, used inside a MEM, is a valid first argument - to CALL. This is a SYMBOL_REF or a pseudo-register, which will be - forced to lr. */ + to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */ int call_operand (op, mode) @@ -1575,7 +1899,10 @@ call_operand (op, mode) return 0; return (GET_CODE (op) == SYMBOL_REF - || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER)); + || (GET_CODE (op) == REG + && (REGNO (op) == LINK_REGISTER_REGNUM + || REGNO (op) == COUNT_REGISTER_REGNUM + || REGNO (op) >= FIRST_PSEUDO_REGISTER))); } /* Return 1 if the operand is a SYMBOL_REF for a function known to be in @@ -1790,10 +2117,8 @@ rs6000_legitimize_address (x, oldx, mode) { HOST_WIDE_INT high_int, low_int; rtx sum; - high_int = INTVAL (XEXP (x, 1)) & (~ (HOST_WIDE_INT) 0xffff); - low_int = INTVAL (XEXP (x, 1)) & 0xffff; - if (low_int & 0x8000) - high_int += 0x10000, low_int |= ((HOST_WIDE_INT) -1) << 16; + low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000; + high_int = INTVAL (XEXP (x, 1)) - low_int; sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0), GEN_INT (high_int)), 0); return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int)); @@ -1802,7 +2127,9 @@ rs6000_legitimize_address (x, oldx, mode) && GET_CODE (XEXP (x, 0)) == REG && GET_CODE (XEXP (x, 1)) != CONST_INT && GET_MODE_NUNITS (mode) == 1 - && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode) + && ((TARGET_HARD_FLOAT && TARGET_FPRS) + || TARGET_POWERPC64 + || (mode != DFmode && mode != TFmode)) && (TARGET_POWERPC64 || mode != DImode) && mode != TImode) { @@ -1821,13 +2148,34 @@ rs6000_legitimize_address (x, oldx, mode) reg = force_reg (Pmode, x); return reg; } + else if (SPE_VECTOR_MODE (mode)) + { + /* We accept [reg + reg] and [reg + OFFSET]. */ + + if (GET_CODE (x) == PLUS) + { + rtx op1 = XEXP (x, 0); + rtx op2 = XEXP (x, 1); + + op1 = force_reg (Pmode, op1); + + if (GET_CODE (op2) != REG + && (GET_CODE (op2) != CONST_INT + || !SPE_CONST_OFFSET_OK (INTVAL (op2)))) + op2 = force_reg (Pmode, op2); + + return gen_rtx_PLUS (Pmode, op1, op2); + } + + return force_reg (Pmode, x); + } else if (TARGET_ELF && TARGET_32BIT && TARGET_NO_TOC && ! flag_pic && GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE && CONSTANT_P (x) && GET_MODE_NUNITS (mode) == 1 && (GET_MODE_BITSIZE (mode) <= 32 - || (TARGET_HARD_FLOAT && mode == DFmode))) + || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode))) { rtx reg = gen_reg_rtx (Pmode); emit_insn (gen_elf_high (reg, (x))); @@ -1838,7 +2186,7 @@ rs6000_legitimize_address (x, oldx, mode) && GET_CODE (x) != CONST_INT && GET_CODE (x) != CONST_DOUBLE && CONSTANT_P (x) - && (TARGET_HARD_FLOAT || mode != DFmode) + && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode) && mode != DImode && mode != TImode) { @@ -1925,6 +2273,7 @@ rs6000_legitimize_reload_address (x, mode, opnum, type, ind_levels, win) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode) && GET_CODE (XEXP (x, 1)) == CONST_INT + && !SPE_VECTOR_MODE (mode) && !ALTIVEC_VECTOR_MODE (mode)) { HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); @@ -2013,6 +2362,7 @@ rs6000_legitimate_address (mode, x, reg_ok_strict) return 1; if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) && !ALTIVEC_VECTOR_MODE (mode) + && !SPE_VECTOR_MODE (mode) && TARGET_UPDATE && LEGITIMATE_INDIRECT_ADDRESS_P (XEXP (x, 0), reg_ok_strict)) return 1; @@ -2030,7 +2380,9 @@ rs6000_legitimate_address (mode, x, reg_ok_strict) if (LEGITIMATE_OFFSET_ADDRESS_P (mode, x, reg_ok_strict)) return 1; if (mode != TImode - && (TARGET_HARD_FLOAT || TARGET_POWERPC64 || mode != DFmode) + && ((TARGET_HARD_FLOAT && TARGET_FPRS) + || TARGET_POWERPC64 + || (mode != DFmode && mode != TFmode)) && (TARGET_POWERPC64 || mode != DImode) && LEGITIMATE_INDEXED_ADDRESS_P (x, reg_ok_strict)) return 1; @@ -2051,35 +2403,59 @@ rs6000_emit_set_const (dest, mode, source, n) enum machine_mode mode; int n ATTRIBUTE_UNUSED; { + rtx result, insn, set; HOST_WIDE_INT c0, c1; - if (mode == QImode || mode == HImode || mode == SImode) + if (mode == QImode || mode == HImode) { if (dest == NULL) dest = gen_reg_rtx (mode); emit_insn (gen_rtx_SET (VOIDmode, dest, source)); return dest; } - - if (GET_CODE (source) == CONST_INT) + else if (mode == SImode) { - c0 = INTVAL (source); - c1 = -(c0 < 0); + result = no_new_pseudos ? dest : gen_reg_rtx (SImode); + + emit_insn (gen_rtx_SET (VOIDmode, result, + GEN_INT (INTVAL (source) + & (~ (HOST_WIDE_INT) 0xffff)))); + emit_insn (gen_rtx_SET (VOIDmode, dest, + gen_rtx_IOR (SImode, result, + GEN_INT (INTVAL (source) & 0xffff)))); + result = dest; } - else if (GET_CODE (source) == CONST_DOUBLE) + else if (mode == DImode) { + if (GET_CODE (source) == CONST_INT) + { + c0 = INTVAL (source); + c1 = -(c0 < 0); + } + else if (GET_CODE (source) == CONST_DOUBLE) + { #if HOST_BITS_PER_WIDE_INT >= 64 - c0 = CONST_DOUBLE_LOW (source); - c1 = -(c0 < 0); + c0 = CONST_DOUBLE_LOW (source); + c1 = -(c0 < 0); #else - c0 = CONST_DOUBLE_LOW (source); - c1 = CONST_DOUBLE_HIGH (source); + c0 = CONST_DOUBLE_LOW (source); + c1 = CONST_DOUBLE_HIGH (source); #endif + } + else + abort (); + + result = rs6000_emit_set_long_const (dest, c0, c1); } else abort (); - return rs6000_emit_set_long_const (dest, c0, c1); + insn = get_last_insn (); + set = single_set (insn); + if (! CONSTANT_P (SET_SRC (set))) + set_unique_reg_note (insn, REG_EQUAL, source); + + return result; } /* Having failed to find a 3 insn sequence in rs6000_emit_set_const, @@ -2190,8 +2566,7 @@ rs6000_emit_move (dest, source, mode) /* FIXME. This should never happen. */ /* Since it seems that it does, do the safe thing and convert to a CONST_INT. */ - operands[1] = - GEN_INT (trunc_int_for_mode (CONST_DOUBLE_LOW (operands[1]), mode)); + operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode); } if (GET_CODE (operands[1]) == CONST_DOUBLE && ! FLOAT_MODE_P (mode) @@ -2223,10 +2598,25 @@ rs6000_emit_move (dest, source, mode) return; } - if (! no_new_pseudos && GET_CODE (operands[0]) != REG) - operands[1] = force_reg (mode, operands[1]); + if (!no_new_pseudos) + { + if (GET_CODE (operands[1]) == MEM && optimize > 0 + && (mode == QImode || mode == HImode || mode == SImode) + && GET_MODE_SIZE (mode) < GET_MODE_SIZE (word_mode)) + { + rtx reg = gen_reg_rtx (word_mode); + + emit_insn (gen_rtx_SET (word_mode, reg, + gen_rtx_ZERO_EXTEND (word_mode, + operands[1]))); + operands[1] = gen_lowpart (mode, reg); + } + if (GET_CODE (operands[0]) != REG) + operands[1] = force_reg (mode, operands[1]); + } - if (mode == SFmode && ! TARGET_POWERPC && TARGET_HARD_FLOAT + if (mode == SFmode && ! TARGET_POWERPC + && TARGET_HARD_FLOAT && TARGET_FPRS && GET_CODE (operands[0]) == MEM) { int regnum; @@ -2250,16 +2640,15 @@ rs6000_emit_move (dest, source, mode) } } - /* Handle the case where reload calls us with an invalid address; - and the case of CONSTANT_P_RTX. */ - if (!VECTOR_MODE_P (mode) + /* Handle the case where reload calls us with an invalid address. */ + if (reload_in_progress && mode == Pmode && (! general_operand (operands[1], mode) - || ! nonimmediate_operand (operands[0], mode) - || GET_CODE (operands[1]) == CONSTANT_P_RTX)) - { - emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); - return; - } + || ! nonimmediate_operand (operands[0], mode))) + goto emit_set; + + /* Handle the case of CONSTANT_P_RTX. */ + if (GET_CODE (operands[1]) == CONSTANT_P_RTX) + goto emit_set; /* FIXME: In the long term, this switch statement should go away and be replaced by a sequence of tests based on things like @@ -2285,6 +2674,10 @@ rs6000_emit_move (dest, source, mode) case V8HImode: case V4SFmode: case V4SImode: + case V4HImode: + case V2SFmode: + case V2SImode: + case V1DImode: if (CONSTANT_P (operands[1]) && !easy_vector_constant (operands[1])) operands[1] = force_const_mem (mode, operands[1]); @@ -2451,6 +2844,16 @@ rs6000_emit_move (dest, source, mode) operands[1] = replace_equiv_address (operands[1], copy_addr_to_reg (XEXP (operands[1], 0))); + if (TARGET_POWER) + { + emit_insn (gen_rtx_PARALLEL (VOIDmode, + gen_rtvec (2, + gen_rtx_SET (VOIDmode, + operands[0], operands[1]), + gen_rtx_CLOBBER (VOIDmode, + gen_rtx_SCRATCH (SImode))))); + return; + } break; default: @@ -2460,13 +2863,11 @@ rs6000_emit_move (dest, source, mode) /* Above, we may have called force_const_mem which may have returned an invalid address. If we can, fix this up; otherwise, reload will have to deal with it. */ - if (GET_CODE (operands[1]) == MEM - && ! memory_address_p (mode, XEXP (operands[1], 0)) - && ! reload_in_progress) - operands[1] = adjust_address (operands[1], mode, 0); + if (GET_CODE (operands[1]) == MEM && ! reload_in_progress) + operands[1] = validize_mem (operands[1]); + emit_set: emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); - return; } /* Initialize a variable CUM of type CUMULATIVE_ARGS @@ -2477,11 +2878,12 @@ rs6000_emit_move (dest, source, mode) so we never return a PARALLEL. */ void -init_cumulative_args (cum, fntype, libname, incoming) +init_cumulative_args (cum, fntype, libname, incoming, libcall) CUMULATIVE_ARGS *cum; tree fntype; rtx libname ATTRIBUTE_UNUSED; int incoming; + int libcall; { static CUMULATIVE_ARGS zero_cumulative; @@ -2490,7 +2892,8 @@ init_cumulative_args (cum, fntype, libname, incoming) cum->fregno = FP_ARG_MIN_REG; cum->vregno = ALTIVEC_ARG_MIN_REG; cum->prototype = (fntype && TYPE_ARG_TYPES (fntype)); - cum->call_cookie = CALL_NORMAL; + cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall) + ? CALL_LIBCALL : CALL_NORMAL); cum->sysv_gregno = GP_ARG_MIN_REG; if (incoming) @@ -2506,8 +2909,10 @@ init_cumulative_args (cum, fntype, libname, incoming) cum->orig_nargs = cum->nargs_prototype; - /* Check for longcall's */ - if (fntype && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))) + /* Check for a longcall attribute. */ + if (fntype + && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype)) + && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))) cum->call_cookie = CALL_LONG; if (TARGET_DEBUG_ARG) @@ -2568,6 +2973,8 @@ function_arg_boundary (mode, type) { if (DEFAULT_ABI == ABI_V4 && (mode == DImode || mode == DFmode)) return 64; + else if (SPE_VECTOR_MODE (mode)) + return 64; else if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) return 128; else @@ -2594,9 +3001,12 @@ function_arg_advance (cum, mode, type, named) else cum->words += RS6000_ARG_SIZE (mode, type); } + else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode) + && named && cum->sysv_gregno <= GP_ARG_MAX_REG) + cum->sysv_gregno++; else if (DEFAULT_ABI == ABI_V4) { - if (TARGET_HARD_FLOAT + if (TARGET_HARD_FLOAT && TARGET_FPRS && (mode == SFmode || mode == DFmode)) { if (cum->fregno <= FP_ARG_V4_MAX_REG) @@ -2620,11 +3030,12 @@ function_arg_advance (cum, mode, type, named) else n_words = RS6000_ARG_SIZE (mode, type); - /* Long long is put in odd registers. */ + /* Long long and SPE vectors are put in odd registers. */ if (n_words == 2 && (gregno & 1) == 0) gregno += 1; - /* Long long is not split between registers and stack. */ + /* Long long and SPE vectors are not split between registers + and stack. */ if (gregno + n_words - 1 > GP_ARG_MAX_REG) { /* Long long is aligned on the stack. */ @@ -2656,8 +3067,9 @@ function_arg_advance (cum, mode, type, named) cum->words += align + RS6000_ARG_SIZE (mode, type); - if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_HARD_FLOAT) - cum->fregno++; + if (GET_MODE_CLASS (mode) == MODE_FLOAT + && TARGET_HARD_FLOAT && TARGET_FPRS) + cum->fregno += (mode == TFmode ? 2 : 1); if (TARGET_DEBUG_ARG) { @@ -2689,7 +3101,7 @@ function_arg_advance (cum, mode, type, named) If this is floating-point and no prototype is specified, we use both an FP and integer register (or possibly FP reg and stack). Library - functions (when TYPE is zero) always have the proper types for args, + functions (when CALL_LIBCALL is set) always have the proper types for args, so we can pass the FP value just in one register. emit_library_function doesn't support PARALLEL anyway. */ @@ -2709,14 +3121,18 @@ function_arg (cum, mode, type, named) if (mode == VOIDmode) { if (abi == ABI_V4 - && TARGET_HARD_FLOAT && cum->nargs_prototype < 0 - && type && (cum->prototype || TARGET_NO_PROTOTYPE)) + && (cum->call_cookie & CALL_LIBCALL) == 0 + && (cum->prototype || TARGET_NO_PROTOTYPE)) { - return GEN_INT (cum->call_cookie - | ((cum->fregno == FP_ARG_MIN_REG) - ? CALL_V4_SET_FP_ARGS - : CALL_V4_CLEAR_FP_ARGS)); + /* For the SPE, we need to crxor CR6 always. */ + if (TARGET_SPE_ABI) + return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS); + else if (TARGET_HARD_FLOAT && TARGET_FPRS) + return GEN_INT (cum->call_cookie + | ((cum->fregno == FP_ARG_MIN_REG) + ? CALL_V4_SET_FP_ARGS + : CALL_V4_CLEAR_FP_ARGS)); } return GEN_INT (cum->call_cookie); @@ -2729,9 +3145,16 @@ function_arg (cum, mode, type, named) else return NULL; } + else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode) && named) + { + if (cum->sysv_gregno <= GP_ARG_MAX_REG) + return gen_rtx_REG (mode, cum->sysv_gregno); + else + return NULL; + } else if (abi == ABI_V4) { - if (TARGET_HARD_FLOAT + if (TARGET_HARD_FLOAT && TARGET_FPRS && (mode == SFmode || mode == DFmode)) { if (cum->fregno <= FP_ARG_V4_MAX_REG) @@ -2751,13 +3174,29 @@ function_arg (cum, mode, type, named) else n_words = RS6000_ARG_SIZE (mode, type); - /* Long long is put in odd registers. */ + /* Long long and SPE vectors are put in odd registers. */ if (n_words == 2 && (gregno & 1) == 0) gregno += 1; - /* Long long is not split between registers and stack. */ + /* Long long and SPE vectors are not split between registers + and stack. */ if (gregno + n_words - 1 <= GP_ARG_MAX_REG) - return gen_rtx_REG (mode, gregno); + { + /* SPE vectors in ... get split into 2 registers. */ + if (TARGET_SPE && TARGET_SPE_ABI + && SPE_VECTOR_MODE (mode) && !named) + { + rtx r1, r2; + enum machine_mode m = SImode; + + r1 = gen_rtx_REG (m, gregno); + r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx); + r2 = gen_rtx_REG (m, gregno + 1); + r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4)); + return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2)); + } + return gen_rtx_REG (mode, gregno); + } else return NULL; } @@ -2850,7 +3289,10 @@ function_arg_partial_nregs (cum, mode, type, named) the argument itself. The pointer is passed in whatever way is appropriate for passing a pointer to that type. - Under V.4, structures and unions are passed by reference. */ + Under V.4, structures and unions are passed by reference. + + As an extension to all ABIs, variable sized types are passed by + reference. */ int function_arg_pass_by_reference (cum, mode, type, named) @@ -2868,8 +3310,7 @@ function_arg_pass_by_reference (cum, mode, type, named) return 1; } - - return 0; + return type && int_size_in_bytes (type) <= 0; } /* Perform any needed actions needed for a function that is receiving a @@ -2916,8 +3357,6 @@ setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl) if (DEFAULT_ABI == ABI_V4) { /* Indicate to allocate space on the stack for varargs save area. */ - /* ??? Does this really have to be located at a magic spot on the - stack, or can we allocate this with assign_stack_local instead. */ cfun->machine->sysv_varargs_p = 1; if (! no_rtl) save_area = plus_constant (virtual_stack_vars_rtx, @@ -2955,7 +3394,8 @@ setup_incoming_varargs (cum, mode, type, pretend_size, no_rtl) /* Save FP registers if needed. */ if (DEFAULT_ABI == ABI_V4 - && TARGET_HARD_FLOAT && ! no_rtl + && TARGET_HARD_FLOAT && TARGET_FPRS + && ! no_rtl && next_cum.fregno <= FP_ARG_V4_MAX_REG) { int fregno = next_cum.fregno; @@ -2996,7 +3436,7 @@ rs6000_build_va_list () if (DEFAULT_ABI != ABI_V4) return build_pointer_type (char_type_node); - record = make_lang_type (RECORD_TYPE); + record = (*lang_hooks.types.make_type) (RECORD_TYPE); type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record); f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"), @@ -3029,8 +3469,7 @@ rs6000_build_va_list () /* Implement va_start. */ void -rs6000_va_start (stdarg_p, valist, nextarg) - int stdarg_p; +rs6000_va_start (valist, nextarg) tree valist; rtx nextarg; { @@ -3041,7 +3480,7 @@ rs6000_va_start (stdarg_p, valist, nextarg) /* Only SVR4 needs something special. */ if (DEFAULT_ABI != ABI_V4) { - std_expand_builtin_va_start (stdarg_p, valist, nextarg); + std_expand_builtin_va_start (valist, nextarg); return; } @@ -3109,13 +3548,29 @@ rs6000_va_arg (valist, type) int indirect_p, size, rsize, n_reg, sav_ofs, sav_scale; rtx lab_false, lab_over, addr_rtx, r; - /* For AIX, the rule is that structures are passed left-aligned in - their stack slot. However, GCC does not presently do this: - structures which are the same size as integer types are passed - right-aligned, as if they were in fact integers. This only - matters for structures of size 1 or 2, or 4 when TARGET_64BIT. */ if (DEFAULT_ABI != ABI_V4) - return std_expand_builtin_va_arg (valist, type); + { + /* Variable sized types are passed by reference. */ + if (int_size_in_bytes (type) <= 0) + { + u = build_pointer_type (type); + + /* Args grow upward. */ + t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist, + build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0)); + TREE_SIDE_EFFECTS (t) = 1; + + t = build1 (NOP_EXPR, build_pointer_type (u), t); + TREE_SIDE_EFFECTS (t) = 1; + + t = build1 (INDIRECT_REF, u, t); + TREE_SIDE_EFFECTS (t) = 1; + + return expand_expr (t, NULL_RTX, VOIDmode, EXPAND_NORMAL); + } + else + return std_expand_builtin_va_arg (valist, type); + } f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node)); f_fpr = TREE_CHAIN (f_gpr); @@ -3142,7 +3597,7 @@ rs6000_va_arg (valist, type) size = UNITS_PER_WORD; rsize = 1; } - else if (FLOAT_TYPE_P (type) && ! TARGET_SOFT_FLOAT) + else if (FLOAT_TYPE_P (type) && TARGET_HARD_FLOAT && TARGET_FPRS) { /* FP args go in FP registers, if present. */ indirect_p = 0; @@ -3167,8 +3622,8 @@ rs6000_va_arg (valist, type) lab_over = gen_label_rtx (); addr_rtx = gen_reg_rtx (Pmode); - /* Vectors never go in registers. */ - if (TREE_CODE (type) != VECTOR_TYPE) + /* AltiVec vectors never go in registers. */ + if (!TARGET_ALTIVEC || TREE_CODE (type) != VECTOR_TYPE) { TREE_THIS_VOLATILE (reg) = 1; emit_cmp_and_jump_insns @@ -3222,7 +3677,8 @@ rs6000_va_arg (valist, type) All AltiVec vectors go in the overflow area. So in the AltiVec case we need to get the vectors from the overflow area, but remember where the GPRs and FPRs are. */ - if (n_reg > 1 && TREE_CODE (type) != VECTOR_TYPE) + if (n_reg > 1 && (TREE_CODE (type) != VECTOR_TYPE + || !TARGET_ALTIVEC)) { t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, build_int_2 (8, 0)); TREE_SIDE_EFFECTS (t) = 1; @@ -3236,8 +3692,8 @@ rs6000_va_arg (valist, type) { int align; - /* Vectors are 16 byte aligned. */ - if (TREE_CODE (type) == VECTOR_TYPE) + /* AltiVec vectors are 16 byte aligned. */ + if (TARGET_ALTIVEC && TREE_CODE (type) == VECTOR_TYPE) align = 15; else align = 7; @@ -3270,20 +3726,13 @@ rs6000_va_arg (valist, type) /* Builtins. */ -#define def_builtin(MASK, NAME, TYPE, CODE) \ -do { \ - if ((MASK) & target_flags) \ - builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL); \ +#define def_builtin(MASK, NAME, TYPE, CODE) \ +do { \ + if ((MASK) & target_flags) \ + builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \ + NULL, NULL_TREE); \ } while (0) -struct builtin_description -{ - const unsigned int mask; - const enum insn_code icode; - const char *const name; - const enum rs6000_builtins code; -}; - /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */ static const struct builtin_description bdesc_3arg[] = @@ -3325,7 +3774,7 @@ static const struct builtin_description bdesc_dst[] = /* Simple binary operations: VECc = foo (VECa, VECb). */ -static const struct builtin_description bdesc_2arg[] = +static struct builtin_description bdesc_2arg[] = { { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM }, { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM }, @@ -3365,11 +3814,11 @@ static const struct builtin_description bdesc_2arg[] = { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS }, { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB }, { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB }, - { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH }, - { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH }, - { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW }, - { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW }, - { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP }, + { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH }, + { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH }, + { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW }, + { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW }, + { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP }, { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB }, { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH }, { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW }, @@ -3440,6 +3889,150 @@ static const struct builtin_description bdesc_2arg[] = { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS }, { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS }, { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR }, + + /* Place holder, leave as first spe builtin. */ + { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW }, + { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND }, + { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC }, + { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS }, + { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU }, + { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV }, + { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD }, + { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV }, + { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL }, + { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB }, + { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI }, + { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO }, + { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO }, + { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI }, + { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA }, + { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN }, + { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA }, + { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN }, + { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA }, + { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN }, + { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF }, + { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA }, + { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW }, + { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW }, + { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI }, + { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA }, + { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW }, + { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW }, + { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF }, + { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA }, + { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW }, + { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW }, + { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW }, + { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW }, + { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI }, + { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA }, + { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW }, + { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW }, + { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW }, + { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW }, + { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA }, + { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN }, + { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA }, + { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN }, + { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA }, + { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN }, + { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF }, + { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA }, + { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW }, + { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW }, + { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI }, + { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA }, + { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW }, + { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW }, + { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF }, + { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA }, + { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW }, + { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW }, + { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW }, + { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW }, + { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI }, + { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA }, + { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW }, + { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW }, + { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW }, + { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW }, + { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF }, + { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA }, + { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI }, + { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA }, + { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF }, + { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA }, + { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI }, + { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA }, + { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW }, + { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW }, + { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW }, + { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW }, + { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI }, + { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA }, + { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW }, + { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW }, + { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW }, + { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW }, + { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF }, + { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA }, + { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA }, + { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN }, + { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI }, + { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA }, + { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA }, + { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN }, + { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF }, + { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA }, + { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA }, + { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN }, + { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI }, + { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA }, + { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA }, + { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN }, + { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND }, + { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR }, + { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR }, + { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC }, + { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW }, + { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW }, + { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS }, + { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU }, + { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW }, + + /* SPE binary operations expecting a 5-bit unsigned literal. */ + { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW }, + + { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI }, + { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI }, + { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS }, + { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU }, + { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW }, + { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA }, + { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA }, + { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA }, + { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA }, + { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA }, + { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA }, + { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN }, + { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN }, + { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN }, + { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN }, + { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN }, + { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN }, + { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA }, + { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA }, + { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA }, + { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA }, + { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN }, + { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN }, + { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN }, + { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN }, + { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC }, + + /* Place-holder. Leave as last binary SPE builtin. */ + { 0, CODE_FOR_spe_evxor, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }, }; /* AltiVec predicates. */ @@ -3470,6 +4063,42 @@ static const struct builtin_description_predicates bdesc_altivec_preds[] = { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P } }; +/* SPE predicates. */ +static struct builtin_description bdesc_spe_predicates[] = +{ + /* Place-holder. Leave as first. */ + { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ }, + { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS }, + { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU }, + { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS }, + { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU }, + { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ }, + { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT }, + { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT }, + { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ }, + { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT }, + /* Place-holder. Leave as last. */ + { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT }, +}; + +/* SPE evsel predicates. */ +static struct builtin_description bdesc_spe_evsel[] = +{ + /* Place-holder. Leave as first. */ + { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS }, + { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU }, + { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS }, + { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU }, + { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ }, + { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT }, + { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT }, + { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ }, + { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT }, + { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT }, + /* Place-holder. Leave as last. */ + { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ }, +}; + /* ABS* opreations. */ static const struct builtin_description bdesc_abs[] = @@ -3486,7 +4115,7 @@ static const struct builtin_description bdesc_abs[] = /* Simple unary operations: VECb = foo (unsigned literal) or VECb = foo (VECa). */ -static const struct builtin_description bdesc_1arg[] = +static struct builtin_description bdesc_1arg[] = { { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP }, { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP }, @@ -3505,10 +4134,46 @@ static const struct builtin_description bdesc_1arg[] = { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB }, { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX }, { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH }, + + /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and + end with SPE_BUILTIN_EVSUBFUSIAAW. */ + { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS }, + { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW }, + { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW }, + { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW }, + { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW }, + { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW }, + { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW }, + { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB }, + { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH }, + { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS }, + { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF }, + { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI }, + { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF }, + { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI }, + { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF }, + { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI }, + { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ }, + { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF }, + { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI }, + { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ }, + { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS }, + { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG }, + { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA }, + { 0, CODE_FOR_spe_evneg, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG }, + { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW }, + { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW }, + { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW }, + { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW }, + { 0, CODE_FOR_spe_evsplatfi, "__builtin_spe_evsplatfi", SPE_BUILTIN_EVSPLATFI }, + { 0, CODE_FOR_spe_evsplati, "__builtin_spe_evsplati", SPE_BUILTIN_EVSPLATI }, + + /* Place-holder. Leave as last unary SPE builtin. */ + { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }, }; static rtx -altivec_expand_unop_builtin (icode, arglist, target) +rs6000_expand_unop_builtin (icode, arglist, target) enum insn_code icode; tree arglist; rtx target; @@ -3519,9 +4184,29 @@ altivec_expand_unop_builtin (icode, arglist, target) enum machine_mode tmode = insn_data[icode].operand[0].mode; enum machine_mode mode0 = insn_data[icode].operand[1].mode; + if (icode == CODE_FOR_nothing) + /* Builtin not supported on this processor. */ + return 0; + /* If we got invalid arguments bail out before generating bad rtl. */ if (arg0 == error_mark_node) - return NULL_RTX; + return const0_rtx; + + if (icode == CODE_FOR_altivec_vspltisb + || icode == CODE_FOR_altivec_vspltish + || icode == CODE_FOR_altivec_vspltisw + || icode == CODE_FOR_spe_evsplatfi + || icode == CODE_FOR_spe_evsplati) + { + /* Only allow 5-bit *signed* literals. */ + if (GET_CODE (op0) != CONST_INT + || INTVAL (op0) > 0x1f + || INTVAL (op0) < -0x1f) + { + error ("argument 1 must be a 5-bit signed literal"); + return const0_rtx; + } + } if (target == 0 || GET_MODE (target) != tmode @@ -3553,7 +4238,7 @@ altivec_expand_abs_builtin (icode, arglist, target) /* If we have invalid arguments, bail out before generating bad rtl. */ if (arg0 == error_mark_node) - return NULL_RTX; + return const0_rtx; if (target == 0 || GET_MODE (target) != tmode @@ -3575,7 +4260,7 @@ altivec_expand_abs_builtin (icode, arglist, target) } static rtx -altivec_expand_binop_builtin (icode, arglist, target) +rs6000_expand_binop_builtin (icode, arglist, target) enum insn_code icode; tree arglist; rtx target; @@ -3589,9 +4274,46 @@ altivec_expand_binop_builtin (icode, arglist, target) enum machine_mode mode0 = insn_data[icode].operand[1].mode; enum machine_mode mode1 = insn_data[icode].operand[2].mode; + if (icode == CODE_FOR_nothing) + /* Builtin not supported on this processor. */ + return 0; + /* If we got invalid arguments bail out before generating bad rtl. */ if (arg0 == error_mark_node || arg1 == error_mark_node) - return NULL_RTX; + return const0_rtx; + + if (icode == CODE_FOR_altivec_vcfux + || icode == CODE_FOR_altivec_vcfsx + || icode == CODE_FOR_altivec_vctsxs + || icode == CODE_FOR_altivec_vctuxs + || icode == CODE_FOR_altivec_vspltb + || icode == CODE_FOR_altivec_vsplth + || icode == CODE_FOR_altivec_vspltw + || icode == CODE_FOR_spe_evaddiw + || icode == CODE_FOR_spe_evldd + || icode == CODE_FOR_spe_evldh + || icode == CODE_FOR_spe_evldw + || icode == CODE_FOR_spe_evlhhesplat + || icode == CODE_FOR_spe_evlhhossplat + || icode == CODE_FOR_spe_evlhhousplat + || icode == CODE_FOR_spe_evlwhe + || icode == CODE_FOR_spe_evlwhos + || icode == CODE_FOR_spe_evlwhou + || icode == CODE_FOR_spe_evlwhsplat + || icode == CODE_FOR_spe_evlwwsplat + || icode == CODE_FOR_spe_evrlwi + || icode == CODE_FOR_spe_evslwi + || icode == CODE_FOR_spe_evsrwis + || icode == CODE_FOR_spe_evsrwiu) + { + /* Only allow 5-bit unsigned literals. */ + if (TREE_CODE (arg1) != INTEGER_CST + || TREE_INT_CST_LOW (arg1) & ~0x1f) + { + error ("argument 2 must be a 5-bit unsigned literal"); + return const0_rtx; + } + } if (target == 0 || GET_MODE (target) != tmode @@ -3632,7 +4354,7 @@ altivec_expand_predicate_builtin (icode, opcode, arglist, target) if (TREE_CODE (cr6_form) != INTEGER_CST) { error ("argument 1 of __builtin_altivec_predicate must be a constant"); - return NULL_RTX; + return const0_rtx; } else cr6_form_int = TREE_INT_CST_LOW (cr6_form); @@ -3642,7 +4364,7 @@ altivec_expand_predicate_builtin (icode, opcode, arglist, target) /* If we have invalid arguments, bail out before generating bad rtl. */ if (arg0 == error_mark_node || arg1 == error_mark_node) - return NULL_RTX; + return const0_rtx; if (target == 0 || GET_MODE (target) != tmode @@ -3712,7 +4434,7 @@ altivec_expand_stv_builtin (icode, arglist) if (arg0 == error_mark_node || arg1 == error_mark_node || arg2 == error_mark_node) - return NULL_RTX; + return const0_rtx; if (! (*insn_data[icode].operand[2].predicate) (op0, mode2)) op0 = copy_to_mode_reg (mode2, op0); @@ -3728,7 +4450,7 @@ altivec_expand_stv_builtin (icode, arglist) } static rtx -altivec_expand_ternop_builtin (icode, arglist, target) +rs6000_expand_ternop_builtin (icode, arglist, target) enum insn_code icode; tree arglist; rtx target; @@ -3745,11 +4467,29 @@ altivec_expand_ternop_builtin (icode, arglist, target) enum machine_mode mode1 = insn_data[icode].operand[2].mode; enum machine_mode mode2 = insn_data[icode].operand[3].mode; + if (icode == CODE_FOR_nothing) + /* Builtin not supported on this processor. */ + return 0; + /* If we got invalid arguments bail out before generating bad rtl. */ if (arg0 == error_mark_node || arg1 == error_mark_node || arg2 == error_mark_node) - return NULL_RTX; + return const0_rtx; + + if (icode == CODE_FOR_altivec_vsldoi_4sf + || icode == CODE_FOR_altivec_vsldoi_4si + || icode == CODE_FOR_altivec_vsldoi_8hi + || icode == CODE_FOR_altivec_vsldoi_16qi) + { + /* Only allow 4-bit unsigned literals. */ + if (TREE_CODE (arg2) != INTEGER_CST + || TREE_INT_CST_LOW (arg2) & ~0xf) + { + error ("argument 3 must be a 4-bit unsigned literal"); + return const0_rtx; + } + } if (target == 0 || GET_MODE (target) != tmode @@ -3770,184 +4510,214 @@ altivec_expand_ternop_builtin (icode, arglist, target) return target; } + +/* Expand the lvx builtins. */ static rtx -altivec_expand_builtin (exp, target) +altivec_expand_ld_builtin (exp, target, expandedp) tree exp; rtx target; + bool *expandedp; { - struct builtin_description *d; - struct builtin_description_predicates *dp; - size_t i; - enum insn_code icode; tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); tree arglist = TREE_OPERAND (exp, 1); - tree arg0, arg1, arg2; - rtx op0, op1, op2, pat; - enum machine_mode tmode, mode0, mode1, mode2; unsigned int fcode = DECL_FUNCTION_CODE (fndecl); - + tree arg0; + enum machine_mode tmode, mode0; + rtx pat, op0; + enum insn_code icode; + switch (fcode) { case ALTIVEC_BUILTIN_LD_INTERNAL_16qi: icode = CODE_FOR_altivec_lvx_16qi; - arg0 = TREE_VALUE (arglist); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - tmode = insn_data[icode].operand[0].mode; - mode0 = insn_data[icode].operand[1].mode; - - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); - - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); - - pat = GEN_FCN (icode) (target, op0); - if (! pat) - return 0; - emit_insn (pat); - return target; - + break; case ALTIVEC_BUILTIN_LD_INTERNAL_8hi: icode = CODE_FOR_altivec_lvx_8hi; - arg0 = TREE_VALUE (arglist); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - tmode = insn_data[icode].operand[0].mode; - mode0 = insn_data[icode].operand[1].mode; + break; + case ALTIVEC_BUILTIN_LD_INTERNAL_4si: + icode = CODE_FOR_altivec_lvx_4si; + break; + case ALTIVEC_BUILTIN_LD_INTERNAL_4sf: + icode = CODE_FOR_altivec_lvx_4sf; + break; + default: + *expandedp = false; + return NULL_RTX; + } - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); + *expandedp = true; - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); + arg0 = TREE_VALUE (arglist); + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); + tmode = insn_data[icode].operand[0].mode; + mode0 = insn_data[icode].operand[1].mode; - pat = GEN_FCN (icode) (target, op0); - if (! pat) - return 0; - emit_insn (pat); - return target; + if (target == 0 + || GET_MODE (target) != tmode + || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) + target = gen_reg_rtx (tmode); - case ALTIVEC_BUILTIN_LD_INTERNAL_4si: - icode = CODE_FOR_altivec_lvx_4si; - arg0 = TREE_VALUE (arglist); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - tmode = insn_data[icode].operand[0].mode; - mode0 = insn_data[icode].operand[1].mode; + if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) + op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); + pat = GEN_FCN (icode) (target, op0); + if (! pat) + return 0; + emit_insn (pat); + return target; +} - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); +/* Expand the stvx builtins. */ +static rtx +altivec_expand_st_builtin (exp, target, expandedp) + tree exp; + rtx target ATTRIBUTE_UNUSED; + bool *expandedp; +{ + tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); + tree arglist = TREE_OPERAND (exp, 1); + unsigned int fcode = DECL_FUNCTION_CODE (fndecl); + tree arg0, arg1; + enum machine_mode mode0, mode1; + rtx pat, op0, op1; + enum insn_code icode; - pat = GEN_FCN (icode) (target, op0); - if (! pat) - return 0; - emit_insn (pat); - return target; + switch (fcode) + { + case ALTIVEC_BUILTIN_ST_INTERNAL_16qi: + icode = CODE_FOR_altivec_stvx_16qi; + break; + case ALTIVEC_BUILTIN_ST_INTERNAL_8hi: + icode = CODE_FOR_altivec_stvx_8hi; + break; + case ALTIVEC_BUILTIN_ST_INTERNAL_4si: + icode = CODE_FOR_altivec_stvx_4si; + break; + case ALTIVEC_BUILTIN_ST_INTERNAL_4sf: + icode = CODE_FOR_altivec_stvx_4sf; + break; + default: + *expandedp = false; + return NULL_RTX; + } - case ALTIVEC_BUILTIN_LD_INTERNAL_4sf: - icode = CODE_FOR_altivec_lvx_4sf; - arg0 = TREE_VALUE (arglist); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - tmode = insn_data[icode].operand[0].mode; - mode0 = insn_data[icode].operand[1].mode; + arg0 = TREE_VALUE (arglist); + arg1 = TREE_VALUE (TREE_CHAIN (arglist)); + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + mode0 = insn_data[icode].operand[0].mode; + mode1 = insn_data[icode].operand[1].mode; - if (target == 0 - || GET_MODE (target) != tmode - || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) - target = gen_reg_rtx (tmode); + if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) + op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); + if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) + op1 = copy_to_mode_reg (mode1, op1); - if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) - op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); + pat = GEN_FCN (icode) (op0, op1); + if (pat) + emit_insn (pat); - pat = GEN_FCN (icode) (target, op0); - if (! pat) - return 0; - emit_insn (pat); - return target; + *expandedp = true; + return NULL_RTX; +} - case ALTIVEC_BUILTIN_ST_INTERNAL_16qi: - icode = CODE_FOR_altivec_stvx_16qi; - arg0 = TREE_VALUE (arglist); - arg1 = TREE_VALUE (TREE_CHAIN (arglist)); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); - mode0 = insn_data[icode].operand[0].mode; - mode1 = insn_data[icode].operand[1].mode; +/* Expand the dst builtins. */ +static rtx +altivec_expand_dst_builtin (exp, target, expandedp) + tree exp; + rtx target ATTRIBUTE_UNUSED; + bool *expandedp; +{ + tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); + tree arglist = TREE_OPERAND (exp, 1); + unsigned int fcode = DECL_FUNCTION_CODE (fndecl); + tree arg0, arg1, arg2; + enum machine_mode mode0, mode1, mode2; + rtx pat, op0, op1, op2; + struct builtin_description *d; + size_t i; - if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) - op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); - if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); + *expandedp = false; - pat = GEN_FCN (icode) (op0, op1); - if (pat) - emit_insn (pat); - return NULL_RTX; + /* Handle DST variants. */ + d = (struct builtin_description *) bdesc_dst; + for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) + if (d->code == fcode) + { + arg0 = TREE_VALUE (arglist); + arg1 = TREE_VALUE (TREE_CHAIN (arglist)); + arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); + mode0 = insn_data[d->icode].operand[0].mode; + mode1 = insn_data[d->icode].operand[1].mode; + mode2 = insn_data[d->icode].operand[2].mode; - case ALTIVEC_BUILTIN_ST_INTERNAL_8hi: - icode = CODE_FOR_altivec_stvx_8hi; - arg0 = TREE_VALUE (arglist); - arg1 = TREE_VALUE (TREE_CHAIN (arglist)); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); - mode0 = insn_data[icode].operand[0].mode; - mode1 = insn_data[icode].operand[1].mode; + /* Invalid arguments, bail out before generating bad rtl. */ + if (arg0 == error_mark_node + || arg1 == error_mark_node + || arg2 == error_mark_node) + return const0_rtx; - if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) - op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); - if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); + if (TREE_CODE (arg2) != INTEGER_CST + || TREE_INT_CST_LOW (arg2) & ~0x3) + { + error ("argument to `%s' must be a 2-bit unsigned literal", d->name); + return const0_rtx; + } - pat = GEN_FCN (icode) (op0, op1); - if (pat) - emit_insn (pat); - return NULL_RTX; + if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0)) + op0 = copy_to_mode_reg (mode0, op0); + if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1)) + op1 = copy_to_mode_reg (mode1, op1); - case ALTIVEC_BUILTIN_ST_INTERNAL_4si: - icode = CODE_FOR_altivec_stvx_4si; - arg0 = TREE_VALUE (arglist); - arg1 = TREE_VALUE (TREE_CHAIN (arglist)); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); - mode0 = insn_data[icode].operand[0].mode; - mode1 = insn_data[icode].operand[1].mode; + pat = GEN_FCN (d->icode) (op0, op1, op2); + if (pat != 0) + emit_insn (pat); - if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) - op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); - if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); + *expandedp = true; + return NULL_RTX; + } - pat = GEN_FCN (icode) (op0, op1); - if (pat) - emit_insn (pat); - return NULL_RTX; + return NULL_RTX; +} - case ALTIVEC_BUILTIN_ST_INTERNAL_4sf: - icode = CODE_FOR_altivec_stvx_4sf; - arg0 = TREE_VALUE (arglist); - arg1 = TREE_VALUE (TREE_CHAIN (arglist)); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); - mode0 = insn_data[icode].operand[0].mode; - mode1 = insn_data[icode].operand[1].mode; +/* Expand the builtin in EXP and store the result in TARGET. Store + true in *EXPANDEDP if we found a builtin to expand. */ +static rtx +altivec_expand_builtin (exp, target, expandedp) + tree exp; + rtx target; + bool *expandedp; +{ + struct builtin_description *d; + struct builtin_description_predicates *dp; + size_t i; + enum insn_code icode; + tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); + tree arglist = TREE_OPERAND (exp, 1); + tree arg0; + rtx op0, pat; + enum machine_mode tmode, mode0; + unsigned int fcode = DECL_FUNCTION_CODE (fndecl); - if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) - op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); - if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); + target = altivec_expand_ld_builtin (exp, target, expandedp); + if (*expandedp) + return target; - pat = GEN_FCN (icode) (op0, op1); - if (pat) - emit_insn (pat); - return NULL_RTX; + target = altivec_expand_st_builtin (exp, target, expandedp); + if (*expandedp) + return target; + + target = altivec_expand_dst_builtin (exp, target, expandedp); + if (*expandedp) + return target; + + *expandedp = true; + switch (fcode) + { case ALTIVEC_BUILTIN_STVX: return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist); case ALTIVEC_BUILTIN_STVEBX: @@ -3958,7 +4728,7 @@ altivec_expand_builtin (exp, target) return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist); case ALTIVEC_BUILTIN_STVXL: return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist); - + case ALTIVEC_BUILTIN_MFVSCR: icode = CODE_FOR_altivec_mfvscr; tmode = insn_data[icode].operand[0].mode; @@ -3982,7 +4752,7 @@ altivec_expand_builtin (exp, target) /* If we got invalid arguments bail out before generating bad rtl. */ if (arg0 == error_mark_node) - return NULL_RTX; + return const0_rtx; if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) op0 = copy_to_mode_reg (mode0, op0); @@ -3991,7 +4761,7 @@ altivec_expand_builtin (exp, target) if (pat) emit_insn (pat); return NULL_RTX; - + case ALTIVEC_BUILTIN_DSSALL: emit_insn (gen_altivec_dssall ()); return NULL_RTX; @@ -4004,7 +4774,14 @@ altivec_expand_builtin (exp, target) /* If we got invalid arguments bail out before generating bad rtl. */ if (arg0 == error_mark_node) - return NULL_RTX; + return const0_rtx; + + if (TREE_CODE (arg0) != INTEGER_CST + || TREE_INT_CST_LOW (arg0) & ~0x3) + { + error ("argument to dss must be a 2-bit unsigned literal"); + return const0_rtx; + } if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) op0 = copy_to_mode_reg (mode0, op0); @@ -4013,66 +4790,15 @@ altivec_expand_builtin (exp, target) return NULL_RTX; } - /* Handle DST variants. */ - d = (struct builtin_description *) bdesc_dst; - for (i = 0; i < sizeof (bdesc_dst) / sizeof *d; i++, d++) - if (d->code == fcode) - { - arg0 = TREE_VALUE (arglist); - arg1 = TREE_VALUE (TREE_CHAIN (arglist)); - arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); - op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); - op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); - op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); - mode0 = insn_data[d->icode].operand[0].mode; - mode1 = insn_data[d->icode].operand[1].mode; - mode2 = insn_data[d->icode].operand[2].mode; - - /* Invalid arguments, bail out before generating bad rtl. */ - if (arg0 == error_mark_node - || arg1 == error_mark_node - || arg2 == error_mark_node) - return NULL_RTX; - - if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0)) - op0 = copy_to_mode_reg (mode0, op0); - if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1)) - op1 = copy_to_mode_reg (mode1, op1); - - if (GET_CODE (op2) != CONST_INT || INTVAL (op2) > 3) - { - error ("argument 3 of `%s' must be a 2-bit literal", d->name); - return NULL_RTX; - } - - pat = GEN_FCN (d->icode) (op0, op1, op2); - if (pat != 0) - emit_insn (pat); - - return NULL_RTX; - } - /* Expand abs* operations. */ d = (struct builtin_description *) bdesc_abs; - for (i = 0; i < sizeof (bdesc_abs) / sizeof *d; i++, d++) + for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) if (d->code == fcode) return altivec_expand_abs_builtin (d->icode, arglist, target); - /* Handle simple unary operations. */ - d = (struct builtin_description *) bdesc_1arg; - for (i = 0; i < sizeof (bdesc_1arg) / sizeof *d; i++, d++) - if (d->code == fcode) - return altivec_expand_unop_builtin (d->icode, arglist, target); - - /* Handle simple binary operations. */ - d = (struct builtin_description *) bdesc_2arg; - for (i = 0; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++) - if (d->code == fcode) - return altivec_expand_binop_builtin (d->icode, arglist, target); - /* Expand the AltiVec predicates. */ dp = (struct builtin_description_predicates *) bdesc_altivec_preds; - for (i = 0; i < sizeof (bdesc_altivec_preds) / sizeof *dp; i++, dp++) + for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) if (dp->code == fcode) return altivec_expand_predicate_builtin (dp->icode, dp->opcode, arglist, target); @@ -4080,41 +4806,357 @@ altivec_expand_builtin (exp, target) switch (fcode) { case ALTIVEC_BUILTIN_LVSL: - return altivec_expand_binop_builtin (CODE_FOR_altivec_lvsl, + return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvsl, arglist, target); case ALTIVEC_BUILTIN_LVSR: - return altivec_expand_binop_builtin (CODE_FOR_altivec_lvsr, - arglist, target); + return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvsr, + arglist, target); case ALTIVEC_BUILTIN_LVEBX: - return altivec_expand_binop_builtin (CODE_FOR_altivec_lvebx, - arglist, target); + return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvebx, + arglist, target); case ALTIVEC_BUILTIN_LVEHX: - return altivec_expand_binop_builtin (CODE_FOR_altivec_lvehx, - arglist, target); + return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvehx, + arglist, target); case ALTIVEC_BUILTIN_LVEWX: - return altivec_expand_binop_builtin (CODE_FOR_altivec_lvewx, - arglist, target); + return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvewx, + arglist, target); case ALTIVEC_BUILTIN_LVXL: - return altivec_expand_binop_builtin (CODE_FOR_altivec_lvxl, - arglist, target); + return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvxl, + arglist, target); case ALTIVEC_BUILTIN_LVX: - return altivec_expand_binop_builtin (CODE_FOR_altivec_lvx, - arglist, target); + return rs6000_expand_binop_builtin (CODE_FOR_altivec_lvx, + arglist, target); default: break; /* Fall through. */ } - /* Handle simple ternary operations. */ - d = (struct builtin_description *) bdesc_3arg; - for (i = 0; i < sizeof (bdesc_3arg) / sizeof *d; i++, d++) + *expandedp = false; + return NULL_RTX; +} + +/* Binops that need to be initialized manually, but can be expanded + automagically by rs6000_expand_binop_builtin. */ +static struct builtin_description bdesc_2arg_spe[] = +{ + { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX }, + { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX }, + { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX }, + { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX }, + { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX }, + { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX }, + { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX }, + { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX }, + { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX }, + { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX }, + { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX }, + { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD }, + { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW }, + { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH }, + { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE }, + { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU }, + { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS }, + { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT }, + { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT }, + { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT }, + { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT }, + { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT } +}; + +/* Expand the builtin in EXP and store the result in TARGET. Store + true in *EXPANDEDP if we found a builtin to expand. + + This expands the SPE builtins that are not simple unary and binary + operations. */ +static rtx +spe_expand_builtin (exp, target, expandedp) + tree exp; + rtx target; + bool *expandedp; +{ + tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); + tree arglist = TREE_OPERAND (exp, 1); + tree arg1, arg0; + unsigned int fcode = DECL_FUNCTION_CODE (fndecl); + enum insn_code icode; + enum machine_mode tmode, mode0; + rtx pat, op0; + struct builtin_description *d; + size_t i; + + *expandedp = true; + + /* Syntax check for a 5-bit unsigned immediate. */ + switch (fcode) + { + case SPE_BUILTIN_EVSTDD: + case SPE_BUILTIN_EVSTDH: + case SPE_BUILTIN_EVSTDW: + case SPE_BUILTIN_EVSTWHE: + case SPE_BUILTIN_EVSTWHO: + case SPE_BUILTIN_EVSTWWE: + case SPE_BUILTIN_EVSTWWO: + arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); + if (TREE_CODE (arg1) != INTEGER_CST + || TREE_INT_CST_LOW (arg1) & ~0x1f) + { + error ("argument 2 must be a 5-bit unsigned literal"); + return const0_rtx; + } + break; + default: + break; + } + + d = (struct builtin_description *) bdesc_2arg_spe; + for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d) if (d->code == fcode) - return altivec_expand_ternop_builtin (d->icode, arglist, target); + return rs6000_expand_binop_builtin (d->icode, arglist, target); - abort (); + d = (struct builtin_description *) bdesc_spe_predicates; + for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d) + if (d->code == fcode) + return spe_expand_predicate_builtin (d->icode, arglist, target); + + d = (struct builtin_description *) bdesc_spe_evsel; + for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d) + if (d->code == fcode) + return spe_expand_evsel_builtin (d->icode, arglist, target); + + switch (fcode) + { + case SPE_BUILTIN_EVSTDDX: + return altivec_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist); + case SPE_BUILTIN_EVSTDHX: + return altivec_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist); + case SPE_BUILTIN_EVSTDWX: + return altivec_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist); + case SPE_BUILTIN_EVSTWHEX: + return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist); + case SPE_BUILTIN_EVSTWHOX: + return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist); + case SPE_BUILTIN_EVSTWWEX: + return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist); + case SPE_BUILTIN_EVSTWWOX: + return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist); + case SPE_BUILTIN_EVSTDD: + return altivec_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist); + case SPE_BUILTIN_EVSTDH: + return altivec_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist); + case SPE_BUILTIN_EVSTDW: + return altivec_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist); + case SPE_BUILTIN_EVSTWHE: + return altivec_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist); + case SPE_BUILTIN_EVSTWHO: + return altivec_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist); + case SPE_BUILTIN_EVSTWWE: + return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist); + case SPE_BUILTIN_EVSTWWO: + return altivec_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist); + case SPE_BUILTIN_MFSPEFSCR: + icode = CODE_FOR_spe_mfspefscr; + tmode = insn_data[icode].operand[0].mode; + + if (target == 0 + || GET_MODE (target) != tmode + || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) + target = gen_reg_rtx (tmode); + + pat = GEN_FCN (icode) (target); + if (! pat) + return 0; + emit_insn (pat); + return target; + case SPE_BUILTIN_MTSPEFSCR: + icode = CODE_FOR_spe_mtspefscr; + arg0 = TREE_VALUE (arglist); + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); + mode0 = insn_data[icode].operand[0].mode; + + if (arg0 == error_mark_node) + return const0_rtx; + + if (! (*insn_data[icode].operand[0].predicate) (op0, mode0)) + op0 = copy_to_mode_reg (mode0, op0); + + pat = GEN_FCN (icode) (op0); + if (pat) + emit_insn (pat); + return NULL_RTX; + default: + break; + } + + *expandedp = false; return NULL_RTX; } +static rtx +spe_expand_predicate_builtin (icode, arglist, target) + enum insn_code icode; + tree arglist; + rtx target; +{ + rtx pat, scratch, tmp; + tree form = TREE_VALUE (arglist); + tree arg0 = TREE_VALUE (TREE_CHAIN (arglist)); + tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); + rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); + rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + enum machine_mode mode0 = insn_data[icode].operand[1].mode; + enum machine_mode mode1 = insn_data[icode].operand[2].mode; + int form_int; + enum rtx_code code; + + if (TREE_CODE (form) != INTEGER_CST) + { + error ("argument 1 of __builtin_spe_predicate must be a constant"); + return const0_rtx; + } + else + form_int = TREE_INT_CST_LOW (form); + + if (mode0 != mode1) + abort (); + + if (arg0 == error_mark_node || arg1 == error_mark_node) + return const0_rtx; + + if (target == 0 + || GET_MODE (target) != SImode + || ! (*insn_data[icode].operand[0].predicate) (target, SImode)) + target = gen_reg_rtx (SImode); + + if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) + op0 = copy_to_mode_reg (mode0, op0); + if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) + op1 = copy_to_mode_reg (mode1, op1); + + scratch = gen_reg_rtx (CCmode); + + pat = GEN_FCN (icode) (scratch, op0, op1); + if (! pat) + return const0_rtx; + emit_insn (pat); + + /* There are 4 variants for each predicate: _any_, _all_, _upper_, + _lower_. We use one compare, but look in different bits of the + CR for each variant. + + There are 2 elements in each SPE simd type (upper/lower). The CR + bits are set as follows: + + BIT0 | BIT 1 | BIT 2 | BIT 3 + U | L | (U | L) | (U & L) + + So, for an "all" relationship, BIT 3 would be set. + For an "any" relationship, BIT 2 would be set. Etc. + + Following traditional nomenclature, these bits map to: + + BIT0 | BIT 1 | BIT 2 | BIT 3 + LT | GT | EQ | OV + + Later, we will generate rtl to look in the LT/EQ/EQ/OV bits. + */ + + switch (form_int) + { + /* All variant. OV bit. */ + case 0: + /* We need to get to the OV bit, which is the ORDERED bit. We + could generate (ordered:SI (reg:CC xx) (const_int 0)), but + that's ugly and will trigger a validate_condition_mode abort. + So let's just use another pattern. */ + emit_insn (gen_move_from_CR_ov_bit (target, scratch)); + return target; + /* Any variant. EQ bit. */ + case 1: + code = EQ; + break; + /* Upper variant. LT bit. */ + case 2: + code = LT; + break; + /* Lower variant. GT bit. */ + case 3: + code = GT; + break; + default: + error ("argument 1 of __builtin_spe_predicate is out of range"); + return const0_rtx; + } + + tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx); + emit_move_insn (target, tmp); + + return target; +} + +/* The evsel builtins look like this: + + e = __builtin_spe_evsel_OP (a, b, c, d); + + and work like this: + + e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper]; + e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower]; +*/ + +static rtx +spe_expand_evsel_builtin (icode, arglist, target) + enum insn_code icode; + tree arglist; + rtx target; +{ + rtx pat, scratch; + tree arg0 = TREE_VALUE (arglist); + tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); + tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); + tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist)))); + rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); + rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); + rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0); + enum machine_mode mode0 = insn_data[icode].operand[1].mode; + enum machine_mode mode1 = insn_data[icode].operand[2].mode; + + if (mode0 != mode1) + abort (); + + if (arg0 == error_mark_node || arg1 == error_mark_node + || arg2 == error_mark_node || arg3 == error_mark_node) + return const0_rtx; + + if (target == 0 + || GET_MODE (target) != mode0 + || ! (*insn_data[icode].operand[0].predicate) (target, mode0)) + target = gen_reg_rtx (mode0); + + if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) + op0 = copy_to_mode_reg (mode0, op0); + if (! (*insn_data[icode].operand[1].predicate) (op1, mode1)) + op1 = copy_to_mode_reg (mode0, op1); + if (! (*insn_data[icode].operand[1].predicate) (op2, mode1)) + op2 = copy_to_mode_reg (mode0, op2); + if (! (*insn_data[icode].operand[1].predicate) (op3, mode1)) + op3 = copy_to_mode_reg (mode0, op3); + + /* Generate the compare. */ + scratch = gen_reg_rtx (CCmode); + pat = GEN_FCN (icode) (scratch, op0, op1); + if (! pat) + return const0_rtx; + emit_insn (pat); + + if (mode0 == V2SImode) + emit_insn (gen_spe_evsel (target, op2, op3, scratch)); + else + emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch)); + + return target; +} + /* Expand an expression EXP that calls a built-in function, with result going to TARGET if that's convenient (and in mode MODE if that's convenient). @@ -4129,487 +5171,695 @@ rs6000_expand_builtin (exp, target, subtarget, mode, ignore) enum machine_mode mode ATTRIBUTE_UNUSED; int ignore ATTRIBUTE_UNUSED; { + tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); + tree arglist = TREE_OPERAND (exp, 1); + unsigned int fcode = DECL_FUNCTION_CODE (fndecl); + struct builtin_description *d; + size_t i; + rtx ret; + bool success; + if (TARGET_ALTIVEC) - return altivec_expand_builtin (exp, target); + { + ret = altivec_expand_builtin (exp, target, &success); + + if (success) + return ret; + } + if (TARGET_SPE) + { + ret = spe_expand_builtin (exp, target, &success); + + if (success) + return ret; + } + + if (TARGET_ALTIVEC || TARGET_SPE) + { + /* Handle simple unary operations. */ + d = (struct builtin_description *) bdesc_1arg; + for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) + if (d->code == fcode) + return rs6000_expand_unop_builtin (d->icode, arglist, target); + + /* Handle simple binary operations. */ + d = (struct builtin_description *) bdesc_2arg; + for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) + if (d->code == fcode) + return rs6000_expand_binop_builtin (d->icode, arglist, target); + + /* Handle simple ternary operations. */ + d = (struct builtin_description *) bdesc_3arg; + for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) + if (d->code == fcode) + return rs6000_expand_ternop_builtin (d->icode, arglist, target); + } abort (); + return NULL_RTX; } static void rs6000_init_builtins () { + if (TARGET_SPE) + spe_init_builtins (); if (TARGET_ALTIVEC) altivec_init_builtins (); + if (TARGET_ALTIVEC || TARGET_SPE) + rs6000_common_init_builtins (); } +/* Search through a set of builtins and enable the mask bits. + DESC is an array of builtins. + SIZE is the totaly number of builtins. + START is the builtin enum at which to start. + END is the builtin enum at which to end. */ static void -altivec_init_builtins (void) +enable_mask_for_builtins (desc, size, start, end) + struct builtin_description *desc; + int size; + enum rs6000_builtins start, end; { - struct builtin_description *d; - struct builtin_description_predicates *dp; - size_t i; + int i; - tree endlink = void_list_node; + for (i = 0; i < size; ++i) + if (desc[i].code == start) + break; - tree pint_type_node = build_pointer_type (integer_type_node); - tree pvoid_type_node = build_pointer_type (void_type_node); - tree pshort_type_node = build_pointer_type (short_integer_type_node); - tree pchar_type_node = build_pointer_type (char_type_node); - tree pfloat_type_node = build_pointer_type (float_type_node); + if (i == size) + return; - tree v4sf_ftype_v4sf_v4sf_v16qi - = build_function_type (V4SF_type_node, - tree_cons (NULL_TREE, V4SF_type_node, - tree_cons (NULL_TREE, V4SF_type_node, - tree_cons (NULL_TREE, - V16QI_type_node, - endlink)))); - tree v4si_ftype_v4si_v4si_v16qi - = build_function_type (V4SI_type_node, - tree_cons (NULL_TREE, V4SI_type_node, - tree_cons (NULL_TREE, V4SI_type_node, - tree_cons (NULL_TREE, - V16QI_type_node, - endlink)))); - tree v8hi_ftype_v8hi_v8hi_v16qi - = build_function_type (V8HI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - tree_cons (NULL_TREE, - V16QI_type_node, - endlink)))); - tree v16qi_ftype_v16qi_v16qi_v16qi - = build_function_type (V16QI_type_node, - tree_cons (NULL_TREE, V16QI_type_node, - tree_cons (NULL_TREE, V16QI_type_node, - tree_cons (NULL_TREE, - V16QI_type_node, - endlink)))); + for (; i < size; ++i) + { + /* Flip all the bits on. */ + desc[i].mask = target_flags; + if (desc[i].code == end) + break; + } +} - /* V4SI foo (char). */ - tree v4si_ftype_char - = build_function_type (V4SI_type_node, - tree_cons (NULL_TREE, char_type_node, endlink)); +static void +spe_init_builtins () +{ + tree endlink = void_list_node; + tree puint_type_node = build_pointer_type (unsigned_type_node); + tree pushort_type_node = build_pointer_type (short_unsigned_type_node); + tree pv2si_type_node = build_pointer_type (V2SI_type_node); + struct builtin_description *d; + size_t i; - /* V8HI foo (char). */ - tree v8hi_ftype_char - = build_function_type (V8HI_type_node, - tree_cons (NULL_TREE, char_type_node, endlink)); + tree v2si_ftype_4_v2si + = build_function_type + (V2SI_type_node, + tree_cons (NULL_TREE, V2SI_type_node, + tree_cons (NULL_TREE, V2SI_type_node, + tree_cons (NULL_TREE, V2SI_type_node, + tree_cons (NULL_TREE, V2SI_type_node, + endlink))))); + + tree v2sf_ftype_4_v2sf + = build_function_type + (V2SF_type_node, + tree_cons (NULL_TREE, V2SF_type_node, + tree_cons (NULL_TREE, V2SF_type_node, + tree_cons (NULL_TREE, V2SF_type_node, + tree_cons (NULL_TREE, V2SF_type_node, + endlink))))); + + tree int_ftype_int_v2si_v2si + = build_function_type + (integer_type_node, + tree_cons (NULL_TREE, integer_type_node, + tree_cons (NULL_TREE, V2SI_type_node, + tree_cons (NULL_TREE, V2SI_type_node, + endlink)))); - /* V16QI foo (char). */ - tree v16qi_ftype_char - = build_function_type (V16QI_type_node, - tree_cons (NULL_TREE, char_type_node, endlink)); - /* V4SF foo (V4SF). */ - tree v4sf_ftype_v4sf - = build_function_type (V4SF_type_node, - tree_cons (NULL_TREE, V4SF_type_node, endlink)); - - /* V4SI foo (int *). */ - tree v4si_ftype_pint - = build_function_type (V4SI_type_node, - tree_cons (NULL_TREE, pint_type_node, endlink)); - /* V8HI foo (short *). */ - tree v8hi_ftype_pshort - = build_function_type (V8HI_type_node, - tree_cons (NULL_TREE, pshort_type_node, endlink)); - /* V16QI foo (char *). */ - tree v16qi_ftype_pchar - = build_function_type (V16QI_type_node, - tree_cons (NULL_TREE, pchar_type_node, endlink)); - /* V4SF foo (float *). */ - tree v4sf_ftype_pfloat - = build_function_type (V4SF_type_node, - tree_cons (NULL_TREE, pfloat_type_node, endlink)); - - /* V8HI foo (V16QI). */ - tree v8hi_ftype_v16qi - = build_function_type (V8HI_type_node, - tree_cons (NULL_TREE, V16QI_type_node, endlink)); + tree int_ftype_int_v2sf_v2sf + = build_function_type + (integer_type_node, + tree_cons (NULL_TREE, integer_type_node, + tree_cons (NULL_TREE, V2SF_type_node, + tree_cons (NULL_TREE, V2SF_type_node, + endlink)))); - /* void foo (void *, int, char/literal). */ - tree void_ftype_pvoid_int_char + tree void_ftype_v2si_puint_int = build_function_type (void_type_node, - tree_cons (NULL_TREE, pvoid_type_node, - tree_cons (NULL_TREE, integer_type_node, + tree_cons (NULL_TREE, V2SI_type_node, + tree_cons (NULL_TREE, puint_type_node, tree_cons (NULL_TREE, - char_type_node, + integer_type_node, endlink)))); - /* void foo (int *, V4SI). */ - tree void_ftype_pint_v4si + tree void_ftype_v2si_puint_char = build_function_type (void_type_node, - tree_cons (NULL_TREE, pint_type_node, - tree_cons (NULL_TREE, V4SI_type_node, - endlink))); - /* void foo (short *, V8HI). */ - tree void_ftype_pshort_v8hi - = build_function_type (void_type_node, - tree_cons (NULL_TREE, pshort_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - endlink))); - /* void foo (char *, V16QI). */ - tree void_ftype_pchar_v16qi - = build_function_type (void_type_node, - tree_cons (NULL_TREE, pchar_type_node, - tree_cons (NULL_TREE, V16QI_type_node, - endlink))); - /* void foo (float *, V4SF). */ - tree void_ftype_pfloat_v4sf - = build_function_type (void_type_node, - tree_cons (NULL_TREE, pfloat_type_node, - tree_cons (NULL_TREE, V4SF_type_node, - endlink))); - - /* void foo (V4SI). */ - tree void_ftype_v4si - = build_function_type (void_type_node, - tree_cons (NULL_TREE, V4SI_type_node, - endlink)); - - /* void foo (vint, int, void *). */ - tree void_ftype_v4si_int_pvoid - = build_function_type (void_type_node, - tree_cons (NULL_TREE, V4SI_type_node, - tree_cons (NULL_TREE, integer_type_node, + tree_cons (NULL_TREE, V2SI_type_node, + tree_cons (NULL_TREE, puint_type_node, tree_cons (NULL_TREE, - pvoid_type_node, + char_type_node, endlink)))); - /* void foo (vchar, int, void *). */ - tree void_ftype_v16qi_int_pvoid + tree void_ftype_v2si_pv2si_int = build_function_type (void_type_node, - tree_cons (NULL_TREE, V16QI_type_node, - tree_cons (NULL_TREE, integer_type_node, + tree_cons (NULL_TREE, V2SI_type_node, + tree_cons (NULL_TREE, pv2si_type_node, tree_cons (NULL_TREE, - pvoid_type_node, + integer_type_node, endlink)))); - /* void foo (vshort, int, void *). */ - tree void_ftype_v8hi_int_pvoid + tree void_ftype_v2si_pv2si_char = build_function_type (void_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - tree_cons (NULL_TREE, integer_type_node, + tree_cons (NULL_TREE, V2SI_type_node, + tree_cons (NULL_TREE, pv2si_type_node, tree_cons (NULL_TREE, - pvoid_type_node, + char_type_node, endlink)))); - /* void foo (char). */ - tree void_ftype_qi + tree void_ftype_int = build_function_type (void_type_node, - tree_cons (NULL_TREE, char_type_node, - endlink)); + tree_cons (NULL_TREE, integer_type_node, endlink)); - /* void foo (void). */ - tree void_ftype_void - = build_function_type (void_type_node, void_list_node); - - /* vshort foo (void). */ - tree v8hi_ftype_void - = build_function_type (V8HI_type_node, void_list_node); + tree int_ftype_void + = build_function_type (integer_type_node, + tree_cons (NULL_TREE, void_type_node, endlink)); - tree v4si_ftype_v4si_v4si - = build_function_type (V4SI_type_node, - tree_cons (NULL_TREE, V4SI_type_node, - tree_cons (NULL_TREE, V4SI_type_node, + tree v2si_ftype_pv2si_int + = build_function_type (V2SI_type_node, + tree_cons (NULL_TREE, pv2si_type_node, + tree_cons (NULL_TREE, integer_type_node, endlink))); - /* These are for the unsigned 5 bit literals. */ - - tree v4sf_ftype_v4si_char - = build_function_type (V4SF_type_node, - tree_cons (NULL_TREE, V4SI_type_node, - tree_cons (NULL_TREE, char_type_node, - endlink))); - tree v4si_ftype_v4sf_char - = build_function_type (V4SI_type_node, - tree_cons (NULL_TREE, V4SF_type_node, - tree_cons (NULL_TREE, char_type_node, - endlink))); - tree v4si_ftype_v4si_char - = build_function_type (V4SI_type_node, - tree_cons (NULL_TREE, V4SI_type_node, - tree_cons (NULL_TREE, char_type_node, - endlink))); - tree v8hi_ftype_v8hi_char - = build_function_type (V8HI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - tree_cons (NULL_TREE, char_type_node, + tree v2si_ftype_puint_int + = build_function_type (V2SI_type_node, + tree_cons (NULL_TREE, puint_type_node, + tree_cons (NULL_TREE, integer_type_node, endlink))); - tree v16qi_ftype_v16qi_char - = build_function_type (V16QI_type_node, - tree_cons (NULL_TREE, V16QI_type_node, - tree_cons (NULL_TREE, char_type_node, + + tree v2si_ftype_pushort_int + = build_function_type (V2SI_type_node, + tree_cons (NULL_TREE, pushort_type_node, + tree_cons (NULL_TREE, integer_type_node, endlink))); - /* These are for the unsigned 4 bit literals. */ + /* The initialization of the simple binary and unary builtins is + done in rs6000_common_init_builtins, but we have to enable the + mask bits here manually because we have run out of `target_flags' + bits. We really need to redesign this mask business. */ + + enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg, + ARRAY_SIZE (bdesc_2arg), + SPE_BUILTIN_EVADDW, + SPE_BUILTIN_EVXOR); + enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg, + ARRAY_SIZE (bdesc_1arg), + SPE_BUILTIN_EVABS, + SPE_BUILTIN_EVSUBFUSIAAW); + enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates, + ARRAY_SIZE (bdesc_spe_predicates), + SPE_BUILTIN_EVCMPEQ, + SPE_BUILTIN_EVFSTSTLT); + enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel, + ARRAY_SIZE (bdesc_spe_evsel), + SPE_BUILTIN_EVSEL_CMPGTS, + SPE_BUILTIN_EVSEL_FSTSTEQ); + + /* Initialize irregular SPE builtins. */ + + def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR); + def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR); + def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX); + def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX); + def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX); + def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX); + def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX); + def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX); + def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX); + def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD); + def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH); + def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW); + def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE); + def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO); + def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE); + def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO); + + /* Loads. */ + def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX); + def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX); + def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX); + def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX); + def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX); + def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX); + def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX); + def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX); + def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX); + def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX); + def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX); + def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD); + def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW); + def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH); + def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT); + def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT); + def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT); + def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE); + def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS); + def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU); + def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT); + def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT); + + /* Predicates. */ + d = (struct builtin_description *) bdesc_spe_predicates; + for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++) + { + tree type; - tree v16qi_ftype_v16qi_v16qi_char - = build_function_type (V16QI_type_node, - tree_cons (NULL_TREE, V16QI_type_node, - tree_cons (NULL_TREE, V16QI_type_node, - tree_cons (NULL_TREE, - char_type_node, - endlink)))); + switch (insn_data[d->icode].operand[1].mode) + { + case V2SImode: + type = int_ftype_int_v2si_v2si; + break; + case V2SFmode: + type = int_ftype_int_v2sf_v2sf; + break; + default: + abort (); + } - tree v8hi_ftype_v8hi_v8hi_char - = build_function_type (V8HI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - tree_cons (NULL_TREE, - char_type_node, - endlink)))); + def_builtin (d->mask, d->name, type, d->code); + } - tree v4si_ftype_v4si_v4si_char - = build_function_type (V4SI_type_node, - tree_cons (NULL_TREE, V4SI_type_node, - tree_cons (NULL_TREE, V4SI_type_node, - tree_cons (NULL_TREE, - char_type_node, - endlink)))); + /* Evsel predicates. */ + d = (struct builtin_description *) bdesc_spe_evsel; + for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++) + { + tree type; - tree v4sf_ftype_v4sf_v4sf_char - = build_function_type (V4SF_type_node, - tree_cons (NULL_TREE, V4SF_type_node, - tree_cons (NULL_TREE, V4SF_type_node, - tree_cons (NULL_TREE, - char_type_node, - endlink)))); + switch (insn_data[d->icode].operand[1].mode) + { + case V2SImode: + type = v2si_ftype_4_v2si; + break; + case V2SFmode: + type = v2sf_ftype_4_v2sf; + break; + default: + abort (); + } - /* End of 4 bit literals. */ + def_builtin (d->mask, d->name, type, d->code); + } +} - tree v4sf_ftype_v4sf_v4sf - = build_function_type (V4SF_type_node, - tree_cons (NULL_TREE, V4SF_type_node, - tree_cons (NULL_TREE, V4SF_type_node, - endlink))); - tree v4sf_ftype_v4sf_v4sf_v4si - = build_function_type (V4SF_type_node, - tree_cons (NULL_TREE, V4SF_type_node, - tree_cons (NULL_TREE, V4SF_type_node, - tree_cons (NULL_TREE, - V4SI_type_node, - endlink)))); - tree v4sf_ftype_v4sf_v4sf_v4sf - = build_function_type (V4SF_type_node, - tree_cons (NULL_TREE, V4SF_type_node, - tree_cons (NULL_TREE, V4SF_type_node, - tree_cons (NULL_TREE, - V4SF_type_node, - endlink)))); - tree v4si_ftype_v4si_v4si_v4si - = build_function_type (V4SI_type_node, - tree_cons (NULL_TREE, V4SI_type_node, - tree_cons (NULL_TREE, V4SI_type_node, - tree_cons (NULL_TREE, - V4SI_type_node, - endlink)))); +static void +altivec_init_builtins () +{ + struct builtin_description *d; + struct builtin_description_predicates *dp; + size_t i; + tree pfloat_type_node = build_pointer_type (float_type_node); + tree pint_type_node = build_pointer_type (integer_type_node); + tree pshort_type_node = build_pointer_type (short_integer_type_node); + tree pchar_type_node = build_pointer_type (char_type_node); - tree v8hi_ftype_v8hi_v8hi - = build_function_type (V8HI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - endlink))); - tree v8hi_ftype_v8hi_v8hi_v8hi - = build_function_type (V8HI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - tree_cons (NULL_TREE, - V8HI_type_node, - endlink)))); - tree v4si_ftype_v8hi_v8hi_v4si - = build_function_type (V4SI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - tree_cons (NULL_TREE, - V4SI_type_node, - endlink)))); - tree v4si_ftype_v16qi_v16qi_v4si - = build_function_type (V4SI_type_node, - tree_cons (NULL_TREE, V16QI_type_node, - tree_cons (NULL_TREE, V16QI_type_node, - tree_cons (NULL_TREE, - V4SI_type_node, - endlink)))); - - tree v16qi_ftype_v16qi_v16qi - = build_function_type (V16QI_type_node, - tree_cons (NULL_TREE, V16QI_type_node, - tree_cons (NULL_TREE, V16QI_type_node, - endlink))); - - tree v4si_ftype_v4sf_v4sf - = build_function_type (V4SI_type_node, - tree_cons (NULL_TREE, V4SF_type_node, - tree_cons (NULL_TREE, V4SF_type_node, - endlink))); + tree pvoid_type_node = build_pointer_type (void_type_node); - tree v4si_ftype_v4si - = build_function_type (V4SI_type_node, - tree_cons (NULL_TREE, V4SI_type_node, endlink)); + tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST)); + tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST)); + tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST)); + tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST)); - tree v8hi_ftype_v8hi - = build_function_type (V8HI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, endlink)); + tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST)); + + tree int_ftype_int_v4si_v4si + = build_function_type_list (integer_type_node, + integer_type_node, V4SI_type_node, + V4SI_type_node, NULL_TREE); + tree v4sf_ftype_pcfloat + = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE); + tree void_ftype_pfloat_v4sf + = build_function_type_list (void_type_node, + pfloat_type_node, V4SF_type_node, NULL_TREE); + tree v4si_ftype_pcint + = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE); + tree void_ftype_pint_v4si + = build_function_type_list (void_type_node, + pint_type_node, V4SI_type_node, NULL_TREE); + tree v8hi_ftype_pcshort + = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE); + tree void_ftype_pshort_v8hi + = build_function_type_list (void_type_node, + pshort_type_node, V8HI_type_node, NULL_TREE); + tree v16qi_ftype_pcchar + = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE); + tree void_ftype_pchar_v16qi + = build_function_type_list (void_type_node, + pchar_type_node, V16QI_type_node, NULL_TREE); + tree void_ftype_v4si + = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE); + tree v8hi_ftype_void + = build_function_type (V8HI_type_node, void_list_node); + tree void_ftype_void + = build_function_type (void_type_node, void_list_node); + tree void_ftype_qi + = build_function_type_list (void_type_node, char_type_node, NULL_TREE); + + tree v16qi_ftype_int_pcvoid + = build_function_type_list (V16QI_type_node, + integer_type_node, pcvoid_type_node, NULL_TREE); + tree v8hi_ftype_int_pcvoid + = build_function_type_list (V8HI_type_node, + integer_type_node, pcvoid_type_node, NULL_TREE); + tree v4si_ftype_int_pcvoid + = build_function_type_list (V4SI_type_node, + integer_type_node, pcvoid_type_node, NULL_TREE); + tree void_ftype_v4si_int_pvoid + = build_function_type_list (void_type_node, + V4SI_type_node, integer_type_node, + pvoid_type_node, NULL_TREE); + tree void_ftype_v16qi_int_pvoid + = build_function_type_list (void_type_node, + V16QI_type_node, integer_type_node, + pvoid_type_node, NULL_TREE); + tree void_ftype_v8hi_int_pvoid + = build_function_type_list (void_type_node, + V8HI_type_node, integer_type_node, + pvoid_type_node, NULL_TREE); + tree int_ftype_int_v8hi_v8hi + = build_function_type_list (integer_type_node, + integer_type_node, V8HI_type_node, + V8HI_type_node, NULL_TREE); + tree int_ftype_int_v16qi_v16qi + = build_function_type_list (integer_type_node, + integer_type_node, V16QI_type_node, + V16QI_type_node, NULL_TREE); + tree int_ftype_int_v4sf_v4sf + = build_function_type_list (integer_type_node, + integer_type_node, V4SF_type_node, + V4SF_type_node, NULL_TREE); + tree v4si_ftype_v4si + = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE); + tree v8hi_ftype_v8hi + = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE); tree v16qi_ftype_v16qi - = build_function_type (V16QI_type_node, - tree_cons (NULL_TREE, V16QI_type_node, endlink)); + = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE); + tree v4sf_ftype_v4sf + = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); + tree void_ftype_pcvoid_int_char + = build_function_type_list (void_type_node, + pcvoid_type_node, integer_type_node, + char_type_node, NULL_TREE); + + def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat, + ALTIVEC_BUILTIN_LD_INTERNAL_4sf); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf, + ALTIVEC_BUILTIN_ST_INTERNAL_4sf); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint, + ALTIVEC_BUILTIN_LD_INTERNAL_4si); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si, + ALTIVEC_BUILTIN_ST_INTERNAL_4si); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort, + ALTIVEC_BUILTIN_LD_INTERNAL_8hi); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi, + ALTIVEC_BUILTIN_ST_INTERNAL_8hi); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar, + ALTIVEC_BUILTIN_LD_INTERNAL_16qi); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, + ALTIVEC_BUILTIN_ST_INTERNAL_16qi); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_qi, ALTIVEC_BUILTIN_DSS); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVSL); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVSR); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVEBX); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVEHX); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVEWX); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVXL); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_int_pcvoid, ALTIVEC_BUILTIN_LVX); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVX); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVEWX); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVXL); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_int_pvoid, ALTIVEC_BUILTIN_STVEBX); + def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_int_pvoid, ALTIVEC_BUILTIN_STVEHX); - tree v8hi_ftype_v16qi_v16qi - = build_function_type (V8HI_type_node, - tree_cons (NULL_TREE, V16QI_type_node, - tree_cons (NULL_TREE, V16QI_type_node, - endlink))); + /* Add the DST variants. */ + d = (struct builtin_description *) bdesc_dst; + for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++) + def_builtin (d->mask, d->name, void_ftype_pcvoid_int_char, d->code); - tree v4si_ftype_v8hi_v8hi - = build_function_type (V4SI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - endlink))); + /* Initialize the predicates. */ + dp = (struct builtin_description_predicates *) bdesc_altivec_preds; + for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++) + { + enum machine_mode mode1; + tree type; - tree v8hi_ftype_v4si_v4si - = build_function_type (V8HI_type_node, - tree_cons (NULL_TREE, V4SI_type_node, - tree_cons (NULL_TREE, V4SI_type_node, - endlink))); + mode1 = insn_data[dp->icode].operand[1].mode; - tree v16qi_ftype_v8hi_v8hi - = build_function_type (V16QI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - endlink))); + switch (mode1) + { + case V4SImode: + type = int_ftype_int_v4si_v4si; + break; + case V8HImode: + type = int_ftype_int_v8hi_v8hi; + break; + case V16QImode: + type = int_ftype_int_v16qi_v16qi; + break; + case V4SFmode: + type = int_ftype_int_v4sf_v4sf; + break; + default: + abort (); + } + + def_builtin (dp->mask, dp->name, type, dp->code); + } - tree v4si_ftype_v16qi_v4si - = build_function_type (V4SI_type_node, - tree_cons (NULL_TREE, V16QI_type_node, - tree_cons (NULL_TREE, V4SI_type_node, - endlink))); + /* Initialize the abs* operators. */ + d = (struct builtin_description *) bdesc_abs; + for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++) + { + enum machine_mode mode0; + tree type; - tree v4si_ftype_v16qi_v16qi - = build_function_type (V4SI_type_node, - tree_cons (NULL_TREE, V16QI_type_node, - tree_cons (NULL_TREE, V16QI_type_node, - endlink))); + mode0 = insn_data[d->icode].operand[0].mode; - tree v4si_ftype_v8hi_v4si - = build_function_type (V4SI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - tree_cons (NULL_TREE, V4SI_type_node, - endlink))); + switch (mode0) + { + case V4SImode: + type = v4si_ftype_v4si; + break; + case V8HImode: + type = v8hi_ftype_v8hi; + break; + case V16QImode: + type = v16qi_ftype_v16qi; + break; + case V4SFmode: + type = v4sf_ftype_v4sf; + break; + default: + abort (); + } + + def_builtin (d->mask, d->name, type, d->code); + } +} - tree v4si_ftype_v8hi - = build_function_type (V4SI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, endlink)); +static void +rs6000_common_init_builtins () +{ + struct builtin_description *d; + size_t i; - tree int_ftype_v4si_v4si - = build_function_type (integer_type_node, - tree_cons (NULL_TREE, V4SI_type_node, - tree_cons (NULL_TREE, V4SI_type_node, - endlink))); + tree v4sf_ftype_v4sf_v4sf_v16qi + = build_function_type_list (V4SF_type_node, + V4SF_type_node, V4SF_type_node, + V16QI_type_node, NULL_TREE); + tree v4si_ftype_v4si_v4si_v16qi + = build_function_type_list (V4SI_type_node, + V4SI_type_node, V4SI_type_node, + V16QI_type_node, NULL_TREE); + tree v8hi_ftype_v8hi_v8hi_v16qi + = build_function_type_list (V8HI_type_node, + V8HI_type_node, V8HI_type_node, + V16QI_type_node, NULL_TREE); + tree v16qi_ftype_v16qi_v16qi_v16qi + = build_function_type_list (V16QI_type_node, + V16QI_type_node, V16QI_type_node, + V16QI_type_node, NULL_TREE); + tree v4si_ftype_char + = build_function_type_list (V4SI_type_node, char_type_node, NULL_TREE); + tree v8hi_ftype_char + = build_function_type_list (V8HI_type_node, char_type_node, NULL_TREE); + tree v16qi_ftype_char + = build_function_type_list (V16QI_type_node, char_type_node, NULL_TREE); + tree v8hi_ftype_v16qi + = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE); + tree v4sf_ftype_v4sf + = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE); - tree int_ftype_v4sf_v4sf - = build_function_type (integer_type_node, - tree_cons (NULL_TREE, V4SF_type_node, - tree_cons (NULL_TREE, V4SF_type_node, - endlink))); + tree v2si_ftype_v2si_v2si + = build_function_type_list (V2SI_type_node, + V2SI_type_node, V2SI_type_node, NULL_TREE); - tree int_ftype_v16qi_v16qi - = build_function_type (integer_type_node, - tree_cons (NULL_TREE, V16QI_type_node, - tree_cons (NULL_TREE, V16QI_type_node, - endlink))); + tree v2sf_ftype_v2sf_v2sf + = build_function_type_list (V2SF_type_node, + V2SF_type_node, V2SF_type_node, NULL_TREE); - tree int_ftype_int_v4si_v4si - = build_function_type - (integer_type_node, - tree_cons (NULL_TREE, integer_type_node, - tree_cons (NULL_TREE, V4SI_type_node, - tree_cons (NULL_TREE, V4SI_type_node, - endlink)))); + tree v2si_ftype_int_int + = build_function_type_list (V2SI_type_node, + integer_type_node, integer_type_node, + NULL_TREE); - tree int_ftype_int_v4sf_v4sf - = build_function_type - (integer_type_node, - tree_cons (NULL_TREE, integer_type_node, - tree_cons (NULL_TREE, V4SF_type_node, - tree_cons (NULL_TREE, V4SF_type_node, - endlink)))); + tree v2si_ftype_v2si + = build_function_type_list (V2SI_type_node, V2SI_type_node, NULL_TREE); - tree int_ftype_int_v8hi_v8hi - = build_function_type - (integer_type_node, - tree_cons (NULL_TREE, integer_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - endlink)))); + tree v2sf_ftype_v2sf + = build_function_type_list (V2SF_type_node, + V2SF_type_node, NULL_TREE); + + tree v2sf_ftype_v2si + = build_function_type_list (V2SF_type_node, + V2SI_type_node, NULL_TREE); - tree int_ftype_int_v16qi_v16qi - = build_function_type - (integer_type_node, - tree_cons (NULL_TREE, integer_type_node, - tree_cons (NULL_TREE, V16QI_type_node, - tree_cons (NULL_TREE, V16QI_type_node, - endlink)))); + tree v2si_ftype_v2sf + = build_function_type_list (V2SI_type_node, + V2SF_type_node, NULL_TREE); - tree v16qi_ftype_int_pvoid - = build_function_type (V16QI_type_node, - tree_cons (NULL_TREE, integer_type_node, - tree_cons (NULL_TREE, pvoid_type_node, - endlink))); + tree v2si_ftype_v2si_char + = build_function_type_list (V2SI_type_node, + V2SI_type_node, char_type_node, NULL_TREE); - tree v4si_ftype_int_pvoid - = build_function_type (V4SI_type_node, - tree_cons (NULL_TREE, integer_type_node, - tree_cons (NULL_TREE, pvoid_type_node, - endlink))); + tree v2si_ftype_int_char + = build_function_type_list (V2SI_type_node, + integer_type_node, char_type_node, NULL_TREE); - tree v8hi_ftype_int_pvoid - = build_function_type (V8HI_type_node, - tree_cons (NULL_TREE, integer_type_node, - tree_cons (NULL_TREE, pvoid_type_node, - endlink))); + tree v2si_ftype_char + = build_function_type_list (V2SI_type_node, char_type_node, NULL_TREE); - tree int_ftype_v8hi_v8hi - = build_function_type (integer_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - tree_cons (NULL_TREE, V8HI_type_node, - endlink))); + tree int_ftype_int_int + = build_function_type_list (integer_type_node, + integer_type_node, integer_type_node, + NULL_TREE); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pfloat, ALTIVEC_BUILTIN_LD_INTERNAL_4sf); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf, ALTIVEC_BUILTIN_ST_INTERNAL_4sf); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pint, ALTIVEC_BUILTIN_LD_INTERNAL_4si); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si, ALTIVEC_BUILTIN_ST_INTERNAL_4si); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pshort, ALTIVEC_BUILTIN_LD_INTERNAL_8hi); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi, ALTIVEC_BUILTIN_ST_INTERNAL_8hi); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pchar, ALTIVEC_BUILTIN_LD_INTERNAL_16qi); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi, ALTIVEC_BUILTIN_ST_INTERNAL_16qi); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_qi, ALTIVEC_BUILTIN_DSS); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_int_pvoid, ALTIVEC_BUILTIN_LVSL); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_int_pvoid, ALTIVEC_BUILTIN_LVSR); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_int_pvoid, ALTIVEC_BUILTIN_LVEBX); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_int_pvoid, ALTIVEC_BUILTIN_LVEHX); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_int_pvoid, ALTIVEC_BUILTIN_LVEWX); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_int_pvoid, ALTIVEC_BUILTIN_LVXL); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_int_pvoid, ALTIVEC_BUILTIN_LVX); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVX); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_int_pvoid, ALTIVEC_BUILTIN_STVEBX); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_int_pvoid, ALTIVEC_BUILTIN_STVEHX); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVEWX); - def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_int_pvoid, ALTIVEC_BUILTIN_STVXL); + tree v4si_ftype_v4si_v4si + = build_function_type_list (V4SI_type_node, + V4SI_type_node, V4SI_type_node, NULL_TREE); + tree v4sf_ftype_v4si_char + = build_function_type_list (V4SF_type_node, + V4SI_type_node, char_type_node, NULL_TREE); + tree v4si_ftype_v4sf_char + = build_function_type_list (V4SI_type_node, + V4SF_type_node, char_type_node, NULL_TREE); + tree v4si_ftype_v4si_char + = build_function_type_list (V4SI_type_node, + V4SI_type_node, char_type_node, NULL_TREE); + tree v8hi_ftype_v8hi_char + = build_function_type_list (V8HI_type_node, + V8HI_type_node, char_type_node, NULL_TREE); + tree v16qi_ftype_v16qi_char + = build_function_type_list (V16QI_type_node, + V16QI_type_node, char_type_node, NULL_TREE); + tree v16qi_ftype_v16qi_v16qi_char + = build_function_type_list (V16QI_type_node, + V16QI_type_node, V16QI_type_node, + char_type_node, NULL_TREE); + tree v8hi_ftype_v8hi_v8hi_char + = build_function_type_list (V8HI_type_node, + V8HI_type_node, V8HI_type_node, + char_type_node, NULL_TREE); + tree v4si_ftype_v4si_v4si_char + = build_function_type_list (V4SI_type_node, + V4SI_type_node, V4SI_type_node, + char_type_node, NULL_TREE); + tree v4sf_ftype_v4sf_v4sf_char + = build_function_type_list (V4SF_type_node, + V4SF_type_node, V4SF_type_node, + char_type_node, NULL_TREE); + tree v4sf_ftype_v4sf_v4sf + = build_function_type_list (V4SF_type_node, + V4SF_type_node, V4SF_type_node, NULL_TREE); + tree v4sf_ftype_v4sf_v4sf_v4si + = build_function_type_list (V4SF_type_node, + V4SF_type_node, V4SF_type_node, + V4SI_type_node, NULL_TREE); + tree v4sf_ftype_v4sf_v4sf_v4sf + = build_function_type_list (V4SF_type_node, + V4SF_type_node, V4SF_type_node, + V4SF_type_node, NULL_TREE); + tree v4si_ftype_v4si_v4si_v4si + = build_function_type_list (V4SI_type_node, + V4SI_type_node, V4SI_type_node, + V4SI_type_node, NULL_TREE); + tree v8hi_ftype_v8hi_v8hi + = build_function_type_list (V8HI_type_node, + V8HI_type_node, V8HI_type_node, NULL_TREE); + tree v8hi_ftype_v8hi_v8hi_v8hi + = build_function_type_list (V8HI_type_node, + V8HI_type_node, V8HI_type_node, + V8HI_type_node, NULL_TREE); + tree v4si_ftype_v8hi_v8hi_v4si + = build_function_type_list (V4SI_type_node, + V8HI_type_node, V8HI_type_node, + V4SI_type_node, NULL_TREE); + tree v4si_ftype_v16qi_v16qi_v4si + = build_function_type_list (V4SI_type_node, + V16QI_type_node, V16QI_type_node, + V4SI_type_node, NULL_TREE); + tree v16qi_ftype_v16qi_v16qi + = build_function_type_list (V16QI_type_node, + V16QI_type_node, V16QI_type_node, NULL_TREE); + tree v4si_ftype_v4sf_v4sf + = build_function_type_list (V4SI_type_node, + V4SF_type_node, V4SF_type_node, NULL_TREE); + tree v8hi_ftype_v16qi_v16qi + = build_function_type_list (V8HI_type_node, + V16QI_type_node, V16QI_type_node, NULL_TREE); + tree v4si_ftype_v8hi_v8hi + = build_function_type_list (V4SI_type_node, + V8HI_type_node, V8HI_type_node, NULL_TREE); + tree v8hi_ftype_v4si_v4si + = build_function_type_list (V8HI_type_node, + V4SI_type_node, V4SI_type_node, NULL_TREE); + tree v16qi_ftype_v8hi_v8hi + = build_function_type_list (V16QI_type_node, + V8HI_type_node, V8HI_type_node, NULL_TREE); + tree v4si_ftype_v16qi_v4si + = build_function_type_list (V4SI_type_node, + V16QI_type_node, V4SI_type_node, NULL_TREE); + tree v4si_ftype_v16qi_v16qi + = build_function_type_list (V4SI_type_node, + V16QI_type_node, V16QI_type_node, NULL_TREE); + tree v4si_ftype_v8hi_v4si + = build_function_type_list (V4SI_type_node, + V8HI_type_node, V4SI_type_node, NULL_TREE); + tree v4si_ftype_v8hi + = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE); + tree int_ftype_v4si_v4si + = build_function_type_list (integer_type_node, + V4SI_type_node, V4SI_type_node, NULL_TREE); + tree int_ftype_v4sf_v4sf + = build_function_type_list (integer_type_node, + V4SF_type_node, V4SF_type_node, NULL_TREE); + tree int_ftype_v16qi_v16qi + = build_function_type_list (integer_type_node, + V16QI_type_node, V16QI_type_node, NULL_TREE); + tree int_ftype_v8hi_v8hi + = build_function_type_list (integer_type_node, + V8HI_type_node, V8HI_type_node, NULL_TREE); /* Add the simple ternary operators. */ d = (struct builtin_description *) bdesc_3arg; - for (i = 0; i < sizeof (bdesc_3arg) / sizeof *d; i++, d++) + for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++) { enum machine_mode mode0, mode1, mode2, mode3; tree type; - if (d->name == 0) + if (d->name == 0 || d->icode == CODE_FOR_nothing) continue; mode0 = insn_data[d->icode].operand[0].mode; @@ -4694,49 +5944,14 @@ altivec_init_builtins (void) def_builtin (d->mask, d->name, type, d->code); } - /* Add the DST variants. */ - d = (struct builtin_description *) bdesc_dst; - for (i = 0; i < sizeof (bdesc_dst) / sizeof *d; i++, d++) - def_builtin (d->mask, d->name, void_ftype_pvoid_int_char, d->code); - - /* Initialize the predicates. */ - dp = (struct builtin_description_predicates *) bdesc_altivec_preds; - for (i = 0; i < sizeof (bdesc_altivec_preds) / sizeof *dp; i++, dp++) - { - enum machine_mode mode1; - tree type; - - mode1 = insn_data[dp->icode].operand[1].mode; - - switch (mode1) - { - case V4SImode: - type = int_ftype_int_v4si_v4si; - break; - case V8HImode: - type = int_ftype_int_v8hi_v8hi; - break; - case V16QImode: - type = int_ftype_int_v16qi_v16qi; - break; - case V4SFmode: - type = int_ftype_int_v4sf_v4sf; - break; - default: - abort (); - } - - def_builtin (dp->mask, dp->name, type, dp->code); - } - /* Add the simple binary operators. */ d = (struct builtin_description *) bdesc_2arg; - for (i = 0; i < sizeof (bdesc_2arg) / sizeof *d; i++, d++) + for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++) { enum machine_mode mode0, mode1, mode2; tree type; - if (d->name == 0) + if (d->name == 0 || d->icode == CODE_FOR_nothing) continue; mode0 = insn_data[d->icode].operand[0].mode; @@ -4760,6 +5975,15 @@ altivec_init_builtins (void) case V8HImode: type = v8hi_ftype_v8hi_v8hi; break; + case V2SImode: + type = v2si_ftype_v2si_v2si; + break; + case V2SFmode: + type = v2sf_ftype_v2sf_v2sf; + break; + case SImode: + type = int_ftype_int_int; + break; default: abort (); } @@ -4819,6 +6043,15 @@ altivec_init_builtins (void) else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode) type = v4si_ftype_v4sf_char; + else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode) + type = v2si_ftype_int_int; + + else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode) + type = v2si_ftype_v2si_char; + + else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode) + type = v2si_ftype_int_char; + /* int, x, x. */ else if (mode0 == SImode) { @@ -4847,44 +6080,14 @@ altivec_init_builtins (void) def_builtin (d->mask, d->name, type, d->code); } - /* Initialize the abs* operators. */ - d = (struct builtin_description *) bdesc_abs; - for (i = 0; i < sizeof (bdesc_abs) / sizeof *d; i++, d++) - { - enum machine_mode mode0; - tree type; - - mode0 = insn_data[d->icode].operand[0].mode; - - switch (mode0) - { - case V4SImode: - type = v4si_ftype_v4si; - break; - case V8HImode: - type = v8hi_ftype_v8hi; - break; - case V16QImode: - type = v16qi_ftype_v16qi; - break; - case V4SFmode: - type = v4sf_ftype_v4sf; - break; - default: - abort (); - } - - def_builtin (d->mask, d->name, type, d->code); - } - /* Add the simple unary operators. */ d = (struct builtin_description *) bdesc_1arg; - for (i = 0; i < sizeof (bdesc_1arg) / sizeof *d; i++, d++) + for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++) { enum machine_mode mode0, mode1; tree type; - if (d->name == 0) + if (d->name == 0 || d->icode == CODE_FOR_nothing) continue; mode0 = insn_data[d->icode].operand[0].mode; @@ -4902,6 +6105,16 @@ altivec_init_builtins (void) type = v8hi_ftype_v16qi; else if (mode0 == V4SImode && mode1 == V8HImode) type = v4si_ftype_v8hi; + else if (mode0 == V2SImode && mode1 == V2SImode) + type = v2si_ftype_v2si; + else if (mode0 == V2SFmode && mode1 == V2SFmode) + type = v2sf_ftype_v2sf; + else if (mode0 == V2SFmode && mode1 == V2SImode) + type = v2sf_ftype_v2si; + else if (mode0 == V2SImode && mode1 == V2SFmode) + type = v2si_ftype_v2sf; + else if (mode0 == V2SImode && mode1 == QImode) + type = v2si_ftype_char; else abort (); @@ -5550,9 +6763,10 @@ validate_condition_mode (code, mode) abort (); /* These should never be generated except for - flag_unsafe_math_optimizations. */ + flag_unsafe_math_optimizations and flag_finite_math_only. */ if (mode == CCFPmode && ! flag_unsafe_math_optimizations + && ! flag_finite_math_only && (code == LE || code == GE || code == UNEQ || code == LTGT || code == UNGT || code == UNLT)) @@ -5603,6 +6817,7 @@ branch_positive_comparison_operator (op, mode) code = GET_CODE (op); return (code == EQ || code == LT || code == GT + || (TARGET_SPE && TARGET_HARD_FLOAT && !TARGET_FPRS && code == NE) || code == LTU || code == GTU || code == UNORDERED); } @@ -6054,8 +7269,12 @@ ccr_bit (op, scc_p) switch (code) { case NE: + if (TARGET_SPE && TARGET_HARD_FLOAT && cc_mode == CCFPmode) + return base_bit + 1; return scc_p ? base_bit + 3 : base_bit + 2; case EQ: + if (TARGET_SPE && TARGET_HARD_FLOAT && cc_mode == CCFPmode) + return base_bit + 1; return base_bit + 2; case GT: case GTU: case UNLE: return base_bit + 1; @@ -6095,29 +7314,93 @@ rs6000_got_register (value) return pic_offset_table_rtx; } -/* Functions to init, mark and free struct machine_function. - These will be called, via pointer variables, - from push_function_context and pop_function_context. */ +/* Function to init struct machine_function. + This will be called, via a pointer variable, + from push_function_context. */ -static void -rs6000_init_machine_status (p) - struct function *p; +static struct machine_function * +rs6000_init_machine_status () { - p->machine = (machine_function *) xcalloc (1, sizeof (machine_function)); + return ggc_alloc_cleared (sizeof (machine_function)); } + +/* These macros test for integers and extract the low-order bits. */ +#define INT_P(X) \ +((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ + && GET_MODE (X) == VOIDmode) -static void -rs6000_free_machine_status (p) - struct function *p; +#define INT_LOWPART(X) \ + (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) + +int +extract_MB (op) + rtx op; { - if (p->machine == NULL) - return; + int i; + unsigned long val = INT_LOWPART (op); + + /* If the high bit is zero, the value is the first 1 bit we find + from the left. */ + if ((val & 0x80000000) == 0) + { + if ((val & 0xffffffff) == 0) + abort (); - free (p->machine); - p->machine = NULL; + i = 1; + while (((val <<= 1) & 0x80000000) == 0) + ++i; + return i; + } + + /* If the high bit is set and the low bit is not, or the mask is all + 1's, the value is zero. */ + if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff) + return 0; + + /* Otherwise we have a wrap-around mask. Look for the first 0 bit + from the right. */ + i = 31; + while (((val >>= 1) & 1) != 0) + --i; + + return i; +} + +int +extract_ME (op) + rtx op; +{ + int i; + unsigned long val = INT_LOWPART (op); + + /* If the low bit is zero, the value is the first 1 bit we find from + the right. */ + if ((val & 1) == 0) + { + if ((val & 0xffffffff) == 0) + abort (); + + i = 30; + while (((val >>= 1) & 1) == 0) + --i; + + return i; + } + + /* If the low bit is set and the high bit is not, or the mask is all + 1's, the value is 31. */ + if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff) + return 31; + + /* Otherwise we have a wrap-around mask. Look for the first 0 bit + from the left. */ + i = 0; + while (((val <<= 1) & 0x80000000) != 0) + ++i; + + return i; } - /* Print an operand. Recognize special options, documented below. */ #if TARGET_ELF @@ -6136,14 +7419,7 @@ print_operand (file, x, code) { int i; HOST_WIDE_INT val; - - /* These macros test for integers and extract the low-order bits. */ -#define INT_P(X) \ -((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \ - && GET_MODE (X) == VOIDmode) - -#define INT_LOWPART(X) \ - (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X)) + unsigned HOST_WIDE_INT uval; switch (code) { @@ -6209,6 +7485,15 @@ print_operand (file, x, code) fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 3, base_bit + 2, base_bit + 2); } + else if (TARGET_SPE && TARGET_HARD_FLOAT + && GET_CODE (x) == EQ + && GET_MODE (XEXP (x, 0)) == CCFPmode) + { + int base_bit = 4 * (REGNO (XEXP (x, 0)) - CR0_REGNO); + + fprintf (file, "crnor %d,%d,%d\n\t", base_bit + 1, + base_bit + 1, base_bit + 1); + } return; case 'E': @@ -6239,7 +7524,7 @@ print_operand (file, x, code) case 'G': /* X is a constant integer. If it is negative, print "m", - otherwise print "z". This is to make a aze or ame insn. */ + otherwise print "z". This is to make an aze or ame insn. */ if (GET_CODE (x) != CONST_INT) output_operand_lossage ("invalid %%G value"); else if (INTVAL (x) >= 0) @@ -6319,6 +7604,11 @@ print_operand (file, x, code) output_operand_lossage ("invalid %%K value"); print_operand_address (file, XEXP (XEXP (x, 0), 0)); fputs ("@l", file); + /* For GNU as, there must be a non-alphanumeric character + between 'l' and the number. The '-' is added by + print_operand() already. */ + if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0) + fputs ("+", file); print_operand (file, XEXP (XEXP (x, 0), 1), 0); } return; @@ -6354,34 +7644,7 @@ print_operand (file, x, code) if (! mask_operand (x, SImode)) output_operand_lossage ("invalid %%m value"); - val = INT_LOWPART (x); - - /* If the high bit is set and the low bit is not, the value is zero. - If the high bit is zero, the value is the first 1 bit we find from - the left. */ - if ((val & 0x80000000) && ((val & 1) == 0)) - { - putc ('0', file); - return; - } - else if ((val & 0x80000000) == 0) - { - for (i = 1; i < 32; i++) - if ((val <<= 1) & 0x80000000) - break; - fprintf (file, "%d", i); - return; - } - - /* Otherwise, look for the first 0 bit from the right. The result is its - number plus 1. We know the low-order bit is one. */ - for (i = 0; i < 32; i++) - if (((val >>= 1) & 1) == 0) - break; - - /* If we ended in ...01, i would be 0. The correct value is 31, so - we want 31 - i. */ - fprintf (file, "%d", 31 - i); + fprintf (file, "%d", extract_MB (x)); return; case 'M': @@ -6389,35 +7652,7 @@ print_operand (file, x, code) if (! mask_operand (x, SImode)) output_operand_lossage ("invalid %%M value"); - val = INT_LOWPART (x); - - /* If the low bit is set and the high bit is not, the value is 31. - If the low bit is zero, the value is the first 1 bit we find from - the right. */ - if ((val & 1) && ((val & 0x80000000) == 0)) - { - fputs ("31", file); - return; - } - else if ((val & 1) == 0) - { - for (i = 0; i < 32; i++) - if ((val >>= 1) & 1) - break; - - /* If we had ....10, i would be 0. The result should be - 30, so we need 30 - i. */ - fprintf (file, "%d", 30 - i); - return; - } - - /* Otherwise, look for the first 0 bit from the left. The result is its - number minus 1. We know the high-order bit is one. */ - for (i = 0; i < 32; i++) - if (((val <<= 1) & 0x80000000) == 0) - break; - - fprintf (file, "%d", i); + fprintf (file, "%d", extract_ME (x)); return; /* %n outputs the negative of its operand. */ @@ -6513,68 +7748,43 @@ print_operand (file, x, code) return; case 'S': - /* PowerPC64 mask position. All 0's and all 1's are excluded. + /* PowerPC64 mask position. All 0's is excluded. CONST_INT 32-bit mask is considered sign-extended so any transition must occur within the CONST_INT, not on the boundary. */ if (! mask64_operand (x, DImode)) output_operand_lossage ("invalid %%S value"); - val = INT_LOWPART (x); + uval = INT_LOWPART (x); - if (val & 1) /* Clear Left */ + if (uval & 1) /* Clear Left */ { - for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) - if (!((val >>= 1) & 1)) - break; - -#if HOST_BITS_PER_WIDE_INT == 32 - if (GET_CODE (x) == CONST_DOUBLE && i == 32) - { - val = CONST_DOUBLE_HIGH (x); - - if (val == 0) - --i; - else - for (i = 32; i < 64; i++) - if (!((val >>= 1) & 1)) - break; - } -#endif - /* i = index of last set bit from right - mask begins at 63 - i from left */ - if (i > 63) - output_operand_lossage ("%%S computed all 1's mask"); - - fprintf (file, "%d", 63 - i); - return; + uval &= ((unsigned HOST_WIDE_INT) 1 << 63 << 1) - 1; + i = 64; } - else /* Clear Right */ + else /* Clear Right */ { - for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++) - if ((val >>= 1) & 1) - break; + uval = ~uval; + uval &= ((unsigned HOST_WIDE_INT) 1 << 63 << 1) - 1; + i = 63; + } + while (uval != 0) + --i, uval >>= 1; + if (i < 0) + abort (); + fprintf (file, "%d", i); + return; -#if HOST_BITS_PER_WIDE_INT == 32 - if (GET_CODE (x) == CONST_DOUBLE && i == 32) - { - val = CONST_DOUBLE_HIGH (x); + case 't': + /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */ + if (GET_CODE (x) != REG || GET_MODE (x) != CCmode) + abort (); - if (val == (HOST_WIDE_INT) -1) - --i; - else - for (i = 32; i < 64; i++) - if ((val >>= 1) & 1) - break; - } -#endif - /* i = index of last clear bit from right - mask ends at 62 - i from left */ - if (i > 62) - output_operand_lossage ("%%S computed all 0's mask"); + /* Bit 3 is OV bit. */ + i = 4 * (REGNO (x) - CR0_REGNO) + 3; - fprintf (file, "%d", 62 - i); - return; - } + /* If we want bit 31, write a shift count of zero, not 32. */ + fprintf (file, "%d", i == 31 ? 0 : i + 1); + return; case 'T': /* Print the symbolic name of a branch target register. */ @@ -6768,7 +7978,7 @@ print_operand (file, x, code) } return; - /* Print AltiVec memory operand. */ + /* Print AltiVec or SPE memory operand. */ case 'y': { rtx tmp; @@ -6778,6 +7988,30 @@ print_operand (file, x, code) tmp = XEXP (x, 0); + if (TARGET_SPE) + { + /* Handle [reg]. */ + if (GET_CODE (tmp) == REG) + { + fprintf (file, "0(%s)", reg_names[REGNO (tmp)]); + break; + } + /* Handle [reg+UIMM]. */ + else if (GET_CODE (tmp) == PLUS && + GET_CODE (XEXP (tmp, 1)) == CONST_INT) + { + int x; + + if (GET_CODE (XEXP (tmp, 0)) != REG) + abort (); + + x = INTVAL (XEXP (tmp, 1)); + fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]); + break; + } + + /* Fall through. Must be [reg+reg]. */ + } if (GET_CODE (tmp) == REG) fprintf (file, "0,%s", reg_names[REGNO (tmp)]); else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG) @@ -6909,7 +8143,7 @@ print_operand_address (file, x) abort (); } -/* Target hook for assembling integer objects. The powerpc version has +/* Target hook for assembling integer objects. The PowerPC version has to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP is defined. It also needs to handle DI-mode objects on 64-bit targets. */ @@ -6972,6 +8206,37 @@ rs6000_assemble_integer (x, size, aligned_p) #endif /* RELOCATABLE_NEEDS_FIXUP */ return default_assemble_integer (x, size, aligned_p); } + +#ifdef HAVE_GAS_HIDDEN +/* Emit an assembler directive to set symbol visibility for DECL to + VISIBILITY_TYPE. */ + +static void +rs6000_assemble_visibility (decl, vis) + tree decl; + int vis; +{ + /* Functions need to have their entry point symbol visibility set as + well as their descriptor symbol visibility. */ + if (DEFAULT_ABI == ABI_AIX && TREE_CODE (decl) == FUNCTION_DECL) + { + static const char * const visibility_types[] = { + NULL, "internal", "hidden", "protected" + }; + + const char *name, *type; + + name = ((* targetm.strip_name_encoding) + (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)))); + type = visibility_types[vis]; + + fprintf (asm_out_file, "\t.%s\t%s\n", type, name); + fprintf (asm_out_file, "\t.%s\t.%s\n", type, name); + } + else + default_assemble_visibility (decl, vis); +} +#endif enum rtx_code rs6000_reverse_condition (mode, code) @@ -7006,15 +8271,134 @@ rs6000_generate_compare (code) /* First, the compare. */ compare_result = gen_reg_rtx (comp_mode); - emit_insn (gen_rtx_SET (VOIDmode, compare_result, - gen_rtx_COMPARE (comp_mode, - rs6000_compare_op0, - rs6000_compare_op1))); + + /* SPE FP compare instructions on the GPRs. Yuck! */ + if ((TARGET_SPE && TARGET_HARD_FLOAT) && rs6000_compare_fp_p) + { + rtx cmp, or1, or2, or_result, compare_result2; + + switch (code) + { + case EQ: + case UNEQ: + case NE: + case LTGT: + cmp = flag_unsafe_math_optimizations + ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0, + rs6000_compare_op1) + : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0, + rs6000_compare_op1); + break; + case GT: + case GTU: + case UNGT: + case UNGE: + case GE: + case GEU: + cmp = flag_unsafe_math_optimizations + ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0, + rs6000_compare_op1) + : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0, + rs6000_compare_op1); + break; + case LT: + case LTU: + case UNLT: + case UNLE: + case LE: + case LEU: + cmp = flag_unsafe_math_optimizations + ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0, + rs6000_compare_op1) + : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0, + rs6000_compare_op1); + break; + default: + abort (); + } + + /* Synthesize LE and GE from LT/GT || EQ. */ + if (code == LE || code == GE || code == LEU || code == GEU) + { + /* Synthesize GE/LE frome GT/LT || EQ. */ + + emit_insn (cmp); + + switch (code) + { + case LE: code = LT; break; + case GE: code = GT; break; + case LEU: code = LT; break; + case GEU: code = GT; break; + default: abort (); + } + + or1 = gen_reg_rtx (SImode); + or2 = gen_reg_rtx (SImode); + or_result = gen_reg_rtx (CCEQmode); + compare_result2 = gen_reg_rtx (CCFPmode); + + /* Do the EQ. */ + cmp = flag_unsafe_math_optimizations + ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0, + rs6000_compare_op1) + : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0, + rs6000_compare_op1); + emit_insn (cmp); + + /* The MC8540 FP compare instructions set the CR bits + differently than other PPC compare instructions. For + that matter, there is no generic test instruction, but a + testgt, testlt, and testeq. For a true condition, bit 2 + is set (x1xx) in the CR. Following the traditional CR + values: + + LT GT EQ OV + bit3 bit2 bit1 bit0 + + ... bit 2 would be a GT CR alias, so later on we + look in the GT bits for the branch instructins. + However, we must be careful to emit correct RTL in + the meantime, so optimizations don't get confused. */ + + or1 = gen_rtx (NE, SImode, compare_result, const0_rtx); + or2 = gen_rtx (NE, SImode, compare_result2, const0_rtx); + + /* OR them together. */ + cmp = gen_rtx_SET (VOIDmode, or_result, + gen_rtx_COMPARE (CCEQmode, + gen_rtx_IOR (SImode, or1, or2), + const_true_rtx)); + compare_result = or_result; + code = EQ; + } + else + { + /* We only care about 1 bit (x1xx), so map everything to NE to + maintain rtl sanity. We'll get to the right bit (x1xx) at + code output time. */ + if (code == NE || code == LTGT) + /* Do the inverse here because we have no cmpne + instruction. We use the cmpeq instruction and expect + to get a 0 instead. */ + code = EQ; + else + code = NE; + } + + emit_insn (cmp); + } + else + emit_insn (gen_rtx_SET (VOIDmode, compare_result, + gen_rtx_COMPARE (comp_mode, + rs6000_compare_op0, + rs6000_compare_op1))); /* Some kinds of FP comparisons need an OR operation; except for flag_unsafe_math_optimizations we don't bother. */ if (rs6000_compare_fp_p && ! flag_unsafe_math_optimizations + && ! (TARGET_HARD_FLOAT && TARGET_SPE) && (code == LE || code == GE || code == UNEQ || code == LTGT || code == UNGT || code == UNLT)) @@ -7104,7 +8488,7 @@ rs6000_emit_cbranch (code, loc) condition code register and its mode specifies what kind of comparison we made. - REVERSED is non-zero if we should reverse the sense of the comparison. + REVERSED is nonzero if we should reverse the sense of the comparison. INSN is the insn. */ @@ -7142,6 +8526,19 @@ output_cbranch (op, label, reversed, insn) code = reverse_condition (code); } + if ((TARGET_SPE && TARGET_HARD_FLOAT) && mode == CCFPmode) + { + /* The efscmp/tst* instructions twiddle bit 2, which maps nicely + to the GT bit. */ + if (code == EQ) + /* Opposite of GT. */ + code = UNLE; + else if (code == NE) + code = GT; + else + abort (); + } + switch (code) { /* Not all of these are actually distinct opcodes, but @@ -7168,21 +8565,30 @@ output_cbranch (op, label, reversed, insn) /* Maybe we have a guess as to how likely the branch is. The old mnemonics don't have a way to specify this information. */ + pred = ""; note = find_reg_note (insn, REG_BR_PROB, NULL_RTX); if (note != NULL_RTX) { /* PROB is the difference from 50%. */ int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2; - - /* For branches that are very close to 50%, assume not-taken. */ - if (abs (prob) > REG_BR_PROB_BASE / 20 - && ((prob > 0) ^ need_longbranch)) - pred = "+"; - else - pred = "-"; + bool always_hint = rs6000_cpu != PROCESSOR_POWER4; + + /* Only hint for highly probable/improbable branches on newer + cpus as static prediction overrides processor dynamic + prediction. For older cpus we may as well always hint, but + assume not taken for branches that are very close to 50% as a + mispredicted taken branch is more expensive than a + mispredicted not-taken branch. */ + if (always_hint + || abs (prob) > REG_BR_PROB_BASE / 100 * 48) + { + if (abs (prob) > REG_BR_PROB_BASE / 20 + && ((prob > 0) ^ need_longbranch)) + pred = "+"; + else + pred = "-"; + } } - else - pred = ""; if (label == NULL) s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred); @@ -7228,7 +8634,10 @@ rs6000_emit_cmove (dest, op, true_cond, false_cond) rtx temp; /* These modes should always match. */ - if (GET_MODE (op1) != compare_mode) + if (GET_MODE (op1) != compare_mode + /* In the isel case however, we can use a compare immediate, so + op1 may be a small constant. */ + && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode))) return 0; if (GET_MODE (true_cond) != result_mode) return 0; @@ -7237,10 +8646,12 @@ rs6000_emit_cmove (dest, op, true_cond, false_cond) /* First, work out if the hardware can do this at all, or if it's too slow... */ - /* If the comparison is an integer one, since we only have fsel - it'll be cheaper to use a branch. */ if (! rs6000_compare_fp_p) - return 0; + { + if (TARGET_ISEL) + return rs6000_emit_int_cmove (dest, op, true_cond, false_cond); + return 0; + } /* Eliminate half of the comparisons by switching operands, this makes the remaining code simpler. */ @@ -7264,11 +8675,11 @@ rs6000_emit_cmove (dest, op, true_cond, false_cond) /* We're going to try to implement comparions by performing a subtract, then comparing against zero. Unfortunately, Inf - Inf is NaN which is not zero, and so if we don't - know that the the operand is finite and the comparison + know that the operand is finite and the comparison would treat EQ different to UNORDERED, we can't do it. */ if (! flag_unsafe_math_optimizations && code != GT && code != UNGE - && (GET_CODE (op1) != CONST_DOUBLE || target_isinf (c1)) + && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1)) /* Constructs of the form (a OP b ? a : b) are safe. */ && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond)) || (! rtx_equal_p (op0, true_cond) @@ -7372,6 +8783,53 @@ rs6000_emit_cmove (dest, op, true_cond, false_cond) return 1; } +/* Same as above, but for ints (isel). */ + +static int +rs6000_emit_int_cmove (dest, op, true_cond, false_cond) + rtx dest; + rtx op; + rtx true_cond; + rtx false_cond; +{ + rtx condition_rtx, cr; + + /* All isel implementations thus far are 32-bits. */ + if (GET_MODE (rs6000_compare_op0) != SImode) + return 0; + + /* We still have to do the compare, because isel doesn't do a + compare, it just looks at the CRx bits set by a previous compare + instruction. */ + condition_rtx = rs6000_generate_compare (GET_CODE (op)); + cr = XEXP (condition_rtx, 0); + + if (GET_MODE (cr) == CCmode) + emit_insn (gen_isel_signed (dest, condition_rtx, + true_cond, false_cond, cr)); + else + emit_insn (gen_isel_unsigned (dest, condition_rtx, + true_cond, false_cond, cr)); + + return 1; +} + +const char * +output_isel (operands) + rtx *operands; +{ + enum rtx_code code; + + code = GET_CODE (operands[1]); + if (code == GE || code == GEU || code == LE || code == LEU || code == NE) + { + PUT_CODE (operands[1], reverse_condition (code)); + return "isel %0,%3,%2,%j1"; + } + else + return "isel %0,%2,%3,%j1"; +} + void rs6000_emit_minmax (dest, code, op0, op1) rtx dest; @@ -7380,12 +8838,19 @@ rs6000_emit_minmax (dest, code, op0, op1) rtx op1; { enum machine_mode mode = GET_MODE (op0); + enum rtx_code c; rtx target; + + if (code == SMAX || code == SMIN) + c = GE; + else + c = GEU; + if (code == SMAX || code == UMAX) - target = emit_conditional_move (dest, GE, op0, op1, mode, + target = emit_conditional_move (dest, c, op0, op1, mode, op0, op1, mode, 0); else - target = emit_conditional_move (dest, GE, op0, op1, mode, + target = emit_conditional_move (dest, c, op0, op1, mode, op1, op0, mode, 0); if (target == NULL_RTX) abort (); @@ -7409,13 +8874,14 @@ first_reg_to_save () if (regs_ever_live[first_reg] && (! call_used_regs[first_reg] || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM - && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1) + && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))) break; #if TARGET_MACHO - if (flag_pic && current_function_uses_pic_offset_table && - (first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)) + if (flag_pic + && current_function_uses_pic_offset_table + && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM) return RS6000_PIC_OFFSET_TABLE_REGNUM; #endif @@ -7583,6 +9049,10 @@ is_altivec_return_reg (reg, xyes) +---------------------------------------+ | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y +---------------------------------------+ + | SPE: area for 64-bit GP registers | + +---------------------------------------+ + | SPE alignment padding | + +---------------------------------------+ | saved CR (C) | 8+P+A+V+L+X+W+Y+Z +---------------------------------------+ | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C @@ -7638,6 +9108,20 @@ rs6000_stack_info () else info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save); + /* For the SPE, we have an additional upper 32-bits on each GPR. + Ideally we should save the entire 64-bits only when the upper + half is used in SIMD instructions. Since we only record + registers live (not the size they are used in), this proves + difficult because we'd have to traverse the instruction chain at + the right time, taking reload into account. This is a real pain, + so we opt to save the GPRs in 64-bits always. Anyone overly + concerned with frame size can fix this. ;-). + + So... since we save all GPRs (except the SP) in 64-bits, the + traditional GP save area will be empty. */ + if (TARGET_SPE_ABI) + info_ptr->gp_size = 0; + info_ptr->first_fp_reg_save = first_fp_reg_to_save (); info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save); @@ -7686,7 +9170,9 @@ rs6000_stack_info () unsigned int i; for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i) continue; - ehrd_size = i * UNITS_PER_WORD; + + /* SPE saves EH registers in 64-bits. */ + ehrd_size = i * (TARGET_SPE_ABI ? UNITS_PER_SPE_WORD : UNITS_PER_WORD); } else ehrd_size = 0; @@ -7699,7 +9185,12 @@ rs6000_stack_info () info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size, 8); - if (TARGET_ALTIVEC_ABI) + if (TARGET_SPE_ABI) + info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save); + else + info_ptr->spe_gp_size = 0; + + if (TARGET_ALTIVEC_ABI && TARGET_ALTIVEC_VRSAVE) { info_ptr->vrsave_mask = compute_vrsave_mask (); info_ptr->vrsave_size = info_ptr->vrsave_mask ? 4 : 0; @@ -7754,7 +9245,26 @@ rs6000_stack_info () info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size; info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size; - if (TARGET_ALTIVEC_ABI) + if (TARGET_SPE_ABI) + { + /* Align stack so SPE GPR save area is aligned on a + double-word boundary. */ + if (info_ptr->spe_gp_size != 0) + info_ptr->spe_padding_size + = 8 - (-info_ptr->cr_save_offset % 8); + else + info_ptr->spe_padding_size = 0; + + info_ptr->spe_gp_save_offset + = info_ptr->cr_save_offset + - info_ptr->spe_padding_size + - info_ptr->spe_gp_size; + + /* Adjust for SPE case. */ + info_ptr->toc_save_offset + = info_ptr->spe_gp_save_offset - info_ptr->toc_size; + } + else if (TARGET_ALTIVEC_ABI) { info_ptr->vrsave_save_offset = info_ptr->cr_save_offset - info_ptr->vrsave_size; @@ -7787,10 +9297,11 @@ rs6000_stack_info () + info_ptr->altivec_size + info_ptr->altivec_padding_size + info_ptr->vrsave_size + + info_ptr->spe_gp_size + + info_ptr->spe_padding_size + ehrd_size + info_ptr->cr_size + info_ptr->lr_size - + info_ptr->vrsave_size + info_ptr->toc_size, (TARGET_ALTIVEC_ABI || ABI_DARWIN) ? 16 : 8); @@ -7841,6 +9352,9 @@ rs6000_stack_info () if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0) info_ptr->vrsave_save_offset = 0; + if (! TARGET_SPE_ABI || info_ptr->spe_gp_size == 0) + info_ptr->spe_gp_save_offset = 0; + if (! info_ptr->lr_save_p) info_ptr->lr_save_offset = 0; @@ -7882,6 +9396,9 @@ debug_stack_info (info) if (TARGET_ALTIVEC_ABI) fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n"); + if (TARGET_SPE_ABI) + fprintf (stderr, "\tSPE ABI extensions enabled.\n"); + if (info->first_gp_reg_save != 32) fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save); @@ -7920,6 +9437,10 @@ debug_stack_info (info) fprintf (stderr, "\taltivec_save_offset = %5d\n", info->altivec_save_offset); + if (info->spe_gp_save_offset) + fprintf (stderr, "\tspe_gp_save_offset = %5d\n", + info->spe_gp_save_offset); + if (info->vrsave_save_offset) fprintf (stderr, "\tvrsave_save_offset = %5d\n", info->vrsave_save_offset); @@ -7954,6 +9475,9 @@ debug_stack_info (info) if (info->gp_size) fprintf (stderr, "\tgp_size = %5d\n", info->gp_size); + if (info->spe_gp_size) + fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size); + if (info->fp_size) fprintf (stderr, "\tfp_size = %5d\n", info->fp_size); @@ -7967,6 +9491,10 @@ debug_stack_info (info) fprintf (stderr, "\taltivec_padding_size= %5d\n", info->altivec_padding_size); + if (info->spe_padding_size) + fprintf (stderr, "\tspe_padding_size = %5d\n", + info->spe_padding_size); + if (info->lr_size) fprintf (stderr, "\tlr_size = %5d\n", info->lr_size); @@ -7993,10 +9521,7 @@ rs6000_return_addr (count, frame) /* Currently we don't optimize very well between prolog and body code and for PIC code the code can be actually quite bad, so don't try to be too clever here. */ - if (count != 0 - || flag_pic != 0 - || DEFAULT_ABI == ABI_AIX - || DEFAULT_ABI == ABI_AIX_NODESC) + if (count != 0 || flag_pic != 0) { cfun->machine->ra_needs_full_frame = 1; @@ -8014,25 +9539,92 @@ rs6000_return_addr (count, frame) return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM); } +/* Say whether a function is a candidate for sibcall handling or not. + We do not allow indirect calls to be optimized into sibling calls. + Also, we can't do it if there are any vector parameters; there's + nowhere to put the VRsave code so it works; note that functions with + vector parameters are required to have a prototype, so the argument + type info must be available here. (The tail recursion case can work + with vector parameters, but there's no way to distinguish here.) */ +int +function_ok_for_sibcall (fndecl) + tree fndecl; +{ + tree type; + if (fndecl) + { + if (TARGET_ALTIVEC_VRSAVE) + { + for (type = TYPE_ARG_TYPES (TREE_TYPE (fndecl)); + type; type = TREE_CHAIN (type)) + { + if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE) + return 0; + } + } + if (DEFAULT_ABI == ABI_DARWIN + || (*targetm.binds_local_p) (fndecl)) + { + tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (fndecl)); + + if (!lookup_attribute ("longcall", attr_list) + || lookup_attribute ("shortcall", attr_list)) + return 1; + } + } + return 0; +} + static int rs6000_ra_ever_killed () { rtx top; + rtx reg; + rtx insn; -#ifdef ASM_OUTPUT_MI_THUNK - if (current_function_is_thunk) + /* Irritatingly, there are two kinds of thunks -- those created with + TARGET_ASM_OUTPUT_MI_THUNK and those with DECL_THUNK_P that go + through the regular part of the compiler. This is a very hacky + way to tell them apart. */ + if (current_function_is_thunk && !no_new_pseudos) return 0; -#endif - if (!has_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM) - || cfun->machine->ra_needs_full_frame) - return regs_ever_live[LINK_REGISTER_REGNUM]; + /* regs_ever_live has LR marked as used if any sibcalls are present, + but this should not force saving and restoring in the + pro/epilogue. Likewise, reg_set_between_p thinks a sibcall + clobbers LR, so that is inappropriate. */ + + /* Also, the prologue can generate a store into LR that + doesn't really count, like this: + + move LR->R0 + bcl to set PIC register + move LR->R31 + move R0->LR + + When we're called from the epilogue, we need to avoid counting + this as a store. */ + push_topmost_sequence (); top = get_insns (); pop_topmost_sequence (); + reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); - return reg_set_between_p (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), - top, NULL_RTX); + for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn)) + { + if (INSN_P (insn)) + { + if (FIND_REG_INC_NOTE (insn, reg)) + return 1; + else if (GET_CODE (insn) == CALL_INSN + && !SIBLING_CALL_P (insn)) + return 1; + else if (set_of (reg, insn) != NULL_RTX + && !prologue_epilogue_contains (insn)) + return 1; + } + } + return 0; } /* Add a REG_MAYBE_DEAD note to the insn. */ @@ -8053,7 +9645,7 @@ void rs6000_emit_load_toc_table (fromprolog) int fromprolog; { - rtx dest; + rtx dest, insn; dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1) @@ -8061,8 +9653,12 @@ rs6000_emit_load_toc_table (fromprolog) rtx temp = (fromprolog ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM) : gen_reg_rtx (Pmode)); - rs6000_maybe_dead (emit_insn (gen_load_toc_v4_pic_si (temp))); - rs6000_maybe_dead (emit_move_insn (dest, temp)); + insn = emit_insn (gen_load_toc_v4_pic_si (temp)); + if (fromprolog) + rs6000_maybe_dead (insn); + insn = emit_move_insn (dest, temp); + if (fromprolog) + rs6000_maybe_dead (insn); } else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2) { @@ -8109,14 +9705,13 @@ rs6000_emit_load_toc_table (fromprolog) ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++); symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); - rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1b (tempLR, - symF, - tocsym))); - rs6000_maybe_dead (emit_move_insn (dest, tempLR)); - rs6000_maybe_dead (emit_move_insn (temp0, - gen_rtx_MEM (Pmode, dest))); + emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym)); + emit_move_insn (dest, tempLR); + emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest)); } - rs6000_maybe_dead (emit_insn (gen_addsi3 (dest, temp0, dest))); + insn = emit_insn (gen_addsi3 (dest, temp0, dest)); + if (fromprolog) + rs6000_maybe_dead (insn); } else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC) { @@ -8126,15 +9721,21 @@ rs6000_emit_load_toc_table (fromprolog) ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1); realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); - rs6000_maybe_dead (emit_insn (gen_elf_high (dest, realsym))); - rs6000_maybe_dead (emit_insn (gen_elf_low (dest, dest, realsym))); + insn = emit_insn (gen_elf_high (dest, realsym)); + if (fromprolog) + rs6000_maybe_dead (insn); + insn = emit_insn (gen_elf_low (dest, dest, realsym)); + if (fromprolog) + rs6000_maybe_dead (insn); } else if (DEFAULT_ABI == ABI_AIX) { if (TARGET_32BIT) - rs6000_maybe_dead (emit_insn (gen_load_toc_aix_si (dest))); + insn = emit_insn (gen_load_toc_aix_si (dest)); else - rs6000_maybe_dead (emit_insn (gen_load_toc_aix_di (dest))); + insn = emit_insn (gen_load_toc_aix_di (dest)); + if (fromprolog) + rs6000_maybe_dead (insn); } else abort (); @@ -8273,10 +9874,8 @@ rs6000_emit_eh_toc_restore (stacksize) bottom_of_stack, stacksize, NULL_RTX, 1, OPTAB_WIDEN); - emit_move_insn (tocompare, - GEN_INT (trunc_int_for_mode (TARGET_32BIT - ? 0x80410014 - : 0xE8410028, SImode))); + emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014 + : 0xE8410028, SImode)); if (insn_after_throw == NULL_RTX) abort (); @@ -8460,8 +10059,19 @@ rs6000_frame_related (insn, reg, val, reg2, rreg) { rtx real, temp; + /* copy_rtx will not make unique copies of registers, so we need to + ensure we don't have unwanted sharing here. */ + if (reg == reg2) + reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); + + if (reg == rreg) + reg = gen_raw_REG (GET_MODE (reg), REGNO (reg)); + real = copy_rtx (PATTERN (insn)); + if (reg2 != NULL_RTX) + real = replace_rtx (real, reg2, rreg); + real = replace_rtx (real, reg, gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM), @@ -8514,9 +10124,6 @@ rs6000_frame_related (insn, reg, val, reg2, rreg) else abort (); - if (reg2 != NULL_RTX) - real = replace_rtx (real, reg2, rreg); - RTX_FRAME_RELATED_P (insn) = 1; REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, real, @@ -8585,6 +10192,78 @@ generate_set_vrsave (reg, info, epiloguep) return insn; } +/* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes. + Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */ + +static void +emit_frame_save (frame_reg, frame_ptr, mode, regno, offset, total_size) + rtx frame_reg; + rtx frame_ptr; + enum machine_mode mode; + unsigned int regno; + int offset; + int total_size; +{ + rtx reg, offset_rtx, insn, mem, addr, int_rtx; + rtx replacea, replaceb; + + int_rtx = GEN_INT (offset); + + /* Some cases that need register indexed addressing. */ + if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode)) + || (TARGET_SPE_ABI + && SPE_VECTOR_MODE (mode) + && !SPE_CONST_OFFSET_OK (offset))) + { + /* Whomever calls us must make sure r11 is available in the + flow path of instructions in the prologue. */ + offset_rtx = gen_rtx_REG (Pmode, 11); + emit_move_insn (offset_rtx, int_rtx); + + replacea = offset_rtx; + replaceb = int_rtx; + } + else + { + offset_rtx = int_rtx; + replacea = NULL_RTX; + replaceb = NULL_RTX; + } + + reg = gen_rtx_REG (mode, regno); + addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx); + mem = gen_rtx_MEM (mode, addr); + set_mem_alias_set (mem, rs6000_sr_alias_set); + + insn = emit_move_insn (mem, reg); + + rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb); +} + +/* Emit an offset memory reference suitable for a frame store, while + converting to a valid addressing mode. */ + +static rtx +gen_frame_mem_offset (mode, reg, offset) + enum machine_mode mode; + rtx reg; + int offset; +{ + rtx int_rtx, offset_rtx; + + int_rtx = GEN_INT (offset); + + if (TARGET_SPE_ABI && SPE_VECTOR_MODE (mode)) + { + offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH); + emit_move_insn (offset_rtx, int_rtx); + } + else + offset_rtx = int_rtx; + + return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx)); +} + /* Emit function prologue as insns. */ void @@ -8602,7 +10281,14 @@ rs6000_emit_prologue () int using_store_multiple; HOST_WIDE_INT sp_offset = 0; + if (TARGET_SPE_ABI) + { + reg_mode = V2SImode; + reg_size = 8; + } + using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 + && !TARGET_SPE_ABI && info->first_gp_reg_save < 31); saving_FPRs_inline = (info->first_fp_reg_save == 64 || FP_SAVE_INLINE (info->first_fp_reg_save)); @@ -8712,20 +10398,10 @@ rs6000_emit_prologue () for (i = 0; i < 64 - info->first_fp_reg_save; i++) if ((regs_ever_live[info->first_fp_reg_save+i] && ! call_used_regs[info->first_fp_reg_save+i])) - { - rtx addr, reg, mem; - reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i); - addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, - GEN_INT (info->fp_save_offset - + sp_offset - + 8 * i)); - mem = gen_rtx_MEM (DFmode, addr); - set_mem_alias_set (mem, rs6000_sr_alias_set); - - insn = emit_move_insn (mem, reg); - rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, - NULL_RTX, NULL_RTX); - } + emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode, + info->first_fp_reg_save + i, + info->fp_save_offset + sp_offset + 8 * i, + info->total_size); } else if (info->first_fp_reg_save != 64) { @@ -8765,10 +10441,9 @@ rs6000_emit_prologue () the store-multiple instructions. */ if (using_store_multiple) { - rtvec p, dwarfp; + rtvec p; int i; p = rtvec_alloc (32 - info->first_gp_reg_save); - dwarfp = rtvec_alloc (32 - info->first_gp_reg_save); for (i = 0; i < 32 - info->first_gp_reg_save; i++) { rtx addr, reg, mem; @@ -8793,21 +10468,50 @@ rs6000_emit_prologue () if ((regs_ever_live[info->first_gp_reg_save+i] && ! call_used_regs[info->first_gp_reg_save+i]) || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM - && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1) + && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) { rtx addr, reg, mem; reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i); - addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, - GEN_INT (info->gp_save_offset - + sp_offset - + reg_size * i)); - mem = gen_rtx_MEM (reg_mode, addr); - set_mem_alias_set (mem, rs6000_sr_alias_set); - insn = emit_move_insn (mem, reg); - rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, - NULL_RTX, NULL_RTX); + if (TARGET_SPE_ABI) + { + int offset = info->spe_gp_save_offset + sp_offset + 8 * i; + rtx b; + + if (!SPE_CONST_OFFSET_OK (offset)) + { + b = gen_rtx_REG (Pmode, FIXED_SCRATCH); + emit_move_insn (b, GEN_INT (offset)); + } + else + b = GEN_INT (offset); + + addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); + mem = gen_rtx_MEM (V2SImode, addr); + set_mem_alias_set (mem, rs6000_sr_alias_set); + insn = emit_move_insn (mem, reg); + + if (GET_CODE (b) == CONST_INT) + rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, + NULL_RTX, NULL_RTX); + else + rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, + b, GEN_INT (offset)); + } + else + { + addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, + GEN_INT (info->gp_save_offset + + sp_offset + + reg_size * i)); + mem = gen_rtx_MEM (reg_mode, addr); + set_mem_alias_set (mem, rs6000_sr_alias_set); + + insn = emit_move_insn (mem, reg); + rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, + NULL_RTX, NULL_RTX); + } } } @@ -8819,22 +10523,14 @@ rs6000_emit_prologue () for (i = 0; ; ++i) { - rtx addr, reg, mem; - regno = EH_RETURN_DATA_REGNO (i); if (regno == INVALID_REGNUM) break; - reg = gen_rtx_REG (reg_mode, regno); - addr = plus_constant (frame_reg_rtx, - info->ehrd_offset + sp_offset - + reg_size * (int) i); - mem = gen_rtx_MEM (reg_mode, addr); - set_mem_alias_set (mem, rs6000_sr_alias_set); - - insn = emit_move_insn (mem, reg); - rs6000_frame_related (insn, frame_ptr_rtx, info->total_size, - NULL_RTX, NULL_RTX); + emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno, + info->ehrd_offset + sp_offset + + reg_size * (int) i, + info->total_size); } } @@ -8889,7 +10585,7 @@ rs6000_emit_prologue () /* Set frame pointer, if needed. */ if (frame_pointer_needed) { - insn = emit_move_insn (gen_rtx_REG (reg_mode, FRAME_POINTER_REGNUM), + insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM), sp_reg_rtx); RTX_FRAME_RELATED_P (insn) = 1; } @@ -8917,17 +10613,21 @@ rs6000_emit_prologue () gen_rtx_REG (Pmode, 11)); } +#if TARGET_MACHO if (DEFAULT_ABI == ABI_DARWIN && flag_pic && current_function_uses_pic_offset_table) { rtx dest = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM); + char *picbase = machopic_function_base_name (); + rtx src = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1)); - rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest))); + rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (dest, src))); rs6000_maybe_dead ( emit_move_insn (gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM), gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM))); } +#endif } /* Write function prologue. */ @@ -9016,8 +10716,15 @@ rs6000_emit_epilogue (sibcall) int reg_size = TARGET_POWERPC64 ? 8 : 4; int i; + if (TARGET_SPE_ABI) + { + reg_mode = V2SImode; + reg_size = 8; + } + info = rs6000_stack_info (); using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64 + && !TARGET_SPE_ABI && info->first_gp_reg_save < 31); restoring_FPRs_inline = (sibcall || current_function_calls_eh_return @@ -9102,9 +10809,8 @@ rs6000_emit_epilogue (sibcall) /* Get the old lr if we saved it. */ if (info->lr_save_p) { - rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, - GEN_INT (info->lr_save_offset + sp_offset)); - rtx mem = gen_rtx_MEM (Pmode, addr); + rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx, + info->lr_save_offset + sp_offset); set_mem_alias_set (mem, rs6000_sr_alias_set); @@ -9135,16 +10841,15 @@ rs6000_emit_epilogue (sibcall) for (i = 0; ; ++i) { - rtx addr, mem; + rtx mem; regno = EH_RETURN_DATA_REGNO (i); if (regno == INVALID_REGNUM) break; - addr = plus_constant (frame_reg_rtx, - info->ehrd_offset + sp_offset - + reg_size * (int) i); - mem = gen_rtx_MEM (reg_mode, addr); + mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx, + info->ehrd_offset + sp_offset + + reg_size * (int) i); set_mem_alias_set (mem, rs6000_sr_alias_set); emit_move_insn (gen_rtx_REG (reg_mode, regno), mem); @@ -9179,7 +10884,7 @@ rs6000_emit_epilogue (sibcall) if ((regs_ever_live[info->first_gp_reg_save+i] && ! call_used_regs[info->first_gp_reg_save+i]) || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM - && ((DEFAULT_ABI == ABI_V4 && flag_pic == 1) + && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0) || (DEFAULT_ABI == ABI_DARWIN && flag_pic)))) { rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, @@ -9188,11 +10893,28 @@ rs6000_emit_epilogue (sibcall) + reg_size * i)); rtx mem = gen_rtx_MEM (reg_mode, addr); + /* Restore 64-bit quantities for SPE. */ + if (TARGET_SPE_ABI) + { + int offset = info->spe_gp_save_offset + sp_offset + 8 * i; + rtx b; + + if (!SPE_CONST_OFFSET_OK (offset)) + { + b = gen_rtx_REG (Pmode, FIXED_SCRATCH); + emit_move_insn (b, GEN_INT (offset)); + } + else + b = GEN_INT (offset); + + addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b); + mem = gen_rtx_MEM (V2SImode, addr); + } + set_mem_alias_set (mem, rs6000_sr_alias_set); emit_move_insn (gen_rtx_REG (reg_mode, - info->first_gp_reg_save + i), - mem); + info->first_gp_reg_save + i), mem); } /* Restore fpr's if we need to do it without calling a function. */ @@ -9350,7 +11072,6 @@ rs6000_output_function_epilogue (file, size) HOST_WIDE_INT size ATTRIBUTE_UNUSED; { rs6000_stack_t *info = rs6000_stack_info (); - int optional_tbtab = (optimize_size || TARGET_ELF) ? 0 : 1; if (! HAVE_epilogue) { @@ -9403,22 +11124,33 @@ rs6000_output_function_epilogue (file, size) System V.4 Powerpc's (and the embedded ABI derived from it) use a different traceback table. */ - if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive) + if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive + && rs6000_traceback != traceback_none) { - const char *fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); + const char *fname = NULL; const char *language_string = lang_hooks.name; int fixed_parms = 0, float_parms = 0, parm_info = 0; int i; + int optional_tbtab; - while (*fname == '.') /* V.4 encodes . in the name */ - fname++; + if (rs6000_traceback == traceback_full) + optional_tbtab = 1; + else if (rs6000_traceback == traceback_part) + optional_tbtab = 0; + else + optional_tbtab = !optimize_size && !TARGET_ELF; - /* Need label immediately before tbtab, so we can compute its offset - from the function start. */ - if (*fname == '*') - ++fname; - ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); - ASM_OUTPUT_LABEL (file, fname); + if (optional_tbtab) + { + fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); + while (*fname == '.') /* V.4 encodes . in the name */ + fname++; + + /* Need label immediately before tbtab, so we can compute + its offset from the function start. */ + ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT"); + ASM_OUTPUT_LABEL (file, fname); + } /* The .tbtab pseudo-op can only be used for the first eight expressions, since it can't handle the possibly variable @@ -9513,7 +11245,7 @@ rs6000_output_function_epilogue (file, size) if (mode == SFmode) bits = 0x2; - else if (mode == DFmode) + else if (mode == DFmode || mode == TFmode) bits = 0x3; else abort (); @@ -9590,6 +11322,8 @@ rs6000_output_function_epilogue (file, size) /* Omit this list of longs, because there are no CTL anchors. */ /* Length of function name. */ + if (*fname == '*') + ++fname; fprintf (file, "\t.short %d\n", (int) strlen (fname)); /* Function name. */ @@ -9602,7 +11336,6 @@ rs6000_output_function_epilogue (file, size) fputs ("\t.align 2\n", file); } - return; } /* A C compound statement that outputs the assembler code for a thunk @@ -9637,11 +11370,12 @@ rs6000_output_function_epilogue (file, size) calls FUNCTION instead of jumping to it. The generic approach does not support varargs. */ -void -output_mi_thunk (file, thunk_fndecl, delta, function) +static void +rs6000_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function) FILE *file; tree thunk_fndecl ATTRIBUTE_UNUSED; - int delta; + HOST_WIDE_INT delta; + HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED; tree function; { const char *this_reg = @@ -9659,9 +11393,9 @@ output_mi_thunk (file, thunk_fndecl, delta, function) if (delta >= -32768 && delta <= 32767) { if (! TARGET_NEW_MNEMONICS) - fprintf (file, "\tcal %s,%d(%s)\n", this_reg, delta, this_reg); + fprintf (file, "\tcal %s,%d(%s)\n", this_reg, (int) delta, this_reg); else - fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta); + fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, (int) delta); } /* 64-bit constants. If "int" is 32 bits, we'll never hit this abort. */ @@ -9671,7 +11405,7 @@ output_mi_thunk (file, thunk_fndecl, delta, function) /* Large constants that can be done by one addis instruction. */ else if ((delta & 0xffff) == 0) asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg, - delta >> 16); + (int) (delta >> 16)); /* 32-bit constants that can be done by an add and addis instruction. */ else @@ -9702,6 +11436,7 @@ output_mi_thunk (file, thunk_fndecl, delta, function) case ABI_V4: case ABI_AIX_NODESC: + case ABI_DARWIN: prefix = ""; break; } @@ -9712,8 +11447,10 @@ output_mi_thunk (file, thunk_fndecl, delta, function) fname = XSTR (XEXP (DECL_RTL (function), 0), 0); if (current_file_function_operand (XEXP (DECL_RTL (function), 0), VOIDmode) - && ! lookup_attribute ("longcall", - TYPE_ATTRIBUTES (TREE_TYPE (function)))) + && (! lookup_attribute ("longcall", + TYPE_ATTRIBUTES (TREE_TYPE (function))) + || lookup_attribute ("shortcall", + TYPE_ATTRIBUTES (TREE_TYPE (function))))) { fprintf (file, "\tb %s", prefix); assemble_name (file, fname); @@ -9745,10 +11482,7 @@ output_mi_thunk (file, thunk_fndecl, delta, function) } assemble_name (file, fname); putc ('\n', file); - if (TARGET_ELF) - function_section (current_function_decl); - else - text_section (); + function_section (current_function_decl); if (TARGET_MINIMAL_TOC) asm_fprintf (file, (TARGET_32BIT) ? "\t{l|lwz} %s,%s(%s)\n" : "\tld %s,%s(%s)\n", r12, @@ -9795,7 +11529,6 @@ output_mi_thunk (file, thunk_fndecl, delta, function) } } } - /* A quick summary of the various types of 'constant-pool tables' under PowerPC: @@ -9843,20 +11576,34 @@ static unsigned rs6000_hash_constant (k) rtx k; { - unsigned result = (GET_CODE (k) << 3) ^ GET_MODE (k); - const char *format = GET_RTX_FORMAT (GET_CODE (k)); - int flen = strlen (format); - int fidx; + enum rtx_code code = GET_CODE (k); + enum machine_mode mode = GET_MODE (k); + unsigned result = (code << 3) ^ mode; + const char *format; + int flen, fidx; - if (GET_CODE (k) == LABEL_REF) - return result * 1231 + X0INT (XEXP (k, 0), 3); + format = GET_RTX_FORMAT (code); + flen = strlen (format); + fidx = 0; - if (GET_CODE (k) == CONST_DOUBLE) - fidx = 1; - else if (GET_CODE (k) == CODE_LABEL) - fidx = 3; - else - fidx = 0; + switch (code) + { + case LABEL_REF: + return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0)); + + case CONST_DOUBLE: + if (mode != VOIDmode) + return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result; + flen = 2; + break; + + case CODE_LABEL: + fidx = 3; + break; + + default: + break; + } for (; fidx < flen; fidx++) switch (format[fidx]) @@ -9893,6 +11640,7 @@ rs6000_hash_constant (k) default: abort (); } + return result; } @@ -9919,29 +11667,7 @@ toc_hash_eq (h1, h2) != ((const struct toc_hash_struct *) h2)->key_mode) return 0; - /* Gotcha: One of these const_doubles will be in memory. - The other may be on the constant-pool chain. - So rtx_equal_p will think they are different... */ - if (r1 == r2) - return 1; - if (GET_CODE (r1) != GET_CODE (r2) - || GET_MODE (r1) != GET_MODE (r2)) - return 0; - if (GET_CODE (r1) == CONST_DOUBLE) - { - int format_len = strlen (GET_RTX_FORMAT (CONST_DOUBLE)); - int i; - for (i = 1; i < format_len; i++) - if (XWINT (r1, i) != XWINT (r2, i)) - return 0; - - return 1; - } - else if (GET_CODE (r1) == LABEL_REF) - return (CODE_LABEL_NUMBER (XEXP (r1, 0)) - == CODE_LABEL_NUMBER (XEXP (r2, 0))); - else - return rtx_equal_p (r1, r2); + return rtx_equal_p (r1, r2); } /* Mark the hash table-entry HASH_ENTRY. */ @@ -10071,7 +11797,42 @@ output_toc (file, x, labelno, mode) /* Handle FP constants specially. Note that if we have a minimal TOC, things we put here aren't actually in the TOC, so we can allow FP constants. */ - if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) + if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode) + { + REAL_VALUE_TYPE rv; + long k[4]; + + REAL_VALUE_FROM_CONST_DOUBLE (rv, x); + REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k); + + if (TARGET_64BIT) + { + if (TARGET_MINIMAL_TOC) + fputs (DOUBLE_INT_ASM_OP, file); + else + fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", + k[0] & 0xffffffff, k[1] & 0xffffffff, + k[2] & 0xffffffff, k[3] & 0xffffffff); + fprintf (file, "0x%lx%08lx,0x%lx%08lx\n", + k[0] & 0xffffffff, k[1] & 0xffffffff, + k[2] & 0xffffffff, k[3] & 0xffffffff); + return; + } + else + { + if (TARGET_MINIMAL_TOC) + fputs ("\t.long ", file); + else + fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],", + k[0] & 0xffffffff, k[1] & 0xffffffff, + k[2] & 0xffffffff, k[3] & 0xffffffff); + fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n", + k[0] & 0xffffffff, k[1] & 0xffffffff, + k[2] & 0xffffffff, k[3] & 0xffffffff); + return; + } + } + else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) { REAL_VALUE_TYPE rv; long k[2]; @@ -10232,7 +11993,7 @@ output_toc (file, x, labelno, mode) else abort (); - STRIP_NAME_ENCODING (real_name, name); + real_name = (*targetm.strip_name_encoding) (name); if (TARGET_MINIMAL_TOC) fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file); else @@ -10368,7 +12129,7 @@ rs6000_gen_section_name (buf, filename, section_desc) } len = strlen (after_last_slash) + strlen (section_desc) + 2; - *buf = (char *) permalloc (len); + *buf = (char *) xmalloc (len); p = *buf; *p++ = '_'; @@ -10407,7 +12168,7 @@ output_profile_hook (labelno) rtx fun; ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); - STRIP_NAME_ENCODING (label_name, ggc_strdup (buf)); + label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf)); fun = gen_rtx_SYMBOL_REF (Pmode, label_name); emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1, @@ -10546,18 +12307,24 @@ rs6000_adjust_cost (insn, link, dep_insn, cost) switch (get_attr_type (insn)) { case TYPE_JMPREG: - /* Tell the first scheduling pass about the latency between + /* Tell the first scheduling pass about the latency between a mtctr and bctr (and mtlr and br/blr). The first scheduling pass will not know about this latency since the mtctr instruction, which has the latency associated to it, will be generated by reload. */ - return TARGET_POWER ? 5 : 4; + return TARGET_POWER ? 5 : 4; case TYPE_BRANCH: /* Leave some extra cycles between a compare and its dependent branch, to inhibit expensive mispredicts. */ - if ((rs6000_cpu_attr == CPU_PPC750 - || rs6000_cpu_attr == CPU_PPC7400 - || rs6000_cpu_attr == CPU_PPC7450) + if ((rs6000_cpu_attr == CPU_PPC603 + || rs6000_cpu_attr == CPU_PPC604 + || rs6000_cpu_attr == CPU_PPC604E + || rs6000_cpu_attr == CPU_PPC620 + || rs6000_cpu_attr == CPU_PPC630 + || rs6000_cpu_attr == CPU_PPC750 + || rs6000_cpu_attr == CPU_PPC7400 + || rs6000_cpu_attr == CPU_PPC7450 + || rs6000_cpu_attr == CPU_POWER4) && recog_memoized (dep_insn) && (INSN_CODE (dep_insn) >= 0) && (get_attr_type (dep_insn) == TYPE_COMPARE @@ -10638,6 +12405,7 @@ rs6000_issue_rate () case CPU_PPC604E: case CPU_PPC620: case CPU_PPC630: + case CPU_POWER4: return 4; default: return 1; @@ -10730,12 +12498,13 @@ rs6000_initialize_trampoline (addr, fnaddr, cxt) const struct attribute_spec rs6000_attribute_table[] = { /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */ - { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, - { NULL, 0, 0, false, false, false, NULL } + { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, + { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute }, + { NULL, 0, 0, false, false, false, NULL } }; -/* Handle a "longcall" attribute; arguments as in struct - attribute_spec.handler. */ +/* Handle a "longcall" or "shortcall" attribute; arguments as in + struct attribute_spec.handler. */ static tree rs6000_handle_longcall_attribute (node, name, args, flags, no_add_attrs) @@ -10757,6 +12526,20 @@ rs6000_handle_longcall_attribute (node, name, args, flags, no_add_attrs) return NULL_TREE; } +/* Set longcall attributes on all functions declared when + rs6000_default_long_calls is true. */ +static void +rs6000_set_default_type_attributes (type) + tree type; +{ + if (rs6000_default_long_calls + && (TREE_CODE (type) == FUNCTION_TYPE + || TREE_CODE (type) == METHOD_TYPE)) + TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"), + NULL_TREE, + TYPE_ATTRIBUTES (type)); +} + /* Return a reference suitable for calling a function with the longcall attribute. */ @@ -10785,6 +12568,8 @@ rs6000_longcall_ref (call_ref) } +#ifdef USING_ELFOS_H + /* A C statement or statements to switch to the appropriate section for output of RTX in mode MODE. You can assume that RTX is some kind of constant in RTL. The argument MODE is redundant except in @@ -10794,22 +12579,16 @@ rs6000_longcall_ref (call_ref) Do not define this macro if you put all constants in the read-only data section. */ -#ifdef USING_ELFOS_H - -void -rs6000_select_rtx_section (mode, x) +static void +rs6000_elf_select_rtx_section (mode, x, align) enum machine_mode mode; rtx x; + unsigned HOST_WIDE_INT align; { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) toc_section (); - else if (flag_pic - && (GET_CODE (x) == SYMBOL_REF - || GET_CODE (x) == LABEL_REF - || GET_CODE (x) == CONST)) - data_section (); else - const_section (); + default_elf_select_rtx_section (mode, x, align); } /* A C statement or statements to switch to the appropriate @@ -10817,46 +12596,14 @@ rs6000_select_rtx_section (mode, x) or a constant of some sort. RELOC indicates whether forming the initial value of DECL requires link-time relocations. */ -void -rs6000_select_section (decl, reloc) +static void +rs6000_elf_select_section (decl, reloc, align) tree decl; int reloc; + unsigned HOST_WIDE_INT align; { - int size = int_size_in_bytes (TREE_TYPE (decl)); - int needs_sdata; - int readonly; - static void (* const sec_funcs[4]) PARAMS ((void)) = { - &const_section, - &sdata2_section, - &data_section, - &sdata_section - }; - - needs_sdata = (size > 0 - && size <= g_switch_value - && rs6000_sdata != SDATA_NONE - && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))); - - if (TREE_CODE (decl) == STRING_CST) - readonly = ! flag_writable_strings; - else if (TREE_CODE (decl) == VAR_DECL) - readonly = (! ((flag_pic || DEFAULT_ABI == ABI_AIX) && reloc) - && TREE_READONLY (decl) - && ! TREE_SIDE_EFFECTS (decl) - && DECL_INITIAL (decl) - && DECL_INITIAL (decl) != error_mark_node - && TREE_CONSTANT (DECL_INITIAL (decl))); - else if (TREE_CODE (decl) == CONSTRUCTOR) - readonly = (! ((flag_pic || DEFAULT_ABI == ABI_AIX) && reloc) - && ! TREE_SIDE_EFFECTS (decl) - && TREE_CONSTANT (decl)); - else - readonly = ! ((flag_pic || DEFAULT_ABI == ABI_AIX) && reloc); - - if (needs_sdata && rs6000_sdata != SDATA_EABI) - readonly = 0; - - (*sec_funcs[(readonly ? 0 : 2) + (needs_sdata ? 1 : 0)])(); + default_elf_select_section_1 (decl, reloc, align, + flag_pic || DEFAULT_ABI == ABI_AIX); } /* A C statement to build up a unique section name, expressed as a @@ -10865,120 +12612,18 @@ rs6000_select_section (decl, reloc) link-time relocations. If you do not define this macro, GCC will use the symbol name prefixed by `.' as the section name. Note - this macro can now be called for uninitialized data items as well as - initialised data and functions. */ + initialized data and functions. */ -void -rs6000_unique_section (decl, reloc) +static void +rs6000_elf_unique_section (decl, reloc) tree decl; int reloc; { - int len; - int sec; - const char *name; - char *string; - const char *prefix; - - static const char *const prefixes[7][2] = - { - { ".rodata.", ".gnu.linkonce.r." }, - { ".sdata2.", ".gnu.linkonce.s2." }, - { ".data.", ".gnu.linkonce.d." }, - { ".sdata.", ".gnu.linkonce.s." }, - { ".bss.", ".gnu.linkonce.b." }, - { ".sbss.", ".gnu.linkonce.sb." }, - { ".text.", ".gnu.linkonce.t." } - }; - - if (TREE_CODE (decl) == FUNCTION_DECL) - sec = 6; - else - { - int readonly; - int needs_sdata; - int size; - - if (TREE_CODE (decl) == STRING_CST) - readonly = ! flag_writable_strings; - else if (TREE_CODE (decl) == VAR_DECL) - readonly = (! ((flag_pic || DEFAULT_ABI == ABI_AIX) && reloc) - && TREE_READONLY (decl) - && ! TREE_SIDE_EFFECTS (decl) - && TREE_CONSTANT (DECL_INITIAL (decl))); - else - readonly = ! ((flag_pic || DEFAULT_ABI == ABI_AIX) && reloc); - - size = int_size_in_bytes (TREE_TYPE (decl)); - needs_sdata = (size > 0 - && size <= g_switch_value - && rs6000_sdata != SDATA_NONE - && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))); - - if (DECL_INITIAL (decl) == 0 - || DECL_INITIAL (decl) == error_mark_node) - sec = 4; - else if (! readonly) - sec = 2; - else - sec = 0; - - if (needs_sdata) - { - /* .sdata2 is only for EABI. */ - if (sec == 0 && rs6000_sdata != SDATA_EABI) - sec = 2; - sec += 1; - } - } - - STRIP_NAME_ENCODING (name, IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))); - prefix = prefixes[sec][DECL_ONE_ONLY (decl)]; - len = strlen (name) + strlen (prefix); - string = alloca (len + 1); - - sprintf (string, "%s%s", prefix, name); - - DECL_SECTION_NAME (decl) = build_string (len, string); -} - - -static bool -rs6000_binds_local_p (exp) - tree exp; -{ - bool local_p; - tree attr; - - /* A non-decl is an entry in the constant pool. */ - if (!DECL_P (exp)) - local_p = true; - /* Static variables are always local. */ - else if (! TREE_PUBLIC (exp)) - local_p = true; - /* Otherwise, variables defined outside this object may not be local. */ - else if (DECL_EXTERNAL (exp)) - local_p = false; - /* Linkonce and weak data are never local. */ - else if (DECL_ONE_ONLY (exp) || DECL_WEAK (exp)) - local_p = false; - /* If PIC, then assume that any global name can be overridden by - * symbols resolved from other modules. */ - else if (flag_pic || rs6000_flag_pic) - local_p = false; - /* Uninitialized COMMON variable may be unified with symbols - * resolved from other modules. */ - else if (DECL_COMMON (exp) - && (DECL_INITIAL (exp) == NULL - || DECL_INITIAL (exp) == error_mark_node)) - local_p = false; - /* Otherwise we're left with initialized (or non-common) global data - * which is of necessity defined locally. */ - else - local_p = true; - - return local_p; + default_unique_section_1 (decl, reloc, + flag_pic || DEFAULT_ABI == ABI_AIX); } - + /* If we are referencing a function that is static or is known to be in this file, make the SYMBOL_REF special. We can use this to indicate that we can branch to this function without emitting a no-op after the @@ -10987,14 +12632,18 @@ rs6000_binds_local_p (exp) the function descriptor name. This saves a lot of overriding code to read the prefixes. */ -void -rs6000_encode_section_info (decl) +static void +rs6000_elf_encode_section_info (decl, first) tree decl; + int first; { + if (!first) + return; + if (TREE_CODE (decl) == FUNCTION_DECL) { rtx sym_ref = XEXP (DECL_RTL (decl), 0); - if (rs6000_binds_local_p (decl)) + if ((*targetm.binds_local_p) (decl)) SYMBOL_REF_FLAG (sym_ref) = 1; if (DEFAULT_ABI == ABI_AIX) @@ -11019,7 +12668,7 @@ rs6000_encode_section_info (decl) const char *name = (char *)0; int len = 0; - if (rs6000_binds_local_p (decl)) + if ((*targetm.binds_local_p) (decl)) SYMBOL_REF_FLAG (sym_ref) = 1; if (section_name) @@ -11048,7 +12697,6 @@ rs6000_encode_section_info (decl) || (len == sizeof (".PPC.EMB.sbss0") - 1 && strcmp (name, ".PPC.EMB.sbss0") == 0)))) { - rtx sym_ref = XEXP (DECL_RTL (decl), 0); size_t len = strlen (XSTR (sym_ref, 0)); char *str = alloca (len + 2); @@ -11059,6 +12707,43 @@ rs6000_encode_section_info (decl) } } +static const char * +rs6000_elf_strip_name_encoding (str) + const char *str; +{ + while (*str == '*' || *str == '@') + str++; + return str; +} + +static bool +rs6000_elf_in_small_data_p (decl) + tree decl; +{ + if (rs6000_sdata == SDATA_NONE) + return false; + + if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl)) + { + const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl)); + if (strcmp (section, ".sdata") == 0 + || strcmp (section, ".sdata2") == 0 + || strcmp (section, ".sbss") == 0) + return true; + } + else + { + HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl)); + + if (size > 0 + && size <= g_switch_value + && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl))) + return true; + } + + return false; +} + #endif /* USING_ELFOS_H */ @@ -11106,16 +12791,9 @@ rs6000_fatal_bad_address (op) static void rs6000_add_gc_roots () { - ggc_add_rtx_root (&rs6000_compare_op0, 1); - ggc_add_rtx_root (&rs6000_compare_op1, 1); - toc_hash_table = htab_create (1021, toc_hash_function, toc_hash_eq, NULL); ggc_add_root (&toc_hash_table, 1, sizeof (toc_hash_table), toc_hash_mark_table); - -#if TARGET_MACHO - machopic_add_gc_roots (); -#endif } #if TARGET_MACHO @@ -11177,8 +12855,7 @@ output_compiler_stub () { char tmp_buf[256]; char label_buf[256]; - char *label; - tree tmp_stub, stub; + tree stub; if (!flag_pic) for (stub = stub_list; stub; stub = TREE_CHAIN (stub)) @@ -11264,7 +12941,7 @@ output_call (insn, call_dest, operand_number) if (no_previous_def (funname)) { - int line_number; + int line_number = 0; rtx label_rtx = gen_label_rtx (); char *label_buf, temp_buf[256]; ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L", @@ -11324,7 +13001,7 @@ machopic_output_stub (file, symb, stub) static int label = 0; /* Lose our funky encoding stuff so it doesn't contaminate the stub. */ - STRIP_NAME_ENCODING (symb, symb); + symb = (*targetm.strip_name_encoding) (symb); label += 1; @@ -11444,7 +13121,9 @@ rs6000_elf_section_type_flags (decl, name, reloc) const char *name; int reloc; { - unsigned int flags = default_section_type_flags (decl, name, reloc); + unsigned int flags + = default_section_type_flags_1 (decl, name, reloc, + flag_pic || DEFAULT_ABI == ABI_AIX); if (TARGET_RELOCATABLE) flags |= SECTION_WRITE; @@ -11522,12 +13201,215 @@ rs6000_elf_asm_out_destructor (symbol, priority) } #endif -#ifdef OBJECT_FORMAT_COFF +#if TARGET_XCOFF static void -xcoff_asm_named_section (name, flags) +rs6000_xcoff_asm_globalize_label (stream, name) + FILE *stream; const char *name; - unsigned int flags ATTRIBUTE_UNUSED; { - fprintf (asm_out_file, "\t.csect %s\n", name); + fputs (GLOBAL_ASM_OP, stream); + RS6000_OUTPUT_BASENAME (stream, name); + putc ('\n', stream); } -#endif + +static void +rs6000_xcoff_asm_named_section (name, flags) + const char *name; + unsigned int flags; +{ + int smclass; + static const char * const suffix[3] = { "PR", "RO", "RW" }; + + if (flags & SECTION_CODE) + smclass = 0; + else if (flags & SECTION_WRITE) + smclass = 2; + else + smclass = 1; + + fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n", + (flags & SECTION_CODE) ? "." : "", + name, suffix[smclass], flags & SECTION_ENTSIZE); +} + +static void +rs6000_xcoff_select_section (decl, reloc, align) + tree decl; + int reloc; + unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED; +{ + if (decl_readonly_section_1 (decl, reloc, 1)) + { + if (TREE_PUBLIC (decl)) + read_only_data_section (); + else + read_only_private_data_section (); + } + else + { + if (TREE_PUBLIC (decl)) + data_section (); + else + private_data_section (); + } +} + +static void +rs6000_xcoff_unique_section (decl, reloc) + tree decl; + int reloc ATTRIBUTE_UNUSED; +{ + const char *name; + + /* Use select_section for private and uninitialized data. */ + if (!TREE_PUBLIC (decl) + || DECL_COMMON (decl) + || DECL_INITIAL (decl) == NULL_TREE + || DECL_INITIAL (decl) == error_mark_node + || (flag_zero_initialized_in_bss + && initializer_zerop (DECL_INITIAL (decl)))) + return; + + name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); + name = (*targetm.strip_name_encoding) (name); + DECL_SECTION_NAME (decl) = build_string (strlen (name), name); +} + +/* Select section for constant in constant pool. + + On RS/6000, all constants are in the private read-only data area. + However, if this is being placed in the TOC it must be output as a + toc entry. */ + +static void +rs6000_xcoff_select_rtx_section (mode, x, align) + enum machine_mode mode; + rtx x; + unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED; +{ + if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode)) + toc_section (); + else + read_only_private_data_section (); +} + +/* Remove any trailing [DS] or the like from the symbol name. */ + +static const char * +rs6000_xcoff_strip_name_encoding (name) + const char *name; +{ + size_t len; + if (*name == '*') + name++; + len = strlen (name); + if (name[len - 1] == ']') + return ggc_alloc_string (name, len - 4); + else + return name; +} + +/* Section attributes. AIX is always PIC. */ + +static unsigned int +rs6000_xcoff_section_type_flags (decl, name, reloc) + tree decl; + const char *name; + int reloc; +{ + unsigned int align; + unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1); + + /* Align to at least UNIT size. */ + if (flags & SECTION_CODE) + align = MIN_UNITS_PER_WORD; + else + /* Increase alignment of large objects if not already stricter. */ + align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT), + int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD + ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD); + + return flags | (exact_log2 (align) & SECTION_ENTSIZE); +} + +#endif /* TARGET_XCOFF */ + +/* Note that this is also used for PPC64 Linux. */ + +static void +rs6000_xcoff_encode_section_info (decl, first) + tree decl; + int first ATTRIBUTE_UNUSED; +{ + if (TREE_CODE (decl) == FUNCTION_DECL + && (*targetm.binds_local_p) (decl)) + SYMBOL_REF_FLAG (XEXP (DECL_RTL (decl), 0)) = 1; +} + +/* Cross-module name binding. For AIX and PPC64 Linux, which always are + PIC, use private copy of flag_pic. */ + +static bool +rs6000_binds_local_p (decl) + tree decl; +{ + return default_binds_local_p_1 (decl, flag_pic || rs6000_flag_pic); +} + +/* A C expression returning the cost of moving data from a register of class + CLASS1 to one of CLASS2. */ + +int +rs6000_register_move_cost (mode, from, to) + enum machine_mode mode; + enum reg_class from, to; +{ + /* Moves from/to GENERAL_REGS. */ + if (reg_classes_intersect_p (to, GENERAL_REGS) + || reg_classes_intersect_p (from, GENERAL_REGS)) + { + if (! reg_classes_intersect_p (to, GENERAL_REGS)) + from = to; + + if (from == FLOAT_REGS || from == ALTIVEC_REGS) + return (rs6000_memory_move_cost (mode, from, 0) + + rs6000_memory_move_cost (mode, GENERAL_REGS, 0)); + +/* It's more expensive to move CR_REGS than CR0_REGS because of the shift...*/ + else if (from == CR_REGS) + return 4; + + else +/* A move will cost one instruction per GPR moved. */ + return 2 * HARD_REGNO_NREGS (0, mode); + } + +/* Moving between two similar registers is just one instruction. */ + else if (reg_classes_intersect_p (to, from)) + return mode == TFmode ? 4 : 2; + +/* Everything else has to go through GENERAL_REGS. */ + else + return (rs6000_register_move_cost (mode, GENERAL_REGS, to) + + rs6000_register_move_cost (mode, from, GENERAL_REGS)); +} + +/* A C expressions returning the cost of moving data of MODE from a register to + or from memory. */ + +int +rs6000_memory_move_cost (mode, class, in) + enum machine_mode mode; + enum reg_class class; + int in ATTRIBUTE_UNUSED; +{ + if (reg_classes_intersect_p (class, GENERAL_REGS)) + return 4 * HARD_REGNO_NREGS (0, mode); + else if (reg_classes_intersect_p (class, FLOAT_REGS)) + return 4 * HARD_REGNO_NREGS (32, mode); + else if (reg_classes_intersect_p (class, ALTIVEC_REGS)) + return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode); + else + return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS); +} + diff --git a/contrib/gcc/config/rs6000/rs6000.h b/contrib/gcc/config/rs6000/rs6000.h index 8c77dd5..957fcec 100644 --- a/contrib/gcc/config/rs6000/rs6000.h +++ b/contrib/gcc/config/rs6000/rs6000.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for IBM RS/6000. Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2001, 2002 Free Software Foundation, Inc. + 2000, 2001, 2002, 2003 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) This file is part of GNU CC. @@ -46,46 +46,6 @@ Boston, MA 02111-1307, USA. */ #define TARGET_CPU_DEFAULT ((char *)0) #endif -/* Common CPP definitions used by CPP_SPEC among the various targets - for handling -mcpu=xxx switches. */ -#define CPP_CPU_SPEC \ -"%{!mcpu*: \ - %{mpower: %{!mpower2: -D_ARCH_PWR}} \ - %{mpower2: -D_ARCH_PWR2} \ - %{mpowerpc*: -D_ARCH_PPC} \ - %{mno-power: %{!mpowerpc*: -D_ARCH_COM}} \ - %{!mno-power: %{!mpower2: %(cpp_default)}}} \ -%{mcpu=common: -D_ARCH_COM} \ -%{mcpu=power: -D_ARCH_PWR} \ -%{mcpu=power2: -D_ARCH_PWR2} \ -%{mcpu=powerpc: -D_ARCH_PPC} \ -%{mcpu=rios: -D_ARCH_PWR} \ -%{mcpu=rios1: -D_ARCH_PWR} \ -%{mcpu=rios2: -D_ARCH_PWR2} \ -%{mcpu=rsc: -D_ARCH_PWR} \ -%{mcpu=rsc1: -D_ARCH_PWR} \ -%{mcpu=401: -D_ARCH_PPC} \ -%{mcpu=403: -D_ARCH_PPC} \ -%{mcpu=405: -D_ARCH_PPC} \ -%{mcpu=505: -D_ARCH_PPC} \ -%{mcpu=601: -D_ARCH_PPC -D_ARCH_PWR} \ -%{mcpu=602: -D_ARCH_PPC} \ -%{mcpu=603: -D_ARCH_PPC} \ -%{mcpu=603e: -D_ARCH_PPC} \ -%{mcpu=ec603e: -D_ARCH_PPC} \ -%{mcpu=604: -D_ARCH_PPC} \ -%{mcpu=604e: -D_ARCH_PPC} \ -%{mcpu=620: -D_ARCH_PPC} \ -%{mcpu=740: -D_ARCH_PPC} \ -%{mcpu=7400: -D_ARCH_PPC} \ -%{mcpu=7450: -D_ARCH_PPC} \ -%{mcpu=750: -D_ARCH_PPC} \ -%{mcpu=801: -D_ARCH_PPC} \ -%{mcpu=821: -D_ARCH_PPC} \ -%{mcpu=823: -D_ARCH_PPC} \ -%{mcpu=860: -D_ARCH_PPC} \ -%{maltivec: -D__ALTIVEC__}" - /* Common ASM definitions used by ASM_SPEC among the various targets for handling -mcpu=xxx switches. */ #define ASM_CPU_SPEC \ @@ -98,6 +58,8 @@ Boston, MA 02111-1307, USA. */ %{mcpu=common: -mcom} \ %{mcpu=power: -mpwr} \ %{mcpu=power2: -mpwrx} \ +%{mcpu=power3: -m604} \ +%{mcpu=power4: -mpower4} \ %{mcpu=powerpc: -mppc} \ %{mcpu=rios: -mpwr} \ %{mcpu=rios1: -mpwr} \ @@ -116,6 +78,7 @@ Boston, MA 02111-1307, USA. */ %{mcpu=604: -mppc} \ %{mcpu=604e: -mppc} \ %{mcpu=620: -mppc} \ +%{mcpu=630: -m604} \ %{mcpu=740: -mppc} \ %{mcpu=7400: -mppc} \ %{mcpu=7450: -mppc} \ @@ -124,6 +87,7 @@ Boston, MA 02111-1307, USA. */ %{mcpu=821: -mppc} \ %{mcpu=823: -mppc} \ %{mcpu=860: -mppc} \ +%{mcpu=8540: -me500} \ %{maltivec: -maltivec}" #define CPP_DEFAULT_SPEC "" @@ -143,7 +107,6 @@ Boston, MA 02111-1307, USA. */ #define SUBTARGET_EXTRA_SPECS #define EXTRA_SPECS \ - { "cpp_cpu", CPP_CPU_SPEC }, \ { "cpp_default", CPP_DEFAULT_SPEC }, \ { "asm_cpu", ASM_CPU_SPEC }, \ { "asm_default", ASM_DEFAULT_SPEC }, \ @@ -197,7 +160,7 @@ extern int target_flags; /* Disable use of FPRs. */ #define MASK_SOFT_FLOAT 0x00000800 -/* Enable load/store multiple, even on powerpc */ +/* Enable load/store multiple, even on PowerPC */ #define MASK_MULTIPLE 0x00001000 #define MASK_MULTIPLE_SET 0x00002000 @@ -395,7 +358,9 @@ enum processor_type PROCESSOR_PPC630, PROCESSOR_PPC750, PROCESSOR_PPC7400, - PROCESSOR_PPC7450 + PROCESSOR_PPC7450, + PROCESSOR_PPC8540, + PROCESSOR_POWER4 }; extern enum processor_type rs6000_cpu; @@ -427,9 +392,18 @@ extern enum processor_type rs6000_cpu; {"tune=", &rs6000_select[2].string, \ N_("Schedule code for given CPU") }, \ {"debug=", &rs6000_debug_name, N_("Enable debug output") }, \ + {"traceback=", &rs6000_traceback_name, \ + N_("Select full, part, or no traceback table") }, \ {"abi=", &rs6000_abi_string, N_("Specify ABI to use") }, \ {"long-double-", &rs6000_long_double_size_string, \ N_("Specify size of long double (64 or 128 bits)") }, \ + {"isel=", &rs6000_isel_string, \ + N_("Specify yes/no if isel instructions should be generated") }, \ + {"vrsave=", &rs6000_altivec_vrsave_string, \ + N_("Specify yes/no if VRSAVE instructions should be generated for AltiVec") }, \ + {"longcall", &rs6000_longcall_switch, \ + N_("Avoid all range limits on call instructions") }, \ + {"no-longcall", &rs6000_longcall_switch, "" }, \ SUBTARGET_OPTIONS \ } @@ -453,14 +427,30 @@ extern int rs6000_debug_arg; /* debug argument handling */ #define TARGET_DEBUG_STACK rs6000_debug_stack #define TARGET_DEBUG_ARG rs6000_debug_arg +extern const char *rs6000_traceback_name; /* Type of traceback table. */ + /* These are separate from target_flags because we've run out of bits there. */ extern const char *rs6000_long_double_size_string; extern int rs6000_long_double_type_size; extern int rs6000_altivec_abi; +extern int rs6000_spe_abi; +extern int rs6000_isel; +extern int rs6000_fprs; +extern const char *rs6000_isel_string; +extern const char *rs6000_altivec_vrsave_string; +extern int rs6000_altivec_vrsave; +extern const char *rs6000_longcall_switch; +extern int rs6000_default_long_calls; #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128) #define TARGET_ALTIVEC_ABI rs6000_altivec_abi +#define TARGET_ALTIVEC_VRSAVE rs6000_altivec_vrsave + +#define TARGET_SPE_ABI 0 +#define TARGET_SPE 0 +#define TARGET_ISEL 0 +#define TARGET_FPRS 1 /* Sometimes certain combinations of command options do not make sense on a particular target machine. You can define a macro @@ -480,11 +470,37 @@ extern int rs6000_altivec_abi; /* Show we can debug even without a frame pointer. */ #define CAN_DEBUG_WITHOUT_FP - -/* target machine storage layout */ -/* Define to support cross compilation to an RS6000 target. */ -#define REAL_ARITHMETIC +/* Target pragma. */ +#define REGISTER_TARGET_PRAGMAS(PFILE) do { \ + cpp_register_pragma (PFILE, 0, "longcall", rs6000_pragma_longcall); \ +} while (0) + +/* Target #defines. */ +#define TARGET_CPU_CPP_BUILTINS() \ + rs6000_cpu_cpp_builtins (pfile) + +/* This is used by rs6000_cpu_cpp_builtins to indicate the byte order + we're compiling for. Some configurations may need to override it. */ +#define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ + do \ + { \ + if (BYTES_BIG_ENDIAN) \ + { \ + builtin_define ("__BIG_ENDIAN__"); \ + builtin_define ("_BIG_ENDIAN"); \ + builtin_assert ("machine=bigendian"); \ + } \ + else \ + { \ + builtin_define ("__LITTLE_ENDIAN__"); \ + builtin_define ("_LITTLE_ENDIAN"); \ + builtin_assert ("machine=littleendian"); \ + } \ + } \ + while (0) + +/* Target machine storage layout. */ /* Define this macro if it is advisable to hold scalars in registers in a wider mode than that declared by the program. In such cases, @@ -522,21 +538,18 @@ extern int rs6000_altivec_abi; instructions for them. Might as well be consistent with bits and bytes. */ #define WORDS_BIG_ENDIAN 1 -/* number of bits in an addressable storage unit */ -#define BITS_PER_UNIT 8 - -/* Width in bits of a "word", which is the contents of a machine register. - Note that this is not necessarily the width of data type `int'; - if using 16-bit ints on a 68000, this would still be 32. - But on a machine with 16-bit registers, this would be 16. */ -#define BITS_PER_WORD (! TARGET_POWERPC64 ? 32 : 64) #define MAX_BITS_PER_WORD 64 /* Width of a word, in units (bytes). */ #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) +#ifdef IN_LIBGCC2 +#define MIN_UNITS_PER_WORD UNITS_PER_WORD +#else #define MIN_UNITS_PER_WORD 4 +#endif #define UNITS_PER_FP_WORD 8 #define UNITS_PER_ALTIVEC_WORD 16 +#define UNITS_PER_SPE_WORD 8 /* Type used for ptrdiff_t, as a string used in a declaration. */ #define PTRDIFF_TYPE "int" @@ -572,12 +585,6 @@ extern int rs6000_altivec_abi; words. */ #define LONG_LONG_TYPE_SIZE 64 -/* A C expression for the size in bits of the type `char' on the - target machine. If you don't define this, the default is one - quarter of a word. (If this would be less than one storage unit, - it is rounded up to one unit.) */ -#define CHAR_TYPE_SIZE BITS_PER_UNIT - /* A C expression for the size in bits of the type `float' on the target machine. If you don't define this, the default is one word. */ @@ -627,7 +634,8 @@ extern int rs6000_altivec_abi; local store. TYPE is the data type, and ALIGN is the alignment that the object would ordinarily have. */ #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ - ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : ALIGN) + ((TARGET_ALTIVEC && TREE_CODE (TYPE) == VECTOR_TYPE) ? 128 : \ + (TARGET_SPE && TREE_CODE (TYPE) == VECTOR_TYPE) ? 64 : ALIGN) /* Alignment of field after `int : 0' in a structure. */ #define EMPTY_FIELD_BOUNDARY 32 @@ -635,7 +643,19 @@ extern int rs6000_altivec_abi; /* Every structure's size must be a multiple of this. */ #define STRUCTURE_SIZE_BOUNDARY 8 -/* A bitfield declared as `int' forces `int' alignment for the struct. */ +/* Return 1 if a structure or array containing FIELD should be + accessed using `BLKMODE'. + + For the SPE, simd types are V2SI, and gcc can be tempted to put the + entire thing in a DI and use subregs to access the internals. + store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the + back-end. Because a single GPR can hold a V2SI, but not a DI, the + best thing to do is set structs to BLKmode and avoid Severe Tire + Damage. */ +#define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \ + (TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) + +/* A bit-field declared as `int' forces `int' alignment for the struct. */ #define PCC_BITFIELD_TYPE_MATTERS 1 /* Make strings word-aligned so strcpy from constants will be faster. @@ -649,12 +669,12 @@ extern int rs6000_altivec_abi; /* Make arrays of chars word-aligned for the same reasons. Align vectors to 128 bits. */ #define DATA_ALIGNMENT(TYPE, ALIGN) \ - (TREE_CODE (TYPE) == VECTOR_TYPE ? 128 \ + (TREE_CODE (TYPE) == VECTOR_TYPE ? (TARGET_SPE_ABI ? 64 : 128) \ : TREE_CODE (TYPE) == ARRAY_TYPE \ && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) -/* Non-zero if move instructions will actually fail to work +/* Nonzero if move instructions will actually fail to work when given unaligned data. */ #define STRICT_ALIGNMENT 0 @@ -663,7 +683,8 @@ extern int rs6000_altivec_abi; emulated in a trap handler. */ #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \ (STRICT_ALIGNMENT \ - || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == DImode) \ + || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ + || (MODE) == DImode) \ && (ALIGN) < 32)) /* Standard register usage. */ @@ -688,7 +709,7 @@ extern int rs6000_altivec_abi; a register, in order to work around problems in allocating stack storage in inline functions. */ -#define FIRST_PSEUDO_REGISTER 110 +#define FIRST_PSEUDO_REGISTER 113 /* This must be included for pre gcc 3.0 glibc compatibility. */ #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 @@ -712,7 +733,8 @@ extern int rs6000_altivec_abi; /* AltiVec registers. */ \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 1 \ + 1, 1 \ + , 1, 1 \ } /* 1 for registers not available across function calls. @@ -731,7 +753,8 @@ extern int rs6000_altivec_abi; /* AltiVec registers. */ \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 1 \ + 1, 1 \ + , 1, 1 \ } /* Like `CALL_USED_REGISTERS' except this macro doesn't require that @@ -749,7 +772,8 @@ extern int rs6000_altivec_abi; /* AltiVec registers. */ \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ - 0 \ + 0, 0 \ + , 0, 0 \ } #define MQ_REGNO 64 @@ -764,6 +788,9 @@ extern int rs6000_altivec_abi; #define LAST_ALTIVEC_REGNO 108 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) #define VRSAVE_REGNO 109 +#define VSCR_REGNO 110 +#define SPE_ACC_REGNO 111 +#define SPEFSCR_REGNO 112 /* List the order in which to allocate registers. Each register must be listed once, even those in FIXED_REGISTERS. @@ -786,7 +813,8 @@ extern int rs6000_altivec_abi; mq (not saved; best to use it if we can) ctr (not saved; when we have the choice ctr is better) lr (saved) - cr5, r1, r2, ap, xer, vrsave (fixed) + cr5, r1, r2, ap, xer, vrsave, vscr (fixed) + spe_acc, spefscr (fixed) AltiVec registers: v0 - v1 (not saved or used for anything) @@ -817,7 +845,8 @@ extern int rs6000_altivec_abi; 79, \ 96, 95, 94, 93, 92, 91, \ 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, \ - 97, 109 \ + 97, 109, 110 \ + , 111, 112 \ } /* True if register is floating-point. */ @@ -832,6 +861,9 @@ extern int rs6000_altivec_abi; /* True if register is an integer register. */ #define INT_REGNO_P(N) ((N) <= 31 || (N) == ARG_POINTER_REGNUM) +/* SPE SIMD registers are just the GPRs. */ +#define SPE_SIMD_REGNO_P(N) ((N) <= 31) + /* True if register is the XER register. */ #define XER_REGNO_P(N) ((N) == XER_REGNO) @@ -843,28 +875,41 @@ extern int rs6000_altivec_abi; This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers. + For the SPE, GPRs are 64 bits but only 32 bits are visible in + scalar instructions. The upper 32 bits are only available to the + SIMD instructions. + POWER and PowerPC GPRs hold 32 bits worth; PowerPC64 GPRs and FPRs point register holds 64 bits worth. */ #define HARD_REGNO_NREGS(REGNO, MODE) \ (FP_REGNO_P (REGNO) \ ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \ + : (SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE)) \ + ? ((GET_MODE_SIZE (MODE) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD) \ : ALTIVEC_REGNO_P (REGNO) \ ? ((GET_MODE_SIZE (MODE) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD) \ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) #define ALTIVEC_VECTOR_MODE(MODE) \ - ((MODE) == V16QImode \ - || (MODE) == V8HImode \ - || (MODE) == V4SFmode \ - || (MODE) == V4SImode) + ((MODE) == V16QImode \ + || (MODE) == V8HImode \ + || (MODE) == V4SFmode \ + || (MODE) == V4SImode) + +#define SPE_VECTOR_MODE(MODE) \ + ((MODE) == V4HImode \ + || (MODE) == V2SFmode \ + || (MODE) == V1DImode \ + || (MODE) == V2SImode) /* Define this macro to be nonzero if the port is prepared to handle insns involving vector mode MODE. At the very least, it must have move patterns for this mode. */ -#define VECTOR_MODE_SUPPORTED_P(MODE) \ - (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE)) +#define VECTOR_MODE_SUPPORTED_P(MODE) \ + ((TARGET_SPE && SPE_VECTOR_MODE (MODE)) \ + || (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (MODE))) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. For POWER and PowerPC, the GPRs can hold any mode, but the float @@ -878,10 +923,10 @@ extern int rs6000_altivec_abi; || (GET_MODE_CLASS (MODE) == MODE_INT \ && GET_MODE_SIZE (MODE) == UNITS_PER_FP_WORD)) \ : ALTIVEC_REGNO_P (REGNO) ? ALTIVEC_VECTOR_MODE (MODE) \ + : SPE_SIMD_REGNO_P (REGNO) && TARGET_SPE && SPE_VECTOR_MODE (MODE) ? 1 \ : CR_REGNO_P (REGNO) ? GET_MODE_CLASS (MODE) == MODE_CC \ : XER_REGNO_P (REGNO) ? (MODE) == PSImode \ - : ! INT_REGNO_P (REGNO) ? (GET_MODE_CLASS (MODE) == MODE_INT \ - && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD) \ + : ! INT_REGNO_P (REGNO) ? GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \ : 1) /* Value is 1 if it is a good idea to tie two pseudo registers @@ -904,35 +949,14 @@ extern int rs6000_altivec_abi; : 1) /* A C expression returning the cost of moving data from a register of class - CLASS1 to one of CLASS2. - - On the RS/6000, copying between floating-point and fixed-point - registers is expensive. */ - -#define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ - ((CLASS1) == FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 2 \ - : (CLASS1) == FLOAT_REGS && (CLASS2) != FLOAT_REGS ? 10 \ - : (CLASS1) != FLOAT_REGS && (CLASS2) == FLOAT_REGS ? 10 \ - : (CLASS1) == ALTIVEC_REGS && (CLASS2) != ALTIVEC_REGS ? 20 \ - : (CLASS1) != ALTIVEC_REGS && (CLASS2) == ALTIVEC_REGS ? 20 \ - : (((CLASS1) == SPECIAL_REGS || (CLASS1) == MQ_REGS \ - || (CLASS1) == LINK_REGS || (CLASS1) == CTR_REGS \ - || (CLASS1) == LINK_OR_CTR_REGS) \ - && ((CLASS2) == SPECIAL_REGS || (CLASS2) == MQ_REGS \ - || (CLASS2) == LINK_REGS || (CLASS2) == CTR_REGS \ - || (CLASS2) == LINK_OR_CTR_REGS)) ? 10 \ - : 2) + CLASS1 to one of CLASS2. */ -/* A C expressions returning the cost of moving data of MODE from a register to - or from memory. +#define REGISTER_MOVE_COST rs6000_register_move_cost - On the RS/6000, bump this up a bit. */ +/* A C expressions returning the cost of moving data of MODE from a register to + or from memory. */ -#define MEMORY_MOVE_COST(MODE, CLASS, IN) \ - ((GET_MODE_CLASS (MODE) == MODE_FLOAT \ - && (rs6000_cpu == PROCESSOR_RIOS1 || rs6000_cpu == PROCESSOR_PPC601) \ - ? 3 : 2) \ - + 4) +#define MEMORY_MOVE_COST rs6000_memory_move_cost /* Specify the cost of a branch insn; roughly the number of extra insns that should be added to avoid a branch. @@ -942,6 +966,20 @@ extern int rs6000_altivec_abi; #define BRANCH_COST 3 + +/* A fixed register used at prologue and epilogue generation to fix + addressing modes. The SPE needs heavy addressing fixes at the last + minute, and it's best to save a register for it. + + AltiVec also needs fixes, but we've gotten around using r11, which + is actually wrong because when use_backchain_to_restore_sp is true, + we end up clobbering r11. + + The AltiVec case needs to be fixed. Dunno if we should break ABI + compatability and reserve a register for it as well.. */ + +#define FIXED_SCRATCH (TARGET_SPE ? 14 : 11) + /* Define this macro to change register usage conditional on target flags. Set MQ register fixed (already call_used) if not POWER architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not be allocated. @@ -956,12 +994,16 @@ extern int rs6000_altivec_abi; if (TARGET_64BIT) \ fixed_regs[13] = call_used_regs[13] \ = call_really_used_regs[13] = 1; \ - if (TARGET_SOFT_FLOAT) \ + if (TARGET_SOFT_FLOAT || !TARGET_FPRS) \ for (i = 32; i < 64; i++) \ fixed_regs[i] = call_used_regs[i] \ = call_really_used_regs[i] = 1; \ if (DEFAULT_ABI == ABI_V4 \ && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \ + && flag_pic == 2) \ + fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \ + if (DEFAULT_ABI == ABI_V4 \ + && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM \ && flag_pic == 1) \ fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ @@ -972,6 +1014,15 @@ extern int rs6000_altivec_abi; = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] \ = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1; \ + if (TARGET_ALTIVEC) \ + global_regs[VSCR_REGNO] = 1; \ + if (TARGET_SPE) \ + { \ + global_regs[SPEFSCR_REGNO] = 1; \ + fixed_regs[FIXED_SCRATCH] \ + = call_used_regs[FIXED_SCRATCH] \ + = call_really_used_regs[FIXED_SCRATCH] = 1; \ + } \ if (! TARGET_ALTIVEC) \ { \ for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i) \ @@ -1056,6 +1107,9 @@ enum reg_class FLOAT_REGS, ALTIVEC_REGS, VRSAVE_REGS, + VSCR_REGS, + SPE_ACC_REGS, + SPEFSCR_REGS, NON_SPECIAL_REGS, MQ_REGS, LINK_REGS, @@ -1083,6 +1137,9 @@ enum reg_class "FLOAT_REGS", \ "ALTIVEC_REGS", \ "VRSAVE_REGS", \ + "VSCR_REGS", \ + "SPE_ACC_REGS", \ + "SPEFSCR_REGS", \ "NON_SPECIAL_REGS", \ "MQ_REGS", \ "LINK_REGS", \ @@ -1109,6 +1166,9 @@ enum reg_class { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \ { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \ + { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \ { 0xffffffff, 0xffffffff, 0x00000008, 0x00000000 }, /* NON_SPECIAL_REGS */ \ { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \ { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \ @@ -1141,6 +1201,9 @@ enum reg_class : (REGNO) == ARG_POINTER_REGNUM ? BASE_REGS \ : (REGNO) == XER_REGNO ? XER_REGS \ : (REGNO) == VRSAVE_REGNO ? VRSAVE_REGS \ + : (REGNO) == VSCR_REGNO ? VRSAVE_REGS \ + : (REGNO) == SPE_ACC_REGNO ? SPE_ACC_REGS \ + : (REGNO) == SPEFSCR_REGNO ? SPEFSCR_REGS \ : NO_REGS) /* The class value for index registers, and the one for base regs. */ @@ -1169,8 +1232,8 @@ enum reg_class Return 1 if VALUE is in the range specified by C. `I' is a signed 16-bit constant - `J' is a constant with only the high-order 16 bits non-zero - `K' is a constant with only the low-order 16 bits non-zero + `J' is a constant with only the high-order 16 bits nonzero + `K' is a constant with only the low-order 16 bits nonzero `L' is a signed 16-bit constant shifted left 16 bits `M' is a constant that is greater than 31 `N' is a positive constant that is an exact power of two @@ -1209,7 +1272,8 @@ enum reg_class 'R' is for AIX TOC entries. 'S' is a constant that can be placed into a 64-bit mask operand 'T' is a constant that can be placed into a 32-bit mask operand - 'U' is for V.4 small data references. */ + 'U' is for V.4 small data references. + 't' is for AND masks that can be performed by two rldic{l,r} insns. */ #define EXTRA_CONSTRAINT(OP, C) \ ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG \ @@ -1218,6 +1282,10 @@ enum reg_class : (C) == 'T' ? mask_operand (OP, SImode) \ : (C) == 'U' ? (DEFAULT_ABI == ABI_V4 \ && small_data_operand (OP, GET_MODE (OP))) \ + : (C) == 't' ? (mask64_2_operand (OP, DImode) \ + && (fixed_regs[CR0_REGNO] \ + || !logical_operand (OP, DImode)) \ + && !mask64_operand (OP, DImode)) \ : 0) /* Given an rtx X being reloaded into a reg required to be @@ -1273,16 +1341,16 @@ enum reg_class ? ((GET_MODE_SIZE (MODE) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD) \ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) -/* If defined, gives a class of registers that cannot be used as the - operand of a SUBREG that changes the mode of the object illegally. */ -#define CLASS_CANNOT_CHANGE_MODE FLOAT_REGS +/* Return a class of registers that cannot change FROM mode to TO mode. */ -/* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */ +#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ + (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ + ? reg_classes_intersect_p (FLOAT_REGS, CLASS) \ + : (SPE_VECTOR_MODE (FROM) + SPE_VECTOR_MODE (TO)) == 1 \ + ? reg_classes_intersect_p (GENERAL_REGS, CLASS) \ + : 0) -#define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \ - (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)) - /* Stack layout; function entry, exit and calling. */ /* Enumeration to give which calling sequence to use. */ @@ -1315,6 +1383,7 @@ typedef struct rs6000_stack { int lr_save_offset; /* offset to save LR from initial SP */ int cr_save_offset; /* offset to save CR from initial SP */ int vrsave_save_offset; /* offset to save VRSAVE from initial SP */ + int spe_gp_save_offset; /* offset to save spe 64-bit gprs */ int toc_save_offset; /* offset to save the TOC pointer */ int varargs_save_offset; /* offset to save the varargs registers */ int ehrd_offset; /* offset to EH return data */ @@ -1332,6 +1401,8 @@ typedef struct rs6000_stack { int vrsave_size; /* size to hold VRSAVE if not in save_size */ int altivec_padding_size; /* size of altivec alignment padding if not in save_size */ + int spe_gp_size; /* size of 64-bit GPR save size for SPE */ + int spe_padding_size; int toc_size; /* size to hold TOC if not in save_size */ int total_size; /* total bytes allocated for stack */ } rs6000_stack_t; @@ -1450,6 +1521,8 @@ typedef struct rs6000_stack { If the precise function being called is known, FUNC is its FUNCTION_DECL; otherwise, FUNC is 0. + On the SPE, both FPs and vectors are returned in r3. + On RS/6000 an integer value is in r3 and a floating-point value is in fp1, unless -msoft-float. */ @@ -1458,8 +1531,13 @@ typedef struct rs6000_stack { && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \ || POINTER_TYPE_P (VALTYPE) \ ? word_mode : TYPE_MODE (VALTYPE), \ - TREE_CODE (VALTYPE) == VECTOR_TYPE ? ALTIVEC_ARG_RETURN \ - : TREE_CODE (VALTYPE) == REAL_TYPE && TARGET_HARD_FLOAT \ + TREE_CODE (VALTYPE) == VECTOR_TYPE \ + && TARGET_ALTIVEC ? ALTIVEC_ARG_RETURN \ + : TREE_CODE (VALTYPE) == REAL_TYPE \ + && TARGET_SPE_ABI && !TARGET_FPRS \ + ? GP_ARG_RETURN \ + : TREE_CODE (VALTYPE) == REAL_TYPE \ + && TARGET_HARD_FLOAT && TARGET_FPRS \ ? FP_ARG_RETURN : GP_ARG_RETURN) /* Define how to find the value returned by a library function @@ -1468,7 +1546,7 @@ typedef struct rs6000_stack { #define LIBCALL_VALUE(MODE) \ gen_rtx_REG (MODE, ALTIVEC_VECTOR_MODE (MODE) ? ALTIVEC_ARG_RETURN \ : GET_MODE_CLASS (MODE) == MODE_FLOAT \ - && TARGET_HARD_FLOAT \ + && TARGET_HARD_FLOAT && TARGET_FPRS \ ? FP_ARG_RETURN : GP_ARG_RETURN) /* The AIX ABI for the RS/6000 specifies that all structures are @@ -1481,13 +1559,17 @@ typedef struct rs6000_stack { default, and -m switches get the final word. See rs6000_override_options for more details. + The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit + long double support is enabled. These values are returned in memory. + int_size_in_bytes returns -1 for variable size objects, which go in memory always. The cast to unsigned makes -1 > 8. */ #define RETURN_IN_MEMORY(TYPE) \ - (AGGREGATE_TYPE_P (TYPE) && \ - (TARGET_AIX_STRUCT_RET || \ - (unsigned HOST_WIDEST_INT) int_size_in_bytes (TYPE) > 8)) + ((AGGREGATE_TYPE_P (TYPE) \ + && (TARGET_AIX_STRUCT_RET \ + || (unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > 8)) \ + || (DEFAULT_ABI == ABI_V4 && TYPE_MODE (TYPE) == TFmode)) /* DRAFT_V4_STRUCT_RET defaults off. */ #define DRAFT_V4_STRUCT_RET 0 @@ -1534,29 +1616,30 @@ typedef struct rs6000_stack { #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ #define CALL_LONG 0x00000008 /* always call indirect */ +#define CALL_LIBCALL 0x00000010 /* libcall */ /* 1 if N is a possible register number for a function value as seen by the caller. On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ -#define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_ARG_RETURN \ - || ((N) == FP_ARG_RETURN) \ - || (TARGET_ALTIVEC && \ - (N) == ALTIVEC_ARG_RETURN)) +#define FUNCTION_VALUE_REGNO_P(N) \ + ((N) == GP_ARG_RETURN \ + || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT) \ + || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC)) /* 1 if N is a possible register number for function argument passing. On RS/6000, these are r3-r10 and fp1-fp13. On AltiVec, v2 - v13 are used for passing vectors. */ #define FUNCTION_ARG_REGNO_P(N) \ - (((unsigned)((N) - GP_ARG_MIN_REG) < (unsigned)(GP_ARG_NUM_REG)) \ - || (TARGET_ALTIVEC && \ - (unsigned)((N) - ALTIVEC_ARG_MIN_REG) < (unsigned)(ALTIVEC_ARG_NUM_REG)) \ - || ((unsigned)((N) - FP_ARG_MIN_REG) < (unsigned)(FP_ARG_NUM_REG))) - + ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \ + || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \ + && TARGET_ALTIVEC) \ + || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \ + && TARGET_HARD_FLOAT)) /* A C structure for machine-specific, per-function data. This is added to the cfun structure. */ -typedef struct machine_function +typedef struct machine_function GTY(()) { /* Whether a System V.4 varargs area was created. */ int sysv_varargs_p; @@ -1607,13 +1690,18 @@ typedef struct rs6000_args For a library call, FNTYPE is 0. */ #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \ - init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE) + init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE) /* Similar, but when scanning the definition of a procedure. We always set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,LIBNAME) \ - init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE) + init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE) + +/* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ + +#define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ + init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE) /* Update the data in CUM to advance over an argument of mode MODE and data type TYPE. @@ -1622,13 +1710,13 @@ typedef struct rs6000_args #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ function_arg_advance (&CUM, MODE, TYPE, NAMED) -/* Non-zero if we can use a floating-point register to pass this arg. */ +/* Nonzero if we can use a floating-point register to pass this arg. */ #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \ (GET_MODE_CLASS (MODE) == MODE_FLOAT \ && (CUM).fregno <= FP_ARG_MAX_REG \ - && TARGET_HARD_FLOAT) + && TARGET_HARD_FLOAT && TARGET_FPRS) -/* Non-zero if we can use an AltiVec register to pass this arg. */ +/* Nonzero if we can use an AltiVec register to pass this arg. */ #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE) \ (ALTIVEC_VECTOR_MODE (MODE) \ && (CUM).vregno <= ALTIVEC_ARG_MAX_REG \ @@ -1712,8 +1800,8 @@ typedef struct rs6000_args (VALIST) = rs6000_build_va_list () /* Implement `va_start' for varargs and stdarg. */ -#define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \ - rs6000_va_start (stdarg, valist, nextarg) +#define EXPAND_BUILTIN_VA_START(valist, nextarg) \ + rs6000_va_start (valist, nextarg) /* Implement `va_arg'. */ #define EXPAND_BUILTIN_VA_ARG(valist, type) \ @@ -1731,6 +1819,10 @@ typedef struct rs6000_args argument is passed depends on whether or not it is a named argument. */ #define STRICT_ARGUMENT_NAMING 1 +/* We do not allow indirect calls to be optimized into sibling calls, nor + do we allow calls with vector parameters. */ +#define FUNCTION_OK_FOR_SIBCALL(DECL) function_ok_for_sibcall ((DECL)) + /* Output assembler code to FILE to increment profiler label # LABELNO for profiling a function entry. */ @@ -1741,7 +1833,7 @@ typedef struct rs6000_args the stack pointer does not matter. No definition is equivalent to always zero. - On the RS/6000, this is non-zero because we can restore the stack from + On the RS/6000, this is nonzero because we can restore the stack from its backpointer, which we maintain. */ #define EXIT_IGNORE_STACK 1 @@ -1755,7 +1847,7 @@ typedef struct rs6000_args || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ || (current_function_calls_eh_return \ && TARGET_AIX \ - && (REGNO) == TOC_REGISTER)) + && (REGNO) == 2)) /* TRAMPOLINE_TEMPLATE deleted */ @@ -1818,7 +1910,7 @@ typedef struct rs6000_args {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ - { 30, 30} } + { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } /* Given FROM and TO register numbers, say whether this elimination is allowed. Frame pointer elimination is automatically handled. @@ -1829,10 +1921,11 @@ typedef struct rs6000_args We need r30 if -mminimal-toc was specified, and there are constant pool references. */ -#define CAN_ELIMINATE(FROM, TO) \ - ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ - ? ! frame_pointer_needed \ - : (FROM) == 30 ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \ +#define CAN_ELIMINATE(FROM, TO) \ + ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ + ? ! frame_pointer_needed \ + : (FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM \ + ? ! TARGET_MINIMAL_TOC || TARGET_NO_TOC || get_pool_size () == 0 \ : 1) /* Define the offset between two registers, one to be eliminated, and the other @@ -1847,7 +1940,7 @@ typedef struct rs6000_args (OFFSET) = info->total_size; \ else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ (OFFSET) = (info->push_p) ? info->total_size : 0; \ - else if ((FROM) == 30) \ + else if ((FROM) == RS6000_PIC_OFFSET_TABLE_REGNUM) \ (OFFSET) = 0; \ else \ abort (); \ @@ -1962,6 +2055,9 @@ typedef struct rs6000_args #define TOC_RELATIVE_EXPR_P(X) (toc_relative_expr_p (X)) +/* SPE offset addressing is limited to 5-bits worth of double words. */ +#define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0) + #define LEGITIMATE_CONSTANT_POOL_ADDRESS_P(X) \ (TARGET_TOC \ && GET_CODE (X) == PLUS \ @@ -1986,11 +2082,14 @@ typedef struct rs6000_args && LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 0) \ && (! ALTIVEC_VECTOR_MODE (MODE) \ || (GET_CODE (XEXP (X,1)) == CONST_INT && INTVAL (XEXP (X,1)) == 0)) \ + && (! SPE_VECTOR_MODE (MODE) \ + || (GET_CODE (XEXP (X, 1)) == CONST_INT \ + && SPE_CONST_OFFSET_OK (INTVAL (XEXP (X, 1))))) \ && (((MODE) != DFmode && (MODE) != DImode) \ || (TARGET_32BIT \ ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 4) \ : ! (INTVAL (XEXP (X, 1)) & 3))) \ - && ((MODE) != TImode \ + && (((MODE) != TFmode && (MODE) != TImode) \ || (TARGET_32BIT \ ? LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 12) \ : (LEGITIMATE_ADDRESS_INTEGER_P (XEXP (X, 1), 8) \ @@ -2013,7 +2112,7 @@ typedef struct rs6000_args && ! flag_pic && ! TARGET_TOC \ && GET_MODE_NUNITS (MODE) == 1 \ && (GET_MODE_BITSIZE (MODE) <= 32 \ - || (TARGET_HARD_FLOAT && (MODE) == DFmode)) \ + || (TARGET_HARD_FLOAT && TARGET_FPRS && (MODE) == DFmode)) \ && GET_CODE (X) == LO_SUM \ && GET_CODE (XEXP (X, 0)) == REG \ && INT_REG_OK_FOR_BASE_P (XEXP (X, 0), (STRICT)) \ @@ -2106,7 +2205,7 @@ do { \ #define RS6000_PIC_OFFSET_TABLE_REGNUM 30 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM) -#define TOC_REGISTER (TARGET_MINIMAL_TOC ? 30 : 2) +#define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define @@ -2178,7 +2277,7 @@ do { \ #define MAX_MOVE_MAX 8 /* Nonzero if access to memory by bytes is no faster than for words. - Also non-zero if doing byte operations (specifically shifts) in registers + Also nonzero if doing byte operations (specifically shifts) in registers is undesirable. */ #define SLOW_BYTE_ACCESS 1 @@ -2259,6 +2358,8 @@ do { \ ? COSTS_N_INSNS (2) \ : COSTS_N_INSNS (1)); \ case MULT: \ + if (optimize_size) \ + return COSTS_N_INSNS (2); \ switch (rs6000_cpu) \ { \ case PROCESSOR_RIOS1: \ @@ -2292,6 +2393,7 @@ do { \ : COSTS_N_INSNS (3)); \ case PROCESSOR_PPC403: \ case PROCESSOR_PPC604: \ + case PROCESSOR_PPC8540: \ return COSTS_N_INSNS (4); \ case PROCESSOR_PPC620: \ case PROCESSOR_PPC630: \ @@ -2300,6 +2402,11 @@ do { \ ? COSTS_N_INSNS (5) : COSTS_N_INSNS (7) \ : INTVAL (XEXP (X, 1)) >= -256 && INTVAL (XEXP (X, 1)) <= 255 \ ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4)); \ + case PROCESSOR_POWER4: \ + return (GET_CODE (XEXP (X, 1)) != CONST_INT \ + ? GET_MODE (XEXP (X, 1)) != DImode \ + ? COSTS_N_INSNS (3) : COSTS_N_INSNS (4) \ + : COSTS_N_INSNS (2)); \ } \ case DIV: \ case MOD: \ @@ -2334,10 +2441,12 @@ do { \ return COSTS_N_INSNS (20); \ case PROCESSOR_PPC620: \ case PROCESSOR_PPC630: \ + case PROCESSOR_POWER4: \ return (GET_MODE (XEXP (X, 1)) != DImode \ ? COSTS_N_INSNS (21) \ : COSTS_N_INSNS (37)); \ case PROCESSOR_PPC750: \ + case PROCESSOR_PPC8540: \ case PROCESSOR_PPC7400: \ return COSTS_N_INSNS (19); \ case PROCESSOR_PPC7450: \ @@ -2368,18 +2477,6 @@ do { \ /* #define ADJUST_INSN_LENGTH(X,LENGTH) */ -/* Add any extra modes needed to represent the condition code. - - For the RS/6000, we need separate modes when unsigned (logical) comparisons - are being done and we need a separate mode for floating-point. We also - use a mode for the case when we are comparing the results of two - comparisons, as then only the EQ bit is valid in the register. */ - -#define EXTRA_CC_MODES \ - CC(CCUNSmode, "CCUNS") \ - CC(CCFPmode, "CCFP") \ - CC(CCEQmode, "CCEQ") - /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, return the mode to be used for the comparison. For floating-point, CCFPmode should be used. CCUNSmode should be used @@ -2397,7 +2494,8 @@ do { \ stored from the compare operation. Note that we can't use "rtx" here since it hasn't been defined! */ -extern struct rtx_def *rs6000_compare_op0, *rs6000_compare_op1; +extern GTY(()) rtx rs6000_compare_op0; +extern GTY(()) rtx rs6000_compare_op1; extern int rs6000_compare_fp_p; /* Control the assembler format that we output. */ @@ -2633,6 +2731,9 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ &rs6000_reg_names[107][0], /* v30 */ \ &rs6000_reg_names[108][0], /* v31 */ \ &rs6000_reg_names[109][0], /* vrsave */ \ + &rs6000_reg_names[110][0], /* vscr */ \ + &rs6000_reg_names[111][0], /* spe_acc */ \ + &rs6000_reg_names[112][0], /* spefscr */ \ } /* print-rtl can't handle the above REGISTER_NAMES, so define the @@ -2641,8 +2742,8 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ #define DEBUG_REGISTER_NAMES \ { \ - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ + "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ @@ -2651,12 +2752,13 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", \ "mq", "lr", "ctr", "ap", \ "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \ - "xer", \ + "xer", \ "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \ "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \ "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \ "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \ - "vrsave" \ + "vrsave", "vscr", \ + "spe_acc", "spefscr" \ } /* Table of additional register names to use in user input. */ @@ -2686,7 +2788,8 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \ {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \ {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \ - {"vrsave", 109}, \ + {"vrsave", 109}, {"vscr", 110}, \ + {"spe_acc", 111}, {"spefscr", 112}, \ /* no additional names for: mq, lr, ctr, ap */ \ {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \ {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \ @@ -2787,12 +2890,16 @@ extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ {"non_add_cint_operand", {CONST_INT}}, \ {"and_operand", {SUBREG, REG, CONST_INT}}, \ {"and64_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ + {"and64_2_operand", {SUBREG, REG, CONST_INT}}, \ {"logical_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ {"non_logical_cint_operand", {CONST_INT, CONST_DOUBLE}}, \ {"mask_operand", {CONST_INT}}, \ - {"mask64_operand", {CONST_INT, CONST_DOUBLE}}, \ + {"mask_operand_wrap", {CONST_INT}}, \ + {"mask64_operand", {CONST_INT}}, \ + {"mask64_2_operand", {CONST_INT}}, \ {"count_register_operand", {REG}}, \ {"xer_operand", {REG}}, \ + {"symbol_ref_operand", {SYMBOL_REF}}, \ {"call_operand", {SYMBOL_REF, REG}}, \ {"current_file_function_operand", {SYMBOL_REF}}, \ {"input_operand", {SUBREG, MEM, REG, CONST_INT, \ @@ -3032,4 +3139,238 @@ enum rs6000_builtins ALTIVEC_BUILTIN_ABS_V4SF, ALTIVEC_BUILTIN_ABS_V8HI, ALTIVEC_BUILTIN_ABS_V16QI + /* SPE builtins. */ + , SPE_BUILTIN_EVADDW, + SPE_BUILTIN_EVAND, + SPE_BUILTIN_EVANDC, + SPE_BUILTIN_EVDIVWS, + SPE_BUILTIN_EVDIVWU, + SPE_BUILTIN_EVEQV, + SPE_BUILTIN_EVFSADD, + SPE_BUILTIN_EVFSDIV, + SPE_BUILTIN_EVFSMUL, + SPE_BUILTIN_EVFSSUB, + SPE_BUILTIN_EVLDDX, + SPE_BUILTIN_EVLDHX, + SPE_BUILTIN_EVLDWX, + SPE_BUILTIN_EVLHHESPLATX, + SPE_BUILTIN_EVLHHOSSPLATX, + SPE_BUILTIN_EVLHHOUSPLATX, + SPE_BUILTIN_EVLWHEX, + SPE_BUILTIN_EVLWHOSX, + SPE_BUILTIN_EVLWHOUX, + SPE_BUILTIN_EVLWHSPLATX, + SPE_BUILTIN_EVLWWSPLATX, + SPE_BUILTIN_EVMERGEHI, + SPE_BUILTIN_EVMERGEHILO, + SPE_BUILTIN_EVMERGELO, + SPE_BUILTIN_EVMERGELOHI, + SPE_BUILTIN_EVMHEGSMFAA, + SPE_BUILTIN_EVMHEGSMFAN, + SPE_BUILTIN_EVMHEGSMIAA, + SPE_BUILTIN_EVMHEGSMIAN, + SPE_BUILTIN_EVMHEGUMIAA, + SPE_BUILTIN_EVMHEGUMIAN, + SPE_BUILTIN_EVMHESMF, + SPE_BUILTIN_EVMHESMFA, + SPE_BUILTIN_EVMHESMFAAW, + SPE_BUILTIN_EVMHESMFANW, + SPE_BUILTIN_EVMHESMI, + SPE_BUILTIN_EVMHESMIA, + SPE_BUILTIN_EVMHESMIAAW, + SPE_BUILTIN_EVMHESMIANW, + SPE_BUILTIN_EVMHESSF, + SPE_BUILTIN_EVMHESSFA, + SPE_BUILTIN_EVMHESSFAAW, + SPE_BUILTIN_EVMHESSFANW, + SPE_BUILTIN_EVMHESSIAAW, + SPE_BUILTIN_EVMHESSIANW, + SPE_BUILTIN_EVMHEUMI, + SPE_BUILTIN_EVMHEUMIA, + SPE_BUILTIN_EVMHEUMIAAW, + SPE_BUILTIN_EVMHEUMIANW, + SPE_BUILTIN_EVMHEUSIAAW, + SPE_BUILTIN_EVMHEUSIANW, + SPE_BUILTIN_EVMHOGSMFAA, + SPE_BUILTIN_EVMHOGSMFAN, + SPE_BUILTIN_EVMHOGSMIAA, + SPE_BUILTIN_EVMHOGSMIAN, + SPE_BUILTIN_EVMHOGUMIAA, + SPE_BUILTIN_EVMHOGUMIAN, + SPE_BUILTIN_EVMHOSMF, + SPE_BUILTIN_EVMHOSMFA, + SPE_BUILTIN_EVMHOSMFAAW, + SPE_BUILTIN_EVMHOSMFANW, + SPE_BUILTIN_EVMHOSMI, + SPE_BUILTIN_EVMHOSMIA, + SPE_BUILTIN_EVMHOSMIAAW, + SPE_BUILTIN_EVMHOSMIANW, + SPE_BUILTIN_EVMHOSSF, + SPE_BUILTIN_EVMHOSSFA, + SPE_BUILTIN_EVMHOSSFAAW, + SPE_BUILTIN_EVMHOSSFANW, + SPE_BUILTIN_EVMHOSSIAAW, + SPE_BUILTIN_EVMHOSSIANW, + SPE_BUILTIN_EVMHOUMI, + SPE_BUILTIN_EVMHOUMIA, + SPE_BUILTIN_EVMHOUMIAAW, + SPE_BUILTIN_EVMHOUMIANW, + SPE_BUILTIN_EVMHOUSIAAW, + SPE_BUILTIN_EVMHOUSIANW, + SPE_BUILTIN_EVMWHSMF, + SPE_BUILTIN_EVMWHSMFA, + SPE_BUILTIN_EVMWHSMI, + SPE_BUILTIN_EVMWHSMIA, + SPE_BUILTIN_EVMWHSSF, + SPE_BUILTIN_EVMWHSSFA, + SPE_BUILTIN_EVMWHUMI, + SPE_BUILTIN_EVMWHUMIA, + SPE_BUILTIN_EVMWLSMIAAW, + SPE_BUILTIN_EVMWLSMIANW, + SPE_BUILTIN_EVMWLSSIAAW, + SPE_BUILTIN_EVMWLSSIANW, + SPE_BUILTIN_EVMWLUMI, + SPE_BUILTIN_EVMWLUMIA, + SPE_BUILTIN_EVMWLUMIAAW, + SPE_BUILTIN_EVMWLUMIANW, + SPE_BUILTIN_EVMWLUSIAAW, + SPE_BUILTIN_EVMWLUSIANW, + SPE_BUILTIN_EVMWSMF, + SPE_BUILTIN_EVMWSMFA, + SPE_BUILTIN_EVMWSMFAA, + SPE_BUILTIN_EVMWSMFAN, + SPE_BUILTIN_EVMWSMI, + SPE_BUILTIN_EVMWSMIA, + SPE_BUILTIN_EVMWSMIAA, + SPE_BUILTIN_EVMWSMIAN, + SPE_BUILTIN_EVMWHSSFAA, + SPE_BUILTIN_EVMWSSF, + SPE_BUILTIN_EVMWSSFA, + SPE_BUILTIN_EVMWSSFAA, + SPE_BUILTIN_EVMWSSFAN, + SPE_BUILTIN_EVMWUMI, + SPE_BUILTIN_EVMWUMIA, + SPE_BUILTIN_EVMWUMIAA, + SPE_BUILTIN_EVMWUMIAN, + SPE_BUILTIN_EVNAND, + SPE_BUILTIN_EVNOR, + SPE_BUILTIN_EVOR, + SPE_BUILTIN_EVORC, + SPE_BUILTIN_EVRLW, + SPE_BUILTIN_EVSLW, + SPE_BUILTIN_EVSRWS, + SPE_BUILTIN_EVSRWU, + SPE_BUILTIN_EVSTDDX, + SPE_BUILTIN_EVSTDHX, + SPE_BUILTIN_EVSTDWX, + SPE_BUILTIN_EVSTWHEX, + SPE_BUILTIN_EVSTWHOX, + SPE_BUILTIN_EVSTWWEX, + SPE_BUILTIN_EVSTWWOX, + SPE_BUILTIN_EVSUBFW, + SPE_BUILTIN_EVXOR, + SPE_BUILTIN_EVABS, + SPE_BUILTIN_EVADDSMIAAW, + SPE_BUILTIN_EVADDSSIAAW, + SPE_BUILTIN_EVADDUMIAAW, + SPE_BUILTIN_EVADDUSIAAW, + SPE_BUILTIN_EVCNTLSW, + SPE_BUILTIN_EVCNTLZW, + SPE_BUILTIN_EVEXTSB, + SPE_BUILTIN_EVEXTSH, + SPE_BUILTIN_EVFSABS, + SPE_BUILTIN_EVFSCFSF, + SPE_BUILTIN_EVFSCFSI, + SPE_BUILTIN_EVFSCFUF, + SPE_BUILTIN_EVFSCFUI, + SPE_BUILTIN_EVFSCTSF, + SPE_BUILTIN_EVFSCTSI, + SPE_BUILTIN_EVFSCTSIZ, + SPE_BUILTIN_EVFSCTUF, + SPE_BUILTIN_EVFSCTUI, + SPE_BUILTIN_EVFSCTUIZ, + SPE_BUILTIN_EVFSNABS, + SPE_BUILTIN_EVFSNEG, + SPE_BUILTIN_EVMRA, + SPE_BUILTIN_EVNEG, + SPE_BUILTIN_EVRNDW, + SPE_BUILTIN_EVSUBFSMIAAW, + SPE_BUILTIN_EVSUBFSSIAAW, + SPE_BUILTIN_EVSUBFUMIAAW, + SPE_BUILTIN_EVSUBFUSIAAW, + SPE_BUILTIN_EVADDIW, + SPE_BUILTIN_EVLDD, + SPE_BUILTIN_EVLDH, + SPE_BUILTIN_EVLDW, + SPE_BUILTIN_EVLHHESPLAT, + SPE_BUILTIN_EVLHHOSSPLAT, + SPE_BUILTIN_EVLHHOUSPLAT, + SPE_BUILTIN_EVLWHE, + SPE_BUILTIN_EVLWHOS, + SPE_BUILTIN_EVLWHOU, + SPE_BUILTIN_EVLWHSPLAT, + SPE_BUILTIN_EVLWWSPLAT, + SPE_BUILTIN_EVRLWI, + SPE_BUILTIN_EVSLWI, + SPE_BUILTIN_EVSRWIS, + SPE_BUILTIN_EVSRWIU, + SPE_BUILTIN_EVSTDD, + SPE_BUILTIN_EVSTDH, + SPE_BUILTIN_EVSTDW, + SPE_BUILTIN_EVSTWHE, + SPE_BUILTIN_EVSTWHO, + SPE_BUILTIN_EVSTWWE, + SPE_BUILTIN_EVSTWWO, + SPE_BUILTIN_EVSUBIFW, + + /* Compares. */ + SPE_BUILTIN_EVCMPEQ, + SPE_BUILTIN_EVCMPGTS, + SPE_BUILTIN_EVCMPGTU, + SPE_BUILTIN_EVCMPLTS, + SPE_BUILTIN_EVCMPLTU, + SPE_BUILTIN_EVFSCMPEQ, + SPE_BUILTIN_EVFSCMPGT, + SPE_BUILTIN_EVFSCMPLT, + SPE_BUILTIN_EVFSTSTEQ, + SPE_BUILTIN_EVFSTSTGT, + SPE_BUILTIN_EVFSTSTLT, + + /* EVSEL compares. */ + SPE_BUILTIN_EVSEL_CMPEQ, + SPE_BUILTIN_EVSEL_CMPGTS, + SPE_BUILTIN_EVSEL_CMPGTU, + SPE_BUILTIN_EVSEL_CMPLTS, + SPE_BUILTIN_EVSEL_CMPLTU, + SPE_BUILTIN_EVSEL_FSCMPEQ, + SPE_BUILTIN_EVSEL_FSCMPGT, + SPE_BUILTIN_EVSEL_FSCMPLT, + SPE_BUILTIN_EVSEL_FSTSTEQ, + SPE_BUILTIN_EVSEL_FSTSTGT, + SPE_BUILTIN_EVSEL_FSTSTLT, + + SPE_BUILTIN_EVSPLATFI, + SPE_BUILTIN_EVSPLATI, + SPE_BUILTIN_EVMWHSSMAA, + SPE_BUILTIN_EVMWHSMFAA, + SPE_BUILTIN_EVMWHSMIAA, + SPE_BUILTIN_EVMWHUSIAA, + SPE_BUILTIN_EVMWHUMIAA, + SPE_BUILTIN_EVMWHSSFAN, + SPE_BUILTIN_EVMWHSSIAN, + SPE_BUILTIN_EVMWHSMFAN, + SPE_BUILTIN_EVMWHSMIAN, + SPE_BUILTIN_EVMWHUSIAN, + SPE_BUILTIN_EVMWHUMIAN, + SPE_BUILTIN_EVMWHGSSFAA, + SPE_BUILTIN_EVMWHGSMFAA, + SPE_BUILTIN_EVMWHGSMIAA, + SPE_BUILTIN_EVMWHGUMIAA, + SPE_BUILTIN_EVMWHGSSFAN, + SPE_BUILTIN_EVMWHGSMFAN, + SPE_BUILTIN_EVMWHGSMIAN, + SPE_BUILTIN_EVMWHGUMIAN, + SPE_BUILTIN_MTSPEFSCR, + SPE_BUILTIN_MFSPEFSCR, + SPE_BUILTIN_BRINC }; diff --git a/contrib/gcc/config/rs6000/rs6000.md b/contrib/gcc/config/rs6000/rs6000.md index ec16c19..4c95031 100644 --- a/contrib/gcc/config/rs6000/rs6000.md +++ b/contrib/gcc/config/rs6000/rs6000.md @@ -1,6 +1,6 @@ ;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler ;; Copyright (C) 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, -;; 1999, 2000, 2001 Free Software Foundation, Inc. +;; 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) ;; This file is part of GNU CC. @@ -32,6 +32,8 @@ ;; 8 movsi_got ;; 9/v eh_reg_restore ;; 10 fctiwz +;; 15 load_macho_picbase +;; 16 macho_correct_pic ;; 19 movesi_from_cr ;; 20 movesi_to_cr @@ -56,7 +58,7 @@ ;; Processor type -- this attribute must exactly match the processor_type ;; enumeration in rs6000.h. -(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450" +(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,power4" (const (symbol_ref "rs6000_cpu_attr"))) ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY @@ -375,42 +377,52 @@ (and (eq_attr "type" "cr_logical") (eq_attr "cpu" "ppc7450")) 1 1) + (define_function_unit "vec_alu2" 2 0 (and (eq_attr "type" "vecsimple") (eq_attr "cpu" "ppc7450")) 1 2 [(eq_attr "type" "vecsimple")]) + (define_function_unit "vec_alu2" 2 0 (and (eq_attr "type" "vecsimple") (eq_attr "cpu" "ppc7450")) 1 1 [(eq_attr "type" "!vecsimple")]) + (define_function_unit "vec_alu2" 2 0 (and (eq_attr "type" "veccomplex") (eq_attr "cpu" "ppc7450")) 4 2 [(eq_attr "type" "veccomplex")]) + (define_function_unit "vec_alu2" 2 0 (and (eq_attr "type" "veccomplex") (eq_attr "cpu" "ppc7450")) 4 1 [(eq_attr "type" "!veccomplex")]) + (define_function_unit "vec_alu2" 2 0 (and (eq_attr "type" "veccmp") (eq_attr "cpu" "ppc7450")) 2 2 [(eq_attr "type" "veccmp")]) + (define_function_unit "vec_alu2" 2 0 (and (eq_attr "type" "veccmp") (eq_attr "cpu" "ppc7450")) 2 1 [(eq_attr "type" "!veccmp")]) + (define_function_unit "vec_alu2" 2 0 (and (eq_attr "type" "vecfloat") (eq_attr "cpu" "ppc7450")) 4 2 [(eq_attr "type" "vecfloat")]) + (define_function_unit "vec_alu2" 2 0 (and (eq_attr "type" "vecfloat") (eq_attr "cpu" "ppc7450")) 4 1 [(eq_attr "type" "!vecfloat")]) + (define_function_unit "vec_alu2" 2 0 (and (eq_attr "type" "vecperm") (eq_attr "cpu" "ppc7450")) 2 2 [(eq_attr "type" "vecperm")]) + (define_function_unit "vec_alu2" 2 0 (and (eq_attr "type" "vecperm") (eq_attr "cpu" "ppc7450")) @@ -489,7 +501,7 @@ (define_function_unit "iu" 1 0 (and (eq_attr "type" "compare,delayed_compare") - (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630")) + (eq_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc601,ppc603")) 3 1) ; some extra cycles added by TARGET_SCHED_ADJUST_COST between compare @@ -533,7 +545,7 @@ ; fp compare uses fp unit (define_function_unit "fpu" 1 0 (and (eq_attr "type" "fpcompare") - (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630")) + (eq_attr "cpu" "rs64a,ppc601,ppc603,ppc604,ppc604e,ppc620")) 5 1) (define_function_unit "fpu" 1 0 @@ -699,22 +711,12 @@ ; RIOS2 has two symmetric FPUs. (define_function_unit "fpu2" 2 0 - (and (eq_attr "type" "fp") - (eq_attr "cpu" "rios2")) - 2 1) - -(define_function_unit "fpu2" 2 0 - (and (eq_attr "type" "fp") - (eq_attr "cpu" "ppc630")) - 3 1) - -(define_function_unit "fpu2" 2 0 - (and (eq_attr "type" "dmul") + (and (eq_attr "type" "fp,dmul") (eq_attr "cpu" "rios2")) 2 1) (define_function_unit "fpu2" 2 0 - (and (eq_attr "type" "dmul") + (and (eq_attr "type" "fp,dmul") (eq_attr "cpu" "ppc630")) 3 1) @@ -748,6 +750,109 @@ (eq_attr "cpu" "ppc630")) 26 26) +;; Power4 +(define_function_unit "lsu2" 2 0 + (and (eq_attr "type" "load") + (eq_attr "cpu" "power4")) + 3 1) + +(define_function_unit "lsu2" 2 0 + (and (eq_attr "type" "fpload") + (eq_attr "cpu" "power4")) + 5 1) + +(define_function_unit "lsu2" 2 0 + (and (eq_attr "type" "store,fpstore") + (eq_attr "cpu" "power4")) + 1 1) + +(define_function_unit "iu2" 2 0 + (and (eq_attr "type" "integer") + (eq_attr "cpu" "power4")) + 2 1) + +(define_function_unit "iu2" 2 0 + (and (eq_attr "type" "lmul") + (eq_attr "cpu" "power4")) + 7 6) + +(define_function_unit "iu2" 2 0 + (and (eq_attr "type" "imul") + (eq_attr "cpu" "power4")) + 5 4) + +(define_function_unit "iu2" 2 0 + (and (eq_attr "type" "imul2,imul3") + (eq_attr "cpu" "power4")) + 4 3) + +(define_function_unit "iu2" 2 0 + (and (eq_attr "type" "idiv") + (eq_attr "cpu" "power4")) + 36 35) + +(define_function_unit "iu2" 2 0 + (and (eq_attr "type" "ldiv") + (eq_attr "cpu" "power4")) + 68 67) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "idiv") + (eq_attr "cpu" "power4")) + 36 35) + +(define_function_unit "imuldiv" 1 0 + (and (eq_attr "type" "ldiv") + (eq_attr "cpu" "power4")) + 68 67) + +(define_function_unit "iu2" 2 0 + (and (eq_attr "type" "compare") + (eq_attr "cpu" "power4")) + 3 1) + +(define_function_unit "iu2" 2 0 + (and (eq_attr "type" "delayed_compare") + (eq_attr "cpu" "power4")) + 4 1) + +(define_function_unit "bpu" 1 0 + (and (eq_attr "type" "mtjmpr") + (eq_attr "cpu" "power4")) + 3 1) + +(define_function_unit "bpu" 1 0 + (and (eq_attr "type" "jmpreg,branch") + (eq_attr "cpu" "power4")) + 2 1) + +(define_function_unit "cru" 1 0 + (and (eq_attr "type" "cr_logical") + (eq_attr "cpu" "power4")) + 4 1) + +(define_function_unit "fpu2" 2 0 + (and (eq_attr "type" "fp,dmul") + (eq_attr "cpu" "power4")) + 6 1) + +; adjust_cost increases the cost of dependent branches, +; so shave a few cycles off for fpcompare. +(define_function_unit "fpu2" 2 0 + (and (eq_attr "type" "fpcompare") + (eq_attr "cpu" "power4")) + 5 1) + +(define_function_unit "fpu2" 2 0 + (and (eq_attr "type" "sdiv,ddiv") + (eq_attr "cpu" "power4")) + 33 28) + +(define_function_unit "fpu2" 2 0 + (and (eq_attr "type" "ssqrt,dsqrt") + (eq_attr "cpu" "power4")) + 40 35) + ;; Start with fixed-point load and store insns. Here we put only the more ;; complex forms. Basic data transfer is done later. @@ -1631,7 +1736,7 @@ ? operands[0] : gen_reg_rtx (SImode)); HOST_WIDE_INT val = INTVAL (operands[2]); - HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); + HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); /* The ordering here is important for the prolog expander. @@ -1740,7 +1845,7 @@ " { HOST_WIDE_INT val = INTVAL (operands[2]); - HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); + HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; HOST_WIDE_INT rest = trunc_int_for_mode (val - low, SImode); operands[3] = GEN_INT (rest); @@ -1936,9 +2041,18 @@ (minus:SI (match_dup 2) (match_dup 1)))) (set (match_operand:SI 0 "gpc_reg_operand" "") (minus:SI (match_dup 2) (match_dup 3)))] - "TARGET_POWER" + "TARGET_POWER || TARGET_ISEL" " -{ operands[3] = gen_reg_rtx (SImode); }") +{ + if (TARGET_ISEL) + { + operands[2] = force_reg (SImode, operands[2]); + rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); + DONE; + } + + operands[3] = gen_reg_rtx (SImode); +}") (define_split [(set (match_operand:SI 0 "gpc_reg_operand" "") @@ -1961,9 +2075,17 @@ (minus:SI (match_dup 2) (match_dup 1)))) (set (match_operand:SI 0 "gpc_reg_operand" "") (plus:SI (match_dup 3) (match_dup 1)))] - "TARGET_POWER" + "TARGET_POWER || TARGET_ISEL" " -{ operands[3] = gen_reg_rtx (SImode); }") +{ + if (TARGET_ISEL) + { + operands[2] = force_reg (SImode, operands[2]); + rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); + DONE; + } + operands[3] = gen_reg_rtx (SImode); +}") (define_split [(set (match_operand:SI 0 "gpc_reg_operand" "") @@ -1988,9 +2110,14 @@ (minus:SI (match_dup 4) (match_dup 3)))) (set (match_operand:SI 0 "gpc_reg_operand" "") (minus:SI (match_dup 2) (match_dup 3)))] - "TARGET_POWER" + "TARGET_POWER || TARGET_ISEL" " { + if (TARGET_ISEL) + { + rs6000_emit_minmax (operands[0], UMIN, operands[1], operands[2]); + DONE; + } operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); operands[5] = GEN_INT (-2147483647 - 1); @@ -2006,9 +2133,14 @@ (minus:SI (match_dup 4) (match_dup 3)))) (set (match_operand:SI 0 "gpc_reg_operand" "") (plus:SI (match_dup 3) (match_dup 1)))] - "TARGET_POWER" + "TARGET_POWER || TARGET_ISEL" " { + if (TARGET_ISEL) + { + rs6000_emit_minmax (operands[0], UMAX, operands[1], operands[2]); + DONE; + } operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); operands[5] = GEN_INT (-2147483647 - 1); @@ -2107,37 +2239,50 @@ "" " { - if (! TARGET_POWER) + if (TARGET_ISEL) + { + emit_insn (gen_abssi2_isel (operands[0], operands[1])); + DONE; + } + else if (! TARGET_POWER) { emit_insn (gen_abssi2_nopower (operands[0], operands[1])); DONE; } }") -(define_insn "abssi2_power" +(define_insn "*abssi2_power" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] "TARGET_POWER" "abs %0,%1") -(define_insn "abssi2_nopower" +(define_insn_and_split "abssi2_isel" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (abs:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) + (clobber (match_scratch:SI 2 "=b")) + (clobber (match_scratch:CC 3 "=y"))] + "TARGET_ISEL" + "#" + "&& reload_completed" + [(set (match_dup 2) (neg:SI (match_dup 1))) + (set (match_dup 3) + (compare:CC (match_dup 1) + (const_int 0))) + (set (match_dup 0) + (if_then_else:SI (ge (match_dup 3) + (const_int 0)) + (match_dup 1) + (match_dup 2)))] + "") + +(define_insn_and_split "abssi2_nopower" [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") - (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) + (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0"))) (clobber (match_scratch:SI 2 "=&r,&r"))] - "! TARGET_POWER" - "* -{ - return (TARGET_POWERPC) - ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%2,%0\" - : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%2,%0\"; -}" - [(set_attr "length" "12")]) - -(define_split - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (abs:SI (match_operand:SI 1 "gpc_reg_operand" ""))) - (clobber (match_scratch:SI 2 ""))] - "! TARGET_POWER && reload_completed" + "! TARGET_POWER && ! TARGET_ISEL" + "#" + "&& reload_completed" [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) (set (match_dup 0) (minus:SI (match_dup 0) (match_dup 2)))] @@ -2149,24 +2294,13 @@ "TARGET_POWER" "nabs %0,%1") -(define_insn "*nabs_no_power" +(define_insn_and_split "*nabs_nopower" [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,r") - (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) + (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r,0")))) (clobber (match_scratch:SI 2 "=&r,&r"))] "! TARGET_POWER" - "* -{ - return (TARGET_POWERPC) - ? \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;subf %0,%0,%2\" - : \"{srai|srawi} %2,%1,31\;xor %0,%2,%1\;{sf|subfc} %0,%0,%2\"; -}" - [(set_attr "length" "12")]) - -(define_split - [(set (match_operand:SI 0 "gpc_reg_operand" "") - (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "")))) - (clobber (match_scratch:SI 2 ""))] - "! TARGET_POWER && reload_completed" + "#" + "&& reload_completed" [(set (match_dup 2) (ashiftrt:SI (match_dup 1) (const_int 31))) (set (match_dup 0) (xor:SI (match_dup 2) (match_dup 1))) (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 0)))] @@ -2538,7 +2672,7 @@ rtx temp2; if (GET_CODE (operands[2]) != CONST_INT - || INTVAL (operands[2]) < 0 + || INTVAL (operands[2]) <= 0 || (i = exact_log2 (INTVAL (operands[2]))) < 0) FAIL; @@ -2804,7 +2938,7 @@ {andiu.|andis.} %0,%1,%u2") ;; Note to set cr's other than cr0 we do the and immediate and then -;; the test again -- this avoids a mcrf which on the higher end +;; the test again -- this avoids a mfcr which on the higher end ;; machines causes an execution serialization (define_insn "*andsi3_internal2" @@ -2827,6 +2961,26 @@ [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") (set_attr "length" "4,4,4,4,8,8,8,8")]) +(define_insn "*andsi3_internal3" + [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") + (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") + (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) + (const_int 0))) + (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) + (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] + "TARGET_POWERPC64" + "@ + # + {andil.|andi.} %3,%1,%b2 + {andiu.|andis.} %3,%1,%u2 + {rlinm.|rlwinm.} %3,%1,0,%m2,%M2 + # + # + # + #" + [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") + (set_attr "length" "8,4,4,4,8,8,8,8")]) + (define_split [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") @@ -2834,7 +2988,7 @@ (const_int 0))) (clobber (match_scratch:SI 3 "")) (clobber (match_scratch:CC 4 ""))] - "! TARGET_POWERPC64 && reload_completed" + "reload_completed" [(parallel [(set (match_dup 3) (and:SI (match_dup 1) (match_dup 2))) @@ -2844,7 +2998,27 @@ (const_int 0)))] "") -(define_insn "*andsi3_internal3" +;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the +;; whole 64 bit reg, and we don't know what is in the high 32 bits. + +(define_split + [(set (match_operand:CC 0 "cc_reg_operand" "") + (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (clobber (match_scratch:SI 3 "")) + (clobber (match_scratch:CC 4 ""))] + "TARGET_POWERPC64 && reload_completed" + [(parallel [(set (match_dup 3) + (and:SI (match_dup 1) + (match_dup 2))) + (clobber (match_dup 4))]) + (set (match_dup 0) + (compare:CC (match_dup 3) + (const_int 0)))] + "") + +(define_insn "*andsi3_internal4" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) @@ -2866,6 +3040,28 @@ [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") (set_attr "length" "4,4,4,4,8,8,8,8")]) +(define_insn "*andsi3_internal5" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") + (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") + (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") + (and:SI (match_dup 1) + (match_dup 2))) + (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] + "TARGET_POWERPC64" + "@ + # + {andil.|andi.} %0,%1,%b2 + {andiu.|andis.} %0,%1,%u2 + {rlinm.|rlwinm.} %0,%1,0,%m2,%M2 + # + # + # + #" + [(set_attr "type" "compare,compare,compare,delayed_compare,compare,compare,compare,compare") + (set_attr "length" "8,4,4,4,8,8,8,8")]) + (define_split [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") @@ -2875,7 +3071,7 @@ (and:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:CC 4 ""))] - "! TARGET_POWERPC64 && reload_completed" + "reload_completed" [(parallel [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 2))) @@ -2885,6 +3081,104 @@ (const_int 0)))] "") +(define_split + [(set (match_operand:CC 3 "cc_reg_operand" "") + (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "gpc_reg_operand" "")) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "") + (and:SI (match_dup 1) + (match_dup 2))) + (clobber (match_scratch:CC 4 ""))] + "TARGET_POWERPC64 && reload_completed" + [(parallel [(set (match_dup 0) + (and:SI (match_dup 1) + (match_dup 2))) + (clobber (match_dup 4))]) + (set (match_dup 3) + (compare:CC (match_dup 0) + (const_int 0)))] + "") + +;; Handle the PowerPC64 rlwinm corner case + +(define_insn_and_split "*andsi3_internal6" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (and:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "mask_operand_wrap" "i")))] + "TARGET_POWERPC64" + "#" + "TARGET_POWERPC64" + [(set (match_dup 0) + (and:SI (rotate:SI (match_dup 1) (match_dup 3)) + (match_dup 4))) + (set (match_dup 0) + (rotate:SI (match_dup 0) (match_dup 5)))] + " +{ + int mb = extract_MB (operands[2]); + int me = extract_ME (operands[2]); + operands[3] = GEN_INT (me + 1); + operands[5] = GEN_INT (32 - (me + 1)); + operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); +}" + [(set_attr "length" "8")]) + +(define_insn_and_split "*andsi3_internal7" + [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") + (compare:CC (and:SI (match_operand:SI 0 "gpc_reg_operand" "r,r") + (match_operand:SI 1 "mask_operand_wrap" "i,i")) + (const_int 0))) + (clobber (match_scratch:SI 3 "=r,r"))] + "TARGET_POWERPC64" + "#" + "TARGET_POWERPC64" + [(parallel [(set (match_dup 2) + (compare:CC (and:SI (rotate:SI (match_dup 0) (match_dup 4)) + (match_dup 5)) + (const_int 0))) + (clobber (match_dup 3))])] + " +{ + int mb = extract_MB (operands[1]); + int me = extract_ME (operands[1]); + operands[4] = GEN_INT (me + 1); + operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); +}" + [(set_attr "type" "delayed_compare,compare") + (set_attr "length" "4,8")]) + +(define_insn_and_split "*andsi3_internal8" + [(set (match_operand:CC 3 "cc_reg_operand" "=x,??y") + (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "mask_operand_wrap" "i,i")) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (and:SI (match_dup 1) + (match_dup 2)))] + "TARGET_POWERPC64" + "#" + "TARGET_POWERPC64" + [(parallel [(set (match_dup 3) + (compare:CC (and:SI (rotate:SI (match_dup 1) (match_dup 4)) + (match_dup 5)) + (const_int 0))) + (set (match_dup 0) + (and:SI (rotate:SI (match_dup 1) (match_dup 4)) + (match_dup 5)))]) + (set (match_dup 0) + (rotate:SI (match_dup 0) (match_dup 6)))] + " +{ + int mb = extract_MB (operands[2]); + int me = extract_ME (operands[2]); + operands[4] = GEN_INT (me + 1); + operands[6] = GEN_INT (32 - (me + 1)); + operands[5] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); +}" + [(set_attr "type" "delayed_compare,compare") + (set_attr "length" "8,12")]) + (define_expand "iorsi3" [(set (match_operand:SI 0 "gpc_reg_operand" "") (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") @@ -3321,7 +3615,7 @@ #" [(set_attr "type" "compare") (set_attr "length" "4,8")]) - + (define_split [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") (compare:CC @@ -3341,7 +3635,7 @@ (compare:CC (match_dup 0) (const_int 0)))] "") - + ;; Rotate and shift insns, in all their variants. These support shifts, ;; field inserts and extracts, and various combinations thereof. (define_expand "insv" @@ -3519,7 +3813,7 @@ (match_operand:SI 3 "const_int_operand" "i,i")) (const_int 0))) (clobber (match_scratch:SI 4 "=r,r"))] - "! TARGET_POWERPC64" + "" "* { int start = INTVAL (operands[3]) & 31; @@ -3529,7 +3823,7 @@ if (which_alternative == 1) return \"#\"; - /* If the bitfield being tested fits in the upper or lower half of a + /* If the bit-field being tested fits in the upper or lower half of a word, it is possible to use andiu. or andil. to test it. This is useful because the condition register set-use delay is smaller for andi[ul]. than for rlinm. This doesn't work when the starting bit @@ -3561,7 +3855,7 @@ (match_operand:SI 3 "const_int_operand" "")) (const_int 0))) (clobber (match_scratch:SI 4 ""))] - "! TARGET_POWERPC64 && reload_completed" + "reload_completed" [(set (match_dup 4) (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) @@ -3578,7 +3872,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] - "! TARGET_POWERPC64" + "" "* { int start = INTVAL (operands[3]) & 31; @@ -3588,9 +3882,11 @@ if (which_alternative == 1) return \"#\"; + /* Since we are using the output value, we can't ignore any need for + a shift. The bit-field must end at the LSB. */ if (start >= 16 && start + size == 32) { - operands[3] = GEN_INT ((1 << (32 - start)) - 1); + operands[3] = GEN_INT ((1 << size) - 1); return \"{andil.|andi.} %0,%1,%3\"; } @@ -3600,7 +3896,7 @@ operands[3] = GEN_INT (start + size); return \"{rlinm.|rlwinm.} %0,%1,%3,%s2,31\"; }" - [(set_attr "type" "delayed_compare") + [(set_attr "type" "compare") (set_attr "length" "4,8")]) (define_split @@ -3611,7 +3907,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] - "! TARGET_POWERPC64 && reload_completed" + "reload_completed" [(set (match_dup 0) (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) (set (match_dup 4) @@ -3694,7 +3990,7 @@ (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r"))] - "! TARGET_POWERPC64" + "" "@ {rl%I2nm.|rlw%I2nm.} %3,%1,%h2,0xffffffff #" @@ -3707,7 +4003,7 @@ (match_operand:SI 2 "reg_or_cint_operand" "")) (const_int 0))) (clobber (match_scratch:SI 3 ""))] - "! TARGET_POWERPC64 && reload_completed" + "reload_completed" [(set (match_dup 3) (rotate:SI (match_dup 1) (match_dup 2))) (set (match_dup 0) @@ -3722,7 +4018,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (rotate:SI (match_dup 1) (match_dup 2)))] - "! TARGET_POWERPC64" + "" "@ {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,0xffffffff #" @@ -3736,7 +4032,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (rotate:SI (match_dup 1) (match_dup 2)))] - "! TARGET_POWERPC64 && reload_completed" + "reload_completed" [(set (match_dup 0) (rotate:SI (match_dup 1) (match_dup 2))) (set (match_dup 3) @@ -3748,7 +4044,7 @@ [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) - (match_operand:SI 3 "mask_operand" "T")))] + (match_operand:SI 3 "mask_operand" "n")))] "" "{rl%I2nm|rlw%I2nm} %0,%1,%h2,%m3,%M3") @@ -3757,10 +4053,10 @@ (compare:CC (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) - (match_operand:SI 3 "mask_operand" "T,T")) + (match_operand:SI 3 "mask_operand" "n,n")) (const_int 0))) (clobber (match_scratch:SI 4 "=r,r"))] - "! TARGET_POWERPC64" + "" "@ {rl%I2nm.|rlw%I2nm.} %4,%1,%h2,%m3,%M3 #" @@ -3775,7 +4071,7 @@ (match_operand:SI 3 "mask_operand" "")) (const_int 0))) (clobber (match_scratch:SI 4 ""))] - "! TARGET_POWERPC64 && reload_completed" + "reload_completed" [(set (match_dup 4) (and:SI (rotate:SI (match_dup 1) (match_dup 2)) @@ -3790,11 +4086,11 @@ (compare:CC (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "ri,ri")) - (match_operand:SI 3 "mask_operand" "T,T")) + (match_operand:SI 3 "mask_operand" "n,n")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] - "! TARGET_POWERPC64" + "" "@ {rl%I2nm.|rlw%I2nm.} %0,%1,%h2,%m3,%M3 #" @@ -3810,7 +4106,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] - "! TARGET_POWERPC64 && reload_completed" + "reload_completed" [(set (match_dup 0) (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (set (match_dup 4) @@ -4128,7 +4424,7 @@ [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) - (match_operand:SI 3 "mask_operand" "T")))] + (match_operand:SI 3 "mask_operand" "n")))] "includes_lshift_p (operands[2], operands[3])" "{rlinm|rlwinm} %0,%1,%h2,%m3,%M3") @@ -4137,10 +4433,10 @@ (compare:CC (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "const_int_operand" "i,i")) - (match_operand:SI 3 "mask_operand" "T,T")) + (match_operand:SI 3 "mask_operand" "n,n")) (const_int 0))) (clobber (match_scratch:SI 4 "=r,r"))] - "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])" + "includes_lshift_p (operands[2], operands[3])" "@ {rlinm.|rlwinm.} %4,%1,%h2,%m3,%M3 #" @@ -4155,7 +4451,7 @@ (match_operand:SI 3 "mask_operand" "")) (const_int 0))) (clobber (match_scratch:SI 4 ""))] - "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed" + "includes_lshift_p (operands[2], operands[3]) && reload_completed" [(set (match_dup 4) (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) @@ -4169,11 +4465,11 @@ (compare:CC (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "const_int_operand" "i,i")) - (match_operand:SI 3 "mask_operand" "T,T")) + (match_operand:SI 3 "mask_operand" "n,n")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] - "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3])" + "includes_lshift_p (operands[2], operands[3])" "@ {rlinm.|rlwinm.} %0,%1,%h2,%m3,%M3 #" @@ -4189,7 +4485,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] - "! TARGET_POWERPC64 && includes_lshift_p (operands[2], operands[3]) && reload_completed" + "includes_lshift_p (operands[2], operands[3]) && reload_completed" [(set (match_dup 0) (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (set (match_dup 4) @@ -4367,7 +4663,7 @@ [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) - (match_operand:SI 3 "mask_operand" "T")))] + (match_operand:SI 3 "mask_operand" "n")))] "includes_rshift_p (operands[2], operands[3])" "{rlinm|rlwinm} %0,%1,%s2,%m3,%M3") @@ -4376,10 +4672,10 @@ (compare:CC (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "const_int_operand" "i,i")) - (match_operand:SI 3 "mask_operand" "T,T")) + (match_operand:SI 3 "mask_operand" "n,n")) (const_int 0))) (clobber (match_scratch:SI 4 "=r,r"))] - "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])" + "includes_rshift_p (operands[2], operands[3])" "@ {rlinm.|rlwinm.} %4,%1,%s2,%m3,%M3 #" @@ -4394,7 +4690,7 @@ (match_operand:SI 3 "mask_operand" "")) (const_int 0))) (clobber (match_scratch:SI 4 ""))] - "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed" + "includes_rshift_p (operands[2], operands[3]) && reload_completed" [(set (match_dup 4) (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) @@ -4408,11 +4704,11 @@ (compare:CC (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "const_int_operand" "i,i")) - (match_operand:SI 3 "mask_operand" "T,T")) + (match_operand:SI 3 "mask_operand" "n,n")) (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] - "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3])" + "includes_rshift_p (operands[2], operands[3])" "@ {rlinm.|rlwinm.} %0,%1,%s2,%m3,%M3 #" @@ -4428,7 +4724,7 @@ (const_int 0))) (set (match_operand:SI 0 "gpc_reg_operand" "") (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] - "! TARGET_POWERPC64 && includes_rshift_p (operands[2], operands[3]) && reload_completed" + "includes_rshift_p (operands[2], operands[3]) && reload_completed" [(set (match_dup 0) (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (set (match_dup 4) @@ -4794,7 +5090,7 @@ (define_insn "extendsfdf2" [(set (match_operand:DF 0 "gpc_reg_operand" "=f") (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && TARGET_FPRS" "* { if (REGNO (operands[0]) == REGNO (operands[1])) @@ -4807,35 +5103,47 @@ (define_insn "truncdfsf2" [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && TARGET_FPRS" "frsp %0,%1" [(set_attr "type" "fp")]) (define_insn "aux_truncdfsf2" [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (unspec:SF [(match_operand:SF 1 "gpc_reg_operand" "f")] 0))] - "! TARGET_POWERPC && TARGET_HARD_FLOAT" + "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" "frsp %0,%1" [(set_attr "type" "fp")]) -(define_insn "negsf2" +(define_expand "negsf2" + [(set (match_operand:SF 0 "gpc_reg_operand" "") + (neg:SF (match_operand:SF 1 "gpc_reg_operand" "")))] + "TARGET_HARD_FLOAT" + "") + +(define_insn "*negsf2" [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && TARGET_FPRS" "fneg %0,%1" [(set_attr "type" "fp")]) -(define_insn "abssf2" +(define_expand "abssf2" + [(set (match_operand:SF 0 "gpc_reg_operand" "") + (abs:SF (match_operand:SF 1 "gpc_reg_operand" "")))] + "TARGET_HARD_FLOAT" + "") + +(define_insn "*abssf2" [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && TARGET_FPRS" "fabs %0,%1" [(set_attr "type" "fp")]) (define_insn "" [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && TARGET_FPRS" "fnabs %0,%1" [(set_attr "type" "fp")]) @@ -4850,7 +5158,7 @@ [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (match_operand:SF 2 "gpc_reg_operand" "f")))] - "TARGET_POWERPC && TARGET_HARD_FLOAT" + "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" "fadds %0,%1,%2" [(set_attr "type" "fp")]) @@ -4858,7 +5166,7 @@ [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (match_operand:SF 2 "gpc_reg_operand" "f")))] - "! TARGET_POWERPC && TARGET_HARD_FLOAT" + "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" "{fa|fadd} %0,%1,%2" [(set_attr "type" "fp")]) @@ -4873,7 +5181,7 @@ [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") (match_operand:SF 2 "gpc_reg_operand" "f")))] - "TARGET_POWERPC && TARGET_HARD_FLOAT" + "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" "fsubs %0,%1,%2" [(set_attr "type" "fp")]) @@ -4881,7 +5189,7 @@ [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") (match_operand:SF 2 "gpc_reg_operand" "f")))] - "! TARGET_POWERPC && TARGET_HARD_FLOAT" + "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" "{fs|fsub} %0,%1,%2" [(set_attr "type" "fp")]) @@ -4896,7 +5204,7 @@ [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (match_operand:SF 2 "gpc_reg_operand" "f")))] - "TARGET_POWERPC && TARGET_HARD_FLOAT" + "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" "fmuls %0,%1,%2" [(set_attr "type" "fp")]) @@ -4904,7 +5212,7 @@ [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (match_operand:SF 2 "gpc_reg_operand" "f")))] - "! TARGET_POWERPC && TARGET_HARD_FLOAT" + "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" "{fm|fmul} %0,%1,%2" [(set_attr "type" "dmul")]) @@ -4919,7 +5227,7 @@ [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") (match_operand:SF 2 "gpc_reg_operand" "f")))] - "TARGET_POWERPC && TARGET_HARD_FLOAT" + "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" "fdivs %0,%1,%2" [(set_attr "type" "sdiv")]) @@ -4927,7 +5235,7 @@ [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") (match_operand:SF 2 "gpc_reg_operand" "f")))] - "! TARGET_POWERPC && TARGET_HARD_FLOAT" + "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS" "{fd|fdiv} %0,%1,%2" [(set_attr "type" "ddiv")]) @@ -4936,7 +5244,7 @@ (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 3 "gpc_reg_operand" "f")))] - "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" + "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" "fmadds %0,%1,%2,%3" [(set_attr "type" "fp")]) @@ -4945,7 +5253,7 @@ (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 3 "gpc_reg_operand" "f")))] - "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" + "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" "{fma|fmadd} %0,%1,%2,%3" [(set_attr "type" "dmul")]) @@ -4954,7 +5262,7 @@ (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 3 "gpc_reg_operand" "f")))] - "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" + "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" "fmsubs %0,%1,%2,%3" [(set_attr "type" "fp")]) @@ -4963,7 +5271,7 @@ (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 3 "gpc_reg_operand" "f")))] - "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" + "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" "{fms|fmsub} %0,%1,%2,%3" [(set_attr "type" "dmul")]) @@ -4972,7 +5280,18 @@ (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 3 "gpc_reg_operand" "f"))))] - "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" + "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD + && HONOR_SIGNED_ZEROS (SFmode)" + "fnmadds %0,%1,%2,%3" + [(set_attr "type" "fp")]) + +(define_insn "" + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) + (match_operand:SF 2 "gpc_reg_operand" "f")) + (match_operand:SF 3 "gpc_reg_operand" "f")))] + "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD + && ! HONOR_SIGNED_ZEROS (SFmode)" "fnmadds %0,%1,%2,%3" [(set_attr "type" "fp")]) @@ -4981,7 +5300,17 @@ (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 3 "gpc_reg_operand" "f"))))] - "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" + "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" + "{fnma|fnmadd} %0,%1,%2,%3" + [(set_attr "type" "dmul")]) + +(define_insn "" + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (minus:SF (mult:SF (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")) + (match_operand:SF 2 "gpc_reg_operand" "f")) + (match_operand:SF 3 "gpc_reg_operand" "f")))] + "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD + && ! HONOR_SIGNED_ZEROS (SFmode)" "{fnma|fnmadd} %0,%1,%2,%3" [(set_attr "type" "dmul")]) @@ -4990,7 +5319,18 @@ (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 3 "gpc_reg_operand" "f"))))] - "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" + "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD + && HONOR_SIGNED_ZEROS (SFmode)" + "fnmsubs %0,%1,%2,%3" + [(set_attr "type" "fp")]) + +(define_insn "" + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") + (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") + (match_operand:SF 2 "gpc_reg_operand" "f"))))] + "TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD + && ! HONOR_SIGNED_ZEROS (SFmode)" "fnmsubs %0,%1,%2,%3" [(set_attr "type" "fp")]) @@ -4999,27 +5339,37 @@ (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") (match_operand:SF 2 "gpc_reg_operand" "f")) (match_operand:SF 3 "gpc_reg_operand" "f"))))] - "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FUSED_MADD" + "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" "{fnms|fnmsub} %0,%1,%2,%3" [(set_attr "type" "dmul")]) +(define_insn "" + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (minus:SF (match_operand:SF 3 "gpc_reg_operand" "f") + (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") + (match_operand:SF 2 "gpc_reg_operand" "f"))))] + "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD + && ! HONOR_SIGNED_ZEROS (SFmode)" + "{fnms|fnmsub} %0,%1,%2,%3" + [(set_attr "type" "fp")]) + (define_expand "sqrtsf2" [(set (match_operand:SF 0 "gpc_reg_operand" "") (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "")))] - "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" + "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" "") (define_insn "" [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] - "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT" + "TARGET_PPC_GPOPT && TARGET_HARD_FLOAT && TARGET_FPRS" "fsqrts %0,%1" [(set_attr "type" "ssqrt")]) (define_insn "" [(set (match_operand:SF 0 "gpc_reg_operand" "=f") (sqrt:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] - "TARGET_POWER2 && TARGET_HARD_FLOAT" + "TARGET_POWER2 && TARGET_HARD_FLOAT && TARGET_FPRS" "fsqrt %0,%1" [(set_attr "type" "dsqrt")]) @@ -5033,7 +5383,7 @@ (match_operand:SF 2 "gpc_reg_operand" "")) (match_dup 1) (match_dup 2)))] - "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" + "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") (define_expand "minsf3" @@ -5042,7 +5392,7 @@ (match_operand:SF 2 "gpc_reg_operand" "")) (match_dup 2) (match_dup 1)))] - "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" + "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") (define_split @@ -5050,7 +5400,7 @@ (match_operator:SF 3 "min_max_operator" [(match_operand:SF 1 "gpc_reg_operand" "") (match_operand:SF 2 "gpc_reg_operand" "")]))] - "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" + "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" [(const_int 0)] " { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), @@ -5058,12 +5408,60 @@ DONE; }") +(define_expand "movsicc" + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (if_then_else:SI (match_operand 1 "comparison_operator" "") + (match_operand:SI 2 "gpc_reg_operand" "") + (match_operand:SI 3 "gpc_reg_operand" "")))] + "TARGET_ISEL" + " +{ + if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) + DONE; + else + FAIL; +}") + +;; We use the BASE_REGS for the isel input operands because, if rA is +;; 0, the value of 0 is placed in rD upon truth. Similarly for rB +;; because we may switch the operands and rB may end up being rA. +;; +;; We need 2 patterns: an unsigned and a signed pattern. We could +;; leave out the mode in operand 4 and use one pattern, but reload can +;; change the mode underneath our feet and then gets confused trying +;; to reload the value. +(define_insn "isel_signed" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (if_then_else:SI + (match_operator 1 "comparison_operator" + [(match_operand:CC 4 "cc_reg_operand" "y") + (const_int 0)]) + (match_operand:SI 2 "gpc_reg_operand" "b") + (match_operand:SI 3 "gpc_reg_operand" "b")))] + "TARGET_ISEL" + "* +{ return output_isel (operands); }" + [(set_attr "length" "4")]) + +(define_insn "isel_unsigned" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (if_then_else:SI + (match_operator 1 "comparison_operator" + [(match_operand:CCUNS 4 "cc_reg_operand" "y") + (const_int 0)]) + (match_operand:SI 2 "gpc_reg_operand" "b") + (match_operand:SI 3 "gpc_reg_operand" "b")))] + "TARGET_ISEL" + "* +{ return output_isel (operands); }" + [(set_attr "length" "4")]) + (define_expand "movsfcc" [(set (match_operand:SF 0 "gpc_reg_operand" "") (if_then_else:SF (match_operand 1 "comparison_operator" "") (match_operand:SF 2 "gpc_reg_operand" "") (match_operand:SF 3 "gpc_reg_operand" "")))] - "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" + "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" " { if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) @@ -5078,7 +5476,7 @@ (match_operand:SF 4 "zero_fp_constant" "F")) (match_operand:SF 2 "gpc_reg_operand" "f") (match_operand:SF 3 "gpc_reg_operand" "f")))] - "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" + "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" "fsel %0,%1,%2,%3" [(set_attr "type" "fp")]) @@ -5088,28 +5486,28 @@ (match_operand:DF 4 "zero_fp_constant" "F")) (match_operand:SF 2 "gpc_reg_operand" "f") (match_operand:SF 3 "gpc_reg_operand" "f")))] - "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" + "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" "fsel %0,%1,%2,%3" [(set_attr "type" "fp")]) (define_insn "negdf2" [(set (match_operand:DF 0 "gpc_reg_operand" "=f") (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && TARGET_FPRS" "fneg %0,%1" [(set_attr "type" "fp")]) (define_insn "absdf2" [(set (match_operand:DF 0 "gpc_reg_operand" "=f") (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && TARGET_FPRS" "fabs %0,%1" [(set_attr "type" "fp")]) (define_insn "" [(set (match_operand:DF 0 "gpc_reg_operand" "=f") (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && TARGET_FPRS" "fnabs %0,%1" [(set_attr "type" "fp")]) @@ -5117,7 +5515,7 @@ [(set (match_operand:DF 0 "gpc_reg_operand" "=f") (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (match_operand:DF 2 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && TARGET_FPRS" "{fa|fadd} %0,%1,%2" [(set_attr "type" "fp")]) @@ -5125,7 +5523,7 @@ [(set (match_operand:DF 0 "gpc_reg_operand" "=f") (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") (match_operand:DF 2 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && TARGET_FPRS" "{fs|fsub} %0,%1,%2" [(set_attr "type" "fp")]) @@ -5133,7 +5531,7 @@ [(set (match_operand:DF 0 "gpc_reg_operand" "=f") (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (match_operand:DF 2 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && TARGET_FPRS" "{fm|fmul} %0,%1,%2" [(set_attr "type" "dmul")]) @@ -5141,7 +5539,7 @@ [(set (match_operand:DF 0 "gpc_reg_operand" "=f") (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") (match_operand:DF 2 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && TARGET_FPRS" "{fd|fdiv} %0,%1,%2" [(set_attr "type" "ddiv")]) @@ -5150,7 +5548,7 @@ (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (match_operand:DF 2 "gpc_reg_operand" "f")) (match_operand:DF 3 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" "{fma|fmadd} %0,%1,%2,%3" [(set_attr "type" "dmul")]) @@ -5159,7 +5557,7 @@ (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (match_operand:DF 2 "gpc_reg_operand" "f")) (match_operand:DF 3 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD" "{fms|fmsub} %0,%1,%2,%3" [(set_attr "type" "dmul")]) @@ -5168,7 +5566,18 @@ (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (match_operand:DF 2 "gpc_reg_operand" "f")) (match_operand:DF 3 "gpc_reg_operand" "f"))))] - "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD + && HONOR_SIGNED_ZEROS (DFmode)" + "{fnma|fnmadd} %0,%1,%2,%3" + [(set_attr "type" "dmul")]) + +(define_insn "" + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (minus:DF (mult:DF (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")) + (match_operand:DF 2 "gpc_reg_operand" "f")) + (match_operand:DF 3 "gpc_reg_operand" "f")))] + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD + && ! HONOR_SIGNED_ZEROS (DFmode)" "{fnma|fnmadd} %0,%1,%2,%3" [(set_attr "type" "dmul")]) @@ -5177,14 +5586,25 @@ (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") (match_operand:DF 2 "gpc_reg_operand" "f")) (match_operand:DF 3 "gpc_reg_operand" "f"))))] - "TARGET_HARD_FLOAT && TARGET_FUSED_MADD" + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD + && HONOR_SIGNED_ZEROS (DFmode)" + "{fnms|fnmsub} %0,%1,%2,%3" + [(set_attr "type" "dmul")]) + +(define_insn "" + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (minus:DF (match_operand:DF 3 "gpc_reg_operand" "f") + (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") + (match_operand:DF 2 "gpc_reg_operand" "f"))))] + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD + && ! HONOR_SIGNED_ZEROS (DFmode)" "{fnms|fnmsub} %0,%1,%2,%3" [(set_attr "type" "dmul")]) (define_insn "sqrtdf2" [(set (match_operand:DF 0 "gpc_reg_operand" "=f") (sqrt:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] - "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT" + "(TARGET_PPC_GPOPT || TARGET_POWER2) && TARGET_HARD_FLOAT && TARGET_FPRS" "fsqrt %0,%1" [(set_attr "type" "dsqrt")]) @@ -5197,7 +5617,7 @@ (match_operand:DF 2 "gpc_reg_operand" "")) (match_dup 1) (match_dup 2)))] - "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" + "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" "{ rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); DONE;}") (define_expand "mindf3" @@ -5206,7 +5626,7 @@ (match_operand:DF 2 "gpc_reg_operand" "")) (match_dup 2) (match_dup 1)))] - "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" + "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" "{ rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); DONE;}") (define_split @@ -5214,7 +5634,7 @@ (match_operator:DF 3 "min_max_operator" [(match_operand:DF 1 "gpc_reg_operand" "") (match_operand:DF 2 "gpc_reg_operand" "")]))] - "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" + "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" [(const_int 0)] " { rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), @@ -5227,7 +5647,7 @@ (if_then_else:DF (match_operand 1 "comparison_operator" "") (match_operand:DF 2 "gpc_reg_operand" "") (match_operand:DF 3 "gpc_reg_operand" "")))] - "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" + "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" " { if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) @@ -5242,7 +5662,7 @@ (match_operand:DF 4 "zero_fp_constant" "F")) (match_operand:DF 2 "gpc_reg_operand" "f") (match_operand:DF 3 "gpc_reg_operand" "f")))] - "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT" + "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS" "fsel %0,%1,%2,%3" [(set_attr "type" "fp")]) @@ -5258,6 +5678,18 @@ ;; Conversions to and from floating-point. +(define_expand "fixunssfsi2" + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (unsigned_fix:SI (fix:SF (match_operand:SF 1 "gpc_reg_operand" ""))))] + "TARGET_HARD_FLOAT && !TARGET_FPRS" + "") + +(define_expand "fix_truncsfsi2" + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (fix:SI (match_operand:SF 1 "gpc_reg_operand" "")))] + "TARGET_HARD_FLOAT && !TARGET_FPRS" + "") + ; For each of these conversions, there is a define_expand, a define_insn ; with a '#' template, and a define_split (with C code). The idea is ; to allow constant folding with the template of the define_insn, @@ -5271,7 +5703,7 @@ (clobber (match_dup 4)) (clobber (match_dup 5)) (clobber (match_dup 6))])] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && TARGET_FPRS" " { if (TARGET_POWERPC64) @@ -5284,7 +5716,7 @@ } operands[2] = force_reg (SImode, GEN_INT (0x43300000)); - operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode)); + operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode)); operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); operands[5] = gen_reg_rtx (DFmode); operands[6] = gen_reg_rtx (SImode); @@ -5298,7 +5730,7 @@ (clobber (match_operand:DF 4 "memory_operand" "=o")) (clobber (match_operand:DF 5 "gpc_reg_operand" "=f")) (clobber (match_operand:SI 6 "gpc_reg_operand" "=r"))] - "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" + "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" "#" [(set_attr "length" "24")]) @@ -5310,7 +5742,7 @@ (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) (clobber (match_operand:DF 5 "gpc_reg_operand" "")) (clobber (match_operand:SI 6 "gpc_reg_operand" ""))] - "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" + "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" [(set (match_operand:DF 0 "gpc_reg_operand" "") (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) (use (match_operand:SI 2 "gpc_reg_operand" "")) @@ -5340,6 +5772,12 @@ DONE; }") +(define_expand "floatunssisf2" + [(set (match_operand:SF 0 "gpc_reg_operand" "") + (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] + "TARGET_HARD_FLOAT && !TARGET_FPRS" + "") + (define_expand "floatunssidf2" [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) @@ -5347,7 +5785,7 @@ (use (match_dup 3)) (clobber (match_dup 4)) (clobber (match_dup 5))])] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && TARGET_FPRS" " { if (TARGET_POWERPC64) @@ -5361,7 +5799,7 @@ } operands[2] = force_reg (SImode, GEN_INT (0x43300000)); - operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode)); + operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode)); operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0); operands[5] = gen_reg_rtx (DFmode); }") @@ -5373,7 +5811,7 @@ (use (match_operand:DF 3 "gpc_reg_operand" "f")) (clobber (match_operand:DF 4 "memory_operand" "=o")) (clobber (match_operand:DF 5 "gpc_reg_operand" "=f"))] - "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" + "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" "#" [(set_attr "length" "20")]) @@ -5384,7 +5822,7 @@ (use (match_operand:DF 3 "gpc_reg_operand" "")) (clobber (match_operand:DF 4 "offsettable_mem_operand" "")) (clobber (match_operand:DF 5 "gpc_reg_operand" ""))] - "! TARGET_POWERPC64 && TARGET_HARD_FLOAT" + "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" [(set (match_operand:DF 0 "gpc_reg_operand" "") (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) (use (match_operand:SI 2 "gpc_reg_operand" "")) @@ -5416,7 +5854,7 @@ (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) (clobber (match_dup 2)) (clobber (match_dup 3))])] - "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" + "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" " { operands[2] = gen_reg_rtx (DImode); @@ -5426,9 +5864,9 @@ (define_insn "*fix_truncdfsi2_internal" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))) - (clobber (match_operand:DI 2 "gpc_reg_operand" "=*f")) + (clobber (match_operand:DI 2 "gpc_reg_operand" "=f")) (clobber (match_operand:DI 3 "memory_operand" "=o"))] - "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" + "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" "#" [(set_attr "length" "16")]) @@ -5437,7 +5875,7 @@ (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) (clobber (match_operand:DI 2 "gpc_reg_operand" "")) (clobber (match_operand:DI 3 "offsettable_mem_operand" ""))] - "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" + "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" [(set (match_operand:SI 0 "gpc_reg_operand" "") (fix:SI (match_operand:DF 1 "gpc_reg_operand" ""))) (clobber (match_operand:DI 2 "gpc_reg_operand" "")) @@ -5464,14 +5902,20 @@ (define_insn "fctiwz" [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") (unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))] - "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT" + "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS" "{fcirz|fctiwz} %0,%1" [(set_attr "type" "fp")]) +(define_expand "floatsisf2" + [(set (match_operand:SF 0 "gpc_reg_operand" "") + (float:SF (match_operand:SI 1 "gpc_reg_operand" "")))] + "TARGET_HARD_FLOAT && !TARGET_FPRS" + "") + (define_insn "floatdidf2" [(set (match_operand:DF 0 "gpc_reg_operand" "=f") (float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))] - "TARGET_POWERPC64 && TARGET_HARD_FLOAT" + "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" "fcfid %0,%1" [(set_attr "type" "fp")]) @@ -5481,7 +5925,7 @@ (clobber (match_operand:DI 2 "memory_operand" "=o")) (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] - "TARGET_POWERPC64 && TARGET_HARD_FLOAT" + "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" "#" "" [(set (match_dup 3) (sign_extend:DI (match_dup 1))) @@ -5496,7 +5940,7 @@ (clobber (match_operand:DI 2 "memory_operand" "=o")) (clobber (match_operand:DI 3 "gpc_reg_operand" "=r")) (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))] - "TARGET_POWERPC64 && TARGET_HARD_FLOAT" + "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" "#" "" [(set (match_dup 3) (zero_extend:DI (match_dup 1))) @@ -5508,9 +5952,72 @@ (define_insn "fix_truncdfdi2" [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") (fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))] - "TARGET_POWERPC64 && TARGET_HARD_FLOAT" + "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" "fctidz %0,%1" [(set_attr "type" "fp")]) + +(define_expand "floatdisf2" + [(set (match_operand:SF 0 "gpc_reg_operand" "") + (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))] + "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" + " +{ + if (!flag_unsafe_math_optimizations) + { + rtx label = gen_label_rtx (); + emit_insn (gen_floatdisf2_internal2 (operands[1], label)); + emit_label (label); + } + emit_insn (gen_floatdisf2_internal1 (operands[0], operands[1])); + DONE; +}") + +;; This is not IEEE compliant if rounding mode is "round to nearest". +;; If the DI->DF conversion is inexact, then it's possible to suffer +;; from double rounding. +(define_insn_and_split "floatdisf2_internal1" + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (float:SF (match_operand:DI 1 "gpc_reg_operand" "*f"))) + (clobber (match_scratch:DF 2 "=f"))] + "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" + "#" + "&& reload_completed" + [(set (match_dup 2) + (float:DF (match_dup 1))) + (set (match_dup 0) + (float_truncate:SF (match_dup 2)))] + "") + +;; Twiddles bits to avoid double rounding. +;; Bits that might be trucated when converting to DFmode are replaced +;; by a bit that won't be lost at that stage, but is below the SFmode +;; rounding position. +(define_expand "floatdisf2_internal2" + [(parallel [(set (match_dup 4) + (compare:CC (and:DI (match_operand:DI 0 "" "") + (const_int 2047)) + (const_int 0))) + (set (match_dup 2) (and:DI (match_dup 0) (const_int 2047))) + (clobber (match_scratch:CC 7 ""))]) + (set (match_dup 3) (ashiftrt:DI (match_dup 0) (const_int 53))) + (set (match_dup 3) (plus:DI (match_dup 3) (const_int 1))) + (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) + (label_ref (match_operand:DI 1 "" "")) + (pc))) + (set (match_dup 5) (compare:CCUNS (match_dup 3) (const_int 2))) + (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0)) + (label_ref (match_dup 1)) + (pc))) + (set (match_dup 0) (xor:DI (match_dup 0) (match_dup 2))) + (set (match_dup 0) (ior:DI (match_dup 0) (const_int 2048)))] + "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS" + " +{ + operands[2] = gen_reg_rtx (DImode); + operands[3] = gen_reg_rtx (DImode); + operands[4] = gen_reg_rtx (CCmode); + operands[5] = gen_reg_rtx (CCUNSmode); +}") ;; Define the DImode operations that can be done in a small number ;; of instructions. The & constraints are to prevent the register @@ -5838,6 +6345,16 @@ {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 sraiq %0,%1,%h2\;srliq %L0,%L1,%h2" [(set_attr "length" "8")]) + +(define_insn "ashrdi3_no_power" + [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") + (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") + (match_operand:SI 2 "const_int_operand" "M,i")))] + "TARGET_32BIT && !TARGET_POWER" + "@ + {srai|srawi} %0,%1,31\;{srai|srawi} %L0,%1,%h2 + {sri|srwi} %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;{srai|srawi} %0,%1,%h2" + [(set_attr "length" "8,12")]) ;; PowerPC64 DImode operations. @@ -5861,7 +6378,7 @@ ? operands[0] : gen_reg_rtx (DImode)); HOST_WIDE_INT val = INTVAL (operands[2]); - HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); + HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); if (!CONST_OK_FOR_LETTER_P (rest, 'L')) @@ -5964,7 +6481,7 @@ " { HOST_WIDE_INT val = INTVAL (operands[2]); - HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); + HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; HOST_WIDE_INT rest = trunc_int_for_mode (val - low, DImode); operands[4] = GEN_INT (low); @@ -6119,37 +6636,25 @@ } }") -(define_insn "absdi2" +(define_insn_and_split "absdi2" [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") - (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) + (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0"))) (clobber (match_scratch:DI 2 "=&r,&r"))] "TARGET_POWERPC64" - "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%2,%0" - [(set_attr "length" "12")]) - -(define_split - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (abs:DI (match_operand:DI 1 "gpc_reg_operand" ""))) - (clobber (match_scratch:DI 2 ""))] - "TARGET_POWERPC64 && reload_completed" + "#" + "&& reload_completed" [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) (set (match_dup 0) (minus:DI (match_dup 0) (match_dup 2)))] "") -(define_insn "*nabsdi2" +(define_insn_and_split "*nabsdi2" [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") - (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) + (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))) (clobber (match_scratch:DI 2 "=&r,&r"))] "TARGET_POWERPC64" - "sradi %2,%1,63\;xor %0,%2,%1\;subf %0,%0,%2" - [(set_attr "length" "12")]) - -(define_split - [(set (match_operand:DI 0 "gpc_reg_operand" "") - (neg:DI (abs:DI (match_operand:DI 1 "gpc_reg_operand" "")))) - (clobber (match_scratch:DI 2 ""))] - "TARGET_POWERPC64 && reload_completed" + "#" + "&& reload_completed" [(set (match_dup 2) (ashiftrt:DI (match_dup 1) (const_int 63))) (set (match_dup 0) (xor:DI (match_dup 2) (match_dup 1))) (set (match_dup 0) (minus:DI (match_dup 2) (match_dup 0)))] @@ -6445,7 +6950,7 @@ [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r") (match_operand:DI 2 "reg_or_cint_operand" "ri")) - (match_operand:DI 3 "mask64_operand" "S")))] + (match_operand:DI 3 "mask64_operand" "n")))] "TARGET_POWERPC64" "rld%I2c%B3 %0,%1,%H2,%S3") @@ -6454,7 +6959,7 @@ (compare:CC (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) - (match_operand:DI 3 "mask64_operand" "S,S")) + (match_operand:DI 3 "mask64_operand" "n,n")) (const_int 0))) (clobber (match_scratch:DI 4 "=r,r"))] "TARGET_POWERPC64" @@ -6487,7 +6992,7 @@ (compare:CC (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (match_operand:DI 2 "reg_or_cint_operand" "ri,ri")) - (match_operand:DI 3 "mask64_operand" "S,S")) + (match_operand:DI 3 "mask64_operand" "n,n")) (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] @@ -6902,7 +7407,7 @@ [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) - (match_operand:DI 3 "mask64_operand" "S")))] + (match_operand:DI 3 "mask64_operand" "n")))] "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" "rldicr %0,%1,%H2,%S3") @@ -6911,7 +7416,7 @@ (compare:CC (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "const_int_operand" "i,i")) - (match_operand:DI 3 "mask64_operand" "S,S")) + (match_operand:DI 3 "mask64_operand" "n,n")) (const_int 0))) (clobber (match_scratch:DI 4 "=r,r"))] "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" @@ -6944,7 +7449,7 @@ (compare:CC (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "const_int_operand" "i,i")) - (match_operand:DI 3 "mask64_operand" "S,S")) + (match_operand:DI 3 "mask64_operand" "n,n")) (const_int 0))) (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] @@ -7059,7 +7564,7 @@ [(set (match_operand:DI 0 "gpc_reg_operand" "") (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_cint_operand" "")))] - "TARGET_POWERPC64 || TARGET_POWER" + "" " { if (TARGET_POWERPC64) @@ -7069,6 +7574,11 @@ emit_insn (gen_ashrdi3_power (operands[0], operands[1], operands[2])); DONE; } + else if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT) + { + emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2])); + DONE; + } else FAIL; }") @@ -7137,24 +7647,47 @@ "") (define_insn "anddi3" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") - (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") - (match_operand:DI 2 "and64_operand" "?r,S,K,J"))) - (clobber (match_scratch:CC 3 "=X,X,x,x"))] + [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r") + (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r") + (match_operand:DI 2 "and64_2_operand" "?r,S,K,J,t"))) + (clobber (match_scratch:CC 3 "=X,X,x,x,X"))] "TARGET_POWERPC64" "@ and %0,%1,%2 rldic%B2 %0,%1,0,%S2 andi. %0,%1,%b2 - andis. %0,%1,%u2") + andis. %0,%1,%u2 + #" + [(set_attr "length" "4,4,4,4,8")]) + +(define_split + [(set (match_operand:DI 0 "gpc_reg_operand" "") + (and:DI (match_operand:DI 1 "gpc_reg_operand" "") + (match_operand:DI 2 "mask64_2_operand" ""))) + (clobber (match_scratch:CC 3 ""))] + "TARGET_POWERPC64 + && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) + && !mask64_operand (operands[2], DImode)" + [(set (match_dup 0) + (and:DI (rotate:DI (match_dup 1) + (match_dup 4)) + (match_dup 5))) + (set (match_dup 0) + (and:DI (rotate:DI (match_dup 0) + (match_dup 6)) + (match_dup 7)))] + " +{ + build_mask64_2_operands (operands[2], &operands[4]); +}") (define_insn "*anddi3_internal2" - [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y") - (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,") - (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J")) + [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") + (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") + (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) (const_int 0))) - (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r")) - (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))] + (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r")) + (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] "TARGET_POWERPC64" "@ and. %3,%1,%2 @@ -7164,9 +7697,11 @@ # # # + # + # #" - [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare") - (set_attr "length" "4,4,4,4,8,8,8,8")]) + [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") + (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) (define_split [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") @@ -7185,14 +7720,39 @@ (const_int 0)))] "") +(define_split + [(set (match_operand:CC 0 "cc_reg_operand" "") + (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") + (match_operand:DI 2 "mask64_2_operand" "")) + (const_int 0))) + (clobber (match_scratch:DI 3 "")) + (clobber (match_scratch:CC 4 ""))] + "TARGET_POWERPC64 && reload_completed + && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) + && !mask64_operand (operands[2], DImode)" + [(set (match_dup 3) + (and:DI (rotate:DI (match_dup 1) + (match_dup 5)) + (match_dup 6))) + (parallel [(set (match_dup 0) + (compare:CC (and:DI (rotate:DI (match_dup 3) + (match_dup 7)) + (match_dup 8)) + (const_int 0))) + (clobber (match_dup 3))])] + " +{ + build_mask64_2_operands (operands[2], &operands[5]); +}") + (define_insn "*anddi3_internal3" - [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,?y,??y,??y") - (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") - (match_operand:DI 2 "and64_operand" "r,S,K,J,r,S,K,J")) + [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,?y,?y,??y,??y,?y") + (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") + (match_operand:DI 2 "and64_2_operand" "r,S,K,J,t,r,S,K,J,t")) (const_int 0))) - (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") + (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r") (and:DI (match_dup 1) (match_dup 2))) - (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,x,x"))] + (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,x,x,X"))] "TARGET_POWERPC64" "@ and. %0,%1,%2 @@ -7202,9 +7762,11 @@ # # # + # + # #" - [(set_attr "type" "compare,delayed_compare,compare,compare,compare,delayed_compare,compare,compare") - (set_attr "length" "4,4,4,4,8,8,8,8")]) + [(set_attr "type" "compare,delayed_compare,compare,compare,delayed_compare,compare,compare,compare,compare,compare") + (set_attr "length" "4,4,4,4,8,8,8,8,8,12")]) (define_split [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") @@ -7223,6 +7785,35 @@ (const_int 0)))] "") +(define_split + [(set (match_operand:CC 3 "cc_reg_operand" "") + (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") + (match_operand:DI 2 "mask64_2_operand" "")) + (const_int 0))) + (set (match_operand:DI 0 "gpc_reg_operand" "") + (and:DI (match_dup 1) (match_dup 2))) + (clobber (match_scratch:CC 4 ""))] + "TARGET_POWERPC64 && reload_completed + && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) + && !mask64_operand (operands[2], DImode)" + [(set (match_dup 0) + (and:DI (rotate:DI (match_dup 1) + (match_dup 5)) + (match_dup 6))) + (parallel [(set (match_dup 3) + (compare:CC (and:DI (rotate:DI (match_dup 0) + (match_dup 7)) + (match_dup 8)) + (const_int 0))) + (set (match_dup 0) + (and:DI (rotate:DI (match_dup 0) + (match_dup 7)) + (match_dup 8)))])] + " +{ + build_mask64_2_operands (operands[2], &operands[5]); +}") + (define_expand "iordi3" [(set (match_operand:DI 0 "gpc_reg_operand" "") (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") @@ -7622,7 +8213,7 @@ (define_insn "movsi_low" [(set (match_operand:SI 0 "gpc_reg_operand" "=r") - (mem:SI (lo_sum:SI (match_operand:SI 1 "register_operand" "b") + (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") (match_operand 2 "" ""))))] "TARGET_MACHO && ! TARGET_64BIT" "{l|lwz} %0,lo16(%2)(%1)" @@ -7630,7 +8221,7 @@ (set_attr "length" "4")]) (define_insn "movsi_low_st" - [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "register_operand" "b") + [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") (match_operand 2 "" ""))) (match_operand:SI 0 "gpc_reg_operand" "r"))] "TARGET_MACHO && ! TARGET_64BIT" @@ -7640,9 +8231,9 @@ (define_insn "movdf_low" [(set (match_operand:DF 0 "gpc_reg_operand" "=f,!r") - (mem:DF (lo_sum:SI (match_operand:SI 1 "register_operand" "b,b") + (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") (match_operand 2 "" ""))))] - "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT" + "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" "* { switch (which_alternative) @@ -7670,19 +8261,19 @@ (set_attr "length" "4,12")]) (define_insn "movdf_low_st" - [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "register_operand" "b") + [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") (match_operand 2 "" ""))) (match_operand:DF 0 "gpc_reg_operand" "f"))] - "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT" + "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" "stfd %0,lo16(%2)(%1)" [(set_attr "type" "store") (set_attr "length" "4")]) (define_insn "movsf_low" [(set (match_operand:SF 0 "gpc_reg_operand" "=f,!r") - (mem:SF (lo_sum:SI (match_operand:SI 1 "register_operand" "b,b") + (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") (match_operand 2 "" ""))))] - "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT" + "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" "@ lfs %0,lo16(%2)(%1) {l|lwz} %0,lo16(%2)(%1)" @@ -7690,10 +8281,10 @@ (set_attr "length" "4")]) (define_insn "movsf_low_st" - [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "register_operand" "b,b") + [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b") (match_operand 2 "" ""))) (match_operand:SF 0 "gpc_reg_operand" "f,!r"))] - "TARGET_MACHO && TARGET_HARD_FLOAT && ! TARGET_64BIT" + "TARGET_MACHO && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_64BIT" "@ stfs %0,lo16(%2)(%1) {st|stw} %0,lo16(%2)(%1)" @@ -7718,7 +8309,7 @@ mt%0 %1 mt%0 %1 mt%0 %1 - cror 0,0,0" + {cror 0,0,0|nop}" [(set_attr "type" "*,*,load,store,*,*,*,*,*,*,mtjmpr,*,*") (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) @@ -7736,9 +8327,12 @@ (ior:SI (match_dup 0) (match_dup 3)))] " -{ - operands[2] = GEN_INT (INTVAL (operands[1]) & (~ (HOST_WIDE_INT) 0xffff)); - operands[3] = GEN_INT (INTVAL (operands[1]) & 0xffff); +{ rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2); + + if (tem == operands[0]) + DONE; + else + FAIL; }") (define_insn "*movsi_internal2" @@ -7771,7 +8365,7 @@ "" "{ rs6000_emit_move (operands[0], operands[1], HImode); DONE; }") -(define_insn "" +(define_insn "*movhi_internal" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] "gpc_reg_operand (operands[0], HImode) @@ -7784,7 +8378,7 @@ mf%1 %0 mt%0 %1 mt%0 %1 - cror 0,0,0" + {cror 0,0,0|nop}" [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) (define_expand "movqi" @@ -7793,7 +8387,7 @@ "" "{ rs6000_emit_move (operands[0], operands[1], QImode); DONE; }") -(define_insn "" +(define_insn "*movqi_internal" [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*q,*c*l,*h") (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,r,0"))] "gpc_reg_operand (operands[0], QImode) @@ -7806,7 +8400,7 @@ mf%1 %0 mt%0 %1 mt%0 %1 - cror 0,0,0" + {cror 0,0,0|nop}" [(set_attr "type" "*,load,store,*,*,*,mtjmpr,*")]) ;; Here is how to move condition codes around. When we store CC data in @@ -7818,9 +8412,9 @@ "" "") -(define_insn "" - [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m") - (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))] +(define_insn "*movcc_internal1" + [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,cl,q,r,r,m") + (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,r,r,h,m,r"))] "register_operand (operands[0], CCmode) || register_operand (operands[1], CCmode)" "@ @@ -7830,10 +8424,13 @@ mfcr %0 mfcr %0\;{rlinm|rlwinm} %0,%0,%f1,0xf0000000 mr %0,%1 + mt%0 %1 + mt%0 %1 + mf%1 %0 {l%U1%X1|lwz%U1%X1} %0,%1 {st%U0%U1|stw%U0%U1} %1,%0" - [(set_attr "type" "*,*,*,compare,*,*,load,store") - (set_attr "length" "*,*,12,*,8,*,*,*")]) + [(set_attr "type" "cr_logical,cr_logical,cr_logical,cr_logical,cr_logical,*,*,mtjmpr,*,load,store") + (set_attr "length" "4,4,12,4,8,4,4,4,4,4,4")]) ;; For floating-point, we normally deal with the floating-point registers ;; unless -msoft-float is used. The sole exception is that parameter passing @@ -7868,14 +8465,15 @@ else operands[2] = gen_lowpart (SImode, operands[0]); - operands[3] = GEN_INT (trunc_int_for_mode (l, SImode)); + operands[3] = gen_int_mode (l, SImode); }") (define_insn "*movsf_hardfloat" - [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!r,!r") - (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,G,Fn"))] + [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!r,!r") + (match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,G,Fn"))] "(gpc_reg_operand (operands[0], SFmode) - || gpc_reg_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT" + || gpc_reg_operand (operands[1], SFmode)) + && (TARGET_HARD_FLOAT && TARGET_FPRS)" "@ mr %0,%1 {l%U1%X1|lwz%U1%X1} %0,%1 @@ -7883,18 +8481,25 @@ fmr %0,%1 lfs%U1%X1 %0,%1 stfs%U0%X0 %1,%0 + mt%0 %1 + mt%0 %1 + mf%1 %0 # #" - [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*") - (set_attr "length" "4,4,4,4,4,4,4,8")]) + [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*") + (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")]) (define_insn "*movsf_softfloat" - [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,r") - (match_operand:SF 1 "input_operand" "r,m,r,I,L,R,G,Fn"))] + [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r") + (match_operand:SF 1 "input_operand" "r,r,r,h,m,r,I,L,R,G,Fn"))] "(gpc_reg_operand (operands[0], SFmode) - || gpc_reg_operand (operands[1], SFmode)) && TARGET_SOFT_FLOAT" + || gpc_reg_operand (operands[1], SFmode)) + && (TARGET_SOFT_FLOAT || !TARGET_FPRS)" "@ mr %0,%1 + mt%0 %1 + mt%0 %1 + mf%1 %0 {l%U1%X1|lwz%U1%X1} %0,%1 {st%U0%X0|stw%U0%X0} %1,%0 {lil|li} %0,%1 @@ -7902,8 +8507,8 @@ {cal|la} %0,%a1 # #" - [(set_attr "type" "*,load,store,*,*,*,*,*") - (set_attr "length" "4,4,4,4,4,4,4,8")]) + [(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*") + (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")]) (define_expand "movdf" @@ -7933,7 +8538,7 @@ operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; #else operands[4] = GEN_INT (value >> 32); - operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000)); + operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); #endif }") @@ -7958,8 +8563,8 @@ operands[2] = operand_subword (operands[0], endian, 0, DFmode); operands[3] = operand_subword (operands[0], 1 - endian, 0, DFmode); - operands[4] = GEN_INT (trunc_int_for_mode (l[endian], SImode)); - operands[5] = GEN_INT (trunc_int_for_mode (l[1 - endian], SImode)); + operands[4] = gen_int_mode (l[endian], SImode); + operands[5] = gen_int_mode (l[1 - endian], SImode); }") (define_split @@ -7984,10 +8589,10 @@ operands[2] = gen_lowpart (DImode, operands[0]); /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ #if HOST_BITS_PER_WIDE_INT >= 64 - val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 | - ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); + val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 + | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); - operands[3] = immed_double_const (val, -(val < 0), DImode); + operands[3] = gen_int_mode (val, DImode); #else operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); #endif @@ -8000,9 +8605,9 @@ ;; The "??" is a kludge until we can figure out a more reasonable way ;; of handling these non-offsettable values. (define_insn "*movdf_hardfloat32" - [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m") - (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))] - "! TARGET_POWERPC64 && TARGET_HARD_FLOAT + [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!r,!r,!r") + (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,G,H,F"))] + "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && (gpc_reg_operand (operands[0], DFmode) || gpc_reg_operand (operands[1], DFmode))" "* @@ -8078,24 +8683,24 @@ return \"\"; } case 3: + return \"fmr %0,%1\"; case 4: + return \"lfd%U1%X1 %0,%1\"; case 5: - return \"#\"; + return \"stfd%U0%X0 %1,%0\"; case 6: - return \"fmr %0,%1\"; case 7: - return \"lfd%U1%X1 %0,%1\"; case 8: - return \"stfd%U0%X0 %1,%0\"; + return \"#\"; } }" - [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") - (set_attr "length" "8,16,16,8,12,16,*,*,*")]) + [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*") + (set_attr "length" "8,16,16,4,4,4,8,12,16")]) (define_insn "*movdf_softfloat32" [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] - "! TARGET_POWERPC64 && TARGET_SOFT_FLOAT + "! TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && (gpc_reg_operand (operands[0], DFmode) || gpc_reg_operand (operands[1], DFmode))" "* @@ -8134,50 +8739,56 @@ (set_attr "length" "8,8,8,8,12,16")]) (define_insn "*movdf_hardfloat64" - [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,!r,!r,!r,f,f,m") - (match_operand:DF 1 "input_operand" "r,m,r,G,H,F,f,m,f"))] - "TARGET_POWERPC64 && TARGET_HARD_FLOAT + [(set (match_operand:DF 0 "nonimmediate_operand" "=!r,??r,m,f,f,m,!cl,!r,!r,!r,!r") + (match_operand:DF 1 "input_operand" "r,m,r,f,m,f,r,h,G,H,F"))] + "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && (gpc_reg_operand (operands[0], DFmode) || gpc_reg_operand (operands[1], DFmode))" "@ mr %0,%1 ld%U1%X1 %0,%1 std%U0%X0 %1,%0 - # - # - # fmr %0,%1 lfd%U1%X1 %0,%1 - stfd%U0%X0 %1,%0" - [(set_attr "type" "*,load,store,*,*,*,fp,fpload,fpstore") - (set_attr "length" "4,4,4,8,12,16,4,4,4")]) + stfd%U0%X0 %1,%0 + mt%0 %1 + mf%1 %0 + # + # + #" + [(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*") + (set_attr "length" "4,4,4,4,4,4,4,4,8,12,16")]) (define_insn "*movdf_softfloat64" - [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,r,r,r") - (match_operand:DF 1 "input_operand" "r,m,r,G,H,F"))] - "TARGET_POWERPC64 && TARGET_SOFT_FLOAT + [(set (match_operand:DF 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r") + (match_operand:DF 1 "input_operand" "r,r,h,m,r,G,H,F"))] + "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) && (gpc_reg_operand (operands[0], DFmode) || gpc_reg_operand (operands[1], DFmode))" "@ mr %0,%1 + mt%0 %1 + mf%1 %0 ld%U1%X1 %0,%1 std%U0%X0 %1,%0 # # #" - [(set_attr "type" "*,load,store,*,*,*") - (set_attr "length" "*,*,*,8,12,16")]) + [(set_attr "type" "*,*,*,load,store,*,*,*") + (set_attr "length" "4,4,4,4,4,8,12,16")]) (define_expand "movtf" [(set (match_operand:TF 0 "general_operand" "") (match_operand:TF 1 "any_operand" ""))] - "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" + "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS + && TARGET_LONG_DOUBLE_128" "{ rs6000_emit_move (operands[0], operands[1], TFmode); DONE; }") (define_insn "*movtf_internal" [(set (match_operand:TF 0 "nonimmediate_operand" "=f,f,m,!r,!r,!r") (match_operand:TF 1 "input_operand" "f,m,f,G,H,F"))] - "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128 + "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS + && TARGET_LONG_DOUBLE_128 && (gpc_reg_operand (operands[0], TFmode) || gpc_reg_operand (operands[1], TFmode))" "* @@ -8195,9 +8806,9 @@ else return \"fmr %0,%1\;fmr %L0,%L1\"; case 1: - return \"lfd %0,%1\;lfd %L0,%L1\"; + return \"lfd %0,%1\;lfd %L0,%Y1\"; case 2: - return \"stfd %1,%0\;stfd %L1,%L0\"; + return \"stfd %1,%0\;stfd %L1,%Y0\"; case 3: case 4: case 5: @@ -8209,104 +8820,185 @@ (define_split [(set (match_operand:TF 0 "gpc_reg_operand" "") - (match_operand:TF 1 "const_double_operand" ""))] - "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" - [(set (match_dup 3) (match_dup 1)) - (set (match_dup 0) - (float_extend:TF (match_dup 3)))] + (match_operand:TF 1 "easy_fp_constant" ""))] + "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) + && TARGET_HARD_FLOAT && TARGET_FPRS && ! TARGET_POWERPC64 + && TARGET_LONG_DOUBLE_128 && reload_completed + && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) + || (GET_CODE (operands[0]) == SUBREG + && GET_CODE (SUBREG_REG (operands[0])) == REG + && REGNO (SUBREG_REG (operands[0])) <= 31))" + [(set (match_dup 2) (match_dup 6)) + (set (match_dup 3) (match_dup 7)) + (set (match_dup 4) (match_dup 8)) + (set (match_dup 5) (match_dup 9))] " { - operands[2] = operand_subword (operands[1], 0, 0, DFmode); - operands[3] = gen_reg_rtx (DFmode); + long l[4]; + REAL_VALUE_TYPE rv; + + REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); + REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, l); + + operands[2] = operand_subword (operands[0], 0, 0, TFmode); + operands[3] = operand_subword (operands[0], 1, 0, TFmode); + operands[4] = operand_subword (operands[0], 2, 0, TFmode); + operands[5] = operand_subword (operands[0], 3, 0, TFmode); + operands[6] = gen_int_mode (l[0], SImode); + operands[7] = gen_int_mode (l[1], SImode); + operands[8] = gen_int_mode (l[2], SImode); + operands[9] = gen_int_mode (l[3], SImode); }") -(define_insn_and_split "extenddftf2" - [(set (match_operand:TF 0 "gpc_reg_operand" "=f") - (float_extend:TF (match_operand:DF 1 "gpc_reg_operand" "f")))] - "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" - "#" - "" - [(set (match_dup 2) (match_dup 3))] +(define_split + [(set (match_operand:TF 0 "gpc_reg_operand" "") + (match_operand:TF 1 "easy_fp_constant" ""))] + "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) + && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 + && TARGET_LONG_DOUBLE_128 && reload_completed + && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) + || (GET_CODE (operands[0]) == SUBREG + && GET_CODE (SUBREG_REG (operands[0])) == REG + && REGNO (SUBREG_REG (operands[0])) <= 31))" + [(set (match_dup 2) (match_dup 4)) + (set (match_dup 3) (match_dup 5))] " { - operands[2] = gen_rtx_REG (DFmode, REGNO (operands[0] + 1)); - operands[3] = CONST0_RTX (DFmode); + long l[4]; + REAL_VALUE_TYPE rv; + HOST_WIDE_INT val; + + REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); + REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, l); + + operands[2] = gen_lowpart (DImode, operands[0]); + operands[3] = gen_highpart (DImode, operands[0]); +#if HOST_BITS_PER_WIDE_INT >= 64 + val = ((HOST_WIDE_INT)(unsigned long)l[0] << 32 + | ((HOST_WIDE_INT)(unsigned long)l[1])); + operands[4] = gen_int_mode (val, DImode); + + val = ((HOST_WIDE_INT)(unsigned long)l[2] << 32 + | ((HOST_WIDE_INT)(unsigned long)l[3])); + operands[5] = gen_int_mode (val, DImode); +#else + operands[4] = immed_double_const (l[1], l[0], DImode); + operands[5] = immed_double_const (l[3], l[2], DImode); +#endif }") -(define_insn_and_split "extendsftf2" +(define_insn "extenddftf2" + [(set (match_operand:TF 0 "gpc_reg_operand" "=f") + (float_extend:TF (match_operand:DF 1 "gpc_reg_operand" "f")))] + "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS + && TARGET_LONG_DOUBLE_128" + "* +{ + if (REGNO (operands[0]) == REGNO (operands[1])) + return \"fsub %L0,%L0,%L0\"; + else + return \"fmr %0,%1\;fsub %L0,%L0,%L0\"; +}" + [(set_attr "type" "fp")]) + +(define_insn "extendsftf2" [(set (match_operand:TF 0 "gpc_reg_operand" "=f") (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "f")))] - "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" - "#" - "" - [(set (match_dup 2) (match_dup 3))] - " + "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS + && TARGET_LONG_DOUBLE_128" + "* { - operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0] + 1)); - operands[3] = CONST0_RTX (SFmode); -}") + if (REGNO (operands[0]) == REGNO (operands[1])) + return \"fsub %L0,%L0,%L0\"; + else + return \"fmr %0,%1\;fsub %L0,%L0,%L0\"; +}" + [(set_attr "type" "fp")]) (define_insn "trunctfdf2" [(set (match_operand:DF 0 "gpc_reg_operand" "=f") (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "f")))] - "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" + "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS + && TARGET_LONG_DOUBLE_128" "fadd %0,%1,%L1" [(set_attr "type" "fp") (set_attr "length" "8")]) (define_insn_and_split "trunctfsf2" [(set (match_operand:SF 0 "gpc_reg_operand" "=f") - (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f")))] - "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" + (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "f"))) + (clobber (match_scratch:DF 2 "=f"))] + "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT + && TARGET_FPRS && TARGET_LONG_DOUBLE_128" "#" - "" + "&& reload_completed" [(set (match_dup 2) (float_truncate:DF (match_dup 1))) (set (match_dup 0) (float_truncate:SF (match_dup 2)))] - " -{ - operands[2] = gen_reg_rtx (DFmode); -}") + "") -(define_expand "floatditf2" +(define_insn_and_split "floatditf2" + [(set (match_operand:TF 0 "gpc_reg_operand" "=f") + (float:TF (match_operand:DI 1 "gpc_reg_operand" "*f"))) + (clobber (match_scratch:DF 2 "=f"))] + "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64 + && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" + "#" + "&& reload_completed" [(set (match_dup 2) - (float:DF (match_operand:DI 1 "gpc_reg_operand" ""))) - (set (match_operand:TF 0 "gpc_reg_operand" "") + (float:DF (match_dup 1))) + (set (match_dup 0) (float_extend:TF (match_dup 2)))] - "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64 - && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" - "{ operands[2] = gen_reg_rtx (DFmode); }") + "") -(define_expand "floatsitf2" +(define_insn_and_split "floatsitf2" + [(set (match_operand:TF 0 "gpc_reg_operand" "=f") + (float:TF (match_operand:SI 1 "gpc_reg_operand" "r"))) + (clobber (match_scratch:DF 2 "=f"))] + "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS + && TARGET_LONG_DOUBLE_128" + "#" + "&& reload_completed" [(set (match_dup 2) - (float:DF (match_operand:SI 1 "gpc_reg_operand" ""))) - (set (match_operand:TF 0 "gpc_reg_operand" "") + (float:DF (match_dup 1))) + (set (match_dup 0) (float_extend:TF (match_dup 2)))] - "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" - "{ operands[2] = gen_reg_rtx (DFmode); }") + "") -(define_expand "fix_trunctfdi2" - [(set (match_dup 2) - (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" ""))) - (set (match_operand:DI 0 "gpc_reg_operand" "") - (fix:SI (match_dup 2)))] +(define_insn_and_split "fix_trunctfdi2" + [(set (match_operand:DI 0 "gpc_reg_operand" "=*f") + (fix:DI (match_operand:TF 1 "gpc_reg_operand" "f"))) + (clobber (match_scratch:DF 2 "=f"))] "DEFAULT_ABI == ABI_AIX && TARGET_POWERPC64 - && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" - "{ operands[2] = gen_reg_rtx (DFmode); }") + && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" + "#" + "&& reload_completed" + [(set (match_dup 2) + (float_truncate:DF (match_dup 1))) + (set (match_dup 0) + (fix:DI (match_dup 2)))] + "") -(define_expand "fix_trunctfsi2" +(define_insn_and_split "fix_trunctfsi2" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (fix:SI (match_operand:TF 1 "gpc_reg_operand" "f"))) + (clobber (match_scratch:DF 2 "=f"))] + "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS + && TARGET_LONG_DOUBLE_128" + "#" + "&& reload_completed" [(set (match_dup 2) - (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" ""))) - (set (match_operand:SI 0 "gpc_reg_operand" "") + (float_truncate:DF (match_dup 1))) + (set (match_dup 0) (fix:SI (match_dup 2)))] - "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" - "{ operands[2] = gen_reg_rtx (DFmode); }") + "") (define_insn "negtf2" [(set (match_operand:TF 0 "gpc_reg_operand" "=f") (neg:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] - "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" + "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS + && TARGET_LONG_DOUBLE_128" "* { if (REGNO (operands[0]) == REGNO (operands[1]) + 1) @@ -8320,7 +9012,8 @@ (define_insn "abstf2" [(set (match_operand:TF 0 "gpc_reg_operand" "=f") (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f")))] - "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" + "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS + && TARGET_LONG_DOUBLE_128" "* { if (REGNO (operands[0]) == REGNO (operands[1]) + 1) @@ -8334,7 +9027,8 @@ (define_insn "" [(set (match_operand:TF 0 "gpc_reg_operand" "=f") (neg:TF (abs:TF (match_operand:TF 1 "gpc_reg_operand" "f"))))] - "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" + "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS + && TARGET_LONG_DOUBLE_128" "* { if (REGNO (operands[0]) == REGNO (operands[1]) + 1) @@ -8400,7 +9094,7 @@ } }" [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,*,*,*,*") - (set_attr "length" "8,8,8,*,*,*,8,12,8,12,16")]) + (set_attr "length" "8,8,8,4,4,4,8,12,8,12,16")]) (define_split [(set (match_operand:DI 0 "gpc_reg_operand" "") @@ -8419,7 +9113,7 @@ operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; #else operands[4] = GEN_INT (value >> 32); - operands[1] = GEN_INT ((value & 0x7fffffff) - (value & 0x80000000)); + operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); #endif }") @@ -8439,8 +9133,34 @@ operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); }") +(define_split + [(set (match_operand:TI 0 "gpc_reg_operand" "") + (match_operand:TI 1 "const_double_operand" ""))] + "TARGET_POWERPC64" + [(set (match_dup 2) (match_dup 4)) + (set (match_dup 3) (match_dup 5))] + " +{ + operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, + TImode); + operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, + TImode); + if (GET_CODE (operands[1]) == CONST_DOUBLE) + { + operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); + operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); + } + else if (GET_CODE (operands[1]) == CONST_INT) + { + operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0)); + operands[5] = operands[1]; + } + else + FAIL; +}") + (define_insn "*movdi_internal64" - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,f,f,m,r,*h,*h") + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,r,r,r,?f,f,m,r,*h,*h") (match_operand:DI 1 "input_operand" "r,m,r,I,L,nF,R,f,m,f,*h,r,0"))] "TARGET_POWERPC64 && (gpc_reg_operand (operands[0], DImode) @@ -8458,7 +9178,7 @@ stfd%U0%X0 %1,%0 mf%1 %0 mt%0 %1 - cror 0,0,0" + {cror 0,0,0|nop}" [(set_attr "type" "*,load,store,*,*,*,*,fp,fpload,fpstore,*,mtjmpr,*") (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")]) @@ -8615,12 +9335,11 @@ } }" [(set_attr "type" "store,store,*,load,load") - (set_attr "length" "*,16,16,*,16")]) + (set_attr "length" "4,16,16,4,16")]) (define_insn "*movti_string" - [(set (match_operand:TI 0 "reg_or_mem_operand" "=m,????r,????r") - (match_operand:TI 1 "reg_or_mem_operand" "r,r,m")) - (clobber (match_scratch:SI 2 "=X,X,X"))] + [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,????r,????r,????r") + (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))] "TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64 && (gpc_reg_operand (operands[0], TImode) || gpc_reg_operand (operands[1], TImode))" "* @@ -8631,9 +9350,10 @@ abort (); case 0: - return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; - + return \"{stsi|stswi} %1,%P0,16\"; case 1: + return \"{st%U0|stw%U0} %1,%0\;{st|stw} %L1,%L0\;{st|stw} %Y1,%Y0\;{st|stw} %Z1,%Z0\"; + case 2: /* Normally copy registers with lowest numbered register copied first. But copy in the other order if the first register of the output is the second, third, or fourth register in the input. */ @@ -8642,7 +9362,13 @@ return \"mr %Z0,%Z1\;mr %Y0,%Y1\;mr %L0,%L1\;mr %0,%1\"; else return \"mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1\"; - case 2: + case 3: + /* If the address is not used in the output, we can use lsi. Otherwise, + fall through to generating four loads. */ + if (! reg_overlap_mentioned_p (operands[0], operands[1])) + return \"{lsi|lswi} %0,%P1,16\"; + /* ... fall through ... */ + case 4: /* If the address register is the same as the register for the lowest- addressed word, load it last. Similarly for the next two words. Otherwise load lowest address to highest. */ @@ -8659,8 +9385,8 @@ return \"{l%U1|lwz%U1} %0,%1\;{l|lwz} %L0,%L1\;{l|lwz} %Y0,%Y1\;{l|lwz} %Z0,%Z1\"; } }" - [(set_attr "type" "store,*,load") - (set_attr "length" "16,16,16")]) + [(set_attr "type" "store,store,*,load,load") + (set_attr "length" "4,16,16,4,16")]) (define_insn "*movti_ppc64" [(set (match_operand:TI 0 "nonimmediate_operand" "=r,r,m") @@ -8731,7 +9457,7 @@ for (i = 0; i < count; i++) XVECEXP (operands[3], 0, i) = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), - adjust_address (op1, SImode, i * 4)); + adjust_address_nv (op1, SImode, i * 4)); }") (define_insn "*ldmsi8" @@ -8881,14 +9607,14 @@ op0 = replace_equiv_address (operands[0], to); XVECEXP (operands[3], 0, 0) - = gen_rtx_SET (VOIDmode, adjust_address (op0, SImode, 0), operands[1]); + = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]); XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)); for (i = 1; i < count; i++) XVECEXP (operands[3], 0, i + 1) = gen_rtx_SET (VOIDmode, - adjust_address (op0, SImode, i * 4), + adjust_address_nv (op0, SImode, i * 4), gen_rtx_REG (SImode, regno + i)); }") @@ -9426,7 +10152,7 @@ (match_operand:SI 2 "reg_or_short_operand" "r,I")))) (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] - "TARGET_HARD_FLOAT && TARGET_UPDATE" + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" "@ lfsux %3,%0,%2 lfsu %3,%2(%0)" @@ -9438,7 +10164,7 @@ (match_operand:SF 3 "gpc_reg_operand" "f,f")) (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] - "TARGET_HARD_FLOAT && TARGET_UPDATE" + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" "@ stfsux %3,%0,%2 stfsu %3,%2(%0)" @@ -9450,7 +10176,7 @@ (match_operand:SI 2 "reg_or_short_operand" "r,I")))) (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] - "TARGET_SOFT_FLOAT && TARGET_UPDATE" + "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" "@ {lux|lwzux} %3,%0,%2 {lu|lwzu} %3,%2(%0)" @@ -9462,7 +10188,7 @@ (match_operand:SF 3 "gpc_reg_operand" "r,r")) (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] - "TARGET_SOFT_FLOAT && TARGET_UPDATE" + "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE" "@ {stux|stwux} %3,%0,%2 {stu|stwu} %3,%2(%0)" @@ -9474,7 +10200,7 @@ (match_operand:SI 2 "reg_or_short_operand" "r,I")))) (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] - "TARGET_HARD_FLOAT && TARGET_UPDATE" + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" "@ lfdux %3,%0,%2 lfdu %3,%2(%0)" @@ -9486,7 +10212,7 @@ (match_operand:DF 3 "gpc_reg_operand" "f,f")) (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] - "TARGET_HARD_FLOAT && TARGET_UPDATE" + "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_UPDATE" "@ stfdux %3,%0,%2 stfdu %3,%2(%0)" @@ -9500,7 +10226,7 @@ (set (match_operand:DF 2 "gpc_reg_operand" "=f") (match_operand:DF 3 "memory_operand" ""))] "TARGET_POWER2 - && TARGET_HARD_FLOAT + && TARGET_HARD_FLOAT && TARGET_FPRS && registers_ok_for_quad_peep (operands[0], operands[2]) && ! MEM_VOLATILE_P (operands[1]) && ! MEM_VOLATILE_P (operands[3]) && addrs_ok_for_quad_peep (XEXP (operands[1], 0), XEXP (operands[3], 0))" @@ -9512,7 +10238,7 @@ (set (match_operand:DF 2 "memory_operand" "") (match_operand:DF 3 "gpc_reg_operand" "f"))] "TARGET_POWER2 - && TARGET_HARD_FLOAT + && TARGET_HARD_FLOAT && TARGET_FPRS && registers_ok_for_quad_peep (operands[1], operands[3]) && ! MEM_VOLATILE_P (operands[0]) && ! MEM_VOLATILE_P (operands[2]) && addrs_ok_for_quad_peep (XEXP (operands[0], 0), XEXP (operands[2], 0))" @@ -9697,7 +10423,7 @@ (match_operand:SI 1 "immediate_operand" "s")) (unspec [(match_dup 1)] 7)] "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" - "bl %1\\n%1:" + "bcl 20,31,%1\\n%1:" [(set_attr "type" "branch") (set_attr "length" "4")]) @@ -9706,13 +10432,13 @@ (match_operand:SI 1 "immediate_operand" "s")) (unspec [(match_dup 1) (match_operand 2 "immediate_operand" "s")] 6)] "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" - "bl %1\\n\\t.long %2-%1+4\\n%1:" + "bcl 20,31,%1\\n\\t.long %2-%1+4\\n%1:" [(set_attr "type" "branch") (set_attr "length" "8")]) (define_insn "load_toc_v4_PIC_2" - [(set (match_operand:SI 0 "register_operand" "=r") - (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "b") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") (minus:SI (match_operand:SI 2 "immediate_operand" "s") (match_operand:SI 3 "immediate_operand" "s")))))] "TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2" @@ -9721,30 +10447,53 @@ (define_insn "load_macho_picbase" [(set (match_operand:SI 0 "register_operand" "=l") - (unspec:SI [(const_int 0)] 15))] + (unspec:SI [(match_operand:SI 1 "immediate_operand" "s")] 15))] "(DEFAULT_ABI == ABI_DARWIN) && flag_pic" - "* -{ -#if TARGET_MACHO - char *picbase = machopic_function_base_name (); - operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1)); -#endif - return \"bcl 20,31,%1\\n%1:\"; -}" + "bcl 20,31,%1\\n%1:" [(set_attr "type" "branch") (set_attr "length" "4")]) +(define_insn "macho_correct_pic" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (plus:SI (match_operand:SI 1 "gpc_reg_operand" "=r") + (unspec:SI [(match_operand:SI 2 "immediate_operand" "s") + (match_operand:SI 3 "immediate_operand" "s")] + 16)))] + "DEFAULT_ABI == ABI_DARWIN" + "addis %0,%1,ha16(%2-%3)\n\taddi %1,%1,lo16(%2-%3)" + [(set_attr "length" "8")]) + ;; If the TOC is shared over a translation unit, as happens with all ;; the kinds of PIC that we support, we need to restore the TOC ;; pointer only when jumping over units of translation. +;; On Darwin, we need to reload the picbase. (define_expand "builtin_setjmp_receiver" [(use (label_ref (match_operand 0 "" "")))] "(DEFAULT_ABI == ABI_V4 && flag_pic == 1) - || (TARGET_TOC && TARGET_MINIMAL_TOC)" + || (TARGET_TOC && TARGET_MINIMAL_TOC) + || (DEFAULT_ABI == ABI_DARWIN && flag_pic)" " { - rs6000_emit_load_toc_table (FALSE); +#if TARGET_MACHO + if (DEFAULT_ABI == ABI_DARWIN) + { + char *picbase = machopic_function_base_name (); + rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (picbase, -1)); + rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); + rtx tmplabrtx; + char tmplab[20]; + + ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\", + CODE_LABEL_NUMBER (operands[0])); + tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string (tmplab, -1)); + + emit_insn (gen_load_macho_picbase (picreg, tmplabrtx)); + emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx)); + } + else +#endif + rs6000_emit_load_toc_table (FALSE); DONE; }") @@ -9943,7 +10692,7 @@ }") ;; Call to function in current module. No TOC pointer reload needed. -;; Operand2 is non-zero if we are using the V.4 calling sequence and +;; Operand2 is nonzero if we are using the V.4 calling sequence and ;; either the function was not prototyped, or it was prototyped as a ;; variable argument function. It is > 0 if FP registers were passed ;; and < 0 if they were not. @@ -10029,7 +10778,7 @@ ;; Call to function which may be in another module. Restore the TOC ;; pointer (r2) after the call unless this is System V. -;; Operand2 is non-zero if we are using the V.4 calling sequence and +;; Operand2 is nonzero if we are using the V.4 calling sequence and ;; either the function was not prototyped, or it was prototyped as a ;; variable argument function. It is > 0 if FP registers were passed ;; and < 0 if they were not. @@ -10048,7 +10797,7 @@ (set_attr "length" "8")]) (define_insn "*call_nonlocal_aix32" - [(call (mem:SI (match_operand:SI 0 "call_operand" "s")) + [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) (match_operand 1 "" "g")) (use (match_operand:SI 2 "immediate_operand" "O")) (clobber (match_scratch:SI 3 "=l"))] @@ -10073,7 +10822,7 @@ (set_attr "length" "8")]) (define_insn "*call_nonlocal_aix64" - [(call (mem:SI (match_operand:DI 0 "call_operand" "s")) + [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) (match_operand 1 "" "g")) (use (match_operand:SI 2 "immediate_operand" "O")) (clobber (match_scratch:SI 3 "=l"))] @@ -10100,7 +10849,7 @@ (define_insn "*call_value_nonlocal_aix32" [(set (match_operand 0 "" "") - (call (mem:SI (match_operand:SI 1 "call_operand" "s")) + (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) (match_operand 2 "" "g"))) (use (match_operand:SI 3 "immediate_operand" "O")) (clobber (match_scratch:SI 4 "=l"))] @@ -10127,7 +10876,7 @@ (define_insn "*call_value_nonlocal_aix64" [(set (match_operand 0 "" "") - (call (mem:SI (match_operand:DI 1 "call_operand" "s")) + (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) (match_operand 2 "" "g"))) (use (match_operand:SI 3 "immediate_operand" "O")) (clobber (match_scratch:SI 4 "=l"))] @@ -10144,68 +10893,89 @@ ;; operands[2] is the value FUNCTION_ARG returns for the VOID argument ;; which indicates how to set cr1 -(define_insn "*call_nonlocal_sysv" - [(call (mem:SI (match_operand:SI 0 "call_operand" "cl,cl,s,s")) - (match_operand 1 "" "g,g,g,g")) - (use (match_operand:SI 2 "immediate_operand" "O,n,O,n")) - (clobber (match_scratch:SI 3 "=l,l,l,l"))] +(define_insn "*call_indirect_nonlocal_sysv" + [(call (mem:SI (match_operand:SI 0 "register_operand" "cl,cl")) + (match_operand 1 "" "g,g")) + (use (match_operand:SI 2 "immediate_operand" "O,n")) + (clobber (match_scratch:SI 3 "=l,l"))] "DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN" - "* { if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) - output_asm_insn (\"crxor 6,6,6\", operands); + output_asm_insn ("crxor 6,6,6", operands); else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) - output_asm_insn (\"creqv 6,6,6\", operands); + output_asm_insn ("creqv 6,6,6", operands); - switch (which_alternative) - { - default: - abort (); - case 0: - case 1: - return \"b%T0l\"; - case 2: - case 3: - return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@plt\" : \"bl %z0\"; - } -}" - [(set_attr "type" "jmpreg,jmpreg,branch,branch") - (set_attr "length" "4,8,4,8")]) + return "b%T0l"; +} + [(set_attr "type" "jmpreg,jmpreg") + (set_attr "length" "4,8")]) -(define_insn "*call_value_nonlocal_sysv" +(define_insn "*call_nonlocal_sysv" + [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) + (match_operand 1 "" "g,g")) + (use (match_operand:SI 2 "immediate_operand" "O,n")) + (clobber (match_scratch:SI 3 "=l,l"))] + "(DEFAULT_ABI == ABI_AIX_NODESC + || DEFAULT_ABI == ABI_V4 + || DEFAULT_ABI == ABI_DARWIN) + && (INTVAL (operands[2]) & CALL_LONG) == 0" +{ + if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) + output_asm_insn ("crxor 6,6,6", operands); + + else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) + output_asm_insn ("creqv 6,6,6", operands); + + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z0@plt" : "bl %z0"; +} + [(set_attr "type" "branch,branch") + (set_attr "length" "4,8")]) + +(define_insn "*call_value_indirect_nonlocal_sysv" [(set (match_operand 0 "" "") - (call (mem:SI (match_operand:SI 1 "call_operand" "cl,cl,s,s")) - (match_operand 2 "" "g,g,g,g"))) - (use (match_operand:SI 3 "immediate_operand" "O,n,O,n")) - (clobber (match_scratch:SI 4 "=l,l,l,l"))] + (call (mem:SI (match_operand:SI 1 "register_operand" "cl,cl")) + (match_operand 2 "" "g,g"))) + (use (match_operand:SI 3 "immediate_operand" "O,n")) + (clobber (match_scratch:SI 4 "=l,l"))] "DEFAULT_ABI == ABI_AIX_NODESC || DEFAULT_ABI == ABI_V4 || DEFAULT_ABI == ABI_DARWIN" - "* { if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) - output_asm_insn (\"crxor 6,6,6\", operands); + output_asm_insn ("crxor 6,6,6", operands); else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) - output_asm_insn (\"creqv 6,6,6\", operands); + output_asm_insn ("creqv 6,6,6", operands); - switch (which_alternative) - { - default: - abort (); - case 0: - case 1: - return \"b%T1l\"; - case 2: - case 3: - return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@plt\" : \"bl %z1\"; - } -}" - [(set_attr "type" "jmpreg,jmpreg,branch,branch") - (set_attr "length" "4,8,4,8")]) + return "b%T1l"; +} + [(set_attr "type" "jmpreg,jmpreg") + (set_attr "length" "4,8")]) + +(define_insn "*call_value_nonlocal_sysv" + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) + (match_operand 2 "" "g,g"))) + (use (match_operand:SI 3 "immediate_operand" "O,n")) + (clobber (match_scratch:SI 4 "=l,l"))] + "(DEFAULT_ABI == ABI_AIX_NODESC + || DEFAULT_ABI == ABI_V4 + || DEFAULT_ABI == ABI_DARWIN) + && (INTVAL (operands[3]) & CALL_LONG) == 0" +{ + if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) + output_asm_insn ("crxor 6,6,6", operands); + + else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) + output_asm_insn ("creqv 6,6,6", operands); + + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? "bl %z1@plt" : "bl %z1"; +} + [(set_attr "type" "branch,branch") + (set_attr "length" "4,8")]) ;; Call subroutine returning any type. (define_expand "untyped_call" @@ -10235,6 +11005,247 @@ DONE; }") +;; sibling call patterns +(define_expand "sibcall" + [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) + (match_operand 1 "" "")) + (use (match_operand 2 "" "")) + (use (scratch:SI)) + (return)])] + "" + " +{ +#if TARGET_MACHO + if (flag_pic) + operands[0] = machopic_indirect_call_target (operands[0]); +#endif + + if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT) + abort (); + + operands[0] = XEXP (operands[0], 0); + +}") + +;; this and similar patterns must be marked as using LR, otherwise +;; dataflow will try to delete the store into it. This is true +;; even when the actual reg to jump to is in CTR, when LR was +;; saved and restored around the PIC-setting BCL. +(define_insn "*sibcall_local32" + [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) + (match_operand 1 "" "g,g")) + (use (match_operand:SI 2 "immediate_operand" "O,n")) + (use (match_scratch:SI 3 "=l,l")) + (return)] + "(INTVAL (operands[2]) & CALL_LONG) == 0" + "* +{ + if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) + output_asm_insn (\"crxor 6,6,6\", operands); + + else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) + output_asm_insn (\"creqv 6,6,6\", operands); + + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; +}" + [(set_attr "type" "branch") + (set_attr "length" "4,8")]) + +(define_insn "*sibcall_local64" + [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) + (match_operand 1 "" "g,g")) + (use (match_operand:SI 2 "immediate_operand" "O,n")) + (use (match_scratch:SI 3 "=l,l")) + (return)] + "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" + "* +{ + if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) + output_asm_insn (\"crxor 6,6,6\", operands); + + else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) + output_asm_insn (\"creqv 6,6,6\", operands); + + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; +}" + [(set_attr "type" "branch") + (set_attr "length" "4,8")]) + +(define_insn "*sibcall_value_local32" + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) + (match_operand 2 "" "g,g"))) + (use (match_operand:SI 3 "immediate_operand" "O,n")) + (use (match_scratch:SI 4 "=l,l")) + (return)] + "(INTVAL (operands[3]) & CALL_LONG) == 0" + "* +{ + if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) + output_asm_insn (\"crxor 6,6,6\", operands); + + else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) + output_asm_insn (\"creqv 6,6,6\", operands); + + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; +}" + [(set_attr "type" "branch") + (set_attr "length" "4,8")]) + + +(define_insn "*sibcall_value_local64" + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) + (match_operand 2 "" "g,g"))) + (use (match_operand:SI 3 "immediate_operand" "O,n")) + (use (match_scratch:SI 4 "=l,l")) + (return)] + "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" + "* +{ + if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) + output_asm_insn (\"crxor 6,6,6\", operands); + + else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) + output_asm_insn (\"creqv 6,6,6\", operands); + + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; +}" + [(set_attr "type" "branch") + (set_attr "length" "4,8")]) + +(define_insn "*sibcall_nonlocal_aix32" + [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s")) + (match_operand 1 "" "g")) + (use (match_operand:SI 2 "immediate_operand" "O")) + (use (match_scratch:SI 3 "=l")) + (return)] + "TARGET_32BIT + && DEFAULT_ABI == ABI_AIX + && (INTVAL (operands[2]) & CALL_LONG) == 0" + "b %z0" + [(set_attr "type" "branch") + (set_attr "length" "4")]) + +(define_insn "*sibcall_nonlocal_aix64" + [(call (mem:SI (match_operand:DI 0 "symbol_ref_operand" "s")) + (match_operand 1 "" "g")) + (use (match_operand:SI 2 "immediate_operand" "O")) + (use (match_scratch:SI 3 "=l")) + (return)] + "TARGET_64BIT + && DEFAULT_ABI == ABI_AIX + && (INTVAL (operands[2]) & CALL_LONG) == 0" + "b %z0" + [(set_attr "type" "branch") + (set_attr "length" "4")]) + +(define_insn "*sibcall_value_nonlocal_aix32" + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s")) + (match_operand 2 "" "g"))) + (use (match_operand:SI 3 "immediate_operand" "O")) + (use (match_scratch:SI 4 "=l")) + (return)] + "TARGET_32BIT + && DEFAULT_ABI == ABI_AIX + && (INTVAL (operands[3]) & CALL_LONG) == 0" + "b %z1" + [(set_attr "type" "branch") + (set_attr "length" "4")]) + +(define_insn "*sibcall_value_nonlocal_aix64" + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:DI 1 "symbol_ref_operand" "s")) + (match_operand 2 "" "g"))) + (use (match_operand:SI 3 "immediate_operand" "O")) + (use (match_scratch:SI 4 "=l")) + (return)] + "TARGET_64BIT + && DEFAULT_ABI == ABI_AIX + && (INTVAL (operands[3]) & CALL_LONG) == 0" + "b %z1" + [(set_attr "type" "branch") + (set_attr "length" "4")]) + +(define_insn "*sibcall_nonlocal_sysv" + [(call (mem:SI (match_operand:SI 0 "symbol_ref_operand" "s,s")) + (match_operand 1 "" "")) + (use (match_operand 2 "immediate_operand" "O,n")) + (use (match_scratch:SI 3 "=l,l")) + (return)] + "(DEFAULT_ABI == ABI_DARWIN + || DEFAULT_ABI == ABI_V4 + || DEFAULT_ABI == ABI_AIX_NODESC) + && (INTVAL (operands[2]) & CALL_LONG) == 0" + "* +{ + if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) + output_asm_insn (\"crxor 6,6,6\", operands); + + else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) + output_asm_insn (\"creqv 6,6,6\", operands); + + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@plt\" : \"b %z0\"; +}" + [(set_attr "type" "branch,branch") + (set_attr "length" "4,8")]) + +(define_expand "sibcall_value" + [(parallel [(set (match_operand 0 "register_operand" "") + (call (mem:SI (match_operand 1 "address_operand" "")) + (match_operand 2 "" ""))) + (use (match_operand 3 "" "")) + (use (scratch:SI)) + (return)])] + "" + " +{ +#if TARGET_MACHO + if (flag_pic) + operands[1] = machopic_indirect_call_target (operands[1]); +#endif + + if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT) + abort (); + + operands[1] = XEXP (operands[1], 0); + +}") + +(define_insn "*sibcall_value_nonlocal_sysv" + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:SI 1 "symbol_ref_operand" "s,s")) + (match_operand 2 "" ""))) + (use (match_operand:SI 3 "immediate_operand" "O,n")) + (use (match_scratch:SI 4 "=l,l")) + (return)] + "(DEFAULT_ABI == ABI_DARWIN + || DEFAULT_ABI == ABI_V4 + || DEFAULT_ABI == ABI_AIX_NODESC) + && (INTVAL (operands[3]) & CALL_LONG) == 0" + "* +{ + if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) + output_asm_insn (\"crxor 6,6,6\", operands); + + else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) + output_asm_insn (\"creqv 6,6,6\", operands); + + return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@plt\" : \"b %z1\"; +}" + [(set_attr "type" "branch,branch") + (set_attr "length" "4,8")]) + +(define_expand "sibcall_epilogue" + [(use (const_int 0))] + "TARGET_SCHED_PROLOG" + " +{ + rs6000_emit_epilogue (TRUE); + DONE; +}") + ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and ;; all of memory. This blocks insns from being moved across this point. @@ -10302,7 +11313,7 @@ (define_expand "cmpdf" [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") (match_operand:DF 1 "gpc_reg_operand" "")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && TARGET_FPRS" " { rs6000_compare_op0 = operands[0]; @@ -10314,7 +11325,8 @@ (define_expand "cmptf" [(set (cc0) (compare (match_operand:TF 0 "gpc_reg_operand" "") (match_operand:TF 1 "gpc_reg_operand" "")))] - "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" + "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT + && TARGET_FPRS && TARGET_LONG_DOUBLE_128" " { rs6000_compare_op0 = operands[0]; @@ -10549,7 +11561,7 @@ with C to get the sign-extended value. */ HOST_WIDE_INT c = INTVAL (operands[2]); - HOST_WIDE_INT sextc = (c & 0x7fff) - (c & 0x8000); + HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000; HOST_WIDE_INT xorv = c ^ sextc; operands[4] = GEN_INT (xorv); @@ -10621,7 +11633,7 @@ [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") (match_operand:SF 2 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && TARGET_FPRS" "fcmpu %0,%1,%2" [(set_attr "type" "fpcompare")]) @@ -10629,7 +11641,7 @@ [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") (match_operand:DF 2 "gpc_reg_operand" "f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT && TARGET_FPRS" "fcmpu %0,%1,%2" [(set_attr "type" "fpcompare")]) @@ -10638,7 +11650,8 @@ [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "f") (match_operand:TF 2 "gpc_reg_operand" "f")))] - "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_LONG_DOUBLE_128" + "DEFAULT_ABI == ABI_AIX && TARGET_HARD_FLOAT && TARGET_FPRS + && TARGET_LONG_DOUBLE_128" "fcmpu %0,%1,%2\;bne %0,$+4\;fcmpu %0,%L1,%L2" [(set_attr "type" "fpcompare") (set_attr "length" "12")]) @@ -10657,6 +11670,15 @@ (const_int 0)]))] "" "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" + [(set_attr "type" "cr_logical") + (set_attr "length" "12")]) + +;; Same as above, but get the OV/ORDERED bit. +(define_insn "move_from_CR_ov_bit" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] 724))] + "TARGET_ISEL" + "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%t1,1" [(set_attr "length" "12")]) (define_insn "" @@ -10666,7 +11688,8 @@ (const_int 0)]))] "TARGET_POWERPC64" "%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%J1,1" - [(set_attr "length" "12")]) + [(set_attr "type" "cr_logical") + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") @@ -10722,7 +11745,8 @@ return \"%D1mfcr %0\;{rlinm|rlwinm} %0,%0,%4,%5,%5\"; }" - [(set_attr "length" "12")]) + [(set_attr "type" "cr_logical") + (set_attr "length" "12")]) (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") @@ -10735,7 +11759,7 @@ (set (match_operand:SI 4 "gpc_reg_operand" "=r,r") (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) (match_dup 3)))] - "! TARGET_POWERPC64" + "" "* { int is_bit = ccr_bit (operands[1], 1); @@ -10770,7 +11794,7 @@ (set (match_operand:SI 4 "gpc_reg_operand" "") (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) (match_dup 3)))] - "! TARGET_POWERPC64 && reload_completed" + "reload_completed" [(set (match_dup 4) (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) (match_dup 3))) @@ -10791,9 +11815,10 @@ (match_operator:SI 4 "scc_comparison_operator" [(match_operand 5 "cc_reg_operand" "y") (const_int 0)]))] - "REGNO (operands[2]) != REGNO (operands[5])" - "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" - [(set_attr "length" "20")]) + "REGNO (operands[2]) != REGNO (operands[5])" + "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" + [(set_attr "type" "cr_logical") + (set_attr "length" "20")]) (define_peephole [(set (match_operand:DI 0 "gpc_reg_operand" "=r") @@ -10804,9 +11829,10 @@ (match_operator:DI 4 "scc_comparison_operator" [(match_operand 5 "cc_reg_operand" "y") (const_int 0)]))] - "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" - "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" - [(set_attr "length" "20")]) + "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" + "%D1%D4mfcr %3\;{rlinm|rlwinm} %0,%3,%J1,1\;{rlinm|rlwinm} %3,%3,%J4,1" + [(set_attr "type" "cr_logical") + (set_attr "length" "20")]) ;; There are some scc insns that can be done directly, without a compare. ;; These are faster because they don't involve the communications between @@ -11069,7 +12095,7 @@ (lshiftrt:SI (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) (const_int 31))) (clobber (match_scratch:SI 2 "=&r"))] - "! TARGET_POWER && ! TARGET_POWERPC64" + "! TARGET_POWER && ! TARGET_POWERPC64 && !TARGET_ISEL" "{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1" [(set_attr "length" "8")]) @@ -11134,9 +12160,9 @@ (clobber (match_scratch:SI 4 ""))] "! TARGET_POWERPC64 && reload_completed" [(parallel [(set (match_dup 3) - (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) - (const_int 31)) - (match_dup 2))) + (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) + (const_int 31)) + (match_dup 2))) (clobber (match_dup 4))]) (set (match_dup 0) (compare:CC (match_dup 3) @@ -13028,7 +14054,7 @@ "cc_reg_operand" "y") (const_int 0)]) (const_int 0)))] - "" + "!TARGET_SPE" "{crnor %E0,%j1,%j1|crnot %E0,%j1}" [(set_attr "type" "cr_logical")]) @@ -13282,7 +14308,7 @@ return \"bdz $+8\;b %l0\"; }" [(set_attr "type" "branch") - (set_attr "length" "*,12,16")]) + (set_attr "length" "4,12,16")]) (define_insn "*ctrsi_internal2" [(set (pc) @@ -13306,7 +14332,7 @@ return \"{bdn|bdnz} $+8\;b %l0\"; }" [(set_attr "type" "branch") - (set_attr "length" "*,12,16")]) + (set_attr "length" "4,12,16")]) (define_insn "*ctrdi_internal1" [(set (pc) @@ -13330,7 +14356,7 @@ return \"bdz $+8\;b %l0\"; }" [(set_attr "type" "branch") - (set_attr "length" "*,12,16")]) + (set_attr "length" "4,12,16")]) (define_insn "*ctrdi_internal2" [(set (pc) @@ -13354,7 +14380,7 @@ return \"{bdn|bdnz} $+8\;b %l0\"; }" [(set_attr "type" "branch") - (set_attr "length" "*,12,16")]) + (set_attr "length" "4,12,16")]) ;; Similar, but we can use GE since we have a REG_NONNEG. @@ -13380,7 +14406,7 @@ return \"bdz $+8\;b %l0\"; }" [(set_attr "type" "branch") - (set_attr "length" "*,12,16")]) + (set_attr "length" "4,12,16")]) (define_insn "*ctrsi_internal4" [(set (pc) @@ -13404,7 +14430,7 @@ return \"{bdn|bdnz} $+8\;b %l0\"; }" [(set_attr "type" "branch") - (set_attr "length" "*,12,16")]) + (set_attr "length" "4,12,16")]) (define_insn "*ctrdi_internal3" [(set (pc) @@ -13428,7 +14454,7 @@ return \"bdz $+8\;b %l0\"; }" [(set_attr "type" "branch") - (set_attr "length" "*,12,16")]) + (set_attr "length" "4,12,16")]) (define_insn "*ctrdi_internal4" [(set (pc) @@ -13452,7 +14478,7 @@ return \"{bdn|bdnz} $+8\;b %l0\"; }" [(set_attr "type" "branch") - (set_attr "length" "*,12,16")]) + (set_attr "length" "4,12,16")]) ;; Similar but use EQ @@ -13478,7 +14504,7 @@ return \"{bdn|bdnz} $+8\;b %l0\"; }" [(set_attr "type" "branch") - (set_attr "length" "*,12,16")]) + (set_attr "length" "4,12,16")]) (define_insn "*ctrsi_internal6" [(set (pc) @@ -13502,7 +14528,7 @@ return \"bdz $+8\;b %l0\"; }" [(set_attr "type" "branch") - (set_attr "length" "*,12,16")]) + (set_attr "length" "4,12,16")]) (define_insn "*ctrdi_internal5" [(set (pc) @@ -13526,7 +14552,7 @@ return \"{bdn|bdnz} $+8\;b %l0\"; }" [(set_attr "type" "branch") - (set_attr "length" "*,12,16")]) + (set_attr "length" "4,12,16")]) (define_insn "*ctrdi_internal6" [(set (pc) @@ -13550,7 +14576,7 @@ return \"bdz $+8\;b %l0\"; }" [(set_attr "type" "branch") - (set_attr "length" "*,12,16")]) + (set_attr "length" "4,12,16")]) ;; Now the splitters if we could not allocate the CTR register @@ -13712,7 +14738,8 @@ (unspec:SI [(reg:CC 68) (reg:CC 69) (reg:CC 70) (reg:CC 71) (reg:CC 72) (reg:CC 73) (reg:CC 74) (reg:CC 75)] 19))] "" - "mfcr %0") + "mfcr %0" + [(set_attr "type" "cr_logical")]) (define_insn "*stmw" [(match_parallel 0 "stmw_operation" @@ -13763,17 +14790,17 @@ ; faster; for instance, on the 601 and 750. (define_expand "movsi_to_cr_one" - [(set (match_operand:CC 0 "cc_reg_operand" "=y") - (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") - (match_dup 2)] 20))] - "" - "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") + [(set (match_operand:CC 0 "cc_reg_operand" "=y") + (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") + (match_dup 2)] 20))] + "" + "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") (define_insn "*movsi_to_cr" - [(match_parallel 0 "mtcrf_operation" - [(set (match_operand:CC 1 "cc_reg_operand" "=y") - (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r") - (match_operand 3 "immediate_operand" "n")] + [(match_parallel 0 "mtcrf_operation" + [(set (match_operand:CC 1 "cc_reg_operand" "=y") + (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r") + (match_operand 3 "immediate_operand" "n")] 20))])] "" "* @@ -13784,28 +14811,30 @@ mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); operands[4] = GEN_INT (mask); return \"mtcrf %4,%2\"; -}") +}" + [(set_attr "type" "cr_logical")]) (define_insn "" - [(set (match_operand:CC 0 "cc_reg_operand" "=y") - (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") - (match_operand 2 "immediate_operand" "n")] 20))] - "GET_CODE (operands[0]) == REG - && CR_REGNO_P (REGNO (operands[0])) - && GET_CODE (operands[2]) == CONST_INT - && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" - "mtcrf %R0,%1") + [(set (match_operand:CC 0 "cc_reg_operand" "=y") + (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand 2 "immediate_operand" "n")] 20))] + "GET_CODE (operands[0]) == REG + && CR_REGNO_P (REGNO (operands[0])) + && GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" + "mtcrf %R0,%1" + [(set_attr "type" "cr_logical")]) ; The load-multiple instructions have similar properties. ; Note that "load_multiple" is a name known to the machine-independent ; code that actually corresponds to the powerpc load-string. (define_insn "*lmw" - [(match_parallel 0 "lmw_operation" - [(set (match_operand:SI 1 "gpc_reg_operand" "=r") - (match_operand:SI 2 "memory_operand" "m"))])] - "TARGET_MULTIPLE" - "{lm|lmw} %1,%2") + [(match_parallel 0 "lmw_operation" + [(set (match_operand:SI 1 "gpc_reg_operand" "=r") + (match_operand:SI 2 "memory_operand" "m"))])] + "TARGET_MULTIPLE" + "{lm|lmw} %1,%2") (define_insn "*return_internal_si" [(return) @@ -13846,19 +14875,17 @@ ; This is used in compiling the unwind routines. (define_expand "eh_return" - [(use (match_operand 0 "general_operand" "")) - (use (match_operand 1 "general_operand" ""))] + [(use (match_operand 0 "general_operand" ""))] "" " { #if TARGET_AIX - rs6000_emit_eh_toc_restore (operands[0]); + rs6000_emit_eh_toc_restore (EH_RETURN_STACKADJ_RTX); #endif if (TARGET_32BIT) - emit_insn (gen_eh_set_lr_si (operands[1])); + emit_insn (gen_eh_set_lr_si (operands[0])); else - emit_insn (gen_eh_set_lr_di (operands[1])); - emit_move_insn (EH_RETURN_STACKADJ_RTX, operands[0]); + emit_insn (gen_eh_set_lr_di (operands[0])); DONE; }") @@ -13921,1850 +14948,6 @@ return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\"; }" [(set_attr "type" "load")]) - -;; AltiVec patterns - -;; Generic LVX load instruction. -(define_insn "altivec_lvx_4si" - [(set (match_operand:V4SI 0 "altivec_register_operand" "=v") - (match_operand:V4SI 1 "memory_operand" "m"))] - "TARGET_ALTIVEC" - "lvx %0,%y1" - [(set_attr "type" "vecload")]) - -(define_insn "altivec_lvx_8hi" - [(set (match_operand:V8HI 0 "altivec_register_operand" "=v") - (match_operand:V8HI 1 "memory_operand" "m"))] - "TARGET_ALTIVEC" - "lvx %0,%y1" - [(set_attr "type" "vecload")]) - -(define_insn "altivec_lvx_16qi" - [(set (match_operand:V16QI 0 "altivec_register_operand" "=v") - (match_operand:V16QI 1 "memory_operand" "m"))] - "TARGET_ALTIVEC" - "lvx %0,%y1" - [(set_attr "type" "vecload")]) - -(define_insn "altivec_lvx_4sf" - [(set (match_operand:V4SF 0 "altivec_register_operand" "=v") - (match_operand:V4SF 1 "memory_operand" "m"))] - "TARGET_ALTIVEC" - "lvx %0,%y1" - [(set_attr "type" "vecload")]) - -;; Generic STVX store instruction. -(define_insn "altivec_stvx_4si" - [(set (match_operand:V4SI 0 "memory_operand" "=m") - (match_operand:V4SI 1 "altivec_register_operand" "v"))] - "TARGET_ALTIVEC" - "stvx %1,%y0" - [(set_attr "type" "vecstore")]) - -(define_insn "altivec_stvx_8hi" - [(set (match_operand:V8HI 0 "memory_operand" "=m") - (match_operand:V8HI 1 "altivec_register_operand" "v"))] - "TARGET_ALTIVEC" - "stvx %1,%y0" - [(set_attr "type" "vecstore")]) - -(define_insn "altivec_stvx_16qi" - [(set (match_operand:V16QI 0 "memory_operand" "=m") - (match_operand:V16QI 1 "altivec_register_operand" "v"))] - "TARGET_ALTIVEC" - "stvx %1,%y0" - [(set_attr "type" "vecstore")]) - -(define_insn "altivec_stvx_4sf" - [(set (match_operand:V4SF 0 "memory_operand" "=m") - (match_operand:V4SF 1 "altivec_register_operand" "v"))] - "TARGET_ALTIVEC" - "stvx %1,%y0" - [(set_attr "type" "vecstore")]) - -;; Vector move instructions. -(define_expand "movv4si" - [(set (match_operand:V4SI 0 "nonimmediate_operand" "") - (match_operand:V4SI 1 "any_operand" ""))] - "TARGET_ALTIVEC" - "{ rs6000_emit_move (operands[0], operands[1], V4SImode); DONE; }") - -(define_insn "*movv4si_internal" - [(set (match_operand:V4SI 0 "nonimmediate_operand" "=m,v,v,o,r,r") - (match_operand:V4SI 1 "input_operand" "v,m,v,r,o,r"))] - "TARGET_ALTIVEC" - "@ - stvx %1,%y0 - lvx %0,%y1 - vor %0,%1,%1 - stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 - lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 - mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" - [(set_attr "type" "altivec") - (set_attr "length" "*,*,*,16,16,16")]) - -(define_expand "movv8hi" - [(set (match_operand:V8HI 0 "nonimmediate_operand" "") - (match_operand:V8HI 1 "any_operand" ""))] - "TARGET_ALTIVEC" - "{ rs6000_emit_move (operands[0], operands[1], V8HImode); DONE; }") - -(define_insn "*movv8hi_internal1" - [(set (match_operand:V8HI 0 "nonimmediate_operand" "=m,v,v,o,r,r") - (match_operand:V8HI 1 "input_operand" "v,m,v,r,o,r"))] - "TARGET_ALTIVEC" - "@ - stvx %1,%y0 - lvx %0,%y1 - vor %0,%1,%1 - stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 - lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 - mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" - [(set_attr "type" "altivec") - (set_attr "length" "*,*,*,16,16,16")]) - -(define_expand "movv16qi" - [(set (match_operand:V16QI 0 "nonimmediate_operand" "") - (match_operand:V16QI 1 "any_operand" ""))] - "TARGET_ALTIVEC" - "{ rs6000_emit_move (operands[0], operands[1], V16QImode); DONE; }") - -(define_insn "*movv16qi_internal1" - [(set (match_operand:V16QI 0 "nonimmediate_operand" "=m,v,v,o,r,r") - (match_operand:V16QI 1 "input_operand" "v,m,v,r,o,r"))] - "TARGET_ALTIVEC" - "@ - stvx %1,%y0 - lvx %0,%y1 - vor %0,%1,%1 - stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 - lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 - mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" - [(set_attr "type" "altivec") - (set_attr "length" "*,*,*,16,16,16")]) - -(define_expand "movv4sf" - [(set (match_operand:V4SF 0 "nonimmediate_operand" "") - (match_operand:V4SF 1 "any_operand" ""))] - "TARGET_ALTIVEC" - "{ rs6000_emit_move (operands[0], operands[1], V4SFmode); DONE; }") - -(define_insn "*movv4sf_internal1" - [(set (match_operand:V4SF 0 "nonimmediate_operand" "=m,v,v,o,r,r") - (match_operand:V4SF 1 "input_operand" "v,m,v,r,o,r"))] - "TARGET_ALTIVEC" - "@ - stvx %1,%y0 - lvx %0,%y1 - vor %0,%1,%1 - stw%U0 %1,%0\;stw %L1,%L0\;stw %Y1,%Y0\;stw %Z1,%Z0 - lwz%U1 %0,%1\;lwz %L0,%L1\;lwz %Y0,%Y1\;lwz %Z0,%Z1 - mr %0,%1\;mr %L0,%L1\;mr %Y0,%Y1\;mr %Z0,%Z1" - [(set_attr "type" "altivec") - (set_attr "length" "*,*,*,16,16,16")]) - -(define_insn "get_vrsave_internal" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec:SI [(reg:SI 109)] 214))] - "TARGET_ALTIVEC" - "* -{ - if (TARGET_MACHO) - return \"mtspr 256,%0\"; - else - return \"mtvrsave %0\"; -}" - [(set_attr "type" "altivec")]) - -(define_insn "*set_vrsave_internal" - [(match_parallel 0 "vrsave_operation" - [(set (reg:SI 109) - (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r") - (reg:SI 109)] 30))])] - "TARGET_ALTIVEC" - "* -{ - if (TARGET_MACHO) - return \"mfspr %1,256\"; - else - return \"mtvrsave %1\"; -}" - [(set_attr "type" "altivec")]) - -;; Vector clears -(define_insn "*movv4si_const0" - [(set (match_operand:V4SI 0 "altivec_register_operand" "=v") - (match_operand:V4SI 1 "zero_constant" ""))] - "TARGET_ALTIVEC" - "vxor %0,%0,%0" - [(set_attr "type" "vecsimple")]) - -(define_insn "*movv4sf_const0" - [(set (match_operand:V4SF 0 "altivec_register_operand" "=v") - (match_operand:V4SF 1 "zero_constant" ""))] - - "TARGET_ALTIVEC" - "vxor %0,%0,%0" - [(set_attr "type" "vecsimple")]) - -(define_insn "*movv8hi_const0" - [(set (match_operand:V8HI 0 "altivec_register_operand" "=v") - (match_operand:V8HI 1 "zero_constant" ""))] - "TARGET_ALTIVEC" - "vxor %0,%0,%0" - [(set_attr "type" "vecsimple")]) - -(define_insn "*movv16qi_const0" - [(set (match_operand:V16QI 0 "altivec_register_operand" "=v") - (match_operand:V16QI 1 "zero_constant" ""))] - "TARGET_ALTIVEC" - "vxor %0,%0,%0" - [(set_attr "type" "vecsimple")]) - -;; Simple binary operations. - -(define_insn "addv16qi3" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (plus:V16QI (match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vaddubm %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "addv8hi3" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (plus:V8HI (match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vadduhm %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "addv4si3" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (plus:V4SI (match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vadduwm %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "addv4sf3" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (plus:V4SF (match_operand:V4SF 1 "register_operand" "v") - (match_operand:V4SF 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vaddfp %0,%1,%2" - [(set_attr "type" "vecfloat")]) - -(define_insn "altivec_vaddcuw" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 35))] - "TARGET_ALTIVEC" - "vaddcuw %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vaddubs" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")] 36))] - "TARGET_ALTIVEC" - "vaddubs %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vaddsbs" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")] 37))] - "TARGET_ALTIVEC" - "vaddsbs %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vadduhs" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 38))] - "TARGET_ALTIVEC" - "vadduhs %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vaddshs" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 39))] - "TARGET_ALTIVEC" - "vaddshs %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vadduws" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 40))] - "TARGET_ALTIVEC" - "vadduws %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vaddsws" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 41))] - "TARGET_ALTIVEC" - "vaddsws %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "andv4si3" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (and:V4SI (match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vand %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vandc" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (and:V4SI (match_operand:V4SI 1 "register_operand" "v") - (not:V4SI (match_operand:V4SI 2 "register_operand" "v"))))] - "TARGET_ALTIVEC" - "vandc %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vavgub" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")] 44))] - "TARGET_ALTIVEC" - "vavgub %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vavgsb" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")] 45))] - "TARGET_ALTIVEC" - "vavgsb %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vavguh" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 46))] - "TARGET_ALTIVEC" - "vavguh %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vavgsh" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 47))] - "TARGET_ALTIVEC" - "vavgsh %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vavguw" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 48))] - "TARGET_ALTIVEC" - "vavguw %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vavgsw" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 49))] - "TARGET_ALTIVEC" - "vavgsw %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vcmpbfp" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") - (match_operand:V4SF 2 "register_operand" "v")] 50))] - "TARGET_ALTIVEC" - "vcmpbfp %0,%1,%2" - [(set_attr "type" "veccmp")]) - -(define_insn "altivec_vcmpequb" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")] 51))] - "TARGET_ALTIVEC" - "vcmpequb %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vcmpequh" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 52))] - "TARGET_ALTIVEC" - "vcmpequh %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vcmpequw" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 53))] - "TARGET_ALTIVEC" - "vcmpequw %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vcmpeqfp" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") - (match_operand:V4SF 2 "register_operand" "v")] 54))] - "TARGET_ALTIVEC" - "vcmpeqfp %0,%1,%2" - [(set_attr "type" "veccmp")]) - -(define_insn "altivec_vcmpgefp" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") - (match_operand:V4SF 2 "register_operand" "v")] 55))] - "TARGET_ALTIVEC" - "vcmpgefp %0,%1,%2" - [(set_attr "type" "veccmp")]) - -(define_insn "altivec_vcmpgtub" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")] 56))] - "TARGET_ALTIVEC" - "vcmpgtub %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vcmpgtsb" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")] 57))] - "TARGET_ALTIVEC" - "vcmpgtsb %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vcmpgtuh" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 58))] - "TARGET_ALTIVEC" - "vcmpgtuh %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vcmpgtsh" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 59))] - "TARGET_ALTIVEC" - "vcmpgtsh %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vcmpgtuw" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 60))] - "TARGET_ALTIVEC" - "vcmpgtuw %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vcmpgtsw" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 61))] - "TARGET_ALTIVEC" - "vcmpgtsw %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vcmpgtfp" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") - (match_operand:V4SF 2 "register_operand" "v")] 62))] - "TARGET_ALTIVEC" - "vcmpgtfp %0,%1,%2" - [(set_attr "type" "veccmp")]) - -;; Fused multiply add -(define_insn "altivec_vmaddfp" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v") - (match_operand:V4SF 2 "register_operand" "v")) - (match_operand:V4SF 3 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vmaddfp %0,%1,%2,%3" - [(set_attr "type" "vecfloat")]) - -;; The unspec here is a vec splat of 0. We do multiply as a fused -;; multiply-add with an add of a 0 vector. - -(define_expand "mulv4sf3" - [(set (match_dup 3) (unspec:V4SF [(const_int 0)] 142)) - (set (match_operand:V4SF 0 "register_operand" "=v") - (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v") - (match_operand:V4SF 2 "register_operand" "v")) - (match_dup 3)))] - "TARGET_ALTIVEC && TARGET_FUSED_MADD" - " -{ operands[3] = gen_reg_rtx (V4SFmode); }") - -;; Fused multiply subtract -(define_insn "altivec_vnmsubfp" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v") - (match_operand:V4SF 2 "register_operand" "v")) - (match_operand:V4SF 3 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vnmsubfp %0,%1,%2,%3" - [(set_attr "type" "vecfloat")]) - - -(define_insn "altivec_vmsumubm" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v") - (match_operand:V4SI 3 "register_operand" "v")] 65))] - "TARGET_ALTIVEC" - "vmsumubm %0, %1, %2, %3" - [(set_attr "type" "veccomplex")]) - -(define_insn "altivec_vmsummbm" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v") - (match_operand:V4SI 3 "register_operand" "v")] 66))] - "TARGET_ALTIVEC" - "vmsumubm %0, %1, %2, %3" - [(set_attr "type" "veccomplex")]) - -(define_insn "altivec_vmsumuhm" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v") - (match_operand:V4SI 3 "register_operand" "v")] 67))] - "TARGET_ALTIVEC" - "vmsumuhm %0, %1, %2, %3" - [(set_attr "type" "veccomplex")]) - -(define_insn "altivec_vmsumshm" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v") - (match_operand:V4SI 3 "register_operand" "v")] 68))] - "TARGET_ALTIVEC" - "vmsumshm %0, %1, %2, %3" - [(set_attr "type" "veccomplex")]) - -(define_insn "altivec_vmsumuhs" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v") - (match_operand:V4SI 3 "register_operand" "v")] 69))] - "TARGET_ALTIVEC" - "vmsumuhs %0, %1, %2, %3" - [(set_attr "type" "veccomplex")]) - -(define_insn "altivec_vmsumshs" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v") - (match_operand:V4SI 3 "register_operand" "v")] 70))] - "TARGET_ALTIVEC" - "vmsumshs %0, %1, %2, %3" - [(set_attr "type" "veccomplex")]) - -(define_insn "umaxv16qi3" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (umax:V16QI (match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vmaxub %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "smaxv16qi3" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (smax:V16QI (match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vmaxsb %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "umaxv8hi3" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (umax:V8HI (match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vmaxuh %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "smaxv8hi3" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (smax:V8HI (match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vmaxsh %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "umaxv4si3" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (umax:V4SI (match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vmaxuw %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "smaxv4si3" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (smax:V4SI (match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vmaxsw %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "smaxv4sf3" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (smax:V4SF (match_operand:V4SF 1 "register_operand" "v") - (match_operand:V4SF 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vmaxfp %0,%1,%2" - [(set_attr "type" "veccmp")]) - -(define_insn "altivec_vmhaddshs" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v") - (match_operand:V8HI 3 "register_operand" "v")] 71))] - "TARGET_ALTIVEC" - "vmhaddshs %0, %1, %2, %3" - [(set_attr "type" "veccomplex")]) -(define_insn "altivec_vmhraddshs" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v") - (match_operand:V8HI 3 "register_operand" "v")] 72))] - "TARGET_ALTIVEC" - "vmhraddshs %0, %1, %2, %3" - [(set_attr "type" "veccomplex")]) -(define_insn "altivec_vmladduhm" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v") - (match_operand:V8HI 3 "register_operand" "v")] 73))] - "TARGET_ALTIVEC" - "vmladduhm %0, %1, %2, %3" - [(set_attr "type" "veccomplex")]) - -(define_insn "altivec_vmrghb" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v") - (parallel [(const_int 8) - (const_int 9) - (const_int 10) - (const_int 11) - (const_int 12) - (const_int 13) - (const_int 14) - (const_int 15) - (const_int 0) - (const_int 1) - (const_int 2) - (const_int 3) - (const_int 4) - (const_int 5) - (const_int 6) - (const_int 7)])) - (match_operand:V16QI 2 "register_operand" "v") - (const_int 255)))] - "TARGET_ALTIVEC" - "vmrghb %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vmrghh" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v") - (parallel [(const_int 4) - (const_int 5) - (const_int 6) - (const_int 7) - (const_int 0) - (const_int 1) - (const_int 2) - (const_int 3)])) - (match_operand:V8HI 2 "register_operand" "v") - (const_int 15)))] - "TARGET_ALTIVEC" - "vmrghh %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vmrghw" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v") - (parallel [(const_int 2) - (const_int 3) - (const_int 0) - (const_int 1)])) - (match_operand:V4SI 2 "register_operand" "v") - (const_int 12)))] - "TARGET_ALTIVEC" - "vmrghw %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vmrglb" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v") - (parallel [(const_int 8) - (const_int 9) - (const_int 10) - (const_int 11) - (const_int 12) - (const_int 13) - (const_int 14) - (const_int 15) - (const_int 0) - (const_int 1) - (const_int 2) - (const_int 3) - (const_int 4) - (const_int 5) - (const_int 6) - (const_int 7)])) - (match_operand:V16QI 1 "register_operand" "v") - (const_int 255)))] - "TARGET_ALTIVEC" - "vmrglb %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vmrglh" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v") - (parallel [(const_int 4) - (const_int 5) - (const_int 6) - (const_int 7) - (const_int 0) - (const_int 1) - (const_int 2) - (const_int 3)])) - (match_operand:V8HI 1 "register_operand" "v") - (const_int 15)))] - "TARGET_ALTIVEC" - "vmrglh %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vmrglw" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v") - (parallel [(const_int 2) - (const_int 3) - (const_int 0) - (const_int 1)])) - (match_operand:V4SI 1 "register_operand" "v") - (const_int 12)))] - "TARGET_ALTIVEC" - "vmrglw %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "uminv16qi3" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (umin:V16QI (match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vminub %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "sminv16qi3" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (smin:V16QI (match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vminsb %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "uminv8hi3" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (umin:V8HI (match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vminuh %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "sminv8hi3" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (smin:V8HI (match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vminsh %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "uminv4si3" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (umin:V4SI (match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vminuw %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "sminv4si3" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (smin:V4SI (match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vminsw %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "sminv4sf3" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (smin:V4SF (match_operand:V4SF 1 "register_operand" "v") - (match_operand:V4SF 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vminfp %0,%1,%2" - [(set_attr "type" "veccmp")]) - -(define_insn "altivec_vmuleub" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")] 83))] - "TARGET_ALTIVEC" - "vmuleub %0,%1,%2" - [(set_attr "type" "veccomplex")]) - -(define_insn "altivec_vmulesb" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")] 84))] - "TARGET_ALTIVEC" - "vmulesb %0,%1,%2" - [(set_attr "type" "veccomplex")]) - -(define_insn "altivec_vmuleuh" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 85))] - "TARGET_ALTIVEC" - "vmuleuh %0,%1,%2" - [(set_attr "type" "veccomplex")]) - -(define_insn "altivec_vmulesh" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 86))] - "TARGET_ALTIVEC" - "vmulesh %0,%1,%2" - [(set_attr "type" "veccomplex")]) - -(define_insn "altivec_vmuloub" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")] 87))] - "TARGET_ALTIVEC" - "vmuloub %0,%1,%2" - [(set_attr "type" "veccomplex")]) - -(define_insn "altivec_vmulosb" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")] 88))] - "TARGET_ALTIVEC" - "vmulosb %0,%1,%2" - [(set_attr "type" "veccomplex")]) - -(define_insn "altivec_vmulouh" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 89))] - "TARGET_ALTIVEC" - "vmulouh %0,%1,%2" - [(set_attr "type" "veccomplex")]) - -(define_insn "altivec_vmulosh" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 90))] - "TARGET_ALTIVEC" - "vmulosh %0,%1,%2" - [(set_attr "type" "veccomplex")]) - -(define_insn "altivec_vnor" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (not:V4SI (ior:V4SI (match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v"))))] - "TARGET_ALTIVEC" - "vnor %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "iorv4si3" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (ior:V4SI (match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vor %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vpkuhum" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 93))] - "TARGET_ALTIVEC" - "vpkuhum %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vpkuwum" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 94))] - "TARGET_ALTIVEC" - "vpkuwum %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vpkpx" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 95))] - "TARGET_ALTIVEC" - "vpkpx %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vpkuhss" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 96))] - "TARGET_ALTIVEC" - "vpkuhss %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vpkshss" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 97))] - "TARGET_ALTIVEC" - "vpkshss %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vpkuwss" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 98))] - "TARGET_ALTIVEC" - "vpkuwss %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vpkswss" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 99))] - "TARGET_ALTIVEC" - "vpkswss %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vpkuhus" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 100))] - "TARGET_ALTIVEC" - "vpkuhus %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vpkshus" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 101))] - "TARGET_ALTIVEC" - "vpkshus %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vpkuwus" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 102))] - "TARGET_ALTIVEC" - "vpkuwus %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vpkswus" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 103))] - "TARGET_ALTIVEC" - "vpkswus %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vrlb" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")] 104))] - "TARGET_ALTIVEC" - "vrlb %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vrlh" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 105))] - "TARGET_ALTIVEC" - "vrlh %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vrlw" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 106))] - "TARGET_ALTIVEC" - "vrlw %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vslb" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")] 107))] - "TARGET_ALTIVEC" - "vslb %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vslh" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 108))] - "TARGET_ALTIVEC" - "vslh %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vslw" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 109))] - "TARGET_ALTIVEC" - "vslw %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vsl" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 110))] - "TARGET_ALTIVEC" - "vsl %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vslo" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 111))] - "TARGET_ALTIVEC" - "vslo %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vsrb" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")] 112))] - "TARGET_ALTIVEC" - "vsrb %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vsrh" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 113))] - "TARGET_ALTIVEC" - "vsrh %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vsrw" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 114))] - "TARGET_ALTIVEC" - "vsrw %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vsrab" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")] 115))] - "TARGET_ALTIVEC" - "vsrab %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vsrah" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 116))] - "TARGET_ALTIVEC" - "vsrah %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vsraw" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 117))] - "TARGET_ALTIVEC" - "vsraw %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vsr" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 118))] - "TARGET_ALTIVEC" - "vsr %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vsro" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 119))] - "TARGET_ALTIVEC" - "vsro %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "subv16qi3" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (minus:V16QI (match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vsububm %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "subv8hi3" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (minus:V8HI (match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vsubuhm %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "subv4si3" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (minus:V4SI (match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vsubuwm %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "subv4sf3" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (minus:V4SF (match_operand:V4SF 1 "register_operand" "v") - (match_operand:V4SF 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vsubfp %0,%1,%2" - [(set_attr "type" "vecfloat")]) - -(define_insn "altivec_vsubcuw" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 124))] - "TARGET_ALTIVEC" - "vsubcuw %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vsububs" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")] 125))] - "TARGET_ALTIVEC" - "vsububs %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vsubsbs" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v")] 126))] - "TARGET_ALTIVEC" - "vsubsbs %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vsubuhs" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 127))] - "TARGET_ALTIVEC" - "vsubuhs %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vsubshs" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v")] 128))] - "TARGET_ALTIVEC" - "vsubshs %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vsubuws" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 129))] - "TARGET_ALTIVEC" - "vsubuws %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vsubsws" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 130))] - "TARGET_ALTIVEC" - "vsubsws %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vsum4ubs" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 131))] - "TARGET_ALTIVEC" - "vsum4ubs %0,%1,%2" - [(set_attr "type" "veccomplex")]) - -(define_insn "altivec_vsum4sbs" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 132))] - "TARGET_ALTIVEC" - "vsum4sbs %0,%1,%2" - [(set_attr "type" "veccomplex")]) - -(define_insn "altivec_vsum4shs" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 133))] - "TARGET_ALTIVEC" - "vsum4shs %0,%1,%2" - [(set_attr "type" "veccomplex")]) - -(define_insn "altivec_vsum2sws" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 134))] - "TARGET_ALTIVEC" - "vsum2sws %0,%1,%2" - [(set_attr "type" "veccomplex")]) - -(define_insn "altivec_vsumsws" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")] 135))] - "TARGET_ALTIVEC" - "vsumsws %0,%1,%2" - [(set_attr "type" "veccomplex")]) - -(define_insn "xorv4si3" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (xor:V4SI (match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vxor %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vspltb" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:QI 2 "immediate_operand" "i")] 136))] - "TARGET_ALTIVEC" - "vspltb %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vsplth" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:QI 2 "immediate_operand" "i")] 137))] - "TARGET_ALTIVEC" - "vsplth %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vspltw" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:QI 2 "immediate_operand" "i")] 138))] - "TARGET_ALTIVEC" - "vspltw %0,%1,%2" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vspltisb" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:QI 1 "immediate_operand" "i")] 139))] - "TARGET_ALTIVEC" - "vspltisb %0, %1" - [(set_attr "type" "vecsimple")]) - - -(define_insn "altivec_vspltish" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:QI 1 "immediate_operand" "i")] 140))] - "TARGET_ALTIVEC" - "vspltish %0, %1" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_vspltisw" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:QI 1 "immediate_operand" "i")] 141))] - "TARGET_ALTIVEC" - "vspltisw %0, %1" - [(set_attr "type" "vecsimple")]) - -(define_insn "" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (unspec:V4SF [(match_operand:QI 1 "immediate_operand" "i")] 142))] - "TARGET_ALTIVEC" - "vspltisw %0, %1" - [(set_attr "type" "vecsimple")]) - -(define_insn "ftruncv4sf2" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))] - "TARGET_ALTIVEC" - "vrfiz %0, %1" - [(set_attr "type" "vecfloat")]) - -(define_insn "altivec_vperm_4si" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v") - (match_operand:V16QI 3 "register_operand" "v")] 144))] - "TARGET_ALTIVEC" - "vperm %0,%1,%2,%3" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vperm_4sf" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") - (match_operand:V4SF 2 "register_operand" "v") - (match_operand:V16QI 3 "register_operand" "v")] 145))] - "TARGET_ALTIVEC" - "vperm %0,%1,%2,%3" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vperm_8hi" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v") - (match_operand:V16QI 3 "register_operand" "v")] 146))] - "TARGET_ALTIVEC" - "vperm %0,%1,%2,%3" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vperm_16qi" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v") - (match_operand:V16QI 3 "register_operand" "v")] 147))] - "TARGET_ALTIVEC" - "vperm %0,%1,%2,%3" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vrfip" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 148))] - "TARGET_ALTIVEC" - "vrfip %0, %1" - [(set_attr "type" "vecfloat")]) - -(define_insn "altivec_vrfin" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 149))] - "TARGET_ALTIVEC" - "vrfin %0, %1" - [(set_attr "type" "vecfloat")]) - -(define_insn "altivec_vrfim" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 150))] - "TARGET_ALTIVEC" - "vrfim %0, %1" - [(set_attr "type" "vecfloat")]) - -(define_insn "altivec_vcfux" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:QI 2 "immediate_operand" "i")] 151))] - "TARGET_ALTIVEC" - "vcfux %0, %1, %2" - [(set_attr "type" "vecfloat")]) - -(define_insn "altivec_vcfsx" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:QI 2 "immediate_operand" "i")] 152))] - "TARGET_ALTIVEC" - "vcfsx %0, %1, %2" - [(set_attr "type" "vecfloat")]) - -(define_insn "altivec_vctuxs" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") - (match_operand:QI 2 "immediate_operand" "i")] 153))] - "TARGET_ALTIVEC" - "vctuxs %0, %1, %2" - [(set_attr "type" "vecfloat")]) - -(define_insn "altivec_vctsxs" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v") - (match_operand:QI 2 "immediate_operand" "i")] 154))] - "TARGET_ALTIVEC" - "vctsxs %0, %1, %2" - [(set_attr "type" "vecfloat")]) - -(define_insn "altivec_vlogefp" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 155))] - "TARGET_ALTIVEC" - "vlogefp %0, %1" - [(set_attr "type" "vecfloat")]) - -(define_insn "altivec_vexptefp" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 156))] - "TARGET_ALTIVEC" - "vexptefp %0, %1" - [(set_attr "type" "vecfloat")]) - -(define_insn "altivec_vrsqrtefp" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 157))] - "TARGET_ALTIVEC" - "vrsqrtefp %0, %1" - [(set_attr "type" "vecfloat")]) - -(define_insn "altivec_vrefp" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")] 158))] - "TARGET_ALTIVEC" - "vrefp %0, %1" - [(set_attr "type" "vecfloat")]) - -(define_insn "altivec_vsel_4si" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v") - (match_operand:V4SI 3 "register_operand" "v")] 159))] - "TARGET_ALTIVEC" - "vsel %0,%1,%2,%3" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vsel_4sf" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") - (match_operand:V4SF 2 "register_operand" "v") - (match_operand:V4SI 3 "register_operand" "v")] 160))] - "TARGET_ALTIVEC" - "vsel %0,%1,%2,%3" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vsel_8hi" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v") - (match_operand:V8HI 3 "register_operand" "v")] 161))] - "TARGET_ALTIVEC" - "vsel %0,%1,%2,%3" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vsel_16qi" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v") - (match_operand:V16QI 3 "register_operand" "v")] 162))] - "TARGET_ALTIVEC" - "vsel %0,%1,%2,%3" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vsldoi_4si" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v") - (match_operand:QI 3 "immediate_operand" "i")] 163))] - "TARGET_ALTIVEC" - "vsldoi %0, %1, %2, %3" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vsldoi_4sf" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v") - (match_operand:V4SF 2 "register_operand" "v") - (match_operand:QI 3 "immediate_operand" "i")] 164))] - "TARGET_ALTIVEC" - "vsldoi %0, %1, %2, %3" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vsldoi_8hi" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v") - (match_operand:QI 3 "immediate_operand" "i")] 165))] - "TARGET_ALTIVEC" - "vsldoi %0, %1, %2, %3" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vsldoi_16qi" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v") - (match_operand:QI 3 "immediate_operand" "i")] 166))] - "TARGET_ALTIVEC" - "vsldoi %0, %1, %2, %3" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vupkhsb" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 167))] - "TARGET_ALTIVEC" - "vupkhsb %0, %1" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vupkhpx" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 168))] - "TARGET_ALTIVEC" - "vupkhpx %0, %1" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vupkhsh" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 169))] - "TARGET_ALTIVEC" - "vupkhsh %0, %1" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vupklsb" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")] 170))] - "TARGET_ALTIVEC" - "vupklsb %0, %1" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vupklpx" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 171))] - "TARGET_ALTIVEC" - "vupklpx %0, %1" - [(set_attr "type" "vecperm")]) - -(define_insn "altivec_vupklsh" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")] 172))] - "TARGET_ALTIVEC" - "vupklsh %0, %1" - [(set_attr "type" "vecperm")]) - -;; AltiVec predicates. - -(define_expand "cr6_test_for_zero" - [(set (match_operand:SI 0 "register_operand" "=r") - (eq:SI (reg:CC 74) - (const_int 0)))] - "TARGET_ALTIVEC" - "") - -(define_expand "cr6_test_for_zero_reverse" - [(set (match_operand:SI 0 "register_operand" "=r") - (eq:SI (reg:CC 74) - (const_int 0))) - (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))] - "TARGET_ALTIVEC" - "") -(define_expand "cr6_test_for_lt" - [(set (match_operand:SI 0 "register_operand" "=r") - (lt:SI (reg:CC 74) - (const_int 0)))] - "TARGET_ALTIVEC" - "") - -(define_expand "cr6_test_for_lt_reverse" - [(set (match_operand:SI 0 "register_operand" "=r") - (lt:SI (reg:CC 74) - (const_int 0))) - (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))] - "TARGET_ALTIVEC" - "") - -;; We can get away with generating the opcode on the fly (%3 below) -;; because all the predicates have the same scheduling parameters. - -(define_insn "altivec_predicate_v4si" - [(set (reg:CC 74) - (unspec:CC [(match_operand:V4SI 1 "register_operand" "v") - (match_operand:V4SI 2 "register_operand" "v") - (match_operand 3 "any_operand" "")] 173)) - (clobber (match_scratch:V4SI 0 "=v"))] - "TARGET_ALTIVEC" - "%3 %0,%1,%2" -[(set_attr "type" "veccmp")]) - -(define_insn "altivec_predicate_v4sf" - [(set (reg:CC 74) - (unspec:CC [(match_operand:V4SF 1 "register_operand" "v") - (match_operand:V4SF 2 "register_operand" "v") - (match_operand 3 "any_operand" "")] 174)) - (clobber (match_scratch:V4SF 0 "=v"))] - "TARGET_ALTIVEC" - "%3 %0,%1,%2" -[(set_attr "type" "veccmp")]) - -(define_insn "altivec_predicate_v8hi" - [(set (reg:CC 74) - (unspec:CC [(match_operand:V8HI 1 "register_operand" "v") - (match_operand:V8HI 2 "register_operand" "v") - (match_operand 3 "any_operand" "")] 175)) - (clobber (match_scratch:V8HI 0 "=v"))] - "TARGET_ALTIVEC" - "%3 %0,%1,%2" -[(set_attr "type" "veccmp")]) - -(define_insn "altivec_predicate_v16qi" - [(set (reg:CC 74) - (unspec:CC [(match_operand:V16QI 1 "register_operand" "v") - (match_operand:V16QI 2 "register_operand" "v") - (match_operand 3 "any_operand" "")] 175)) - (clobber (match_scratch:V16QI 0 "=v"))] - "TARGET_ALTIVEC" - "%3 %0,%1,%2" -[(set_attr "type" "veccmp")]) - -(define_insn "altivec_mtvscr" - [(unspec [(match_operand:V4SI 0 "register_operand" "v")] 186)] - "TARGET_ALTIVEC" - "mtvscr %0" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_mfvscr" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(const_int 0)] 187))] - "TARGET_ALTIVEC" - "mfvscr %0" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_dssall" - [(unspec [(const_int 0)] 188)] - "TARGET_ALTIVEC" - "dssall" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_dss" - [(unspec [(match_operand:QI 0 "immediate_operand" "i")] 189)] - "TARGET_ALTIVEC" - "dss %0" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_dst" - [(unspec [(match_operand:SI 0 "register_operand" "b") - (match_operand:SI 1 "register_operand" "r") - (match_operand:QI 2 "immediate_operand" "i")] 190)] - "TARGET_ALTIVEC" - "dst %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_dstt" - [(unspec [(match_operand:SI 0 "register_operand" "b") - (match_operand:SI 1 "register_operand" "r") - (match_operand:QI 2 "immediate_operand" "i")] 191)] - "TARGET_ALTIVEC" - "dstt %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_dstst" - [(unspec [(match_operand:SI 0 "register_operand" "b") - (match_operand:SI 1 "register_operand" "r") - (match_operand:QI 2 "immediate_operand" "i")] 192)] - "TARGET_ALTIVEC" - "dstst %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_dststt" - [(unspec [(match_operand:SI 0 "register_operand" "b") - (match_operand:SI 1 "register_operand" "r") - (match_operand:QI 2 "immediate_operand" "i")] 193)] - "TARGET_ALTIVEC" - "dststt %0,%1,%2" - [(set_attr "type" "vecsimple")]) - -(define_insn "altivec_lvsl" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:SI 1 "register_operand" "b") - (match_operand:SI 2 "register_operand" "r")] 194))] - "TARGET_ALTIVEC" - "lvsl %0,%1,%2" - [(set_attr "type" "vecload")]) - -(define_insn "altivec_lvsr" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:SI 1 "register_operand" "b") - (match_operand:SI 2 "register_operand" "r")] 195))] - "TARGET_ALTIVEC" - "lvsr %0,%1,%2" - [(set_attr "type" "vecload")]) - -;; Parallel some of the LVE* and STV*'s with unspecs because some have -;; identical rtl but different instructions-- and gcc gets confused. - -(define_insn "altivec_lvebx" - [(parallel - [(set (match_operand:V16QI 0 "register_operand" "=v") - (mem:V16QI (plus:SI (match_operand:SI 1 "register_operand" "b") - (match_operand:SI 2 "register_operand" "r")))) - (unspec [(const_int 0)] 196)])] - "TARGET_ALTIVEC" - "lvebx %0,%1,%2" - [(set_attr "type" "vecload")]) - -(define_insn "altivec_lvehx" - [(parallel - [(set (match_operand:V8HI 0 "register_operand" "=v") - (mem:V8HI - (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b") - (match_operand:SI 2 "register_operand" "r")) - (const_int -2)))) - (unspec [(const_int 0)] 197)])] - "TARGET_ALTIVEC" - "lvehx %0,%1,%2" - [(set_attr "type" "vecload")]) - -(define_insn "altivec_lvewx" - [(parallel - [(set (match_operand:V4SI 0 "register_operand" "=v") - (mem:V4SI - (and:SI (plus:SI (match_operand:SI 1 "register_operand" "b") - (match_operand:SI 2 "register_operand" "r")) - (const_int -4)))) - (unspec [(const_int 0)] 198)])] - "TARGET_ALTIVEC" - "lvewx %0,%1,%2" - [(set_attr "type" "vecload")]) - -(define_insn "altivec_lvxl" - [(parallel - [(set (match_operand:V4SI 0 "register_operand" "=v") - (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b") - (match_operand:SI 2 "register_operand" "r")))) - (unspec [(const_int 0)] 213)])] - "TARGET_ALTIVEC" - "lvxl %0,%1,%2" - [(set_attr "type" "vecload")]) - -(define_insn "altivec_lvx" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (mem:V4SI (plus:SI (match_operand:SI 1 "register_operand" "b") - (match_operand:SI 2 "register_operand" "r"))))] - "TARGET_ALTIVEC" - "lvx %0,%1,%2" - [(set_attr "type" "vecload")]) - -(define_insn "altivec_stvx" - [(parallel - [(set (mem:V4SI - (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") - (match_operand:SI 1 "register_operand" "r")) - (const_int -16))) - (match_operand:V4SI 2 "register_operand" "v")) - (unspec [(const_int 0)] 201)])] - "TARGET_ALTIVEC" - "stvx %2,%0,%1" - [(set_attr "type" "vecstore")]) - -(define_insn "altivec_stvxl" - [(parallel - [(set (mem:V4SI - (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") - (match_operand:SI 1 "register_operand" "r")) - (const_int -16))) - (match_operand:V4SI 2 "register_operand" "v")) - (unspec [(const_int 0)] 202)])] - "TARGET_ALTIVEC" - "stvxl %2,%0,%1" - [(set_attr "type" "vecstore")]) - -(define_insn "altivec_stvebx" - [(parallel - [(set (mem:V16QI - (plus:SI (match_operand:SI 0 "register_operand" "b") - (match_operand:SI 1 "register_operand" "r"))) - (match_operand:V16QI 2 "register_operand" "v")) - (unspec [(const_int 0)] 203)])] - "TARGET_ALTIVEC" - "stvebx %2,%0,%1" - [(set_attr "type" "vecstore")]) - -(define_insn "altivec_stvehx" - [(parallel - [(set (mem:V8HI - (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") - (match_operand:SI 1 "register_operand" "r")) - (const_int -2))) - (match_operand:V8HI 2 "register_operand" "v")) - (unspec [(const_int 0)] 204)])] - "TARGET_ALTIVEC" - "stvehx %2,%0,%1" - [(set_attr "type" "vecstore")]) - -(define_insn "altivec_stvewx" - [(parallel - [(set (mem:V4SI - (and:SI (plus:SI (match_operand:SI 0 "register_operand" "b") - (match_operand:SI 1 "register_operand" "r")) - (const_int -4))) - (match_operand:V4SI 2 "register_operand" "v")) - (unspec [(const_int 0)] 205)])] - "TARGET_ALTIVEC" - "stvewx %2,%0,%1" - [(set_attr "type" "vecstore")]) - -(define_insn "absv16qi2" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (abs:V16QI (match_operand:V16QI 1 "register_operand" "v"))) - (clobber (match_scratch:V16QI 2 "=v")) - (clobber (match_scratch:V16QI 3 "=v"))] - "TARGET_ALTIVEC" - "vspltisb %2,0\;vsububm %3,%2,%1\;vmaxsb %0,%1,%3" - [(set_attr "type" "altivec") - (set_attr "length" "12")]) - -(define_insn "absv8hi2" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (abs:V8HI (match_operand:V8HI 1 "register_operand" "v"))) - (clobber (match_scratch:V8HI 2 "=v")) - (clobber (match_scratch:V8HI 3 "=v"))] - "TARGET_ALTIVEC" - "vspltisb %2,0\;vsubuhm %3,%2,%1\;vmaxsh %0,%1,%3" - [(set_attr "type" "altivec") - (set_attr "length" "12")]) - -(define_insn "absv4si2" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (abs:V4SI (match_operand:V4SI 1 "register_operand" "v"))) - (clobber (match_scratch:V4SI 2 "=v")) - (clobber (match_scratch:V4SI 3 "=v"))] - "TARGET_ALTIVEC" - "vspltisb %2,0\;vsubuwm %3,%2,%1\;vmaxsw %0,%1,%3" - [(set_attr "type" "altivec") - (set_attr "length" "12")]) - -(define_insn "absv4sf2" - [(set (match_operand:V4SF 0 "register_operand" "=v") - (abs:V4SF (match_operand:V4SF 1 "register_operand" "v"))) - (clobber (match_scratch:V4SF 2 "=v")) - (clobber (match_scratch:V4SF 3 "=v"))] - "TARGET_ALTIVEC" - "vspltisw %2, -1\;vslw %3,%2,%2\;vandc %0,%1,%3" - [(set_attr "type" "altivec") - (set_attr "length" "12")]) - -(define_insn "altivec_abss_v16qi" - [(set (match_operand:V16QI 0 "register_operand" "=v") - (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")] 210)) - (clobber (match_scratch:V16QI 2 "=v")) - (clobber (match_scratch:V16QI 3 "=v"))] - "TARGET_ALTIVEC" - "vspltisb %2,0\;vsubsbs %3,%2,%1\;vmaxsb %0,%1,%3" - [(set_attr "type" "altivec") - (set_attr "length" "12")]) - -(define_insn "altivec_abss_v8hi" - [(set (match_operand:V8HI 0 "register_operand" "=v") - (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")] 211)) - (clobber (match_scratch:V8HI 2 "=v")) - (clobber (match_scratch:V8HI 3 "=v"))] - "TARGET_ALTIVEC" - "vspltisb %2,0\;vsubshs %3,%2,%1\;vmaxsh %0,%1,%3" - [(set_attr "type" "altivec") - (set_attr "length" "12")]) - -(define_insn "altivec_abss_v4si" - [(set (match_operand:V4SI 0 "register_operand" "=v") - (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")] 212)) - (clobber (match_scratch:V4SI 2 "=v")) - (clobber (match_scratch:V4SI 3 "=v"))] - "TARGET_ALTIVEC" - "vspltisb %2,0\;vsubsws %3,%2,%1\;vmaxsw %0,%1,%3" - [(set_attr "type" "altivec") - (set_attr "length" "12")]) +(include "altivec.md") +(include "spe.md") diff --git a/contrib/gcc/config/rs6000/rtems.h b/contrib/gcc/config/rs6000/rtems.h index cc8295a..7e75846 100644 --- a/contrib/gcc/config/rs6000/rtems.h +++ b/contrib/gcc/config/rs6000/rtems.h @@ -21,9 +21,17 @@ Boston, MA 02111-1307, USA. */ /* Specify predefined symbols in preprocessor. */ -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "-DPPC -D__rtems__ -D__USE_INIT_FINI__ \ - -Asystem=rtems -Acpu=powerpc -Amachine=powerpc" +#undef TARGET_OS_CPP_BUILTINS +#define TARGET_OS_CPP_BUILTINS() \ + do \ + { \ + builtin_define_std ("PPC"); \ + builtin_define ("__rtems__"); \ + builtin_assert ("system=rtems"); \ + builtin_assert ("cpu=powerpc"); \ + builtin_assert ("machine=powerpc"); \ + } \ + while (0) #undef CPP_OS_DEFAULT_SPEC #define CPP_OS_DEFAULT_SPEC "%(cpp_os_rtems)" diff --git a/contrib/gcc/config/rs6000/spe.h b/contrib/gcc/config/rs6000/spe.h new file mode 100644 index 0000000..b15dac5 --- /dev/null +++ b/contrib/gcc/config/rs6000/spe.h @@ -0,0 +1,1096 @@ +/* PowerPC E500 user include file. + Copyright (C) 2002, 2003 Free Software Foundation, Inc. + Contributed by Aldy Hernandez (aldyh@redhat.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* As a special exception, if you include this header file into source + files compiled by GCC, this header file does not by itself cause + the resulting executable to be covered by the GNU General Public + License. This exception does not however invalidate any other + reasons why the executable file might be covered by the GNU General + Public License. */ + +#ifndef _SPE_H +#define _SPE_H + +#define __vector __attribute__((vector_size(8))) + +typedef int int32_t; +typedef unsigned uint32_t; +typedef short int16_t; +typedef unsigned short uint16_t; +typedef long long int64_t; +typedef unsigned long long uint64_t; + +typedef short __vector __ev64_s16__; +typedef unsigned short __vector __ev64_u16__; +typedef int __vector __ev64_s32__; +typedef unsigned __vector __ev64_u32__; +typedef long long __vector __ev64_s64__; +typedef unsigned long long __vector __ev64_u64__; +typedef float __vector __ev64_fs__; +typedef int __vector __ev64_opaque__; + +#define __v2si __ev64_opaque__ +#define __v2sf __ev64_fs__ + +#define __ev_addw(a,b) __builtin_spe_evaddw((__v2si) (a), (__v2si) (b)) +#define __ev_addiw(a,b) __builtin_spe_evaddiw ((__v2si) (a), (b)) +#define __ev_subfw(a,b) __builtin_spe_evsubfw ((__v2si) (a), (__v2si) (b)) +#define __ev_subw(a,b) __builtin_spe_evsubfw ((__v2si) (b), (__v2si) (a)) +/* ??? The spe_evsubifw pattern accepts operands reversed, so we need to also + reverse them here between the intrinsic and the builtin function. */ +#define __ev_subifw(a,b) __builtin_spe_evsubifw ((__v2si) (b), (a)) +#define __ev_subiw(a,b) __builtin_spe_evsubifw ((__v2si) (a), (b)) +#define __ev_abs(a) __builtin_spe_evabs ((__v2si) (a)) +#define __ev_neg(a) __builtin_spe_evneg ((__v2si) (a)) +#define __ev_extsb(a) __builtin_spe_evextsb ((__v2si) (a)) +#define __ev_extsh(a) __builtin_spe_evextsh ((__v2si) (a)) +#define __ev_and(a,b) __builtin_spe_evand ((__v2si) (a), (__v2si) (b)) +#define __ev_or(a,b) __builtin_spe_evor ((__v2si) (a), (__v2si) (b)) +#define __ev_xor(a,b) __builtin_spe_evxor ((__v2si) (a), (__v2si) (b)) +#define __ev_nand(a,b) __builtin_spe_evnand ((__v2si) (a), (__v2si) (b)) +#define __ev_nor(a,b) __builtin_spe_evnor ((__v2si) (a), (__v2si) (b)) +#define __ev_eqv(a,b) __builtin_spe_eveqv ((__v2si) (a), (__v2si) (b)) +#define __ev_andc(a,b) __builtin_spe_evandc ((__v2si) (a), (__v2si) (b)) +#define __ev_orc(a,b) __builtin_spe_evorc ((__v2si) (a), (__v2si) (b)) +#define __ev_rlw(a,b) __builtin_spe_evrlw ((__v2si) (a), (__v2si) (b)) +#define __ev_rlwi(a,b) __builtin_spe_evrlwi ((__v2si) (a), (b)) +#define __ev_slw(a,b) __builtin_spe_evslw ((__v2si) (a), (__v2si) (b)) +#define __ev_slwi(a,b) __builtin_spe_evslwi ((__v2si) (a), (b)) +#define __ev_srws(a,b) __builtin_spe_evsrws ((__v2si) (a), (__v2si) (b)) +#define __ev_srwu(a,b) __builtin_spe_evsrwu ((__v2si) (a), (__v2si) (b)) +#define __ev_srwis(a,b) __builtin_spe_evsrwis ((__v2si) (a), (b)) +#define __ev_srwiu(a,b) __builtin_spe_evsrwiu ((__v2si) (a), (b)) +#define __ev_cntlzw(a) __builtin_spe_evcntlzw ((__v2si) (a)) +#define __ev_cntlsw(a) __builtin_spe_evcntlsw ((__v2si) (a)) +#define __ev_rndw(a) __builtin_spe_evrndw ((__v2si) (a)) +#define __ev_mergehi(a,b) __builtin_spe_evmergehi ((__v2si) (a), (__v2si) (b)) +#define __ev_mergelo(a,b) __builtin_spe_evmergelo ((__v2si) (a), (__v2si) (b)) +#define __ev_mergelohi(a,b) __builtin_spe_evmergelohi ((__v2si) (a), (__v2si) (b)) +#define __ev_mergehilo(a,b) __builtin_spe_evmergehilo ((__v2si) (a), (__v2si) (b)) +#define __ev_splati(a) __builtin_spe_evsplati ((a)) +#define __ev_splatfi(a) __builtin_spe_evsplatfi ((a)) +#define __ev_divws(a,b) __builtin_spe_evdivws ((__v2si) (a), (__v2si) (b)) +#define __ev_divwu(a,b) __builtin_spe_evdivwu ((__v2si) (a), (__v2si) (b)) +#define __ev_mra(a) __builtin_spe_evmra ((__v2si) (a)) + +#define __brinc __builtin_spe_brinc + +/* Loads. */ + +#define __ev_lddx(a,b) __builtin_spe_evlddx ((void *)(a), (b)) +#define __ev_ldwx(a,b) __builtin_spe_evldwx ((void *)(a), (b)) +#define __ev_ldhx(a,b) __builtin_spe_evldhx ((void *)(a), (b)) +#define __ev_lwhex(a,b) __builtin_spe_evlwhex ((a), (b)) +#define __ev_lwhoux(a,b) __builtin_spe_evlwhoux ((a), (b)) +#define __ev_lwhosx(a,b) __builtin_spe_evlwhosx ((a), (b)) +#define __ev_lwwsplatx(a,b) __builtin_spe_evlwwsplatx ((a), (b)) +#define __ev_lwhsplatx(a,b) __builtin_spe_evlwhsplatx ((a), (b)) +#define __ev_lhhesplatx(a,b) __builtin_spe_evlhhesplatx ((a), (b)) +#define __ev_lhhousplatx(a,b) __builtin_spe_evlhhousplatx ((a), (b)) +#define __ev_lhhossplatx(a,b) __builtin_spe_evlhhossplatx ((a), (b)) +#define __ev_ldd(a,b) __builtin_spe_evldd ((void *)(a), (b)) +#define __ev_ldw(a,b) __builtin_spe_evldw ((void *)(a), (b)) +#define __ev_ldh(a,b) __builtin_spe_evldh ((void *)(a), (b)) +#define __ev_lwhe(a,b) __builtin_spe_evlwhe ((a), (b)) +#define __ev_lwhou(a,b) __builtin_spe_evlwhou ((a), (b)) +#define __ev_lwhos(a,b) __builtin_spe_evlwhos ((a), (b)) +#define __ev_lwwsplat(a,b) __builtin_spe_evlwwsplat ((a), (b)) +#define __ev_lwhsplat(a,b) __builtin_spe_evlwhsplat ((a), (b)) +#define __ev_lhhesplat(a,b) __builtin_spe_evlhhesplat ((a), (b)) +#define __ev_lhhousplat(a,b) __builtin_spe_evlhhousplat ((a), (b)) +#define __ev_lhhossplat(a,b) __builtin_spe_evlhhossplat ((a), (b)) + +/* Stores. */ + +#define __ev_stddx(a,b,c) __builtin_spe_evstddx ((__v2si)(a), (void *)(b), (c)) +#define __ev_stdwx(a,b,c) __builtin_spe_evstdwx ((__v2si)(a), (void *)(b), (c)) +#define __ev_stdhx(a,b,c) __builtin_spe_evstdhx ((__v2si)(a), (void *)(b), (c)) +#define __ev_stwwex(a,b,c) __builtin_spe_evstwwex ((__v2si)(a), (b), (c)) +#define __ev_stwwox(a,b,c) __builtin_spe_evstwwox ((__v2si)(a), (b), (c)) +#define __ev_stwhex(a,b,c) __builtin_spe_evstwhex ((__v2si)(a), (b), (c)) +#define __ev_stwhox(a,b,c) __builtin_spe_evstwhox ((__v2si)(a), (b), (c)) +#define __ev_stdd(a,b,c) __builtin_spe_evstdd ((__v2si)(a), (void *)(b), (c)) +#define __ev_stdw(a,b,c) __builtin_spe_evstdw ((__v2si)(a), (void *)(b), (c)) +#define __ev_stdh(a,b,c) __builtin_spe_evstdh ((__v2si)(a), (void *)(b), (c)) +#define __ev_stwwe(a,b,c) __builtin_spe_evstwwe ((__v2si)(a), (b), (c)) +#define __ev_stwwo(a,b,c) __builtin_spe_evstwwo ((__v2si)(a), (b), (c)) +#define __ev_stwhe(a,b,c) __builtin_spe_evstwhe ((__v2si)(a), (b), (c)) +#define __ev_stwho(a,b,c) __builtin_spe_evstwho ((__v2si)(a), (b), (c)) + +/* Fixed point complex. */ + +#define __ev_mhossf(a, b) __builtin_spe_evmhossf ((__v2si) (a), (__v2si) (b)) +#define __ev_mhosmf(a, b) __builtin_spe_evmhosmf ((__v2si) (a), (__v2si) (b)) +#define __ev_mhosmi(a, b) __builtin_spe_evmhosmi ((__v2si) (a), (__v2si) (b)) +#define __ev_mhoumi(a, b) __builtin_spe_evmhoumi ((__v2si) (a), (__v2si) (b)) +#define __ev_mhessf(a, b) __builtin_spe_evmhessf ((__v2si) (a), (__v2si) (b)) +#define __ev_mhesmf(a, b) __builtin_spe_evmhesmf ((__v2si) (a), (__v2si) (b)) +#define __ev_mhesmi(a, b) __builtin_spe_evmhesmi ((__v2si) (a), (__v2si) (b)) +#define __ev_mheumi(a, b) __builtin_spe_evmheumi ((__v2si) (a), (__v2si) (b)) +#define __ev_mhossfa(a, b) __builtin_spe_evmhossfa ((__v2si) (a), (__v2si) (b)) +#define __ev_mhosmfa(a, b) __builtin_spe_evmhosmfa ((__v2si) (a), (__v2si) (b)) +#define __ev_mhosmia(a, b) __builtin_spe_evmhosmia ((__v2si) (a), (__v2si) (b)) +#define __ev_mhoumia(a, b) __builtin_spe_evmhoumia ((__v2si) (a), (__v2si) (b)) +#define __ev_mhessfa(a, b) __builtin_spe_evmhessfa ((__v2si) (a), (__v2si) (b)) +#define __ev_mhesmfa(a, b) __builtin_spe_evmhesmfa ((__v2si) (a), (__v2si) (b)) +#define __ev_mhesmia(a, b) __builtin_spe_evmhesmia ((__v2si) (a), (__v2si) (b)) +#define __ev_mheumia(a, b) __builtin_spe_evmheumia ((__v2si) (a), (__v2si) (b)) + +#define __ev_mhoumf __ev_mhoumi +#define __ev_mheumf __ev_mheumi +#define __ev_mhoumfa __ev_mhoumia +#define __ev_mheumfa __ev_mheumia + +#define __ev_mhossfaaw(a, b) __builtin_spe_evmhossfaaw ((__v2si) (a), (__v2si) (b)) +#define __ev_mhossiaaw(a, b) __builtin_spe_evmhossiaaw ((__v2si) (a), (__v2si) (b)) +#define __ev_mhosmfaaw(a, b) __builtin_spe_evmhosmfaaw ((__v2si) (a), (__v2si) (b)) +#define __ev_mhosmiaaw(a, b) __builtin_spe_evmhosmiaaw ((__v2si) (a), (__v2si) (b)) +#define __ev_mhousiaaw(a, b) __builtin_spe_evmhousiaaw ((__v2si) (a), (__v2si) (b)) +#define __ev_mhoumiaaw(a, b) __builtin_spe_evmhoumiaaw ((__v2si) (a), (__v2si) (b)) +#define __ev_mhessfaaw(a, b) __builtin_spe_evmhessfaaw ((__v2si) (a), (__v2si) (b)) +#define __ev_mhessiaaw(a, b) __builtin_spe_evmhessiaaw ((__v2si) (a), (__v2si) (b)) +#define __ev_mhesmfaaw(a, b) __builtin_spe_evmhesmfaaw ((__v2si) (a), (__v2si) (b)) +#define __ev_mhesmiaaw(a, b) __builtin_spe_evmhesmiaaw ((__v2si) (a), (__v2si) (b)) +#define __ev_mheusiaaw(a, b) __builtin_spe_evmheusiaaw ((__v2si) (a), (__v2si) (b)) +#define __ev_mheumiaaw(a, b) __builtin_spe_evmheumiaaw ((__v2si) (a), (__v2si) (b)) + +#define __ev_mhousfaaw __ev_mhousiaaw +#define __ev_mhoumfaaw __ev_mhoumiaaw +#define __ev_mheusfaaw __ev_mheusiaaw +#define __ev_mheumfaaw __ev_mheumiaaw + +#define __ev_mhossfanw(a, b) __builtin_spe_evmhossfanw ((__v2si) (a), (__v2si) (b)) +#define __ev_mhossianw(a, b) __builtin_spe_evmhossianw ((__v2si) (a), (__v2si) (b)) +#define __ev_mhosmfanw(a, b) __builtin_spe_evmhosmfanw ((__v2si) (a), (__v2si) (b)) +#define __ev_mhosmianw(a, b) __builtin_spe_evmhosmianw ((__v2si) (a), (__v2si) (b)) +#define __ev_mhousianw(a, b) __builtin_spe_evmhousianw ((__v2si) (a), (__v2si) (b)) +#define __ev_mhoumianw(a, b) __builtin_spe_evmhoumianw ((__v2si) (a), (__v2si) (b)) +#define __ev_mhessfanw(a, b) __builtin_spe_evmhessfanw ((__v2si) (a), (__v2si) (b)) +#define __ev_mhessianw(a, b) __builtin_spe_evmhessianw ((__v2si) (a), (__v2si) (b)) +#define __ev_mhesmfanw(a, b) __builtin_spe_evmhesmfanw ((__v2si) (a), (__v2si) (b)) +#define __ev_mhesmianw(a, b) __builtin_spe_evmhesmianw ((__v2si) (a), (__v2si) (b)) +#define __ev_mheusianw(a, b) __builtin_spe_evmheusianw ((__v2si) (a), (__v2si) (b)) +#define __ev_mheumianw(a, b) __builtin_spe_evmheumianw ((__v2si) (a), (__v2si) (b)) + +#define __ev_mhousfanw __ev_mhousianw +#define __ev_mhoumfanw __ev_mhoumianw +#define __ev_mheusfanw __ev_mheusianw +#define __ev_mheumfanw __ev_mheumianw + +#define __ev_mhogsmfaa(a, b) __builtin_spe_evmhogsmfaa ((__v2si) (a), (__v2si) (b)) +#define __ev_mhogsmiaa(a, b) __builtin_spe_evmhogsmiaa ((__v2si) (a), (__v2si) (b)) +#define __ev_mhogumiaa(a, b) __builtin_spe_evmhogumiaa ((__v2si) (a), (__v2si) (b)) +#define __ev_mhegsmfaa(a, b) __builtin_spe_evmhegsmfaa ((__v2si) (a), (__v2si) (b)) +#define __ev_mhegsmiaa(a, b) __builtin_spe_evmhegsmiaa ((__v2si) (a), (__v2si) (b)) +#define __ev_mhegumiaa(a, b) __builtin_spe_evmhegumiaa ((__v2si) (a), (__v2si) (b)) + +#define __ev_mhogumfaa __ev_mhogumiaa +#define __ev_mhegumfaa __ev_mhegumiaa + +#define __ev_mhogsmfan(a, b) __builtin_spe_evmhogsmfan ((__v2si) (a), (__v2si) (b)) +#define __ev_mhogsmian(a, b) __builtin_spe_evmhogsmian ((__v2si) (a), (__v2si) (b)) +#define __ev_mhogumian(a, b) __builtin_spe_evmhogumian ((__v2si) (a), (__v2si) (b)) +#define __ev_mhegsmfan(a, b) __builtin_spe_evmhegsmfan ((__v2si) (a), (__v2si) (b)) +#define __ev_mhegsmian(a, b) __builtin_spe_evmhegsmian ((__v2si) (a), (__v2si) (b)) +#define __ev_mhegumian(a, b) __builtin_spe_evmhegumian ((__v2si) (a), (__v2si) (b)) + +#define __ev_mhogumfan __ev_mhogumian +#define __ev_mhegumfan __ev_mhegumian + +#define __ev_mwhssf(a, b) __builtin_spe_evmwhssf ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhsmf(a, b) __builtin_spe_evmwhsmf ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhsmi(a, b) __builtin_spe_evmwhsmi ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhumi(a, b) __builtin_spe_evmwhumi ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhssfa(a, b) __builtin_spe_evmwhssfa ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhsmfa(a, b) __builtin_spe_evmwhsmfa ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhsmia(a, b) __builtin_spe_evmwhsmia ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhumia(a, b) __builtin_spe_evmwhumia ((__v2si) (a), (__v2si) (b)) + +#define __ev_mwhumf __ev_mwhumi +#define __ev_mwhumfa __ev_mwhumia + +#define __ev_mwlumi(a, b) __builtin_spe_evmwlumi ((__v2si) (a), (__v2si) (b)) +#define __ev_mwlumia(a, b) __builtin_spe_evmwlumia ((__v2si) (a), (__v2si) (b)) +#define __ev_mwlumiaaw(a, b) __builtin_spe_evmwlumiaaw ((__v2si) (a), (__v2si) (b)) + +#define __ev_mwlssiaaw(a, b) __builtin_spe_evmwlssiaaw ((__v2si) (a), (__v2si) (b)) +#define __ev_mwlsmiaaw(a, b) __builtin_spe_evmwlsmiaaw ((__v2si) (a), (__v2si) (b)) +#define __ev_mwlusiaaw(a, b) __builtin_spe_evmwlusiaaw ((__v2si) (a), (__v2si) (b)) +#define __ev_mwlusiaaw(a, b) __builtin_spe_evmwlusiaaw ((__v2si) (a), (__v2si) (b)) + +#define __ev_mwlssianw(a, b) __builtin_spe_evmwlssianw ((__v2si) (a), (__v2si) (b)) +#define __ev_mwlsmianw(a, b) __builtin_spe_evmwlsmianw ((__v2si) (a), (__v2si) (b)) +#define __ev_mwlusianw(a, b) __builtin_spe_evmwlusianw ((__v2si) (a), (__v2si) (b)) +#define __ev_mwlumianw(a, b) __builtin_spe_evmwlumianw ((__v2si) (a), (__v2si) (b)) + +#define __ev_mwssf(a, b) __builtin_spe_evmwssf ((__v2si) (a), (__v2si) (b)) +#define __ev_mwsmf(a, b) __builtin_spe_evmwsmf ((__v2si) (a), (__v2si) (b)) +#define __ev_mwsmi(a, b) __builtin_spe_evmwsmi ((__v2si) (a), (__v2si) (b)) +#define __ev_mwumi(a, b) __builtin_spe_evmwumi ((__v2si) (a), (__v2si) (b)) +#define __ev_mwssfa(a, b) __builtin_spe_evmwssfa ((__v2si) (a), (__v2si) (b)) +#define __ev_mwsmfa(a, b) __builtin_spe_evmwsmfa ((__v2si) (a), (__v2si) (b)) +#define __ev_mwsmia(a, b) __builtin_spe_evmwsmia ((__v2si) (a), (__v2si) (b)) +#define __ev_mwumia(a, b) __builtin_spe_evmwumia ((__v2si) (a), (__v2si) (b)) + +#define __ev_mwumf __ev_mwumi +#define __ev_mwumfa __ev_mwumia + +#define __ev_mwssfaa(a, b) __builtin_spe_evmwssfaa ((__v2si) (a), (__v2si) (b)) +#define __ev_mwsmfaa(a, b) __builtin_spe_evmwsmfaa ((__v2si) (a), (__v2si) (b)) +#define __ev_mwsmiaa(a, b) __builtin_spe_evmwsmiaa ((__v2si) (a), (__v2si) (b)) +#define __ev_mwumiaa(a, b) __builtin_spe_evmwumiaa ((__v2si) (a), (__v2si) (b)) + +#define __ev_mwumfaa __ev_mwumiaa + +#define __ev_mwssfan(a, b) __builtin_spe_evmwssfan ((__v2si) (a), (__v2si) (b)) +#define __ev_mwsmfan(a, b) __builtin_spe_evmwsmfan ((__v2si) (a), (__v2si) (b)) +#define __ev_mwsmian(a, b) __builtin_spe_evmwsmian ((__v2si) (a), (__v2si) (b)) +#define __ev_mwumian(a, b) __builtin_spe_evmwumian ((__v2si) (a), (__v2si) (b)) + +#define __ev_mwumfan __ev_mwumian + +#define __ev_addssiaaw(a) __builtin_spe_evaddssiaaw ((__v2si) (a)) +#define __ev_addsmiaaw(a) __builtin_spe_evaddsmiaaw ((__v2si) (a)) +#define __ev_addusiaaw(a) __builtin_spe_evaddusiaaw ((__v2si) (a)) +#define __ev_addumiaaw(a) __builtin_spe_evaddumiaaw ((__v2si) (a)) + +#define __ev_addusfaaw __ev_addusiaaw +#define __ev_addumfaaw __ev_addumiaaw +#define __ev_addsmfaaw __ev_addsmiaaw +#define __ev_addssfaaw __ev_addssiaaw + +#define __ev_subfssiaaw(a) __builtin_spe_evsubfssiaaw ((__v2si) (a)) +#define __ev_subfsmiaaw(a) __builtin_spe_evsubfsmiaaw ((__v2si) (a)) +#define __ev_subfusiaaw(a) __builtin_spe_evsubfusiaaw ((__v2si) (a)) +#define __ev_subfumiaaw(a) __builtin_spe_evsubfumiaaw ((__v2si) (a)) + +#define __ev_subfusfaaw __ev_subfusiaaw +#define __ev_subfumfaaw __ev_subfumiaaw +#define __ev_subfsmfaaw __ev_subfsmiaaw +#define __ev_subfssfaaw __ev_subfssiaaw + +/* Floating Point SIMD Instructions */ + +/* These all return V2SF, but we need to cast them to V2SI + because the SPE expect all functions to be __ev64_opaque__. */ + +#define __ev_fsabs(a) ((__v2si) __builtin_spe_evfsabs ((__v2sf) (a))) +#define __ev_fsnabs(a) ((__v2si) __builtin_spe_evfsnabs ((__v2sf) (a))) +#define __ev_fsneg(a) ((__v2si) __builtin_spe_evfsneg ((__v2sf) (a))) +#define __ev_fsadd(a, b) ((__v2si) __builtin_spe_evfsadd ((__v2sf) (a), (__v2sf) (b))) +#define __ev_fssub(a, b) ((__v2si) __builtin_spe_evfssub ((__v2sf) (a), (__v2sf) (b))) +#define __ev_fsmul(a, b) ((__v2si) __builtin_spe_evfsmul ((__v2sf) (a), (__v2sf) b)) +#define __ev_fsdiv(a, b) ((__v2si) __builtin_spe_evfsdiv ((__v2sf) (a), (__v2sf) b)) +#define __ev_fscfui(a) ((__v2si) __builtin_spe_evfscfui ((__v2si) (a))) +#define __ev_fscfsi(a) ((__v2si) __builtin_spe_evfscfsi ((__v2sf) (a))) +#define __ev_fscfuf(a) ((__v2si) __builtin_spe_evfscfuf ((__v2sf) (a))) +#define __ev_fscfsf(a) ((__v2si) __builtin_spe_evfscfsf ((__v2sf) (a))) +#define __ev_fsctui(a) ((__v2si) __builtin_spe_evfsctui ((__v2sf) (a))) +#define __ev_fsctsi(a) ((__v2si) __builtin_spe_evfsctsi ((__v2sf) (a))) +#define __ev_fsctuf(a) ((__v2si) __builtin_spe_evfsctuf ((__v2sf) (a))) +#define __ev_fsctsf(a) ((__v2si) __builtin_spe_evfsctsf ((__v2sf) (a))) +#define __ev_fsctuiz(a) ((__v2si) __builtin_spe_evfsctuiz ((__v2sf) (a))) +#define __ev_fsctsiz(a) ((__v2si) __builtin_spe_evfsctsiz ((__v2sf) (a))) + +/* NOT SUPPORTED IN FIRST e500, support via two instructions: */ + +#define __ev_mwhusfaaw __ev_mwhusiaaw +#define __ev_mwhumfaaw __ev_mwhumiaaw +#define __ev_mwhusfanw __ev_mwhusianw +#define __ev_mwhumfanw __ev_mwhumianw +#define __ev_mwhgumfaa __ev_mwhgumiaa +#define __ev_mwhgumfan __ev_mwhgumian + +#define __ev_mwhgssfaa(a, b) __internal_ev_mwhgssfaa ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhgsmfaa(a, b) __internal_ev_mwhgsmfaa ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhgsmiaa(a, b) __internal_ev_mwhgsmiaa ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhgumiaa(a, b) __internal_ev_mwhgumiaa ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhgssfan(a, b) __internal_ev_mwhgssfan ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhgsmfan(a, b) __internal_ev_mwhgsmfan ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhgsmian(a, b) __internal_ev_mwhgsmian ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhgumian(a, b) __internal_ev_mwhgumian ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhssiaaw(a, b) __internal_ev_mwhssiaaw ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhssfaaw(a, b) __internal_ev_mwhssfaaw ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhsmfaaw(a, b) __internal_ev_mwhsmfaaw ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhsmiaaw(a, b) __internal_ev_mwhsmiaaw ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhusiaaw(a, b) __internal_ev_mwhusiaaw ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhumiaaw(a, b) __internal_ev_mwhumiaaw ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhssfanw(a, b) __internal_ev_mwhssfanw ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhssianw(a, b) __internal_ev_mwhssianw ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhsmfanw(a, b) __internal_ev_mwhsmfanw ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhsmianw(a, b) __internal_ev_mwhsmianw ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhusianw(a, b) __internal_ev_mwhusianw ((__v2si) (a), (__v2si) (b)) +#define __ev_mwhumianw(a, b) __internal_ev_mwhumianw ((__v2si) (a), (__v2si) (b)) + +static inline __ev64_opaque__ +__internal_ev_mwhssfaaw (__ev64_opaque__ a, __ev64_opaque__ b) +{ + __ev64_opaque__ t; + + t = __ev_mwhssf (a, b); + return __ev_addssiaaw (t); +} + +static inline __ev64_opaque__ +__internal_ev_mwhssiaaw (__ev64_opaque__ a, __ev64_opaque__ b) +{ + __ev64_opaque__ t; + + t = __ev_mwhsmi (a, b); + return __ev_addssiaaw (t); +} + +static inline __ev64_opaque__ +__internal_ev_mwhsmfaaw (__ev64_opaque__ a, __ev64_opaque__ b) +{ + __ev64_opaque__ t; + + t = __ev_mwhsmf (a, b); + return __ev_addsmiaaw (t); +} + +static inline __ev64_opaque__ +__internal_ev_mwhsmiaaw (__ev64_opaque__ a, __ev64_opaque__ b) +{ + __ev64_opaque__ t; + + t = __ev_mwhsmi (a, b); + return __ev_addsmiaaw (t); +} + +static inline __ev64_opaque__ +__internal_ev_mwhusiaaw (__ev64_opaque__ a, __ev64_opaque__ b) +{ + __ev64_opaque__ t; + + t = __ev_mwhumi (a, b); + return __ev_addusiaaw (t); +} + +static inline __ev64_opaque__ +__internal_ev_mwhumiaaw (__ev64_opaque__ a, __ev64_opaque__ b) +{ + __ev64_opaque__ t; + + t = __ev_mwhumi (a, b); + return __ev_addumiaaw (t); +} + +static inline __ev64_opaque__ +__internal_ev_mwhssfanw (__ev64_opaque__ a, __ev64_opaque__ b) +{ + __ev64_opaque__ t; + + t = __ev_mwhssf (a, b); + return __ev_subfssiaaw (t); +} + +static inline __ev64_opaque__ +__internal_ev_mwhssianw (__ev64_opaque__ a, __ev64_opaque__ b) +{ + __ev64_opaque__ t; + + t = __ev_mwhsmi (a, b); + return __ev_subfssiaaw (t); +} + +static inline __ev64_opaque__ +__internal_ev_mwhsmfanw (__ev64_opaque__ a, __ev64_opaque__ b) +{ + __ev64_opaque__ t; + + t = __ev_mwhsmf (a, b); + return __ev_subfsmiaaw (t); +} + +static inline __ev64_opaque__ +__internal_ev_mwhsmianw (__ev64_opaque__ a, __ev64_opaque__ b) +{ + __ev64_opaque__ t; + + t = __ev_mwhsmi (a, b); + return __ev_subfsmiaaw (t); +} + +static inline __ev64_opaque__ +__internal_ev_mwhusianw (__ev64_opaque__ a, __ev64_opaque__ b) +{ + __ev64_opaque__ t; + + t = __ev_mwhumi (a, b); + return __ev_subfusiaaw (t); +} + +static inline __ev64_opaque__ +__internal_ev_mwhumianw (__ev64_opaque__ a, __ev64_opaque__ b) +{ + __ev64_opaque__ t; + + t = __ev_mwhumi (a, b); + return __ev_subfumiaaw (t); +} + +static inline __ev64_opaque__ +__internal_ev_mwhgssfaa (__ev64_opaque__ a, __ev64_opaque__ b) +{ + __ev64_opaque__ t; + + t = __ev_mwhssf (a, b); + return __ev_mwsmiaa (t, ((__ev64_s32__){1, 1})); +} + +static inline __ev64_opaque__ +__internal_ev_mwhgsmfaa (__ev64_opaque__ a, __ev64_opaque__ b) +{ + __ev64_opaque__ t; + + t = __ev_mwhsmf (a, b); + return __ev_mwsmiaa (t, ((__ev64_s32__){1, 1})); +} + +static inline __ev64_opaque__ +__internal_ev_mwhgsmiaa (__ev64_opaque__ a, __ev64_opaque__ b) +{ + __ev64_opaque__ t; + + t = __ev_mwhsmi (a, b); + return __ev_mwsmiaa (t, ((__ev64_s32__){1, 1})); +} + +static inline __ev64_opaque__ +__internal_ev_mwhgumiaa (__ev64_opaque__ a, __ev64_opaque__ b) +{ + __ev64_opaque__ t; + + t = __ev_mwhumi (a, b); + return __ev_mwumiaa (t, ((__ev64_s32__){1, 1})); +} + +static inline __ev64_opaque__ +__internal_ev_mwhgssfan (__ev64_opaque__ a, __ev64_opaque__ b) +{ + __ev64_opaque__ t; + + t = __ev_mwhssf (a, b); + return __ev_mwsmian (t, ((__ev64_s32__){1, 1})); +} + +static inline __ev64_opaque__ +__internal_ev_mwhgsmfan (__ev64_opaque__ a, __ev64_opaque__ b) +{ + __ev64_opaque__ t; + + t = __ev_mwhsmf (a, b); + return __ev_mwsmian (t, ((__ev64_s32__){1, 1})); +} + +static inline __ev64_opaque__ +__internal_ev_mwhgsmian (__ev64_opaque__ a, __ev64_opaque__ b) +{ + __ev64_opaque__ t; + + t = __ev_mwhsmi (a, b); + return __ev_mwsmian (t, ((__ev64_s32__){1, 1})); +} + +static inline __ev64_opaque__ +__internal_ev_mwhgumian (__ev64_opaque__ a, __ev64_opaque__ b) +{ + __ev64_opaque__ t; + + t = __ev_mwhumi (a, b); + return __ev_mwumian (t, ((__ev64_s32__){1, 1})); +} + +/* END OF NOT SUPPORTED */ + +/* __ev_create* functions. */ + +#define __ev_create_ufix32_u32 __ev_create_u32 +#define __ev_create_sfix32_s32 __ev_create_s32 + +static inline __ev64_opaque__ +__ev_create_s16 (int16_t a, int16_t b, int16_t c, int16_t d) +{ + union + { + __ev64_opaque__ v; + int16_t i[4]; + } u; + + u.i[0] = a; + u.i[1] = b; + u.i[2] = c; + u.i[3] = d; + + return u.v; +} + +static inline __ev64_opaque__ +__ev_create_u16 (uint16_t a, uint16_t b, uint16_t c, uint16_t d) + +{ + union + { + __ev64_opaque__ v; + uint16_t i[4]; + } u; + + u.i[0] = a; + u.i[1] = b; + u.i[2] = c; + u.i[3] = d; + + return u.v; +} + +static inline __ev64_opaque__ +__ev_create_s32 (int32_t a, int32_t b) +{ + union + { + __ev64_opaque__ v; + int32_t i[2]; + } u; + + u.i[0] = a; + u.i[1] = b; + + return u.v; +} + +static inline __ev64_opaque__ +__ev_create_u32 (uint32_t a, uint32_t b) +{ + union + { + __ev64_opaque__ v; + uint32_t i[2]; + } u; + + u.i[0] = a; + u.i[1] = b; + + return u.v; +} + +static inline __ev64_opaque__ +__ev_create_fs (float a, float b) +{ + union + { + __ev64_opaque__ v; + float f[2]; + } u; + + u.f[0] = a; + u.f[1] = b; + + return u.v; +} + +static inline __ev64_opaque__ +__ev_create_sfix32_fs (float a, float b) +{ + __ev64_opaque__ ev; + + ev = (__ev64_opaque__) __ev_create_fs (a, b); + return (__ev64_opaque__) __builtin_spe_evfsctsf ((__v2sf) ev); +} + +static inline __ev64_opaque__ +__ev_create_ufix32_fs (float a, float b) +{ + __ev64_opaque__ ev; + + ev = (__ev64_opaque__) __ev_create_fs (a, b); + return (__ev64_opaque__) __builtin_spe_evfsctuf ((__v2sf) ev); +} + +static inline __ev64_opaque__ +__ev_create_s64 (int64_t a) +{ + union + { + __ev64_opaque__ v; + int64_t i; + } u; + + u.i = a; + return u.v; +} + +static inline __ev64_opaque__ +__ev_create_u64 (uint64_t a) +{ + union + { + __ev64_opaque__ v; + uint64_t i; + } u; + + u.i = a; + return u.v; +} + +static inline uint64_t +__ev_convert_u64 (__ev64_opaque__ a) +{ + return (uint64_t) a; +} + +static inline int64_t +__ev_convert_s64 (__ev64_opaque__ a) +{ + return (int64_t) a; +} + +/* __ev_get_* functions. */ + +#define __ev_get_upper_u32(a) __ev_get_u32_internal ((__ev64_opaque__) (a), 0) +#define __ev_get_lower_u32(a) __ev_get_u32_internal ((__ev64_opaque__) (a), 1) +#define __ev_get_upper_s32(a) __ev_get_s32_internal ((__ev64_opaque__) (a), 0) +#define __ev_get_lower_s32(a) __ev_get_s32_internal ((__ev64_opaque__) (a), 1) +#define __ev_get_upper_fs(a) __ev_get_fs_internal ((__ev64_opaque__) (a), 0) +#define __ev_get_lower_fs(a) __ev_get_fs_internal ((__ev64_opaque__) (a), 1) +#define __ev_get_upper_ufix32_u32(a) __ev_get_upper_u32(a) +#define __ev_get_lower_ufix32_u32(a) __ev_get_lower_u32(a) +#define __ev_get_upper_sfix32_s32(a) __ev_get_upper_s32(a) +#define __ev_get_lower_sfix32_s32(a) __ev_get_lower_s32(a) +#define __ev_get_upper_sfix32_fs(a) __ev_get_sfix32_fs (a, 0) +#define __ev_get_lower_sfix32_fs(a) __ev_get_sfix32_fs (a, 1) +#define __ev_get_upper_ufix32_fs(a) __ev_get_ufix32_fs (a, 0) +#define __ev_get_lower_ufix32_fs(a) __ev_get_ufix32_fs (a, 1) + +#define __ev_get_u32(a, b) __ev_get_u32_internal ((__ev64_opaque__) (a), b) +#define __ev_get_s32(a, b) __ev_get_s32_internal ((__ev64_opaque__) (a), b) +#define __ev_get_fs(a, b) __ev_get_fs_internal ((__ev64_opaque__) (a), b) +#define __ev_get_u16(a, b) __ev_get_u16_internal ((__ev64_opaque__) (a), b) +#define __ev_get_s16(a, b) __ev_get_s16_internal ((__ev64_opaque__) (a), b) + +#define __ev_get_ufix32_u32(a, b) __ev_get_u32 (a, b) +#define __ev_get_sfix32_s32(a, b) __ev_get_s32 (a, b) +#define __ev_get_ufix32_fs(a, b) __ev_get_ufix32_fs_internal ((__ev64_opaque__)(a), b) +#define __ev_get_sfix32_fs(a, b) __ev_get_sfix32_fs_internal ((__ev64_opaque__)(a), b) + +static inline uint32_t +__ev_get_u32_internal (__ev64_opaque__ a, uint32_t pos) +{ + union + { + __ev64_opaque__ v; + uint32_t i[2]; + } u; + + u.v = a; + return u.i[pos]; +} + +static inline int32_t +__ev_get_s32_internal (__ev64_opaque__ a, uint32_t pos) +{ + union + { + __ev64_opaque__ v; + int32_t i[2]; + } u; + + u.v = a; + return u.i[pos]; +} + +static inline float +__ev_get_fs_internal (__ev64_opaque__ a, uint32_t pos) +{ + union + { + __ev64_opaque__ v; + float f[2]; + } u; + + u.v = a; + return u.f[pos]; +} + +static inline float +__ev_get_sfix32_fs_internal (__ev64_opaque__ a, uint32_t pos) +{ + __ev64_fs__ v; + + v = __builtin_spe_evfscfsf ((__v2sf) a); + return __ev_get_fs_internal ((__ev64_opaque__) v, pos); +} + +static inline float +__ev_get_ufix32_fs_internal (__ev64_opaque__ a, uint32_t pos) +{ + __ev64_fs__ v; + + v = __builtin_spe_evfscfuf ((__v2sf) a); + return __ev_get_fs_internal ((__ev64_opaque__) v, pos); +} + +static inline uint16_t +__ev_get_u16_internal (__ev64_opaque__ a, uint32_t pos) +{ + union + { + __ev64_opaque__ v; + uint16_t i[4]; + } u; + + u.v = a; + return u.i[pos]; +} + +static inline int16_t +__ev_get_s16_internal (__ev64_opaque__ a, uint32_t pos) +{ + union + { + __ev64_opaque__ v; + int16_t i[4]; + } u; + + u.v = a; + return u.i[pos]; +} + +/* __ev_set_* functions. */ + +#define __ev_set_u32(a, b, c) __ev_set_u32_internal ((__ev64_opaque__) a, b, c) +#define __ev_set_s32(a, b, c) __ev_set_s32_internal ((__ev64_opaque__) a, b, c) +#define __ev_set_fs(a, b, c) __ev_set_fs_internal ((__ev64_opaque__) a, b, c) +#define __ev_set_u16(a, b, c) __ev_set_u16_internal ((__ev64_opaque__) a, b, c) +#define __ev_set_s16(a, b, c) __ev_set_s16_internal ((__ev64_opaque__) a, b, c) + +#define __ev_set_ufix32_u32 __ev_set_u32 +#define __ev_set_sfix32_s32 __ev_set_s32 + +#define __ev_set_sfix32_fs(a, b, c) __ev_set_sfix32_fs_internal ((__ev64_opaque__) (a), b, c) +#define __ev_set_ufix32_fs(a, b, c) __ev_set_ufix32_fs_internal ((__ev64_opaque__) (a), b, c) + +#define __ev_set_upper_u32(a, b) __ev_set_u32 (a, b, 0) +#define __ev_set_lower_u32(a, b) __ev_set_u32 (a, b, 1) +#define __ev_set_upper_s32(a, b) __ev_set_s32 (a, b, 0) +#define __ev_set_lower_s32(a, b) __ev_set_s32 (a, b, 1) +#define __ev_set_upper_fs(a, b) __ev_set_fs (a, b, 0) +#define __ev_set_lower_fs(a, b) __ev_set_fs (a, b, 1) +#define __ev_set_upper_ufix32_u32 __ev_set_upper_u32 +#define __ev_set_lower_ufix32_u32 __ev_set_lower_u32 +#define __ev_set_upper_sfix32_s32 __ev_set_upper_s32 +#define __ev_set_lower_sfix32_s32 __ev_set_lower_s32 +#define __ev_set_upper_sfix32_fs(a, b) __ev_set_sfix32_fs (a, b, 0) +#define __ev_set_lower_sfix32_fs(a, b) __ev_set_sfix32_fs (a, b, 1) +#define __ev_set_upper_ufix32_fs(a, b) __ev_set_ufix32_fs (a, b, 0) +#define __ev_set_lower_ufix32_fs(a, b) __ev_set_ufix32_fs (a, b, 1) + +#define __ev_set_acc_vec64(a) __builtin_spe_evmra ((__ev64_opaque__)(a)) + +static inline __ev64_opaque__ +__ev_set_acc_u64 (uint64_t a) +{ + __ev64_opaque__ ev32; + ev32 = __ev_create_u64 (a); + __ev_mra (ev32); + return ev32; +} + +static inline __ev64_opaque__ +__ev_set_acc_s64 (int64_t a) +{ + __ev64_opaque__ ev32; + ev32 = __ev_create_s64 (a); + __ev_mra (ev32); + return ev32; +} + +static inline __ev64_opaque__ +__ev_set_u32_internal (__ev64_opaque__ a, uint32_t b, uint32_t pos) +{ + union + { + __ev64_opaque__ v; + uint32_t i[2]; + } u; + + u.v = a; + u.i[pos] = b; + return u.v; +} + +static inline __ev64_opaque__ +__ev_set_s32_internal (__ev64_opaque__ a, int32_t b, uint32_t pos) +{ + union + { + __ev64_opaque__ v; + int32_t i[2]; + } u; + + u.v = a; + u.i[pos] = b; + return u.v; +} + +static inline __ev64_opaque__ +__ev_set_fs_internal (__ev64_opaque__ a, float b, uint32_t pos) +{ + union + { + __ev64_opaque__ v; + float f[2]; + } u; + + u.v = a; + u.f[pos] = b; + return u.v; +} + +static inline __ev64_opaque__ +__ev_set_sfix32_fs_internal (__ev64_opaque__ a, float b, uint32_t pos) +{ + __ev64_opaque__ v; + float other; + + /* Get other half. */ + other = __ev_get_fs_internal (a, pos ^ 1); + + /* Make an sfix32 with 'b'. */ + v = __ev_create_sfix32_fs (b, b); + + /* Set other half to what it used to be. */ + return __ev_set_fs_internal (v, other, pos ^ 1); +} + +static inline __ev64_opaque__ +__ev_set_ufix32_fs_internal (__ev64_opaque__ a, float b, uint32_t pos) +{ + __ev64_opaque__ v; + float other; + + /* Get other half. */ + other = __ev_get_fs_internal (a, pos ^ 1); + + /* Make an ufix32 with 'b'. */ + v = __ev_create_ufix32_fs (b, b); + + /* Set other half to what it used to be. */ + return __ev_set_fs_internal (v, other, pos ^ 1); +} + +static inline __ev64_opaque__ +__ev_set_u16_internal (__ev64_opaque__ a, uint16_t b, uint32_t pos) +{ + union + { + __ev64_opaque__ v; + uint16_t i[4]; + } u; + + u.v = a; + u.i[pos] = b; + return u.v; +} + +static inline __ev64_opaque__ +__ev_set_s16_internal (__ev64_opaque__ a, int16_t b, uint32_t pos) +{ + union + { + __ev64_opaque__ v; + int16_t i[4]; + } u; + + u.v = a; + u.i[pos] = b; + return u.v; +} + +/* Predicates. */ + +#define __pred_all 0 +#define __pred_any 1 +#define __pred_upper 2 +#define __pred_lower 3 + +#define __ev_any_gts(a, b) __builtin_spe_evcmpgts (__pred_any, (__v2si) (a), (__v2si) (b)) +#define __ev_all_gts(a, b) __builtin_spe_evcmpgts (__pred_all, (__v2si) (a), (__v2si) (b)) +#define __ev_upper_gts(a, b) __builtin_spe_evcmpgts (__pred_upper, (__v2si) (a), (__v2si) (b)) +#define __ev_lower_gts(a, b) __builtin_spe_evcmpgts (__pred_lower, (__v2si) (a), (__v2si) (b)) +#define __ev_select_gts(a, b, c, d) ((__v2si) __builtin_spe_evsel_gts ((__v2si) (a), (__v2si) (b), (__v2si) (c), (__v2si) (d))) + +#define __ev_any_gtu(a, b) __builtin_spe_evcmpgtu (__pred_any, (__v2si) (a), (__v2si) (b)) +#define __ev_all_gtu(a, b) __builtin_spe_evcmpgtu (__pred_all, (__v2si) (a), (__v2si) (b)) +#define __ev_upper_gtu(a, b) __builtin_spe_evcmpgtu (__pred_upper, (__v2si) (a), (__v2si) (b)) +#define __ev_lower_gtu(a, b) __builtin_spe_evcmpgtu (__pred_lower, (__v2si) (a), (__v2si) (b)) +#define __ev_select_gtu(a, b, c, d) ((__v2si) __builtin_spe_evsel_gtu ((__v2si) (a), (__v2si) (b), (__v2si) (c), (__v2si) (d))) + +#define __ev_any_lts(a, b) __builtin_spe_evcmplts (__pred_any, (__v2si) (a), (__v2si) (b)) +#define __ev_all_lts(a, b) __builtin_spe_evcmplts (__pred_all, (__v2si) (a), (__v2si) (b)) +#define __ev_upper_lts(a, b) __builtin_spe_evcmplts (__pred_upper, (__v2si) (a), (__v2si) (b)) +#define __ev_lower_lts(a, b) __builtin_spe_evcmplts (__pred_lower, (__v2si) (a), (__v2si) (b)) +#define __ev_select_lts(a, b, c, d) ((__v2si) __builtin_spe_evsel_lts ((__v2si) (a), (__v2si) (b), (__v2si) (c), (__v2si) (d))) + +#define __ev_any_ltu(a, b) __builtin_spe_evcmpltu (__pred_any, (__v2si) (a), (__v2si) (b)) +#define __ev_all_ltu(a, b) __builtin_spe_evcmpltu (__pred_all, (__v2si) (a), (__v2si) (b)) +#define __ev_upper_ltu(a, b) __builtin_spe_evcmpltu (__pred_upper, (__v2si) (a), (__v2si) (b)) +#define __ev_lower_ltu(a, b) __builtin_spe_evcmpltu (__pred_lower, (__v2si) (a), (__v2si) (b)) +#define __ev_select_ltu(a, b, c, d) ((__v2si) __builtin_spe_evsel_ltu ((__v2si) (a), (__v2si) (b), (__v2si) (c), (__v2si) (d))) +#define __ev_any_eq(a, b) __builtin_spe_evcmpeq (__pred_any, (__v2si) (a), (__v2si) (b)) +#define __ev_all_eq(a, b) __builtin_spe_evcmpeq (__pred_all, (__v2si) (a), (__v2si) (b)) +#define __ev_upper_eq(a, b) __builtin_spe_evcmpeq (__pred_upper, (__v2si) (a), (__v2si) (b)) +#define __ev_lower_eq(a, b) __builtin_spe_evcmpeq (__pred_lower, (__v2si) (a), (__v2si) (b)) +#define __ev_select_eq(a, b, c, d) ((__v2si) __builtin_spe_evsel_eq ((__v2si) (a), (__v2si) (b), (__v2si) (c), (__v2si) (d))) + +#define __ev_any_fs_gt(a, b) __builtin_spe_evfscmpgt (__pred_any, (__v2sf) (a), (__v2sf) (b)) +#define __ev_all_fs_gt(a, b) __builtin_spe_evfscmpgt (__pred_all, (__v2sf) (a), (__v2sf) (b)) +#define __ev_upper_fs_gt(a, b) __builtin_spe_evfscmpgt (__pred_upper, (__v2sf) (a), (__v2sf) (b)) +#define __ev_lower_fs_gt(a, b) __builtin_spe_evfscmpgt (__pred_lower, (__v2sf) (a), (__v2sf) (b)) +#define __ev_select_fs_gt(a, b, c, d) ((__v2si) __builtin_spe_evsel_fsgt ((__v2sf) (a), (__v2sf) (b), (__v2sf) (c), (__v2sf) (d))) + +#define __ev_any_fs_lt(a, b) __builtin_spe_evfscmplt (__pred_any, (__v2sf) (a), (__v2sf) (b)) +#define __ev_all_fs_lt(a, b) __builtin_spe_evfscmplt (__pred_all, (__v2sf) (a), (__v2sf) (b)) +#define __ev_upper_fs_lt(a, b) __builtin_spe_evfscmplt (__pred_upper, (__v2sf) (a), (__v2sf) (b)) +#define __ev_lower_fs_lt(a, b) __builtin_spe_evfscmplt (__pred_lower, (__v2sf) (a), (__v2sf) (b)) +#define __ev_select_fs_lt(a, b, c, d) ((__v2si) __builtin_spe_evsel_fslt ((__v2sf) (a), (__v2sf) (b), (__v2sf) (c), (__v2sf) (d))) + +#define __ev_any_fs_eq(a, b) __builtin_spe_evfscmpeq (__pred_any, (__v2sf) (a), (__v2sf) (b)) +#define __ev_all_fs_eq(a, b) __builtin_spe_evfscmpeq (__pred_all, (__v2sf) (a), (__v2sf) (b)) +#define __ev_upper_fs_eq(a, b) __builtin_spe_evfscmpeq (__pred_upper, (__v2sf) (a), (__v2sf) (b)) +#define __ev_lower_fs_eq(a, b) __builtin_spe_evfscmpeq (__pred_lower, (__v2sf) (a), (__v2sf) (b)) +#define __ev_select_fs_eq(a, b, c, d) ((__v2si) __builtin_spe_evsel_fseq ((__v2sf) (a), (__v2sf) (b), (__v2sf) (c), (__v2sf) (d))) + +#define __ev_any_fs_tst_gt(a, b) __builtin_spe_evfststgt (__pred_any, (__v2sf) (a), (__v2sf) (b)) +#define __ev_all_fs_tst_gt(a, b) __builtin_spe_evfststgt (__pred_all, (__v2sf) (a), (__v2sf) (b)) +#define __ev_upper_fs_tst_gt(a, b) __builtin_spe_evfststgt (__pred_upper, (__v2sf) (a), (__v2sf) (b)) +#define __ev_lower_fs_tst_gt(a, b) __builtin_spe_evfststgt (__pred_lower, (__v2sf) (a), (__v2sf) (b)) +#define __ev_select_fs_tst_gt(a, b, c, d) ((__v2si) __builtin_spe_evsel_fststgt ((__v2sf) (a), (__v2sf) (b), (__v2sf) (c), (__v2sf) (d))) + +#define __ev_any_fs_tst_lt(a, b) __builtin_spe_evfststlt (__pred_any, (__v2sf) (a), (__v2sf) (b)) +#define __ev_all_fs_tst_lt(a, b) __builtin_spe_evfststlt (__pred_all, (__v2sf) (a), (__v2sf) (b)) +#define __ev_upper_fs_tst_lt(a, b) __builtin_spe_evfststlt (__pred_upper, (__v2sf) (a), (__v2sf) (b)) +#define __ev_lower_fs_tst_lt(a, b) __builtin_spe_evfststlt (__pred_lower, (__v2sf) (a), (__v2sf) (b)) +#define __ev_select_fs_tst_lt(a, b, c, d) ((__v2si) __builtin_spe_evsel_fststlt ((__v2sf) (a), (__v2sf) (b), (__v2sf) (c), (__v2sf) (d))) + +#define __ev_any_fs_tst_eq(a, b) __builtin_spe_evfststeq (__pred_any, (__v2sf) (a), (__v2sf) (b)) +#define __ev_all_fs_tst_eq(a, b) __builtin_spe_evfststeq (__pred_all, (__v2sf) (a), (__v2sf) (b)) +#define __ev_upper_fs_tst_eq(a, b) __builtin_spe_evfststeq (__pred_upper, (__v2sf) (a), (__v2sf) (b)) +#define __ev_lower_fs_tst_eq(a, b) __builtin_spe_evfststeq (__pred_lower, (__v2sf) (a), (__v2sf) (b)) +#define __ev_select_fs_tst_eq(a, b, c, d) ((__v2si) __builtin_spe_evsel_fststeq ((__v2sf) (a), (__v2sf) (b), (__v2sf) (c), (__v2sf) (d))) + +/* SPEFSCR accesor functions. */ + +#define __SPEFSCR_SOVH 0x80000000 +#define __SPEFSCR_OVH 0x40000000 +#define __SPEFSCR_FGH 0x20000000 +#define __SPEFSCR_FXH 0x10000000 +#define __SPEFSCR_FINVH 0x08000000 +#define __SPEFSCR_FDBZH 0x04000000 +#define __SPEFSCR_FUNFH 0x02000000 +#define __SPEFSCR_FOVFH 0x01000000 +/* 2 unused bits. */ +#define __SPEFSCR_FINXS 0x00200000 +#define __SPEFSCR_FINVS 0x00100000 +#define __SPEFSCR_FDBZS 0x00080000 +#define __SPEFSCR_FUNFS 0x00040000 +#define __SPEFSCR_FOVFS 0x00020000 +#define __SPEFSCR_MODE 0x00010000 +#define __SPEFSCR_SOV 0x00008000 +#define __SPEFSCR_OV 0x00004000 +#define __SPEFSCR_FG 0x00002000 +#define __SPEFSCR_FX 0x00001000 +#define __SPEFSCR_FINV 0x00000800 +#define __SPEFSCR_FDBZ 0x00000400 +#define __SPEFSCR_FUNF 0x00000200 +#define __SPEFSCR_FOVF 0x00000100 +/* 1 unused bit. */ +#define __SPEFSCR_FINXE 0x00000040 +#define __SPEFSCR_FINVE 0x00000020 +#define __SPEFSCR_FDBZE 0x00000010 +#define __SPEFSCR_FUNFE 0x00000008 +#define __SPEFSCR_FOVFE 0x00000004 +#define __SPEFSCR_FRMC 0x00000003 + +#define __ev_get_spefscr_sovh() (__builtin_spe_mfspefscr () & __SPEFSCR_SOVH) +#define __ev_get_spefscr_ovh() (__builtin_spe_mfspefscr () & __SPEFSCR_OVH) +#define __ev_get_spefscr_fgh() (__builtin_spe_mfspefscr () & __SPEFSCR_FGH) +#define __ev_get_spefscr_fxh() (__builtin_spe_mfspefscr () & __SPEFSCR_FXH) +#define __ev_get_spefscr_finvh() (__builtin_spe_mfspefscr () & __SPEFSCR_FINVH) +#define __ev_get_spefscr_fdbzh() (__builtin_spe_mfspefscr () & __SPEFSCR_FDBZH) +#define __ev_get_spefscr_funfh() (__builtin_spe_mfspefscr () & __SPEFSCR_FUNFH) +#define __ev_get_spefscr_fovfh() (__builtin_spe_mfspefscr () & __SPEFSCR_FOVFH) +#define __ev_get_spefscr_finxs() (__builtin_spe_mfspefscr () & __SPEFSCR_FINXS) +#define __ev_get_spefscr_finvs() (__builtin_spe_mfspefscr () & __SPEFSCR_FINVS) +#define __ev_get_spefscr_fdbzs() (__builtin_spe_mfspefscr () & __SPEFSCR_FDBZS) +#define __ev_get_spefscr_funfs() (__builtin_spe_mfspefscr () & __SPEFSCR_FUNFS) +#define __ev_get_spefscr_fovfs() (__builtin_spe_mfspefscr () & __SPEFSCR_FOVFS) +#define __ev_get_spefscr_mode() (__builtin_spe_mfspefscr () & __SPEFSCR_MODE) +#define __ev_get_spefscr_sov() (__builtin_spe_mfspefscr () & __SPEFSCR_SOV) +#define __ev_get_spefscr_ov() (__builtin_spe_mfspefscr () & __SPEFSCR_OV) +#define __ev_get_spefscr_fg() (__builtin_spe_mfspefscr () & __SPEFSCR_FG) +#define __ev_get_spefscr_fx() (__builtin_spe_mfspefscr () & __SPEFSCR_FX) +#define __ev_get_spefscr_finv() (__builtin_spe_mfspefscr () & __SPEFSCR_FINV) +#define __ev_get_spefscr_fdbz() (__builtin_spe_mfspefscr () & __SPEFSCR_FDBZ) +#define __ev_get_spefscr_funf() (__builtin_spe_mfspefscr () & __SPEFSCR_FUNF) +#define __ev_get_spefscr_fovf() (__builtin_spe_mfspefscr () & __SPEFSCR_FOVF) +#define __ev_get_spefscr_finxe() (__builtin_spe_mfspefscr () & __SPEFSCR_FINXE) +#define __ev_get_spefscr_finve() (__builtin_spe_mfspefscr () & __SPEFSCR_FINVE) +#define __ev_get_spefscr_fdbze() (__builtin_spe_mfspefscr () & __SPEFSCR_FDBZE) +#define __ev_get_spefscr_funfe() (__builtin_spe_mfspefscr () & __SPEFSCR_FUNFE) +#define __ev_get_spefscr_fovfe() (__builtin_spe_mfspefscr () & __SPEFSCR_FOVFE) +#define __ev_get_spefscr_frmc() (__builtin_spe_mfspefscr () & __SPEFSCR_FRMC) + +static inline void +__ev_clr_spefscr_field (int mask) +{ + int i; + + i = __builtin_spe_mfspefscr (); + i &= ~mask; + __builtin_spe_mtspefscr (i); +} + +#define __ev_clr_spefscr_sovh() __ev_clr_spefscr_field (__SPEFSCR_SOVH) +#define __ev_clr_spefscr_sov() __ev_clr_spefscr_field (__SPEFSCR_SOV) +#define __ev_clr_spefscr_finxs() __ev_clr_spefscr_field (__SPEFSCR_FINXS) +#define __ev_clr_spefscr_finvs() __ev_clr_spefscr_field (__SPEFSCR_FINVS) +#define __ev_clr_spefscr_fdbzs() __ev_clr_spefscr_field (__SPEFSCR_FDBZS) +#define __ev_clr_spefscr_funfs() __ev_clr_spefscr_field (__SPEFSCR_FUNFS) +#define __ev_clr_spefscr_fovfs() __ev_clr_spefscr_field (__SPEFSCR_FOVFS) + +/* Set rounding mode: + rnd = 0 (nearest) + rnd = 1 (zero) + rnd = 2 (+inf) + rnd = 3 (-inf). */ + +static inline void +__ev_set_spefscr_frmc (int rnd) +{ + int i; + + i = __builtin_spe_mfspefscr (); + i &= ~__SPEFSCR_FRMC; + i |= rnd; +} + +#endif /* _SPE_H */ diff --git a/contrib/gcc/config/rs6000/spe.md b/contrib/gcc/config/rs6000/spe.md new file mode 100644 index 0000000..3413858 --- /dev/null +++ b/contrib/gcc/config/rs6000/spe.md @@ -0,0 +1,2488 @@ +;; e500 SPE description +;; Copyright (C) 2002 Free Software Foundation, Inc. +;; Contributed by Aldy Hernandez (aldy@quesejoda.com) + +;; This file is part of GNU CC. + +;; GNU CC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. + +;; GNU CC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GNU CC; see the file COPYING. If not, write to +;; the Free Software Foundation, 59 Temple Place - Suite 330, +;; Boston, MA 02111-1307, USA. + +(define_constants + [(SPE_ACC_REGNO 111) + (SPEFSCR_REGNO 112)]) + +(define_insn "*negsf2_gpr" + [(set (match_operand:SF 0 "gpc_reg_operand" "=r") + (neg:SF (match_operand:SF 1 "gpc_reg_operand" "r")))] + "TARGET_HARD_FLOAT && !TARGET_FPRS" + "efsneg %0,%1" + [(set_attr "type" "fp")]) + +(define_insn "*abssf2_gpr" + [(set (match_operand:SF 0 "gpc_reg_operand" "=r") + (abs:SF (match_operand:SF 1 "gpc_reg_operand" "r")))] + "TARGET_HARD_FLOAT && !TARGET_FPRS" + "efsabs %0,%1" + [(set_attr "type" "fp")]) + +(define_insn "*addsf3_gpr" + [(set (match_operand:SF 0 "gpc_reg_operand" "=r") + (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%r") + (match_operand:SF 2 "gpc_reg_operand" "r")))] + "TARGET_HARD_FLOAT && !TARGET_FPRS" + "efsadd %0,%1,%2" + [(set_attr "type" "fp")]) + +(define_insn "*subsf3_gpr" + [(set (match_operand:SF 0 "gpc_reg_operand" "=r") + (minus:SF (match_operand:SF 1 "gpc_reg_operand" "r") + (match_operand:SF 2 "gpc_reg_operand" "r")))] + "TARGET_HARD_FLOAT && !TARGET_FPRS" + "efssub %0,%1,%2" + [(set_attr "type" "fp")]) + +(define_insn "*mulsf3_gpr" + [(set (match_operand:SF 0 "gpc_reg_operand" "=r") + (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%r") + (match_operand:SF 2 "gpc_reg_operand" "r")))] + "TARGET_HARD_FLOAT && !TARGET_FPRS" + "efsmul %0,%1,%2" + [(set_attr "type" "fp")]) + +(define_insn "*divsf3_gpr" + [(set (match_operand:SF 0 "gpc_reg_operand" "=r") + (div:SF (match_operand:SF 1 "gpc_reg_operand" "r") + (match_operand:SF 2 "gpc_reg_operand" "r")))] + "TARGET_HARD_FLOAT && !TARGET_FPRS" + "efsdiv %0,%1,%2" + [(set_attr "type" "fp")]) + +(define_insn "spe_efsctuiz" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (unspec:SI [(match_operand:SF 1 "gpc_reg_operand" "r")] 700))] + "TARGET_HARD_FLOAT && !TARGET_FPRS" + "efsctuiz %0,%1" + [(set_attr "type" "fp")]) + +(define_insn "spe_fixunssfsi2" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (unsigned_fix:SI (fix:SF (match_operand:SF 1 "gpc_reg_operand" "r"))))] + "TARGET_HARD_FLOAT && !TARGET_FPRS" + "efsctui %0,%1" + [(set_attr "type" "fp")]) + +(define_insn "spe_fix_truncsfsi2" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))] + "TARGET_HARD_FLOAT && !TARGET_FPRS" + "efsctsi %0,%1" + [(set_attr "type" "fp")]) + +(define_insn "spe_floatunssisf2" + [(set (match_operand:SF 0 "gpc_reg_operand" "=r") + (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))] + "TARGET_HARD_FLOAT && !TARGET_FPRS" + "efscfui %0,%1" + [(set_attr "type" "fp")]) + +(define_insn "spe_floatsisf2" + [(set (match_operand:SF 0 "gpc_reg_operand" "=r") + (float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))] + "TARGET_HARD_FLOAT && !TARGET_FPRS" + "efscfsi %0,%1" + [(set_attr "type" "fp")]) + + +;; SPE SIMD instructions + +(define_insn "spe_evabs" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (abs:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))] + "TARGET_SPE" + "evabs %0,%1" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evandc" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") + (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] + "TARGET_SPE" + "evandc %0,%1,%2" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evand" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")))] + "TARGET_SPE" + "evand %0,%1,%2" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +;; Vector compare instructions + +(define_insn "spe_evcmpeq" + [(set (match_operand:CC 0 "cc_reg_operand" "=y") + (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 500))] + "TARGET_SPE" + "evcmpeq %0,%1,%2" + [(set_attr "type" "veccmp") + (set_attr "length" "4")]) + +(define_insn "spe_evcmpgts" + [(set (match_operand:CC 0 "cc_reg_operand" "=y") + (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 501))] + "TARGET_SPE" + "evcmpgts %0,%1,%2" + [(set_attr "type" "veccmp") + (set_attr "length" "4")]) + +(define_insn "spe_evcmpgtu" + [(set (match_operand:CC 0 "cc_reg_operand" "=y") + (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 502))] + "TARGET_SPE" + "evcmpgtu %0,%1,%2" + [(set_attr "type" "veccmp") + (set_attr "length" "4")]) + +(define_insn "spe_evcmplts" + [(set (match_operand:CC 0 "cc_reg_operand" "=y") + (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 503))] + "TARGET_SPE" + "evcmplts %0,%1,%2" + [(set_attr "type" "veccmp") + (set_attr "length" "4")]) + +(define_insn "spe_evcmpltu" + [(set (match_operand:CC 0 "cc_reg_operand" "=y") + (unspec:CC [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 504))] + "TARGET_SPE" + "evcmpltu %0,%1,%2" + [(set_attr "type" "veccmp") + (set_attr "length" "4")]) + +;; Floating point vector compare instructions + +(define_insn "spe_evfscmpeq" + [(set (match_operand:CC 0 "cc_reg_operand" "=y") + (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") + (match_operand:V2SF 2 "gpc_reg_operand" "r")] 538)) + (clobber (reg:SI SPEFSCR_REGNO))] + "TARGET_SPE" + "evfscmpeq %0,%1,%2" + [(set_attr "type" "veccmp") + (set_attr "length" "4")]) + +(define_insn "spe_evfscmpgt" + [(set (match_operand:CC 0 "cc_reg_operand" "=y") + (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") + (match_operand:V2SF 2 "gpc_reg_operand" "r")] 539)) + (clobber (reg:SI SPEFSCR_REGNO))] + "TARGET_SPE" + "evfscmpgt %0,%1,%2" + [(set_attr "type" "veccmp") + (set_attr "length" "4")]) + +(define_insn "spe_evfscmplt" + [(set (match_operand:CC 0 "cc_reg_operand" "=y") + (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") + (match_operand:V2SF 2 "gpc_reg_operand" "r")] 540)) + (clobber (reg:SI SPEFSCR_REGNO))] + "TARGET_SPE" + "evfscmplt %0,%1,%2" + [(set_attr "type" "veccmp") + (set_attr "length" "4")]) + +(define_insn "spe_evfststeq" + [(set (match_operand:CC 0 "cc_reg_operand" "=y") + (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") + (match_operand:V2SF 2 "gpc_reg_operand" "r")] 541))] + "TARGET_SPE" + "evfststeq %0,%1,%2" + [(set_attr "type" "veccmp") + (set_attr "length" "4")]) + +(define_insn "spe_evfststgt" + [(set (match_operand:CC 0 "cc_reg_operand" "=y") + (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") + (match_operand:V2SF 2 "gpc_reg_operand" "r")] 542))] + "TARGET_SPE" + "evfststgt %0,%1,%2" + [(set_attr "type" "veccmp") + (set_attr "length" "4")]) + +(define_insn "spe_evfststlt" + [(set (match_operand:CC 0 "cc_reg_operand" "=y") + (unspec:CC [(match_operand:V2SF 1 "gpc_reg_operand" "r") + (match_operand:V2SF 2 "gpc_reg_operand" "r")] 543))] + "TARGET_SPE" + "evfststlt %0,%1,%2" + [(set_attr "type" "veccmp") + (set_attr "length" "4")]) + +;; End of vector compare instructions + +(define_insn "spe_evcntlsw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 505))] + "TARGET_SPE" + "evcntlsw %0,%1" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evcntlzw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 506))] + "TARGET_SPE" + "evcntlzw %0,%1" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_eveqv" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (not:V2SI (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] + "TARGET_SPE" + "eveqv %0,%1,%2" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evextsb" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 507))] + "TARGET_SPE" + "evextsb %0,%1" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evextsh" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 508))] + "TARGET_SPE" + "evextsh %0,%1" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evlhhesplat" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand:QI 2 "immediate_operand" "i")))) + (unspec [(const_int 0)] 509)] + "TARGET_SPE" + "evlhhesplat %0,%1,%2" + [(set_attr "type" "vecload") + (set_attr "length" "4")]) + +(define_insn "spe_evlhhesplatx" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand:SI 2 "gpc_reg_operand" "r")))) + (unspec [(const_int 0)] 510)] + "TARGET_SPE" + "evlhhesplatx %0,%1,%2" + [(set_attr "type" "vecload") + (set_attr "length" "4")]) + +(define_insn "spe_evlhhossplat" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand:QI 2 "immediate_operand" "i")))) + (unspec [(const_int 0)] 511)] + "TARGET_SPE" + "evlhhossplat %0,%1,%2" + [(set_attr "type" "vecload") + (set_attr "length" "4")]) + +(define_insn "spe_evlhhossplatx" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand:SI 2 "gpc_reg_operand" "r")))) + (unspec [(const_int 0)] 512)] + "TARGET_SPE" + "evlhhossplatx %0,%1,%2" + [(set_attr "type" "vecload") + (set_attr "length" "4")]) + +(define_insn "spe_evlhhousplat" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand:QI 2 "immediate_operand" "i")))) + (unspec [(const_int 0)] 513)] + "TARGET_SPE" + "evlhhousplat %0,%1,%2" + [(set_attr "type" "vecload") + (set_attr "length" "4")]) + +(define_insn "spe_evlhhousplatx" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand:SI 2 "gpc_reg_operand" "r")))) + (unspec [(const_int 0)] 514)] + "TARGET_SPE" + "evlhhousplatx %0,%1,%2" + [(set_attr "type" "vecload") + (set_attr "length" "4")]) + +(define_insn "spe_evlwhsplat" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand:QI 2 "immediate_operand" "i")))) + (unspec [(const_int 0)] 515)] + "TARGET_SPE" + "evlwhsplat %0,%1,%2" + [(set_attr "type" "vecload") + (set_attr "length" "4")]) + +(define_insn "spe_evlwhsplatx" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand:SI 2 "gpc_reg_operand" "r")))) + (unspec [(const_int 0)] 516)] + "TARGET_SPE" + "evlwhsplatx %0,%1,%2" + [(set_attr "type" "vecload") + (set_attr "length" "4")]) + +(define_insn "spe_evlwwsplat" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand:QI 2 "immediate_operand" "i")))) + (unspec [(const_int 0)] 517)] + "TARGET_SPE" + "evlwwsplat %0,%1,%2" + [(set_attr "type" "vecload") + (set_attr "length" "4")]) + +(define_insn "spe_evlwwsplatx" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand:SI 2 "gpc_reg_operand" "r")))) + (unspec [(const_int 0)] 518)] + "TARGET_SPE" + "evlwwsplatx %0,%1,%2" + [(set_attr "type" "vecload") + (set_attr "length" "4")]) + +(define_insn "spe_evmergehi" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (vec_merge:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") + (vec_select:V2SI + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (parallel [(const_int 1) + (const_int 0)])) + (const_int 2)))] + "TARGET_SPE" + "evmergehi %0,%1,%2" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evmergehilo" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (vec_merge:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (const_int 2)))] + "TARGET_SPE" + "evmergehilo %0,%1,%2" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evmergelo" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (vec_merge:V2SI (vec_select:V2SI + (match_operand:V2SI 1 "gpc_reg_operand" "r") + (parallel [(const_int 1) + (const_int 0)])) + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (const_int 2)))] + "TARGET_SPE" + "evmergelo %0,%1,%2" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evmergelohi" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (vec_merge:V2SI (vec_select:V2SI + (match_operand:V2SI 1 "gpc_reg_operand" "r") + (parallel [(const_int 1) + (const_int 0)])) + (vec_select:V2SI + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (parallel [(const_int 1) + (const_int 0)])) + (const_int 2)))] + "TARGET_SPE" + "evmergelohi %0,%1,%2" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evnand" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (not:V2SI (and:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] + "TARGET_SPE" + "evnand %0,%1,%2" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evneg" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (neg:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r")))] + "TARGET_SPE" + "evneg %0,%1" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evnor" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (not:V2SI (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] + "TARGET_SPE" + "evnor %0,%1,%2" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evorc" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") + (not:V2SI (match_operand:V2SI 2 "gpc_reg_operand" "r"))))] + "TARGET_SPE" + "evorc %0,%1,%2" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evor" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (ior:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")))] + "TARGET_SPE" + "evor %0,%1,%2" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evrlwi" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:QI 2 "immediate_operand" "i")] 519))] + "TARGET_SPE" + "evrlwi %0,%1,%2" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evrlw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 520))] + "TARGET_SPE" + "evrlw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evrndw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 521))] + "TARGET_SPE" + "evrndw %0,%1" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evsel" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (match_operand:CC 3 "cc_reg_operand" "y")] 522))] + "TARGET_SPE" + "evsel %0,%1,%2,%3" + [(set_attr "type" "veccmp") + (set_attr "length" "4")]) + +(define_insn "spe_evsel_fs" + [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") + (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r") + (match_operand:V2SF 2 "gpc_reg_operand" "r") + (match_operand:CC 3 "cc_reg_operand" "y")] 725))] + "TARGET_SPE" + "evsel %0,%1,%2,%3" + [(set_attr "type" "veccmp") + (set_attr "length" "4")]) + +(define_insn "spe_evslwi" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:QI 2 "immediate_operand" "i")] + 523))] + "TARGET_SPE" + "evslwi %0,%1,%2" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evslw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 524))] + "TARGET_SPE" + "evslw %0,%1,%2" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evsrwis" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:QI 2 "immediate_operand" "i")] + 525))] + "TARGET_SPE" + "evsrwis %0,%1,%2" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evsrwiu" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:QI 2 "immediate_operand" "i")] + 526))] + "TARGET_SPE" + "evsrwiu %0,%1,%2" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evsrws" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 527))] + "TARGET_SPE" + "evsrws %0,%1,%2" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evsrwu" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 528))] + "TARGET_SPE" + "evsrwu %0,%1,%2" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evxor" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (xor:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")))] + "TARGET_SPE" + "evxor %0,%1,%2" + [(set_attr "type" "vecsimple") + (set_attr "length" "4")]) + +(define_insn "spe_evfsabs" + [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") + (abs:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))] + "TARGET_SPE" + "evfsabs %0,%1" + [(set_attr "type" "vecfloat") + (set_attr "length" "4")]) + +(define_insn "spe_evfsadd" + [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") + (plus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") + (match_operand:V2SF 2 "gpc_reg_operand" "r"))) + (clobber (reg:SI SPEFSCR_REGNO))] + "TARGET_SPE" + "evfsadd %0,%1,%2" + [(set_attr "type" "vecfloat") + (set_attr "length" "4")]) + +(define_insn "spe_evfscfsf" + [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") + (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 529))] + "TARGET_SPE" + "evfscfsf %0,%1" + [(set_attr "type" "vecfloat") + (set_attr "length" "4")]) + +(define_insn "spe_evfscfsi" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (fix:V2SI (match_operand:V2SF 1 "gpc_reg_operand" "r")))] + "TARGET_SPE" + "evfscfsi %0,%1" + [(set_attr "type" "vecfloat") + (set_attr "length" "4")]) + +(define_insn "spe_evfscfuf" + [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") + (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 530))] + "TARGET_SPE" + "evfscfuf %0,%1" + [(set_attr "type" "vecfloat") + (set_attr "length" "4")]) + +(define_insn "spe_evfscfui" + [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") + (unspec:V2SF [(match_operand:V2SI 1 "gpc_reg_operand" "r")] 701))] + "TARGET_SPE" + "evfscfui %0,%1" + [(set_attr "type" "vecfloat") + (set_attr "length" "4")]) + +(define_insn "spe_evfsctsf" + [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") + (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 531))] + "TARGET_SPE" + "evfsctsf %0,%1" + [(set_attr "type" "vecfloat") + (set_attr "length" "4")]) + +(define_insn "spe_evfsctsi" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 532))] + "TARGET_SPE" + "evfsctsi %0,%1" + [(set_attr "type" "vecfloat") + (set_attr "length" "4")]) + +(define_insn "spe_evfsctsiz" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 533))] + "TARGET_SPE" + "evfsctsiz %0,%1" + [(set_attr "type" "vecfloat") + (set_attr "length" "4")]) + +(define_insn "spe_evfsctuf" + [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") + (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 534))] + "TARGET_SPE" + "evfsctuf %0,%1" + [(set_attr "type" "vecfloat") + (set_attr "length" "4")]) + +(define_insn "spe_evfsctui" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 535))] + "TARGET_SPE" + "evfsctui %0,%1" + [(set_attr "type" "vecfloat") + (set_attr "length" "4")]) + +(define_insn "spe_evfsctuiz" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 536))] + "TARGET_SPE" + "evfsctuiz %0,%1" + [(set_attr "type" "vecfloat") + (set_attr "length" "4")]) + +(define_insn "spe_evfsdiv" + [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") + (div:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") + (match_operand:V2SF 2 "gpc_reg_operand" "r"))) + (clobber (reg:SI SPEFSCR_REGNO))] + "TARGET_SPE" + "evfsdiv %0,%1,%2" + [(set_attr "type" "vecfloat") + (set_attr "length" "4")]) + +(define_insn "spe_evfsmul" + [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") + (mult:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") + (match_operand:V2SF 2 "gpc_reg_operand" "r"))) + (clobber (reg:SI SPEFSCR_REGNO))] + "TARGET_SPE" + "evfsmul %0,%1,%2" + [(set_attr "type" "vecfloat") + (set_attr "length" "4")]) + +(define_insn "spe_evfsnabs" + [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") + (unspec:V2SF [(match_operand:V2SF 1 "gpc_reg_operand" "r")] 537))] + "TARGET_SPE" + "evfsnabs %0,%1" + [(set_attr "type" "vecfloat") + (set_attr "length" "4")]) + +(define_insn "spe_evfsneg" + [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") + (neg:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r")))] + "TARGET_SPE" + "evfsneg %0,%1" + [(set_attr "type" "vecfloat") + (set_attr "length" "4")]) + +(define_insn "spe_evfssub" + [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") + (minus:V2SF (match_operand:V2SF 1 "gpc_reg_operand" "r") + (match_operand:V2SF 2 "gpc_reg_operand" "r"))) + (clobber (reg:SI SPEFSCR_REGNO))] + "TARGET_SPE" + "evfssub %0,%1,%2" + [(set_attr "type" "vecfloat") + (set_attr "length" "4")]) + +;; SPE SIMD load instructions. + +;; Only the hardware engineer who designed the SPE inderstands the +;; plethora of load and store instructions ;-). We have no way of +;; differentiating between them with RTL so use an unspec of const_int 0 +;; to avoid identical RTL. + +(define_insn "spe_evldd" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand:QI 2 "immediate_operand" "i")))) + (unspec [(const_int 0)] 544)] + "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" + "evldd %0,%1,%2" + [(set_attr "type" "vecload") + (set_attr "length" "4")]) + +(define_insn "spe_evlddx" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand:SI 2 "gpc_reg_operand" "r")))) + (unspec [(const_int 0)] 545)] + "TARGET_SPE" + "evlddx %0,%1,%2" + [(set_attr "type" "vecload") + (set_attr "length" "4")]) + +(define_insn "spe_evldh" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand:QI 2 "immediate_operand" "i")))) + (unspec [(const_int 0)] 546)] + "TARGET_SPE && INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 31" + "evldh %0,%1,%2" + [(set_attr "type" "vecload") + (set_attr "length" "4")]) + +(define_insn "spe_evldhx" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand:SI 2 "gpc_reg_operand" "r")))) + (unspec [(const_int 0)] 547)] + "TARGET_SPE" + "evldhx %0,%1,%2" + [(set_attr "type" "vecload") + (set_attr "length" "4")]) + +(define_insn "spe_evldw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand:QI 2 "immediate_operand" "i")))) + (unspec [(const_int 0)] 548)] + "TARGET_SPE" + "evldw %0,%1,%2" + [(set_attr "type" "vecload") + (set_attr "length" "4")]) + +(define_insn "spe_evldwx" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand:SI 2 "gpc_reg_operand" "r")))) + (unspec [(const_int 0)] 549)] + "TARGET_SPE" + "evldwx %0,%1,%2" + [(set_attr "type" "vecload") + (set_attr "length" "4")]) + +(define_insn "spe_evlwhe" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand:QI 2 "immediate_operand" "i")))) + (unspec [(const_int 0)] 550)] + "TARGET_SPE" + "evlwhe %0,%1,%2" + [(set_attr "type" "vecload") + (set_attr "length" "4")]) + +(define_insn "spe_evlwhex" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand:SI 2 "gpc_reg_operand" "r")))) + (unspec [(const_int 0)] 551)] + "TARGET_SPE" + "evlwhex %0,%1,%2" + [(set_attr "type" "vecload") + (set_attr "length" "4")]) + +(define_insn "spe_evlwhos" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand:QI 2 "immediate_operand" "i")))) + (unspec [(const_int 0)] 552)] + "TARGET_SPE" + "evlwhos %0,%1,%2" + [(set_attr "type" "vecload") + (set_attr "length" "4")]) + +(define_insn "spe_evlwhosx" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand:SI 2 "gpc_reg_operand" "r")))) + (unspec [(const_int 0)] 553)] + "TARGET_SPE" + "evlwhosx %0,%1,%2" + [(set_attr "type" "vecload") + (set_attr "length" "4")]) + +(define_insn "spe_evlwhou" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand:QI 2 "immediate_operand" "i")))) + (unspec [(const_int 0)] 554)] + "TARGET_SPE" + "evlwhou %0,%1,%2" + [(set_attr "type" "vecload") + (set_attr "length" "4")]) + +(define_insn "spe_evlwhoux" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (mem:V2SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") + (match_operand:SI 2 "gpc_reg_operand" "r")))) + (unspec [(const_int 0)] 555)] + "TARGET_SPE" + "evlwhoux %0,%1,%2" + [(set_attr "type" "vecload") + (set_attr "length" "4")]) + +(define_insn "spe_brinc" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (unspec:SI [(match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")] 556))] + "TARGET_SPE" + "brinc %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhegsmfaa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 557)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhegsmfaa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhegsmfan" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 558)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhegsmfan %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhegsmiaa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 559)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhegsmiaa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhegsmian" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 560)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhegsmian %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhegumiaa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 561)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhegumiaa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhegumian" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 562)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhegumian %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhesmfaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 563)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhesmfaaw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhesmfanw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 564)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhesmfanw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhesmfa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 565)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhesmfa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhesmf" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 566))] + "TARGET_SPE" + "evmhesmf %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhesmiaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 567)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhesmiaaw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhesmianw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 568)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhesmianw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhesmia" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 569)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhesmia %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhesmi" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 570))] + "TARGET_SPE" + "evmhesmi %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhessfaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 571)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhessfaaw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhessfanw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 572)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhessfanw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhessfa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 573)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhessfa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhessf" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 574)) + (clobber (reg:SI SPEFSCR_REGNO))] + "TARGET_SPE" + "evmhessf %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhessiaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 575)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhessiaaw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhessianw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 576)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhessianw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmheumiaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 577)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmheumiaaw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmheumianw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 578)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmheumianw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmheumia" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 579)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmheumia %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmheumi" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 580))] + "TARGET_SPE" + "evmheumi %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmheusiaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 581)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmheusiaaw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmheusianw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 582)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmheusianw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhogsmfaa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 583)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhogsmfaa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhogsmfan" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 584)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhogsmfan %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhogsmiaa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 585)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhogsmiaa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhogsmian" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 586)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhogsmian %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhogumiaa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 587)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhogumiaa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhogumian" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 588)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhogumian %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhosmfaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 589)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhosmfaaw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhosmfanw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 590)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhosmfanw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhosmfa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 591))] + "TARGET_SPE" + "evmhosmfa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhosmf" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 592)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhosmf %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhosmiaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 593)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhosmiaaw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhosmianw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 594)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhosmianw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhosmia" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 595)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhosmia %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhosmi" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 596))] + "TARGET_SPE" + "evmhosmi %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhossfaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 597)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhossfaaw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhossfanw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 598)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhossfanw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhossfa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 599)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhossfa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhossf" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 600)) + (clobber (reg:SI SPEFSCR_REGNO))] + "TARGET_SPE" + "evmhossf %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhossiaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 601)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhossiaaw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhossianw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 602)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhossianw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhoumiaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 603)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhoumiaaw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhoumianw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 604)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhoumianw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhoumia" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 605)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhoumia %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhoumi" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 606))] + "TARGET_SPE" + "evmhoumi %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhousiaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 607)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhousiaaw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmhousianw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 608)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmhousianw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmmlssfa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 609))] + "TARGET_SPE" + "evmmlssfa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmmlssf" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 610))] + "TARGET_SPE" + "evmmlssf %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhsmfa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 611)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwhsmfa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhsmf" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 612))] + "TARGET_SPE" + "evmwhsmf %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhsmia" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 613)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwhsmia %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhsmi" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 614))] + "TARGET_SPE" + "evmwhsmi %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhssfa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 615)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwhssfa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhusian" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 626))] + "TARGET_SPE" + "evmwhusian %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhssf" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 628)) + (clobber (reg:SI SPEFSCR_REGNO))] + "TARGET_SPE" + "evmwhssf %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhumia" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 629)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwhumia %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhumi" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 630))] + "TARGET_SPE" + "evmwhumi %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwlsmiaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 635)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwlsmiaaw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwlsmianw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 636)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwlsmianw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwlssiaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 641)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwlssiaaw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwlssianw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 642)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwlssianw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwlumiaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 643)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwlumiaaw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwlumianw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 644)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwlumianw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwlumia" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 645)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwlumia %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwlumi" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 646))] + "TARGET_SPE" + "evmwlumi %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwlusiaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 647)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwlusiaaw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwlusianw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 648)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwlusianw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwsmfaa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 649)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwsmfaa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwsmfan" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 650)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwsmfan %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwsmfa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 651)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwsmfa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwsmf" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 652))] + "TARGET_SPE" + "evmwsmf %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwsmiaa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 653)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwsmiaa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwsmian" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 654)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwsmian %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwsmia" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 655)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwsmia %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwsmi" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 656))] + "TARGET_SPE" + "evmwsmi %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwssfaa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 657)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwssfaa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwssfan" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 658)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwssfan %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwssfa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 659)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwssfa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwssf" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 660)) + (clobber (reg:SI SPEFSCR_REGNO))] + "TARGET_SPE" + "evmwssf %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwumiaa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 661)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwumiaa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwumian" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 662)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwumian %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwumia" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 663)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwumia %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwumi" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 664))] + "TARGET_SPE" + "evmwumi %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evaddw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (plus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")))] + "TARGET_SPE" + "evaddw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evaddusiaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 673)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evaddusiaaw %0,%1" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evaddumiaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 674)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evaddumiaaw %0,%1" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evaddssiaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 675)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evaddssiaaw %0,%1" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evaddsmiaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 676)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evaddsmiaaw %0,%1" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evaddiw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:QI 2 "immediate_operand" "i")] 677))] + "TARGET_SPE" + "evaddiw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evsubifw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:QI 2 "immediate_operand" "i")] 678))] + "TARGET_SPE" + "evsubifw %0,%2,%1" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evsubfw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (minus:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")))] + "TARGET_SPE" + "evsubfw %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evsubfusiaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 679)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evsubfusiaaw %0,%1" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evsubfumiaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 680)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evsubfumiaaw %0,%1" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evsubfssiaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 681)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evsubfssiaaw %0,%1" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evsubfsmiaaw" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (reg:V2SI SPE_ACC_REGNO)] 682)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evsubfsmiaaw %0,%1" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmra" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (match_operand:V2SI 1 "gpc_reg_operand" "r")) + (set (reg:V2SI SPE_ACC_REGNO) + (unspec:V2SI [(match_dup 1)] 726))] + "TARGET_SPE" + "evmra %0,%1" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evdivws" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (div:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r"))) + (clobber (reg:SI SPEFSCR_REGNO))] + "TARGET_SPE" + "evdivws %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evdivwu" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (udiv:V2SI (match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r"))) + (clobber (reg:SI SPEFSCR_REGNO))] + "TARGET_SPE" + "evdivwu %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evsplatfi" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 684))] + "TARGET_SPE" + "evsplatfi %0,%1" + [(set_attr "type" "vecperm") + (set_attr "length" "4")]) + +(define_insn "spe_evsplati" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:QI 1 "immediate_operand" "i")] 685))] + "TARGET_SPE" + "evsplati %0,%1" + [(set_attr "type" "vecperm") + (set_attr "length" "4")]) + +(define_insn "spe_evstdd" + [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") + (match_operand:QI 1 "immediate_operand" "i"))) + (match_operand:V2SI 2 "gpc_reg_operand" "r")) + (unspec [(const_int 0)] 686)] + "TARGET_SPE" + "evstdd %2,%0,%1" + [(set_attr "type" "vecstore") + (set_attr "length" "4")]) + +(define_insn "spe_evstddx" + [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") + (match_operand:SI 1 "gpc_reg_operand" "r"))) + (match_operand:V2SI 2 "gpc_reg_operand" "r")) + (unspec [(const_int 0)] 687)] + "TARGET_SPE" + "evstddx %2,%0,%1" + [(set_attr "type" "vecstore") + (set_attr "length" "4")]) + +(define_insn "spe_evstdh" + [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") + (match_operand:QI 1 "immediate_operand" "i"))) + (match_operand:V2SI 2 "gpc_reg_operand" "r")) + (unspec [(const_int 0)] 688)] + "TARGET_SPE" + "evstdh %2,%0,%1" + [(set_attr "type" "vecstore") + (set_attr "length" "4")]) + +(define_insn "spe_evstdhx" + [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") + (match_operand:SI 1 "gpc_reg_operand" "r"))) + (match_operand:V2SI 2 "gpc_reg_operand" "r")) + (unspec [(const_int 0)] 689)] + "TARGET_SPE" + "evstdhx %2,%0,%1" + [(set_attr "type" "vecstore") + (set_attr "length" "4")]) + +(define_insn "spe_evstdw" + [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") + (match_operand:QI 1 "immediate_operand" "i"))) + (match_operand:V2SI 2 "gpc_reg_operand" "r")) + (unspec [(const_int 0)] 690)] + "TARGET_SPE" + "evstdw %2,%0,%1" + [(set_attr "type" "vecstore") + (set_attr "length" "4")]) + +(define_insn "spe_evstdwx" + [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") + (match_operand:SI 1 "gpc_reg_operand" "r"))) + (match_operand:V2SI 2 "gpc_reg_operand" "r")) + (unspec [(const_int 0)] 691)] + "TARGET_SPE" + "evstdwx %2,%0,%1" + [(set_attr "type" "vecstore") + (set_attr "length" "4")]) + +(define_insn "spe_evstwhe" + [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") + (match_operand:QI 1 "immediate_operand" "i"))) + (match_operand:V2SI 2 "gpc_reg_operand" "r")) + (unspec [(const_int 0)] 692)] + "TARGET_SPE" + "evstwhe %2,%0,%1" + [(set_attr "type" "vecstore") + (set_attr "length" "4")]) + +(define_insn "spe_evstwhex" + [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") + (match_operand:SI 1 "gpc_reg_operand" "r"))) + (match_operand:V2SI 2 "gpc_reg_operand" "r")) + (unspec [(const_int 0)] 693)] + "TARGET_SPE" + "evstwhex %2,%0,%1" + [(set_attr "type" "vecstore") + (set_attr "length" "4")]) + +(define_insn "spe_evstwho" + [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") + (match_operand:QI 1 "immediate_operand" "i"))) + (match_operand:V2SI 2 "gpc_reg_operand" "r")) + (unspec [(const_int 0)] 694)] + "TARGET_SPE" + "evstwho %2,%0,%1" + [(set_attr "type" "vecstore") + (set_attr "length" "4")]) + +(define_insn "spe_evstwhox" + [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") + (match_operand:SI 1 "gpc_reg_operand" "r"))) + (match_operand:V2SI 2 "gpc_reg_operand" "r")) + (unspec [(const_int 0)] 695)] + "TARGET_SPE" + "evstwhox %2,%0,%1" + [(set_attr "type" "vecstore") + (set_attr "length" "4")]) + +(define_insn "spe_evstwwe" + [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") + (match_operand:QI 1 "immediate_operand" "i"))) + (match_operand:V2SI 2 "gpc_reg_operand" "r")) + (unspec [(const_int 0)] 696)] + "TARGET_SPE" + "evstwwe %2,%0,%1" + [(set_attr "type" "vecstore") + (set_attr "length" "4")]) + +(define_insn "spe_evstwwex" + [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") + (match_operand:SI 1 "gpc_reg_operand" "r"))) + (match_operand:V2SI 2 "gpc_reg_operand" "r")) + (unspec [(const_int 0)] 697)] + "TARGET_SPE" + "evstwwex %2,%0,%1" + [(set_attr "type" "vecstore") + (set_attr "length" "4")]) + +(define_insn "spe_evstwwo" + [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") + (match_operand:QI 1 "immediate_operand" "i"))) + (match_operand:V2SI 2 "gpc_reg_operand" "r")) + (unspec [(const_int 0)] 698)] + "TARGET_SPE" + "evstwwo %2,%0,%1" + [(set_attr "type" "vecstore") + (set_attr "length" "4")]) + +(define_insn "spe_evstwwox" + [(set (mem:V2SI (plus:SI (match_operand:SI 0 "gpc_reg_operand" "b") + (match_operand:SI 1 "gpc_reg_operand" "r"))) + (match_operand:V2SI 2 "gpc_reg_operand" "r")) + (unspec [(const_int 0)] 699)] + "TARGET_SPE" + "evstwwox %2,%0,%1" + [(set_attr "type" "vecstore") + (set_attr "length" "4")]) + +;; SPE vector clears + +(define_insn "*movv2si_const0" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (match_operand:V2SI 1 "zero_constant" ""))] + "TARGET_SPE" + "evxor %0,%0,%0" + [(set_attr "type" "vecsimple")]) + +(define_insn "*movv2sf_const0" + [(set (match_operand:V2SF 0 "gpc_reg_operand" "=r") + (match_operand:V2SF 1 "zero_constant" ""))] + "TARGET_SPE" + "evxor %0,%0,%0" + [(set_attr "type" "vecsimple")]) + +(define_insn "*movv4hi_const0" + [(set (match_operand:V4HI 0 "gpc_reg_operand" "=r") + (match_operand:V4HI 1 "zero_constant" ""))] + "TARGET_SPE" + "evxor %0,%0,%0" + [(set_attr "type" "vecsimple")]) + +(define_insn "*movv1di_const0" + [(set (match_operand:V1DI 0 "gpc_reg_operand" "=r") + (match_operand:V1DI 1 "zero_constant" ""))] + "TARGET_SPE" + "evxor %0,%0,%0" + [(set_attr "type" "vecsimple")]) + +;; Vector move instructions. + +(define_expand "movv2si" + [(set (match_operand:V2SI 0 "nonimmediate_operand" "") + (match_operand:V2SI 1 "any_operand" ""))] + "TARGET_SPE" + "{ rs6000_emit_move (operands[0], operands[1], V2SImode); DONE; }") + + +(define_insn "*movv2si_internal" + [(set (match_operand:V2SI 0 "nonimmediate_operand" "=m,r,r") + (match_operand:V2SI 1 "input_operand" "r,m,r"))] + "TARGET_SPE" + "@ + evstdd%X0 %1,%y0 + evldd%X1 %0,%y1 + evor %0,%1,%1" + [(set_attr "type" "vecload")]) + +(define_expand "movv1di" + [(set (match_operand:V1DI 0 "nonimmediate_operand" "") + (match_operand:V1DI 1 "any_operand" ""))] + "TARGET_SPE" + "{ rs6000_emit_move (operands[0], operands[1], V1DImode); DONE; }") + +(define_insn "*movv1di_internal" + [(set (match_operand:V1DI 0 "nonimmediate_operand" "=m,r,r") + (match_operand:V1DI 1 "input_operand" "r,m,r"))] + "TARGET_SPE" + "@ + evstdd%X0 %1,%y0 + evldd%X1 %0,%y1 + evor %0,%1,%1" + [(set_attr "type" "vecload")]) + +(define_expand "movv4hi" + [(set (match_operand:V4HI 0 "nonimmediate_operand" "") + (match_operand:V4HI 1 "any_operand" ""))] + "TARGET_SPE" + "{ rs6000_emit_move (operands[0], operands[1], V4HImode); DONE; }") + +(define_insn "*movv4hi_internal" + [(set (match_operand:V4HI 0 "nonimmediate_operand" "=m,r,r") + (match_operand:V4HI 1 "input_operand" "r,m,r"))] + "TARGET_SPE" + "@ + evstdd%X0 %1,%y0 + evldd%X1 %0,%y1 + evor %0,%1,%1" + [(set_attr "type" "vecload")]) + +(define_expand "movv2sf" + [(set (match_operand:V2SF 0 "nonimmediate_operand" "") + (match_operand:V2SF 1 "any_operand" ""))] + "TARGET_SPE" + "{ rs6000_emit_move (operands[0], operands[1], V2SFmode); DONE; }") + +(define_insn "*movv2sf_internal" + [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,r,r") + (match_operand:V2SF 1 "input_operand" "r,m,r"))] + "TARGET_SPE" + "@ + evstdd%X0 %1,%y0 + evldd%X1 %0,%y1 + evor %0,%1,%1" + [(set_attr "type" "vecload")]) + +(define_insn "spe_evmwhssfaa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 702)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwhssfaa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhssmaa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 703)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwhssmaa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhsmfaa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 704)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwhsmfaa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhsmiaa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 705)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwhsmiaa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhusiaa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 706)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwhusiaa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhumiaa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 707)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwhumiaa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhssfan" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 708)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwhssfan %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhssian" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 709)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwhssian %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhsmfan" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 710)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwhsmfan %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhsmian" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 711)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwhsmian %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhumian" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 713)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwhumian %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhgssfaa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 714)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwhgssfaa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhgsmfaa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 715)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwhgsmfaa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhgsmiaa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 716)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwhgsmiaa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhgumiaa" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 717)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwhgumiaa %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhgssfan" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 718)) + (clobber (reg:SI SPEFSCR_REGNO)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwhgssfan %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhgsmfan" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 719)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwhgsmfan %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhgsmian" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 720)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwhgsmian %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_evmwhgumian" + [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r") + (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r") + (match_operand:V2SI 2 "gpc_reg_operand" "r")] 721)) + (clobber (reg:V2SI SPE_ACC_REGNO))] + "TARGET_SPE" + "evmwhgumian %0,%1,%2" + [(set_attr "type" "veccomplex") + (set_attr "length" "4")]) + +(define_insn "spe_mtspefscr" + [(set (reg:SI SPEFSCR_REGNO) + (unspec_volatile:SI [(match_operand:SI 0 "register_operand" "r")] + 722))] + "TARGET_SPE" + "mtspefscr %0" + [(set_attr "type" "vecsimple")]) + +(define_insn "spe_mfspefscr" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec_volatile:SI [(reg:SI SPEFSCR_REGNO)] 723))] + "TARGET_SPE" + "mfspefscr %0" + [(set_attr "type" "vecsimple")]) + +;; MPC8540 single-precision FP instructions on GPRs. +;; We have 2 variants for each. One for IEEE compliant math and one +;; for non IEEE compliant math. + +(define_insn "cmpsfeq_gpr" + [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") + (eq:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") + (match_operand:SF 2 "gpc_reg_operand" "r")))] + "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations" + "efscmpeq %0,%1,%2" + [(set_attr "type" "fpcompare")]) + +(define_insn "tstsfeq_gpr" + [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") + (eq:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") + (match_operand:SF 2 "gpc_reg_operand" "r")))] + "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations" + "efststeq %0,%1,%2" + [(set_attr "type" "fpcompare")]) + +(define_insn "cmpsfgt_gpr" + [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") + (gt:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") + (match_operand:SF 2 "gpc_reg_operand" "r")))] + "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations" + "efscmpgt %0,%1,%2" + [(set_attr "type" "fpcompare")]) + +(define_insn "tstsfgt_gpr" + [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") + (gt:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") + (match_operand:SF 2 "gpc_reg_operand" "r")))] + "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations" + "efststgt %0,%1,%2" + [(set_attr "type" "fpcompare")]) + +(define_insn "cmpsflt_gpr" + [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") + (lt:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") + (match_operand:SF 2 "gpc_reg_operand" "r")))] + "TARGET_HARD_FLOAT && !TARGET_FPRS && !flag_unsafe_math_optimizations" + "efscmplt %0,%1,%2" + [(set_attr "type" "fpcompare")]) + +(define_insn "tstsflt_gpr" + [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") + (lt:CCFP (match_operand:SF 1 "gpc_reg_operand" "r") + (match_operand:SF 2 "gpc_reg_operand" "r")))] + "TARGET_HARD_FLOAT && !TARGET_FPRS && flag_unsafe_math_optimizations" + "efststlt %0,%1,%2" + [(set_attr "type" "fpcompare")]) + diff --git a/contrib/gcc/config/rs6000/sysv4.h b/contrib/gcc/config/rs6000/sysv4.h index ecc37ee..3da996f 100644 --- a/contrib/gcc/config/rs6000/sysv4.h +++ b/contrib/gcc/config/rs6000/sysv4.h @@ -1,5 +1,5 @@ /* Target definitions for GNU compiler for PowerPC running System V.4 - Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2003 + Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. Contributed by Cygnus Support. @@ -21,6 +21,9 @@ the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +/* Header files should be C++ aware in general. */ +#define NO_IMPLICIT_EXTERN_C + /* Yes! We are ELF. */ #define TARGET_OBJECT_FORMAT OBJECT_ELF @@ -34,10 +37,6 @@ Boston, MA 02111-1307, USA. */ #undef ASM_DEFAULT_SPEC #define ASM_DEFAULT_SPEC "-mppc" -/* Override rs6000.h definition. */ -#undef CPP_DEFAULT_SPEC -#define CPP_DEFAULT_SPEC "-D_ARCH_PPC" - /* Small data support types. */ enum rs6000_sdata_type { SDATA_NONE, /* No small data support. */ @@ -152,6 +151,7 @@ extern int g_switch_set; /* Whether -G xx was passed. */ { "emb", 0, \ N_("Set the PPC_EMB bit in the ELF flags header") }, \ { "vxworks", 0, N_("no description yet") }, \ + { "windiss", 0, N_("Use the WindISS simulator") }, \ { "shlib", 0, N_("no description yet") }, \ EXTRA_SUBTARGET_SWITCHES \ { "newlib", 0, N_("no description yet") }, @@ -257,13 +257,16 @@ do { \ rs6000_sdata_name); \ } \ \ - if (rs6000_sdata != SDATA_NONE && DEFAULT_ABI != ABI_V4) \ + if ((rs6000_sdata != SDATA_NONE && DEFAULT_ABI != ABI_V4) \ + || (rs6000_sdata == SDATA_EABI && !TARGET_EABI)) \ { \ rs6000_sdata = SDATA_NONE; \ error ("-msdata=%s and -mcall-%s are incompatible", \ rs6000_sdata_name, rs6000_abi_name); \ } \ \ + targetm.have_srodata_section = rs6000_sdata == SDATA_EABI; \ + \ if (TARGET_RELOCATABLE && !TARGET_MINIMAL_TOC) \ { \ target_flags |= MASK_MINIMAL_TOC; \ @@ -326,7 +329,7 @@ do { \ /* Define this to set the endianness to use in libgcc2.c, which can not depend on target_flags. */ -#if !defined(_LITTLE_ENDIAN) && !defined(__sun__) +#if !defined(__LITTLE_ENDIAN__) && !defined(__sun__) #define LIBGCC2_WORDS_BIG_ENDIAN 1 #else #define LIBGCC2_WORDS_BIG_ENDIAN 0 @@ -383,10 +386,6 @@ do { \ /* Real stack boundary as mandated by the appropriate ABI. */ #define ABI_STACK_BOUNDARY ((TARGET_EABI && !TARGET_ALTIVEC_ABI) ? 64 : 128) -/* No data type wants to be aligned rounder than this. */ -#undef BIGGEST_ALIGNMENT -#define BIGGEST_ALIGNMENT ((TARGET_EABI && !TARGET_ALTIVEC) ? 64 : 128) - /* An expression for the alignment of a structure field FIELD if the alignment computed in the usual way is COMPUTED. */ #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ @@ -433,12 +432,11 @@ do { \ /* Besides the usual ELF sections, we need a toc section. */ /* Override elfos.h definition. */ #undef EXTRA_SECTIONS -#define EXTRA_SECTIONS in_const, in_toc, in_sdata, in_sdata2, in_sbss, in_init, in_fini +#define EXTRA_SECTIONS in_toc, in_sdata, in_sdata2, in_sbss, in_init, in_fini /* Override elfos.h definition. */ #undef EXTRA_SECTION_FUNCTIONS #define EXTRA_SECTION_FUNCTIONS \ - CONST_SECTION_FUNCTION \ TOC_SECTION_FUNCTION \ SDATA_SECTION_FUNCTION \ SDATA2_SECTION_FUNCTION \ @@ -550,41 +548,14 @@ fini_section () \ } \ } -/* A C statement or statements to switch to the appropriate section - for output of RTX in mode MODE. You can assume that RTX is some - kind of constant in RTL. The argument MODE is redundant except in - the case of a `const_int' rtx. Select the section by calling - `text_section' or one of the alternatives for other sections. - - Do not define this macro if you put all constants in the read-only - data section. */ - -/* Override elfos.h definition. */ -#undef SELECT_RTX_SECTION -#define SELECT_RTX_SECTION(MODE, X, ALIGN) rs6000_select_rtx_section (MODE, X) - -/* A C statement or statements to switch to the appropriate - section for output of DECL. DECL is either a `VAR_DECL' node - or a constant of some sort. RELOC indicates whether forming - the initial value of DECL requires link-time relocations. */ - -/* Override elfos.h definition. */ -#undef SELECT_SECTION -#define SELECT_SECTION(DECL, RELOC, ALIGN) rs6000_select_section (DECL, RELOC) +/* Override default elf definitions. */ +#undef TARGET_ASM_SELECT_RTX_SECTION +#define TARGET_ASM_SELECT_RTX_SECTION rs6000_elf_select_rtx_section +#undef TARGET_ASM_SELECT_SECTION +#define TARGET_ASM_SELECT_SECTION rs6000_elf_select_section +#define TARGET_ASM_UNIQUE_SECTION rs6000_elf_unique_section -/* A C statement to build up a unique section name, expressed as a - STRING_CST node, and assign it to DECL_SECTION_NAME (decl). - RELOC indicates whether the initial value of EXP requires - link-time relocations. If you do not define this macro, GCC will use - the symbol name prefixed by `.' as the section name. Note - this - macro can now be called for uninitialized data items as well as - initialised data and functions. */ - -/* Override elfos.h definition. */ -#undef UNIQUE_SECTION -#define UNIQUE_SECTION(DECL, RELOC) rs6000_unique_section (DECL, RELOC) - -/* Return non-zero if this entry is to be written into the constant pool +/* Return nonzero if this entry is to be written into the constant pool in a special way. We do so if this is a SYMBOL_REF, LABEL_REF or a CONST containing one of them. If -mfp-in-toc (the default), we also do this for floating-point constants. We actually can only do this @@ -644,18 +615,14 @@ extern int rs6000_pic_labelno; putc ('\n', FILE); \ } \ \ - fprintf (FILE, "%s", TYPE_ASM_OP); \ - assemble_name (FILE, NAME); \ - putc (',', FILE); \ - fprintf (FILE, TYPE_OPERAND_FMT, "function"); \ - putc ('\n', FILE); \ + ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "function"); \ ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ \ if (DEFAULT_ABI == ABI_AIX) \ { \ const char *desc_name, *orig_name; \ \ - STRIP_NAME_ENCODING (orig_name, NAME); \ + orig_name = (*targetm.strip_name_encoding) (NAME); \ desc_name = orig_name; \ while (*desc_name == '.') \ desc_name++; \ @@ -674,39 +641,6 @@ extern int rs6000_pic_labelno; ASM_OUTPUT_LABEL (FILE, NAME); \ } while (0) -/* A C compound statement that outputs the assembler code for a thunk function, - used to implement C++ virtual function calls with multiple inheritance. The - thunk acts as a wrapper around a virtual function, adjusting the implicit - object parameter before handing control off to the real function. - - First, emit code to add the integer DELTA to the location that contains the - incoming first argument. Assume that this argument contains a pointer, and - is the one used to pass the this' pointer in C++. This is the incoming - argument *before* the function prologue, e.g. %o0' on a sparc. The - addition must preserve the values of all other incoming arguments. - - After the addition, emit code to jump to FUNCTION, which is a - FUNCTION_DECL'. This is a direct pure jump, not a call, and does not touch - the return address. Hence returning from FUNCTION will return to whoever - called the current thunk'. - - The effect must be as if FUNCTION had been called directly with the adjusted - first argument. This macro is responsible for emitting all of the code for - a thunk function; FUNCTION_PROLOGUE' and FUNCTION_EPILOGUE' are not - invoked. - - The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already been - extracted from it.) It might possibly be useful on some targets, but - probably not. - - If you do not define this macro, the target-independent code in the C++ - frontend will generate a less efficient heavyweight thunk that calls - FUNCTION instead of jumping to it. The generic approach does not support - varargs. */ - -#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \ - output_mi_thunk (FILE, THUNK_FNDECL, DELTA, FUNCTION) - /* The USER_LABEL_PREFIX stuff is affected by the -fleading-underscore flag. The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */ @@ -718,15 +652,8 @@ extern int rs6000_pic_labelno; #define ASM_OUTPUT_INTERNAL_LABEL_PREFIX(FILE,PREFIX) \ asm_fprintf (FILE, "%L%s", PREFIX) -#define ASM_OUTPUT_LABEL(FILE,NAME) \ - (assemble_name (FILE, NAME), fputs (":\n", FILE)) - -/* This is how to output a command to make the user-level label named NAME - defined for reference from other files. */ - -#define ASM_GLOBALIZE_LABEL(FILE,NAME) \ - do { fputs ("\t.globl ", FILE); \ - assemble_name (FILE, NAME); putc ('\n', FILE);} while (0) +/* Globalizing directive for a label. */ +#define GLOBAL_ASM_OP "\t.globl " /* This says how to output assembler code to declare an uninitialized internal linkage data object. Under SVR4, @@ -749,11 +676,7 @@ do { \ ASM_OUTPUT_LABEL (FILE, NAME); \ ASM_OUTPUT_SKIP (FILE, SIZE); \ if (!flag_inhibit_size_directive && (SIZE) > 0) \ - { \ - fprintf (FILE, "%s", SIZE_ASM_OP); \ - assemble_name (FILE, NAME); \ - fprintf (FILE, ",%d\n", SIZE); \ - } \ + ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \ } \ else \ { \ @@ -761,12 +684,12 @@ do { \ assemble_name ((FILE), (NAME)); \ fprintf ((FILE), ",%u,%u\n", (SIZE), (ALIGN) / BITS_PER_UNIT); \ } \ + ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \ } while (0) /* Describe how to emit uninitialized external linkage items. */ #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ do { \ - ASM_GLOBALIZE_LABEL (FILE, NAME); \ ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ } while (0) @@ -781,9 +704,7 @@ do { \ do { \ if (DEFAULT_ABI == ABI_V4) \ asm_fprintf (FILE, \ - (TARGET_32BIT \ - ? "\t{stu|stwu} %s,-16(%s)\n\t{st|stw} %s,12(%s)\n" \ - : "\tstdu %s,-32(%s)\n\tstd %s,24(%s)\n"), \ + "\t{stu|stwu} %s,-16(%s)\n\t{st|stw} %s,12(%s)\n", \ reg_names[1], reg_names[1], reg_names[REGNO], \ reg_names[1]); \ } while (0) @@ -795,9 +716,7 @@ do { \ do { \ if (DEFAULT_ABI == ABI_V4) \ asm_fprintf (FILE, \ - (TARGET_32BIT \ - ? "\t{l|lwz} %s,12(%s)\n\t{ai|addic} %s,%s,16\n" \ - : "\tld %s,24(%s)\n\t{ai|addic} %s,%s,32\n"), \ + "\t{l|lwz} %s,12(%s)\n\t{ai|addic} %s,%s,16\n", \ reg_names[REGNO], reg_names[1], reg_names[1], \ reg_names[1]); \ } while (0) @@ -832,39 +751,22 @@ extern int fixuplabelno; /* This is the end of what might become sysv4.h. */ /* Use DWARF 2 debugging information by default. */ -#undef PREFERRED_DEBUGGING_TYPE -#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG +#undef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG /* Historically we have also supported stabs debugging. */ -#define DBX_DEBUGGING_INFO - -/* If we are referencing a function that is static or is known to be - in this file, make the SYMBOL_REF special. We can use this to indicate - that we can branch to this function without emitting a no-op after the - call. For real AIX calling sequences, we also replace the - function name with the real name (1 or 2 leading .'s), rather than - the function descriptor name. This saves a lot of overriding code - to read the prefixes. */ +#define DBX_DEBUGGING_INFO 1 -#undef ENCODE_SECTION_INFO -#define ENCODE_SECTION_INFO(DECL) rs6000_encode_section_info (DECL) +#define TARGET_ENCODE_SECTION_INFO rs6000_elf_encode_section_info +#define TARGET_STRIP_NAME_ENCODING rs6000_elf_strip_name_encoding +#define TARGET_IN_SMALL_DATA_P rs6000_elf_in_small_data_p +#define TARGET_SECTION_TYPE_FLAGS rs6000_elf_section_type_flags /* The ELF version doesn't encode [DS] or whatever at the end of symbols. */ #define RS6000_OUTPUT_BASENAME(FILE, NAME) \ assemble_name (FILE, NAME) -/* This macro gets just the user-specified name - out of the string in a SYMBOL_REF. Discard - a leading * or @. */ -#define STRIP_NAME_ENCODING(VAR,SYMBOL_NAME) \ -do { \ - const char *_name = SYMBOL_NAME; \ - while (*_name == '*' || *_name == '@') \ - _name++; \ - (VAR) = _name; \ -} while (0) - /* This is how to output a reference to a user-level label named NAME. `assemble_name' uses this. */ @@ -893,9 +795,19 @@ do { \ #define TARGET_VERSION fprintf (stderr, " (PowerPC System V.4)"); #endif -#ifndef CPP_PREDEFINES -#define CPP_PREDEFINES \ - "-DPPC -Dunix -D__svr4__ -Asystem=unix -Asystem=svr4 -Acpu=powerpc -Amachine=powerpc" +#ifndef TARGET_OS_CPP_BUILTINS +#define TARGET_OS_CPP_BUILTINS() \ + do \ + { \ + builtin_define_std ("PPC"); \ + builtin_define_std ("unix"); \ + builtin_define ("__svr4__"); \ + builtin_assert ("system=unix"); \ + builtin_assert ("system=svr4"); \ + builtin_assert ("cpu=powerpc"); \ + builtin_assert ("machine=powerpc"); \ + } \ + while (0) #endif /* Pass various options to the assembler. */ @@ -977,12 +889,14 @@ do { \ %{myellowknife: %(link_start_yellowknife) } \ %{mmvme: %(link_start_mvme) } \ %{msim: %(link_start_sim) } \ +%{mwindiss: %(link_start_windiss) } \ %{mcall-freebsd: %(link_start_freebsd) } \ %{mcall-linux: %(link_start_linux) } \ %{mcall-gnu: %(link_start_gnu) } \ %{mcall-netbsd: %(link_start_netbsd) } \ -%{!mads: %{!myellowknife: %{!mmvme: %{!msim: %{!mcall-linux: %{!mcall-gnu: \ - %{!mcall-netbsd: %{!mcall-freebsd: %(link_start_default) }}}}}}}}" +%{!mads: %{!myellowknife: %{!mmvme: %{!msim: %{!mwindiss: \ + %{!mcall-linux: %{!mcall-gnu: %{!mcall-netbsd: \ + %{!mcall-freebsd: %(link_start_default) }}}}}}}}}" #define LINK_START_DEFAULT_SPEC "" @@ -1034,75 +948,37 @@ do { \ %{myellowknife: %(link_os_yellowknife) } \ %{mmvme: %(link_os_mvme) } \ %{msim: %(link_os_sim) } \ +%{mwindiss: %(link_os_windiss) } \ %{mcall-freebsd: %(link_os_freebsd) } \ %{mcall-linux: %(link_os_linux) } \ %{mcall-gnu: %(link_os_gnu) } \ %{mcall-netbsd: %(link_os_netbsd) } \ -%{!mads: %{!myellowknife: %{!mmvme: %{!msim: %{!mcall-freebsd: %{!mcall-linux: %{!mcall-gnu: %{!mcall-netbsd: %(link_os_default) }}}}}}}}" +%{!mads: %{!myellowknife: %{!mmvme: %{!msim: %{!mwindiss: \ + %{!mcall-freebsd: %{!mcall-linux: %{!mcall-gnu: \ + %{!mcall-netbsd: %(link_os_default) }}}}}}}}}" #define LINK_OS_DEFAULT_SPEC "" #define CPP_SYSV_SPEC \ "%{mrelocatable*: -D_RELOCATABLE} \ %{fpic: -D__PIC__=1 -D__pic__=1} \ -%{!fpic: %{fPIC: -D__PIC__=2 -D__pic__=2}} \ -%{mlong-double-128: -D__LONG_DOUBLE_128__=1} \ -%{!mlong-double-64: %(cpp_longdouble_default)} \ -%{mcall-sysv: -D_CALL_SYSV} \ -%{mcall-aix: -D_CALL_AIX} %{mcall-aixdesc: -D_CALL_AIX -D_CALL_AIXDESC} \ -%{!mcall-sysv: %{!mcall-aix: %{!mcall-aixdesc: %(cpp_sysv_default) }}} \ -%{msoft-float: -D_SOFT_FLOAT} \ -%{!msoft-float: %{!mhard-float: \ - %{mcpu=401: -D_SOFT_FLOAT} \ - %{mcpu=403: -D_SOFT_FLOAT} \ - %{mcpu=405: -D_SOFT_FLOAT} \ - %{mcpu=ec603e: -D_SOFT_FLOAT} \ - %{mcpu=801: -D_SOFT_FLOAT} \ - %{mcpu=821: -D_SOFT_FLOAT} \ - %{mcpu=823: -D_SOFT_FLOAT} \ - %{mcpu=860: -D_SOFT_FLOAT} \ - %{!mcpu*: %(cpp_float_default) }}}" - -/* Whether floating point is disabled by default. */ -#define CPP_FLOAT_DEFAULT_SPEC "" - -/* Whether 'long double' is 128 bits by default. */ -#define CPP_LONGDOUBLE_DEFAULT_SPEC "" - -#define CPP_SYSV_DEFAULT_SPEC "-D_CALL_SYSV" - -#define CPP_ENDIAN_BIG_SPEC "-D_BIG_ENDIAN -D__BIG_ENDIAN__ -Amachine=bigendian" - -#define CPP_ENDIAN_LITTLE_SPEC "-D_LITTLE_ENDIAN -D__LITTLE_ENDIAN__ -Amachine=littleendian" - -#define CPP_ENDIAN_SPEC \ -"%{mlittle: %(cpp_endian_little) } \ -%{mlittle-endian: %(cpp_endian_little) } \ -%{mbig: %(cpp_endian_big) } \ -%{mbig-endian: %(cpp_endian_big) } \ -%{!mlittle: %{!mlittle-endian: %{!mbig: %{!mbig-endian: \ - %{mcall-freebsd: %(cpp_endian_big) } \ - %{mcall-linux: %(cpp_endian_big) } \ - %{mcall-gnu: %(cpp_endian_big) } \ - %{mcall-netbsd: %(cpp_endian_big) } \ - %{mcall-i960-old: %(cpp_endian_little) } \ - %{mcall-aixdesc: %(cpp_endian_big) } \ - %{!mcall-linux: %{!mcall-gnu: %{!mcall-freebsd: %{!mcall-netbsd: %{!mcall-aixdesc: %(cpp_endian_default) }}}}}}}}}" - -#define CPP_ENDIAN_DEFAULT_SPEC "%(cpp_endian_big)" +%{!fpic: %{fPIC: -D__PIC__=2 -D__pic__=2}}" /* Override rs6000.h definition. */ #undef CPP_SPEC -#define CPP_SPEC "%{posix: -D_POSIX_SOURCE} %(cpp_sysv) %(cpp_endian) %(cpp_cpu) \ +#define CPP_SPEC "%{posix: -D_POSIX_SOURCE} %(cpp_sysv) \ %{mads: %(cpp_os_ads) } \ %{myellowknife: %(cpp_os_yellowknife) } \ %{mmvme: %(cpp_os_mvme) } \ %{msim: %(cpp_os_sim) } \ +%{mwindiss: %(cpp_os_windiss) } \ %{mcall-freebsd: %(cpp_os_freebsd) } \ %{mcall-linux: %(cpp_os_linux) } \ %{mcall-gnu: %(cpp_os_gnu) } \ %{mcall-netbsd: %(cpp_os_netbsd) } \ -%{!mads: %{!myellowknife: %{!mmvme: %{!msim: %{!mcall-freebsd: %{!mcall-linux: %{!mcall-gnu: %{!mcall-netbsd: %(cpp_os_default) }}}}}}}}" +%{!mads: %{!myellowknife: %{!mmvme: %{!msim: %{!mwindiss: \ + %{!mcall-freebsd: %{!mcall-linux: %{!mcall-gnu: \ + %{!mcall-netbsd: %(cpp_os_default) }}}}}}}}}" #define CPP_OS_DEFAULT_SPEC "" @@ -1113,11 +989,14 @@ do { \ %{myellowknife: %(startfile_yellowknife) } \ %{mmvme: %(startfile_mvme) } \ %{msim: %(startfile_sim) } \ +%{mwindiss: %(startfile_windiss) } \ %{mcall-freebsd: %(startfile_freebsd) } \ %{mcall-linux: %(startfile_linux) } \ %{mcall-gnu: %(startfile_gnu) } \ %{mcall-netbsd: %(startfile_netbsd) } \ -%{!mads: %{!myellowknife: %{!mmvme: %{!msim: %{!mcall-freebsd: %{!mcall-linux: %{!mcall-gnu: %{!mcall-netbsd: %(startfile_default) }}}}}}}}" +%{!mads: %{!myellowknife: %{!mmvme: %{!msim: %{!mwindiss: \ + %{!mcall-freebsd: %{!mcall-linux: %{!mcall-gnu: \ + %{!mcall-netbsd: %(startfile_default) }}}}}}}}}" #define STARTFILE_DEFAULT_SPEC "" @@ -1128,27 +1007,36 @@ do { \ %{myellowknife: %(lib_yellowknife) } \ %{mmvme: %(lib_mvme) } \ %{msim: %(lib_sim) } \ +%{mwindiss: %(lib_windiss) } \ %{mcall-freebsd: %(lib_freebsd) } \ %{mcall-linux: %(lib_linux) } \ %{mcall-gnu: %(lib_gnu) } \ %{mcall-netbsd: %(lib_netbsd) } \ -%{!mads: %{!myellowknife: %{!mmvme: %{!msim: %{!mcall-freebsd: %{!mcall-linux: %{!mcall-gnu: %{!mcall-netbsd: %(lib_default) }}}}}}}}" +%{!mads: %{!myellowknife: %{!mmvme: %{!msim: %{!mwindiss: \ + %{!mcall-freebsd: %{!mcall-linux: %{!mcall-gnu: \ + %{!mcall-netbsd: %(lib_default) }}}}}}}}}" #define LIB_DEFAULT_SPEC "" /* Override svr4.h definition. */ #undef ENDFILE_SPEC -#define ENDFILE_SPEC "crtsavres.o%s \ -%{mads: %(endfile_ads)} \ -%{myellowknife: %(endfile_yellowknife)} \ -%{mmvme: %(endfile_mvme)} \ -%{msim: %(endfile_sim)} \ -%{mcall-freebsd: %(endfile_freebsd) } \ -%{mcall-linux: %(endfile_linux) } \ -%{mcall-gnu: %(endfile_gnu) } \ -%{mcall-netbsd: %(endfile_netbsd) } \ -%{mvxworks: %(endfile_vxworks) } \ -%{!mads: %{!myellowknife: %{!mmvme: %{!msim: %{!mcall-freebsd: %{!mcall-linux: %{!mcall-gnu: %{!mcall-netbsd: %{!mvxworks: %(endfile_default) }}}}}}}}}" +#define ENDFILE_SPEC "\ +%{mads: crtsavres.o%s %(endfile_ads)} \ +%{myellowknife: crtsavres.o%s %(endfile_yellowknife)} \ +%{mmvme: crtsavres.o%s %(endfile_mvme)} \ +%{msim: crtsavres.o%s %(endfile_sim)} \ +%{mwindiss: %(endfile_windiss)} \ +%{mcall-freebsd: crtsavres.o%s %(endfile_freebsd) } \ +%{mcall-linux: crtsavres.o%s %(endfile_linux) } \ +%{mcall-gnu: crtsavres.o%s %(endfile_gnu) } \ +%{mcall-netbsd: crtsavres.o%s %(endfile_netbsd) } \ +%{mvxworks: crtsavres.o%s %(endfile_vxworks) } \ +%{!mads: %{!myellowknife: %{!mmvme: %{!msim: %{!mwindiss: \ + %{!mcall-freebsd: %{!mcall-linux: %{!mcall-gnu: \ + %{!mcall-netbsd: %{!mvxworks: %(crtsavres_default) \ + %(endfile_default) }}}}}}}}}}" + +#define CRTSAVRES_DEFAULT_SPEC "crtsavres.o%s" #define ENDFILE_DEFAULT_SPEC "" @@ -1207,7 +1095,7 @@ do { \ /* FreeBSD support. */ #define CPP_OS_FREEBSD_SPEC "\ - -D__PPC__ -D__ppc__ -D__PowerPC__ -D__powerpc__ \ + -D__ELF__ -D__PPC__ -D__ppc__ -D__PowerPC__ -D__powerpc__ \ -Acpu=powerpc -Amachine=powerpc" #define STARTFILE_FREEBSD_SPEC FBSD_STARTFILE_SPEC @@ -1216,7 +1104,17 @@ do { \ #define LINK_START_FREEBSD_SPEC "" #define LINK_OS_FREEBSD_SPEC "\ - %{symbolic:-Bsymbolic}" + %{p:%e`-p' not supported; use `-pg' and gprof(1)} \ + %{Wl,*:%*} \ + %{v:-V} \ + %{assert*} %{R*} %{rpath*} %{defsym*} \ + %{shared:-Bshareable %{h*} %{soname*}} \ + %{!shared: \ + %{!static: \ + %{rdynamic: -export-dynamic} \ + %{!dynamic-linker: -dynamic-linker /usr/libexec/ld-elf.so.1}} \ + %{static:-Bstatic}} \ + %{symbolic:-Bsymbolic}" /* GNU/Linux support. */ #ifdef USE_GNULIBC_1 @@ -1375,14 +1273,31 @@ ncrtn.o%s" %{mcpu=823: -DCPU=PPC603} \ %{mcpu=860: -DCPU=PPC603}" +/* WindISS support. */ + +#define LIB_WINDISS_SPEC "--start-group -li -lcfp -lwindiss -lram -limpl -limpfp --end-group" + +#define CPP_OS_WINDISS_SPEC "\ +-D__rtasim \ +-D__EABI__ \ +-D__ppc \ +%{!msoft-float: -D__hardfp} \ +" + +#define STARTFILE_WINDISS_SPEC "crt0.o%s crtbegin.o%s" + +#define ENDFILE_WINDISS_SPEC "crtend.o%s" + +#define LINK_START_WINDISS_SPEC "" + +#define LINK_OS_WINDISS_SPEC "" + /* Define any extra SPECS that the compiler needs to generate. */ /* Override rs6000.h definition. */ #undef SUBTARGET_EXTRA_SPECS #define SUBTARGET_EXTRA_SPECS \ { "cpp_sysv", CPP_SYSV_SPEC }, \ - { "cpp_sysv_default", CPP_SYSV_DEFAULT_SPEC }, \ - { "cpp_endian_default", CPP_ENDIAN_DEFAULT_SPEC }, \ - { "cpp_endian", CPP_ENDIAN_SPEC }, \ + { "crtsavres_default", CRTSAVRES_DEFAULT_SPEC }, \ { "lib_ads", LIB_ADS_SPEC }, \ { "lib_yellowknife", LIB_YELLOWKNIFE_SPEC }, \ { "lib_mvme", LIB_MVME_SPEC }, \ @@ -1392,6 +1307,7 @@ ncrtn.o%s" { "lib_linux", LIB_LINUX_SPEC }, \ { "lib_netbsd", LIB_NETBSD_SPEC }, \ { "lib_vxworks", LIB_VXWORKS_SPEC }, \ + { "lib_windiss", LIB_WINDISS_SPEC }, \ { "lib_default", LIB_DEFAULT_SPEC }, \ { "startfile_ads", STARTFILE_ADS_SPEC }, \ { "startfile_yellowknife", STARTFILE_YELLOWKNIFE_SPEC }, \ @@ -1402,6 +1318,7 @@ ncrtn.o%s" { "startfile_linux", STARTFILE_LINUX_SPEC }, \ { "startfile_netbsd", STARTFILE_NETBSD_SPEC }, \ { "startfile_vxworks", STARTFILE_VXWORKS_SPEC }, \ + { "startfile_windiss", STARTFILE_WINDISS_SPEC }, \ { "startfile_default", STARTFILE_DEFAULT_SPEC }, \ { "endfile_ads", ENDFILE_ADS_SPEC }, \ { "endfile_yellowknife", ENDFILE_YELLOWKNIFE_SPEC }, \ @@ -1412,6 +1329,7 @@ ncrtn.o%s" { "endfile_linux", ENDFILE_LINUX_SPEC }, \ { "endfile_netbsd", ENDFILE_NETBSD_SPEC }, \ { "endfile_vxworks", ENDFILE_VXWORKS_SPEC }, \ + { "endfile_windiss", ENDFILE_WINDISS_SPEC }, \ { "endfile_default", ENDFILE_DEFAULT_SPEC }, \ { "link_path", LINK_PATH_SPEC }, \ { "link_shlib", LINK_SHLIB_SPEC }, \ @@ -1426,6 +1344,7 @@ ncrtn.o%s" { "link_start_linux", LINK_START_LINUX_SPEC }, \ { "link_start_netbsd", LINK_START_NETBSD_SPEC }, \ { "link_start_vxworks", LINK_START_VXWORKS_SPEC }, \ + { "link_start_windiss", LINK_START_WINDISS_SPEC }, \ { "link_start_default", LINK_START_DEFAULT_SPEC }, \ { "link_os", LINK_OS_SPEC }, \ { "link_os_ads", LINK_OS_ADS_SPEC }, \ @@ -1437,14 +1356,11 @@ ncrtn.o%s" { "link_os_gnu", LINK_OS_GNU_SPEC }, \ { "link_os_netbsd", LINK_OS_NETBSD_SPEC }, \ { "link_os_vxworks", LINK_OS_VXWORKS_SPEC }, \ + { "link_os_windiss", LINK_OS_WINDISS_SPEC }, \ { "link_os_default", LINK_OS_DEFAULT_SPEC }, \ { "cc1_endian_big", CC1_ENDIAN_BIG_SPEC }, \ { "cc1_endian_little", CC1_ENDIAN_LITTLE_SPEC }, \ { "cc1_endian_default", CC1_ENDIAN_DEFAULT_SPEC }, \ - { "cpp_endian_big", CPP_ENDIAN_BIG_SPEC }, \ - { "cpp_endian_little", CPP_ENDIAN_LITTLE_SPEC }, \ - { "cpp_float_default", CPP_FLOAT_DEFAULT_SPEC }, \ - { "cpp_longdouble_default", CPP_LONGDOUBLE_DEFAULT_SPEC }, \ { "cpp_os_ads", CPP_OS_ADS_SPEC }, \ { "cpp_os_yellowknife", CPP_OS_YELLOWKNIFE_SPEC }, \ { "cpp_os_mvme", CPP_OS_MVME_SPEC }, \ @@ -1453,8 +1369,9 @@ ncrtn.o%s" { "cpp_os_gnu", CPP_OS_GNU_SPEC }, \ { "cpp_os_linux", CPP_OS_LINUX_SPEC }, \ { "cpp_os_netbsd", CPP_OS_NETBSD_SPEC }, \ - { "cpp_os_vxworks", CPP_OS_VXWORKS_SPEC }, \ { "cpp_os_rtems", CPP_OS_RTEMS_SPEC }, \ + { "cpp_os_vxworks", CPP_OS_VXWORKS_SPEC }, \ + { "cpp_os_windiss", CPP_OS_WINDISS_SPEC }, \ { "cpp_os_default", CPP_OS_DEFAULT_SPEC }, /* Define this macro as a C expression for the initializer of an @@ -1481,7 +1398,7 @@ ncrtn.o%s" pack(pop)'. The pack(push,<n>) pragma specifies the maximum alignment (in bytes) of fields within a structure, in much the same way as the __aligned__' and __packed__' __attribute__'s - do. A pack value of zero resets the behaviour to the default. + do. A pack value of zero resets the behavior to the default. Successive invocations of this pragma cause the previous values to be stacked, so that invocations of #pragma pack(pop)' will return to the previous value. */ diff --git a/contrib/gcc/config/rs6000/sysv4le.h b/contrib/gcc/config/rs6000/sysv4le.h index 1c0daea..fda8477 100644 --- a/contrib/gcc/config/rs6000/sysv4le.h +++ b/contrib/gcc/config/rs6000/sysv4le.h @@ -23,9 +23,6 @@ Boston, MA 02111-1307, USA. */ #undef TARGET_DEFAULT #define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_LITTLE_ENDIAN) -#undef CPP_ENDIAN_DEFAULT_SPEC -#define CPP_ENDIAN_DEFAULT_SPEC "%(cpp_endian_little)" - #undef CC1_ENDIAN_DEFAULT_SPEC #define CC1_ENDIAN_DEFAULT_SPEC "%(cc1_endian_little)" diff --git a/contrib/gcc/config/rs6000/t-aix43 b/contrib/gcc/config/rs6000/t-aix43 index 9bbfe00..a716209 100644 --- a/contrib/gcc/config/rs6000/t-aix43 +++ b/contrib/gcc/config/rs6000/t-aix43 @@ -19,27 +19,24 @@ MULTILIB_OPTIONS = pthread \ MULTILIB_DIRNAMES = pthread \ common power powerpc ppc64 -MULTILIB_MATCHES = mcpu?power=mpower \ - mcpu?power=mrios1 \ +MULTILIB_MATCHES = mcpu?power=mcpu?power \ + mcpu?power=mcpu?power2 \ + mcpu?powerpc=mcpu?power3 \ + mcpu?powerpc=mcpu?power4 \ + mcpu?powerpc=mcpu?powerpc \ mcpu?power=mcpu?rios1 \ + mcpu?power=mcpu?rios2 \ mcpu?power=mcpu?rsc \ mcpu?power=mcpu?rsc1 \ - mcpu?power=mpower2 \ - mcpu?power=mrios2 \ - mcpu?power=mcpu?rios2 \ mcpu?powerpc=mcpu?rs64a \ mcpu?powerpc=mcpu?601 \ mcpu?powerpc=mcpu?602 \ mcpu?powerpc=mcpu?603 \ mcpu?powerpc=mcpu?603e \ mcpu?powerpc=mcpu?604 \ + mcpu?powerpc=mcpu?604e \ mcpu?powerpc=mcpu?620 \ - mcpu?powerpc=mcpu?630 \ - mcpu?powerpc=mcpu?750 \ - mcpu?powerpc=mcpu?403 \ - mcpu?powerpc=mpowerpc \ - mcpu?powerpc=mpowerpc-gpopt \ - mcpu?powerpc=mpowerpc-gfxopt + mcpu?powerpc=mcpu?630 LIBGCC = stmp-multilib INSTALL_LIBGCC = install-multilib diff --git a/contrib/gcc/config/rs6000/t-aix52 b/contrib/gcc/config/rs6000/t-aix52 new file mode 100644 index 0000000..bddcdb1 --- /dev/null +++ b/contrib/gcc/config/rs6000/t-aix52 @@ -0,0 +1,52 @@ +# We want fine grained libraries, so use the new code to build the +# floating point emulation libraries. +FPBIT = fp-bit.c +DPBIT = dp-bit.c + +dp-bit.c: $(srcdir)/config/fp-bit.c + cat $(srcdir)/config/fp-bit.c > dp-bit.c + +fp-bit.c: $(srcdir)/config/fp-bit.c + echo '#define FLOAT' > fp-bit.c + cat $(srcdir)/config/fp-bit.c >> fp-bit.c + +# Build the libraries for pthread and all of the +# different processor models + +MULTILIB_OPTIONS = pthread maix64 + +MULTILIB_DIRNAMES = pthread ppc64 + +MULTILIB_MATCHES = + +LIBGCC = stmp-multilib +INSTALL_LIBGCC = install-multilib + +# Build a shared libgcc library. +SHLIB_EXT = .a +SHLIB_LINK = $(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) -shared -nodefaultlibs \ + -Wl,-bE:@shlib_map_file@ -o @multilib_dir@/shr.o \ + @multilib_flags@ @shlib_objs@ -lc \ + `case @shlib_base_name@ in \ + *pthread*) echo -L/usr/lib/threads -lpthreads -lc_r /usr/lib/libc.a ;; \ + *) echo -lc ;; esac` ; \ + rm -f tmp-@shlib_base_name@.a ; \ + $(AR_CREATE_FOR_TARGET) tmp-@shlib_base_name@.a @multilib_dir@/shr.o ; \ + mv tmp-@shlib_base_name@.a @shlib_base_name@.a ; \ + rm -f @multilib_dir@/shr.o +# $(slibdir) double quoted to protect it from expansion while building +# libgcc.mk. We want this delayed until actual install time. +SHLIB_INSTALL = $(INSTALL_DATA) @shlib_base_name@.a $$(DESTDIR)$$(slibdir)/ +SHLIB_LIBS = -lc `case @shlib_base_name@ in *pthread*) echo -lpthread ;; esac` +SHLIB_MKMAP = $(srcdir)/mkmap-flat.awk +SHLIB_MAPFILES = $(srcdir)/libgcc-std.ver +SHLIB_NM_FLAGS = -Bpg -X32_64 + +# Either 32-bit and 64-bit objects in archives. +AR_FLAGS_FOR_TARGET = -X32_64 + +# Compile Ada files with minimal-toc. The primary focus is gnatlib, so +# that the library does not use nearly the entire TOC of applications +# until gnatlib is built as a shared library on AIX. Compiling the +# compiler with -mminimal-toc does not cause any harm. +T_ADAFLAGS = -mminimal-toc diff --git a/contrib/gcc/config/rs6000/t-darwin b/contrib/gcc/config/rs6000/t-darwin index c9c392e..7aca023 100644 --- a/contrib/gcc/config/rs6000/t-darwin +++ b/contrib/gcc/config/rs6000/t-darwin @@ -1,33 +1,2 @@ -# Library code must include trampoline support +# Library code must include trampoline support. LIB2FUNCS_EXTRA = $(srcdir)/config/rs6000/darwin-tramp.asm - -# We want fine grained libraries, so use the new code to build the -# floating point emulation libraries. -FPBIT = fp-bit.c -DPBIT = dp-bit.c - -dp-bit.c: $(srcdir)/config/fp-bit.c - cat $(srcdir)/config/fp-bit.c > dp-bit.c - -fp-bit.c: $(srcdir)/config/fp-bit.c - echo '#define FLOAT' > fp-bit.c - cat $(srcdir)/config/fp-bit.c >> fp-bit.c - -darwin.o: $(srcdir)/config/darwin.c $(CONFIG_H) $(SYSTEM_H) $(RTL_BASE_H) \ - $(REGS_H) hard-reg-set.h insn-config.h conditions.h output.h \ - insn-attr.h flags.h $(TREE_H) $(EXPR_H) reload.h \ - function.h $(GGC_H) $(TM_P_H) - $(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $< - -darwin-c.o: $(srcdir)/config/darwin-c.c $(CONFIG_H) $(SYSTEM_H) \ - $(TREE_H) $(C_TREE_H) c-lex.h c-pragma.h toplev.h cpplib.h \ - $(TM_P_H) - $(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $< - -# Build the libraries for both hard and soft floating point - -MULTILIB_OPTIONS = msoft-float -MULTILIB_DIRNAMES = soft-float - -LIBGCC = stmp-multilib -INSTALL_LIBGCC = install-multilib diff --git a/contrib/gcc/config/rs6000/t-linux64 b/contrib/gcc/config/rs6000/t-linux64 index 48b6150..af7b44b 100644 --- a/contrib/gcc/config/rs6000/t-linux64 +++ b/contrib/gcc/config/rs6000/t-linux64 @@ -5,6 +5,9 @@ TARGET_LIBGCC2_CFLAGS = EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o \ crtsavres.o +# These functions are needed for soft-float on powerpc64-linux. +LIB2FUNCS_EXTRA = $(srcdir)/config/rs6000/ppc64-fp.c + # ld provides these functions as needed. crtsavres.S: echo >crtsavres.S diff --git a/contrib/gcc/config/rs6000/t-netbsd b/contrib/gcc/config/rs6000/t-netbsd new file mode 100644 index 0000000..0cb08e7 --- /dev/null +++ b/contrib/gcc/config/rs6000/t-netbsd @@ -0,0 +1,42 @@ +# Support for NetBSD PowerPC ELF targets (SVR4 ABI). + +LIB2FUNCS_EXTRA = tramp.S + +tramp.S: $(srcdir)/config/rs6000/tramp.asm + cat $(srcdir)/config/rs6000/tramp.asm > tramp.S + +crtsavres.S: $(srcdir)/config/rs6000/crtsavres.asm + cat $(srcdir)/config/rs6000/crtsavres.asm >crtsavres.S + +EXTRA_PARTS += crtsavres$(objext) + +# It is important that crtbegin.o, etc., aren't surprised by stuff in .sdata. +CRTSTUFF_T_CFLAGS += -msdata=none +CRTSTUFF_T_CFLAGS_S += -msdata=none + +# Switch synonyms +MULTILIB_MATCHES_FLOAT = msoft-float=mcpu?401 \ + msoft-float=mcpu?403 \ + msoft-float=mcpu?405 \ + msoft-float=mcpu?ec603e \ + msoft-float=mcpu?801 \ + msoft-float=mcpu?821 \ + msoft-float=mcpu?823 \ + msoft-float=mcpu?860 + +MULTILIB_OPTIONS = msoft-float +MULTILIB_DIRNAMES = soft-float +MULTILIB_EXTRA_OPTS = fPIC mstrict-align +MULTILIB_EXCEPTIONS = + +MULTILIB_MATCHES = ${MULTILIB_MATCHES_FLOAT} + +LIBGCC = stmp-multilib +INSTALL_LIBGCC = install-multilib +EXTRA_MULTILIB_PARTS = crtbegin$(objext) crtend$(objext) \ + crtbeginS$(objext) crtendS$(objext) crtbeginT$(objext) \ + crtsavres$(objext) + +$(T)crtsavres$(objext): crtsavres.S + $(GCC_FOR_TARGET) $(CRTSTUFF_CFLAGS) $(CRTSTUFF_T_CFLAGS) \ + -c crtsavres.S -o $(T)crtsavres$(objext) diff --git a/contrib/gcc/config/rs6000/t-ppccomm b/contrib/gcc/config/rs6000/t-ppccomm index 7570af4..f4fcdce 100644 --- a/contrib/gcc/config/rs6000/t-ppccomm +++ b/contrib/gcc/config/rs6000/t-ppccomm @@ -27,6 +27,7 @@ tramp.S: $(srcdir)/config/rs6000/tramp.asm # Switch synonyms MULTILIB_MATCHES_FLOAT = msoft-float=mcpu?401 \ msoft-float=mcpu?403 \ + msoft-float=mcpu?405 \ msoft-float=mcpu?ec603e \ msoft-float=mcpu?801 \ msoft-float=mcpu?821 \ diff --git a/contrib/gcc/config/rs6000/t-ppcendian b/contrib/gcc/config/rs6000/t-ppcendian new file mode 100644 index 0000000..b6252ee --- /dev/null +++ b/contrib/gcc/config/rs6000/t-ppcendian @@ -0,0 +1,12 @@ +# Multilibs for powerpc embedded ELF targets with altivec. + +MULTILIB_OPTIONS = msoft-float \ + mlittle/mbig + +MULTILIB_DIRNAMES = nof \ + le be + + +MULTILIB_MATCHES = ${MULTILIB_MATCHES_FLOAT} \ + ${MULTILIB_MATCHES_ENDIAN} \ + ${MULTILIB_MATCHES_SYSV} diff --git a/contrib/gcc/config/rs6000/t-rs6000-c-rule b/contrib/gcc/config/rs6000/t-rs6000-c-rule new file mode 100644 index 0000000..a768fb5 --- /dev/null +++ b/contrib/gcc/config/rs6000/t-rs6000-c-rule @@ -0,0 +1,4 @@ +rs6000-c.o: $(srcdir)/config/rs6000/rs6000-c.c \ + $(srcdir)/config/rs6000/rs6000-protos.h \ + $(CONFIG_H) $(SYSTEM_H) $(TREE_H) $(CPPLIB_H) $(TM_P_H) c-pragma.h errors.h + $(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $< $(OUTPUT_OPTION) diff --git a/contrib/gcc/config/rs6000/vxppc.h b/contrib/gcc/config/rs6000/vxppc.h index b13f6f5..91250a6 100644 --- a/contrib/gcc/config/rs6000/vxppc.h +++ b/contrib/gcc/config/rs6000/vxppc.h @@ -39,17 +39,18 @@ Boston, MA 02111-1307, USA. */ #undef LINK_OS_DEFAULT_SPEC #define LINK_OS_DEFAULT_SPEC "%(link_os_vxworks)" -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "\ --D__vxworks -D__vxworks__ -Asystem=vxworks -Asystem=embedded \ --Acpu=powerpc -Amachine=powerpc" - -/* Don't define _LITTLE_ENDIAN or _BIG_ENDIAN */ -#undef CPP_ENDIAN_BIG_SPEC -#define CPP_ENDIAN_BIG_SPEC "-D__BIG_ENDIAN__ -Amachine=bigendian" - -#undef CPP_ENDIAN_LITTLE_SPEC -#define CPP_ENDIAN_LITTLE_SPEC "-D__LITTLE_ENDIAN__ -Amachine=littleendian" +#undef TARGET_OS_CPP_BUILTINS +#define TARGET_OS_CPP_BUILTINS() \ + do \ + { \ + builtin_define ("__vxworks"); \ + builtin_define ("__vxworks__"); \ + builtin_assert ("system=vxworks"); \ + builtin_assert ("system=embedded"); \ + builtin_assert ("cpu=powerpc"); \ + builtin_assert ("machine=powerpc"); \ + } \ + while (0) /* We use stabs-in-elf for debugging */ #undef PREFERRED_DEBUGGING_TYPE diff --git a/contrib/gcc/config/rs6000/windiss.h b/contrib/gcc/config/rs6000/windiss.h new file mode 100644 index 0000000..7aacb23 --- /dev/null +++ b/contrib/gcc/config/rs6000/windiss.h @@ -0,0 +1,47 @@ +/* Support for GCC on PowerPC using WindISS simulator. + Copyright (C) 2002 Free Software Foundation, Inc. + Contributed by CodeSourcery, LLC. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#undef TARGET_VERSION +#define TARGET_VERSION fprintf (stderr, " (PowerPC WindISS)"); + +#undef LIB_DEFAULT_SPEC +#define LIB_DEFAULT_SPEC "%(lib_windiss)" + +#undef STARTFILE_DEFAULT_SPEC +#define STARTFILE_DEFAULT_SPEC "%(startfile_windiss)" + +#undef ENDFILE_DEFAULT_SPEC +#define ENDFILE_DEFAULT_SPEC "%(endfile_windiss)" + +#undef LINK_START_DEFAULT_SPEC +#define LINK_START_DEFAULT_SPEC "%(link_start_windiss)" + +#undef LINK_OS_DEFAULT_SPEC +#define LINK_OS_DEFAULT_SPEC "%(link_os_windiss)" + +#undef CRTSAVRES_DEFAULT_SPEC +#define CRTSAVRES_DEFAULT_SPEC "" + +#undef WCHAR_TYPE +#define WCHAR_TYPE "short unsigned int" + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE 16 diff --git a/contrib/gcc/config/rs6000/xcoff.h b/contrib/gcc/config/rs6000/xcoff.h index a61061a..21d74a9 100644 --- a/contrib/gcc/config/rs6000/xcoff.h +++ b/contrib/gcc/config/rs6000/xcoff.h @@ -23,7 +23,7 @@ Boston, MA 02111-1307, USA. */ #define TARGET_OBJECT_FORMAT OBJECT_XCOFF /* The RS/6000 uses the XCOFF format. */ -#define XCOFF_DEBUGGING_INFO +#define XCOFF_DEBUGGING_INFO 1 /* Define if the object format being used is COFF or a superset. */ #define OBJECT_FORMAT_COFF @@ -135,37 +135,7 @@ toc_section () \ #define READONLY_DATA_SECTION read_only_data_section -/* Select the section for an initialized data object. - - On the RS/6000, we have a special section for all variables except those - that are static. */ - -#define SELECT_SECTION(EXP,RELOC,ALIGN) \ -{ \ - if ((TREE_CODE (EXP) == STRING_CST \ - && ! flag_writable_strings) \ - || (TREE_CODE_CLASS (TREE_CODE (EXP)) == 'd' \ - && TREE_READONLY (EXP) && ! TREE_THIS_VOLATILE (EXP) \ - && DECL_INITIAL (EXP) \ - && (DECL_INITIAL (EXP) == error_mark_node \ - || TREE_CONSTANT (DECL_INITIAL (EXP))) \ - && ! (RELOC))) \ - { \ - if (TREE_PUBLIC (EXP)) \ - read_only_data_section (); \ - else \ - read_only_private_data_section (); \ - } \ - else \ - { \ - if (TREE_PUBLIC (EXP)) \ - data_section (); \ - else \ - private_data_section (); \ - } \ -} - -/* Return non-zero if this entry is to be written into the constant +/* Return nonzero if this entry is to be written into the constant pool in a special way. We do so if this is a SYMBOL_REF, LABEL_REF or a CONST containing one of them. If -mfp-in-toc (the default), we also do this for floating-point constants. We actually can only @@ -189,29 +159,14 @@ toc_section () \ || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ && ! TARGET_NO_FP_IN_TOC))))) -/* Select section for constant in constant pool. - - On RS/6000, all constants are in the private read-only data area. - However, if this is being placed in the TOC it must be output as a - toc entry. */ - -#define SELECT_RTX_SECTION(MODE, X, ALIGN) \ -{ if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ - toc_section (); \ - else \ - read_only_private_data_section (); \ -} - -/* If we are referencing a function that is static or is known to be - in this file, make the SYMBOL_REF special. We can use this to indicate - that we can branch to this function without emitting a no-op after the - call. Do not set this flag if the function is weakly defined. */ - -#define ENCODE_SECTION_INFO(DECL) \ - if (TREE_CODE (DECL) == FUNCTION_DECL \ - && !TREE_PUBLIC (DECL) \ - && !DECL_WEAK (DECL)) \ - SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; +#define TARGET_ASM_GLOBALIZE_LABEL rs6000_xcoff_asm_globalize_label +#define TARGET_ASM_NAMED_SECTION rs6000_xcoff_asm_named_section +#define TARGET_ASM_SELECT_SECTION rs6000_xcoff_select_section +#define TARGET_ASM_SELECT_RTX_SECTION rs6000_xcoff_select_rtx_section +#define TARGET_ASM_UNIQUE_SECTION rs6000_xcoff_unique_section +#define TARGET_ENCODE_SECTION_INFO rs6000_xcoff_encode_section_info +#define TARGET_STRIP_NAME_ENCODING rs6000_xcoff_strip_name_encoding +#define TARGET_SECTION_TYPE_FLAGS rs6000_xcoff_section_type_flags /* FP save and restore routines. */ #define SAVE_FP_PREFIX "._savef" @@ -232,13 +187,8 @@ toc_section () \ /* This outputs NAME to FILE up to the first null or '['. */ -#define RS6000_OUTPUT_BASENAME(FILE, NAME) \ - { \ - const char *_p; \ - \ - STRIP_NAME_ENCODING (_p, (NAME)); \ - assemble_name ((FILE), _p); \ - } +#define RS6000_OUTPUT_BASENAME(FILE, NAME) \ + assemble_name ((FILE), (*targetm.strip_name_encoding) (NAME)) /* This is how to output the definition of a user-level label named NAME, such as the label on a static function or variable NAME. */ @@ -249,31 +199,8 @@ toc_section () \ /* This is how to output a command to make the user-level label named NAME defined for reference from other files. */ -#define ASM_GLOBALIZE_LABEL(FILE,NAME) \ - do { fputs ("\t.globl ", FILE); \ - RS6000_OUTPUT_BASENAME (FILE, NAME); putc ('\n', FILE);} while (0) - -/* Remove any trailing [DS] or the like from the symbol name. */ - -#define STRIP_NAME_ENCODING(VAR,NAME) \ - do \ - { \ - const char *_name = (NAME); \ - size_t _len; \ - if (*_name == '*') \ - _name++; \ - _len = strlen (_name); \ - if (_name[_len - 1] != ']') \ - (VAR) = _name; \ - else \ - { \ - char *_new_name = (char *) alloca (_len + 1); \ - strcpy (_new_name, _name); \ - _new_name[_len - 4] = '\0'; \ - (VAR) = _new_name; \ - } \ - } \ - while (0) +/* Globalizing directive for a label. */ +#define GLOBAL_ASM_OP "\t.globl " /* Output at beginning of assembler file. @@ -296,7 +223,9 @@ toc_section () \ rs6000_gen_section_name (&xcoff_read_only_section_name, \ main_input_filename, ".ro_"); \ \ - fprintf (FILE, "\t.file\t\"%s\"\n", main_input_filename); \ + fputs ("\t.file\t", FILE); \ + output_quoted_string (FILE, main_input_filename); \ + fputc ('\n', FILE); \ if (TARGET_64BIT) \ fputs ("\t.machine\t\"ppc64\"\n", FILE); \ toc_section (); \ @@ -337,7 +266,7 @@ toc_section () \ #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ { rtx sym_ref = XEXP (DECL_RTL (DECL), 0); \ - if (!DECL_WEAK (DECL)) \ + if ((*targetm.binds_local_p) (DECL)) \ SYMBOL_REF_FLAG (sym_ref) = 1; \ if (TREE_PUBLIC (DECL)) \ { \ @@ -367,7 +296,11 @@ toc_section () \ putc ('.', FILE); \ RS6000_OUTPUT_BASENAME (FILE, NAME); \ fputs (":\n", FILE); \ - if (write_symbols == XCOFF_DEBUG) \ + if (write_symbols == XCOFF_DEBUG \ + /* When called before targetm.asm_out.output_mi_thunk, \ + we won't be emitting the rest of the debug info that \ + goes along with this, leading to assembler errors. */ \ + && !(current_function_is_thunk && !no_new_pseudos)) \ xcoffout_declare_function (FILE, DECL, NAME); \ } @@ -379,17 +312,17 @@ toc_section () \ /* This says how to output an external. */ #undef ASM_OUTPUT_EXTERNAL -#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \ -{ rtx _symref = XEXP (DECL_RTL (DECL), 0); \ - if ((TREE_CODE (DECL) == VAR_DECL \ - || TREE_CODE (DECL) == FUNCTION_DECL) \ - && (NAME)[strlen (NAME) - 1] != ']') \ - { \ - char *_name = (char *) permalloc (strlen (XSTR (_symref, 0)) + 5); \ - strcpy (_name, XSTR (_symref, 0)); \ - strcat (_name, TREE_CODE (DECL) == FUNCTION_DECL ? "[DS]" : "[RW]"); \ - XSTR (_symref, 0) = _name; \ - } \ +#define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \ +{ rtx _symref = XEXP (DECL_RTL (DECL), 0); \ + if ((TREE_CODE (DECL) == VAR_DECL \ + || TREE_CODE (DECL) == FUNCTION_DECL) \ + && (NAME)[strlen (NAME) - 1] != ']') \ + { \ + XSTR (_symref, 0) = concat (XSTR (_symref, 0), \ + (TREE_CODE (DECL) == FUNCTION_DECL \ + ? "[DS]" : "[RW]"), \ + NULL); \ + } \ } /* This is how to output an internal numbered label where @@ -426,19 +359,26 @@ toc_section () \ /* This is how to advance the location counter by SIZE bytes. */ +#define SKIP_ASM_OP "\t.space " + #define ASM_OUTPUT_SKIP(FILE,SIZE) \ - fprintf (FILE, "\t.space %d\n", (SIZE)) + fprintf (FILE, "%s%u\n", SKIP_ASM_OP, (SIZE)) /* This says how to output an assembler line to define a global common symbol. */ -#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGNMENT) \ - do { fputs ("\t.comm ", (FILE)); \ +#define COMMON_ASM_OP "\t.comm " + +#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ + do { fputs (COMMON_ASM_OP, (FILE)); \ RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ - if ( (SIZE) > 4) \ - fprintf ((FILE), ",%d,3\n", (SIZE)); \ + if ((ALIGN) > 32) \ + fprintf ((FILE), ",%u,%u\n", (SIZE), \ + exact_log2 ((ALIGN) / BITS_PER_UNIT)); \ + else if ((SIZE) > 4) \ + fprintf ((FILE), ",%u,3\n", (SIZE)); \ else \ - fprintf ((FILE), ",%d\n", (SIZE)); \ + fprintf ((FILE), ",%u\n", (SIZE)); \ } while (0) /* This says how to output an assembler line @@ -447,10 +387,12 @@ toc_section () \ alignment after preceding TOC section if it was aligned for 64-bit mode. */ +#define LOCAL_COMMON_ASM_OP "\t.lcomm " + #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ - do { fputs ("\t.lcomm ", (FILE)); \ + do { fputs (LOCAL_COMMON_ASM_OP, (FILE)); \ RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ - fprintf ((FILE), ",%d,%s\n", (TARGET_32BIT ? (SIZE) : (ROUNDED)), \ + fprintf ((FILE), ",%u,%s\n", (TARGET_32BIT ? (SIZE) : (ROUNDED)), \ xcoff_bss_section_name); \ } while (0) @@ -476,25 +418,6 @@ toc_section () \ Align entire section to BIGGEST_ALIGNMENT. */ #define DATA_SECTION_ASM_OP "\t.csect .data[RW],3" -/* Define unique section name -- functions only. */ -#define UNIQUE_SECTION(DECL,RELOC) \ - do { \ - int len; \ - const char *name; \ - char *string; \ - \ - if (TREE_CODE (DECL) == FUNCTION_DECL) { \ - name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (DECL)); \ - len = strlen (name) + 5; \ - string = alloca (len + 1); \ - sprintf (string, ".%s[PR]", name); \ - DECL_SECTION_NAME (DECL) = build_string (len, string); \ - } \ - } while (0) - -/* Switch into a generic section. */ -#define TARGET_ASM_NAMED_SECTION xcoff_asm_named_section - /* Define the name of the section to use for the EH language specific data areas (.gcc_except_table on most other systems). */ #define TARGET_ASM_EXCEPTION_SECTION data_section |
