This commit was generated by cvs2svn to compensate for changes in r161651,

which included commits to RCS files with non-trunk default branches.

8 files changed, 91 insertions, 186 deletions

diff --git a/contrib/gcc/config/rs6000/aix51.h b/contrib/gcc/config/rs6000/aix51.h
index 278b6a4..863b97f 100644
--- a/contrib/gcc/config/rs6000/aix51.h
+++ b/contrib/gcc/config/rs6000/aix51.h
@@ -197,7 +197,3 @@ do {									\
 #undef LD_INIT_SWITCH
 #define LD_INIT_SWITCH "-binitfini"
 
-/* AIX 5.1 has the float and long double forms of math functions.  */
-#undef TARGET_C99_FUNCTIONS
-#define TARGET_C99_FUNCTIONS  1
-
diff --git a/contrib/gcc/config/rs6000/host-darwin.c b/contrib/gcc/config/rs6000/host-darwin.c
index 7e80556..d04270c 100644
--- a/contrib/gcc/config/rs6000/host-darwin.c
+++ b/contrib/gcc/config/rs6000/host-darwin.c
@@ -1,5 +1,5 @@
 /* Darwin/powerpc host-specific hook definitions.
-   Copyright (C) 2003 Free Software Foundation, Inc.
+   Copyright (C) 2003, 2004 Free Software Foundation, Inc.
 
    This file is part of GCC.
 
@@ -137,22 +137,18 @@ darwin_rs6000_extra_signals (void)
     fatal_error ("While setting up signal handler: %m");
 }
 
-static void * darwin_rs6000_gt_pch_get_address (size_t);
-static bool darwin_rs6000_gt_pch_use_address (void *, size_t);
-
 #undef HOST_HOOKS_GT_PCH_GET_ADDRESS
 #define HOST_HOOKS_GT_PCH_GET_ADDRESS darwin_rs6000_gt_pch_get_address
 #undef HOST_HOOKS_GT_PCH_USE_ADDRESS
 #define HOST_HOOKS_GT_PCH_USE_ADDRESS darwin_rs6000_gt_pch_use_address
 
-
 /* Yes, this is really supposed to work.  */
 static char pch_address_space[1024*1024*1024] __attribute__((aligned (4096)));
 
 /* Return the address of the PCH address space, if the PCH will fit in it.  */
 
 static void *
-darwin_rs6000_gt_pch_get_address (size_t sz)
+darwin_rs6000_gt_pch_get_address (size_t sz, int fd ATTRIBUTE_UNUSED)
 {
   if (sz <= sizeof (pch_address_space))
     return pch_address_space;
@@ -163,18 +159,19 @@ darwin_rs6000_gt_pch_get_address (size_t sz)
 /* Check ADDR and SZ for validity, and deallocate (using munmap) that part of
    pch_address_space beyond SZ.  */
 
-static bool
-darwin_rs6000_gt_pch_use_address (void *addr, size_t sz)
+static int
+darwin_rs6000_gt_pch_use_address (void *addr, size_t sz, int fd, size_t off)
 {
   const size_t pagesize = getpagesize();
-  bool result;
+  void *mmap_result;
+  int ret;
 
   if ((size_t)pch_address_space % pagesize != 0
       || sizeof (pch_address_space) % pagesize != 0)
     abort ();
   
-  result = (addr == pch_address_space && sz <= sizeof (pch_address_space));
-  if (! result)
+  ret = (addr == pch_address_space && sz <= sizeof (pch_address_space));
+  if (! ret)
     sz = 0;
 
   /* Round the size to a whole page size.  Normally this is a no-op.  */
@@ -183,7 +180,22 @@ darwin_rs6000_gt_pch_use_address (void *addr, size_t sz)
   if (munmap (pch_address_space + sz, sizeof (pch_address_space) - sz) != 0)
     fatal_error ("couldn't unmap pch_address_space: %m\n");
 
-  return result;
+  if (ret)
+    {
+      mmap_result = mmap (addr, sz,
+			  PROT_READ | PROT_WRITE, MAP_PRIVATE | MAP_FIXED,
+			  fd, off);
+
+      /* The file might not be mmap-able.  */
+      ret = mmap_result != (void *) MAP_FAILED;
+
+      /* Sanity check for broken MAP_FIXED.  */
+      if (ret && mmap_result != addr)
+	abort ();
+    }
+
+  return ret;
 }
+
 
 const struct host_hooks host_hooks = HOST_HOOKS_INITIALIZER;
diff --git a/contrib/gcc/config/rs6000/linux64.h b/contrib/gcc/config/rs6000/linux64.h
index 013e23a..84e13a1 100644
--- a/contrib/gcc/config/rs6000/linux64.h
+++ b/contrib/gcc/config/rs6000/linux64.h
@@ -244,6 +244,12 @@
    ? rs6000_special_round_type_align (STRUCT, COMPUTED, SPECIFIED)	\
    : MAX ((COMPUTED), (SPECIFIED)))
 
+/* Use the default for compiling target libs.  */
+#ifdef IN_TARGET_LIBS
+#undef TARGET_ALIGN_NATURAL
+#define TARGET_ALIGN_NATURAL 1
+#endif
+
 /* Indicate that jump tables go in the text section.  */
 #undef  JUMP_TABLES_IN_TEXT_SECTION
 #define JUMP_TABLES_IN_TEXT_SECTION TARGET_64BIT
diff --git a/contrib/gcc/config/rs6000/rs6000-protos.h b/contrib/gcc/config/rs6000/rs6000-protos.h
index 3d17162..3303ecd 100644
--- a/contrib/gcc/config/rs6000/rs6000-protos.h
+++ b/contrib/gcc/config/rs6000/rs6000-protos.h
@@ -105,7 +105,7 @@ extern int registers_ok_for_quad_peep (rtx, rtx);
 extern int addrs_ok_for_quad_peep (rtx, rtx);
 extern bool gpr_or_gpr_p (rtx, rtx);
 extern enum reg_class secondary_reload_class (enum reg_class,
-					      enum machine_mode, rtx, int);
+					      enum machine_mode, rtx);
 extern int ccr_bit (rtx, int);
 extern int extract_MB (rtx);
 extern int extract_ME (rtx);
diff --git a/contrib/gcc/config/rs6000/rs6000.c b/contrib/gcc/config/rs6000/rs6000.c
index 1ffd4da..ea35843 100644
--- a/contrib/gcc/config/rs6000/rs6000.c
+++ b/contrib/gcc/config/rs6000/rs6000.c
@@ -2497,43 +2497,6 @@ word_offset_memref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
   return (off % 4) == 0;
 }
 
-/* Return true if operand is a (MEM (PLUS (REG) (offset))) where offset
-   is not divisible by four.  */
-
-int
-invalid_gpr_mem (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
-  rtx addr;
-  long off;
-
-  if (GET_CODE (op) != MEM)
-    return 0;
-
-  addr = XEXP (op, 0);
-  if (GET_CODE (addr) != PLUS
-      || GET_CODE (XEXP (addr, 0)) != REG
-      || GET_CODE (XEXP (addr, 1)) != CONST_INT)
-    return 0;
-
-  off = INTVAL (XEXP (addr, 1));
-  return (off & 3) != 0;
-}
-
-/* Return true if operand is a hard register that can be used as a base
-   register.  */
-
-int
-base_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
-{
-  unsigned int regno;
-
-  if (!REG_P (op))
-    return 0;
-
-  regno = REGNO (op);
-  return regno != 0 && regno <= 31;
-}
-
 /* Return true if either operand is a general purpose register.  */
 
 bool
@@ -2658,16 +2621,18 @@ legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
 
     case DFmode:
     case DImode:
-      /* Both DFmode and DImode may end up in gprs.  If gprs are 32-bit,
-	 then we need to load/store at both offset and offset+4.  */
-      if (!TARGET_POWERPC64)
+      if (mode == DFmode || !TARGET_POWERPC64)
 	extra = 4;
+      else if (offset & 3)
+	return false;
       break;
 
     case TFmode:
     case TImode:
-      if (!TARGET_POWERPC64)
+      if (mode == TFmode || !TARGET_POWERPC64)
 	extra = 12;
+      else if (offset & 3)
+	return false;
       else
 	extra = 8;
       break;
@@ -2989,7 +2954,7 @@ rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
       rtx r3, got, tga, tmp1, tmp2, eqv;
 
       if (TARGET_64BIT)
-	got = gen_rtx_REG (Pmode, TOC_REGISTER);
+	got = gen_rtx_REG (Pmode, 2);
       else
 	{
 	  if (flag_pic == 1)
@@ -3206,6 +3171,26 @@ rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
       return x;
     }
 #endif
+
+  /* Force ld/std non-word aligned offset into base register by wrapping
+     in offset 0.  */
+  if (GET_CODE (x) == PLUS
+      && GET_CODE (XEXP (x, 0)) == REG
+      && REGNO (XEXP (x, 0)) < 32
+      && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
+      && GET_CODE (XEXP (x, 1)) == CONST_INT
+      && (INTVAL (XEXP (x, 1)) & 3) != 0
+      && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
+      && TARGET_POWERPC64)
+    {
+      x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
+      push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
+		   BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
+		   opnum, (enum reload_type) type);
+      *win = 1;
+      return x;
+    }
+
   if (GET_CODE (x) == PLUS
       && GET_CODE (XEXP (x, 0)) == REG
       && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
@@ -3240,6 +3225,7 @@ rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
       *win = 1;
       return x;
     }
+
 #if TARGET_MACHO
   if (GET_CODE (x) == SYMBOL_REF
       && DEFAULT_ABI == ABI_DARWIN
@@ -3269,6 +3255,7 @@ rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
       return x;
     }
 #endif
+
   if (TARGET_TOC
       && constant_pool_expr_p (x)
       && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
@@ -4369,9 +4356,10 @@ function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
   if (mode == VOIDmode)
     {
       if (abi == ABI_V4
-	  && cum->nargs_prototype < 0
 	  && (cum->call_cookie & CALL_LIBCALL) == 0
-	  && (cum->prototype || TARGET_NO_PROTOTYPE))
+	  && (cum->stdarg
+	      || (cum->nargs_prototype < 0
+		  && (cum->prototype || TARGET_NO_PROTOTYPE))))
 	{
 	  /* For the SPE, we need to crxor CR6 always.  */
 	  if (TARGET_SPE_ABI)
@@ -7856,7 +7844,7 @@ expand_block_move (rtx operands[])
 	  mode = SImode;
 	  gen_func.mov = gen_movsi;
 	}
-      else if (bytes == 2 && (align >= 2 || ! STRICT_ALIGNMENT))
+      else if (bytes >= 2 && (align >= 2 || ! STRICT_ALIGNMENT))
 	{			/* move 2 bytes */
 	  move_bytes = 2;
 	  mode = HImode;
@@ -8725,14 +8713,12 @@ addrs_ok_for_quad_peep (rtx addr1, rtx addr2)
 
 /* Return the register class of a scratch register needed to copy IN into
    or out of a register in CLASS in MODE.  If it can be done directly,
-   NO_REGS is returned.  INP is nonzero if we are loading the reg, zero
-   for storing.  */
+   NO_REGS is returned.  */
 
 enum reg_class
 secondary_reload_class (enum reg_class class,
 			enum machine_mode mode,
-			rtx in,
-			int inp)
+			rtx in)
 {
   int regno;
 
@@ -8757,14 +8743,6 @@ secondary_reload_class (enum reg_class class,
         return BASE_REGS;
     }
 
-  /* A 64-bit gpr load or store using an offset that isn't a multiple of
-     four needs a secondary reload.  */
-  if (TARGET_POWERPC64
-      && GET_MODE_UNIT_SIZE (mode) >= 8
-      && (!inp || class != BASE_REGS)
-      && invalid_gpr_mem (in, mode))
-    return BASE_REGS;
-
   if (GET_CODE (in) == REG)
     {
       regno = REGNO (in);
@@ -11620,6 +11598,8 @@ uses_TOC (void)
 rtx
 create_TOC_reference (rtx symbol) 
 {
+  if (no_new_pseudos)
+    regs_ever_live[TOC_REGISTER] = 1;
   return gen_rtx_PLUS (Pmode, 
 	   gen_rtx_REG (Pmode, TOC_REGISTER),
 	     gen_rtx_CONST (Pmode, 
diff --git a/contrib/gcc/config/rs6000/rs6000.h b/contrib/gcc/config/rs6000/rs6000.h
index f1ad896..01a97da 100644
--- a/contrib/gcc/config/rs6000/rs6000.h
+++ b/contrib/gcc/config/rs6000/rs6000.h
@@ -1492,11 +1492,8 @@ enum reg_class
    or out of a register in CLASS in MODE.  If it can be done directly,
    NO_REGS is returned.  */
 
-#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, IN) \
-  secondary_reload_class (CLASS, MODE, IN, 1)
-
-#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, IN) \
-  secondary_reload_class (CLASS, MODE, IN, 0)
+#define SECONDARY_RELOAD_CLASS(CLASS, MODE, IN) \
+  secondary_reload_class (CLASS, MODE, IN)
 
 /* If we are copying between FP or AltiVec registers and anything
    else, we need a memory location.  */
@@ -2671,8 +2668,6 @@ extern char rs6000_reg_names[][8];	/* register names (0 vs. %r0).  */
   {"lwa_operand", {SUBREG, MEM, REG}},					   \
   {"volatile_mem_operand", {MEM}},					   \
   {"offsettable_mem_operand", {MEM}},					   \
-  {"invalid_gpr_mem", {MEM}},						   \
-  {"base_reg_operand", {REG}},						   \
   {"mem_or_easy_const_operand", {SUBREG, MEM, CONST_DOUBLE}},		   \
   {"add_operand", {SUBREG, REG, CONST_INT}},				   \
   {"non_add_cint_operand", {CONST_INT}},				   \
diff --git a/contrib/gcc/config/rs6000/rs6000.md b/contrib/gcc/config/rs6000/rs6000.md
index 3b062ce..0e242d4 100644
--- a/contrib/gcc/config/rs6000/rs6000.md
+++ b/contrib/gcc/config/rs6000/rs6000.md
@@ -5236,7 +5236,7 @@
    (set (match_dup 0) (plus:DI (match_dup 0)
 			       (const_int 2047)))
    (set (match_dup 4) (compare:CCUNS (match_dup 3)
-				     (const_int 3)))
+				     (const_int 2)))
    (set (match_dup 0) (ior:DI (match_dup 0)
 			      (match_dup 1)))
    (parallel [(set (match_dup 0) (and:DI (match_dup 0)
@@ -7839,8 +7839,8 @@
 }")
 
 (define_insn "*movsf_hardfloat"
-  [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!r,!r")
-	(match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,G,Fn"))]
+  [(set (match_operand:SF 0 "nonimmediate_operand" "=!r,!r,m,f,f,m,!cl,!q,!r,!h,!r,!r")
+	(match_operand:SF 1 "input_operand" "r,m,r,f,m,f,r,r,h,0,G,Fn"))]
   "(gpc_reg_operand (operands[0], SFmode)
    || gpc_reg_operand (operands[1], SFmode))
    && (TARGET_HARD_FLOAT && TARGET_FPRS)"
@@ -7854,10 +7854,11 @@
    mt%0 %1
    mt%0 %1
    mf%1 %0
+   {cror 0,0,0|nop}
    #
    #"
-  [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*")
-   (set_attr "length" "4,4,4,4,4,4,4,4,4,4,8")])
+  [(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*")
+   (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
 
 (define_insn "*movsf_softfloat"
   [(set (match_operand:SF 0 "nonimmediate_operand" "=r,cl,q,r,r,m,r,r,r,r,r,*h")
@@ -8114,67 +8115,26 @@
 ; ld/std require word-aligned displacements -> 'Y' constraint.
 ; List Y->r and r->Y before r->r for reload.
 (define_insn "*movdf_hardfloat64"
-  [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,b,!r,f,f,m,!cl,!r,!r,!r,!r")
-	(match_operand:DF 1 "input_operand" "r,Y,m,r,f,m,f,r,h,G,H,F"))]
+  [(set (match_operand:DF 0 "nonimmediate_operand" "=Y,r,!r,f,f,m,!cl,!r,!h,!r,!r,!r")
+	(match_operand:DF 1 "input_operand" "r,Y,r,f,m,f,r,h,0,G,H,F"))]
   "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS
    && (gpc_reg_operand (operands[0], DFmode)
        || gpc_reg_operand (operands[1], DFmode))"
   "@
    std%U0%X0 %1,%0
    ld%U1%X1 %0,%1
-   #
    mr %0,%1
    fmr %0,%1
    lfd%U1%X1 %0,%1
    stfd%U0%X0 %1,%0
    mt%0 %1
    mf%1 %0
+   {cror 0,0,0|nop}
    #
    #
    #"
-  [(set_attr "type" "store,load,load,*,fp,fpload,fpstore,mtjmpr,*,*,*,*")
-   (set_attr "length" "4,4,8,4,4,4,4,4,4,8,12,16")])
-
-(define_split
-  [(set (match_operand:DF 0 "base_reg_operand" "")
-	(match_operand:DF 1 "invalid_gpr_mem" ""))]
-  "TARGET_POWERPC64 && no_new_pseudos"
-  [(set (match_dup 2) (match_dup 3))
-   (set (match_dup 0) (match_dup 4))]
-  "
-{
-  operands[2] = gen_rtx_REG (Pmode, REGNO (operands[0]));
-  operands[3] = XEXP (operands[1], 0);
-  operands[4] = replace_equiv_address (operands[1], operands[2]);
-}")
-
-(define_expand "reload_outdf"
-  [(parallel [(match_operand:DF 0 "invalid_gpr_mem" "")
-	      (match_operand:DF 1 "register_operand" "")
-	      (match_operand:DI 2 "register_operand" "=&b")])]
-  "TARGET_POWERPC64"
-{
-  if (!TARGET_64BIT)
-    operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]));
-  emit_move_insn (operands[2], XEXP (operands[0], 0));
-  operands[0] = replace_equiv_address (operands[0], operands[2]);
-  emit_move_insn (operands[0], operands[1]);
-  DONE;
-})
-
-(define_expand "reload_indf"
-  [(parallel [(match_operand:DF 0 "register_operand" "")
-	      (match_operand:DF 1 "invalid_gpr_mem" "")
-	      (match_operand:DI 2 "register_operand" "=&b")])]
-  "TARGET_POWERPC64"
-{
-  if (!TARGET_64BIT)
-    operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]));
-  emit_move_insn (operands[2], XEXP (operands[1], 0));
-  operands[1] = replace_equiv_address (operands[1], operands[2]);
-  emit_move_insn (operands[0], operands[1]);
-  DONE;
-})
+  [(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,*,*,*,*,*")
+   (set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
 
 (define_insn "*movdf_softfloat64"
   [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Y,r,cl,r,r,r,r,*h")
@@ -8191,7 +8151,7 @@
    #
    #
    #
-   nop"
+   {cror 0,0,0|nop}"
   [(set_attr "type" "load,store,*,*,*,*,*,*,*")
    (set_attr "length" "4,4,4,4,4,8,12,16,4")])
 
@@ -8519,15 +8479,14 @@
 }")
 
 (define_insn "*movdi_internal64"
-  [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,b,r,r,r,r,r,??f,f,m,r,*h,*h")
-	(match_operand:DI 1 "input_operand" "r,Y,m,r,I,L,nF,R,f,m,f,*h,r,0"))]
+  [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,r,??f,f,m,r,*h,*h")
+	(match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,R,f,m,f,*h,r,0"))]
   "TARGET_POWERPC64
    && (gpc_reg_operand (operands[0], DImode)
        || gpc_reg_operand (operands[1], DImode))"
   "@
    std%U0%X0 %1,%0
    ld%U1%X1 %0,%1
-   #
    mr %0,%1
    li %0,%1
    lis %0,%v1
@@ -8539,51 +8498,8 @@
    mf%1 %0
    mt%0 %1
    {cror 0,0,0|nop}"
-  [(set_attr "type" "store,load,load,*,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
-   (set_attr "length" "4,4,8,4,4,4,20,4,4,4,4,4,4,4")])
-
-(define_split
-  [(set (match_operand:DI 0 "base_reg_operand" "")
-	(match_operand:DI 1 "invalid_gpr_mem" ""))]
-  "TARGET_POWERPC64 && no_new_pseudos"
-  [(set (match_dup 2) (match_dup 3))
-   (set (match_dup 0) (match_dup 4))]
-  "
-{
-  operands[2] = operands[0];
-  if (!TARGET_64BIT)
-    operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]));
-  operands[3] = XEXP (operands[1], 0);
-  operands[4] = replace_equiv_address (operands[1], operands[2]);
-}")
-
-(define_expand "reload_outdi"
-  [(parallel [(match_operand:DI 0 "invalid_gpr_mem" "")
-              (match_operand:DI 1 "register_operand" "")
-              (match_operand:DI 2 "register_operand" "=&b")])]
-  "TARGET_POWERPC64"
-{
-  if (!TARGET_64BIT)
-    operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]));
-  emit_move_insn (operands[2], XEXP (operands[0], 0));
-  operands[0] = replace_equiv_address (operands[0], operands[2]);
-  emit_move_insn (operands[0], operands[1]);
-  DONE;
-})
-
-(define_expand "reload_indi"
-  [(parallel [(match_operand:DI 0 "register_operand" "")
-	      (match_operand:DI 1 "invalid_gpr_mem" "")
-	      (match_operand:DI 2 "register_operand" "=&b")])]
-  "TARGET_POWERPC64"
-{
-  if (!TARGET_64BIT)
-    operands[2] = gen_rtx_REG (SImode, REGNO (operands[2]));
-  emit_move_insn (operands[2], XEXP (operands[1], 0));
-  operands[1] = replace_equiv_address (operands[1], operands[2]);
-  emit_move_insn (operands[0], operands[1]);
-  DONE;
-})
+  [(set_attr "type" "store,load,*,*,*,*,*,fp,fpload,fpstore,mfjmpr,mtjmpr,*")
+   (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4")])
 
 ;; immediate value valid for a single instruction hiding in a const_double
 (define_insn ""
diff --git a/contrib/gcc/config/rs6000/sysv4.h b/contrib/gcc/config/rs6000/sysv4.h
index 57af869..d367aa8 100644
--- a/contrib/gcc/config/rs6000/sysv4.h
+++ b/contrib/gcc/config/rs6000/sysv4.h
@@ -1,6 +1,6 @@
 /* Target definitions for GNU compiler for PowerPC running System V.4
    Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003,
-   2004 Free Software Foundation, Inc.
+   2004, 2005 Free Software Foundation, Inc.
    Contributed by Cygnus Support.
 
    This file is part of GCC.
@@ -123,8 +123,10 @@ extern const char *rs6000_tls_size_string; /* For -mtls-size= */
   { "no-toc",		 0, N_("no description yet") },			\
   { "toc",		 MASK_MINIMAL_TOC, N_("no description yet") },	\
   { "full-toc",		 MASK_MINIMAL_TOC, N_("no description yet") },	\
-  { "prototype",	 MASK_PROTOTYPE, N_("no description yet") },	\
-  { "no-prototype",	-MASK_PROTOTYPE, N_("no description yet") },	\
+  { "prototype",	 MASK_PROTOTYPE,				\
+    N_("Assume all variable arg functions are prototyped") },		\
+  { "no-prototype",	-MASK_PROTOTYPE,				\
+    N_("Non-prototyped functions might take a variable number of args") }, \
   { "no-traceback",	 0, N_("no description yet") },			\
   { "eabi",		 MASK_EABI, N_("Use EABI") },			\
   { "no-eabi",		-MASK_EABI, N_("Don't use EABI") },		\
@@ -1354,8 +1356,6 @@ ncrtn.o%s"
    ? (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4) \
    : DW_EH_PE_absptr)
 
-#define TARGET_ASM_EXCEPTION_SECTION readonly_data_section
-
 #define DOUBLE_INT_ASM_OP "\t.quad\t"
 
 /* Generate entries in .fixup for relocatable addresses.  */