diff options
| author | peter <peter@FreeBSD.org> | 1996-09-18 05:35:50 +0000 |
|---|---|---|
| committer | peter <peter@FreeBSD.org> | 1996-09-18 05:35:50 +0000 |
| commit | d4691e641ba47cb86eef80f5c879e13f9d961724 (patch) | |
| tree | 5b7ea73fc49c8998d9dc87d3eeff5b96439e6856 /contrib/gcc/config/i386 | |
| download | FreeBSD-src-d4691e641ba47cb86eef80f5c879e13f9d961724.zip FreeBSD-src-d4691e641ba47cb86eef80f5c879e13f9d961724.tar.gz | |
Import of unmodified (but trimmed) gcc-2.7.2. The bigger parts of the
non-i386, non-unix, and generatable files have been trimmed, but can easily
be added in later if needed.
gcc-2.7.2.1 will follow shortly, it's a very small delta to this and it's
handy to have both available for reference for such little cost.
The freebsd-specific changes will then be committed, and once the dust has
settled, the bmakefiles will be committed to use this code.
Diffstat (limited to 'contrib/gcc/config/i386')
100 files changed, 17756 insertions, 0 deletions
diff --git a/contrib/gcc/config/i386/386bsd.h b/contrib/gcc/config/i386/386bsd.h new file mode 100644 index 0000000..cdab5f5 --- /dev/null +++ b/contrib/gcc/config/i386/386bsd.h @@ -0,0 +1,81 @@ +/* Configuration for an i386 running 386BSD as the target machine. */ + +/* This is tested by i386gas.h. */ +#define YES_UNDERSCORES + +#include "i386/gstabs.h" + +/* Get perform_* macros to build libgcc.a. */ +#include "i386/perform.h" + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dunix -Di386 -D____386BSD____ -D__386BSD__ -DBSD_NET2 -Asystem(unix) -Asystem(bsd) -Acpu(i386) -Amachine(i386)" + +/* Like the default, except no -lg. */ +#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}" + +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "int" + +#undef WCHAR_TYPE +#define WCHAR_TYPE "short unsigned int" + +#define WCHAR_UNSIGNED 1 + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE 16 + +/* 386BSD does have atexit. */ + +#define HAVE_ATEXIT + +/* Redefine this to use %eax instead of %edx. */ +#undef FUNCTION_PROFILER +#define FUNCTION_PROFILER(FILE, LABELNO) \ +{ \ + if (flag_pic) \ + { \ + fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%eax\n", \ + LPREFIX, (LABELNO)); \ + fprintf (FILE, "\tcall *mcount@GOT(%%ebx)\n"); \ + } \ + else \ + { \ + fprintf (FILE, "\tmovl $%sP%d,%%eax\n", LPREFIX, (LABELNO)); \ + fprintf (FILE, "\tcall mcount\n"); \ + } \ +} + +/* There are conflicting reports about whether this system uses + a different assembler syntax. wilson@cygnus.com says # is right. */ +#undef COMMENT_BEGIN +#define COMMENT_BEGIN "#" + +#undef ASM_APP_ON +#define ASM_APP_ON "#APP\n" + +#undef ASM_APP_OFF +#define ASM_APP_OFF "#NO_APP\n" + +/* The following macros are stolen from i386v4.h */ +/* These have to be defined to get PIC code correct */ + +/* This is how to output an element of a case-vector that is relative. + This is only used for PIC code. See comments by the `casesi' insn in + i386.md for an explanation of the expression this outputs. */ + +#undef ASM_OUTPUT_ADDR_DIFF_ELT +#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ + fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE) + +/* Indicate that jump tables go in the text section. This is + necessary when compiling PIC code. */ + +#define JUMP_TABLES_IN_TEXT_SECTION + +/* Don't default to pcc-struct-return, because gcc is the only compiler, and + we want to retain compatibility with older gcc versions. */ +#define DEFAULT_PCC_STRUCT_RETURN 0 diff --git a/contrib/gcc/config/i386/aix386.h b/contrib/gcc/config/i386/aix386.h new file mode 100644 index 0000000..e0498e7 --- /dev/null +++ b/contrib/gcc/config/i386/aix386.h @@ -0,0 +1,69 @@ +/* Definitions for IBM PS2 running AIX/386 with gas. + From: Minh Tran-Le <TRANLE@intellicorp.com> + Copyright (C) 1988 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* + * This configuration file is for gcc with gas-2.x and gnu ld 2.x + * with aix ps/2 1.3.x. + */ + +/* Define USE_GAS if you have the new version of gas that can handle + * multiple segments and .section pseudo op. This will allow gcc to + * use the .init section for g++ ctor/dtor. + * + * If you don't have gas then undefined USE_GAS. You will also have + * to use collect if you want to use g++ + */ +#define USE_GAS + +#include "i386/aix386ng.h" + +/* Use crt1.o as a startup file and crtn.o as a closing file. + And add crtbegin.o and crtend.o for ctors and dtors */ + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ + "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}} crtbegin.o%s" +#undef ENDFILE_SPEC +#define ENDFILE_SPEC \ + "crtend.o%s crtn.o%s" + +/* Removed the -K flags because the gnu ld does not handle it */ +#undef LINK_SPEC +#define LINK_SPEC "%{T*} %{z:-lm}" + +/* Define a few machine-specific details of the implementation of + constructors. */ + +#undef INIT_SECTION_ASM_OP +#define INIT_SECTION_ASM_OP ".section .init,\"x\"" + +#define CTOR_LIST_BEGIN \ + asm (INIT_SECTION_ASM_OP); \ + asm ("pushl $0") +#define CTOR_LIST_END CTOR_LIST_BEGIN + +#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ + do { \ + init_section (); \ + fprintf (FILE, "\tpushl $"); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) diff --git a/contrib/gcc/config/i386/aix386ng.h b/contrib/gcc/config/i386/aix386ng.h new file mode 100644 index 0000000..5d09fc3 --- /dev/null +++ b/contrib/gcc/config/i386/aix386ng.h @@ -0,0 +1,143 @@ +/* Definitions for IBM PS2 running AIX/386. + From: Minh Tran-Le <TRANLE@intellicorp.com> + Copyright (C) 1988 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + + +#include "i386/i386.h" + +/* Get the generic definitions for system V.3. */ + +#include "svr3.h" + +/* Use the ATT assembler syntax. + This overrides at least one macro (ASM_OUTPUT_LABELREF) from svr3.h. */ + +#include "i386/att.h" + +/* Use crt1.o as a startup file and crtn.o as a closing file. */ + +#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}" +#define ENDFILE_SPEC "crtn.o%s" + +#define LIB_SPEC "%{shlib:-lc_s} -lc" + +/* Special flags for the linker. I don't know what they do. */ + +#define LINK_SPEC "%{K} %{!K:-K} %{T*} %{z:-lm}" + +/* Specify predefined symbols in preprocessor. */ + +#define CPP_PREDEFINES "-Dps2 -Dunix -Di386 -Asystem(unix) -Asystem(aix) -Acpu(i386) -Amachine(i386)" + +#define CPP_SPEC \ + "%{posix:-D_POSIX_SOURCE}%{!posix:-DAIX} -D_I386 -D_AIX -D_MBCS" + +/* special flags for the aix assembler to generate the short form for all + qualifying forward reference */ +/* The buggy /bin/as of aix ps/2 1.2.x cannot always handle it. */ +#if 0 +#define ASM_SPEC "-s2" +#endif /* 0 */ + +#undef ASM_FILE_START +#define ASM_FILE_START(FILE) \ + do { fprintf (FILE, "\t.file\t"); \ + output_quoted_string (FILE, dump_base_name); \ + fprintf (FILE, "\n"); \ + if (optimize) \ + ASM_FILE_START_1 (FILE); \ + else \ + fprintf (FILE, "\t.noopt\n"); \ + } while (0) + +/* This was suggested, but it shouldn't be right for DBX output. -- RMS + #define ASM_OUTPUT_SOURCE_FILENAME(FILE, NAME) */ + +/* Writing `int' for a bitfield forces int alignment for the structure. */ + +#define PCC_BITFIELD_TYPE_MATTERS 1 + +#ifndef USE_GAS +/* Don't write a `.optim' pseudo; this assembler + is said to have a bug when .optim is used. */ + +#undef ASM_FILE_START_1 +#define ASM_FILE_START_1(FILE) fprintf (FILE, "\t.noopt\n") +#endif + +/* Output assembler code to FILE to increment profiler label # LABELNO + for profiling a function entry. */ + +#undef FUNCTION_PROFILER +#define FUNCTION_PROFILER(FILE, LABELNO) \ + fprintf (FILE, "\tleal %sP%d,%%eax\n\tcall mcount\n", LPREFIX, (LABELNO)); + +/* Note that using bss_section here caused errors + in building shared libraries on system V.3. + but AIX 1.2 does not have yet shareable libraries on PS2 */ +#undef ASM_OUTPUT_LOCAL +#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ + (bss_section (), \ + ASM_OUTPUT_LABEL ((FILE), (NAME)), \ + fprintf ((FILE), "\t.set .,.+%u\n", (ROUNDED))) + + +/* Undef all the .init and .fini section stuff if we are not using gas and + * gnu ld so that we can use collect because the standard /bin/as and /bin/ld + * cannot handle those. + */ +#ifndef USE_GAS +# undef INIT_SECTION_ASM_OP +# undef FINI_SECTION_ASM_OP +# undef CTORS_SECTION_ASM_OP +# undef DTORS_SECTION_ASM_OP +# undef ASM_OUTPUT_CONSTRUCTOR +# undef ASM_OUTPUT_DESTRUCTOR +# undef DO_GLOBAL_CTORS_BODY + +# undef CTOR_LIST_BEGIN +# define CTOR_LIST_BEGIN +# undef CTOR_LIST_END +# define CTOR_LIST_END +# undef DTOR_LIST_BEGIN +# define DTOR_LIST_BEGIN +# undef DTOR_LIST_END +# define DTOR_LIST_END + +# undef CONST_SECTION_FUNCTION +# define CONST_SECTION_FUNCTION \ +void \ +const_section () \ +{ \ + extern void text_section(); \ + text_section(); \ +} + +# undef EXTRA_SECTION_FUNCTIONS +# define EXTRA_SECTION_FUNCTIONS \ + CONST_SECTION_FUNCTION \ + BSS_SECTION_FUNCTION + +/* for collect2 */ +# define OBJECT_FORMAT_COFF +# define MY_ISCOFF(magic) \ + ((magic) == I386MAGIC || (magic) == I386SVMAGIC) + +#endif /* !USE_GAS */ diff --git a/contrib/gcc/config/i386/att.h b/contrib/gcc/config/i386/att.h new file mode 100644 index 0000000..f8bbb76 --- /dev/null +++ b/contrib/gcc/config/i386/att.h @@ -0,0 +1,106 @@ +/* Definitions for AT&T assembler syntax for the Intel 80386. + Copyright (C) 1988 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Include common aspects of all 386 Unix assemblers. */ +#include "i386/unix.h" + +#define TARGET_VERSION fprintf (stderr, " (80386, ATT syntax)"); + +/* Define the syntax of instructions and addresses. */ + +/* Prefix for internally generated assembler labels. */ +#define LPREFIX ".L" + +/* Assembler pseudos to introduce constants of various size. */ + +/* #define ASM_BYTE_OP "\t.byte" Now in svr3.h or svr4.h. */ +#define ASM_SHORT "\t.value" +#define ASM_LONG "\t.long" +#define ASM_DOUBLE "\t.double" + +/* How to output an ASCII string constant. */ + +#define ASM_OUTPUT_ASCII(FILE, p, size) \ +do \ +{ int i = 0; \ + while (i < (size)) \ + { if (i%10 == 0) { if (i!=0) fprintf ((FILE), "\n"); \ + fprintf ((FILE), "%s ", ASM_BYTE_OP); } \ + else fprintf ((FILE), ","); \ + fprintf ((FILE), "0x%x", ((p)[i++] & 0377)) ;} \ + fprintf ((FILE), "\n"); \ +} while (0) + +/* Do use .optim by default on this machine. */ +#undef ASM_FILE_START_1 +#define ASM_FILE_START_1(FILE) fprintf (FILE, "\t.optim\n") + +/* This is how to output an assembler line + that says to advance the location counter + to a multiple of 2**LOG bytes. */ + +#define ASM_OUTPUT_ALIGN(FILE,LOG) \ + if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", 1<<(LOG)) + +/* This is how to output an assembler line + that says to advance the location counter by SIZE bytes. */ + +#define ASM_OUTPUT_SKIP(FILE,SIZE) \ + fprintf ((FILE), "\t.set .,.+%u\n", (SIZE)) + +/* Can't use ASM_OUTPUT_SKIP in text section; it doesn't leave 0s. */ + +#define ASM_NO_SKIP_IN_TEXT 1 + +#undef BSS_SECTION_FUNCTION /* Override the definition from svr3.h. */ +#define BSS_SECTION_FUNCTION \ +void \ +bss_section () \ +{ \ + if (in_section != in_bss) \ + { \ + fprintf (asm_out_file, "%s\n", BSS_SECTION_ASM_OP); \ + in_section = in_bss; \ + } \ +} + +/* Define the syntax of labels and symbol definitions/declarations. */ + +/* This is how to store into the string BUF + the symbol_ref name of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. + This is suitable for output with `assemble_name'. */ + +#undef ASM_GENERATE_INTERNAL_LABEL +#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ + sprintf ((BUF), ".%s%d", (PREFIX), (NUMBER)) + +/* This is how to output an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. */ + +#undef ASM_OUTPUT_INTERNAL_LABEL +#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ + fprintf (FILE, ".%s%d:\n", PREFIX, NUM) + +/* This is how to output a reference to a user-level label named NAME. */ + +#undef ASM_OUTPUT_LABELREF +#define ASM_OUTPUT_LABELREF(FILE,NAME) \ + fprintf (FILE, "%s", NAME) diff --git a/contrib/gcc/config/i386/bsd.h b/contrib/gcc/config/i386/bsd.h new file mode 100644 index 0000000..6bf7399 --- /dev/null +++ b/contrib/gcc/config/i386/bsd.h @@ -0,0 +1,130 @@ +/* Definitions for BSD assembler syntax for Intel 386 + (actually AT&T syntax for insns and operands, + adapted to BSD conventions for symbol names and debugging.) + Copyright (C) 1988 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Include common aspects of all 386 Unix assemblers. */ +#include "i386/unix.h" + +/* Use the Sequent Symmetry assembler syntax. */ + +#define TARGET_VERSION fprintf (stderr, " (80386, BSD syntax)"); + +/* Define the syntax of pseudo-ops, labels and comments. */ + +/* Prefix for internally generated assembler labels. If we aren't using + underscores, we are using prefix `.'s to identify labels that should + be ignored, as in `i386/gas.h' --karl@cs.umb.edu */ +#ifdef NO_UNDERSCORES +#define LPREFIX ".L" +#else +#define LPREFIX "L" +#endif /* not NO_UNDERSCORES */ + +/* Assembler pseudos to introduce constants of various size. */ + +#define ASM_BYTE_OP "\t.byte" +#define ASM_SHORT "\t.word" +#define ASM_LONG "\t.long" +#define ASM_DOUBLE "\t.double" + +/* Output at beginning of assembler file. + ??? I am skeptical of this -- RMS. */ + +#define ASM_FILE_START(FILE) \ + do { fprintf (FILE, "\t.file\t"); \ + output_quoted_string (FILE, dump_base_name); \ + fprintf (FILE, "\n"); \ + } while (0) + +/* This was suggested, but it shouldn't be right for DBX output. -- RMS + #define ASM_OUTPUT_SOURCE_FILENAME(FILE, NAME) */ + + +/* Define the syntax of labels and symbol definitions/declarations. */ + +/* This is how to output an assembler line + that says to advance the location counter by SIZE bytes. */ + +#define ASM_OUTPUT_SKIP(FILE,SIZE) \ + fprintf (FILE, "\t.space %u\n", (SIZE)) + +/* Define the syntax of labels and symbol definitions/declarations. */ + +/* This says how to output an assembler line + to define a global common symbol. */ + +#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ +( fputs (".comm ", (FILE)), \ + assemble_name ((FILE), (NAME)), \ + fprintf ((FILE), ",%u\n", (ROUNDED))) + +/* This says how to output an assembler line + to define a local common symbol. */ + +#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ +( fputs (".lcomm ", (FILE)), \ + assemble_name ((FILE), (NAME)), \ + fprintf ((FILE), ",%u\n", (ROUNDED))) + +/* This is how to output an assembler line + that says to advance the location counter + to a multiple of 2**LOG bytes. */ + +#define ASM_OUTPUT_ALIGN(FILE,LOG) \ + if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", (LOG)) + +/* This is how to store into the string BUF + the symbol_ref name of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. + This is suitable for output with `assemble_name'. */ + +#ifdef NO_UNDERSCORES +#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ + sprintf ((BUF), "*.%s%d", (PREFIX), (NUMBER)) +#else +#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ + sprintf ((BUF), "*%s%d", (PREFIX), (NUMBER)) +#endif + +/* This is how to output an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. */ + +#ifdef NO_UNDERSCORES +#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ + fprintf (FILE, ".%s%d:\n", PREFIX, NUM) +#else +#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ + fprintf (FILE, "%s%d:\n", PREFIX, NUM) +#endif + +/* This is how to output a reference to a user-level label named NAME. */ + +#ifdef NO_UNDERSCORES +#define ASM_OUTPUT_LABELREF(FILE,NAME) fprintf (FILE, "%s", NAME) +#else +#define ASM_OUTPUT_LABELREF(FILE,NAME) fprintf (FILE, "_%s", NAME) +#endif /* not NO_UNDERSCORES */ + +/* Sequent has some changes in the format of DBX symbols. */ +#define DBX_NO_XREFS 1 + +/* Don't split DBX symbols into continuations. */ +#define DBX_CONTIN_LENGTH 0 diff --git a/contrib/gcc/config/i386/bsd386.h b/contrib/gcc/config/i386/bsd386.h new file mode 100644 index 0000000..935a2e0 --- /dev/null +++ b/contrib/gcc/config/i386/bsd386.h @@ -0,0 +1,18 @@ +/* Configuration for an i386 running BSDI's BSD/386 1.1 as the target + machine. */ + +#include "i386/386bsd.h" + +/* We exist mostly to add -Dbsdi and such to the predefines. */ + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dunix -Di386 -Dbsdi -D__i386__ -D__bsdi__ -D____386BSD____ -D__386BSD__ -DBSD_NET2 -Asystem(unix) -Asystem(bsd) -Acpu(i386) -Amachine(i386)" + +#undef WCHAR_TYPE +#define WCHAR_TYPE "int" + +#undef WCHAR_UNSIGNED +#define WCHAR_UNSIGNED 0 + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE 32 diff --git a/contrib/gcc/config/i386/config-nt.sed b/contrib/gcc/config/i386/config-nt.sed new file mode 100644 index 0000000..6c86b27 --- /dev/null +++ b/contrib/gcc/config/i386/config-nt.sed @@ -0,0 +1,38 @@ +/^Makefile/,/^ rm -f config.run/d +s/rm -f/del/ +s/|| cp/|| copy/ +/^config.status/,/ fi/d +s/config.status//g +s/\/dev\/null/NUL/g +s/$(srcdir)\/c-parse/c-parse/g +s/$(srcdir)\/c-gperf/c-gperf/g +/^multilib.h/ s/multilib/not-multilib/ +/^target=/ c\ +target=winnt3.5 +/^xmake_file=/ d +/^tmake_file=/ d +/^out_file/ c\ +out_file=config/i386/i386.c +/^out_object_file/ c\ +out_object_file=i386.obj +/^md_file/ c\ +md_file=config/i386/i386.md +/^tm_file/ c\ +tm_file=config/i386/win-nt.h +/^build_xm_file/ c\ +build_xm_file=config/i386/xm-winnt.h +/^host_xm_file/ c\ +host_xm_file=config/i386/xm-winnt.h +/^####target/ i\ +CC = cl \ +CLIB = libc.lib kernel32.lib \ +CFLAGS = -Di386 -DWIN32 -D_WIN32 -D_M_IX86=300 -D_X86_=1 \\\ + -DALMOST_STDC -D_MSC_VER=800 \ +LDFLAGS = -align:0x1000 -subsystem:console -entry:mainCRTStartup \\\ + -stack:1000000,1000 \ +\ +EXTRA_OBJS=winnt.obj \ +winnt.obj: $(srcdir)/config/i386/winnt.c \ +\ $(CC) $(CFLAGS) \\\ +\ -I. -I$(srcdir) -I$(srcdir)/config -c $(srcdir)/config/i386/winnt.c \ + diff --git a/contrib/gcc/config/i386/freebsd.h b/contrib/gcc/config/i386/freebsd.h new file mode 100644 index 0000000..72fcdd1 --- /dev/null +++ b/contrib/gcc/config/i386/freebsd.h @@ -0,0 +1,256 @@ +/* Definitions of target machine for GNU compiler for Intel 80386 + running FreeBSD. + Copyright (C) 1988, 1992, 1994 Free Software Foundation, Inc. + Contributed by Poul-Henning Kamp <phk@login.dkuug.dk> + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* This goes away when the math-emulator is fixed */ +#define TARGET_CPU_DEFAULT 0400 /* TARGET_NO_FANCY_MATH_387 */ + +/* This is tested by i386gas.h. */ +#define YES_UNDERSCORES + +/* Don't assume anything about the header files. */ +#define NO_IMPLICIT_EXTERN_C + +#include "i386/gstabs.h" + +/* Get perform_* macros to build libgcc.a. */ +#include "i386/perform.h" + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dunix -Di386 -D__FreeBSD__ -D__386BSD__ -Asystem(unix) -Asystem(FreeBSD) -Acpu(i386) -Amachine(i386)" + +/* Like the default, except no -lg. */ +#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}" + +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "int" + +#undef WCHAR_TYPE +#define WCHAR_TYPE "short unsigned int" + +#define WCHAR_UNSIGNED 1 + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE 16 + +#define HAVE_ATEXIT + +/* There are conflicting reports about whether this system uses + a different assembler syntax. wilson@cygnus.com says # is right. */ +#undef COMMENT_BEGIN +#define COMMENT_BEGIN "#" + +#undef ASM_APP_ON +#define ASM_APP_ON "#APP\n" + +#undef ASM_APP_OFF +#define ASM_APP_OFF "#NO_APP\n" + +/* The following macros are stolen from i386v4.h */ +/* These have to be defined to get PIC code correct */ + +/* This is how to output an element of a case-vector that is relative. + This is only used for PIC code. See comments by the `casesi' insn in + i386.md for an explanation of the expression this outputs. */ + +#undef ASM_OUTPUT_ADDR_DIFF_ELT +#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ + fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE) + +/* Indicate that jump tables go in the text section. This is + necessary when compiling PIC code. */ + +#define JUMP_TABLES_IN_TEXT_SECTION + +/* Don't default to pcc-struct-return, because gcc is the only compiler, and + we want to retain compatibility with older gcc versions. */ +#define DEFAULT_PCC_STRUCT_RETURN 0 + +/* Profiling routines, partially copied from i386/osfrose.h. */ + +/* Redefine this to use %eax instead of %edx. */ +#undef FUNCTION_PROFILER +#define FUNCTION_PROFILER(FILE, LABELNO) \ +{ \ + if (flag_pic) \ + { \ + fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%eax\n", \ + LPREFIX, (LABELNO)); \ + fprintf (FILE, "\tcall *mcount@GOT(%%ebx)\n"); \ + } \ + else \ + { \ + fprintf (FILE, "\tmovl $%sP%d,%%eax\n", LPREFIX, (LABELNO)); \ + fprintf (FILE, "\tcall mcount\n"); \ + } \ +} + +/* + * Some imports from svr4.h in support of shared libraries. + * Currently, we need the DECLARE_OBJECT_SIZE stuff. + */ + +/* Define the strings used for the special svr4 .type and .size directives. + These strings generally do not vary from one system running svr4 to + another, but if a given system (e.g. m88k running svr) needs to use + different pseudo-op names for these, they may be overridden in the + file which includes this one. */ + +#define TYPE_ASM_OP ".type" +#define SIZE_ASM_OP ".size" + +/* This is how we tell the assembler that a symbol is weak. */ + +#define ASM_WEAKEN_LABEL(FILE,NAME) \ + do { fputs ("\t.weak\t", FILE); assemble_name (FILE, NAME); \ + fputc ('\n', FILE); } while (0) + +/* The following macro defines the format used to output the second + operand of the .type assembler directive. Different svr4 assemblers + expect various different forms for this operand. The one given here + is just a default. You may need to override it in your machine- + specific tm.h file (depending upon the particulars of your assembler). */ + +#define TYPE_OPERAND_FMT "@%s" + +/* Write the extra assembler code needed to declare a function's result. + Most svr4 assemblers don't require any special declaration of the + result value, but there are exceptions. */ + +#ifndef ASM_DECLARE_RESULT +#define ASM_DECLARE_RESULT(FILE, RESULT) +#endif + +/* These macros generate the special .type and .size directives which + are used to set the corresponding fields of the linker symbol table + entries in an ELF object file under SVR4. These macros also output + the starting labels for the relevant functions/objects. */ + +/* Write the extra assembler code needed to declare a function properly. + Some svr4 assemblers need to also have something extra said about the + function's return value. We allow for that here. */ + +#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ + do { \ + fprintf (FILE, "\t%s\t ", TYPE_ASM_OP); \ + assemble_name (FILE, NAME); \ + putc (',', FILE); \ + fprintf (FILE, TYPE_OPERAND_FMT, "function"); \ + putc ('\n', FILE); \ + ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ + ASM_OUTPUT_LABEL(FILE, NAME); \ + } while (0) + +/* Write the extra assembler code needed to declare an object properly. */ + +#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL) \ + do { \ + fprintf (FILE, "\t%s\t ", TYPE_ASM_OP); \ + assemble_name (FILE, NAME); \ + putc (',', FILE); \ + fprintf (FILE, TYPE_OPERAND_FMT, "object"); \ + putc ('\n', FILE); \ + size_directive_output = 0; \ + if (!flag_inhibit_size_directive && DECL_SIZE (DECL)) \ + { \ + size_directive_output = 1; \ + fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ + } \ + ASM_OUTPUT_LABEL(FILE, NAME); \ + } while (0) + +/* Output the size directive for a decl in rest_of_decl_compilation + in the case where we did not do so before the initializer. + Once we find the error_mark_node, we know that the value of + size_directive_output was set + by ASM_DECLARE_OBJECT_NAME when it was run for the same decl. */ + +#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \ +do { \ + char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ + if (!flag_inhibit_size_directive && DECL_SIZE (DECL) \ + && ! AT_END && TOP_LEVEL \ + && DECL_INITIAL (DECL) == error_mark_node \ + && !size_directive_output) \ + { \ + fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (FILE, name); \ + fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL)));\ + } \ + } while (0) + + +/* This is how to declare the size of a function. */ + +#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \ + do { \ + if (!flag_inhibit_size_directive) \ + { \ + char label[256]; \ + static int labelno; \ + labelno++; \ + ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno); \ + ASM_OUTPUT_INTERNAL_LABEL (FILE, "Lfe", labelno); \ + fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (FILE, (FNAME)); \ + fprintf (FILE, ","); \ + assemble_name (FILE, label); \ + fprintf (FILE, "-"); \ + assemble_name (FILE, (FNAME)); \ + putc ('\n', FILE); \ + } \ + } while (0) + +#define ASM_SPEC " %| %{fpic:-k} %{fPIC:-k}" +#define LINK_SPEC \ + "%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp %{static:-Bstatic} %{assert*}" + +/* This is defined when gcc is compiled in the BSD-directory-tree, and must + * make up for the gap to all the stuff done in the GNU-makefiles. + */ + +#ifdef FREEBSD_NATIVE + +#define INCLUDE_DEFAULTS { \ + { "/usr/include", 0 }, \ + { "/usr/include/g++", 1 }, \ + { 0, 0} \ + } + +#undef MD_EXEC_PREFIX +#define MD_EXEC_PREFIX "/usr/libexec/" + +#undef STANDARD_STARTFILE_PREFIX +#define STANDARD_STARTFILE_PREFIX "/usr/lib" + +#if 0 /* This is very wrong!!! */ +#define DEFAULT_TARGET_MACHINE "i386-unknown-freebsd_1.0" +#define GPLUSPLUS_INCLUDE_DIR "/usr/local/lib/gcc-lib/i386-unknown-freebsd_1.0/2.5.8/include" +#define TOOL_INCLUDE_DIR "/usr/local/i386-unknown-freebsd_1.0/include" +#define GCC_INCLUDE_DIR "/usr/local/lib/gcc-lib/i386-unknown-freebsd_1.0/2.5.8/include" +#endif + +#endif /* FREEBSD_NATIVE */ diff --git a/contrib/gcc/config/i386/freebsd.h.fixed b/contrib/gcc/config/i386/freebsd.h.fixed new file mode 100644 index 0000000..72fcdd1 --- /dev/null +++ b/contrib/gcc/config/i386/freebsd.h.fixed @@ -0,0 +1,256 @@ +/* Definitions of target machine for GNU compiler for Intel 80386 + running FreeBSD. + Copyright (C) 1988, 1992, 1994 Free Software Foundation, Inc. + Contributed by Poul-Henning Kamp <phk@login.dkuug.dk> + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* This goes away when the math-emulator is fixed */ +#define TARGET_CPU_DEFAULT 0400 /* TARGET_NO_FANCY_MATH_387 */ + +/* This is tested by i386gas.h. */ +#define YES_UNDERSCORES + +/* Don't assume anything about the header files. */ +#define NO_IMPLICIT_EXTERN_C + +#include "i386/gstabs.h" + +/* Get perform_* macros to build libgcc.a. */ +#include "i386/perform.h" + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dunix -Di386 -D__FreeBSD__ -D__386BSD__ -Asystem(unix) -Asystem(FreeBSD) -Acpu(i386) -Amachine(i386)" + +/* Like the default, except no -lg. */ +#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}" + +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "int" + +#undef WCHAR_TYPE +#define WCHAR_TYPE "short unsigned int" + +#define WCHAR_UNSIGNED 1 + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE 16 + +#define HAVE_ATEXIT + +/* There are conflicting reports about whether this system uses + a different assembler syntax. wilson@cygnus.com says # is right. */ +#undef COMMENT_BEGIN +#define COMMENT_BEGIN "#" + +#undef ASM_APP_ON +#define ASM_APP_ON "#APP\n" + +#undef ASM_APP_OFF +#define ASM_APP_OFF "#NO_APP\n" + +/* The following macros are stolen from i386v4.h */ +/* These have to be defined to get PIC code correct */ + +/* This is how to output an element of a case-vector that is relative. + This is only used for PIC code. See comments by the `casesi' insn in + i386.md for an explanation of the expression this outputs. */ + +#undef ASM_OUTPUT_ADDR_DIFF_ELT +#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ + fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE) + +/* Indicate that jump tables go in the text section. This is + necessary when compiling PIC code. */ + +#define JUMP_TABLES_IN_TEXT_SECTION + +/* Don't default to pcc-struct-return, because gcc is the only compiler, and + we want to retain compatibility with older gcc versions. */ +#define DEFAULT_PCC_STRUCT_RETURN 0 + +/* Profiling routines, partially copied from i386/osfrose.h. */ + +/* Redefine this to use %eax instead of %edx. */ +#undef FUNCTION_PROFILER +#define FUNCTION_PROFILER(FILE, LABELNO) \ +{ \ + if (flag_pic) \ + { \ + fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%eax\n", \ + LPREFIX, (LABELNO)); \ + fprintf (FILE, "\tcall *mcount@GOT(%%ebx)\n"); \ + } \ + else \ + { \ + fprintf (FILE, "\tmovl $%sP%d,%%eax\n", LPREFIX, (LABELNO)); \ + fprintf (FILE, "\tcall mcount\n"); \ + } \ +} + +/* + * Some imports from svr4.h in support of shared libraries. + * Currently, we need the DECLARE_OBJECT_SIZE stuff. + */ + +/* Define the strings used for the special svr4 .type and .size directives. + These strings generally do not vary from one system running svr4 to + another, but if a given system (e.g. m88k running svr) needs to use + different pseudo-op names for these, they may be overridden in the + file which includes this one. */ + +#define TYPE_ASM_OP ".type" +#define SIZE_ASM_OP ".size" + +/* This is how we tell the assembler that a symbol is weak. */ + +#define ASM_WEAKEN_LABEL(FILE,NAME) \ + do { fputs ("\t.weak\t", FILE); assemble_name (FILE, NAME); \ + fputc ('\n', FILE); } while (0) + +/* The following macro defines the format used to output the second + operand of the .type assembler directive. Different svr4 assemblers + expect various different forms for this operand. The one given here + is just a default. You may need to override it in your machine- + specific tm.h file (depending upon the particulars of your assembler). */ + +#define TYPE_OPERAND_FMT "@%s" + +/* Write the extra assembler code needed to declare a function's result. + Most svr4 assemblers don't require any special declaration of the + result value, but there are exceptions. */ + +#ifndef ASM_DECLARE_RESULT +#define ASM_DECLARE_RESULT(FILE, RESULT) +#endif + +/* These macros generate the special .type and .size directives which + are used to set the corresponding fields of the linker symbol table + entries in an ELF object file under SVR4. These macros also output + the starting labels for the relevant functions/objects. */ + +/* Write the extra assembler code needed to declare a function properly. + Some svr4 assemblers need to also have something extra said about the + function's return value. We allow for that here. */ + +#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ + do { \ + fprintf (FILE, "\t%s\t ", TYPE_ASM_OP); \ + assemble_name (FILE, NAME); \ + putc (',', FILE); \ + fprintf (FILE, TYPE_OPERAND_FMT, "function"); \ + putc ('\n', FILE); \ + ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \ + ASM_OUTPUT_LABEL(FILE, NAME); \ + } while (0) + +/* Write the extra assembler code needed to declare an object properly. */ + +#define ASM_DECLARE_OBJECT_NAME(FILE, NAME, DECL) \ + do { \ + fprintf (FILE, "\t%s\t ", TYPE_ASM_OP); \ + assemble_name (FILE, NAME); \ + putc (',', FILE); \ + fprintf (FILE, TYPE_OPERAND_FMT, "object"); \ + putc ('\n', FILE); \ + size_directive_output = 0; \ + if (!flag_inhibit_size_directive && DECL_SIZE (DECL)) \ + { \ + size_directive_output = 1; \ + fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ + } \ + ASM_OUTPUT_LABEL(FILE, NAME); \ + } while (0) + +/* Output the size directive for a decl in rest_of_decl_compilation + in the case where we did not do so before the initializer. + Once we find the error_mark_node, we know that the value of + size_directive_output was set + by ASM_DECLARE_OBJECT_NAME when it was run for the same decl. */ + +#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \ +do { \ + char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ + if (!flag_inhibit_size_directive && DECL_SIZE (DECL) \ + && ! AT_END && TOP_LEVEL \ + && DECL_INITIAL (DECL) == error_mark_node \ + && !size_directive_output) \ + { \ + fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (FILE, name); \ + fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL)));\ + } \ + } while (0) + + +/* This is how to declare the size of a function. */ + +#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \ + do { \ + if (!flag_inhibit_size_directive) \ + { \ + char label[256]; \ + static int labelno; \ + labelno++; \ + ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno); \ + ASM_OUTPUT_INTERNAL_LABEL (FILE, "Lfe", labelno); \ + fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (FILE, (FNAME)); \ + fprintf (FILE, ","); \ + assemble_name (FILE, label); \ + fprintf (FILE, "-"); \ + assemble_name (FILE, (FNAME)); \ + putc ('\n', FILE); \ + } \ + } while (0) + +#define ASM_SPEC " %| %{fpic:-k} %{fPIC:-k}" +#define LINK_SPEC \ + "%{!nostdlib:%{!r*:%{!e*:-e start}}} -dc -dp %{static:-Bstatic} %{assert*}" + +/* This is defined when gcc is compiled in the BSD-directory-tree, and must + * make up for the gap to all the stuff done in the GNU-makefiles. + */ + +#ifdef FREEBSD_NATIVE + +#define INCLUDE_DEFAULTS { \ + { "/usr/include", 0 }, \ + { "/usr/include/g++", 1 }, \ + { 0, 0} \ + } + +#undef MD_EXEC_PREFIX +#define MD_EXEC_PREFIX "/usr/libexec/" + +#undef STANDARD_STARTFILE_PREFIX +#define STANDARD_STARTFILE_PREFIX "/usr/lib" + +#if 0 /* This is very wrong!!! */ +#define DEFAULT_TARGET_MACHINE "i386-unknown-freebsd_1.0" +#define GPLUSPLUS_INCLUDE_DIR "/usr/local/lib/gcc-lib/i386-unknown-freebsd_1.0/2.5.8/include" +#define TOOL_INCLUDE_DIR "/usr/local/i386-unknown-freebsd_1.0/include" +#define GCC_INCLUDE_DIR "/usr/local/lib/gcc-lib/i386-unknown-freebsd_1.0/2.5.8/include" +#endif + +#endif /* FREEBSD_NATIVE */ diff --git a/contrib/gcc/config/i386/gas.h b/contrib/gcc/config/i386/gas.h new file mode 100644 index 0000000..d020157 --- /dev/null +++ b/contrib/gcc/config/i386/gas.h @@ -0,0 +1,155 @@ +/* Definitions for Intel 386 running system V with gnu tools + Copyright (C) 1988, 1993, 1994 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Note that i386/seq-gas.h is a GAS configuration that does not use this + file. */ + +#include "i386/i386.h" + +#ifndef YES_UNDERSCORES +/* Define this now, because i386/bsd.h tests it. */ +#define NO_UNDERSCORES +#endif + +/* Use the bsd assembler syntax. */ +/* we need to do this because gas is really a bsd style assembler, + * and so doesn't work well this these att-isms: + * + * ASM_OUTPUT_SKIP is .set .,.+N, which isn't implemented in gas + * ASM_OUTPUT_LOCAL is done with .set .,.+N, but that can't be + * used to define bss static space + * + * Next is the question of whether to uses underscores. RMS didn't + * like this idea at first, but since it is now obvious that we + * need this separate tm file for use with gas, at least to get + * dbx debugging info, I think we should also switch to underscores. + * We can keep i386v for real att style output, and the few + * people who want both form will have to compile twice. + */ + +#include "i386/bsd.h" + +/* these come from i386/bsd.h, but are specific to sequent */ +#undef DBX_NO_XREFS +#undef DBX_CONTIN_LENGTH + +/* Ask for COFF symbols. */ + +#define SDB_DEBUGGING_INFO + +/* Specify predefined symbols in preprocessor. */ + +#define CPP_PREDEFINES "-Dunix -Di386 -Asystem(unix) -Acpu(i386) -Amachine(i386)" +#define CPP_SPEC "%{posix:-D_POSIX_SOURCE}" + +/* Allow #sccs in preprocessor. */ + +#define SCCS_DIRECTIVE + +/* Output #ident as a .ident. */ + +#define ASM_OUTPUT_IDENT(FILE, NAME) fprintf (FILE, "\t.ident \"%s\"\n", NAME); + +/* Implicit library calls should use memcpy, not bcopy, etc. */ + +#define TARGET_MEM_FUNCTIONS + +#if 0 /* People say gas uses the log as the arg to .align. */ +/* When using gas, .align N aligns to an N-byte boundary. */ + +#undef ASM_OUTPUT_ALIGN +#define ASM_OUTPUT_ALIGN(FILE,LOG) \ + if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", 1<<(LOG)) +#endif + +/* Align labels, etc. at 4-byte boundaries. + For the 486, align to 16-byte boundary for sake of cache. */ + +#undef ASM_OUTPUT_ALIGN_CODE +#define ASM_OUTPUT_ALIGN_CODE(FILE) \ + fprintf ((FILE), "\t.align %d,0x90\n", i386_align_jumps) + +/* Align start of loop at 4-byte boundary. */ + +#undef ASM_OUTPUT_LOOP_ALIGN +#define ASM_OUTPUT_LOOP_ALIGN(FILE) \ + fprintf ((FILE), "\t.align %d,0x90\n", i386_align_loops) + + +/* A C statement or statements which output an assembler instruction + opcode to the stdio stream STREAM. The macro-operand PTR is a + variable of type `char *' which points to the opcode name in its + "internal" form--the form that is written in the machine description. + + GAS version 1.38.1 doesn't understand the `repz' opcode mnemonic. + So use `repe' instead. */ + +#define ASM_OUTPUT_OPCODE(STREAM, PTR) \ +{ \ + if ((PTR)[0] == 'r' \ + && (PTR)[1] == 'e' \ + && (PTR)[2] == 'p') \ + { \ + if ((PTR)[3] == 'z') \ + { \ + fprintf (STREAM, "repe"); \ + (PTR) += 4; \ + } \ + else if ((PTR)[3] == 'n' && (PTR)[4] == 'z') \ + { \ + fprintf (STREAM, "repne"); \ + (PTR) += 5; \ + } \ + } \ +} + +/* Define macro used to output shift-double opcodes when the shift + count is in %cl. Some assemblers require %cl as an argument; + some don't. + + GAS requires the %cl argument, so override i386/unix.h. */ + +#undef AS3_SHIFT_DOUBLE +#define AS3_SHIFT_DOUBLE(a,b,c,d) AS3 (a,b,c,d) + +/* Print opcodes the way that GAS expects them. */ +#define GAS_MNEMONICS 1 + +#ifdef NO_UNDERSCORES /* If user-symbols don't have underscores, + then it must take more than `L' to identify + a label that should be ignored. */ + +/* This is how to store into the string BUF + the symbol_ref name of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. + This is suitable for output with `assemble_name'. */ + +#undef ASM_GENERATE_INTERNAL_LABEL +#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ + sprintf ((BUF), ".%s%d", (PREFIX), (NUMBER)) + +/* This is how to output an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. */ + +#undef ASM_OUTPUT_INTERNAL_LABEL +#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ + fprintf (FILE, ".%s%d:\n", PREFIX, NUM) + +#endif /* NO_UNDERSCORES */ diff --git a/contrib/gcc/config/i386/gnu.h b/contrib/gcc/config/i386/gnu.h new file mode 100644 index 0000000..1ad5df9 --- /dev/null +++ b/contrib/gcc/config/i386/gnu.h @@ -0,0 +1,20 @@ +/* Configuration for an i386 running GNU with ELF as the target machine. */ + +/* This does it mostly for us. */ +#include <i386/linux.h> + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES GNU_CPP_PREDEFINES("i386") + +#undef LINK_SPEC +#define LINK_SPEC "-m elf_i386 %{shared:-shared} \ + %{!shared: \ + %{!ibcs: \ + %{!static: \ + %{rdynamic:-export-dynamic} \ + %{!dynamic-linker:-dynamic-linker /lib/ld.so} \ + %{!rpath:-rpath /lib/}} %{static:-static}}}" + + +/* Get machine-independent configuration parameters for the GNU system. */ +#include <gnu.h> diff --git a/contrib/gcc/config/i386/go32.h b/contrib/gcc/config/i386/go32.h new file mode 100644 index 0000000..5618a0d --- /dev/null +++ b/contrib/gcc/config/i386/go32.h @@ -0,0 +1,64 @@ +/* Configuration for an i386 running MS-DOS with djgpp/go32. */ + +/* Don't assume anything about the header files. */ +#define NO_IMPLICIT_EXTERN_C + +#define HANDLE_SYSV_PRAGMA + +#define YES_UNDERSCORES + +#include "i386/gas.h" + +#ifdef CPP_PREDEFINES +#undef CPP_PREDEFINES +#endif +#define CPP_PREDEFINES "-Dunix -Di386 -DGO32 -DMSDOS \ + -Asystem(unix) -Asystem(msdos) -Acpu(i386) -Amachine(i386)" + +#undef EXTRA_SECTIONS +#define EXTRA_SECTIONS in_ctor, in_dtor + +#undef EXTRA_SECTION_FUNCTIONS +#define EXTRA_SECTION_FUNCTIONS \ + CTOR_SECTION_FUNCTION \ + DTOR_SECTION_FUNCTION + +#define CTOR_SECTION_FUNCTION \ +void \ +ctor_section () \ +{ \ + if (in_section != in_ctor) \ + { \ + fprintf (asm_out_file, "\t.section .ctor\n"); \ + in_section = in_ctor; \ + } \ +} + +#define DTOR_SECTION_FUNCTION \ +void \ +dtor_section () \ +{ \ + if (in_section != in_dtor) \ + { \ + fprintf (asm_out_file, "\t.section .dtor\n"); \ + in_section = in_dtor; \ + } \ +} + +#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ + do { \ + ctor_section (); \ + fprintf (FILE, "%s\t", ASM_LONG); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + +#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ + do { \ + dtor_section (); \ + fprintf (FILE, "%s\t", ASM_LONG); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + + diff --git a/contrib/gcc/config/i386/gstabs.h b/contrib/gcc/config/i386/gstabs.h new file mode 100644 index 0000000..5f0ae34 --- /dev/null +++ b/contrib/gcc/config/i386/gstabs.h @@ -0,0 +1,9 @@ +#include "i386/gas.h" + +/* We do not want to output SDB debugging information. */ + +#undef SDB_DEBUGGING_INFO + +/* We want to output DBX debugging information. */ + +#define DBX_DEBUGGING_INFO diff --git a/contrib/gcc/config/i386/i386-aout.h b/contrib/gcc/config/i386/i386-aout.h new file mode 100644 index 0000000..e4be8d5 --- /dev/null +++ b/contrib/gcc/config/i386/i386-aout.h @@ -0,0 +1,34 @@ +/* Definitions for "naked" Intel 386 using a.out (or coff encap'd + a.out) object format and stabs debugging info. + + Copyright (C) 1994 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + + +/* This is tested by gas.h. */ +#define YES_UNDERSCORES + +#include "i386/gstabs.h" + +/* Specify predefined symbols in preprocessor. */ + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Di386" + +/* end of i386-aout.h */ diff --git a/contrib/gcc/config/i386/i386-coff.h b/contrib/gcc/config/i386/i386-coff.h new file mode 100644 index 0000000..915e307 --- /dev/null +++ b/contrib/gcc/config/i386/i386-coff.h @@ -0,0 +1,97 @@ +/* Definitions for "naked" Intel 386 using coff object format files + and coff debugging info. + + Copyright (C) 1994 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + + +#include "i386/gas.h" + +/* Specify predefined symbols in preprocessor. */ + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Di386" + +#undef DBX_DEBUGGING_INFO +#define SDB_DEBUGGING_INFO + +/* Support the ctors and dtors sections for g++. */ + +#define CTORS_SECTION_ASM_OP ".section\t.ctors,\"x\"" +#define DTORS_SECTION_ASM_OP ".section\t.dtors,\"x\"" + +/* A list of other sections which the compiler might be "in" at any + given time. */ + +#undef EXTRA_SECTIONS +#define EXTRA_SECTIONS in_ctors, in_dtors + +/* A list of extra section function definitions. */ + +#undef EXTRA_SECTION_FUNCTIONS +#define EXTRA_SECTION_FUNCTIONS \ + CTORS_SECTION_FUNCTION \ + DTORS_SECTION_FUNCTION + +#define CTORS_SECTION_FUNCTION \ +void \ +ctors_section () \ +{ \ + if (in_section != in_ctors) \ + { \ + fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \ + in_section = in_ctors; \ + } \ +} + +#define DTORS_SECTION_FUNCTION \ +void \ +dtors_section () \ +{ \ + if (in_section != in_dtors) \ + { \ + fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \ + in_section = in_dtors; \ + } \ +} + +#define INT_ASM_OP ".long" + +/* A C statement (sans semicolon) to output an element in the table of + global constructors. */ +#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ + do { \ + ctors_section (); \ + fprintf (FILE, "\t%s\t ", INT_ASM_OP); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + +/* A C statement (sans semicolon) to output an element in the table of + global destructors. */ +#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ + do { \ + dtors_section (); \ + fprintf (FILE, "\t%s\t ", INT_ASM_OP); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + + +/* end of i386-coff.h */ diff --git a/contrib/gcc/config/i386/i386.c b/contrib/gcc/config/i386/i386.c new file mode 100644 index 0000000..48c58a0 --- /dev/null +++ b/contrib/gcc/config/i386/i386.c @@ -0,0 +1,3245 @@ +/* Subroutines for insn-output.c for Intel X86. + Copyright (C) 1988, 1992, 1994, 1995 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include <stdio.h> +#include <setjmp.h> +#include <ctype.h> +#include "config.h" +#include "rtl.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "real.h" +#include "insn-config.h" +#include "conditions.h" +#include "insn-flags.h" +#include "output.h" +#include "insn-attr.h" +#include "tree.h" +#include "flags.h" +#include "function.h" + +#ifdef EXTRA_CONSTRAINT +/* If EXTRA_CONSTRAINT is defined, then the 'S' + constraint in REG_CLASS_FROM_LETTER will no longer work, and various + asm statements that need 'S' for class SIREG will break. */ + error EXTRA_CONSTRAINT conflicts with S constraint letter +/* The previous line used to be #error, but some compilers barf + even if the conditional was untrue. */ +#endif + +#define AT_BP(mode) (gen_rtx (MEM, (mode), frame_pointer_rtx)) + +extern FILE *asm_out_file; +extern char *strcat (); + +char *singlemove_string (); +char *output_move_const_single (); +char *output_fp_cc0_set (); + +char *hi_reg_name[] = HI_REGISTER_NAMES; +char *qi_reg_name[] = QI_REGISTER_NAMES; +char *qi_high_reg_name[] = QI_HIGH_REGISTER_NAMES; + +/* Array of the smallest class containing reg number REGNO, indexed by + REGNO. Used by REGNO_REG_CLASS in i386.h. */ + +enum reg_class regclass_map[FIRST_PSEUDO_REGISTER] = +{ + /* ax, dx, cx, bx */ + AREG, DREG, CREG, BREG, + /* si, di, bp, sp */ + SIREG, DIREG, INDEX_REGS, GENERAL_REGS, + /* FP registers */ + FP_TOP_REG, FP_SECOND_REG, FLOAT_REGS, FLOAT_REGS, + FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, + /* arg pointer */ + INDEX_REGS +}; + +/* Test and compare insns in i386.md store the information needed to + generate branch and scc insns here. */ + +struct rtx_def *i386_compare_op0 = NULL_RTX; +struct rtx_def *i386_compare_op1 = NULL_RTX; +struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)(); + +/* Register allocation order */ +char *i386_reg_alloc_order; +static char regs_allocated[FIRST_PSEUDO_REGISTER]; + +/* # of registers to use to pass arguments. */ +char *i386_regparm_string; /* # registers to use to pass args */ +int i386_regparm; /* i386_regparm_string as a number */ + +/* Alignment to use for loops and jumps */ +char *i386_align_loops_string; /* power of two alignment for loops */ +char *i386_align_jumps_string; /* power of two alignment for non-loop jumps */ +char *i386_align_funcs_string; /* power of two alignment for functions */ + +int i386_align_loops; /* power of two alignment for loops */ +int i386_align_jumps; /* power of two alignment for non-loop jumps */ +int i386_align_funcs; /* power of two alignment for functions */ + + +/* Sometimes certain combinations of command options do not make + sense on a particular target machine. You can define a macro + `OVERRIDE_OPTIONS' to take account of this. This macro, if + defined, is executed once just after all the command options have + been parsed. + + Don't use this macro to turn on various extra optimizations for + `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ + +void +override_options () +{ + int ch, i, regno; + char *p; + int def_align; + +#ifdef SUBTARGET_OVERRIDE_OPTIONS + SUBTARGET_OVERRIDE_OPTIONS; +#endif + + /* Validate registers in register allocation order */ + if (i386_reg_alloc_order) + { + for (i = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++) + { + switch (ch) + { + case 'a': regno = 0; break; + case 'd': regno = 1; break; + case 'c': regno = 2; break; + case 'b': regno = 3; break; + case 'S': regno = 4; break; + case 'D': regno = 5; break; + case 'B': regno = 6; break; + + default: fatal ("Register '%c' is unknown", ch); + } + + if (regs_allocated[regno]) + fatal ("Register '%c' was already specified in the allocation order", ch); + + regs_allocated[regno] = 1; + } + } + + /* Validate -mregparm= value */ + if (i386_regparm_string) + { + i386_regparm = atoi (i386_regparm_string); + if (i386_regparm < 0 || i386_regparm > REGPARM_MAX) + fatal ("-mregparm=%d is not between 0 and %d", i386_regparm, REGPARM_MAX); + } + + def_align = (TARGET_386) ? 2 : 4; + + /* Validate -malign-loops= value, or provide default */ + if (i386_align_loops_string) + { + i386_align_loops = atoi (i386_align_loops_string); + if (i386_align_loops < 0 || i386_align_loops > MAX_CODE_ALIGN) + fatal ("-malign-loops=%d is not between 0 and %d", + i386_align_loops, MAX_CODE_ALIGN); + } + else + i386_align_loops = 2; + + /* Validate -malign-jumps= value, or provide default */ + if (i386_align_jumps_string) + { + i386_align_jumps = atoi (i386_align_jumps_string); + if (i386_align_jumps < 0 || i386_align_jumps > MAX_CODE_ALIGN) + fatal ("-malign-jumps=%d is not between 0 and %d", + i386_align_jumps, MAX_CODE_ALIGN); + } + else + i386_align_jumps = def_align; + + /* Validate -malign-functions= value, or provide default */ + if (i386_align_funcs_string) + { + i386_align_funcs = atoi (i386_align_funcs_string); + if (i386_align_funcs < 0 || i386_align_funcs > MAX_CODE_ALIGN) + fatal ("-malign-functions=%d is not between 0 and %d", + i386_align_funcs, MAX_CODE_ALIGN); + } + else + i386_align_funcs = def_align; +} + +/* A C statement (sans semicolon) to choose the order in which to + allocate hard registers for pseudo-registers local to a basic + block. + + Store the desired register order in the array `reg_alloc_order'. + Element 0 should be the register to allocate first; element 1, the + next register; and so on. + + The macro body should not assume anything about the contents of + `reg_alloc_order' before execution of the macro. + + On most machines, it is not necessary to define this macro. */ + +void +order_regs_for_local_alloc () +{ + int i, ch, order, regno; + + /* User specified the register allocation order */ + if (i386_reg_alloc_order) + { + for (i = order = 0; (ch = i386_reg_alloc_order[i]) != '\0'; i++) + { + switch (ch) + { + case 'a': regno = 0; break; + case 'd': regno = 1; break; + case 'c': regno = 2; break; + case 'b': regno = 3; break; + case 'S': regno = 4; break; + case 'D': regno = 5; break; + case 'B': regno = 6; break; + } + + reg_alloc_order[order++] = regno; + } + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + { + if (!regs_allocated[i]) + reg_alloc_order[order++] = i; + } + } + + /* If users did not specify a register allocation order, favor eax + normally except if DImode variables are used, in which case + favor edx before eax, which seems to cause less spill register + not found messages. */ + else + { + rtx insn; + + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) + reg_alloc_order[i] = i; + + if (optimize) + { + int use_dca = FALSE; + + for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) + { + if (GET_CODE (insn) == INSN) + { + rtx set = NULL_RTX; + rtx pattern = PATTERN (insn); + + if (GET_CODE (pattern) == SET) + set = pattern; + + else if ((GET_CODE (pattern) == PARALLEL + || GET_CODE (pattern) == SEQUENCE) + && GET_CODE (XVECEXP (pattern, 0, 0)) == SET) + set = XVECEXP (pattern, 0, 0); + + if (set && GET_MODE (SET_SRC (set)) == DImode) + { + use_dca = TRUE; + break; + } + } + } + + if (use_dca) + { + reg_alloc_order[0] = 1; /* edx */ + reg_alloc_order[1] = 2; /* ecx */ + reg_alloc_order[2] = 0; /* eax */ + } + } + } +} + + +/* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific + attribute for DECL. The attributes in ATTRIBUTES have previously been + assigned to DECL. */ + +int +i386_valid_decl_attribute_p (decl, attributes, identifier, args) + tree decl; + tree attributes; + tree identifier; + tree args; +{ + return 0; +} + +/* Return nonzero if IDENTIFIER with arguments ARGS is a valid machine specific + attribute for TYPE. The attributes in ATTRIBUTES have previously been + assigned to TYPE. */ + +int +i386_valid_type_attribute_p (type, attributes, identifier, args) + tree type; + tree attributes; + tree identifier; + tree args; +{ + if (TREE_CODE (type) != FUNCTION_TYPE + && TREE_CODE (type) != FIELD_DECL + && TREE_CODE (type) != TYPE_DECL) + return 0; + + /* Stdcall attribute says callee is responsible for popping arguments + if they are not variable. */ + if (is_attribute_p ("stdcall", identifier)) + return (args == NULL_TREE); + + /* Cdecl attribute says the callee is a normal C declaration */ + if (is_attribute_p ("cdecl", identifier)) + return (args == NULL_TREE); + + /* Regparm attribute specifies how many integer arguments are to be + passed in registers */ + if (is_attribute_p ("regparm", identifier)) + { + tree cst; + + if (!args || TREE_CODE (args) != TREE_LIST + || TREE_CHAIN (args) != NULL_TREE + || TREE_VALUE (args) == NULL_TREE) + return 0; + + cst = TREE_VALUE (args); + if (TREE_CODE (cst) != INTEGER_CST) + return 0; + + if (TREE_INT_CST_HIGH (cst) != 0 + || TREE_INT_CST_LOW (cst) < 0 + || TREE_INT_CST_LOW (cst) > REGPARM_MAX) + return 0; + + return 1; + } + + return 0; +} + +/* Return 0 if the attributes for two types are incompatible, 1 if they + are compatible, and 2 if they are nearly compatible (which causes a + warning to be generated). */ + +int +i386_comp_type_attributes (type1, type2) + tree type1; + tree type2; +{ + return 1; +} + + +/* Value is the number of bytes of arguments automatically + popped when returning from a subroutine call. + FUNDECL is the declaration node of the function (as a tree), + FUNTYPE is the data type of the function (as a tree), + or for a library call it is an identifier node for the subroutine name. + SIZE is the number of bytes of arguments passed on the stack. + + On the 80386, the RTD insn may be used to pop them if the number + of args is fixed, but if the number is variable then the caller + must pop them all. RTD can't be used for library calls now + because the library is compiled with the Unix compiler. + Use of RTD is a selectable option, since it is incompatible with + standard Unix calling sequences. If the option is not selected, + the caller must always pop the args. + + The attribute stdcall is equivalent to RTD on a per module basis. */ + +int +i386_return_pops_args (fundecl, funtype, size) + tree fundecl; + tree funtype; + int size; +{ + int rtd = TARGET_RTD; + + if (TREE_CODE (funtype) == IDENTIFIER_NODE) + return 0; + + /* Cdecl functions override -mrtd, and never pop the stack */ + if (lookup_attribute ("cdecl", TYPE_ATTRIBUTES (funtype))) + return 0; + + /* Stdcall functions will pop the stack if not variable args */ + if (lookup_attribute ("stdcall", TYPE_ATTRIBUTES (funtype))) + rtd = 1; + + if (rtd) + { + if (TYPE_ARG_TYPES (funtype) == NULL_TREE + || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (funtype))) == void_type_node)) + return size; + + if (aggregate_value_p (TREE_TYPE (funtype))) + return GET_MODE_SIZE (Pmode); + } + + return 0; +} + + +/* Argument support functions. */ + +/* Initialize a variable CUM of type CUMULATIVE_ARGS + for a call to a function whose data type is FNTYPE. + For a library call, FNTYPE is 0. */ + +void +init_cumulative_args (cum, fntype, libname) + CUMULATIVE_ARGS *cum; /* argument info to initialize */ + tree fntype; /* tree ptr for function decl */ + rtx libname; /* SYMBOL_REF of library name or 0 */ +{ + static CUMULATIVE_ARGS zero_cum; + tree param, next_param; + + if (TARGET_DEBUG_ARG) + { + fprintf (stderr, "\ninit_cumulative_args ("); + if (fntype) + { + tree ret_type = TREE_TYPE (fntype); + fprintf (stderr, "fntype code = %s, ret code = %s", + tree_code_name[ (int)TREE_CODE (fntype) ], + tree_code_name[ (int)TREE_CODE (ret_type) ]); + } + else + fprintf (stderr, "no fntype"); + + if (libname) + fprintf (stderr, ", libname = %s", XSTR (libname, 0)); + } + + *cum = zero_cum; + + /* Set up the number of registers to use for passing arguments. */ + cum->nregs = i386_regparm; + if (fntype) + { + tree attr = lookup_attribute ("regparm", TYPE_ATTRIBUTES (fntype)); + if (attr) + cum->nregs = TREE_INT_CST_LOW (TREE_VALUE (TREE_VALUE (attr))); + } + + /* Determine if this function has variable arguments. This is + indicated by the last argument being 'void_type_mode' if there + are no variable arguments. If there are variable arguments, then + we won't pass anything in registers */ + + if (cum->nregs) + { + for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0; + param != (tree)0; + param = next_param) + { + next_param = TREE_CHAIN (param); + if (next_param == (tree)0 && TREE_VALUE (param) != void_type_node) + cum->nregs = 0; + } + } + + if (TARGET_DEBUG_ARG) + fprintf (stderr, ", nregs=%d )\n", cum->nregs); + + return; +} + +/* Update the data in CUM to advance over an argument + of mode MODE and data type TYPE. + (TYPE is null for libcalls where that information may not be available.) */ + +void +function_arg_advance (cum, mode, type, named) + CUMULATIVE_ARGS *cum; /* current arg information */ + enum machine_mode mode; /* current arg mode */ + tree type; /* type of the argument or 0 if lib support */ + int named; /* whether or not the argument was named */ +{ + int bytes = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); + int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; + + if (TARGET_DEBUG_ARG) + fprintf (stderr, + "function_adv( size=%d, words=%2d, nregs=%d, mode=%4s, named=%d )\n\n", + words, cum->words, cum->nregs, GET_MODE_NAME (mode), named); + + cum->words += words; + cum->nregs -= words; + cum->regno += words; + + if (cum->nregs <= 0) + { + cum->nregs = 0; + cum->regno = 0; + } + + return; +} + +/* Define where to put the arguments to a function. + Value is zero to push the argument on the stack, + or a hard register in which to store the argument. + + MODE is the argument's machine mode. + TYPE is the data type of the argument (as a tree). + This is null for libcalls where that information may + not be available. + CUM is a variable of type CUMULATIVE_ARGS which gives info about + the preceding args and about the function being called. + NAMED is nonzero if this argument is a named parameter + (otherwise it is an extra parameter matching an ellipsis). */ + +struct rtx_def * +function_arg (cum, mode, type, named) + CUMULATIVE_ARGS *cum; /* current arg information */ + enum machine_mode mode; /* current arg mode */ + tree type; /* type of the argument or 0 if lib support */ + int named; /* != 0 for normal args, == 0 for ... args */ +{ + rtx ret = NULL_RTX; + int bytes = (mode == BLKmode) ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); + int words = (bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; + + switch (mode) + { + default: /* for now, pass fp/complex values on the stack */ + break; + + case BLKmode: + case DImode: + case SImode: + case HImode: + case QImode: + if (words <= cum->nregs) + ret = gen_rtx (REG, mode, cum->regno); + break; + } + + if (TARGET_DEBUG_ARG) + { + fprintf (stderr, + "function_arg( size=%d, words=%2d, nregs=%d, mode=%4s, named=%d", + words, cum->words, cum->nregs, GET_MODE_NAME (mode), named); + + if (ret) + fprintf (stderr, ", reg=%%e%s", reg_names[ REGNO(ret) ]); + else + fprintf (stderr, ", stack"); + + fprintf (stderr, " )\n"); + } + + return ret; +} + +/* For an arg passed partly in registers and partly in memory, + this is the number of registers used. + For args passed entirely in registers or entirely in memory, zero. */ + +int +function_arg_partial_nregs (cum, mode, type, named) + CUMULATIVE_ARGS *cum; /* current arg information */ + enum machine_mode mode; /* current arg mode */ + tree type; /* type of the argument or 0 if lib support */ + int named; /* != 0 for normal args, == 0 for ... args */ +{ + return 0; +} + + +/* Output an insn whose source is a 386 integer register. SRC is the + rtx for the register, and TEMPLATE is the op-code template. SRC may + be either SImode or DImode. + + The template will be output with operands[0] as SRC, and operands[1] + as a pointer to the top of the 386 stack. So a call from floatsidf2 + would look like this: + + output_op_from_reg (operands[1], AS1 (fild%z0,%1)); + + where %z0 corresponds to the caller's operands[1], and is used to + emit the proper size suffix. + + ??? Extend this to handle HImode - a 387 can load and store HImode + values directly. */ + +void +output_op_from_reg (src, template) + rtx src; + char *template; +{ + rtx xops[4]; + int size = GET_MODE_SIZE (GET_MODE (src)); + + xops[0] = src; + xops[1] = AT_SP (Pmode); + xops[2] = GEN_INT (size); + xops[3] = stack_pointer_rtx; + + if (size > UNITS_PER_WORD) + { + rtx high; + if (size > 2 * UNITS_PER_WORD) + { + high = gen_rtx (REG, SImode, REGNO (src) + 2); + output_asm_insn (AS1 (push%L0,%0), &high); + } + high = gen_rtx (REG, SImode, REGNO (src) + 1); + output_asm_insn (AS1 (push%L0,%0), &high); + } + output_asm_insn (AS1 (push%L0,%0), &src); + + output_asm_insn (template, xops); + + output_asm_insn (AS2 (add%L3,%2,%3), xops); +} + +/* Output an insn to pop an value from the 387 top-of-stack to 386 + register DEST. The 387 register stack is popped if DIES is true. If + the mode of DEST is an integer mode, a `fist' integer store is done, + otherwise a `fst' float store is done. */ + +void +output_to_reg (dest, dies) + rtx dest; + int dies; +{ + rtx xops[4]; + int size = GET_MODE_SIZE (GET_MODE (dest)); + + xops[0] = AT_SP (Pmode); + xops[1] = stack_pointer_rtx; + xops[2] = GEN_INT (size); + xops[3] = dest; + + output_asm_insn (AS2 (sub%L1,%2,%1), xops); + + if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_INT) + { + if (dies) + output_asm_insn (AS1 (fistp%z3,%y0), xops); + else + output_asm_insn (AS1 (fist%z3,%y0), xops); + } + else if (GET_MODE_CLASS (GET_MODE (dest)) == MODE_FLOAT) + { + if (dies) + output_asm_insn (AS1 (fstp%z3,%y0), xops); + else + { + if (GET_MODE (dest) == XFmode) + { + output_asm_insn (AS1 (fstp%z3,%y0), xops); + output_asm_insn (AS1 (fld%z3,%y0), xops); + } + else + output_asm_insn (AS1 (fst%z3,%y0), xops); + } + } + else + abort (); + + output_asm_insn (AS1 (pop%L0,%0), &dest); + + if (size > UNITS_PER_WORD) + { + dest = gen_rtx (REG, SImode, REGNO (dest) + 1); + output_asm_insn (AS1 (pop%L0,%0), &dest); + if (size > 2 * UNITS_PER_WORD) + { + dest = gen_rtx (REG, SImode, REGNO (dest) + 1); + output_asm_insn (AS1 (pop%L0,%0), &dest); + } + } +} + +char * +singlemove_string (operands) + rtx *operands; +{ + rtx x; + if (GET_CODE (operands[0]) == MEM + && GET_CODE (x = XEXP (operands[0], 0)) == PRE_DEC) + { + if (XEXP (x, 0) != stack_pointer_rtx) + abort (); + return "push%L1 %1"; + } + else if (GET_CODE (operands[1]) == CONST_DOUBLE) + { + return output_move_const_single (operands); + } + else if (GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == REG) + return AS2 (mov%L0,%1,%0); + else if (CONSTANT_P (operands[1])) + return AS2 (mov%L0,%1,%0); + else + { + output_asm_insn ("push%L1 %1", operands); + return "pop%L0 %0"; + } +} + +/* Return a REG that occurs in ADDR with coefficient 1. + ADDR can be effectively incremented by incrementing REG. */ + +static rtx +find_addr_reg (addr) + rtx addr; +{ + while (GET_CODE (addr) == PLUS) + { + if (GET_CODE (XEXP (addr, 0)) == REG) + addr = XEXP (addr, 0); + else if (GET_CODE (XEXP (addr, 1)) == REG) + addr = XEXP (addr, 1); + else if (CONSTANT_P (XEXP (addr, 0))) + addr = XEXP (addr, 1); + else if (CONSTANT_P (XEXP (addr, 1))) + addr = XEXP (addr, 0); + else + abort (); + } + if (GET_CODE (addr) == REG) + return addr; + abort (); +} + + +/* Output an insn to add the constant N to the register X. */ + +static void +asm_add (n, x) + int n; + rtx x; +{ + rtx xops[2]; + xops[0] = x; + + if (n == -1) + output_asm_insn (AS1 (dec%L0,%0), xops); + else if (n == 1) + output_asm_insn (AS1 (inc%L0,%0), xops); + else if (n < 0) + { + xops[1] = GEN_INT (-n); + output_asm_insn (AS2 (sub%L0,%1,%0), xops); + } + else if (n > 0) + { + xops[1] = GEN_INT (n); + output_asm_insn (AS2 (add%L0,%1,%0), xops); + } +} + + +/* Output assembler code to perform a doubleword move insn + with operands OPERANDS. */ + +char * +output_move_double (operands) + rtx *operands; +{ + enum {REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1; + rtx latehalf[2]; + rtx middlehalf[2]; + rtx xops[2]; + rtx addreg0 = 0, addreg1 = 0; + int dest_overlapped_low = 0; + int size = GET_MODE_SIZE (GET_MODE (operands[0])); + + middlehalf[0] = 0; + middlehalf[1] = 0; + + /* First classify both operands. */ + + if (REG_P (operands[0])) + optype0 = REGOP; + else if (offsettable_memref_p (operands[0])) + optype0 = OFFSOP; + else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) + optype0 = POPOP; + else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) + optype0 = PUSHOP; + else if (GET_CODE (operands[0]) == MEM) + optype0 = MEMOP; + else + optype0 = RNDOP; + + if (REG_P (operands[1])) + optype1 = REGOP; + else if (CONSTANT_P (operands[1])) + optype1 = CNSTOP; + else if (offsettable_memref_p (operands[1])) + optype1 = OFFSOP; + else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) + optype1 = POPOP; + else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) + optype1 = PUSHOP; + else if (GET_CODE (operands[1]) == MEM) + optype1 = MEMOP; + else + optype1 = RNDOP; + + /* Check for the cases that the operand constraints are not + supposed to allow to happen. Abort if we get one, + because generating code for these cases is painful. */ + + if (optype0 == RNDOP || optype1 == RNDOP) + abort (); + + /* If one operand is decrementing and one is incrementing + decrement the former register explicitly + and change that operand into ordinary indexing. */ + + if (optype0 == PUSHOP && optype1 == POPOP) + { + /* ??? Can this ever happen on i386? */ + operands[0] = XEXP (XEXP (operands[0], 0), 0); + asm_add (-size, operands[0]); + if (GET_MODE (operands[1]) == XFmode) + operands[0] = gen_rtx (MEM, XFmode, operands[0]); + else if (GET_MODE (operands[0]) == DFmode) + operands[0] = gen_rtx (MEM, DFmode, operands[0]); + else + operands[0] = gen_rtx (MEM, DImode, operands[0]); + optype0 = OFFSOP; + } + + if (optype0 == POPOP && optype1 == PUSHOP) + { + /* ??? Can this ever happen on i386? */ + operands[1] = XEXP (XEXP (operands[1], 0), 0); + asm_add (-size, operands[1]); + if (GET_MODE (operands[1]) == XFmode) + operands[1] = gen_rtx (MEM, XFmode, operands[1]); + else if (GET_MODE (operands[1]) == DFmode) + operands[1] = gen_rtx (MEM, DFmode, operands[1]); + else + operands[1] = gen_rtx (MEM, DImode, operands[1]); + optype1 = OFFSOP; + } + + /* If an operand is an unoffsettable memory ref, find a register + we can increment temporarily to make it refer to the second word. */ + + if (optype0 == MEMOP) + addreg0 = find_addr_reg (XEXP (operands[0], 0)); + + if (optype1 == MEMOP) + addreg1 = find_addr_reg (XEXP (operands[1], 0)); + + /* Ok, we can do one word at a time. + Normally we do the low-numbered word first, + but if either operand is autodecrementing then we + do the high-numbered word first. + + In either case, set up in LATEHALF the operands to use + for the high-numbered word and in some cases alter the + operands in OPERANDS to be suitable for the low-numbered word. */ + + if (size == 12) + { + if (optype0 == REGOP) + { + middlehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 2); + } + else if (optype0 == OFFSOP) + { + middlehalf[0] = adj_offsettable_operand (operands[0], 4); + latehalf[0] = adj_offsettable_operand (operands[0], 8); + } + else + { + middlehalf[0] = operands[0]; + latehalf[0] = operands[0]; + } + + if (optype1 == REGOP) + { + middlehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2); + } + else if (optype1 == OFFSOP) + { + middlehalf[1] = adj_offsettable_operand (operands[1], 4); + latehalf[1] = adj_offsettable_operand (operands[1], 8); + } + else if (optype1 == CNSTOP) + { + if (GET_CODE (operands[1]) == CONST_DOUBLE) + { + REAL_VALUE_TYPE r; long l[3]; + + REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); + REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); + operands[1] = GEN_INT (l[0]); + middlehalf[1] = GEN_INT (l[1]); + latehalf[1] = GEN_INT (l[2]); + } + else if (CONSTANT_P (operands[1])) + /* No non-CONST_DOUBLE constant should ever appear here. */ + abort (); + } + else + { + middlehalf[1] = operands[1]; + latehalf[1] = operands[1]; + } + } + else /* size is not 12: */ + { + if (optype0 == REGOP) + latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + else if (optype0 == OFFSOP) + latehalf[0] = adj_offsettable_operand (operands[0], 4); + else + latehalf[0] = operands[0]; + + if (optype1 == REGOP) + latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); + else if (optype1 == OFFSOP) + latehalf[1] = adj_offsettable_operand (operands[1], 4); + else if (optype1 == CNSTOP) + split_double (operands[1], &operands[1], &latehalf[1]); + else + latehalf[1] = operands[1]; + } + + /* If insn is effectively movd N (sp),-(sp) then we will do the + high word first. We should use the adjusted operand 1 + (which is N+4 (sp) or N+8 (sp)) + for the low word and middle word as well, + to compensate for the first decrement of sp. */ + if (optype0 == PUSHOP + && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM + && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) + middlehalf[1] = operands[1] = latehalf[1]; + + /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)), + if the upper part of reg N does not appear in the MEM, arrange to + emit the move late-half first. Otherwise, compute the MEM address + into the upper part of N and use that as a pointer to the memory + operand. */ + if (optype0 == REGOP + && (optype1 == OFFSOP || optype1 == MEMOP)) + { + if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)) + && reg_mentioned_p (latehalf[0], XEXP (operands[1], 0))) + { + /* If both halves of dest are used in the src memory address, + compute the address into latehalf of dest. */ +compadr: + xops[0] = latehalf[0]; + xops[1] = XEXP (operands[1], 0); + output_asm_insn (AS2 (lea%L0,%a1,%0), xops); + if( GET_MODE (operands[1]) == XFmode ) + { +/* abort (); */ + operands[1] = gen_rtx (MEM, XFmode, latehalf[0]); + middlehalf[1] = adj_offsettable_operand (operands[1], size-8); + latehalf[1] = adj_offsettable_operand (operands[1], size-4); + } + else + { + operands[1] = gen_rtx (MEM, DImode, latehalf[0]); + latehalf[1] = adj_offsettable_operand (operands[1], size-4); + } + } + else if (size == 12 + && reg_mentioned_p (middlehalf[0], XEXP (operands[1], 0))) + { + /* Check for two regs used by both source and dest. */ + if (reg_mentioned_p (operands[0], XEXP (operands[1], 0)) + || reg_mentioned_p (latehalf[0], XEXP (operands[1], 0))) + goto compadr; + + /* JRV says this can't happen: */ + if (addreg0 || addreg1) + abort(); + + /* Only the middle reg conflicts; simply put it last. */ + output_asm_insn (singlemove_string (operands), operands); + output_asm_insn (singlemove_string (latehalf), latehalf); + output_asm_insn (singlemove_string (middlehalf), middlehalf); + return ""; + } + else if (reg_mentioned_p (operands[0], XEXP (operands[1], 0))) + /* If the low half of dest is mentioned in the source memory + address, the arrange to emit the move late half first. */ + dest_overlapped_low = 1; + } + + /* If one or both operands autodecrementing, + do the two words, high-numbered first. */ + + /* Likewise, the first move would clobber the source of the second one, + do them in the other order. This happens only for registers; + such overlap can't happen in memory unless the user explicitly + sets it up, and that is an undefined circumstance. */ + +/* + if (optype0 == PUSHOP || optype1 == PUSHOP + || (optype0 == REGOP && optype1 == REGOP + && REGNO (operands[0]) == REGNO (latehalf[1])) + || dest_overlapped_low) +*/ + if (optype0 == PUSHOP || optype1 == PUSHOP + || (optype0 == REGOP && optype1 == REGOP + && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1])) + || REGNO (operands[0]) == REGNO (latehalf[1]))) + || dest_overlapped_low) + { + /* Make any unoffsettable addresses point at high-numbered word. */ + if (addreg0) + asm_add (size-4, addreg0); + if (addreg1) + asm_add (size-4, addreg1); + + /* Do that word. */ + output_asm_insn (singlemove_string (latehalf), latehalf); + + /* Undo the adds we just did. */ + if (addreg0) + asm_add (-4, addreg0); + if (addreg1) + asm_add (-4, addreg1); + + if (size == 12) + { + output_asm_insn (singlemove_string (middlehalf), middlehalf); + if (addreg0) + asm_add (-4, addreg0); + if (addreg1) + asm_add (-4, addreg1); + } + + /* Do low-numbered word. */ + return singlemove_string (operands); + } + + /* Normal case: do the two words, low-numbered first. */ + + output_asm_insn (singlemove_string (operands), operands); + + /* Do the middle one of the three words for long double */ + if (size == 12) + { + if (addreg0) + asm_add (4, addreg0); + if (addreg1) + asm_add (4, addreg1); + + output_asm_insn (singlemove_string (middlehalf), middlehalf); + } + + /* Make any unoffsettable addresses point at high-numbered word. */ + if (addreg0) + asm_add (4, addreg0); + if (addreg1) + asm_add (4, addreg1); + + /* Do that word. */ + output_asm_insn (singlemove_string (latehalf), latehalf); + + /* Undo the adds we just did. */ + if (addreg0) + asm_add (4-size, addreg0); + if (addreg1) + asm_add (4-size, addreg1); + + return ""; +} + + +#define MAX_TMPS 2 /* max temporary registers used */ + +/* Output the appropriate code to move push memory on the stack */ + +char * +output_move_pushmem (operands, insn, length, tmp_start, n_operands) + rtx operands[]; + rtx insn; + int length; + int tmp_start; + int n_operands; +{ + + struct { + char *load; + char *push; + rtx xops[2]; + } tmp_info[MAX_TMPS]; + + rtx src = operands[1]; + int max_tmps = 0; + int offset = 0; + int stack_p = reg_overlap_mentioned_p (stack_pointer_rtx, src); + int stack_offset = 0; + int i, num_tmps; + rtx xops[1]; + + if (!offsettable_memref_p (src)) + fatal_insn ("Source is not offsettable", insn); + + if ((length & 3) != 0) + fatal_insn ("Pushing non-word aligned size", insn); + + /* Figure out which temporary registers we have available */ + for (i = tmp_start; i < n_operands; i++) + { + if (GET_CODE (operands[i]) == REG) + { + if (reg_overlap_mentioned_p (operands[i], src)) + continue; + + tmp_info[ max_tmps++ ].xops[1] = operands[i]; + if (max_tmps == MAX_TMPS) + break; + } + } + + if (max_tmps == 0) + for (offset = length - 4; offset >= 0; offset -= 4) + { + xops[0] = adj_offsettable_operand (src, offset + stack_offset); + output_asm_insn (AS1(push%L0,%0), xops); + if (stack_p) + stack_offset += 4; + } + + else + for (offset = length - 4; offset >= 0; ) + { + for (num_tmps = 0; num_tmps < max_tmps && offset >= 0; num_tmps++) + { + tmp_info[num_tmps].load = AS2(mov%L0,%0,%1); + tmp_info[num_tmps].push = AS1(push%L0,%1); + tmp_info[num_tmps].xops[0] = adj_offsettable_operand (src, offset + stack_offset); + offset -= 4; + } + + for (i = 0; i < num_tmps; i++) + output_asm_insn (tmp_info[i].load, tmp_info[i].xops); + + for (i = 0; i < num_tmps; i++) + output_asm_insn (tmp_info[i].push, tmp_info[i].xops); + + if (stack_p) + stack_offset += 4*num_tmps; + } + + return ""; +} + + + +/* Output the appropriate code to move data between two memory locations */ + +char * +output_move_memory (operands, insn, length, tmp_start, n_operands) + rtx operands[]; + rtx insn; + int length; + int tmp_start; + int n_operands; +{ + struct { + char *load; + char *store; + rtx xops[3]; + } tmp_info[MAX_TMPS]; + + rtx dest = operands[0]; + rtx src = operands[1]; + rtx qi_tmp = NULL_RTX; + int max_tmps = 0; + int offset = 0; + int i, num_tmps; + rtx xops[3]; + + if (GET_CODE (dest) == MEM + && GET_CODE (XEXP (dest, 0)) == PRE_INC + && XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx) + return output_move_pushmem (operands, insn, length, tmp_start, n_operands); + + if (!offsettable_memref_p (src)) + fatal_insn ("Source is not offsettable", insn); + + if (!offsettable_memref_p (dest)) + fatal_insn ("Destination is not offsettable", insn); + + /* Figure out which temporary registers we have available */ + for (i = tmp_start; i < n_operands; i++) + { + if (GET_CODE (operands[i]) == REG) + { + if ((length & 1) != 0 && !qi_tmp && QI_REG_P (operands[i])) + qi_tmp = operands[i]; + + if (reg_overlap_mentioned_p (operands[i], dest)) + fatal_insn ("Temporary register overlaps the destination", insn); + + if (reg_overlap_mentioned_p (operands[i], src)) + fatal_insn ("Temporary register overlaps the source", insn); + + tmp_info[ max_tmps++ ].xops[2] = operands[i]; + if (max_tmps == MAX_TMPS) + break; + } + } + + if (max_tmps == 0) + fatal_insn ("No scratch registers were found to do memory->memory moves", insn); + + if ((length & 1) != 0) + { + if (!qi_tmp) + fatal_insn ("No byte register found when moving odd # of bytes.", insn); + } + + while (length > 1) + { + for (num_tmps = 0; num_tmps < max_tmps; num_tmps++) + { + if (length >= 4) + { + tmp_info[num_tmps].load = AS2(mov%L0,%1,%2); + tmp_info[num_tmps].store = AS2(mov%L0,%2,%0); + tmp_info[num_tmps].xops[0] = adj_offsettable_operand (dest, offset); + tmp_info[num_tmps].xops[1] = adj_offsettable_operand (src, offset); + offset += 4; + length -= 4; + } + else if (length >= 2) + { + tmp_info[num_tmps].load = AS2(mov%W0,%1,%2); + tmp_info[num_tmps].store = AS2(mov%W0,%2,%0); + tmp_info[num_tmps].xops[0] = adj_offsettable_operand (dest, offset); + tmp_info[num_tmps].xops[1] = adj_offsettable_operand (src, offset); + offset += 2; + length -= 2; + } + else + break; + } + + for (i = 0; i < num_tmps; i++) + output_asm_insn (tmp_info[i].load, tmp_info[i].xops); + + for (i = 0; i < num_tmps; i++) + output_asm_insn (tmp_info[i].store, tmp_info[i].xops); + } + + if (length == 1) + { + xops[0] = adj_offsettable_operand (dest, offset); + xops[1] = adj_offsettable_operand (src, offset); + xops[2] = qi_tmp; + output_asm_insn (AS2(mov%B0,%1,%2), xops); + output_asm_insn (AS2(mov%B0,%2,%0), xops); + } + + return ""; +} + + +int +standard_80387_constant_p (x) + rtx x; +{ +#if ! defined (REAL_IS_NOT_DOUBLE) || defined (REAL_ARITHMETIC) + REAL_VALUE_TYPE d; + jmp_buf handler; + int is0, is1; + + if (setjmp (handler)) + return 0; + + set_float_handler (handler); + REAL_VALUE_FROM_CONST_DOUBLE (d, x); + is0 = REAL_VALUES_EQUAL (d, dconst0); + is1 = REAL_VALUES_EQUAL (d, dconst1); + set_float_handler (NULL_PTR); + + if (is0) + return 1; + + if (is1) + return 2; + + /* Note that on the 80387, other constants, such as pi, + are much slower to load as standard constants + than to load from doubles in memory! */ +#endif + + return 0; +} + +char * +output_move_const_single (operands) + rtx *operands; +{ + if (FP_REG_P (operands[0])) + { + int conval = standard_80387_constant_p (operands[1]); + + if (conval == 1) + return "fldz"; + + if (conval == 2) + return "fld1"; + } + if (GET_CODE (operands[1]) == CONST_DOUBLE) + { + REAL_VALUE_TYPE r; long l; + + if (GET_MODE (operands[1]) == XFmode) + abort (); + + REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); + REAL_VALUE_TO_TARGET_SINGLE (r, l); + operands[1] = GEN_INT (l); + } + return singlemove_string (operands); +} + +/* Returns 1 if OP is either a symbol reference or a sum of a symbol + reference and a constant. */ + +int +symbolic_operand (op, mode) + register rtx op; + enum machine_mode mode; +{ + switch (GET_CODE (op)) + { + case SYMBOL_REF: + case LABEL_REF: + return 1; + case CONST: + op = XEXP (op, 0); + return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF + || GET_CODE (XEXP (op, 0)) == LABEL_REF) + && GET_CODE (XEXP (op, 1)) == CONST_INT); + default: + return 0; + } +} + +/* Test for a valid operand for a call instruction. + Don't allow the arg pointer register or virtual regs + since they may change into reg + const, which the patterns + can't handle yet. */ + +int +call_insn_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (GET_CODE (op) == MEM + && ((CONSTANT_ADDRESS_P (XEXP (op, 0)) + /* This makes a difference for PIC. */ + && general_operand (XEXP (op, 0), Pmode)) + || (GET_CODE (XEXP (op, 0)) == REG + && XEXP (op, 0) != arg_pointer_rtx + && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER + && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER)))) + return 1; + return 0; +} + +/* Like call_insn_operand but allow (mem (symbol_ref ...)) + even if pic. */ + +int +expander_call_insn_operand (op, mode) + rtx op; + enum machine_mode mode; +{ + if (GET_CODE (op) == MEM + && (CONSTANT_ADDRESS_P (XEXP (op, 0)) + || (GET_CODE (XEXP (op, 0)) == REG + && XEXP (op, 0) != arg_pointer_rtx + && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER + && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER)))) + return 1; + return 0; +} + +/* Return 1 if OP is a comparison operator that can use the condition code + generated by an arithmetic operation. */ + +int +arithmetic_comparison_operator (op, mode) + register rtx op; + enum machine_mode mode; +{ + enum rtx_code code; + + if (mode != VOIDmode && mode != GET_MODE (op)) + return 0; + code = GET_CODE (op); + if (GET_RTX_CLASS (code) != '<') + return 0; + + return (code != GT && code != LE); +} + +/* Returns 1 if OP contains a symbol reference */ + +int +symbolic_reference_mentioned_p (op) + rtx op; +{ + register char *fmt; + register int i; + + if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF) + return 1; + + fmt = GET_RTX_FORMAT (GET_CODE (op)); + for (i = GET_RTX_LENGTH (GET_CODE (op)) - 1; i >= 0; i--) + { + if (fmt[i] == 'E') + { + register int j; + + for (j = XVECLEN (op, i) - 1; j >= 0; j--) + if (symbolic_reference_mentioned_p (XVECEXP (op, i, j))) + return 1; + } + else if (fmt[i] == 'e' && symbolic_reference_mentioned_p (XEXP (op, i))) + return 1; + } + + return 0; +} + +/* This function generates the assembly code for function entry. + FILE is an stdio stream to output the code to. + SIZE is an int: how many units of temporary storage to allocate. */ + +void +function_prologue (file, size) + FILE *file; + int size; +{ + register int regno; + int limit; + rtx xops[4]; + int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table + || current_function_uses_const_pool); + + xops[0] = stack_pointer_rtx; + xops[1] = frame_pointer_rtx; + xops[2] = GEN_INT (size); + if (frame_pointer_needed) + { + output_asm_insn ("push%L1 %1", xops); + output_asm_insn (AS2 (mov%L0,%0,%1), xops); + } + + if (size) + output_asm_insn (AS2 (sub%L0,%2,%0), xops); + + /* Note If use enter it is NOT reversed args. + This one is not reversed from intel!! + I think enter is slower. Also sdb doesn't like it. + But if you want it the code is: + { + xops[3] = const0_rtx; + output_asm_insn ("enter %2,%3", xops); + } + */ + limit = (frame_pointer_needed ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM); + for (regno = limit - 1; regno >= 0; regno--) + if ((regs_ever_live[regno] && ! call_used_regs[regno]) + || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) + { + xops[0] = gen_rtx (REG, SImode, regno); + output_asm_insn ("push%L0 %0", xops); + } + + if (pic_reg_used) + { + xops[0] = pic_offset_table_rtx; + xops[1] = (rtx) gen_label_rtx (); + + output_asm_insn (AS1 (call,%P1), xops); + ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (xops[1])); + output_asm_insn (AS1 (pop%L0,%0), xops); + output_asm_insn ("addl $_GLOBAL_OFFSET_TABLE_+[.-%P1],%0", xops); + } +} + +/* Return 1 if it is appropriate to emit `ret' instructions in the + body of a function. Do this only if the epilogue is simple, needing a + couple of insns. Prior to reloading, we can't tell how many registers + must be saved, so return 0 then. + + If NON_SAVING_SETJMP is defined and true, then it is not possible + for the epilogue to be simple, so return 0. This is a special case + since NON_SAVING_SETJMP will not cause regs_ever_live to change until + final, but jump_optimize may need to know sooner if a `return' is OK. */ + +int +simple_386_epilogue () +{ + int regno; + int nregs = 0; + int reglimit = (frame_pointer_needed + ? FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM); + int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table + || current_function_uses_const_pool); + +#ifdef NON_SAVING_SETJMP + if (NON_SAVING_SETJMP && current_function_calls_setjmp) + return 0; +#endif + + if (! reload_completed) + return 0; + + for (regno = reglimit - 1; regno >= 0; regno--) + if ((regs_ever_live[regno] && ! call_used_regs[regno]) + || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) + nregs++; + + return nregs == 0 || ! frame_pointer_needed; +} + + +/* This function generates the assembly code for function exit. + FILE is an stdio stream to output the code to. + SIZE is an int: how many units of temporary storage to deallocate. */ + +void +function_epilogue (file, size) + FILE *file; + int size; +{ + register int regno; + register int nregs, limit; + int offset; + rtx xops[3]; + int pic_reg_used = flag_pic && (current_function_uses_pic_offset_table + || current_function_uses_const_pool); + + /* Compute the number of registers to pop */ + + limit = (frame_pointer_needed + ? FRAME_POINTER_REGNUM + : STACK_POINTER_REGNUM); + + nregs = 0; + + for (regno = limit - 1; regno >= 0; regno--) + if ((regs_ever_live[regno] && ! call_used_regs[regno]) + || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) + nregs++; + + /* sp is often unreliable so we must go off the frame pointer, + */ + + /* In reality, we may not care if sp is unreliable, because we can + restore the register relative to the frame pointer. In theory, + since each move is the same speed as a pop, and we don't need the + leal, this is faster. For now restore multiple registers the old + way. */ + + offset = -size - (nregs * UNITS_PER_WORD); + + xops[2] = stack_pointer_rtx; + + if (nregs > 1 || ! frame_pointer_needed) + { + if (frame_pointer_needed) + { + xops[0] = adj_offsettable_operand (AT_BP (Pmode), offset); + output_asm_insn (AS2 (lea%L2,%0,%2), xops); + } + + for (regno = 0; regno < limit; regno++) + if ((regs_ever_live[regno] && ! call_used_regs[regno]) + || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) + { + xops[0] = gen_rtx (REG, SImode, regno); + output_asm_insn ("pop%L0 %0", xops); + } + } + else + for (regno = 0; regno < limit; regno++) + if ((regs_ever_live[regno] && ! call_used_regs[regno]) + || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) + { + xops[0] = gen_rtx (REG, SImode, regno); + xops[1] = adj_offsettable_operand (AT_BP (Pmode), offset); + output_asm_insn (AS2 (mov%L0,%1,%0), xops); + offset += 4; + } + + if (frame_pointer_needed) + { + /* On i486, mov & pop is faster than "leave". */ + + if (!TARGET_386) + { + xops[0] = frame_pointer_rtx; + output_asm_insn (AS2 (mov%L2,%0,%2), xops); + output_asm_insn ("pop%L0 %0", xops); + } + else + output_asm_insn ("leave", xops); + } + else if (size) + { + /* If there is no frame pointer, we must still release the frame. */ + + xops[0] = GEN_INT (size); + output_asm_insn (AS2 (add%L2,%0,%2), xops); + } + + if (current_function_pops_args && current_function_args_size) + { + xops[1] = GEN_INT (current_function_pops_args); + + /* i386 can only pop 32K bytes (maybe 64K? Is it signed?). If + asked to pop more, pop return address, do explicit add, and jump + indirectly to the caller. */ + + if (current_function_pops_args >= 32768) + { + /* ??? Which register to use here? */ + xops[0] = gen_rtx (REG, SImode, 2); + output_asm_insn ("pop%L0 %0", xops); + output_asm_insn (AS2 (add%L2,%1,%2), xops); + output_asm_insn ("jmp %*%0", xops); + } + else + output_asm_insn ("ret %1", xops); + } + else + output_asm_insn ("ret", xops); +} + + +/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression + that is a valid memory address for an instruction. + The MODE argument is the machine mode for the MEM expression + that wants to use this address. + + On x86, legitimate addresses are: + base movl (base),reg + displacement movl disp,reg + base + displacement movl disp(base),reg + index + base movl (base,index),reg + (index + base) + displacement movl disp(base,index),reg + index*scale movl (,index,scale),reg + index*scale + disp movl disp(,index,scale),reg + index*scale + base movl (base,index,scale),reg + (index*scale + base) + disp movl disp(base,index,scale),reg + + In each case, scale can be 1, 2, 4, 8. */ + +/* This is exactly the same as print_operand_addr, except that + it recognizes addresses instead of printing them. + + It only recognizes address in canonical form. LEGITIMIZE_ADDRESS should + convert common non-canonical forms to canonical form so that they will + be recognized. */ + +#define ADDR_INVALID(msg,insn) \ +do { \ + if (TARGET_DEBUG_ADDR) \ + { \ + fprintf (stderr, msg); \ + debug_rtx (insn); \ + } \ +} while (0) + +int +legitimate_address_p (mode, addr, strict) + enum machine_mode mode; + register rtx addr; + int strict; +{ + rtx base = NULL_RTX; + rtx indx = NULL_RTX; + rtx scale = NULL_RTX; + rtx disp = NULL_RTX; + + if (TARGET_DEBUG_ADDR) + { + fprintf (stderr, + "\n==========\nGO_IF_LEGITIMATE_ADDRESS, mode = %s, strict = %d\n", + GET_MODE_NAME (mode), strict); + + debug_rtx (addr); + } + + if (GET_CODE (addr) == REG || GET_CODE (addr) == SUBREG) + base = addr; /* base reg */ + + else if (GET_CODE (addr) == PLUS) + { + rtx op0 = XEXP (addr, 0); + rtx op1 = XEXP (addr, 1); + enum rtx_code code0 = GET_CODE (op0); + enum rtx_code code1 = GET_CODE (op1); + + if (code0 == REG || code0 == SUBREG) + { + if (code1 == REG || code1 == SUBREG) + { + indx = op0; /* index + base */ + base = op1; + } + + else + { + base = op0; /* base + displacement */ + disp = op1; + } + } + + else if (code0 == MULT) + { + indx = XEXP (op0, 0); + scale = XEXP (op0, 1); + + if (code1 == REG || code1 == SUBREG) + base = op1; /* index*scale + base */ + + else + disp = op1; /* index*scale + disp */ + } + + else if (code0 == PLUS && GET_CODE (XEXP (op0, 0)) == MULT) + { + indx = XEXP (XEXP (op0, 0), 0); /* index*scale + base + disp */ + scale = XEXP (XEXP (op0, 0), 1); + base = XEXP (op0, 1); + disp = op1; + } + + else if (code0 == PLUS) + { + indx = XEXP (op0, 0); /* index + base + disp */ + base = XEXP (op0, 1); + disp = op1; + } + + else + { + ADDR_INVALID ("PLUS subcode is not valid.\n", op0); + return FALSE; + } + } + + else if (GET_CODE (addr) == MULT) + { + indx = XEXP (addr, 0); /* index*scale */ + scale = XEXP (addr, 1); + } + + else + disp = addr; /* displacement */ + + /* Allow arg pointer and stack pointer as index if there is not scaling */ + if (base && indx && !scale + && (indx == arg_pointer_rtx || indx == stack_pointer_rtx)) + { + rtx tmp = base; + base = indx; + indx = tmp; + } + + /* Validate base register */ + /* Don't allow SUBREG's here, it can lead to spill failures when the base + is one word out of a two word structure, which is represented internally + as a DImode int. */ + if (base) + { + if (GET_CODE (base) != REG) + { + ADDR_INVALID ("Base is not a register.\n", base); + return FALSE; + } + + if ((strict && !REG_OK_FOR_BASE_STRICT_P (base)) + || (!strict && !REG_OK_FOR_BASE_NONSTRICT_P (base))) + { + ADDR_INVALID ("Base is not valid.\n", base); + return FALSE; + } + } + + /* Validate index register */ + /* Don't allow SUBREG's here, it can lead to spill failures when the index + is one word out of a two word structure, which is represented internally + as a DImode int. */ + if (indx) + { + if (GET_CODE (indx) != REG) + { + ADDR_INVALID ("Index is not a register.\n", indx); + return FALSE; + } + + if ((strict && !REG_OK_FOR_INDEX_STRICT_P (indx)) + || (!strict && !REG_OK_FOR_INDEX_NONSTRICT_P (indx))) + { + ADDR_INVALID ("Index is not valid.\n", indx); + return FALSE; + } + } + else if (scale) + abort (); /* scale w/o index invalid */ + + /* Validate scale factor */ + if (scale) + { + HOST_WIDE_INT value; + + if (GET_CODE (scale) != CONST_INT) + { + ADDR_INVALID ("Scale is not valid.\n", scale); + return FALSE; + } + + value = INTVAL (scale); + if (value != 1 && value != 2 && value != 4 && value != 8) + { + ADDR_INVALID ("Scale is not a good multiplier.\n", scale); + return FALSE; + } + } + + /* Validate displacement */ + if (disp) + { + if (!CONSTANT_ADDRESS_P (disp)) + { + ADDR_INVALID ("Displacement is not valid.\n", disp); + return FALSE; + } + + if (GET_CODE (disp) == CONST_DOUBLE) + { + ADDR_INVALID ("Displacement is a const_double.\n", disp); + return FALSE; + } + + if (flag_pic && SYMBOLIC_CONST (disp) && base != pic_offset_table_rtx + && (indx != pic_offset_table_rtx || scale != NULL_RTX)) + { + ADDR_INVALID ("Displacement is an invalid pic reference.\n", disp); + return FALSE; + } + + if (HALF_PIC_P () && HALF_PIC_ADDRESS_P (disp) + && (base != NULL_RTX || indx != NULL_RTX)) + { + ADDR_INVALID ("Displacement is an invalid half-pic reference.\n", disp); + return FALSE; + } + } + + if (TARGET_DEBUG_ADDR) + fprintf (stderr, "Address is valid.\n"); + + /* Everything looks valid, return true */ + return TRUE; +} + + +/* Return a legitimate reference for ORIG (an address) using the + register REG. If REG is 0, a new pseudo is generated. + + There are three types of references that must be handled: + + 1. Global data references must load the address from the GOT, via + the PIC reg. An insn is emitted to do this load, and the reg is + returned. + + 2. Static data references must compute the address as an offset + from the GOT, whose base is in the PIC reg. An insn is emitted to + compute the address into a reg, and the reg is returned. Static + data objects have SYMBOL_REF_FLAG set to differentiate them from + global data objects. + + 3. Constant pool addresses must be handled special. They are + considered legitimate addresses, but only if not used with regs. + When printed, the output routines know to print the reference with the + PIC reg, even though the PIC reg doesn't appear in the RTL. + + GO_IF_LEGITIMATE_ADDRESS rejects symbolic references unless the PIC + reg also appears in the address (except for constant pool references, + noted above). + + "switch" statements also require special handling when generating + PIC code. See comments by the `casesi' insn in i386.md for details. */ + +rtx +legitimize_pic_address (orig, reg) + rtx orig; + rtx reg; +{ + rtx addr = orig; + rtx new = orig; + + if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF) + { + if (GET_CODE (addr) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (addr)) + reg = new = orig; + else + { + if (reg == 0) + reg = gen_reg_rtx (Pmode); + + if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_FLAG (addr)) + || GET_CODE (addr) == LABEL_REF) + new = gen_rtx (PLUS, Pmode, pic_offset_table_rtx, orig); + else + new = gen_rtx (MEM, Pmode, + gen_rtx (PLUS, Pmode, + pic_offset_table_rtx, orig)); + + emit_move_insn (reg, new); + } + current_function_uses_pic_offset_table = 1; + return reg; + } + else if (GET_CODE (addr) == CONST || GET_CODE (addr) == PLUS) + { + rtx base; + + if (GET_CODE (addr) == CONST) + { + addr = XEXP (addr, 0); + if (GET_CODE (addr) != PLUS) + abort (); + } + + if (XEXP (addr, 0) == pic_offset_table_rtx) + return orig; + + if (reg == 0) + reg = gen_reg_rtx (Pmode); + + base = legitimize_pic_address (XEXP (addr, 0), reg); + addr = legitimize_pic_address (XEXP (addr, 1), + base == reg ? NULL_RTX : reg); + + if (GET_CODE (addr) == CONST_INT) + return plus_constant (base, INTVAL (addr)); + + if (GET_CODE (addr) == PLUS && CONSTANT_P (XEXP (addr, 1))) + { + base = gen_rtx (PLUS, Pmode, base, XEXP (addr, 0)); + addr = XEXP (addr, 1); + } + return gen_rtx (PLUS, Pmode, base, addr); + } + return new; +} + + +/* Emit insns to move operands[1] into operands[0]. */ + +void +emit_pic_move (operands, mode) + rtx *operands; + enum machine_mode mode; +{ + rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode); + + if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1])) + operands[1] = (rtx) force_reg (SImode, operands[1]); + else + operands[1] = legitimize_pic_address (operands[1], temp); +} + + +/* Try machine-dependent ways of modifying an illegitimate address + to be legitimate. If we find one, return the new, valid address. + This macro is used in only one place: `memory_address' in explow.c. + + OLDX is the address as it was before break_out_memory_refs was called. + In some cases it is useful to look at this to decide what needs to be done. + + MODE and WIN are passed so that this macro can use + GO_IF_LEGITIMATE_ADDRESS. + + It is always safe for this macro to do nothing. It exists to recognize + opportunities to optimize the output. + + For the 80386, we handle X+REG by loading X into a register R and + using R+REG. R will go in a general reg and indexing will be used. + However, if REG is a broken-out memory address or multiplication, + nothing needs to be done because REG can certainly go in a general reg. + + When -fpic is used, special handling is needed for symbolic references. + See comments by legitimize_pic_address in i386.c for details. */ + +rtx +legitimize_address (x, oldx, mode) + register rtx x; + register rtx oldx; + enum machine_mode mode; +{ + int changed = 0; + unsigned log; + + if (TARGET_DEBUG_ADDR) + { + fprintf (stderr, "\n==========\nLEGITIMIZE_ADDRESS, mode = %s\n", GET_MODE_NAME (mode)); + debug_rtx (x); + } + + if (flag_pic && SYMBOLIC_CONST (x)) + return legitimize_pic_address (x, 0); + + /* Canonicalize shifts by 0, 1, 2, 3 into multiply */ + if (GET_CODE (x) == ASHIFT + && GET_CODE (XEXP (x, 1)) == CONST_INT + && (log = (unsigned)exact_log2 (INTVAL (XEXP (x, 1)))) < 4) + { + changed = 1; + x = gen_rtx (MULT, Pmode, + force_reg (Pmode, XEXP (x, 0)), + GEN_INT (1 << log)); + } + + if (GET_CODE (x) == PLUS) + { + /* Canonicalize shifts by 0, 1, 2, 3 into multiply */ + if (GET_CODE (XEXP (x, 0)) == ASHIFT + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT + && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) < 4) + { + changed = 1; + XEXP (x, 0) = gen_rtx (MULT, Pmode, + force_reg (Pmode, XEXP (XEXP (x, 0), 0)), + GEN_INT (1 << log)); + } + + if (GET_CODE (XEXP (x, 1)) == ASHIFT + && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT + && (log = (unsigned)exact_log2 (INTVAL (XEXP (XEXP (x, 1), 1)))) < 4) + { + changed = 1; + XEXP (x, 1) = gen_rtx (MULT, Pmode, + force_reg (Pmode, XEXP (XEXP (x, 1), 0)), + GEN_INT (1 << log)); + } + + /* Put multiply first if it isn't already */ + if (GET_CODE (XEXP (x, 1)) == MULT) + { + rtx tmp = XEXP (x, 0); + XEXP (x, 0) = XEXP (x, 1); + XEXP (x, 1) = tmp; + changed = 1; + } + + /* Canonicalize (plus (mult (reg) (const)) (plus (reg) (const))) + into (plus (plus (mult (reg) (const)) (reg)) (const)). This can be + created by virtual register instantiation, register elimination, and + similar optimizations. */ + if (GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == PLUS) + { + changed = 1; + x = gen_rtx (PLUS, Pmode, + gen_rtx (PLUS, Pmode, XEXP (x, 0), XEXP (XEXP (x, 1), 0)), + XEXP (XEXP (x, 1), 1)); + } + + /* Canonicalize (plus (plus (mult (reg) (const)) (plus (reg) (const))) const) + into (plus (plus (mult (reg) (const)) (reg)) (const)). */ + else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS + && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT + && GET_CODE (XEXP (XEXP (x, 0), 1)) == PLUS + && CONSTANT_P (XEXP (x, 1))) + { + rtx constant, other; + + if (GET_CODE (XEXP (x, 1)) == CONST_INT) + { + constant = XEXP (x, 1); + other = XEXP (XEXP (XEXP (x, 0), 1), 1); + } + else if (GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 1)) == CONST_INT) + { + constant = XEXP (XEXP (XEXP (x, 0), 1), 1); + other = XEXP (x, 1); + } + else + constant = 0; + + if (constant) + { + changed = 1; + x = gen_rtx (PLUS, Pmode, + gen_rtx (PLUS, Pmode, XEXP (XEXP (x, 0), 0), + XEXP (XEXP (XEXP (x, 0), 1), 0)), + plus_constant (other, INTVAL (constant))); + } + } + + if (changed && legitimate_address_p (mode, x, FALSE)) + return x; + + if (GET_CODE (XEXP (x, 0)) == MULT) + { + changed = 1; + XEXP (x, 0) = force_operand (XEXP (x, 0), 0); + } + + if (GET_CODE (XEXP (x, 1)) == MULT) + { + changed = 1; + XEXP (x, 1) = force_operand (XEXP (x, 1), 0); + } + + if (changed + && GET_CODE (XEXP (x, 1)) == REG + && GET_CODE (XEXP (x, 0)) == REG) + return x; + + if (flag_pic && SYMBOLIC_CONST (XEXP (x, 1))) + { + changed = 1; + x = legitimize_pic_address (x, 0); + } + + if (changed && legitimate_address_p (mode, x, FALSE)) + return x; + + if (GET_CODE (XEXP (x, 0)) == REG) + { + register rtx temp = gen_reg_rtx (Pmode); + register rtx val = force_operand (XEXP (x, 1), temp); + if (val != temp) + emit_move_insn (temp, val); + + XEXP (x, 1) = temp; + return x; + } + + else if (GET_CODE (XEXP (x, 1)) == REG) + { + register rtx temp = gen_reg_rtx (Pmode); + register rtx val = force_operand (XEXP (x, 0), temp); + if (val != temp) + emit_move_insn (temp, val); + + XEXP (x, 0) = temp; + return x; + } + } + + return x; +} + + +/* Print an integer constant expression in assembler syntax. Addition + and subtraction are the only arithmetic that may appear in these + expressions. FILE is the stdio stream to write to, X is the rtx, and + CODE is the operand print code from the output string. */ + +static void +output_pic_addr_const (file, x, code) + FILE *file; + rtx x; + int code; +{ + char buf[256]; + + switch (GET_CODE (x)) + { + case PC: + if (flag_pic) + putc ('.', file); + else + abort (); + break; + + case SYMBOL_REF: + case LABEL_REF: + if (GET_CODE (x) == SYMBOL_REF) + assemble_name (file, XSTR (x, 0)); + else + { + ASM_GENERATE_INTERNAL_LABEL (buf, "L", + CODE_LABEL_NUMBER (XEXP (x, 0))); + assemble_name (asm_out_file, buf); + } + + if (GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)) + fprintf (file, "@GOTOFF(%%ebx)"); + else if (code == 'P') + fprintf (file, "@PLT"); + else if (GET_CODE (x) == LABEL_REF) + fprintf (file, "@GOTOFF"); + else if (! SYMBOL_REF_FLAG (x)) + fprintf (file, "@GOT"); + else + fprintf (file, "@GOTOFF"); + + break; + + case CODE_LABEL: + ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x)); + assemble_name (asm_out_file, buf); + break; + + case CONST_INT: + fprintf (file, "%d", INTVAL (x)); + break; + + case CONST: + /* This used to output parentheses around the expression, + but that does not work on the 386 (either ATT or BSD assembler). */ + output_pic_addr_const (file, XEXP (x, 0), code); + break; + + case CONST_DOUBLE: + if (GET_MODE (x) == VOIDmode) + { + /* We can use %d if the number is <32 bits and positive. */ + if (CONST_DOUBLE_HIGH (x) || CONST_DOUBLE_LOW (x) < 0) + fprintf (file, "0x%x%08x", + CONST_DOUBLE_HIGH (x), CONST_DOUBLE_LOW (x)); + else + fprintf (file, "%d", CONST_DOUBLE_LOW (x)); + } + else + /* We can't handle floating point constants; + PRINT_OPERAND must handle them. */ + output_operand_lossage ("floating constant misused"); + break; + + case PLUS: + /* Some assemblers need integer constants to appear last (eg masm). */ + if (GET_CODE (XEXP (x, 0)) == CONST_INT) + { + output_pic_addr_const (file, XEXP (x, 1), code); + if (INTVAL (XEXP (x, 0)) >= 0) + fprintf (file, "+"); + output_pic_addr_const (file, XEXP (x, 0), code); + } + else + { + output_pic_addr_const (file, XEXP (x, 0), code); + if (INTVAL (XEXP (x, 1)) >= 0) + fprintf (file, "+"); + output_pic_addr_const (file, XEXP (x, 1), code); + } + break; + + case MINUS: + output_pic_addr_const (file, XEXP (x, 0), code); + fprintf (file, "-"); + output_pic_addr_const (file, XEXP (x, 1), code); + break; + + default: + output_operand_lossage ("invalid expression as operand"); + } +} + +/* Meaning of CODE: + f -- float insn (print a CONST_DOUBLE as a float rather than in hex). + D,L,W,B,Q,S -- print the opcode suffix for specified size of operand. + R -- print the prefix for register names. + z -- print the opcode suffix for the size of the current operand. + * -- print a star (in certain assembler syntax) + w -- print the operand as if it's a "word" (HImode) even if it isn't. + c -- don't print special prefixes before constant operands. + J -- print the appropriate jump operand. +*/ + +void +print_operand (file, x, code) + FILE *file; + rtx x; + int code; +{ + if (code) + { + switch (code) + { + case '*': + if (USE_STAR) + putc ('*', file); + return; + + case 'L': + PUT_OP_SIZE (code, 'l', file); + return; + + case 'W': + PUT_OP_SIZE (code, 'w', file); + return; + + case 'B': + PUT_OP_SIZE (code, 'b', file); + return; + + case 'Q': + PUT_OP_SIZE (code, 'l', file); + return; + + case 'S': + PUT_OP_SIZE (code, 's', file); + return; + + case 'T': + PUT_OP_SIZE (code, 't', file); + return; + + case 'z': + /* 387 opcodes don't get size suffixes if the operands are + registers. */ + + if (STACK_REG_P (x)) + return; + + /* this is the size of op from size of operand */ + switch (GET_MODE_SIZE (GET_MODE (x))) + { + case 1: + PUT_OP_SIZE ('B', 'b', file); + return; + + case 2: + PUT_OP_SIZE ('W', 'w', file); + return; + + case 4: + if (GET_MODE (x) == SFmode) + { + PUT_OP_SIZE ('S', 's', file); + return; + } + else + PUT_OP_SIZE ('L', 'l', file); + return; + + case 12: + PUT_OP_SIZE ('T', 't', file); + return; + + case 8: + if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT) + { +#ifdef GAS_MNEMONICS + PUT_OP_SIZE ('Q', 'q', file); + return; +#else + PUT_OP_SIZE ('Q', 'l', file); /* Fall through */ +#endif + } + + PUT_OP_SIZE ('Q', 'l', file); + return; + } + + case 'b': + case 'w': + case 'k': + case 'h': + case 'y': + case 'P': + break; + + case 'J': + switch (GET_CODE (x)) + { + /* These conditions are appropriate for testing the result + of an arithmetic operation, not for a compare operation. + Cases GE, LT assume CC_NO_OVERFLOW true. All cases assume + CC_Z_IN_NOT_C false and not floating point. */ + case NE: fputs ("jne", file); return; + case EQ: fputs ("je", file); return; + case GE: fputs ("jns", file); return; + case LT: fputs ("js", file); return; + case GEU: fputs ("jmp", file); return; + case GTU: fputs ("jne", file); return; + case LEU: fputs ("je", file); return; + case LTU: fputs ("#branch never", file); return; + + /* no matching branches for GT nor LE */ + } + abort (); + + default: + { + char str[50]; + + sprintf (str, "invalid operand code `%c'", code); + output_operand_lossage (str); + } + } + } + if (GET_CODE (x) == REG) + { + PRINT_REG (x, code, file); + } + else if (GET_CODE (x) == MEM) + { + PRINT_PTR (x, file); + if (CONSTANT_ADDRESS_P (XEXP (x, 0))) + { + if (flag_pic) + output_pic_addr_const (file, XEXP (x, 0), code); + else + output_addr_const (file, XEXP (x, 0)); + } + else + output_address (XEXP (x, 0)); + } + else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode) + { + REAL_VALUE_TYPE r; long l; + REAL_VALUE_FROM_CONST_DOUBLE (r, x); + REAL_VALUE_TO_TARGET_SINGLE (r, l); + PRINT_IMMED_PREFIX (file); + fprintf (file, "0x%x", l); + } + /* These float cases don't actually occur as immediate operands. */ + else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode) + { + REAL_VALUE_TYPE r; char dstr[30]; + REAL_VALUE_FROM_CONST_DOUBLE (r, x); + REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr); + fprintf (file, "%s", dstr); + } + else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == XFmode) + { + REAL_VALUE_TYPE r; char dstr[30]; + REAL_VALUE_FROM_CONST_DOUBLE (r, x); + REAL_VALUE_TO_DECIMAL (r, "%.22e", dstr); + fprintf (file, "%s", dstr); + } + else + { + if (code != 'P') + { + if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE) + PRINT_IMMED_PREFIX (file); + else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF + || GET_CODE (x) == LABEL_REF) + PRINT_OFFSET_PREFIX (file); + } + if (flag_pic) + output_pic_addr_const (file, x, code); + else + output_addr_const (file, x); + } +} + +/* Print a memory operand whose address is ADDR. */ + +void +print_operand_address (file, addr) + FILE *file; + register rtx addr; +{ + register rtx reg1, reg2, breg, ireg; + rtx offset; + + switch (GET_CODE (addr)) + { + case REG: + ADDR_BEG (file); + fprintf (file, "%se", RP); + fputs (hi_reg_name[REGNO (addr)], file); + ADDR_END (file); + break; + + case PLUS: + reg1 = 0; + reg2 = 0; + ireg = 0; + breg = 0; + offset = 0; + if (CONSTANT_ADDRESS_P (XEXP (addr, 0))) + { + offset = XEXP (addr, 0); + addr = XEXP (addr, 1); + } + else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))) + { + offset = XEXP (addr, 1); + addr = XEXP (addr, 0); + } + if (GET_CODE (addr) != PLUS) ; + else if (GET_CODE (XEXP (addr, 0)) == MULT) + { + reg1 = XEXP (addr, 0); + addr = XEXP (addr, 1); + } + else if (GET_CODE (XEXP (addr, 1)) == MULT) + { + reg1 = XEXP (addr, 1); + addr = XEXP (addr, 0); + } + else if (GET_CODE (XEXP (addr, 0)) == REG) + { + reg1 = XEXP (addr, 0); + addr = XEXP (addr, 1); + } + else if (GET_CODE (XEXP (addr, 1)) == REG) + { + reg1 = XEXP (addr, 1); + addr = XEXP (addr, 0); + } + if (GET_CODE (addr) == REG || GET_CODE (addr) == MULT) + { + if (reg1 == 0) reg1 = addr; + else reg2 = addr; + addr = 0; + } + if (offset != 0) + { + if (addr != 0) abort (); + addr = offset; + } + if ((reg1 && GET_CODE (reg1) == MULT) + || (reg2 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg2)))) + { + breg = reg2; + ireg = reg1; + } + else if (reg1 != 0 && REGNO_OK_FOR_BASE_P (REGNO (reg1))) + { + breg = reg1; + ireg = reg2; + } + + if (ireg != 0 || breg != 0) + { + int scale = 1; + + if (addr != 0) + { + if (flag_pic) + output_pic_addr_const (file, addr, 0); + + else if (GET_CODE (addr) == LABEL_REF) + output_asm_label (addr); + + else + output_addr_const (file, addr); + } + + if (ireg != 0 && GET_CODE (ireg) == MULT) + { + scale = INTVAL (XEXP (ireg, 1)); + ireg = XEXP (ireg, 0); + } + + /* The stack pointer can only appear as a base register, + never an index register, so exchange the regs if it is wrong. */ + + if (scale == 1 && ireg && REGNO (ireg) == STACK_POINTER_REGNUM) + { + rtx tmp; + + tmp = breg; + breg = ireg; + ireg = tmp; + } + + /* output breg+ireg*scale */ + PRINT_B_I_S (breg, ireg, scale, file); + break; + } + + case MULT: + { + int scale; + if (GET_CODE (XEXP (addr, 0)) == CONST_INT) + { + scale = INTVAL (XEXP (addr, 0)); + ireg = XEXP (addr, 1); + } + else + { + scale = INTVAL (XEXP (addr, 1)); + ireg = XEXP (addr, 0); + } + output_addr_const (file, const0_rtx); + PRINT_B_I_S ((rtx) 0, ireg, scale, file); + } + break; + + default: + if (GET_CODE (addr) == CONST_INT + && INTVAL (addr) < 0x8000 + && INTVAL (addr) >= -0x8000) + fprintf (file, "%d", INTVAL (addr)); + else + { + if (flag_pic) + output_pic_addr_const (file, addr, 0); + else + output_addr_const (file, addr); + } + } +} + +/* Set the cc_status for the results of an insn whose pattern is EXP. + On the 80386, we assume that only test and compare insns, as well + as SI, HI, & DI mode ADD, SUB, NEG, AND, IOR, XOR, ASHIFT, + ASHIFTRT, and LSHIFTRT instructions set the condition codes usefully. + Also, we assume that jumps, moves and sCOND don't affect the condition + codes. All else clobbers the condition codes, by assumption. + + We assume that ALL integer add, minus, etc. instructions effect the + condition codes. This MUST be consistent with i386.md. + + We don't record any float test or compare - the redundant test & + compare check in final.c does not handle stack-like regs correctly. */ + +void +notice_update_cc (exp) + rtx exp; +{ + if (GET_CODE (exp) == SET) + { + /* Jumps do not alter the cc's. */ + if (SET_DEST (exp) == pc_rtx) + return; + /* Moving register or memory into a register: + it doesn't alter the cc's, but it might invalidate + the RTX's which we remember the cc's came from. + (Note that moving a constant 0 or 1 MAY set the cc's). */ + if (REG_P (SET_DEST (exp)) + && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM + || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<')) + { + if (cc_status.value1 + && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value1)) + cc_status.value1 = 0; + if (cc_status.value2 + && reg_overlap_mentioned_p (SET_DEST (exp), cc_status.value2)) + cc_status.value2 = 0; + return; + } + /* Moving register into memory doesn't alter the cc's. + It may invalidate the RTX's which we remember the cc's came from. */ + if (GET_CODE (SET_DEST (exp)) == MEM + && (REG_P (SET_SRC (exp)) + || GET_RTX_CLASS (GET_CODE (SET_SRC (exp))) == '<')) + { + if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM) + cc_status.value1 = 0; + if (cc_status.value2 && GET_CODE (cc_status.value2) == MEM) + cc_status.value2 = 0; + return; + } + /* Function calls clobber the cc's. */ + else if (GET_CODE (SET_SRC (exp)) == CALL) + { + CC_STATUS_INIT; + return; + } + /* Tests and compares set the cc's in predictable ways. */ + else if (SET_DEST (exp) == cc0_rtx) + { + CC_STATUS_INIT; + cc_status.value1 = SET_SRC (exp); + return; + } + /* Certain instructions effect the condition codes. */ + else if (GET_MODE (SET_SRC (exp)) == SImode + || GET_MODE (SET_SRC (exp)) == HImode + || GET_MODE (SET_SRC (exp)) == QImode) + switch (GET_CODE (SET_SRC (exp))) + { + case ASHIFTRT: case LSHIFTRT: + case ASHIFT: + /* Shifts on the 386 don't set the condition codes if the + shift count is zero. */ + if (GET_CODE (XEXP (SET_SRC (exp), 1)) != CONST_INT) + { + CC_STATUS_INIT; + break; + } + /* We assume that the CONST_INT is non-zero (this rtx would + have been deleted if it were zero. */ + + case PLUS: case MINUS: case NEG: + case AND: case IOR: case XOR: + cc_status.flags = CC_NO_OVERFLOW; + cc_status.value1 = SET_SRC (exp); + cc_status.value2 = SET_DEST (exp); + break; + + default: + CC_STATUS_INIT; + } + else + { + CC_STATUS_INIT; + } + } + else if (GET_CODE (exp) == PARALLEL + && GET_CODE (XVECEXP (exp, 0, 0)) == SET) + { + if (SET_DEST (XVECEXP (exp, 0, 0)) == pc_rtx) + return; + if (SET_DEST (XVECEXP (exp, 0, 0)) == cc0_rtx) + { + CC_STATUS_INIT; + if (stack_regs_mentioned_p (SET_SRC (XVECEXP (exp, 0, 0)))) + cc_status.flags |= CC_IN_80387; + else + cc_status.value1 = SET_SRC (XVECEXP (exp, 0, 0)); + return; + } + CC_STATUS_INIT; + } + else + { + CC_STATUS_INIT; + } +} + +/* Split one or more DImode RTL references into pairs of SImode + references. The RTL can be REG, offsettable MEM, integer constant, or + CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to + split and "num" is its length. lo_half and hi_half are output arrays + that parallel "operands". */ + +void +split_di (operands, num, lo_half, hi_half) + rtx operands[]; + int num; + rtx lo_half[], hi_half[]; +{ + while (num--) + { + if (GET_CODE (operands[num]) == REG) + { + lo_half[num] = gen_rtx (REG, SImode, REGNO (operands[num])); + hi_half[num] = gen_rtx (REG, SImode, REGNO (operands[num]) + 1); + } + else if (CONSTANT_P (operands[num])) + { + split_double (operands[num], &lo_half[num], &hi_half[num]); + } + else if (offsettable_memref_p (operands[num])) + { + lo_half[num] = operands[num]; + hi_half[num] = adj_offsettable_operand (operands[num], 4); + } + else + abort(); + } +} + +/* Return 1 if this is a valid binary operation on a 387. + OP is the expression matched, and MODE is its mode. */ + +int +binary_387_op (op, mode) + register rtx op; + enum machine_mode mode; +{ + if (mode != VOIDmode && mode != GET_MODE (op)) + return 0; + + switch (GET_CODE (op)) + { + case PLUS: + case MINUS: + case MULT: + case DIV: + return GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT; + + default: + return 0; + } +} + + +/* Return 1 if this is a valid shift or rotate operation on a 386. + OP is the expression matched, and MODE is its mode. */ + +int +shift_op (op, mode) + register rtx op; + enum machine_mode mode; +{ + rtx operand = XEXP (op, 0); + + if (mode != VOIDmode && mode != GET_MODE (op)) + return 0; + + if (GET_MODE (operand) != GET_MODE (op) + || GET_MODE_CLASS (GET_MODE (op)) != MODE_INT) + return 0; + + return (GET_CODE (op) == ASHIFT + || GET_CODE (op) == ASHIFTRT + || GET_CODE (op) == LSHIFTRT + || GET_CODE (op) == ROTATE + || GET_CODE (op) == ROTATERT); +} + +/* Return 1 if OP is COMPARE rtx with mode VOIDmode. + MODE is not used. */ + +int +VOIDmode_compare_op (op, mode) + register rtx op; + enum machine_mode mode; +{ + return GET_CODE (op) == COMPARE && GET_MODE (op) == VOIDmode; +} + +/* Output code to perform a 387 binary operation in INSN, one of PLUS, + MINUS, MULT or DIV. OPERANDS are the insn operands, where operands[3] + is the expression of the binary operation. The output may either be + emitted here, or returned to the caller, like all output_* functions. + + There is no guarantee that the operands are the same mode, as they + might be within FLOAT or FLOAT_EXTEND expressions. */ + +char * +output_387_binary_op (insn, operands) + rtx insn; + rtx *operands; +{ + rtx temp; + char *base_op; + static char buf[100]; + + switch (GET_CODE (operands[3])) + { + case PLUS: + if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT + || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) + base_op = "fiadd"; + else + base_op = "fadd"; + break; + + case MINUS: + if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT + || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) + base_op = "fisub"; + else + base_op = "fsub"; + break; + + case MULT: + if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT + || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) + base_op = "fimul"; + else + base_op = "fmul"; + break; + + case DIV: + if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT + || GET_MODE_CLASS (GET_MODE (operands[2])) == MODE_INT) + base_op = "fidiv"; + else + base_op = "fdiv"; + break; + + default: + abort (); + } + + strcpy (buf, base_op); + + switch (GET_CODE (operands[3])) + { + case MULT: + case PLUS: + if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2])) + { + temp = operands[2]; + operands[2] = operands[1]; + operands[1] = temp; + } + + if (GET_CODE (operands[2]) == MEM) + return strcat (buf, AS1 (%z2,%2)); + + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1))); + RET; + } + else if (NON_STACK_REG_P (operands[2])) + { + output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1))); + RET; + } + + if (find_regno_note (insn, REG_DEAD, REGNO (operands[2]))) + return strcat (buf, AS2 (p,%2,%0)); + + if (STACK_TOP_P (operands[0])) + return strcat (buf, AS2C (%y2,%0)); + else + return strcat (buf, AS2C (%2,%0)); + + case MINUS: + case DIV: + if (GET_CODE (operands[1]) == MEM) + return strcat (buf, AS1 (r%z1,%1)); + + if (GET_CODE (operands[2]) == MEM) + return strcat (buf, AS1 (%z2,%2)); + + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], strcat (buf, AS1 (r%z0,%1))); + RET; + } + else if (NON_STACK_REG_P (operands[2])) + { + output_op_from_reg (operands[2], strcat (buf, AS1 (%z0,%1))); + RET; + } + + if (! STACK_REG_P (operands[1]) || ! STACK_REG_P (operands[2])) + abort (); + + if (find_regno_note (insn, REG_DEAD, REGNO (operands[2]))) + return strcat (buf, AS2 (rp,%2,%0)); + + if (find_regno_note (insn, REG_DEAD, REGNO (operands[1]))) + return strcat (buf, AS2 (p,%1,%0)); + + if (STACK_TOP_P (operands[0])) + { + if (STACK_TOP_P (operands[1])) + return strcat (buf, AS2C (%y2,%0)); + else + return strcat (buf, AS2 (r,%y1,%0)); + } + else if (STACK_TOP_P (operands[1])) + return strcat (buf, AS2C (%1,%0)); + else + return strcat (buf, AS2 (r,%2,%0)); + + default: + abort (); + } +} + +/* Output code for INSN to convert a float to a signed int. OPERANDS + are the insn operands. The output may be SFmode or DFmode and the + input operand may be SImode or DImode. As a special case, make sure + that the 387 stack top dies if the output mode is DImode, because the + hardware requires this. */ + +char * +output_fix_trunc (insn, operands) + rtx insn; + rtx *operands; +{ + int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + rtx xops[2]; + + if (! STACK_TOP_P (operands[1]) || + (GET_MODE (operands[0]) == DImode && ! stack_top_dies)) + abort (); + + xops[0] = GEN_INT (12); + xops[1] = operands[4]; + + output_asm_insn (AS1 (fnstc%W2,%2), operands); + output_asm_insn (AS2 (mov%L2,%2,%4), operands); + output_asm_insn (AS2 (mov%B1,%0,%h1), xops); + output_asm_insn (AS2 (mov%L4,%4,%3), operands); + output_asm_insn (AS1 (fldc%W3,%3), operands); + + if (NON_STACK_REG_P (operands[0])) + output_to_reg (operands[0], stack_top_dies); + else if (GET_CODE (operands[0]) == MEM) + { + if (stack_top_dies) + output_asm_insn (AS1 (fistp%z0,%0), operands); + else + output_asm_insn (AS1 (fist%z0,%0), operands); + } + else + abort (); + + return AS1 (fldc%W2,%2); +} + +/* Output code for INSN to compare OPERANDS. The two operands might + not have the same mode: one might be within a FLOAT or FLOAT_EXTEND + expression. If the compare is in mode CCFPEQmode, use an opcode that + will not fault if a qNaN is present. */ + +char * +output_float_compare (insn, operands) + rtx insn; + rtx *operands; +{ + int stack_top_dies; + rtx body = XVECEXP (PATTERN (insn), 0, 0); + int unordered_compare = GET_MODE (SET_SRC (body)) == CCFPEQmode; + + if (! STACK_TOP_P (operands[0])) + abort (); + + stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + + if (STACK_REG_P (operands[1]) + && stack_top_dies + && find_regno_note (insn, REG_DEAD, REGNO (operands[1])) + && REGNO (operands[1]) != FIRST_STACK_REG) + { + /* If both the top of the 387 stack dies, and the other operand + is also a stack register that dies, then this must be a + `fcompp' float compare */ + + if (unordered_compare) + output_asm_insn ("fucompp", operands); + else + output_asm_insn ("fcompp", operands); + } + else + { + static char buf[100]; + + /* Decide if this is the integer or float compare opcode, or the + unordered float compare. */ + + if (unordered_compare) + strcpy (buf, "fucom"); + else if (GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_FLOAT) + strcpy (buf, "fcom"); + else + strcpy (buf, "ficom"); + + /* Modify the opcode if the 387 stack is to be popped. */ + + if (stack_top_dies) + strcat (buf, "p"); + + if (NON_STACK_REG_P (operands[1])) + output_op_from_reg (operands[1], strcat (buf, AS1 (%z0,%1))); + else + output_asm_insn (strcat (buf, AS1 (%z1,%y1)), operands); + } + + /* Now retrieve the condition code. */ + + return output_fp_cc0_set (insn); +} + +/* Output opcodes to transfer the results of FP compare or test INSN + from the FPU to the CPU flags. If TARGET_IEEE_FP, ensure that if the + result of the compare or test is unordered, no comparison operator + succeeds except NE. Return an output template, if any. */ + +char * +output_fp_cc0_set (insn) + rtx insn; +{ + rtx xops[3]; + rtx unordered_label; + rtx next; + enum rtx_code code; + + xops[0] = gen_rtx (REG, HImode, 0); + output_asm_insn (AS1 (fnsts%W0,%0), xops); + + if (! TARGET_IEEE_FP) + return "sahf"; + + next = next_cc0_user (insn); + if (next == NULL_RTX) + abort (); + + if (GET_CODE (next) == JUMP_INSN + && GET_CODE (PATTERN (next)) == SET + && SET_DEST (PATTERN (next)) == pc_rtx + && GET_CODE (SET_SRC (PATTERN (next))) == IF_THEN_ELSE) + { + code = GET_CODE (XEXP (SET_SRC (PATTERN (next)), 0)); + } + else if (GET_CODE (PATTERN (next)) == SET) + { + code = GET_CODE (SET_SRC (PATTERN (next))); + } + else + abort (); + + xops[0] = gen_rtx (REG, QImode, 0); + + switch (code) + { + case GT: + xops[1] = GEN_INT (0x45); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + /* je label */ + break; + + case LT: + xops[1] = GEN_INT (0x45); + xops[2] = GEN_INT (0x01); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); + /* je label */ + break; + + case GE: + xops[1] = GEN_INT (0x05); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + /* je label */ + break; + + case LE: + xops[1] = GEN_INT (0x45); + xops[2] = GEN_INT (0x40); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + output_asm_insn (AS1 (dec%B0,%h0), xops); + output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); + /* jb label */ + break; + + case EQ: + xops[1] = GEN_INT (0x45); + xops[2] = GEN_INT (0x40); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + output_asm_insn (AS2 (cmp%B0,%2,%h0), xops); + /* je label */ + break; + + case NE: + xops[1] = GEN_INT (0x44); + xops[2] = GEN_INT (0x40); + output_asm_insn (AS2 (and%B0,%1,%h0), xops); + output_asm_insn (AS2 (xor%B0,%2,%h0), xops); + /* jne label */ + break; + + case GTU: + case LTU: + case GEU: + case LEU: + default: + abort (); + } + RET; +} + +#define MAX_386_STACK_LOCALS 2 + +static rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS]; + +/* Define the structure for the machine field in struct function. */ +struct machine_function +{ + rtx i386_stack_locals[(int) MAX_MACHINE_MODE][MAX_386_STACK_LOCALS]; +}; + +/* Functions to save and restore i386_stack_locals. + These will be called, via pointer variables, + from push_function_context and pop_function_context. */ + +void +save_386_machine_status (p) + struct function *p; +{ + p->machine = (struct machine_function *) xmalloc (sizeof i386_stack_locals); + bcopy ((char *) i386_stack_locals, (char *) p->machine->i386_stack_locals, + sizeof i386_stack_locals); +} + +void +restore_386_machine_status (p) + struct function *p; +{ + bcopy ((char *) p->machine->i386_stack_locals, (char *) i386_stack_locals, + sizeof i386_stack_locals); + free (p->machine); +} + +/* Clear stack slot assignments remembered from previous functions. + This is called from INIT_EXPANDERS once before RTL is emitted for each + function. */ + +void +clear_386_stack_locals () +{ + enum machine_mode mode; + int n; + + for (mode = VOIDmode; (int) mode < (int) MAX_MACHINE_MODE; + mode = (enum machine_mode) ((int) mode + 1)) + for (n = 0; n < MAX_386_STACK_LOCALS; n++) + i386_stack_locals[(int) mode][n] = NULL_RTX; + + /* Arrange to save and restore i386_stack_locals around nested functions. */ + save_machine_status = save_386_machine_status; + restore_machine_status = restore_386_machine_status; +} + +/* Return a MEM corresponding to a stack slot with mode MODE. + Allocate a new slot if necessary. + + The RTL for a function can have several slots available: N is + which slot to use. */ + +rtx +assign_386_stack_local (mode, n) + enum machine_mode mode; + int n; +{ + if (n < 0 || n >= MAX_386_STACK_LOCALS) + abort (); + + if (i386_stack_locals[(int) mode][n] == NULL_RTX) + i386_stack_locals[(int) mode][n] + = assign_stack_local (mode, GET_MODE_SIZE (mode), 0); + + return i386_stack_locals[(int) mode][n]; +} diff --git a/contrib/gcc/config/i386/i386.h b/contrib/gcc/config/i386/i386.h new file mode 100644 index 0000000..b00b0e5 --- /dev/null +++ b/contrib/gcc/config/i386/i386.h @@ -0,0 +1,1934 @@ +/* Definitions of target machine for GNU compiler for Intel X86 + (386, 486, Pentium). + Copyright (C) 1988, 1992, 1994, 1995 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + + +/* The purpose of this file is to define the characteristics of the i386, + independent of assembler syntax or operating system. + + Three other files build on this one to describe a specific assembler syntax: + bsd386.h, att386.h, and sun386.h. + + The actual tm.h file for a particular system should include + this file, and then the file for the appropriate assembler syntax. + + Many macros that specify assembler syntax are omitted entirely from + this file because they really belong in the files for particular + assemblers. These include AS1, AS2, AS3, RP, IP, LPREFIX, L_SIZE, + PUT_OP_SIZE, USE_STAR, ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, + PRINT_B_I_S, and many that start with ASM_ or end in ASM_OP. */ + +/* Names to predefine in the preprocessor for this target machine. */ + +#define I386 1 + +/* Stubs for half-pic support if not OSF/1 reference platform. */ + +#ifndef HALF_PIC_P +#define HALF_PIC_P() 0 +#define HALF_PIC_NUMBER_PTRS 0 +#define HALF_PIC_NUMBER_REFS 0 +#define HALF_PIC_ENCODE(DECL) +#define HALF_PIC_DECLARE(NAME) +#define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.") +#define HALF_PIC_ADDRESS_P(X) 0 +#define HALF_PIC_PTR(X) X +#define HALF_PIC_FINISH(STREAM) +#endif + +/* Run-time compilation parameters selecting different hardware subsets. */ + +extern int target_flags; + +/* Macros used in the machine description to test the flags. */ + +/* configure can arrange to make this 2, to force a 486. */ +#ifndef TARGET_CPU_DEFAULT +#define TARGET_CPU_DEFAULT 0 +#endif + +/* Masks for the -m switches */ +#define MASK_80387 000000000001 /* Hardware floating point */ +#define MASK_486 000000000002 /* 80486 specific */ +#define MASK_NOTUSED1 000000000004 /* bit not currently used */ +#define MASK_RTD 000000000010 /* Use ret that pops args */ +#define MASK_ALIGN_DOUBLE 000000000020 /* align doubles to 2 word boundary */ +#define MASK_SVR3_SHLIB 000000000040 /* Uninit locals into bss */ +#define MASK_IEEE_FP 000000000100 /* IEEE fp comparisons */ +#define MASK_FLOAT_RETURNS 000000000200 /* Return float in st(0) */ +#define MASK_NO_FANCY_MATH_387 000000000400 /* Disable sin, cos, sqrt */ + + /* Temporary codegen switches */ +#define MASK_DEBUG_ADDR 000001000000 /* Debug GO_IF_LEGITIMATE_ADDRESS */ +#define MASK_NO_WIDE_MULTIPLY 000002000000 /* Disable 32x32->64 multiplies */ +#define MASK_NO_MOVE 000004000000 /* Don't generate mem->mem */ +#define MASK_DEBUG_ARG 000010000000 /* Debug function_arg */ + +/* Use the floating point instructions */ +#define TARGET_80387 (target_flags & MASK_80387) + +/* Compile using ret insn that pops args. + This will not work unless you use prototypes at least + for all functions that can take varying numbers of args. */ +#define TARGET_RTD (target_flags & MASK_RTD) + +/* Align doubles to a two word boundary. This breaks compatibility with + the published ABI's for structures containing doubles, but produces + faster code on the pentium. */ +#define TARGET_ALIGN_DOUBLE (target_flags & MASK_ALIGN_DOUBLE) + +/* Put uninitialized locals into bss, not data. + Meaningful only on svr3. */ +#define TARGET_SVR3_SHLIB (target_flags & MASK_SVR3_SHLIB) + +/* Use IEEE floating point comparisons. These handle correctly the cases + where the result of a comparison is unordered. Normally SIGFPE is + generated in such cases, in which case this isn't needed. */ +#define TARGET_IEEE_FP (target_flags & MASK_IEEE_FP) + +/* Functions that return a floating point value may return that value + in the 387 FPU or in 386 integer registers. If set, this flag causes + the 387 to be used, which is compatible with most calling conventions. */ +#define TARGET_FLOAT_RETURNS_IN_80387 (target_flags & MASK_FLOAT_RETURNS) + +/* Disable generation of FP sin, cos and sqrt operations for 387. + This is because FreeBSD lacks these in the math-emulator-code */ +#define TARGET_NO_FANCY_MATH_387 (target_flags & MASK_NO_FANCY_MATH_387) + +/* Temporary switches for tuning code generation */ + +/* Disable 32x32->64 bit multiplies that are used for long long multiplies + and division by constants, but sometimes cause reload problems. */ +#define TARGET_NO_WIDE_MULTIPLY (target_flags & MASK_NO_WIDE_MULTIPLY) +#define TARGET_WIDE_MULTIPLY (!TARGET_NO_WIDE_MULTIPLY) + +/* Debug GO_IF_LEGITIMATE_ADDRESS */ +#define TARGET_DEBUG_ADDR (target_flags & MASK_DEBUG_ADDR) + +/* Debug FUNCTION_ARG macros */ +#define TARGET_DEBUG_ARG (target_flags & MASK_DEBUG_ARG) + +/* Hack macros for tuning code generation */ +#define TARGET_MOVE ((target_flags & MASK_NO_MOVE) == 0) /* Don't generate memory->memory */ + +/* Specific hardware switches */ +#define TARGET_486 (target_flags & MASK_486) /* 80486DX, 80486SX, 80486DX[24] */ +#define TARGET_386 (!TARGET_486) /* 80386 */ + +#define TARGET_SWITCHES \ +{ { "80387", MASK_80387 }, \ + { "no-80387", -MASK_80387 }, \ + { "hard-float", MASK_80387 }, \ + { "soft-float", -MASK_80387 }, \ + { "no-soft-float", MASK_80387 }, \ + { "386", -MASK_486 }, \ + { "no-386", MASK_486 }, \ + { "486", MASK_486 }, \ + { "no-486", -MASK_486 }, \ + { "rtd", MASK_RTD }, \ + { "no-rtd", -MASK_RTD }, \ + { "align-double", MASK_ALIGN_DOUBLE }, \ + { "no-align-double", -MASK_ALIGN_DOUBLE }, \ + { "svr3-shlib", MASK_SVR3_SHLIB }, \ + { "no-svr3-shlib", -MASK_SVR3_SHLIB }, \ + { "ieee-fp", MASK_IEEE_FP }, \ + { "no-ieee-fp", -MASK_IEEE_FP }, \ + { "fp-ret-in-387", MASK_FLOAT_RETURNS }, \ + { "no-fp-ret-in-387", -MASK_FLOAT_RETURNS }, \ + { "no-fancy-math-387", MASK_NO_FANCY_MATH_387 }, \ + { "fancy-math-387", -MASK_NO_FANCY_MATH_387 }, \ + { "no-wide-multiply", MASK_NO_WIDE_MULTIPLY }, \ + { "wide-multiply", -MASK_NO_WIDE_MULTIPLY }, \ + { "debug-addr", MASK_DEBUG_ADDR }, \ + { "no-debug-addr", -MASK_DEBUG_ADDR }, \ + { "move", -MASK_NO_MOVE }, \ + { "no-move", MASK_NO_MOVE }, \ + { "debug-arg", MASK_DEBUG_ARG }, \ + { "no-debug-arg", -MASK_DEBUG_ARG }, \ + SUBTARGET_SWITCHES \ + { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT}} + +/* This macro is similar to `TARGET_SWITCHES' but defines names of + command options that have values. Its definition is an + initializer with a subgrouping for each command option. + + Each subgrouping contains a string constant, that defines the + fixed part of the option name, and the address of a variable. The + variable, type `char *', is set to the variable part of the given + option if the fixed part matches. The actual option name is made + by appending `-m' to the specified name. */ +#define TARGET_OPTIONS \ +{ { "reg-alloc=", &i386_reg_alloc_order }, \ + { "regparm=", &i386_regparm_string }, \ + { "align-loops=", &i386_align_loops_string }, \ + { "align-jumps=", &i386_align_jumps_string }, \ + { "align-functions=", &i386_align_funcs_string }, \ + SUBTARGET_OPTIONS \ +} + +/* Sometimes certain combinations of command options do not make + sense on a particular target machine. You can define a macro + `OVERRIDE_OPTIONS' to take account of this. This macro, if + defined, is executed once just after all the command options have + been parsed. + + Don't use this macro to turn on various extra optimizations for + `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ + +#define OVERRIDE_OPTIONS override_options () + +/* These are meant to be redefined in the host dependent files */ +#define SUBTARGET_SWITCHES +#define SUBTARGET_OPTIONS + + +/* target machine storage layout */ + +/* Define for XFmode extended real floating point support. + This will automatically cause REAL_ARITHMETIC to be defined. */ +#define LONG_DOUBLE_TYPE_SIZE 96 + +/* Define if you don't want extended real, but do want to use the + software floating point emulator for REAL_ARITHMETIC and + decimal <-> binary conversion. */ +/* #define REAL_ARITHMETIC */ + +/* Define this if most significant byte of a word is the lowest numbered. */ +/* That is true on the 80386. */ + +#define BITS_BIG_ENDIAN 0 + +/* Define this if most significant byte of a word is the lowest numbered. */ +/* That is not true on the 80386. */ +#define BYTES_BIG_ENDIAN 0 + +/* Define this if most significant word of a multiword number is the lowest + numbered. */ +/* Not true for 80386 */ +#define WORDS_BIG_ENDIAN 0 + +/* number of bits in an addressable storage unit */ +#define BITS_PER_UNIT 8 + +/* Width in bits of a "word", which is the contents of a machine register. + Note that this is not necessarily the width of data type `int'; + if using 16-bit ints on a 80386, this would still be 32. + But on a machine with 16-bit registers, this would be 16. */ +#define BITS_PER_WORD 32 + +/* Width of a word, in units (bytes). */ +#define UNITS_PER_WORD 4 + +/* Width in bits of a pointer. + See also the macro `Pmode' defined below. */ +#define POINTER_SIZE 32 + +/* Allocation boundary (in *bits*) for storing arguments in argument list. */ +#define PARM_BOUNDARY 32 + +/* Boundary (in *bits*) on which stack pointer should be aligned. */ +#define STACK_BOUNDARY 32 + +/* Allocation boundary (in *bits*) for the code of a function. + For i486, we get better performance by aligning to a cache + line (i.e. 16 byte) boundary. */ +#define FUNCTION_BOUNDARY (1 << (i386_align_funcs + 3)) + +/* Alignment of field after `int : 0' in a structure. */ + +#define EMPTY_FIELD_BOUNDARY 32 + +/* Minimum size in bits of the largest boundary to which any + and all fundamental data types supported by the hardware + might need to be aligned. No data type wants to be aligned + rounder than this. The i386 supports 64-bit floating point + quantities, but these can be aligned on any 32-bit boundary. + The published ABIs say that doubles should be aligned on word + boundaries, but the Pentium gets better performance with them + aligned on 64 bit boundaries. */ +#define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32) + +/* Set this non-zero if move instructions will actually fail to work + when given unaligned data. */ +#define STRICT_ALIGNMENT 0 + +/* If bit field type is int, don't let it cross an int, + and give entire struct the alignment of an int. */ +/* Required on the 386 since it doesn't have bitfield insns. */ +#define PCC_BITFIELD_TYPE_MATTERS 1 + +/* Maximum power of 2 that code can be aligned to. */ +#define MAX_CODE_ALIGN 6 /* 64 byte alignment */ + +/* Align loop starts for optimal branching. */ +#define ASM_OUTPUT_LOOP_ALIGN(FILE) ASM_OUTPUT_ALIGN (FILE, i386_align_loops) + +/* This is how to align an instruction for optimal branching. + On i486 we'll get better performance by aligning on a + cache line (i.e. 16 byte) boundary. */ +#define ASM_OUTPUT_ALIGN_CODE(FILE) ASM_OUTPUT_ALIGN ((FILE), i386_align_jumps) + + +/* Standard register usage. */ + +/* This processor has special stack-like registers. See reg-stack.c + for details. */ + +#define STACK_REGS + +/* Number of actual hardware registers. + The hardware registers are assigned numbers for the compiler + from 0 to just below FIRST_PSEUDO_REGISTER. + All registers that the compiler knows about must be given numbers, + even those that are not normally considered general registers. + + In the 80386 we give the 8 general purpose registers the numbers 0-7. + We number the floating point registers 8-15. + Note that registers 0-7 can be accessed as a short or int, + while only 0-3 may be used with byte `mov' instructions. + + Reg 16 does not correspond to any hardware register, but instead + appears in the RTL as an argument pointer prior to reload, and is + eliminated during reloading in favor of either the stack or frame + pointer. */ + +#define FIRST_PSEUDO_REGISTER 17 + +/* 1 for registers that have pervasive standard uses + and are not available for the register allocator. + On the 80386, the stack pointer is such, as is the arg pointer. */ +#define FIXED_REGISTERS \ +/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \ +{ 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1 } + +/* 1 for registers not available across function calls. + These must include the FIXED_REGISTERS and also any + registers that can be used without being saved. + The latter must include the registers where values are returned + and the register where structure-value addresses are passed. + Aside from that, you can include as many other registers as you like. */ + +#define CALL_USED_REGISTERS \ +/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \ +{ 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } + +/* Order in which to allocate registers. Each register must be + listed once, even those in FIXED_REGISTERS. List frame pointer + late and fixed registers last. Note that, in general, we prefer + registers listed in CALL_USED_REGISTERS, keeping the others + available for storage of persistent values. + + Three different versions of REG_ALLOC_ORDER have been tried: + + If the order is edx, ecx, eax, ... it produces a slightly faster compiler, + but slower code on simple functions returning values in eax. + + If the order is eax, ecx, edx, ... it causes reload to abort when compiling + perl 4.036 due to not being able to create a DImode register (to hold a 2 + word union). + + If the order is eax, edx, ecx, ... it produces better code for simple + functions, and a slightly slower compiler. Users complained about the code + generated by allocating edx first, so restore the 'natural' order of things. */ + +#define REG_ALLOC_ORDER \ +/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \ +{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 } + +/* A C statement (sans semicolon) to choose the order in which to + allocate hard registers for pseudo-registers local to a basic + block. + + Store the desired register order in the array `reg_alloc_order'. + Element 0 should be the register to allocate first; element 1, the + next register; and so on. + + The macro body should not assume anything about the contents of + `reg_alloc_order' before execution of the macro. + + On most machines, it is not necessary to define this macro. */ + +#define ORDER_REGS_FOR_LOCAL_ALLOC order_regs_for_local_alloc () + +/* Macro to conditionally modify fixed_regs/call_used_regs. */ +#define CONDITIONAL_REGISTER_USAGE \ + { \ + if (flag_pic) \ + { \ + fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ + call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ + } \ + if (! TARGET_80387 && ! TARGET_FLOAT_RETURNS_IN_80387) \ + { \ + int i; \ + HARD_REG_SET x; \ + COPY_HARD_REG_SET (x, reg_class_contents[(int)FLOAT_REGS]); \ + for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ + if (TEST_HARD_REG_BIT (x, i)) \ + fixed_regs[i] = call_used_regs[i] = 1; \ + } \ + } + +/* Return number of consecutive hard regs needed starting at reg REGNO + to hold something of mode MODE. + This is ordinarily the length in words of a value of mode MODE + but can be less for certain modes in special long registers. + + Actually there are no two word move instructions for consecutive + registers. And only registers 0-3 may have mov byte instructions + applied to them. + */ + +#define HARD_REGNO_NREGS(REGNO, MODE) \ + (FP_REGNO_P (REGNO) ? 1 \ + : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) + +/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. + On the 80386, the first 4 cpu registers can hold any mode + while the floating point registers may hold only floating point. + Make it clear that the fp regs could not hold a 16-byte float. */ + +/* The casts to int placate a compiler on a microvax, + for cross-compiler testing. */ + +#define HARD_REGNO_MODE_OK(REGNO, MODE) \ + ((REGNO) < 2 ? 1 \ + : (REGNO) < 4 ? 1 \ + : FP_REGNO_P (REGNO) \ + ? (((int) GET_MODE_CLASS (MODE) == (int) MODE_FLOAT \ + || (int) GET_MODE_CLASS (MODE) == (int) MODE_COMPLEX_FLOAT) \ + && GET_MODE_UNIT_SIZE (MODE) <= 12) \ + : (int) (MODE) != (int) QImode) + +/* Value is 1 if it is a good idea to tie two pseudo registers + when one has mode MODE1 and one has mode MODE2. + If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, + for any hard reg, then this must be 0 for correct output. */ + +#define MODES_TIEABLE_P(MODE1, MODE2) ((MODE1) == (MODE2)) + +/* A C expression returning the cost of moving data from a register of class + CLASS1 to one of CLASS2. + + On the i386, copying between floating-point and fixed-point + registers is expensive. */ + +#define REGISTER_MOVE_COST(CLASS1, CLASS2) \ + (((FLOAT_CLASS_P (CLASS1) && ! FLOAT_CLASS_P (CLASS2)) \ + || (! FLOAT_CLASS_P (CLASS1) && FLOAT_CLASS_P (CLASS2))) ? 10 \ + : 2) + +/* Specify the registers used for certain standard purposes. + The values of these macros are register numbers. */ + +/* on the 386 the pc register is %eip, and is not usable as a general + register. The ordinary mov instructions won't work */ +/* #define PC_REGNUM */ + +/* Register to use for pushing function arguments. */ +#define STACK_POINTER_REGNUM 7 + +/* Base register for access to local variables of the function. */ +#define FRAME_POINTER_REGNUM 6 + +/* First floating point reg */ +#define FIRST_FLOAT_REG 8 + +/* First & last stack-like regs */ +#define FIRST_STACK_REG FIRST_FLOAT_REG +#define LAST_STACK_REG (FIRST_FLOAT_REG + 7) + +/* Value should be nonzero if functions must have frame pointers. + Zero means the frame pointer need not be set up (and parms + may be accessed via the stack pointer) in functions that seem suitable. + This is computed in `reload', in reload1.c. */ +#define FRAME_POINTER_REQUIRED 0 + +/* Base register for access to arguments of the function. */ +#define ARG_POINTER_REGNUM 16 + +/* Register in which static-chain is passed to a function. */ +#define STATIC_CHAIN_REGNUM 2 + +/* Register to hold the addressing base for position independent + code access to data items. */ +#define PIC_OFFSET_TABLE_REGNUM 3 + +/* Register in which address to store a structure value + arrives in the function. On the 386, the prologue + copies this from the stack to register %eax. */ +#define STRUCT_VALUE_INCOMING 0 + +/* Place in which caller passes the structure value address. + 0 means push the value on the stack like an argument. */ +#define STRUCT_VALUE 0 + +/* A C expression which can inhibit the returning of certain function + values in registers, based on the type of value. A nonzero value + says to return the function value in memory, just as large + structures are always returned. Here TYPE will be a C expression + of type `tree', representing the data type of the value. + + Note that values of mode `BLKmode' must be explicitly handled by + this macro. Also, the option `-fpcc-struct-return' takes effect + regardless of this macro. On most systems, it is possible to + leave the macro undefined; this causes a default definition to be + used, whose value is the constant 1 for `BLKmode' values, and 0 + otherwise. + + Do not use this macro to indicate that structures and unions + should always be returned in memory. You should instead use + `DEFAULT_PCC_STRUCT_RETURN' to indicate this. */ + +#define RETURN_IN_MEMORY(TYPE) \ + ((TYPE_MODE (TYPE) == BLKmode) || int_size_in_bytes (TYPE) > 12) + + +/* Define the classes of registers for register constraints in the + machine description. Also define ranges of constants. + + One of the classes must always be named ALL_REGS and include all hard regs. + If there is more than one class, another class must be named NO_REGS + and contain no registers. + + The name GENERAL_REGS must be the name of a class (or an alias for + another name such as ALL_REGS). This is the class of registers + that is allowed by "g" or "r" in a register constraint. + Also, registers outside this class are allocated only when + instructions express preferences for them. + + The classes must be numbered in nondecreasing order; that is, + a larger-numbered class must never be contained completely + in a smaller-numbered class. + + For any two classes, it is very desirable that there be another + class that represents their union. + + It might seem that class BREG is unnecessary, since no useful 386 + opcode needs reg %ebx. But some systems pass args to the OS in ebx, + and the "b" register constraint is useful in asms for syscalls. */ + +enum reg_class +{ + NO_REGS, + AREG, DREG, CREG, BREG, + AD_REGS, /* %eax/%edx for DImode */ + Q_REGS, /* %eax %ebx %ecx %edx */ + SIREG, DIREG, + INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ + GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ + FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ + FLOAT_REGS, + ALL_REGS, LIM_REG_CLASSES +}; + +#define N_REG_CLASSES (int) LIM_REG_CLASSES + +#define FLOAT_CLASS_P(CLASS) (reg_class_subset_p (CLASS, FLOAT_REGS)) + +/* Give names of register classes as strings for dump file. */ + +#define REG_CLASS_NAMES \ +{ "NO_REGS", \ + "AREG", "DREG", "CREG", "BREG", \ + "AD_REGS", \ + "Q_REGS", \ + "SIREG", "DIREG", \ + "INDEX_REGS", \ + "GENERAL_REGS", \ + "FP_TOP_REG", "FP_SECOND_REG", \ + "FLOAT_REGS", \ + "ALL_REGS" } + +/* Define which registers fit in which classes. + This is an initializer for a vector of HARD_REG_SET + of length N_REG_CLASSES. */ + +#define REG_CLASS_CONTENTS \ +{ 0, \ + 0x1, 0x2, 0x4, 0x8, /* AREG, DREG, CREG, BREG */ \ + 0x3, /* AD_REGS */ \ + 0xf, /* Q_REGS */ \ + 0x10, 0x20, /* SIREG, DIREG */ \ + 0x07f, /* INDEX_REGS */ \ + 0x100ff, /* GENERAL_REGS */ \ + 0x0100, 0x0200, /* FP_TOP_REG, FP_SECOND_REG */ \ + 0xff00, /* FLOAT_REGS */ \ + 0x1ffff } + +/* The same information, inverted: + Return the class number of the smallest class containing + reg number REGNO. This could be a conditional expression + or could index an array. */ + +#define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) + +/* When defined, the compiler allows registers explicitly used in the + rtl to be used as spill registers but prevents the compiler from + extending the lifetime of these registers. */ + +#define SMALL_REGISTER_CLASSES + +#define QI_REG_P(X) \ + (REG_P (X) && REGNO (X) < 4) +#define NON_QI_REG_P(X) \ + (REG_P (X) && REGNO (X) >= 4 && REGNO (X) < FIRST_PSEUDO_REGISTER) + +#define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) +#define FP_REGNO_P(n) ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) + +#define STACK_REG_P(xop) (REG_P (xop) && \ + REGNO (xop) >= FIRST_STACK_REG && \ + REGNO (xop) <= LAST_STACK_REG) + +#define NON_STACK_REG_P(xop) (REG_P (xop) && ! STACK_REG_P (xop)) + +#define STACK_TOP_P(xop) (REG_P (xop) && REGNO (xop) == FIRST_STACK_REG) + +/* Try to maintain the accuracy of the death notes for regs satisfying the + following. Important for stack like regs, to know when to pop. */ + +/* #define PRESERVE_DEATH_INFO_REGNO_P(x) FP_REGNO_P(x) */ + +/* 1 if register REGNO can magically overlap other regs. + Note that nonzero values work only in very special circumstances. */ + +/* #define OVERLAPPING_REGNO_P(REGNO) FP_REGNO_P (REGNO) */ + +/* The class value for index registers, and the one for base regs. */ + +#define INDEX_REG_CLASS INDEX_REGS +#define BASE_REG_CLASS GENERAL_REGS + +/* Get reg_class from a letter such as appears in the machine description. */ + +#define REG_CLASS_FROM_LETTER(C) \ + ((C) == 'r' ? GENERAL_REGS : \ + (C) == 'q' ? Q_REGS : \ + (C) == 'f' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ + ? FLOAT_REGS \ + : NO_REGS) : \ + (C) == 't' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ + ? FP_TOP_REG \ + : NO_REGS) : \ + (C) == 'u' ? (TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 \ + ? FP_SECOND_REG \ + : NO_REGS) : \ + (C) == 'a' ? AREG : \ + (C) == 'b' ? BREG : \ + (C) == 'c' ? CREG : \ + (C) == 'd' ? DREG : \ + (C) == 'A' ? AD_REGS : \ + (C) == 'D' ? DIREG : \ + (C) == 'S' ? SIREG : NO_REGS) + +/* The letters I, J, K, L and M in a register constraint string + can be used to stand for particular ranges of immediate operands. + This macro defines what the ranges are. + C is the letter, and VALUE is a constant value. + Return 1 if VALUE is in the range specified by C. + + I is for non-DImode shifts. + J is for DImode shifts. + K and L are for an `andsi' optimization. + M is for shifts that can be executed by the "lea" opcode. + */ + +#define CONST_OK_FOR_LETTER_P(VALUE, C) \ + ((C) == 'I' ? (VALUE) >= 0 && (VALUE) <= 31 : \ + (C) == 'J' ? (VALUE) >= 0 && (VALUE) <= 63 : \ + (C) == 'K' ? (VALUE) == 0xff : \ + (C) == 'L' ? (VALUE) == 0xffff : \ + (C) == 'M' ? (VALUE) >= 0 && (VALUE) <= 3 : \ + (C) == 'N' ? (VALUE) >= 0 && (VALUE) <= 255 :\ + 0) + +/* Similar, but for floating constants, and defining letters G and H. + Here VALUE is the CONST_DOUBLE rtx itself. We allow constants even if + TARGET_387 isn't set, because the stack register converter may need to + load 0.0 into the function value register. */ + +#define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ + ((C) == 'G' ? standard_80387_constant_p (VALUE) : 0) + +/* Place additional restrictions on the register class to use when it + is necessary to be able to hold a value of mode MODE in a reload + register for which class CLASS would ordinarily be used. */ + +#define LIMIT_RELOAD_CLASS(MODE, CLASS) \ + ((MODE) == QImode && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS) \ + ? Q_REGS : (CLASS)) + +/* Given an rtx X being reloaded into a reg required to be + in class CLASS, return the class of reg to actually use. + In general this is just CLASS; but on some machines + in some cases it is preferable to use a more restrictive class. + On the 80386 series, we prevent floating constants from being + reloaded into floating registers (since no move-insn can do that) + and we ensure that QImodes aren't reloaded into the esi or edi reg. */ + +/* Put float CONST_DOUBLE in the constant pool instead of fp regs. + QImode must go into class Q_REGS. + Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and + movdf to do mem-to-mem moves through integer regs. */ + +#define PREFERRED_RELOAD_CLASS(X,CLASS) \ + (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode ? NO_REGS \ + : GET_MODE (X) == QImode && ! reg_class_subset_p (CLASS, Q_REGS) ? Q_REGS \ + : ((CLASS) == ALL_REGS \ + && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) ? GENERAL_REGS \ + : (CLASS)) + +/* If we are copying between general and FP registers, we need a memory + location. */ + +#define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ + ((FLOAT_CLASS_P (CLASS1) && ! FLOAT_CLASS_P (CLASS2)) \ + || (! FLOAT_CLASS_P (CLASS1) && FLOAT_CLASS_P (CLASS2))) + +/* Return the maximum number of consecutive registers + needed to represent mode MODE in a register of class CLASS. */ +/* On the 80386, this is the size of MODE in words, + except in the FP regs, where a single reg is always enough. */ +#define CLASS_MAX_NREGS(CLASS, MODE) \ + (FLOAT_CLASS_P (CLASS) ? 1 : \ + ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) + +/* A C expression whose value is nonzero if pseudos that have been + assigned to registers of class CLASS would likely be spilled + because registers of CLASS are needed for spill registers. + + The default value of this macro returns 1 if CLASS has exactly one + register and zero otherwise. On most machines, this default + should be used. Only define this macro to some other expression + if pseudo allocated by `local-alloc.c' end up in memory because + their hard registers were needed for spill registers. If this + macro returns nonzero for those classes, those pseudos will only + be allocated by `global.c', which knows how to reallocate the + pseudo to another register. If there would not be another + register available for reallocation, you should not change the + definition of this macro since the only effect of such a + definition would be to slow down register allocation. */ + +#define CLASS_LIKELY_SPILLED_P(CLASS) \ + (((CLASS) == AREG) \ + || ((CLASS) == DREG) \ + || ((CLASS) == CREG) \ + || ((CLASS) == BREG) \ + || ((CLASS) == AD_REGS) \ + || ((CLASS) == SIREG) \ + || ((CLASS) == DIREG)) + + +/* Stack layout; function entry, exit and calling. */ + +/* Define this if pushing a word on the stack + makes the stack pointer a smaller address. */ +#define STACK_GROWS_DOWNWARD + +/* Define this if the nominal address of the stack frame + is at the high-address end of the local variables; + that is, each additional local variable allocated + goes at a more negative offset in the frame. */ +#define FRAME_GROWS_DOWNWARD + +/* Offset within stack frame to start allocating local variables at. + If FRAME_GROWS_DOWNWARD, this is the offset to the END of the + first local allocated. Otherwise, it is the offset to the BEGINNING + of the first local allocated. */ +#define STARTING_FRAME_OFFSET 0 + +/* If we generate an insn to push BYTES bytes, + this says how many the stack pointer really advances by. + On 386 pushw decrements by exactly 2 no matter what the position was. + On the 386 there is no pushb; we use pushw instead, and this + has the effect of rounding up to 2. */ + +#define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & (-2)) + +/* Offset of first parameter from the argument pointer register value. */ +#define FIRST_PARM_OFFSET(FNDECL) 0 + +/* Value is the number of bytes of arguments automatically + popped when returning from a subroutine call. + FUNDECL is the declaration node of the function (as a tree), + FUNTYPE is the data type of the function (as a tree), + or for a library call it is an identifier node for the subroutine name. + SIZE is the number of bytes of arguments passed on the stack. + + On the 80386, the RTD insn may be used to pop them if the number + of args is fixed, but if the number is variable then the caller + must pop them all. RTD can't be used for library calls now + because the library is compiled with the Unix compiler. + Use of RTD is a selectable option, since it is incompatible with + standard Unix calling sequences. If the option is not selected, + the caller must always pop the args. + + The attribute stdcall is equivalent to RTD on a per module basis. */ + +#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \ + (i386_return_pops_args (FUNDECL, FUNTYPE, SIZE)) + +/* Define how to find the value returned by a function. + VALTYPE is the data type of the value (as a tree). + If the precise function being called is known, FUNC is its FUNCTION_DECL; + otherwise, FUNC is 0. */ +#define FUNCTION_VALUE(VALTYPE, FUNC) \ + gen_rtx (REG, TYPE_MODE (VALTYPE), \ + VALUE_REGNO (TYPE_MODE (VALTYPE))) + +/* Define how to find the value returned by a library function + assuming the value has mode MODE. */ + +#define LIBCALL_VALUE(MODE) \ + gen_rtx (REG, MODE, VALUE_REGNO (MODE)) + +/* Define the size of the result block used for communication between + untyped_call and untyped_return. The block contains a DImode value + followed by the block used by fnsave and frstor. */ + +#define APPLY_RESULT_SIZE (8+108) + +/* 1 if N is a possible register number for function argument passing. */ +#define FUNCTION_ARG_REGNO_P(N) ((N) >= 0 && (N) < REGPARM_MAX) + +/* Define a data type for recording info about an argument list + during the scan of that argument list. This data type should + hold all necessary information about the function itself + and about the args processed so far, enough to enable macros + such as FUNCTION_ARG to determine where the next arg should go. */ + +typedef struct i386_args { + int words; /* # words passed so far */ + int nregs; /* # registers available for passing */ + int regno; /* next available register number */ +} CUMULATIVE_ARGS; + +/* Initialize a variable CUM of type CUMULATIVE_ARGS + for a call to a function whose data type is FNTYPE. + For a library call, FNTYPE is 0. */ + +#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ + (init_cumulative_args (&CUM, FNTYPE, LIBNAME)) + +/* Update the data in CUM to advance over an argument + of mode MODE and data type TYPE. + (TYPE is null for libcalls where that information may not be available.) */ + +#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ + (function_arg_advance (&CUM, MODE, TYPE, NAMED)) + +/* Define where to put the arguments to a function. + Value is zero to push the argument on the stack, + or a hard register in which to store the argument. + + MODE is the argument's machine mode. + TYPE is the data type of the argument (as a tree). + This is null for libcalls where that information may + not be available. + CUM is a variable of type CUMULATIVE_ARGS which gives info about + the preceding args and about the function being called. + NAMED is nonzero if this argument is a named parameter + (otherwise it is an extra parameter matching an ellipsis). */ + +#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ + (function_arg (&CUM, MODE, TYPE, NAMED)) + +/* For an arg passed partly in registers and partly in memory, + this is the number of registers used. + For args passed entirely in registers or entirely in memory, zero. */ + +#define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ + (function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)) + +/* This macro generates the assembly code for function entry. + FILE is a stdio stream to output the code to. + SIZE is an int: how many units of temporary storage to allocate. + Refer to the array `regs_ever_live' to determine which registers + to save; `regs_ever_live[I]' is nonzero if register number I + is ever used in the function. This macro is responsible for + knowing which registers should not be saved even if used. */ + +#define FUNCTION_PROLOGUE(FILE, SIZE) \ + function_prologue (FILE, SIZE) + +/* Output assembler code to FILE to increment profiler label # LABELNO + for profiling a function entry. */ + +#define FUNCTION_PROFILER(FILE, LABELNO) \ +{ \ + if (flag_pic) \ + { \ + fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n", \ + LPREFIX, (LABELNO)); \ + fprintf (FILE, "\tcall *_mcount@GOT(%%ebx)\n"); \ + } \ + else \ + { \ + fprintf (FILE, "\tmovl $%sP%d,%%edx\n", LPREFIX, (LABELNO)); \ + fprintf (FILE, "\tcall _mcount\n"); \ + } \ +} + +/* A C statement or compound statement to output to FILE some + assembler code to initialize basic-block profiling for the current + object module. This code should call the subroutine + `__bb_init_func' once per object module, passing it as its sole + argument the address of a block allocated in the object module. + + The name of the block is a local symbol made with this statement: + + ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 0); + + Of course, since you are writing the definition of + `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you + can take a short cut in the definition of this macro and use the + name that you know will result. + + The first word of this block is a flag which will be nonzero if the + object module has already been initialized. So test this word + first, and do not call `__bb_init_func' if the flag is nonzero. */ + +#undef FUNCTION_BLOCK_PROFILER +#define FUNCTION_BLOCK_PROFILER(STREAM, LABELNO) \ +do \ + { \ + static int num_func = 0; \ + rtx xops[8]; \ + char block_table[80], false_label[80]; \ + \ + ASM_GENERATE_INTERNAL_LABEL (block_table, "LPBX", 0); \ + ASM_GENERATE_INTERNAL_LABEL (false_label, "LPBZ", num_func); \ + \ + xops[0] = const0_rtx; \ + xops[1] = gen_rtx (SYMBOL_REF, VOIDmode, block_table); \ + xops[2] = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, VOIDmode, false_label)); \ + xops[3] = gen_rtx (MEM, Pmode, gen_rtx (SYMBOL_REF, VOIDmode, "__bb_init_func")); \ + xops[4] = gen_rtx (MEM, Pmode, xops[1]); \ + xops[5] = stack_pointer_rtx; \ + xops[6] = GEN_INT (4); \ + xops[7] = gen_rtx (REG, Pmode, 0); /* eax */ \ + \ + CONSTANT_POOL_ADDRESS_P (xops[1]) = TRUE; \ + CONSTANT_POOL_ADDRESS_P (xops[2]) = TRUE; \ + \ + output_asm_insn (AS2(cmp%L4,%0,%4), xops); \ + output_asm_insn (AS1(jne,%2), xops); \ + \ + if (!flag_pic) \ + output_asm_insn (AS1(push%L1,%1), xops); \ + else \ + { \ + output_asm_insn (AS2 (lea%L7,%a1,%7), xops); \ + output_asm_insn (AS1 (push%L7,%7), xops); \ + } \ + \ + output_asm_insn (AS1(call,%P3), xops); \ + output_asm_insn (AS2(add%L0,%6,%5), xops); \ + ASM_OUTPUT_INTERNAL_LABEL (STREAM, "LPBZ", num_func); \ + num_func++; \ + } \ +while (0) + + +/* A C statement or compound statement to increment the count + associated with the basic block number BLOCKNO. Basic blocks are + numbered separately from zero within each compilation. The count + associated with block number BLOCKNO is at index BLOCKNO in a + vector of words; the name of this array is a local symbol made + with this statement: + + ASM_GENERATE_INTERNAL_LABEL (BUFFER, "LPBX", 2); + + Of course, since you are writing the definition of + `ASM_GENERATE_INTERNAL_LABEL' as well as that of this macro, you + can take a short cut in the definition of this macro and use the + name that you know will result. */ + +#define BLOCK_PROFILER(STREAM, BLOCKNO) \ +do \ + { \ + rtx xops[1], cnt_rtx; \ + char counts[80]; \ + \ + ASM_GENERATE_INTERNAL_LABEL (counts, "LPBX", 2); \ + cnt_rtx = gen_rtx (SYMBOL_REF, VOIDmode, counts); \ + SYMBOL_REF_FLAG (cnt_rtx) = TRUE; \ + \ + if (BLOCKNO) \ + cnt_rtx = plus_constant (cnt_rtx, (BLOCKNO)*4); \ + \ + if (flag_pic) \ + cnt_rtx = gen_rtx (PLUS, Pmode, pic_offset_table_rtx, cnt_rtx); \ + \ + xops[0] = gen_rtx (MEM, SImode, cnt_rtx); \ + output_asm_insn (AS1(inc%L0,%0), xops); \ + } \ +while (0) + +/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, + the stack pointer does not matter. The value is tested only in + functions that have frame pointers. + No definition is equivalent to always zero. */ +/* Note on the 386 it might be more efficient not to define this since + we have to restore it ourselves from the frame pointer, in order to + use pop */ + +#define EXIT_IGNORE_STACK 1 + +/* This macro generates the assembly code for function exit, + on machines that need it. If FUNCTION_EPILOGUE is not defined + then individual return instructions are generated for each + return statement. Args are same as for FUNCTION_PROLOGUE. + + The function epilogue should not depend on the current stack pointer! + It should use the frame pointer only. This is mandatory because + of alloca; we also take advantage of it to omit stack adjustments + before returning. + + If the last non-note insn in the function is a BARRIER, then there + is no need to emit a function prologue, because control does not fall + off the end. This happens if the function ends in an "exit" call, or + if a `return' insn is emitted directly into the function. */ + +#define FUNCTION_EPILOGUE(FILE, SIZE) \ +do { \ + rtx last = get_last_insn (); \ + if (last && GET_CODE (last) == NOTE) \ + last = prev_nonnote_insn (last); \ + if (! last || GET_CODE (last) != BARRIER) \ + function_epilogue (FILE, SIZE); \ +} while (0) + +/* Output assembler code for a block containing the constant parts + of a trampoline, leaving space for the variable parts. */ + +/* On the 386, the trampoline contains three instructions: + mov #STATIC,ecx + mov #FUNCTION,eax + jmp @eax */ +#define TRAMPOLINE_TEMPLATE(FILE) \ +{ \ + ASM_OUTPUT_CHAR (FILE, GEN_INT (0xb9)); \ + ASM_OUTPUT_SHORT (FILE, const0_rtx); \ + ASM_OUTPUT_SHORT (FILE, const0_rtx); \ + ASM_OUTPUT_CHAR (FILE, GEN_INT (0xb8)); \ + ASM_OUTPUT_SHORT (FILE, const0_rtx); \ + ASM_OUTPUT_SHORT (FILE, const0_rtx); \ + ASM_OUTPUT_CHAR (FILE, GEN_INT (0xff)); \ + ASM_OUTPUT_CHAR (FILE, GEN_INT (0xe0)); \ +} + +/* Length in units of the trampoline for entering a nested function. */ + +#define TRAMPOLINE_SIZE 12 + +/* Emit RTL insns to initialize the variable parts of a trampoline. + FNADDR is an RTX for the address of the function's pure code. + CXT is an RTX for the static chain value for the function. */ + +#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ +{ \ + emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 1)), CXT); \ + emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 6)), FNADDR); \ +} + +/* Definitions for register eliminations. + + This is an array of structures. Each structure initializes one pair + of eliminable registers. The "from" register number is given first, + followed by "to". Eliminations of the same "from" register are listed + in order of preference. + + We have two registers that can be eliminated on the i386. First, the + frame pointer register can often be eliminated in favor of the stack + pointer register. Secondly, the argument pointer register can always be + eliminated; it is replaced with either the stack or frame pointer. */ + +#define ELIMINABLE_REGS \ +{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ + { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ + { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} + +/* Given FROM and TO register numbers, say whether this elimination is allowed. + Frame pointer elimination is automatically handled. + + For the i386, if frame pointer elimination is being done, we would like to + convert ap into sp, not fp. + + All other eliminations are valid. */ + +#define CAN_ELIMINATE(FROM, TO) \ + ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM \ + ? ! frame_pointer_needed \ + : 1) + +/* Define the offset between two registers, one to be eliminated, and the other + its replacement, at the start of a routine. */ + +#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ +{ \ + if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \ + (OFFSET) = 8; /* Skip saved PC and previous frame pointer */ \ + else \ + { \ + int regno; \ + int offset = 0; \ + \ + for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) \ + if ((regs_ever_live[regno] && ! call_used_regs[regno]) \ + || (current_function_uses_pic_offset_table \ + && regno == PIC_OFFSET_TABLE_REGNUM)) \ + offset += 4; \ + \ + (OFFSET) = offset + get_frame_size (); \ + \ + if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ + (OFFSET) += 4; /* Skip saved PC */ \ + } \ +} + +/* Addressing modes, and classification of registers for them. */ + +/* #define HAVE_POST_INCREMENT */ +/* #define HAVE_POST_DECREMENT */ + +/* #define HAVE_PRE_DECREMENT */ +/* #define HAVE_PRE_INCREMENT */ + +/* Macros to check register numbers against specific register classes. */ + +/* These assume that REGNO is a hard or pseudo reg number. + They give nonzero only if REGNO is a hard reg of the suitable class + or a pseudo reg currently allocated to a suitable hard reg. + Since they use reg_renumber, they are safe only once reg_renumber + has been allocated, which happens in local-alloc.c. */ + +#define REGNO_OK_FOR_INDEX_P(REGNO) \ + ((REGNO) < STACK_POINTER_REGNUM \ + || (unsigned) reg_renumber[REGNO] < STACK_POINTER_REGNUM) + +#define REGNO_OK_FOR_BASE_P(REGNO) \ + ((REGNO) <= STACK_POINTER_REGNUM \ + || (REGNO) == ARG_POINTER_REGNUM \ + || (unsigned) reg_renumber[REGNO] <= STACK_POINTER_REGNUM) + +#define REGNO_OK_FOR_SIREG_P(REGNO) ((REGNO) == 4 || reg_renumber[REGNO] == 4) +#define REGNO_OK_FOR_DIREG_P(REGNO) ((REGNO) == 5 || reg_renumber[REGNO] == 5) + +/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx + and check its validity for a certain class. + We have two alternate definitions for each of them. + The usual definition accepts all pseudo regs; the other rejects + them unless they have been allocated suitable hard regs. + The symbol REG_OK_STRICT causes the latter definition to be used. + + Most source files want to accept pseudo regs in the hope that + they will get allocated to the class that the insn wants them to be in. + Source files for reload pass need to be strict. + After reload, it makes no difference, since pseudo regs have + been eliminated by then. */ + + +/* Non strict versions, pseudos are ok */ +#define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ + (REGNO (X) < STACK_POINTER_REGNUM \ + || REGNO (X) >= FIRST_PSEUDO_REGISTER) + +#define REG_OK_FOR_BASE_NONSTRICT_P(X) \ + (REGNO (X) <= STACK_POINTER_REGNUM \ + || REGNO (X) == ARG_POINTER_REGNUM \ + || REGNO (X) >= FIRST_PSEUDO_REGISTER) + +#define REG_OK_FOR_STRREG_NONSTRICT_P(X) \ + (REGNO (X) == 4 || REGNO (X) == 5 || REGNO (X) >= FIRST_PSEUDO_REGISTER) + +/* Strict versions, hard registers only */ +#define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) +#define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) +#define REG_OK_FOR_STRREG_STRICT_P(X) \ + (REGNO_OK_FOR_DIREG_P (REGNO (X)) || REGNO_OK_FOR_SIREG_P (REGNO (X))) + +#ifndef REG_OK_STRICT +#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P(X) +#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P(X) +#define REG_OK_FOR_STRREG_P(X) REG_OK_FOR_STRREG_NONSTRICT_P(X) + +#else +#define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P(X) +#define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P(X) +#define REG_OK_FOR_STRREG_P(X) REG_OK_FOR_STRREG_STRICT_P(X) +#endif + +/* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression + that is a valid memory address for an instruction. + The MODE argument is the machine mode for the MEM expression + that wants to use this address. + + The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS, + except for CONSTANT_ADDRESS_P which is usually machine-independent. + + See legitimize_pic_address in i386.c for details as to what + constitutes a legitimate address when -fpic is used. */ + +#define MAX_REGS_PER_ADDRESS 2 + +#define CONSTANT_ADDRESS_P(X) \ + (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ + || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ + || GET_CODE (X) == HIGH) + +/* Nonzero if the constant value X is a legitimate general operand. + It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ + +#define LEGITIMATE_CONSTANT_P(X) 1 + +#ifdef REG_OK_STRICT +#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ +{ \ + if (legitimate_address_p (MODE, X, 1)) \ + goto ADDR; \ +} + +#else +#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ +{ \ + if (legitimate_address_p (MODE, X, 0)) \ + goto ADDR; \ +} + +#endif + +/* Try machine-dependent ways of modifying an illegitimate address + to be legitimate. If we find one, return the new, valid address. + This macro is used in only one place: `memory_address' in explow.c. + + OLDX is the address as it was before break_out_memory_refs was called. + In some cases it is useful to look at this to decide what needs to be done. + + MODE and WIN are passed so that this macro can use + GO_IF_LEGITIMATE_ADDRESS. + + It is always safe for this macro to do nothing. It exists to recognize + opportunities to optimize the output. + + For the 80386, we handle X+REG by loading X into a register R and + using R+REG. R will go in a general reg and indexing will be used. + However, if REG is a broken-out memory address or multiplication, + nothing needs to be done because REG can certainly go in a general reg. + + When -fpic is used, special handling is needed for symbolic references. + See comments by legitimize_pic_address in i386.c for details. */ + +#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ +{ \ + rtx orig_x = (X); \ + (X) = legitimize_address (X, OLDX, MODE); \ + if (memory_address_p (MODE, X)) \ + goto WIN; \ +} + +/* Nonzero if the constant value X is a legitimate general operand + when generating PIC code. It is given that flag_pic is on and + that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ + +#define LEGITIMATE_PIC_OPERAND_P(X) \ + (! SYMBOLIC_CONST (X) \ + || (GET_CODE (X) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (X))) + +#define SYMBOLIC_CONST(X) \ +(GET_CODE (X) == SYMBOL_REF \ + || GET_CODE (X) == LABEL_REF \ + || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) + +/* Go to LABEL if ADDR (a legitimate address expression) + has an effect that depends on the machine mode it is used for. + On the 80386, only postdecrement and postincrement address depend thus + (the amount of decrement or increment being the length of the operand). */ +#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ + if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == POST_DEC) goto LABEL + +/* Define this macro if references to a symbol must be treated + differently depending on something about the variable or + function named by the symbol (such as what section it is in). + + On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol + so that we may access it directly in the GOT. */ + +#define ENCODE_SECTION_INFO(DECL) \ +do \ + { \ + if (flag_pic) \ + { \ + rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ + ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \ + SYMBOL_REF_FLAG (XEXP (rtl, 0)) \ + = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ + || ! TREE_PUBLIC (DECL)); \ + } \ + } \ +while (0) + +/* Initialize data used by insn expanders. This is called from + init_emit, once for each function, before code is generated. + For 386, clear stack slot assignments remembered from previous + functions. */ + +#define INIT_EXPANDERS clear_386_stack_locals () + +/* The `FINALIZE_PIC' macro serves as a hook to emit these special + codes once the function is being compiled into assembly code, but + not before. (It is not done before, because in the case of + compiling an inline function, it would lead to multiple PIC + prologues being included in functions which used inline functions + and were compiled to assembly language.) */ + +#define FINALIZE_PIC \ +do \ + { \ + extern int current_function_uses_pic_offset_table; \ + \ + current_function_uses_pic_offset_table |= profile_flag | profile_block_flag; \ + } \ +while (0) + + +/* If defined, a C expression whose value is nonzero if IDENTIFIER + with arguments ARGS is a valid machine specific attribute for DECL. + The attributes in ATTRIBUTES have previously been assigned to DECL. */ + +#define VALID_MACHINE_DECL_ATTRIBUTE(DECL, ATTRIBUTES, NAME, ARGS) \ + (i386_valid_decl_attribute_p (DECL, ATTRIBUTES, NAME, ARGS)) + +/* If defined, a C expression whose value is nonzero if IDENTIFIER + with arguments ARGS is a valid machine specific attribute for TYPE. + The attributes in ATTRIBUTES have previously been assigned to TYPE. */ + +#define VALID_MACHINE_TYPE_ATTRIBUTE(TYPE, ATTRIBUTES, NAME, ARGS) \ + (i386_valid_type_attribute_p (TYPE, ATTRIBUTES, NAME, ARGS)) + +/* If defined, a C expression whose value is zero if the attributes on + TYPE1 and TYPE2 are incompatible, one if they are compatible, and + two if they are nearly compatible (which causes a warning to be + generated). */ + +#define COMP_TYPE_ATTRIBUTES(TYPE1, TYPE2) \ + (i386_comp_type_attributes (TYPE1, TYPE2)) + +/* If defined, a C statement that assigns default attributes to newly + defined TYPE. */ + +/* #define SET_DEFAULT_TYPE_ATTRIBUTES (TYPE) */ + +/* Max number of args passed in registers. If this is more than 3, we will + have problems with ebx (register #4), since it is a caller save register and + is also used as the pic register in ELF. So for now, don't allow more than + 3 registers to be passed in registers. */ + +#define REGPARM_MAX 3 + + +/* Specify the machine mode that this machine uses + for the index in the tablejump instruction. */ +#define CASE_VECTOR_MODE Pmode + +/* Define this if the tablejump instruction expects the table + to contain offsets from the address of the table. + Do not define this if the table should contain absolute addresses. */ +/* #define CASE_VECTOR_PC_RELATIVE */ + +/* Specify the tree operation to be used to convert reals to integers. + This should be changed to take advantage of fist --wfs ?? + */ +#define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR + +/* This is the kind of divide that is easiest to do in the general case. */ +#define EASY_DIV_EXPR TRUNC_DIV_EXPR + +/* Define this as 1 if `char' should by default be signed; else as 0. */ +#define DEFAULT_SIGNED_CHAR 1 + +/* Max number of bytes we can move from memory to memory + in one reasonably fast instruction. */ +#define MOVE_MAX 4 + +/* MOVE_RATIO is the number of move instructions that is better than a + block move. Make this large on i386, since the block move is very + inefficient with small blocks, and the hard register needs of the + block move require much reload work. */ +#define MOVE_RATIO 5 + +/* Define this if zero-extension is slow (more than one real instruction). */ +/* #define SLOW_ZERO_EXTEND */ + +/* Nonzero if access to memory by bytes is slow and undesirable. */ +#define SLOW_BYTE_ACCESS 0 + +/* Define if shifts truncate the shift count + which implies one can omit a sign-extension or zero-extension + of a shift count. */ +/* One i386, shifts do truncate the count. But bit opcodes don't. */ + +/* #define SHIFT_COUNT_TRUNCATED */ + +/* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits + is done just by pretending it is already truncated. */ +#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 + +/* We assume that the store-condition-codes instructions store 0 for false + and some other value for true. This is the value stored for true. */ + +#define STORE_FLAG_VALUE 1 + +/* When a prototype says `char' or `short', really pass an `int'. + (The 386 can't easily push less than an int.) */ + +#define PROMOTE_PROTOTYPES + +/* Specify the machine mode that pointers have. + After generation of rtl, the compiler makes no further distinction + between pointers and any other objects of this machine mode. */ +#define Pmode SImode + +/* A function address in a call instruction + is a byte address (for indexing purposes) + so give the MEM rtx a byte's mode. */ +#define FUNCTION_MODE QImode + +/* Define this if addresses of constant functions + shouldn't be put through pseudo regs where they can be cse'd. + Desirable on the 386 because a CALL with a constant address is + not much slower than one with a register address. On a 486, + it is faster to call with a constant address than indirect. */ +#define NO_FUNCTION_CSE + +/* Provide the costs of a rtl expression. This is in the body of a + switch on CODE. */ + +#define RTX_COSTS(X,CODE,OUTER_CODE) \ + case MULT: \ + return COSTS_N_INSNS (20); \ + case DIV: \ + case UDIV: \ + case MOD: \ + case UMOD: \ + return COSTS_N_INSNS (20); \ + case ASHIFTRT: \ + case LSHIFTRT: \ + case ASHIFT: \ + return (4 + rtx_cost (XEXP (X, 0), OUTER_CODE) \ + + rtx_cost (XEXP (X, 1), OUTER_CODE)); \ + case PLUS: \ + if (GET_CODE (XEXP (X, 0)) == MULT \ + && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT \ + && (INTVAL (XEXP (XEXP (X, 0), 1)) == 2 \ + || INTVAL (XEXP (XEXP (X, 0), 1)) == 4 \ + || INTVAL (XEXP (XEXP (X, 0), 1)) == 8)) \ + return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \ + + rtx_cost (XEXP (X, 1), OUTER_CODE)); \ + break; + + +/* Compute the cost of computing a constant rtl expression RTX + whose rtx-code is CODE. The body of this macro is a portion + of a switch statement. If the code is computed here, + return it with a return statement. Otherwise, break from the switch. */ + +#define CONST_COSTS(RTX,CODE,OUTER_CODE) \ + case CONST_INT: \ + case CONST: \ + case LABEL_REF: \ + case SYMBOL_REF: \ + return flag_pic && SYMBOLIC_CONST (RTX) ? 2 : 0; \ + case CONST_DOUBLE: \ + { \ + int code; \ + if (GET_MODE (RTX) == VOIDmode) \ + return 2; \ + code = standard_80387_constant_p (RTX); \ + return code == 1 ? 0 : \ + code == 2 ? 1 : \ + 2; \ + } + +/* Compute the cost of an address. This is meant to approximate the size + and/or execution delay of an insn using that address. If the cost is + approximated by the RTL complexity, including CONST_COSTS above, as + is usually the case for CISC machines, this macro should not be defined. + For aggressively RISCy machines, only one insn format is allowed, so + this macro should be a constant. The value of this macro only matters + for valid addresses. + + For i386, it is better to use a complex address than let gcc copy + the address into a reg and make a new pseudo. But not if the address + requires to two regs - that would mean more pseudos with longer + lifetimes. */ + +#define ADDRESS_COST(RTX) \ + ((CONSTANT_P (RTX) \ + || (GET_CODE (RTX) == PLUS && CONSTANT_P (XEXP (RTX, 1)) \ + && REG_P (XEXP (RTX, 0)))) ? 0 \ + : REG_P (RTX) ? 1 \ + : 2) + +/* Add any extra modes needed to represent the condition code. + + For the i386, we need separate modes when floating-point equality + comparisons are being done. */ + +#define EXTRA_CC_MODES CCFPEQmode + +/* Define the names for the modes specified above. */ +#define EXTRA_CC_NAMES "CCFPEQ" + +/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, + return the mode to be used for the comparison. + + For floating-point equality comparisons, CCFPEQmode should be used. + VOIDmode should be used in all other cases. */ + +#define SELECT_CC_MODE(OP,X,Y) \ + (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \ + && ((OP) == EQ || (OP) == NE) ? CCFPEQmode : VOIDmode) + +/* Define the information needed to generate branch and scc insns. This is + stored from the compare operation. Note that we can't use "rtx" here + since it hasn't been defined! */ + +extern struct rtx_def *(*i386_compare_gen)(), *(*i386_compare_gen_eq)(); + +/* Tell final.c how to eliminate redundant test instructions. */ + +/* Here we define machine-dependent flags and fields in cc_status + (see `conditions.h'). */ + +/* Set if the cc value is actually in the 80387, so a floating point + conditional branch must be output. */ +#define CC_IN_80387 04000 + +/* Set if the CC value was stored in a nonstandard way, so that + the state of equality is indicated by zero in the carry bit. */ +#define CC_Z_IN_NOT_C 010000 + +/* Store in cc_status the expressions + that the condition codes will describe + after execution of an instruction whose pattern is EXP. + Do not alter them if the instruction would not alter the cc's. */ + +#define NOTICE_UPDATE_CC(EXP, INSN) \ + notice_update_cc((EXP)) + +/* Output a signed jump insn. Use template NORMAL ordinarily, or + FLOAT following a floating point comparison. + Use NO_OV following an arithmetic insn that set the cc's + before a test insn that was deleted. + NO_OV may be zero, meaning final should reinsert the test insn + because the jump cannot be handled properly without it. */ + +#define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ +{ \ + if (cc_prev_status.flags & CC_IN_80387) \ + return FLOAT; \ + if (cc_prev_status.flags & CC_NO_OVERFLOW) \ + return NO_OV; \ + return NORMAL; \ +} + +/* Control the assembler format that we output, to the extent + this does not vary between assemblers. */ + +/* How to refer to registers in assembler output. + This sequence is indexed by compiler's hard-register-number (see above). */ + +/* In order to refer to the first 8 regs as 32 bit regs prefix an "e" + For non floating point regs, the following are the HImode names. + + For float regs, the stack top is sometimes referred to as "%st(0)" + instead of just "%st". PRINT_REG handles this with the "y" code. */ + +#define HI_REGISTER_NAMES \ +{"ax","dx","cx","bx","si","di","bp","sp", \ + "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)","" } + +#define REGISTER_NAMES HI_REGISTER_NAMES + +/* Table of additional register names to use in user input. */ + +#define ADDITIONAL_REGISTER_NAMES \ +{ "eax", 0, "edx", 1, "ecx", 2, "ebx", 3, \ + "esi", 4, "edi", 5, "ebp", 6, "esp", 7, \ + "al", 0, "dl", 1, "cl", 2, "bl", 3, \ + "ah", 0, "dh", 1, "ch", 2, "bh", 3 } + +/* Note we are omitting these since currently I don't know how +to get gcc to use these, since they want the same but different +number as al, and ax. +*/ + +/* note the last four are not really qi_registers, but + the md will have to never output movb into one of them + only a movw . There is no movb into the last four regs */ + +#define QI_REGISTER_NAMES \ +{"al", "dl", "cl", "bl", "si", "di", "bp", "sp",} + +/* These parallel the array above, and can be used to access bits 8:15 + of regs 0 through 3. */ + +#define QI_HIGH_REGISTER_NAMES \ +{"ah", "dh", "ch", "bh", } + +/* How to renumber registers for dbx and gdb. */ + +/* {0,2,1,3,6,7,4,5,12,13,14,15,16,17} */ +#define DBX_REGISTER_NUMBER(n) \ +((n) == 0 ? 0 : \ + (n) == 1 ? 2 : \ + (n) == 2 ? 1 : \ + (n) == 3 ? 3 : \ + (n) == 4 ? 6 : \ + (n) == 5 ? 7 : \ + (n) == 6 ? 4 : \ + (n) == 7 ? 5 : \ + (n) + 4) + +/* This is how to output the definition of a user-level label named NAME, + such as the label on a static function or variable NAME. */ + +#define ASM_OUTPUT_LABEL(FILE,NAME) \ + (assemble_name (FILE, NAME), fputs (":\n", FILE)) + +/* This is how to output an assembler line defining a `double' constant. */ + +#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ +do { long l[2]; \ + REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \ + if (sizeof (int) == sizeof (long)) \ + fprintf (FILE, "%s 0x%x,0x%x\n", ASM_LONG, l[0], l[1]); \ + else \ + fprintf (FILE, "%s 0x%lx,0x%lx\n", ASM_LONG, l[0], l[1]); \ + } while (0) + +/* This is how to output a `long double' extended real constant. */ + +#undef ASM_OUTPUT_LONG_DOUBLE +#define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ +do { long l[3]; \ + REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \ + if (sizeof (int) == sizeof (long)) \ + fprintf (FILE, "%s 0x%x,0x%x,0x%x\n", ASM_LONG, l[0], l[1], l[2]); \ + else \ + fprintf (FILE, "%s 0x%lx,0x%lx,0x%lx\n", ASM_LONG, l[0], l[1], l[2]); \ + } while (0) + +/* This is how to output an assembler line defining a `float' constant. */ + +#define ASM_OUTPUT_FLOAT(FILE,VALUE) \ +do { long l; \ + REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ + if (sizeof (int) == sizeof (long)) \ + fprintf ((FILE), "%s 0x%x\n", ASM_LONG, l); \ + else \ + fprintf ((FILE), "%s 0x%lx\n", ASM_LONG, l); \ + } while (0) + +/* Store in OUTPUT a string (made with alloca) containing + an assembler-name for a local static variable named NAME. + LABELNO is an integer which is different for each call. */ + +#define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ +( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ + sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) + + + +/* This is how to output an assembler line defining an `int' constant. */ + +#define ASM_OUTPUT_INT(FILE,VALUE) \ +( fprintf (FILE, "%s ", ASM_LONG), \ + output_addr_const (FILE,(VALUE)), \ + putc('\n',FILE)) + +/* Likewise for `char' and `short' constants. */ +/* is this supposed to do align too?? */ + +#define ASM_OUTPUT_SHORT(FILE,VALUE) \ +( fprintf (FILE, "%s ", ASM_SHORT), \ + output_addr_const (FILE,(VALUE)), \ + putc('\n',FILE)) + +/* +#define ASM_OUTPUT_SHORT(FILE,VALUE) \ +( fprintf (FILE, "%s ", ASM_BYTE_OP), \ + output_addr_const (FILE,(VALUE)), \ + fputs (",", FILE), \ + output_addr_const (FILE,(VALUE)), \ + fputs (" >> 8\n",FILE)) +*/ + + +#define ASM_OUTPUT_CHAR(FILE,VALUE) \ +( fprintf (FILE, "%s ", ASM_BYTE_OP), \ + output_addr_const (FILE, (VALUE)), \ + putc ('\n', FILE)) + +/* This is how to output an assembler line for a numeric constant byte. */ + +#define ASM_OUTPUT_BYTE(FILE,VALUE) \ + fprintf ((FILE), "%s 0x%x\n", ASM_BYTE_OP, (VALUE)) + +/* This is how to output an insn to push a register on the stack. + It need not be very fast code. */ + +#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ + fprintf (FILE, "\tpushl e%s\n", reg_names[REGNO]) + +/* This is how to output an insn to pop a register from the stack. + It need not be very fast code. */ + +#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ + fprintf (FILE, "\tpopl e%s\n", reg_names[REGNO]) + +/* This is how to output an element of a case-vector that is absolute. + */ + +#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ + fprintf (FILE, "%s %s%d\n", ASM_LONG, LPREFIX, VALUE) + +/* This is how to output an element of a case-vector that is relative. + We don't use these on the 386 yet, because the ATT assembler can't do + forward reference the differences. + */ + +#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ + fprintf (FILE, "\t.word %s%d-%s%d\n",LPREFIX, VALUE,LPREFIX, REL) + +/* Define the parentheses used to group arithmetic operations + in assembler code. */ + +#define ASM_OPEN_PAREN "" +#define ASM_CLOSE_PAREN "" + +/* Define results of standard character escape sequences. */ +#define TARGET_BELL 007 +#define TARGET_BS 010 +#define TARGET_TAB 011 +#define TARGET_NEWLINE 012 +#define TARGET_VT 013 +#define TARGET_FF 014 +#define TARGET_CR 015 + +/* Print operand X (an rtx) in assembler syntax to file FILE. + CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. + The CODE z takes the size of operand from the following digit, and + outputs b,w,or l respectively. + + On the 80386, we use several such letters: + f -- float insn (print a CONST_DOUBLE as a float rather than in hex). + L,W,B,Q,S,T -- print the opcode suffix for specified size of operand. + R -- print the prefix for register names. + z -- print the opcode suffix for the size of the current operand. + * -- print a star (in certain assembler syntax) + w -- print the operand as if it's a "word" (HImode) even if it isn't. + b -- print the operand as if it's a byte (QImode) even if it isn't. + c -- don't print special prefixes before constant operands. */ + +#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ + ((CODE) == '*') + +/* Print the name of a register based on its machine mode and number. + If CODE is 'w', pretend the mode is HImode. + If CODE is 'b', pretend the mode is QImode. + If CODE is 'k', pretend the mode is SImode. + If CODE is 'h', pretend the reg is the `high' byte register. + If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op. */ + +extern char *hi_reg_name[]; +extern char *qi_reg_name[]; +extern char *qi_high_reg_name[]; + +#define PRINT_REG(X, CODE, FILE) \ + do { if (REGNO (X) == ARG_POINTER_REGNUM) \ + abort (); \ + fprintf (FILE, "%s", RP); \ + switch ((CODE == 'w' ? 2 \ + : CODE == 'b' ? 1 \ + : CODE == 'k' ? 4 \ + : CODE == 'y' ? 3 \ + : CODE == 'h' ? 0 \ + : GET_MODE_SIZE (GET_MODE (X)))) \ + { \ + case 3: \ + if (STACK_TOP_P (X)) \ + { \ + fputs ("st(0)", FILE); \ + break; \ + } \ + case 4: \ + case 8: \ + case 12: \ + if (! FP_REG_P (X)) fputs ("e", FILE); \ + case 2: \ + fputs (hi_reg_name[REGNO (X)], FILE); \ + break; \ + case 1: \ + fputs (qi_reg_name[REGNO (X)], FILE); \ + break; \ + case 0: \ + fputs (qi_high_reg_name[REGNO (X)], FILE); \ + break; \ + } \ + } while (0) + +#define PRINT_OPERAND(FILE, X, CODE) \ + print_operand (FILE, X, CODE) + +#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ + print_operand_address (FILE, ADDR) + +/* Print the name of a register for based on its machine mode and number. + This macro is used to print debugging output. + This macro is different from PRINT_REG in that it may be used in + programs that are not linked with aux-output.o. */ + +#define DEBUG_PRINT_REG(X, CODE, FILE) \ + do { static char *hi_name[] = HI_REGISTER_NAMES; \ + static char *qi_name[] = QI_REGISTER_NAMES; \ + fprintf (FILE, "%d %s", REGNO (X), RP); \ + if (REGNO (X) == ARG_POINTER_REGNUM) \ + { fputs ("argp", FILE); break; } \ + if (STACK_TOP_P (X)) \ + { fputs ("st(0)", FILE); break; } \ + if (FP_REG_P (X)) \ + { fputs (hi_name[REGNO(X)], FILE); break; } \ + switch (GET_MODE_SIZE (GET_MODE (X))) \ + { \ + default: \ + fputs ("e", FILE); \ + case 2: \ + fputs (hi_name[REGNO (X)], FILE); \ + break; \ + case 1: \ + fputs (qi_name[REGNO (X)], FILE); \ + break; \ + } \ + } while (0) + +/* Output the prefix for an immediate operand, or for an offset operand. */ +#define PRINT_IMMED_PREFIX(FILE) fputs (IP, (FILE)) +#define PRINT_OFFSET_PREFIX(FILE) fputs (IP, (FILE)) + +/* Routines in libgcc that return floats must return them in an fp reg, + just as other functions do which return such values. + These macros make that happen. */ + +#define FLOAT_VALUE_TYPE float +#define INTIFY(FLOATVAL) FLOATVAL + +/* Nonzero if INSN magically clobbers register REGNO. */ + +/* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) \ + (FP_REGNO_P (REGNO) \ + && (GET_CODE (INSN) == JUMP_INSN || GET_CODE (INSN) == BARRIER)) +*/ + +/* a letter which is not needed by the normal asm syntax, which + we can use for operand syntax in the extended asm */ + +#define ASM_OPERAND_LETTER '#' + +#define RET return "" +#define AT_SP(mode) (gen_rtx (MEM, (mode), stack_pointer_rtx)) + +/* Functions in i386.c */ +extern void override_options (); +extern void order_regs_for_local_alloc (); +extern int i386_valid_decl_attribute_p (); +extern int i386_valid_type_attribute_p (); +extern int i386_return_pops_args (); +extern int i386_comp_type_attributes (); +extern void init_cumulative_args (); +extern void function_arg_advance (); +extern struct rtx_def *function_arg (); +extern int function_arg_partial_nregs (); +extern void output_op_from_reg (); +extern void output_to_reg (); +extern char *singlemove_string (); +extern char *output_move_double (); +extern char *output_move_memory (); +extern char *output_move_pushmem (); +extern int standard_80387_constant_p (); +extern char *output_move_const_single (); +extern int symbolic_operand (); +extern int call_insn_operand (); +extern int expander_call_insn_operand (); +extern int symbolic_reference_mentioned_p (); +extern void emit_pic_move (); +extern void function_prologue (); +extern int simple_386_epilogue (); +extern void function_epilogue (); +extern int legitimate_address_p (); +extern struct rtx_def *legitimize_pic_address (); +extern struct rtx_def *legitimize_address (); +extern void print_operand (); +extern void print_operand_address (); +extern void notice_update_cc (); +extern void split_di (); +extern int binary_387_op (); +extern int shift_op (); +extern int VOIDmode_compare_op (); +extern char *output_387_binary_op (); +extern char *output_fix_trunc (); +extern char *output_float_compare (); +extern char *output_fp_cc0_set (); +extern void save_386_machine_status (); +extern void restore_386_machine_status (); +extern void clear_386_stack_locals (); +extern struct rtx_def *assign_386_stack_local (); + +/* Variables in i386.c */ +extern char *i386_reg_alloc_order; /* register allocation order */ +extern char *i386_regparm_string; /* # registers to use to pass args */ +extern char *i386_align_loops_string; /* power of two alignment for loops */ +extern char *i386_align_jumps_string; /* power of two alignment for non-loop jumps */ +extern char *i386_align_funcs_string; /* power of two alignment for functions */ +extern int i386_regparm; /* i386_regparm_string as a number */ +extern int i386_align_loops; /* power of two alignment for loops */ +extern int i386_align_jumps; /* power of two alignment for non-loop jumps */ +extern int i386_align_funcs; /* power of two alignment for functions */ +extern char *hi_reg_name[]; /* names for 16 bit regs */ +extern char *qi_reg_name[]; /* names for 8 bit regs (low) */ +extern char *qi_high_reg_name[]; /* names for 8 bit regs (high) */ +extern enum reg_class regclass_map[]; /* smalled class containing REGNO */ +extern struct rtx_def *i386_compare_op0; /* operand 0 for comparisons */ +extern struct rtx_def *i386_compare_op1; /* operand 1 for comparisons */ + +/* External variables used */ +extern int optimize; /* optimization level */ +extern int obey_regdecls; /* TRUE if stupid register allocation */ + +/* External functions used */ +extern struct rtx_def *force_operand (); + +/* +Local variables: +version-control: t +End: +*/ diff --git a/contrib/gcc/config/i386/i386.md b/contrib/gcc/config/i386/i386.md new file mode 100644 index 0000000..ff01196 --- /dev/null +++ b/contrib/gcc/config/i386/i386.md @@ -0,0 +1,5775 @@ +;; GCC machine description for Intel X86. +;; Copyright (C) 1988, 1994, 1995 Free Software Foundation, Inc. +;; Mostly by William Schelter. + +;; This file is part of GNU CC. + +;; GNU CC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. + +;; GNU CC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GNU CC; see the file COPYING. If not, write to +;; the Free Software Foundation, 59 Temple Place - Suite 330, +;; Boston, MA 02111-1307, USA. + + +;; The original PO technology requires these to be ordered by speed, +;; so that assigner will pick the fastest. + +;; See file "rtl.def" for documentation on define_insn, match_*, et. al. + +;; Macro #define NOTICE_UPDATE_CC in file i386.h handles condition code +;; updates for most instructions. + +;; Macro REG_CLASS_FROM_LETTER in file i386.h defines the register +;; constraint letters. + +;; the special asm out single letter directives following a '%' are: +;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of +;; operands[1]. +;; 'L' Print the opcode suffix for a 32-bit integer opcode. +;; 'W' Print the opcode suffix for a 16-bit integer opcode. +;; 'B' Print the opcode suffix for an 8-bit integer opcode. +;; 'S' Print the opcode suffix for a 32-bit float opcode. +;; 'Q' Print the opcode suffix for a 64-bit float opcode. +;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode. +;; 'J' Print the appropriate jump operand. + +;; 'b' Print the QImode name of the register for the indicated operand. +;; %b0 would print %al if operands[0] is reg 0. +;; 'w' Likewise, print the HImode name of the register. +;; 'k' Likewise, print the SImode name of the register. +;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh. +;; 'y' Print "st(0)" instead of "st" as a register. + +;; UNSPEC usage: +;; 0 This is a `scas' operation. The mode of the UNSPEC is always SImode. +;; operand 0 is the memory address to scan. +;; operand 1 is a register containing the value to scan for. The mode +;; of the scas opcode will be the same as the mode of this operand. +;; operand 2 is the known alignment of operand 0. +;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT. +;; operand 0 is the argument for `sin'. +;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT. +;; operand 0 is the argument for `cos'. + +;; "movl MEM,REG / testl REG,REG" is faster on a 486 than "cmpl $0,MEM". +;; But restricting MEM here would mean that gcc could not remove a redundant +;; test in cases like "incl MEM / je TARGET". +;; +;; We don't want to allow a constant operand for test insns because +;; (set (cc0) (const_int foo)) has no mode information. Such insns will +;; be folded while optimizing anyway. + +;; All test insns have expanders that save the operands away without +;; actually generating RTL. The bCOND or sCOND (emitted immediately +;; after the tstM or cmp) will actually emit the tstM or cmpM. + +(define_insn "tstsi_1" + [(set (cc0) + (match_operand:SI 0 "nonimmediate_operand" "rm"))] + "" + "* +{ + if (REG_P (operands[0])) + return AS2 (test%L0,%0,%0); + + operands[1] = const0_rtx; + return AS2 (cmp%L0,%1,%0); +}") + +(define_expand "tstsi" + [(set (cc0) + (match_operand:SI 0 "nonimmediate_operand" ""))] + "" + " +{ + i386_compare_gen = gen_tstsi_1; + i386_compare_op0 = operands[0]; + DONE; +}") + +(define_insn "tsthi_1" + [(set (cc0) + (match_operand:HI 0 "nonimmediate_operand" "rm"))] + "" + "* +{ + if (REG_P (operands[0])) + return AS2 (test%W0,%0,%0); + + operands[1] = const0_rtx; + return AS2 (cmp%W0,%1,%0); +}") + +(define_expand "tsthi" + [(set (cc0) + (match_operand:HI 0 "nonimmediate_operand" ""))] + "" + " +{ + i386_compare_gen = gen_tsthi_1; + i386_compare_op0 = operands[0]; + DONE; +}") + +(define_insn "tstqi_1" + [(set (cc0) + (match_operand:QI 0 "nonimmediate_operand" "qm"))] + "" + "* +{ + if (REG_P (operands[0])) + return AS2 (test%B0,%0,%0); + + operands[1] = const0_rtx; + return AS2 (cmp%B0,%1,%0); +}") + +(define_expand "tstqi" + [(set (cc0) + (match_operand:QI 0 "nonimmediate_operand" ""))] + "" + " +{ + i386_compare_gen = gen_tstqi_1; + i386_compare_op0 = operands[0]; + DONE; +}") + +(define_insn "tstsf_cc" + [(set (cc0) + (match_operand:SF 0 "register_operand" "f")) + (clobber (match_scratch:HI 1 "=a"))] + "TARGET_80387 && ! TARGET_IEEE_FP" + "* +{ + if (! STACK_TOP_P (operands[0])) + abort (); + + output_asm_insn (\"ftst\", operands); + + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + output_asm_insn (AS1 (fstp,%y0), operands); + + return output_fp_cc0_set (insn); +}") + +;; Don't generate tstsf if generating IEEE code, since the `ftst' opcode +;; isn't IEEE compliant. + +(define_expand "tstsf" + [(parallel [(set (cc0) + (match_operand:SF 0 "register_operand" "")) + (clobber (match_scratch:HI 1 ""))])] + "TARGET_80387 && ! TARGET_IEEE_FP" + " +{ + i386_compare_gen = gen_tstsf_cc; + i386_compare_op0 = operands[0]; + DONE; +}") + +(define_insn "tstdf_cc" + [(set (cc0) + (match_operand:DF 0 "register_operand" "f")) + (clobber (match_scratch:HI 1 "=a"))] + "TARGET_80387 && ! TARGET_IEEE_FP" + "* +{ + if (! STACK_TOP_P (operands[0])) + abort (); + + output_asm_insn (\"ftst\", operands); + + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + output_asm_insn (AS1 (fstp,%y0), operands); + + return output_fp_cc0_set (insn); +}") + +;; Don't generate tstdf if generating IEEE code, since the `ftst' opcode +;; isn't IEEE compliant. + +(define_expand "tstdf" + [(parallel [(set (cc0) + (match_operand:DF 0 "register_operand" "")) + (clobber (match_scratch:HI 1 ""))])] + "TARGET_80387 && ! TARGET_IEEE_FP" + " +{ + i386_compare_gen = gen_tstdf_cc; + i386_compare_op0 = operands[0]; + DONE; +}") + +(define_insn "tstxf_cc" + [(set (cc0) + (match_operand:XF 0 "register_operand" "f")) + (clobber (match_scratch:HI 1 "=a"))] + "TARGET_80387 && ! TARGET_IEEE_FP" + "* +{ + if (! STACK_TOP_P (operands[0])) + abort (); + + output_asm_insn (\"ftst\", operands); + + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + output_asm_insn (AS1 (fstp,%y0), operands); + + return output_fp_cc0_set (insn); +}") + +;; Don't generate tstdf if generating IEEE code, since the `ftst' opcode +;; isn't IEEE compliant. + +(define_expand "tstxf" + [(parallel [(set (cc0) + (match_operand:XF 0 "register_operand" "")) + (clobber (match_scratch:HI 1 ""))])] + "TARGET_80387 && ! TARGET_IEEE_FP" + " +{ + i386_compare_gen = gen_tstxf_cc; + i386_compare_op0 = operands[0]; + DONE; +}") + +;;- compare instructions. See comments above tstM patterns about +;; expansion of these insns. + +(define_insn "cmpsi_1" + [(set (cc0) + (compare (match_operand:SI 0 "nonimmediate_operand" "mr,r") + (match_operand:SI 1 "general_operand" "ri,mr")))] + "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" + "* +{ + if (CONSTANT_P (operands[0]) || GET_CODE (operands[1]) == MEM) + { + cc_status.flags |= CC_REVERSED; + return AS2 (cmp%L0,%0,%1); + } + return AS2 (cmp%L0,%1,%0); +}") + +(define_expand "cmpsi" + [(set (cc0) + (compare (match_operand:SI 0 "nonimmediate_operand" "") + (match_operand:SI 1 "general_operand" "")))] + "" + " +{ + if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) + operands[0] = force_reg (SImode, operands[0]); + + i386_compare_gen = gen_cmpsi_1; + i386_compare_op0 = operands[0]; + i386_compare_op1 = operands[1]; + DONE; +}") + +(define_insn "cmphi_1" + [(set (cc0) + (compare (match_operand:HI 0 "nonimmediate_operand" "mr,r") + (match_operand:HI 1 "general_operand" "ri,mr")))] + "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" + "* +{ + if (CONSTANT_P (operands[0]) || GET_CODE (operands[1]) == MEM) + { + cc_status.flags |= CC_REVERSED; + return AS2 (cmp%W0,%0,%1); + } + return AS2 (cmp%W0,%1,%0); +}") + +(define_expand "cmphi" + [(set (cc0) + (compare (match_operand:HI 0 "nonimmediate_operand" "") + (match_operand:HI 1 "general_operand" "")))] + "" + " +{ + if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) + operands[0] = force_reg (HImode, operands[0]); + + i386_compare_gen = gen_cmphi_1; + i386_compare_op0 = operands[0]; + i386_compare_op1 = operands[1]; + DONE; +}") + +(define_insn "cmpqi_1" + [(set (cc0) + (compare (match_operand:QI 0 "nonimmediate_operand" "q,mq") + (match_operand:QI 1 "general_operand" "qm,nq")))] + "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" + "* +{ + if (CONSTANT_P (operands[0]) || GET_CODE (operands[1]) == MEM) + { + cc_status.flags |= CC_REVERSED; + return AS2 (cmp%B0,%0,%1); + } + return AS2 (cmp%B0,%1,%0); +}") + +(define_expand "cmpqi" + [(set (cc0) + (compare (match_operand:QI 0 "nonimmediate_operand" "") + (match_operand:QI 1 "general_operand" "")))] + "" + " +{ + if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) + operands[0] = force_reg (QImode, operands[0]); + + i386_compare_gen = gen_cmpqi_1; + i386_compare_op0 = operands[0]; + i386_compare_op1 = operands[1]; + DONE; +}") + +;; These implement float point compares. For each of DFmode and +;; SFmode, there is the normal insn, and an insn where the second operand +;; is converted to the desired mode. + +(define_insn "" + [(set (cc0) + (match_operator 2 "VOIDmode_compare_op" + [(match_operand:XF 0 "nonimmediate_operand" "f") + (match_operand:XF 1 "nonimmediate_operand" "f")])) + (clobber (match_scratch:HI 3 "=a"))] + "TARGET_80387 + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" + "* return output_float_compare (insn, operands);") + +(define_insn "" + [(set (cc0) + (match_operator 2 "VOIDmode_compare_op" + [(match_operand:XF 0 "register_operand" "f") + (float:XF + (match_operand:SI 1 "nonimmediate_operand" "rm"))])) + (clobber (match_scratch:HI 3 "=a"))] + "TARGET_80387" + "* return output_float_compare (insn, operands);") + +(define_insn "" + [(set (cc0) + (match_operator 2 "VOIDmode_compare_op" + [(float:XF + (match_operand:SI 0 "nonimmediate_operand" "rm")) + (match_operand:XF 1 "register_operand" "f")])) + (clobber (match_scratch:HI 3 "=a"))] + "TARGET_80387" + "* return output_float_compare (insn, operands);") + +(define_insn "" + [(set (cc0) + (match_operator 2 "VOIDmode_compare_op" + [(match_operand:XF 0 "register_operand" "f") + (float_extend:XF + (match_operand:DF 1 "nonimmediate_operand" "fm"))])) + (clobber (match_scratch:HI 3 "=a"))] + "TARGET_80387" + "* return output_float_compare (insn, operands);") + +(define_insn "" + [(set (cc0) + (match_operator 2 "VOIDmode_compare_op" + [(match_operand:XF 0 "register_operand" "f") + (float_extend:XF + (match_operand:SF 1 "nonimmediate_operand" "fm"))])) + (clobber (match_scratch:HI 3 "=a"))] + "TARGET_80387" + "* return output_float_compare (insn, operands);") + +(define_insn "" + [(set (cc0) + (compare:CCFPEQ (match_operand:XF 0 "register_operand" "f") + (match_operand:XF 1 "register_operand" "f"))) + (clobber (match_scratch:HI 2 "=a"))] + "TARGET_80387" + "* return output_float_compare (insn, operands);") + +(define_insn "" + [(set (cc0) + (match_operator 2 "VOIDmode_compare_op" + [(match_operand:DF 0 "nonimmediate_operand" "f,fm") + (match_operand:DF 1 "nonimmediate_operand" "fm,f")])) + (clobber (match_scratch:HI 3 "=a,a"))] + "TARGET_80387 + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" + "* return output_float_compare (insn, operands);") + +(define_insn "" + [(set (cc0) + (match_operator 2 "VOIDmode_compare_op" + [(match_operand:DF 0 "register_operand" "f") + (float:DF + (match_operand:SI 1 "nonimmediate_operand" "rm"))])) + (clobber (match_scratch:HI 3 "=a"))] + "TARGET_80387" + "* return output_float_compare (insn, operands);") + +(define_insn "" + [(set (cc0) + (match_operator 2 "VOIDmode_compare_op" + [(float:DF + (match_operand:SI 0 "nonimmediate_operand" "rm")) + (match_operand:DF 1 "register_operand" "f")])) + (clobber (match_scratch:HI 3 "=a"))] + "TARGET_80387" + "* return output_float_compare (insn, operands);") + +(define_insn "" + [(set (cc0) + (match_operator 2 "VOIDmode_compare_op" + [(match_operand:DF 0 "register_operand" "f") + (float_extend:DF + (match_operand:SF 1 "nonimmediate_operand" "fm"))])) + (clobber (match_scratch:HI 3 "=a"))] + "TARGET_80387" + "* return output_float_compare (insn, operands);") + +(define_insn "" + [(set (cc0) + (match_operator 2 "VOIDmode_compare_op" + [(float_extend:DF + (match_operand:SF 0 "nonimmediate_operand" "fm")) + (match_operand:DF 1 "register_operand" "f")])) + (clobber (match_scratch:HI 3 "=a"))] + "TARGET_80387" + "* return output_float_compare (insn, operands);") + +(define_insn "" + [(set (cc0) + (compare:CCFPEQ (match_operand:DF 0 "register_operand" "f") + (match_operand:DF 1 "register_operand" "f"))) + (clobber (match_scratch:HI 2 "=a"))] + "TARGET_80387" + "* return output_float_compare (insn, operands);") + +;; These two insns will never be generated by combine due to the mode of +;; the COMPARE. +;(define_insn "" +; [(set (cc0) +; (compare:CCFPEQ (match_operand:DF 0 "register_operand" "f") +; (float_extend:DF +; (match_operand:SF 1 "register_operand" "f")))) +; (clobber (match_scratch:HI 2 "=a"))] +; "TARGET_80387" +; "* return output_float_compare (insn, operands);") +; +;(define_insn "" +; [(set (cc0) +; (compare:CCFPEQ (float_extend:DF +; (match_operand:SF 0 "register_operand" "f")) +; (match_operand:DF 1 "register_operand" "f"))) +; (clobber (match_scratch:HI 2 "=a"))] +; "TARGET_80387" +; "* return output_float_compare (insn, operands);") + +(define_insn "cmpsf_cc_1" + [(set (cc0) + (match_operator 2 "VOIDmode_compare_op" + [(match_operand:SF 0 "nonimmediate_operand" "f,fm") + (match_operand:SF 1 "nonimmediate_operand" "fm,f")])) + (clobber (match_scratch:HI 3 "=a,a"))] + "TARGET_80387 + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" + "* return output_float_compare (insn, operands);") + +(define_insn "" + [(set (cc0) + (match_operator 2 "VOIDmode_compare_op" + [(match_operand:SF 0 "register_operand" "f") + (float:SF + (match_operand:SI 1 "nonimmediate_operand" "rm"))])) + (clobber (match_scratch:HI 3 "=a"))] + "TARGET_80387" + "* return output_float_compare (insn, operands);") + +(define_insn "" + [(set (cc0) + (match_operator 2 "VOIDmode_compare_op" + [(float:SF + (match_operand:SI 0 "nonimmediate_operand" "rm")) + (match_operand:SF 1 "register_operand" "f")])) + (clobber (match_scratch:HI 3 "=a"))] + "TARGET_80387" + "* return output_float_compare (insn, operands);") + +(define_insn "" + [(set (cc0) + (compare:CCFPEQ (match_operand:SF 0 "register_operand" "f") + (match_operand:SF 1 "register_operand" "f"))) + (clobber (match_scratch:HI 2 "=a"))] + "TARGET_80387" + "* return output_float_compare (insn, operands);") + +(define_expand "cmpxf" + [(set (cc0) + (compare (match_operand:XF 0 "register_operand" "") + (match_operand:XF 1 "nonimmediate_operand" "")))] + "TARGET_80387" + " +{ + i386_compare_gen = gen_cmpxf_cc; + i386_compare_gen_eq = gen_cmpxf_ccfpeq; + i386_compare_op0 = operands[0]; + i386_compare_op1 = operands[1]; + DONE; +}") + +(define_expand "cmpdf" + [(set (cc0) + (compare (match_operand:DF 0 "register_operand" "") + (match_operand:DF 1 "nonimmediate_operand" "")))] + "TARGET_80387" + " +{ + i386_compare_gen = gen_cmpdf_cc; + i386_compare_gen_eq = gen_cmpdf_ccfpeq; + i386_compare_op0 = operands[0]; + i386_compare_op1 = operands[1]; + DONE; +}") + +(define_expand "cmpsf" + [(set (cc0) + (compare (match_operand:SF 0 "register_operand" "") + (match_operand:SF 1 "nonimmediate_operand" "")))] + "TARGET_80387" + " +{ + i386_compare_gen = gen_cmpsf_cc; + i386_compare_gen_eq = gen_cmpsf_ccfpeq; + i386_compare_op0 = operands[0]; + i386_compare_op1 = operands[1]; + DONE; +}") + +(define_expand "cmpxf_cc" + [(parallel [(set (cc0) + (compare (match_operand:XF 0 "register_operand" "") + (match_operand:XF 1 "register_operand" ""))) + (clobber (match_scratch:HI 2 ""))])] + "TARGET_80387" + "") + +(define_expand "cmpxf_ccfpeq" + [(parallel [(set (cc0) + (compare:CCFPEQ (match_operand:XF 0 "register_operand" "") + (match_operand:XF 1 "register_operand" ""))) + (clobber (match_scratch:HI 2 ""))])] + "TARGET_80387" + " +{ + if (! register_operand (operands[1], XFmode)) + operands[1] = copy_to_mode_reg (XFmode, operands[1]); +}") + +(define_expand "cmpdf_cc" + [(parallel [(set (cc0) + (compare (match_operand:DF 0 "register_operand" "") + (match_operand:DF 1 "register_operand" ""))) + (clobber (match_scratch:HI 2 ""))])] + "TARGET_80387" + "") + +(define_expand "cmpdf_ccfpeq" + [(parallel [(set (cc0) + (compare:CCFPEQ (match_operand:DF 0 "register_operand" "") + (match_operand:DF 1 "register_operand" ""))) + (clobber (match_scratch:HI 2 ""))])] + "TARGET_80387" + " +{ + if (! register_operand (operands[1], DFmode)) + operands[1] = copy_to_mode_reg (DFmode, operands[1]); +}") + +(define_expand "cmpsf_cc" + [(parallel [(set (cc0) + (compare (match_operand:SF 0 "register_operand" "") + (match_operand:SF 1 "register_operand" ""))) + (clobber (match_scratch:HI 2 ""))])] + "TARGET_80387" + "") + +(define_expand "cmpsf_ccfpeq" + [(parallel [(set (cc0) + (compare:CCFPEQ (match_operand:SF 0 "register_operand" "") + (match_operand:SF 1 "register_operand" ""))) + (clobber (match_scratch:HI 2 ""))])] + "TARGET_80387" + " +{ + if (! register_operand (operands[1], SFmode)) + operands[1] = copy_to_mode_reg (SFmode, operands[1]); +}") + +;; logical compare + +(define_insn "" + [(set (cc0) + (and:SI (match_operand:SI 0 "general_operand" "%ro") + (match_operand:SI 1 "general_operand" "ri")))] + "" + "* +{ + /* For small integers, we may actually use testb. */ + if (GET_CODE (operands[1]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])) + && (! REG_P (operands[0]) || QI_REG_P (operands[0]))) + { + /* We may set the sign bit spuriously. */ + + if ((INTVAL (operands[1]) & ~0xff) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + return AS2 (test%B0,%1,%b0); + } + + if ((INTVAL (operands[1]) & ~0xff00) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + operands[1] = GEN_INT (INTVAL (operands[1]) >> 8); + + if (QI_REG_P (operands[0])) + return AS2 (test%B0,%1,%h0); + else + { + operands[0] = adj_offsettable_operand (operands[0], 1); + return AS2 (test%B0,%1,%b0); + } + } + + if (GET_CODE (operands[0]) == MEM + && (INTVAL (operands[1]) & ~0xff0000) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + operands[1] = GEN_INT (INTVAL (operands[1]) >> 16); + operands[0] = adj_offsettable_operand (operands[0], 2); + return AS2 (test%B0,%1,%b0); + } + + if (GET_CODE (operands[0]) == MEM + && (INTVAL (operands[1]) & ~0xff000000) == 0) + { + operands[1] = GEN_INT ((INTVAL (operands[1]) >> 24) & 0xff); + operands[0] = adj_offsettable_operand (operands[0], 3); + return AS2 (test%B0,%1,%b0); + } + } + + if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM) + return AS2 (test%L0,%1,%0); + + return AS2 (test%L1,%0,%1); +}") + +(define_insn "" + [(set (cc0) + (and:HI (match_operand:HI 0 "general_operand" "%ro") + (match_operand:HI 1 "general_operand" "ri")))] + "" + "* +{ + if (GET_CODE (operands[1]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])) + && (! REG_P (operands[0]) || QI_REG_P (operands[0]))) + { + if ((INTVAL (operands[1]) & 0xff00) == 0) + { + /* ??? This might not be necessary. */ + if (INTVAL (operands[1]) & 0xffff0000) + operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff); + + /* We may set the sign bit spuriously. */ + cc_status.flags |= CC_NOT_NEGATIVE; + return AS2 (test%B0,%1,%b0); + } + + if ((INTVAL (operands[1]) & 0xff) == 0) + { + operands[1] = GEN_INT ((INTVAL (operands[1]) >> 8) & 0xff); + + if (QI_REG_P (operands[0])) + return AS2 (test%B0,%1,%h0); + else + { + operands[0] = adj_offsettable_operand (operands[0], 1); + return AS2 (test%B0,%1,%b0); + } + } + } + + if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM) + return AS2 (test%W0,%1,%0); + + return AS2 (test%W1,%0,%1); +}") + +(define_insn "" + [(set (cc0) + (and:QI (match_operand:QI 0 "general_operand" "%qm") + (match_operand:QI 1 "general_operand" "qi")))] + "" + "* +{ + if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM) + return AS2 (test%B0,%1,%0); + + return AS2 (test%B1,%0,%1); +}") + +;; move instructions. +;; There is one for each machine mode, +;; and each is preceded by a corresponding push-insn pattern +;; (since pushes are not general_operands on the 386). + +(define_insn "" + [(set (match_operand:SI 0 "push_operand" "=<") + (match_operand:SI 1 "general_operand" "g"))] + "TARGET_386" + "push%L0 %1") + +;; On a 486, it is faster to move MEM to a REG and then push, rather than +;; push MEM directly. + +(define_insn "" + [(set (match_operand:SI 0 "push_operand" "=<") + (match_operand:SI 1 "nonmemory_operand" "ri"))] + "!TARGET_386 && TARGET_MOVE" + "push%L0 %1") + +(define_insn "" + [(set (match_operand:SI 0 "push_operand" "=<") + (match_operand:SI 1 "general_operand" "ri"))] + "!TARGET_386 && !TARGET_MOVE" + "push%L0 %1") + +;; General case of fullword move. + +;; If generating PIC code and operands[1] is a symbolic CONST, emit a +;; move to get the address of the symbolic object from the GOT. + +(define_expand "movsi" + [(set (match_operand:SI 0 "general_operand" "") + (match_operand:SI 1 "general_operand" ""))] + "" + " +{ + extern int flag_pic; + + if (flag_pic && SYMBOLIC_CONST (operands[1])) + emit_pic_move (operands, SImode); + + /* Don't generate memory->memory moves, go through a register */ + else if (TARGET_MOVE + && (reload_in_progress | reload_completed) == 0 + && GET_CODE (operands[0]) == MEM + && GET_CODE (operands[1]) == MEM) + { + operands[1] = force_reg (SImode, operands[1]); + } +}") + +;; On i486, incl reg is faster than movl $1,reg. + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=g,r") + (match_operand:SI 1 "general_operand" "ri,m"))] + "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" + "* +{ + rtx link; + if (operands[1] == const0_rtx && REG_P (operands[0])) + return AS2 (xor%L0,%0,%0); + + if (operands[1] == const1_rtx + && (link = find_reg_note (insn, REG_WAS_0, 0)) + /* Make sure the insn that stored the 0 is still present. */ + && ! INSN_DELETED_P (XEXP (link, 0)) + && GET_CODE (XEXP (link, 0)) != NOTE + /* Make sure cross jumping didn't happen here. */ + && no_labels_between_p (XEXP (link, 0), insn) + /* Make sure the reg hasn't been clobbered. */ + && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) + /* Fastest way to change a 0 to a 1. */ + return AS1 (inc%L0,%0); + + if (flag_pic && SYMBOLIC_CONST (operands[1])) + return AS2 (lea%L0,%a1,%0); + + return AS2 (mov%L0,%1,%0); +}") + +(define_insn "" + [(set (match_operand:HI 0 "push_operand" "=<") + (match_operand:HI 1 "general_operand" "g"))] + "TARGET_386" + "push%W0 %1") + +(define_insn "" + [(set (match_operand:HI 0 "push_operand" "=<") + (match_operand:HI 1 "nonmemory_operand" "ri"))] + "!TARGET_386 && TARGET_MOVE" + "push%W0 %1") + +(define_insn "" + [(set (match_operand:HI 0 "push_operand" "=<") + (match_operand:HI 1 "general_operand" "ri"))] + "!TARGET_386 && !TARGET_MOVE" + "push%W0 %1") + +;; On i486, an incl and movl are both faster than incw and movw. + +(define_expand "movhi" + [(set (match_operand:HI 0 "general_operand" "") + (match_operand:HI 1 "general_operand" ""))] + "" + " +{ + /* Don't generate memory->memory moves, go through a register */ + if (TARGET_MOVE + && (reload_in_progress | reload_completed) == 0 + && GET_CODE (operands[0]) == MEM + && GET_CODE (operands[1]) == MEM) + { + operands[1] = force_reg (HImode, operands[1]); + } +}") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=g,r") + (match_operand:HI 1 "general_operand" "ri,m"))] + "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" + "* +{ + rtx link; + if (REG_P (operands[0]) && operands[1] == const0_rtx) + return AS2 (xor%L0,%k0,%k0); + + if (REG_P (operands[0]) && operands[1] == const1_rtx + && (link = find_reg_note (insn, REG_WAS_0, 0)) + /* Make sure the insn that stored the 0 is still present. */ + && ! INSN_DELETED_P (XEXP (link, 0)) + && GET_CODE (XEXP (link, 0)) != NOTE + /* Make sure cross jumping didn't happen here. */ + && no_labels_between_p (XEXP (link, 0), insn) + /* Make sure the reg hasn't been clobbered. */ + && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) + /* Fastest way to change a 0 to a 1. */ + return AS1 (inc%L0,%k0); + + if (REG_P (operands[0])) + { + if (REG_P (operands[1])) + return AS2 (mov%L0,%k1,%k0); + else if (CONSTANT_P (operands[1])) + return AS2 (mov%L0,%1,%k0); + } + + return AS2 (mov%W0,%1,%0); +}") + +(define_expand "movstricthi" + [(set (strict_low_part (match_operand:HI 0 "general_operand" "")) + (match_operand:HI 1 "general_operand" ""))] + "" + " +{ + /* Don't generate memory->memory moves, go through a register */ + if (TARGET_MOVE + && (reload_in_progress | reload_completed) == 0 + && GET_CODE (operands[0]) == MEM + && GET_CODE (operands[1]) == MEM) + { + operands[1] = force_reg (HImode, operands[1]); + } +}") + +(define_insn "" + [(set (strict_low_part (match_operand:HI 0 "general_operand" "+g,r")) + (match_operand:HI 1 "general_operand" "ri,m"))] + "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" + "* +{ + rtx link; + if (operands[1] == const0_rtx && REG_P (operands[0])) + return AS2 (xor%W0,%0,%0); + + if (operands[1] == const1_rtx + && (link = find_reg_note (insn, REG_WAS_0, 0)) + /* Make sure the insn that stored the 0 is still present. */ + && ! INSN_DELETED_P (XEXP (link, 0)) + && GET_CODE (XEXP (link, 0)) != NOTE + /* Make sure cross jumping didn't happen here. */ + && no_labels_between_p (XEXP (link, 0), insn) + /* Make sure the reg hasn't been clobbered. */ + && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) + /* Fastest way to change a 0 to a 1. */ + return AS1 (inc%W0,%0); + + return AS2 (mov%W0,%1,%0); +}") + +;; emit_push_insn when it calls move_by_pieces +;; requires an insn to "push a byte". +;; But actually we use pushw, which has the effect of rounding +;; the amount pushed up to a halfword. +(define_insn "" + [(set (match_operand:QI 0 "push_operand" "=<") + (match_operand:QI 1 "immediate_operand" "n"))] + "" + "* return AS1 (push%W0,%1);") + +(define_insn "" + [(set (match_operand:QI 0 "push_operand" "=<") + (match_operand:QI 1 "nonimmediate_operand" "q"))] + "!TARGET_MOVE" + "* +{ + operands[1] = gen_rtx (REG, HImode, REGNO (operands[1])); + return AS1 (push%W0,%1); +}") + +(define_insn "" + [(set (match_operand:QI 0 "push_operand" "=<") + (match_operand:QI 1 "register_operand" "q"))] + "TARGET_MOVE" + "* +{ + operands[1] = gen_rtx (REG, HImode, REGNO (operands[1])); + return AS1 (push%W0,%1); +}") + +;; On i486, incb reg is faster than movb $1,reg. + +;; ??? Do a recognizer for zero_extract that looks just like this, but reads +;; or writes %ah, %bh, %ch, %dh. + +(define_expand "movqi" + [(set (match_operand:QI 0 "general_operand" "") + (match_operand:QI 1 "general_operand" ""))] + "" + " +{ + /* Don't generate memory->memory moves, go through a register */ + if (TARGET_MOVE + && (reload_in_progress | reload_completed) == 0 + && GET_CODE (operands[0]) == MEM + && GET_CODE (operands[1]) == MEM) + { + operands[1] = force_reg (QImode, operands[1]); + } +}") + +(define_insn "" + [(set (match_operand:QI 0 "general_operand" "=q,*r,qm") + (match_operand:QI 1 "general_operand" "*g,q,qn"))] + "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" + "* +{ + rtx link; + if (operands[1] == const0_rtx && REG_P (operands[0])) + return AS2 (xor%B0,%0,%0); + + if (operands[1] == const1_rtx + && (link = find_reg_note (insn, REG_WAS_0, 0)) + /* Make sure the insn that stored the 0 is still present. */ + && ! INSN_DELETED_P (XEXP (link, 0)) + && GET_CODE (XEXP (link, 0)) != NOTE + /* Make sure cross jumping didn't happen here. */ + && no_labels_between_p (XEXP (link, 0), insn) + /* Make sure the reg hasn't been clobbered. */ + && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) + /* Fastest way to change a 0 to a 1. */ + return AS1 (inc%B0,%0); + + /* If mov%B0 isn't allowed for one of these regs, use mov%L0. */ + if (NON_QI_REG_P (operands[0]) || NON_QI_REG_P (operands[1])) + return (AS2 (mov%L0,%k1,%k0)); + + return (AS2 (mov%B0,%1,%0)); +}") + +;; If it becomes necessary to support movstrictqi into %esi or %edi, +;; use the insn sequence: +;; +;; shrdl $8,srcreg,dstreg +;; rorl $24,dstreg +;; +;; If operands[1] is a constant, then an andl/orl sequence would be +;; faster. + +(define_expand "movstrictqi" + [(set (strict_low_part (match_operand:QI 0 "general_operand" "")) + (match_operand:QI 1 "general_operand" ""))] + "" + " +{ + /* Don't generate memory->memory moves, go through a register */ + if (TARGET_MOVE + && (reload_in_progress | reload_completed) == 0 + && GET_CODE (operands[0]) == MEM + && GET_CODE (operands[1]) == MEM) + { + operands[1] = force_reg (QImode, operands[1]); + } +}") + +(define_insn "" + [(set (strict_low_part (match_operand:QI 0 "general_operand" "+qm,q")) + (match_operand:QI 1 "general_operand" "*qn,m"))] + "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" + "* +{ + rtx link; + if (operands[1] == const0_rtx && REG_P (operands[0])) + return AS2 (xor%B0,%0,%0); + + if (operands[1] == const1_rtx + && (link = find_reg_note (insn, REG_WAS_0, 0)) + /* Make sure the insn that stored the 0 is still present. */ + && ! INSN_DELETED_P (XEXP (link, 0)) + && GET_CODE (XEXP (link, 0)) != NOTE + /* Make sure cross jumping didn't happen here. */ + && no_labels_between_p (XEXP (link, 0), insn) + /* Make sure the reg hasn't been clobbered. */ + && ! reg_set_between_p (operands[0], XEXP (link, 0), insn)) + /* Fastest way to change a 0 to a 1. */ + return AS1 (inc%B0,%0); + + /* If mov%B0 isn't allowed for one of these regs, use mov%L0. */ + if (NON_QI_REG_P (operands[0]) || NON_QI_REG_P (operands[1])) + { + abort (); + return (AS2 (mov%L0,%k1,%k0)); + } + + return AS2 (mov%B0,%1,%0); +}") + +(define_expand "movsf" + [(set (match_operand:SF 0 "general_operand" "") + (match_operand:SF 1 "general_operand" ""))] + "" + " +{ + /* Special case memory->memory moves and pushes */ + if (TARGET_MOVE + && (reload_in_progress | reload_completed) == 0 + && GET_CODE (operands[0]) == MEM + && (GET_CODE (operands[1]) == MEM || push_operand (operands[0], SFmode))) + { + rtx (*genfunc) PROTO((rtx, rtx)) = (push_operand (operands[0], SFmode)) + ? gen_movsf_push + : gen_movsf_mem; + + emit_insn ((*genfunc) (operands[0], operands[1])); + DONE; + } + + /* If we are loading a floating point constant that isn't 0 or 1 into a register, + indicate we need the pic register loaded. This could be optimized into stores + of constants if the target eventually moves to memory, but better safe than + sorry. */ + if (flag_pic + && GET_CODE (operands[0]) != MEM + && GET_CODE (operands[1]) == CONST_DOUBLE + && !standard_80387_constant_p (operands[1])) + { + current_function_uses_pic_offset_table = 1; + } +}") + +(define_insn "movsf_push_nomove" + [(set (match_operand:SF 0 "push_operand" "=<,<") + (match_operand:SF 1 "general_operand" "gF,f"))] + "!TARGET_MOVE" + "* +{ + if (STACK_REG_P (operands[1])) + { + rtx xops[3]; + + if (! STACK_TOP_P (operands[1])) + abort (); + + xops[0] = AT_SP (SFmode); + xops[1] = GEN_INT (4); + xops[2] = stack_pointer_rtx; + + output_asm_insn (AS2 (sub%L2,%1,%2), xops); + + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + output_asm_insn (AS1 (fstp%S0,%0), xops); + else + output_asm_insn (AS1 (fst%S0,%0), xops); + RET; + } + return AS1 (push%L1,%1); +}") + +(define_insn "movsf_push" + [(set (match_operand:SF 0 "push_operand" "=<,<,<,<") + (match_operand:SF 1 "general_operand" "rF,f,m,m")) + (clobber (match_scratch:SI 2 "=X,X,r,X"))] + "" + "* +{ + if (STACK_REG_P (operands[1])) + { + rtx xops[3]; + + if (! STACK_TOP_P (operands[1])) + abort (); + + xops[0] = AT_SP (SFmode); + xops[1] = GEN_INT (4); + xops[2] = stack_pointer_rtx; + + output_asm_insn (AS2 (sub%L2,%1,%2), xops); + + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + output_asm_insn (AS1 (fstp%S0,%0), xops); + else + output_asm_insn (AS1 (fst%S0,%0), xops); + RET; + } + + else if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != REG) + return AS1 (push%L1,%1); + + else + { + output_asm_insn (AS2 (mov%L2,%1,%2), operands); + return AS1 (push%L2,%2); + } +}") + +;; Special memory<->memory pattern that combine will recreate from the +;; moves to pseudos. +(define_insn "movsf_mem" + [(set (match_operand:SF 0 "memory_operand" "=m") + (match_operand:SF 1 "memory_operand" "m")) + (clobber (match_scratch:SI 2 "=&r"))] + "" + "* +{ + output_asm_insn (AS2 (mov%L2,%1,%2), operands); + return AS2 (mov%L0,%2,%0); +}") + +;; For the purposes of regclass, prefer FLOAT_REGS. +(define_insn "movsf_normal" + [(set (match_operand:SF 0 "general_operand" "=*rfm,*rf,f,!*rm") + (match_operand:SF 1 "general_operand" "*rf,*rfm,fG,fF"))] + "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" + "* +{ + int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + + /* First handle a `pop' insn or a `fld %st(0)' */ + + if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1])) + { + if (stack_top_dies) + return AS1 (fstp,%y0); + else + return AS1 (fld,%y0); + } + + /* Handle a transfer between the 387 and a 386 register */ + + if (STACK_TOP_P (operands[0]) && NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); + RET; + } + + if (STACK_TOP_P (operands[1]) && NON_STACK_REG_P (operands[0])) + { + output_to_reg (operands[0], stack_top_dies); + RET; + } + + /* Handle other kinds of writes from the 387 */ + + if (STACK_TOP_P (operands[1])) + { + if (stack_top_dies) + return AS1 (fstp%z0,%y0); + else + return AS1 (fst%z0,%y0); + } + + /* Handle other kinds of reads to the 387 */ + + if (STACK_TOP_P (operands[0]) && GET_CODE (operands[1]) == CONST_DOUBLE) + return output_move_const_single (operands); + + if (STACK_TOP_P (operands[0])) + return AS1 (fld%z1,%y1); + + /* Handle all SFmode moves not involving the 387 */ + + return singlemove_string (operands); +}") + +(define_insn "swapsf" + [(set (match_operand:SF 0 "register_operand" "f") + (match_operand:SF 1 "register_operand" "f")) + (set (match_dup 1) + (match_dup 0))] + "" + "* +{ + if (STACK_TOP_P (operands[0])) + return AS1 (fxch,%1); + else + return AS1 (fxch,%0); +}") + +(define_expand "movdf" + [(set (match_operand:DF 0 "general_operand" "") + (match_operand:DF 1 "general_operand" ""))] + "" + " +{ + /* Special case memory->memory moves and pushes */ + if (TARGET_MOVE + && (reload_in_progress | reload_completed) == 0 + && GET_CODE (operands[0]) == MEM + && (GET_CODE (operands[1]) == MEM || push_operand (operands[0], DFmode))) + { + rtx (*genfunc) PROTO((rtx, rtx)) = (push_operand (operands[0], DFmode)) + ? gen_movdf_push + : gen_movdf_mem; + + emit_insn ((*genfunc) (operands[0], operands[1])); + DONE; + } + + /* If we are loading a floating point constant that isn't 0 or 1 into a register, + indicate we need the pic register loaded. This could be optimized into stores + of constants if the target eventually moves to memory, but better safe than + sorry. */ + if (flag_pic + && GET_CODE (operands[0]) != MEM + && GET_CODE (operands[1]) == CONST_DOUBLE + && !standard_80387_constant_p (operands[1])) + { + current_function_uses_pic_offset_table = 1; + } +}") + +(define_insn "movdf_push_nomove" + [(set (match_operand:DF 0 "push_operand" "=<,<") + (match_operand:DF 1 "general_operand" "gF,f"))] + "!TARGET_MOVE" + "* +{ + if (STACK_REG_P (operands[1])) + { + rtx xops[3]; + + xops[0] = AT_SP (SFmode); + xops[1] = GEN_INT (8); + xops[2] = stack_pointer_rtx; + + output_asm_insn (AS2 (sub%L2,%1,%2), xops); + + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + output_asm_insn (AS1 (fstp%Q0,%0), xops); + else + output_asm_insn (AS1 (fst%Q0,%0), xops); + + RET; + } + else + return output_move_double (operands); +}") + +(define_insn "movdf_push" + [(set (match_operand:DF 0 "push_operand" "=<,<,<,<,<") + (match_operand:DF 1 "general_operand" "rF,f,o,o,o")) + (clobber (match_scratch:SI 2 "=X,X,&r,&r,X")) + (clobber (match_scratch:SI 3 "=X,X,&r,X,X"))] + "" + "* +{ + if (STACK_REG_P (operands[1])) + { + rtx xops[3]; + + xops[0] = AT_SP (SFmode); + xops[1] = GEN_INT (8); + xops[2] = stack_pointer_rtx; + + output_asm_insn (AS2 (sub%L2,%1,%2), xops); + + if (find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + output_asm_insn (AS1 (fstp%Q0,%0), xops); + else + output_asm_insn (AS1 (fst%Q0,%0), xops); + + RET; + } + + else if (GET_CODE (operands[1]) != MEM) + return output_move_double (operands); + + else + return output_move_pushmem (operands, insn, GET_MODE_SIZE (DFmode), 2, 4); +}") + +(define_insn "movdf_mem" + [(set (match_operand:DF 0 "memory_operand" "=o,o") + (match_operand:DF 1 "memory_operand" "o,o")) + (clobber (match_scratch:SI 2 "=&r,&r")) + (clobber (match_scratch:SI 3 "=&r,X"))] + "" + "* return output_move_memory (operands, insn, GET_MODE_SIZE (DFmode), 2, 4);") + +;; For the purposes of regclass, prefer FLOAT_REGS. +(define_insn "movdf_normal" + [(set (match_operand:DF 0 "general_operand" "=f,fm,!*rf,!*rm") + (match_operand:DF 1 "general_operand" "fmG,f,*rfm,*rfF"))] + "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" + "* +{ + int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + + /* First handle a `pop' insn or a `fld %st(0)' */ + + if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1])) + { + if (stack_top_dies) + return AS1 (fstp,%y0); + else + return AS1 (fld,%y0); + } + + /* Handle a transfer between the 387 and a 386 register */ + + if (STACK_TOP_P (operands[0]) && NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); + RET; + } + + if (STACK_TOP_P (operands[1]) && NON_STACK_REG_P (operands[0])) + { + output_to_reg (operands[0], stack_top_dies); + RET; + } + + /* Handle other kinds of writes from the 387 */ + + if (STACK_TOP_P (operands[1])) + { + if (stack_top_dies) + return AS1 (fstp%z0,%y0); + else + return AS1 (fst%z0,%y0); + } + + /* Handle other kinds of reads to the 387 */ + + if (STACK_TOP_P (operands[0]) && GET_CODE (operands[1]) == CONST_DOUBLE) + return output_move_const_single (operands); + + if (STACK_TOP_P (operands[0])) + return AS1 (fld%z1,%y1); + + /* Handle all DFmode moves not involving the 387 */ + + return output_move_double (operands); +}") + +(define_insn "swapdf" + [(set (match_operand:DF 0 "register_operand" "f") + (match_operand:DF 1 "register_operand" "f")) + (set (match_dup 1) + (match_dup 0))] + "" + "* +{ + if (STACK_TOP_P (operands[0])) + return AS1 (fxch,%1); + else + return AS1 (fxch,%0); +}") + +(define_expand "movxf" + [(set (match_operand:XF 0 "general_operand" "") + (match_operand:XF 1 "general_operand" ""))] + "" + " +{ + /* Special case memory->memory moves and pushes */ + if (TARGET_MOVE + && (reload_in_progress | reload_completed) == 0 + && GET_CODE (operands[0]) == MEM + && (GET_CODE (operands[1]) == MEM || push_operand (operands[0], XFmode))) + { + rtx (*genfunc) PROTO((rtx, rtx)) = (push_operand (operands[0], XFmode)) + ? gen_movxf_push + : gen_movxf_mem; + + emit_insn ((*genfunc) (operands[0], operands[1])); + DONE; + } + + /* If we are loading a floating point constant that isn't 0 or 1 into a register, + indicate we need the pic register loaded. This could be optimized into stores + of constants if the target eventually moves to memory, but better safe than + sorry. */ + if (flag_pic + && GET_CODE (operands[0]) != MEM + && GET_CODE (operands[1]) == CONST_DOUBLE + && !standard_80387_constant_p (operands[1])) + { + current_function_uses_pic_offset_table = 1; + } +}") + + +(define_insn "movxf_push_nomove" + [(set (match_operand:XF 0 "push_operand" "=<,<") + (match_operand:XF 1 "general_operand" "gF,f"))] + "!TARGET_MOVE" + "* +{ + if (STACK_REG_P (operands[1])) + { + rtx xops[3]; + + xops[0] = AT_SP (SFmode); + xops[1] = GEN_INT (12); + xops[2] = stack_pointer_rtx; + + output_asm_insn (AS2 (sub%L2,%1,%2), xops); + output_asm_insn (AS1 (fstp%T0,%0), xops); + if (! find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + output_asm_insn (AS1 (fld%T0,%0), xops); + + RET; + } + else + return output_move_double (operands); + }") + +(define_insn "movxf_push" + [(set (match_operand:XF 0 "push_operand" "=<,<,<,<,<") + (match_operand:XF 1 "general_operand" "rF,f,o,o,o")) + (clobber (match_scratch:SI 2 "=X,X,&r,&r,X")) + (clobber (match_scratch:SI 3 "=X,X,&r,X,X"))] + "" + "* +{ + if (STACK_REG_P (operands[1])) + { + rtx xops[3]; + + xops[0] = AT_SP (SFmode); + xops[1] = GEN_INT (12); + xops[2] = stack_pointer_rtx; + + output_asm_insn (AS2 (sub%L2,%1,%2), xops); + output_asm_insn (AS1 (fstp%T0,%0), xops); + if (! find_regno_note (insn, REG_DEAD, FIRST_STACK_REG)) + output_asm_insn (AS1 (fld%T0,%0), xops); + + RET; + } + + else if (GET_CODE (operands[1]) != MEM + || GET_CODE (operands[2]) != REG) + return output_move_double (operands); + + else + return output_move_pushmem (operands, insn, GET_MODE_SIZE (XFmode), 2, 4); +}") + +(define_insn "movxf_mem" + [(set (match_operand:XF 0 "memory_operand" "=o,o") + (match_operand:XF 1 "memory_operand" "o,o")) + (clobber (match_scratch:SI 2 "=&r,&r")) + (clobber (match_scratch:SI 3 "=&r,X"))] + "" + "* return output_move_memory (operands, insn, GET_MODE_SIZE (XFmode), 2, 4);") + +(define_insn "movxf_normal" + [(set (match_operand:XF 0 "general_operand" "=f,fm,!*rf,!*rm") + (match_operand:XF 1 "general_operand" "fmG,f,*rfm,*rfF"))] + "(!TARGET_MOVE || GET_CODE (operands[0]) != MEM) || (GET_CODE (operands[1]) != MEM)" + "* +{ + int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + + /* First handle a `pop' insn or a `fld %st(0)' */ + + if (STACK_TOP_P (operands[0]) && STACK_TOP_P (operands[1])) + { + if (stack_top_dies) + return AS1 (fstp,%y0); + else + return AS1 (fld,%y0); + } + + /* Handle a transfer between the 387 and a 386 register */ + + if (STACK_TOP_P (operands[0]) && NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); + RET; + } + + if (STACK_TOP_P (operands[1]) && NON_STACK_REG_P (operands[0])) + { + output_to_reg (operands[0], stack_top_dies); + RET; + } + + /* Handle other kinds of writes from the 387 */ + + if (STACK_TOP_P (operands[1])) + { + output_asm_insn (AS1 (fstp%z0,%y0), operands); + if (! stack_top_dies) + return AS1 (fld%z0,%y0); + + RET; + } + + /* Handle other kinds of reads to the 387 */ + + if (STACK_TOP_P (operands[0]) && GET_CODE (operands[1]) == CONST_DOUBLE) + return output_move_const_single (operands); + + if (STACK_TOP_P (operands[0])) + return AS1 (fld%z1,%y1); + + /* Handle all XFmode moves not involving the 387 */ + + return output_move_double (operands); +}") + +(define_insn "swapxf" + [(set (match_operand:XF 0 "register_operand" "f") + (match_operand:XF 1 "register_operand" "f")) + (set (match_dup 1) + (match_dup 0))] + "" + "* +{ + if (STACK_TOP_P (operands[0])) + return AS1 (fxch,%1); + else + return AS1 (fxch,%0); +}") + +(define_insn "" + [(set (match_operand:DI 0 "push_operand" "=<,<,<,<") + (match_operand:DI 1 "general_operand" "riF,o,o,o")) + (clobber (match_scratch:SI 2 "=X,&r,&r,X")) + (clobber (match_scratch:SI 3 "=X,&r,X,X"))] + "" + "* +{ + if (GET_CODE (operands[1]) != MEM) + return output_move_double (operands); + + else + return output_move_pushmem (operands, insn, GET_MODE_SIZE (DImode), 2, 4); +}") + +(define_insn "movdi" + [(set (match_operand:DI 0 "general_operand" "=o,o,r,rm") + (match_operand:DI 1 "general_operand" "o,o,m,riF")) + (clobber (match_scratch:SI 2 "=&r,&r,X,X")) + (clobber (match_scratch:SI 3 "=&r,X,X,X"))] + "" + "* +{ + rtx low[2], high[2], xop[6]; + + if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) + return output_move_double (operands); + else + return output_move_memory (operands, insn, GET_MODE_SIZE (DImode), 2, 4); +}") + + +;;- conversion instructions +;;- NONE + +;;- zero extension instructions +;; See comments by `andsi' for when andl is faster than movzx. + +(define_insn "zero_extendhisi2" + [(set (match_operand:SI 0 "general_operand" "=r") + (zero_extend:SI + (match_operand:HI 1 "nonimmediate_operand" "rm")))] + "" + "* +{ + if ((!TARGET_386 || REGNO (operands[0]) == 0) + && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])) + { + rtx xops[2]; + xops[0] = operands[0]; + xops[1] = GEN_INT (0xffff); + output_asm_insn (AS2 (and%L0,%1,%k0), xops); + RET; + } + +#ifdef INTEL_SYNTAX + return AS2 (movzx,%1,%0); +#else + return AS2 (movz%W0%L0,%1,%0); +#endif +}") + +(define_insn "zero_extendqihi2" + [(set (match_operand:HI 0 "general_operand" "=r") + (zero_extend:HI + (match_operand:QI 1 "nonimmediate_operand" "qm")))] + "" + "* +{ + if ((!TARGET_386 || REGNO (operands[0]) == 0) + && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])) + { + rtx xops[2]; + xops[0] = operands[0]; + xops[1] = GEN_INT (0xff); + output_asm_insn (AS2 (and%L0,%1,%k0), xops); + RET; + } + +#ifdef INTEL_SYNTAX + return AS2 (movzx,%1,%0); +#else + return AS2 (movz%B0%W0,%1,%0); +#endif +}") + +(define_insn "zero_extendqisi2" + [(set (match_operand:SI 0 "general_operand" "=r") + (zero_extend:SI + (match_operand:QI 1 "nonimmediate_operand" "qm")))] + "" + "* +{ + if ((!TARGET_386 || REGNO (operands[0]) == 0) + && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])) + { + rtx xops[2]; + xops[0] = operands[0]; + xops[1] = GEN_INT (0xff); + output_asm_insn (AS2 (and%L0,%1,%k0), xops); + RET; + } + +#ifdef INTEL_SYNTAX + return AS2 (movzx,%1,%0); +#else + return AS2 (movz%B0%L0,%1,%0); +#endif +}") + +(define_insn "zero_extendsidi2" + [(set (match_operand:DI 0 "register_operand" "=r") + (zero_extend:DI + (match_operand:SI 1 "register_operand" "0")))] + "" + "* +{ + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + return AS2 (xor%L0,%0,%0); +}") + +;;- sign extension instructions + +(define_insn "extendsidi2" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extend:DI + (match_operand:SI 1 "register_operand" "0")))] + "" + "* +{ + if (REGNO (operands[0]) == 0) + { + /* This used to be cwtl, but that extends HI to SI somehow. */ +#ifdef INTEL_SYNTAX + return \"cdq\"; +#else + return \"cltd\"; +#endif + } + + operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); + output_asm_insn (AS2 (mov%L0,%0,%1), operands); + + operands[0] = GEN_INT (31); + return AS2 (sar%L1,%0,%1); +}") + +;; Note that the i386 programmers' manual says that the opcodes +;; are named movsx..., but the assembler on Unix does not accept that. +;; We use what the Unix assembler expects. + +(define_insn "extendhisi2" + [(set (match_operand:SI 0 "general_operand" "=r") + (sign_extend:SI + (match_operand:HI 1 "nonimmediate_operand" "rm")))] + "" + "* +{ + if (REGNO (operands[0]) == 0 + && REG_P (operands[1]) && REGNO (operands[1]) == 0) +#ifdef INTEL_SYNTAX + return \"cwde\"; +#else + return \"cwtl\"; +#endif + +#ifdef INTEL_SYNTAX + return AS2 (movsx,%1,%0); +#else + return AS2 (movs%W0%L0,%1,%0); +#endif +}") + +(define_insn "extendqihi2" + [(set (match_operand:HI 0 "general_operand" "=r") + (sign_extend:HI + (match_operand:QI 1 "nonimmediate_operand" "qm")))] + "" + "* +{ + if (REGNO (operands[0]) == 0 + && REG_P (operands[1]) && REGNO (operands[1]) == 0) + return \"cbtw\"; + +#ifdef INTEL_SYNTAX + return AS2 (movsx,%1,%0); +#else + return AS2 (movs%B0%W0,%1,%0); +#endif +}") + +(define_insn "extendqisi2" + [(set (match_operand:SI 0 "general_operand" "=r") + (sign_extend:SI + (match_operand:QI 1 "nonimmediate_operand" "qm")))] + "" + "* +{ +#ifdef INTEL_SYNTAX + return AS2 (movsx,%1,%0); +#else + return AS2 (movs%B0%L0,%1,%0); +#endif +}") + +;; Conversions between float and double. + +(define_insn "extendsfdf2" + [(set (match_operand:DF 0 "general_operand" "=fm,f") + (float_extend:DF + (match_operand:SF 1 "general_operand" "f,fm")))] + "TARGET_80387" + "* +{ + int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); + RET; + } + + if (NON_STACK_REG_P (operands[0])) + { + output_to_reg (operands[0], stack_top_dies); + RET; + } + + if (STACK_TOP_P (operands[0])) + return AS1 (fld%z1,%y1); + + if (GET_CODE (operands[0]) == MEM) + { + if (stack_top_dies) + return AS1 (fstp%z0,%y0); + else + return AS1 (fst%z0,%y0); + } + + abort (); +}") + +(define_insn "extenddfxf2" + [(set (match_operand:XF 0 "general_operand" "=fm,f,f,!*r") + (float_extend:XF + (match_operand:DF 1 "general_operand" "f,fm,!*r,f")))] + "TARGET_80387" + "* +{ + int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); + RET; + } + + if (NON_STACK_REG_P (operands[0])) + { + output_to_reg (operands[0], stack_top_dies); + RET; + } + + if (STACK_TOP_P (operands[0])) + return AS1 (fld%z1,%y1); + + if (GET_CODE (operands[0]) == MEM) + { + output_asm_insn (AS1 (fstp%z0,%y0), operands); + if (! stack_top_dies) + return AS1 (fld%z0,%y0); + RET; + } + + abort (); +}") + +(define_insn "extendsfxf2" + [(set (match_operand:XF 0 "general_operand" "=fm,f,f,!*r") + (float_extend:XF + (match_operand:SF 1 "general_operand" "f,fm,!*r,f")))] + "TARGET_80387" + "* +{ + int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fld%z0,%y1)); + RET; + } + + if (NON_STACK_REG_P (operands[0])) + { + output_to_reg (operands[0], stack_top_dies); + RET; + } + + if (STACK_TOP_P (operands[0])) + return AS1 (fld%z1,%y1); + + if (GET_CODE (operands[0]) == MEM) + { + output_asm_insn (AS1 (fstp%z0,%y0), operands); + if (! stack_top_dies) + return AS1 (fld%z0,%y0); + RET; + } + + abort (); +}") + +(define_expand "truncdfsf2" + [(parallel [(set (match_operand:SF 0 "nonimmediate_operand" "") + (float_truncate:SF + (match_operand:DF 1 "register_operand" ""))) + (clobber (match_dup 2))])] + "TARGET_80387" + " +{ + operands[2] = (rtx) assign_386_stack_local (SFmode, 0); +}") + +;; This cannot output into an f-reg because there is no way to be sure +;; of truncating in that case. Otherwise this is just like a simple move +;; insn. So we pretend we can output to a reg in order to get better +;; register preferencing, but we really use a stack slot. + +(define_insn "" + [(set (match_operand:SF 0 "nonimmediate_operand" "=f,m") + (float_truncate:SF + (match_operand:DF 1 "register_operand" "0,f"))) + (clobber (match_operand:SF 2 "memory_operand" "m,m"))] + "TARGET_80387" + "* +{ + int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + + if (GET_CODE (operands[0]) == MEM) + { + if (stack_top_dies) + return AS1 (fstp%z0,%0); + else + return AS1 (fst%z0,%0); + } + else if (STACK_TOP_P (operands[0])) + { + output_asm_insn (AS1 (fstp%z2,%y2), operands); + return AS1 (fld%z2,%y2); + } + else + abort (); +}") + +(define_insn "truncxfsf2" + [(set (match_operand:SF 0 "general_operand" "=m,!*r") + (float_truncate:SF + (match_operand:XF 1 "register_operand" "f,f")))] + "TARGET_80387" + "* +{ + int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + + if (NON_STACK_REG_P (operands[0])) + { + if (stack_top_dies == 0) + { + output_asm_insn (AS1 (fld,%y1), operands); + stack_top_dies = 1; + } + output_to_reg (operands[0], stack_top_dies); + RET; + } + else if (GET_CODE (operands[0]) == MEM) + { + if (stack_top_dies) + return AS1 (fstp%z0,%0); + else + { + output_asm_insn (AS1 (fld,%y1), operands); + return AS1 (fstp%z0,%0); + } + } + else + abort (); +}") + +(define_insn "truncxfdf2" + [(set (match_operand:DF 0 "general_operand" "=m,!*r") + (float_truncate:DF + (match_operand:XF 1 "register_operand" "f,f")))] + "TARGET_80387" + "* +{ + int stack_top_dies = find_regno_note (insn, REG_DEAD, FIRST_STACK_REG) != 0; + + if (NON_STACK_REG_P (operands[0])) + { + if (stack_top_dies == 0) + { + output_asm_insn (AS1 (fld,%y1), operands); + stack_top_dies = 1; + } + output_to_reg (operands[0], stack_top_dies); + RET; + } + else if (GET_CODE (operands[0]) == MEM) + { + if (stack_top_dies) + return AS1 (fstp%z0,%0); + else + { + output_asm_insn (AS1 (fld,%y1), operands); + return AS1 (fstp%z0,%0); + } + } + else + abort (); +}") + + +;; The 387 requires that the stack top dies after converting to DImode. + +;; Represent an unsigned conversion from SImode to MODE_FLOAT by first +;; doing a signed conversion to DImode, and then taking just the low +;; part. + +(define_expand "fixuns_truncxfsi2" + [(set (match_dup 4) + (match_operand:XF 1 "register_operand" "")) + (parallel [(set (match_dup 2) + (fix:DI (fix:XF (match_dup 4)))) + (clobber (match_dup 4)) + (clobber (match_dup 5)) + (clobber (match_dup 6)) + (clobber (match_scratch:SI 7 ""))]) + (set (match_operand:SI 0 "general_operand" "") + (match_dup 3))] + "TARGET_80387" + " +{ + operands[2] = gen_reg_rtx (DImode); + operands[3] = gen_lowpart (SImode, operands[2]); + operands[4] = gen_reg_rtx (XFmode); + operands[5] = (rtx) assign_386_stack_local (SImode, 0); + operands[6] = (rtx) assign_386_stack_local (SImode, 1); +}") + +(define_expand "fixuns_truncdfsi2" + [(set (match_dup 4) + (match_operand:DF 1 "register_operand" "")) + (parallel [(set (match_dup 2) + (fix:DI (fix:DF (match_dup 4)))) + (clobber (match_dup 4)) + (clobber (match_dup 5)) + (clobber (match_dup 6)) + (clobber (match_scratch:SI 7 ""))]) + (set (match_operand:SI 0 "general_operand" "") + (match_dup 3))] + "TARGET_80387" + " +{ + operands[2] = gen_reg_rtx (DImode); + operands[3] = gen_lowpart (SImode, operands[2]); + operands[4] = gen_reg_rtx (DFmode); + operands[5] = (rtx) assign_386_stack_local (SImode, 0); + operands[6] = (rtx) assign_386_stack_local (SImode, 1); +}") + +(define_expand "fixuns_truncsfsi2" + [(set (match_dup 4) + (match_operand:SF 1 "register_operand" "")) + (parallel [(set (match_dup 2) + (fix:DI (fix:SF (match_dup 4)))) + (clobber (match_dup 4)) + (clobber (match_dup 5)) + (clobber (match_dup 6)) + (clobber (match_scratch:SI 7 ""))]) + (set (match_operand:SI 0 "general_operand" "") + (match_dup 3))] + "TARGET_80387" + " +{ + operands[2] = gen_reg_rtx (DImode); + operands[3] = gen_lowpart (SImode, operands[2]); + operands[4] = gen_reg_rtx (SFmode); + operands[5] = (rtx) assign_386_stack_local (SImode, 0); + operands[6] = (rtx) assign_386_stack_local (SImode, 1); +}") + +;; Signed conversion to DImode. + +(define_expand "fix_truncxfdi2" + [(set (match_dup 2) + (match_operand:XF 1 "register_operand" "")) + (parallel [(set (match_operand:DI 0 "general_operand" "") + (fix:DI (fix:XF (match_dup 2)))) + (clobber (match_dup 2)) + (clobber (match_dup 3)) + (clobber (match_dup 4)) + (clobber (match_scratch:SI 5 ""))])] + "TARGET_80387" + " +{ + operands[1] = copy_to_mode_reg (XFmode, operands[1]); + operands[2] = gen_reg_rtx (XFmode); + operands[3] = (rtx) assign_386_stack_local (SImode, 0); + operands[4] = (rtx) assign_386_stack_local (SImode, 1); +}") + +(define_expand "fix_truncdfdi2" + [(set (match_dup 2) + (match_operand:DF 1 "register_operand" "")) + (parallel [(set (match_operand:DI 0 "general_operand" "") + (fix:DI (fix:DF (match_dup 2)))) + (clobber (match_dup 2)) + (clobber (match_dup 3)) + (clobber (match_dup 4)) + (clobber (match_scratch:SI 5 ""))])] + "TARGET_80387" + " +{ + operands[1] = copy_to_mode_reg (DFmode, operands[1]); + operands[2] = gen_reg_rtx (DFmode); + operands[3] = (rtx) assign_386_stack_local (SImode, 0); + operands[4] = (rtx) assign_386_stack_local (SImode, 1); +}") + +(define_expand "fix_truncsfdi2" + [(set (match_dup 2) + (match_operand:SF 1 "register_operand" "")) + (parallel [(set (match_operand:DI 0 "general_operand" "") + (fix:DI (fix:SF (match_dup 2)))) + (clobber (match_dup 2)) + (clobber (match_dup 3)) + (clobber (match_dup 4)) + (clobber (match_scratch:SI 5 ""))])] + "TARGET_80387" + " +{ + operands[1] = copy_to_mode_reg (SFmode, operands[1]); + operands[2] = gen_reg_rtx (SFmode); + operands[3] = (rtx) assign_386_stack_local (SImode, 0); + operands[4] = (rtx) assign_386_stack_local (SImode, 1); +}") + +;; These match a signed conversion of either DFmode or SFmode to DImode. + +(define_insn "" + [(set (match_operand:DI 0 "general_operand" "=rm") + (fix:DI (fix:XF (match_operand:XF 1 "register_operand" "f")))) + (clobber (match_dup 1)) + (clobber (match_operand:SI 2 "memory_operand" "m")) + (clobber (match_operand:SI 3 "memory_operand" "m")) + (clobber (match_scratch:SI 4 "=&q"))] + "TARGET_80387" + "* return output_fix_trunc (insn, operands);") + +(define_insn "" + [(set (match_operand:DI 0 "general_operand" "=rm") + (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f")))) + (clobber (match_dup 1)) + (clobber (match_operand:SI 2 "memory_operand" "m")) + (clobber (match_operand:SI 3 "memory_operand" "m")) + (clobber (match_scratch:SI 4 "=&q"))] + "TARGET_80387" + "* return output_fix_trunc (insn, operands);") + +(define_insn "" + [(set (match_operand:DI 0 "general_operand" "=rm") + (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f")))) + (clobber (match_dup 1)) + (clobber (match_operand:SI 2 "memory_operand" "m")) + (clobber (match_operand:SI 3 "memory_operand" "m")) + (clobber (match_scratch:SI 4 "=&q"))] + "TARGET_80387" + "* return output_fix_trunc (insn, operands);") + +;; Signed MODE_FLOAT conversion to SImode. + +(define_expand "fix_truncxfsi2" + [(parallel [(set (match_operand:SI 0 "general_operand" "") + (fix:SI + (fix:XF (match_operand:XF 1 "register_operand" "")))) + (clobber (match_dup 2)) + (clobber (match_dup 3)) + (clobber (match_scratch:SI 4 ""))])] + "TARGET_80387" + " +{ + operands[2] = (rtx) assign_386_stack_local (SImode, 0); + operands[3] = (rtx) assign_386_stack_local (SImode, 1); +}") + +(define_expand "fix_truncdfsi2" + [(parallel [(set (match_operand:SI 0 "general_operand" "") + (fix:SI + (fix:DF (match_operand:DF 1 "register_operand" "")))) + (clobber (match_dup 2)) + (clobber (match_dup 3)) + (clobber (match_scratch:SI 4 ""))])] + "TARGET_80387" + " +{ + operands[2] = (rtx) assign_386_stack_local (SImode, 0); + operands[3] = (rtx) assign_386_stack_local (SImode, 1); +}") + +(define_expand "fix_truncsfsi2" + [(parallel [(set (match_operand:SI 0 "general_operand" "") + (fix:SI + (fix:SF (match_operand:SF 1 "register_operand" "")))) + (clobber (match_dup 2)) + (clobber (match_dup 3)) + (clobber (match_scratch:SI 4 ""))])] + "TARGET_80387" + " +{ + operands[2] = (rtx) assign_386_stack_local (SImode, 0); + operands[3] = (rtx) assign_386_stack_local (SImode, 1); +}") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=rm") + (fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f")))) + (clobber (match_operand:SI 2 "memory_operand" "m")) + (clobber (match_operand:SI 3 "memory_operand" "m")) + (clobber (match_scratch:SI 4 "=&q"))] + "TARGET_80387" + "* return output_fix_trunc (insn, operands);") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=rm") + (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f")))) + (clobber (match_operand:SI 2 "memory_operand" "m")) + (clobber (match_operand:SI 3 "memory_operand" "m")) + (clobber (match_scratch:SI 4 "=&q"))] + "TARGET_80387" + "* return output_fix_trunc (insn, operands);") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=rm") + (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f")))) + (clobber (match_operand:SI 2 "memory_operand" "m")) + (clobber (match_operand:SI 3 "memory_operand" "m")) + (clobber (match_scratch:SI 4 "=&q"))] + "TARGET_80387" + "* return output_fix_trunc (insn, operands);") + +;; Conversion between fixed point and floating point. +;; The actual pattern that matches these is at the end of this file. + +;; ??? Possibly represent floatunssidf2 here in gcc2. + +(define_expand "floatsisf2" + [(set (match_operand:SF 0 "register_operand" "") + (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))] + "TARGET_80387" + "") + +(define_expand "floatdisf2" + [(set (match_operand:SF 0 "register_operand" "") + (float:SF (match_operand:DI 1 "nonimmediate_operand" "")))] + "TARGET_80387" + "") + +(define_expand "floatsidf2" + [(set (match_operand:DF 0 "register_operand" "") + (float:DF (match_operand:SI 1 "nonimmediate_operand" "")))] + "TARGET_80387" + "") + +(define_expand "floatdidf2" + [(set (match_operand:DF 0 "register_operand" "") + (float:DF (match_operand:DI 1 "nonimmediate_operand" "")))] + "TARGET_80387" + "") + +(define_expand "floatsixf2" + [(set (match_operand:XF 0 "register_operand" "") + (float:XF (match_operand:SI 1 "nonimmediate_operand" "")))] + "TARGET_80387" + "") + +(define_expand "floatdixf2" + [(set (match_operand:XF 0 "register_operand" "") + (float:XF (match_operand:DI 1 "nonimmediate_operand" "")))] + "TARGET_80387" + "") + +;; This will convert from SImode or DImode to MODE_FLOAT. + +(define_insn "" + [(set (match_operand:XF 0 "register_operand" "=f") + (float:XF (match_operand:DI 1 "general_operand" "rm")))] + "TARGET_80387" + "* +{ + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fild%z0,%1)); + RET; + } + else if (GET_CODE (operands[1]) == MEM) + return AS1 (fild%z1,%1); + else + abort (); +}") + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f") + (float:DF (match_operand:DI 1 "nonimmediate_operand" "rm")))] + "TARGET_80387" + "* +{ + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fild%z0,%1)); + RET; + } + else if (GET_CODE (operands[1]) == MEM) + return AS1 (fild%z1,%1); + else + abort (); +}") + +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=f") + (float:SF (match_operand:DI 1 "nonimmediate_operand" "rm")))] + "TARGET_80387" + "* +{ + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fild%z0,%1)); + RET; + } + else if (GET_CODE (operands[1]) == MEM) + return AS1 (fild%z1,%1); + else + abort (); +}") + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f") + (float:DF (match_operand:SI 1 "nonimmediate_operand" "rm")))] + "TARGET_80387" + "* +{ + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fild%z0,%1)); + RET; + } + else if (GET_CODE (operands[1]) == MEM) + return AS1 (fild%z1,%1); + else + abort (); +}") + +(define_insn "" + [(set (match_operand:XF 0 "register_operand" "=f,f") + (float:XF (match_operand:SI 1 "general_operand" "m,!*r")))] + "TARGET_80387" + "* +{ + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fild%z0,%1)); + RET; + } + else if (GET_CODE (operands[1]) == MEM) + return AS1 (fild%z1,%1); + else + abort (); +}") + +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=f") + (float:SF (match_operand:SI 1 "nonimmediate_operand" "rm")))] + "TARGET_80387" + "* +{ + if (NON_STACK_REG_P (operands[1])) + { + output_op_from_reg (operands[1], AS1 (fild%z0,%1)); + RET; + } + else if (GET_CODE (operands[1]) == MEM) + return AS1 (fild%z1,%1); + else + abort (); +}") + +;;- add instructions + +(define_insn "adddi3" + [(set (match_operand:DI 0 "general_operand" "=&r,ro,o,&r,ro,o,&r,o,o,o") + (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,o,riF,o,or,riF,riF,o") + (match_operand:DI 2 "general_operand" "o,riF,o,0,0,0,oriF,riF,o,o"))) + (clobber (match_scratch:SI 3 "=X,X,&r,X,&r,&r,X,&r,&r,&r"))] + "" + "* +{ + rtx low[3], high[3], xops[7], temp; + + CC_STATUS_INIT; + + if (rtx_equal_p (operands[0], operands[2])) + { + temp = operands[1]; + operands[1] = operands[2]; + operands[2] = temp; + } + + split_di (operands, 3, low, high); + if (!rtx_equal_p (operands[0], operands[1])) + { + xops[0] = high[0]; + xops[1] = low[0]; + xops[2] = high[1]; + xops[3] = low[1]; + + if (GET_CODE (operands[0]) != MEM) + { + output_asm_insn (AS2 (mov%L1,%3,%1), xops); + output_asm_insn (AS2 (mov%L0,%2,%0), xops); + } + else + { + xops[4] = high[2]; + xops[5] = low[2]; + xops[6] = operands[3]; + output_asm_insn (AS2 (mov%L6,%3,%6), xops); + output_asm_insn (AS2 (add%L6,%5,%6), xops); + output_asm_insn (AS2 (mov%L1,%6,%1), xops); + output_asm_insn (AS2 (mov%L6,%2,%6), xops); + output_asm_insn (AS2 (adc%L6,%4,%6), xops); + output_asm_insn (AS2 (mov%L0,%6,%0), xops); + RET; + } + } + + if (GET_CODE (operands[3]) == REG && GET_CODE (operands[2]) != REG) + { + xops[0] = high[0]; + xops[1] = low[0]; + xops[2] = high[2]; + xops[3] = low[2]; + xops[4] = operands[3]; + + output_asm_insn (AS2 (mov%L4,%3,%4), xops); + output_asm_insn (AS2 (add%L1,%4,%1), xops); + output_asm_insn (AS2 (mov%L4,%2,%4), xops); + output_asm_insn (AS2 (adc%L0,%4,%0), xops); + } + + else if (GET_CODE (low[2]) != CONST_INT || INTVAL (low[2]) != 0) + { + output_asm_insn (AS2 (add%L0,%2,%0), low); + output_asm_insn (AS2 (adc%L0,%2,%0), high); + } + + else + output_asm_insn (AS2 (add%L0,%2,%0), high); + + RET; +}") + +;; On a 486, it is faster to do movl/addl than to do a single leal if +;; operands[1] and operands[2] are both registers. + +(define_insn "addsi3" + [(set (match_operand:SI 0 "general_operand" "=?r,rm,r") + (plus:SI (match_operand:SI 1 "general_operand" "%r,0,0") + (match_operand:SI 2 "general_operand" "ri,ri,rm")))] + "" + "* +{ + if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1])) + { + if (REG_P (operands[2]) && REGNO (operands[0]) == REGNO (operands[2])) + return AS2 (add%L0,%1,%0); + + if (operands[2] == stack_pointer_rtx) + { + rtx temp; + + temp = operands[1]; + operands[1] = operands[2]; + operands[2] = temp; + } + + if (operands[2] != stack_pointer_rtx) + { + CC_STATUS_INIT; + operands[1] = SET_SRC (PATTERN (insn)); + return AS2 (lea%L0,%a1,%0); + } + + output_asm_insn (AS2 (mov%L0,%1,%0), operands); + } + + if (operands[2] == const1_rtx) + return AS1 (inc%L0,%0); + + if (operands[2] == constm1_rtx) + return AS1 (dec%L0,%0); + + return AS2 (add%L0,%2,%0); +}") + +;; ??? `lea' here, for three operand add? If leaw is used, only %bx, +;; %si and %di can appear in SET_SRC, and output_asm_insn might not be +;; able to handle the operand. But leal always works? + +(define_insn "addhi3" + [(set (match_operand:HI 0 "general_operand" "=rm,r") + (plus:HI (match_operand:HI 1 "general_operand" "%0,0") + (match_operand:HI 2 "general_operand" "ri,rm")))] + "" + "* +{ + /* ??? what about offsettable memory references? */ + if (QI_REG_P (operands[0]) + && GET_CODE (operands[2]) == CONST_INT + && (INTVAL (operands[2]) & 0xff) == 0) + { + int byteval = (INTVAL (operands[2]) >> 8) & 0xff; + CC_STATUS_INIT; + + if (byteval == 1) + return AS1 (inc%B0,%h0); + else if (byteval == 255) + return AS1 (dec%B0,%h0); + + operands[2] = GEN_INT (byteval); + return AS2 (add%B0,%2,%h0); + } + + if (operands[2] == const1_rtx) + return AS1 (inc%W0,%0); + + if (operands[2] == constm1_rtx + || (GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) == 65535)) + return AS1 (dec%W0,%0); + + return AS2 (add%W0,%2,%0); +}") + +(define_insn "addqi3" + [(set (match_operand:QI 0 "general_operand" "=qm,q") + (plus:QI (match_operand:QI 1 "general_operand" "%0,0") + (match_operand:QI 2 "general_operand" "qn,qmn")))] + "" + "* +{ + if (operands[2] == const1_rtx) + return AS1 (inc%B0,%0); + + if (operands[2] == constm1_rtx + || (GET_CODE (operands[2]) == CONST_INT + && INTVAL (operands[2]) == 255)) + return AS1 (dec%B0,%0); + + return AS2 (add%B0,%2,%0); +}") + +;Lennart Augustsson <augustss@cs.chalmers.se> +;says this pattern just makes slower code: +; pushl %ebp +; addl $-80,(%esp) +;instead of +; leal -80(%ebp),%eax +; pushl %eax +; +;(define_insn "" +; [(set (match_operand:SI 0 "push_operand" "=<") +; (plus:SI (match_operand:SI 1 "general_operand" "%r") +; (match_operand:SI 2 "general_operand" "ri")))] +; "" +; "* +;{ +; rtx xops[4]; +; xops[0] = operands[0]; +; xops[1] = operands[1]; +; xops[2] = operands[2]; +; xops[3] = gen_rtx (MEM, SImode, stack_pointer_rtx); +; output_asm_insn (\"push%z1 %1\", xops); +; output_asm_insn (AS2 (add%z3,%2,%3), xops); +; RET; +;}") + +;; addsi3 is faster, so put this after. + +(define_insn "movsi_lea" + [(set (match_operand:SI 0 "register_operand" "=r") + (match_operand:QI 1 "address_operand" "p"))] + "" + "* +{ + CC_STATUS_INIT; + /* Adding a constant to a register is faster with an add. */ + /* ??? can this ever happen? */ + if (GET_CODE (operands[1]) == PLUS + && GET_CODE (XEXP (operands[1], 1)) == CONST_INT + && rtx_equal_p (operands[0], XEXP (operands[1], 0))) + { + operands[1] = XEXP (operands[1], 1); + + if (operands[1] == const1_rtx) + return AS1 (inc%L0,%0); + + if (operands[1] == constm1_rtx) + return AS1 (dec%L0,%0); + + return AS2 (add%L0,%1,%0); + } + return AS2 (lea%L0,%a1,%0); +}") + +;; The patterns that match these are at the end of this file. + +(define_expand "addxf3" + [(set (match_operand:XF 0 "register_operand" "") + (plus:XF (match_operand:XF 1 "nonimmediate_operand" "") + (match_operand:XF 2 "nonimmediate_operand" "")))] + "TARGET_80387" + "") + +(define_expand "adddf3" + [(set (match_operand:DF 0 "register_operand" "") + (plus:DF (match_operand:DF 1 "nonimmediate_operand" "") + (match_operand:DF 2 "nonimmediate_operand" "")))] + "TARGET_80387" + "") + +(define_expand "addsf3" + [(set (match_operand:SF 0 "register_operand" "") + (plus:SF (match_operand:SF 1 "nonimmediate_operand" "") + (match_operand:SF 2 "nonimmediate_operand" "")))] + "TARGET_80387" + "") + +;;- subtract instructions + +(define_insn "subdi3" + [(set (match_operand:DI 0 "general_operand" "=&r,ro,&r,o,o") + (minus:DI (match_operand:DI 1 "general_operand" "0,0,roiF,riF,o") + (match_operand:DI 2 "general_operand" "o,riF,roiF,riF,o"))) + (clobber (match_scratch:SI 3 "=X,X,X,&r,&r"))] + "" + "* +{ + rtx low[3], high[3], xops[7]; + + CC_STATUS_INIT; + + split_di (operands, 3, low, high); + + if (!rtx_equal_p (operands[0], operands[1])) + { + xops[0] = high[0]; + xops[1] = low[0]; + xops[2] = high[1]; + xops[3] = low[1]; + + if (GET_CODE (operands[0]) != MEM) + { + output_asm_insn (AS2 (mov%L1,%3,%1), xops); + output_asm_insn (AS2 (mov%L0,%2,%0), xops); + } + else + { + xops[4] = high[2]; + xops[5] = low[2]; + xops[6] = operands[3]; + output_asm_insn (AS2 (mov%L6,%3,%6), xops); + output_asm_insn (AS2 (sub%L6,%5,%6), xops); + output_asm_insn (AS2 (mov%L1,%6,%1), xops); + output_asm_insn (AS2 (mov%L6,%2,%6), xops); + output_asm_insn (AS2 (sbb%L6,%4,%6), xops); + output_asm_insn (AS2 (mov%L0,%6,%0), xops); + RET; + } + } + + if (GET_CODE (operands[3]) == REG) + { + xops[0] = high[0]; + xops[1] = low[0]; + xops[2] = high[2]; + xops[3] = low[2]; + xops[4] = operands[3]; + + output_asm_insn (AS2 (mov%L4,%3,%4), xops); + output_asm_insn (AS2 (sub%L1,%4,%1), xops); + output_asm_insn (AS2 (mov%L4,%2,%4), xops); + output_asm_insn (AS2 (sbb%L0,%4,%0), xops); + } + + else if (GET_CODE (low[2]) != CONST_INT || INTVAL (low[2]) != 0) + { + output_asm_insn (AS2 (sub%L0,%2,%0), low); + output_asm_insn (AS2 (sbb%L0,%2,%0), high); + } + + else + output_asm_insn (AS2 (sub%L0,%2,%0), high); + + RET; +}") + +(define_insn "subsi3" + [(set (match_operand:SI 0 "general_operand" "=rm,r") + (minus:SI (match_operand:SI 1 "general_operand" "0,0") + (match_operand:SI 2 "general_operand" "ri,rm")))] + "" + "* return AS2 (sub%L0,%2,%0);") + +(define_insn "subhi3" + [(set (match_operand:HI 0 "general_operand" "=rm,r") + (minus:HI (match_operand:HI 1 "general_operand" "0,0") + (match_operand:HI 2 "general_operand" "ri,rm")))] + "" + "* return AS2 (sub%W0,%2,%0);") + +(define_insn "subqi3" + [(set (match_operand:QI 0 "general_operand" "=qm,q") + (minus:QI (match_operand:QI 1 "general_operand" "0,0") + (match_operand:QI 2 "general_operand" "qn,qmn")))] + "" + "* return AS2 (sub%B0,%2,%0);") + +;; The patterns that match these are at the end of this file. + +(define_expand "subxf3" + [(set (match_operand:XF 0 "register_operand" "") + (minus:XF (match_operand:XF 1 "nonimmediate_operand" "") + (match_operand:XF 2 "nonimmediate_operand" "")))] + "TARGET_80387" + "") + +(define_expand "subdf3" + [(set (match_operand:DF 0 "register_operand" "") + (minus:DF (match_operand:DF 1 "nonimmediate_operand" "") + (match_operand:DF 2 "nonimmediate_operand" "")))] + "TARGET_80387" + "") + +(define_expand "subsf3" + [(set (match_operand:SF 0 "register_operand" "") + (minus:SF (match_operand:SF 1 "nonimmediate_operand" "") + (match_operand:SF 2 "nonimmediate_operand" "")))] + "TARGET_80387" + "") + +;;- multiply instructions + +;(define_insn "mulqi3" +; [(set (match_operand:QI 0 "general_operand" "=a") +; (mult:QI (match_operand:QI 1 "general_operand" "%0") +; (match_operand:QI 2 "general_operand" "qm")))] +; "" +; "imul%B0 %2,%0") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=r") + (mult:HI (match_operand:HI 1 "general_operand" "%0") + (match_operand:HI 2 "general_operand" "r")))] + "GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x80" + "* return AS2 (imul%W0,%2,%0);") + +(define_insn "mulhi3" + [(set (match_operand:HI 0 "general_operand" "=r,r") + (mult:HI (match_operand:HI 1 "general_operand" "%0,rm") + (match_operand:HI 2 "general_operand" "g,i")))] + "" + "* +{ + if (GET_CODE (operands[1]) == REG + && REGNO (operands[1]) == REGNO (operands[0]) + && (GET_CODE (operands[2]) == MEM || GET_CODE (operands[2]) == REG)) + /* Assembler has weird restrictions. */ + return AS2 (imul%W0,%2,%0); + return AS3 (imul%W0,%2,%1,%0); +}") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=r") + (mult:SI (match_operand:SI 1 "general_operand" "%0") + (match_operand:SI 2 "general_operand" "r")))] + "GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0x80" + "* return AS2 (imul%L0,%2,%0);") + +(define_insn "mulsi3" + [(set (match_operand:SI 0 "general_operand" "=r,r") + (mult:SI (match_operand:SI 1 "general_operand" "%0,rm") + (match_operand:SI 2 "general_operand" "g,i")))] + "" + "* +{ + if (GET_CODE (operands[1]) == REG + && REGNO (operands[1]) == REGNO (operands[0]) + && (GET_CODE (operands[2]) == MEM || GET_CODE (operands[2]) == REG)) + /* Assembler has weird restrictions. */ + return AS2 (imul%L0,%2,%0); + return AS3 (imul%L0,%2,%1,%0); +}") + +(define_insn "umulqihi3" + [(set (match_operand:HI 0 "general_operand" "=a") + (mult:HI (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0")) + (zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))] + "" + "mul%B0 %2") + +(define_insn "mulqihi3" + [(set (match_operand:HI 0 "general_operand" "=a") + (mult:HI (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "%0")) + (sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))] + "" + "imul%B0 %2") + +(define_insn "umulsidi3" + [(set (match_operand:DI 0 "register_operand" "=A") + (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) + (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))] + "TARGET_WIDE_MULTIPLY" + "mul%L0 %2") + +(define_insn "mulsidi3" + [(set (match_operand:DI 0 "register_operand" "=A") + (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0")) + (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))] + "TARGET_WIDE_MULTIPLY" + "imul%L0 %2") + +(define_insn "umulsi3_highpart" + [(set (match_operand:SI 0 "register_operand" "=d") + (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%a")) + (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))) + (const_int 32)))) + (clobber (match_scratch:SI 3 "=a"))] + "TARGET_WIDE_MULTIPLY" + "mul%L0 %2") + +(define_insn "smulsi3_highpart" + [(set (match_operand:SI 0 "register_operand" "=d") + (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%a")) + (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))) + (const_int 32)))) + (clobber (match_scratch:SI 3 "=a"))] + "TARGET_WIDE_MULTIPLY" + "imul%L0 %2") + +;; The patterns that match these are at the end of this file. + +(define_expand "mulxf3" + [(set (match_operand:XF 0 "register_operand" "") + (mult:XF (match_operand:XF 1 "nonimmediate_operand" "") + (match_operand:XF 2 "nonimmediate_operand" "")))] + "TARGET_80387" + "") + +(define_expand "muldf3" + [(set (match_operand:DF 0 "register_operand" "") + (mult:DF (match_operand:DF 1 "nonimmediate_operand" "") + (match_operand:DF 2 "nonimmediate_operand" "")))] + "TARGET_80387" + "") + +(define_expand "mulsf3" + [(set (match_operand:SF 0 "register_operand" "") + (mult:SF (match_operand:SF 1 "nonimmediate_operand" "") + (match_operand:SF 2 "nonimmediate_operand" "")))] + "TARGET_80387" + "") + +;;- divide instructions + +(define_insn "divqi3" + [(set (match_operand:QI 0 "general_operand" "=a") + (div:QI (match_operand:HI 1 "general_operand" "0") + (match_operand:QI 2 "general_operand" "qm")))] + "" + "idiv%B0 %2") + +(define_insn "udivqi3" + [(set (match_operand:QI 0 "general_operand" "=a") + (udiv:QI (match_operand:HI 1 "general_operand" "0") + (match_operand:QI 2 "general_operand" "qm")))] + "" + "div%B0 %2") + +;; The patterns that match these are at the end of this file. + +(define_expand "divxf3" + [(set (match_operand:XF 0 "register_operand" "") + (div:XF (match_operand:XF 1 "nonimmediate_operand" "") + (match_operand:XF 2 "nonimmediate_operand" "")))] + "TARGET_80387" + "") + +(define_expand "divdf3" + [(set (match_operand:DF 0 "register_operand" "") + (div:DF (match_operand:DF 1 "nonimmediate_operand" "") + (match_operand:DF 2 "nonimmediate_operand" "")))] + "TARGET_80387" + "") + +(define_expand "divsf3" + [(set (match_operand:SF 0 "register_operand" "") + (div:SF (match_operand:SF 1 "nonimmediate_operand" "") + (match_operand:SF 2 "nonimmediate_operand" "")))] + "TARGET_80387" + "") + +;; Remainder instructions. + +(define_insn "divmodsi4" + [(set (match_operand:SI 0 "register_operand" "=a") + (div:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "general_operand" "rm"))) + (set (match_operand:SI 3 "register_operand" "=&d") + (mod:SI (match_dup 1) (match_dup 2)))] + "" + "* +{ +#ifdef INTEL_SYNTAX + output_asm_insn (\"cdq\", operands); +#else + output_asm_insn (\"cltd\", operands); +#endif + return AS1 (idiv%L0,%2); +}") + +(define_insn "divmodhi4" + [(set (match_operand:HI 0 "register_operand" "=a") + (div:HI (match_operand:HI 1 "register_operand" "0") + (match_operand:HI 2 "general_operand" "rm"))) + (set (match_operand:HI 3 "register_operand" "=&d") + (mod:HI (match_dup 1) (match_dup 2)))] + "" + "cwtd\;idiv%W0 %2") + +;; ??? Can we make gcc zero extend operand[0]? +(define_insn "udivmodsi4" + [(set (match_operand:SI 0 "register_operand" "=a") + (udiv:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "general_operand" "rm"))) + (set (match_operand:SI 3 "register_operand" "=&d") + (umod:SI (match_dup 1) (match_dup 2)))] + "" + "* +{ + output_asm_insn (AS2 (xor%L3,%3,%3), operands); + return AS1 (div%L0,%2); +}") + +;; ??? Can we make gcc zero extend operand[0]? +(define_insn "udivmodhi4" + [(set (match_operand:HI 0 "register_operand" "=a") + (udiv:HI (match_operand:HI 1 "register_operand" "0") + (match_operand:HI 2 "general_operand" "rm"))) + (set (match_operand:HI 3 "register_operand" "=&d") + (umod:HI (match_dup 1) (match_dup 2)))] + "" + "* +{ + output_asm_insn (AS2 (xor%W0,%3,%3), operands); + return AS1 (div%W0,%2); +}") + +/* +;;this should be a valid double division which we may want to add + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=a") + (udiv:DI (match_operand:DI 1 "register_operand" "a") + (match_operand:SI 2 "general_operand" "rm"))) + (set (match_operand:SI 3 "register_operand" "=d") + (umod:SI (match_dup 1) (match_dup 2)))] + "" + "div%L0 %2,%0") +*/ + +;;- and instructions + +;; On i386, +;; movzbl %bl,%ebx +;; is faster than +;; andl $255,%ebx +;; +;; but if the reg is %eax, then the "andl" is faster. +;; +;; On i486, the "andl" is always faster than the "movzbl". +;; +;; On both i386 and i486, a three operand AND is as fast with movzbl or +;; movzwl as with andl, if operands[0] != operands[1]. + +;; The `r' in `rm' for operand 3 looks redundant, but it causes +;; optional reloads to be generated if op 3 is a pseudo in a stack slot. + +;; ??? What if we only change one byte of an offsettable memory reference? +(define_insn "andsi3" + [(set (match_operand:SI 0 "general_operand" "=r,r,rm,r") + (and:SI (match_operand:SI 1 "general_operand" "%rm,qm,0,0") + (match_operand:SI 2 "general_operand" "L,K,ri,rm")))] + "" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) + { + if (INTVAL (operands[2]) == 0xffff && REG_P (operands[0]) + && (! REG_P (operands[1]) + || REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0) + && (TARGET_386 || ! rtx_equal_p (operands[0], operands[1]))) + { + /* ??? tege: Should forget CC_STATUS only if we clobber a + remembered operand. Fix that later. */ + CC_STATUS_INIT; +#ifdef INTEL_SYNTAX + return AS2 (movzx,%w1,%0); +#else + return AS2 (movz%W0%L0,%w1,%0); +#endif + } + + if (INTVAL (operands[2]) == 0xff && REG_P (operands[0]) + && !(REG_P (operands[1]) && NON_QI_REG_P (operands[1])) + && (! REG_P (operands[1]) + || REGNO (operands[0]) != 0 || REGNO (operands[1]) != 0) + && (TARGET_386 || ! rtx_equal_p (operands[0], operands[1]))) + { + /* ??? tege: Should forget CC_STATUS only if we clobber a + remembered operand. Fix that later. */ + CC_STATUS_INIT; +#ifdef INTEL_SYNTAX + return AS2 (movzx,%b1,%0); +#else + return AS2 (movz%B0%L0,%b1,%0); +#endif + } + + if (QI_REG_P (operands[0]) && ~(INTVAL (operands[2]) | 0xff) == 0) + { + CC_STATUS_INIT; + + if (INTVAL (operands[2]) == 0xffffff00) + { + operands[2] = const0_rtx; + return AS2 (mov%B0,%2,%b0); + } + + operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff); + return AS2 (and%B0,%2,%b0); + } + + if (QI_REG_P (operands[0]) && ~(INTVAL (operands[2]) | 0xff00) == 0) + { + CC_STATUS_INIT; + + if (INTVAL (operands[2]) == 0xffff00ff) + { + operands[2] = const0_rtx; + return AS2 (mov%B0,%2,%h0); + } + + operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); + return AS2 (and%B0,%2,%h0); + } + + if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) == 0xffff0000) + { + operands[2] = const0_rtx; + return AS2 (mov%W0,%2,%w0); + } + } + + return AS2 (and%L0,%2,%0); +}") + +(define_insn "andhi3" + [(set (match_operand:HI 0 "general_operand" "=rm,r") + (and:HI (match_operand:HI 1 "general_operand" "%0,0") + (match_operand:HI 2 "general_operand" "ri,rm")))] + "" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) + { + /* Can we ignore the upper byte? */ + if ((! REG_P (operands[0]) || QI_REG_P (operands[0])) + && (INTVAL (operands[2]) & 0xff00) == 0xff00) + { + CC_STATUS_INIT; + + if ((INTVAL (operands[2]) & 0xff) == 0) + { + operands[2] = const0_rtx; + return AS2 (mov%B0,%2,%b0); + } + + operands[2] = GEN_INT (INTVAL (operands[2]) & 0xff); + return AS2 (and%B0,%2,%b0); + } + + /* Can we ignore the lower byte? */ + /* ??? what about offsettable memory references? */ + if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & 0xff) == 0xff) + { + CC_STATUS_INIT; + + if ((INTVAL (operands[2]) & 0xff00) == 0) + { + operands[2] = const0_rtx; + return AS2 (mov%B0,%2,%h0); + } + + operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); + return AS2 (and%B0,%2,%h0); + } + } + + return AS2 (and%W0,%2,%0); +}") + +(define_insn "andqi3" + [(set (match_operand:QI 0 "general_operand" "=qm,q") + (and:QI (match_operand:QI 1 "general_operand" "%0,0") + (match_operand:QI 2 "general_operand" "qn,qmn")))] + "" + "* return AS2 (and%B0,%2,%0);") + +/* I am nervous about these two.. add them later.. +;I presume this means that we have something in say op0= eax which is small +;and we want to and it with memory so we can do this by just an +;andb m,%al and have success. +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=r") + (and:SI (zero_extend:SI + (match_operand:HI 1 "nonimmediate_operand" "rm")) + (match_operand:SI 2 "general_operand" "0")))] + "GET_CODE (operands[2]) == CONST_INT + && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (HImode))" + "and%W0 %1,%0") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=q") + (and:SI + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")) + (match_operand:SI 2 "general_operand" "0")))] + "GET_CODE (operands[2]) == CONST_INT + && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (QImode))" + "and%L0 %1,%0") + +*/ + +;;- Bit set (inclusive or) instructions + +;; ??? What if we only change one byte of an offsettable memory reference? +(define_insn "iorsi3" + [(set (match_operand:SI 0 "general_operand" "=rm,r") + (ior:SI (match_operand:SI 1 "general_operand" "%0,0") + (match_operand:SI 2 "general_operand" "ri,rm")))] + "" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) + { + if ((! REG_P (operands[0]) || QI_REG_P (operands[0])) + && (INTVAL (operands[2]) & ~0xff) == 0) + { + CC_STATUS_INIT; + + if (INTVAL (operands[2]) == 0xff) + return AS2 (mov%B0,%2,%b0); + + return AS2 (or%B0,%2,%b0); + } + + if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & ~0xff00) == 0) + { + CC_STATUS_INIT; + operands[2] = GEN_INT (INTVAL (operands[2]) >> 8); + + if (INTVAL (operands[2]) == 0xff) + return AS2 (mov%B0,%2,%h0); + + return AS2 (or%B0,%2,%h0); + } + } + + return AS2 (or%L0,%2,%0); +}") + +(define_insn "iorhi3" + [(set (match_operand:HI 0 "general_operand" "=rm,r") + (ior:HI (match_operand:HI 1 "general_operand" "%0,0") + (match_operand:HI 2 "general_operand" "ri,rm")))] + "" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) + { + /* Can we ignore the upper byte? */ + if ((! REG_P (operands[0]) || QI_REG_P (operands[0])) + && (INTVAL (operands[2]) & 0xff00) == 0) + { + CC_STATUS_INIT; + if (INTVAL (operands[2]) & 0xffff0000) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); + + if (INTVAL (operands[2]) == 0xff) + return AS2 (mov%B0,%2,%b0); + + return AS2 (or%B0,%2,%b0); + } + + /* Can we ignore the lower byte? */ + /* ??? what about offsettable memory references? */ + if (QI_REG_P (operands[0]) + && (INTVAL (operands[2]) & 0xff) == 0) + { + CC_STATUS_INIT; + operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); + + if (INTVAL (operands[2]) == 0xff) + return AS2 (mov%B0,%2,%h0); + + return AS2 (or%B0,%2,%h0); + } + } + + return AS2 (or%W0,%2,%0); +}") + +(define_insn "iorqi3" + [(set (match_operand:QI 0 "general_operand" "=qm,q") + (ior:QI (match_operand:QI 1 "general_operand" "%0,0") + (match_operand:QI 2 "general_operand" "qn,qmn")))] + "" + "* return AS2 (or%B0,%2,%0);") + +;;- xor instructions + +;; ??? What if we only change one byte of an offsettable memory reference? +(define_insn "xorsi3" + [(set (match_operand:SI 0 "general_operand" "=rm,r") + (xor:SI (match_operand:SI 1 "general_operand" "%0,0") + (match_operand:SI 2 "general_operand" "ri,rm")))] + "" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) + { + if ((! REG_P (operands[0]) || QI_REG_P (operands[0])) + && (INTVAL (operands[2]) & ~0xff) == 0) + { + CC_STATUS_INIT; + + if (INTVAL (operands[2]) == 0xff) + return AS1 (not%B0,%b0); + + return AS2 (xor%B0,%2,%b0); + } + + if (QI_REG_P (operands[0]) && (INTVAL (operands[2]) & ~0xff00) == 0) + { + CC_STATUS_INIT; + operands[2] = GEN_INT (INTVAL (operands[2]) >> 8); + + if (INTVAL (operands[2]) == 0xff) + return AS1 (not%B0,%h0); + + return AS2 (xor%B0,%2,%h0); + } + } + + return AS2 (xor%L0,%2,%0); +}") + +(define_insn "xorhi3" + [(set (match_operand:HI 0 "general_operand" "=rm,r") + (xor:HI (match_operand:HI 1 "general_operand" "%0,0") + (match_operand:HI 2 "general_operand" "ri,rm")))] + "" + "* +{ + if (GET_CODE (operands[2]) == CONST_INT + && ! (GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) + { + /* Can we ignore the upper byte? */ + if ((! REG_P (operands[0]) || QI_REG_P (operands[0])) + && (INTVAL (operands[2]) & 0xff00) == 0) + { + CC_STATUS_INIT; + if (INTVAL (operands[2]) & 0xffff0000) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); + + if (INTVAL (operands[2]) == 0xff) + return AS1 (not%B0,%b0); + + return AS2 (xor%B0,%2,%b0); + } + + /* Can we ignore the lower byte? */ + /* ??? what about offsettable memory references? */ + if (QI_REG_P (operands[0]) + && (INTVAL (operands[2]) & 0xff) == 0) + { + CC_STATUS_INIT; + operands[2] = GEN_INT ((INTVAL (operands[2]) >> 8) & 0xff); + + if (INTVAL (operands[2]) == 0xff) + return AS1 (not%B0,%h0); + + return AS2 (xor%B0,%2,%h0); + } + } + + return AS2 (xor%W0,%2,%0); +}") + +(define_insn "xorqi3" + [(set (match_operand:QI 0 "general_operand" "=qm,q") + (xor:QI (match_operand:QI 1 "general_operand" "%0,0") + (match_operand:QI 2 "general_operand" "qn,qm")))] + "" + "* return AS2 (xor%B0,%2,%0);") + +;;- negation instructions + +(define_insn "negdi2" + [(set (match_operand:DI 0 "general_operand" "=&ro") + (neg:DI (match_operand:DI 1 "general_operand" "0")))] + "" + "* +{ + rtx xops[2], low[1], high[1]; + + CC_STATUS_INIT; + + split_di (operands, 1, low, high); + xops[0] = const0_rtx; + xops[1] = high[0]; + + output_asm_insn (AS1 (neg%L0,%0), low); + output_asm_insn (AS2 (adc%L1,%0,%1), xops); + output_asm_insn (AS1 (neg%L0,%0), high); + RET; +}") + +(define_insn "negsi2" + [(set (match_operand:SI 0 "general_operand" "=rm") + (neg:SI (match_operand:SI 1 "general_operand" "0")))] + "" + "neg%L0 %0") + +(define_insn "neghi2" + [(set (match_operand:HI 0 "general_operand" "=rm") + (neg:HI (match_operand:HI 1 "general_operand" "0")))] + "" + "neg%W0 %0") + +(define_insn "negqi2" + [(set (match_operand:QI 0 "general_operand" "=qm") + (neg:QI (match_operand:QI 1 "general_operand" "0")))] + "" + "neg%B0 %0") + +(define_insn "negsf2" + [(set (match_operand:SF 0 "register_operand" "=f") + (neg:SF (match_operand:SF 1 "general_operand" "0")))] + "TARGET_80387" + "fchs") + +(define_insn "negdf2" + [(set (match_operand:DF 0 "register_operand" "=f") + (neg:DF (match_operand:DF 1 "general_operand" "0")))] + "TARGET_80387" + "fchs") + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f") + (neg:DF (float_extend:DF (match_operand:SF 1 "general_operand" "0"))))] + "TARGET_80387" + "fchs") + +(define_insn "negxf2" + [(set (match_operand:XF 0 "register_operand" "=f") + (neg:XF (match_operand:XF 1 "general_operand" "0")))] + "TARGET_80387" + "fchs") + +(define_insn "" + [(set (match_operand:XF 0 "register_operand" "=f") + (neg:XF (float_extend:XF (match_operand:DF 1 "general_operand" "0"))))] + "TARGET_80387" + "fchs") + +;; Absolute value instructions + +(define_insn "abssf2" + [(set (match_operand:SF 0 "register_operand" "=f") + (abs:SF (match_operand:SF 1 "general_operand" "0")))] + "TARGET_80387" + "fabs") + +(define_insn "absdf2" + [(set (match_operand:DF 0 "register_operand" "=f") + (abs:DF (match_operand:DF 1 "general_operand" "0")))] + "TARGET_80387" + "fabs") + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f") + (abs:DF (float_extend:DF (match_operand:SF 1 "general_operand" "0"))))] + "TARGET_80387" + "fabs") + +(define_insn "absxf2" + [(set (match_operand:XF 0 "register_operand" "=f") + (abs:XF (match_operand:XF 1 "general_operand" "0")))] + "TARGET_80387" + "fabs") + +(define_insn "" + [(set (match_operand:XF 0 "register_operand" "=f") + (abs:XF (float_extend:XF (match_operand:DF 1 "general_operand" "0"))))] + "TARGET_80387" + "fabs") + +(define_insn "sqrtsf2" + [(set (match_operand:SF 0 "register_operand" "=f") + (sqrt:SF (match_operand:SF 1 "general_operand" "0")))] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && (TARGET_IEEE_FP || flag_fast_math) " + "fsqrt") + +(define_insn "sqrtdf2" + [(set (match_operand:DF 0 "register_operand" "=f") + (sqrt:DF (match_operand:DF 1 "general_operand" "0")))] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && (TARGET_IEEE_FP || flag_fast_math) " + "fsqrt") + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f") + (sqrt:DF (float_extend:DF + (match_operand:SF 1 "general_operand" "0"))))] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && (TARGET_IEEE_FP || flag_fast_math) " + "fsqrt") + +(define_insn "sqrtxf2" + [(set (match_operand:XF 0 "register_operand" "=f") + (sqrt:XF (match_operand:XF 1 "general_operand" "0")))] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && (TARGET_IEEE_FP || flag_fast_math) " + "fsqrt") + +(define_insn "" + [(set (match_operand:XF 0 "register_operand" "=f") + (sqrt:XF (float_extend:XF + (match_operand:DF 1 "general_operand" "0"))))] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && (TARGET_IEEE_FP || flag_fast_math) " + "fsqrt") + +(define_insn "" + [(set (match_operand:XF 0 "register_operand" "=f") + (sqrt:XF (float_extend:XF + (match_operand:SF 1 "general_operand" "0"))))] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && (TARGET_IEEE_FP || flag_fast_math) " + "fsqrt") + +(define_insn "sindf2" + [(set (match_operand:DF 0 "register_operand" "=f") + (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 1))] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && (TARGET_IEEE_FP || flag_fast_math) " + "fsin") + +(define_insn "sinsf2" + [(set (match_operand:SF 0 "register_operand" "=f") + (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 1))] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && (TARGET_IEEE_FP || flag_fast_math) " + "fsin") + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f") + (unspec:DF [(float_extend:DF + (match_operand:SF 1 "register_operand" "0"))] 1))] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && (TARGET_IEEE_FP || flag_fast_math) " + "fsin") + +(define_insn "sinxf2" + [(set (match_operand:XF 0 "register_operand" "=f") + (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 1))] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && (TARGET_IEEE_FP || flag_fast_math) " + "fsin") + +(define_insn "cosdf2" + [(set (match_operand:DF 0 "register_operand" "=f") + (unspec:DF [(match_operand:DF 1 "register_operand" "0")] 2))] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && (TARGET_IEEE_FP || flag_fast_math) " + "fcos") + +(define_insn "cossf2" + [(set (match_operand:SF 0 "register_operand" "=f") + (unspec:SF [(match_operand:SF 1 "register_operand" "0")] 2))] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && (TARGET_IEEE_FP || flag_fast_math) " + "fcos") + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f") + (unspec:DF [(float_extend:DF + (match_operand:SF 1 "register_operand" "0"))] 2))] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && (TARGET_IEEE_FP || flag_fast_math) " + "fcos") + +(define_insn "cosxf2" + [(set (match_operand:XF 0 "register_operand" "=f") + (unspec:XF [(match_operand:XF 1 "register_operand" "0")] 2))] + "! TARGET_NO_FANCY_MATH_387 && TARGET_80387 + && (TARGET_IEEE_FP || flag_fast_math) " + "fcos") + +;;- one complement instructions + +(define_insn "one_cmplsi2" + [(set (match_operand:SI 0 "general_operand" "=rm") + (not:SI (match_operand:SI 1 "general_operand" "0")))] + "" + "not%L0 %0") + +(define_insn "one_cmplhi2" + [(set (match_operand:HI 0 "general_operand" "=rm") + (not:HI (match_operand:HI 1 "general_operand" "0")))] + "" + "not%W0 %0") + +(define_insn "one_cmplqi2" + [(set (match_operand:QI 0 "general_operand" "=qm") + (not:QI (match_operand:QI 1 "general_operand" "0")))] + "" + "not%B0 %0") + +;;- arithmetic shift instructions + +;; DImode shifts are implemented using the i386 "shift double" opcode, +;; which is written as "sh[lr]d[lw] imm,reg,reg/mem". If the shift count +;; is variable, then the count is in %cl and the "imm" operand is dropped +;; from the assembler input. + +;; This instruction shifts the target reg/mem as usual, but instead of +;; shifting in zeros, bits are shifted in from reg operand. If the insn +;; is a left shift double, bits are taken from the high order bits of +;; reg, else if the insn is a shift right double, bits are taken from the +;; low order bits of reg. So if %eax is "1234" and %edx is "5678", +;; "shldl $8,%edx,%eax" leaves %edx unchanged and sets %eax to "2345". + +;; Since sh[lr]d does not change the `reg' operand, that is done +;; separately, making all shifts emit pairs of shift double and normal +;; shift. Since sh[lr]d does not shift more than 31 bits, and we wish to +;; support a 63 bit shift, each shift where the count is in a reg expands +;; to three pairs. If the overall shift is by N bits, then the first two +;; pairs shift by N / 2 and the last pair by N & 1. + +;; If the shift count is a constant, we need never emit more than one +;; shift pair, instead using moves and sign extension for counts greater +;; than 31. + +(define_expand "ashldi3" + [(set (match_operand:DI 0 "register_operand" "") + (ashift:DI (match_operand:DI 1 "register_operand" "") + (match_operand:QI 2 "nonmemory_operand" "")))] + "" + " +{ + if (GET_CODE (operands[2]) != CONST_INT + || ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) + { + operands[2] = copy_to_mode_reg (QImode, operands[2]); + emit_insn (gen_ashldi3_non_const_int (operands[0], operands[1], + operands[2])); + } + else + emit_insn (gen_ashldi3_const_int (operands[0], operands[1], operands[2])); + + DONE; +}") + +(define_insn "ashldi3_const_int" + [(set (match_operand:DI 0 "register_operand" "=&r") + (ashift:DI (match_operand:DI 1 "register_operand" "0") + (match_operand:QI 2 "const_int_operand" "J")))] + "" + "* +{ + rtx xops[4], low[1], high[1]; + + CC_STATUS_INIT; + + split_di (operands, 1, low, high); + xops[0] = operands[2]; + xops[1] = const1_rtx; + xops[2] = low[0]; + xops[3] = high[0]; + + if (INTVAL (xops[0]) > 31) + { + output_asm_insn (AS2 (mov%L3,%2,%3), xops); /* Fast shift by 32 */ + output_asm_insn (AS2 (xor%L2,%2,%2), xops); + + if (INTVAL (xops[0]) > 32) + { + xops[0] = GEN_INT (INTVAL (xops[0]) - 32); + output_asm_insn (AS2 (sal%L3,%0,%3), xops); /* Remaining shift */ + } + } + else + { + output_asm_insn (AS3 (shld%L3,%0,%2,%3), xops); + output_asm_insn (AS2 (sal%L2,%0,%2), xops); + } + RET; +}") + +(define_insn "ashldi3_non_const_int" + [(set (match_operand:DI 0 "register_operand" "=&r") + (ashift:DI (match_operand:DI 1 "register_operand" "0") + (match_operand:QI 2 "register_operand" "c"))) + (clobber (match_dup 2))] + "" + "* +{ + rtx xops[4], low[1], high[1]; + + CC_STATUS_INIT; + + split_di (operands, 1, low, high); + xops[0] = operands[2]; + xops[1] = const1_rtx; + xops[2] = low[0]; + xops[3] = high[0]; + + output_asm_insn (AS2 (ror%B0,%1,%0), xops); /* shift count / 2 */ + + output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops); + output_asm_insn (AS2 (sal%L2,%0,%2), xops); + output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops); + output_asm_insn (AS2 (sal%L2,%0,%2), xops); + + xops[1] = GEN_INT (7); /* shift count & 1 */ + + output_asm_insn (AS2 (shr%B0,%1,%0), xops); + + output_asm_insn (AS3_SHIFT_DOUBLE (shld%L3,%0,%2,%3), xops); + output_asm_insn (AS2 (sal%L2,%0,%2), xops); + + RET; +}") + +;; On i386 and i486, "addl reg,reg" is faster than "sall $1,reg" +;; On i486, movl/sall appears slightly faster than leal, but the leal +;; is smaller - use leal for now unless the shift count is 1. + +(define_insn "ashlsi3" + [(set (match_operand:SI 0 "general_operand" "=r,rm") + (ashift:SI (match_operand:SI 1 "general_operand" "r,0") + (match_operand:SI 2 "nonmemory_operand" "M,cI")))] + "" + "* +{ + if (REG_P (operands[0]) && REGNO (operands[0]) != REGNO (operands[1])) + { + if (!TARGET_386 && INTVAL (operands[2]) == 1) + { + output_asm_insn (AS2 (mov%L0,%1,%0), operands); + return AS2 (add%L0,%1,%0); + } + else + { + CC_STATUS_INIT; + + if (operands[1] == stack_pointer_rtx) + { + output_asm_insn (AS2 (mov%L0,%1,%0), operands); + operands[1] = operands[0]; + } + operands[1] = gen_rtx (MULT, SImode, operands[1], + GEN_INT (1 << INTVAL (operands[2]))); + return AS2 (lea%L0,%a1,%0); + } + } + + if (REG_P (operands[2])) + return AS2 (sal%L0,%b2,%0); + + if (REG_P (operands[0]) && operands[2] == const1_rtx) + return AS2 (add%L0,%0,%0); + + return AS2 (sal%L0,%2,%0); +}") + +(define_insn "ashlhi3" + [(set (match_operand:HI 0 "general_operand" "=rm") + (ashift:HI (match_operand:HI 1 "general_operand" "0") + (match_operand:HI 2 "nonmemory_operand" "cI")))] + "" + "* +{ + if (REG_P (operands[2])) + return AS2 (sal%W0,%b2,%0); + + if (REG_P (operands[0]) && operands[2] == const1_rtx) + return AS2 (add%W0,%0,%0); + + return AS2 (sal%W0,%2,%0); +}") + +(define_insn "ashlqi3" + [(set (match_operand:QI 0 "general_operand" "=qm") + (ashift:QI (match_operand:QI 1 "general_operand" "0") + (match_operand:QI 2 "nonmemory_operand" "cI")))] + "" + "* +{ + if (REG_P (operands[2])) + return AS2 (sal%B0,%b2,%0); + + if (REG_P (operands[0]) && operands[2] == const1_rtx) + return AS2 (add%B0,%0,%0); + + return AS2 (sal%B0,%2,%0); +}") + +;; See comment above `ashldi3' about how this works. + +(define_expand "ashrdi3" + [(set (match_operand:DI 0 "register_operand" "") + (ashiftrt:DI (match_operand:DI 1 "register_operand" "") + (match_operand:QI 2 "nonmemory_operand" "")))] + "" + " +{ + if (GET_CODE (operands[2]) != CONST_INT + || ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) + { + operands[2] = copy_to_mode_reg (QImode, operands[2]); + emit_insn (gen_ashrdi3_non_const_int (operands[0], operands[1], + operands[2])); + } + else + emit_insn (gen_ashrdi3_const_int (operands[0], operands[1], operands[2])); + + DONE; +}") + +(define_insn "ashrdi3_const_int" + [(set (match_operand:DI 0 "register_operand" "=&r") + (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") + (match_operand:QI 2 "const_int_operand" "J")))] + "" + "* +{ + rtx xops[4], low[1], high[1]; + + CC_STATUS_INIT; + + split_di (operands, 1, low, high); + xops[0] = operands[2]; + xops[1] = const1_rtx; + xops[2] = low[0]; + xops[3] = high[0]; + + if (INTVAL (xops[0]) > 31) + { + xops[1] = GEN_INT (31); + output_asm_insn (AS2 (mov%L2,%3,%2), xops); + output_asm_insn (AS2 (sar%L3,%1,%3), xops); /* shift by 32 */ + + if (INTVAL (xops[0]) > 32) + { + xops[0] = GEN_INT (INTVAL (xops[0]) - 32); + output_asm_insn (AS2 (sar%L2,%0,%2), xops); /* Remaining shift */ + } + } + else + { + output_asm_insn (AS3 (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (sar%L3,%0,%3), xops); + } + + RET; +}") + +(define_insn "ashrdi3_non_const_int" + [(set (match_operand:DI 0 "register_operand" "=&r") + (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") + (match_operand:QI 2 "register_operand" "c"))) + (clobber (match_dup 2))] + "" + "* +{ + rtx xops[4], low[1], high[1]; + + CC_STATUS_INIT; + + split_di (operands, 1, low, high); + xops[0] = operands[2]; + xops[1] = const1_rtx; + xops[2] = low[0]; + xops[3] = high[0]; + + output_asm_insn (AS2 (ror%B0,%1,%0), xops); /* shift count / 2 */ + + output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (sar%L3,%0,%3), xops); + output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (sar%L3,%0,%3), xops); + + xops[1] = GEN_INT (7); /* shift count & 1 */ + + output_asm_insn (AS2 (shr%B0,%1,%0), xops); + + output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (sar%L3,%0,%3), xops); + + RET; +}") + +(define_insn "ashrsi3" + [(set (match_operand:SI 0 "general_operand" "=rm") + (ashiftrt:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "nonmemory_operand" "cI")))] + "" + "* +{ + if (REG_P (operands[2])) + return AS2 (sar%L0,%b2,%0); + else + return AS2 (sar%L0,%2,%0); +}") + +(define_insn "ashrhi3" + [(set (match_operand:HI 0 "general_operand" "=rm") + (ashiftrt:HI (match_operand:HI 1 "general_operand" "0") + (match_operand:HI 2 "nonmemory_operand" "cI")))] + "" + "* +{ + if (REG_P (operands[2])) + return AS2 (sar%W0,%b2,%0); + else + return AS2 (sar%W0,%2,%0); +}") + +(define_insn "ashrqi3" + [(set (match_operand:QI 0 "general_operand" "=qm") + (ashiftrt:QI (match_operand:QI 1 "general_operand" "0") + (match_operand:QI 2 "nonmemory_operand" "cI")))] + "" + "* +{ + if (REG_P (operands[2])) + return AS2 (sar%B0,%b2,%0); + else + return AS2 (sar%B0,%2,%0); +}") + +;;- logical shift instructions + +;; See comment above `ashldi3' about how this works. + +(define_expand "lshrdi3" + [(set (match_operand:DI 0 "register_operand" "") + (lshiftrt:DI (match_operand:DI 1 "register_operand" "") + (match_operand:QI 2 "nonmemory_operand" "")))] + "" + " +{ + if (GET_CODE (operands[2]) != CONST_INT + || ! CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) + { + operands[2] = copy_to_mode_reg (QImode, operands[2]); + emit_insn (gen_lshrdi3_non_const_int (operands[0], operands[1], + operands[2])); + } + else + emit_insn (gen_lshrdi3_const_int (operands[0], operands[1], operands[2])); + + DONE; +}") + +(define_insn "lshrdi3_const_int" + [(set (match_operand:DI 0 "register_operand" "=&r") + (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") + (match_operand:QI 2 "const_int_operand" "J")))] + "" + "* +{ + rtx xops[4], low[1], high[1]; + + CC_STATUS_INIT; + + split_di (operands, 1, low, high); + xops[0] = operands[2]; + xops[1] = const1_rtx; + xops[2] = low[0]; + xops[3] = high[0]; + + if (INTVAL (xops[0]) > 31) + { + output_asm_insn (AS2 (mov%L2,%3,%2), xops); /* Fast shift by 32 */ + output_asm_insn (AS2 (xor%L3,%3,%3), xops); + + if (INTVAL (xops[0]) > 32) + { + xops[0] = GEN_INT (INTVAL (xops[0]) - 32); + output_asm_insn (AS2 (shr%L2,%0,%2), xops); /* Remaining shift */ + } + } + else + { + output_asm_insn (AS3 (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (shr%L3,%0,%3), xops); + } + + RET; +}") + +(define_insn "lshrdi3_non_const_int" + [(set (match_operand:DI 0 "register_operand" "=&r") + (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") + (match_operand:QI 2 "register_operand" "c"))) + (clobber (match_dup 2))] + "" + "* +{ + rtx xops[4], low[1], high[1]; + + CC_STATUS_INIT; + + split_di (operands, 1, low, high); + xops[0] = operands[2]; + xops[1] = const1_rtx; + xops[2] = low[0]; + xops[3] = high[0]; + + output_asm_insn (AS2 (ror%B0,%1,%0), xops); /* shift count / 2 */ + + output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (shr%L3,%0,%3), xops); + output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (shr%L3,%0,%3), xops); + + xops[1] = GEN_INT (7); /* shift count & 1 */ + + output_asm_insn (AS2 (shr%B0,%1,%0), xops); + + output_asm_insn (AS3_SHIFT_DOUBLE (shrd%L2,%0,%3,%2), xops); + output_asm_insn (AS2 (shr%L3,%0,%3), xops); + + RET; +}") + +(define_insn "lshrsi3" + [(set (match_operand:SI 0 "general_operand" "=rm") + (lshiftrt:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "nonmemory_operand" "cI")))] + "" + "* +{ + if (REG_P (operands[2])) + return AS2 (shr%L0,%b2,%0); + else + return AS2 (shr%L0,%2,%1); +}") + +(define_insn "lshrhi3" + [(set (match_operand:HI 0 "general_operand" "=rm") + (lshiftrt:HI (match_operand:HI 1 "general_operand" "0") + (match_operand:HI 2 "nonmemory_operand" "cI")))] + "" + "* +{ + if (REG_P (operands[2])) + return AS2 (shr%W0,%b2,%0); + else + return AS2 (shr%W0,%2,%0); +}") + +(define_insn "lshrqi3" + [(set (match_operand:QI 0 "general_operand" "=qm") + (lshiftrt:QI (match_operand:QI 1 "general_operand" "0") + (match_operand:QI 2 "nonmemory_operand" "cI")))] + "" + "* +{ + if (REG_P (operands[2])) + return AS2 (shr%B0,%b2,%0); + else + return AS2 (shr%B0,%2,%0); +}") + +;;- rotate instructions + +(define_insn "rotlsi3" + [(set (match_operand:SI 0 "general_operand" "=rm") + (rotate:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "nonmemory_operand" "cI")))] + "" + "* +{ + if (REG_P (operands[2])) + return AS2 (rol%L0,%b2,%0); + else + return AS2 (rol%L0,%2,%0); +}") + +(define_insn "rotlhi3" + [(set (match_operand:HI 0 "general_operand" "=rm") + (rotate:HI (match_operand:HI 1 "general_operand" "0") + (match_operand:HI 2 "nonmemory_operand" "cI")))] + "" + "* +{ + if (REG_P (operands[2])) + return AS2 (rol%W0,%b2,%0); + else + return AS2 (rol%W0,%2,%0); +}") + +(define_insn "rotlqi3" + [(set (match_operand:QI 0 "general_operand" "=qm") + (rotate:QI (match_operand:QI 1 "general_operand" "0") + (match_operand:QI 2 "nonmemory_operand" "cI")))] + "" + "* +{ + if (REG_P (operands[2])) + return AS2 (rol%B0,%b2,%0); + else + return AS2 (rol%B0,%2,%0); +}") + +(define_insn "rotrsi3" + [(set (match_operand:SI 0 "general_operand" "=rm") + (rotatert:SI (match_operand:SI 1 "general_operand" "0") + (match_operand:SI 2 "nonmemory_operand" "cI")))] + "" + "* +{ + if (REG_P (operands[2])) + return AS2 (ror%L0,%b2,%0); + else + return AS2 (ror%L0,%2,%0); +}") + +(define_insn "rotrhi3" + [(set (match_operand:HI 0 "general_operand" "=rm") + (rotatert:HI (match_operand:HI 1 "general_operand" "0") + (match_operand:HI 2 "nonmemory_operand" "cI")))] + "" + "* +{ + if (REG_P (operands[2])) + return AS2 (ror%W0,%b2,%0); + else + return AS2 (ror%W0,%2,%0); +}") + +(define_insn "rotrqi3" + [(set (match_operand:QI 0 "general_operand" "=qm") + (rotatert:QI (match_operand:QI 1 "general_operand" "0") + (match_operand:QI 2 "nonmemory_operand" "cI")))] + "" + "* +{ + if (REG_P (operands[2])) + return AS2 (ror%B0,%b2,%0); + else + return AS2 (ror%B0,%2,%0); +}") + +/* +;; This usually looses. But try a define_expand to recognize a few case +;; we can do efficiently, such as accessing the "high" QImode registers, +;; %ah, %bh, %ch, %dh. +(define_insn "insv" + [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+&r") + (match_operand:SI 1 "general_operand" "i") + (match_operand:SI 2 "general_operand" "i")) + (match_operand:SI 3 "general_operand" "ri"))] + "" + "* +{ + if (INTVAL (operands[1]) + INTVAL (operands[2]) > GET_MODE_BITSIZE (SImode)) + abort (); + if (GET_CODE (operands[3]) == CONST_INT) + { + unsigned int mask = (1 << INTVAL (operands[1])) - 1; + operands[1] = GEN_INT (~(mask << INTVAL (operands[2]))); + output_asm_insn (AS2 (and%L0,%1,%0), operands); + operands[3] = GEN_INT (INTVAL (operands[3]) << INTVAL (operands[2])); + output_asm_insn (AS2 (or%L0,%3,%0), operands); + } + else + { + operands[0] = gen_rtx (REG, SImode, REGNO (operands[0])); + if (INTVAL (operands[2])) + output_asm_insn (AS2 (ror%L0,%2,%0), operands); + output_asm_insn (AS3 (shrd%L0,%1,%3,%0), operands); + operands[2] = GEN_INT (BITS_PER_WORD + - INTVAL (operands[1]) - INTVAL (operands[2])); + if (INTVAL (operands[2])) + output_asm_insn (AS2 (ror%L0,%2,%0), operands); + } + RET; +}") +*/ +/* +;; ??? There are problems with the mode of operand[3]. The point of this +;; is to represent an HImode move to a "high byte" register. + +(define_expand "insv" + [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "") + (match_operand:SI 1 "immediate_operand" "") + (match_operand:SI 2 "immediate_operand" "")) + (match_operand:QI 3 "general_operand" "ri"))] + "" + " +{ + if (GET_CODE (operands[1]) != CONST_INT + || GET_CODE (operands[2]) != CONST_INT) + FAIL; + + if (! (INTVAL (operands[1]) == 8 + && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 0)) + && ! INTVAL (operands[1]) == 1) + FAIL; +}") + +;; ??? Are these constraints right? +(define_insn "" + [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+&qo") + (const_int 8) + (const_int 8)) + (match_operand:QI 1 "general_operand" "qn"))] + "" + "* +{ + if (REG_P (operands[0])) + return AS2 (mov%B0,%1,%h0); + + operands[0] = adj_offsettable_operand (operands[0], 1); + return AS2 (mov%B0,%1,%0); +}") +*/ + +;; On i386, the register count for a bit operation is *not* truncated, +;; so SHIFT_COUNT_TRUNCATED must not be defined. + +;; On i486, the shift & or/and code is faster than bts or btr. If +;; operands[0] is a MEM, the bt[sr] is half as fast as the normal code. + +;; On i386, bts is a little faster if operands[0] is a reg, and a +;; little slower if operands[0] is a MEM, than the shift & or/and code. +;; Use bts & btr, since they reload better. + +;; General bit set and clear. +(define_insn "" + [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+rm") + (const_int 1) + (match_operand:SI 2 "general_operand" "r")) + (match_operand:SI 3 "const_int_operand" "n"))] + "TARGET_386 && GET_CODE (operands[2]) != CONST_INT" + "* +{ + CC_STATUS_INIT; + + if (INTVAL (operands[3]) == 1) + return AS2 (bts%L0,%2,%0); + else + return AS2 (btr%L0,%2,%0); +}") + +;; Bit complement. See comments on previous pattern. +;; ??? Is this really worthwhile? +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=rm") + (xor:SI (ashift:SI (const_int 1) + (match_operand:SI 1 "general_operand" "r")) + (match_operand:SI 2 "general_operand" "0")))] + "TARGET_386 && GET_CODE (operands[1]) != CONST_INT" + "* +{ + CC_STATUS_INIT; + + return AS2 (btc%L0,%1,%0); +}") + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=rm") + (xor:SI (match_operand:SI 1 "general_operand" "0") + (ashift:SI (const_int 1) + (match_operand:SI 2 "general_operand" "r"))))] + "TARGET_386 && GET_CODE (operands[2]) != CONST_INT" + "* +{ + CC_STATUS_INIT; + + return AS2 (btc%L0,%2,%0); +}") + +;; Recognizers for bit-test instructions. + +;; The bt opcode allows a MEM in operands[0]. But on both i386 and +;; i486, it is faster to copy a MEM to REG and then use bt, than to use +;; bt on the MEM directly. + +;; ??? The first argument of a zero_extract must not be reloaded, so +;; don't allow a MEM in the operand predicate without allowing it in the +;; constraint. + +(define_insn "" + [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "r") + (const_int 1) + (match_operand:SI 1 "general_operand" "r")))] + "GET_CODE (operands[1]) != CONST_INT" + "* +{ + cc_status.flags |= CC_Z_IN_NOT_C; + return AS2 (bt%L0,%1,%0); +}") + +(define_insn "" + [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "r") + (match_operand:SI 1 "const_int_operand" "n") + (match_operand:SI 2 "const_int_operand" "n")))] + "" + "* +{ + unsigned int mask; + + mask = ((1 << INTVAL (operands[1])) - 1) << INTVAL (operands[2]); + operands[1] = GEN_INT (mask); + + if (QI_REG_P (operands[0])) + { + if ((mask & ~0xff) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + return AS2 (test%B0,%1,%b0); + } + + if ((mask & ~0xff00) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + operands[1] = GEN_INT (mask >> 8); + return AS2 (test%B0,%1,%h0); + } + } + + return AS2 (test%L0,%1,%0); +}") + +;; ??? All bets are off if operand 0 is a volatile MEM reference. +;; The CPU may access unspecified bytes around the actual target byte. + +(define_insn "" + [(set (cc0) (zero_extract (match_operand:QI 0 "general_operand" "rm") + (match_operand:SI 1 "const_int_operand" "n") + (match_operand:SI 2 "const_int_operand" "n")))] + "GET_CODE (operands[0]) != MEM || ! MEM_VOLATILE_P (operands[0])" + "* +{ + unsigned int mask; + + mask = ((1 << INTVAL (operands[1])) - 1) << INTVAL (operands[2]); + operands[1] = GEN_INT (mask); + + if (! REG_P (operands[0]) || QI_REG_P (operands[0])) + { + if ((mask & ~0xff) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + return AS2 (test%B0,%1,%b0); + } + + if ((mask & ~0xff00) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + operands[1] = GEN_INT (mask >> 8); + + if (QI_REG_P (operands[0])) + return AS2 (test%B0,%1,%h0); + else + { + operands[0] = adj_offsettable_operand (operands[0], 1); + return AS2 (test%B0,%1,%b0); + } + } + + if (GET_CODE (operands[0]) == MEM && (mask & ~0xff0000) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + operands[1] = GEN_INT (mask >> 16); + operands[0] = adj_offsettable_operand (operands[0], 2); + return AS2 (test%B0,%1,%b0); + } + + if (GET_CODE (operands[0]) == MEM && (mask & ~0xff000000) == 0) + { + cc_status.flags |= CC_NOT_NEGATIVE; + operands[1] = GEN_INT (mask >> 24); + operands[0] = adj_offsettable_operand (operands[0], 3); + return AS2 (test%B0,%1,%b0); + } + } + + if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM) + return AS2 (test%L0,%1,%0); + + return AS2 (test%L1,%0,%1); +}") + +;; Store-flag instructions. + +;; For all sCOND expanders, also expand the compare or test insn that +;; generates cc0. Generate an equality comparison if `seq' or `sne'. + +;; The 386 sCOND opcodes can write to memory. But a gcc sCOND insn may +;; not have any input reloads. A MEM write might need an input reload +;; for the address of the MEM. So don't allow MEM as the SET_DEST. + +(define_expand "seq" + [(match_dup 1) + (set (match_operand:QI 0 "register_operand" "") + (eq:QI (cc0) (const_int 0)))] + "" + " +{ + if (TARGET_IEEE_FP + && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT) + operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1); + else + operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); +}") + +(define_insn "" + [(set (match_operand:QI 0 "register_operand" "=q") + (eq:QI (cc0) (const_int 0)))] + "" + "* +{ + if (cc_prev_status.flags & CC_Z_IN_NOT_C) + return AS1 (setnb,%0); + else + return AS1 (sete,%0); +}") + +(define_expand "sne" + [(match_dup 1) + (set (match_operand:QI 0 "register_operand" "") + (ne:QI (cc0) (const_int 0)))] + "" + " +{ + if (TARGET_IEEE_FP + && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT) + operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1); + else + operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); +}") + +(define_insn "" + [(set (match_operand:QI 0 "register_operand" "=q") + (ne:QI (cc0) (const_int 0)))] + "" + "* +{ + if (cc_prev_status.flags & CC_Z_IN_NOT_C) + return AS1 (setb,%0); + else + return AS1 (setne,%0); +} +") + +(define_expand "sgt" + [(match_dup 1) + (set (match_operand:QI 0 "register_operand" "") + (gt:QI (cc0) (const_int 0)))] + "" + "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") + +(define_insn "" + [(set (match_operand:QI 0 "register_operand" "=q") + (gt:QI (cc0) (const_int 0)))] + "" + "* +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (sete,%0); + + OUTPUT_JUMP (\"setg %0\", \"seta %0\", NULL_PTR); +}") + +(define_expand "sgtu" + [(match_dup 1) + (set (match_operand:QI 0 "register_operand" "") + (gtu:QI (cc0) (const_int 0)))] + "" + "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") + +(define_insn "" + [(set (match_operand:QI 0 "register_operand" "=q") + (gtu:QI (cc0) (const_int 0)))] + "" + "* return \"seta %0\"; ") + +(define_expand "slt" + [(match_dup 1) + (set (match_operand:QI 0 "register_operand" "") + (lt:QI (cc0) (const_int 0)))] + "" + "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") + +(define_insn "" + [(set (match_operand:QI 0 "register_operand" "=q") + (lt:QI (cc0) (const_int 0)))] + "" + "* +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (sete,%0); + + OUTPUT_JUMP (\"setl %0\", \"setb %0\", \"sets %0\"); +}") + +(define_expand "sltu" + [(match_dup 1) + (set (match_operand:QI 0 "register_operand" "") + (ltu:QI (cc0) (const_int 0)))] + "" + "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") + +(define_insn "" + [(set (match_operand:QI 0 "register_operand" "=q") + (ltu:QI (cc0) (const_int 0)))] + "" + "* return \"setb %0\"; ") + +(define_expand "sge" + [(match_dup 1) + (set (match_operand:QI 0 "register_operand" "") + (ge:QI (cc0) (const_int 0)))] + "" + "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") + +(define_insn "" + [(set (match_operand:QI 0 "register_operand" "=q") + (ge:QI (cc0) (const_int 0)))] + "" + "* +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (sete,%0); + + OUTPUT_JUMP (\"setge %0\", \"setae %0\", \"setns %0\"); +}") + +(define_expand "sgeu" + [(match_dup 1) + (set (match_operand:QI 0 "register_operand" "") + (geu:QI (cc0) (const_int 0)))] + "" + "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") + +(define_insn "" + [(set (match_operand:QI 0 "register_operand" "=q") + (geu:QI (cc0) (const_int 0)))] + "" + "* return \"setae %0\"; ") + +(define_expand "sle" + [(match_dup 1) + (set (match_operand:QI 0 "register_operand" "") + (le:QI (cc0) (const_int 0)))] + "" + "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") + +(define_insn "" + [(set (match_operand:QI 0 "register_operand" "=q") + (le:QI (cc0) (const_int 0)))] + "" + "* +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (setb,%0); + + OUTPUT_JUMP (\"setle %0\", \"setbe %0\", NULL_PTR); +}") + +(define_expand "sleu" + [(match_dup 1) + (set (match_operand:QI 0 "register_operand" "") + (leu:QI (cc0) (const_int 0)))] + "" + "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") + +(define_insn "" + [(set (match_operand:QI 0 "register_operand" "=q") + (leu:QI (cc0) (const_int 0)))] + "" + "* return \"setbe %0\"; ") + +;; Basic conditional jump instructions. +;; We ignore the overflow flag for signed branch instructions. + +;; For all bCOND expanders, also expand the compare or test insn that +;; generates cc0. Generate an equality comparison if `beq' or `bne'. + +(define_expand "beq" + [(match_dup 1) + (set (pc) + (if_then_else (eq (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " +{ + if (TARGET_IEEE_FP + && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT) + operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1); + else + operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); +}") + +(define_insn "" + [(set (pc) + (if_then_else (eq (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "* +{ + if (cc_prev_status.flags & CC_Z_IN_NOT_C) + return \"jnc %l0\"; + else + return \"je %l0\"; +}") + +(define_expand "bne" + [(match_dup 1) + (set (pc) + (if_then_else (ne (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + " +{ + if (TARGET_IEEE_FP + && GET_MODE_CLASS (GET_MODE (i386_compare_op0)) == MODE_FLOAT) + operands[1] = (*i386_compare_gen_eq)(i386_compare_op0, i386_compare_op1); + else + operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1); +}") + +(define_insn "" + [(set (pc) + (if_then_else (ne (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "* +{ + if (cc_prev_status.flags & CC_Z_IN_NOT_C) + return \"jc %l0\"; + else + return \"jne %l0\"; +}") + +(define_expand "bgt" + [(match_dup 1) + (set (pc) + (if_then_else (gt (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") + +(define_insn "" + [(set (pc) + (if_then_else (gt (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "* +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (je,%l0); + + OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", NULL_PTR); +}") + +(define_expand "bgtu" + [(match_dup 1) + (set (pc) + (if_then_else (gtu (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") + +(define_insn "" + [(set (pc) + (if_then_else (gtu (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "ja %l0") + +(define_expand "blt" + [(match_dup 1) + (set (pc) + (if_then_else (lt (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") + +(define_insn "" + [(set (pc) + (if_then_else (lt (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "* +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (je,%l0); + + OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\"); +}") + +(define_expand "bltu" + [(match_dup 1) + (set (pc) + (if_then_else (ltu (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") + +(define_insn "" + [(set (pc) + (if_then_else (ltu (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "jb %l0") + +(define_expand "bge" + [(match_dup 1) + (set (pc) + (if_then_else (ge (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") + +(define_insn "" + [(set (pc) + (if_then_else (ge (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "* +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (je,%l0); + + OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\"); +}") + +(define_expand "bgeu" + [(match_dup 1) + (set (pc) + (if_then_else (geu (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") + +(define_insn "" + [(set (pc) + (if_then_else (geu (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "jae %l0") + +(define_expand "ble" + [(match_dup 1) + (set (pc) + (if_then_else (le (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") + +(define_insn "" + [(set (pc) + (if_then_else (le (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "* +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (jb,%l0); + + OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", NULL_PTR); +}") + +(define_expand "bleu" + [(match_dup 1) + (set (pc) + (if_then_else (leu (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "operands[1] = (*i386_compare_gen)(i386_compare_op0, i386_compare_op1);") + +(define_insn "" + [(set (pc) + (if_then_else (leu (cc0) + (const_int 0)) + (label_ref (match_operand 0 "" "")) + (pc)))] + "" + "jbe %l0") + +;; Negated conditional jump instructions. + +(define_insn "" + [(set (pc) + (if_then_else (eq (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "* +{ + if (cc_prev_status.flags & CC_Z_IN_NOT_C) + return \"jc %l0\"; + else + return \"jne %l0\"; +}") + +(define_insn "" + [(set (pc) + (if_then_else (ne (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "* +{ + if (cc_prev_status.flags & CC_Z_IN_NOT_C) + return \"jnc %l0\"; + else + return \"je %l0\"; +}") + +(define_insn "" + [(set (pc) + (if_then_else (gt (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "* +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (jne,%l0); + + OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", NULL_PTR); +}") + +(define_insn "" + [(set (pc) + (if_then_else (gtu (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "jbe %l0") + +(define_insn "" + [(set (pc) + (if_then_else (lt (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "* +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (jne,%l0); + + OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\"); +}") + +(define_insn "" + [(set (pc) + (if_then_else (ltu (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "jae %l0") + +(define_insn "" + [(set (pc) + (if_then_else (ge (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "* +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (jne,%l0); + + OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\"); +}") + +(define_insn "" + [(set (pc) + (if_then_else (geu (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "jb %l0") + +(define_insn "" + [(set (pc) + (if_then_else (le (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "* +{ + if (TARGET_IEEE_FP && (cc_prev_status.flags & CC_IN_80387)) + return AS1 (jae,%l0); + + OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", NULL_PTR); +}") + +(define_insn "" + [(set (pc) + (if_then_else (leu (cc0) + (const_int 0)) + (pc) + (label_ref (match_operand 0 "" ""))))] + "" + "ja %l0") + +;; Unconditional and other jump instructions + +(define_insn "jump" + [(set (pc) + (label_ref (match_operand 0 "" "")))] + "" + "jmp %l0") + +(define_insn "indirect_jump" + [(set (pc) (match_operand:SI 0 "general_operand" "rm"))] + "" + "* +{ + CC_STATUS_INIT; + + return AS1 (jmp,%*%0); +}") + +;; ??? could transform while(--i > 0) S; to if (--i > 0) do S; while(--i); +;; if S does not change i + +(define_expand "decrement_and_branch_until_zero" + [(parallel [(set (pc) + (if_then_else (ge (plus:SI (match_operand:SI 0 "general_operand" "") + (const_int -1)) + (const_int 0)) + (label_ref (match_operand 1 "" "")) + (pc))) + (set (match_dup 0) + (plus:SI (match_dup 0) + (const_int -1)))])] + "" + "") + +(define_insn "" + [(set (pc) + (if_then_else (match_operator 0 "arithmetic_comparison_operator" + [(plus:SI (match_operand:SI 1 "general_operand" "+r,m") + (match_operand:SI 2 "general_operand" "rmi,ri")) + (const_int 0)]) + (label_ref (match_operand 3 "" "")) + (pc))) + (set (match_dup 1) + (plus:SI (match_dup 1) + (match_dup 2)))] + "" + "* +{ + CC_STATUS_INIT; + if (operands[2] == constm1_rtx) + output_asm_insn (AS1 (dec%L1,%1), operands); + + else if (operands[1] == const1_rtx) + output_asm_insn (AS1 (inc%L1,%1), operands); + + else + output_asm_insn (AS2 (add%L1,%2,%1), operands); + + return AS1 (%J0,%l3); +}") + +(define_insn "" + [(set (pc) + (if_then_else (match_operator 0 "arithmetic_comparison_operator" + [(minus:SI (match_operand:SI 1 "general_operand" "+r,m") + (match_operand:SI 2 "general_operand" "rmi,ri")) + (const_int 0)]) + (label_ref (match_operand 3 "" "")) + (pc))) + (set (match_dup 1) + (minus:SI (match_dup 1) + (match_dup 2)))] + "" + "* +{ + CC_STATUS_INIT; + if (operands[2] == const1_rtx) + output_asm_insn (AS1 (dec%L1,%1), operands); + + else if (operands[1] == constm1_rtx) + output_asm_insn (AS1 (inc%L1,%1), operands); + + else + output_asm_insn (AS2 (sub%L1,%2,%1), operands); + + return AS1 (%J0,%l3); +}") + +;; Implement switch statements when generating PIC code. Switches are +;; implemented by `tablejump' when not using -fpic. + +;; Emit code here to do the range checking and make the index zero based. + +(define_expand "casesi" + [(set (match_dup 5) + (minus:SI (match_operand:SI 0 "general_operand" "") + (match_operand:SI 1 "general_operand" ""))) + (set (cc0) + (compare:CC (match_dup 5) + (match_operand:SI 2 "general_operand" ""))) + (set (pc) + (if_then_else (gtu (cc0) + (const_int 0)) + (label_ref (match_operand 4 "" "")) + (pc))) + (parallel + [(set (pc) + (minus:SI (reg:SI 3) + (mem:SI (plus:SI (mult:SI (match_dup 5) + (const_int 4)) + (label_ref (match_operand 3 "" "")))))) + (clobber (match_scratch:SI 6 ""))])] + "flag_pic" + " +{ + operands[5] = gen_reg_rtx (SImode); + current_function_uses_pic_offset_table = 1; +}") + +;; Implement a casesi insn. + +;; Each entry in the "addr_diff_vec" looks like this as the result of the +;; two rules below: +;; +;; .long _GLOBAL_OFFSET_TABLE_+[.-.L2] +;; +;; 1. An expression involving an external reference may only use the +;; addition operator, and only with an assembly-time constant. +;; The example above satisfies this because ".-.L2" is a constant. +;; +;; 2. The symbol _GLOBAL_OFFSET_TABLE_ is magic, and at link time is +;; given the value of "GOT - .", where GOT is the actual address of +;; the Global Offset Table. Therefore, the .long above actually +;; stores the value "( GOT - . ) + [ . - .L2 ]", or "GOT - .L2". The +;; expression "GOT - .L2" by itself would generate an error from as(1). +;; +;; The pattern below emits code that looks like this: +;; +;; movl %ebx,reg +;; subl TABLE@GOTOFF(%ebx,index,4),reg +;; jmp reg +;; +;; The addr_diff_vec contents may be directly referenced with @GOTOFF, since +;; the addr_diff_vec is known to be part of this module. +;; +;; The subl above calculates "GOT - (( GOT - . ) + [ . - .L2 ])", which +;; evaluates to just ".L2". + +(define_insn "" + [(set (pc) + (minus:SI (reg:SI 3) + (mem:SI (plus:SI + (mult:SI (match_operand:SI 0 "register_operand" "r") + (const_int 4)) + (label_ref (match_operand 1 "" "")))))) + (clobber (match_scratch:SI 2 "=&r"))] + "" + "* +{ + rtx xops[4]; + + xops[0] = operands[0]; + xops[1] = operands[1]; + xops[2] = operands[2]; + xops[3] = pic_offset_table_rtx; + + output_asm_insn (AS2 (mov%L2,%3,%2), xops); + output_asm_insn (\"sub%L2 %l1@GOTOFF(%3,%0,4),%2\", xops); + output_asm_insn (AS1 (jmp,%*%2), xops); + ASM_OUTPUT_ALIGN_CODE (asm_out_file); + RET; +}") + +(define_insn "tablejump" + [(set (pc) (match_operand:SI 0 "general_operand" "rm")) + (use (label_ref (match_operand 1 "" "")))] + "" + "* +{ + CC_STATUS_INIT; + + return AS1 (jmp,%*%0); +}") + +;; Call insns. + +;; If generating PIC code, the predicate indirect_operand will fail +;; for operands[0] containing symbolic references on all of the named +;; call* patterns. Each named pattern is followed by an unnamed pattern +;; that matches any call to a symbolic CONST (ie, a symbol_ref). The +;; unnamed patterns are only used while generating PIC code, because +;; otherwise the named patterns match. + +;; Call subroutine returning no value. + +(define_expand "call_pop" + [(parallel [(call (match_operand:QI 0 "indirect_operand" "") + (match_operand:SI 1 "general_operand" "")) + (set (reg:SI 7) + (plus:SI (reg:SI 7) + (match_operand:SI 3 "immediate_operand" "")))])] + "" + " +{ + rtx addr; + + if (flag_pic) + current_function_uses_pic_offset_table = 1; + + /* With half-pic, force the address into a register. */ + addr = XEXP (operands[0], 0); + if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr)) + XEXP (operands[0], 0) = force_reg (Pmode, addr); + + if (! expander_call_insn_operand (operands[0], QImode)) + operands[0] + = change_address (operands[0], VOIDmode, + copy_to_mode_reg (Pmode, XEXP (operands[0], 0))); +}") + +(define_insn "" + [(call (match_operand:QI 0 "call_insn_operand" "m") + (match_operand:SI 1 "general_operand" "g")) + (set (reg:SI 7) (plus:SI (reg:SI 7) + (match_operand:SI 3 "immediate_operand" "i")))] + "" + "* +{ + if (GET_CODE (operands[0]) == MEM + && ! CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) + { + operands[0] = XEXP (operands[0], 0); + return AS1 (call,%*%0); + } + else + return AS1 (call,%P0); +}") + +(define_insn "" + [(call (mem:QI (match_operand:SI 0 "symbolic_operand" "")) + (match_operand:SI 1 "general_operand" "g")) + (set (reg:SI 7) (plus:SI (reg:SI 7) + (match_operand:SI 3 "immediate_operand" "i")))] + "!HALF_PIC_P ()" + "call %P0") + +(define_expand "call" + [(call (match_operand:QI 0 "indirect_operand" "") + (match_operand:SI 1 "general_operand" ""))] + ;; Operand 1 not used on the i386. + "" + " +{ + rtx addr; + + if (flag_pic) + current_function_uses_pic_offset_table = 1; + + /* With half-pic, force the address into a register. */ + addr = XEXP (operands[0], 0); + if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr)) + XEXP (operands[0], 0) = force_reg (Pmode, addr); + + if (! expander_call_insn_operand (operands[0], QImode)) + operands[0] + = change_address (operands[0], VOIDmode, + copy_to_mode_reg (Pmode, XEXP (operands[0], 0))); +}") + +(define_insn "" + [(call (match_operand:QI 0 "call_insn_operand" "m") + (match_operand:SI 1 "general_operand" "g"))] + ;; Operand 1 not used on the i386. + "" + "* +{ + if (GET_CODE (operands[0]) == MEM + && ! CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) + { + operands[0] = XEXP (operands[0], 0); + return AS1 (call,%*%0); + } + else + return AS1 (call,%P0); +}") + +(define_insn "" + [(call (mem:QI (match_operand:SI 0 "symbolic_operand" "")) + (match_operand:SI 1 "general_operand" "g"))] + ;; Operand 1 not used on the i386. + "!HALF_PIC_P ()" + "call %P0") + +;; Call subroutine, returning value in operand 0 +;; (which must be a hard register). + +(define_expand "call_value_pop" + [(parallel [(set (match_operand 0 "" "") + (call (match_operand:QI 1 "indirect_operand" "") + (match_operand:SI 2 "general_operand" ""))) + (set (reg:SI 7) + (plus:SI (reg:SI 7) + (match_operand:SI 4 "immediate_operand" "")))])] + "" + " +{ + rtx addr; + + if (flag_pic) + current_function_uses_pic_offset_table = 1; + + /* With half-pic, force the address into a register. */ + addr = XEXP (operands[1], 0); + if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr)) + XEXP (operands[1], 0) = force_reg (Pmode, addr); + + if (! expander_call_insn_operand (operands[1], QImode)) + operands[1] + = change_address (operands[1], VOIDmode, + copy_to_mode_reg (Pmode, XEXP (operands[1], 0))); +}") + +(define_insn "" + [(set (match_operand 0 "" "=rf") + (call (match_operand:QI 1 "call_insn_operand" "m") + (match_operand:SI 2 "general_operand" "g"))) + (set (reg:SI 7) (plus:SI (reg:SI 7) + (match_operand:SI 4 "immediate_operand" "i")))] + "" + "* +{ + if (GET_CODE (operands[1]) == MEM + && ! CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) + { + operands[1] = XEXP (operands[1], 0); + output_asm_insn (AS1 (call,%*%1), operands); + } + else + output_asm_insn (AS1 (call,%P1), operands); + + RET; +}") + +(define_insn "" + [(set (match_operand 0 "" "=rf") + (call (mem:QI (match_operand:SI 1 "symbolic_operand" "")) + (match_operand:SI 2 "general_operand" "g"))) + (set (reg:SI 7) (plus:SI (reg:SI 7) + (match_operand:SI 4 "immediate_operand" "i")))] + "!HALF_PIC_P ()" + "call %P1") + +(define_expand "call_value" + [(set (match_operand 0 "" "") + (call (match_operand:QI 1 "indirect_operand" "") + (match_operand:SI 2 "general_operand" "")))] + ;; Operand 2 not used on the i386. + "" + " +{ + rtx addr; + + if (flag_pic) + current_function_uses_pic_offset_table = 1; + + /* With half-pic, force the address into a register. */ + addr = XEXP (operands[1], 0); + if (GET_CODE (addr) != REG && HALF_PIC_P () && !CONSTANT_ADDRESS_P (addr)) + XEXP (operands[1], 0) = force_reg (Pmode, addr); + + if (! expander_call_insn_operand (operands[1], QImode)) + operands[1] + = change_address (operands[1], VOIDmode, + copy_to_mode_reg (Pmode, XEXP (operands[1], 0))); +}") + +(define_insn "" + [(set (match_operand 0 "" "=rf") + (call (match_operand:QI 1 "call_insn_operand" "m") + (match_operand:SI 2 "general_operand" "g")))] + ;; Operand 2 not used on the i386. + "" + "* +{ + if (GET_CODE (operands[1]) == MEM + && ! CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) + { + operands[1] = XEXP (operands[1], 0); + output_asm_insn (AS1 (call,%*%1), operands); + } + else + output_asm_insn (AS1 (call,%P1), operands); + + RET; +}") + +(define_insn "" + [(set (match_operand 0 "" "=rf") + (call (mem:QI (match_operand:SI 1 "symbolic_operand" "")) + (match_operand:SI 2 "general_operand" "g")))] + ;; Operand 2 not used on the i386. + "!HALF_PIC_P ()" + "call %P1") + +;; Call subroutine returning any type. + +(define_expand "untyped_call" + [(parallel [(call (match_operand 0 "" "") + (const_int 0)) + (match_operand 1 "" "") + (match_operand 2 "" "")])] + "" + " +{ + int i; + + /* In order to give reg-stack an easier job in validating two + coprocessor registers as containing a possible return value, + simply pretend the untyped call returns a complex long double + value. */ + emit_call_insn (TARGET_80387 + ? gen_call_value (gen_rtx (REG, XCmode, FIRST_FLOAT_REG), + operands[0], const0_rtx) + : gen_call (operands[0], const0_rtx)); + + for (i = 0; i < XVECLEN (operands[2], 0); i++) + { + rtx set = XVECEXP (operands[2], 0, i); + emit_move_insn (SET_DEST (set), SET_SRC (set)); + } + + /* The optimizer does not know that the call sets the function value + registers we stored in the result block. We avoid problems by + claiming that all hard registers are used and clobbered at this + point. */ + emit_insn (gen_blockage ()); + + DONE; +}") + +;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and +;; all of memory. This blocks insns from being moved across this point. + +(define_insn "blockage" + [(unspec_volatile [(const_int 0)] 0)] + "" + "") + +;; Insn emitted into the body of a function to return from a function. +;; This is only done if the function's epilogue is known to be simple. +;; See comments for simple_386_epilogue in i386.c. + +(define_insn "return" + [(return)] + "simple_386_epilogue ()" + "* +{ + function_epilogue (asm_out_file, get_frame_size ()); + RET; +}") + +(define_insn "nop" + [(const_int 0)] + "" + "nop") + +(define_expand "movstrsi" + [(parallel [(set (match_operand:BLK 0 "memory_operand" "") + (match_operand:BLK 1 "memory_operand" "")) + (use (match_operand:SI 2 "const_int_operand" "")) + (use (match_operand:SI 3 "const_int_operand" "")) + (clobber (match_scratch:SI 4 "")) + (clobber (match_dup 5)) + (clobber (match_dup 6))])] + "" + " +{ + rtx addr0, addr1; + + if (GET_CODE (operands[2]) != CONST_INT) + FAIL; + + addr0 = copy_to_mode_reg (Pmode, XEXP (operands[0], 0)); + addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); + + operands[5] = addr0; + operands[6] = addr1; + + operands[0] = gen_rtx (MEM, BLKmode, addr0); + operands[1] = gen_rtx (MEM, BLKmode, addr1); +}") + +;; It might seem that operands 0 & 1 could use predicate register_operand. +;; But strength reduction might offset the MEM expression. So we let +;; reload put the address into %edi & %esi. + +(define_insn "" + [(set (mem:BLK (match_operand:SI 0 "address_operand" "D")) + (mem:BLK (match_operand:SI 1 "address_operand" "S"))) + (use (match_operand:SI 2 "const_int_operand" "n")) + (use (match_operand:SI 3 "immediate_operand" "i")) + (clobber (match_scratch:SI 4 "=&c")) + (clobber (match_dup 0)) + (clobber (match_dup 1))] + "" + "* +{ + rtx xops[2]; + + output_asm_insn (\"cld\", operands); + if (GET_CODE (operands[2]) == CONST_INT) + { + if (INTVAL (operands[2]) & ~0x03) + { + xops[0] = GEN_INT ((INTVAL (operands[2]) >> 2) & 0x3fffffff); + xops[1] = operands[4]; + + output_asm_insn (AS2 (mov%L1,%0,%1), xops); +#ifdef INTEL_SYNTAX + output_asm_insn (\"rep movsd\", xops); +#else + output_asm_insn (\"rep\;movsl\", xops); +#endif + } + if (INTVAL (operands[2]) & 0x02) + output_asm_insn (\"movsw\", operands); + if (INTVAL (operands[2]) & 0x01) + output_asm_insn (\"movsb\", operands); + } + else + abort (); + RET; +}") + +(define_expand "cmpstrsi" + [(parallel [(set (match_operand:SI 0 "general_operand" "") + (compare:SI (match_operand:BLK 1 "general_operand" "") + (match_operand:BLK 2 "general_operand" ""))) + (use (match_operand:SI 3 "general_operand" "")) + (use (match_operand:SI 4 "immediate_operand" "")) + (clobber (match_dup 5)) + (clobber (match_dup 6)) + (clobber (match_dup 3))])] + "" + " +{ + rtx addr1, addr2; + + addr1 = copy_to_mode_reg (Pmode, XEXP (operands[1], 0)); + addr2 = copy_to_mode_reg (Pmode, XEXP (operands[2], 0)); + operands[3] = copy_to_mode_reg (SImode, operands[3]); + + operands[5] = addr1; + operands[6] = addr2; + + operands[1] = gen_rtx (MEM, BLKmode, addr1); + operands[2] = gen_rtx (MEM, BLKmode, addr2); + +}") + +;; memcmp recognizers. The `cmpsb' opcode does nothing if the count is +;; zero. Emit extra code to make sure that a zero-length compare is EQ. + +;; It might seem that operands 0 & 1 could use predicate register_operand. +;; But strength reduction might offset the MEM expression. So we let +;; reload put the address into %edi & %esi. + +;; ??? Most comparisons have a constant length, and it's therefore +;; possible to know that the length is non-zero, and to avoid the extra +;; code to handle zero-length compares. + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=&r") + (compare:SI (mem:BLK (match_operand:SI 1 "address_operand" "S")) + (mem:BLK (match_operand:SI 2 "address_operand" "D")))) + (use (match_operand:SI 3 "register_operand" "c")) + (use (match_operand:SI 4 "immediate_operand" "i")) + (clobber (match_dup 1)) + (clobber (match_dup 2)) + (clobber (match_dup 3))] + "" + "* +{ + rtx xops[4], label; + + label = gen_label_rtx (); + + output_asm_insn (\"cld\", operands); + output_asm_insn (AS2 (xor%L0,%0,%0), operands); + output_asm_insn (\"repz\;cmps%B2\", operands); + output_asm_insn (\"je %l0\", &label); + + xops[0] = operands[0]; + xops[1] = gen_rtx (MEM, QImode, + gen_rtx (PLUS, SImode, operands[1], constm1_rtx)); + xops[2] = gen_rtx (MEM, QImode, + gen_rtx (PLUS, SImode, operands[2], constm1_rtx)); + xops[3] = operands[3]; + + output_asm_insn (AS2 (movz%B1%L0,%1,%0), xops); + output_asm_insn (AS2 (movz%B2%L3,%2,%3), xops); + + output_asm_insn (AS2 (sub%L0,%3,%0), xops); + ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (label)); + RET; +}") + +(define_insn "" + [(set (cc0) + (compare:SI (mem:BLK (match_operand:SI 0 "address_operand" "S")) + (mem:BLK (match_operand:SI 1 "address_operand" "D")))) + (use (match_operand:SI 2 "register_operand" "c")) + (use (match_operand:SI 3 "immediate_operand" "i")) + (clobber (match_dup 0)) + (clobber (match_dup 1)) + (clobber (match_dup 2))] + "" + "* +{ + rtx xops[2]; + + cc_status.flags |= CC_NOT_SIGNED; + + xops[0] = gen_rtx (REG, QImode, 0); + xops[1] = CONST0_RTX (QImode); + + output_asm_insn (\"cld\", operands); + output_asm_insn (AS2 (test%B0,%1,%0), xops); + return \"repz\;cmps%B2\"; +}") + +(define_expand "ffssi2" + [(set (match_dup 2) + (plus:SI (ffs:SI (match_operand:SI 1 "general_operand" "")) + (const_int -1))) + (set (match_operand:SI 0 "general_operand" "") + (plus:SI (match_dup 2) (const_int 1)))] + "" + "operands[2] = gen_reg_rtx (SImode);") + +;; Note, you cannot optimize away the branch following the bsfl by assuming +;; that the destination is not modified if the input is 0, since not all +;; x86 implementations do this. + +(define_insn "" + [(set (match_operand:SI 0 "general_operand" "=&r") + (plus:SI (ffs:SI (match_operand:SI 1 "general_operand" "rm")) + (const_int -1)))] + "" + "* +{ + rtx xops[3]; + static int ffssi_label_number; + char buffer[30]; + + xops[0] = operands[0]; + xops[1] = operands[1]; + xops[2] = constm1_rtx; + output_asm_insn (AS2 (bsf%L0,%1,%0), xops); +#ifdef LOCAL_LABEL_PREFIX + sprintf (buffer, \"jnz %sLFFSSI%d\", + LOCAL_LABEL_PREFIX, ffssi_label_number); +#else + sprintf (buffer, \"jnz %sLFFSSI%d\", + \"\", ffssi_label_number); +#endif + output_asm_insn (buffer, xops); + output_asm_insn (AS2 (mov%L0,%2,%0), xops); +#ifdef LOCAL_LABEL_PREFIX + sprintf (buffer, \"%sLFFSSI%d:\", + LOCAL_LABEL_PREFIX, ffssi_label_number); +#else + sprintf (buffer, \"%sLFFSSI%d:\", + \"\", ffssi_label_number); +#endif + output_asm_insn (buffer, xops); + + ffssi_label_number++; + return \"\"; +}") + +(define_expand "ffshi2" + [(set (match_dup 2) + (plus:HI (ffs:HI (match_operand:HI 1 "general_operand" "")) + (const_int -1))) + (set (match_operand:HI 0 "general_operand" "") + (plus:HI (match_dup 2) (const_int 1)))] + "" + "operands[2] = gen_reg_rtx (HImode);") + +(define_insn "" + [(set (match_operand:HI 0 "general_operand" "=&r") + (plus:HI (ffs:HI (match_operand:SI 1 "general_operand" "rm")) + (const_int -1)))] + "" + "* +{ + rtx xops[3]; + static int ffshi_label_number; + char buffer[30]; + + xops[0] = operands[0]; + xops[1] = operands[1]; + xops[2] = constm1_rtx; + output_asm_insn (AS2 (bsf%W0,%1,%0), xops); +#ifdef LOCAL_LABEL_PREFIX + sprintf (buffer, \"jnz %sLFFSHI%d\", + LOCAL_LABEL_PREFIX, ffshi_label_number); +#else + sprintf (buffer, \"jnz %sLFFSHI%d\", + \"\", ffshi_label_number); +#endif + output_asm_insn (buffer, xops); + output_asm_insn (AS2 (mov%W0,%2,%0), xops); +#ifdef LOCAL_LABEL_PREFIX + sprintf (buffer, \"%sLFFSHI%d:\", + LOCAL_LABEL_PREFIX, ffshi_label_number); +#else + sprintf (buffer, \"%sLFFSHI%d:\", + \"\", ffshi_label_number); +#endif + output_asm_insn (buffer, xops); + + ffshi_label_number++; + return \"\"; +}") + +;; These patterns match the binary 387 instructions for addM3, subM3, +;; mulM3 and divM3. There are three patterns for each of DFmode and +;; SFmode. The first is the normal insn, the second the same insn but +;; with one operand a conversion, and the third the same insn but with +;; the other operand a conversion. The conversion may be SFmode or +;; SImode if the target mode DFmode, but only SImode if the target mode +;; is SFmode. + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f,f") + (match_operator:DF 3 "binary_387_op" + [(match_operand:DF 1 "nonimmediate_operand" "0,fm") + (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))] + "TARGET_80387" + "* return output_387_binary_op (insn, operands);") + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f") + (match_operator:DF 3 "binary_387_op" + [(float:DF (match_operand:SI 1 "general_operand" "rm")) + (match_operand:DF 2 "general_operand" "0")]))] + "TARGET_80387" + "* return output_387_binary_op (insn, operands);") + +(define_insn "" + [(set (match_operand:XF 0 "register_operand" "=f,f") + (match_operator:XF 3 "binary_387_op" + [(match_operand:XF 1 "nonimmediate_operand" "0,f") + (match_operand:XF 2 "nonimmediate_operand" "f,0")]))] + "TARGET_80387" + "* return output_387_binary_op (insn, operands);") + +(define_insn "" + [(set (match_operand:XF 0 "register_operand" "=f") + (match_operator:XF 3 "binary_387_op" + [(float:XF (match_operand:SI 1 "general_operand" "rm")) + (match_operand:XF 2 "general_operand" "0")]))] + "TARGET_80387" + "* return output_387_binary_op (insn, operands);") + +(define_insn "" + [(set (match_operand:XF 0 "register_operand" "=f,f") + (match_operator:XF 3 "binary_387_op" + [(float_extend:XF (match_operand:SF 1 "general_operand" "fm,0")) + (match_operand:XF 2 "general_operand" "0,f")]))] + "TARGET_80387" + "* return output_387_binary_op (insn, operands);") + +(define_insn "" + [(set (match_operand:XF 0 "register_operand" "=f") + (match_operator:XF 3 "binary_387_op" + [(match_operand:XF 1 "general_operand" "0") + (float:XF (match_operand:SI 2 "general_operand" "rm"))]))] + "TARGET_80387" + "* return output_387_binary_op (insn, operands);") + +(define_insn "" + [(set (match_operand:XF 0 "register_operand" "=f,f") + (match_operator:XF 3 "binary_387_op" + [(match_operand:XF 1 "general_operand" "0,f") + (float_extend:XF + (match_operand:SF 2 "general_operand" "fm,0"))]))] + "TARGET_80387" + "* return output_387_binary_op (insn, operands);") + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f,f") + (match_operator:DF 3 "binary_387_op" + [(float_extend:DF (match_operand:SF 1 "general_operand" "fm,0")) + (match_operand:DF 2 "general_operand" "0,f")]))] + "TARGET_80387" + "* return output_387_binary_op (insn, operands);") + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f") + (match_operator:DF 3 "binary_387_op" + [(match_operand:DF 1 "general_operand" "0") + (float:DF (match_operand:SI 2 "general_operand" "rm"))]))] + "TARGET_80387" + "* return output_387_binary_op (insn, operands);") + +(define_insn "" + [(set (match_operand:DF 0 "register_operand" "=f,f") + (match_operator:DF 3 "binary_387_op" + [(match_operand:DF 1 "general_operand" "0,f") + (float_extend:DF + (match_operand:SF 2 "general_operand" "fm,0"))]))] + "TARGET_80387" + "* return output_387_binary_op (insn, operands);") + +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=f,f") + (match_operator:SF 3 "binary_387_op" + [(match_operand:SF 1 "nonimmediate_operand" "0,fm") + (match_operand:SF 2 "nonimmediate_operand" "fm,0")]))] + "TARGET_80387" + "* return output_387_binary_op (insn, operands);") + +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=f") + (match_operator:SF 3 "binary_387_op" + [(float:SF (match_operand:SI 1 "general_operand" "rm")) + (match_operand:SF 2 "general_operand" "0")]))] + "TARGET_80387" + "* return output_387_binary_op (insn, operands);") + +(define_insn "" + [(set (match_operand:SF 0 "register_operand" "=f") + (match_operator:SF 3 "binary_387_op" + [(match_operand:SF 1 "general_operand" "0") + (float:SF (match_operand:SI 2 "general_operand" "rm"))]))] + "TARGET_80387" + "* return output_387_binary_op (insn, operands);") + +(define_expand "strlensi" + [(parallel [(set (match_dup 4) + (unspec:SI [(mem:BLK (match_operand:BLK 1 "general_operand" "")) + (match_operand:QI 2 "register_operand" "") + (match_operand:SI 3 "immediate_operand" "")] 0)) + (clobber (match_dup 1))]) + (set (match_dup 5) + (not:SI (match_dup 4))) + (set (match_operand:SI 0 "register_operand" "") + (minus:SI (match_dup 5) + (const_int 1)))] + "" + " +{ + operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); + operands[4] = gen_reg_rtx (SImode); + operands[5] = gen_reg_rtx (SImode); +}") + +;; It might seem that operands 0 & 1 could use predicate register_operand. +;; But strength reduction might offset the MEM expression. So we let +;; reload put the address into %edi. + +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=&c") + (unspec:SI [(mem:BLK (match_operand:SI 1 "address_operand" "D")) + (match_operand:QI 2 "register_operand" "a") + (match_operand:SI 3 "immediate_operand" "i")] 0)) + (clobber (match_dup 1))] + "" + "* +{ + rtx xops[2]; + + xops[0] = operands[0]; + xops[1] = constm1_rtx; + output_asm_insn (\"cld\", operands); + output_asm_insn (AS2 (mov%L0,%1,%0), xops); + return \"repnz\;scas%B2\"; +}") diff --git a/contrib/gcc/config/i386/i386iscgas.h b/contrib/gcc/config/i386/i386iscgas.h new file mode 100644 index 0000000..526fe37 --- /dev/null +++ b/contrib/gcc/config/i386/i386iscgas.h @@ -0,0 +1,67 @@ +/* Definitions for Intel 386 running Interactive Unix System V, + producing stabs-in-coff output (using a slightly modified gas). + Specifically, this is for recent versions that support POSIX; + for version 2.0.2, use configuration option i386-sysv instead. */ + +/* Underscores are not used on ISC systems (probably not on any COFF + system), despite the comments in i386/gas.h. If this is not defined, + enquire (for example) will fail to link. --karl@cs.umb.edu */ +#define NO_UNDERSCORES + +/* Mostly like other gas-using systems. */ +#include "i386/gas.h" + +/* But with ISC-specific additions. */ +#include "i386/isc.h" + +/* We do not want to output SDB debugging information. */ + +#undef SDB_DEBUGGING_INFO + +/* We want to output DBX debugging information. */ + +#define DBX_DEBUGGING_INFO + + +/* The function `dbxout_init' in dbxout.c omits the first character of + `ltext_label_name' when outputting the main source directory and main + source filename. I don't understand why, but rather than making a + system-independent change there, I override dbxout.c's defaults. + Perhaps it would be better to use ".Ltext0" instead of + `ltext_label_name', but we've already generated the label, so we just + use it here. --karl@cs.umb.edu */ +#define DBX_OUTPUT_MAIN_SOURCE_DIRECTORY(asmfile, cwd) \ + do { fprintf (asmfile, "%s ", ASM_STABS_OP); \ + output_quoted_string (asmfile, cwd); \ + fprintf (asmfile, ",%d,0,0,%s\n", N_SO, ltext_label_name); \ + } while (0) +#define DBX_OUTPUT_MAIN_SOURCE_FILENAME(asmfile, input_file_name) \ + fprintf (asmfile, "%s ", ASM_STABS_OP); \ + output_quoted_string (input_file_name); \ + fprintf (asmfile, ",%d,0,0,%s\n", N_SO, ltext_label_name); \ + text_section (); \ + ASM_OUTPUT_INTERNAL_LABEL (asmfile, "Ltext", 0) + + +/* Because we don't include `svr3.h', we haven't yet defined SIZE_TYPE + and PTRDIFF_TYPE. ISC's definitions don't match GCC's defaults, so: */ + +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "int" + + +/* But we can't use crtbegin.o and crtend.o, because gas 1.38.1 doesn't + grok .section. The definitions here are otherwise identical to those + in i386/isc.h. */ +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ + "%{!shlib:%{posix:%{pg:mcrtp1.o%s}%{!pg:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}}\ + %{!posix:%{pg:mcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}\ + %{p:-L/lib/libp} %{pg:-L/lib/libp}}}\ + %{shlib:%{posix:crtp1.o%s}%{!posix:crt1.o%s}}" + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC "crtn.o%s" diff --git a/contrib/gcc/config/i386/isc.h b/contrib/gcc/config/i386/isc.h new file mode 100644 index 0000000..cf8c5f6 --- /dev/null +++ b/contrib/gcc/config/i386/isc.h @@ -0,0 +1,89 @@ +/* Assembler-independent definitions for an Intel 386 running + Interactive Unix System V. Specifically, this is for recent versions + that support POSIX. */ + +/* Use crt1.o, not crt0.o, as a startup file, and crtn.o as a closing file. */ +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ + "%{!shlib:%{posix:%{pg:mcrtp1.o%s}%{!pg:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}}\ + %{Xp:%{pg:mcrtp1.o%s}%{!pg:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}}\ + %{!posix:%{!Xp:%{pg:mcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}\ + %{p:-L/lib/libp} %{pg:-L/lib/libp}}}}\ + %{shlib:%{Xp:crtp1.o%s}%{posix:crtp1.o%s}%{!posix:%{!Xp:crt1.o%s}}}\ + crtbegin.o%s" + +#define ENDFILE_SPEC "crtend.o%s crtn.o%s" + +/* Library spec */ +#undef LIB_SPEC +#define LIB_SPEC "%{shlib:-lc_s} %{posix:-lcposix} %{Xp:-lcposix} -lc -lg" + +#undef CPP_SPEC +#define CPP_SPEC "%{posix:-D_POSIX_SOURCE} %{Xp:-D_POSIX_SOURCE}" + +/* ISC 2.2 uses `char' for `wchar_t'. */ +#undef WCHAR_TYPE +#define WCHAR_TYPE "char" + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE BITS_PER_UNIT + +#if 0 +/* This is apparently not true: ISC versions up to 3.0, at least, use + the standard calling sequence in which the called function pops the + extra arg. */ +/* caller has to pop the extra argument passed to functions that return + structures. */ + +#undef RETURN_POPS_ARGS +#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \ + (TREE_CODE (FUNTYPE) == IDENTIFIER_NODE ? 0 \ + : (TARGET_RTD \ + && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ + || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ + == void_type_node))) ? (SIZE) \ + : 0) +/* On other 386 systems, the last line looks like this: + : (aggregate_value_p (TREE_TYPE (FUNTYPE))) ? GET_MODE_SIZE (Pmode) : 0) */ +#endif + +/* Handle #pragma pack and #pragma weak. */ +#define HANDLE_SYSV_PRAGMA + +/* By default, target has a 80387, uses IEEE compatible arithmetic, + and returns float values in the 387, ie, + (TARGET_80387 | TARGET_FLOAT_RETURNS_IN_80387) + + ISC's software emulation of a 387 fails to handle the `fucomp' + opcode. fucomp is only used when generating IEEE compliant code. + So don't make TARGET_IEEE_FP default for ISC. */ + +#undef TARGET_DEFAULT +#define TARGET_DEFAULT 0201 + +/* The ISC 2.0.2 software FPU emulator apparently can't handle + 80-bit XFmode insns, so don't generate them. */ +#undef LONG_DOUBLE_TYPE_SIZE +#define LONG_DOUBLE_TYPE_SIZE 64 + +/* The ISC assembler does not like a .file directive with a name + longer than 14 characters. Truncating it will not permit + debugging to work properly, but at least we won't get an error + message. */ + +#undef ASM_FILE_START +#define ASM_FILE_START(FILE) \ + do { \ + char c; \ + int max = 0; \ + char *string = dump_base_name; \ + \ + fputs ("\t.file\t\"", FILE); \ + \ + while ((c = *string++) != 0 && max++ < 14) { \ + if (c == '\"' || c == '\\') \ + putc ('\\', FILE); \ + putc (c, FILE); \ + } \ + fputs ("\"\n", FILE); \ + } while (0) diff --git a/contrib/gcc/config/i386/isccoff.h b/contrib/gcc/config/i386/isccoff.h new file mode 100644 index 0000000..383b981 --- /dev/null +++ b/contrib/gcc/config/i386/isccoff.h @@ -0,0 +1,12 @@ +/* Definitions for Intel 386 running Interactive Unix System V. + Specifically, this is for recent versions that support POSIX; + for version 2.0.2, use configuration option i386-sysv instead. + (But set TARGET_DEFAULT to 0201 if you do that, + if you don't have a real 80387.) */ + +/* Mostly it's like AT&T Unix System V. */ + +#include "i386/sysv3.h" + +/* But with a few changes. */ +#include "i386/isc.h" diff --git a/contrib/gcc/config/i386/iscdbx.h b/contrib/gcc/config/i386/iscdbx.h new file mode 100644 index 0000000..6c2d42e --- /dev/null +++ b/contrib/gcc/config/i386/iscdbx.h @@ -0,0 +1,43 @@ +/* Definitions for Intel 386 running Interactive Unix System V, + using dbx-in-coff encapsulation. + Specifically, this is for recent versions that support POSIX. + Copyright (C) 1992, 1995 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Mostly it's like AT&T Unix System V with dbx-in-coff. */ + +#include "i386/svr3dbx.h" + +/* But with a few changes. */ +#undef ENDFILE_SPEC +#include "i386/isc.h" + +/* Overridden defines for ifile usage. */ + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ + "%{!r:%{!z:svr3.ifile%s}%{z:svr3z.ifile%s}}\ + %{!shlib:%{posix:%{pg:mcrtp1.o%s}%{!pg:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}}\ + %{Xp:%{pg:mcrtp1.o%s}%{!pg:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}}\ + %{!posix:%{!Xp:%{pg:mcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}}}\ + %{p:-L/usr/lib/libp} %{pg:-L/usr/lib/libp}}\ + %{shlib:%{posix:crtp1.o%s}%{Xp:crtp1.o%s}%{!posix:%{!Xp:crt1.o%s}}}" + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC "crtn.o%s" diff --git a/contrib/gcc/config/i386/linux-aout.h b/contrib/gcc/config/i386/linux-aout.h new file mode 100644 index 0000000..7e46c68 --- /dev/null +++ b/contrib/gcc/config/i386/linux-aout.h @@ -0,0 +1,76 @@ +/* Definitions for Intel 386 running Linux + Copyright (C) 1992, 1994, 1995 Free Software Foundation, Inc. + Contributed by H.J. Lu (hjl@nynexst.com) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* This is tested by i386/gas.h. */ +#define YES_UNDERSCORES + +#include <i386/gstabs.h> +#include <linux-aout.h> /* some common stuff */ + +/* Specify predefined symbols in preprocessor. */ + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dunix -Di386 -Dlinux -Asystem(unix) -Asystem(posix) -Acpu(i386) -Amachine(i386)" + +#undef CPP_SPEC +#if TARGET_CPU_DEFAULT == 2 +#define CPP_SPEC "%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{!m386:-D__i486__} %{posix:-D_POSIX_SOURCE}" +#else +#define CPP_SPEC "%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{m486:-D__i486__} %{posix:-D_POSIX_SOURCE}" +#endif + +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "int" + +#undef WCHAR_TYPE +#define WCHAR_TYPE "long int" + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE BITS_PER_WORD + +/* Don't default to pcc-struct-return, because gcc is the only compiler, + and we want to retain compatibility with older gcc versions. */ +#define DEFAULT_PCC_STRUCT_RETURN 0 + +#undef LIB_SPEC + +#if 1 +/* We no longer link with libc_p.a or libg.a by default. If you + * want to profile or debug the Linux C library, please add + * -lc_p or -ggdb to LDFLAGS at the link time, respectively. + */ +#define LIB_SPEC \ +"%{mieee-fp:-lieee} %{p:-lgmon} %{pg:-lgmon} %{!ggdb:-lc} %{ggdb:-lg}" +#else +#define LIB_SPEC \ +"%{mieee-fp:-lieee} %{p:-lgmon -lc_p} %{pg:-lgmon -lc_p} \ + %{!p:%{!pg:%{!g*:-lc} %{g*:-lg -static}}}" +#endif + + +#undef LINK_SPEC +#define LINK_SPEC "-m i386linux" + +/* Get perform_* macros to build libgcc.a. */ +#include "i386/perform.h" diff --git a/contrib/gcc/config/i386/linux-oldld.h b/contrib/gcc/config/i386/linux-oldld.h new file mode 100644 index 0000000..c3066ba --- /dev/null +++ b/contrib/gcc/config/i386/linux-oldld.h @@ -0,0 +1,76 @@ +/* Definitions for Intel 386 running Linux with pre-BFD a.out linkers + Copyright (C) 1995 Free Software Foundation, Inc. + Contributed by Michael Meissner (meissner@cygnus.com) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* This is tested by i386/gas.h. */ +#define YES_UNDERSCORES + +#include <i386/gstabs.h> +#include <linux-aout.h> /* some common stuff */ + +/* Specify predefined symbols in preprocessor. */ + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dunix -Di386 -Dlinux -Asystem(unix) -Asystem(posix) -Acpu(i386) -Amachine(i386)" + +#undef CPP_SPEC +#if TARGET_CPU_DEFAULT == 2 +#define CPP_SPEC "%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{!m386:-D__i486__} %{posix:-D_POSIX_SOURCE}" +#else +#define CPP_SPEC "%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{m486:-D__i486__} %{posix:-D_POSIX_SOURCE}" +#endif + +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "int" + +#undef WCHAR_TYPE +#define WCHAR_TYPE "long int" + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE BITS_PER_WORD + +/* Don't default to pcc-struct-return, because gcc is the only compiler, + and we want to retain compatibility with older gcc versions. */ +#define DEFAULT_PCC_STRUCT_RETURN 0 + +#undef LIB_SPEC + +#if 1 +/* We no longer link with libc_p.a or libg.a by default. If you + * want to profile or debug the Linux C library, please add + * -lc_p or -ggdb to LDFLAGS at the link time, respectively. + */ +#define LIB_SPEC \ +"%{mieee-fp:-lieee} %{p:-lgmon} %{pg:-lgmon} %{!ggdb:-lc} %{ggdb:-lg}" +#else +#define LIB_SPEC \ +"%{mieee-fp:-lieee} %{p:-lgmon -lc_p} %{pg:-lgmon -lc_p} \ + %{!p:%{!pg:%{!g*:-lc} %{g*:-lg -static}}}" +#endif + + +#undef LINK_SPEC +#define LINK_SPEC "" + +/* Get perform_* macros to build libgcc.a. */ +#include <i386/perform.h> diff --git a/contrib/gcc/config/i386/linux.h b/contrib/gcc/config/i386/linux.h new file mode 100644 index 0000000..f077de5 --- /dev/null +++ b/contrib/gcc/config/i386/linux.h @@ -0,0 +1,212 @@ +/* Definitions for Intel 386 running Linux with ELF format + Copyright (C) 1994, 1995 Free Software Foundation, Inc. + Contributed by Eric Youngdale. + Modified for stabs-in-ELF by H.J. Lu. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define LINUX_DEFAULT_ELF + +/* A lie, I guess, but the general idea behind linux/ELF is that we are + supposed to be outputting something that will assemble under SVr4. + This gets us pretty close. */ +#include <i386/i386.h> /* Base i386 target machine definitions */ +#include <i386/att.h> /* Use the i386 AT&T assembler syntax */ +#include <linux.h> /* some common stuff */ + +#undef TARGET_VERSION +#define TARGET_VERSION fprintf (stderr, " (i386 Linux/ELF)"); + +/* The svr4 ABI for the i386 says that records and unions are returned + in memory. */ +#undef DEFAULT_PCC_STRUCT_RETURN +#define DEFAULT_PCC_STRUCT_RETURN 1 + +/* This is how to output an element of a case-vector that is relative. + This is only used for PIC code. See comments by the `casesi' insn in + i386.md for an explanation of the expression this outputs. */ +#undef ASM_OUTPUT_ADDR_DIFF_ELT +#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ + fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE) + +/* Indicate that jump tables go in the text section. This is + necessary when compiling PIC code. */ +#define JUMP_TABLES_IN_TEXT_SECTION + +/* Copy this from the svr4 specifications... */ +/* Define the register numbers to be used in Dwarf debugging information. + The SVR4 reference port C compiler uses the following register numbers + in its Dwarf output code: + 0 for %eax (gnu regno = 0) + 1 for %ecx (gnu regno = 2) + 2 for %edx (gnu regno = 1) + 3 for %ebx (gnu regno = 3) + 4 for %esp (gnu regno = 7) + 5 for %ebp (gnu regno = 6) + 6 for %esi (gnu regno = 4) + 7 for %edi (gnu regno = 5) + The following three DWARF register numbers are never generated by + the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4 + believes these numbers have these meanings. + 8 for %eip (no gnu equivalent) + 9 for %eflags (no gnu equivalent) + 10 for %trapno (no gnu equivalent) + It is not at all clear how we should number the FP stack registers + for the x86 architecture. If the version of SDB on x86/svr4 were + a bit less brain dead with respect to floating-point then we would + have a precedent to follow with respect to DWARF register numbers + for x86 FP registers, but the SDB on x86/svr4 is so completely + broken with respect to FP registers that it is hardly worth thinking + of it as something to strive for compatibility with. + The version of x86/svr4 SDB I have at the moment does (partially) + seem to believe that DWARF register number 11 is associated with + the x86 register %st(0), but that's about all. Higher DWARF + register numbers don't seem to be associated with anything in + particular, and even for DWARF regno 11, SDB only seems to under- + stand that it should say that a variable lives in %st(0) (when + asked via an `=' command) if we said it was in DWARF regno 11, + but SDB still prints garbage when asked for the value of the + variable in question (via a `/' command). + (Also note that the labels SDB prints for various FP stack regs + when doing an `x' command are all wrong.) + Note that these problems generally don't affect the native SVR4 + C compiler because it doesn't allow the use of -O with -g and + because when it is *not* optimizing, it allocates a memory + location for each floating-point variable, and the memory + location is what gets described in the DWARF AT_location + attribute for the variable in question. + Regardless of the severe mental illness of the x86/svr4 SDB, we + do something sensible here and we use the following DWARF + register numbers. Note that these are all stack-top-relative + numbers. + 11 for %st(0) (gnu regno = 8) + 12 for %st(1) (gnu regno = 9) + 13 for %st(2) (gnu regno = 10) + 14 for %st(3) (gnu regno = 11) + 15 for %st(4) (gnu regno = 12) + 16 for %st(5) (gnu regno = 13) + 17 for %st(6) (gnu regno = 14) + 18 for %st(7) (gnu regno = 15) +*/ +#undef DBX_REGISTER_NUMBER +#define DBX_REGISTER_NUMBER(n) \ +((n) == 0 ? 0 \ + : (n) == 1 ? 2 \ + : (n) == 2 ? 1 \ + : (n) == 3 ? 3 \ + : (n) == 4 ? 6 \ + : (n) == 5 ? 7 \ + : (n) == 6 ? 5 \ + : (n) == 7 ? 4 \ + : ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) ? (n)+3 \ + : (-1)) + +/* Output assembler code to FILE to increment profiler label # LABELNO + for profiling a function entry. */ + +#undef FUNCTION_PROFILER +#define FUNCTION_PROFILER(FILE, LABELNO) \ +{ \ + if (flag_pic) \ + { \ + fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n", \ + LPREFIX, (LABELNO)); \ + fprintf (FILE, "\tcall *mcount@GOT(%%ebx)\n"); \ + } \ + else \ + { \ + fprintf (FILE, "\tmovl $%sP%d,%%edx\n", LPREFIX, (LABELNO)); \ + fprintf (FILE, "\tcall mcount\n"); \ + } \ +} + +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "int" + +#undef WCHAR_TYPE +#define WCHAR_TYPE "long int" + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE BITS_PER_WORD + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-D__ELF__ -Dunix -Di386 -Dlinux -Asystem(unix) -Asystem(posix) -Acpu(i386) -Amachine(i386)" + +#undef CPP_SPEC +#if TARGET_CPU_DEFAULT == 2 +#define CPP_SPEC "%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{!m386:-D__i486__} %{posix:-D_POSIX_SOURCE}" +#else +#define CPP_SPEC "%{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__} %{m486:-D__i486__} %{posix:-D_POSIX_SOURCE}" +#endif + +#undef LIB_SPEC +#if 1 +/* We no longer link with libc_p.a or libg.a by default. If you + * want to profile or debug the Linux C library, please add + * -lc_p or -ggdb to LDFLAGS at the link time, respectively. + */ +#define LIB_SPEC \ + "%{!shared: %{mieee-fp:-lieee} %{p:-lgmon} %{pg:-lgmon} \ + %{!ggdb:-lc} %{ggdb:-lg}}" +#else +#define LIB_SPEC \ + "%{!shared: \ + %{mieee-fp:-lieee} %{p:-lgmon -lc_p} %{pg:-lgmon -lc_p} \ + %{!p:%{!pg:%{!g*:-lc} %{g*:-lg}}}}" +#endif + +/* Provide a LINK_SPEC appropriate for Linux. Here we provide support + for the special GCC options -static and -shared, which allow us to + link things in one of these three modes by applying the appropriate + combinations of options at link-time. We like to support here for + as many of the other GNU linker options as possible. But I don't + have the time to search for those flags. I am sure how to add + support for -soname shared_object_name. H.J. + + I took out %{v:%{!V:-V}}. It is too much :-(. They can use + -Wl,-V. + + When the -shared link option is used a final link is not being + done. */ + +/* If ELF is the default format, we should not use /lib/elf. */ + +#undef LINK_SPEC +#ifndef LINUX_DEFAULT_ELF +#define LINK_SPEC "-m elf_i386 %{shared:-shared} \ + %{!shared: \ + %{!ibcs: \ + %{!static: \ + %{rdynamic:-export-dynamic} \ + %{!dynamic-linker:-dynamic-linker /lib/elf/ld-linux.so.1} \ + %{!rpath:-rpath /lib/elf/}} %{static:-static}}}" +#else +#define LINK_SPEC "-m elf_i386 %{shared:-shared} \ + %{!shared: \ + %{!ibcs: \ + %{!static: \ + %{rdynamic:-export-dynamic} \ + %{!dynamic-linker:-dynamic-linker /lib/ld-linux.so.1}} \ + %{static:-static}}}" +#endif + +/* Get perform_* macros to build libgcc.a. */ +#include "i386/perform.h" diff --git a/contrib/gcc/config/i386/lynx-ng.h b/contrib/gcc/config/i386/lynx-ng.h new file mode 100644 index 0000000..ec4e2961 --- /dev/null +++ b/contrib/gcc/config/i386/lynx-ng.h @@ -0,0 +1,37 @@ +/* Definitions for Intel 386 running LynxOS, using Lynx's old as and ld. + Copyright (C) 1993, 1995 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include <i386/gstabs.h> +#include <lynx-ng.h> + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dunix -Di386 -DI386 -DLynx -DIBITS32 -Asystem(unix) -Asystem(lynx) -Acpu(i386) -Amachine(i386)" + +/* Provide required defaults for linker switches. */ + +#undef LINK_SPEC +#define LINK_SPEC "-P1000 %{msystem-v:-V} %{mcoff:-k}" + +/* Apparently LynxOS clobbers ebx when you call into the OS. */ + +#undef CALL_USED_REGISTERS +#define CALL_USED_REGISTERS \ +/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \ +{ 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } diff --git a/contrib/gcc/config/i386/lynx.h b/contrib/gcc/config/i386/lynx.h new file mode 100644 index 0000000..4ac00a0 --- /dev/null +++ b/contrib/gcc/config/i386/lynx.h @@ -0,0 +1,39 @@ +/* Definitions for Intel 386 running LynxOS. + Copyright (C) 1993, 1995 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include <i386/gstabs.h> +#include <lynx.h> + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dunix -Di386 -DI386 -DLynx -DIBITS32 -Asystem(unix) -Asystem(lynx) -Acpu(i386) -Amachine(i386)" + +/* This is how to output a reference to a user-level label named NAME. */ + +/* Override the svr3 convention of adding a leading underscore. */ + +#undef ASM_OUTPUT_LABELREF +#define ASM_OUTPUT_LABELREF(FILE,NAME) fprintf (FILE, "%s", NAME) + +/* Apparently LynxOS clobbers ebx when you call into the OS. */ + +#undef CALL_USED_REGISTERS +#define CALL_USED_REGISTERS \ +/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7,arg*/ \ +{ 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 } diff --git a/contrib/gcc/config/i386/mach.h b/contrib/gcc/config/i386/mach.h new file mode 100644 index 0000000..4b7cf37 --- /dev/null +++ b/contrib/gcc/config/i386/mach.h @@ -0,0 +1,20 @@ +/* Configuration for an i386 running Mach as the target machine. */ + +/* We do want to add an underscore to the front of each user symbol. + i386/gas.h checks this. */ +#define YES_UNDERSCORES + +#include "i386/gstabs.h" + +/* Get perform_* macros to build libgcc.a. */ +#include "i386/perform.h" + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dunix -Di386 -DMACH -Asystem(unix) -Asystem(mach) -Acpu(i386) -Amachine(i386)" + +/* Specify extra dir to search for include files. */ +#define SYSTEM_INCLUDE_DIR "/usr/mach/include" + +/* Don't default to pcc-struct-return, because gcc is the only compiler, and + we want to retain compatibility with older gcc versions. */ +#define DEFAULT_PCC_STRUCT_RETURN 0 diff --git a/contrib/gcc/config/i386/netbsd.h b/contrib/gcc/config/i386/netbsd.h new file mode 100644 index 0000000..180ff35 --- /dev/null +++ b/contrib/gcc/config/i386/netbsd.h @@ -0,0 +1,80 @@ +/* This goes away when the math-emulator is fixed */ +#define TARGET_CPU_DEFAULT 0400 /* TARGET_NO_FANCY_MATH_387 */ + +/* This is tested by i386gas.h. */ +#define YES_UNDERSCORES + +#include <i386/gstabs.h> + +/* Get perform_* macros to build libgcc.a. */ +#include <i386/perform.h> + +/* Get generic NetBSD definitions. */ +#include <netbsd.h> + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dunix -Di386 -D__NetBSD__ -Asystem(unix) -Asystem(NetBSD) -Acpu(i386) -Amachine(i386)" + +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "int" + +#undef WCHAR_TYPE +#define WCHAR_TYPE "int" + +#undef WCHAR_UNSIGNED +#define WCHAR_UNSIGNED 0 + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE 32 + +#define HANDLE_SYSV_PRAGMA + +/* There are conflicting reports about whether this system uses + a different assembler syntax. wilson@cygnus.com says # is right. */ +#undef COMMENT_BEGIN +#define COMMENT_BEGIN "#" + +#undef ASM_APP_ON +#define ASM_APP_ON "#APP\n" + +#undef ASM_APP_OFF +#define ASM_APP_OFF "#NO_APP\n" + +/* The following macros are stolen from i386v4.h */ +/* These have to be defined to get PIC code correct */ + +/* This is how to output an element of a case-vector that is relative. + This is only used for PIC code. See comments by the `casesi' insn in + i386.md for an explanation of the expression this outputs. */ + +#undef ASM_OUTPUT_ADDR_DIFF_ELT +#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ + fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE) + +/* Indicate that jump tables go in the text section. This is + necessary when compiling PIC code. */ + +#define JUMP_TABLES_IN_TEXT_SECTION + +/* Don't default to pcc-struct-return, because gcc is the only compiler, and + we want to retain compatibility with older gcc versions. */ +#define DEFAULT_PCC_STRUCT_RETURN 0 + +/* Profiling routines, partially copied from i386/osfrose.h. */ + +/* Redefine this to use %eax instead of %edx. */ +#undef FUNCTION_PROFILER +#define FUNCTION_PROFILER(FILE, LABELNO) \ +{ \ + if (flag_pic) \ + { \ + fprintf (FILE, "\tcall mcount@PLT\n"); \ + } \ + else \ + { \ + fprintf (FILE, "\tcall mcount\n"); \ + } \ +} diff --git a/contrib/gcc/config/i386/next.c b/contrib/gcc/config/i386/next.c new file mode 100644 index 0000000..f249647 --- /dev/null +++ b/contrib/gcc/config/i386/next.c @@ -0,0 +1,7 @@ +/* next.c: Functions for NeXT as target machine for GNU C compiler. */ + +/* Note that the include below means that we can't debug routines in + i386.c when running on a COFF system. */ + +#include "i386/i386.c" +#include "nextstep.c" diff --git a/contrib/gcc/config/i386/next.h b/contrib/gcc/config/i386/next.h new file mode 100644 index 0000000..c0d6d72 --- /dev/null +++ b/contrib/gcc/config/i386/next.h @@ -0,0 +1,226 @@ +/* Target definitions for GNU compiler for Intel x86 CPU running NeXTSTEP + Copyright (C) 1993, 1995 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "i386/gas.h" +#include "nextstep.h" + +/* By default, target has a 80387, with IEEE FP. */ + +#undef TARGET_DEFAULT +#define TARGET_DEFAULT (1|0100) + +/* Implicit library calls should use memcpy, not bcopy, etc. */ + +#define TARGET_MEM_FUNCTIONS + +/* Machines that use the AT&T assembler syntax + also return floating point values in an FP register. + Define how to find the value returned by a function. + VALTYPE is the data type of the value (as a tree). + If the precise function being called is known, FUNC is its FUNCTION_DECL; + otherwise, FUNC is 0. */ + +#undef VALUE_REGNO +#define VALUE_REGNO(MODE) \ + ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ + ? FIRST_FLOAT_REG : 0) + +/* 1 if N is a possible register number for a function value. */ + +#undef FUNCTION_VALUE_REGNO_P +#define FUNCTION_VALUE_REGNO_P(N) ((N) == 0 || (N)== FIRST_FLOAT_REG) + +#ifdef REAL_VALUE_TO_TARGET_LONG_DOUBLE +#undef ASM_OUTPUT_LONG_DOUBLE +#define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ + do { \ + long hex[3]; \ + REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, hex); \ + if (sizeof (int) == sizeof (long)) \ + fprintf (FILE, "\t.long 0x%x\n\t.long 0x%x\n\t.long 0x%x\n", \ + hex[0], hex[1], hex[2]); \ + else \ + fprintf (FILE, "\t.long 0x%lx\n\t.long 0x%lx\n\t.long 0x%lx\n", \ + hex[0], hex[1], hex[2]); \ + } while (0) +#endif + +#ifdef REAL_VALUE_TO_TARGET_DOUBLE +#undef ASM_OUTPUT_DOUBLE +#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ + do { \ + long hex[2]; \ + REAL_VALUE_TO_TARGET_DOUBLE (VALUE, hex); \ + if (sizeof (int) == sizeof (long)) \ + fprintf (FILE, "\t.long 0x%x\n\t.long 0x%x\n", hex[0], hex[1]); \ + else \ + fprintf (FILE, "\t.long 0x%lx\n\t.long 0x%lx\n", hex[0], hex[1]); \ + } while (0) +#endif + +/* This is how to output an assembler line defining a `float' constant. */ + +#ifdef REAL_VALUE_TO_TARGET_SINGLE +#undef ASM_OUTPUT_FLOAT +#define ASM_OUTPUT_FLOAT(FILE,VALUE) \ + do { \ + long hex; \ + REAL_VALUE_TO_TARGET_SINGLE (VALUE, hex); \ + if (sizeof (int) == sizeof (long)) \ + fprintf (FILE, "\t.long 0x%x\n", hex); \ + else \ + fprintf (FILE, "\t.long 0x%lx\n", hex); \ + } while (0) +#endif + +/* A C statement or statements which output an assembler instruction + opcode to the stdio stream STREAM. The macro-operand PTR is a + variable of type `char *' which points to the opcode name in its + "internal" form--the form that is written in the machine description. + + GAS version 1.38.1 doesn't understand the `repz' opcode mnemonic. + So use `repe' instead. */ + +#undef ASM_OUTPUT_OPCODE +#define ASM_OUTPUT_OPCODE(STREAM, PTR) \ +{ \ + if ((PTR)[0] == 'r' \ + && (PTR)[1] == 'e' \ + && (PTR)[2] == 'p') \ + { \ + if ((PTR)[3] == 'z') \ + { \ + fprintf (STREAM, "repe"); \ + (PTR) += 4; \ + } \ + else if ((PTR)[3] == 'n' && (PTR)[4] == 'z') \ + { \ + fprintf (STREAM, "repne"); \ + (PTR) += 5; \ + } \ + } \ +} + +/* Define macro used to output shift-double opcodes when the shift + count is in %cl. Some assemblers require %cl as an argument; + some don't. + + GAS requires the %cl argument, so override unx386.h. */ + +#undef AS3_SHIFT_DOUBLE +#define AS3_SHIFT_DOUBLE(a,b,c,d) AS3 (a,b,c,d) + +/* Print opcodes the way that GAS expects them. */ +#define GAS_MNEMONICS 1 + +/* Names to predefine in the preprocessor for this target machine. */ + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Di386 -DNeXT -Dunix -D__MACH__ -D__LITTLE_ENDIAN__ -D__ARCHITECTURE__=\"i386\" -Asystem(unix) -Asystem(mach) -Acpu(i386) -Amachine(i386)" + +/* This accounts for the return pc and saved fp on the i386. */ + +#define OBJC_FORWARDING_STACK_OFFSET 8 +#define OBJC_FORWARDING_MIN_OFFSET 8 + +/* We do not want a dot in internal labels. */ + +#undef LPREFIX +#define LPREFIX "L" + +#undef ASM_GENERATE_INTERNAL_LABEL +#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ + sprintf ((BUF), "*%s%d", (PREFIX), (NUMBER)) + +#undef ASM_OUTPUT_INTERNAL_LABEL +#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ + fprintf (FILE, "%s%d:\n", PREFIX, NUM) + +/* Output to assembler file text saying following lines + may contain character constants, extra white space, comments, etc. */ + +#undef ASM_APP_ON +#define ASM_APP_ON "#APP\n" + +/* Output to assembler file text saying following lines + no longer contain unusual constructs. */ + +#undef ASM_APP_OFF +#define ASM_APP_OFF "#NO_APP\n" + +#undef ASM_OUTPUT_REG_PUSH +#define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ + fprintf (FILE, "\tpushl %se%s\n", "%", reg_names[REGNO]) + +#undef ASM_OUTPUT_REG_POP +#define ASM_OUTPUT_REG_POP(FILE,REGNO) \ + fprintf (FILE, "\tpopl %se%s\n", "%", reg_names[REGNO]) + +/* This is being overridden because the default i386 configuration + generates calls to "_mcount". NeXT system libraries all use + "mcount". */ + +#undef FUNCTION_PROFILER +#define FUNCTION_PROFILER(FILE, LABELNO) \ +{ \ + if (flag_pic) \ + { \ + fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n", \ + LPREFIX, (LABELNO)); \ + fprintf (FILE, "\tcall *mcount@GOT(%%ebx)\n"); \ + } \ + else \ + { \ + fprintf (FILE, "\tmovl $%sP%d,%%edx\n", LPREFIX, (LABELNO)); \ + fprintf (FILE, "\tcall mcount\n"); \ + } \ +} + +/* BEGIN Calling Convention CHANGES */ + +/* These changes violate the Intel/Unix ABI. Specifically, they + change the way that space for a block return value is passed to a + function. The ABI says that the pointer is passed on the stack. + We change to pass the pointer in %ebx. This makes the NeXT + Objective-C forwarding mechanism possible to implement on an i386. */ + +/* Do NOT pass address of structure values on the stack. */ + +#undef STRUCT_VALUE_INCOMING +#undef STRUCT_VALUE + +/* Pass them in %ebx. */ + +#undef STRUCT_VALUE_REGNUM +#define STRUCT_VALUE_REGNUM 3 + +/* Because we are passing the pointer in a register, we don't need to + rely on the callee to pop it. */ + +#undef RETURN_POPS_ARGS +#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \ + (TREE_CODE (FUNTYPE) == IDENTIFIER_NODE \ + ? 0 \ + : (TARGET_RTD \ + && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ + || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ + == void_type_node))) ? (SIZE) : 0) + +/* END Calling Convention CHANGES */ diff --git a/contrib/gcc/config/i386/os2.h b/contrib/gcc/config/i386/os2.h new file mode 100644 index 0000000..8bbab36 --- /dev/null +++ b/contrib/gcc/config/i386/os2.h @@ -0,0 +1,76 @@ +/* Definitions of target machine for GNU compiler + for an Intel i386 or later processor running OS/2 2.x. + Copyright (C) 1993, 1994, 1995 Free Software Foundation, Inc. + Contributed by Samuel Figueroa (figueroa@cs.nyu.edu) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#ifndef DEFAULT_TARGET_MACHINE +#define DEFAULT_TARGET_MACHINE "i386-os2" +#endif +#ifndef LINK_SPEC +#define LINK_SPEC "/st:1048576/pm:vio/noi/a:16/e/bas:65536/nol" +#endif +#ifndef LIB_SPEC +#define LIB_SPEC "libgcc libc" +#endif +#ifndef STARTFILE_SPEC +#define STARTFILE_SPEC "libcrt.lib" +#endif +#ifndef MD_EXEC_PREFIX +#define MD_EXEC_PREFIX "\\gcc\\bin\\" +#endif +#ifndef STANDARD_STARTFILE_PREFIX +#define STANDARD_STARTFILE_PREFIX "\\gcc\\lib\\" +#endif +#ifndef LOCAL_INCLUDE_DIR +#define LOCAL_INCLUDE_DIR "\\gcc\\include" +#endif + +#define YES_UNDERSCORES +#include "i386/gstabs.h" + +#define USE_COLLECT + +#define BIGGEST_FIELD_ALIGNMENT \ + (maximum_field_alignment ? maximum_field_alignment : 32) + +extern int maximum_field_alignment; + +#undef PCC_BITFIELD_TYPE_MATTERS +#define PCC_BITFIELD_TYPE_MATTERS (maximum_field_alignment == 0) + +/* Define this macro if it is advisable to hold scalars in registers + in a wider mode than that declared by the program. In such cases, + the value is constrained to be within the bounds of the declared + type, but kept valid in the wider mode. The signedness of the + extension may differ from that of the type. */ + +#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ + if (GET_MODE_CLASS (MODE) == MODE_INT \ + && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ + (MODE) = SImode; + +/* Define this if function arguments should also be promoted using the above + procedure. */ + +#define PROMOTE_FUNCTION_ARGS + +/* Likewise, if the function return value is promoted. */ + +#define PROMOTE_FUNCTION_RETURN diff --git a/contrib/gcc/config/i386/osfelf.h b/contrib/gcc/config/i386/osfelf.h new file mode 100644 index 0000000..7e71fe9 --- /dev/null +++ b/contrib/gcc/config/i386/osfelf.h @@ -0,0 +1,79 @@ +/* Definitions of target machine for GNU compiler. + Intel 386 (OSF/1 with ELF) version. + Copyright (C) 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "config/i386/osfrose.h" + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-DOSF -DOSF1 -Dunix -Di386 -Asystem(unix) -Asystem(xpg4) -Acpu(i386) -Amachine(i386)" + +#undef CPP_SPEC +#define CPP_SPEC "\ +%{mrose: -D__ROSE__ %{!pic-none: -D__SHARED__}} \ +%{!mrose: -D__ELF__ %{fpic: -D__SHARED__}} \ +%{mno-underscores: -D__NO_UNDERSCORES__} \ +%{!mrose: %{!munderscores: -D__NO_UNDERSCORES__}} \ +%{.S: %{!ansi:%{!traditional:%{!traditional-cpp:%{!ftraditional: -traditional}}}}} \ +%{.S: -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \ +%{.cc: -D__LANGUAGE_C_PLUS_PLUS} \ +%{.cxx: -D__LANGUAGE_C_PLUS_PLUS} \ +%{.C: -D__LANGUAGE_C_PLUS_PLUS} \ +%{.m: -D__LANGUAGE_OBJECTIVE_C} \ +%{!.S: -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C}}" + +/* Turn on -pic-extern by default for OSF/rose, -fpic for ELF. */ +#undef CC1_SPEC +#define CC1_SPEC "\ +%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \ +%{!melf: %{!mrose: -melf }} \ +%{!mrose: %{!munderscores: %{!mno-underscores: -mno-underscores }} \ + %{!mmcount: %{!mno-mcount: %{!mmcount-ptr: -mmcount-ptr }}}} \ +%{mrose: %{!mmcount: %{!mno-mcount: %{!mmcount-ptr: -mmcount }}} \ + %{pic-extern: -mhalf-pic } %{pic-lib: -mhalf-pic } \ + %{!pic-extern: %{!pic-lib: %{pic-none: -mno-half-pic} %{!pic-none: -mhalf-pic}}} \ + %{pic-calls: } %{pic-names*: }}" + +#undef ASM_SPEC +#define ASM_SPEC "%{v*: -v}" + +#undef LINK_SPEC +#define LINK_SPEC "%{v*: -v} \ +%{mrose: %{!noshrlib: %{pic-none: -noshrlib} %{!pic-none: -warn_nopic}} \ + %{nostdlib} %{noshrlib} %{glue}} \ +%{!mrose: %{dy} %{dn} %{glue: } \ + %{h*} %{z*} \ + %{static:-dn -Bstatic} \ + %{shared:-G -dy} \ + %{symbolic:-Bsymbolic -G -dy} \ + %{G:-G} \ + %{!dy: %{!dn: %{!static: %{!shared: %{!symbolic: \ + %{noshrlib: -dn } %{pic-none: -dn } \ + %{!noshrlib: %{!pic-none: -dy}}}}}}}}" + +#undef TARGET_VERSION_INTERNAL +#undef TARGET_VERSION + +#undef I386_VERSION +#define I386_VERSION " 80386, ELF objects" + +#define TARGET_VERSION_INTERNAL(STREAM) fputs (I386_VERSION, STREAM) +#define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr) + +#undef OBJECT_FORMAT_ROSE diff --git a/contrib/gcc/config/i386/osfrose.h b/contrib/gcc/config/i386/osfrose.h new file mode 100644 index 0000000..3aae1e1 --- /dev/null +++ b/contrib/gcc/config/i386/osfrose.h @@ -0,0 +1,923 @@ +/* Definitions of target machine for GNU compiler. + Intel 386 (OSF/1 with OSF/rose) version. + Copyright (C) 1991, 1992, 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "halfpic.h" +#include "i386/gstabs.h" + +/* Get perform_* macros to build libgcc.a. */ +#include "i386/perform.h" + +#define OSF_OS + +#undef WORD_SWITCH_TAKES_ARG +#define WORD_SWITCH_TAKES_ARG(STR) \ + (DEFAULT_WORD_SWITCH_TAKES_ARG (STR) || !strcmp (STR, "pic-names")) + +/* This defines which switch letters take arguments. On svr4, most of + the normal cases (defined in gcc.c) apply, and we also have -h* and + -z* options (for the linker). */ + +#define SWITCH_TAKES_ARG(CHAR) \ + ( (CHAR) == 'D' \ + || (CHAR) == 'U' \ + || (CHAR) == 'o' \ + || (CHAR) == 'e' \ + || (CHAR) == 'T' \ + || (CHAR) == 'u' \ + || (CHAR) == 'I' \ + || (CHAR) == 'm' \ + || (CHAR) == 'L' \ + || (CHAR) == 'A' \ + || (CHAR) == 'h' \ + || (CHAR) == 'z') + +#define MASK_HALF_PIC 010000000000 /* Mask for half-pic code */ +#define MASK_HALF_PIC_DEBUG 004000000000 /* Debug flag */ +#define MASK_ELF 002000000000 /* ELF not rose */ +#define MASK_NO_IDENT 001000000000 /* suppress .ident */ +#define MASK_NO_UNDERSCORES 000400000000 /* suppress leading _ */ +#define MASK_LARGE_ALIGN 000200000000 /* align to >word boundaries */ +#define MASK_NO_MCOUNT 000100000000 /* profiling uses mcount_ptr */ + +#define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC) +#define TARGET_DEBUG (target_flags & MASK_HALF_PIC_DEBUG) +#define HALF_PIC_DEBUG TARGET_DEBUG +#define TARGET_ELF (target_flags & MASK_ELF) +#define TARGET_ROSE ((target_flags & MASK_ELF) == 0) +#define TARGET_IDENT ((target_flags & MASK_NO_IDENT) == 0) +#define TARGET_UNDERSCORES ((target_flags & MASK_NO_UNDERSCORES) == 0) +#define TARGET_LARGE_ALIGN (target_flags & MASK_LARGE_ALIGN) +#define TARGET_MCOUNT ((target_flags & MASK_NO_MCOUNT) == 0) + +#undef SUBTARGET_SWITCHES +#define SUBTARGET_SWITCHES \ + { "half-pic", MASK_HALF_PIC}, \ + { "no-half-pic", -MASK_HALF_PIC}, \ + { "debug-half-pic", MASK_HALF_PIC_DEBUG}, \ + { "debugb", MASK_HALF_PIC_DEBUG}, \ + { "elf", MASK_ELF}, \ + { "rose", -MASK_ELF}, \ + { "ident", -MASK_NO_IDENT}, \ + { "no-ident", MASK_NO_IDENT}, \ + { "underscores", -MASK_NO_UNDERSCORES}, \ + { "no-underscores", MASK_NO_UNDERSCORES}, \ + { "large-align", MASK_LARGE_ALIGN}, \ + { "no-large-align", -MASK_LARGE_ALIGN}, \ + { "mcount", -MASK_NO_MCOUNT}, \ + { "mcount-ptr", MASK_NO_MCOUNT}, \ + { "no-mcount", MASK_NO_MCOUNT}, + +/* OSF/rose uses stabs, not dwarf. */ +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG + +#ifndef DWARF_DEBUGGING_INFO +#define DWARF_DEBUGGING_INFO /* enable dwarf debugging for testing */ +#endif + +/* Handle #pragma weak and #pragma pack. */ + +#define HANDLE_SYSV_PRAGMA +#define SUPPORTS_WEAK TARGET_ELF + +/* Change default predefines. */ +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-DOSF -DOSF1 -Dunix -Di386 -Asystem(unix) -Asystem(xpg4) -Acpu(i386) -Amachine(i386)" + +#undef CPP_SPEC +#define CPP_SPEC "\ +%{!melf: -D__ROSE__ %{!pic-none: -D__SHARED__}} \ +%{melf: -D__ELF__ %{fpic: -D__SHARED__}} \ +%{mno-underscores: -D__NO_UNDERSCORES__} \ +%{melf: %{!munderscores: -D__NO_UNDERSCORES__}} \ +%{.S: %{!ansi:%{!traditional:%{!traditional-cpp:%{!ftraditional: -traditional}}}}} \ +%{.S: -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \ +%{.cc: -D__LANGUAGE_C_PLUS_PLUS} \ +%{.cxx: -D__LANGUAGE_C_PLUS_PLUS} \ +%{.C: -D__LANGUAGE_C_PLUS_PLUS} \ +%{.m: -D__LANGUAGE_OBJECTIVE_C} \ +%{!.S: -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C}}" + +/* Turn on -pic-extern by default for OSF/rose, -fpic for ELF. */ +#undef CC1_SPEC +#define CC1_SPEC "\ +%{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \ +%{!melf: %{!mrose: -mrose }} \ +%{melf: %{!munderscores: %{!mno-underscores: -mno-underscores }} \ + %{!mmcount: %{!mno-mcount: %{!mmcount-ptr: -mmcount-ptr }}}} \ +%{!melf: %{!munderscores: %{!mno-underscores: -munderscores }} \ + %{!mmcount: %{!mno-mcount: %{!mmcount-ptr: -mmcount }}} \ + %{pic-extern: -mhalf-pic } %{pic-lib: -mhalf-pic } \ + %{!pic-extern: %{!pic-lib: %{pic-none: -mno-half-pic} %{!pic-none: -mhalf-pic}}} \ + %{pic-calls: } %{pic-names*: }}" + +#undef ASM_SPEC +#define ASM_SPEC "%{v*: -v}" + +#undef LINK_SPEC +#define LINK_SPEC "%{v*: -v} \ +%{!melf: %{!noshrlib: %{pic-none: -noshrlib} %{!pic-none: -warn_nopic}} \ + %{nostdlib} %{noshrlib} %{glue}} \ +%{melf: %{dy} %{dn} %{glue: } \ + %{h*} %{z*} \ + %{static:-dn -Bstatic} \ + %{shared:-G -dy} \ + %{symbolic:-Bsymbolic -G -dy} \ + %{G:-G} \ + %{!dy: %{!dn: %{!static: %{!shared: %{!symbolic: \ + %{noshrlib: -dn } %{pic-none: -dn } \ + %{!noshrlib: %{!pic-none: -dy}}}}}}}}" + +#undef LIB_SPEC +#define LIB_SPEC "-lc" + +#undef LIBG_SPEC +#define LIBG_SPEC "" + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}" + +#undef TARGET_VERSION_INTERNAL +#undef TARGET_VERSION + +#define I386_VERSION " 80386, OSF/rose objects" + +#define TARGET_VERSION_INTERNAL(STREAM) fputs (I386_VERSION, STREAM) +#define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr) + +#undef MD_EXEC_PREFIX +#define MD_EXEC_PREFIX "/usr/ccs/gcc/" + +#undef MD_STARTFILE_PREFIX +#define MD_STARTFILE_PREFIX "/usr/ccs/lib/" + +/* Specify size_t, ptrdiff_t, and wchar_t types. */ +#undef SIZE_TYPE +#undef PTRDIFF_TYPE +#undef WCHAR_TYPE +#undef WCHAR_TYPE_SIZE + +#define SIZE_TYPE "long unsigned int" +#define PTRDIFF_TYPE "int" +#define WCHAR_TYPE "unsigned int" +#define WCHAR_TYPE_SIZE BITS_PER_WORD + +/* Define this macro if the system header files support C++ as well + as C. This macro inhibits the usual method of using system header + files in C++, which is to pretend that the file's contents are + enclosed in `extern "C" {...}'. */ +#define NO_IMPLICIT_EXTERN_C + +/* Turn off long double being 96 bits. */ +#undef LONG_DOUBLE_TYPE_SIZE +#define LONG_DOUBLE_TYPE_SIZE 64 + +/* This macro generates the assembly code for function entry. + FILE is a stdio stream to output the code to. + SIZE is an int: how many units of temporary storage to allocate. + Refer to the array `regs_ever_live' to determine which registers + to save; `regs_ever_live[I]' is nonzero if register number I + is ever used in the function. This macro is responsible for + knowing which registers should not be saved even if used. + + We override it here to allow for the new profiling code to go before + the prologue and the old mcount code to go after the prologue (and + after %ebx has been set up for ELF shared library support). */ + +#define OSF_PROFILE_BEFORE_PROLOGUE \ + (!TARGET_MCOUNT \ + && !current_function_needs_context \ + && (!flag_pic \ + || !frame_pointer_needed \ + || (!current_function_uses_pic_offset_table \ + && !current_function_uses_const_pool))) + +#undef FUNCTION_PROLOGUE +#define FUNCTION_PROLOGUE(FILE, SIZE) \ +do \ + { \ + char *prefix = (TARGET_UNDERSCORES) ? "_" : ""; \ + char *lprefix = LPREFIX; \ + int labelno = profile_label_no; \ + \ + if (profile_flag && OSF_PROFILE_BEFORE_PROLOGUE) \ + { \ + if (!flag_pic && !HALF_PIC_P ()) \ + { \ + fprintf (FILE, "\tmovl $%sP%d,%%edx\n", lprefix, labelno); \ + fprintf (FILE, "\tcall *%s_mcount_ptr\n", prefix); \ + } \ + \ + else if (HALF_PIC_P ()) \ + { \ + rtx symref; \ + \ + HALF_PIC_EXTERNAL ("_mcount_ptr"); \ + symref = HALF_PIC_PTR (gen_rtx (SYMBOL_REF, Pmode, \ + "_mcount_ptr")); \ + \ + fprintf (FILE, "\tmovl $%sP%d,%%edx\n", lprefix, labelno); \ + fprintf (FILE, "\tmovl %s%s,%%eax\n", prefix, \ + XSTR (symref, 0)); \ + fprintf (FILE, "\tcall *(%%eax)\n"); \ + } \ + \ + else \ + { \ + static int call_no = 0; \ + \ + fprintf (FILE, "\tcall %sPc%d\n", lprefix, call_no); \ + fprintf (FILE, "%sPc%d:\tpopl %%eax\n", lprefix, call_no); \ + fprintf (FILE, "\taddl $_GLOBAL_OFFSET_TABLE_+[.-%sPc%d],%%eax\n", \ + lprefix, call_no++); \ + fprintf (FILE, "\tleal %sP%d@GOTOFF(%%eax),%%edx\n", \ + lprefix, labelno); \ + fprintf (FILE, "\tmovl %s_mcount_ptr@GOT(%%eax),%%eax\n", \ + prefix); \ + fprintf (FILE, "\tcall *(%%eax)\n"); \ + } \ + } \ + \ + function_prologue (FILE, SIZE); \ + } \ +while (0) + +/* A C statement or compound statement to output to FILE some assembler code to + call the profiling subroutine `mcount'. Before calling, the assembler code + must load the address of a counter variable into a register where `mcount' + expects to find the address. The name of this variable is `LP' followed by + the number LABELNO, so you would generate the name using `LP%d' in a + `fprintf'. + + The details of how the address should be passed to `mcount' are determined + by your operating system environment, not by GNU CC. To figure them out, + compile a small program for profiling using the system's installed C + compiler and look at the assembler code that results. */ + +#undef FUNCTION_PROFILER +#define FUNCTION_PROFILER(FILE, LABELNO) \ +do \ + { \ + if (!OSF_PROFILE_BEFORE_PROLOGUE) \ + { \ + char *prefix = (TARGET_UNDERSCORES) ? "_" : ""; \ + char *lprefix = LPREFIX; \ + int labelno = LABELNO; \ + \ + /* Note that OSF/rose blew it in terms of calling mcount, \ + since OSF/rose prepends a leading underscore, but mcount's \ + doesn't. At present, we keep this kludge for ELF as well \ + to allow old kernels to build profiling. */ \ + \ + if (flag_pic \ + && !current_function_uses_pic_offset_table \ + && !current_function_uses_const_pool) \ + abort (); \ + \ + if (TARGET_MCOUNT && flag_pic) \ + { \ + fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n", \ + lprefix, labelno); \ + fprintf (FILE, "\tcall *%smcount@GOT(%%ebx)\n", prefix); \ + } \ + \ + else if (TARGET_MCOUNT && HALF_PIC_P ()) \ + { \ + rtx symdef; \ + \ + HALF_PIC_EXTERNAL ("mcount"); \ + symdef = HALF_PIC_PTR (gen_rtx (SYMBOL_REF, Pmode, "mcount")); \ + fprintf (FILE, "\tmovl $%sP%d,%%edx\n", lprefix, labelno); \ + fprintf (FILE, "\tcall *%s%s\n", prefix, XSTR (symdef, 0)); \ + } \ + \ + else if (TARGET_MCOUNT) \ + { \ + fprintf (FILE, "\tmovl $%sP%d,%%edx\n", lprefix, labelno); \ + fprintf (FILE, "\tcall %smcount\n", prefix); \ + } \ + \ + else if (flag_pic && frame_pointer_needed) \ + { \ + fprintf (FILE, "\tmovl 4(%%ebp),%%ecx\n"); \ + fprintf (FILE, "\tpushl %%ecx\n"); \ + fprintf (FILE, "\tleal %sP%d@GOTOFF(%%ebx),%%edx\n", \ + lprefix, labelno); \ + fprintf (FILE, "\tmovl _mcount_ptr@GOT(%%ebx),%%eax\n"); \ + fprintf (FILE, "\tcall *(%%eax)\n"); \ + fprintf (FILE, "\tpopl %%eax\n"); \ + } \ + \ + else if (frame_pointer_needed) \ + { \ + fprintf (FILE, "\tmovl 4(%%ebp),%%ecx\n"); \ + fprintf (FILE, "\tpushl %%ecx\n"); \ + fprintf (FILE, "\tmovl $%sP%d,%%edx\n", lprefix, labelno); \ + fprintf (FILE, "\tcall *_mcount_ptr\n"); \ + fprintf (FILE, "\tpopl %%eax\n"); \ + } \ + \ + else \ + abort (); \ + } \ + } \ +while (0) + +/* A C function or functions which are needed in the library to + support block profiling. When support goes into libc, undo + the #if 0. */ + +#if 0 +#undef BLOCK_PROFILING_CODE +#define BLOCK_PROFILING_CODE +#endif + +/* Prefix for internally generated assembler labels. If we aren't using + underscores, we are using prefix `.'s to identify labels that should + be ignored, as in `i386/gas.h' --karl@cs.umb.edu */ +#undef LPREFIX +#define LPREFIX ((TARGET_UNDERSCORES) ? "L" : ".L") + +/* This is how to store into the string BUF + the symbol_ref name of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. + This is suitable for output with `assemble_name'. */ + +#undef ASM_GENERATE_INTERNAL_LABEL +#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ + sprintf ((BUF), "*%s%s%d", (TARGET_UNDERSCORES) ? "" : ".", \ + (PREFIX), (NUMBER)) + +/* This is how to output an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. */ + +#undef ASM_OUTPUT_INTERNAL_LABEL +#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ + fprintf (FILE, "%s%s%d:\n", (TARGET_UNDERSCORES) ? "" : ".", \ + PREFIX, NUM) + +/* This is how to output a reference to a user-level label named NAME. */ + +#undef ASM_OUTPUT_LABELREF +#define ASM_OUTPUT_LABELREF(FILE,NAME) \ + fprintf (FILE, "%s%s", (TARGET_UNDERSCORES) ? "_" : "", NAME) + +/* This is how to output an element of a case-vector that is relative. + This is only used for PIC code. See comments by the `casesi' insn in + i386.md for an explanation of the expression this outputs. */ + +#undef ASM_OUTPUT_ADDR_DIFF_ELT +#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ + fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE) + +/* Output a definition */ +#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2) \ +do \ +{ \ + fprintf ((FILE), "\t%s\t", SET_ASM_OP); \ + assemble_name (FILE, LABEL1); \ + fprintf (FILE, ","); \ + assemble_name (FILE, LABEL2); \ + fprintf (FILE, "\n"); \ + } \ +while (0) + +/* A C expression to output text to align the location counter in the + way that is desirable at a point in the code that is reached only + by jumping. + + This macro need not be defined if you don't want any special + alignment to be done at such a time. Most machine descriptions do + not currently define the macro. */ + +#undef ASM_OUTPUT_ALIGN_CODE +#define ASM_OUTPUT_ALIGN_CODE(STREAM) \ + fprintf (STREAM, "\t.align\t%d\n", \ + (!TARGET_LARGE_ALIGN && i386_align_jumps > 2) ? 2 : i386_align_jumps) + +/* A C expression to output text to align the location counter in the + way that is desirable at the beginning of a loop. + + This macro need not be defined if you don't want any special + alignment to be done at such a time. Most machine descriptions do + not currently define the macro. */ + +#undef ASM_OUTPUT_LOOP_ALIGN +#define ASM_OUTPUT_LOOP_ALIGN(STREAM) \ + fprintf (STREAM, "\t.align\t%d\n", i386_align_loops) + +/* A C statement to output to the stdio stream STREAM an assembler + command to advance the location counter to a multiple of 2 to the + POWER bytes. POWER will be a C expression of type `int'. */ + +#undef ASM_OUTPUT_ALIGN +#define ASM_OUTPUT_ALIGN(STREAM, POWER) \ + fprintf (STREAM, "\t.align\t%d\n", \ + (!TARGET_LARGE_ALIGN && (POWER) > 2) ? 2 : (POWER)) + +/* A C expression that is 1 if the RTX X is a constant which is a + valid address. On most machines, this can be defined as + `CONSTANT_P (X)', but a few machines are more restrictive in + which constant addresses are supported. + + `CONSTANT_P' accepts integer-values expressions whose values are + not explicitly known, such as `symbol_ref', `label_ref', and + `high' expressions and `const' arithmetic expressions, in + addition to `const_int' and `const_double' expressions. */ + +#define CONSTANT_ADDRESS_P_ORIG(X) \ + (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ + || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ + || GET_CODE (X) == HIGH) + +#undef CONSTANT_ADDRESS_P +#define CONSTANT_ADDRESS_P(X) \ + ((CONSTANT_ADDRESS_P_ORIG (X)) && (!HALF_PIC_P () || !HALF_PIC_ADDRESS_P (X))) + +/* Nonzero if the constant value X is a legitimate general operand. + It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ + +#undef LEGITIMATE_CONSTANT_P +#define LEGITIMATE_CONSTANT_P(X) \ + (!HALF_PIC_P () \ + || GET_CODE (X) == CONST_DOUBLE \ + || GET_CODE (X) == CONST_INT \ + || !HALF_PIC_ADDRESS_P (X)) + +/* Sometimes certain combinations of command options do not make sense + on a particular target machine. You can define a macro + `OVERRIDE_OPTIONS' to take account of this. This macro, if + defined, is executed once just after all the command options have + been parsed. */ + +#undef SUBTARGET_OVERRIDE_OPTIONS +#define SUBTARGET_OVERRIDE_OPTIONS \ +{ \ + /* \ + if (TARGET_ELF && TARGET_HALF_PIC) \ + { \ + target_flags &= ~MASK_HALF_PIC; \ + flag_pic = 1; \ + } \ + */ \ + \ + if (TARGET_ROSE && flag_pic) \ + { \ + target_flags |= MASK_HALF_PIC; \ + flag_pic = 0; \ + } \ + \ + if (TARGET_HALF_PIC) \ + half_pic_init (); \ +} + +/* Define this macro if references to a symbol must be treated + differently depending on something about the variable or + function named by the symbol (such as what section it is in). + + The macro definition, if any, is executed immediately after the + rtl for DECL has been created and stored in `DECL_RTL (DECL)'. + The value of the rtl will be a `mem' whose address is a + `symbol_ref'. + + The usual thing for this macro to do is to a flag in the + `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified + name string in the `symbol_ref' (if one bit is not enough + information). + + The best way to modify the name string is by adding text to the + beginning, with suitable punctuation to prevent any ambiguity. + Allocate the new name in `saveable_obstack'. You will have to + modify `ASM_OUTPUT_LABELREF' to remove and decode the added text + and output the name accordingly. + + You can also check the information stored in the `symbol_ref' in + the definition of `GO_IF_LEGITIMATE_ADDRESS' or + `PRINT_OPERAND_ADDRESS'. */ + +#undef ENCODE_SECTION_INFO +#define ENCODE_SECTION_INFO(DECL) \ +do \ + { \ + if (HALF_PIC_P ()) \ + HALF_PIC_ENCODE (DECL); \ + \ + else if (flag_pic) \ + { \ + rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ + ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \ + SYMBOL_REF_FLAG (XEXP (rtl, 0)) \ + = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ + || ! TREE_PUBLIC (DECL)); \ + } \ + } \ +while (0) + + +/* On most machines, read-only variables, constants, and jump tables + are placed in the text section. If this is not the case on your + machine, this macro should be defined to be the name of a function + (either `data_section' or a function defined in `EXTRA_SECTIONS') + that switches to the section to be used for read-only items. + + If these items should be placed in the text section, this macro + should not be defined. */ + +#if 0 +#undef READONLY_DATA_SECTION +#define READONLY_DATA_SECTION() \ +do \ + { \ + if (TARGET_ELF) \ + { \ + if (in_section != in_rodata) \ + { \ + fprintf (asm_out_file, "\t.section \"rodata\"\n"); \ + in_section = in_rodata; \ + } \ + } \ + else \ + text_section (); \ + } \ +while (0) +#endif + +/* A list of names for sections other than the standard two, which are + `in_text' and `in_data'. You need not define this macro on a + system with no other sections (that GCC needs to use). */ + +#undef EXTRA_SECTIONS +#define EXTRA_SECTIONS in_rodata, in_data1 + +/* Given a decl node or constant node, choose the section to output it in + and select that section. */ + +#undef SELECT_RTX_SECTION +#define SELECT_RTX_SECTION(MODE, RTX) \ +do \ + { \ + if (MODE == Pmode && HALF_PIC_P () && HALF_PIC_ADDRESS_P (RTX)) \ + data_section (); \ + else \ + readonly_data_section (); \ + } \ +while (0) + +#undef SELECT_SECTION +#define SELECT_SECTION(DECL, RELOC) \ +{ \ + if (RELOC && HALF_PIC_P ()) \ + data_section (); \ + \ + else if (TREE_CODE (DECL) == STRING_CST) \ + { \ + if (flag_writable_strings) \ + data_section (); \ + else \ + readonly_data_section (); \ + } \ + \ + else if (TREE_CODE (DECL) != VAR_DECL) \ + readonly_data_section (); \ + \ + else if (!TREE_READONLY (DECL) || TREE_SIDE_EFFECTS (DECL) \ + || !DECL_INITIAL (DECL) \ + || (DECL_INITIAL (DECL) != error_mark_node \ + && !TREE_CONSTANT (DECL_INITIAL (DECL)))) \ + data_section (); \ + \ + else \ + readonly_data_section (); \ +} + + +/* Define the strings used for the special svr4 .type and .size directives. + These strings generally do not vary from one system running svr4 to + another, but if a given system (e.g. m88k running svr) needs to use + different pseudo-op names for these, they may be overridden in the + file which includes this one. */ + +#define TYPE_ASM_OP ".type" +#define SIZE_ASM_OP ".size" +#define SET_ASM_OP ".set" + +/* This is how we tell the assembler that a symbol is weak. */ + +#define ASM_WEAKEN_LABEL(FILE,NAME) \ + do { fputs ("\t.weak\t", FILE); assemble_name (FILE, NAME); \ + fputc ('\n', FILE); } while (0) + +/* The following macro defines the format used to output the second + operand of the .type assembler directive. Different svr4 assemblers + expect various different forms for this operand. The one given here + is just a default. You may need to override it in your machine- + specific tm.h file (depending upon the particulars of your assembler). */ + +#define TYPE_OPERAND_FMT "@%s" + +/* A C statement (sans semicolon) to output to the stdio stream + STREAM any text necessary for declaring the name NAME of an + initialized variable which is being defined. This macro must + output the label definition (perhaps using `ASM_OUTPUT_LABEL'). + The argument DECL is the `VAR_DECL' tree node representing the + variable. + + If this macro is not defined, then the variable name is defined + in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */ + +#undef ASM_DECLARE_OBJECT_NAME +#define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \ +do \ + { \ + ASM_OUTPUT_LABEL(STREAM,NAME); \ + HALF_PIC_DECLARE (NAME); \ + if (TARGET_ELF) \ + { \ + fprintf (STREAM, "\t%s\t ", TYPE_ASM_OP); \ + assemble_name (STREAM, NAME); \ + putc (',', STREAM); \ + fprintf (STREAM, TYPE_OPERAND_FMT, "object"); \ + putc ('\n', STREAM); \ + size_directive_output = 0; \ + if (!flag_inhibit_size_directive && DECL_SIZE (DECL)) \ + { \ + size_directive_output = 1; \ + fprintf (STREAM, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (STREAM, NAME); \ + fprintf (STREAM, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ + } \ + } \ + } \ +while (0) + +/* Output the size directive for a decl in rest_of_decl_compilation + in the case where we did not do so before the initializer. + Once we find the error_mark_node, we know that the value of + size_directive_output was set + by ASM_DECLARE_OBJECT_NAME when it was run for the same decl. */ + +#define ASM_FINISH_DECLARE_OBJECT(FILE, DECL, TOP_LEVEL, AT_END) \ +do { \ + char *name = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ + if (TARGET_ELF \ + && !flag_inhibit_size_directive && DECL_SIZE (DECL) \ + && ! AT_END && TOP_LEVEL \ + && DECL_INITIAL (DECL) == error_mark_node \ + && !size_directive_output) \ + { \ + fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (FILE, name); \ + fprintf (FILE, ",%d\n", int_size_in_bytes (TREE_TYPE (DECL))); \ + } \ + } while (0) + +/* This is how to declare a function name. */ + +#undef ASM_DECLARE_FUNCTION_NAME +#define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \ +do \ + { \ + ASM_OUTPUT_LABEL(STREAM,NAME); \ + HALF_PIC_DECLARE (NAME); \ + if (TARGET_ELF) \ + { \ + fprintf (STREAM, "\t%s\t ", TYPE_ASM_OP); \ + assemble_name (STREAM, NAME); \ + putc (',', STREAM); \ + fprintf (STREAM, TYPE_OPERAND_FMT, "function"); \ + putc ('\n', STREAM); \ + ASM_DECLARE_RESULT (STREAM, DECL_RESULT (DECL)); \ + } \ + } \ +while (0) + +/* Write the extra assembler code needed to declare a function's result. + Most svr4 assemblers don't require any special declaration of the + result value, but there are exceptions. */ + +#ifndef ASM_DECLARE_RESULT +#define ASM_DECLARE_RESULT(FILE, RESULT) +#endif + +/* This is how to declare the size of a function. */ + +#define ASM_DECLARE_FUNCTION_SIZE(FILE, FNAME, DECL) \ +do \ + { \ + if (TARGET_ELF && !flag_inhibit_size_directive) \ + { \ + char label[256]; \ + static int labelno; \ + labelno++; \ + ASM_GENERATE_INTERNAL_LABEL (label, "Lfe", labelno); \ + ASM_OUTPUT_INTERNAL_LABEL (FILE, "Lfe", labelno); \ + fprintf (FILE, "\t%s\t ", SIZE_ASM_OP); \ + assemble_name (FILE, (FNAME)); \ + fprintf (FILE, ","); \ + assemble_name (FILE, label); \ + fprintf (FILE, "-"); \ + assemble_name (FILE, (FNAME)); \ + putc ('\n', FILE); \ + } \ + } \ +while (0) + +/* Attach a special .ident directive to the end of the file to identify + the version of GCC which compiled this code. The format of the + .ident string is patterned after the ones produced by native svr4 + C compilers. */ + +#define IDENT_ASM_OP ".ident" + +/* Allow #sccs in preprocessor. */ + +#define SCCS_DIRECTIVE + +/* This says what to print at the end of the assembly file */ +#define ASM_FILE_END(STREAM) \ +do \ + { \ + if (HALF_PIC_P ()) \ + HALF_PIC_FINISH (STREAM); \ + \ + if (TARGET_IDENT) \ + { \ + char *fstart = main_input_filename; \ + char *fname; \ + \ + if (!fstart) \ + fstart = "<no file>"; \ + \ + fname = fstart + strlen (fstart) - 1; \ + while (fname > fstart && *fname != '/') \ + fname--; \ + \ + if (*fname == '/') \ + fname++; \ + \ + fprintf ((STREAM), "\t%s\t\"GCC: (GNU) %s %s -O%d", \ + IDENT_ASM_OP, version_string, fname, optimize); \ + \ + if (write_symbols == PREFERRED_DEBUGGING_TYPE) \ + fprintf ((STREAM), " -g%d", (int)debug_info_level); \ + \ + else if (write_symbols == DBX_DEBUG) \ + fprintf ((STREAM), " -gstabs%d", (int)debug_info_level); \ + \ + else if (write_symbols == DWARF_DEBUG) \ + fprintf ((STREAM), " -gdwarf%d", (int)debug_info_level); \ + \ + else if (write_symbols != NO_DEBUG) \ + fprintf ((STREAM), " -g??%d", (int)debug_info_level); \ + \ + if (flag_omit_frame_pointer) \ + fprintf ((STREAM), " -fomit-frame-pointer"); \ + \ + if (flag_strength_reduce) \ + fprintf ((STREAM), " -fstrength-reduce"); \ + \ + if (flag_unroll_loops) \ + fprintf ((STREAM), " -funroll-loops"); \ + \ + if (flag_schedule_insns) \ + fprintf ((STREAM), " -fschedule-insns"); \ + \ + if (flag_schedule_insns_after_reload) \ + fprintf ((STREAM), " -fschedule-insns2"); \ + \ + if (flag_force_mem) \ + fprintf ((STREAM), " -fforce-mem"); \ + \ + if (flag_force_addr) \ + fprintf ((STREAM), " -fforce-addr"); \ + \ + if (flag_inline_functions) \ + fprintf ((STREAM), " -finline-functions"); \ + \ + if (flag_caller_saves) \ + fprintf ((STREAM), " -fcaller-saves"); \ + \ + if (flag_pic) \ + fprintf ((STREAM), (flag_pic > 1) ? " -fPIC" : " -fpic"); \ + \ + if (flag_inhibit_size_directive) \ + fprintf ((STREAM), " -finhibit-size-directive"); \ + \ + if (flag_gnu_linker) \ + fprintf ((STREAM), " -fgnu-linker"); \ + \ + if (profile_flag) \ + fprintf ((STREAM), " -p"); \ + \ + if (profile_block_flag) \ + fprintf ((STREAM), " -a"); \ + \ + if (TARGET_IEEE_FP) \ + fprintf ((STREAM), " -mieee-fp"); \ + \ + if (TARGET_HALF_PIC) \ + fprintf ((STREAM), " -mhalf-pic"); \ + \ + if (!TARGET_MOVE) \ + fprintf ((STREAM), " -mno-move"); \ + \ + if (TARGET_386) \ + fprintf ((STREAM), " -m386"); \ + \ + else if (TARGET_486) \ + fprintf ((STREAM), " -m486"); \ + \ + else \ + fprintf ((STREAM), " -munknown-machine"); \ + \ + fprintf ((STREAM), (TARGET_ELF) ? " -melf\"\n" : " -mrose\"\n"); \ + } \ + } \ +while (0) + +/* Tell collect that the object format is OSF/rose. */ +#define OBJECT_FORMAT_ROSE + +/* Tell collect where the appropriate binaries are. */ +#define REAL_NM_FILE_NAME "/usr/ccs/gcc/bfd-nm" +#define REAL_STRIP_FILE_NAME "/usr/ccs/bin/strip" + +/* Use atexit for static constructors/destructors, instead of defining + our own exit function. */ +#define HAVE_ATEXIT + +/* Define this macro meaning that gcc should find the library 'libgcc.a' + by hand, rather than passing the argument '-lgcc' to tell the linker + to do the search */ +#define LINK_LIBGCC_SPECIAL + +/* A C statement to output assembler commands which will identify the object + file as having been compile with GNU CC. We don't need or want this for + OSF1. GDB doesn't need it and kdb doesn't like it */ +#define ASM_IDENTIFY_GCC(FILE) + +/* Identify the front-end which produced this file. To keep symbol + space down, and not confuse kdb, only do this if the language is + not C. */ + +#define ASM_IDENTIFY_LANGUAGE(STREAM) \ +{ \ + if (strcmp (lang_identify (), "c") != 0) \ + output_lang_identify (STREAM); \ +} + +/* Generate calls to memcpy, etc., not bcopy, etc. */ +#define TARGET_MEM_FUNCTIONS + +/* Don't default to pcc-struct-return, because gcc is the only compiler, and + we want to retain compatibility with older gcc versions. */ +#define DEFAULT_PCC_STRUCT_RETURN 0 + +/* Map i386 registers to the numbers dwarf expects. Of course this is different + from what stabs expects. */ + +#define DWARF_DBX_REGISTER_NUMBER(n) \ +((n) == 0 ? 0 \ + : (n) == 1 ? 2 \ + : (n) == 2 ? 1 \ + : (n) == 3 ? 3 \ + : (n) == 4 ? 6 \ + : (n) == 5 ? 7 \ + : (n) == 6 ? 5 \ + : (n) == 7 ? 4 \ + : ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) ? (n)+3 \ + : (-1)) + +/* Now what stabs expects in the register. */ +#define STABS_DBX_REGISTER_NUMBER(n) \ +((n) == 0 ? 0 : \ + (n) == 1 ? 2 : \ + (n) == 2 ? 1 : \ + (n) == 3 ? 3 : \ + (n) == 4 ? 6 : \ + (n) == 5 ? 7 : \ + (n) == 6 ? 4 : \ + (n) == 7 ? 5 : \ + (n) + 4) + +#undef DBX_REGISTER_NUMBER +#define DBX_REGISTER_NUMBER(n) ((write_symbols == DWARF_DEBUG) \ + ? DWARF_DBX_REGISTER_NUMBER(n) \ + : STABS_DBX_REGISTER_NUMBER(n)) diff --git a/contrib/gcc/config/i386/perform.h b/contrib/gcc/config/i386/perform.h new file mode 100644 index 0000000..8d6d0b7 --- /dev/null +++ b/contrib/gcc/config/i386/perform.h @@ -0,0 +1,98 @@ +/* Definitions for AT&T assembler syntax for the Intel 80386. + Copyright (C) 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Defines to be able to build libgcc.a with GCC. */ + +/* It might seem that these are not important, since gcc 2 will never + call libgcc for these functions. But programs might be linked with + code compiled by gcc 1, and then these will be used. */ + +/* The arg names used to be a and b, but `a' appears inside strings + and that confuses non-ANSI cpp. */ + +#define perform_udivsi3(arg0,arg1) \ +{ \ + register int dx asm("dx"); \ + register int ax asm("ax"); \ + \ + dx = 0; \ + ax = arg0; \ + asm ("divl %3" : "=a" (ax), "=d" (dx) : "a" (ax), "g" (arg1), "d" (dx)); \ + return ax; \ +} + +#define perform_divsi3(arg0,arg1) \ +{ \ + register int dx asm("dx"); \ + register int ax asm("ax"); \ + register int cx asm("cx"); \ + \ + ax = arg0; \ + cx = arg1; \ + asm ("cltd\n\tidivl %3" : "=a" (ax), "=&d" (dx) : "a" (ax), "c" (cx)); \ + return ax; \ +} + +#define perform_umodsi3(arg0,arg1) \ +{ \ + register int dx asm("dx"); \ + register int ax asm("ax"); \ + \ + dx = 0; \ + ax = arg0; \ + asm ("divl %3" : "=a" (ax), "=d" (dx) : "a" (ax), "g" (arg1), "d" (dx)); \ + return dx; \ +} + +#define perform_modsi3(arg0,arg1) \ +{ \ + register int dx asm("dx"); \ + register int ax asm("ax"); \ + register int cx asm("cx"); \ + \ + ax = arg0; \ + cx = arg1; \ + asm ("cltd\n\tidivl %3" : "=a" (ax), "=&d" (dx) : "a" (ax), "c" (cx)); \ + return dx; \ +} + +#define perform_fixdfsi(arg0) \ +{ \ + auto unsigned short ostatus; \ + auto unsigned short nstatus; \ + auto int ret; \ + auto double tmp; \ + \ + &ostatus; /* guarantee these land in memory */ \ + &nstatus; \ + &ret; \ + &tmp; \ + \ + asm volatile ("fnstcw %0" : "=m" (ostatus)); \ + nstatus = ostatus | 0x0c00; \ + asm volatile ("fldcw %0" : /* no outputs */ : "m" (nstatus)); \ + tmp = arg0; \ + asm volatile ("fldl %0" : /* no outputs */ : "m" (tmp)); \ + asm volatile ("fistpl %0" : "=m" (ret)); \ + asm volatile ("fldcw %0" : /* no outputs */ : "m" (ostatus)); \ + \ + return ret; \ +} + diff --git a/contrib/gcc/config/i386/sco.h b/contrib/gcc/config/i386/sco.h new file mode 100644 index 0000000..37dc032 --- /dev/null +++ b/contrib/gcc/config/i386/sco.h @@ -0,0 +1,117 @@ +/* Definitions for Intel 386 running SCO Unix System V. + Copyright (C) 1988, 1992, 1994, 1995 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* Mostly it's like AT&T Unix System V. */ + +#include "i386/sysv3.h" + +/* By default, target has a 80387, uses IEEE compatible arithmetic, + and returns float values in the 387, ie, + (TARGET_80387 | TARGET_FLOAT_RETURNS_IN_80387) + + SCO's software emulation of a 387 fails to handle the `fucomp' + opcode. fucomp is only used when generating IEEE compliant code. + So don't make TARGET_IEEE_FP default for SCO. */ + +#undef TARGET_DEFAULT +#define TARGET_DEFAULT 0201 + +/* Let's guess that the SCO software FPU emulator can't handle + 80-bit XFmode insns, so don't generate them. */ +#undef LONG_DOUBLE_TYPE_SIZE +#define LONG_DOUBLE_TYPE_SIZE 64 + +/* Use crt1.o as a startup file and crtn.o as a closing file. */ + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ + "%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}} crtbegin.o%s" + +#define ENDFILE_SPEC "crtend.o%s crtn.o%s" + +/* Library spec, including SCO international language support. */ + +#undef LIB_SPEC +#define LIB_SPEC \ + "%{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp} %{scointl:libintl.a%s} -lc" + +/* Specify predefined symbols in preprocessor. */ + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dunix -Di386 -DM_UNIX -DM_I386 -DM_COFF -DM_WORDSWAP -Asystem(unix) -Asystem(svr3) -Acpu(i386) -Amachine(i386)" + +#undef CPP_SPEC +#define CPP_SPEC "%{scointl:-DM_INTERNAT}" + +/* This spec is used for telling cpp whether char is signed or not. */ + +#undef SIGNED_CHAR_SPEC +#if DEFAULT_SIGNED_CHAR +#define SIGNED_CHAR_SPEC \ + "%{funsigned-char:-D__CHAR_UNSIGNED__ -D_CHAR_UNSIGNED}" +#else +#define SIGNED_CHAR_SPEC \ + "%{!fsigned-char:-D__CHAR_UNSIGNED__ -D_CHAR_UNSIGNED}" +#endif + +/* Use atexit for static destructors, instead of defining + our own exit function. */ +#define HAVE_ATEXIT + +/* Specify the size_t type. */ +#define SIZE_TYPE "unsigned int" + +#if 0 /* Not yet certain whether this is needed. */ +/* If no 387, use the general regs to return floating values, + since this system does not emulate the 80387. */ + +#undef VALUE_REGNO +#define VALUE_REGNO(MODE) \ + ((TARGET_80387 + && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode) + ? FIRST_FLOAT_REG : 0) + +#undef HARD_REGNO_MODE_OK +#define HARD_REGNO_MODE_OK(REGNO, MODE) \ + ((REGNO) < 2 ? 1 \ + : (REGNO) < 4 ? 1 \ + : FP_REGNO_P (REGNO) ? ((GET_MODE_CLASS (MODE) == MODE_FLOAT \ + || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ + && TARGET_80387 \ + && GET_MODE_UNIT_SIZE (MODE) <= 8) \ + : (MODE) != QImode) +#endif + +/* caller has to pop the extra argument passed to functions that return + structures. */ + +#undef RETURN_POPS_ARGS +#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \ + (TREE_CODE (FUNTYPE) == IDENTIFIER_NODE ? 0 \ + : (TARGET_RTD \ + && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ + || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ + == void_type_node))) ? (SIZE) \ + : 0) +/* On other 386 systems, the last line looks like this: + : (aggregate_value_p (TREE_TYPE (FUNTYPE))) ? GET_MODE_SIZE (Pmode) : 0) */ + +/* Handle #pragma pack. */ +#define HANDLE_SYSV_PRAGMA diff --git a/contrib/gcc/config/i386/sco4.h b/contrib/gcc/config/i386/sco4.h new file mode 100644 index 0000000..fc389b4 --- /dev/null +++ b/contrib/gcc/config/i386/sco4.h @@ -0,0 +1,86 @@ +/* Definitions for Intel 386 running SCO Unix System V 3.2 Version 4. + Written by Chip Salzenberg. + Copyright (C) 1992, 1994 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + + +/* Mostly it's like earlier SCO UNIX. */ + +#include "i386/sco.h" + +/* Use crt1.o as a startup file and crtn.o as a closing file. */ + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ + "%{scoxpg3:%{p:mcrt1X.o%s}%{!p:crt1X.o%s}} \ + %{!scoxpg3:\ + %{posix:%{p:mcrt1P.o%s}%{!p:crt1P.o%s}} \ + %{!posix:\ + %{ansi:%{p:mcrt1A.o%s}%{!p:crt1A.o%s}} \ + %{!ansi:%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}}}} \ + crtbegin.o%s" + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC \ + "crtend.o%s \ + %{scoxpg3:crtnX.o%s} \ + %{!scoxpg3:\ + %{posix:crtnP.o%s} \ + %{!posix:\ + %{ansi:crtnA.o%s} \ + %{!ansi:crtn.o%s}}}" + +/* Library spec. */ + +#undef LIB_SPEC +#define LIB_SPEC \ + "%{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp} \ + %{scoxpg3:-lcX -lcP -lcA} \ + %{!scoxpg3:\ + %{posix:-lcP -lcA} \ + %{!posix:\ + %{ansi:-lcA} \ + %{!ansi:%{scointl:-lintl} -lc}}}" + +/* Macros, macros everywhere: + Specify predefined symbols in preprocessor. */ + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES \ + "-Asystem(unix) -Asystem(svr3) -Acpu(i386) -Amachine(i386)" + +#undef CPP_SPEC +#define CPP_SPEC \ + "-D_i386 -D_M_I386 -D_M_I86 -D_M_I86SM -D_M_SDATA -D_M_STEXT \ + -D_unix -D_M_UNIX -D_M_XENIX \ + -D_M_SYS5 -D_M_SYSV -D_M_SYS3 -D_M_SYSIII \ + -D_M_COFF -D_M_BITFIELDS -D_M_WORDSWAP \ + %{scoxpg3:-D_XOPEN_SOURCE -D_STRICT_NAMES} \ + %{!scoxpg3:%{posix:-D_POSIX_SOURCE -D_STRICT_NAMES}} \ + %{!scoxpg3:%{!posix:\ + %{ansi:-D_STRICT_NAMES}%{!ansi:\ + -Di386 -DM_I386 -DM_I86 -DM_I86SM -DM_SDATA -DM_STEXT \ + -Dunix -DM_UNIX -DM_XENIX \ + -DM_SYS5 -DM_SYSV -DM_SYS3 -DM_SYSIII \ + -DM_COFF -DM_BITFIELDS -DM_WORDSWAP \ + %{scointl:-D_M_INTERNAT -DM_INTERNAT} \ + %{traditional:-D_KR -D_SVID -D_NO_PROTOTYPE}}}}" + +/* The system headers are C++-aware. */ +#define NO_IMPLICIT_EXTERN_C diff --git a/contrib/gcc/config/i386/sco4dbx.h b/contrib/gcc/config/i386/sco4dbx.h new file mode 100644 index 0000000..0387c24 --- /dev/null +++ b/contrib/gcc/config/i386/sco4dbx.h @@ -0,0 +1,81 @@ +/* Definitions for Intel 386 running SCO Unix System V 3.2 Version 4.s, + using dbx-in-coff encapsulation. + Copyright (C) 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + + +/* Mostly it's like earlier SCO UNIX. */ + +#include "i386/scodbx.h" + +/* Use crt1.o as a startup file and crtn.o as a closing file. */ + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ + "%{!r:%{!z:gcc.ifile%s}%{z:gccz.ifile%s}}\ + %{scoxpg3:%{p:mcrt1X.o%s}%{!p:crt1X.o%s}} \ + %{!scoxpg3:\ + %{posix:%{p:mcrt1P.o%s}%{!p:crt1P.o%s}} \ + %{!posix:\ + %{ansi:%{p:mcrt1A.o%s}%{!p:crt1A.o%s}} \ + %{!ansi:%{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}}}}" + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC \ + "%{scoxpg3:crtnX.o%s} \ + %{!scoxpg3:\ + %{posix:crtnP.o%s} \ + %{!posix:\ + %{ansi:crtnA.o%s} \ + %{!ansi:crtn.o%s}}}" + +/* Library spec. */ + +#undef LIB_SPEC +#define LIB_SPEC \ + "%{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp} \ + %{scoxpg3:-lcX -lcP -lcA} \ + %{!scoxpg3:\ + %{posix:-lcP -lcA} \ + %{!posix:\ + %{ansi:-lcA} \ + %{!ansi:%{scointl:-lintl} -lc}}}" + +/* Macros, macros everywhere: + Specify predefined symbols in preprocessor. */ + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Di386 -Dunix -Asystem(unix) -Asystem(svr3) -Acpu(i386) -Amachine(i386)" + +#undef CPP_SPEC +#define CPP_SPEC \ + "-D_M_I386 -D_M_I86 -D_M_I86SM -D_M_SDATA -D_M_STEXT \ + -D_M_UNIX -D_M_XENIX \ + -D_M_SYS5 -D_M_SYSV -D_M_SYS3 -D_M_SYSIII \ + -D_M_COFF -D_M_BITFIELDS -D_M_WORDSWAP \ + %{scoxpg3:-D_XOPEN_SOURCE -D_STRICT_NAMES} \ + %{!scoxpg3:%{posix:-D_POSIX_SOURCE -D_STRICT_NAMES}} \ + %{!scoxpg3:%{!posix:\ + %{ansi:-D_STRICT_NAMES}%{!ansi:\ + -DM_I386 -DM_I86 -DM_I86SM -DM_SDATA -DM_STEXT \ + -DM_UNIX -DM_XENIX \ + -DM_SYS5 -DM_SYSV -DM_SYS3 -DM_SYSIII \ + -DM_COFF -DM_BITFIELDS -DM_WORDSWAP \ + %{scointl:-D_M_INTERNAT -DM_INTERNAT} \ + %{traditional:-D_KR -D_SVID -D_NO_PROTOTYPE}}}}" diff --git a/contrib/gcc/config/i386/scodbx.h b/contrib/gcc/config/i386/scodbx.h new file mode 100644 index 0000000..1309735 --- /dev/null +++ b/contrib/gcc/config/i386/scodbx.h @@ -0,0 +1,92 @@ +/* Definitions for Intel 386 running SCO Unix System V, + using dbx-in-coff encapsulation. + Copyright (C) 1992, 1995 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "i386/svr3dbx.h" + +/* Overridden defines for SCO systems from sco.h. */ + +/* By default, target has a 80387, uses IEEE compatible arithmetic, + and returns float values in the 387, ie, + (TARGET_80387 | TARGET_FLOAT_RETURNS_IN_80387) + + SCO's software emulation of a 387 fails to handle the `fucomp' + opcode. fucomp is only used when generating IEEE compliant code. + So don't make TARGET_IEEE_FP default for SCO. */ + +#undef TARGET_DEFAULT +#define TARGET_DEFAULT 0201 + +/* Use crt1.o as a startup file and crtn.o as a closing file. */ + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ + "%{!r:%{!z:svr3.ifile%s}%{z:svr3z.ifile%s}}\ + %{pg:gcrt1.o%s}%{!pg:%{p:mcrt1.o%s}%{!p:crt1.o%s}}" + +/* Library spec, including SCO international language support. */ + +#undef LIB_SPEC +#define LIB_SPEC \ + "%{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp} %{scointl:libintl.a%s} -lc" + +/* Specify predefined symbols in preprocessor. */ + +#undef CPP_PREDEFINES +#define CPP_PREDEFINES "-Dunix -Di386 -DM_UNIX -DM_I386 -DM_COFF -DM_WORDSWAP -Asystem(unix) -Asystem(svr3) -Acpu(i386) -Amachine(i386)" + +#undef CPP_SPEC +#define CPP_SPEC "%{scointl:-DM_INTERNAT}" + +/* This spec is used for telling cpp whether char is signed or not. */ + +#undef SIGNED_CHAR_SPEC +#if DEFAULT_SIGNED_CHAR +#define SIGNED_CHAR_SPEC \ + "%{funsigned-char:-D__CHAR_UNSIGNED__ -D_CHAR_UNSIGNED}" +#else +#define SIGNED_CHAR_SPEC \ + "%{!fsigned-char:-D__CHAR_UNSIGNED__ -D_CHAR_UNSIGNED}" +#endif + +/* Use atexit for static destructors, instead of defining + our own exit function. */ +#define HAVE_ATEXIT + +/* caller has to pop the extra argument passed to functions that return + structures. */ + +#undef RETURN_POPS_ARGS +#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \ + (TREE_CODE (FUNTYPE) == IDENTIFIER_NODE ? 0 \ + : (TARGET_RTD \ + && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ + || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ + == void_type_node))) ? (SIZE) \ + : 0) +/* On other 386 systems, the last line looks like this: + : (aggregate_value_p (TREE_TYPE (FUNTYPE))) ? GET_MODE_SIZE (Pmode) : 0) */ + +/* Use periods rather than dollar signs in special g++ assembler names. */ + +#define NO_DOLLAR_IN_LABEL + +/* Handle #pragma pack. */ +#define HANDLE_SYSV_PRAGMA diff --git a/contrib/gcc/config/i386/seq-gas.h b/contrib/gcc/config/i386/seq-gas.h new file mode 100644 index 0000000..2ee0719 --- /dev/null +++ b/contrib/gcc/config/i386/seq-gas.h @@ -0,0 +1,46 @@ +/* Definitions for Sequent Intel 386 using GAS. + Copyright (C) 1992 Free Software Foundation, Inc. + +/* Mostly it's like a Sequent 386 without GAS. */ + +#include "i386/sequent.h" + +/* A C statement or statements which output an assembler instruction + opcode to the stdio stream STREAM. The macro-operand PTR is a + variable of type `char *' which points to the opcode name in its + "internal" form--the form that is written in the machine description. + + GAS version 1.38.1 doesn't understand the `repz' opcode mnemonic. + So use `repe' instead. */ + +#undef ASM_OUTPUT_OPCODE +#define ASM_OUTPUT_OPCODE(STREAM, PTR) \ +{ \ + if ((PTR)[0] == 'r' \ + && (PTR)[1] == 'e' \ + && (PTR)[2] == 'p') \ + { \ + if ((PTR)[3] == 'z') \ + { \ + fprintf (STREAM, "repe"); \ + (PTR) += 4; \ + } \ + else if ((PTR)[3] == 'n' && (PTR)[4] == 'z') \ + { \ + fprintf (STREAM, "repne"); \ + (PTR) += 5; \ + } \ + } \ +} + +/* Define macro used to output shift-double opcodes when the shift + count is in %cl. Some assemblers require %cl as an argument; + some don't. + + GAS requires the %cl argument, so override i386/unix.h. */ + +#undef AS3_SHIFT_DOUBLE +#define AS3_SHIFT_DOUBLE(a,b,c,d) AS3 (a,b,c,d) + +/* Print opcodes the way that GAS expects them. */ +#define GAS_MNEMONICS 1 diff --git a/contrib/gcc/config/i386/seq-sysv3.h b/contrib/gcc/config/i386/seq-sysv3.h new file mode 100644 index 0000000..e3182ee --- /dev/null +++ b/contrib/gcc/config/i386/seq-sysv3.h @@ -0,0 +1,56 @@ +/* Sequent DYNIX/ptx 1.x (SVr3) */ + +#include "i386/sysv3.h" + +/* Sequent Symmetry SVr3 doesn't have crtn.o; crt1.o doesn't work + but crt0.o does. */ + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ +"%{pg:gcrt0.o%s}\ + %{!pg:%{posix:%{p:mcrtp0.o%s}%{!p:crtp0.o%s}}\ + %{!posix:%{p:mcrt0.o%s}%{!p:crt0.o%s}}} crtbegin.o%s\ + %{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp}" + +#undef LIB_SPEC +#define LIB_SPEC \ +"%{posix:-lcposix}\ + %{shlib:-lc_s}\ + %{fshared-data:-lpps -lseq} -lc crtend.o%s" + +#undef CPP_SPEC +#define CPP_SPEC "%{posix:-D_POSIX_SOURCE} -D_SEQUENT_=1" + +/* Although the .init section is used, it is not automatically invoked. + This because the _start() function in /lib/crt0.o never calls anything + from the .init section */ +#define INVOKE__main + +/* Assembler pseudo-op for initialized shared variables (.shdata). */ +#undef SHARED_SECTION_ASM_OP +#define SHARED_SECTION_ASM_OP ".section .shdata, \"ws\"" + +/* Assembler pseudo-op for uninitialized shared global variables (.shbss). */ +#undef ASM_OUTPUT_SHARED_COMMON +#define ASM_OUTPUT_SHARED_COMMON(FILE, NAME, SIZE, ROUNDED) \ +( fputs(".comm ", (FILE)), \ + assemble_name((FILE), (NAME)), \ + fprintf((FILE), ",%u,-3\n", (SIZE))) + +/* Assembler pseudo-op for uninitialized shared local variables (.shbss). */ +#undef SHARED_BSS_SECTION_ASM_OP +#define SHARED_BSS_SECTION_ASM_OP ".section .shbss, \"bs\"" +#undef BSS_SECTION_FUNCTION +#define BSS_SECTION_FUNCTION \ +void \ +bss_section () \ +{ \ + if (in_section != in_bss) \ + { \ + if (flag_shared_data) \ + fprintf (asm_out_file, "%s\n", SHARED_BSS_SECTION_ASM_OP); \ + else \ + fprintf (asm_out_file, "%s\n", BSS_SECTION_ASM_OP); \ + in_section = in_bss; \ + } \ +} diff --git a/contrib/gcc/config/i386/seq2-sysv3.h b/contrib/gcc/config/i386/seq2-sysv3.h new file mode 100644 index 0000000..763c5f0 --- /dev/null +++ b/contrib/gcc/config/i386/seq2-sysv3.h @@ -0,0 +1,8 @@ +/* Sequent DYNIX/ptx 2.x (SVr3) */ + +#include "i386/seq-sysv3.h" + +/* Use atexit for static destructors, instead of defining + our own exit function. */ +#define HAVE_ATEXIT + diff --git a/contrib/gcc/config/i386/sequent.h b/contrib/gcc/config/i386/sequent.h new file mode 100644 index 0000000..4d76c38 --- /dev/null +++ b/contrib/gcc/config/i386/sequent.h @@ -0,0 +1,152 @@ +/* Definitions for Sequent Intel 386. + Copyright (C) 1988, 1994 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "i386/i386.h" + +/* Use the BSD assembler syntax. */ + +#include "i386/bsd.h" + +/* By default, don't use IEEE compatible arithmetic comparisons + because the assembler can't handle the fucom insn. + Return float values in the 387. + (TARGET_80387 | TARGET_FLOAT_RETURNS_IN_80387) */ + +#undef TARGET_DEFAULT +#define TARGET_DEFAULT 0201 + +/* Specify predefined symbols in preprocessor. */ + +#define CPP_PREDEFINES "-Dunix -Di386 -Dsequent -Asystem(unix) -Acpu(i386) -Amachine(i386)" + +/* Pass -Z and -ZO options to the linker. */ + +#define LINK_SPEC "%{Z*}" + +#if 0 /* Dynix 3.1 is said to accept -L. */ +/* Dynix V3.0.12 doesn't accept -L at all. */ + +#define LINK_LIBGCC_SPECIAL +#endif + +/* Link with libg.a when debugging, for dbx's sake. */ + +#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} " + +/* We don't want to output SDB debugging information. */ + +#undef SDB_DEBUGGING_INFO + +/* We want to output DBX debugging information. */ + +#define DBX_DEBUGGING_INFO + +/* Sequent Symmetry has size_t defined as int in /usr/include/sys/types.h */ +#define SIZE_TYPE "int" + +/* gcc order is ax, dx, cx, bx, si, di, bp, sp, st, st. + * dbx order is ax, dx, cx, st(0), st(1), bx, si, di, st(2), st(3), + * st(4), st(5), st(6), st(7), sp, bp */ + +/* ??? The right thing would be to change the ordering of the + registers to correspond to the conventions of this system, + and get rid of DBX_REGISTER_NUMBER. */ + +#undef DBX_REGISTER_NUMBER +#define DBX_REGISTER_NUMBER(n) \ +((n) < 3 ? (n) : (n) < 6 ? (n) + 2 \ + : (n) == 6 ? 15 : (n) == 7 ? 14 : 3) + +/* malcolmp@hydra.maths.unsw.EDU.AU says these two definitions + fix trouble in dbx. */ +#undef DBX_OUTPUT_LBRAC +#define DBX_OUTPUT_LBRAC(file,name) \ + fprintf (asmfile, "%s %d,0,%d,", ASM_STABN_OP, N_LBRAC, depth); \ + assemble_name (asmfile, buf); \ + fprintf (asmfile, "\n"); + +#undef DBX_OUTPUT_RBRAC +#define DBX_OUTPUT_RBRAC(file,name) \ + fprintf (asmfile, "%s %d,0,%d,", ASM_STABN_OP, N_RBRAC, depth); \ + assemble_name (asmfile, buf); \ + fprintf (asmfile, "\n"); + +/* Prevent anything from being allocated in the register pair cx/bx, + since that would confuse GDB. */ + +#undef HARD_REGNO_MODE_OK +#define HARD_REGNO_MODE_OK(REGNO, MODE) \ + (((REGNO) < 2 ? 1 \ + : (REGNO) < 4 ? 1 \ + : FP_REGNO_P (REGNO) ? (GET_MODE_CLASS (MODE) == MODE_FLOAT \ + || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ + : (MODE) != QImode) \ + && ! (REGNO == 2 && GET_MODE_UNIT_SIZE (MODE) > 4)) + +/* Output assembler code to FILE to increment profiler label # LABELNO + for profiling a function entry. */ + +#undef FUNCTION_PROFILER +#define FUNCTION_PROFILER(FILE, LABELNO) \ + fprintf (FILE, "\tmovl $.LP%d,%%eax\n\tcall mcount\n", (LABELNO)); + +/* Assembler pseudo-op for shared data segment. */ +#define SHARED_SECTION_ASM_OP ".shdata" + +/* A C statement or statements which output an assembler instruction + opcode to the stdio stream STREAM. The macro-operand PTR is a + variable of type `char *' which points to the opcode name in its + "internal" form--the form that is written in the machine description. + + The Sequent assembler (identified as "Balance 8000 Assembler + 07/17/85 3.90" by "as -v") does not understand the `movs[bwl]' string + move mnemonics - it uses `smov[bwl]' instead. Change "movs" into + "smov", carefully avoiding the sign-extend opcodes. */ + +#define ASM_OUTPUT_OPCODE(STREAM, PTR) \ +{ \ + if ((PTR)[0] == 'm' \ + && (PTR)[1] == 'o' \ + && (PTR)[2] == 'v' \ + && (PTR)[3] == 's' \ + && ((PTR)[4] == 'b' || (PTR)[4] == 'w' || (PTR)[4] == 'l') \ + && ((PTR)[5] == ' ' || (PTR)[5] == '\t'|| (PTR)[5] == '\0')) \ + { \ + fprintf (STREAM, "smov"); \ + (PTR) += 4; \ + } \ +} + +/* 10-Aug-92 pes Local labels are prefixed with ".L" */ +#undef LPREFIX +#define LPREFIX ".L" + +#undef ASM_GENERATE_INTERNAL_LABEL +#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER)\ + sprintf ((BUF), "*.%s%d", (PREFIX), (NUMBER)) + +#undef ASM_OUTPUT_INTERNAL_LABEL +#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM)\ + fprintf (FILE, ".%s%d:\n", PREFIX, NUM) + +/* The native compiler passes the address of the returned structure in eax. */ +#undef STRUCT_VALUE +#undef STRUCT_VALUE_INCOMING +#define STRUCT_VALUE_REGNUM 0 diff --git a/contrib/gcc/config/i386/sol2-c1.asm b/contrib/gcc/config/i386/sol2-c1.asm new file mode 100644 index 0000000..72fdfb8 --- /dev/null +++ b/contrib/gcc/config/i386/sol2-c1.asm @@ -0,0 +1,156 @@ +! crt1.s for Solaris 2, x86 + +! Copyright (C) 1993 Free Software Foundation, Inc. +! Written By Fred Fish, Nov 1992 +! +! This file is free software; you can redistribute it and/or modify it +! under the terms of the GNU General Public License as published by the +! Free Software Foundation; either version 2, or (at your option) any +! later version. +! +! In addition to the permissions in the GNU General Public License, the +! Free Software Foundation gives you unlimited permission to link the +! compiled version of this file with other programs, and to distribute +! those programs without any restriction coming from the use of this +! file. (The General Public License restrictions do apply in other +! respects; for example, they cover modification of the file, and +! distribution when not linked into another program.) +! +! This file is distributed in the hope that it will be useful, but +! WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! General Public License for more details. +! +! You should have received a copy of the GNU General Public License +! along with this program; see the file COPYING. If not, write to +! the Free Software Foundation, 59 Temple Place - Suite 330, +! Boston, MA 02111-1307, USA. +! +! As a special exception, if you link this library with files +! compiled with GCC to produce an executable, this does not cause +! the resulting executable to be covered by the GNU General Public License. +! This exception does not however invalidate any other reasons why +! the executable file might be covered by the GNU General Public License. +! + +! This file takes control of the process from the kernel, as specified +! in section 3 of the System V Application Binary Interface, Intel386 +! Processor Supplement. It has been constructed from information obtained +! from the ABI, information obtained from single stepping existing +! Solaris executables through their startup code with gdb, and from +! information obtained by single stepping executables on other i386 SVR4 +! implementations. This file is the first thing linked into any executable. + + .file "crt1.s" + .ident "GNU C crt1.s" + .weak _cleanup + .weak _DYNAMIC + .text + +! Start creating the initial frame by pushing a NULL value for the return +! address of the initial frame, and mark the end of the stack frame chain +! (the innermost stack frame) with a NULL value, per page 3-32 of the ABI. +! Initialize the first stack frame pointer in %ebp (the contents of which +! are unspecified at process initialization). + + .globl _start +_start: + pushl $0x0 + pushl $0x0 + movl %esp,%ebp + +! As specified per page 3-32 of the ABI, %edx contains a function +! pointer that should be registered with atexit(), for proper +! shared object termination. Just push it onto the stack for now +! to preserve it. We want to register _cleanup() first. + + pushl %edx + +! Check to see if there is an _cleanup() function linked in, and if +! so, register it with atexit() as the last thing to be run by +! atexit(). + + movl $_cleanup,%eax + testl %eax,%eax + je .L1 + pushl $_cleanup + call atexit + addl $0x4,%esp +.L1: + +! Now check to see if we have an _DYNAMIC table, and if so then +! we need to register the function pointer previously in %edx, but +! now conveniently saved on the stack as the argument to pass to +! atexit(). + + movl $_DYNAMIC,%eax + testl %eax,%eax + je .L2 + call atexit +.L2: + +! Register _fini() with atexit(). We will take care of calling _init() +! directly. + + pushl $_fini + call atexit + +! Compute the address of the environment vector on the stack and load +! it into the global variable _environ. Currently argc is at 8 off +! the frame pointer. Fetch the argument count into %eax, scale by the +! size of each arg (4 bytes) and compute the address of the environment +! vector which is 16 bytes (the two zero words we pushed, plus argc, +! plus the null word terminating the arg vector) further up the stack, +! off the frame pointer (whew!). + + movl 8(%ebp),%eax + leal 16(%ebp,%eax,4),%edx + movl %edx,_environ + +! Push the environment vector pointer, the argument vector pointer, +! and the argument count on to the stack to set up the arguments +! for _init(), _fpstart(), and main(). Note that the environment +! vector pointer and the arg count were previously loaded into +! %edx and %eax respectively. The only new value we need to compute +! is the argument vector pointer, which is at a fixed address off +! the initial frame pointer. + + pushl %edx + leal 12(%ebp),%edx + pushl %edx + pushl %eax + +! Call _init(argc, argv, environ), _fpstart(argc, argv, environ), and +! main(argc, argv, environ). + + call _init + call __fpstart + call main + +! Pop the argc, argv, and environ arguments off the stack, push the +! value returned from main(), and call exit(). + + addl $12,%esp + pushl %eax + call exit + +! An inline equivalent of _exit, as specified in Figure 3-26 of the ABI. + + pushl $0x0 + movl $0x1,%eax + lcall $7,$0 + +! If all else fails, just try a halt! + + hlt + .type _start,@function + .size _start,.-_start + +! A dummy profiling support routine for non-profiling executables, +! in case we link in some objects that have been compiled for profiling. + + .globl _mcount +_mcount: + ret + .type _mcount,@function + .size _mcount,.-_mcount diff --git a/contrib/gcc/config/i386/sol2-ci.asm b/contrib/gcc/config/i386/sol2-ci.asm new file mode 100644 index 0000000..439c709 --- /dev/null +++ b/contrib/gcc/config/i386/sol2-ci.asm @@ -0,0 +1,51 @@ +! crti.s for Solaris 2, x86. + +! Copyright (C) 1993 Free Software Foundation, Inc. +! Written By Fred Fish, Nov 1992 +! +! This file is free software; you can redistribute it and/or modify it +! under the terms of the GNU General Public License as published by the +! Free Software Foundation; either version 2, or (at your option) any +! later version. +! +! In addition to the permissions in the GNU General Public License, the +! Free Software Foundation gives you unlimited permission to link the +! compiled version of this file with other programs, and to distribute +! those programs without any restriction coming from the use of this +! file. (The General Public License restrictions do apply in other +! respects; for example, they cover modification of the file, and +! distribution when not linked into another program.) +! +! This file is distributed in the hope that it will be useful, but +! WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! General Public License for more details. +! +! You should have received a copy of the GNU General Public License +! along with this program; see the file COPYING. If not, write to +! the Free Software Foundation, 59 Temple Place - Suite 330, +! Boston, MA 02111-1307, USA. +! +! As a special exception, if you link this library with files +! compiled with GCC to produce an executable, this does not cause +! the resulting executable to be covered by the GNU General Public License. +! This exception does not however invalidate any other reasons why +! the executable file might be covered by the GNU General Public License. +! + +! This file just supplies labeled starting points for the .init and .fini +! sections. It is linked in before the values-Xx.o files and also before +! crtbegin.o. + + .file "crti.s" + .ident "GNU C crti.s" + + .section .init + .globl _init + .type _init,@function +_init: + + .section .fini + .globl _fini + .type _fini,@function +_fini: diff --git a/contrib/gcc/config/i386/sol2-cn.asm b/contrib/gcc/config/i386/sol2-cn.asm new file mode 100644 index 0000000..3f3bad9 --- /dev/null +++ b/contrib/gcc/config/i386/sol2-cn.asm @@ -0,0 +1,46 @@ +! crtn.s for Solaris 2, x86. + +! Copyright (C) 1993 Free Software Foundation, Inc. +! Written By Fred Fish, Nov 1992 +! +! This file is free software; you can redistribute it and/or modify it +! under the terms of the GNU General Public License as published by the +! Free Software Foundation; either version 2, or (at your option) any +! later version. +! +! In addition to the permissions in the GNU General Public License, the +! Free Software Foundation gives you unlimited permission to link the +! compiled version of this file with other programs, and to distribute +! those programs without any restriction coming from the use of this +! file. (The General Public License restrictions do apply in other +! respects; for example, they cover modification of the file, and +! distribution when not linked into another program.) +! +! This file is distributed in the hope that it will be useful, but +! WITHOUT ANY WARRANTY; without even the implied warranty of +! MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +! General Public License for more details. +! +! You should have received a copy of the GNU General Public License +! along with this program; see the file COPYING. If not, write to +! the Free Software Foundation, 59 Temple Place - Suite 330, +! Boston, MA 02111-1307, USA. +! +! As a special exception, if you link this library with files +! compiled with GCC to produce an executable, this does not cause +! the resulting executable to be covered by the GNU General Public License. +! This exception does not however invalidate any other reasons why +! the executable file might be covered by the GNU General Public License. +! + +! This file just supplies returns for the .init and .fini sections. It is +! linked in after all other files. + + .file "crtn.o" + .ident "GNU C crtn.o" + + .section .init + ret $0x0 + + .section .fini + ret $0x0 diff --git a/contrib/gcc/config/i386/sol2.h b/contrib/gcc/config/i386/sol2.h new file mode 100644 index 0000000..cc5ebca --- /dev/null +++ b/contrib/gcc/config/i386/sol2.h @@ -0,0 +1,91 @@ +/* Target definitions for GNU compiler for Intel 80386 running Solaris 2 + Copyright (C) 1993, 1995 Free Software Foundation, Inc. + + Written by Fred Fish (fnf@cygnus.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "i386/sysv4.h" + +/* The Solaris 2.0 x86 linker botches alignment of code sections. + It tries to align to a 16 byte boundary by padding with 0x00000090 + ints, rather than 0x90 bytes (nop). This generates trash in the + ".init" section since the contribution from crtbegin.o is only 7 + bytes. The linker pads it to 16 bytes with a single 0x90 byte, and + two 0x00000090 ints, which generates a segmentation violation when + executed. This macro forces the assembler to do the padding, since + it knows what it is doing. */ + +#define FORCE_INIT_SECTION_ALIGN do { asm (ALIGN_ASM_OP ## " 16"); } while (0) +#define FORCE_FINI_SECTION_ALIGN FORCE_INIT_SECTION_ALIGN + +/* Add "sun" to the list of symbols defined for SVR4. */ +#undef CPP_PREDEFINES +#define CPP_PREDEFINES \ + "-Di386 -Dunix -D__svr4__ -D__SVR4 -Dsun \ + -Asystem(unix) -Asystem(svr4) -Acpu(i386) -Amachine(i386)" + +#undef CPP_SPEC +#define CPP_SPEC "\ + %{compat-bsd:-iwithprefixbefore ucbinclude -I/usr/ucbinclude}" + +#undef LIB_SPEC +#define LIB_SPEC \ + "%{compat-bsd:-lucb -lsocket -lnsl -lelf -laio} %{!shared:%{!symbolic:-lc}}" + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC "crtend.o%s %{pg:crtn.o%s}%{!pg:crtn.o%s}" + +/* This should be the same as in svr4.h, except with -R added. */ +#undef LINK_SPEC +#define LINK_SPEC \ + "%{h*} %{V} %{v:%{!V:-V}} \ + %{b} %{Wl,*:%*} \ + %{static:-dn -Bstatic} \ + %{shared:-G -dy -z text} \ + %{symbolic:-Bsymbolic -G -dy -z text} \ + %{G:-G} \ + %{YP,*} \ + %{R*} \ + %{compat-bsd: \ + %{!YP,*:%{p:-Y P,/usr/ucblib:/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \ + %{!p:-Y P,/usr/ucblib:/usr/ccs/lib:/usr/lib}} \ + -R /usr/ucblib} \ + %{!compat-bsd: \ + %{!YP,*:%{p:-Y P,/usr/ccs/lib/libp:/usr/lib/libp:/usr/ccs/lib:/usr/lib} \ + %{!p:-Y P,/usr/ccs/lib:/usr/lib}}} \ + %{Qy:} %{!Qn:-Qy}" + +/* This defines which switch letters take arguments. + It is as in svr4.h but with -R added. */ + +#undef SWITCH_TAKES_ARG +#define SWITCH_TAKES_ARG(CHAR) \ + ( (CHAR) == 'D' \ + || (CHAR) == 'U' \ + || (CHAR) == 'o' \ + || (CHAR) == 'e' \ + || (CHAR) == 'u' \ + || (CHAR) == 'I' \ + || (CHAR) == 'm' \ + || (CHAR) == 'L' \ + || (CHAR) == 'R' \ + || (CHAR) == 'A' \ + || (CHAR) == 'h' \ + || (CHAR) == 'z') + diff --git a/contrib/gcc/config/i386/sun.h b/contrib/gcc/config/i386/sun.h new file mode 100644 index 0000000..ecc0e82 --- /dev/null +++ b/contrib/gcc/config/i386/sun.h @@ -0,0 +1,83 @@ +/* Definitions for Intel 386 running SunOS 4.0. + Copyright (C) 1988, 1995 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + + +#include "i386/i386.h" + +/* Use the Sun assembler syntax. */ + +#include "i386/sun386.h" + +/* Use crt0.o as a startup file. */ + +#define STARTFILE_SPEC \ + "%{pg:gcrt0.o%s}%{!pg:%{p:mcrt0.o%s}%{!p:crt0.o%s}}" + +#define LIB_SPEC "%{g:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p} \ +%{g:-lg} %{sun386:}" +/* That last item is just to prevent a spurious error. */ + +#undef LINK_SPEC +#define LINK_SPEC \ + "%{!nostdlib:%{!r*:%{!e*:-e _start}}} -dc -dp %{static:-Bstatic}" + +/* Extra switches to give the assembler. */ + +#define ASM_SPEC "%{R} -i386 %{keep-local-as-symbols:-L}" + +/* Specify predefined symbols in preprocessor. */ + +#define CPP_PREDEFINES "-Dunix -Di386 -Dsun386 -Dsun -Asystem(unix) -Asystem(bsd) -Acpu(i386) -Amachine(i386)" + +/* Allow #sccs in preprocessor. */ + +#define SCCS_DIRECTIVE + +/* Output #ident as a .ident. */ + +#define ASM_OUTPUT_IDENT(FILE, NAME) fprintf (FILE, "\t.ident \"%s\"\n", NAME); + +/* We don't want to output SDB debugging information. */ + +#undef SDB_DEBUGGING_INFO + +/* We want to output DBX debugging information. */ + +#define DBX_DEBUGGING_INFO + +/* Implicit library calls should use memcpy, not bcopy, etc. */ + +#define TARGET_MEM_FUNCTIONS + +/* Force structure alignment to the type used for a bitfield. */ + +#define PCC_BITFIELD_TYPE_MATTERS 1 + +/* This is partly guess. */ + +#undef DBX_REGISTER_NUMBER +#define DBX_REGISTER_NUMBER(n) \ + ((n) == 0 ? 11 : (n) == 1 ? 9 : (n) == 2 ? 10 : (n) == 3 ? 8 \ + : (n) == 4 ? 5 : (n) == 5 ? 4 : (n) == 6 ? 6 : (n)) + +/* Every debugger symbol must be in the text section. + Otherwise the assembler or the linker screws up. */ + +#define DEBUG_SYMS_TEXT diff --git a/contrib/gcc/config/i386/sun386.h b/contrib/gcc/config/i386/sun386.h new file mode 100644 index 0000000..6e26807 --- /dev/null +++ b/contrib/gcc/config/i386/sun386.h @@ -0,0 +1,143 @@ +/* Definitions for Sun assembler syntax for the Intel 80386. + Copyright (C) 1988 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + + +/* Include common aspects of all 386 Unix assemblers. */ +#include "i386/unix.h" + +#define TARGET_VERSION fprintf (stderr, " (80386, Sun syntax)"); + +/* Define the syntax of instructions and addresses. */ + +/* Prefix for internally generated assembler labels. */ +#define LPREFIX ".L" + +/* Define the syntax of pseudo-ops, labels and comments. */ + +/* Assembler pseudos to introduce constants of various size. */ + +#define ASM_BYTE_OP "\t.byte" +#define ASM_SHORT "\t.value" +#define ASM_LONG "\t.long" +#define ASM_DOUBLE "\t.double" + +/* How to output an ASCII string constant. */ + +#define ASM_OUTPUT_ASCII(FILE, p, size) \ +do \ +{ int i = 0; \ + while (i < (size)) \ + { if (i%10 == 0) { if (i!=0) fprintf ((FILE), "\n"); \ + fprintf ((FILE), "%s ", ASM_BYTE_OP); } \ + else fprintf ((FILE), ","); \ + fprintf ((FILE), "0x%x", ((p)[i++] & 0377)) ;} \ + fprintf ((FILE), "\n"); \ +} while (0) + +/* Output at beginning of assembler file. */ +/* The .file command should always begin the output. */ + +#undef ASM_FILE_START +#define ASM_FILE_START(FILE) \ + do { \ + extern char *version_string, *language_string; \ + { \ + int len = strlen (dump_base_name); \ + char *na = dump_base_name + len; \ + char shorter[15]; \ + /* NA gets DUMP_BASE_NAME sans directory names. */\ + while (na > dump_base_name) \ + { \ + if (na[-1] == '/') \ + break; \ + na--; \ + } \ + strncpy (shorter, na, 14); \ + shorter[14] = 0; \ + fprintf (FILE, "\t.file\t"); \ + output_quoted_string (FILE, shorter); \ + fprintf (FILE, "\n"); \ + } \ + fprintf (FILE, "\t.version\t\"%s %s\"\n", \ + language_string, version_string); \ + if (optimize) ASM_FILE_START_1 (FILE); \ + } while (0) + +#define ASM_FILE_START_1(FILE) fprintf (FILE, "\t.optim\n") + +/* This is how to output an assembler line + that says to advance the location counter + to a multiple of 2**LOG bytes. */ + +#define ASM_OUTPUT_ALIGN(FILE,LOG) \ + if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", 1<<(LOG)) + +/* This is how to output an assembler line + that says to advance the location counter by SIZE bytes. */ + +#define ASM_OUTPUT_SKIP(FILE,SIZE) \ + fprintf ((FILE), "\t.set\t.,.+%u\n", (SIZE)) + +/* Output before read-only data. */ + +#undef TEXT_SECTION_ASM_OP +#define TEXT_SECTION_ASM_OP ".text" + +/* Output before writable data. */ + +#undef DATA_SECTION_ASM_OP +#define DATA_SECTION_ASM_OP ".data" + +/* Define the syntax of labels and symbol definitions/declarations. */ + +/* This says how to output an assembler line + to define a global common symbol. */ + +#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ +( fputs (".comm ", (FILE)), \ + assemble_name ((FILE), (NAME)), \ + fprintf ((FILE), ",%u\n", (ROUNDED))) + +/* This says how to output an assembler line + to define a local common symbol. */ + +#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ +( fputs (".lcomm ", (FILE)), \ + assemble_name ((FILE), (NAME)), \ + fprintf ((FILE), ",%u\n", (ROUNDED))) + +/* This is how to store into the string BUF + the symbol_ref name of an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. + This is suitable for output with `assemble_name'. */ + +#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ + sprintf ((BUF), "*.%s%d", (PREFIX), (NUMBER)) + +/* This is how to output a reference to a user-level label named NAME. */ + +#define ASM_OUTPUT_LABELREF(FILE,NAME) \ + fprintf (FILE, "%s", NAME) + +/* This is how to output an internal numbered label where + PREFIX is the class of label and NUM is the number within the class. */ + +#define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ + fprintf (FILE, ".%s%d:\n", PREFIX, NUM) diff --git a/contrib/gcc/config/i386/svr3.ifile b/contrib/gcc/config/i386/svr3.ifile new file mode 100644 index 0000000..f0bb3a0 --- /dev/null +++ b/contrib/gcc/config/i386/svr3.ifile @@ -0,0 +1,45 @@ +/* + * svr3.ifile - for collectless G++ on i386 System V. + * Leaves memory configured at address 0. + * + * Install this file as $prefix/gcc-lib/TARGET/VERSION/gcc.ifile + * + * BLOCK to an offset that leaves room for many headers ( the value + * here allows for a file header, an outheader, and up to 11 section + * headers on most systems. + * BIND to an address that includes page 0 in mapped memory. The value + * used for BLOCK should be or'd into this value. Here I'm setting BLOCK + * to 0x200 and BIND to ( value_used_for(BLOCK) ) + * If you are using shared libraries, watch that you don't overlap the + * address ranges assigned for shared libs. + * + * GROUP BIND to a location in the next segment. Here, the only value + * that you should change (I think) is that within NEXT, which I've set + * to my hardware segment size. You can always use a larger size, but not + * a smaller one. + */ +SECTIONS +{ + .text BIND(0x000200) BLOCK (0x200) : + { + /* plenty for room for headers */ + *(.init) + *(.text) + vfork = fork; /* I got tired of editing peoples sloppy code */ + *(.fini) + } + GROUP BIND( NEXT(0x400000) + (ADDR(.text) + (SIZEOF(.text)) % 0x1000)): + { + .data : { + __CTOR_LIST__ = . ; + . += 4 ; /* leading NULL */ + *(.ctor) + . += 4 ; /* trailing NULL */ + __DTOR_LIST__ = . ; + . += 4 ; /* leading NULL */ + *(.dtor) + . += 4 ; /* trailing NULL */ + } + .bss : { } + } +} diff --git a/contrib/gcc/config/i386/svr3dbx.h b/contrib/gcc/config/i386/svr3dbx.h new file mode 100644 index 0000000..d3348d5 --- /dev/null +++ b/contrib/gcc/config/i386/svr3dbx.h @@ -0,0 +1,97 @@ +/* Definitions for Intel 386 running system V, using dbx-in-coff encapsulation. + Copyright (C) 1992, 1995 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "i386/svr3gas.h" + +/* We do not want to output SDB debugging information. */ + +#undef SDB_DEBUGGING_INFO + +/* We want to output DBX debugging information. */ + +#define DBX_DEBUGGING_INFO + +/* Compensate for botch in dbxout_init/dbxout_source_file which + unconditionally drops the first character from ltext_label_name */ + +#undef ASM_GENERATE_INTERNAL_LABEL +#define ASM_GENERATE_INTERNAL_LABEL(BUF,PREFIX,NUMBER) \ + sprintf ((BUF), "*.%s%d", (PREFIX), (NUMBER)) + +/* With the current gas, .align N aligns to an N-byte boundary. + This is done to be compatible with the system assembler. + You must specify -DOTHER_ALIGN when building gas-1.38.1. */ + +#undef ASM_OUTPUT_ALIGN +#define ASM_OUTPUT_ALIGN(FILE,LOG) \ + if ((LOG)!=0) fprintf ((FILE), "\t.align %d\n", 1<<(LOG)) + +/* Align labels, etc. at 4-byte boundaries. + For the 486, align to 16-byte boundary for sake of cache. */ + +#undef ASM_OUTPUT_ALIGN_CODE +#define ASM_OUTPUT_ALIGN_CODE(FILE) \ + fprintf ((FILE), "\t.align %d,0x90\n", \ + 1 << i386_align_jumps) + +/* Align start of loop at 4-byte boundary. */ + +#undef ASM_OUTPUT_LOOP_ALIGN +#define ASM_OUTPUT_LOOP_ALIGN(FILE) \ + fprintf ((FILE), "\t.align %d,0x90\n", 1 << i386_align_loops); + + +/* Additional overrides needed for dbx-in-coff gas, mostly taken from pbb.h */ + +/* Although the gas we use can create .ctor and .dtor sections from N_SETT + stabs, it does not support section directives, so we need to have the loader + define the lists. + */ +#define CTOR_LISTS_DEFINED_EXTERNALLY + +/* similar to default, but allows for the table defined by ld with svr3.ifile. + nptrs is always 0. So we need to instead check that __DTOR_LIST__[1] != 0. + The old check is left in so that the same macro can be used if and when + a future version of gas does support section directives. */ + +#define DO_GLOBAL_DTORS_BODY {int nptrs = *(int *)__DTOR_LIST__; int i; \ + if (nptrs == -1 || (__DTOR_LIST__[0] == 0 && __DTOR_LIST__[1] != 0)) \ + for (nptrs = 0; __DTOR_LIST__[nptrs + 1] != 0; nptrs++); \ + for (i = nptrs; i >= 1; i--) \ + __DTOR_LIST__[i] (); } + +/* Use crt1.o as a startup file and crtn.o as a closing file. */ +/* + * The loader directive file svr3.ifile defines how to merge the constructor + * sections into the data section. Also, since gas only puts out those + * sections in response to N_SETT stabs, and does not (yet) have a + * ".sections" directive, svr3.ifile also defines the list symbols + * __DTOR_LIST__ and __CTOR_LIST__. + */ +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ + "%{!r:%{!z:svr3.ifile%s}%{z:svr3z.ifile%s}}\ + %{pg:gcrt1.o%s}%{!pg:%{posix:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}%{!posix:%{p:mcrt1.o%s}%{!p:crt1.o%s}}} \ + %{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp}" + +#define ENDFILE_SPEC "crtn.o%s" + +#undef LIB_SPEC +#define LIB_SPEC "%{posix:-lcposix} %{shlib:-lc_s} -lc -lg" diff --git a/contrib/gcc/config/i386/svr3gas.h b/contrib/gcc/config/i386/svr3gas.h new file mode 100644 index 0000000..401c766 --- /dev/null +++ b/contrib/gcc/config/i386/svr3gas.h @@ -0,0 +1,305 @@ +/* Definitions for Intel 386 running system V, using gas. + Copyright (C) 1992 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "i386/gas.h" + +/* Add stuff that normally comes from i386/sysv3.h */ + +/* longjmp may fail to restore the registers if called from the same + function that called setjmp. To compensate, the compiler avoids + putting variables in registers in functions that use both setjmp + and longjmp. */ + +#define NON_SAVING_SETJMP \ + (current_function_calls_setjmp && current_function_calls_longjmp) + +/* longjmp may fail to restore the stack pointer if the saved frame + pointer is the same as the caller's frame pointer. Requiring a frame + pointer in any function that calls setjmp or longjmp avoids this + problem, unless setjmp and longjmp are called from the same function. + Since a frame pointer will be required in such a function, it is OK + that the stack pointer is not restored. */ + +#undef FRAME_POINTER_REQUIRED +#define FRAME_POINTER_REQUIRED \ + (current_function_calls_setjmp || current_function_calls_longjmp) + +/* Modify ASM_OUTPUT_LOCAL slightly to test -msvr3-shlib, adapted to gas */ +#undef ASM_OUTPUT_LOCAL +#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ + do { \ + int align = exact_log2 (ROUNDED); \ + if (align > 2) align = 2; \ + if (TARGET_SVR3_SHLIB) \ + { \ + data_section (); \ + ASM_OUTPUT_ALIGN ((FILE), align == -1 ? 2 : align); \ + ASM_OUTPUT_LABEL ((FILE), (NAME)); \ + fprintf ((FILE), "\t.set .,.+%u\n", (ROUNDED)); \ + } \ + else \ + { \ + fputs (".lcomm ", (FILE)); \ + assemble_name ((FILE), (NAME)); \ + fprintf ((FILE), ",%u\n", (ROUNDED)); \ + } \ + } while (0) + +/* Add stuff that normally comes from i386/sysv3.h via svr3.h */ + +/* Define the actual types of some ANSI-mandated types. These + definitions should work for most SVR3 systems. */ + +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "int" + +#undef WCHAR_TYPE +#define WCHAR_TYPE "long int" + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE BITS_PER_WORD + +/* ??? This stuff is copied from config/svr3.h. In the future, + this file should be rewritten to include config/svr3.h + and override what isn't right. */ + +/* Support const sections and the ctors and dtors sections for g++. + Note that there appears to be two different ways to support const + sections at the moment. You can either #define the symbol + READONLY_DATA_SECTION (giving it some code which switches to the + readonly data section) or else you can #define the symbols + EXTRA_SECTIONS, EXTRA_SECTION_FUNCTIONS, SELECT_SECTION, and + SELECT_RTX_SECTION. We do both here just to be on the safe side. + However, use of the const section is turned off by default + unless the specific tm.h file turns it on by defining + USE_CONST_SECTION as 1. */ + +/* Define a few machine-specific details of the implementation of + constructors. + + The __CTORS_LIST__ goes in the .init section. Define CTOR_LIST_BEGIN + and CTOR_LIST_END to contribute to the .init section an instruction to + push a word containing 0 (or some equivalent of that). + + Define ASM_OUTPUT_CONSTRUCTOR to push the address of the constructor. */ + +#define USE_CONST_SECTION 0 + +#define INIT_SECTION_ASM_OP ".section\t.init" +#define FINI_SECTION_ASM_OP ".section .fini,\"x\"" +#define CONST_SECTION_ASM_OP ".section\t.rodata, \"x\"" +#define CTORS_SECTION_ASM_OP INIT_SECTION_ASM_OP +#define DTORS_SECTION_ASM_OP FINI_SECTION_ASM_OP + +/* CTOR_LIST_BEGIN and CTOR_LIST_END are machine-dependent + because they push on the stack. */ + +#ifdef STACK_GROWS_DOWNWARD + +/* Constructor list on stack is in reverse order. Go to the end of the + list and go backwards to call constructors in the right order. */ +#define DO_GLOBAL_CTORS_BODY \ +do { \ + func_ptr *p, *beg = alloca (0); \ + for (p = beg; *p; p++) \ + ; \ + while (p != beg) \ + (*--p) (); \ +} while (0) + +#else + +/* Constructor list on stack is in correct order. Just call them. */ +#define DO_GLOBAL_CTORS_BODY \ +do { \ + func_ptr *p, *beg = alloca (0); \ + for (p = beg; *p; ) \ + (*p++) (); \ +} while (0) + +#endif /* STACK_GROWS_DOWNWARD */ + +/* Add extra sections .init and .fini, in addition to .bss from att386.h. */ + +#undef EXTRA_SECTIONS +#define EXTRA_SECTIONS in_const, in_bss, in_init, in_fini + +#undef EXTRA_SECTION_FUNCTIONS +#define EXTRA_SECTION_FUNCTIONS \ + CONST_SECTION_FUNCTION \ + BSS_SECTION_FUNCTION \ + INIT_SECTION_FUNCTION \ + FINI_SECTION_FUNCTION + +#define BSS_SECTION_FUNCTION \ +void \ +bss_section () \ +{ \ + if (in_section != in_bss) \ + { \ + fprintf (asm_out_file, "\t%s\n", BSS_SECTION_ASM_OP); \ + in_section = in_bss; \ + } \ +} + +#define INIT_SECTION_FUNCTION \ +void \ +init_section () \ +{ \ + if (in_section != in_init) \ + { \ + fprintf (asm_out_file, "\t%s\n", INIT_SECTION_ASM_OP); \ + in_section = in_init; \ + } \ +} + +#define FINI_SECTION_FUNCTION \ +void \ +fini_section () \ +{ \ + if (in_section != in_fini) \ + { \ + fprintf (asm_out_file, "\t%s\n", FINI_SECTION_ASM_OP); \ + in_section = in_fini; \ + } \ +} + +#define READONLY_DATA_SECTION() const_section () + +#define CONST_SECTION_FUNCTION \ +void \ +const_section () \ +{ \ + extern void text_section(); \ + if (!USE_CONST_SECTION) \ + text_section(); \ + else if (in_section != in_const) \ + { \ + fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP); \ + in_section = in_const; \ + } \ +} + +/* The ctors and dtors sections are not normally put into use + by EXTRA_SECTIONS and EXTRA_SECTION_FUNCTIONS as defined in svr3.h, + but it can't hurt to define these macros for whatever systems use them. */ +#define CTORS_SECTION_FUNCTION \ +void \ +ctors_section () \ +{ \ + if (in_section != in_ctors) \ + { \ + fprintf (asm_out_file, "%s\n", CTORS_SECTION_ASM_OP); \ + in_section = in_ctors; \ + } \ +} + +#define DTORS_SECTION_FUNCTION \ +void \ +dtors_section () \ +{ \ + if (in_section != in_dtors) \ + { \ + fprintf (asm_out_file, "%s\n", DTORS_SECTION_ASM_OP); \ + in_section = in_dtors; \ + } \ +} + +/* This is machine-dependent + because it needs to push something on the stack. */ +#undef ASM_OUTPUT_CONSTRUCTOR + +/* A C statement (sans semicolon) to output an element in the table of + global destructors. */ +#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ + do { \ + fini_section (); \ + fprintf (FILE, "%s\t ", ASM_LONG); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + +/* A C statement or statements to switch to the appropriate + section for output of DECL. DECL is either a `VAR_DECL' node + or a constant of some sort. RELOC indicates whether forming + the initial value of DECL requires link-time relocations. */ + +#define SELECT_SECTION(DECL,RELOC) \ +{ \ + if (TREE_CODE (DECL) == STRING_CST) \ + { \ + if (! flag_writable_strings) \ + const_section (); \ + else \ + data_section (); \ + } \ + else if (TREE_CODE (DECL) == VAR_DECL) \ + { \ + if ((0 && RELOC) /* should be (flag_pic && RELOC) */ \ + || !TREE_READONLY (DECL) || TREE_SIDE_EFFECTS (DECL) \ + || !DECL_INITIAL (DECL) \ + || (DECL_INITIAL (DECL) != error_mark_node \ + && !TREE_CONSTANT (DECL_INITIAL (DECL)))) \ + data_section (); \ + else \ + const_section (); \ + } \ + else \ + const_section (); \ +} + +/* A C statement or statements to switch to the appropriate + section for output of RTX in mode MODE. RTX is some kind + of constant in RTL. The argument MODE is redundant except + in the case of a `const_int' rtx. Currently, these always + go into the const section. */ + +#define SELECT_RTX_SECTION(MODE,RTX) const_section() + +/* This is copied from i386/sysv3.h. */ + +/* Define a few machine-specific details of the implementation of + constructors. + + The __CTORS_LIST__ goes in the .init section. Define CTOR_LIST_BEGIN + and CTOR_LIST_END to contribute to the .init section an instruction to + push a word containing 0 (or some equivalent of that). + + ASM_OUTPUT_CONSTRUCTOR should be defined to push the address of the + constructor. */ + +#undef INIT_SECTION_ASM_OP +#define INIT_SECTION_ASM_OP ".section .init,\"x\"" + +#define CTOR_LIST_BEGIN \ + asm (INIT_SECTION_ASM_OP); \ + asm ("pushl $0") +#define CTOR_LIST_END CTOR_LIST_BEGIN + +#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ + do { \ + init_section (); \ + fprintf (FILE, "\tpushl $"); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) diff --git a/contrib/gcc/config/i386/svr3z.ifile b/contrib/gcc/config/i386/svr3z.ifile new file mode 100644 index 0000000..4fdbb93 --- /dev/null +++ b/contrib/gcc/config/i386/svr3z.ifile @@ -0,0 +1,45 @@ +/* + * svr3z.ifile - for collectless G++ on i386 System V. + * Leaves memory unconfigured at address 0. + * + * Install this file as $prefix/gcc-lib/TARGET/VERSION/gccz.ifile + * + * BLOCK to an offset that leaves room for many headers ( the value + * here allows for a file header, an outheader, and up to 11 section + * headers on most systems. + * BIND to an address that excludes page 0 from being mapped. The value + * used for BLOCK should be or'd into this value. Here I'm setting BLOCK + * to 0x200 and BIND to ( 0x400000 | value_used_for(BLOCK) ) + * If you are using shared libraries, watch that you don't overlap the + * address ranges assigned for shared libs. + * + * GROUP BIND to a location in the next segment. Here, the only value + * that you should change (I think) is that within NEXT, which I've set + * to my hardware segment size. You can always use a larger size, but not + * a smaller one. + */ +SECTIONS +{ + .text BIND(0x400200) BLOCK (0x200) : + { + /* plenty for room for headers */ + *(.init) + *(.text) + vfork = fork; /* I got tired of editing peoples sloppy code */ + *(.fini) + } + GROUP BIND( NEXT(0x400000) + (ADDR(.text) + (SIZEOF(.text)) % 0x1000)): + { + .data : { + __CTOR_LIST__ = . ; + . += 4 ; /* leading NULL */ + *(.ctor) + . += 4 ; /* trailing NULL */ + __DTOR_LIST__ = . ; + . += 4 ; /* leading NULL */ + *(.dtor) + . += 4 ; /* trailing NULL */ + } + .bss : { } + } +} diff --git a/contrib/gcc/config/i386/sysv3.h b/contrib/gcc/config/i386/sysv3.h new file mode 100644 index 0000000..8c5cfc4 --- /dev/null +++ b/contrib/gcc/config/i386/sysv3.h @@ -0,0 +1,124 @@ +/* Definitions for Intel 386 running system V. + Copyright (C) 1988 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + + +#include "i386/i386.h" + +/* Use default settings for system V.3. */ + +#include "svr3.h" + +/* Use the ATT assembler syntax. + This overrides at least one macro (ASM_OUTPUT_LABELREF) from svr3.h. */ + +#include "i386/att.h" + +/* Use crt1.o as a startup file and crtn.o as a closing file. */ + +#define STARTFILE_SPEC \ + "%{pg:gcrt1.o%s}%{!pg:%{posix:%{p:mcrtp1.o%s}%{!p:crtp1.o%s}}%{!posix:%{p:mcrt1.o%s}%{!p:crt1.o%s}}} crtbegin.o%s\ + %{p:-L/usr/lib/libp}%{pg:-L/usr/lib/libp}" + +/* ??? There is a suggestion that -lg is needed here. + Does anyone know whether this is right? */ +#define LIB_SPEC "%{posix:-lcposix} %{shlib:-lc_s} -lc crtend.o%s crtn.o%s" + +/* Specify predefined symbols in preprocessor. */ + +#define CPP_PREDEFINES "-Dunix -Di386 -Asystem(unix) -Asystem(svr3) -Acpu(i386) -Amachine(i386)" + +#define CPP_SPEC "%{posix:-D_POSIX_SOURCE}" + +/* Writing `int' for a bitfield forces int alignment for the structure. */ + +#define PCC_BITFIELD_TYPE_MATTERS 1 + +/* Don't write a `.optim' pseudo; this assembler doesn't handle them. */ + +#undef ASM_FILE_START_1 +#define ASM_FILE_START_1(FILE) + +/* We want to be able to get DBX debugging information via -gstabs. */ + +#undef DBX_DEBUGGING_INFO +#define DBX_DEBUGGING_INFO + +#undef PREFERRED_DEBUGGING_TYPE +#define PREFERRED_DEBUGGING_TYPE SDB_DEBUG + +/* longjmp may fail to restore the registers if called from the same + function that called setjmp. To compensate, the compiler avoids + putting variables in registers in functions that use both setjmp + and longjmp. */ + +#define NON_SAVING_SETJMP \ + (current_function_calls_setjmp && current_function_calls_longjmp) + +/* longjmp may fail to restore the stack pointer if the saved frame + pointer is the same as the caller's frame pointer. Requiring a frame + pointer in any function that calls setjmp or longjmp avoids this + problem, unless setjmp and longjmp are called from the same function. + Since a frame pointer will be required in such a function, it is OK + that the stack pointer is not restored. */ + +#undef FRAME_POINTER_REQUIRED +#define FRAME_POINTER_REQUIRED \ + (current_function_calls_setjmp || current_function_calls_longjmp) + +/* Modify ASM_OUTPUT_LOCAL slightly to test -msvr3-shlib. */ +#undef ASM_OUTPUT_LOCAL +#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ + do { \ + int align = exact_log2 (ROUNDED); \ + if (align > 2) align = 2; \ + if (TARGET_SVR3_SHLIB) \ + data_section (); \ + else \ + bss_section (); \ + ASM_OUTPUT_ALIGN ((FILE), align == -1 ? 2 : align); \ + ASM_OUTPUT_LABEL ((FILE), (NAME)); \ + fprintf ((FILE), "\t.set .,.+%u\n", (ROUNDED)); \ + } while (0) + +/* Define a few machine-specific details of the implementation of + constructors. + + The __CTORS_LIST__ goes in the .init section. Define CTOR_LIST_BEGIN + and CTOR_LIST_END to contribute to the .init section an instruction to + push a word containing 0 (or some equivalent of that). + + ASM_OUTPUT_CONSTRUCTOR should be defined to push the address of the + constructor. */ + +#undef INIT_SECTION_ASM_OP +#define INIT_SECTION_ASM_OP ".section .init,\"x\"" + +#define CTOR_LIST_BEGIN \ + asm (INIT_SECTION_ASM_OP); \ + asm ("pushl $0") +#define CTOR_LIST_END CTOR_LIST_BEGIN + +#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ + do { \ + init_section (); \ + fprintf (FILE, "\tpushl $"); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) diff --git a/contrib/gcc/config/i386/sysv4.h b/contrib/gcc/config/i386/sysv4.h new file mode 100644 index 0000000..92fcada --- /dev/null +++ b/contrib/gcc/config/i386/sysv4.h @@ -0,0 +1,245 @@ +/* Target definitions for GNU compiler for Intel 80386 running System V.4 + Copyright (C) 1991 Free Software Foundation, Inc. + + Written by Ron Guilmette (rfg@netcom.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "i386/i386.h" /* Base i386 target machine definitions */ +#include "i386/att.h" /* Use the i386 AT&T assembler syntax */ +#include "svr4.h" /* Definitions common to all SVR4 targets */ + +#undef TARGET_VERSION +#define TARGET_VERSION fprintf (stderr, " (i386 System V Release 4)"); + +/* The svr4 ABI for the i386 says that records and unions are returned + in memory. */ + +#undef RETURN_IN_MEMORY +#define RETURN_IN_MEMORY(TYPE) \ + (TYPE_MODE (TYPE) == BLKmode) + +/* Define which macros to predefine. __svr4__ is our extension. */ +/* This used to define X86, but james@bigtex.cactus.org says that + is supposed to be defined optionally by user programs--not by default. */ +#define CPP_PREDEFINES \ + "-Di386 -Dunix -D__svr4__ -Asystem(unix) -Asystem(svr4) -Acpu(i386) -Amachine(i386)" + +/* This is how to output assembly code to define a `float' constant. + We always have to use a .long pseudo-op to do this because the native + SVR4 ELF assembler is buggy and it generates incorrect values when we + try to use the .float pseudo-op instead. */ + +#undef ASM_OUTPUT_FLOAT +#define ASM_OUTPUT_FLOAT(FILE,VALUE) \ +do { long value; \ + REAL_VALUE_TO_TARGET_SINGLE ((VALUE), value); \ + if (sizeof (int) == sizeof (long)) \ + fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value); \ + else \ + fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value); \ + } while (0) + +/* This is how to output assembly code to define a `double' constant. + We always have to use a pair of .long pseudo-ops to do this because + the native SVR4 ELF assembler is buggy and it generates incorrect + values when we try to use the the .double pseudo-op instead. */ + +#undef ASM_OUTPUT_DOUBLE +#define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ +do { long value[2]; \ + REAL_VALUE_TO_TARGET_DOUBLE ((VALUE), value); \ + if (sizeof (int) == sizeof (long)) \ + { \ + fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[0]); \ + fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[1]); \ + } \ + else \ + { \ + fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[0]); \ + fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[1]); \ + } \ + } while (0) + + +#undef ASM_OUTPUT_LONG_DOUBLE +#define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ +do { long value[3]; \ + REAL_VALUE_TO_TARGET_LONG_DOUBLE ((VALUE), value); \ + if (sizeof (int) == sizeof (long)) \ + { \ + fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[0]); \ + fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[1]); \ + fprintf((FILE), "%s\t0x%x\n", ASM_LONG, value[2]); \ + } \ + else \ + { \ + fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[0]); \ + fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[1]); \ + fprintf((FILE), "%s\t0x%lx\n", ASM_LONG, value[2]); \ + } \ + } while (0) + +/* Output at beginning of assembler file. */ +/* The .file command should always begin the output. */ + +#undef ASM_FILE_START +#define ASM_FILE_START(FILE) \ + do { \ + output_file_directive (FILE, main_input_filename); \ + fprintf (FILE, "\t.version\t\"01.01\"\n"); \ + } while (0) + +/* Define the register numbers to be used in Dwarf debugging information. + The SVR4 reference port C compiler uses the following register numbers + in its Dwarf output code: + + 0 for %eax (gnu regno = 0) + 1 for %ecx (gnu regno = 2) + 2 for %edx (gnu regno = 1) + 3 for %ebx (gnu regno = 3) + 4 for %esp (gnu regno = 7) + 5 for %ebp (gnu regno = 6) + 6 for %esi (gnu regno = 4) + 7 for %edi (gnu regno = 5) + + The following three DWARF register numbers are never generated by + the SVR4 C compiler or by the GNU compilers, but SDB on x86/svr4 + believes these numbers have these meanings. + + 8 for %eip (no gnu equivalent) + 9 for %eflags (no gnu equivalent) + 10 for %trapno (no gnu equivalent) + + It is not at all clear how we should number the FP stack registers + for the x86 architecture. If the version of SDB on x86/svr4 were + a bit less brain dead with respect to floating-point then we would + have a precedent to follow with respect to DWARF register numbers + for x86 FP registers, but the SDB on x86/svr4 is so completely + broken with respect to FP registers that it is hardly worth thinking + of it as something to strive for compatibility with. + + The version of x86/svr4 SDB I have at the moment does (partially) + seem to believe that DWARF register number 11 is associated with + the x86 register %st(0), but that's about all. Higher DWARF + register numbers don't seem to be associated with anything in + particular, and even for DWARF regno 11, SDB only seems to under- + stand that it should say that a variable lives in %st(0) (when + asked via an `=' command) if we said it was in DWARF regno 11, + but SDB still prints garbage when asked for the value of the + variable in question (via a `/' command). + + (Also note that the labels SDB prints for various FP stack regs + when doing an `x' command are all wrong.) + + Note that these problems generally don't affect the native SVR4 + C compiler because it doesn't allow the use of -O with -g and + because when it is *not* optimizing, it allocates a memory + location for each floating-point variable, and the memory + location is what gets described in the DWARF AT_location + attribute for the variable in question. + + Regardless of the severe mental illness of the x86/svr4 SDB, we + do something sensible here and we use the following DWARF + register numbers. Note that these are all stack-top-relative + numbers. + + 11 for %st(0) (gnu regno = 8) + 12 for %st(1) (gnu regno = 9) + 13 for %st(2) (gnu regno = 10) + 14 for %st(3) (gnu regno = 11) + 15 for %st(4) (gnu regno = 12) + 16 for %st(5) (gnu regno = 13) + 17 for %st(6) (gnu regno = 14) + 18 for %st(7) (gnu regno = 15) +*/ + +#undef DBX_REGISTER_NUMBER +#define DBX_REGISTER_NUMBER(n) \ +((n) == 0 ? 0 \ + : (n) == 1 ? 2 \ + : (n) == 2 ? 1 \ + : (n) == 3 ? 3 \ + : (n) == 4 ? 6 \ + : (n) == 5 ? 7 \ + : (n) == 6 ? 5 \ + : (n) == 7 ? 4 \ + : ((n) >= FIRST_STACK_REG && (n) <= LAST_STACK_REG) ? (n)+3 \ + : (-1)) + +/* The routine used to output sequences of byte values. We use a special + version of this for most svr4 targets because doing so makes the + generated assembly code more compact (and thus faster to assemble) + as well as more readable. Note that if we find subparts of the + character sequence which end with NUL (and which are shorter than + STRING_LIMIT) we output those using ASM_OUTPUT_LIMITED_STRING. */ + +#undef ASM_OUTPUT_ASCII +#define ASM_OUTPUT_ASCII(FILE, STR, LENGTH) \ + do \ + { \ + register unsigned char *_ascii_bytes = (unsigned char *) (STR); \ + register unsigned char *limit = _ascii_bytes + (LENGTH); \ + register unsigned bytes_in_chunk = 0; \ + for (; _ascii_bytes < limit; _ascii_bytes++) \ + { \ + register unsigned char *p; \ + if (bytes_in_chunk >= 64) \ + { \ + fputc ('\n', (FILE)); \ + bytes_in_chunk = 0; \ + } \ + for (p = _ascii_bytes; p < limit && *p != '\0'; p++) \ + continue; \ + if (p < limit && (p - _ascii_bytes) <= STRING_LIMIT) \ + { \ + if (bytes_in_chunk > 0) \ + { \ + fputc ('\n', (FILE)); \ + bytes_in_chunk = 0; \ + } \ + ASM_OUTPUT_LIMITED_STRING ((FILE), _ascii_bytes); \ + _ascii_bytes = p; \ + } \ + else \ + { \ + if (bytes_in_chunk == 0) \ + fprintf ((FILE), "\t.byte\t"); \ + else \ + fputc (',', (FILE)); \ + fprintf ((FILE), "0x%02x", *_ascii_bytes); \ + bytes_in_chunk += 5; \ + } \ + } \ + if (bytes_in_chunk > 0) \ + fprintf ((FILE), "\n"); \ + } \ + while (0) + +/* This is how to output an element of a case-vector that is relative. + This is only used for PIC code. See comments by the `casesi' insn in + i386.md for an explanation of the expression this outputs. */ + +#undef ASM_OUTPUT_ADDR_DIFF_ELT +#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ + fprintf (FILE, "\t.long _GLOBAL_OFFSET_TABLE_+[.-%s%d]\n", LPREFIX, VALUE) + +/* Indicate that jump tables go in the text section. This is + necessary when compiling PIC code. */ + +#define JUMP_TABLES_IN_TEXT_SECTION diff --git a/contrib/gcc/config/i386/sysv4gdb.h b/contrib/gcc/config/i386/sysv4gdb.h new file mode 100644 index 0000000..dd1e8f2 --- /dev/null +++ b/contrib/gcc/config/i386/sysv4gdb.h @@ -0,0 +1,7 @@ +/* Target definitions for GNU compiler for Intel 80386 running System V.4 + with gas and gdb. */ + +/* Use stabs instead of DWARF debug format. */ +#define PREFERRED_DEBUGGING_TYPE DBX_DEBUG + +#include "i386/sysv4.h" diff --git a/contrib/gcc/config/i386/t-crtpic b/contrib/gcc/config/i386/t-crtpic new file mode 100644 index 0000000..f5dd073 --- /dev/null +++ b/contrib/gcc/config/i386/t-crtpic @@ -0,0 +1,9 @@ +# The pushl in CTOR initialization interferes with frame pointer elimination. + +# We need to use -fPIC when we are using gcc to compile the routines in +# crtstuff.c. This is only really needed when we are going to use gcc/g++ +# to produce a shared library, but since we don't know ahead of time when +# we will be doing that, we just always use -fPIC when compiling the +# routines in crtstuff.c. + +CRTSTUFF_T_CFLAGS = -fPIC -fno-omit-frame-pointer diff --git a/contrib/gcc/config/i386/t-crtstuff b/contrib/gcc/config/i386/t-crtstuff new file mode 100644 index 0000000..a202df6 --- /dev/null +++ b/contrib/gcc/config/i386/t-crtstuff @@ -0,0 +1,2 @@ +# The pushl in CTOR initialization interferes with frame pointer elimination. +CRTSTUFF_T_CFLAGS = -fno-omit-frame-pointer diff --git a/contrib/gcc/config/i386/t-i386bare b/contrib/gcc/config/i386/t-i386bare new file mode 100644 index 0000000..2970fa7 --- /dev/null +++ b/contrib/gcc/config/i386/t-i386bare @@ -0,0 +1,3 @@ +# The i386 md has all of these taken care of, according to sef. +LIBGCC1 = +CROSS_LIBGCC1 = diff --git a/contrib/gcc/config/i386/t-iscscodbx b/contrib/gcc/config/i386/t-iscscodbx new file mode 100644 index 0000000..928a758 --- /dev/null +++ b/contrib/gcc/config/i386/t-iscscodbx @@ -0,0 +1,2 @@ +# The one that comes with the system is POSIX-compliant. +LIMITS_H = diff --git a/contrib/gcc/config/i386/t-next b/contrib/gcc/config/i386/t-next new file mode 100644 index 0000000..ec6373f --- /dev/null +++ b/contrib/gcc/config/i386/t-next @@ -0,0 +1,9 @@ +# libgcc1.c is not needed, since the standard library has these functions. +LIBGCC1=libgcc1.null +CROSS_LIBGCC1=libgcc1.null + +# Specify other dirs of system header files to be fixed. +OTHER_FIXINCLUDES_DIRS= /LocalDeveloper/Headers + +# <limits.h> is sometimes in /usr/include/ansi/limits.h. +LIMITS_H_TEST = [ -f $(SYSTEM_HEADER_DIR)/limits.h -o -f $(SYSTEM_HEADER_DIR)/ansi/limits.h ] diff --git a/contrib/gcc/config/i386/t-sol2 b/contrib/gcc/config/i386/t-sol2 new file mode 100644 index 0000000..f79f6ca --- /dev/null +++ b/contrib/gcc/config/i386/t-sol2 @@ -0,0 +1,32 @@ +# we need to supply our own assembly versions of libgcc1.c files, +# since the user may not have native 'cc' available + +LIBGCC1 = libgcc1.null +CROSS_LIBGCC1 = libgcc1.null + +# gmon build rule: +gmon.o: $(srcdir)/config/i386/gmon-sol2.c $(GCC_PASSES) $(CONFIG_H) + $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(INCLUDES) \ + -c $(srcdir)/config/i386/gmon-sol2.c -o gmon.o + +# Assemble startup files. +# Apparently Sun believes that assembler files don't need comments, because no +# single ASCII character is valid (tried them all). So we manually strip out +# the comments with sed. This bug may only be in the Early Access releases. +crt1.o: $(srcdir)/config/i386/sol2-c1.asm + sed -e '/^!/d' <$(srcdir)/config/i386/sol2-c1.asm >crt1.s + $(AS) -o crt1.o crt1.s +crti.o: $(srcdir)/config/i386/sol2-ci.asm + sed -e '/^!/d' <$(srcdir)/config/i386/sol2-ci.asm >crti.s + $(AS) -o crti.o crti.s +crtn.o: $(srcdir)/config/i386/sol2-cn.asm + sed -e '/^!/d' <$(srcdir)/config/i386/sol2-cn.asm >crtn.s + $(AS) -o crtn.o crtn.s + +# We need to use -fPIC when we are using gcc to compile the routines in +# crtstuff.c. This is only really needed when we are going to use gcc/g++ +# to produce a shared library, but since we don't know ahead of time when +# we will be doing that, we just always use -fPIC when compiling the +# routines in crtstuff.c. + +CRTSTUFF_T_CFLAGS = -fPIC diff --git a/contrib/gcc/config/i386/t-svr3dbx b/contrib/gcc/config/i386/t-svr3dbx new file mode 100644 index 0000000..5171137 --- /dev/null +++ b/contrib/gcc/config/i386/t-svr3dbx @@ -0,0 +1,7 @@ +# gas 1.38.1 supporting dbx-in-coff requires a link script. + +svr3.ifile: $(srcdir)/config/i386/svr3.ifile + rm -f svr3.ifile; cp $(srcdir)/config/i386/svr3.ifile . + +svr3z.ifile: $(srcdir)/config/i386/svr3z.ifile + rm -f svr3z.ifile; cp $(srcdir)/config/i386/svr3z.ifile . diff --git a/contrib/gcc/config/i386/t-vsta b/contrib/gcc/config/i386/t-vsta new file mode 100644 index 0000000..6160b7e --- /dev/null +++ b/contrib/gcc/config/i386/t-vsta @@ -0,0 +1,2 @@ +LIBGCC1 = libgcc1.null +CROSS_LIBGCC1 = libgcc1.null diff --git a/contrib/gcc/config/i386/t-winnt b/contrib/gcc/config/i386/t-winnt new file mode 100644 index 0000000..e8e1a0a --- /dev/null +++ b/contrib/gcc/config/i386/t-winnt @@ -0,0 +1,2 @@ +winnt.o: $(srcdir)/config/i386/winnt.c + $(CC) -I. -I$(srcdir) -I$(srcdir)/config -c $(srcdir)/config/i386/winnt.c diff --git a/contrib/gcc/config/i386/unix.h b/contrib/gcc/config/i386/unix.h new file mode 100644 index 0000000..f38fe27 --- /dev/null +++ b/contrib/gcc/config/i386/unix.h @@ -0,0 +1,148 @@ +/* Definitions for Unix assembler syntax for the Intel 80386. + Copyright (C) 1988, 1994 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* This file defines the aspects of assembler syntax + that are the same for all the i386 Unix systems + (though they may differ in non-Unix systems). */ + +/* Define some concatenation macros to concatenate an opcode + and one, two or three operands. In other assembler syntaxes + they may alter the order of ther operands. */ + +/* Note that the other files fail to use these + in some of the places where they should. */ + +#if defined(__STDC__) || defined(ALMOST_STDC) +#define AS2(a,b,c) #a " " #b "," #c +#define AS2C(b,c) " " #b "," #c +#define AS3(a,b,c,d) #a " " #b "," #c "," #d +#define AS1(a,b) #a " " #b +#else +#define AS1(a,b) "a b" +#define AS2(a,b,c) "a b,c" +#define AS2C(b,c) " b,c" +#define AS3(a,b,c,d) "a b,c,d" +#endif + +/* Define macro used to output shift-double opcodes when the shift + count is in %cl. Some assemblers require %cl as an argument; + some don't. This macro controls what to do: by default, don't + print %cl. */ +#define AS3_SHIFT_DOUBLE(a,b,c,d) AS2 (a,c,d) + +/* Output the size-letter for an opcode. + CODE is the letter used in an operand spec (L, B, W, S or Q). + CH is the corresponding lower case letter + (except if CODE is `Q' then CH is `l', unless GAS_MNEMONICS). */ +#define PUT_OP_SIZE(CODE,CH,FILE) putc (CH,(FILE)) + +/* Opcode suffix for fullword insn. */ +#define L_SIZE "l" + +/* Prefix for register names in this syntax. */ +#define RP "%" + +/* Prefix for immediate operands in this syntax. */ +#define IP "$" + +/* Indirect call instructions should use `*'. */ +#define USE_STAR 1 + +/* Prefix for a memory-operand X. */ +#define PRINT_PTR(X, FILE) + +/* Delimiters that surround base reg and index reg. */ +#define ADDR_BEG(FILE) putc('(', (FILE)) +#define ADDR_END(FILE) putc(')', (FILE)) + +/* Print an index register (whose rtx is IREG). */ +#define PRINT_IREG(FILE,IREG) \ + do \ + { fputs (",", (FILE)); PRINT_REG ((IREG), 0, (FILE)); } \ + while (0) + +/* Print an index scale factor SCALE. */ +#define PRINT_SCALE(FILE,SCALE) \ + if ((SCALE) != 1) fprintf ((FILE), ",%d", (SCALE)) + +/* Print a base/index combination. + BREG is the base reg rtx, IREG is the index reg rtx, + and SCALE is the index scale factor (an integer). */ + +#define PRINT_B_I_S(BREG,IREG,SCALE,FILE) \ + { ADDR_BEG (FILE); \ + if (BREG) PRINT_REG ((BREG), 0, (FILE)); \ + if ((IREG) != 0) \ + { PRINT_IREG ((FILE), (IREG)); \ + PRINT_SCALE ((FILE), (SCALE)); } \ + ADDR_END (FILE); } + +/* Define the syntax of pseudo-ops, labels and comments. */ + +/* String containing the assembler's comment-starter. */ + +#define ASM_COMMENT_START "/" +#define COMMENT_BEGIN "/" + +/* Output to assembler file text saying following lines + may contain character constants, extra white space, comments, etc. */ + +#define ASM_APP_ON "/APP\n" + +/* Output to assembler file text saying following lines + no longer contain unusual constructs. */ + +#define ASM_APP_OFF "/NO_APP\n" + +/* Output before read-only data. */ + +#define TEXT_SECTION_ASM_OP ".text" + +/* Output before writable (initialized) data. */ + +#define DATA_SECTION_ASM_OP ".data" + +/* Output before writable (uninitialized) data. */ + +#define BSS_SECTION_ASM_OP ".bss" + +/* This is how to output a command to make the user-level label named NAME + defined for reference from other files. */ + +#define ASM_GLOBALIZE_LABEL(FILE,NAME) \ + (fputs (".globl ", FILE), assemble_name (FILE, NAME), fputs ("\n", FILE)) + +/* By default, target has a 80387, uses IEEE compatible arithmetic, + and returns float values in the 387, ie, + (TARGET_80387 | TARGET_IEEE_FP | TARGET_FLOAT_RETURNS_IN_80387) */ + +#define TARGET_DEFAULT 0301 + +/* Floating-point return values come in the FP register. */ + +#define VALUE_REGNO(MODE) \ + (GET_MODE_CLASS (MODE) == MODE_FLOAT \ + && TARGET_FLOAT_RETURNS_IN_80387 ? FIRST_FLOAT_REG : 0) + +/* 1 if N is a possible register number for a function value. */ + +#define FUNCTION_VALUE_REGNO_P(N) \ + ((N) == 0 || ((N)== FIRST_FLOAT_REG && TARGET_FLOAT_RETURNS_IN_80387)) + diff --git a/contrib/gcc/config/i386/v3gas.h b/contrib/gcc/config/i386/v3gas.h new file mode 100644 index 0000000..fe558d2 --- /dev/null +++ b/contrib/gcc/config/i386/v3gas.h @@ -0,0 +1,80 @@ +/* Definitions for Intel 386 running system V, using gas. + Copyright (C) 1992, 1995 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include <i386/gas.h> + +/* Add stuff that normally comes from i386v.h */ + +/* longjmp may fail to restore the registers if called from the same + function that called setjmp. To compensate, the compiler avoids + putting variables in registers in functions that use both setjmp + and longjmp. */ + +#define NON_SAVING_SETJMP \ + (current_function_calls_setjmp && current_function_calls_longjmp) + +/* longjmp may fail to restore the stack pointer if the saved frame + pointer is the same as the caller's frame pointer. Requiring a frame + pointer in any function that calls setjmp or longjmp avoids this + problem, unless setjmp and longjmp are called from the same function. + Since a frame pointer will be required in such a function, it is OK + that the stack pointer is not restored. */ + +#undef FRAME_POINTER_REQUIRED +#define FRAME_POINTER_REQUIRED \ + (current_function_calls_setjmp || current_function_calls_longjmp) + +/* Modify ASM_OUTPUT_LOCAL slightly to test -msvr3-shlib, adapted to gas */ +#undef ASM_OUTPUT_LOCAL +#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ + do { \ + int align = exact_log2 (ROUNDED); \ + if (align > 2) align = 2; \ + if (TARGET_SVR3_SHLIB) \ + { \ + data_section (); \ + ASM_OUTPUT_ALIGN ((FILE), align == -1 ? 2 : align); \ + ASM_OUTPUT_LABEL ((FILE), (NAME)); \ + fprintf ((FILE), "\t.set .,.+%u\n", (ROUNDED)); \ + } \ + else \ + { \ + fputs (".lcomm ", (FILE)); \ + assemble_name ((FILE), (NAME)); \ + fprintf ((FILE), ",%u\n", (ROUNDED)); \ + } \ + } while (0) + +/* Add stuff that normally comes from i386v.h via svr3.h */ + +/* Define the actual types of some ANSI-mandated types. These + definitions should work for most SVR3 systems. */ + +#undef SIZE_TYPE +#define SIZE_TYPE "unsigned int" + +#undef PTRDIFF_TYPE +#define PTRDIFF_TYPE "int" + +#undef WCHAR_TYPE +#define WCHAR_TYPE "long int" + +#undef WCHAR_TYPE_SIZE +#define WCHAR_TYPE_SIZE BITS_PER_WORD diff --git a/contrib/gcc/config/i386/vsta.h b/contrib/gcc/config/i386/vsta.h new file mode 100644 index 0000000..ee7fab9 --- /dev/null +++ b/contrib/gcc/config/i386/vsta.h @@ -0,0 +1,78 @@ +/* Configuration for an i386 running VSTa micro-kernel. + Copyright (C) 1994 Free Software Foundation, Inc. + Contributed by Rob Savoye (rob@cygnus.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define YES_UNDERSCORES + +#include "i386/gas.h" + +#ifdef CPP_PREDEFINES +#undef CPP_PREDEFINES +#endif +#define CPP_PREDEFINES "-Dunix -Di386 -DVSTA \ + -Asystem(unix) -Asystem(vsta) -Acpu(i386) -Amachine(i386)" + +#undef EXTRA_SECTIONS +#define EXTRA_SECTIONS in_ctor, in_dtor + +#undef EXTRA_SECTION_FUNCTIONS +#define EXTRA_SECTION_FUNCTIONS \ + CTOR_SECTION_FUNCTION \ + DTOR_SECTION_FUNCTION + +#define CTOR_SECTION_FUNCTION \ +void \ +ctor_section () \ +{ \ + if (in_section != in_ctor) \ + { \ + fprintf (asm_out_file, "\t.section .ctor\n"); \ + in_section = in_ctor; \ + } \ +} + +#define DTOR_SECTION_FUNCTION \ +void \ +dtor_section () \ +{ \ + if (in_section != in_dtor) \ + { \ + fprintf (asm_out_file, "\t.section .dtor\n"); \ + in_section = in_dtor; \ + } \ +} + +#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ + do { \ + ctor_section (); \ + fprintf (FILE, "%s\t", ASM_LONG); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + +#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ + do { \ + dtor_section (); \ + fprintf (FILE, "%s\t", ASM_LONG); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + + diff --git a/contrib/gcc/config/i386/win-nt.h b/contrib/gcc/config/i386/win-nt.h new file mode 100644 index 0000000..60c0bb6 --- /dev/null +++ b/contrib/gcc/config/i386/win-nt.h @@ -0,0 +1,152 @@ +/* Operating system specific defines to be used when targeting GCC for + Windows NT 3.x on an i386. + Copyright (C) 1994, 1995 Free Software Foundation, Inc. + Contributed by Douglas B. Rupp (drupp@cs.washington.edu). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define YES_UNDERSCORES + +#include "i386/gas.h" + +#ifdef CPP_PREDEFINES +#undef CPP_PREDEFINES +#endif +#define CPP_PREDEFINES "-Dunix -Di386 -DWIN32 -D_WIN32 \ + -DWINNT -D_M_IX86=300 -D_X86_=1 -D__STDC__=0 -DALMOST_STDC -D_MSC_VER=800 \ + -D__stdcall=__attribute__((__stdcall__)) \ + -D__cdecl=__attribute__((__cdecl__)) \ + -D_cdecl=__attribute__((__cdecl__)) \ + -Asystem(unix) -Asystem(winnt) -Acpu(i386) -Amachine(i386)" + +#define SIZE_TYPE "unsigned int" +#define PTRDIFF_TYPE "int" +#define WCHAR_UNSIGNED 1 +#define WCHAR_TYPE_SIZE 16 +#define WCHAR_TYPE "short unsigned int" +#undef LONG_DOUBLE_TYPE_SIZE +#define LONG_DOUBLE_TYPE_SIZE 64 +#define HAVE_ATEXIT 1 + +#undef EXTRA_SECTIONS +#define EXTRA_SECTIONS in_ctor, in_dtor + +#undef EXTRA_SECTION_FUNCTIONS +#define EXTRA_SECTION_FUNCTIONS \ + CTOR_SECTION_FUNCTION \ + DTOR_SECTION_FUNCTION + +#define CTOR_SECTION_FUNCTION \ +void \ +ctor_section () \ +{ \ + if (in_section != in_ctor) \ + { \ + fprintf (asm_out_file, "\t.section .ctor\n"); \ + in_section = in_ctor; \ + } \ +} + +#define DTOR_SECTION_FUNCTION \ +void \ +dtor_section () \ +{ \ + if (in_section != in_dtor) \ + { \ + fprintf (asm_out_file, "\t.section .dtor\n"); \ + in_section = in_dtor; \ + } \ +} + +#define ASM_OUTPUT_CONSTRUCTOR(FILE,NAME) \ + do { \ + ctor_section (); \ + fprintf (FILE, "%s\t", ASM_LONG); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + +#define ASM_OUTPUT_DESTRUCTOR(FILE,NAME) \ + do { \ + dtor_section (); \ + fprintf (FILE, "%s\t", ASM_LONG); \ + assemble_name (FILE, NAME); \ + fprintf (FILE, "\n"); \ + } while (0) + +/* Define this macro if references to a symbol must be treated + differently depending on something about the variable or + function named by the symbol (such as what section it is in). + + On i386, if using PIC, mark a SYMBOL_REF for a non-global symbol + so that we may access it directly in the GOT. + + On i386 running Windows NT, modify the assembler name with a suffix + consisting of an atsign (@) followed by string of digits that represents + the number of bytes of arguments passed to the function, if it has the + attribute STDCALL. */ + +#ifdef ENCODE_SECTION_INFO +#undef ENCODE_SECTION_INFO +#define ENCODE_SECTION_INFO(DECL) \ +do \ + { \ + if (flag_pic) \ + { \ + rtx rtl = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ + ? TREE_CST_RTL (DECL) : DECL_RTL (DECL)); \ + SYMBOL_REF_FLAG (XEXP (rtl, 0)) \ + = (TREE_CODE_CLASS (TREE_CODE (DECL)) != 'd' \ + || ! TREE_PUBLIC (DECL)); \ + } \ + if (TREE_CODE (DECL) == FUNCTION_DECL) \ + if (lookup_attribute ("stdcall", \ + TYPE_ATTRIBUTES (TREE_TYPE (DECL)))) \ + XEXP (DECL_RTL (DECL), 0) = \ + gen_rtx (SYMBOL_REF, Pmode, gen_stdcall_suffix (DECL)); \ + } \ +while (0) +#endif + +/* The global __fltused is necessary to cause the printf/scanf routines + for outputting/inputting floating point numbers to be loaded. Since this + is kind of hard to detect, we just do it all the time. */ + +#ifdef ASM_FILE_START +#undef ASM_FILE_START +#endif +#define ASM_FILE_START(FILE) \ + do { fprintf (FILE, "\t.file\t"); \ + output_quoted_string (FILE, dump_base_name); \ + fprintf (FILE, "\n"); \ + fprintf (FILE, ".global\t__fltused\n"); \ + } while (0) + +/* if the switch "-mwindows" is passed to ld, then specify to the Microsoft + linker the proper switches and libraries to build a graphical program */ + +#undef LIB_SPEC +#define LIB_SPEC "%{mwindows:-subsystem windows -e _WinMainCRTStartup \ + USER32.LIB%s GDI32.LIB%s COMDLG32.LIB%s WINSPOOL.LIB%s} \ + %{!mwindows:-subsystem console -e _mainCRTStartup} \ + %{mcrtmt:LIBCMT.LIB%s KERNEL32.LIB%s ADVAPI32.LIB%s} \ + %{!mcrtmt:LIBC.LIB%s KERNEL32.LIB%s ADVAPI32.LIB%s} \ + %{v}" + +#include "winnt/win-nt.h" + diff --git a/contrib/gcc/config/i386/winnt.c b/contrib/gcc/config/i386/winnt.c new file mode 100644 index 0000000..3a7ebf1 --- /dev/null +++ b/contrib/gcc/config/i386/winnt.c @@ -0,0 +1,60 @@ +/* Subroutines for insn-output.c for Windows NT. + Contributed by Douglas Rupp (drupp@cs.washington.edu) + Copyright (C) 1995 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include <stdio.h> +#include "config.h" +#include "rtl.h" +#include "regs.h" +#include "hard-reg-set.h" +#include "output.h" +#include "tree.h" +#include "flags.h" + +/* Return string which is the former assembler name modified with a + suffix consisting of an atsign (@) followed by the number of bytes of + arguments */ + +char * +gen_stdcall_suffix (decl) + tree decl; +{ + int total = 0; + char *asmname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); + char *newsym; + + if (TYPE_ARG_TYPES (TREE_TYPE (decl))) + if (TREE_VALUE (tree_last (TYPE_ARG_TYPES (TREE_TYPE (decl)))) + == void_type_node) + { + tree formal_type = TYPE_ARG_TYPES (TREE_TYPE (decl)); + + while (TREE_VALUE (formal_type) != void_type_node) + { + total += TREE_INT_CST_LOW (TYPE_SIZE (TREE_VALUE (formal_type))); + formal_type = TREE_CHAIN (formal_type); + } + } + + newsym = xmalloc (strlen (asmname) + 10); + sprintf (newsym, "%s@%d", asmname, total/BITS_PER_UNIT); + return IDENTIFIER_POINTER (get_identifier (newsym)); +} + diff --git a/contrib/gcc/config/i386/x-aix b/contrib/gcc/config/i386/x-aix new file mode 100644 index 0000000..b191e48 --- /dev/null +++ b/contrib/gcc/config/i386/x-aix @@ -0,0 +1,12 @@ +# There is an alloca in -lbsd, but it is limited to 32K +ALLOCA = alloca.o + +# If you are running out of memory while compiling gcc, with the standard +# /bin/cc uncomment MALLOCLIB line. That version of malloc is slower but +# has less overhead than the one in libc. +#MALLOCLIB = -lmalloc + +# Uncomment out the next line if you want to link with the shareable libc_s. +#CLIB_S = -lc_s + +CLIB = -lld $(MALLOCLIB) $(CLIB_S) diff --git a/contrib/gcc/config/i386/x-freebsd b/contrib/gcc/config/i386/x-freebsd new file mode 100644 index 0000000..a9b13ba --- /dev/null +++ b/contrib/gcc/config/i386/x-freebsd @@ -0,0 +1,3 @@ +# Don't run fixproto +STMP_FIXPROTO = +CLIB=-lgnumalloc diff --git a/contrib/gcc/config/i386/x-isc b/contrib/gcc/config/i386/x-isc new file mode 100644 index 0000000..ea65ec8 --- /dev/null +++ b/contrib/gcc/config/i386/x-isc @@ -0,0 +1,3 @@ +CLIB = -lPW -lcposix +X_CFLAGS = -D_POSIX_SOURCE +ENQUIRE_LDFLAGS = -posix $(LDFLAGS) diff --git a/contrib/gcc/config/i386/x-isc3 b/contrib/gcc/config/i386/x-isc3 new file mode 100644 index 0000000..527cca8 --- /dev/null +++ b/contrib/gcc/config/i386/x-isc3 @@ -0,0 +1,4 @@ +CLIB = -lPW +# One person said it needs -DPOSIX_JC, but daa@CERF.NET says no. +X_CFLAGS = -D_SYSV3 -Xp +ENQUIRE_LDFLAGS = $(LDFLAGS) diff --git a/contrib/gcc/config/i386/x-ncr3000 b/contrib/gcc/config/i386/x-ncr3000 new file mode 100644 index 0000000..4ae168b --- /dev/null +++ b/contrib/gcc/config/i386/x-ncr3000 @@ -0,0 +1,34 @@ +# Makefile additions for the NCR3000 as host system. + +# Using -O with the AT&T compiler fails, with a message about a missing +# /usr/ccs/lib/optim pass. So override the default in Makefile.in + +CCLIBFLAGS= + +## Supposedly not needed now that xm-sysv4.h includes alloc.h for Metaware. +### NCR3000 ships with a MetaWare compiler installed as CC, which chokes and +### dies all over the place on GCC source. However, the AT&T compiler, +### crusty as it is, can be used to bootstrap GCC. It can be found in +### /usr/ccs/ATT/cc. It is also used to compile the things that should +### not be compiled with GCC. +## +##CC = /usr/ccs/ATT/cc +##OLDCC = /usr/ccs/ATT/cc + +# The rest is just x-i386v4. + +# Some versions of SVR4 have an alloca in /usr/ucblib/libucb.a, and if we are +# careful to link that in after libc we can use it, but since newer versions of +# SVR4 are dropping libucb, it is better to just use the portable C version for +# bootstrapping. Do this by defining ALLOCA. + +ALLOCA = alloca.o + +# We used to build all stages *without* shared libraries because that may make +# debugging the compiler easier (until there is a GDB which supports +# both Dwarf *and* svr4 shared libraries). + +# But james@bigtex.cactus.org says that redefining GCC_CFLAGS causes trouble, +# and that it is easy enough to debug using shared libraries. +# CCLIBFLAGS=-Bstatic -dn -g +# GCC_CFLAGS=-static -g -O2 -B./ diff --git a/contrib/gcc/config/i386/x-next b/contrib/gcc/config/i386/x-next new file mode 100644 index 0000000..a16b918 --- /dev/null +++ b/contrib/gcc/config/i386/x-next @@ -0,0 +1,3 @@ +# Make assignments for compiling on NeXT with their compiler version. +CC=cc -traditional-cpp +OLDCC=cc -traditional-cpp diff --git a/contrib/gcc/config/i386/x-osfrose b/contrib/gcc/config/i386/x-osfrose new file mode 100644 index 0000000..a419bdb --- /dev/null +++ b/contrib/gcc/config/i386/x-osfrose @@ -0,0 +1,31 @@ +# Define CC and OLDCC as the same, so that the tests: +# if [ x"$(OLDCC)" = x"$(CC)" ] ... +# +# will succeed (if OLDCC != CC, it is assumed that GCC is +# being used in secondary stage builds). + +BUILD = +CC = $(OLDCC) +CLIB = -lld +X_CFLAGS = $(DEB_OPT) $(MSTATS) $(SHLIB) $(X_DEFINES) +X_CFLAGS_NODEBUG = $(NO_DEBUG) $(MSTATS) $(OPT) $(PROFILE) $(SHLIB) $(X_DEFINES) $(XCFLAGS) +CPP_ABORT = # -Dabort=fancy_abort +CPPFLAGS = $(CPP_ABORT) $(SYSTEM_INCLUDES) +DEB_OPT = $(OPT) $(DEBUG) $(PROFILE) +DEBUG = +DEBUG_COLLECT = # -DDEBUG +CCLIBFLAGS = -O -DNO_HALF_PIC +GCC_CFLAGS = $(INTERNAL_CFLAGS) $(X_CFLAGS) $(T_CFLAGS) $(CFLAGS) -B./ -DPOSIX -DNO_HALF_PIC +INSTALL = installbsd -c +LDFLAGS = +MSTATS = # -mstats +OLDCC = /usr/ccs/gcc/gcc +OPT = -O +PROFILE = +SHLIB = -pic-none +SYSTEM_INCLUDES = # -I${BUILD}/usr/include +X_DEFINES = -Dvfork=fork + +libdir = /usr/ccs +mandir = /usr/ccs/gcc/$(target)/$(version) +bindir = /usr/ccs/gcc/$(target)/$(version) diff --git a/contrib/gcc/config/i386/x-sco b/contrib/gcc/config/i386/x-sco new file mode 100644 index 0000000..f7f14e9 --- /dev/null +++ b/contrib/gcc/config/i386/x-sco @@ -0,0 +1,7 @@ +RANLIB = : +RANLIB_TEST = false +CC = rcc $(RCCFLAGS) +OLDCC = rcc $(RCCFLAGS) +RCCFLAGS = -Dunix -Di386 -DM_UNIX -DM_I386 -DNULL=0 +CCLIBFLAGS = +CLIB = -lmalloc -lPW diff --git a/contrib/gcc/config/i386/x-sco4 b/contrib/gcc/config/i386/x-sco4 new file mode 100644 index 0000000..be6080f --- /dev/null +++ b/contrib/gcc/config/i386/x-sco4 @@ -0,0 +1,10 @@ +RANLIB = : +RANLIB_TEST = false +CC = rcc $(RCCFLAGS) +OLDCC = rcc $(RCCFLAGS) +RCCFLAGS = -Dunix -Di386 -DM_UNIX -DM_I386 -DNULL=0 +CCLIBFLAGS = +CLIB = -lmalloc -lPW + +# See all the declarations. +FIXPROTO_DEFINES = -D_XOPEN_SOURCE diff --git a/contrib/gcc/config/i386/x-sysv3 b/contrib/gcc/config/i386/x-sysv3 new file mode 100644 index 0000000..a1391df --- /dev/null +++ b/contrib/gcc/config/i386/x-sysv3 @@ -0,0 +1 @@ +CLIB=-lPW diff --git a/contrib/gcc/config/i386/x-vsta b/contrib/gcc/config/i386/x-vsta new file mode 100644 index 0000000..e2279a4 --- /dev/null +++ b/contrib/gcc/config/i386/x-vsta @@ -0,0 +1 @@ +CLIB=-lm diff --git a/contrib/gcc/config/i386/xm-aix.h b/contrib/gcc/config/i386/xm-aix.h new file mode 100644 index 0000000..5e5d402 --- /dev/null +++ b/contrib/gcc/config/i386/xm-aix.h @@ -0,0 +1,37 @@ +/* Configuration for GNU C-compiler for IBM PS/2 running AIX/386. + Copyright (C) 1988, 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define USG + +#undef TRUE +#undef FALSE + +#include "i386/xm-i386.h" + +#define bcopy(a,b,c) memcpy (b,a,c) +#define bzero(a,b) memset (a,0,b) +#define bcmp(a,b,c) memcmp (a,b,c) + +/* If not compiled with GNU C, use the portable alloca. */ +#ifndef __GNUC__ +#define USE_C_ALLOCA +#endif + +#define HAVE_PUTENV diff --git a/contrib/gcc/config/i386/xm-bsd386.h b/contrib/gcc/config/i386/xm-bsd386.h new file mode 100644 index 0000000..9deb7ef --- /dev/null +++ b/contrib/gcc/config/i386/xm-bsd386.h @@ -0,0 +1,6 @@ +/* Configuration for GCC for Intel i386 running BSDI's BSD/386 as host. */ + +#include "i386/xm-i386.h" + +#define HAVE_STRERROR + diff --git a/contrib/gcc/config/i386/xm-dos.h b/contrib/gcc/config/i386/xm-dos.h new file mode 100644 index 0000000..1dd0c01 --- /dev/null +++ b/contrib/gcc/config/i386/xm-dos.h @@ -0,0 +1,20 @@ +#include "i386/xm-i386.h" + +/* Inhibit cccp.c's definition of putenv. */ +#define HAVE_PUTENV + +/* Use semicolons to separate elements of a path. */ +#define PATH_SEPARATOR ';' + +/* Use backslashs to separate levels of directory. */ +#define DIR_SEPARATOR '\\' + +/* Suffix for executable file names. */ +#define EXECUTABLE_SUFFIX ".exe" + +#define MKTEMP_EACH_FILE 1 + +#define NO_PRECOMPILES 1 + +/* sys_errlist proto in cccp.c doesn't match djgpp */ +#define HAVE_STRERROR diff --git a/contrib/gcc/config/i386/xm-freebsd.h b/contrib/gcc/config/i386/xm-freebsd.h new file mode 100644 index 0000000..007a609 --- /dev/null +++ b/contrib/gcc/config/i386/xm-freebsd.h @@ -0,0 +1,4 @@ +/* Configuration for GCC for Intel i386 running FreeBSD as host. */ + +#include <i386/xm-i386.h> +#include <xm-freebsd.h> diff --git a/contrib/gcc/config/i386/xm-gnu.h b/contrib/gcc/config/i386/xm-gnu.h new file mode 100644 index 0000000..0b5985f --- /dev/null +++ b/contrib/gcc/config/i386/xm-gnu.h @@ -0,0 +1,5 @@ +/* Configuration for GCC for Intel i386 running GNU as host. */ + +#include <i386/xm-i386.h> +#include <xm-gnu.h> + diff --git a/contrib/gcc/config/i386/xm-i386.h b/contrib/gcc/config/i386/xm-i386.h new file mode 100644 index 0000000..acc1657 --- /dev/null +++ b/contrib/gcc/config/i386/xm-i386.h @@ -0,0 +1,43 @@ +/* Configuration for GNU C-compiler for Intel 80386. + Copyright (C) 1988, 1993 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#ifndef i386 +#define i386 +#endif + +/* #defines that need visibility everywhere. */ +#define FALSE 0 +#define TRUE 1 + +/* This describes the machine the compiler is hosted on. */ +#define HOST_BITS_PER_CHAR 8 +#define HOST_BITS_PER_SHORT 16 +#define HOST_BITS_PER_INT 32 +#define HOST_BITS_PER_LONG 32 +#define HOST_BITS_PER_LONGLONG 64 + +/* Arguments to use with `exit'. */ +#define SUCCESS_EXIT_CODE 0 +#define FATAL_EXIT_CODE 33 + +/* target machine dependencies. + tm.h is a symbolic link to the actual target specific file. */ + +#include "tm.h" diff --git a/contrib/gcc/config/i386/xm-isc.h b/contrib/gcc/config/i386/xm-isc.h new file mode 100644 index 0000000..7a0a47c --- /dev/null +++ b/contrib/gcc/config/i386/xm-isc.h @@ -0,0 +1,6 @@ +#include "i386/xm-sysv3.h" + +#ifndef REAL_ARITHMETIC +#define REAL_VALUE_ATOF(x, mode) strtod ((x), (char **)0) +extern double strtod (); +#endif diff --git a/contrib/gcc/config/i386/xm-linux.h b/contrib/gcc/config/i386/xm-linux.h new file mode 100644 index 0000000..42f097d --- /dev/null +++ b/contrib/gcc/config/i386/xm-linux.h @@ -0,0 +1,24 @@ +/* Configuration for GCC for Intel i386 running Linux. + Copyright (C) 1993, 1994, 1995 Free Software Foundation, Inc. + Contributed by H.J. Lu (hjl@nynexst.com) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include <i386/xm-i386.h> +#include <xm-linux.h> + diff --git a/contrib/gcc/config/i386/xm-lynx.h b/contrib/gcc/config/i386/xm-lynx.h new file mode 100644 index 0000000..359e41b --- /dev/null +++ b/contrib/gcc/config/i386/xm-lynx.h @@ -0,0 +1,33 @@ +/* Configuration for GNU C-compiler for i386 platforms running LynxOS. + Copyright (C) 1995 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include <xm-lynx.h> + +/* This describes the machine the compiler is hosted on. */ +#define HOST_BITS_PER_CHAR 8 +#define HOST_BITS_PER_SHORT 16 +#define HOST_BITS_PER_INT 32 +#define HOST_BITS_PER_LONG 32 +#define HOST_BITS_PER_LONGLONG 64 + +/* target machine dependencies. + tm.h is a symbolic link to the actual target specific file. */ + +#include "tm.h" diff --git a/contrib/gcc/config/i386/xm-netbsd.h b/contrib/gcc/config/i386/xm-netbsd.h new file mode 100644 index 0000000..3a9f324 --- /dev/null +++ b/contrib/gcc/config/i386/xm-netbsd.h @@ -0,0 +1,4 @@ +/* Configuration for GCC for Intel i386 running NetBSD as host. */ + +#include <i386/xm-i386.h> +#include <xm-netbsd.h> diff --git a/contrib/gcc/config/i386/xm-next.h b/contrib/gcc/config/i386/xm-next.h new file mode 100644 index 0000000..bf90328 --- /dev/null +++ b/contrib/gcc/config/i386/xm-next.h @@ -0,0 +1,5 @@ +#include "i386/xm-i386.h" + +/* malloc does better with chunks the size of a page. */ + +#define OBSTACK_CHUNK_SIZE (getpagesize ()) diff --git a/contrib/gcc/config/i386/xm-os2.h b/contrib/gcc/config/i386/xm-os2.h new file mode 100644 index 0000000..5ff2899 --- /dev/null +++ b/contrib/gcc/config/i386/xm-os2.h @@ -0,0 +1,57 @@ +/* Configuration for GNU compiler + for an Intel i386 or later processor running OS/2 2.x. + Copyright (C) 1993, 1994, 1995 Free Software Foundation, Inc. + Contributed by Samuel Figueroa (figueroa@cs.nyu.edu) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#ifndef OS2 +#define OS2 +#endif + +#ifdef __IBMC__ +#include <stdlib.h> /* this defines alloca */ +#define USG +#define ONLY_INT_FIELDS +#define HAVE_PUTENV +#define USE_PROTOTYPES 1 +#define bcmp(a,b,c) memcmp (a,b,c) +#define bcopy(a,b,c) memcpy (b,a,c) +#define bzero(a,b) memset (a,0,b) +#define index strchr +#define rindex strrchr +#define strcasecmp stricmp +#define kill(a,b) raise(b) +#define mktemp tmpnam +#else +#define ____386BSD____ +int spawnv (int modeflag, char *path, char *argv[]); +int spawnvp (int modeflag, char *path, char *argv[]); +#endif /* __IBMC__ */ + +#ifndef PATH_SEPARATOR +#define PATH_SEPARATOR ';' +#endif +#ifndef DIR_SEPARATOR +#define DIR_SEPARATOR '\\' +#endif + +#define EXECUTABLE_SUFFIX ".exe" +#define OBJECT_SUFFIX ".obj" + +#include "i386/xm-i386.h" diff --git a/contrib/gcc/config/i386/xm-osf.h b/contrib/gcc/config/i386/xm-osf.h new file mode 100644 index 0000000..fda50d9 --- /dev/null +++ b/contrib/gcc/config/i386/xm-osf.h @@ -0,0 +1,32 @@ +/* Configuration for GNU C-compiler for 386 running OSF/1 + Copyright (C) 1994 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#undef TRUE +#undef FALSE + +#include "i386/xm-i386.h" + +#define bcopy(a,b,c) memcpy (b,a,c) +#define bzero(a,b) memset (a,0,b) +#define bcmp(a,b,c) memcmp (a,b,c) + +#define HAVE_PUTENV +#define HAVE_VPRINTF + diff --git a/contrib/gcc/config/i386/xm-sco.h b/contrib/gcc/config/i386/xm-sco.h new file mode 100644 index 0000000..01a63d90 --- /dev/null +++ b/contrib/gcc/config/i386/xm-sco.h @@ -0,0 +1,22 @@ +/* Configuration for GCC for Intel i386 running SCO. */ + +#include "i386/xm-sysv3.h" + +/* On SCO 3.2.1, ldexp rejects values outside [0.5, 1). */ + +#define BROKEN_LDEXP + +/* Big buffers improve performance. */ + +#define IO_BUFFER_SIZE (0x8000 - 1024) + +/* SCO has a very small ARG_MAX. */ +#define SMALL_ARG_MAX + +#ifndef __GNUC__ +/* The SCO compiler gets it wrong, and treats enumerated bitfields + as signed quantities, making it impossible to use an 8-bit enum + for compiling GNU C++. */ +#define ONLY_INT_FIELDS 1 +#define CODE_FIELD_BUG 1 +#endif diff --git a/contrib/gcc/config/i386/xm-sun.h b/contrib/gcc/config/i386/xm-sun.h new file mode 100644 index 0000000..d2e714e --- /dev/null +++ b/contrib/gcc/config/i386/xm-sun.h @@ -0,0 +1,27 @@ +/* Configuration for GNU C-compiler for Intel 80386 running SunOS 4.0. + Copyright (C) 1988 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define USG + +#include "i386/xm-i386.h" + +#define bcopy(a,b,c) memcpy (b,a,c) +#define bzero(a,b) memset (a,0,b) +#define bcmp(a,b,c) memcmp (a,b,c) diff --git a/contrib/gcc/config/i386/xm-sysv3.h b/contrib/gcc/config/i386/xm-sysv3.h new file mode 100644 index 0000000..72078bb --- /dev/null +++ b/contrib/gcc/config/i386/xm-sysv3.h @@ -0,0 +1,4 @@ +/* Configuration for GCC for Intel i386 running System V Release 3. */ + +#include "i386/xm-i386.h" +#include "xm-svr3.h" diff --git a/contrib/gcc/config/i386/xm-sysv4.h b/contrib/gcc/config/i386/xm-sysv4.h new file mode 100644 index 0000000..49d52b4 --- /dev/null +++ b/contrib/gcc/config/i386/xm-sysv4.h @@ -0,0 +1,16 @@ +/* Configuration for GCC for Intel i386 running System V Release 4. */ + +#include "i386/xm-i386.h" +#include "xm-svr4.h" + +/* If not compiled with GNU C, use the portable alloca. */ +#ifndef __GNUC__ +#define USE_C_ALLOCA +#endif +#ifdef __HIGHC__ +#include <alloca.h> /* for MetaWare High-C on NCR System 3000 */ +#endif + +/* Univel, at least, has a small ARG_MAX. Defining this is harmless + except for causing extra stat calls in the driver program. */ +#define SMALL_ARG_MAX diff --git a/contrib/gcc/config/i386/xm-vsta.h b/contrib/gcc/config/i386/xm-vsta.h new file mode 100644 index 0000000..bb333ae --- /dev/null +++ b/contrib/gcc/config/i386/xm-vsta.h @@ -0,0 +1,26 @@ +/* Configuration for GNU C-compiler for Intel 80386. + Copyright (C) 1994 Free Software Foundation, Inc. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#define NO_STAB_H + +#include "i386/xm-i386.h" + +/* Use semicolons to separate elements of a path. */ +#define PATH_SEPARATOR ';' diff --git a/contrib/gcc/config/i386/xm-winnt.h b/contrib/gcc/config/i386/xm-winnt.h new file mode 100644 index 0000000..d36d2cd --- /dev/null +++ b/contrib/gcc/config/i386/xm-winnt.h @@ -0,0 +1,24 @@ +/* Configuration for GNU compiler + for an Intel i386 or later processor running Windows NT 3.x. + Copyright (C) 1994 Free Software Foundation, Inc. + Contributed by Douglas B. Rupp (drupp@cs.washington.edu) + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#include "winnt/xm-winnt.h" +#include "i386/xm-i386.h" |
