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| author | kan <kan@FreeBSD.org> | 2004-07-28 03:11:36 +0000 |
|---|---|---|
| committer | kan <kan@FreeBSD.org> | 2004-07-28 03:11:36 +0000 |
| commit | 5e00ec74d8ce58f99801200d4d3d0412c7cc1b28 (patch) | |
| tree | 052f4bb635f2bea2c5e350bd60c902be100a0d1e /contrib/gcc/config/arm | |
| parent | 87b8398a7d9f9bf0e28bbcd54a4fc27db2125f38 (diff) | |
| download | FreeBSD-src-5e00ec74d8ce58f99801200d4d3d0412c7cc1b28.zip FreeBSD-src-5e00ec74d8ce58f99801200d4d3d0412c7cc1b28.tar.gz | |
Gcc 3.4.2 20040728.
Diffstat (limited to 'contrib/gcc/config/arm')
49 files changed, 13362 insertions, 3986 deletions
diff --git a/contrib/gcc/config/arm/README-interworking b/contrib/gcc/config/arm/README-interworking index de8b278..0a03cdc 100644 --- a/contrib/gcc/config/arm/README-interworking +++ b/contrib/gcc/config/arm/README-interworking @@ -404,7 +404,7 @@ Instead the pseudo op is attached to a new label .real_start_of_<name> (where <name> is the name of the function) which indicates the start of the Thumb code. This does have the interesting side effect in that if this function is now called from a Thumb mode piece of code -outsside of the current file, the linker will generate a calling stub +outside of the current file, the linker will generate a calling stub to switch from Thumb mode into ARM mode, and then this is immediately overridden by the function's header which switches back into Thumb mode. diff --git a/contrib/gcc/config/arm/aof.h b/contrib/gcc/config/arm/aof.h index 965337c..5a6ab2c 100644 --- a/contrib/gcc/config/arm/aof.h +++ b/contrib/gcc/config/arm/aof.h @@ -1,24 +1,24 @@ /* Definitions of target machine for GNU compiler, for Advanced RISC Machines ARM compilation, AOF Assembler. - Copyright (C) 1995, 1996, 1997, 2000 Free Software Foundation, Inc. + Copyright (C) 1995, 1996, 1997, 2000, 2003 Free Software Foundation, Inc. Contributed by Richard Earnshaw (rearnsha@armltd.co.uk) -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ @@ -27,7 +27,7 @@ Boston, MA 02111-1307, USA. */ #define LINK_LIBGCC_SPECIAL 1 #define LINK_SPEC "%{aof} %{bin} %{aif} %{ihf} %{shl,*} %{reent*} %{split} \ - %{ov*,*} %{reloc*} -nodebug" + %{ov*} %{reloc*} -nodebug" #define STARTFILE_SPEC "crtbegin.o%s" @@ -59,64 +59,70 @@ Boston, MA 02111-1307, USA. */ #define EXTRA_SECTIONS in_zero_init, in_common #define EXTRA_SECTION_FUNCTIONS \ -ZERO_INIT_SECTION \ -COMMON_SECTION + ZERO_INIT_SECTION \ + COMMON_SECTION #define ZERO_INIT_SECTION \ -void \ -zero_init_section () \ -{ \ - static int zero_init_count = 1; \ - if (in_section != in_zero_init) \ - { \ - fprintf (asm_out_file, "\tAREA |C$$zidata%d|,NOINIT\n", \ - zero_init_count++); \ - in_section = in_zero_init; \ - } \ -} + void \ + zero_init_section () \ + { \ + static int zero_init_count = 1; \ + \ + if (in_section != in_zero_init) \ + { \ + fprintf (asm_out_file, "\tAREA |C$$zidata%d|,NOINIT\n", \ + zero_init_count++); \ + in_section = in_zero_init; \ + } \ + } /* Used by ASM_OUTPUT_COMMON (below) to tell varasm.c that we've changed areas. */ #define COMMON_SECTION \ -void \ -common_section () \ -{ \ - if (in_section != in_common) \ - { \ + void \ + common_section () \ + { \ + if (in_section != in_common) \ in_section = in_common; \ - } \ -} -#define CTOR_LIST_BEGIN \ -asm (CTORS_SECTION_ASM_OP); \ -extern func_ptr __CTOR_END__[1]; \ -func_ptr __CTOR_LIST__[1] = {__CTOR_END__}; + } -#define CTOR_LIST_END \ -asm (CTORS_SECTION_ASM_OP); \ -func_ptr __CTOR_END__[1] = { (func_ptr) 0 }; +#define CTOR_LIST_BEGIN \ + asm (CTORS_SECTION_ASM_OP); \ + extern func_ptr __CTOR_END__[1]; \ + func_ptr __CTOR_LIST__[1] = {__CTOR_END__}; -#define DO_GLOBAL_CTORS_BODY \ -do { \ - func_ptr *ptr = __CTOR_LIST__ + 1; \ - while (*ptr) \ - (*ptr++) (); \ -} while (0) +#define CTOR_LIST_END \ + asm (CTORS_SECTION_ASM_OP); \ + func_ptr __CTOR_END__[1] = { (func_ptr) 0 }; -#define DTOR_LIST_BEGIN \ -asm (DTORS_SECTION_ASM_OP); \ -extern func_ptr __DTOR_END__[1]; \ -func_ptr __DTOR_LIST__[1] = {__DTOR_END__}; +#define DO_GLOBAL_CTORS_BODY \ + do \ + { \ + func_ptr *ptr = __CTOR_LIST__ + 1; \ + \ + while (*ptr) \ + (*ptr++) (); \ + } \ + while (0) -#define DTOR_LIST_END \ -asm (DTORS_SECTION_ASM_OP); \ -func_ptr __DTOR_END__[1] = { (func_ptr) 0 }; +#define DTOR_LIST_BEGIN \ + asm (DTORS_SECTION_ASM_OP); \ + extern func_ptr __DTOR_END__[1]; \ + func_ptr __DTOR_LIST__[1] = {__DTOR_END__}; -#define DO_GLOBAL_DTORS_BODY \ -do { \ - func_ptr *ptr = __DTOR_LIST__ + 1; \ - while (*ptr) \ - (*ptr++) (); \ -} while (0) +#define DTOR_LIST_END \ + asm (DTORS_SECTION_ASM_OP); \ + func_ptr __DTOR_END__[1] = { (func_ptr) 0 }; + +#define DO_GLOBAL_DTORS_BODY \ + do \ + { \ + func_ptr *ptr = __DTOR_LIST__ + 1; \ + \ + while (*ptr) \ + (*ptr++) (); \ + } \ + while (0) /* We really want to put Thumb tables in a read-only data section, but switching to another section during function output is not @@ -124,68 +130,18 @@ do { \ whole table generation until the end of the function. */ #define JUMP_TABLES_IN_TEXT_SECTION 1 -#ifndef ARM_OS_NAME -#define ARM_OS_NAME "(generic)" -#endif - -/* For the AOF linker, we need to reference __main to force the standard - library to get linked in. */ - -#define ASM_FILE_START(STREAM) \ -{ \ - fprintf ((STREAM), "%s Generated by gcc %s for ARM/%s\n", \ - ASM_COMMENT_START, version_string, ARM_OS_NAME); \ - fprintf ((STREAM), "__r0\tRN\t0\n"); \ - fprintf ((STREAM), "__a1\tRN\t0\n"); \ - fprintf ((STREAM), "__a2\tRN\t1\n"); \ - fprintf ((STREAM), "__a3\tRN\t2\n"); \ - fprintf ((STREAM), "__a4\tRN\t3\n"); \ - fprintf ((STREAM), "__v1\tRN\t4\n"); \ - fprintf ((STREAM), "__v2\tRN\t5\n"); \ - fprintf ((STREAM), "__v3\tRN\t6\n"); \ - fprintf ((STREAM), "__v4\tRN\t7\n"); \ - fprintf ((STREAM), "__v5\tRN\t8\n"); \ - fprintf ((STREAM), "__v6\tRN\t9\n"); \ - fprintf ((STREAM), "__sl\tRN\t10\n"); \ - fprintf ((STREAM), "__fp\tRN\t11\n"); \ - fprintf ((STREAM), "__ip\tRN\t12\n"); \ - fprintf ((STREAM), "__sp\tRN\t13\n"); \ - fprintf ((STREAM), "__lr\tRN\t14\n"); \ - fprintf ((STREAM), "__pc\tRN\t15\n"); \ - fprintf ((STREAM), "__f0\tFN\t0\n"); \ - fprintf ((STREAM), "__f1\tFN\t1\n"); \ - fprintf ((STREAM), "__f2\tFN\t2\n"); \ - fprintf ((STREAM), "__f3\tFN\t3\n"); \ - fprintf ((STREAM), "__f4\tFN\t4\n"); \ - fprintf ((STREAM), "__f5\tFN\t5\n"); \ - fprintf ((STREAM), "__f6\tFN\t6\n"); \ - fprintf ((STREAM), "__f7\tFN\t7\n"); \ - text_section (); \ -} - /* Some systems use __main in a way incompatible with its use in gcc, in these cases use the macros NAME__MAIN to give a quoted symbol and SYMBOL__MAIN to give the same symbol without quotes for an alternative entry point. You - must define both, or neither. */ + must define both, or neither. */ #define NAME__MAIN "__gccmain" #define SYMBOL__MAIN __gccmain -#define ASM_FILE_END(STREAM) \ -do \ -{ \ - if (flag_pic) \ - aof_dump_pic_table (STREAM); \ - aof_dump_imports (STREAM); \ - fputs ("\tEND\n", (STREAM)); \ -} while (0); - #define ASM_COMMENT_START ";" +#define ASM_APP_ON "" +#define ASM_APP_OFF "" -#define ASM_APP_ON "" - -#define ASM_APP_OFF "" - -#define ASM_OUTPUT_ASCII(STREAM,PTR,LEN) \ +#define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) \ { \ int i; \ const char *ptr = (PTR); \ @@ -193,31 +149,30 @@ do \ for (i = 0; i < (long)(LEN); i++) \ fprintf ((STREAM), " &%02x%s", \ (unsigned ) *(ptr++), \ - (i + 1 < (long)(LEN) \ + (i + 1 < (long)(LEN) \ ? ((i & 3) == 3 ? "\n\tDCB" : ",") \ : "\n")); \ } #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == '\n') -/* Output of Uninitialized Variables */ +/* Output of Uninitialized Variables. */ -#define ASM_OUTPUT_COMMON(STREAM,NAME,SIZE,ROUNDED) \ +#define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \ (common_section (), \ fprintf ((STREAM), "\tAREA "), \ assemble_name ((STREAM), (NAME)), \ fprintf ((STREAM), ", DATA, COMMON\n\t%% %d\t%s size=%d\n", \ - (ROUNDED), ASM_COMMENT_START, SIZE)) + (int)(ROUNDED), ASM_COMMENT_START, (int)(SIZE))) -#define ASM_OUTPUT_LOCAL(STREAM,NAME,SIZE,ROUNDED) \ +#define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \ (zero_init_section (), \ assemble_name ((STREAM), (NAME)), \ fprintf ((STREAM), "\n"), \ fprintf ((STREAM), "\t%% %d\t%s size=%d\n", \ - (ROUNDED), ASM_COMMENT_START, SIZE)) + (int)(ROUNDED), ASM_COMMENT_START, (int)(SIZE))) /* Output and Generation of Labels */ - extern int arm_main_function; /* Globalizing directive for a label. */ @@ -267,26 +222,31 @@ do { \ #define ASM_GENERATE_INTERNAL_LABEL(STRING,PREFIX,NUM) \ sprintf ((STRING), "*|%s..%ld|", (PREFIX), (long)(NUM)) -#define ASM_FORMAT_PRIVATE_NAME(OUTVAR,NAME,NUMBER) \ - ((OUTVAR) = (char *) alloca (strlen ((NAME)) + 10), \ - sprintf ((OUTVAR), "%s.%d", (NAME), (NUMBER))) - -/* How initialization functions are handled */ +/* How initialization functions are handled. */ #define CTORS_SECTION_ASM_OP "\tAREA\t|C$$gnu_ctorsvec|, DATA, READONLY" #define DTORS_SECTION_ASM_OP "\tAREA\t|C$$gnu_dtorsvec|, DATA, READONLY" -/* Output of Assembler Instructions */ - -#define REGISTER_NAMES \ -{ \ - "a1", "a2", "a3", "a4", \ - "v1", "v2", "v3", "v4", \ - "v5", "v6", "sl", "fp", \ - "ip", "sp", "lr", "pc", \ - "f0", "f1", "f2", "f3", \ - "f4", "f5", "f6", "f7", \ - "cc", "sfp", "afp" \ +/* Output of Assembler Instructions. */ + +#define REGISTER_NAMES \ +{ \ + "a1", "a2", "a3", "a4", \ + "v1", "v2", "v3", "v4", \ + "v5", "v6", "sl", "fp", \ + "ip", "sp", "lr", "pc", \ + "f0", "f1", "f2", "f3", \ + "f4", "f5", "f6", "f7", \ + "cc", "sfp", "afp", \ + "mv0", "mv1", "mv2", "mv3", \ + "mv4", "mv5", "mv6", "mv7", \ + "mv8", "mv9", "mv10", "mv11", \ + "mv12", "mv13", "mv14", "mv15", \ + "wcgr0", "wcgr1", "wcgr2", "wcgr3", \ + "wr0", "wr1", "wr2", "wr3", \ + "wr4", "wr5", "wr6", "wr7", \ + "wr8", "wr9", "wr10", "wr11", \ + "wr12", "wr13", "wr14", "wr15" \ } #define ADDITIONAL_REGISTER_NAMES \ @@ -316,37 +276,40 @@ do { \ /* AOF does not prefix user function names with an underscore. */ #define ARM_MCOUNT_NAME "_mcount" -/* Output of Dispatch Tables */ - -#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \ - do { \ - if (TARGET_ARM) \ - fprintf ((STREAM), "\tb\t|L..%d|\n", (VALUE)); \ - else \ - fprintf ((STREAM), "\tDCD\t|L..%d| - |L..%d|\n", (VALUE), (REL)); \ - } while (0) - -#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ +/* Output of Dispatch Tables. */ +#define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ + do \ + { \ + if (TARGET_ARM) \ + fprintf ((STREAM), "\tb\t|L..%d|\n", (VALUE)); \ + else \ + fprintf ((STREAM), "\tDCD\t|L..%d| - |L..%d|\n", (VALUE), (REL)); \ + } \ + while (0) + +#define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ fprintf ((STREAM), "\tDCD\t|L..%d|\n", (VALUE)) -/* A label marking the start of a jump table is a data label. */ -#define ASM_OUTPUT_CASE_LABEL(STREAM,PREFIX,NUM,TABLE) \ +/* A label marking the start of a jump table is a data label. */ +#define ASM_OUTPUT_CASE_LABEL(STREAM, PREFIX, NUM, TABLE) \ fprintf ((STREAM), "\tALIGN\n|%s..%d|\n", (PREFIX), (NUM)) -/* Assembler Commands for Alignment */ - -#define ASM_OUTPUT_SKIP(STREAM,NBYTES) \ - fprintf ((STREAM), "\t%%\t%d\n", (NBYTES)) - -#define ASM_OUTPUT_ALIGN(STREAM,POWER) \ -do { \ - register int amount = 1 << (POWER); \ - if (amount == 2) \ - fprintf ((STREAM), "\tALIGN 2\n"); \ - else if (amount == 4) \ - fprintf ((STREAM), "\tALIGN\n"); \ - else \ - fprintf ((STREAM), "\tALIGN %d\n", amount); \ -} while (0) +/* Assembler Commands for Alignment. */ +#define ASM_OUTPUT_SKIP(STREAM, NBYTES) \ + fprintf ((STREAM), "\t%%\t%d\n", (int) (NBYTES)) + +#define ASM_OUTPUT_ALIGN(STREAM, POWER) \ + do \ + { \ + int amount = 1 << (POWER); \ + \ + if (amount == 2) \ + fprintf ((STREAM), "\tALIGN 2\n"); \ + else if (amount == 4) \ + fprintf ((STREAM), "\tALIGN\n"); \ + else \ + fprintf ((STREAM), "\tALIGN %d\n", amount); \ + } \ + while (0) #undef DBX_DEBUGGING_INFO diff --git a/contrib/gcc/config/arm/aout.h b/contrib/gcc/config/arm/aout.h index 8f4a605..1f060fa 100644 --- a/contrib/gcc/config/arm/aout.h +++ b/contrib/gcc/config/arm/aout.h @@ -3,40 +3,22 @@ Free Software Foundation, Inc. Contributed by Richard Earnshaw (rearnsha@armltd.co.uk). -This file is part of GNU CC. - -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. - -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ - -#ifndef ARM_OS_NAME -#define ARM_OS_NAME "(generic)" -#endif - -/* The text to go at the start of the assembler file */ -#ifndef ASM_FILE_START -#define ASM_FILE_START(STREAM) \ -{ \ - asm_fprintf (STREAM,"%Rrfp\t.req\t%Rr9\n"); \ - asm_fprintf (STREAM,"%Rsl\t.req\t%Rr10\n"); \ - asm_fprintf (STREAM,"%Rfp\t.req\t%Rr11\n"); \ - asm_fprintf (STREAM,"%Rip\t.req\t%Rr12\n"); \ - asm_fprintf (STREAM,"%Rsp\t.req\t%Rr13\n"); \ - asm_fprintf (STREAM,"%Rlr\t.req\t%Rr14\n"); \ - asm_fprintf (STREAM,"%Rpc\t.req\t%Rr15\n"); \ -} -#endif + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ #ifndef ASM_APP_ON #define ASM_APP_ON "" @@ -52,7 +34,7 @@ Boston, MA 02111-1307, USA. */ /* Note: If USER_LABEL_PREFIX or LOCAL_LABEL_PREFIX are changed, make sure that this change is reflected in the function - coff_arm_is_local_label_name() in bfd/coff-arm.c */ + coff_arm_is_local_label_name() in bfd/coff-arm.c. */ #ifndef REGISTER_PREFIX #define REGISTER_PREFIX "" #endif @@ -65,7 +47,6 @@ Boston, MA 02111-1307, USA. */ #define LOCAL_LABEL_PREFIX "" #endif - /* The assembler's names for the registers. */ #ifndef REGISTER_NAMES #define REGISTER_NAMES \ @@ -73,7 +54,16 @@ Boston, MA 02111-1307, USA. */ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc", \ "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ - "cc", "sfp", "afp" \ + "cc", "sfp", "afp", \ + "mv0", "mv1", "mv2", "mv3", \ + "mv4", "mv5", "mv6", "mv7", \ + "mv8", "mv9", "mv10", "mv11", \ + "mv12", "mv13", "mv14", "mv15", \ + "wcgr0", "wcgr1", "wcgr2", "wcgr3", \ + "wr0", "wr1", "wr2", "wr3", \ + "wr4", "wr5", "wr6", "wr7", \ + "wr8", "wr9", "wr10", "wr11", \ + "wr12", "wr13", "wr14", "wr15" \ } #endif @@ -98,11 +88,75 @@ Boston, MA 02111-1307, USA. */ {"r12", 12}, /* ip */ \ {"r13", 13}, /* sp */ \ {"r14", 14}, /* lr */ \ - {"r15", 15} /* pc */ \ + {"r15", 15}, /* pc */ \ + {"mvf0", 27}, \ + {"mvf1", 28}, \ + {"mvf2", 29}, \ + {"mvf3", 30}, \ + {"mvf4", 31}, \ + {"mvf5", 32}, \ + {"mvf6", 33}, \ + {"mvf7", 34}, \ + {"mvf8", 35}, \ + {"mvf9", 36}, \ + {"mvf10", 37}, \ + {"mvf11", 38}, \ + {"mvf12", 39}, \ + {"mvf13", 40}, \ + {"mvf14", 41}, \ + {"mvf15", 42}, \ + {"mvd0", 27}, \ + {"mvd1", 28}, \ + {"mvd2", 29}, \ + {"mvd3", 30}, \ + {"mvd4", 31}, \ + {"mvd5", 32}, \ + {"mvd6", 33}, \ + {"mvd7", 34}, \ + {"mvd8", 35}, \ + {"mvd9", 36}, \ + {"mvd10", 37}, \ + {"mvd11", 38}, \ + {"mvd12", 39}, \ + {"mvd13", 40}, \ + {"mvd14", 41}, \ + {"mvd15", 42}, \ + {"mvfx0", 27}, \ + {"mvfx1", 28}, \ + {"mvfx2", 29}, \ + {"mvfx3", 30}, \ + {"mvfx4", 31}, \ + {"mvfx5", 32}, \ + {"mvfx6", 33}, \ + {"mvfx7", 34}, \ + {"mvfx8", 35}, \ + {"mvfx9", 36}, \ + {"mvfx10", 37}, \ + {"mvfx11", 38}, \ + {"mvfx12", 39}, \ + {"mvfx13", 40}, \ + {"mvfx14", 41}, \ + {"mvfx15", 42}, \ + {"mvdx0", 27}, \ + {"mvdx1", 28}, \ + {"mvdx2", 29}, \ + {"mvdx3", 30}, \ + {"mvdx4", 31}, \ + {"mvdx5", 32}, \ + {"mvdx6", 33}, \ + {"mvdx7", 34}, \ + {"mvdx8", 35}, \ + {"mvdx9", 36}, \ + {"mvdx10", 37}, \ + {"mvdx11", 38}, \ + {"mvdx12", 39}, \ + {"mvdx13", 40}, \ + {"mvdx14", 41}, \ + {"mvdx15", 42} \ } #endif -/* Arm Assembler barfs on dollars */ +/* Arm Assembler barfs on dollars. */ #define DOLLARS_IN_IDENTIFIERS 0 #ifndef NO_DOLLAR_IN_LABEL @@ -110,7 +164,7 @@ Boston, MA 02111-1307, USA. */ #endif /* Generate DBX debugging information. riscix.h will undefine this because - the native assembler does not support stabs. */ + the native assembler does not support stabs. */ #define DBX_DEBUGGING_INFO 1 /* Acorn dbx moans about continuation chars, so don't use any. */ @@ -127,7 +181,7 @@ Boston, MA 02111-1307, USA. */ output_quoted_string (STREAM, NAME); \ fprintf (STREAM, ",%d,0,315,%s\n", N_SO, <ext_label_name[1]); \ text_section (); \ - ASM_OUTPUT_INTERNAL_LABEL (STREAM, "Ltext", 0); \ + (*targetm.asm_out.internal_label) (STREAM, "Ltext", 0); \ } \ while (0) @@ -151,11 +205,6 @@ Boston, MA 02111-1307, USA. */ sprintf (STRING, "*%s%s%u", LOCAL_LABEL_PREFIX, PREFIX, (unsigned int)(NUM)) #endif -/* Construct a private name. */ -#define ASM_FORMAT_PRIVATE_NAME(OUTVAR, NAME, NUMBER) \ - ((OUTVAR) = (char *) alloca (strlen (NAME) + 10), \ - sprintf (OUTVAR, "%s.%d", NAME, NUMBER)) - /* Output an element of a dispatch table. */ #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ asm_fprintf (STREAM, "\t.word\t%LL%d\n", VALUE) @@ -173,12 +222,12 @@ Boston, MA 02111-1307, USA. */ #undef ASM_OUTPUT_ASCII #define ASM_OUTPUT_ASCII(STREAM, PTR, LEN) \ - output_ascii_pseudo_op (STREAM, (const unsigned char *)(PTR), LEN) + output_ascii_pseudo_op (STREAM, (const unsigned char *) (PTR), LEN) /* Output a gap. In fact we fill it with nulls. */ #undef ASM_OUTPUT_SKIP #define ASM_OUTPUT_SKIP(STREAM, NBYTES) \ - fprintf (STREAM, "\t.space\t%d\n", NBYTES) + fprintf (STREAM, "\t.space\t%d\n", (int) (NBYTES)) /* Align output to a power of two. Horrible /bin/as. */ #ifndef ASM_OUTPUT_ALIGN @@ -195,7 +244,7 @@ Boston, MA 02111-1307, USA. */ while (0) #endif -/* Output a common block */ +/* Output a common block. */ #ifndef ASM_OUTPUT_COMMON #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \ do \ @@ -203,7 +252,7 @@ Boston, MA 02111-1307, USA. */ fprintf (STREAM, "\t.comm\t"); \ assemble_name (STREAM, NAME); \ asm_fprintf (STREAM, ", %d\t%@ %d\n", \ - ROUNDED, SIZE); \ + (int)(ROUNDED), (int)(SIZE)); \ } \ while (0) #endif @@ -219,7 +268,7 @@ Boston, MA 02111-1307, USA. */ bss_section (); \ ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \ ASM_OUTPUT_LABEL (STREAM, NAME); \ - fprintf (STREAM, "\t.space\t%d\n", SIZE); \ + fprintf (STREAM, "\t.space\t%d\n", (int)(SIZE)); \ } \ while (0) #endif @@ -229,9 +278,6 @@ Boston, MA 02111-1307, USA. */ #define ASM_OUTPUT_ALIGNED_BSS(STREAM, DECL, NAME, SIZE, ALIGN) \ asm_output_aligned_bss (STREAM, DECL, NAME, SIZE, ALIGN) #endif - -/* Output a source line for the debugger. */ -/* #define ASM_OUTPUT_SOURCE_LINE(STREAM,LINE) */ /* Output a #ident directive. */ #ifndef ASM_OUTPUT_IDENT diff --git a/contrib/gcc/config/arm/arm-modes.def b/contrib/gcc/config/arm/arm-modes.def index 48f9ddf..b853551 100644 --- a/contrib/gcc/config/arm/arm-modes.def +++ b/contrib/gcc/config/arm/arm-modes.def @@ -5,42 +5,48 @@ More major hacks by Richard Earnshaw (rearnsha@arm.com) Minor hacks by Nick Clifton (nickc@cygnus.com) -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +/* Extended precision floating point. + FIXME What format is this? */ +FLOAT_MODE (XF, 12, 0); /* CCFPEmode should be used with floating inequalities, CCFPmode should be used with floating equalities. CC_NOOVmode should be used with SImode integer equalities. CC_Zmode should be used if only the Z flag is set correctly - CCmode should be used otherwise. */ + CC_Nmode should be used if only the N (sign) flag is set correctly + CCmode should be used otherwise. */ -CC (CC_NOOV) -CC (CC_Z) -CC (CC_SWP) -CC (CCFP) -CC (CCFPE) -CC (CC_DNE) -CC (CC_DEQ) -CC (CC_DLE) -CC (CC_DLT) -CC (CC_DGE) -CC (CC_DGT) -CC (CC_DLEU) -CC (CC_DLTU) -CC (CC_DGEU) -CC (CC_DGTU) -CC (CC_C) +CC_MODE (CC_NOOV); +CC_MODE (CC_Z); +CC_MODE (CC_SWP); +CC_MODE (CCFP); +CC_MODE (CCFPE); +CC_MODE (CC_DNE); +CC_MODE (CC_DEQ); +CC_MODE (CC_DLE); +CC_MODE (CC_DLT); +CC_MODE (CC_DGE); +CC_MODE (CC_DGT); +CC_MODE (CC_DLEU); +CC_MODE (CC_DLTU); +CC_MODE (CC_DGEU); +CC_MODE (CC_DGTU); +CC_MODE (CC_C); +CC_MODE (CC_N); diff --git a/contrib/gcc/config/arm/arm-protos.h b/contrib/gcc/config/arm/arm-protos.h index cae9bea..471254e 100644 --- a/contrib/gcc/config/arm/arm-protos.h +++ b/contrib/gcc/config/arm/arm-protos.h @@ -1,220 +1,206 @@ /* Prototypes for exported functions defined in arm.c and pe.c - Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc. + Copyright (C) 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. Contributed by Richard Earnshaw (rearnsha@arm.com) Minor hacks by Nick Clifton (nickc@cygnus.com) -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ #ifndef GCC_ARM_PROTOS_H #define GCC_ARM_PROTOS_H -extern void rdata_section PARAMS ((void)); -extern void arm_override_options PARAMS ((void)); -extern int use_return_insn PARAMS ((int)); -extern int arm_regno_class PARAMS ((int)); -extern void arm_finalize_pic PARAMS ((int)); -extern int arm_volatile_func PARAMS ((void)); -extern const char * arm_output_epilogue PARAMS ((int)); -extern void arm_expand_prologue PARAMS ((void)); -extern HOST_WIDE_INT arm_get_frame_size PARAMS ((void)); -/* Used in arm.md, but defined in output.c. */ -extern void assemble_align PARAMS ((int)); -extern const char * arm_strip_name_encoding PARAMS ((const char *)); -extern void arm_asm_output_labelref PARAMS ((FILE *, const char *)); -extern unsigned long arm_current_func_type PARAMS ((void)); -extern unsigned int arm_compute_initial_elimination_offset PARAMS ((unsigned int, unsigned int)); +extern void arm_override_options (void); +extern int use_return_insn (int, rtx); +extern int arm_regno_class (int); +extern void arm_finalize_pic (int); +extern int arm_volatile_func (void); +extern const char *arm_output_epilogue (rtx); +extern void arm_expand_prologue (void); +extern HOST_WIDE_INT arm_get_frame_size (void); +extern const char *arm_strip_name_encoding (const char *); +extern void arm_asm_output_labelref (FILE *, const char *); +extern unsigned long arm_current_func_type (void); +extern unsigned int arm_compute_initial_elimination_offset (unsigned int, + unsigned int); #ifdef TREE_CODE -extern int arm_return_in_memory PARAMS ((tree)); -extern void arm_encode_call_attribute PARAMS ((tree, int)); -extern int arm_function_ok_for_sibcall PARAMS ((tree)); +extern int arm_return_in_memory (tree); +extern void arm_encode_call_attribute (tree, int); #endif #ifdef RTX_CODE -extern int arm_hard_regno_mode_ok PARAMS ((unsigned int, - enum machine_mode)); -extern int const_ok_for_arm PARAMS ((HOST_WIDE_INT)); -extern int arm_split_constant PARAMS ((RTX_CODE, enum machine_mode, - HOST_WIDE_INT, rtx, rtx, int)); -extern RTX_CODE arm_canonicalize_comparison PARAMS ((RTX_CODE, rtx *)); -extern int legitimate_pic_operand_p PARAMS ((rtx)); -extern rtx legitimize_pic_address PARAMS ((rtx, enum machine_mode, rtx)); -extern int arm_rtx_costs PARAMS ((rtx, RTX_CODE, RTX_CODE)); -extern int const_double_rtx_ok_for_fpu PARAMS ((rtx)); -extern int neg_const_double_rtx_ok_for_fpu PARAMS ((rtx)); +extern int arm_hard_regno_mode_ok (unsigned int, enum machine_mode); +extern int const_ok_for_arm (HOST_WIDE_INT); +extern int arm_split_constant (RTX_CODE, enum machine_mode, HOST_WIDE_INT, rtx, + rtx, int); +extern RTX_CODE arm_canonicalize_comparison (RTX_CODE, rtx *); +extern int legitimate_pic_operand_p (rtx); +extern rtx legitimize_pic_address (rtx, enum machine_mode, rtx); +extern int arm_legitimate_address_p (enum machine_mode, rtx, int); +extern int thumb_legitimate_address_p (enum machine_mode, rtx, int); +extern int thumb_legitimate_offset_p (enum machine_mode, HOST_WIDE_INT); +extern rtx arm_legitimize_address (rtx, rtx, enum machine_mode); +extern int const_double_rtx_ok_for_fpa (rtx); +extern int neg_const_double_rtx_ok_for_fpa (rtx); /* Predicates. */ -extern int s_register_operand PARAMS ((rtx, enum machine_mode)); -extern int arm_hard_register_operand PARAMS ((rtx, enum machine_mode)); -extern int f_register_operand PARAMS ((rtx, enum machine_mode)); -extern int reg_or_int_operand PARAMS ((rtx, enum machine_mode)); -extern int arm_reload_memory_operand PARAMS ((rtx, enum machine_mode)); -extern int arm_rhs_operand PARAMS ((rtx, enum machine_mode)); -extern int arm_rhsm_operand PARAMS ((rtx, enum machine_mode)); -extern int arm_add_operand PARAMS ((rtx, enum machine_mode)); -extern int arm_not_operand PARAMS ((rtx, enum machine_mode)); -extern int offsettable_memory_operand PARAMS ((rtx, enum machine_mode)); -extern int alignable_memory_operand PARAMS ((rtx, enum machine_mode)); -extern int bad_signed_byte_operand PARAMS ((rtx, enum machine_mode)); -extern int fpu_rhs_operand PARAMS ((rtx, enum machine_mode)); -extern int fpu_add_operand PARAMS ((rtx, enum machine_mode)); -extern int power_of_two_operand PARAMS ((rtx, enum machine_mode)); -extern int nonimmediate_di_operand PARAMS ((rtx, enum machine_mode)); -extern int di_operand PARAMS ((rtx, enum machine_mode)); -extern int nonimmediate_soft_df_operand PARAMS ((rtx, enum machine_mode)); -extern int soft_df_operand PARAMS ((rtx, enum machine_mode)); -extern int index_operand PARAMS ((rtx, enum machine_mode)); -extern int const_shift_operand PARAMS ((rtx, enum machine_mode)); -extern int arm_comparison_operator PARAMS ((rtx, enum machine_mode)); -extern int shiftable_operator PARAMS ((rtx, enum machine_mode)); -extern int shift_operator PARAMS ((rtx, enum machine_mode)); -extern int equality_operator PARAMS ((rtx, enum machine_mode)); -extern int minmax_operator PARAMS ((rtx, enum machine_mode)); -extern int cc_register PARAMS ((rtx, enum machine_mode)); -extern int dominant_cc_register PARAMS ((rtx, enum machine_mode)); -extern int logical_binary_operator PARAMS ((rtx, enum machine_mode)); -extern int multi_register_push PARAMS ((rtx, enum machine_mode)); -extern int load_multiple_operation PARAMS ((rtx, enum machine_mode)); -extern int store_multiple_operation PARAMS ((rtx, enum machine_mode)); - -extern int symbol_mentioned_p PARAMS ((rtx)); -extern int label_mentioned_p PARAMS ((rtx)); -extern RTX_CODE minmax_code PARAMS ((rtx)); -extern int adjacent_mem_locations PARAMS ((rtx, rtx)); -extern int load_multiple_sequence PARAMS ((rtx *, int, int *, int *, - HOST_WIDE_INT *)); -extern const char * emit_ldm_seq PARAMS ((rtx *, int)); -extern int store_multiple_sequence PARAMS ((rtx *, int, int *, int *, - HOST_WIDE_INT *)); -extern const char * emit_stm_seq PARAMS ((rtx *, int)); -extern rtx arm_gen_load_multiple PARAMS ((int, int, rtx, int, int, int, - int, int)); -extern rtx arm_gen_store_multiple PARAMS ((int, int, rtx, int, int, int, - int, int)); -extern int arm_gen_movstrqi PARAMS ((rtx *)); -extern rtx arm_gen_rotated_half_load PARAMS ((rtx)); -extern enum machine_mode arm_select_cc_mode PARAMS ((RTX_CODE, rtx, rtx)); -extern rtx arm_gen_compare_reg PARAMS ((RTX_CODE, rtx, rtx)); -extern rtx arm_gen_return_addr_mask PARAMS ((void)); -extern void arm_reload_in_hi PARAMS ((rtx *)); -extern void arm_reload_out_hi PARAMS ((rtx *)); -extern void arm_reorg PARAMS ((rtx)); -extern const char * fp_immediate_constant PARAMS ((rtx)); -extern const char * output_call PARAMS ((rtx *)); -extern const char * output_call_mem PARAMS ((rtx *)); -extern const char * output_mov_long_double_fpu_from_arm PARAMS ((rtx *)); -extern const char * output_mov_long_double_arm_from_fpu PARAMS ((rtx *)); -extern const char * output_mov_long_double_arm_from_arm PARAMS ((rtx *)); -extern const char * output_mov_double_fpu_from_arm PARAMS ((rtx *)); -extern const char * output_mov_double_arm_from_fpu PARAMS ((rtx *)); -extern const char * output_move_double PARAMS ((rtx *)); -extern const char * output_mov_immediate PARAMS ((rtx *)); -extern const char * output_add_immediate PARAMS ((rtx *)); -extern const char * arithmetic_instr PARAMS ((rtx, int)); -extern void output_ascii_pseudo_op PARAMS ((FILE *, const unsigned char *, - int)); -extern const char * output_return_instruction PARAMS ((rtx, int, int)); -extern void arm_poke_function_name PARAMS ((FILE *, const char *)); -extern void arm_print_operand PARAMS ((FILE *, rtx, int)); -extern void arm_print_operand_address PARAMS ((FILE *, rtx)); -extern void arm_final_prescan_insn PARAMS ((rtx)); -extern int arm_go_if_legitimate_address PARAMS ((enum machine_mode, rtx)); -extern int arm_debugger_arg_offset PARAMS ((int, rtx)); -extern int arm_is_longcall_p PARAMS ((rtx, int, int)); +extern int s_register_operand (rtx, enum machine_mode); +extern int arm_hard_register_operand (rtx, enum machine_mode); +extern int f_register_operand (rtx, enum machine_mode); +extern int reg_or_int_operand (rtx, enum machine_mode); +extern int arm_reload_memory_operand (rtx, enum machine_mode); +extern int arm_rhs_operand (rtx, enum machine_mode); +extern int arm_rhsm_operand (rtx, enum machine_mode); +extern int arm_add_operand (rtx, enum machine_mode); +extern int arm_addimm_operand (rtx, enum machine_mode); +extern int arm_not_operand (rtx, enum machine_mode); +extern int offsettable_memory_operand (rtx, enum machine_mode); +extern int alignable_memory_operand (rtx, enum machine_mode); +extern int bad_signed_byte_operand (rtx, enum machine_mode); +extern int fpa_rhs_operand (rtx, enum machine_mode); +extern int fpa_add_operand (rtx, enum machine_mode); +extern int power_of_two_operand (rtx, enum machine_mode); +extern int nonimmediate_di_operand (rtx, enum machine_mode); +extern int di_operand (rtx, enum machine_mode); +extern int nonimmediate_soft_df_operand (rtx, enum machine_mode); +extern int soft_df_operand (rtx, enum machine_mode); +extern int index_operand (rtx, enum machine_mode); +extern int const_shift_operand (rtx, enum machine_mode); +extern int arm_comparison_operator (rtx, enum machine_mode); +extern int shiftable_operator (rtx, enum machine_mode); +extern int shift_operator (rtx, enum machine_mode); +extern int equality_operator (rtx, enum machine_mode); +extern int minmax_operator (rtx, enum machine_mode); +extern int cc_register (rtx, enum machine_mode); +extern int dominant_cc_register (rtx, enum machine_mode); +extern int logical_binary_operator (rtx, enum machine_mode); +extern int multi_register_push (rtx, enum machine_mode); +extern int load_multiple_operation (rtx, enum machine_mode); +extern int store_multiple_operation (rtx, enum machine_mode); +extern int cirrus_fp_register (rtx, enum machine_mode); +extern int cirrus_general_operand (rtx, enum machine_mode); +extern int cirrus_register_operand (rtx, enum machine_mode); +extern int cirrus_shift_const (rtx, enum machine_mode); +extern int cirrus_memory_offset (rtx); + +extern int symbol_mentioned_p (rtx); +extern int label_mentioned_p (rtx); +extern RTX_CODE minmax_code (rtx); +extern int adjacent_mem_locations (rtx, rtx); +extern int load_multiple_sequence (rtx *, int, int *, int *, HOST_WIDE_INT *); +extern const char *emit_ldm_seq (rtx *, int); +extern int store_multiple_sequence (rtx *, int, int *, int *, HOST_WIDE_INT *); +extern const char * emit_stm_seq (rtx *, int); +extern rtx arm_gen_load_multiple (int, int, rtx, int, int, int, int, int); +extern rtx arm_gen_store_multiple (int, int, rtx, int, int, int, int, int); +extern int arm_gen_movstrqi (rtx *); +extern rtx arm_gen_rotated_half_load (rtx); +extern enum machine_mode arm_select_cc_mode (RTX_CODE, rtx, rtx); +extern enum machine_mode arm_select_dominance_cc_mode (rtx, rtx, + HOST_WIDE_INT); +extern rtx arm_gen_compare_reg (RTX_CODE, rtx, rtx); +extern rtx arm_gen_return_addr_mask (void); +extern void arm_reload_in_hi (rtx *); +extern void arm_reload_out_hi (rtx *); +extern const char *fp_immediate_constant (rtx); +extern const char *output_call (rtx *); +extern const char *output_call_mem (rtx *); +extern const char *output_mov_long_double_fpa_from_arm (rtx *); +extern const char *output_mov_long_double_arm_from_fpa (rtx *); +extern const char *output_mov_long_double_arm_from_arm (rtx *); +extern const char *output_mov_double_fpa_from_arm (rtx *); +extern const char *output_mov_double_arm_from_fpa (rtx *); +extern const char *output_move_double (rtx *); +extern const char *output_mov_immediate (rtx *); +extern const char *output_add_immediate (rtx *); +extern const char *arithmetic_instr (rtx, int); +extern void output_ascii_pseudo_op (FILE *, const unsigned char *, int); +extern const char *output_return_instruction (rtx, int, int); +extern void arm_poke_function_name (FILE *, const char *); +extern void arm_print_operand (FILE *, rtx, int); +extern void arm_print_operand_address (FILE *, rtx); +extern void arm_final_prescan_insn (rtx); +extern int arm_go_if_legitimate_address (enum machine_mode, rtx); +extern int arm_debugger_arg_offset (int, rtx); +extern int arm_is_longcall_p (rtx, int, int); +extern int arm_emit_vector_const (FILE *, rtx); +extern const char * arm_output_load_gr (rtx *); #if defined TREE_CODE -extern rtx arm_function_arg PARAMS ((CUMULATIVE_ARGS *, - enum machine_mode, tree, int)); -extern void arm_init_cumulative_args PARAMS ((CUMULATIVE_ARGS *, tree, rtx, - int)); -extern rtx arm_va_arg PARAMS ((tree, tree)); -extern int arm_function_arg_pass_by_reference PARAMS ((CUMULATIVE_ARGS *, - enum machine_mode, - tree, int)); - +extern rtx arm_function_arg (CUMULATIVE_ARGS *, enum machine_mode, tree, int); +extern void arm_init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, tree); +extern rtx arm_va_arg (tree, tree); +extern int arm_function_arg_pass_by_reference (CUMULATIVE_ARGS *, + enum machine_mode, tree, int); #endif #if defined AOF_ASSEMBLER -extern rtx aof_pic_entry PARAMS ((rtx)); -extern void aof_dump_pic_table PARAMS ((FILE *)); -extern char * aof_text_section PARAMS ((void)); -extern char * aof_data_section PARAMS ((void)); -extern void aof_add_import PARAMS ((const char *)); -extern void aof_delete_import PARAMS ((const char *)); -extern void aof_dump_imports PARAMS ((FILE *)); -extern void zero_init_section PARAMS ((void)); -extern void common_section PARAMS ((void)); +extern rtx aof_pic_entry (rtx); +extern char *aof_text_section (void); +extern char *aof_data_section (void); +extern void aof_add_import (const char *); +extern void aof_delete_import (const char *); +extern void zero_init_section (void); +extern void common_section (void); #endif /* AOF_ASSEMBLER */ #endif /* RTX_CODE */ -extern int arm_float_words_big_endian PARAMS ((void)); +extern int arm_float_words_big_endian (void); /* Thumb functions. */ -extern void arm_init_expanders PARAMS ((void)); -extern int thumb_far_jump_used_p PARAMS ((int)); -extern const char * thumb_unexpanded_epilogue PARAMS ((void)); -extern HOST_WIDE_INT thumb_get_frame_size PARAMS ((void)); -extern void thumb_expand_prologue PARAMS ((void)); -extern void thumb_expand_epilogue PARAMS ((void)); +extern void arm_init_expanders (void); +extern int thumb_far_jump_used_p (int); +extern const char *thumb_unexpanded_epilogue (void); +extern HOST_WIDE_INT thumb_get_frame_size (void); +extern void thumb_expand_prologue (void); +extern void thumb_expand_epilogue (void); #ifdef TREE_CODE -extern int is_called_in_ARM_mode PARAMS ((tree)); +extern int is_called_in_ARM_mode (tree); #endif -extern int thumb_shiftable_const PARAMS ((unsigned HOST_WIDE_INT)); +extern int thumb_shiftable_const (unsigned HOST_WIDE_INT); #ifdef RTX_CODE -extern void thumb_final_prescan_insn PARAMS ((rtx)); -extern const char * thumb_load_double_from_address - PARAMS ((rtx *)); -extern const char * thumb_output_move_mem_multiple - PARAMS ((int, rtx *)); -extern void thumb_expand_movstrqi PARAMS ((rtx *)); -extern int thumb_cmp_operand PARAMS ((rtx, enum machine_mode)); -extern rtx * thumb_legitimize_pic_address - PARAMS ((rtx, enum machine_mode, rtx)); -extern int thumb_go_if_legitimate_address - PARAMS ((enum machine_mode, rtx)); -extern rtx arm_return_addr PARAMS ((int, rtx)); -extern void thumb_reload_out_hi PARAMS ((rtx *)); -extern void thumb_reload_in_hi PARAMS ((rtx *)); +extern void thumb_final_prescan_insn (rtx); +extern const char *thumb_load_double_from_address (rtx *); +extern const char *thumb_output_move_mem_multiple (int, rtx *); +extern void thumb_expand_movstrqi (rtx *); +extern int thumb_cmp_operand (rtx, enum machine_mode); +extern int thumb_cbrch_target_operand (rtx, enum machine_mode); +extern rtx *thumb_legitimize_pic_address (rtx, enum machine_mode, rtx); +extern int thumb_go_if_legitimate_address (enum machine_mode, rtx); +extern rtx arm_return_addr (int, rtx); +extern void thumb_reload_out_hi (rtx *); +extern void thumb_reload_in_hi (rtx *); #endif /* Defined in pe.c. */ -extern int arm_dllexport_name_p PARAMS ((const char *)); -extern int arm_dllimport_name_p PARAMS ((const char *)); +extern int arm_dllexport_name_p (const char *); +extern int arm_dllimport_name_p (const char *); #ifdef TREE_CODE -extern void arm_pe_unique_section PARAMS ((tree, int)); -extern void arm_pe_encode_section_info PARAMS ((tree, int)); -extern int arm_dllexport_p PARAMS ((tree)); -extern int arm_dllimport_p PARAMS ((tree)); -extern void arm_mark_dllexport PARAMS ((tree)); -extern void arm_mark_dllimport PARAMS ((tree)); -#endif - -extern void arm_init_builtins PARAMS ((void)); -#if defined (TREE_CODE) && defined (RTX_CODE) -extern rtx arm_expand_builtin PARAMS ((tree, rtx, rtx, - enum machine_mode, int)); +extern void arm_pe_unique_section (tree, int); +extern void arm_pe_encode_section_info (tree, rtx, int); +extern int arm_dllexport_p (tree); +extern int arm_dllimport_p (tree); +extern void arm_mark_dllexport (tree); +extern void arm_mark_dllimport (tree); #endif -#ifdef GCC_C_PRAGMA_H /* included from code that cares about pragmas */ -extern void arm_pr_long_calls PARAMS ((cpp_reader *)); -extern void arm_pr_no_long_calls PARAMS ((cpp_reader *)); -extern void arm_pr_long_calls_off PARAMS ((cpp_reader *)); -#endif +extern void arm_pr_long_calls (struct cpp_reader *); +extern void arm_pr_no_long_calls (struct cpp_reader *); +extern void arm_pr_long_calls_off (struct cpp_reader *); #endif /* ! GCC_ARM_PROTOS_H */ diff --git a/contrib/gcc/config/arm/arm.c b/contrib/gcc/config/arm/arm.c index 7422f1d..91e4486 100644 --- a/contrib/gcc/config/arm/arm.c +++ b/contrib/gcc/config/arm/arm.c @@ -1,29 +1,31 @@ /* Output routines for GCC for ARM. - Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 - Free Software Foundation, Inc. + Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, + 2002, 2003, 2004 Free Software Foundation, Inc. Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) and Martin Simmons (@harleqn.co.uk). More major hacks by Richard Earnshaw (rearnsha@arm.com). -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ #include "config.h" #include "system.h" +#include "coretypes.h" +#include "tm.h" #include "rtl.h" #include "tree.h" #include "obstack.h" @@ -48,91 +50,107 @@ Boston, MA 02111-1307, USA. */ #include "tm_p.h" #include "target.h" #include "target-def.h" +#include "debug.h" /* Forward definitions of types. */ typedef struct minipool_node Mnode; typedef struct minipool_fixup Mfix; -/* In order to improve the layout of the prototypes below - some short type abbreviations are defined here. */ -#define Hint HOST_WIDE_INT -#define Mmode enum machine_mode -#define Ulong unsigned long -#define Ccstar const char * - const struct attribute_spec arm_attribute_table[]; /* Forward function declarations. */ -static void arm_add_gc_roots PARAMS ((void)); -static int arm_gen_constant PARAMS ((enum rtx_code, Mmode, Hint, rtx, rtx, int, int)); -static unsigned bit_count PARAMS ((Ulong)); -static int const_ok_for_op PARAMS ((Hint, enum rtx_code)); -static rtx emit_multi_reg_push PARAMS ((int)); -static rtx emit_sfm PARAMS ((int, int)); +static void arm_add_gc_roots (void); +static int arm_gen_constant (enum rtx_code, enum machine_mode, HOST_WIDE_INT, + rtx, rtx, int, int); +static unsigned bit_count (unsigned long); +static int arm_address_register_rtx_p (rtx, int); +static int arm_legitimate_index_p (enum machine_mode, rtx, int); +static int thumb_base_register_rtx_p (rtx, enum machine_mode, int); +inline static int thumb_index_register_rtx_p (rtx, int); +static int const_ok_for_op (HOST_WIDE_INT, enum rtx_code); +static rtx emit_multi_reg_push (int); +static rtx emit_sfm (int, int); #ifndef AOF_ASSEMBLER -static bool arm_assemble_integer PARAMS ((rtx, unsigned int, int)); +static bool arm_assemble_integer (rtx, unsigned int, int); #endif -static Ccstar fp_const_from_val PARAMS ((REAL_VALUE_TYPE *)); -static arm_cc get_arm_condition_code PARAMS ((rtx)); -static void init_fpa_table PARAMS ((void)); -static Hint int_log2 PARAMS ((Hint)); -static rtx is_jump_table PARAMS ((rtx)); -static Ccstar output_multi_immediate PARAMS ((rtx *, Ccstar, Ccstar, int, Hint)); -static void print_multi_reg PARAMS ((FILE *, Ccstar, int, int)); -static Mmode select_dominance_cc_mode PARAMS ((rtx, rtx, Hint)); -static Ccstar shift_op PARAMS ((rtx, Hint *)); -static struct machine_function * arm_init_machine_status PARAMS ((void)); -static int number_of_first_bit_set PARAMS ((int)); -static void replace_symbols_in_block PARAMS ((tree, rtx, rtx)); -static void thumb_exit PARAMS ((FILE *, int, rtx)); -static void thumb_pushpop PARAMS ((FILE *, int, int)); -static Ccstar thumb_condition_code PARAMS ((rtx, int)); -static rtx is_jump_table PARAMS ((rtx)); -static Hint get_jump_table_size PARAMS ((rtx)); -static Mnode * move_minipool_fix_forward_ref PARAMS ((Mnode *, Mnode *, Hint)); -static Mnode * add_minipool_forward_ref PARAMS ((Mfix *)); -static Mnode * move_minipool_fix_backward_ref PARAMS ((Mnode *, Mnode *, Hint)); -static Mnode * add_minipool_backward_ref PARAMS ((Mfix *)); -static void assign_minipool_offsets PARAMS ((Mfix *)); -static void arm_print_value PARAMS ((FILE *, rtx)); -static void dump_minipool PARAMS ((rtx)); -static int arm_barrier_cost PARAMS ((rtx)); -static Mfix * create_fix_barrier PARAMS ((Mfix *, Hint)); -static void push_minipool_barrier PARAMS ((rtx, Hint)); -static void push_minipool_fix PARAMS ((rtx, Hint, rtx *, Mmode, rtx)); -static void note_invalid_constants PARAMS ((rtx, Hint)); -static int current_file_function_operand PARAMS ((rtx)); -static Ulong arm_compute_save_reg0_reg12_mask PARAMS ((void)); -static Ulong arm_compute_save_reg_mask PARAMS ((void)); -static Ulong arm_isr_value PARAMS ((tree)); -static Ulong arm_compute_func_type PARAMS ((void)); -static tree arm_handle_fndecl_attribute PARAMS ((tree *, tree, tree, int, bool *)); -static tree arm_handle_isr_attribute PARAMS ((tree *, tree, tree, int, bool *)); -static void arm_output_function_epilogue PARAMS ((FILE *, Hint)); -static void arm_output_function_prologue PARAMS ((FILE *, Hint)); -static void thumb_output_function_prologue PARAMS ((FILE *, Hint)); -static int arm_comp_type_attributes PARAMS ((tree, tree)); -static void arm_set_default_type_attributes PARAMS ((tree)); -static int arm_adjust_cost PARAMS ((rtx, rtx, rtx, int)); -static int count_insns_for_constant PARAMS ((HOST_WIDE_INT, int)); -static int arm_get_strip_length PARAMS ((int)); +static const char *fp_const_from_val (REAL_VALUE_TYPE *); +static arm_cc get_arm_condition_code (rtx); +static void init_fpa_table (void); +static HOST_WIDE_INT int_log2 (HOST_WIDE_INT); +static rtx is_jump_table (rtx); +static const char *output_multi_immediate (rtx *, const char *, const char *, + int, HOST_WIDE_INT); +static void print_multi_reg (FILE *, const char *, int, int); +static const char *shift_op (rtx, HOST_WIDE_INT *); +static struct machine_function *arm_init_machine_status (void); +static int number_of_first_bit_set (int); +static void replace_symbols_in_block (tree, rtx, rtx); +static void thumb_exit (FILE *, int, rtx); +static void thumb_pushpop (FILE *, int, int, int *, int); +static rtx is_jump_table (rtx); +static HOST_WIDE_INT get_jump_table_size (rtx); +static Mnode *move_minipool_fix_forward_ref (Mnode *, Mnode *, HOST_WIDE_INT); +static Mnode *add_minipool_forward_ref (Mfix *); +static Mnode *move_minipool_fix_backward_ref (Mnode *, Mnode *, HOST_WIDE_INT); +static Mnode *add_minipool_backward_ref (Mfix *); +static void assign_minipool_offsets (Mfix *); +static void arm_print_value (FILE *, rtx); +static void dump_minipool (rtx); +static int arm_barrier_cost (rtx); +static Mfix *create_fix_barrier (Mfix *, HOST_WIDE_INT); +static void push_minipool_barrier (rtx, HOST_WIDE_INT); +static void push_minipool_fix (rtx, HOST_WIDE_INT, rtx *, enum machine_mode, + rtx); +static void arm_reorg (void); +static bool note_invalid_constants (rtx, HOST_WIDE_INT, int); +static int current_file_function_operand (rtx); +static unsigned long arm_compute_save_reg0_reg12_mask (void); +static unsigned long arm_compute_save_reg_mask (void); +static unsigned long arm_isr_value (tree); +static unsigned long arm_compute_func_type (void); +static tree arm_handle_fndecl_attribute (tree *, tree, tree, int, bool *); +static tree arm_handle_isr_attribute (tree *, tree, tree, int, bool *); +static void arm_output_function_epilogue (FILE *, HOST_WIDE_INT); +static void arm_output_function_prologue (FILE *, HOST_WIDE_INT); +static void thumb_output_function_prologue (FILE *, HOST_WIDE_INT); +static int arm_comp_type_attributes (tree, tree); +static void arm_set_default_type_attributes (tree); +static int arm_adjust_cost (rtx, rtx, rtx, int); +static int arm_use_dfa_pipeline_interface (void); +static int count_insns_for_constant (HOST_WIDE_INT, int); +static int arm_get_strip_length (int); +static bool arm_function_ok_for_sibcall (tree, tree); +static void arm_internal_label (FILE *, const char *, unsigned long); +static void arm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, + tree); +static int arm_rtx_costs_1 (rtx, enum rtx_code, enum rtx_code); +static bool arm_rtx_costs (rtx, int, int, int *); +static int arm_address_cost (rtx); +static bool arm_memory_load_p (rtx); +static bool arm_cirrus_insn_p (rtx); +static void cirrus_reorg (rtx); +static void arm_init_builtins (void); +static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); +static void arm_init_iwmmxt_builtins (void); +static rtx safe_vector_operand (rtx, enum machine_mode); +static rtx arm_expand_binop_builtin (enum insn_code, tree, rtx); +static rtx arm_expand_unop_builtin (enum insn_code, tree, rtx, int); +static rtx arm_expand_builtin (tree, rtx, rtx, enum machine_mode, int); + #ifdef OBJECT_FORMAT_ELF -static void arm_elf_asm_named_section PARAMS ((const char *, unsigned int)); +static void arm_elf_asm_named_section (const char *, unsigned int); #endif #ifndef ARM_PE -static void arm_encode_section_info PARAMS ((tree, int)); +static void arm_encode_section_info (tree, rtx, int); #endif #ifdef AOF_ASSEMBLER -static void aof_globalize_label PARAMS ((FILE *, const char *)); +static void aof_globalize_label (FILE *, const char *); +static void aof_dump_imports (FILE *); +static void aof_dump_pic_table (FILE *); +static void aof_file_start (void); +static void aof_file_end (void); #endif -static void arm_output_mi_thunk PARAMS ((FILE *, tree, - HOST_WIDE_INT, - HOST_WIDE_INT, tree)); - -#undef Hint -#undef Mmode -#undef Ulong -#undef Ccstar + /* Initialize the GCC target structure. */ #ifdef TARGET_DLLIMPORT_DECL_ATTRIBUTES @@ -152,6 +170,10 @@ static void arm_output_mi_thunk PARAMS ((FILE *, tree, #define TARGET_ASM_ALIGNED_SI_OP "\tDCD\t" #undef TARGET_ASM_GLOBALIZE_LABEL #define TARGET_ASM_GLOBALIZE_LABEL aof_globalize_label +#undef TARGET_ASM_FILE_START +#define TARGET_ASM_FILE_START aof_file_start +#undef TARGET_ASM_FILE_END +#define TARGET_ASM_FILE_END aof_file_end #else #undef TARGET_ASM_ALIGNED_SI_OP #define TARGET_ASM_ALIGNED_SI_OP NULL @@ -171,15 +193,12 @@ static void arm_output_mi_thunk PARAMS ((FILE *, tree, #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES arm_set_default_type_attributes -#undef TARGET_INIT_BUILTINS -#define TARGET_INIT_BUILTINS arm_init_builtins - -#undef TARGET_EXPAND_BUILTIN -#define TARGET_EXPAND_BUILTIN arm_expand_builtin - #undef TARGET_SCHED_ADJUST_COST #define TARGET_SCHED_ADJUST_COST arm_adjust_cost +#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE +#define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE arm_use_dfa_pipeline_interface + #undef TARGET_ENCODE_SECTION_INFO #ifdef ARM_PE #define TARGET_ENCODE_SECTION_INFO arm_pe_encode_section_info @@ -187,14 +206,33 @@ static void arm_output_mi_thunk PARAMS ((FILE *, tree, #define TARGET_ENCODE_SECTION_INFO arm_encode_section_info #endif -#undef TARGET_STRIP_NAME_ENCODING +#undef TARGET_STRIP_NAME_ENCODING #define TARGET_STRIP_NAME_ENCODING arm_strip_name_encoding -#undef TARGET_ASM_OUTPUT_MI_THUNK +#undef TARGET_ASM_INTERNAL_LABEL +#define TARGET_ASM_INTERNAL_LABEL arm_internal_label + +#undef TARGET_FUNCTION_OK_FOR_SIBCALL +#define TARGET_FUNCTION_OK_FOR_SIBCALL arm_function_ok_for_sibcall + +#undef TARGET_ASM_OUTPUT_MI_THUNK #define TARGET_ASM_OUTPUT_MI_THUNK arm_output_mi_thunk -#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK +#undef TARGET_ASM_CAN_OUTPUT_MI_THUNK #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall +#undef TARGET_RTX_COSTS +#define TARGET_RTX_COSTS arm_rtx_costs +#undef TARGET_ADDRESS_COST +#define TARGET_ADDRESS_COST arm_address_cost + +#undef TARGET_MACHINE_DEPENDENT_REORG +#define TARGET_MACHINE_DEPENDENT_REORG arm_reorg + +#undef TARGET_INIT_BUILTINS +#define TARGET_INIT_BUILTINS arm_init_builtins +#undef TARGET_EXPAND_BUILTIN +#define TARGET_EXPAND_BUILTIN arm_expand_builtin + struct gcc_target targetm = TARGET_INITIALIZER; /* Obstack for minipool constant handling. */ @@ -215,10 +253,10 @@ int making_const_table; rtx arm_compare_op0, arm_compare_op1; /* What type of floating point are we tuning for? */ -enum floating_point_type arm_fpu; +enum fputype arm_fpu_tune; /* What type of floating point instructions are available? */ -enum floating_point_type arm_fpu_arch; +enum fputype arm_fpu_arch; /* What program mode is the cpu running in? 26-bit mode or 32-bit mode. */ enum prog_mode_type arm_prgmode; @@ -240,8 +278,13 @@ int arm_structure_size_boundary = DEFAULT_STRUCTURE_SIZE_BOUNDARY; #define FL_THUMB (1 << 6) /* Thumb aware */ #define FL_LDSCHED (1 << 7) /* Load scheduling necessary */ #define FL_STRONG (1 << 8) /* StrongARM */ -#define FL_ARCH5E (1 << 9) /* DSP extenstions to v5 */ +#define FL_ARCH5E (1 << 9) /* DSP extensions to v5 */ #define FL_XSCALE (1 << 10) /* XScale */ +#define FL_CIRRUS (1 << 11) /* Cirrus/DSP. */ +#define FL_IWMMXT (1 << 29) /* XScale v2 or "Intel Wireless MMX technology". */ +#define FL_ARCH6J (1 << 12) /* Architecture rel 6. Adds + media instructions. */ +#define FL_VFPV2 (1 << 13) /* Vector Floating Point V2. */ /* The bits in this mask specify which instructions we are allowed to generate. */ @@ -274,12 +317,21 @@ int arm_ld_sched = 0; /* Nonzero if this chip is a StrongARM. */ int arm_is_strong = 0; +/* Nonzero if this chip supports Intel Wireless MMX technology. */ +int arm_arch_iwmmxt = 0; + /* Nonzero if this chip is an XScale. */ -int arm_is_xscale = 0; +int arm_arch_xscale = 0; + +/* Nonzero if tuning for XScale */ +int arm_tune_xscale = 0; /* Nonzero if this chip is an ARM6 or an ARM7. */ int arm_is_6_or_7 = 0; +/* Nonzero if this chip is a Cirrus/DSP. */ +int arm_is_cirrus = 0; + /* Nonzero if generating Thumb instructions. */ int thumb_code = 0; @@ -352,16 +404,17 @@ static const struct processors all_cores[] = {"arm700", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, {"arm700i", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, {"arm710", FL_MODE26 | FL_MODE32 }, - {"arm710t", FL_MODE26 | FL_MODE32 | FL_THUMB }, {"arm720", FL_MODE26 | FL_MODE32 }, - {"arm720t", FL_MODE26 | FL_MODE32 | FL_THUMB }, - {"arm740t", FL_MODE26 | FL_MODE32 | FL_THUMB }, {"arm710c", FL_MODE26 | FL_MODE32 }, {"arm7100", FL_MODE26 | FL_MODE32 }, {"arm7500", FL_MODE26 | FL_MODE32 }, - /* Doesn't have an external co-proc, but does have embedded fpu. */ + /* Doesn't have an external co-proc, but does have embedded fpa. */ {"arm7500fe", FL_CO_PROC | FL_MODE26 | FL_MODE32 }, + /* V4 Architecture Processors */ {"arm7tdmi", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB }, + {"arm710t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB }, + {"arm720t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB }, + {"arm740t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB }, {"arm8", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, {"arm810", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, {"arm9", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, @@ -370,14 +423,21 @@ static const struct processors all_cores[] = {"arm940t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, {"arm9tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED }, {"arm9e", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED }, + {"ep9312", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS }, {"strongarm", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, {"strongarm110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, {"strongarm1100", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, {"strongarm1110", FL_MODE26 | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_STRONG }, + /* V5 Architecture Processors */ {"arm10tdmi", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 }, {"arm1020t", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_ARCH5 }, + {"arm926ejs", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E }, + {"arm1026ejs", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E }, {"xscale", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE }, - + {"iwmmxt", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT }, + /* V6 Architecture Processors */ + {"arm1136js", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6J }, + {"arm1136jfs", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6J | FL_VFPV2 }, {NULL, 0} }; @@ -396,10 +456,13 @@ static const struct processors all_architectures[] = { "armv5", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 }, { "armv5t", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 }, { "armv5te", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E }, + { "armv6j", FL_CO_PROC | FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_ARCH5 | FL_ARCH5E | FL_ARCH6J }, + { "ep9312", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_LDSCHED | FL_CIRRUS }, + {"iwmmxt", FL_MODE32 | FL_FAST_MULT | FL_ARCH4 | FL_THUMB | FL_LDSCHED | FL_STRONG | FL_ARCH5 | FL_ARCH5E | FL_XSCALE | FL_IWMMXT }, { NULL, 0 } }; -/* This is a magic stucture. The 'string' field is magically filled in +/* This is a magic structure. The 'string' field is magically filled in with a pointer to the value specified by the user on the command line assuming that the user has specified such a value. */ @@ -413,8 +476,7 @@ struct arm_cpu_select arm_select[] = /* Return the number of bits set in VALUE. */ static unsigned -bit_count (value) - unsigned long value; +bit_count (unsigned long value) { unsigned long count = 0; @@ -430,7 +492,7 @@ bit_count (value) /* Fix up any incompatible options that the user has specified. This has now turned into a maze. */ void -arm_override_options () +arm_override_options (void) { unsigned i; @@ -493,6 +555,12 @@ arm_override_options () { TARGET_CPU_arm9, "arm9" }, { TARGET_CPU_strongarm, "strongarm" }, { TARGET_CPU_xscale, "xscale" }, + { TARGET_CPU_ep9312, "ep9312" }, + { TARGET_CPU_iwmmxt, "iwmmxt" }, + { TARGET_CPU_arm926ej_s, "arm926ej-s" }, + { TARGET_CPU_arm1026ej_s, "arm1026ej-s" }, + { TARGET_CPU_arm1136j_s, "arm1136j_s" }, + { TARGET_CPU_arm1136jf_s, "arm1136jf_s" }, { TARGET_CPU_generic, "arm" }, { 0, 0 } }; @@ -622,6 +690,9 @@ arm_override_options () target_flags &= ~ARM_FLAG_THUMB; } + if (!TARGET_APCS_32) + inform ("future releases of GCC will not support -mapcs-26"); + if (TARGET_APCS_FRAME && TARGET_THUMB) { /* warning ("ignoring -mapcs-frame because -mthumb was used"); */ @@ -684,40 +755,62 @@ arm_override_options () arm_arch4 = (insn_flags & FL_ARCH4) != 0; arm_arch5 = (insn_flags & FL_ARCH5) != 0; arm_arch5e = (insn_flags & FL_ARCH5E) != 0; - arm_is_xscale = (insn_flags & FL_XSCALE) != 0; + arm_arch_xscale = (insn_flags & FL_XSCALE) != 0; arm_ld_sched = (tune_flags & FL_LDSCHED) != 0; arm_is_strong = (tune_flags & FL_STRONG) != 0; thumb_code = (TARGET_ARM == 0); arm_is_6_or_7 = (((tune_flags & (FL_MODE26 | FL_MODE32)) && !(tune_flags & FL_ARCH4))) != 0; + arm_tune_xscale = (tune_flags & FL_XSCALE) != 0; + arm_is_cirrus = (tune_flags & FL_CIRRUS) != 0; + arm_arch_iwmmxt = (insn_flags & FL_IWMMXT) != 0; - /* Default value for floating point code... if no co-processor - bus, then schedule for emulated floating point. Otherwise, - assume the user has an FPA. - Note: this does not prevent use of floating point instructions, - -msoft-float does that. */ - arm_fpu = (tune_flags & FL_CO_PROC) ? FP_HARD : FP_SOFT3; + if (TARGET_IWMMXT && (! TARGET_ATPCS)) + target_flags |= ARM_FLAG_ATPCS; + + if (arm_is_cirrus) + { + arm_fpu_tune = FPUTYPE_MAVERICK; + + /* Ignore -mhard-float if -mcpu=ep9312. */ + if (TARGET_HARD_FLOAT) + target_flags ^= ARM_FLAG_SOFT_FLOAT; + } + else + /* Default value for floating point code... if no co-processor + bus, then schedule for emulated floating point. Otherwise, + assume the user has an FPA. + Note: this does not prevent use of floating point instructions, + -msoft-float does that. */ + arm_fpu_tune = (tune_flags & FL_CO_PROC) ? FPUTYPE_FPA : FPUTYPE_FPA_EMU3; if (target_fp_name) { if (streq (target_fp_name, "2")) - arm_fpu_arch = FP_SOFT2; + arm_fpu_arch = FPUTYPE_FPA_EMU2; else if (streq (target_fp_name, "3")) - arm_fpu_arch = FP_SOFT3; + arm_fpu_arch = FPUTYPE_FPA_EMU3; else error ("invalid floating point emulation option: -mfpe-%s", target_fp_name); } else - arm_fpu_arch = FP_DEFAULT; + arm_fpu_arch = FPUTYPE_DEFAULT; - if (TARGET_FPE && arm_fpu != FP_HARD) - arm_fpu = FP_SOFT2; + if (TARGET_FPE) + { + if (arm_fpu_tune == FPUTYPE_FPA_EMU3) + arm_fpu_tune = FPUTYPE_FPA_EMU2; + else if (arm_fpu_tune == FPUTYPE_MAVERICK) + warning ("-mfpe switch not supported by ep9312 target cpu - ignored."); + else if (arm_fpu_tune != FPUTYPE_FPA) + arm_fpu_tune = FPUTYPE_FPA_EMU2; + } /* For arm2/3 there is no need to do any scheduling if there is only a floating point emulator, or we are doing software floating-point. */ - if ((TARGET_SOFT_FLOAT || arm_fpu != FP_HARD) + if ((TARGET_SOFT_FLOAT || arm_fpu_tune != FPUTYPE_FPA) && (tune_flags & FL_MODE32) == 0) flag_schedule_insns = flag_schedule_insns_after_reload = 0; @@ -756,30 +849,44 @@ arm_override_options () flag_schedule_insns = 0; } - /* If optimizing for space, don't synthesize constants. - For processors with load scheduling, it never costs more than 2 cycles - to load a constant, and the load scheduler may well reduce that to 1. */ - if (optimize_size || (tune_flags & FL_LDSCHED)) - arm_constant_limit = 1; - - if (arm_is_xscale) - arm_constant_limit = 2; - - /* If optimizing for size, bump the number of instructions that we - are prepared to conditionally execute (even on a StrongARM). - Otherwise for the StrongARM, which has early execution of branches, - a sequence that is worth skipping is shorter. */ if (optimize_size) - max_insns_skipped = 6; - else if (arm_is_strong) - max_insns_skipped = 3; + { + /* There's some dispute as to whether this should be 1 or 2. However, + experiments seem to show that in pathological cases a setting of + 1 degrades less severely than a setting of 2. This could change if + other parts of the compiler change their behavior. */ + arm_constant_limit = 1; + + /* If optimizing for size, bump the number of instructions that we + are prepared to conditionally execute (even on a StrongARM). */ + max_insns_skipped = 6; + } + else + { + /* For processors with load scheduling, it never costs more than + 2 cycles to load a constant, and the load scheduler may well + reduce that to 1. */ + if (tune_flags & FL_LDSCHED) + arm_constant_limit = 1; + + /* On XScale the longer latency of a load makes it more difficult + to achieve a good schedule, so it's faster to synthesize + constants that can be done in two insns. */ + if (arm_tune_xscale) + arm_constant_limit = 2; + + /* StrongARM has early execution of branches, so a sequence + that is worth skipping is shorter. */ + if (arm_is_strong) + max_insns_skipped = 3; + } /* Register global variables with the garbage collector. */ arm_add_gc_roots (); } static void -arm_add_gc_roots () +arm_add_gc_roots (void) { gcc_obstack_init(&minipool_obstack); minipool_startobj = (char *) obstack_alloc (&minipool_obstack, 0); @@ -816,8 +923,7 @@ static const isr_attribute_arg isr_attribute_args [] = function, or ARM_FT_UNKNOWN if the type cannot be determined. */ static unsigned long -arm_isr_value (argument) - tree argument; +arm_isr_value (tree argument) { const isr_attribute_arg * ptr; const char * arg; @@ -834,7 +940,7 @@ arm_isr_value (argument) arg = TREE_STRING_POINTER (TREE_VALUE (argument)); /* Check it against the list of known arguments. */ - for (ptr = isr_attribute_args; ptr->arg != NULL; ptr ++) + for (ptr = isr_attribute_args; ptr->arg != NULL; ptr++) if (streq (arg, ptr->arg)) return ptr->return_value; @@ -845,7 +951,7 @@ arm_isr_value (argument) /* Computes the type of the current function. */ static unsigned long -arm_compute_func_type () +arm_compute_func_type (void) { unsigned long type = ARM_FT_UNKNOWN; tree a; @@ -892,7 +998,7 @@ arm_compute_func_type () /* Returns the type of the current function. */ unsigned long -arm_current_func_type () +arm_current_func_type (void) { if (ARM_FUNC_TYPE (cfun->machine->func_type) == ARM_FT_UNKNOWN) cfun->machine->func_type = arm_compute_func_type (); @@ -900,20 +1006,22 @@ arm_current_func_type () return cfun->machine->func_type; } -/* Return 1 if it is possible to return using a single instruction. */ +/* Return 1 if it is possible to return using a single instruction. + If SIBLING is non-null, this is a test for a return before a sibling + call. SIBLING is the call insn, so we can examine its register usage. */ int -use_return_insn (iscond) - int iscond; +use_return_insn (int iscond, rtx sibling) { int regno; unsigned int func_type; unsigned long saved_int_regs; + unsigned HOST_WIDE_INT stack_adjust; /* Never use a return instruction before reload has run. */ if (!reload_completed) return 0; - + func_type = arm_current_func_type (); /* Naked functions and volatile functions need special @@ -924,19 +1032,61 @@ use_return_insn (iscond) /* So do interrupt functions that use the frame pointer. */ if (IS_INTERRUPT (func_type) && frame_pointer_needed) return 0; - + + stack_adjust = arm_get_frame_size () + current_function_outgoing_args_size; + /* As do variadic functions. */ if (current_function_pretend_args_size || cfun->machine->uses_anonymous_args - /* Of if the function calls __builtin_eh_return () */ + /* Or if the function calls __builtin_eh_return () */ || ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER - /* Or if there is no frame pointer and there is a stack adjustment. */ - || ((arm_get_frame_size () + current_function_outgoing_args_size != 0) - && !frame_pointer_needed)) + /* Or if the function calls alloca */ + || current_function_calls_alloca + /* Or if there is a stack adjustment. However, if the stack pointer + is saved on the stack, we can use a pre-incrementing stack load. */ + || !(stack_adjust == 0 || (frame_pointer_needed && stack_adjust == 4))) return 0; saved_int_regs = arm_compute_save_reg_mask (); + /* Unfortunately, the insn + + ldmib sp, {..., sp, ...} + + triggers a bug on most SA-110 based devices, such that the stack + pointer won't be correctly restored if the instruction takes a + page fault. We work around this problem by popping r3 along with + the other registers, since that is never slower than executing + another instruction. + + We test for !arm_arch5 here, because code for any architecture + less than this could potentially be run on one of the buggy + chips. */ + if (stack_adjust == 4 && !arm_arch5) + { + /* Validate that r3 is a call-clobbered register (always true in + the default abi) ... */ + if (!call_used_regs[3]) + return 0; + + /* ... that it isn't being used for a return value (always true + until we implement return-in-regs), or for a tail-call + argument ... */ + if (sibling) + { + if (GET_CODE (sibling) != CALL_INSN) + abort (); + + if (find_regno_fusage (sibling, USE, 3)) + return 0; + } + + /* ... and that there are no call-saved registers in r0-r2 + (always true in the default ABI). */ + if (saved_int_regs & 0x7) + return 0; + } + /* Can't be done if interworking with Thumb, and any registers have been stacked. */ if (TARGET_INTERWORK && saved_int_regs != 0) @@ -960,21 +1110,25 @@ use_return_insn (iscond) if (saved_int_regs && !(saved_int_regs & (1 << LR_REGNUM))) return 0; - /* Can't be done if any of the FPU regs are pushed, + /* Can't be done if any of the FPA regs are pushed, since this also requires an insn. */ if (TARGET_HARD_FLOAT) for (regno = FIRST_ARM_FP_REGNUM; regno <= LAST_ARM_FP_REGNUM; regno++) if (regs_ever_live[regno] && !call_used_regs[regno]) return 0; + if (TARGET_REALLY_IWMMXT) + for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++) + if (regs_ever_live[regno] && ! call_used_regs [regno]) + return 0; + return 1; } /* Return TRUE if int I is a valid immediate ARM constant. */ int -const_ok_for_arm (i) - HOST_WIDE_INT i; +const_ok_for_arm (HOST_WIDE_INT i) { unsigned HOST_WIDE_INT mask = ~(unsigned HOST_WIDE_INT)0xFF; @@ -1005,9 +1159,7 @@ const_ok_for_arm (i) /* Return true if I is a valid constant for the operation CODE. */ static int -const_ok_for_op (i, code) - HOST_WIDE_INT i; - enum rtx_code code; +const_ok_for_op (HOST_WIDE_INT i, enum rtx_code code) { if (const_ok_for_arm (i)) return 1; @@ -1041,13 +1193,8 @@ const_ok_for_op (i, code) Return value is the number of insns emitted. */ int -arm_split_constant (code, mode, val, target, source, subtargets) - enum rtx_code code; - enum machine_mode mode; - HOST_WIDE_INT val; - rtx target; - rtx source; - int subtargets; +arm_split_constant (enum rtx_code code, enum machine_mode mode, + HOST_WIDE_INT val, rtx target, rtx source, int subtargets) { if (subtargets || code == SET || (GET_CODE (target) == REG && GET_CODE (source) == REG @@ -1095,9 +1242,7 @@ arm_split_constant (code, mode, val, target, source, subtargets) } static int -count_insns_for_constant (remainder, i) - HOST_WIDE_INT remainder; - int i; +count_insns_for_constant (HOST_WIDE_INT remainder, int i) { HOST_WIDE_INT temp1; int num_insns = 0; @@ -1127,14 +1272,9 @@ count_insns_for_constant (remainder, i) RTL generation. */ static int -arm_gen_constant (code, mode, val, target, source, subtargets, generate) - enum rtx_code code; - enum machine_mode mode; - HOST_WIDE_INT val; - rtx target; - rtx source; - int subtargets; - int generate; +arm_gen_constant (enum rtx_code code, enum machine_mode mode, + HOST_WIDE_INT val, rtx target, rtx source, int subtargets, + int generate) { int can_invert = 0; int can_negate = 0; @@ -1709,9 +1849,7 @@ arm_gen_constant (code, mode, val, target, source, subtargets, generate) immediate value easier to load. */ enum rtx_code -arm_canonicalize_comparison (code, op1) - enum rtx_code code; - rtx * op1; +arm_canonicalize_comparison (enum rtx_code code, rtx * op1) { unsigned HOST_WIDE_INT i = INTVAL (*op1); @@ -1771,10 +1909,8 @@ arm_canonicalize_comparison (code, op1) /* Decide whether a type should be returned in memory (true) or in a register (false). This is called by the macro RETURN_IN_MEMORY. */ - int -arm_return_in_memory (type) - tree type; +arm_return_in_memory (tree type) { HOST_WIDE_INT size; @@ -1791,12 +1927,12 @@ arm_return_in_memory (type) return (size < 0 || size > UNITS_PER_WORD); } - /* For the arm-wince targets we choose to be compitable with Microsoft's + /* For the arm-wince targets we choose to be compatible with Microsoft's ARM and Thumb compilers, which always return aggregates in memory. */ #ifndef ARM_WINCE /* All structures/unions bigger than one word are returned in memory. Also catch the case where int_size_in_bytes returns -1. In this case - the aggregate is either huge or of varaible size, and in either case + the aggregate is either huge or of variable size, and in either case we will want to return it via memory and not in a register. */ if (size < 0 || size > UNITS_PER_WORD) return 1; @@ -1876,11 +2012,13 @@ arm_return_in_memory (type) return 1; } -/* Indicate whether or not words of a double are in big-endian order. */ +/* Indicate whether or not words of a double are in big-endian order. */ int -arm_float_words_big_endian () +arm_float_words_big_endian (void) { + if (TARGET_CIRRUS) + return 0; /* For FPA, float words are always big-endian. For VFP, floats words follow the memory system mode. */ @@ -1901,14 +2039,13 @@ arm_float_words_big_endian () for a call to a function whose data type is FNTYPE. For a library call, FNTYPE is NULL. */ void -arm_init_cumulative_args (pcum, fntype, libname, indirect) - CUMULATIVE_ARGS * pcum; - tree fntype; - rtx libname ATTRIBUTE_UNUSED; - int indirect ATTRIBUTE_UNUSED; +arm_init_cumulative_args (CUMULATIVE_ARGS *pcum, tree fntype, + rtx libname ATTRIBUTE_UNUSED, + tree fndecl ATTRIBUTE_UNUSED) { /* On the ARM, the offset starts at 0. */ - pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype))) ? 1 : 0); + pcum->nregs = ((fntype && aggregate_value_p (TREE_TYPE (fntype), fntype)) ? 1 : 0); + pcum->iwmmxt_nregs = 0; pcum->call_cookie = CALL_NORMAL; @@ -1924,6 +2061,24 @@ arm_init_cumulative_args (pcum, fntype, libname, indirect) else if (lookup_attribute ("long_call", TYPE_ATTRIBUTES (fntype))) pcum->call_cookie = CALL_LONG; } + + /* Varargs vectors are treated the same as long long. + named_count avoids having to change the way arm handles 'named' */ + pcum->named_count = 0; + pcum->nargs = 0; + + if (TARGET_REALLY_IWMMXT && fntype) + { + tree fn_arg; + + for (fn_arg = TYPE_ARG_TYPES (fntype); + fn_arg; + fn_arg = TREE_CHAIN (fn_arg)) + pcum->named_count += 1; + + if (! pcum->named_count) + pcum->named_count = INT_MAX; + } } /* Determine where to put an argument to a function. @@ -1940,12 +2095,33 @@ arm_init_cumulative_args (pcum, fntype, libname, indirect) (otherwise it is an extra parameter matching an ellipsis). */ rtx -arm_function_arg (pcum, mode, type, named) - CUMULATIVE_ARGS * pcum; - enum machine_mode mode; - tree type ATTRIBUTE_UNUSED; - int named; +arm_function_arg (CUMULATIVE_ARGS *pcum, enum machine_mode mode, + tree type ATTRIBUTE_UNUSED, int named) { + if (TARGET_REALLY_IWMMXT) + { + if (VECTOR_MODE_SUPPORTED_P (mode)) + { + /* varargs vectors are treated the same as long long. + named_count avoids having to change the way arm handles 'named' */ + if (pcum->named_count <= pcum->nargs + 1) + { + if (pcum->nregs == 1) + pcum->nregs += 1; + if (pcum->nregs <= 2) + return gen_rtx_REG (mode, pcum->nregs); + else + return NULL_RTX; + } + else if (pcum->iwmmxt_nregs <= 9) + return gen_rtx_REG (mode, pcum->iwmmxt_nregs + FIRST_IWMMXT_REGNUM); + else + return NULL_RTX; + } + else if ((mode == DImode || mode == DFmode) && pcum->nregs & 1) + pcum->nregs += 1; + } + if (mode == VOIDmode) /* Compute operand 2 of the call insn. */ return GEN_INT (pcum->call_cookie); @@ -1960,11 +2136,9 @@ arm_function_arg (pcum, mode, type, named) extension to the ARM ABI. */ int -arm_function_arg_pass_by_reference (cum, mode, type, named) - CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED; - enum machine_mode mode ATTRIBUTE_UNUSED; - tree type; - int named ATTRIBUTE_UNUSED; +arm_function_arg_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED, + enum machine_mode mode ATTRIBUTE_UNUSED, + tree type, int named ATTRIBUTE_UNUSED) { return type && TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST; } @@ -1972,8 +2146,7 @@ arm_function_arg_pass_by_reference (cum, mode, type, named) /* Implement va_arg. */ rtx -arm_va_arg (valist, type) - tree valist, type; +arm_va_arg (tree valist, tree type) { /* Variable sized types are passed by reference. */ if (TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST) @@ -1982,6 +2155,26 @@ arm_va_arg (valist, type) return gen_rtx_MEM (ptr_mode, force_reg (Pmode, addr)); } + if (FUNCTION_ARG_BOUNDARY (TYPE_MODE (type), NULL) == IWMMXT_ALIGNMENT) + { + tree minus_eight; + tree t; + + /* Maintain 64-bit alignment of the valist pointer by + constructing: valist = ((valist + (8 - 1)) & -8). */ + minus_eight = build_int_2 (- (IWMMXT_ALIGNMENT / BITS_PER_UNIT), -1); + t = build_int_2 ((IWMMXT_ALIGNMENT / BITS_PER_UNIT) - 1, 0); + t = build (PLUS_EXPR, TREE_TYPE (valist), valist, t); + t = build (BIT_AND_EXPR, TREE_TYPE (t), t, minus_eight); + t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t); + TREE_SIDE_EFFECTS (t) = 1; + expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); + + /* This is to stop the combine pass optimizing + away the alignment adjustment. */ + mark_reg_pointer (arg_pointer_rtx, PARM_BOUNDARY); + } + return std_expand_builtin_va_arg (valist, type); } @@ -1996,22 +2189,19 @@ typedef enum static arm_pragma_enum arm_pragma_long_calls = OFF; void -arm_pr_long_calls (pfile) - cpp_reader * pfile ATTRIBUTE_UNUSED; +arm_pr_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED) { arm_pragma_long_calls = LONG; } void -arm_pr_no_long_calls (pfile) - cpp_reader * pfile ATTRIBUTE_UNUSED; +arm_pr_no_long_calls (struct cpp_reader * pfile ATTRIBUTE_UNUSED) { arm_pragma_long_calls = SHORT; } void -arm_pr_long_calls_off (pfile) - cpp_reader * pfile ATTRIBUTE_UNUSED; +arm_pr_long_calls_off (struct cpp_reader * pfile ATTRIBUTE_UNUSED) { arm_pragma_long_calls = OFF; } @@ -2050,14 +2240,9 @@ const struct attribute_spec arm_attribute_table[] = /* Handle an attribute requiring a FUNCTION_DECL; arguments as in struct attribute_spec.handler. */ - static tree -arm_handle_fndecl_attribute (node, name, args, flags, no_add_attrs) - tree * node; - tree name; - tree args ATTRIBUTE_UNUSED; - int flags ATTRIBUTE_UNUSED; - bool * no_add_attrs; +arm_handle_fndecl_attribute (tree *node, tree name, tree args ATTRIBUTE_UNUSED, + int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) { if (TREE_CODE (*node) != FUNCTION_DECL) { @@ -2071,14 +2256,9 @@ arm_handle_fndecl_attribute (node, name, args, flags, no_add_attrs) /* Handle an "interrupt" or "isr" attribute; arguments as in struct attribute_spec.handler. */ - static tree -arm_handle_isr_attribute (node, name, args, flags, no_add_attrs) - tree * node; - tree name; - tree args; - int flags; - bool * no_add_attrs; +arm_handle_isr_attribute (tree *node, tree name, tree args, int flags, + bool *no_add_attrs) { if (DECL_P (*node)) { @@ -2136,11 +2316,8 @@ arm_handle_isr_attribute (node, name, args, flags, no_add_attrs) /* Return 0 if the attributes for two types are incompatible, 1 if they are compatible, and 2 if they are nearly compatible (which causes a warning to be generated). */ - static int -arm_comp_type_attributes (type1, type2) - tree type1; - tree type2; +arm_comp_type_attributes (tree type1, tree type2) { int l1, l2, s1, s2; @@ -2181,11 +2358,8 @@ arm_comp_type_attributes (type1, type2) /* Encode long_call or short_call attribute by prefixing symbol name in DECL with a special character FLAG. */ - void -arm_encode_call_attribute (decl, flag) - tree decl; - int flag; +arm_encode_call_attribute (tree decl, int flag) { const char * str = XSTR (XEXP (DECL_RTL (decl), 0), 0); int len = strlen (str); @@ -2206,10 +2380,8 @@ arm_encode_call_attribute (decl, flag) /* Assigns default attributes to newly defined type. This is used to set short_call/long_call attributes for function types of functions defined inside corresponding #pragma scopes. */ - static void -arm_set_default_type_attributes (type) - tree type; +arm_set_default_type_attributes (tree type) { /* Add __attribute__ ((long_call)) to all functions, when inside #pragma long_calls or __attribute__ ((short_call)), @@ -2232,12 +2404,10 @@ arm_set_default_type_attributes (type) } /* Return 1 if the operand is a SYMBOL_REF for a function known to be - defined within the current compilation unit. If this caanot be + defined within the current compilation unit. If this cannot be determined, then 0 is returned. */ - static int -current_file_function_operand (sym_ref) - rtx sym_ref; +current_file_function_operand (rtx sym_ref) { /* This is a bit of a fib. A function will have a short call flag applied to its name if it has the short call attribute, or it has @@ -2277,12 +2447,8 @@ current_file_function_operand (sym_ref) "call_symbol" and "call_symbol_value" patterns and to 0 in the "call" and "call_value" patterns. This is because of the difference in the SYM_REFs passed by these patterns. */ - int -arm_is_longcall_p (sym_ref, call_cookie, call_symbol) - rtx sym_ref; - int call_cookie; - int call_symbol; +arm_is_longcall_p (rtx sym_ref, int call_cookie, int call_symbol) { if (!call_symbol) { @@ -2310,17 +2476,18 @@ arm_is_longcall_p (sym_ref, call_cookie, call_symbol) } /* Return nonzero if it is ok to make a tail-call to DECL. */ - -int -arm_function_ok_for_sibcall (decl) - tree decl; +static bool +arm_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) { int call_type = TARGET_LONG_CALLS ? CALL_LONG : CALL_NORMAL; + if (cfun->machine->sibcall_blocked) + return false; + /* Never tailcall something for which we have no decl, or if we are in Thumb mode. */ if (decl == NULL || TARGET_THUMB) - return 0; + return false; /* Get the calling method. */ if (lookup_attribute ("short_call", TYPE_ATTRIBUTES (TREE_TYPE (decl)))) @@ -2332,26 +2499,29 @@ arm_function_ok_for_sibcall (decl) a branch instruction. However, if not compiling PIC, we know we can reach the symbol if it is in this compilation unit. */ if (call_type == CALL_LONG && (flag_pic || !TREE_ASM_WRITTEN (decl))) - return 0; + return false; /* If we are interworking and the function is not declared static then we can't tail-call it unless we know that it exists in this compilation unit (since it might be a Thumb routine). */ if (TARGET_INTERWORK && TREE_PUBLIC (decl) && !TREE_ASM_WRITTEN (decl)) - return 0; + return false; /* Never tailcall from an ISR routine - it needs a special exit sequence. */ if (IS_INTERRUPT (arm_current_func_type ())) - return 0; + return false; /* Everything else is ok. */ - return 1; + return true; } +/* Addressing mode support functions. */ + +/* Return nonzero if X is a legitimate immediate operand when compiling + for PIC. */ int -legitimate_pic_operand_p (x) - rtx x; +legitimate_pic_operand_p (rtx x) { if (CONSTANT_P (x) && flag_pic @@ -2365,10 +2535,7 @@ legitimate_pic_operand_p (x) } rtx -legitimize_pic_address (orig, mode, reg) - rtx orig; - enum machine_mode mode; - rtx reg; +legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg) { if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF) @@ -2406,7 +2573,7 @@ legitimize_pic_address (orig, mode, reg) if ((GET_CODE (orig) == LABEL_REF || (GET_CODE (orig) == SYMBOL_REF && - ENCODED_SHORT_CALL_ATTR_P (XSTR (orig, 0)))) + SYMBOL_REF_LOCAL_P (orig))) && NEED_GOT_RELOC) pic_ref = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, address); else @@ -2455,14 +2622,14 @@ legitimize_pic_address (orig, mode, reg) { /* The base register doesn't really matter, we only want to test the index for the appropriate mode. */ - ARM_GO_IF_LEGITIMATE_INDEX (mode, 0, offset, win); - - if (!no_new_pseudos) - offset = force_reg (Pmode, offset); - else - abort (); + if (!arm_legitimate_index_p (mode, offset, 0)) + { + if (!no_new_pseudos) + offset = force_reg (Pmode, offset); + else + abort (); + } - win: if (GET_CODE (offset) == CONST_INT) return plus_constant (base, INTVAL (offset)); } @@ -2486,10 +2653,8 @@ legitimize_pic_address (orig, mode, reg) generated insns at the start of the function); false if called by an exception receiver that needs the PIC register reloaded (in which case the insns are just dumped at the current location). */ - void -arm_finalize_pic (prologue) - int prologue ATTRIBUTE_UNUSED; +arm_finalize_pic (int prologue ATTRIBUTE_UNUSED) { #ifndef AOF_ASSEMBLER rtx l1, pic_tmp, pic_tmp2, seq, pic_rtx; @@ -2540,6 +2705,417 @@ arm_finalize_pic (prologue) #endif /* AOF_ASSEMBLER */ } +/* Return nonzero if X is valid as an ARM state addressing register. */ +static int +arm_address_register_rtx_p (rtx x, int strict_p) +{ + int regno; + + if (GET_CODE (x) != REG) + return 0; + + regno = REGNO (x); + + if (strict_p) + return ARM_REGNO_OK_FOR_BASE_P (regno); + + return (regno <= LAST_ARM_REGNUM + || regno >= FIRST_PSEUDO_REGISTER + || regno == FRAME_POINTER_REGNUM + || regno == ARG_POINTER_REGNUM); +} + +/* Return nonzero if X is a valid ARM state address operand. */ +int +arm_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) +{ + if (arm_address_register_rtx_p (x, strict_p)) + return 1; + + else if (GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_DEC) + return arm_address_register_rtx_p (XEXP (x, 0), strict_p); + + else if ((GET_CODE (x) == POST_MODIFY || GET_CODE (x) == PRE_MODIFY) + && GET_MODE_SIZE (mode) <= 4 + && arm_address_register_rtx_p (XEXP (x, 0), strict_p) + && GET_CODE (XEXP (x, 1)) == PLUS + && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0))) + return arm_legitimate_index_p (mode, XEXP (XEXP (x, 1), 1), strict_p); + + /* After reload constants split into minipools will have addresses + from a LABEL_REF. */ + else if (reload_completed + && (GET_CODE (x) == LABEL_REF + || (GET_CODE (x) == CONST + && GET_CODE (XEXP (x, 0)) == PLUS + && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) + return 1; + + else if (mode == TImode) + return 0; + + else if (mode == DImode || (TARGET_SOFT_FLOAT && mode == DFmode)) + { + if (GET_CODE (x) == PLUS + && arm_address_register_rtx_p (XEXP (x, 0), strict_p) + && GET_CODE (XEXP (x, 1)) == CONST_INT) + { + HOST_WIDE_INT val = INTVAL (XEXP (x, 1)); + + if (val == 4 || val == -4 || val == -8) + return 1; + } + } + + else if (GET_CODE (x) == PLUS) + { + rtx xop0 = XEXP (x, 0); + rtx xop1 = XEXP (x, 1); + + return ((arm_address_register_rtx_p (xop0, strict_p) + && arm_legitimate_index_p (mode, xop1, strict_p)) + || (arm_address_register_rtx_p (xop1, strict_p) + && arm_legitimate_index_p (mode, xop0, strict_p))); + } + +#if 0 + /* Reload currently can't handle MINUS, so disable this for now */ + else if (GET_CODE (x) == MINUS) + { + rtx xop0 = XEXP (x, 0); + rtx xop1 = XEXP (x, 1); + + return (arm_address_register_rtx_p (xop0, strict_p) + && arm_legitimate_index_p (mode, xop1, strict_p)); + } +#endif + + else if (GET_MODE_CLASS (mode) != MODE_FLOAT + && GET_CODE (x) == SYMBOL_REF + && CONSTANT_POOL_ADDRESS_P (x) + && ! (flag_pic + && symbol_mentioned_p (get_pool_constant (x)))) + return 1; + + else if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == POST_DEC) + && (GET_MODE_SIZE (mode) <= 4) + && arm_address_register_rtx_p (XEXP (x, 0), strict_p)) + return 1; + + return 0; +} + +/* Return nonzero if INDEX is valid for an address index operand in + ARM state. */ +static int +arm_legitimate_index_p (enum machine_mode mode, rtx index, int strict_p) +{ + HOST_WIDE_INT range; + enum rtx_code code = GET_CODE (index); + + if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) + return (code == CONST_INT && INTVAL (index) < 1024 + && INTVAL (index) > -1024 + && (INTVAL (index) & 3) == 0); + + if (TARGET_CIRRUS + && (GET_MODE_CLASS (mode) == MODE_FLOAT || mode == DImode)) + return (code == CONST_INT + && INTVAL (index) < 255 + && INTVAL (index) > -255); + + if (arm_address_register_rtx_p (index, strict_p) + && GET_MODE_SIZE (mode) <= 4) + return 1; + + if (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (mode)) + return (code == CONST_INT + && INTVAL (index) < 256 + && INTVAL (index) > -256); + + /* XXX What about ldrsb? */ + if (GET_MODE_SIZE (mode) <= 4 && code == MULT + && (!arm_arch4 || (mode) != HImode)) + { + rtx xiop0 = XEXP (index, 0); + rtx xiop1 = XEXP (index, 1); + + return ((arm_address_register_rtx_p (xiop0, strict_p) + && power_of_two_operand (xiop1, SImode)) + || (arm_address_register_rtx_p (xiop1, strict_p) + && power_of_two_operand (xiop0, SImode))); + } + + if (GET_MODE_SIZE (mode) <= 4 + && (code == LSHIFTRT || code == ASHIFTRT + || code == ASHIFT || code == ROTATERT) + && (!arm_arch4 || (mode) != HImode)) + { + rtx op = XEXP (index, 1); + + return (arm_address_register_rtx_p (XEXP (index, 0), strict_p) + && GET_CODE (op) == CONST_INT + && INTVAL (op) > 0 + && INTVAL (op) <= 31); + } + + /* XXX For ARM v4 we may be doing a sign-extend operation during the + load, but that has a restricted addressing range and we are unable + to tell here whether that is the case. To be safe we restrict all + loads to that range. */ + if (arm_arch4) + range = (mode == HImode || mode == QImode) ? 256 : 4096; + else + range = (mode == HImode) ? 4095 : 4096; + + return (code == CONST_INT + && INTVAL (index) < range + && INTVAL (index) > -range); +} + +/* Return nonzero if X is valid as a Thumb state base register. */ +static int +thumb_base_register_rtx_p (rtx x, enum machine_mode mode, int strict_p) +{ + int regno; + + if (GET_CODE (x) != REG) + return 0; + + regno = REGNO (x); + + if (strict_p) + return THUMB_REGNO_MODE_OK_FOR_BASE_P (regno, mode); + + return (regno <= LAST_LO_REGNUM + || regno > LAST_VIRTUAL_REGISTER + || regno == FRAME_POINTER_REGNUM + || (GET_MODE_SIZE (mode) >= 4 + && (regno == STACK_POINTER_REGNUM + || regno >= FIRST_PSEUDO_REGISTER + || x == hard_frame_pointer_rtx + || x == arg_pointer_rtx))); +} + +/* Return nonzero if x is a legitimate index register. This is the case + for any base register that can access a QImode object. */ +inline static int +thumb_index_register_rtx_p (rtx x, int strict_p) +{ + return thumb_base_register_rtx_p (x, QImode, strict_p); +} + +/* Return nonzero if x is a legitimate Thumb-state address. + + The AP may be eliminated to either the SP or the FP, so we use the + least common denominator, e.g. SImode, and offsets from 0 to 64. + + ??? Verify whether the above is the right approach. + + ??? Also, the FP may be eliminated to the SP, so perhaps that + needs special handling also. + + ??? Look at how the mips16 port solves this problem. It probably uses + better ways to solve some of these problems. + + Although it is not incorrect, we don't accept QImode and HImode + addresses based on the frame pointer or arg pointer until the + reload pass starts. This is so that eliminating such addresses + into stack based ones won't produce impossible code. */ +int +thumb_legitimate_address_p (enum machine_mode mode, rtx x, int strict_p) +{ + /* ??? Not clear if this is right. Experiment. */ + if (GET_MODE_SIZE (mode) < 4 + && !(reload_in_progress || reload_completed) + && (reg_mentioned_p (frame_pointer_rtx, x) + || reg_mentioned_p (arg_pointer_rtx, x) + || reg_mentioned_p (virtual_incoming_args_rtx, x) + || reg_mentioned_p (virtual_outgoing_args_rtx, x) + || reg_mentioned_p (virtual_stack_dynamic_rtx, x) + || reg_mentioned_p (virtual_stack_vars_rtx, x))) + return 0; + + /* Accept any base register. SP only in SImode or larger. */ + else if (thumb_base_register_rtx_p (x, mode, strict_p)) + return 1; + + /* This is PC relative data before arm_reorg runs. */ + else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x) + && GET_CODE (x) == SYMBOL_REF + && CONSTANT_POOL_ADDRESS_P (x) && ! flag_pic) + return 1; + + /* This is PC relative data after arm_reorg runs. */ + else if (GET_MODE_SIZE (mode) >= 4 && reload_completed + && (GET_CODE (x) == LABEL_REF + || (GET_CODE (x) == CONST + && GET_CODE (XEXP (x, 0)) == PLUS + && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF + && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))) + return 1; + + /* Post-inc indexing only supported for SImode and larger. */ + else if (GET_CODE (x) == POST_INC && GET_MODE_SIZE (mode) >= 4 + && thumb_index_register_rtx_p (XEXP (x, 0), strict_p)) + return 1; + + else if (GET_CODE (x) == PLUS) + { + /* REG+REG address can be any two index registers. */ + /* We disallow FRAME+REG addressing since we know that FRAME + will be replaced with STACK, and SP relative addressing only + permits SP+OFFSET. */ + if (GET_MODE_SIZE (mode) <= 4 + && XEXP (x, 0) != frame_pointer_rtx + && XEXP (x, 1) != frame_pointer_rtx + && thumb_index_register_rtx_p (XEXP (x, 0), strict_p) + && thumb_index_register_rtx_p (XEXP (x, 1), strict_p)) + return 1; + + /* REG+const has 5-7 bit offset for non-SP registers. */ + else if ((thumb_index_register_rtx_p (XEXP (x, 0), strict_p) + || XEXP (x, 0) == arg_pointer_rtx) + && GET_CODE (XEXP (x, 1)) == CONST_INT + && thumb_legitimate_offset_p (mode, INTVAL (XEXP (x, 1)))) + return 1; + + /* REG+const has 10 bit offset for SP, but only SImode and + larger is supported. */ + /* ??? Should probably check for DI/DFmode overflow here + just like GO_IF_LEGITIMATE_OFFSET does. */ + else if (GET_CODE (XEXP (x, 0)) == REG + && REGNO (XEXP (x, 0)) == STACK_POINTER_REGNUM + && GET_MODE_SIZE (mode) >= 4 + && GET_CODE (XEXP (x, 1)) == CONST_INT + && INTVAL (XEXP (x, 1)) >= 0 + && INTVAL (XEXP (x, 1)) + GET_MODE_SIZE (mode) <= 1024 + && (INTVAL (XEXP (x, 1)) & 3) == 0) + return 1; + + else if (GET_CODE (XEXP (x, 0)) == REG + && REGNO (XEXP (x, 0)) == FRAME_POINTER_REGNUM + && GET_MODE_SIZE (mode) >= 4 + && GET_CODE (XEXP (x, 1)) == CONST_INT + && (INTVAL (XEXP (x, 1)) & 3) == 0) + return 1; + } + + else if (GET_MODE_CLASS (mode) != MODE_FLOAT + && GET_MODE_SIZE (mode) == 4 + && GET_CODE (x) == SYMBOL_REF + && CONSTANT_POOL_ADDRESS_P (x) + && !(flag_pic + && symbol_mentioned_p (get_pool_constant (x)))) + return 1; + + return 0; +} + +/* Return nonzero if VAL can be used as an offset in a Thumb-state address + instruction of mode MODE. */ +int +thumb_legitimate_offset_p (enum machine_mode mode, HOST_WIDE_INT val) +{ + switch (GET_MODE_SIZE (mode)) + { + case 1: + return val >= 0 && val < 32; + + case 2: + return val >= 0 && val < 64 && (val & 1) == 0; + + default: + return (val >= 0 + && (val + GET_MODE_SIZE (mode)) <= 128 + && (val & 3) == 0); + } +} + +/* Try machine-dependent ways of modifying an illegitimate address + to be legitimate. If we find one, return the new, valid address. */ +rtx +arm_legitimize_address (rtx x, rtx orig_x, enum machine_mode mode) +{ + if (GET_CODE (x) == PLUS) + { + rtx xop0 = XEXP (x, 0); + rtx xop1 = XEXP (x, 1); + + if (CONSTANT_P (xop0) && !symbol_mentioned_p (xop0)) + xop0 = force_reg (SImode, xop0); + + if (CONSTANT_P (xop1) && !symbol_mentioned_p (xop1)) + xop1 = force_reg (SImode, xop1); + + if (ARM_BASE_REGISTER_RTX_P (xop0) + && GET_CODE (xop1) == CONST_INT) + { + HOST_WIDE_INT n, low_n; + rtx base_reg, val; + n = INTVAL (xop1); + + if (mode == DImode || (TARGET_SOFT_FLOAT && mode == DFmode)) + { + low_n = n & 0x0f; + n &= ~0x0f; + if (low_n > 4) + { + n += 16; + low_n -= 16; + } + } + else + { + low_n = ((mode) == TImode ? 0 + : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); + n -= low_n; + } + + base_reg = gen_reg_rtx (SImode); + val = force_operand (gen_rtx_PLUS (SImode, xop0, + GEN_INT (n)), NULL_RTX); + emit_move_insn (base_reg, val); + x = (low_n == 0 ? base_reg + : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); + } + else if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1)) + x = gen_rtx_PLUS (SImode, xop0, xop1); + } + + /* XXX We don't allow MINUS any more -- see comment in + arm_legitimate_address_p (). */ + else if (GET_CODE (x) == MINUS) + { + rtx xop0 = XEXP (x, 0); + rtx xop1 = XEXP (x, 1); + + if (CONSTANT_P (xop0)) + xop0 = force_reg (SImode, xop0); + + if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) + xop1 = force_reg (SImode, xop1); + + if (xop0 != XEXP (x, 0) || xop1 != XEXP (x, 1)) + x = gen_rtx_MINUS (SImode, xop0, xop1); + } + + if (flag_pic) + { + /* We need to find and carefully transform any SYMBOL and LABEL + references; so go back to the original address expression. */ + rtx new_x = legitimize_pic_address (orig_x, mode, NULL_RTX); + + if (new_x != orig_x) + x = new_x; + } + + return x; +} + + + #define REG_OR_SUBREG_REG(X) \ (GET_CODE (X) == REG \ || (GET_CODE (X) == SUBREG && GET_CODE (SUBREG_REG (X)) == REG)) @@ -2550,12 +3126,9 @@ arm_finalize_pic (prologue) #ifndef COSTS_N_INSNS #define COSTS_N_INSNS(N) ((N) * 4 - 2) #endif - -int -arm_rtx_costs (x, code, outer) - rtx x; - enum rtx_code code; - enum rtx_code outer; +/* Worker routine for arm_rtx_costs. */ +static inline int +arm_rtx_costs_1 (rtx x, enum rtx_code code, enum rtx_code outer) { enum machine_mode mode = GET_MODE (x); enum rtx_code subcode; @@ -2605,12 +3178,12 @@ arm_rtx_costs (x, code, outer) return COSTS_N_INSNS (2); return COSTS_N_INSNS (3); } - else if (outer == PLUS + else if ((outer == PLUS || outer == COMPARE) && INTVAL (x) < 256 && INTVAL (x) > -256) - return 0; - else if (outer == COMPARE - && (unsigned HOST_WIDE_INT) INTVAL (x) < 256) - return 0; + return 0; + else if (outer == AND + && INTVAL (x) < 256 && INTVAL (x) >= -256) + return COSTS_N_INSNS (1); else if (outer == ASHIFT || outer == ASHIFTRT || outer == LSHIFTRT) return 0; @@ -2634,7 +3207,7 @@ arm_rtx_costs (x, code, outer) case AND: case XOR: case IOR: - /* XXX guess. */ + /* XXX guess. */ return 8; case ADDRESSOF: @@ -2647,7 +3220,7 @@ arm_rtx_costs (x, code, outer) ? 4 : 0)); case IF_THEN_ELSE: - /* XXX a guess. */ + /* XXX a guess. */ if (GET_CODE (XEXP (x, 1)) == PC || GET_CODE (XEXP (x, 2)) == PC) return 14; return 2; @@ -2673,16 +3246,6 @@ arm_rtx_costs (x, code, outer) default: return 99; -#if 0 - case FFS: - case FLOAT: - case FIX: - case UNSIGNED_FIX: - /* XXX guess */ - fprintf (stderr, "unexpected code for thumb in rtx_costs: %s\n", - rtx_name[code]); - abort (); -#endif } } @@ -2697,7 +3260,9 @@ arm_rtx_costs (x, code, outer) case DIV: case MOD: - return 100; + case UDIV: + case UMOD: + return optimize_size ? COSTS_N_INSNS (2) : 100; case ROTATE: if (mode == SImode && GET_CODE (XEXP (x, 1)) == REG) @@ -2735,11 +3300,11 @@ arm_rtx_costs (x, code, outer) if (GET_MODE_CLASS (mode) == MODE_FLOAT) return (2 + ((REG_OR_SUBREG_REG (XEXP (x, 1)) || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE - && const_double_rtx_ok_for_fpu (XEXP (x, 1)))) + && const_double_rtx_ok_for_fpa (XEXP (x, 1)))) ? 0 : 8) + ((REG_OR_SUBREG_REG (XEXP (x, 0)) || (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE - && const_double_rtx_ok_for_fpu (XEXP (x, 0)))) + && const_double_rtx_ok_for_fpa (XEXP (x, 0)))) ? 0 : 8)); if (((GET_CODE (XEXP (x, 0)) == CONST_INT @@ -2764,7 +3329,7 @@ arm_rtx_costs (x, code, outer) return (2 + (REG_OR_SUBREG_REG (XEXP (x, 0)) ? 0 : 8) + ((REG_OR_SUBREG_REG (XEXP (x, 1)) || (GET_CODE (XEXP (x, 1)) == CONST_DOUBLE - && const_double_rtx_ok_for_fpu (XEXP (x, 1)))) + && const_double_rtx_ok_for_fpa (XEXP (x, 1)))) ? 0 : 8)); /* Fall through */ @@ -2830,19 +3395,41 @@ arm_rtx_costs (x, code, outer) { unsigned HOST_WIDE_INT i = (INTVAL (XEXP (x, 1)) & (unsigned HOST_WIDE_INT) 0xffffffff); - int add_cost = const_ok_for_arm (i) ? 4 : 8; - int j; + int cost, const_ok = const_ok_for_arm (i); + int j, booth_unit_size; + + if (arm_tune_xscale) + { + unsigned HOST_WIDE_INT masked_const; + + /* The cost will be related to two insns. + First a load of the constant (MOV or LDR), then a multiply. */ + cost = 2; + if (! const_ok) + cost += 1; /* LDR is probably more expensive because + of longer result latency. */ + masked_const = i & 0xffff8000; + if (masked_const != 0 && masked_const != 0xffff8000) + { + masked_const = i & 0xf8000000; + if (masked_const == 0 || masked_const == 0xf8000000) + cost += 1; + else + cost += 2; + } + return cost; + } /* Tune as appropriate. */ - int booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2); - + cost = const_ok ? 4 : 8; + booth_unit_size = ((tune_flags & FL_FAST_MULT) ? 8 : 2); for (j = 0; i && j < 32; j += booth_unit_size) { i >>= booth_unit_size; - add_cost += 2; + cost += 2; } - return add_cost; + return cost; } return (((tune_flags & FL_FAST_MULT) ? 8 : 30) @@ -2900,6 +3487,13 @@ arm_rtx_costs (x, code, outer) case SImode: return (1 + (GET_CODE (XEXP (x, 0)) == MEM ? 10 : 0)); + case V8QImode: + case V4HImode: + case V2SImode: + case V4QImode: + case V2HImode: + return 1; + default: break; } @@ -2924,10 +3518,10 @@ arm_rtx_costs (x, code, outer) return 6; case CONST_DOUBLE: - if (const_double_rtx_ok_for_fpu (x)) + if (const_double_rtx_ok_for_fpa (x)) return outer == SET ? 2 : -1; else if ((outer == COMPARE || outer == PLUS) - && neg_const_double_rtx_ok_for_fpu (x)) + && neg_const_double_rtx_ok_for_fpa (x)) return -1; return 7; @@ -2936,21 +3530,82 @@ arm_rtx_costs (x, code, outer) } } +static bool +arm_rtx_costs (rtx x, int code, int outer_code, int *total) +{ + *total = arm_rtx_costs_1 (x, code, outer_code); + return true; +} + +/* All address computations that can be done are free, but rtx cost returns + the same for practically all of them. So we weight the different types + of address here in the order (most pref first): + PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ +static inline int +arm_arm_address_cost (rtx x) +{ + enum rtx_code c = GET_CODE (x); + + if (c == PRE_INC || c == PRE_DEC || c == POST_INC || c == POST_DEC) + return 0; + if (c == MEM || c == LABEL_REF || c == SYMBOL_REF) + return 10; + + if (c == PLUS || c == MINUS) + { + char cl0 = GET_RTX_CLASS (GET_CODE (XEXP (x, 0))); + char cl1 = GET_RTX_CLASS (GET_CODE (XEXP (x, 1))); + + if (GET_CODE (XEXP (x, 0)) == CONST_INT) + return 2; + + if (cl0 == '2' || cl0 == 'c' || cl1 == '2' || cl1 == 'c') + return 3; + + return 4; + } + + return 6; +} + +static inline int +arm_thumb_address_cost (rtx x) +{ + enum rtx_code c = GET_CODE (x); + + if (c == REG) + return 1; + if (c == PLUS + && GET_CODE (XEXP (x, 0)) == REG + && GET_CODE (XEXP (x, 1)) == CONST_INT) + return 1; + + return 2; +} + +static int +arm_address_cost (rtx x) +{ + return TARGET_ARM ? arm_arm_address_cost (x) : arm_thumb_address_cost (x); +} + +static int +arm_use_dfa_pipeline_interface (void) +{ + return true; +} + static int -arm_adjust_cost (insn, link, dep, cost) - rtx insn; - rtx link; - rtx dep; - int cost; +arm_adjust_cost (rtx insn, rtx link, rtx dep, int cost) { rtx i_pat, d_pat; /* Some true dependencies can have a higher cost depending on precisely how certain input operands are used. */ - if (arm_is_xscale + if (arm_tune_xscale && REG_NOTE_KIND (link) == 0 - && recog_memoized (insn) < 0 - && recog_memoized (dep) < 0) + && recog_memoized (insn) >= 0 + && recog_memoized (dep) >= 0) { int shift_opnum = get_attr_shift (insn); enum attr_type attr_type = get_attr_type (dep); @@ -3017,8 +3672,6 @@ arm_adjust_cost (insn, link, dep, cost) return cost; } -/* This code has been fixed for cross compilation. */ - static int fpa_consts_inited = 0; static const char * const strings_fpa[8] = @@ -3030,7 +3683,7 @@ static const char * const strings_fpa[8] = static REAL_VALUE_TYPE values_fpa[8]; static void -init_fpa_table () +init_fpa_table (void) { int i; REAL_VALUE_TYPE r; @@ -3044,11 +3697,9 @@ init_fpa_table () fpa_consts_inited = 1; } -/* Return TRUE if rtx X is a valid immediate FPU constant. */ - +/* Return TRUE if rtx X is a valid immediate FPA constant. */ int -const_double_rtx_ok_for_fpu (x) - rtx x; +const_double_rtx_ok_for_fpa (rtx x) { REAL_VALUE_TYPE r; int i; @@ -3067,11 +3718,9 @@ const_double_rtx_ok_for_fpu (x) return 0; } -/* Return TRUE if rtx X is a valid immediate FPU constant. */ - +/* Return TRUE if rtx X is a valid immediate FPA constant. */ int -neg_const_double_rtx_ok_for_fpu (x) - rtx x; +neg_const_double_rtx_ok_for_fpa (rtx x) { REAL_VALUE_TYPE r; int i; @@ -3100,11 +3749,8 @@ neg_const_double_rtx_ok_for_fpu (x) code. SUBREG(MEM) always needs a reload in the places where s_register_operand is used, and this seemed to lead to excessive reloading. */ - int -s_register_operand (op, mode) - rtx op; - enum machine_mode mode; +s_register_operand (rtx op, enum machine_mode mode) { if (GET_MODE (op) != mode && mode != VOIDmode) return 0; @@ -3121,11 +3767,8 @@ s_register_operand (op, mode) } /* A hard register operand (even before reload. */ - int -arm_hard_register_operand (op, mode) - rtx op; - enum machine_mode mode; +arm_hard_register_operand (rtx op, enum machine_mode mode) { if (GET_MODE (op) != mode && mode != VOIDmode) return 0; @@ -3135,11 +3778,8 @@ arm_hard_register_operand (op, mode) } /* Only accept reg, subreg(reg), const_int. */ - int -reg_or_int_operand (op, mode) - rtx op; - enum machine_mode mode; +reg_or_int_operand (rtx op, enum machine_mode mode) { if (GET_CODE (op) == CONST_INT) return 1; @@ -3158,11 +3798,8 @@ reg_or_int_operand (op, mode) } /* Return 1 if OP is an item in memory, given that we are in reload. */ - int -arm_reload_memory_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; +arm_reload_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { int regno = true_regnum (op); @@ -3176,18 +3813,11 @@ arm_reload_memory_operand (op, mode) memory access (architecture V4). MODE is QImode if called when computing constraints, or VOIDmode when emitting patterns. In this latter case we cannot use memory_operand() - because it will fail on badly formed MEMs, which is precisly what we are + because it will fail on badly formed MEMs, which is precisely what we are trying to catch. */ - int -bad_signed_byte_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; +bad_signed_byte_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { -#if 0 - if ((mode == QImode && !memory_operand (op, mode)) || GET_CODE (op) != MEM) - return 0; -#endif if (GET_CODE (op) != MEM) return 0; @@ -3211,11 +3841,8 @@ bad_signed_byte_operand (op, mode) } /* Return TRUE for valid operands for the rhs of an ARM instruction. */ - int -arm_rhs_operand (op, mode) - rtx op; - enum machine_mode mode; +arm_rhs_operand (rtx op, enum machine_mode mode) { return (s_register_operand (op, mode) || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op)))); @@ -3223,11 +3850,8 @@ arm_rhs_operand (op, mode) /* Return TRUE for valid operands for the rhs of an ARM instruction, or a load. */ - int -arm_rhsm_operand (op, mode) - rtx op; - enum machine_mode mode; +arm_rhsm_operand (rtx op, enum machine_mode mode) { return (s_register_operand (op, mode) || (GET_CODE (op) == CONST_INT && const_ok_for_arm (INTVAL (op))) @@ -3236,11 +3860,8 @@ arm_rhsm_operand (op, mode) /* Return TRUE for valid operands for the rhs of an ARM instruction, or if a constant that is valid when negated. */ - int -arm_add_operand (op, mode) - rtx op; - enum machine_mode mode; +arm_add_operand (rtx op, enum machine_mode mode) { if (TARGET_THUMB) return thumb_cmp_operand (op, mode); @@ -3251,10 +3872,17 @@ arm_add_operand (op, mode) || const_ok_for_arm (-INTVAL (op))))); } +/* Return TRUE for valid ARM constants (or when valid if negated). */ +int +arm_addimm_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) +{ + return (GET_CODE (op) == CONST_INT + && (const_ok_for_arm (INTVAL (op)) + || const_ok_for_arm (-INTVAL (op)))); +} + int -arm_not_operand (op, mode) - rtx op; - enum machine_mode mode; +arm_not_operand (rtx op, enum machine_mode mode) { return (s_register_operand (op, mode) || (GET_CODE (op) == CONST_INT @@ -3264,11 +3892,8 @@ arm_not_operand (op, mode) /* Return TRUE if the operand is a memory reference which contains an offsettable address. */ - int -offsettable_memory_operand (op, mode) - rtx op; - enum machine_mode mode; +offsettable_memory_operand (rtx op, enum machine_mode mode) { if (mode == VOIDmode) mode = GET_MODE (op); @@ -3281,11 +3906,8 @@ offsettable_memory_operand (op, mode) /* Return TRUE if the operand is a memory reference which is, or can be made word aligned by adjusting the offset. */ - int -alignable_memory_operand (op, mode) - rtx op; - enum machine_mode mode; +alignable_memory_operand (rtx op, enum machine_mode mode) { rtx reg; @@ -3310,11 +3932,8 @@ alignable_memory_operand (op, mode) /* Similar to s_register_operand, but does not allow hard integer registers. */ - int -f_register_operand (op, mode) - rtx op; - enum machine_mode mode; +f_register_operand (rtx op, enum machine_mode mode) { if (GET_MODE (op) != mode && mode != VOIDmode) return 0; @@ -3326,15 +3945,12 @@ f_register_operand (op, mode) to be a register operand. */ return (GET_CODE (op) == REG && (REGNO (op) >= FIRST_PSEUDO_REGISTER - || REGNO_REG_CLASS (REGNO (op)) == FPU_REGS)); + || REGNO_REG_CLASS (REGNO (op)) == FPA_REGS)); } -/* Return TRUE for valid operands for the rhs of an FPU instruction. */ - +/* Return TRUE for valid operands for the rhs of an FPA instruction. */ int -fpu_rhs_operand (op, mode) - rtx op; - enum machine_mode mode; +fpa_rhs_operand (rtx op, enum machine_mode mode) { if (s_register_operand (op, mode)) return TRUE; @@ -3343,15 +3959,13 @@ fpu_rhs_operand (op, mode) return FALSE; if (GET_CODE (op) == CONST_DOUBLE) - return const_double_rtx_ok_for_fpu (op); + return const_double_rtx_ok_for_fpa (op); return FALSE; } int -fpu_add_operand (op, mode) - rtx op; - enum machine_mode mode; +fpa_add_operand (rtx op, enum machine_mode mode) { if (s_register_operand (op, mode)) return TRUE; @@ -3360,18 +3974,263 @@ fpu_add_operand (op, mode) return FALSE; if (GET_CODE (op) == CONST_DOUBLE) - return (const_double_rtx_ok_for_fpu (op) - || neg_const_double_rtx_ok_for_fpu (op)); + return (const_double_rtx_ok_for_fpa (op) + || neg_const_double_rtx_ok_for_fpa (op)); return FALSE; } -/* Return nonzero if OP is a constant power of two. */ +/* Return nonzero if OP is a valid Cirrus memory address pattern. */ +int +cirrus_memory_offset (rtx op) +{ + /* Reject eliminable registers. */ + if (! (reload_in_progress || reload_completed) + && ( reg_mentioned_p (frame_pointer_rtx, op) + || reg_mentioned_p (arg_pointer_rtx, op) + || reg_mentioned_p (virtual_incoming_args_rtx, op) + || reg_mentioned_p (virtual_outgoing_args_rtx, op) + || reg_mentioned_p (virtual_stack_dynamic_rtx, op) + || reg_mentioned_p (virtual_stack_vars_rtx, op))) + return 0; + + if (GET_CODE (op) == MEM) + { + rtx ind; + + ind = XEXP (op, 0); + + /* Match: (mem (reg)). */ + if (GET_CODE (ind) == REG) + return 1; + + /* Match: + (mem (plus (reg) + (const))). */ + if (GET_CODE (ind) == PLUS + && GET_CODE (XEXP (ind, 0)) == REG + && REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode) + && GET_CODE (XEXP (ind, 1)) == CONST_INT) + return 1; + } + + return 0; +} + +/* Return nonzero if OP is a Cirrus or general register. */ +int +cirrus_register_operand (rtx op, enum machine_mode mode) +{ + if (GET_MODE (op) != mode && mode != VOIDmode) + return FALSE; + + if (GET_CODE (op) == SUBREG) + op = SUBREG_REG (op); + + return (GET_CODE (op) == REG + && (REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS + || REGNO_REG_CLASS (REGNO (op)) == GENERAL_REGS)); +} + +/* Return nonzero if OP is a cirrus FP register. */ +int +cirrus_fp_register (rtx op, enum machine_mode mode) +{ + if (GET_MODE (op) != mode && mode != VOIDmode) + return FALSE; + + if (GET_CODE (op) == SUBREG) + op = SUBREG_REG (op); + + return (GET_CODE (op) == REG + && (REGNO (op) >= FIRST_PSEUDO_REGISTER + || REGNO_REG_CLASS (REGNO (op)) == CIRRUS_REGS)); +} + +/* Return nonzero if OP is a 6bit constant (0..63). */ +int +cirrus_shift_const (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) +{ + return (GET_CODE (op) == CONST_INT + && INTVAL (op) >= 0 + && INTVAL (op) < 64); +} + +/* Returns TRUE if INSN is an "LDR REG, ADDR" instruction. + Use by the Cirrus Maverick code which has to workaround + a hardware bug triggered by such instructions. */ +static bool +arm_memory_load_p (rtx insn) +{ + rtx body, lhs, rhs;; + + if (insn == NULL_RTX || GET_CODE (insn) != INSN) + return false; + + body = PATTERN (insn); + + if (GET_CODE (body) != SET) + return false; + + lhs = XEXP (body, 0); + rhs = XEXP (body, 1); + + lhs = REG_OR_SUBREG_RTX (lhs); + + /* If the destination is not a general purpose + register we do not have to worry. */ + if (GET_CODE (lhs) != REG + || REGNO_REG_CLASS (REGNO (lhs)) != GENERAL_REGS) + return false; + + /* As well as loads from memory we also have to react + to loads of invalid constants which will be turned + into loads from the minipool. */ + return (GET_CODE (rhs) == MEM + || GET_CODE (rhs) == SYMBOL_REF + || note_invalid_constants (insn, -1, false)); +} + +/* Return TRUE if INSN is a Cirrus instruction. */ +static bool +arm_cirrus_insn_p (rtx insn) +{ + enum attr_cirrus attr; + + /* get_attr aborts on USE and CLOBBER. */ + if (!insn + || GET_CODE (insn) != INSN + || GET_CODE (PATTERN (insn)) == USE + || GET_CODE (PATTERN (insn)) == CLOBBER) + return 0; + + attr = get_attr_cirrus (insn); + + return attr != CIRRUS_NOT; +} + +/* Cirrus reorg for invalid instruction combinations. */ +static void +cirrus_reorg (rtx first) +{ + enum attr_cirrus attr; + rtx body = PATTERN (first); + rtx t; + int nops; + + /* Any branch must be followed by 2 non Cirrus instructions. */ + if (GET_CODE (first) == JUMP_INSN && GET_CODE (body) != RETURN) + { + nops = 0; + t = next_nonnote_insn (first); + + if (arm_cirrus_insn_p (t)) + ++ nops; + + if (arm_cirrus_insn_p (next_nonnote_insn (t))) + ++ nops; + + while (nops --) + emit_insn_after (gen_nop (), first); + + return; + } + + /* (float (blah)) is in parallel with a clobber. */ + if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) + body = XVECEXP (body, 0, 0); + + if (GET_CODE (body) == SET) + { + rtx lhs = XEXP (body, 0), rhs = XEXP (body, 1); + + /* cfldrd, cfldr64, cfstrd, cfstr64 must + be followed by a non Cirrus insn. */ + if (get_attr_cirrus (first) == CIRRUS_DOUBLE) + { + if (arm_cirrus_insn_p (next_nonnote_insn (first))) + emit_insn_after (gen_nop (), first); + + return; + } + else if (arm_memory_load_p (first)) + { + unsigned int arm_regno; + + /* Any ldr/cfmvdlr, ldr/cfmvdhr, ldr/cfmvsr, ldr/cfmv64lr, + ldr/cfmv64hr combination where the Rd field is the same + in both instructions must be split with a non Cirrus + insn. Example: + + ldr r0, blah + nop + cfmvsr mvf0, r0. */ + + /* Get Arm register number for ldr insn. */ + if (GET_CODE (lhs) == REG) + arm_regno = REGNO (lhs); + else if (GET_CODE (rhs) == REG) + arm_regno = REGNO (rhs); + else + abort (); + + /* Next insn. */ + first = next_nonnote_insn (first); + + if (! arm_cirrus_insn_p (first)) + return; + + body = PATTERN (first); + + /* (float (blah)) is in parallel with a clobber. */ + if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0)) + body = XVECEXP (body, 0, 0); + if (GET_CODE (body) == FLOAT) + body = XEXP (body, 0); + + if (get_attr_cirrus (first) == CIRRUS_MOVE + && GET_CODE (XEXP (body, 1)) == REG + && arm_regno == REGNO (XEXP (body, 1))) + emit_insn_after (gen_nop (), first); + + return; + } + } + + /* get_attr aborts on USE and CLOBBER. */ + if (!first + || GET_CODE (first) != INSN + || GET_CODE (PATTERN (first)) == USE + || GET_CODE (PATTERN (first)) == CLOBBER) + return; + + attr = get_attr_cirrus (first); + + /* Any coprocessor compare instruction (cfcmps, cfcmpd, ...) + must be followed by a non-coprocessor instruction. */ + if (attr == CIRRUS_COMPARE) + { + nops = 0; + + t = next_nonnote_insn (first); + + if (arm_cirrus_insn_p (t)) + ++ nops; + + if (arm_cirrus_insn_p (next_nonnote_insn (t))) + ++ nops; + + while (nops --) + emit_insn_after (gen_nop (), first); + + return; + } +} + +/* Return nonzero if OP is a constant power of two. */ int -power_of_two_operand (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; +power_of_two_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { if (GET_CODE (op) == CONST_INT) { @@ -3387,11 +4246,8 @@ power_of_two_operand (op, mode) Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address). Note that this disallows MEM(REG+REG), but allows MEM(PRE/POST_INC/DEC(REG)). */ - int -di_operand (op, mode) - rtx op; - enum machine_mode mode; +di_operand (rtx op, enum machine_mode mode) { if (s_register_operand (op, mode)) return TRUE; @@ -3417,11 +4273,8 @@ di_operand (op, mode) } /* Like di_operand, but don't accept constants. */ - int -nonimmediate_di_operand (op, mode) - rtx op; - enum machine_mode mode; +nonimmediate_di_operand (rtx op, enum machine_mode mode) { if (s_register_operand (op, mode)) return TRUE; @@ -3442,11 +4295,8 @@ nonimmediate_di_operand (op, mode) Either: REG, SUBREG, CONST_DOUBLE or MEM(DImode_address). Note that this disallows MEM(REG+REG), but allows MEM(PRE/POST_INC/DEC(REG)). */ - int -soft_df_operand (op, mode) - rtx op; - enum machine_mode mode; +soft_df_operand (rtx op, enum machine_mode mode) { if (s_register_operand (op, mode)) return TRUE; @@ -3474,11 +4324,8 @@ soft_df_operand (op, mode) } /* Like soft_df_operand, but don't accept constants. */ - int -nonimmediate_soft_df_operand (op, mode) - rtx op; - enum machine_mode mode; +nonimmediate_soft_df_operand (rtx op, enum machine_mode mode) { if (s_register_operand (op, mode)) return TRUE; @@ -3495,11 +4342,8 @@ nonimmediate_soft_df_operand (op, mode) } /* Return TRUE for valid index operands. */ - int -index_operand (op, mode) - rtx op; - enum machine_mode mode; +index_operand (rtx op, enum machine_mode mode) { return (s_register_operand (op, mode) || (immediate_operand (op, mode) @@ -3510,11 +4354,8 @@ index_operand (op, mode) /* Return TRUE for valid shifts by a constant. This also accepts any power of two on the (somewhat overly relaxed) assumption that the shift operator in this case was a mult. */ - int -const_shift_operand (op, mode) - rtx op; - enum machine_mode mode; +const_shift_operand (rtx op, enum machine_mode mode) { return (power_of_two_operand (op, mode) || (immediate_operand (op, mode) @@ -3524,11 +4365,8 @@ const_shift_operand (op, mode) /* Return TRUE for arithmetic operators which can be combined with a multiply (shift). */ - int -shiftable_operator (x, mode) - rtx x; - enum machine_mode mode; +shiftable_operator (rtx x, enum machine_mode mode) { enum rtx_code code; @@ -3542,11 +4380,8 @@ shiftable_operator (x, mode) } /* Return TRUE for binary logical operators. */ - int -logical_binary_operator (x, mode) - rtx x; - enum machine_mode mode; +logical_binary_operator (rtx x, enum machine_mode mode) { enum rtx_code code; @@ -3559,11 +4394,8 @@ logical_binary_operator (x, mode) } /* Return TRUE for shift operators. */ - int -shift_operator (x, mode) - rtx x; - enum machine_mode mode; +shift_operator (rtx x,enum machine_mode mode) { enum rtx_code code; @@ -3580,21 +4412,15 @@ shift_operator (x, mode) } /* Return TRUE if x is EQ or NE. */ - int -equality_operator (x, mode) - rtx x; - enum machine_mode mode ATTRIBUTE_UNUSED; +equality_operator (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED) { return GET_CODE (x) == EQ || GET_CODE (x) == NE; } /* Return TRUE if x is a comparison operator other than LTGT or UNEQ. */ - int -arm_comparison_operator (x, mode) - rtx x; - enum machine_mode mode; +arm_comparison_operator (rtx x, enum machine_mode mode) { return (comparison_operator (x, mode) && GET_CODE (x) != LTGT @@ -3602,11 +4428,8 @@ arm_comparison_operator (x, mode) } /* Return TRUE for SMIN SMAX UMIN UMAX operators. */ - int -minmax_operator (x, mode) - rtx x; - enum machine_mode mode; +minmax_operator (rtx x, enum machine_mode mode) { enum rtx_code code = GET_CODE (x); @@ -3618,11 +4441,8 @@ minmax_operator (x, mode) /* Return TRUE if this is the condition code register, if we aren't given a mode, accept any class CCmode register. */ - int -cc_register (x, mode) - rtx x; - enum machine_mode mode; +cc_register (rtx x, enum machine_mode mode) { if (mode == VOIDmode) { @@ -3643,11 +4463,8 @@ cc_register (x, mode) /* Return TRUE if this is the condition code register, if we aren't given a mode, accept any class CCmode register which indicates a dominance expression. */ - int -dominant_cc_register (x, mode) - rtx x; - enum machine_mode mode; +dominant_cc_register (rtx x, enum machine_mode mode) { if (mode == VOIDmode) { @@ -3657,7 +4474,7 @@ dominant_cc_register (x, mode) return FALSE; } - if ( mode != CC_DNEmode && mode != CC_DEQmode + if (mode != CC_DNEmode && mode != CC_DEQmode && mode != CC_DLEmode && mode != CC_DLTmode && mode != CC_DGEmode && mode != CC_DGTmode && mode != CC_DLEUmode && mode != CC_DLTUmode @@ -3668,10 +4485,8 @@ dominant_cc_register (x, mode) } /* Return TRUE if X references a SYMBOL_REF. */ - int -symbol_mentioned_p (x) - rtx x; +symbol_mentioned_p (rtx x) { const char * fmt; int i; @@ -3699,10 +4514,8 @@ symbol_mentioned_p (x) } /* Return TRUE if X references a LABEL_REF. */ - int -label_mentioned_p (x) - rtx x; +label_mentioned_p (rtx x) { const char * fmt; int i; @@ -3729,8 +4542,7 @@ label_mentioned_p (x) } enum rtx_code -minmax_code (x) - rtx x; +minmax_code (rtx x) { enum rtx_code code = GET_CODE (x); @@ -3747,10 +4559,8 @@ minmax_code (x) } /* Return 1 if memory locations are adjacent. */ - int -adjacent_mem_locations (a, b) - rtx a, b; +adjacent_mem_locations (rtx a, rtx b) { if ((GET_CODE (XEXP (a, 0)) == REG || (GET_CODE (XEXP (a, 0)) == PLUS @@ -3778,6 +4588,12 @@ adjacent_mem_locations (a, b) else reg1 = REGNO (XEXP (b, 0)); + /* Don't accept any offset that will require multiple + instructions to handle, since this would cause the + arith_adjacentmem pattern to output an overlong sequence. */ + if (!const_ok_for_op (PLUS, val0) || !const_ok_for_op (PLUS, val1)) + return 0; + return (reg0 == reg1) && ((val1 - val0) == 4 || (val0 - val1) == 4); } return 0; @@ -3785,11 +4601,8 @@ adjacent_mem_locations (a, b) /* Return 1 if OP is a load multiple operation. It is known to be parallel and the first section will be tested. */ - int -load_multiple_operation (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; +load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { HOST_WIDE_INT count = XVECLEN (op, 0); int dest_regno; @@ -3810,7 +4623,6 @@ load_multiple_operation (op, mode) /* Now check it more carefully. */ if (GET_CODE (SET_DEST (elt)) != REG || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG - || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt)) || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4) return 0; @@ -3848,11 +4660,8 @@ load_multiple_operation (op, mode) /* Return 1 if OP is a store multiple operation. It is known to be parallel and the first section will be tested. */ - int -store_multiple_operation (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; +store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { HOST_WIDE_INT count = XVECLEN (op, 0); int src_regno; @@ -3873,7 +4682,6 @@ store_multiple_operation (op, mode) /* Now check it more carefully. */ if (GET_CODE (SET_DEST (elt)) != REG || GET_CODE (XEXP (SET_SRC (elt), 0)) != REG - || REGNO (XEXP (SET_SRC (elt), 0)) != REGNO (SET_DEST (elt)) || GET_CODE (XEXP (SET_SRC (elt), 1)) != CONST_INT || INTVAL (XEXP (SET_SRC (elt), 1)) != (count - 1) * 4) return 0; @@ -3910,12 +4718,8 @@ store_multiple_operation (op, mode) } int -load_multiple_sequence (operands, nops, regs, base, load_offset) - rtx * operands; - int nops; - int * regs; - int * base; - HOST_WIDE_INT * load_offset; +load_multiple_sequence (rtx *operands, int nops, int *regs, int *base, + HOST_WIDE_INT *load_offset) { int unsorted_regs[4]; HOST_WIDE_INT unsorted_offsets[4]; @@ -4085,9 +4889,7 @@ load_multiple_sequence (operands, nops, regs, base, load_offset) } const char * -emit_ldm_seq (operands, nops) - rtx * operands; - int nops; +emit_ldm_seq (rtx *operands, int nops) { int regs[4]; int base_reg; @@ -4145,12 +4947,8 @@ emit_ldm_seq (operands, nops) } int -store_multiple_sequence (operands, nops, regs, base, load_offset) - rtx * operands; - int nops; - int * regs; - int * base; - HOST_WIDE_INT * load_offset; +store_multiple_sequence (rtx *operands, int nops, int *regs, int *base, + HOST_WIDE_INT * load_offset) { int unsorted_regs[4]; HOST_WIDE_INT unsorted_offsets[4]; @@ -4282,9 +5080,7 @@ store_multiple_sequence (operands, nops, regs, base, load_offset) } const char * -emit_stm_seq (operands, nops) - rtx * operands; - int nops; +emit_stm_seq (rtx *operands, int nops) { int regs[4]; int base_reg; @@ -4328,9 +5124,7 @@ emit_stm_seq (operands, nops) } int -multi_register_push (op, mode) - rtx op; - enum machine_mode mode ATTRIBUTE_UNUSED; +multi_register_push (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { if (GET_CODE (op) != PARALLEL || (GET_CODE (XVECEXP (op, 0, 0)) != SET) @@ -4344,16 +5138,9 @@ multi_register_push (op, mode) /* Routines for use in generating RTL. */ rtx -arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p, - in_struct_p, scalar_p) - int base_regno; - int count; - rtx from; - int up; - int write_back; - int unchanging_p; - int in_struct_p; - int scalar_p; +arm_gen_load_multiple (int base_regno, int count, rtx from, int up, + int write_back, int unchanging_p, int in_struct_p, + int scalar_p) { int i = 0, j; rtx result; @@ -4388,7 +5175,7 @@ arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p, As a compromise, we use ldr for counts of 1 or 2 regs, and ldm for counts of 3 or 4 regs. */ - if (arm_is_xscale && count <= 2 && ! optimize_size) + if (arm_tune_xscale && count <= 2 && ! optimize_size) { rtx seq; @@ -4437,16 +5224,9 @@ arm_gen_load_multiple (base_regno, count, from, up, write_back, unchanging_p, } rtx -arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p, - in_struct_p, scalar_p) - int base_regno; - int count; - rtx to; - int up; - int write_back; - int unchanging_p; - int in_struct_p; - int scalar_p; +arm_gen_store_multiple (int base_regno, int count, rtx to, int up, + int write_back, int unchanging_p, int in_struct_p, + int scalar_p) { int i = 0, j; rtx result; @@ -4455,7 +5235,7 @@ arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p, /* See arm_gen_load_multiple for discussion of the pros/cons of ldm/stm usage for XScale. */ - if (arm_is_xscale && count <= 2 && ! optimize_size) + if (arm_tune_xscale && count <= 2 && ! optimize_size) { rtx seq; @@ -4505,8 +5285,7 @@ arm_gen_store_multiple (base_regno, count, to, up, write_back, unchanging_p, } int -arm_gen_movstrqi (operands) - rtx * operands; +arm_gen_movstrqi (rtx *operands) { HOST_WIDE_INT in_words_to_go, out_words_to_go, last_bytes; int i; @@ -4689,8 +5468,7 @@ arm_gen_movstrqi (operands) known to be alignable and of the form reg, or plus (reg, const). */ rtx -arm_gen_rotated_half_load (memref) - rtx memref; +arm_gen_rotated_half_load (rtx memref) { HOST_WIDE_INT offset = 0; rtx base = XEXP (memref, 0); @@ -4714,19 +5492,17 @@ arm_gen_rotated_half_load (memref) return gen_rtx_ROTATE (SImode, base, GEN_INT (16)); } -/* Select a dominance comparison mode if possible. We support three forms. - COND_OR == 0 => (X && Y) - COND_OR == 1 => ((! X( || Y) - COND_OR == 2 => (X || Y) - If we are unable to support a dominance comparsison we return CC mode. - This will then fail to match for the RTL expressions that generate this - call. */ - -static enum machine_mode -select_dominance_cc_mode (x, y, cond_or) - rtx x; - rtx y; - HOST_WIDE_INT cond_or; +/* Select a dominance comparison mode if possible for a test of the general + form (OP (COND_OR (X) (Y)) (const_int 0)). We support three forms. + COND_OR == DOM_CC_X_AND_Y => (X && Y) + COND_OR == DOM_CC_NX_OR_Y => ((! X) || Y) + COND_OR == DOM_CC_X_OR_Y => (X || Y) + In all cases OP will be either EQ or NE, but we don't need to know which + here. If we are unable to support a dominance comparison we return + CC mode. This will then fail to match for the RTL expressions that + generate this call. */ +enum machine_mode +arm_select_dominance_cc_mode (rtx x, rtx y, HOST_WIDE_INT cond_or) { enum rtx_code cond1, cond2; int swapped = 0; @@ -4743,7 +5519,7 @@ select_dominance_cc_mode (x, y, cond_or) /* The if_then_else variant of this tests the second condition if the first passes, but is true if the first fails. Reverse the first condition to get a true "inclusive-or" expression. */ - if (cond_or == 1) + if (cond_or == DOM_CC_NX_OR_Y) cond1 = reverse_condition (cond1); /* If the comparisons are not equal, and one doesn't dominate the other, @@ -4763,7 +5539,7 @@ select_dominance_cc_mode (x, y, cond_or) switch (cond1) { case EQ: - if (cond2 == EQ || !cond_or) + if (cond2 == EQ || cond_or == DOM_CC_X_AND_Y) return CC_DEQmode; switch (cond2) @@ -4778,7 +5554,7 @@ select_dominance_cc_mode (x, y, cond_or) break; case LT: - if (cond2 == LT || !cond_or) + if (cond2 == LT || cond_or == DOM_CC_X_AND_Y) return CC_DLTmode; if (cond2 == LE) return CC_DLEmode; @@ -4787,7 +5563,7 @@ select_dominance_cc_mode (x, y, cond_or) break; case GT: - if (cond2 == GT || !cond_or) + if (cond2 == GT || cond_or == DOM_CC_X_AND_Y) return CC_DGTmode; if (cond2 == GE) return CC_DGEmode; @@ -4796,7 +5572,7 @@ select_dominance_cc_mode (x, y, cond_or) break; case LTU: - if (cond2 == LTU || !cond_or) + if (cond2 == LTU || cond_or == DOM_CC_X_AND_Y) return CC_DLTUmode; if (cond2 == LEU) return CC_DLEUmode; @@ -4805,7 +5581,7 @@ select_dominance_cc_mode (x, y, cond_or) break; case GTU: - if (cond2 == GTU || !cond_or) + if (cond2 == GTU || cond_or == DOM_CC_X_AND_Y) return CC_DGTUmode; if (cond2 == GEU) return CC_DGEUmode; @@ -4838,10 +5614,7 @@ select_dominance_cc_mode (x, y, cond_or) } enum machine_mode -arm_select_cc_mode (op, x, y) - enum rtx_code op; - rtx x; - rtx y; +arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) { /* All floating point compares return CCFP if it is an equality comparison, and CCFPE otherwise. */ @@ -4865,6 +5638,8 @@ arm_select_cc_mode (op, x, y) case LE: case GT: case GE: + if (TARGET_CIRRUS) + return CCFPmode; return CCFPEmode; default: @@ -4904,24 +5679,35 @@ arm_select_cc_mode (op, x, y) || XEXP (x, 2) == const1_rtx) && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<') - return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), - INTVAL (XEXP (x, 2))); + return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), + INTVAL (XEXP (x, 2))); /* Alternate canonicalizations of the above. These are somewhat cleaner. */ if (GET_CODE (x) == AND && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<') - return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 0); + return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), + DOM_CC_X_AND_Y); if (GET_CODE (x) == IOR && GET_RTX_CLASS (GET_CODE (XEXP (x, 0))) == '<' && GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == '<') - return select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), 2); + return arm_select_dominance_cc_mode (XEXP (x, 0), XEXP (x, 1), + DOM_CC_X_OR_Y); + + /* An operation (on Thumb) where we want to test for a single bit. + This is done by shifting that bit up into the top bit of a + scratch register; we can then branch on the sign bit. */ + if (TARGET_THUMB + && GET_MODE (x) == SImode + && (op == EQ || op == NE) + && (GET_CODE (x) == ZERO_EXTRACT)) + return CC_Nmode; /* An operation that sets the condition codes as a side-effect, the V flag is not set correctly, so we can only use comparisons where this doesn't matter. (For LT and GE we can use "mi" and "pl" - instead. */ + instead.) */ if (GET_MODE (x) == SImode && y == const0_rtx && (op == EQ || op == NE || op == LT || op == GE) @@ -4931,7 +5717,8 @@ arm_select_cc_mode (op, x, y) || GET_CODE (x) == NOT || GET_CODE (x) == NEG || GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT - || GET_CODE (x) == ROTATERT || GET_CODE (x) == ZERO_EXTRACT)) + || GET_CODE (x) == ROTATERT + || (TARGET_ARM && GET_CODE (x) == ZERO_EXTRACT))) return CC_NOOVmode; if (GET_MODE (x) == QImode && (op == EQ || op == NE)) @@ -4948,11 +5735,8 @@ arm_select_cc_mode (op, x, y) /* X and Y are two things to compare using CODE. Emit the compare insn and return the rtx for register 0 in the proper mode. FP means this is a floating point compare: I don't think that it is needed on the arm. */ - rtx -arm_gen_compare_reg (code, x, y) - enum rtx_code code; - rtx x, y; +arm_gen_compare_reg (enum rtx_code code, rtx x, rtx y) { enum machine_mode mode = SELECT_CC_MODE (code, x, y); rtx cc_reg = gen_rtx_REG (mode, CC_REGNUM); @@ -4966,9 +5750,8 @@ arm_gen_compare_reg (code, x, y) /* Generate a sequence of insns that will generate the correct return address mask depending on the physical architecture that the program is running on. */ - rtx -arm_gen_return_addr_mask () +arm_gen_return_addr_mask (void) { rtx reg = gen_reg_rtx (Pmode); @@ -4977,8 +5760,7 @@ arm_gen_return_addr_mask () } void -arm_reload_in_hi (operands) - rtx * operands; +arm_reload_in_hi (rtx *operands) { rtx ref = operands[1]; rtx base, scratch; @@ -5089,16 +5871,14 @@ arm_reload_in_hi (operands) 0)))); } -/* Handle storing a half-word to memory during reload by synthesising as two +/* Handle storing a half-word to memory during reload by synthesizing as two byte stores. Take care not to clobber the input values until after we have moved them somewhere safe. This code assumes that if the DImode scratch in operands[2] overlaps either the input value or output address in some way, then that value must die in this insn (we absolutely need two scratch registers for some corner cases). */ - void -arm_reload_out_hi (operands) - rtx * operands; +arm_reload_out_hi (rtx *operands) { rtx ref = operands[0]; rtx outval = operands[1]; @@ -5256,11 +6036,8 @@ arm_reload_out_hi (operands) } /* Print a symbolic form of X to the debug file, F. */ - static void -arm_print_value (f, x) - FILE * f; - rtx x; +arm_print_value (FILE *f, rtx x) { switch (GET_CODE (x)) { @@ -5272,6 +6049,21 @@ arm_print_value (f, x) fprintf (f, "<0x%lx,0x%lx>", (long)XWINT (x, 2), (long)XWINT (x, 3)); return; + case CONST_VECTOR: + { + int i; + + fprintf (f, "<"); + for (i = 0; i < CONST_VECTOR_NUNITS (x); i++) + { + fprintf (f, HOST_WIDE_INT_PRINT_HEX, INTVAL (CONST_VECTOR_ELT (x, i))); + if (i < (CONST_VECTOR_NUNITS (x) - 1)) + fputc (',', f); + } + fprintf (f, ">"); + } + return; + case CONST_STRING: fprintf (f, "\"%s\"", XSTR (x, 0)); return; @@ -5392,6 +6184,8 @@ struct minipool_node rtx value; /* The mode of value. */ enum machine_mode mode; + /* The size of the value. With iWMMXt enabled + sizes > 4 also imply an alignment of 8-bytes. */ int fix_size; }; @@ -5425,10 +6219,8 @@ Mfix * minipool_barrier; /* Determines if INSN is the start of a jump table. Returns the end of the TABLE or NULL_RTX. */ - static rtx -is_jump_table (insn) - rtx insn; +is_jump_table (rtx insn) { rtx table; @@ -5450,8 +6242,7 @@ is_jump_table (insn) #endif static HOST_WIDE_INT -get_jump_table_size (insn) - rtx insn; +get_jump_table_size (rtx insn) { /* ADDR_VECs only take room if read-only data does into the text section. */ @@ -5472,13 +6263,10 @@ get_jump_table_size (insn) /* Move a minipool fix MP from its current location to before MAX_MP. If MAX_MP is NULL, then MP doesn't need moving, but the addressing - contrains may need updating. */ - + constraints may need updating. */ static Mnode * -move_minipool_fix_forward_ref (mp, max_mp, max_address) - Mnode * mp; - Mnode * max_mp; - HOST_WIDE_INT max_address; +move_minipool_fix_forward_ref (Mnode *mp, Mnode *max_mp, + HOST_WIDE_INT max_address) { /* This should never be true and the code below assumes these are different. */ @@ -5533,10 +6321,8 @@ move_minipool_fix_forward_ref (mp, max_mp, max_address) /* Add a constant to the minipool for a forward reference. Returns the node added or NULL if the constant will not fit in this pool. */ - static Mnode * -add_minipool_forward_ref (fix) - Mfix * fix; +add_minipool_forward_ref (Mfix *fix) { /* If set, max_mp is the first pool_entry that has a lower constraint than the one we are trying to add. */ @@ -5575,13 +6361,26 @@ add_minipool_forward_ref (fix) if (max_mp == NULL && mp->max_address > max_address) max_mp = mp; + + /* If we are inserting an 8-bytes aligned quantity and + we have not already found an insertion point, then + make sure that all such 8-byte aligned quantities are + placed at the start of the pool. */ + if (TARGET_REALLY_IWMMXT + && max_mp == NULL + && fix->fix_size == 8 + && mp->fix_size != 8) + { + max_mp = mp; + max_address = mp->max_address; + } } /* The value is not currently in the minipool, so we need to create a new entry for it. If MAX_MP is NULL, the entry will be put on the end of the list since the placement is less constrained than any existing entry. Otherwise, we insert the new fix before - MAX_MP and, if neceesary, adjust the constraints on the other + MAX_MP and, if necessary, adjust the constraints on the other entries. */ mp = xmalloc (sizeof (* mp)); mp->fix_size = fix->fix_size; @@ -5639,10 +6438,8 @@ add_minipool_forward_ref (fix) } static Mnode * -move_minipool_fix_backward_ref (mp, min_mp, min_address) - Mnode * mp; - Mnode * min_mp; - HOST_WIDE_INT min_address; +move_minipool_fix_backward_ref (Mnode *mp, Mnode *min_mp, + HOST_WIDE_INT min_address) { HOST_WIDE_INT offset; @@ -5702,17 +6499,15 @@ move_minipool_fix_backward_ref (mp, min_mp, min_address) somewhat confusing because the calculated offsets for each fix do not take into account the size of the pool (which is still under construction. */ - static Mnode * -add_minipool_backward_ref (fix) - Mfix * fix; +add_minipool_backward_ref (Mfix *fix) { /* If set, min_mp is the last pool_entry that has a lower constraint than the one we are trying to add. */ - Mnode * min_mp = NULL; + Mnode *min_mp = NULL; /* This can be negative, since it is only a constraint. */ HOST_WIDE_INT min_address = fix->address - fix->backwards; - Mnode * mp; + Mnode *mp; /* If we can't reach the current pool from this insn, or if we can't insert this entry at the end of the pool without pushing other @@ -5752,7 +6547,14 @@ add_minipool_backward_ref (fix) { /* Note the insertion point if necessary. */ if (mp->min_address < min_address) - min_mp = mp; + { + /* For now, we do not allow the insertion of 8-byte alignment + requiring nodes anywhere but at the start of the pool. */ + if (TARGET_REALLY_IWMMXT && fix->fix_size == 8 && mp->fix_size != 8) + return NULL; + else + min_mp = mp; + } else if (mp->max_address < minipool_barrier->address + mp->offset + fix->fix_size) { @@ -5763,6 +6565,18 @@ add_minipool_backward_ref (fix) min_mp = mp; min_address = mp->min_address + fix->fix_size; } + /* If we are inserting an 8-bytes aligned quantity and + we have not already found an insertion point, then + make sure that all such 8-byte aligned quantities are + placed at the start of the pool. */ + else if (TARGET_REALLY_IWMMXT + && min_mp == NULL + && fix->fix_size == 8 + && mp->fix_size < 8) + { + min_mp = mp; + min_address = mp->min_address + fix->fix_size; + } } } @@ -5829,11 +6643,10 @@ add_minipool_backward_ref (fix) } static void -assign_minipool_offsets (barrier) - Mfix * barrier; +assign_minipool_offsets (Mfix *barrier) { HOST_WIDE_INT offset = 0; - Mnode * mp; + Mnode *mp; minipool_barrier = barrier; @@ -5848,19 +6661,27 @@ assign_minipool_offsets (barrier) /* Output the literal table */ static void -dump_minipool (scan) - rtx scan; +dump_minipool (rtx scan) { Mnode * mp; Mnode * nmp; + int align64 = 0; + + if (TARGET_REALLY_IWMMXT) + for (mp = minipool_vector_head; mp != NULL; mp = mp->next) + if (mp->refcount > 0 && mp->fix_size == 8) + { + align64 = 1; + break; + } if (rtl_dump_file) fprintf (rtl_dump_file, - ";; Emitting minipool after insn %u; address %ld\n", - INSN_UID (scan), (unsigned long) minipool_barrier->address); + ";; Emitting minipool after insn %u; address %ld; align %d (bytes)\n", + INSN_UID (scan), (unsigned long) minipool_barrier->address, align64 ? 8 : 4); scan = emit_label_after (gen_label_rtx (), scan); - scan = emit_insn_after (gen_align_4 (), scan); + scan = emit_insn_after (align64 ? gen_align_8 () : gen_align_4 (), scan); scan = emit_label_after (minipool_vector_label, scan); for (mp = minipool_vector_head; mp != NULL; mp = nmp) @@ -5919,10 +6740,8 @@ dump_minipool (scan) } /* Return the cost of forcibly inserting a barrier after INSN. */ - static int -arm_barrier_cost (insn) - rtx insn; +arm_barrier_cost (rtx insn) { /* Basing the location of the pool on the loop depth is preferable, but at the moment, the basic block information seems to be @@ -5956,11 +6775,8 @@ arm_barrier_cost (insn) (FIX->address,MAX_ADDRESS) to forcibly insert a minipool barrier. Create the barrier by inserting a jump and add a new fix entry for it. */ - static Mfix * -create_fix_barrier (fix, max_address) - Mfix * fix; - HOST_WIDE_INT max_address; +create_fix_barrier (Mfix *fix, HOST_WIDE_INT max_address) { HOST_WIDE_INT count = 0; rtx barrier; @@ -6042,9 +6858,7 @@ create_fix_barrier (fix, max_address) /* Record that there is a natural barrier in the insn stream at ADDRESS. */ static void -push_minipool_barrier (insn, address) - rtx insn; - HOST_WIDE_INT address; +push_minipool_barrier (rtx insn, HOST_WIDE_INT address) { Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); @@ -6066,17 +6880,13 @@ push_minipool_barrier (insn, address) fixing; VALUE is the constant that must be loaded, which is of type MODE. */ static void -push_minipool_fix (insn, address, loc, mode, value) - rtx insn; - HOST_WIDE_INT address; - rtx * loc; - enum machine_mode mode; - rtx value; +push_minipool_fix (rtx insn, HOST_WIDE_INT address, rtx *loc, + enum machine_mode mode, rtx value) { Mfix * fix = (Mfix *) obstack_alloc (&minipool_obstack, sizeof (* fix)); #ifdef AOF_ASSEMBLER - /* PIC symbol refereneces need to be converted into offsets into the + /* PIC symbol references need to be converted into offsets into the based area. */ /* XXX This shouldn't be done here. */ if (flag_pic && GET_CODE (value) == SYMBOL_REF) @@ -6099,6 +6909,13 @@ push_minipool_fix (insn, address, loc, mode, value) if (fix->forwards == 0 && fix->backwards == 0) abort (); + /* With iWMMXt enabled, the pool is aligned to an 8-byte boundary. + So there might be an empty word before the start of the pool. + Hence we reduce the forward range by 4 to allow for this + possibility. */ + if (TARGET_REALLY_IWMMXT && fix->fix_size == 8) + fix->forwards -= 4; + if (rtl_dump_file) { fprintf (rtl_dump_file, @@ -6121,13 +6938,15 @@ push_minipool_fix (insn, address, loc, mode, value) minipool_fix_tail = fix; } -/* Scan INSN and note any of its operands that need fixing. */ - -static void -note_invalid_constants (insn, address) - rtx insn; - HOST_WIDE_INT address; +/* Scan INSN and note any of its operands that need fixing. + If DO_PUSHES is false we do not actually push any of the fixups + needed. The function returns TRUE is any fixups were needed/pushed. + This is used by arm_memory_load_p() which needs to know about loads + of constants that will be converted into minipool loads. */ +static bool +note_invalid_constants (rtx insn, HOST_WIDE_INT address, int do_pushes) { + bool result = false; int opno; extract_insn (insn); @@ -6135,8 +6954,10 @@ note_invalid_constants (insn, address) if (!constrain_operands (1)) fatal_insn_not_found (insn); - /* Fill in recog_op_alt with information about the constraints of this - insn. */ + if (recog_data.n_alternatives == 0) + return false; + + /* Fill in recog_op_alt with information about the constraints of this insn. */ preprocess_constraints (); for (opno = 0; opno < recog_data.n_operands; opno++) @@ -6154,32 +6975,47 @@ note_invalid_constants (insn, address) rtx op = recog_data.operand[opno]; if (CONSTANT_P (op)) - push_minipool_fix (insn, address, recog_data.operand_loc[opno], - recog_data.operand_mode[opno], op); -#if 0 - /* RWE: Now we look correctly at the operands for the insn, - this shouldn't be needed any more. */ -#ifndef AOF_ASSEMBLER - /* XXX Is this still needed? */ - else if (GET_CODE (op) == UNSPEC && XINT (op, 1) == UNSPEC_PIC_SYM) - push_minipool_fix (insn, address, recog_data.operand_loc[opno], - recog_data.operand_mode[opno], - XVECEXP (op, 0, 0)); -#endif -#endif + { + if (do_pushes) + push_minipool_fix (insn, address, recog_data.operand_loc[opno], + recog_data.operand_mode[opno], op); + result = true; + } else if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (XEXP (op, 0))) - push_minipool_fix (insn, address, recog_data.operand_loc[opno], - recog_data.operand_mode[opno], - get_pool_constant (XEXP (op, 0))); + { + if (do_pushes) + { + rtx cop = avoid_constant_pool_reference (op); + + /* Casting the address of something to a mode narrower + than a word can cause avoid_constant_pool_reference() + to return the pool reference itself. That's no good to + us here. Lets just hope that we can use the + constant pool value directly. */ + if (op == cop) + cop = get_pool_constant (XEXP (op, 0)); + + push_minipool_fix (insn, address, + recog_data.operand_loc[opno], + recog_data.operand_mode[opno], cop); + } + + result = true; + } } } + + return result; } -void -arm_reorg (first) - rtx first; +/* Gcc puts the pool in the wrong place for ARM, since we can only + load addresses a limited distance around the pc. We do some + special munging to move the constant pool values to the correct + point in the code. */ +static void +arm_reorg (void) { rtx insn; HOST_WIDE_INT address = 0; @@ -6189,20 +7025,26 @@ arm_reorg (first) /* The first insn must always be a note, or the code below won't scan it properly. */ - if (GET_CODE (first) != NOTE) + insn = get_insns (); + if (GET_CODE (insn) != NOTE) abort (); /* Scan all the insns and record the operands that will need fixing. */ - for (insn = next_nonnote_insn (first); insn; insn = next_nonnote_insn (insn)) + for (insn = next_nonnote_insn (insn); insn; insn = next_nonnote_insn (insn)) { + if (TARGET_CIRRUS_FIX_INVALID_INSNS + && (arm_cirrus_insn_p (insn) + || GET_CODE (insn) == JUMP_INSN + || arm_memory_load_p (insn))) + cirrus_reorg (insn); + if (GET_CODE (insn) == BARRIER) push_minipool_barrier (insn, address); - else if (GET_CODE (insn) == INSN || GET_CODE (insn) == CALL_INSN - || GET_CODE (insn) == JUMP_INSN) + else if (INSN_P (insn)) { rtx table; - note_invalid_constants (insn, address); + note_invalid_constants (insn, address, true); address += get_attr_length (insn); /* If the insn is a vector jump, add the size of the table @@ -6336,10 +7178,8 @@ arm_reorg (first) /* If the rtx is the correct value then return the string of the number. In this way we can ensure that valid double constants are generated even when cross compiling. */ - const char * -fp_immediate_constant (x) - rtx x; +fp_immediate_constant (rtx x) { REAL_VALUE_TYPE r; int i; @@ -6356,10 +7196,8 @@ fp_immediate_constant (x) } /* As for fp_immediate_constant, but value is passed directly, not in rtx. */ - static const char * -fp_const_from_val (r) - REAL_VALUE_TYPE * r; +fp_const_from_val (REAL_VALUE_TYPE *r) { int i; @@ -6377,13 +7215,8 @@ fp_const_from_val (r) MASK is the ARM register set mask of which only bits 0-15 are important. REG is the base register, either the frame pointer or the stack pointer, INSTR is the possibly suffixed load or store instruction. */ - static void -print_multi_reg (stream, instr, reg, mask) - FILE * stream; - const char * instr; - int reg; - int mask; +print_multi_reg (FILE *stream, const char *instr, int reg, int mask) { int i; int not_first = FALSE; @@ -6402,14 +7235,25 @@ print_multi_reg (stream, instr, reg, mask) not_first = TRUE; } - fprintf (stream, "}%s\n", TARGET_APCS_32 ? "" : "^"); + fprintf (stream, "}"); + + /* Add a ^ character for the 26-bit ABI, but only if we were loading + the PC. Otherwise we would generate an UNPREDICTABLE instruction. + Strictly speaking the instruction would be unpredicatble only if + we were writing back the base register as well, but since we never + want to generate an LDM type 2 instruction (register bank switching) + which is what you get if the PC is not being loaded, we do not need + to check for writeback. */ + if (! TARGET_APCS_32 + && ((mask & (1 << PC_REGNUM)) != 0)) + fprintf (stream, "^"); + + fprintf (stream, "\n"); } /* Output a 'call' insn. */ - const char * -output_call (operands) - rtx * operands; +output_call (rtx *operands) { /* Handle calls to lr using ip (which may be clobbered in subr anyway). */ @@ -6430,10 +7274,8 @@ output_call (operands) } /* Output a 'call' insn that is a reference in memory. */ - const char * -output_call_mem (operands) - rtx * operands; +output_call_mem (rtx *operands) { if (TARGET_INTERWORK) { @@ -6460,13 +7302,11 @@ output_call_mem (operands) } -/* Output a move from arm registers to an fpu registers. - OPERANDS[0] is an fpu register. +/* Output a move from arm registers to an fpa registers. + OPERANDS[0] is an fpa register. OPERANDS[1] is the first registers of an arm register pair. */ - const char * -output_mov_long_double_fpu_from_arm (operands) - rtx * operands; +output_mov_long_double_fpa_from_arm (rtx *operands) { int arm_reg0 = REGNO (operands[1]); rtx ops[3]; @@ -6484,13 +7324,11 @@ output_mov_long_double_fpu_from_arm (operands) return ""; } -/* Output a move from an fpu register to arm registers. +/* Output a move from an fpa register to arm registers. OPERANDS[0] is the first registers of an arm register pair. - OPERANDS[1] is an fpu register. */ - + OPERANDS[1] is an fpa register. */ const char * -output_mov_long_double_arm_from_fpu (operands) - rtx * operands; +output_mov_long_double_arm_from_fpa (rtx *operands) { int arm_reg0 = REGNO (operands[0]); rtx ops[3]; @@ -6510,10 +7348,8 @@ output_mov_long_double_arm_from_fpu (operands) /* Output a move from arm registers to arm registers of a long double OPERANDS[0] is the destination. OPERANDS[1] is the source. */ - const char * -output_mov_long_double_arm_from_arm (operands) - rtx * operands; +output_mov_long_double_arm_from_arm (rtx *operands) { /* We have to be careful here because the two might overlap. */ int dest_start = REGNO (operands[0]); @@ -6544,13 +7380,11 @@ output_mov_long_double_arm_from_arm (operands) } -/* Output a move from arm registers to an fpu registers. - OPERANDS[0] is an fpu register. +/* Output a move from arm registers to an fpa registers. + OPERANDS[0] is an fpa register. OPERANDS[1] is the first registers of an arm register pair. */ - const char * -output_mov_double_fpu_from_arm (operands) - rtx * operands; +output_mov_double_fpa_from_arm (rtx *operands) { int arm_reg0 = REGNO (operands[1]); rtx ops[2]; @@ -6565,13 +7399,11 @@ output_mov_double_fpu_from_arm (operands) return ""; } -/* Output a move from an fpu register to arm registers. +/* Output a move from an fpa register to arm registers. OPERANDS[0] is the first registers of an arm register pair. - OPERANDS[1] is an fpu register. */ - + OPERANDS[1] is an fpa register. */ const char * -output_mov_double_arm_from_fpu (operands) - rtx * operands; +output_mov_double_arm_from_fpa (rtx *operands) { int arm_reg0 = REGNO (operands[0]); rtx ops[2]; @@ -6589,10 +7421,8 @@ output_mov_double_arm_from_fpu (operands) /* Output a move between double words. It must be REG<-REG, REG<-CONST_DOUBLE, REG<-CONST_INT, REG<-MEM or MEM<-REG and all MEMs must be offsettable addresses. */ - const char * -output_move_double (operands) - rtx * operands; +output_move_double (rtx *operands) { enum rtx_code code0 = GET_CODE (operands[0]); enum rtx_code code1 = GET_CODE (operands[1]); @@ -6616,6 +7446,105 @@ output_move_double (operands) else output_asm_insn ("mov%?\t%R0, %R1\n\tmov%?\t%Q0, %Q1", operands); } + else if (code1 == CONST_VECTOR) + { + HOST_WIDE_INT hint = 0; + + switch (GET_MODE (operands[1])) + { + case V2SImode: + otherops[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 1))); + operands[1] = GEN_INT (INTVAL (CONST_VECTOR_ELT (operands[1], 0))); + break; + + case V4HImode: + if (BYTES_BIG_ENDIAN) + { + hint = INTVAL (CONST_VECTOR_ELT (operands[1], 2)); + hint <<= 16; + hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3)); + } + else + { + hint = INTVAL (CONST_VECTOR_ELT (operands[1], 3)); + hint <<= 16; + hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2)); + } + + otherops[1] = GEN_INT (hint); + hint = 0; + + if (BYTES_BIG_ENDIAN) + { + hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0)); + hint <<= 16; + hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1)); + } + else + { + hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1)); + hint <<= 16; + hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0)); + } + + operands[1] = GEN_INT (hint); + break; + + case V8QImode: + if (BYTES_BIG_ENDIAN) + { + hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4)); + hint <<= 8; + hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5)); + hint <<= 8; + hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6)); + hint <<= 8; + hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7)); + } + else + { + hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 7)); + hint <<= 8; + hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 6)); + hint <<= 8; + hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 5)); + hint <<= 8; + hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 4)); + } + + otherops[1] = GEN_INT (hint); + hint = 0; + + if (BYTES_BIG_ENDIAN) + { + hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0)); + hint <<= 8; + hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1)); + hint <<= 8; + hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2)); + hint <<= 8; + hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3)); + } + else + { + hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 3)); + hint <<= 8; + hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 2)); + hint <<= 8; + hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 1)); + hint <<= 8; + hint |= INTVAL (CONST_VECTOR_ELT (operands[1], 0)); + } + + operands[1] = GEN_INT (hint); + break; + + default: + abort (); + } + output_mov_immediate (operands); + output_mov_immediate (otherops); + } else if (code1 == CONST_DOUBLE) { if (GET_MODE (operands[1]) == DFmode) @@ -6715,7 +7644,7 @@ output_move_double (operands) { if (GET_CODE (otherops[2]) == CONST_INT) { - switch (INTVAL (otherops[2])) + switch ((int) INTVAL (otherops[2])) { case -8: output_asm_insn ("ldm%?db\t%1, %M0", otherops); @@ -6791,7 +7720,7 @@ output_move_double (operands) case PLUS: if (GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) { - switch (INTVAL (XEXP (XEXP (operands[0], 0), 1))) + switch ((int) INTVAL (XEXP (XEXP (operands[0], 0), 1))) { case -8: output_asm_insn ("stm%?db\t%m0, %M1", operands); @@ -6825,10 +7754,8 @@ output_move_double (operands) /* Output an arbitrary MOV reg, #n. OPERANDS[0] is a register. OPERANDS[1] is a const_int. */ - const char * -output_mov_immediate (operands) - rtx * operands; +output_mov_immediate (rtx *operands) { HOST_WIDE_INT n = INTVAL (operands[1]); @@ -6848,9 +7775,9 @@ output_mov_immediate (operands) int i; /* If all else fails, make it out of ORRs or BICs as appropriate. */ - for (i = 0; i < 32; i ++) + for (i = 0; i < 32; i++) if (n & 1 << i) - n_ones ++; + n_ones++; if (n_ones > 16) /* Shorter to use MVN with BIC in this case. */ output_multi_immediate (operands, "mvn%?\t%0, %1", "bic%?\t%0, %0, %1", 1, ~ n); @@ -6863,10 +7790,8 @@ output_mov_immediate (operands) /* Output an ADD r, s, #n where n may be too big for one instruction. If adding zero to one register, output nothing. */ - const char * -output_add_immediate (operands) - rtx * operands; +output_add_immediate (rtx *operands) { HOST_WIDE_INT n = INTVAL (operands[2]); @@ -6891,14 +7816,9 @@ output_add_immediate (operands) INSTR2 is the output pattern to use for subsequent constants. IMMED_OP is the index of the constant slot in OPERANDS. N is the constant value. */ - static const char * -output_multi_immediate (operands, instr1, instr2, immed_op, n) - rtx * operands; - const char * instr1; - const char * instr2; - int immed_op; - HOST_WIDE_INT n; +output_multi_immediate (rtx *operands, const char *instr1, const char *instr2, + int immed_op, HOST_WIDE_INT n) { #if HOST_BITS_PER_WIDE_INT > 32 n &= 0xffffffff; @@ -6935,11 +7855,8 @@ output_multi_immediate (operands, instr1, instr2, immed_op, n) The returned result should not be overwritten. OP is the rtx of the operation. SHIFT_FIRST_ARG is TRUE if the first argument of the operator was shifted. */ - const char * -arithmetic_instr (op, shift_first_arg) - rtx op; - int shift_first_arg; +arithmetic_instr (rtx op, int shift_first_arg) { switch (GET_CODE (op)) { @@ -6968,11 +7885,8 @@ arithmetic_instr (op, shift_first_arg) OP is the rtx code of the shift. On exit, *AMOUNTP will be -1 if the shift is by a register, or a constant shift. */ - static const char * -shift_op (op, amountp) - rtx op; - HOST_WIDE_INT *amountp; +shift_op (rtx op, HOST_WIDE_INT *amountp) { const char * mnem; enum rtx_code code = GET_CODE (op); @@ -7045,8 +7959,7 @@ shift_op (op, amountp) /* Obtain the shift from the POWER of two. */ static HOST_WIDE_INT -int_log2 (power) - HOST_WIDE_INT power; +int_log2 (HOST_WIDE_INT power) { HOST_WIDE_INT shift = 0; @@ -7054,7 +7967,7 @@ int_log2 (power) { if (shift > 31) abort (); - shift ++; + shift++; } return shift; @@ -7065,10 +7978,7 @@ int_log2 (power) #define MAX_ASCII_LEN 51 void -output_ascii_pseudo_op (stream, p, len) - FILE * stream; - const unsigned char * p; - int len; +output_ascii_pseudo_op (FILE *stream, const unsigned char *p, int len) { int i; int len_so_far = 0; @@ -7122,7 +8032,7 @@ output_ascii_pseudo_op (stream, p, len) case '\\': putc ('\\', stream); len_so_far++; - /* drop through. */ + /* Drop through. */ default: if (c >= ' ' && c <= '~') @@ -7145,9 +8055,8 @@ output_ascii_pseudo_op (stream, p, len) /* Compute the register sabe mask for registers 0 through 12 inclusive. This code is used by both arm_compute_save_reg_mask and arm_compute_initial_elimination_offset. */ - static unsigned long -arm_compute_save_reg0_reg12_mask () +arm_compute_save_reg0_reg12_mask (void) { unsigned long func_type = arm_current_func_type (); unsigned int save_reg_mask = 0; @@ -7207,7 +8116,7 @@ arm_compute_save_reg0_reg12_mask () saved on the stack for the current function. */ static unsigned long -arm_compute_save_reg_mask () +arm_compute_save_reg_mask (void) { unsigned int save_reg_mask = 0; unsigned long func_type = arm_current_func_type (); @@ -7239,7 +8148,7 @@ arm_compute_save_reg_mask () it. If we are pushing other registers onto the stack however, we can save an instruction in the epilogue by pushing the link register now and then popping it back into the PC. This incurs extra memory - accesses though, so we only do it when optimising for size, and only + accesses though, so we only do it when optimizing for size, and only if we know that we will not need a fancy return sequence. */ if (regs_ever_live [LR_REGNUM] || (save_reg_mask @@ -7250,17 +8159,41 @@ arm_compute_save_reg_mask () if (cfun->machine->lr_save_eliminated) save_reg_mask &= ~ (1 << LR_REGNUM); + if (TARGET_REALLY_IWMMXT + && ((bit_count (save_reg_mask) + + ARM_NUM_INTS (current_function_pretend_args_size)) % 2) != 0) + { + unsigned int reg; + + /* The total number of registers that are going to be pushed + onto the stack is odd. We need to ensure that the stack + is 64-bit aligned before we start to save iWMMXt registers, + and also before we start to create locals. (A local variable + might be a double or long long which we will load/store using + an iWMMXt instruction). Therefore we need to push another + ARM register, so that the stack will be 64-bit aligned. We + try to avoid using the arg registers (r0 -r3) as they might be + used to pass values in a tail call. */ + for (reg = 4; reg <= 12; reg++) + if ((save_reg_mask & (1 << reg)) == 0) + break; + + if (reg <= 12) + save_reg_mask |= (1 << reg); + else + { + cfun->machine->sibcall_blocked = 1; + save_reg_mask |= (1 << 3); + } + } + return save_reg_mask; } -/* Generate a function exit sequence. If REALLY_RETURN is true, then do +/* Generate a function exit sequence. If REALLY_RETURN is false, then do everything bar the final return instruction. */ - const char * -output_return_instruction (operand, really_return, reverse) - rtx operand; - int really_return; - int reverse; +output_return_instruction (rtx operand, int really_return, int reverse) { char conditional[10]; char instr[100]; @@ -7275,8 +8208,9 @@ output_return_instruction (operand, really_return, reverse) if (IS_VOLATILE (func_type) && TARGET_ABORT_NORETURN) { - /* If this function was declared non-returning, and we have found a tail - call, then we have to trust that the called function won't return. */ + /* If this function was declared non-returning, and we have + found a tail call, then we have to trust that the called + function won't return. */ if (really_return) { rtx ops[2]; @@ -7315,15 +8249,25 @@ output_return_instruction (operand, really_return, reverse) return_reg = reg_names[LR_REGNUM]; if ((live_regs_mask & (1 << IP_REGNUM)) == (1 << IP_REGNUM)) - /* There are two possible reasons for the IP register being saved. - Either a stack frame was created, in which case IP contains the - old stack pointer, or an ISR routine corrupted it. If this in an - ISR routine then just restore IP, otherwise restore IP into SP. */ - if (! IS_INTERRUPT (func_type)) - { - live_regs_mask &= ~ (1 << IP_REGNUM); - live_regs_mask |= (1 << SP_REGNUM); - } + { + /* There are three possible reasons for the IP register + being saved. 1) a stack frame was created, in which case + IP contains the old stack pointer, or 2) an ISR routine + corrupted it, or 3) it was saved to align the stack on + iWMMXt. In case 1, restore IP into SP, otherwise just + restore IP. */ + if (frame_pointer_needed) + { + live_regs_mask &= ~ (1 << IP_REGNUM); + live_regs_mask |= (1 << SP_REGNUM); + } + else + { + if (! IS_INTERRUPT (func_type) + && ! TARGET_REALLY_IWMMXT) + abort (); + } + } /* On some ARM architectures it is faster to use LDR rather than LDM to load a single register. On other architectures, the @@ -7348,11 +8292,29 @@ output_return_instruction (operand, really_return, reverse) char *p; int first = 1; - /* Generate the load multiple instruction to restore the registers. */ - if (frame_pointer_needed) - sprintf (instr, "ldm%sea\t%%|fp, {", conditional); - else if (live_regs_mask & (1 << SP_REGNUM)) - sprintf (instr, "ldm%sfd\t%%|sp, {", conditional); + /* Generate the load multiple instruction to restore the + registers. Note we can get here, even if + frame_pointer_needed is true, but only if sp already + points to the base of the saved core registers. */ + if (live_regs_mask & (1 << SP_REGNUM)) + { + unsigned HOST_WIDE_INT stack_adjust = + arm_get_frame_size () + current_function_outgoing_args_size; + + if (stack_adjust != 0 && stack_adjust != 4) + abort (); + + if (stack_adjust && arm_arch5) + sprintf (instr, "ldm%sib\t%%|sp, {", conditional); + else + { + /* If we can't use ldmib (SA110 bug), then try to pop r3 + instead. */ + if (stack_adjust) + live_regs_mask |= 1 << 3; + sprintf (instr, "ldm%sfd\t%%|sp, {", conditional); + } + } else sprintf (instr, "ldm%sfd\t%%|sp!, {", conditional); @@ -7378,20 +8340,22 @@ output_return_instruction (operand, really_return, reverse) if (live_regs_mask & (1 << LR_REGNUM)) { - int l = strlen (return_reg); - - if (! first) - { - memcpy (p, ", ", 2); - p += 2; - } - - memcpy (p, "%|", 2); - memcpy (p + 2, return_reg, l); - strcpy (p + 2 + l, ((TARGET_APCS_32 - && !IS_INTERRUPT (func_type)) - || !really_return) - ? "}" : "}^"); + sprintf (p, "%s%%|%s}", first ? "" : ", ", return_reg); + /* Decide if we need to add the ^ symbol to the end of the + register list. This causes the saved condition codes + register to be copied into the current condition codes + register. We do the copy if we are conforming to the 32-bit + ABI and this is an interrupt function, or if we are + conforming to the 26-bit ABI. There is a special case for + the 26-bit ABI however, which is if we are writing back the + stack pointer but not loading the PC. In this case adding + the ^ symbol would create a type 2 LDM instruction, where + writeback is UNPREDICTABLE. We are safe in leaving the ^ + character off in this case however, since the actual return + instruction will be a MOVS which will restore the CPSR. */ + if ((TARGET_APCS_32 && IS_INTERRUPT (func_type)) + || (! TARGET_APCS_32 && really_return)) + strcat (p, "^"); } else strcpy (p, "}"); @@ -7471,18 +8435,15 @@ output_return_instruction (operand, really_return, reverse) a leaf function. These function types will not contain a stack backtrace structure, therefore it is not possible to determine the function name. */ - void -arm_poke_function_name (stream, name) - FILE * stream; - const char * name; +arm_poke_function_name (FILE *stream, const char *name) { unsigned long alignlength; unsigned long length; rtx x; length = strlen (name) + 1; - alignlength = ROUND_UP (length); + alignlength = ROUND_UP_WORD (length); ASM_OUTPUT_ASCII (stream, name, length); ASM_OUTPUT_ALIGN (stream, 2); @@ -7492,11 +8453,8 @@ arm_poke_function_name (stream, name) /* Place some comments into the assembler stream describing the current function. */ - static void -arm_output_function_prologue (f, frame_size) - FILE * f; - HOST_WIDE_INT frame_size; +arm_output_function_prologue (FILE *f, HOST_WIDE_INT frame_size) { unsigned long func_type; @@ -7543,7 +8501,7 @@ arm_output_function_prologue (f, frame_size) if (IS_NESTED (func_type)) asm_fprintf (f, "\t%@ Nested: function declared inside another function.\n"); - asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %d\n", + asm_fprintf (f, "\t%@ args = %d, pretend = %d, frame = %wd\n", current_function_args_size, current_function_pretend_args_size, frame_size); @@ -7563,8 +8521,7 @@ arm_output_function_prologue (f, frame_size) } const char * -arm_output_epilogue (really_return) - int really_return; +arm_output_epilogue (rtx sibling) { int reg; unsigned long saved_regs_mask; @@ -7576,10 +8533,12 @@ arm_output_epilogue (really_return) int frame_size = arm_get_frame_size (); FILE * f = asm_out_file; rtx eh_ofs = cfun->machine->eh_epilogue_sp_ofs; + unsigned int lrm_count = 0; + int really_return = (sibling == NULL); /* If we have already generated the return instruction then it is futile to generate anything else. */ - if (use_return_insn (FALSE) && return_used_this_function) + if (use_return_insn (FALSE, sibling) && return_used_this_function) return ""; func_type = arm_current_func_type (); @@ -7607,12 +8566,15 @@ arm_output_epilogue (really_return) abort (); saved_regs_mask = arm_compute_save_reg_mask (); - + + if (TARGET_IWMMXT) + lrm_count = bit_count (saved_regs_mask); + /* XXX We should adjust floats_offset for any anonymous args, and then re-adjust vfp_offset below to compensate. */ /* Compute how far away the floats will be. */ - for (reg = 0; reg <= LAST_ARM_REGNUM; reg ++) + for (reg = 0; reg <= LAST_ARM_REGNUM; reg++) if (saved_regs_mask & (1 << reg)) floats_offset += 4; @@ -7620,7 +8582,7 @@ arm_output_epilogue (really_return) { int vfp_offset = 4; - if (arm_fpu_arch == FP_SOFT2) + if (arm_fpu_arch == FPUTYPE_FPA_EMU2) { for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--) if (regs_ever_live[reg] && !call_used_regs[reg]) @@ -7665,6 +8627,26 @@ arm_output_epilogue (really_return) FP_REGNUM, floats_offset - vfp_offset); } + if (TARGET_IWMMXT) + { + /* The frame pointer is guaranteed to be non-double-word aligned. + This is because it is set to (old_stack_pointer - 4) and the + old_stack_pointer was double word aligned. Thus the offset to + the iWMMXt registers to be loaded must also be non-double-word + sized, so that the resultant address *is* double-word aligned. + We can ignore floats_offset since that was already included in + the live_regs_mask. */ + lrm_count += (lrm_count % 2 ? 2 : 1); + + for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++) + if (regs_ever_live[reg] && !call_used_regs[reg]) + { + asm_fprintf (f, "\twldrd\t%r, [%r, #-%d]\n", + reg, FP_REGNUM, lrm_count * 4); + lrm_count += 2; + } + } + /* saved_regs_mask should contain the IP, which at the time of stack frame generation actually contains the old stack pointer. So a quick way to unwind the stack is just pop the IP register directly @@ -7684,8 +8666,22 @@ arm_output_epilogue (really_return) saved_regs_mask &= ~ (1 << LR_REGNUM); else saved_regs_mask &= ~ (1 << PC_REGNUM); - - print_multi_reg (f, "ldmea\t%r", FP_REGNUM, saved_regs_mask); + + /* We must use SP as the base register, because SP is one of the + registers being restored. If an interrupt or page fault + happens in the ldm instruction, the SP might or might not + have been restored. That would be bad, as then SP will no + longer indicate the safe area of stack, and we can get stack + corruption. Using SP as the base register means that it will + be reset correctly to the original value, should an interrupt + occur. If the stack pointer already points at the right + place, then omit the subtraction. */ + if (((frame_size + current_function_outgoing_args_size + floats_offset) + != 4 * (1 + (int) bit_count (saved_regs_mask))) + || current_function_calls_alloca) + asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, FP_REGNUM, + 4 * bit_count (saved_regs_mask)); + print_multi_reg (f, "ldmfd\t%r", SP_REGNUM, saved_regs_mask); if (IS_INTERRUPT (func_type)) /* Interrupt handlers will have pushed the @@ -7703,7 +8699,7 @@ arm_output_epilogue (really_return) output_add_immediate (operands); } - if (arm_fpu_arch == FP_SOFT2) + if (arm_fpu_arch == FPUTYPE_FPA_EMU2) { for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++) if (regs_ever_live[reg] && !call_used_regs[reg]) @@ -7742,6 +8738,11 @@ arm_output_epilogue (really_return) start_reg, reg - start_reg, SP_REGNUM); } + if (TARGET_IWMMXT) + for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++) + if (regs_ever_live[reg] && !call_used_regs[reg]) + asm_fprintf (f, "\twldrd\t%r, [%r, #+8]!\n", reg, SP_REGNUM); + /* If we can, restore the LR into the PC. */ if (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL && really_return @@ -7784,13 +8785,6 @@ arm_output_epilogue (really_return) } } -#if 0 - if (ARM_FUNC_TYPE (func_type) == ARM_FT_EXCEPTION_HANDLER) - /* Adjust the stack to remove the exception handler stuff. */ - asm_fprintf (f, "\tadd\t%r, %r, %r\n", SP_REGNUM, SP_REGNUM, - REGNO (eh_ofs)); -#endif - if (! really_return || (ARM_FUNC_TYPE (func_type) == ARM_FT_NORMAL && current_function_pretend_args_size == 0 @@ -7842,9 +8836,8 @@ arm_output_epilogue (really_return) } static void -arm_output_function_epilogue (file, frame_size) - FILE *file ATTRIBUTE_UNUSED; - HOST_WIDE_INT frame_size; +arm_output_function_epilogue (FILE *file ATTRIBUTE_UNUSED, + HOST_WIDE_INT frame_size) { if (TARGET_THUMB) { @@ -7858,7 +8851,7 @@ arm_output_function_epilogue (file, frame_size) /* We need to take into account any stack-frame rounding. */ frame_size = arm_get_frame_size (); - if (use_return_insn (FALSE) + if (use_return_insn (FALSE, NULL) && return_used_this_function && (frame_size + current_function_outgoing_args_size) != 0 && !frame_pointer_needed) @@ -7873,10 +8866,8 @@ arm_output_function_epilogue (file, frame_size) Unfortunately, since this insn does not reflect very well the actual semantics of the operation, we need to annotate the insn for the benefit of DWARF2 frame unwind information. */ - static rtx -emit_multi_reg_push (mask) - int mask; +emit_multi_reg_push (int mask) { int num_regs = 0; int num_dwarf_regs; @@ -8002,9 +8993,7 @@ emit_multi_reg_push (mask) } static rtx -emit_sfm (base_reg, count) - int base_reg; - int count; +emit_sfm (int base_reg, int count) { rtx par; rtx dwarf; @@ -8094,11 +9083,8 @@ emit_sfm (base_reg, count) The sign of the number returned reflects the direction of stack growth, so the values are positive for all eliminations except from the soft frame pointer to the hard frame pointer. */ - unsigned int -arm_compute_initial_elimination_offset (from, to) - unsigned int from; - unsigned int to; +arm_compute_initial_elimination_offset (unsigned int from, unsigned int to) { unsigned int local_vars = arm_get_frame_size (); unsigned int outgoing_args = current_function_outgoing_args_size; @@ -8118,34 +9104,32 @@ arm_compute_initial_elimination_offset (from, to) /* Make sure that we compute which registers will be saved on the stack using the same algorithm that is used by - arm_compute_save_reg_mask(). */ - reg_mask = arm_compute_save_reg0_reg12_mask (); + the prologue creation code. */ + reg_mask = arm_compute_save_reg_mask (); /* Now count the number of bits set in save_reg_mask. - For each set bit we need 4 bytes of stack space. */ - while (reg_mask) - { - call_saved_registers += 4; - reg_mask = reg_mask & ~ (reg_mask & - reg_mask); - } - - if ((regs_ever_live[LR_REGNUM] - /* If optimizing for size, then we save the link register if - any other integer register is saved. This gives a smaller - return sequence. */ - || (optimize_size && call_saved_registers > 0)) - /* But if a stack frame is going to be created, the LR will - be saved as part of that, so we do not need to allow for - it here. */ - && ! frame_pointer_needed) - call_saved_registers += 4; + If we have already counted the registers in the stack + frame, do not count them again. Non call-saved registers + might be saved in the call-save area of the stack, if + doing so will preserve the stack's alignment. Hence we + must count them here. For each set bit we need 4 bytes + of stack space. */ + if (frame_pointer_needed) + reg_mask &= 0x07ff; + call_saved_registers += 4 * bit_count (reg_mask); /* If the hard floating point registers are going to be used then they must be saved on the stack as well. Each register occupies 12 bytes of stack space. */ - for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg ++) + for (reg = FIRST_ARM_FP_REGNUM; reg <= LAST_ARM_FP_REGNUM; reg++) if (regs_ever_live[reg] && ! call_used_regs[reg]) call_saved_registers += 12; + + if (TARGET_REALLY_IWMMXT) + /* Check for the call-saved iWMMXt registers. */ + for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++) + if (regs_ever_live[reg] && ! call_used_regs [reg]) + call_saved_registers += 8; } /* The stack frame contains 4 registers - the old frame pointer, @@ -8227,13 +9211,12 @@ arm_compute_initial_elimination_offset (from, to) /* Calculate the size of the stack frame, taking into account any padding that is required to ensure stack-alignment. */ - HOST_WIDE_INT -arm_get_frame_size () +arm_get_frame_size (void) { int regno; - int base_size = ROUND_UP (get_frame_size ()); + int base_size = ROUND_UP_WORD (get_frame_size ()); int entry_size = 0; unsigned long func_type = arm_current_func_type (); int leaf; @@ -8288,6 +9271,14 @@ arm_get_frame_size () entry_size += 12; } + if (TARGET_REALLY_IWMMXT) + { + /* Check for the call-saved iWMMXt registers. */ + for (regno = FIRST_IWMMXT_REGNUM; regno <= LAST_IWMMXT_REGNUM; regno++) + if (regs_ever_live [regno] && ! call_used_regs [regno]) + entry_size += 8; + } + if ((entry_size + base_size + current_function_outgoing_args_size) & 7) base_size += 4; if ((entry_size + base_size + current_function_outgoing_args_size) & 7) @@ -8299,9 +9290,8 @@ arm_get_frame_size () } /* Generate the prologue instructions for entry into an ARM function. */ - void -arm_expand_prologue () +arm_expand_prologue (void) { int reg; rtx amount; @@ -8460,12 +9450,24 @@ arm_expand_prologue () RTX_FRAME_RELATED_P (insn) = 1; } + if (TARGET_IWMMXT) + for (reg = FIRST_IWMMXT_REGNUM; reg <= LAST_IWMMXT_REGNUM; reg++) + if (regs_ever_live[reg] && ! call_used_regs [reg]) + { + insn = gen_rtx_PRE_DEC (V2SImode, stack_pointer_rtx); + insn = gen_rtx_MEM (V2SImode, insn); + insn = emit_insn (gen_rtx_SET (VOIDmode, insn, + gen_rtx_REG (V2SImode, reg))); + RTX_FRAME_RELATED_P (insn) = 1; + } + if (! IS_VOLATILE (func_type)) { - /* Save any floating point call-saved registers used by this function. */ - if (arm_fpu_arch == FP_SOFT2) + /* Save any floating point call-saved registers used by this + function. */ + if (arm_fpu_arch == FPUTYPE_FPA_EMU2) { - for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg --) + for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--) if (regs_ever_live[reg] && !call_used_regs[reg]) { insn = gen_rtx_PRE_DEC (XFmode, stack_pointer_rtx); @@ -8479,7 +9481,7 @@ arm_expand_prologue () { int start_reg = LAST_ARM_FP_REGNUM; - for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg --) + for (reg = LAST_ARM_FP_REGNUM; reg >= FIRST_ARM_FP_REGNUM; reg--) { if (regs_ever_live[reg] && !call_used_regs[reg]) { @@ -8524,7 +9526,8 @@ arm_expand_prologue () insn = gen_rtx_REG (SImode, 3); else /* if (current_function_pretend_args_size == 0) */ { - insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx, GEN_INT (4)); + insn = gen_rtx_PLUS (SImode, hard_frame_pointer_rtx, + GEN_INT (4)); insn = gen_rtx_MEM (SImode, insn); } @@ -8587,12 +9590,8 @@ arm_expand_prologue () before output. If CODE is 'B' then output a bitwise inverted value of X (a const int). If X is a REG and CODE is `M', output a ldm/stm style multi-reg. */ - void -arm_print_operand (stream, x, code) - FILE * stream; - rtx x; - int code; +arm_print_operand (FILE *stream, rtx x, int code) { switch (code) { @@ -8655,6 +9654,16 @@ arm_print_operand (stream, x, code) fprintf (stream, "%s", arithmetic_instr (x, 1)); return; + /* Truncate Cirrus shift counts. */ + case 's': + if (GET_CODE (x) == CONST_INT) + { + fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x3f); + return; + } + arm_print_operand (stream, x, 0); + return; + case 'I': fprintf (stream, "%s", arithmetic_instr (x, 0)); return; @@ -8670,10 +9679,7 @@ arm_print_operand (stream, x, code) if (val == -1) arm_print_operand (stream, XEXP (x, 1), 0); else - { - fputc ('#', stream); - fprintf (stream, HOST_WIDE_INT_PRINT_DEC, val); - } + fprintf (stream, "#" HOST_WIDE_INT_PRINT_DEC, val); } } return; @@ -8682,13 +9688,13 @@ arm_print_operand (stream, x, code) In a pair of registers containing a DI or DF value the 'Q' operand returns the register number of the register containing - the least signficant part of the value. The 'R' operand returns + the least significant part of the value. The 'R' operand returns the register number of the register containing the most significant part of the value. The 'H' operand returns the higher of the two register numbers. On a run where WORDS_BIG_ENDIAN is true the 'H' operand is the - same as the 'Q' operand, since the most signficant part of the + same as the 'Q' operand, since the most significant part of the value is held in the lower number register. The reverse is true on systems where WORDS_BIG_ENDIAN is false. @@ -8740,11 +9746,8 @@ arm_print_operand (stream, x, code) if (x == const_true_rtx) return; - if (TARGET_ARM) - fputs (arm_condition_codes[get_arm_condition_code (x)], - stream); - else - fputs (thumb_condition_code (x, 0), stream); + fputs (arm_condition_codes[get_arm_condition_code (x)], + stream); return; case 'D': @@ -8753,12 +9756,76 @@ arm_print_operand (stream, x, code) if (x == const_true_rtx) abort (); - if (TARGET_ARM) - fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE - (get_arm_condition_code (x))], - stream); + fputs (arm_condition_codes[ARM_INVERSE_CONDITION_CODE + (get_arm_condition_code (x))], + stream); + return; + + /* Cirrus registers can be accessed in a variety of ways: + single floating point (f) + double floating point (d) + 32bit integer (fx) + 64bit integer (dx). */ + case 'W': /* Cirrus register in F mode. */ + case 'X': /* Cirrus register in D mode. */ + case 'Y': /* Cirrus register in FX mode. */ + case 'Z': /* Cirrus register in DX mode. */ + if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS) + abort (); + + fprintf (stream, "mv%s%s", + code == 'W' ? "f" + : code == 'X' ? "d" + : code == 'Y' ? "fx" : "dx", reg_names[REGNO (x)] + 2); + + return; + + /* Print cirrus register in the mode specified by the register's mode. */ + case 'V': + { + int mode = GET_MODE (x); + + if (GET_CODE (x) != REG || REGNO_REG_CLASS (REGNO (x)) != CIRRUS_REGS) + abort (); + + fprintf (stream, "mv%s%s", + mode == DFmode ? "d" + : mode == SImode ? "fx" + : mode == DImode ? "dx" + : "f", reg_names[REGNO (x)] + 2); + + return; + } + + case 'U': + if (GET_CODE (x) != REG + || REGNO (x) < FIRST_IWMMXT_GR_REGNUM + || REGNO (x) > LAST_IWMMXT_GR_REGNUM) + /* Bad value for wCG register number. */ + abort (); + else + fprintf (stream, "%d", REGNO (x) - FIRST_IWMMXT_GR_REGNUM); + return; + + /* Print an iWMMXt control register name. */ + case 'w': + if (GET_CODE (x) != CONST_INT + || INTVAL (x) < 0 + || INTVAL (x) >= 16) + /* Bad value for wC register number. */ + abort (); else - fputs (thumb_condition_code (x, 1), stream); + { + static const char * wc_reg_names [16] = + { + "wCID", "wCon", "wCSSF", "wCASF", + "wC4", "wC5", "wC6", "wC7", + "wCGR0", "wCGR1", "wCGR2", "wCGR3", + "wC12", "wC13", "wC14", "wC15" + }; + + fprintf (stream, wc_reg_names [INTVAL (x)]); + } return; default: @@ -8787,12 +9854,8 @@ arm_print_operand (stream, x, code) #ifndef AOF_ASSEMBLER /* Target hook for assembling integer objects. The ARM version needs to handle word-sized values specially. */ - static bool -arm_assemble_integer (x, size, aligned_p) - rtx x; - unsigned int size; - int aligned_p; +arm_assemble_integer (rtx x, unsigned int size, int aligned_p) { if (size == UNITS_PER_WORD && aligned_p) { @@ -8800,13 +9863,13 @@ arm_assemble_integer (x, size, aligned_p) output_addr_const (asm_out_file, x); /* Mark symbols as position independent. We only do this in the - .text segment, not in the .data segment. */ + .text segment, not in the .data segment. */ if (NEED_GOT_RELOC && flag_pic && making_const_table && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)) { if (GET_CODE (x) == SYMBOL_REF && (CONSTANT_POOL_ADDRESS_P (x) - || ENCODED_SHORT_CALL_ATTR_P (XSTR (x, 0)))) + || SYMBOL_REF_LOCAL_P (x))) fputs ("(GOTOFF)", asm_out_file); else if (GET_CODE (x) == LABEL_REF) fputs ("(GOTOFF)", asm_out_file); @@ -8817,6 +9880,36 @@ arm_assemble_integer (x, size, aligned_p) return true; } + if (VECTOR_MODE_SUPPORTED_P (GET_MODE (x))) + { + int i, units; + + if (GET_CODE (x) != CONST_VECTOR) + abort (); + + units = CONST_VECTOR_NUNITS (x); + + switch (GET_MODE (x)) + { + case V2SImode: size = 4; break; + case V4HImode: size = 2; break; + case V8QImode: size = 1; break; + default: + abort (); + } + + for (i = 0; i < units; i++) + { + rtx elt; + + elt = CONST_VECTOR_ELT (x, i); + assemble_integer + (elt, size, i == 0 ? BIGGEST_ALIGNMENT : size * BITS_PER_UNIT, 1); + } + + return true; + } + return default_assemble_integer (x, size, aligned_p); } #endif @@ -8838,7 +9931,7 @@ arm_assemble_integer (x, size, aligned_p) 0 -> 2 final_prescan_insn if the `target' is an unconditional branch 1 -> 3 ASM_OUTPUT_OPCODE after not having output the conditional branch 2 -> 4 ASM_OUTPUT_OPCODE after not having output the conditional branch - 3 -> 0 ASM_OUTPUT_INTERNAL_LABEL if the `target' label is reached + 3 -> 0 (*targetm.asm_out.internal_label) if the `target' label is reached (the target label has CODE_LABEL_NUMBER equal to arm_target_label). 4 -> 0 final_prescan_insn if the `target' unconditional branch is reached (the target insn is arm_target_insn). @@ -8855,10 +9948,8 @@ arm_assemble_integer (x, size, aligned_p) /* Returns the index of the ARM condition code string in `arm_condition_codes'. COMPARISON should be an rtx like `(eq (...) (...))'. */ - static enum arm_cond_code -get_arm_condition_code (comparison) - rtx comparison; +get_arm_condition_code (rtx comparison) { enum machine_mode mode = GET_MODE (XEXP (comparison, 0)); int code; @@ -8907,6 +9998,14 @@ get_arm_condition_code (comparison) default: abort (); } + case CC_Nmode: + switch (comp_code) + { + case NE: return ARM_MI; + case EQ: return ARM_PL; + default: abort (); + } + case CCFPEmode: case CCFPmode: /* These encodings assume that AC=1 in the FPA system control @@ -8978,10 +10077,8 @@ get_arm_condition_code (comparison) abort (); } - void -arm_final_prescan_insn (insn) - rtx insn; +arm_final_prescan_insn (rtx insn) { /* BODY will hold the body of INSN. */ rtx body = PATTERN (insn); @@ -9065,15 +10162,6 @@ arm_final_prescan_insn (insn) if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) > 0) body = XVECEXP (body, 0, 0); -#if 0 - /* If this is a conditional return then we don't want to know */ - if (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC - && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE - && (GET_CODE (XEXP (SET_SRC (body), 1)) == RETURN - || GET_CODE (XEXP (SET_SRC (body), 2)) == RETURN)) - return; -#endif - if (reverse || (GET_CODE (body) == SET && GET_CODE (SET_DEST (body)) == PC && GET_CODE (SET_SRC (body)) == IF_THEN_ELSE)) @@ -9201,7 +10289,8 @@ arm_final_prescan_insn (insn) /* If this is an unconditional branch to the same label, succeed. If it is to another label, do nothing. If it is conditional, fail. */ - /* XXX Probably, the tests for SET and the PC are unnecessary. */ + /* XXX Probably, the tests for SET and the PC are + unnecessary. */ scanbody = PATTERN (this_insn); if (GET_CODE (scanbody) == SET @@ -9219,7 +10308,7 @@ arm_final_prescan_insn (insn) /* Fail if a conditional return is undesirable (eg on a StrongARM), but still allow this if optimizing for size. */ else if (GET_CODE (scanbody) == RETURN - && !use_return_insn (TRUE) + && !use_return_insn (TRUE, NULL) && !optimize_size) fail = TRUE; else if (GET_CODE (scanbody) == RETURN @@ -9252,6 +10341,18 @@ arm_final_prescan_insn (insn) || GET_CODE (scanbody) == PARALLEL) || get_attr_conds (this_insn) != CONDS_NOCOND) fail = TRUE; + + /* A conditional cirrus instruction must be followed by + a non Cirrus instruction. However, since we + conditionalize instructions in this function and by + the time we get here we can't add instructions + (nops), because shorten_branches() has already been + called, we will disable conditionalizing Cirrus + instructions to be safe. */ + if (GET_CODE (scanbody) != USE + && GET_CODE (scanbody) != CLOBBER + && get_attr_cirrus (this_insn) != CIRRUS_NOT) + fail = TRUE; break; default: @@ -9273,7 +10374,7 @@ arm_final_prescan_insn (insn) } if (!this_insn) { - /* Oh, dear! we ran off the end.. give up */ + /* Oh, dear! we ran off the end.. give up. */ recog (PATTERN (insn), insn, NULL); arm_ccfsm_state = 0; arm_target_insn = NULL; @@ -9318,11 +10419,8 @@ arm_final_prescan_insn (insn) /* Returns true if REGNO is a valid register for holding a quantity of tyoe MODE. */ - int -arm_hard_regno_mode_ok (regno, mode) - unsigned int regno; - enum machine_mode mode; +arm_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode) { if (GET_MODE_CLASS (mode) == MODE_CC) return regno == CC_REGNUM; @@ -9335,8 +10433,22 @@ arm_hard_regno_mode_ok (regno, mode) start of an even numbered register pair. */ return (ARM_NUM_REGS (mode) < 2) || (regno < LAST_LO_REGNUM); + if (IS_CIRRUS_REGNUM (regno)) + /* We have outlawed SI values in Cirrus registers because they + reside in the lower 32 bits, but SF values reside in the + upper 32 bits. This causes gcc all sorts of grief. We can't + even split the registers into pairs because Cirrus SI values + get sign extended to 64bits-- aldyh. */ + return (GET_MODE_CLASS (mode) == MODE_FLOAT) || (mode == DImode); + + if (IS_IWMMXT_GR_REGNUM (regno)) + return mode == SImode; + + if (IS_IWMMXT_REGNUM (regno)) + return VALID_IWMMXT_REG_MODE (mode); + if (regno <= LAST_ARM_REGNUM) - /* We allow any value to be stored in the general regisetrs. */ + /* We allow any value to be stored in the general registers. */ return 1; if ( regno == FRAME_POINTER_REGNUM @@ -9344,7 +10456,7 @@ arm_hard_regno_mode_ok (regno, mode) /* We only allow integers in the fake hard registers. */ return GET_MODE_CLASS (mode) == MODE_INT; - /* The only registers left are the FPU registers + /* The only registers left are the FPA registers which we only allow to hold FP values. */ return GET_MODE_CLASS (mode) == MODE_FLOAT && regno >= FIRST_ARM_FP_REGNUM @@ -9352,8 +10464,7 @@ arm_hard_regno_mode_ok (regno, mode) } int -arm_regno_class (regno) - int regno; +arm_regno_class (int regno) { if (TARGET_THUMB) { @@ -9374,16 +10485,22 @@ arm_regno_class (regno) if (regno == CC_REGNUM) return NO_REGS; - return FPU_REGS; + if (IS_CIRRUS_REGNUM (regno)) + return CIRRUS_REGS; + + if (IS_IWMMXT_REGNUM (regno)) + return IWMMXT_REGS; + + if (IS_IWMMXT_GR_REGNUM (regno)) + return IWMMXT_GR_REGS; + + return FPA_REGS; } /* Handle a special case when computing the offset of an argument from the frame pointer. */ - int -arm_debugger_arg_offset (value, addr) - int value; - rtx addr; +arm_debugger_arg_offset (int value, rtx addr) { rtx insn; @@ -9434,7 +10551,7 @@ arm_debugger_arg_offset (value, addr) which is the frame pointer a constant integer - then... */ + then... */ for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) { @@ -9462,30 +10579,568 @@ arm_debugger_arg_offset (value, addr) return value; } + +#define def_mbuiltin(MASK, NAME, TYPE, CODE) \ + do \ + { \ + if ((MASK) & insn_flags) \ + builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE); \ + } \ + while (0) + +struct builtin_description +{ + const unsigned int mask; + const enum insn_code icode; + const char * const name; + const enum arm_builtins code; + const enum rtx_code comparison; + const unsigned int flag; +}; -#define def_builtin(NAME, TYPE, CODE) \ - builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, NULL, NULL_TREE) +static const struct builtin_description bdesc_2arg[] = +{ +#define IWMMXT_BUILTIN(code, string, builtin) \ + { FL_IWMMXT, CODE_FOR_##code, "__builtin_arm_" string, \ + ARM_BUILTIN_##builtin, 0, 0 }, + + IWMMXT_BUILTIN (addv8qi3, "waddb", WADDB) + IWMMXT_BUILTIN (addv4hi3, "waddh", WADDH) + IWMMXT_BUILTIN (addv2si3, "waddw", WADDW) + IWMMXT_BUILTIN (subv8qi3, "wsubb", WSUBB) + IWMMXT_BUILTIN (subv4hi3, "wsubh", WSUBH) + IWMMXT_BUILTIN (subv2si3, "wsubw", WSUBW) + IWMMXT_BUILTIN (ssaddv8qi3, "waddbss", WADDSSB) + IWMMXT_BUILTIN (ssaddv4hi3, "waddhss", WADDSSH) + IWMMXT_BUILTIN (ssaddv2si3, "waddwss", WADDSSW) + IWMMXT_BUILTIN (sssubv8qi3, "wsubbss", WSUBSSB) + IWMMXT_BUILTIN (sssubv4hi3, "wsubhss", WSUBSSH) + IWMMXT_BUILTIN (sssubv2si3, "wsubwss", WSUBSSW) + IWMMXT_BUILTIN (usaddv8qi3, "waddbus", WADDUSB) + IWMMXT_BUILTIN (usaddv4hi3, "waddhus", WADDUSH) + IWMMXT_BUILTIN (usaddv2si3, "waddwus", WADDUSW) + IWMMXT_BUILTIN (ussubv8qi3, "wsubbus", WSUBUSB) + IWMMXT_BUILTIN (ussubv4hi3, "wsubhus", WSUBUSH) + IWMMXT_BUILTIN (ussubv2si3, "wsubwus", WSUBUSW) + IWMMXT_BUILTIN (mulv4hi3, "wmulul", WMULUL) + IWMMXT_BUILTIN (smulv4hi3_highpart, "wmulsh", WMULSH) + IWMMXT_BUILTIN (umulv4hi3_highpart, "wmuluh", WMULUH) + IWMMXT_BUILTIN (eqv8qi3, "wcmpeqb", WCMPEQB) + IWMMXT_BUILTIN (eqv4hi3, "wcmpeqh", WCMPEQH) + IWMMXT_BUILTIN (eqv2si3, "wcmpeqw", WCMPEQW) + IWMMXT_BUILTIN (gtuv8qi3, "wcmpgtub", WCMPGTUB) + IWMMXT_BUILTIN (gtuv4hi3, "wcmpgtuh", WCMPGTUH) + IWMMXT_BUILTIN (gtuv2si3, "wcmpgtuw", WCMPGTUW) + IWMMXT_BUILTIN (gtv8qi3, "wcmpgtsb", WCMPGTSB) + IWMMXT_BUILTIN (gtv4hi3, "wcmpgtsh", WCMPGTSH) + IWMMXT_BUILTIN (gtv2si3, "wcmpgtsw", WCMPGTSW) + IWMMXT_BUILTIN (umaxv8qi3, "wmaxub", WMAXUB) + IWMMXT_BUILTIN (smaxv8qi3, "wmaxsb", WMAXSB) + IWMMXT_BUILTIN (umaxv4hi3, "wmaxuh", WMAXUH) + IWMMXT_BUILTIN (smaxv4hi3, "wmaxsh", WMAXSH) + IWMMXT_BUILTIN (umaxv2si3, "wmaxuw", WMAXUW) + IWMMXT_BUILTIN (smaxv2si3, "wmaxsw", WMAXSW) + IWMMXT_BUILTIN (uminv8qi3, "wminub", WMINUB) + IWMMXT_BUILTIN (sminv8qi3, "wminsb", WMINSB) + IWMMXT_BUILTIN (uminv4hi3, "wminuh", WMINUH) + IWMMXT_BUILTIN (sminv4hi3, "wminsh", WMINSH) + IWMMXT_BUILTIN (uminv2si3, "wminuw", WMINUW) + IWMMXT_BUILTIN (sminv2si3, "wminsw", WMINSW) + IWMMXT_BUILTIN (iwmmxt_anddi3, "wand", WAND) + IWMMXT_BUILTIN (iwmmxt_nanddi3, "wandn", WANDN) + IWMMXT_BUILTIN (iwmmxt_iordi3, "wor", WOR) + IWMMXT_BUILTIN (iwmmxt_xordi3, "wxor", WXOR) + IWMMXT_BUILTIN (iwmmxt_uavgv8qi3, "wavg2b", WAVG2B) + IWMMXT_BUILTIN (iwmmxt_uavgv4hi3, "wavg2h", WAVG2H) + IWMMXT_BUILTIN (iwmmxt_uavgrndv8qi3, "wavg2br", WAVG2BR) + IWMMXT_BUILTIN (iwmmxt_uavgrndv4hi3, "wavg2hr", WAVG2HR) + IWMMXT_BUILTIN (iwmmxt_wunpckilb, "wunpckilb", WUNPCKILB) + IWMMXT_BUILTIN (iwmmxt_wunpckilh, "wunpckilh", WUNPCKILH) + IWMMXT_BUILTIN (iwmmxt_wunpckilw, "wunpckilw", WUNPCKILW) + IWMMXT_BUILTIN (iwmmxt_wunpckihb, "wunpckihb", WUNPCKIHB) + IWMMXT_BUILTIN (iwmmxt_wunpckihh, "wunpckihh", WUNPCKIHH) + IWMMXT_BUILTIN (iwmmxt_wunpckihw, "wunpckihw", WUNPCKIHW) + IWMMXT_BUILTIN (iwmmxt_wmadds, "wmadds", WMADDS) + IWMMXT_BUILTIN (iwmmxt_wmaddu, "wmaddu", WMADDU) + +#define IWMMXT_BUILTIN2(code, builtin) \ + { FL_IWMMXT, CODE_FOR_##code, NULL, ARM_BUILTIN_##builtin, 0, 0 }, + + IWMMXT_BUILTIN2 (iwmmxt_wpackhss, WPACKHSS) + IWMMXT_BUILTIN2 (iwmmxt_wpackwss, WPACKWSS) + IWMMXT_BUILTIN2 (iwmmxt_wpackdss, WPACKDSS) + IWMMXT_BUILTIN2 (iwmmxt_wpackhus, WPACKHUS) + IWMMXT_BUILTIN2 (iwmmxt_wpackwus, WPACKWUS) + IWMMXT_BUILTIN2 (iwmmxt_wpackdus, WPACKDUS) + IWMMXT_BUILTIN2 (ashlv4hi3_di, WSLLH) + IWMMXT_BUILTIN2 (ashlv4hi3, WSLLHI) + IWMMXT_BUILTIN2 (ashlv2si3_di, WSLLW) + IWMMXT_BUILTIN2 (ashlv2si3, WSLLWI) + IWMMXT_BUILTIN2 (ashldi3_di, WSLLD) + IWMMXT_BUILTIN2 (ashldi3_iwmmxt, WSLLDI) + IWMMXT_BUILTIN2 (lshrv4hi3_di, WSRLH) + IWMMXT_BUILTIN2 (lshrv4hi3, WSRLHI) + IWMMXT_BUILTIN2 (lshrv2si3_di, WSRLW) + IWMMXT_BUILTIN2 (lshrv2si3, WSRLWI) + IWMMXT_BUILTIN2 (lshrdi3_di, WSRLD) + IWMMXT_BUILTIN2 (lshrdi3, WSRLDI) + IWMMXT_BUILTIN2 (ashrv4hi3_di, WSRAH) + IWMMXT_BUILTIN2 (ashrv4hi3, WSRAHI) + IWMMXT_BUILTIN2 (ashrv2si3_di, WSRAW) + IWMMXT_BUILTIN2 (ashrv2si3, WSRAWI) + IWMMXT_BUILTIN2 (ashrdi3_di, WSRAD) + IWMMXT_BUILTIN2 (ashrdi3, WSRADI) + IWMMXT_BUILTIN2 (rorv4hi3_di, WRORH) + IWMMXT_BUILTIN2 (rorv4hi3, WRORHI) + IWMMXT_BUILTIN2 (rorv2si3_di, WRORW) + IWMMXT_BUILTIN2 (rorv2si3, WRORWI) + IWMMXT_BUILTIN2 (rordi3_di, WRORD) + IWMMXT_BUILTIN2 (rordi3, WRORDI) + IWMMXT_BUILTIN2 (iwmmxt_wmacuz, WMACUZ) + IWMMXT_BUILTIN2 (iwmmxt_wmacsz, WMACSZ) +}; -void -arm_init_builtins () +static const struct builtin_description bdesc_1arg[] = +{ + IWMMXT_BUILTIN (iwmmxt_tmovmskb, "tmovmskb", TMOVMSKB) + IWMMXT_BUILTIN (iwmmxt_tmovmskh, "tmovmskh", TMOVMSKH) + IWMMXT_BUILTIN (iwmmxt_tmovmskw, "tmovmskw", TMOVMSKW) + IWMMXT_BUILTIN (iwmmxt_waccb, "waccb", WACCB) + IWMMXT_BUILTIN (iwmmxt_wacch, "wacch", WACCH) + IWMMXT_BUILTIN (iwmmxt_waccw, "waccw", WACCW) + IWMMXT_BUILTIN (iwmmxt_wunpckehub, "wunpckehub", WUNPCKEHUB) + IWMMXT_BUILTIN (iwmmxt_wunpckehuh, "wunpckehuh", WUNPCKEHUH) + IWMMXT_BUILTIN (iwmmxt_wunpckehuw, "wunpckehuw", WUNPCKEHUW) + IWMMXT_BUILTIN (iwmmxt_wunpckehsb, "wunpckehsb", WUNPCKEHSB) + IWMMXT_BUILTIN (iwmmxt_wunpckehsh, "wunpckehsh", WUNPCKEHSH) + IWMMXT_BUILTIN (iwmmxt_wunpckehsw, "wunpckehsw", WUNPCKEHSW) + IWMMXT_BUILTIN (iwmmxt_wunpckelub, "wunpckelub", WUNPCKELUB) + IWMMXT_BUILTIN (iwmmxt_wunpckeluh, "wunpckeluh", WUNPCKELUH) + IWMMXT_BUILTIN (iwmmxt_wunpckeluw, "wunpckeluw", WUNPCKELUW) + IWMMXT_BUILTIN (iwmmxt_wunpckelsb, "wunpckelsb", WUNPCKELSB) + IWMMXT_BUILTIN (iwmmxt_wunpckelsh, "wunpckelsh", WUNPCKELSH) + IWMMXT_BUILTIN (iwmmxt_wunpckelsw, "wunpckelsw", WUNPCKELSW) +}; + +/* Set up all the iWMMXt builtins. This is + not called if TARGET_IWMMXT is zero. */ + +static void +arm_init_iwmmxt_builtins (void) { + const struct builtin_description * d; + size_t i; tree endlink = void_list_node; - tree int_endlink = tree_cons (NULL_TREE, integer_type_node, endlink); - tree pchar_type_node = build_pointer_type (char_type_node); - tree int_ftype_int, void_ftype_pchar; + tree int_ftype_int + = build_function_type (integer_type_node, + tree_cons (NULL_TREE, integer_type_node, endlink)); + tree v8qi_ftype_v8qi_v8qi_int + = build_function_type (V8QI_type_node, + tree_cons (NULL_TREE, V8QI_type_node, + tree_cons (NULL_TREE, V8QI_type_node, + tree_cons (NULL_TREE, + integer_type_node, + endlink)))); + tree v4hi_ftype_v4hi_int + = build_function_type (V4HI_type_node, + tree_cons (NULL_TREE, V4HI_type_node, + tree_cons (NULL_TREE, integer_type_node, + endlink))); + tree v2si_ftype_v2si_int + = build_function_type (V2SI_type_node, + tree_cons (NULL_TREE, V2SI_type_node, + tree_cons (NULL_TREE, integer_type_node, + endlink))); + tree v2si_ftype_di_di + = build_function_type (V2SI_type_node, + tree_cons (NULL_TREE, long_long_integer_type_node, + tree_cons (NULL_TREE, long_long_integer_type_node, + endlink))); + tree di_ftype_di_int + = build_function_type (long_long_integer_type_node, + tree_cons (NULL_TREE, long_long_integer_type_node, + tree_cons (NULL_TREE, integer_type_node, + endlink))); + tree di_ftype_di_int_int + = build_function_type (long_long_integer_type_node, + tree_cons (NULL_TREE, long_long_integer_type_node, + tree_cons (NULL_TREE, integer_type_node, + tree_cons (NULL_TREE, + integer_type_node, + endlink)))); + tree int_ftype_v8qi + = build_function_type (integer_type_node, + tree_cons (NULL_TREE, V8QI_type_node, + endlink)); + tree int_ftype_v4hi + = build_function_type (integer_type_node, + tree_cons (NULL_TREE, V4HI_type_node, + endlink)); + tree int_ftype_v2si + = build_function_type (integer_type_node, + tree_cons (NULL_TREE, V2SI_type_node, + endlink)); + tree int_ftype_v8qi_int + = build_function_type (integer_type_node, + tree_cons (NULL_TREE, V8QI_type_node, + tree_cons (NULL_TREE, integer_type_node, + endlink))); + tree int_ftype_v4hi_int + = build_function_type (integer_type_node, + tree_cons (NULL_TREE, V4HI_type_node, + tree_cons (NULL_TREE, integer_type_node, + endlink))); + tree int_ftype_v2si_int + = build_function_type (integer_type_node, + tree_cons (NULL_TREE, V2SI_type_node, + tree_cons (NULL_TREE, integer_type_node, + endlink))); + tree v8qi_ftype_v8qi_int_int + = build_function_type (V8QI_type_node, + tree_cons (NULL_TREE, V8QI_type_node, + tree_cons (NULL_TREE, integer_type_node, + tree_cons (NULL_TREE, + integer_type_node, + endlink)))); + tree v4hi_ftype_v4hi_int_int + = build_function_type (V4HI_type_node, + tree_cons (NULL_TREE, V4HI_type_node, + tree_cons (NULL_TREE, integer_type_node, + tree_cons (NULL_TREE, + integer_type_node, + endlink)))); + tree v2si_ftype_v2si_int_int + = build_function_type (V2SI_type_node, + tree_cons (NULL_TREE, V2SI_type_node, + tree_cons (NULL_TREE, integer_type_node, + tree_cons (NULL_TREE, + integer_type_node, + endlink)))); + /* Miscellaneous. */ + tree v8qi_ftype_v4hi_v4hi + = build_function_type (V8QI_type_node, + tree_cons (NULL_TREE, V4HI_type_node, + tree_cons (NULL_TREE, V4HI_type_node, + endlink))); + tree v4hi_ftype_v2si_v2si + = build_function_type (V4HI_type_node, + tree_cons (NULL_TREE, V2SI_type_node, + tree_cons (NULL_TREE, V2SI_type_node, + endlink))); + tree v2si_ftype_v4hi_v4hi + = build_function_type (V2SI_type_node, + tree_cons (NULL_TREE, V4HI_type_node, + tree_cons (NULL_TREE, V4HI_type_node, + endlink))); + tree v2si_ftype_v8qi_v8qi + = build_function_type (V2SI_type_node, + tree_cons (NULL_TREE, V8QI_type_node, + tree_cons (NULL_TREE, V8QI_type_node, + endlink))); + tree v4hi_ftype_v4hi_di + = build_function_type (V4HI_type_node, + tree_cons (NULL_TREE, V4HI_type_node, + tree_cons (NULL_TREE, + long_long_integer_type_node, + endlink))); + tree v2si_ftype_v2si_di + = build_function_type (V2SI_type_node, + tree_cons (NULL_TREE, V2SI_type_node, + tree_cons (NULL_TREE, + long_long_integer_type_node, + endlink))); + tree void_ftype_int_int + = build_function_type (void_type_node, + tree_cons (NULL_TREE, integer_type_node, + tree_cons (NULL_TREE, integer_type_node, + endlink))); + tree di_ftype_void + = build_function_type (long_long_unsigned_type_node, endlink); + tree di_ftype_v8qi + = build_function_type (long_long_integer_type_node, + tree_cons (NULL_TREE, V8QI_type_node, + endlink)); + tree di_ftype_v4hi + = build_function_type (long_long_integer_type_node, + tree_cons (NULL_TREE, V4HI_type_node, + endlink)); + tree di_ftype_v2si + = build_function_type (long_long_integer_type_node, + tree_cons (NULL_TREE, V2SI_type_node, + endlink)); + tree v2si_ftype_v4hi + = build_function_type (V2SI_type_node, + tree_cons (NULL_TREE, V4HI_type_node, + endlink)); + tree v4hi_ftype_v8qi + = build_function_type (V4HI_type_node, + tree_cons (NULL_TREE, V8QI_type_node, + endlink)); + + tree di_ftype_di_v4hi_v4hi + = build_function_type (long_long_unsigned_type_node, + tree_cons (NULL_TREE, + long_long_unsigned_type_node, + tree_cons (NULL_TREE, V4HI_type_node, + tree_cons (NULL_TREE, + V4HI_type_node, + endlink)))); + + tree di_ftype_v4hi_v4hi + = build_function_type (long_long_unsigned_type_node, + tree_cons (NULL_TREE, V4HI_type_node, + tree_cons (NULL_TREE, V4HI_type_node, + endlink))); + + /* Normal vector binops. */ + tree v8qi_ftype_v8qi_v8qi + = build_function_type (V8QI_type_node, + tree_cons (NULL_TREE, V8QI_type_node, + tree_cons (NULL_TREE, V8QI_type_node, + endlink))); + tree v4hi_ftype_v4hi_v4hi + = build_function_type (V4HI_type_node, + tree_cons (NULL_TREE, V4HI_type_node, + tree_cons (NULL_TREE, V4HI_type_node, + endlink))); + tree v2si_ftype_v2si_v2si + = build_function_type (V2SI_type_node, + tree_cons (NULL_TREE, V2SI_type_node, + tree_cons (NULL_TREE, V2SI_type_node, + endlink))); + tree di_ftype_di_di + = build_function_type (long_long_unsigned_type_node, + tree_cons (NULL_TREE, long_long_unsigned_type_node, + tree_cons (NULL_TREE, + long_long_unsigned_type_node, + endlink))); + + /* Add all builtins that are more or less simple operations on two + operands. */ + for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) + { + /* Use one of the operands; the target can have a different mode for + mask-generating compares. */ + enum machine_mode mode; + tree type; + + if (d->name == 0) + continue; + + mode = insn_data[d->icode].operand[1].mode; + + switch (mode) + { + case V8QImode: + type = v8qi_ftype_v8qi_v8qi; + break; + case V4HImode: + type = v4hi_ftype_v4hi_v4hi; + break; + case V2SImode: + type = v2si_ftype_v2si_v2si; + break; + case DImode: + type = di_ftype_di_di; + break; + + default: + abort (); + } + + def_mbuiltin (d->mask, d->name, type, d->code); + } + + /* Add the remaining MMX insns with somewhat more complicated types. */ + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wzero", di_ftype_void, ARM_BUILTIN_WZERO); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_setwcx", void_ftype_int_int, ARM_BUILTIN_SETWCX); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_getwcx", int_ftype_int, ARM_BUILTIN_GETWCX); + + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSLLH); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllw", v2si_ftype_v2si_di, ARM_BUILTIN_WSLLW); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslld", di_ftype_di_di, ARM_BUILTIN_WSLLD); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSLLHI); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsllwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSLLWI); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wslldi", di_ftype_di_int, ARM_BUILTIN_WSLLDI); + + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRLH); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRLW); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrld", di_ftype_di_di, ARM_BUILTIN_WSRLD); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRLHI); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrlwi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRLWI); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrldi", di_ftype_di_int, ARM_BUILTIN_WSRLDI); + + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrah", v4hi_ftype_v4hi_di, ARM_BUILTIN_WSRAH); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsraw", v2si_ftype_v2si_di, ARM_BUILTIN_WSRAW); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrad", di_ftype_di_di, ARM_BUILTIN_WSRAD); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrahi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSRAHI); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsrawi", v2si_ftype_v2si_int, ARM_BUILTIN_WSRAWI); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsradi", di_ftype_di_int, ARM_BUILTIN_WSRADI); + + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorh", v4hi_ftype_v4hi_di, ARM_BUILTIN_WRORH); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorw", v2si_ftype_v2si_di, ARM_BUILTIN_WRORW); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrord", di_ftype_di_di, ARM_BUILTIN_WRORD); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorhi", v4hi_ftype_v4hi_int, ARM_BUILTIN_WRORHI); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrorwi", v2si_ftype_v2si_int, ARM_BUILTIN_WRORWI); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wrordi", di_ftype_di_int, ARM_BUILTIN_WRORDI); + + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wshufh", v4hi_ftype_v4hi_int, ARM_BUILTIN_WSHUFH); + + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadb", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADB); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadh", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADH); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadbz", v2si_ftype_v8qi_v8qi, ARM_BUILTIN_WSADBZ); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wsadhz", v2si_ftype_v4hi_v4hi, ARM_BUILTIN_WSADHZ); + + def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsb", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMSB); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMSH); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmsw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMSW); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmub", int_ftype_v8qi_int, ARM_BUILTIN_TEXTRMUB); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuh", int_ftype_v4hi_int, ARM_BUILTIN_TEXTRMUH); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_textrmuw", int_ftype_v2si_int, ARM_BUILTIN_TEXTRMUW); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrb", v8qi_ftype_v8qi_int_int, ARM_BUILTIN_TINSRB); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrh", v4hi_ftype_v4hi_int_int, ARM_BUILTIN_TINSRH); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_tinsrw", v2si_ftype_v2si_int_int, ARM_BUILTIN_TINSRW); + + def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccb", di_ftype_v8qi, ARM_BUILTIN_WACCB); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wacch", di_ftype_v4hi, ARM_BUILTIN_WACCH); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_waccw", di_ftype_v2si, ARM_BUILTIN_WACCW); + + def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskb", int_ftype_v8qi, ARM_BUILTIN_TMOVMSKB); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskh", int_ftype_v4hi, ARM_BUILTIN_TMOVMSKH); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmovmskw", int_ftype_v2si, ARM_BUILTIN_TMOVMSKW); + + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhss", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHSS); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackhus", v8qi_ftype_v4hi_v4hi, ARM_BUILTIN_WPACKHUS); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwus", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWUS); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackwss", v4hi_ftype_v2si_v2si, ARM_BUILTIN_WPACKWSS); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdus", v2si_ftype_di_di, ARM_BUILTIN_WPACKDUS); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wpackdss", v2si_ftype_di_di, ARM_BUILTIN_WPACKDSS); + + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHUB); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHUH); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehuw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHUW); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKEHSB); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKEHSH); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckehsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKEHSW); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelub", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELUB); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELUH); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckeluw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELUW); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsb", v4hi_ftype_v8qi, ARM_BUILTIN_WUNPCKELSB); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsh", v2si_ftype_v4hi, ARM_BUILTIN_WUNPCKELSH); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wunpckelsw", di_ftype_v2si, ARM_BUILTIN_WUNPCKELSW); + + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacs", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACS); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacsz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACSZ); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacu", di_ftype_di_v4hi_v4hi, ARM_BUILTIN_WMACU); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_wmacuz", di_ftype_v4hi_v4hi, ARM_BUILTIN_WMACUZ); + + def_mbuiltin (FL_IWMMXT, "__builtin_arm_walign", v8qi_ftype_v8qi_v8qi_int, ARM_BUILTIN_WALIGN); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmia", di_ftype_di_int_int, ARM_BUILTIN_TMIA); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiaph", di_ftype_di_int_int, ARM_BUILTIN_TMIAPH); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabb", di_ftype_di_int_int, ARM_BUILTIN_TMIABB); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiabt", di_ftype_di_int_int, ARM_BUILTIN_TMIABT); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatb", di_ftype_di_int_int, ARM_BUILTIN_TMIATB); + def_mbuiltin (FL_IWMMXT, "__builtin_arm_tmiatt", di_ftype_di_int_int, ARM_BUILTIN_TMIATT); +} + +static void +arm_init_builtins (void) +{ + if (TARGET_REALLY_IWMMXT) + arm_init_iwmmxt_builtins (); +} + +/* Errors in the source file can cause expand_expr to return const0_rtx + where we expect a vector. To avoid crashing, use one of the vector + clear instructions. */ + +static rtx +safe_vector_operand (rtx x, enum machine_mode mode) +{ + if (x != const0_rtx) + return x; + x = gen_reg_rtx (mode); + + emit_insn (gen_iwmmxt_clrdi (mode == DImode ? x + : gen_rtx_SUBREG (DImode, x, 0))); + return x; +} + +/* Subroutine of arm_expand_builtin to take care of binop insns. */ + +static rtx +arm_expand_binop_builtin (enum insn_code icode, + tree arglist, rtx target) +{ + rtx pat; + tree arg0 = TREE_VALUE (arglist); + tree arg1 = TREE_VALUE (TREE_CHAIN (arglist)); + rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); + rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + enum machine_mode tmode = insn_data[icode].operand[0].mode; + enum machine_mode mode0 = insn_data[icode].operand[1].mode; + enum machine_mode mode1 = insn_data[icode].operand[2].mode; + + if (VECTOR_MODE_P (mode0)) + op0 = safe_vector_operand (op0, mode0); + if (VECTOR_MODE_P (mode1)) + op1 = safe_vector_operand (op1, mode1); + + if (! target + || GET_MODE (target) != tmode + || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) + target = gen_reg_rtx (tmode); + + /* In case the insn wants input operands in modes different from + the result, abort. */ + if (GET_MODE (op0) != mode0 || GET_MODE (op1) != mode1) + abort (); + + if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) + op0 = copy_to_mode_reg (mode0, op0); + if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) + op1 = copy_to_mode_reg (mode1, op1); + + pat = GEN_FCN (icode) (target, op0, op1); + if (! pat) + return 0; + emit_insn (pat); + return target; +} - /* void func (char *) */ - void_ftype_pchar - = build_function_type_list (void_type_node, pchar_type_node, NULL_TREE); +/* Subroutine of arm_expand_builtin to take care of unop insns. */ - /* int func (int) */ - int_ftype_int - = build_function_type (integer_type_node, int_endlink); +static rtx +arm_expand_unop_builtin (enum insn_code icode, + tree arglist, rtx target, int do_load) +{ + rtx pat; + tree arg0 = TREE_VALUE (arglist); + rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); + enum machine_mode tmode = insn_data[icode].operand[0].mode; + enum machine_mode mode0 = insn_data[icode].operand[1].mode; + + if (! target + || GET_MODE (target) != tmode + || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) + target = gen_reg_rtx (tmode); + if (do_load) + op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0)); + else + { + if (VECTOR_MODE_P (mode0)) + op0 = safe_vector_operand (op0, mode0); + + if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) + op0 = copy_to_mode_reg (mode0, op0); + } - /* Initialize arm V5 builtins. */ - if (arm_arch5) - def_builtin ("__builtin_clz", int_ftype_int, ARM_BUILTIN_CLZ); + pat = GEN_FCN (icode) (target, op0); + if (! pat) + return 0; + emit_insn (pat); + return target; } /* Expand an expression EXP that calls a built-in function, @@ -9494,47 +11149,223 @@ arm_init_builtins () SUBTARGET may be used as the target for computing one of EXP's operands. IGNORE is nonzero if the value is to be ignored. */ -rtx -arm_expand_builtin (exp, target, subtarget, mode, ignore) - tree exp; - rtx target; - rtx subtarget ATTRIBUTE_UNUSED; - enum machine_mode mode ATTRIBUTE_UNUSED; - int ignore ATTRIBUTE_UNUSED; -{ - enum insn_code icode; - tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); - tree arglist = TREE_OPERAND (exp, 1); - tree arg0; - rtx op0, pat; - enum machine_mode tmode, mode0; - int fcode = DECL_FUNCTION_CODE (fndecl); +static rtx +arm_expand_builtin (tree exp, + rtx target, + rtx subtarget ATTRIBUTE_UNUSED, + enum machine_mode mode ATTRIBUTE_UNUSED, + int ignore ATTRIBUTE_UNUSED) +{ + const struct builtin_description * d; + enum insn_code icode; + tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0); + tree arglist = TREE_OPERAND (exp, 1); + tree arg0; + tree arg1; + tree arg2; + rtx op0; + rtx op1; + rtx op2; + rtx pat; + int fcode = DECL_FUNCTION_CODE (fndecl); + size_t i; + enum machine_mode tmode; + enum machine_mode mode0; + enum machine_mode mode1; + enum machine_mode mode2; switch (fcode) { - default: - break; - - case ARM_BUILTIN_CLZ: - icode = CODE_FOR_clz; + case ARM_BUILTIN_TEXTRMSB: + case ARM_BUILTIN_TEXTRMUB: + case ARM_BUILTIN_TEXTRMSH: + case ARM_BUILTIN_TEXTRMUH: + case ARM_BUILTIN_TEXTRMSW: + case ARM_BUILTIN_TEXTRMUW: + icode = (fcode == ARM_BUILTIN_TEXTRMSB ? CODE_FOR_iwmmxt_textrmsb + : fcode == ARM_BUILTIN_TEXTRMUB ? CODE_FOR_iwmmxt_textrmub + : fcode == ARM_BUILTIN_TEXTRMSH ? CODE_FOR_iwmmxt_textrmsh + : fcode == ARM_BUILTIN_TEXTRMUH ? CODE_FOR_iwmmxt_textrmuh + : CODE_FOR_iwmmxt_textrmw); + + arg0 = TREE_VALUE (arglist); + arg1 = TREE_VALUE (TREE_CHAIN (arglist)); + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + tmode = insn_data[icode].operand[0].mode; + mode0 = insn_data[icode].operand[1].mode; + mode1 = insn_data[icode].operand[2].mode; + + if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) + op0 = copy_to_mode_reg (mode0, op0); + if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) + { + /* @@@ better error message */ + error ("selector must be an immediate"); + return gen_reg_rtx (tmode); + } + if (target == 0 + || GET_MODE (target) != tmode + || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) + target = gen_reg_rtx (tmode); + pat = GEN_FCN (icode) (target, op0, op1); + if (! pat) + return 0; + emit_insn (pat); + return target; + + case ARM_BUILTIN_TINSRB: + case ARM_BUILTIN_TINSRH: + case ARM_BUILTIN_TINSRW: + icode = (fcode == ARM_BUILTIN_TINSRB ? CODE_FOR_iwmmxt_tinsrb + : fcode == ARM_BUILTIN_TINSRH ? CODE_FOR_iwmmxt_tinsrh + : CODE_FOR_iwmmxt_tinsrw); + arg0 = TREE_VALUE (arglist); + arg1 = TREE_VALUE (TREE_CHAIN (arglist)); + arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); + tmode = insn_data[icode].operand[0].mode; + mode0 = insn_data[icode].operand[1].mode; + mode1 = insn_data[icode].operand[2].mode; + mode2 = insn_data[icode].operand[3].mode; + + if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) + op0 = copy_to_mode_reg (mode0, op0); + if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) + op1 = copy_to_mode_reg (mode1, op1); + if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) + { + /* @@@ better error message */ + error ("selector must be an immediate"); + return const0_rtx; + } + if (target == 0 + || GET_MODE (target) != tmode + || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) + target = gen_reg_rtx (tmode); + pat = GEN_FCN (icode) (target, op0, op1, op2); + if (! pat) + return 0; + emit_insn (pat); + return target; + + case ARM_BUILTIN_SETWCX: + arg0 = TREE_VALUE (arglist); + arg1 = TREE_VALUE (TREE_CHAIN (arglist)); + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + emit_insn (gen_iwmmxt_tmcr (op0, op1)); + return 0; + + case ARM_BUILTIN_GETWCX: + arg0 = TREE_VALUE (arglist); + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); + target = gen_reg_rtx (SImode); + emit_insn (gen_iwmmxt_tmrc (target, op0)); + return target; + + case ARM_BUILTIN_WSHUFH: + icode = CODE_FOR_iwmmxt_wshufh; + arg0 = TREE_VALUE (arglist); + arg1 = TREE_VALUE (TREE_CHAIN (arglist)); + op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + tmode = insn_data[icode].operand[0].mode; + mode1 = insn_data[icode].operand[1].mode; + mode2 = insn_data[icode].operand[2].mode; + + if (! (*insn_data[icode].operand[1].predicate) (op0, mode1)) + op0 = copy_to_mode_reg (mode1, op0); + if (! (*insn_data[icode].operand[2].predicate) (op1, mode2)) + { + /* @@@ better error message */ + error ("mask must be an immediate"); + return const0_rtx; + } + if (target == 0 + || GET_MODE (target) != tmode + || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) + target = gen_reg_rtx (tmode); + pat = GEN_FCN (icode) (target, op0, op1); + if (! pat) + return 0; + emit_insn (pat); + return target; + + case ARM_BUILTIN_WSADB: + return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadb, arglist, target); + case ARM_BUILTIN_WSADH: + return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadh, arglist, target); + case ARM_BUILTIN_WSADBZ: + return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadbz, arglist, target); + case ARM_BUILTIN_WSADHZ: + return arm_expand_binop_builtin (CODE_FOR_iwmmxt_wsadhz, arglist, target); + + /* Several three-argument builtins. */ + case ARM_BUILTIN_WMACS: + case ARM_BUILTIN_WMACU: + case ARM_BUILTIN_WALIGN: + case ARM_BUILTIN_TMIA: + case ARM_BUILTIN_TMIAPH: + case ARM_BUILTIN_TMIATT: + case ARM_BUILTIN_TMIATB: + case ARM_BUILTIN_TMIABT: + case ARM_BUILTIN_TMIABB: + icode = (fcode == ARM_BUILTIN_WMACS ? CODE_FOR_iwmmxt_wmacs + : fcode == ARM_BUILTIN_WMACU ? CODE_FOR_iwmmxt_wmacu + : fcode == ARM_BUILTIN_TMIA ? CODE_FOR_iwmmxt_tmia + : fcode == ARM_BUILTIN_TMIAPH ? CODE_FOR_iwmmxt_tmiaph + : fcode == ARM_BUILTIN_TMIABB ? CODE_FOR_iwmmxt_tmiabb + : fcode == ARM_BUILTIN_TMIABT ? CODE_FOR_iwmmxt_tmiabt + : fcode == ARM_BUILTIN_TMIATB ? CODE_FOR_iwmmxt_tmiatb + : fcode == ARM_BUILTIN_TMIATT ? CODE_FOR_iwmmxt_tmiatt + : CODE_FOR_iwmmxt_walign); arg0 = TREE_VALUE (arglist); + arg1 = TREE_VALUE (TREE_CHAIN (arglist)); + arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist))); op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0); + op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0); + op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0); tmode = insn_data[icode].operand[0].mode; mode0 = insn_data[icode].operand[1].mode; + mode1 = insn_data[icode].operand[2].mode; + mode2 = insn_data[icode].operand[3].mode; if (! (*insn_data[icode].operand[1].predicate) (op0, mode0)) op0 = copy_to_mode_reg (mode0, op0); + if (! (*insn_data[icode].operand[2].predicate) (op1, mode1)) + op1 = copy_to_mode_reg (mode1, op1); + if (! (*insn_data[icode].operand[3].predicate) (op2, mode2)) + op2 = copy_to_mode_reg (mode2, op2); if (target == 0 || GET_MODE (target) != tmode || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) target = gen_reg_rtx (tmode); - pat = GEN_FCN (icode) (target, op0); + pat = GEN_FCN (icode) (target, op0, op1, op2); if (! pat) return 0; emit_insn (pat); return target; + + case ARM_BUILTIN_WZERO: + target = gen_reg_rtx (DImode); + emit_insn (gen_iwmmxt_clrdi (target)); + return target; + + default: + break; } + for (i = 0, d = bdesc_2arg; i < ARRAY_SIZE (bdesc_2arg); i++, d++) + if (d->code == (const enum arm_builtins) fcode) + return arm_expand_binop_builtin (d->icode, arglist, target); + + for (i = 0, d = bdesc_1arg; i < ARRAY_SIZE (bdesc_1arg); i++, d++) + if (d->code == (const enum arm_builtins) fcode) + return arm_expand_unop_builtin (d->icode, arglist, target, 0); + /* @@@ Should really do something sensible here. */ return NULL_RTX; } @@ -9543,12 +11374,8 @@ arm_expand_builtin (exp, target, subtarget, mode, ignore) checking to see if any of the variables created in that function match the RTX called 'orig'. If they do then replace them with the RTX called 'new'. */ - static void -replace_symbols_in_block (block, orig, new) - tree block; - rtx orig; - rtx new; +replace_symbols_in_block (tree block, rtx orig, rtx new) { for (; block; block = BLOCK_CHAIN (block)) { @@ -9577,12 +11404,8 @@ replace_symbols_in_block (block, orig, new) /* Return the number (counting from 0) of the least significant set bit in MASK. */ -#ifdef __GNUC__ -inline -#endif -static int -number_of_first_bit_set (mask) - int mask; +inline static int +number_of_first_bit_set (int mask) { int bit; @@ -9598,10 +11421,7 @@ number_of_first_bit_set (mask) If 'reg_containing_return_addr' is -1, then the return address is actually on the stack, at the stack pointer. */ static void -thumb_exit (f, reg_containing_return_addr, eh_ofs) - FILE * f; - int reg_containing_return_addr; - rtx eh_ofs; +thumb_exit (FILE *f, int reg_containing_return_addr, rtx eh_ofs) { unsigned regs_available_for_popping; unsigned regs_to_pop; @@ -9756,7 +11576,8 @@ thumb_exit (f, reg_containing_return_addr, eh_ofs) } /* Pop as many registers as we can. */ - thumb_pushpop (f, regs_available_for_popping, FALSE); + thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, + regs_available_for_popping); /* Process the registers we popped. */ if (reg_containing_return_addr == -1) @@ -9768,7 +11589,7 @@ thumb_exit (f, reg_containing_return_addr, eh_ofs) number_of_first_bit_set (regs_available_for_popping); /* Remove this register for the mask of available registers, so that - the return address will not be corrupted by futher pops. */ + the return address will not be corrupted by further pops. */ regs_available_for_popping &= ~(1 << reg_containing_return_addr); } @@ -9837,7 +11658,8 @@ thumb_exit (f, reg_containing_return_addr, eh_ofs) int popped_into; int move_to; - thumb_pushpop (f, regs_available_for_popping, FALSE); + thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, + regs_available_for_popping); /* We have popped either FP or SP. Move whichever one it is into the correct register. */ @@ -9857,7 +11679,8 @@ thumb_exit (f, reg_containing_return_addr, eh_ofs) { int popped_into; - thumb_pushpop (f, regs_available_for_popping, FALSE); + thumb_pushpop (f, regs_available_for_popping, FALSE, NULL, + regs_available_for_popping); popped_into = number_of_first_bit_set (regs_available_for_popping); @@ -9887,16 +11710,20 @@ thumb_exit (f, reg_containing_return_addr, eh_ofs) asm_fprintf (f, "\tbx\t%r\n", reg_containing_return_addr); } -/* Emit code to push or pop registers to or from the stack. */ - +/* Emit code to push or pop registers to or from the stack. F is the + assembly file. MASK is the registers to push or pop. PUSH is + non-zero if we should push, and zero if we should pop. For debugging + output, if pushing, adjust CFA_OFFSET by the amount of space added + to the stack. REAL_REGS should have the same number of bits set as + MASK, and will be used instead (in the same order) to describe which + registers were saved - this is used to mark the save slots when we + push high registers after moving them to low registers. */ static void -thumb_pushpop (f, mask, push) - FILE * f; - int mask; - int push; +thumb_pushpop (FILE *f, int mask, int push, int *cfa_offset, int real_regs) { int regno; int lo_mask = mask & 0xFF; + int pushed_words = 0; if (lo_mask == 0 && !push && (mask & (1 << 15))) { @@ -9917,6 +11744,8 @@ thumb_pushpop (f, mask, push) if ((lo_mask & ~1) != 0) fprintf (f, ", "); + + pushed_words++; } } @@ -9927,6 +11756,8 @@ thumb_pushpop (f, mask, push) fprintf (f, ", "); asm_fprintf (f, "%r", LR_REGNUM); + + pushed_words++; } else if (!push && (mask & (1 << PC_REGNUM))) { @@ -9951,11 +11782,27 @@ thumb_pushpop (f, mask, push) } fprintf (f, "}\n"); + + if (push && pushed_words && dwarf2out_do_frame ()) + { + char *l = dwarf2out_cfi_label (); + int pushed_mask = real_regs; + + *cfa_offset += pushed_words * 4; + dwarf2out_def_cfa (l, SP_REGNUM, *cfa_offset); + + pushed_words = 0; + pushed_mask = real_regs; + for (regno = 0; regno <= 14; regno++, pushed_mask >>= 1) + { + if (pushed_mask & 1) + dwarf2out_reg_save (l, regno, 4 * pushed_words++ - *cfa_offset); + } + } } void -thumb_final_prescan_insn (insn) - rtx insn; +thumb_final_prescan_insn (rtx insn) { if (flag_print_asm_name) asm_fprintf (asm_out_file, "%@ 0x%04x\n", @@ -9963,8 +11810,7 @@ thumb_final_prescan_insn (insn) } int -thumb_shiftable_const (val) - unsigned HOST_WIDE_INT val; +thumb_shiftable_const (unsigned HOST_WIDE_INT val) { unsigned HOST_WIDE_INT mask = 0xff; int i; @@ -9981,10 +11827,8 @@ thumb_shiftable_const (val) /* Returns nonzero if the current function contains, or might contain a far jump. */ - int -thumb_far_jump_used_p (in_prologue) - int in_prologue; +thumb_far_jump_used_p (int in_prologue) { rtx insn; @@ -10039,7 +11883,7 @@ thumb_far_jump_used_p (in_prologue) && get_attr_far_jump (insn) == FAR_JUMP_YES ) { - /* Record the fact that we have decied that + /* Record the fact that we have decided that the function does use far jumps. */ cfun->machine->far_jump_used = 1; return 1; @@ -10050,10 +11894,8 @@ thumb_far_jump_used_p (in_prologue) } /* Return nonzero if FUNC must be entered in ARM mode. */ - int -is_called_in_ARM_mode (func) - tree func; +is_called_in_ARM_mode (tree func) { if (TREE_CODE (func) != FUNCTION_DECL) abort (); @@ -10069,10 +11911,9 @@ is_called_in_ARM_mode (func) #endif } -/* The bits which aren't usefully expanded as rtl. */ - +/* The bits which aren't usefully expanded as rtl. */ const char * -thumb_unexpanded_epilogue () +thumb_unexpanded_epilogue (void) { int regno; int live_regs_mask = 0; @@ -10096,7 +11937,7 @@ thumb_unexpanded_epilogue () high_regs_pushed++; /* The prolog may have pushed some high registers to use as - work registers. eg the testuite file: + work registers. eg the testsuite file: gcc/testsuite/gcc/gcc.c-torture/execute/complex-2.c compiles to produce: push {r4, r5, r6, r7, lr} @@ -10155,8 +11996,8 @@ thumb_unexpanded_epilogue () mask &= (2 << regno) - 1; /* A noop if regno == 8 */ - /* Pop the values into the low register(s). */ - thumb_pushpop (asm_out_file, mask, 0); + /* Pop the values into the low register(s). */ + thumb_pushpop (asm_out_file, mask, 0, NULL, mask); /* Move the value(s) into the high registers. */ for (regno = 0; regno <= LAST_LO_REGNUM; regno++) @@ -10183,7 +12024,7 @@ thumb_unexpanded_epilogue () { /* The stack backtrace structure creation code had to push R7 in order to get a work register, so we pop - it now. */ + it now. */ live_regs_mask |= (1 << LAST_LO_REGNUM); } @@ -10198,7 +12039,8 @@ thumb_unexpanded_epilogue () structure was created which includes an adjusted stack pointer, so just pop everything. */ if (live_regs_mask) - thumb_pushpop (asm_out_file, live_regs_mask, FALSE); + thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL, + live_regs_mask); if (eh_ofs) thumb_exit (asm_out_file, 2, eh_ofs); @@ -10218,11 +12060,13 @@ thumb_unexpanded_epilogue () live_regs_mask &= ~(1 << PC_REGNUM); if (live_regs_mask) - thumb_pushpop (asm_out_file, live_regs_mask, FALSE); + thumb_pushpop (asm_out_file, live_regs_mask, FALSE, NULL, + live_regs_mask); if (had_to_push_lr) /* Get the return address into a temporary register. */ - thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0); + thumb_pushpop (asm_out_file, 1 << LAST_ARG_REGNUM, 0, NULL, + 1 << LAST_ARG_REGNUM); /* Remove the argument registers that were pushed onto the stack. */ asm_fprintf (asm_out_file, "\tadd\t%r, %r, #%d\n", @@ -10240,9 +12084,8 @@ thumb_unexpanded_epilogue () } /* Functions to save and restore machine-specific function data. */ - static struct machine_function * -arm_init_machine_status () +arm_init_machine_status (void) { struct machine_function *machine; machine = (machine_function *) ggc_alloc_cleared (sizeof (machine_function)); @@ -10255,11 +12098,8 @@ arm_init_machine_status () /* Return an RTX indicating where the return address to the calling function can be found. */ - rtx -arm_return_addr (count, frame) - int count; - rtx frame ATTRIBUTE_UNUSED; +arm_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) { if (count != 0) return NULL_RTX; @@ -10275,20 +12115,19 @@ arm_return_addr (count, frame) } /* Do anything needed before RTL is emitted for each function. */ - void -arm_init_expanders () +arm_init_expanders (void) { /* Arrange to initialize and mark the machine per-function status. */ init_machine_status = arm_init_machine_status; } HOST_WIDE_INT -thumb_get_frame_size () +thumb_get_frame_size (void) { int regno; - int base_size = ROUND_UP (get_frame_size ()); + int base_size = ROUND_UP_WORD (get_frame_size ()); int count_regs = 0; int entry_size = 0; int leaf; @@ -10370,10 +12209,11 @@ thumb_get_frame_size () } /* Generate the rest of a function's prologue. */ - void -thumb_expand_prologue () +thumb_expand_prologue (void) { + rtx insn, dwarf; + HOST_WIDE_INT amount = (thumb_get_frame_size () + current_function_outgoing_args_size); unsigned long func_type; @@ -10391,15 +12231,21 @@ thumb_expand_prologue () } if (frame_pointer_needed) - emit_insn (gen_movsi (hard_frame_pointer_rtx, stack_pointer_rtx)); + { + insn = emit_insn (gen_movsi (hard_frame_pointer_rtx, stack_pointer_rtx)); + RTX_FRAME_RELATED_P (insn) = 1; + } if (amount) { - amount = ROUND_UP (amount); + amount = ROUND_UP_WORD (amount); if (amount < 512) - emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, - GEN_INT (- amount))); + { + insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, + GEN_INT (- amount))); + RTX_FRAME_RELATED_P (insn) = 1; + } else { int regno; @@ -10429,7 +12275,7 @@ thumb_expand_prologue () { rtx spare = gen_rtx (REG, SImode, IP_REGNUM); - /* Choose an arbitary, non-argument low register. */ + /* Choose an arbitrary, non-argument low register. */ reg = gen_rtx (REG, SImode, LAST_LO_REGNUM); /* Save it by copying it into a high, scratch register. */ @@ -10439,8 +12285,16 @@ thumb_expand_prologue () /* Decrement the stack. */ emit_insn (gen_movsi (reg, GEN_INT (- amount))); - emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, - reg)); + insn = emit_insn (gen_addsi3 (stack_pointer_rtx, + stack_pointer_rtx, reg)); + RTX_FRAME_RELATED_P (insn) = 1; + dwarf = gen_rtx_SET (SImode, stack_pointer_rtx, + plus_constant (stack_pointer_rtx, + GEN_INT (- amount))); + RTX_FRAME_RELATED_P (dwarf) = 1; + REG_NOTES (insn) + = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, + REG_NOTES (insn)); /* Restore the low register's original value. */ emit_insn (gen_movsi (reg, spare)); @@ -10456,8 +12310,17 @@ thumb_expand_prologue () reg = gen_rtx (REG, SImode, regno); emit_insn (gen_movsi (reg, GEN_INT (- amount))); - emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, - reg)); + + insn = emit_insn (gen_addsi3 (stack_pointer_rtx, + stack_pointer_rtx, reg)); + RTX_FRAME_RELATED_P (insn) = 1; + dwarf = gen_rtx_SET (SImode, stack_pointer_rtx, + plus_constant (stack_pointer_rtx, + GEN_INT (- amount))); + RTX_FRAME_RELATED_P (dwarf) = 1; + REG_NOTES (insn) + = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR, dwarf, + REG_NOTES (insn)); } } } @@ -10467,11 +12330,12 @@ thumb_expand_prologue () } void -thumb_expand_epilogue () +thumb_expand_epilogue (void) { HOST_WIDE_INT amount = (thumb_get_frame_size () + current_function_outgoing_args_size); - + int regno; + /* Naked functions don't have prologues. */ if (IS_NAKED (arm_current_func_type ())) return; @@ -10480,7 +12344,7 @@ thumb_expand_epilogue () emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx)); else if (amount) { - amount = ROUND_UP (amount); + amount = ROUND_UP_WORD (amount); if (amount < 512) emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, @@ -10501,15 +12365,23 @@ thumb_expand_epilogue () if (current_function_profile || TARGET_NO_SCHED_PRO) emit_insn (gen_blockage ()); + + /* Emit a clobber for each insn that will be restored in the epilogue, + so that flow2 will get register lifetimes correct. */ + for (regno = 0; regno < 13; regno++) + if (regs_ever_live[regno] && !call_used_regs[regno]) + emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, regno))); + + if (! regs_ever_live[LR_REGNUM]) + emit_insn (gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM))); } static void -thumb_output_function_prologue (f, size) - FILE * f; - HOST_WIDE_INT size ATTRIBUTE_UNUSED; +thumb_output_function_prologue (FILE *f, HOST_WIDE_INT size ATTRIBUTE_UNUSED) { int live_regs_mask = 0; int high_regs_pushed = 0; + int cfa_offset = 0; int regno; if (IS_NAKED (arm_current_func_type ())) @@ -10536,7 +12408,7 @@ thumb_output_function_prologue (f, size) the assembler to bypass the ARM code when this function is called from a Thumb encoded function elsewhere in the same file. Hence the definition of STUB_NAME here must - agree with the definition in gas/config/tc-arm.c */ + agree with the definition in gas/config/tc-arm.c. */ #define STUB_NAME ".real_start_of" @@ -10572,6 +12444,16 @@ thumb_output_function_prologue (f, size) asm_fprintf (f, "\tsub\t%r, %r, #%d\n", SP_REGNUM, SP_REGNUM, current_function_pretend_args_size); + + /* We don't need to record the stores for unwinding (would it + help the debugger any if we did?), but record the change in + the stack pointer. */ + if (dwarf2out_do_frame ()) + { + char *l = dwarf2out_cfi_label (); + cfa_offset = cfa_offset + current_function_pretend_args_size; + dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset); + } } for (regno = 0; regno <= LAST_LO_REGNUM; regno++) @@ -10611,7 +12493,7 @@ thumb_output_function_prologue (f, size) if (regs_ever_live [LAST_ARG_REGNUM] == 0) work_register = LAST_ARG_REGNUM; - else /* We must push a register of our own */ + else /* We must push a register of our own. */ live_regs_mask |= (1 << LAST_LO_REGNUM); } @@ -10627,9 +12509,16 @@ thumb_output_function_prologue (f, size) asm_fprintf (f, "\tsub\t%r, %r, #16\t%@ Create stack backtrace structure\n", SP_REGNUM, SP_REGNUM); - + + if (dwarf2out_do_frame ()) + { + char *l = dwarf2out_cfi_label (); + cfa_offset = cfa_offset + 16; + dwarf2out_def_cfa (l, SP_REGNUM, cfa_offset); + } + if (live_regs_mask) - thumb_pushpop (f, live_regs_mask, 1); + thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask); for (offset = 0, wr = 1 << 15; wr != 0; wr >>= 1) if (wr & live_regs_mask) @@ -10673,7 +12562,7 @@ thumb_output_function_prologue (f, size) ARM_HARD_FRAME_POINTER_REGNUM, work_register); } else if (live_regs_mask) - thumb_pushpop (f, live_regs_mask, 1); + thumb_pushpop (f, live_regs_mask, 1, &cfa_offset, live_regs_mask); for (regno = 8; regno < 13; regno++) if (THUMB_REG_PUSHED_P (regno)) @@ -10701,6 +12590,8 @@ thumb_output_function_prologue (f, size) while (high_regs_pushed > 0) { + int real_regs_mask = 0; + for (regno = LAST_LO_REGNUM; regno >= 0; regno--) { if (mask & (1 << regno)) @@ -10708,6 +12599,7 @@ thumb_output_function_prologue (f, size) asm_fprintf (f, "\tmov\t%r, %r\n", regno, next_hi_reg); high_regs_pushed--; + real_regs_mask |= (1 << next_hi_reg); if (high_regs_pushed) { @@ -10723,8 +12615,8 @@ thumb_output_function_prologue (f, size) } } } - - thumb_pushpop (f, mask, 1); + + thumb_pushpop (f, mask, 1, &cfa_offset, real_regs_mask); } if (pushable_regs == 0 @@ -10736,10 +12628,8 @@ thumb_output_function_prologue (f, size) /* Handle the case of a double word load into a low register from a computed memory address. The computed address may involve a register which is overwritten by the load. */ - const char * -thumb_load_double_from_address (operands) - rtx *operands; +thumb_load_double_from_address (rtx *operands) { rtx addr; rtx base; @@ -10858,11 +12748,8 @@ thumb_load_double_from_address (operands) return ""; } - const char * -thumb_output_move_mem_multiple (n, operands) - int n; - rtx * operands; +thumb_output_move_mem_multiple (int n, rtx *operands) { rtx tmp; @@ -10911,10 +12798,8 @@ thumb_output_move_mem_multiple (n, operands) } /* Routines for generating rtl. */ - void -thumb_expand_movstrqi (operands) - rtx * operands; +thumb_expand_movstrqi (rtx *operands) { rtx out = copy_to_mode_reg (SImode, XEXP (operands[0], 0)); rtx in = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); @@ -10964,70 +12849,58 @@ thumb_expand_movstrqi (operands) } int -thumb_cmp_operand (op, mode) - rtx op; - enum machine_mode mode; +thumb_cmp_operand (rtx op, enum machine_mode mode) { return ((GET_CODE (op) == CONST_INT - && (unsigned HOST_WIDE_INT) (INTVAL (op)) < 256) - || register_operand (op, mode)); + && INTVAL (op) < 256 + && INTVAL (op) >= 0) + || s_register_operand (op, mode)); } -static const char * -thumb_condition_code (x, invert) - rtx x; - int invert; +int +thumb_cmpneg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) { - static const char * const conds[] = - { - "eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", - "hi", "ls", "ge", "lt", "gt", "le" - }; - int val; + return (GET_CODE (op) == CONST_INT + && INTVAL (op) < 0 + && INTVAL (op) > -256); +} - switch (GET_CODE (x)) - { - case EQ: val = 0; break; - case NE: val = 1; break; - case GEU: val = 2; break; - case LTU: val = 3; break; - case GTU: val = 8; break; - case LEU: val = 9; break; - case GE: val = 10; break; - case LT: val = 11; break; - case GT: val = 12; break; - case LE: val = 13; break; - default: - abort (); - } +/* Return TRUE if a result can be stored in OP without clobbering the + condition code register. Prior to reload we only accept a + register. After reload we have to be able to handle memory as + well, since a pseudo may not get a hard reg and reload cannot + handle output-reloads on jump insns. + + We could possibly handle mem before reload as well, but that might + complicate things with the need to handle increment + side-effects. */ - return conds[val ^ invert]; +int +thumb_cbrch_target_operand (rtx op, enum machine_mode mode) +{ + return (s_register_operand (op, mode) + || ((reload_in_progress || reload_completed) + && memory_operand (op, mode))); } /* Handle storing a half-word to memory during reload. */ - void -thumb_reload_out_hi (operands) - rtx * operands; +thumb_reload_out_hi (rtx *operands) { emit_insn (gen_thumb_movhi_clobber (operands[0], operands[1], operands[2])); } -/* Handle storing a half-word to memory during reload. */ - +/* Handle reading a half-word from memory during reload. */ void -thumb_reload_in_hi (operands) - rtx * operands ATTRIBUTE_UNUSED; +thumb_reload_in_hi (rtx *operands ATTRIBUTE_UNUSED) { abort (); } /* Return the length of a function name prefix that starts with the character 'c'. */ - static int -arm_get_strip_length (c) - int c; +arm_get_strip_length (int c) { switch (c) { @@ -11038,10 +12911,8 @@ arm_get_strip_length (c) /* Return a pointer to a function's name with any and all prefix encodings stripped from it. */ - const char * -arm_strip_name_encoding (name) - const char * name; +arm_strip_name_encoding (const char *name) { int skip; @@ -11054,11 +12925,8 @@ arm_strip_name_encoding (name) /* If there is a '*' anywhere in the name's prefix, then emit the stripped name verbatim, otherwise prepend an underscore if leading underscores are being used. */ - void -arm_asm_output_labelref (stream, name) - FILE * stream; - const char * name; +arm_asm_output_labelref (FILE *stream, const char *name) { int skip; int verbatim = 0; @@ -11089,8 +12957,7 @@ struct pic_chain static struct pic_chain * aof_pic_chain = NULL; rtx -aof_pic_entry (x) - rtx x; +aof_pic_entry (rtx x) { struct pic_chain ** chainp; int offset; @@ -11112,8 +12979,7 @@ aof_pic_entry (x) } void -aof_dump_pic_table (f) - FILE * f; +aof_dump_pic_table (FILE *f) { struct pic_chain * chain; @@ -11136,7 +13002,7 @@ aof_dump_pic_table (f) int arm_text_section_count = 1; char * -aof_text_section () +aof_text_section (void ) { static char buf[100]; sprintf (buf, "\tAREA |C$$code%d|, CODE, READONLY", @@ -11149,7 +13015,7 @@ aof_text_section () static int arm_data_section_count = 1; char * -aof_data_section () +aof_data_section (void) { static char buf[100]; sprintf (buf, "\tAREA |C$$data%d|, DATA", arm_data_section_count++); @@ -11175,8 +13041,7 @@ struct import static struct import * imports_list = NULL; void -aof_add_import (name) - const char * name; +aof_add_import (const char *name) { struct import * new; @@ -11191,8 +13056,7 @@ aof_add_import (name) } void -aof_delete_import (name) - const char * name; +aof_delete_import (const char *name) { struct import ** old; @@ -11208,9 +13072,8 @@ aof_delete_import (name) int arm_main_function = 0; -void -aof_dump_imports (f) - FILE * f; +static void +aof_dump_imports (FILE *f) { /* The AOF assembler needs this to cause the startup code to be extracted from the library. Brining in __main causes the whole thing to work @@ -11233,14 +13096,52 @@ aof_dump_imports (f) } static void -aof_globalize_label (stream, name) - FILE *stream; - const char *name; +aof_globalize_label (FILE *stream, const char *name) { default_globalize_label (stream, name); if (! strcmp (name, "main")) arm_main_function = 1; } + +static void +aof_file_start (void) +{ + fputs ("__r0\tRN\t0\n", asm_out_file); + fputs ("__a1\tRN\t0\n", asm_out_file); + fputs ("__a2\tRN\t1\n", asm_out_file); + fputs ("__a3\tRN\t2\n", asm_out_file); + fputs ("__a4\tRN\t3\n", asm_out_file); + fputs ("__v1\tRN\t4\n", asm_out_file); + fputs ("__v2\tRN\t5\n", asm_out_file); + fputs ("__v3\tRN\t6\n", asm_out_file); + fputs ("__v4\tRN\t7\n", asm_out_file); + fputs ("__v5\tRN\t8\n", asm_out_file); + fputs ("__v6\tRN\t9\n", asm_out_file); + fputs ("__sl\tRN\t10\n", asm_out_file); + fputs ("__fp\tRN\t11\n", asm_out_file); + fputs ("__ip\tRN\t12\n", asm_out_file); + fputs ("__sp\tRN\t13\n", asm_out_file); + fputs ("__lr\tRN\t14\n", asm_out_file); + fputs ("__pc\tRN\t15\n", asm_out_file); + fputs ("__f0\tFN\t0\n", asm_out_file); + fputs ("__f1\tFN\t1\n", asm_out_file); + fputs ("__f2\tFN\t2\n", asm_out_file); + fputs ("__f3\tFN\t3\n", asm_out_file); + fputs ("__f4\tFN\t4\n", asm_out_file); + fputs ("__f5\tFN\t5\n", asm_out_file); + fputs ("__f6\tFN\t6\n", asm_out_file); + fputs ("__f7\tFN\t7\n", asm_out_file); + text_section (); +} + +static void +aof_file_end (void) +{ + if (flag_pic) + aof_dump_pic_table (asm_out_file); + aof_dump_imports (asm_out_file); + fputs ("\tEND\n", asm_out_file); +} #endif /* AOF_ASSEMBLER */ #ifdef OBJECT_FORMAT_ELF @@ -11252,9 +13153,7 @@ aof_globalize_label (stream, name) used before the section type. */ static void -arm_elf_asm_named_section (name, flags) - const char *name; - unsigned int flags; +arm_elf_asm_named_section (const char *name, unsigned int flags) { char flagchars[10], *f = flagchars; @@ -11309,20 +13208,14 @@ arm_elf_asm_named_section (name, flags) simplification. */ static void -arm_encode_section_info (decl, first) - tree decl; - int first; +arm_encode_section_info (tree decl, rtx rtl, int first) { /* This doesn't work with AOF syntax, since the string table may be in a different AREA. */ #ifndef AOF_ASSEMBLER if (optimize > 0 && TREE_CONSTANT (decl) && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) - { - rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' - ? TREE_CST_RTL (decl) : DECL_RTL (decl)); - SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; - } + SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; #endif /* If we are referencing a function that is weak then encode a long call @@ -11338,24 +13231,43 @@ arm_encode_section_info (decl, first) } #endif /* !ARM_PE */ +static void +arm_internal_label (FILE *stream, const char *prefix, unsigned long labelno) +{ + if (arm_ccfsm_state == 3 && (unsigned) arm_target_label == labelno + && !strcmp (prefix, "L")) + { + arm_ccfsm_state = 0; + arm_target_insn = NULL; + } + default_internal_label (stream, prefix, labelno); +} + /* Output code to add DELTA to the first argument, and then jump to FUNCTION. Used for C++ multiple inheritance. */ - static void -arm_output_mi_thunk (file, thunk, delta, vcall_offset, function) - FILE *file; - tree thunk ATTRIBUTE_UNUSED; - HOST_WIDE_INT delta; - HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED; - tree function; +arm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, + HOST_WIDE_INT delta, + HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, + tree function) { + static int thunk_label = 0; + char label[256]; int mi_delta = delta; const char *const mi_op = mi_delta < 0 ? "sub" : "add"; int shift = 0; - int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function))) + int this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function) ? 1 : 0); if (mi_delta < 0) mi_delta = - mi_delta; + if (TARGET_THUMB) + { + int labelno = thunk_label++; + ASM_GENERATE_INTERNAL_LABEL (label, "LTHUMBFUNC", labelno); + fputs ("\tldr\tr12, ", file); + assemble_name (file, label); + fputc ('\n', file); + } while (mi_delta != 0) { if ((mi_delta & (3 << shift)) == 0) @@ -11369,10 +13281,78 @@ arm_output_mi_thunk (file, thunk, delta, vcall_offset, function) shift += 8; } } - fputs ("\tb\t", file); - assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); - if (NEED_PLT_RELOC) - fputs ("(PLT)", file); - fputc ('\n', file); + if (TARGET_THUMB) + { + fprintf (file, "\tbx\tr12\n"); + ASM_OUTPUT_ALIGN (file, 2); + assemble_name (file, label); + fputs (":\n", file); + assemble_integer (XEXP (DECL_RTL (function), 0), 4, BITS_PER_WORD, 1); + } + else + { + fputs ("\tb\t", file); + assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); + if (NEED_PLT_RELOC) + fputs ("(PLT)", file); + fputc ('\n', file); + } +} + +int +arm_emit_vector_const (FILE *file, rtx x) +{ + int i; + const char * pattern; + + if (GET_CODE (x) != CONST_VECTOR) + abort (); + + switch (GET_MODE (x)) + { + case V2SImode: pattern = "%08x"; break; + case V4HImode: pattern = "%04x"; break; + case V8QImode: pattern = "%02x"; break; + default: abort (); + } + + fprintf (file, "0x"); + for (i = CONST_VECTOR_NUNITS (x); i--;) + { + rtx element; + + element = CONST_VECTOR_ELT (x, i); + fprintf (file, pattern, INTVAL (element)); + } + + return 1; } +const char * +arm_output_load_gr (rtx *operands) +{ + rtx reg; + rtx offset; + rtx wcgr; + rtx sum; + + if (GET_CODE (operands [1]) != MEM + || GET_CODE (sum = XEXP (operands [1], 0)) != PLUS + || GET_CODE (reg = XEXP (sum, 0)) != REG + || GET_CODE (offset = XEXP (sum, 1)) != CONST_INT + || ((INTVAL (offset) < 1024) && (INTVAL (offset) > -1024))) + return "wldrw%?\t%0, %1"; + + /* Fix up an out-of-range load of a GR register. */ + output_asm_insn ("str%?\t%0, [sp, #-4]!\t@ Start of GR load expansion", & reg); + wcgr = operands[0]; + operands[0] = reg; + output_asm_insn ("ldr%?\t%0, %1", operands); + + operands[0] = wcgr; + operands[1] = reg; + output_asm_insn ("tmcr%?\t%0, %1", operands); + output_asm_insn ("ldr%?\t%0, [sp], #4\t@ End of GR load expansion", & reg); + + return ""; +} diff --git a/contrib/gcc/config/arm/arm.h b/contrib/gcc/config/arm/arm.h index eda2d47..3a13d91 100644 --- a/contrib/gcc/config/arm/arm.h +++ b/contrib/gcc/config/arm/arm.h @@ -1,27 +1,27 @@ /* Definitions of target machine for GNU compiler, for ARM. Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, - 2001, 2002 Free Software Foundation, Inc. + 2001, 2002, 2003, 2004 Free Software Foundation, Inc. Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) and Martin Simmons (@harleqn.co.uk). More major hacks by Richard Earnshaw (rearnsha@arm.com) Minor hacks by Nick Clifton (nickc@cygnus.com) -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, Boston, + MA 02111-1307, USA. */ #ifndef GCC_ARM_H #define GCC_ARM_H @@ -96,6 +96,12 @@ Boston, MA 02111-1307, USA. */ #define TARGET_CPU_arm9 0x0080 #define TARGET_CPU_arm9tdmi 0x0080 #define TARGET_CPU_xscale 0x0100 +#define TARGET_CPU_ep9312 0x0200 +#define TARGET_CPU_iwmmxt 0x0400 +#define TARGET_CPU_arm926ej_s 0x0800 +#define TARGET_CPU_arm1026ej_s 0x1000 +#define TARGET_CPU_arm1136j_s 0x2000 +#define TARGET_CPU_arm1136jf_s 0x4000 /* Configure didn't specify. */ #define TARGET_CPU_generic 0x8000 @@ -124,12 +130,12 @@ extern GTY(()) rtx arm_compare_op1; /* The label of the current constant pool. */ extern rtx pool_vector_label; /* Set to 1 when a return insn is output, this means that the epilogue - is not needed. */ + is not needed. */ extern int return_used_this_function; /* Used to produce AOF syntax assembler. */ extern GTY(()) rtx aof_pic_label; -/* Just in case configure has failed to define anything. */ +/* Just in case configure has failed to define anything. */ #ifndef TARGET_CPU_DEFAULT #define TARGET_CPU_DEFAULT TARGET_CPU_generic #endif @@ -164,7 +170,21 @@ extern GTY(()) rtx aof_pic_label; #if TARGET_CPU_DEFAULT == TARGET_CPU_xscale #define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__" #else -Unrecognized value in TARGET_CPU_DEFAULT. +#if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312 +#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_4T__ -D__MAVERICK__" +/* Set TARGET_DEFAULT to the default, but without soft-float. */ +#ifdef TARGET_DEFAULT +#undef TARGET_DEFAULT +#define TARGET_DEFAULT \ + (ARM_FLAG_APCS_32 | ARM_FLAG_MMU_TRAPS | ARM_FLAG_APCS_FRAME) +#endif +#else +#if TARGET_CPU_DEFAULT == TARGET_CPU_iwmmxt +#define CPP_ARCH_DEFAULT_SPEC "-D__ARM_ARCH_5TE__ -D__XSCALE__ -D__IWMMXT__" +#else +#error Unrecognized value in TARGET_CPU_DEFAULT. +#endif +#endif #endif #endif #endif @@ -212,6 +232,8 @@ Unrecognized value in TARGET_CPU_DEFAULT. %{march=strongarm1100:-D__ARM_ARCH_4__} \ %{march=xscale:-D__ARM_ARCH_5TE__} \ %{march=xscale:-D__XSCALE__} \ +%{march=ep9312:-D__ARM_ARCH_4T__} \ +%{march=ep9312:-D__MAVERICK__} \ %{march=armv2:-D__ARM_ARCH_2__} \ %{march=armv2a:-D__ARM_ARCH_2__} \ %{march=armv3:-D__ARM_ARCH_3__} \ @@ -251,6 +273,11 @@ Unrecognized value in TARGET_CPU_DEFAULT. %{mcpu=strongarm1100:-D__ARM_ARCH_4__} \ %{mcpu=xscale:-D__ARM_ARCH_5TE__} \ %{mcpu=xscale:-D__XSCALE__} \ + %{mcpu=ep9312:-D__ARM_ARCH_4T__} \ + %{mcpu=ep9312:-D__MAVERICK__} \ + %{mcpu=iwmmxt:-D__ARM_ARCH_5TE__} \ + %{mcpu=iwmmxt:-D__XSCALE__} \ + %{mcpu=iwmmxt:-D__IWMMXT__} \ %{!mcpu*:%(cpp_cpu_arch_default)}} \ " @@ -263,7 +290,7 @@ Unrecognized value in TARGET_CPU_DEFAULT. is an initializer with a subgrouping for each command option. Each subgrouping contains a string constant, that defines the - specification name, and a string constant that used by the GNU CC driver + specification name, and a string constant that used by the GCC driver program. Do not define this macro if it does not need to do anything. */ @@ -345,7 +372,7 @@ Unrecognized value in TARGET_CPU_DEFAULT. function tries to return. */ #define ARM_FLAG_ABORT_NORETURN (1 << 13) -/* Nonzero if function prologues should not load the PIC register. */ +/* Nonzero if function prologues should not load the PIC register. */ #define ARM_FLAG_SINGLE_PIC_BASE (1 << 14) /* Nonzero if all call instructions should be indirect. */ @@ -376,6 +403,9 @@ Unrecognized value in TARGET_CPU_DEFAULT. /* Nonzero means to use ARM/Thumb Procedure Call Standard conventions. */ #define ARM_FLAG_ATPCS (1 << 22) +/* Fix invalid Cirrus instruction combinations by inserting NOPs. */ +#define CIRRUS_FIX_INVALID_INSNS (1 << 23) + #define TARGET_APCS_FRAME (target_flags & ARM_FLAG_APCS_FRAME) #define TARGET_POKE_FUNCTION_NAME (target_flags & ARM_FLAG_POKE) #define TARGET_FPE (target_flags & ARM_FLAG_FPE) @@ -387,6 +417,10 @@ Unrecognized value in TARGET_CPU_DEFAULT. #define TARGET_MMU_TRAPS (target_flags & ARM_FLAG_MMU_TRAPS) #define TARGET_SOFT_FLOAT (target_flags & ARM_FLAG_SOFT_FLOAT) #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT) +#define TARGET_CIRRUS (arm_is_cirrus) +#define TARGET_ANY_HARD_FLOAT (TARGET_HARD_FLOAT || TARGET_CIRRUS) +#define TARGET_IWMMXT (arm_arch_iwmmxt) +#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_ARM) #define TARGET_VFP (target_flags & ARM_FLAG_VFP) #define TARGET_BIG_END (target_flags & ARM_FLAG_BIG_END) #define TARGET_INTERWORK (target_flags & ARM_FLAG_INTERWORK) @@ -403,6 +437,7 @@ Unrecognized value in TARGET_CPU_DEFAULT. #define TARGET_BACKTRACE (leaf_function_p () \ ? (target_flags & THUMB_FLAG_LEAF_BACKTRACE) \ : (target_flags & THUMB_FLAG_BACKTRACE)) +#define TARGET_CIRRUS_FIX_INVALID_INSNS (target_flags & CIRRUS_FIX_INVALID_INSNS) /* SUBTARGET_SWITCHES is used to add flags on a per-config basis. */ #ifndef SUBTARGET_SWITCHES @@ -421,8 +456,7 @@ Unrecognized value in TARGET_CPU_DEFAULT. {"fpe", ARM_FLAG_FPE, "" }, \ {"apcs-32", ARM_FLAG_APCS_32, \ N_("Use the 32-bit version of the APCS") }, \ - {"apcs-26", -ARM_FLAG_APCS_32, \ - N_("Use the 26-bit version of the APCS") }, \ + {"apcs-26", -ARM_FLAG_APCS_32, ""}, \ {"apcs-stack-check", ARM_FLAG_APCS_STACK, "" }, \ {"no-apcs-stack-check", -ARM_FLAG_APCS_STACK, "" }, \ {"apcs-float", ARM_FLAG_APCS_FLOAT, \ @@ -434,10 +468,6 @@ Unrecognized value in TARGET_CPU_DEFAULT. {"alignment-traps", ARM_FLAG_MMU_TRAPS, \ N_("The MMU will trap on unaligned accesses") }, \ {"no-alignment-traps", -ARM_FLAG_MMU_TRAPS, "" }, \ - {"short-load-bytes", ARM_FLAG_MMU_TRAPS, "" }, \ - {"no-short-load-bytes", -ARM_FLAG_MMU_TRAPS, "" }, \ - {"short-load-words", -ARM_FLAG_MMU_TRAPS, "" }, \ - {"no-short-load-words", ARM_FLAG_MMU_TRAPS, "" }, \ {"soft-float", ARM_FLAG_SOFT_FLOAT, \ N_("Use library calls to perform FP operations") }, \ {"hard-float", -ARM_FLAG_SOFT_FLOAT, \ @@ -481,6 +511,10 @@ Unrecognized value in TARGET_CPU_DEFAULT. N_("Thumb: Assume function pointers may go to non-Thumb aware code") }, \ {"no-caller-super-interworking", -THUMB_FLAG_CALLER_SUPER_INTERWORKING, \ "" }, \ + {"cirrus-fix-invalid-insns", CIRRUS_FIX_INVALID_INSNS, \ + N_("Cirrus: Place NOPs to avoid invalid instruction combinations") }, \ + {"no-cirrus-fix-invalid-insns", -CIRRUS_FIX_INVALID_INSNS, \ + N_("Cirrus: Do not break up invalid instruction combinations with NOPs") },\ SUBTARGET_SWITCHES \ {"", TARGET_DEFAULT, "" } \ } @@ -488,19 +522,33 @@ Unrecognized value in TARGET_CPU_DEFAULT. #define TARGET_OPTIONS \ { \ {"cpu=", & arm_select[0].string, \ - N_("Specify the name of the target CPU") }, \ + N_("Specify the name of the target CPU"), 0}, \ {"arch=", & arm_select[1].string, \ - N_("Specify the name of the target architecture") }, \ - {"tune=", & arm_select[2].string, "" }, \ - {"fpe=", & target_fp_name, "" }, \ + N_("Specify the name of the target architecture"), 0}, \ + {"tune=", & arm_select[2].string, "", 0}, \ + {"fpe=", & target_fp_name, "" , 0}, \ {"fp=", & target_fp_name, \ - N_("Specify the version of the floating point emulator") }, \ + N_("Specify the version of the floating point emulator"), 0},\ {"structure-size-boundary=", & structure_size_string, \ - N_("Specify the minimum bit alignment of structures") }, \ + N_("Specify the minimum bit alignment of structures"), 0}, \ {"pic-register=", & arm_pic_register_string, \ - N_("Specify the register to be used for PIC addressing") } \ + N_("Specify the register to be used for PIC addressing"), 0} \ } +/* Support for a compile-time default CPU, et cetera. The rules are: + --with-arch is ignored if -march or -mcpu are specified. + --with-cpu is ignored if -march or -mcpu are specified, and is overridden + by --with-arch. + --with-tune is ignored if -mtune or -mcpu are specified (but not affected + by -march). + --with-float is ignored if -mhard-float or -msoft-float are + specified. */ +#define OPTION_DEFAULT_SPECS \ + {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ + {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ + {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ + {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" } + struct arm_cpu_select { const char * string; @@ -519,33 +567,45 @@ enum prog_mode_type prog_mode32 }; -/* Recast the program mode class to be the prog_mode attribute */ +/* Recast the program mode class to be the prog_mode attribute. */ #define arm_prog_mode ((enum attr_prog_mode) arm_prgmode) extern enum prog_mode_type arm_prgmode; /* What sort of floating point unit do we have? Hardware or software. If software, is it issue 2 or issue 3? */ -enum floating_point_type +enum fputype { - FP_HARD, - FP_SOFT2, - FP_SOFT3 + /* Software floating point, FPA style double fmt. */ + FPUTYPE_SOFT_FPA, + /* Full FPA support. */ + FPUTYPE_FPA, + /* Emulated FPA hardware, Issue 2 emulator (no LFM/SFM). */ + FPUTYPE_FPA_EMU2, + /* Emulated FPA hardware, Issue 3 emulator. */ + FPUTYPE_FPA_EMU3, + /* Cirrus Maverick floating point co-processor. */ + FPUTYPE_MAVERICK }; /* Recast the floating point class to be the floating point attribute. */ -#define arm_fpu_attr ((enum attr_fpu) arm_fpu) +#define arm_fpu_attr ((enum attr_fpu) arm_fpu_tune) /* What type of floating point to tune for */ -extern enum floating_point_type arm_fpu; +extern enum fputype arm_fpu_tune; /* What type of floating point instructions are available */ -extern enum floating_point_type arm_fpu_arch; +extern enum fputype arm_fpu_arch; /* Default floating point architecture. Override in sub-target if necessary. */ -#ifndef FP_DEFAULT -#define FP_DEFAULT FP_SOFT2 +#ifndef FPUTYPE_DEFAULT +#define FPUTYPE_DEFAULT FPUTYPE_FPA_EMU2 +#endif + +#if TARGET_CPU_DEFAULT == TARGET_CPU_ep9312 +#undef FPUTYPE_DEFAULT +#define FPUTYPE_DEFAULT FPUTYPE_MAVERICK #endif /* Nonzero if the processor has a fast multiply insn, and one that does @@ -570,14 +630,23 @@ extern int thumb_code; /* Nonzero if this chip is a StrongARM. */ extern int arm_is_strong; +/* Nonzero if this chip is a Cirrus variant. */ +extern int arm_is_cirrus; + +/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ +extern int arm_arch_iwmmxt; + /* Nonzero if this chip is an XScale. */ -extern int arm_is_xscale; +extern int arm_arch_xscale; + +/* Nonzero if tuning for XScale */ +extern int arm_tune_xscale; /* Nonzero if this chip is an ARM6 or an ARM7. */ extern int arm_is_6_or_7; #ifndef TARGET_DEFAULT -#define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME) +#define TARGET_DEFAULT (ARM_FLAG_APCS_FRAME | ARM_FLAG_MMU_TRAPS) #endif /* The frame pointer register used in gcc has nothing to do with debugging; @@ -641,20 +710,6 @@ extern int arm_is_6_or_7; /* This is required to ensure that push insns always push a word. */ #define PROMOTE_FUNCTION_ARGS -/* For the ARM: - I think I have added all the code to make this work. Unfortunately, - early releases of the floating point emulation code on RISCiX used a - different format for extended precision numbers. On my RISCiX box there - is a bug somewhere which causes the machine to lock up when running enquire - with long doubles. There is the additional aspect that Norcroft C - treats long doubles as doubles and we ought to remain compatible. - Perhaps someone with an FPA coprocessor and not running RISCiX would like - to try this someday. */ -/* #define LONG_DOUBLE_TYPE_SIZE 96 */ - -/* Disable XFmode patterns in md file */ -#define ENABLE_XF_PATTERNS 0 - /* Define this if most significant bit is lowest numbered in instructions that operate on numbered bit-fields. */ #define BITS_BIG_ENDIAN 0 @@ -679,14 +734,16 @@ extern int arm_is_6_or_7; #endif /* Define this if most significant word of doubles is the lowest numbered. - The rules are different based on whether or not we use FPA-format or - VFP-format doubles. */ + The rules are different based on whether or not we use FPA-format, + VFP-format or some other floating point co-processor's format doubles. */ #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ()) #define UNITS_PER_WORD 4 #define PARM_BOUNDARY 32 +#define IWMMXT_ALIGNMENT 64 + #define STACK_BOUNDARY 32 #define PREFERRED_STACK_BOUNDARY (TARGET_ATPCS ? 64 : 32) @@ -700,13 +757,53 @@ extern int arm_is_6_or_7; #define EMPTY_FIELD_BOUNDARY 32 -#define BIGGEST_ALIGNMENT 32 +#define BIGGEST_ALIGNMENT (TARGET_REALLY_IWMMXT ? 64 : 32) + +#define TYPE_NEEDS_IWMMXT_ALIGNMENT(TYPE) \ + (TARGET_REALLY_IWMMXT \ + && ((TREE_CODE (TYPE) == VECTOR_TYPE) || (TYPE_MODE (TYPE) == DImode) || (TYPE_MODE (TYPE) == DFmode))) + +/* XXX Blah -- this macro is used directly by libobjc. Since it + supports no vector modes, cut out the complexity and fall back + on BIGGEST_FIELD_ALIGNMENT. */ +#ifdef IN_TARGET_LIBS +#define BIGGEST_FIELD_ALIGNMENT 64 +#else +/* An expression for the alignment of a structure field FIELD if the + alignment computed in the usual way is COMPUTED. GCC uses this + value instead of the value in `BIGGEST_ALIGNMENT' or + `BIGGEST_FIELD_ALIGNMENT', if defined, for structure fields only. */ +#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ + (TYPE_NEEDS_IWMMXT_ALIGNMENT (TREE_TYPE (FIELD)) \ + ? IWMMXT_ALIGNMENT \ + : (COMPUTED)) +#endif + +/* If defined, a C expression to compute the alignment for a static variable. + TYPE is the data type, and ALIGN is the alignment that the object + would ordinarily have. The value of this macro is used instead of that + alignment to align the object. + + If this macro is not defined, then ALIGN is used. */ +#define DATA_ALIGNMENT(TYPE, ALIGN) \ + (TYPE_NEEDS_IWMMXT_ALIGNMENT (TYPE) ? IWMMXT_ALIGNMENT : ALIGN) + +/* If defined, a C expression to compute the alignment for a + variables in the local store. TYPE is the data type, and + BASIC-ALIGN is the alignment that the object would ordinarily + have. The value of this macro is used instead of that alignment + to align the object. + + If this macro is not defined, then BASIC-ALIGN is used. */ +#define LOCAL_ALIGNMENT(TYPE, ALIGN) \ + (TYPE_NEEDS_IWMMXT_ALIGNMENT (TYPE) ? IWMMXT_ALIGNMENT : ALIGN) /* Make strings word-aligned so strcpy from constants will be faster. */ -#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_is_xscale ? 1 : 2) +#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2) #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ - ((TREE_CODE (EXP) == STRING_CST \ + ((TARGET_REALLY_IWMMXT && TREE_CODE (EXP) == VECTOR_TYPE) ? IWMMXT_ALIGNMENT : \ + (TREE_CODE (EXP) == STRING_CST \ && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) @@ -721,7 +818,7 @@ extern int arm_structure_size_boundary; /* This is the value used to initialize arm_structure_size_boundary. If a particular arm target wants to change the default value it should change - the definition of this macro, not STRUCTRUE_SIZE_BOUNDARY. See netbsd.h + the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h for an example of this. */ #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 @@ -770,6 +867,11 @@ extern const char * structure_size_string; *: See CONDITIONAL_REGISTER_USAGE */ +/* + mvf0 Cirrus floating point result + mvf1-mvf3 Cirrus floating point scratch + mvf4-mvf15 S Cirrus floating point variable. */ + /* The stack backtrace structure is as follows: fp points to here: | save code pointer | [fp] | return link value | [fp, #-4] @@ -799,7 +901,12 @@ extern const char * structure_size_string; 0,0,0,0,0,0,0,0, \ 0,0,0,0,0,1,0,1, \ 0,0,0,0,0,0,0,0, \ - 1,1,1 \ + 1,1,1, \ + 1,1,1,1,1,1,1,1, \ + 1,1,1,1,1,1,1,1, \ + 1,1,1,1,1,1,1,1, \ + 1,1,1,1,1,1,1,1, \ + 1,1,1,1 \ } /* 1 for registers not available across function calls. @@ -809,13 +916,18 @@ extern const char * structure_size_string; and the register where structure-value addresses are passed. Aside from that, you can include as many other registers as you like. The CC is not preserved over function calls on the ARM 6, so it is - easier to assume this for all. SFP is preserved, since FP is. */ + easier to assume this for all. SFP is preserved, since FP is. */ #define CALL_USED_REGISTERS \ { \ 1,1,1,1,0,0,0,0, \ 0,0,0,0,1,1,1,1, \ 1,1,1,1,0,0,0,0, \ - 1,1,1 \ + 1,1,1, \ + 1,1,1,1,1,1,1,1, \ + 1,1,1,1,1,1,1,1, \ + 1,1,1,1,1,1,1,1, \ + 1,1,1,1,1,1,1,1, \ + 1,1,1,1 \ } #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE @@ -832,7 +944,57 @@ extern const char * structure_size_string; regno <= LAST_ARM_FP_REGNUM; ++regno) \ fixed_regs[regno] = call_used_regs[regno] = 1; \ } \ - if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ + \ + if (TARGET_THUMB && optimize_size) \ + { \ + /* When optimizing for size, it's better not to use \ + the HI regs, because of the overhead of stacking \ + them. */ \ + for (regno = FIRST_HI_REGNUM; \ + regno <= LAST_HI_REGNUM; ++regno) \ + fixed_regs[regno] = call_used_regs[regno] = 1; \ + } \ + \ + /* The link register can be clobbered by any branch insn, \ + but we have no way to track that at present, so mark \ + it as unavailable. */ \ + if (TARGET_THUMB) \ + fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \ + \ + if (TARGET_CIRRUS) \ + { \ + for (regno = FIRST_ARM_FP_REGNUM; \ + regno <= LAST_ARM_FP_REGNUM; ++ regno) \ + fixed_regs[regno] = call_used_regs[regno] = 1; \ + for (regno = FIRST_CIRRUS_FP_REGNUM; \ + regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \ + { \ + fixed_regs[regno] = 0; \ + call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \ + } \ + } \ + \ + if (TARGET_REALLY_IWMMXT) \ + { \ + regno = FIRST_IWMMXT_GR_REGNUM; \ + /* The 2002/10/09 revision of the XScale ABI has wCG0 \ + and wCG1 as call-preserved registers. The 2002/11/21 \ + revision changed this so that all wCG registers are \ + scratch registers. */ \ + for (regno = FIRST_IWMMXT_GR_REGNUM; \ + regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \ + fixed_regs[regno] = call_used_regs[regno] = 0; \ + /* The XScale ABI has wR0 - wR9 as scratch registers, \ + the rest as call-preserved registers. */ \ + for (regno = FIRST_IWMMXT_REGNUM; \ + regno <= LAST_IWMMXT_REGNUM; ++ regno) \ + { \ + fixed_regs[regno] = 0; \ + call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \ + } \ + } \ + \ + if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ { \ fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ @@ -850,7 +1012,7 @@ extern const char * structure_size_string; SUBTARGET_CONDITIONAL_REGISTER_USAGE \ } -/* These are a couple of extensions to the formats accecpted +/* These are a couple of extensions to the formats accepted by asm_fprintf: %@ prints out ASM_COMMENT_START %r prints out REGISTER_PREFIX reg_names[arg] */ @@ -865,7 +1027,7 @@ extern const char * structure_size_string; break; /* Round X up to the nearest word. */ -#define ROUND_UP(X) (((X) + 3) & ~3) +#define ROUND_UP_WORD(X) (((X) + 3) & ~3) /* Convert fron bytes to ints. */ #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) @@ -882,7 +1044,7 @@ extern const char * structure_size_string; /* The number of (integer) argument register available. */ #define NUM_ARG_REGS 4 -/* Return the regiser number of the N'th (integer) argument. */ +/* Return the register number of the N'th (integer) argument. */ #define ARG_REGISTER(N) (N - 1) #if 0 /* FIXME: The ARM backend has special code to handle structure @@ -905,8 +1067,11 @@ extern const char * structure_size_string; /* The number of the last argument register. */ #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) -/* The number of the last "lo" register (thumb). */ +/* The numbers of the Thumb register ranges. */ +#define FIRST_LO_REGNUM 0 #define LAST_LO_REGNUM 7 +#define FIRST_HI_REGNUM 8 +#define LAST_HI_REGNUM 11 /* The register that holds the return address in exception handlers. */ #define EXCEPTION_LR_REGNUM 2 @@ -922,7 +1087,7 @@ extern const char * structure_size_string; should point to a special register that we will make sure is eliminated. For the Thumb we have another problem. The TPCS defines the frame pointer - as r11, and GCC belives that it is always possible to use the frame pointer + as r11, and GCC believes that it is always possible to use the frame pointer as base register for addressing purposes. (See comments in find_reloads_address()). But - the Thumb does not allow high registers, including r11, to be used as base address registers. Hence our problem. @@ -930,7 +1095,7 @@ extern const char * structure_size_string; The solution used here, and in the old thumb port is to use r7 instead of r11 as the hard frame pointer and to have special code to generate backtrace structures on the stack (if required to do so via a command line - option) using r11. This is the only 'user visable' use of r11 as a frame + option) using r11. This is the only 'user visible' use of r11 as a frame pointer. */ #define ARM_HARD_FRAME_POINTER_REGNUM 11 #define THUMB_HARD_FRAME_POINTER_REGNUM 7 @@ -949,14 +1114,30 @@ extern const char * structure_size_string; #define FIRST_ARM_FP_REGNUM 16 #define LAST_ARM_FP_REGNUM 23 +#define FIRST_IWMMXT_GR_REGNUM 43 +#define LAST_IWMMXT_GR_REGNUM 46 +#define FIRST_IWMMXT_REGNUM 47 +#define LAST_IWMMXT_REGNUM 62 +#define IS_IWMMXT_REGNUM(REGNUM) \ + (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) +#define IS_IWMMXT_GR_REGNUM(REGNUM) \ + (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) + /* Base register for access to local variables of the function. */ #define FRAME_POINTER_REGNUM 25 /* Base register for access to arguments of the function. */ #define ARG_POINTER_REGNUM 26 -/* The number of hard registers is 16 ARM + 8 FPU + 1 CC + 1 SFP. */ -#define FIRST_PSEUDO_REGISTER 27 +#define FIRST_CIRRUS_FP_REGNUM 27 +#define LAST_CIRRUS_FP_REGNUM 42 +#define IS_CIRRUS_REGNUM(REGNUM) \ + (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM)) + +/* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */ +/* + 16 Cirrus registers take us up to 43. */ +/* Intel Wireless MMX Technology registers add 16 + 4 more. */ +#define FIRST_PSEUDO_REGISTER 63 /* Value should be nonzero if functions must have frame pointers. Zero means the frame pointer need not be set up (and parms may be accessed @@ -973,7 +1154,7 @@ extern const char * structure_size_string; This is ordinarily the length in words of a value of mode MODE but can be less for certain modes in special long registers. - On the ARM regs are UNITS_PER_WORD bits wide; FPU regs can hold any FP + On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP mode. */ #define HARD_REGNO_NREGS(REGNO, MODE) \ ((TARGET_ARM \ @@ -993,6 +1174,12 @@ extern const char * structure_size_string; #define MODES_TIEABLE_P(MODE1, MODE2) \ (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) +#define VECTOR_MODE_SUPPORTED_P(MODE) \ + ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode) + +#define VALID_IWMMXT_REG_MODE(MODE) \ + (VECTOR_MODE_SUPPORTED_P (MODE) || (MODE) == DImode) + /* The order in which register should be allocated. It is good to use ip since no saving is required (though calls clobber it) and it never contains function parameters. It is quite good to use lr since other calls may @@ -1004,6 +1191,11 @@ extern const char * structure_size_string; 3, 2, 1, 0, 12, 14, 4, 5, \ 6, 7, 8, 10, 9, 11, 13, 15, \ 16, 17, 18, 19, 20, 21, 22, 23, \ + 27, 28, 29, 30, 31, 32, 33, 34, \ + 35, 36, 37, 38, 39, 40, 41, 42, \ + 43, 44, 45, 46, 47, 48, 49, 50, \ + 51, 52, 53, 54, 55, 56, 57, 58, \ + 59, 60, 61, 62, \ 24, 25, 26 \ } @@ -1016,12 +1208,15 @@ extern const char * structure_size_string; /* Register and constant classes. */ -/* Register classes: used to be simple, just all ARM regs or all FPU regs +/* Register classes: used to be simple, just all ARM regs or all FPA regs Now that the Thumb is involved it has become more complicated. */ enum reg_class { NO_REGS, - FPU_REGS, + FPA_REGS, + CIRRUS_REGS, + IWMMXT_GR_REGS, + IWMMXT_REGS, LO_REGS, STACK_REG, BASE_REGS, @@ -1034,11 +1229,14 @@ enum reg_class #define N_REG_CLASSES (int) LIM_REG_CLASSES -/* Give names of register classes as strings for dump file. */ +/* Give names of register classes as strings for dump file. */ #define REG_CLASS_NAMES \ { \ "NO_REGS", \ - "FPU_REGS", \ + "FPA_REGS", \ + "CIRRUS_REGS", \ + "IWMMXT_GR_REGS", \ + "IWMMXT_REGS", \ "LO_REGS", \ "STACK_REG", \ "BASE_REGS", \ @@ -1053,15 +1251,18 @@ enum reg_class of length N_REG_CLASSES. */ #define REG_CLASS_CONTENTS \ { \ - { 0x0000000 }, /* NO_REGS */ \ - { 0x0FF0000 }, /* FPU_REGS */ \ - { 0x00000FF }, /* LO_REGS */ \ - { 0x0002000 }, /* STACK_REG */ \ - { 0x00020FF }, /* BASE_REGS */ \ - { 0x000FF00 }, /* HI_REGS */ \ - { 0x1000000 }, /* CC_REG */ \ - { 0x200FFFF }, /* GENERAL_REGS */ \ - { 0x2FFFFFF } /* ALL_REGS */ \ + { 0x00000000, 0x0 }, /* NO_REGS */ \ + { 0x00FF0000, 0x0 }, /* FPA_REGS */ \ + { 0xF8000000, 0x000007FF }, /* CIRRUS_REGS */ \ + { 0x00000000, 0x00007800 }, /* IWMMXT_GR_REGS */\ + { 0x00000000, 0x7FFF8000 }, /* IWMMXT_REGS */ \ + { 0x000000FF, 0x0 }, /* LO_REGS */ \ + { 0x00002000, 0x0 }, /* STACK_REG */ \ + { 0x000020FF, 0x0 }, /* BASE_REGS */ \ + { 0x0000FF00, 0x0 }, /* HI_REGS */ \ + { 0x01000000, 0x0 }, /* CC_REG */ \ + { 0x0200FFFF, 0x0 }, /* GENERAL_REGS */\ + { 0xFAFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \ } /* The same information, inverted: @@ -1070,12 +1271,18 @@ enum reg_class or could index an array. */ #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) +/* FPA registers can't do dubreg as all values are reformatted to internal + precision. */ +#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ + (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ + ? reg_classes_intersect_p (FPA_REGS, (CLASS)) : 0) + /* The class value for index registers, and the one for base regs. */ #define INDEX_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS) #define BASE_REG_CLASS (TARGET_THUMB ? LO_REGS : GENERAL_REGS) /* For the Thumb the high registers cannot be used as base registers - when addressing quanitities in QI or HI mode; if we don't know the + when addressing quantities in QI or HI mode; if we don't know the mode, then we must be conservative. After reload we must also be conservative, since we can't support SP+reg addressing, and we can't fix up any bad substitutions. */ @@ -1086,14 +1293,17 @@ enum reg_class /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows registers explicitly used in the rtl to be used as spill registers but prevents the compiler from extending the lifetime of these - registers. */ + registers. */ #define SMALL_REGISTER_CLASSES TARGET_THUMB /* Get reg_class from a letter such as appears in the machine description. - We only need constraint `f' for FPU_REGS (`r' == GENERAL_REGS) for the + We only need constraint `f' for FPA_REGS (`r' == GENERAL_REGS) for the ARM, but several more letters for the Thumb. */ #define REG_CLASS_FROM_LETTER(C) \ - ( (C) == 'f' ? FPU_REGS \ + ( (C) == 'f' ? FPA_REGS \ + : (C) == 'v' ? CIRRUS_REGS \ + : (C) == 'y' ? IWMMXT_REGS \ + : (C) == 'z' ? IWMMXT_GR_REGS \ : (C) == 'l' ? (TARGET_ARM ? GENERAL_REGS : LO_REGS) \ : TARGET_ARM ? NO_REGS \ : (C) == 'h' ? HI_REGS \ @@ -1136,11 +1346,11 @@ enum reg_class (TARGET_ARM ? \ CONST_OK_FOR_ARM_LETTER (VALUE, C) : CONST_OK_FOR_THUMB_LETTER (VALUE, C)) -/* Constant letter 'G' for the FPU immediate constants. +/* Constant letter 'G' for the FPA immediate constants. 'H' means the same constant negated. */ #define CONST_DOUBLE_OK_FOR_ARM_LETTER(X, C) \ - ((C) == 'G' ? const_double_rtx_ok_for_fpu (X) : \ - (C) == 'H' ? neg_const_double_rtx_ok_for_fpu (X) : 0) + ((C) == 'G' ? const_double_rtx_ok_for_fpa (X) : \ + (C) == 'H' ? neg_const_double_rtx_ok_for_fpa (X) : 0) #define CONST_DOUBLE_OK_FOR_LETTER_P(X, C) \ (TARGET_ARM ? \ @@ -1150,15 +1360,16 @@ enum reg_class an offset from a register. `S' means any symbol that has the SYMBOL_REF_FLAG set or a CONSTANT_POOL address. This means that the symbol is in the text segment and can be - accessed without using a load. */ + accessed without using a load. */ #define EXTRA_CONSTRAINT_ARM(OP, C) \ ((C) == 'Q' ? GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG : \ (C) == 'R' ? (GET_CODE (OP) == MEM \ && GET_CODE (XEXP (OP, 0)) == SYMBOL_REF \ && CONSTANT_POOL_ADDRESS_P (XEXP (OP, 0))) : \ - (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) \ - : 0) + (C) == 'S' ? (optimize > 0 && CONSTANT_ADDRESS_P (OP)) : \ + (C) == 'T' ? cirrus_memory_offset (OP) : \ + 0) #define EXTRA_CONSTRAINT_THUMB(X, C) \ ((C) == 'Q' ? (GET_CODE (X) == MEM \ @@ -1200,15 +1411,23 @@ enum reg_class ? GENERAL_REGS : NO_REGS) \ : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) -/* If we need to load shorts byte-at-a-time, then we need a scratch. */ +/* If we need to load shorts byte-at-a-time, then we need a scratch. */ #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ + /* Cannot load constants into Cirrus registers. */ \ + ((TARGET_CIRRUS \ + && (CLASS) == CIRRUS_REGS \ + && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \ + ? GENERAL_REGS : \ (TARGET_ARM ? \ + (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ + && CONSTANT_P (X)) \ + ? GENERAL_REGS : \ (((MODE) == HImode && ! arm_arch4 && TARGET_MMU_TRAPS \ && (GET_CODE (X) == MEM \ || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \ && true_regnum (X) == -1))) \ ? GENERAL_REGS : NO_REGS) \ - : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)) + : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) /* Try a machine-dependent way of reloading an illegitimate address operand. If we find one, push the reload and jump to WIN. This @@ -1231,6 +1450,9 @@ enum reg_class \ if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \ low = ((val & 0xf) ^ 0x8) - 0x8; \ + else if (TARGET_CIRRUS) \ + /* Need to be careful, -256 is not a valid offset. */ \ + low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ else if (MODE == SImode \ || (MODE == SFmode && TARGET_SOFT_FLOAT) \ || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \ @@ -1267,7 +1489,7 @@ enum reg_class } \ while (0) -/* ??? If an HImode FP+large_offset address is converted to an HImode +/* XXX If an HImode FP+large_offset address is converted to an HImode SP+large_offset address, then reload won't know how to fix it. It sees only that SP isn't valid for HImode, and so reloads the SP into an index register, but the resulting address is still invalid because the offset @@ -1282,7 +1504,7 @@ enum reg_class && GET_CODE (XEXP (X, 0)) == REG \ && XEXP (X, 0) == stack_pointer_rtx \ && GET_CODE (XEXP (X, 1)) == CONST_INT \ - && ! THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \ + && ! thumb_legitimate_offset_p (MODE, INTVAL (XEXP (X, 1)))) \ { \ rtx orig_X = X; \ X = copy_rtx (X); \ @@ -1301,15 +1523,24 @@ enum reg_class /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. - ARM regs are UNITS_PER_WORD bits while FPU regs can hold any FP mode */ + ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */ #define CLASS_MAX_NREGS(CLASS, MODE) \ - ((CLASS) == FPU_REGS ? 1 : ARM_NUM_REGS (MODE)) + (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE)) -/* Moves between FPU_REGS and GENERAL_REGS are two memory insns. */ +/* If defined, gives a class of registers that cannot be used as the + operand of a SUBREG that changes the mode of the object illegally. */ + +/* Moves between FPA_REGS and GENERAL_REGS are two memory insns. */ #define REGISTER_MOVE_COST(MODE, FROM, TO) \ (TARGET_ARM ? \ - ((FROM) == FPU_REGS && (TO) != FPU_REGS ? 20 : \ - (FROM) != FPU_REGS && (TO) == FPU_REGS ? 20 : 2) \ + ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \ + (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \ + (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \ + (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \ + (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \ + (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \ + (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \ + 2) \ : \ ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2) @@ -1334,8 +1565,8 @@ enum reg_class /* If we generate an insn to push BYTES bytes, this says how many the stack pointer really advances by. */ /* The push insns do not do this rounding implicitly. - So don't define this. */ -/* #define PUSH_ROUNDING(NPUSHED) ROUND_UP (NPUSHED) */ + So don't define this. */ +/* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ /* Define this if the maximum size of all the outgoing args is to be accumulated and pushed during the prologue. The amount can be @@ -1361,6 +1592,10 @@ enum reg_class #define LIBCALL_VALUE(MODE) \ (TARGET_ARM && TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT \ ? gen_rtx_REG (MODE, FIRST_ARM_FP_REGNUM) \ + : TARGET_ARM && TARGET_CIRRUS && GET_MODE_CLASS (MODE) == MODE_FLOAT \ + ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \ + : TARGET_REALLY_IWMMXT && VECTOR_MODE_SUPPORTED_P (MODE) \ + ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \ : gen_rtx_REG (MODE, ARG_REGISTER (1))) /* Define how to find the value returned by a function. @@ -1372,18 +1607,21 @@ enum reg_class /* 1 if N is a possible register number for a function value. On the ARM, only r0 and f0 can return results. */ +/* On a Cirrus chip, mvf0 can return results. */ #define FUNCTION_VALUE_REGNO_P(REGNO) \ ((REGNO) == ARG_REGISTER (1) \ + || (TARGET_ARM && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) && TARGET_CIRRUS) \ + || (TARGET_ARM && ((REGNO) == FIRST_IWMMXT_REGNUM) && TARGET_IWMMXT) \ || (TARGET_ARM && ((REGNO) == FIRST_ARM_FP_REGNUM) && TARGET_HARD_FLOAT)) /* How large values are returned */ /* A C expression which can inhibit the returning of certain function values - in registers, based on the type of value. */ + in registers, based on the type of value. */ #define RETURN_IN_MEMORY(TYPE) arm_return_in_memory (TYPE) /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return values must be in memory. On the ARM, they need only do so if larger - than a word, or if they contain elements offset from zero in the struct. */ + than a word, or if they contain elements offset from zero in the struct. */ #define DEFAULT_PCC_STRUCT_RETURN 0 /* Flags for the call/call_value rtl operations set up by function_arg. */ @@ -1417,7 +1655,7 @@ enum reg_class #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ -#define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ +#define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ /* Some macros to test these flags. */ #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) @@ -1430,7 +1668,7 @@ enum reg_class This is added to the cfun structure. */ typedef struct machine_function GTY(()) { - /* Additionsl stack adjustment in __builtin_eh_throw. */ + /* Additional stack adjustment in __builtin_eh_throw. */ rtx eh_epilogue_sp_ofs; /* Records if LR has to be saved for far jumps. */ int far_jump_used; @@ -1444,6 +1682,9 @@ typedef struct machine_function GTY(()) unsigned long func_type; /* Record if the function has a variable argument list. */ int uses_anonymous_args; + /* Records if sibcalls are blocked because an argument + register is needed to preserve stack alignment. */ + int sibcall_blocked; } machine_function; @@ -1454,7 +1695,11 @@ typedef struct { /* This is the number of registers of arguments scanned so far. */ int nregs; - /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT . */ + /* This is the number of iWMMXt register arguments scanned so far. */ + int iwmmxt_nregs; + int named_count; + int nargs; + /* One of CALL_NORMAL, CALL_LONG or CALL_SHORT. */ int call_cookie; } CUMULATIVE_ARGS; @@ -1483,7 +1728,8 @@ typedef struct this is the number of registers used. For args passed entirely in registers or entirely in memory, zero. */ #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ - ( NUM_ARG_REGS > (CUM).nregs \ + (VECTOR_MODE_SUPPORTED_P (MODE) ? 0 : \ + NUM_ARG_REGS > (CUM).nregs \ && (NUM_ARG_REGS < ((CUM).nregs + ARM_NUM_REGS2 (MODE, TYPE))) \ ? NUM_ARG_REGS - (CUM).nregs : 0) @@ -1499,30 +1745,40 @@ typedef struct for a call to a function whose data type is FNTYPE. For a library call, FNTYPE is 0. On the ARM, the offset starts at 0. */ -#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ - arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (INDIRECT)) +#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ + arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) /* Update the data in CUM to advance over an argument of mode MODE and data type TYPE. (TYPE is null for libcalls where that information may not be available.) */ #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ + (CUM).nargs += 1; \ + if (VECTOR_MODE_SUPPORTED_P (MODE)) \ + if ((CUM).named_count <= (CUM).nargs) \ + (CUM).nregs += 2; \ + else \ + (CUM).iwmmxt_nregs += 1; \ + else \ (CUM).nregs += ARM_NUM_REGS2 (MODE, TYPE) +/* If defined, a C expression that gives the alignment boundary, in bits, of an + argument with the specified mode and type. If it is not defined, + `PARM_BOUNDARY' is used for all arguments. */ +#define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \ + (TARGET_REALLY_IWMMXT && (VALID_IWMMXT_REG_MODE (MODE) || ((MODE) == DFmode)) \ + ? IWMMXT_ALIGNMENT : PARM_BOUNDARY) + /* 1 if N is a possible register number for function argument passing. On the ARM, r0-r3 are used to pass args. */ -#define FUNCTION_ARG_REGNO_P(REGNO) (IN_RANGE ((REGNO), 0, 3)) +#define FUNCTION_ARG_REGNO_P(REGNO) \ + (IN_RANGE ((REGNO), 0, 3) \ + || (TARGET_REALLY_IWMMXT && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) /* Implement `va_arg'. */ #define EXPAND_BUILTIN_VA_ARG(valist, type) \ arm_va_arg (valist, type) -/* Tail calling. */ - -/* A C expression that evaluates to true if it is ok to perform a sibling - call to DECL. */ -#define FUNCTION_OK_FOR_SIBCALL(DECL) arm_function_ok_for_sibcall ((DECL)) - /* Perform any actions needed for a function that is receiving a variable number of arguments. CUM is as above. MODE and TYPE are the mode and type of the current parameter. PRETEND_SIZE is a variable that should be set to @@ -1610,7 +1866,7 @@ typedef struct /* Determine if the epilogue should be output as RTL. You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ #define USE_RETURN_INSN(ISCOND) \ - (TARGET_ARM ? use_return_insn (ISCOND) : 0) + (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0) /* Definitions for register eliminations. @@ -1721,7 +1977,7 @@ typedef struct ldr pc, [pc] .word static chain value .word function's address - ??? FIXME: When the trampoline returns, r8 will be clobbered. */ + XXX FIXME: When the trampoline returns, r8 will be clobbered. */ #define ARM_TRAMPOLINE_TEMPLATE(FILE) \ { \ asm_fprintf (FILE, "\tldr\t%r, [%r, #0]\n", \ @@ -1770,20 +2026,30 @@ typedef struct /* Emit RTL insns to initialize the variable parts of a trampoline. FNADDR is an RTX for the address of the function's pure code. CXT is an RTX for the static chain value for the function. */ -#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ -{ \ - emit_move_insn \ - (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 8 : 16)), CXT); \ - emit_move_insn \ - (gen_rtx_MEM (SImode, plus_constant (TRAMP, TARGET_ARM ? 12 : 20)), FNADDR); \ +#ifndef INITIALIZE_TRAMPOLINE +#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ +{ \ + emit_move_insn (gen_rtx_MEM (SImode, \ + plus_constant (TRAMP, \ + TARGET_ARM ? 8 : 16)), \ + CXT); \ + emit_move_insn (gen_rtx_MEM (SImode, \ + plus_constant (TRAMP, \ + TARGET_ARM ? 12 : 20)), \ + FNADDR); \ } +#endif /* Addressing modes, and classification of registers for them. */ -#define HAVE_POST_INCREMENT 1 -#define HAVE_PRE_INCREMENT TARGET_ARM -#define HAVE_POST_DECREMENT TARGET_ARM -#define HAVE_PRE_DECREMENT TARGET_ARM +#define HAVE_POST_INCREMENT 1 +#define HAVE_PRE_INCREMENT TARGET_ARM +#define HAVE_POST_DECREMENT TARGET_ARM +#define HAVE_PRE_DECREMENT TARGET_ARM +#define HAVE_PRE_MODIFY_DISP TARGET_ARM +#define HAVE_POST_MODIFY_DISP TARGET_ARM +#define HAVE_PRE_MODIFY_REG TARGET_ARM +#define HAVE_POST_MODIFY_REG TARGET_ARM /* Macros to check register numbers against specific register classes. */ @@ -1791,7 +2057,7 @@ typedef struct They give nonzero only if REGNO is a hard reg of the suitable class or a pseudo reg currently allocated to a suitable hard reg. Since they use reg_renumber, they are safe only once reg_renumber - has been allocated, which happens in local-alloc.c. */ + has been allocated, which happens in local-alloc.c. */ #define TEST_REGNO(R, TEST, VALUE) \ ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) @@ -1817,7 +2083,7 @@ typedef struct REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) /* Maximum number of registers that can appear in a valid memory address. - Shifts in addresses can't be by a register. */ + Shifts in addresses can't be by a register. */ #define MAX_REGS_PER_ADDRESS 2 /* Recognize any constant value that is a valid address. */ @@ -1872,7 +2138,7 @@ typedef struct #define SUBTARGET_NAME_ENCODING_LENGTHS #endif -/* This is a C fragement for the inside of a switch statement. +/* This is a C fragment for the inside of a switch statement. Each case label should return the number of characters to be stripped from the start of a function's name, if that name starts with the indicated character. */ @@ -1913,6 +2179,8 @@ typedef struct || (X) == hard_frame_pointer_rtx \ || (X) == arg_pointer_rtx))) +#define REG_STRICT_P 0 + #else /* REG_OK_STRICT */ #define ARM_REG_OK_FOR_BASE_P(X) \ @@ -1921,6 +2189,8 @@ typedef struct #define THUMB_REG_MODE_OK_FOR_BASE_P(X, MODE) \ THUMB_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) +#define REG_STRICT_P 1 + #endif /* REG_OK_STRICT */ /* Now define some helpers in terms of the above. */ @@ -1948,340 +2218,56 @@ typedef struct /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a valid memory address for an instruction. The MODE argument is the machine mode for the MEM expression - that wants to use this address. - - The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ + that wants to use this address. */ -/* --------------------------------arm version----------------------------- */ #define ARM_BASE_REGISTER_RTX_P(X) \ (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X)) #define ARM_INDEX_REGISTER_RTX_P(X) \ (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X)) -/* A C statement (sans semicolon) to jump to LABEL for legitimate index RTXs - used by the macro GO_IF_LEGITIMATE_ADDRESS. Floating point indices can - only be small constants. */ -#define ARM_GO_IF_LEGITIMATE_INDEX(MODE, BASE_REGNO, INDEX, LABEL) \ - do \ - { \ - HOST_WIDE_INT range; \ - enum rtx_code code = GET_CODE (INDEX); \ - \ - if (TARGET_HARD_FLOAT && GET_MODE_CLASS (MODE) == MODE_FLOAT) \ - { \ - if (code == CONST_INT && INTVAL (INDEX) < 1024 \ - && INTVAL (INDEX) > -1024 \ - && (INTVAL (INDEX) & 3) == 0) \ - goto LABEL; \ - } \ - else \ - { \ - if (ARM_INDEX_REGISTER_RTX_P (INDEX) \ - && GET_MODE_SIZE (MODE) <= 4) \ - goto LABEL; \ - if (GET_MODE_SIZE (MODE) <= 4 && code == MULT \ - && (! arm_arch4 || (MODE) != HImode)) \ - { \ - rtx xiop0 = XEXP (INDEX, 0); \ - rtx xiop1 = XEXP (INDEX, 1); \ - if (ARM_INDEX_REGISTER_RTX_P (xiop0) \ - && power_of_two_operand (xiop1, SImode)) \ - goto LABEL; \ - if (ARM_INDEX_REGISTER_RTX_P (xiop1) \ - && power_of_two_operand (xiop0, SImode)) \ - goto LABEL; \ - } \ - if (GET_MODE_SIZE (MODE) <= 4 \ - && (code == LSHIFTRT || code == ASHIFTRT \ - || code == ASHIFT || code == ROTATERT) \ - && (! arm_arch4 || (MODE) != HImode)) \ - { \ - rtx op = XEXP (INDEX, 1); \ - if (ARM_INDEX_REGISTER_RTX_P (XEXP (INDEX, 0)) \ - && GET_CODE (op) == CONST_INT && INTVAL (op) > 0 \ - && INTVAL (op) <= 31) \ - goto LABEL; \ - } \ - /* NASTY: Since this limits the addressing of unsigned \ - byte loads. */ \ - range = ((MODE) == HImode || (MODE) == QImode) \ - ? (arm_arch4 ? 256 : 4095) : 4096; \ - if (code == CONST_INT && INTVAL (INDEX) < range \ - && INTVAL (INDEX) > -range) \ - goto LABEL; \ - } \ - } \ - while (0) +#define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \ + { \ + if (arm_legitimate_address_p (MODE, X, REG_STRICT_P)) \ + goto WIN; \ + } -/* Jump to LABEL if X is a valid address RTX. This must take - REG_OK_STRICT into account when deciding about valid registers. +#define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE,X,WIN) \ + { \ + if (thumb_legitimate_address_p (MODE, X, REG_STRICT_P)) \ + goto WIN; \ + } - Allow REG, REG+REG, REG+INDEX, INDEX+REG, REG-INDEX, and non - floating SYMBOL_REF to the constant pool. Allow REG-only and - AUTINC-REG if handling TImode or HImode. Other symbol refs must be - forced though a static cell to ensure addressability. */ -#define ARM_GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ -{ \ - if (ARM_BASE_REGISTER_RTX_P (X)) \ - goto LABEL; \ - else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC) \ - && GET_CODE (XEXP (X, 0)) == REG \ - && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \ - goto LABEL; \ - else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \ - && (GET_CODE (X) == LABEL_REF \ - || (GET_CODE (X) == CONST \ - && GET_CODE (XEXP ((X), 0)) == PLUS \ - && GET_CODE (XEXP (XEXP ((X), 0), 0)) == LABEL_REF \ - && GET_CODE (XEXP (XEXP ((X), 0), 1)) == CONST_INT)))\ - goto LABEL; \ - else if ((MODE) == TImode) \ - ; \ - else if ((MODE) == DImode || (TARGET_SOFT_FLOAT && (MODE) == DFmode)) \ - { \ - if (GET_CODE (X) == PLUS && ARM_BASE_REGISTER_RTX_P (XEXP (X, 0)) \ - && GET_CODE (XEXP (X, 1)) == CONST_INT) \ - { \ - HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ - if (val == 4 || val == -4 || val == -8) \ - goto LABEL; \ - } \ - } \ - else if (GET_CODE (X) == PLUS) \ - { \ - rtx xop0 = XEXP (X, 0); \ - rtx xop1 = XEXP (X, 1); \ - \ - if (ARM_BASE_REGISTER_RTX_P (xop0)) \ - ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop0), xop1, LABEL); \ - else if (ARM_BASE_REGISTER_RTX_P (xop1)) \ - ARM_GO_IF_LEGITIMATE_INDEX (MODE, REGNO (xop1), xop0, LABEL); \ - } \ - /* Reload currently can't handle MINUS, so disable this for now */ \ - /* else if (GET_CODE (X) == MINUS) \ - { \ - rtx xop0 = XEXP (X,0); \ - rtx xop1 = XEXP (X,1); \ - \ - if (ARM_BASE_REGISTER_RTX_P (xop0)) \ - ARM_GO_IF_LEGITIMATE_INDEX (MODE, -1, xop1, LABEL); \ - } */ \ - else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \ - && GET_CODE (X) == SYMBOL_REF \ - && CONSTANT_POOL_ADDRESS_P (X) \ - && ! (flag_pic \ - && symbol_mentioned_p (get_pool_constant (X)))) \ - goto LABEL; \ - else if ((GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_DEC) \ - && (GET_MODE_SIZE (MODE) <= 4) \ - && GET_CODE (XEXP (X, 0)) == REG \ - && ARM_REG_OK_FOR_BASE_P (XEXP (X, 0))) \ - goto LABEL; \ -} - -/* ---------------------thumb version----------------------------------*/ -#define THUMB_LEGITIMATE_OFFSET(MODE, VAL) \ - (GET_MODE_SIZE (MODE) == 1 ? ((unsigned HOST_WIDE_INT) (VAL) < 32) \ - : GET_MODE_SIZE (MODE) == 2 ? ((unsigned HOST_WIDE_INT) (VAL) < 64 \ - && ((VAL) & 1) == 0) \ - : ((VAL) >= 0 && ((VAL) + GET_MODE_SIZE (MODE)) <= 128 \ - && ((VAL) & 3) == 0)) - -/* The AP may be eliminated to either the SP or the FP, so we use the - least common denominator, e.g. SImode, and offsets from 0 to 64. */ - -/* ??? Verify whether the above is the right approach. */ - -/* ??? Also, the FP may be eliminated to the SP, so perhaps that - needs special handling also. */ - -/* ??? Look at how the mips16 port solves this problem. It probably uses - better ways to solve some of these problems. */ - -/* Although it is not incorrect, we don't accept QImode and HImode - addresses based on the frame pointer or arg pointer until the - reload pass starts. This is so that eliminating such addresses - into stack based ones won't produce impossible code. */ -#define THUMB_GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ -{ \ -/* ??? Not clear if this is right. Experiment. */ \ - if (GET_MODE_SIZE (MODE) < 4 \ - && ! (reload_in_progress || reload_completed) \ - && ( reg_mentioned_p (frame_pointer_rtx, X) \ - || reg_mentioned_p (arg_pointer_rtx, X) \ - || reg_mentioned_p (virtual_incoming_args_rtx, X) \ - || reg_mentioned_p (virtual_outgoing_args_rtx, X) \ - || reg_mentioned_p (virtual_stack_dynamic_rtx, X) \ - || reg_mentioned_p (virtual_stack_vars_rtx, X))) \ - ; \ - /* Accept any base register. SP only in SImode or larger. */ \ - else if (GET_CODE (X) == REG \ - && THUMB_REG_MODE_OK_FOR_BASE_P (X, MODE)) \ - goto WIN; \ - /* This is PC relative data before MACHINE_DEPENDENT_REORG runs. */ \ - else if (GET_MODE_SIZE (MODE) >= 4 && CONSTANT_P (X) \ - && GET_CODE (X) == SYMBOL_REF \ - && CONSTANT_POOL_ADDRESS_P (X) && ! flag_pic) \ - goto WIN; \ - /* This is PC relative data after MACHINE_DEPENDENT_REORG runs. */ \ - else if (GET_MODE_SIZE (MODE) >= 4 && reload_completed \ - && (GET_CODE (X) == LABEL_REF \ - || (GET_CODE (X) == CONST \ - && GET_CODE (XEXP (X, 0)) == PLUS \ - && GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF \ - && GET_CODE (XEXP (XEXP (X, 0), 1)) == CONST_INT))) \ - goto WIN; \ - /* Post-inc indexing only supported for SImode and larger. */ \ - else if (GET_CODE (X) == POST_INC && GET_MODE_SIZE (MODE) >= 4 \ - && GET_CODE (XEXP (X, 0)) == REG \ - && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0))) \ - goto WIN; \ - else if (GET_CODE (X) == PLUS) \ - { \ - /* REG+REG address can be any two index registers. */ \ - /* We disallow FRAME+REG addressing since we know that FRAME \ - will be replaced with STACK, and SP relative addressing only \ - permits SP+OFFSET. */ \ - if (GET_MODE_SIZE (MODE) <= 4 \ - && GET_CODE (XEXP (X, 0)) == REG \ - && GET_CODE (XEXP (X, 1)) == REG \ - && XEXP (X, 0) != frame_pointer_rtx \ - && XEXP (X, 1) != frame_pointer_rtx \ - && XEXP (X, 0) != virtual_stack_vars_rtx \ - && XEXP (X, 1) != virtual_stack_vars_rtx \ - && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \ - && THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 1))) \ - goto WIN; \ - /* REG+const has 5-7 bit offset for non-SP registers. */ \ - else if (GET_CODE (XEXP (X, 0)) == REG \ - && (THUMB_REG_OK_FOR_INDEX_P (XEXP (X, 0)) \ - || XEXP (X, 0) == arg_pointer_rtx) \ - && GET_CODE (XEXP (X, 1)) == CONST_INT \ - && THUMB_LEGITIMATE_OFFSET (MODE, INTVAL (XEXP (X, 1)))) \ - goto WIN; \ - /* REG+const has 10 bit offset for SP, but only SImode and \ - larger is supported. */ \ - /* ??? Should probably check for DI/DFmode overflow here \ - just like GO_IF_LEGITIMATE_OFFSET does. */ \ - else if (GET_CODE (XEXP (X, 0)) == REG \ - && REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \ - && GET_MODE_SIZE (MODE) >= 4 \ - && GET_CODE (XEXP (X, 1)) == CONST_INT \ - && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (X, 1)) \ - + GET_MODE_SIZE (MODE)) <= 1024 \ - && (INTVAL (XEXP (X, 1)) & 3) == 0) \ - goto WIN; \ - else if (GET_CODE (XEXP (X, 0)) == REG \ - && REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \ - && GET_MODE_SIZE (MODE) >= 4 \ - && GET_CODE (XEXP (X, 1)) == CONST_INT \ - && (INTVAL (XEXP (X, 1)) & 3) == 0) \ - goto WIN; \ - } \ - else if (GET_MODE_CLASS (MODE) != MODE_FLOAT \ - && GET_CODE (X) == SYMBOL_REF \ - && CONSTANT_POOL_ADDRESS_P (X) \ - && ! (flag_pic \ - && symbol_mentioned_p (get_pool_constant (X)))) \ - goto WIN; \ -} - -/* ------------------------------------------------------------------- */ #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, WIN) \ if (TARGET_ARM) \ ARM_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) \ else /* if (TARGET_THUMB) */ \ THUMB_GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN) -/* ------------------------------------------------------------------- */ + /* Try machine-dependent ways of modifying an illegitimate address - to be legitimate. If we find one, return the new, valid address. - This macro is used in only one place: `memory_address' in explow.c. - - OLDX is the address as it was before break_out_memory_refs was called. - In some cases it is useful to look at this to decide what needs to be done. - - MODE and WIN are passed so that this macro can use - GO_IF_LEGITIMATE_ADDRESS. - - It is always safe for this macro to do nothing. It exists to recognize - opportunities to optimize the output. - - On the ARM, try to convert [REG, #BIGCONST] - into ADD BASE, REG, #UPPERCONST and [BASE, #VALIDCONST], - where VALIDCONST == 0 in case of TImode. */ -#define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ -{ \ - if (GET_CODE (X) == PLUS) \ - { \ - rtx xop0 = XEXP (X, 0); \ - rtx xop1 = XEXP (X, 1); \ - \ - if (CONSTANT_P (xop0) && ! symbol_mentioned_p (xop0)) \ - xop0 = force_reg (SImode, xop0); \ - if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \ - xop1 = force_reg (SImode, xop1); \ - if (ARM_BASE_REGISTER_RTX_P (xop0) \ - && GET_CODE (xop1) == CONST_INT) \ - { \ - HOST_WIDE_INT n, low_n; \ - rtx base_reg, val; \ - n = INTVAL (xop1); \ - \ - if (MODE == DImode || (TARGET_SOFT_FLOAT && MODE == DFmode)) \ - { \ - low_n = n & 0x0f; \ - n &= ~0x0f; \ - if (low_n > 4) \ - { \ - n += 16; \ - low_n -= 16; \ - } \ - } \ - else \ - { \ - low_n = ((MODE) == TImode ? 0 \ - : n >= 0 ? (n & 0xfff) : -((-n) & 0xfff)); \ - n -= low_n; \ - } \ - base_reg = gen_reg_rtx (SImode); \ - val = force_operand (gen_rtx_PLUS (SImode, xop0, \ - GEN_INT (n)), NULL_RTX); \ - emit_move_insn (base_reg, val); \ - (X) = (low_n == 0 ? base_reg \ - : gen_rtx_PLUS (SImode, base_reg, GEN_INT (low_n))); \ - } \ - else if (xop0 != XEXP (X, 0) || xop1 != XEXP (x, 1)) \ - (X) = gen_rtx_PLUS (SImode, xop0, xop1); \ - } \ - else if (GET_CODE (X) == MINUS) \ - { \ - rtx xop0 = XEXP (X, 0); \ - rtx xop1 = XEXP (X, 1); \ - \ - if (CONSTANT_P (xop0)) \ - xop0 = force_reg (SImode, xop0); \ - if (CONSTANT_P (xop1) && ! symbol_mentioned_p (xop1)) \ - xop1 = force_reg (SImode, xop1); \ - if (xop0 != XEXP (X, 0) || xop1 != XEXP (X, 1)) \ - (X) = gen_rtx_MINUS (SImode, xop0, xop1); \ - } \ - if (flag_pic) \ - (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \ - if (memory_address_p (MODE, X)) \ - goto WIN; \ -} + to be legitimate. If we find one, return the new, valid address. */ +#define ARM_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ +do { \ + X = arm_legitimize_address (X, OLDX, MODE); \ + \ + if (memory_address_p (MODE, X)) \ + goto WIN; \ +} while (0) -#define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ - if (flag_pic) \ - (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); - -#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ - if (TARGET_ARM) \ - ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) \ - else \ - THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN) +#define THUMB_LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ +do { \ + if (flag_pic) \ + (X) = legitimize_pic_address (OLDX, MODE, NULL_RTX); \ +} while (0) + +#define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ +do { \ + if (TARGET_ARM) \ + ARM_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \ + else \ + THUMB_LEGITIMIZE_ADDRESS (X, OLDX, MODE, WIN); \ +} while (0) /* Go to LABEL if ADDR (a legitimate address expression) has an effect that depends on the machine mode it is used for. */ @@ -2305,7 +2291,7 @@ typedef struct /* Define as C expression which evaluates to nonzero if the tablejump instruction expects the table to contain offsets from the address of the table. - Do not define this if the table should contain absolute addresses. */ + Do not define this if the table should contain absolute addresses. */ /* #define CASE_VECTOR_PC_RELATIVE 1 */ /* signed 'char' is most compatible, but RISC OS wants it unsigned. @@ -2322,7 +2308,7 @@ typedef struct #define MOVE_MAX 4 #undef MOVE_RATIO -#define MOVE_RATIO (arm_is_xscale ? 4 : 2) +#define MOVE_RATIO (arm_tune_xscale ? 4 : 2) /* Define if operations between registers always perform the operation on the full register even if a narrower mode is specified. */ @@ -2350,7 +2336,7 @@ typedef struct /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). On the arm, Y in a register is used modulo 256 for the shift. Only for - rotates is modulo 32 used. */ + rotates is modulo 32 used. */ /* #define SHIFT_COUNT_TRUNCATED 1 */ /* All integers have the same format so truncation is easy. */ @@ -2370,44 +2356,12 @@ typedef struct ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ || (X) == arg_pointer_rtx) -#define DEFAULT_RTX_COSTS(X, CODE, OUTER_CODE) \ - return arm_rtx_costs (X, CODE, OUTER_CODE); - /* Moves to and from memory are quite expensive */ #define MEMORY_MOVE_COST(M, CLASS, IN) \ (TARGET_ARM ? 10 : \ ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \ * (CLASS == LO_REGS ? 1 : 2))) -/* All address computations that can be done are free, but rtx cost returns - the same for practically all of them. So we weight the different types - of address here in the order (most pref first): - PRE/POST_INC/DEC, SHIFT or NON-INT sum, INT sum, REG, MEM or LABEL. */ -#define ARM_ADDRESS_COST(X) \ - (10 - ((GET_CODE (X) == MEM || GET_CODE (X) == LABEL_REF \ - || GET_CODE (X) == SYMBOL_REF) \ - ? 0 \ - : ((GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC \ - || GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \ - ? 10 \ - : (((GET_CODE (X) == PLUS || GET_CODE (X) == MINUS) \ - ? 6 + (GET_CODE (XEXP (X, 1)) == CONST_INT ? 2 \ - : ((GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == '2' \ - || GET_RTX_CLASS (GET_CODE (XEXP (X, 0))) == 'c' \ - || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == '2' \ - || GET_RTX_CLASS (GET_CODE (XEXP (X, 1))) == 'c') \ - ? 1 : 0)) \ - : 4))))) - -#define THUMB_ADDRESS_COST(X) \ - ((GET_CODE (X) == REG \ - || (GET_CODE (X) == PLUS && GET_CODE (XEXP (X, 0)) == REG \ - && GET_CODE (XEXP (X, 1)) == CONST_INT)) \ - ? 1 : 2) - -#define ADDRESS_COST(X) \ - (TARGET_ARM ? ARM_ADDRESS_COST (X) : THUMB_ADDRESS_COST (X)) - /* Try to generate sequences that don't involve branches, we can then use conditional instructions */ #define BRANCH_COST \ @@ -2444,13 +2398,13 @@ extern const char * arm_pic_register_string; extern int making_const_table; /* Handle pragmas for compatibility with Intel's compilers. */ -#define REGISTER_TARGET_PRAGMAS(PFILE) do { \ - cpp_register_pragma (PFILE, 0, "long_calls", arm_pr_long_calls); \ - cpp_register_pragma (PFILE, 0, "no_long_calls", arm_pr_no_long_calls); \ - cpp_register_pragma (PFILE, 0, "long_calls_off", arm_pr_long_calls_off); \ +#define REGISTER_TARGET_PRAGMAS() do { \ + c_register_pragma (0, "long_calls", arm_pr_long_calls); \ + c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ + c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ } while (0) -/* Condition code information. */ +/* Condition code information. */ /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, return the mode to be used for the comparison. */ @@ -2472,54 +2426,33 @@ extern int making_const_table; } \ while (0) -#define STORE_FLAG_VALUE 1 - +/* The arm5 clz instruction returns 32. */ +#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) - -/* Gcc puts the pool in the wrong place for ARM, since we can only - load addresses a limited distance around the pc. We do some - special munging to move the constant pool values to the correct - point in the code. */ -#define MACHINE_DEPENDENT_REORG(INSN) \ - arm_reorg (INSN); \ - #undef ASM_APP_OFF #define ASM_APP_OFF (TARGET_THUMB ? "\t.code\t16\n" : "") -/* Output an internal label definition. */ -#ifndef ASM_OUTPUT_INTERNAL_LABEL -#define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \ - do \ - { \ - char * s = (char *) alloca (40 + strlen (PREFIX)); \ - \ - if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \ - && !strcmp (PREFIX, "L")) \ - { \ - arm_ccfsm_state = 0; \ - arm_target_insn = NULL; \ - } \ - ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \ - ASM_OUTPUT_LABEL (STREAM, s); \ - } \ - while (0) -#endif - /* Output a push or a pop instruction (only used when profiling). */ #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ - if (TARGET_ARM) \ - asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ - STACK_POINTER_REGNUM, REGNO); \ - else \ - asm_fprintf (STREAM, "\tpush {%r}\n", REGNO) + do \ + { \ + if (TARGET_ARM) \ + asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ + STACK_POINTER_REGNUM, REGNO); \ + else \ + asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ + } while (0) #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ - if (TARGET_ARM) \ - asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ - STACK_POINTER_REGNUM, REGNO); \ - else \ - asm_fprintf (STREAM, "\tpop {%r}\n", REGNO) + do \ + { \ + if (TARGET_ARM) \ + asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ + STACK_POINTER_REGNUM, REGNO); \ + else \ + asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ + } while (0) /* This is how to output a label which precedes a jumptable. Since Thumb instructions are 2 bytes, we may need explicit alignment here. */ @@ -2529,7 +2462,7 @@ extern int making_const_table; { \ if (TARGET_THUMB) \ ASM_OUTPUT_ALIGN (FILE, 2); \ - ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \ + (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \ } \ while (0) @@ -2538,10 +2471,11 @@ extern int making_const_table; { \ if (TARGET_THUMB) \ { \ - if (is_called_in_ARM_mode (DECL)) \ + if (is_called_in_ARM_mode (DECL) \ + || current_function_is_thunk) \ fprintf (STREAM, "\t.code 32\n") ; \ else \ - fprintf (STREAM, "\t.thumb_func\n") ; \ + fprintf (STREAM, "\t.code 16\n\t.thumb_func\n") ; \ } \ if (TARGET_POKE_FUNCTION_NAME) \ arm_poke_function_name (STREAM, (char *) NAME); \ @@ -2572,19 +2506,19 @@ extern int making_const_table; /* To support -falign-* switches we need to use .p2align so that alignment directives in code sections will be padded with no-op instructions, rather than zeroes. */ -#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP) \ +#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ if ((LOG) != 0) \ { \ if ((MAX_SKIP) == 0) \ - fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ + fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ else \ fprintf ((FILE), "\t.p2align %d,,%d\n", \ - (LOG), (MAX_SKIP)); \ + (int) (LOG), (int) (MAX_SKIP)); \ } #endif /* Only perform branch elimination (by making instructions conditional) if - we're optimising. Otherwise it's of no use anyway. */ + we're optimizing. Otherwise it's of no use anyway. */ #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ if (TARGET_ARM && optimize) \ arm_final_prescan_insn (INSN); \ @@ -2609,79 +2543,99 @@ extern int making_const_table; : 0)))) /* Output the address of an operand. */ -#define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \ -{ \ - int is_minus = GET_CODE (X) == MINUS; \ - \ - if (GET_CODE (X) == REG) \ - asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \ - else if (GET_CODE (X) == PLUS || is_minus) \ - { \ - rtx base = XEXP (X, 0); \ - rtx index = XEXP (X, 1); \ - HOST_WIDE_INT offset = 0; \ - if (GET_CODE (base) != REG) \ - { \ - /* Ensure that BASE is a register */ \ - /* (one of them must be). */ \ - rtx temp = base; \ - base = index; \ - index = temp; \ - } \ - switch (GET_CODE (index)) \ - { \ - case CONST_INT: \ - offset = INTVAL (index); \ - if (is_minus) \ - offset = -offset; \ - asm_fprintf (STREAM, "[%r, #%d]", \ - REGNO (base), offset); \ - break; \ - \ - case REG: \ - asm_fprintf (STREAM, "[%r, %s%r]", \ - REGNO (base), is_minus ? "-" : "", \ - REGNO (index)); \ - break; \ - \ - case MULT: \ - case ASHIFTRT: \ - case LSHIFTRT: \ - case ASHIFT: \ - case ROTATERT: \ - { \ - asm_fprintf (STREAM, "[%r, %s%r", \ - REGNO (base), is_minus ? "-" : "", \ - REGNO (XEXP (index, 0))); \ - arm_print_operand (STREAM, index, 'S'); \ - fputs ("]", STREAM); \ - break; \ - } \ - \ - default: \ - abort(); \ - } \ - } \ - else if ( GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC\ - || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC)\ - { \ - extern int output_memory_reference_mode; \ - \ - if (GET_CODE (XEXP (X, 0)) != REG) \ - abort (); \ - \ - if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ - asm_fprintf (STREAM, "[%r, #%s%d]!", \ - REGNO (XEXP (X, 0)), \ - GET_CODE (X) == PRE_DEC ? "-" : "", \ - GET_MODE_SIZE (output_memory_reference_mode));\ - else \ - asm_fprintf (STREAM, "[%r], #%s%d", \ - REGNO (XEXP (X, 0)), \ - GET_CODE (X) == POST_DEC ? "-" : "", \ - GET_MODE_SIZE (output_memory_reference_mode));\ - } \ - else output_addr_const (STREAM, X); \ +#define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \ +{ \ + int is_minus = GET_CODE (X) == MINUS; \ + \ + if (GET_CODE (X) == REG) \ + asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \ + else if (GET_CODE (X) == PLUS || is_minus) \ + { \ + rtx base = XEXP (X, 0); \ + rtx index = XEXP (X, 1); \ + HOST_WIDE_INT offset = 0; \ + if (GET_CODE (base) != REG) \ + { \ + /* Ensure that BASE is a register. */ \ + /* (one of them must be). */ \ + rtx temp = base; \ + base = index; \ + index = temp; \ + } \ + switch (GET_CODE (index)) \ + { \ + case CONST_INT: \ + offset = INTVAL (index); \ + if (is_minus) \ + offset = -offset; \ + asm_fprintf (STREAM, "[%r, #%wd]", \ + REGNO (base), offset); \ + break; \ + \ + case REG: \ + asm_fprintf (STREAM, "[%r, %s%r]", \ + REGNO (base), is_minus ? "-" : "", \ + REGNO (index)); \ + break; \ + \ + case MULT: \ + case ASHIFTRT: \ + case LSHIFTRT: \ + case ASHIFT: \ + case ROTATERT: \ + { \ + asm_fprintf (STREAM, "[%r, %s%r", \ + REGNO (base), is_minus ? "-" : "", \ + REGNO (XEXP (index, 0))); \ + arm_print_operand (STREAM, index, 'S'); \ + fputs ("]", STREAM); \ + break; \ + } \ + \ + default: \ + abort(); \ + } \ + } \ + else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \ + || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \ + { \ + extern enum machine_mode output_memory_reference_mode; \ + \ + if (GET_CODE (XEXP (X, 0)) != REG) \ + abort (); \ + \ + if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ + asm_fprintf (STREAM, "[%r, #%s%d]!", \ + REGNO (XEXP (X, 0)), \ + GET_CODE (X) == PRE_DEC ? "-" : "", \ + GET_MODE_SIZE (output_memory_reference_mode)); \ + else \ + asm_fprintf (STREAM, "[%r], #%s%d", \ + REGNO (XEXP (X, 0)), \ + GET_CODE (X) == POST_DEC ? "-" : "", \ + GET_MODE_SIZE (output_memory_reference_mode)); \ + } \ + else if (GET_CODE (X) == PRE_MODIFY) \ + { \ + asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \ + if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \ + asm_fprintf (STREAM, "#%wd]!", \ + INTVAL (XEXP (XEXP (X, 1), 1))); \ + else \ + asm_fprintf (STREAM, "%r]!", \ + REGNO (XEXP (XEXP (X, 1), 1))); \ + } \ + else if (GET_CODE (X) == POST_MODIFY) \ + { \ + asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \ + if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \ + asm_fprintf (STREAM, "#%wd", \ + INTVAL (XEXP (XEXP (X, 1), 1))); \ + else \ + asm_fprintf (STREAM, "%r", \ + REGNO (XEXP (XEXP (X, 1), 1))); \ + } \ + else output_addr_const (STREAM, X); \ } #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \ @@ -2692,10 +2646,12 @@ extern int making_const_table; asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \ else if (GET_CODE (X) == PLUS) \ { \ + if (GET_CODE (XEXP (X, 0)) != REG) \ + abort (); \ if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ - asm_fprintf (STREAM, "[%r, #%d]", \ + asm_fprintf (STREAM, "[%r, #%wd]", \ REGNO (XEXP (X, 0)), \ - (int) INTVAL (XEXP (X, 1))); \ + INTVAL (XEXP (X, 1))); \ else \ asm_fprintf (STREAM, "[%r, %r]", \ REGNO (XEXP (X, 0)), \ @@ -2710,7 +2666,12 @@ extern int making_const_table; ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \ else \ THUMB_PRINT_OPERAND_ADDRESS (STREAM, X) - + +#define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ + if (GET_CODE (X) != CONST_VECTOR \ + || ! arm_emit_vector_const (FILE, X)) \ + goto FAIL; + /* A C expression whose value is RTL representing the value of the return address for the frame COUNT steps up from the current frame. */ @@ -2746,13 +2707,16 @@ extern int making_const_table; {"arm_hard_register_operand", {REG}}, \ {"f_register_operand", {SUBREG, REG}}, \ {"arm_add_operand", {SUBREG, REG, CONST_INT}}, \ - {"fpu_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \ - {"fpu_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \ + {"arm_addimm_operand", {CONST_INT}}, \ + {"fpa_add_operand", {SUBREG, REG, CONST_DOUBLE}}, \ + {"fpa_rhs_operand", {SUBREG, REG, CONST_DOUBLE}}, \ {"arm_rhs_operand", {SUBREG, REG, CONST_INT}}, \ {"arm_not_operand", {SUBREG, REG, CONST_INT}}, \ {"reg_or_int_operand", {SUBREG, REG, CONST_INT}}, \ {"index_operand", {SUBREG, REG, CONST_INT}}, \ {"thumb_cmp_operand", {SUBREG, REG, CONST_INT}}, \ + {"thumb_cmpneg_operand", {CONST_INT}}, \ + {"thumb_cbrch_target_operand", {SUBREG, REG, MEM}}, \ {"offsettable_memory_operand", {MEM}}, \ {"bad_signed_byte_operand", {MEM}}, \ {"alignable_memory_operand", {MEM}}, \ @@ -2774,18 +2738,180 @@ extern int making_const_table; {"multi_register_push", {PARALLEL}}, \ {"cc_register", {REG}}, \ {"logical_binary_operator", {AND, IOR, XOR}}, \ + {"cirrus_register_operand", {REG}}, \ + {"cirrus_fp_register", {REG}}, \ + {"cirrus_shift_const", {CONST_INT}}, \ {"dominant_cc_register", {REG}}, /* Define this if you have special predicates that know special things about modes. Genrecog will warn about certain forms of match_operand without a mode; if the operand predicate is listed in - SPECIAL_MODE_PREDICATES, the warning will be suppressed. */ + SPECIAL_MODE_PREDICATES, the warning will be suppressed. */ #define SPECIAL_MODE_PREDICATES \ "cc_register", "dominant_cc_register", enum arm_builtins { - ARM_BUILTIN_CLZ, + ARM_BUILTIN_GETWCX, + ARM_BUILTIN_SETWCX, + + ARM_BUILTIN_WZERO, + + ARM_BUILTIN_WAVG2BR, + ARM_BUILTIN_WAVG2HR, + ARM_BUILTIN_WAVG2B, + ARM_BUILTIN_WAVG2H, + + ARM_BUILTIN_WACCB, + ARM_BUILTIN_WACCH, + ARM_BUILTIN_WACCW, + + ARM_BUILTIN_WMACS, + ARM_BUILTIN_WMACSZ, + ARM_BUILTIN_WMACU, + ARM_BUILTIN_WMACUZ, + + ARM_BUILTIN_WSADB, + ARM_BUILTIN_WSADBZ, + ARM_BUILTIN_WSADH, + ARM_BUILTIN_WSADHZ, + + ARM_BUILTIN_WALIGN, + + ARM_BUILTIN_TMIA, + ARM_BUILTIN_TMIAPH, + ARM_BUILTIN_TMIABB, + ARM_BUILTIN_TMIABT, + ARM_BUILTIN_TMIATB, + ARM_BUILTIN_TMIATT, + + ARM_BUILTIN_TMOVMSKB, + ARM_BUILTIN_TMOVMSKH, + ARM_BUILTIN_TMOVMSKW, + + ARM_BUILTIN_TBCSTB, + ARM_BUILTIN_TBCSTH, + ARM_BUILTIN_TBCSTW, + + ARM_BUILTIN_WMADDS, + ARM_BUILTIN_WMADDU, + + ARM_BUILTIN_WPACKHSS, + ARM_BUILTIN_WPACKWSS, + ARM_BUILTIN_WPACKDSS, + ARM_BUILTIN_WPACKHUS, + ARM_BUILTIN_WPACKWUS, + ARM_BUILTIN_WPACKDUS, + + ARM_BUILTIN_WADDB, + ARM_BUILTIN_WADDH, + ARM_BUILTIN_WADDW, + ARM_BUILTIN_WADDSSB, + ARM_BUILTIN_WADDSSH, + ARM_BUILTIN_WADDSSW, + ARM_BUILTIN_WADDUSB, + ARM_BUILTIN_WADDUSH, + ARM_BUILTIN_WADDUSW, + ARM_BUILTIN_WSUBB, + ARM_BUILTIN_WSUBH, + ARM_BUILTIN_WSUBW, + ARM_BUILTIN_WSUBSSB, + ARM_BUILTIN_WSUBSSH, + ARM_BUILTIN_WSUBSSW, + ARM_BUILTIN_WSUBUSB, + ARM_BUILTIN_WSUBUSH, + ARM_BUILTIN_WSUBUSW, + + ARM_BUILTIN_WAND, + ARM_BUILTIN_WANDN, + ARM_BUILTIN_WOR, + ARM_BUILTIN_WXOR, + + ARM_BUILTIN_WCMPEQB, + ARM_BUILTIN_WCMPEQH, + ARM_BUILTIN_WCMPEQW, + ARM_BUILTIN_WCMPGTUB, + ARM_BUILTIN_WCMPGTUH, + ARM_BUILTIN_WCMPGTUW, + ARM_BUILTIN_WCMPGTSB, + ARM_BUILTIN_WCMPGTSH, + ARM_BUILTIN_WCMPGTSW, + + ARM_BUILTIN_TEXTRMSB, + ARM_BUILTIN_TEXTRMSH, + ARM_BUILTIN_TEXTRMSW, + ARM_BUILTIN_TEXTRMUB, + ARM_BUILTIN_TEXTRMUH, + ARM_BUILTIN_TEXTRMUW, + ARM_BUILTIN_TINSRB, + ARM_BUILTIN_TINSRH, + ARM_BUILTIN_TINSRW, + + ARM_BUILTIN_WMAXSW, + ARM_BUILTIN_WMAXSH, + ARM_BUILTIN_WMAXSB, + ARM_BUILTIN_WMAXUW, + ARM_BUILTIN_WMAXUH, + ARM_BUILTIN_WMAXUB, + ARM_BUILTIN_WMINSW, + ARM_BUILTIN_WMINSH, + ARM_BUILTIN_WMINSB, + ARM_BUILTIN_WMINUW, + ARM_BUILTIN_WMINUH, + ARM_BUILTIN_WMINUB, + + ARM_BUILTIN_WMULUH, + ARM_BUILTIN_WMULSH, + ARM_BUILTIN_WMULUL, + + ARM_BUILTIN_PSADBH, + ARM_BUILTIN_WSHUFH, + + ARM_BUILTIN_WSLLH, + ARM_BUILTIN_WSLLW, + ARM_BUILTIN_WSLLD, + ARM_BUILTIN_WSRAH, + ARM_BUILTIN_WSRAW, + ARM_BUILTIN_WSRAD, + ARM_BUILTIN_WSRLH, + ARM_BUILTIN_WSRLW, + ARM_BUILTIN_WSRLD, + ARM_BUILTIN_WRORH, + ARM_BUILTIN_WRORW, + ARM_BUILTIN_WRORD, + ARM_BUILTIN_WSLLHI, + ARM_BUILTIN_WSLLWI, + ARM_BUILTIN_WSLLDI, + ARM_BUILTIN_WSRAHI, + ARM_BUILTIN_WSRAWI, + ARM_BUILTIN_WSRADI, + ARM_BUILTIN_WSRLHI, + ARM_BUILTIN_WSRLWI, + ARM_BUILTIN_WSRLDI, + ARM_BUILTIN_WRORHI, + ARM_BUILTIN_WRORWI, + ARM_BUILTIN_WRORDI, + + ARM_BUILTIN_WUNPCKIHB, + ARM_BUILTIN_WUNPCKIHH, + ARM_BUILTIN_WUNPCKIHW, + ARM_BUILTIN_WUNPCKILB, + ARM_BUILTIN_WUNPCKILH, + ARM_BUILTIN_WUNPCKILW, + + ARM_BUILTIN_WUNPCKEHSB, + ARM_BUILTIN_WUNPCKEHSH, + ARM_BUILTIN_WUNPCKEHSW, + ARM_BUILTIN_WUNPCKEHUB, + ARM_BUILTIN_WUNPCKEHUH, + ARM_BUILTIN_WUNPCKEHUW, + ARM_BUILTIN_WUNPCKELSB, + ARM_BUILTIN_WUNPCKELSH, + ARM_BUILTIN_WUNPCKELSW, + ARM_BUILTIN_WUNPCKELUB, + ARM_BUILTIN_WUNPCKELUH, + ARM_BUILTIN_WUNPCKELUW, + ARM_BUILTIN_MAX }; #endif /* ! GCC_ARM_H */ diff --git a/contrib/gcc/config/arm/arm.md b/contrib/gcc/config/arm/arm.md index 0e60712..9f10d10 100644 --- a/contrib/gcc/config/arm/arm.md +++ b/contrib/gcc/config/arm/arm.md @@ -1,32 +1,29 @@ ;;- Machine description for ARM for GNU compiler ;; Copyright 1991, 1993, 1994, 1995, 1996, 1996, 1997, 1998, 1999, 2000, -;; 2001, 2002 Free Software Foundation, Inc. +;; 2001, 2002, 2003 2004 Free Software Foundation, Inc. ;; Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) ;; and Martin Simmons (@harleqn.co.uk). ;; More major hacks by Richard Earnshaw (rearnsha@arm.com). -;; This file is part of GNU CC. +;; This file is part of GCC. -;; GNU CC is free software; you can redistribute it and/or modify -;; it under the terms of the GNU General Public License as published by -;; the Free Software Foundation; either version 2, or (at your option) -;; any later version. +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 2, or (at your +;; option) any later version. -;; GNU CC is distributed in the hope that it will be useful, -;; but WITHOUT ANY WARRANTY; without even the implied warranty of -;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -;; GNU General Public License for more details. +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. ;; You should have received a copy of the GNU General Public License -;; along with GNU CC; see the file COPYING. If not, write to +;; along with GCC; see the file COPYING. If not, write to ;; the Free Software Foundation, 59 Temple Place - Suite 330, ;; Boston, MA 02111-1307, USA. ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. -;; There are patterns in this file to support XFmode arithmetic. -;; Unfortunately RISC iX doesn't work well with these so they are disabled. -;; (See arm.h) ;;--------------------------------------------------------------------------- ;; Constants @@ -41,6 +38,13 @@ (LAST_ARM_REGNUM 15) ] ) +;; 3rd operand to select_dominance_cc_mode +(define_constants + [(DOM_CC_X_AND_Y 0) + (DOM_CC_NX_OR_Y 1) + (DOM_CC_X_OR_Y 2) + ] +) ;; UNSPEC Usage: ;; Note: sin and cos are no-longer used. @@ -65,15 +69,24 @@ ; prevent combine from trying to rip it apart. (UNSPEC_PRLG_STK 5) ; A special barrier that prevents frame accesses ; being scheduled before the stack adjustment insn. - (UNSPEC_CLZ 5) ; `clz' instruction, count leading zeros (SImode): - ; operand 0 is the result, - ; operand 1 is the parameter. (UNSPEC_PROLOGUE_USE 6) ; As USE insns are not meaningful after reload, ; this unspec is used to prevent the deletion of ; instructions setting registers for EH handling ; and stack frame generation. Operand 0 is the ; register to "use". (UNSPEC_CHECK_ARCH 7); Set CCs to indicate 26-bit or 32-bit mode. + (UNSPEC_WSHUFH 8) ; Used by the intrinsic form of the iWMMXt WSHUFH instruction. + (UNSPEC_WACC 9) ; Used by the intrinsic form of the iWMMXt WACC instruction. + (UNSPEC_TMOVMSK 10) ; Used by the intrinsic form of the iWMMXt TMOVMSK instruction. + (UNSPEC_WSAD 11) ; Used by the intrinsic form of the iWMMXt WSAD instruction. + (UNSPEC_WSADZ 12) ; Used by the intrinsic form of the iWMMXt WSADZ instruction. + (UNSPEC_WMACS 13) ; Used by the intrinsic form of the iWMMXt WMACS instruction. + (UNSPEC_WMACU 14) ; Used by the intrinsic form of the iWMMXt WMACU instruction. + (UNSPEC_WMACSZ 15) ; Used by the intrinsic form of the iWMMXt WMACSZ instruction. + (UNSPEC_WMACUZ 16) ; Used by the intrinsic form of the iWMMXt WMACUZ instruction. + (UNSPEC_CLRDI 17) ; Used by the intrinsic form of the iWMMXt CLRDI instruction. + (UNSPEC_WMADDS 18) ; Used by the intrinsic form of the iWMMXt WMADDS instruction. + (UNSPEC_WMADDU 19) ; Used by the intrinsic form of the iWMMXt WMADDU instruction. ] ) @@ -98,6 +111,12 @@ ; a 32-bit object. (VUNSPEC_POOL_8 7) ; `pool-entry(8)'. An entry in the constant pool for ; a 64-bit object. + (VUNSPEC_TMRC 8) ; Used by the iWMMXt TMRC instruction. + (VUNSPEC_TMCR 9) ; Used by the iWMMXt TMCR instruction. + (VUNSPEC_ALIGN8 10) ; 8-byte alignment version of VUNSPEC_ALIGN + (VUNSPEC_WCMP_EQ 11) ; Used by the iWMMXt WCMPEQ instructions + (VUNSPEC_WCMP_GTU 12) ; Used by the iWMMXt WCMPGTU instructions + (VUNSPEC_WCMP_GT 13) ; Used by the iwMMXT WCMPGT instructions ] ) @@ -120,13 +139,14 @@ ;; Operand number of an input operand that is shifted. Zero if the ;; given instruction does not shift one of its input operands. -(define_attr "is_xscale" "no,yes" (const (symbol_ref "arm_is_xscale"))) +(define_attr "is_xscale" "no,yes" (const (symbol_ref "arm_tune_xscale"))) (define_attr "shift" "" (const_int 0)) ; Floating Point Unit. If we only have floating point emulation, then there ; is no point in scheduling the floating point insns. (Well, for best ; performance we should try and group them together). -(define_attr "fpu" "fpa,fpe2,fpe3" (const (symbol_ref "arm_fpu_attr"))) +(define_attr "fpu" "softfpa,fpa,fpe2,fpe3,maverick" + (const (symbol_ref "arm_fpu_attr"))) ; LENGTH of an instruction (in bytes) (define_attr "length" "" (const_int 4)) @@ -157,7 +177,6 @@ ; mult a multiply instruction ; block blockage insn, this blocks all functional units ; float a floating point arithmetic operation (subject to expansion) -; fdivx XFmode floating point division ; fdivd DFmode floating point division ; fdivs SFmode floating point division ; fmul Floating point multiply @@ -178,9 +197,12 @@ ; store2 store 2 words ; store3 store 3 words ; store4 store 4 words +; Additions for Cirrus Maverick co-processor: +; mav_farith Floating point arithmetic (4 cycle) +; mav_dmult Double multiplies (7 cycle) ; (define_attr "type" - "normal,mult,block,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith,float_em,f_load,f_store,f_mem_r,r_mem_f,f_2_r,r_2_f,call,load,store1,store2,store3,store4" + "normal,mult,block,float,fdivx,fdivd,fdivs,fmul,ffmul,farith,ffarith,float_em,f_load,f_store,f_mem_r,r_mem_f,f_2_r,r_2_f,call,load,store1,store2,store3,store4,mav_farith,mav_dmult" (const_string "normal")) ; Load scheduling, set from the arm_ld_sched variable @@ -221,7 +243,7 @@ ; Only model the write buffer for ARM6 and ARM7. Earlier processors don't ; have one. Later ones, such as StrongARM, have write-back caches, so don't -; suffer blockages enough to warrent modelling this (and it can adversely +; suffer blockages enough to warrant modelling this (and it can adversely ; affect the schedule). (define_attr "model_wbuf" "no,yes" (const (symbol_ref "arm_is_6_or_7"))) @@ -245,50 +267,10 @@ ;; distant label. Only applicable to Thumb code. (define_attr "far_jump" "yes,no" (const_string "no")) -;; (define_function_unit {name} {num-units} {n-users} {test} -;; {ready-delay} {issue-delay} [{conflict-list}]) - -;;-------------------------------------------------------------------- -;; Floating point unit (FPA) -;;-------------------------------------------------------------------- -(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa") - (eq_attr "type" "fdivx")) 71 69) - -(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa") - (eq_attr "type" "fdivd")) 59 57) - -(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa") - (eq_attr "type" "fdivs")) 31 29) - -(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa") - (eq_attr "type" "fmul")) 9 7) - -(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa") - (eq_attr "type" "ffmul")) 6 4) +(define_automaton "arm") -(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa") - (eq_attr "type" "farith")) 4 2) - -(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa") - (eq_attr "type" "ffarith")) 2 2) - -(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa") - (eq_attr "type" "r_2_f")) 5 3) - -(define_function_unit "fpa" 1 0 (and (eq_attr "fpu" "fpa") - (eq_attr "type" "f_2_r")) 1 2) - -; The fpa10 doesn't really have a memory read unit, but it can start to -; speculatively execute the instruction in the pipeline, provided the data -; is already loaded, so pretend reads have a delay of 2 (and that the -; pipeline is infinite). - -(define_function_unit "fpa_mem" 1 0 (and (eq_attr "fpu" "fpa") - (eq_attr "type" "f_load")) 3 1) - -;;-------------------------------------------------------------------- ;; Write buffer -;;-------------------------------------------------------------------- +; ; Strictly, we should model a 4-deep write buffer for ARM7xx based chips ; ; The write buffer on some of the arm6 processors is hard to model exactly. @@ -300,102 +282,101 @@ ; writes will take 2 FCLK cycles per word, if FCLK and MCLK are asynchronous ; (they aren't allowed to be at present) then there is a startup cost of 1MCLK ; cycle to add as well. +(define_cpu_unit "write_buf" "arm") -(define_function_unit "write_buf" 1 2 - (and (eq_attr "model_wbuf" "yes") - (eq_attr "type" "store1,r_mem_f")) 5 3) -(define_function_unit "write_buf" 1 2 - (and (eq_attr "model_wbuf" "yes") - (eq_attr "type" "store2")) 7 4) -(define_function_unit "write_buf" 1 2 - (and (eq_attr "model_wbuf" "yes") - (eq_attr "type" "store3")) 9 5) -(define_function_unit "write_buf" 1 2 - (and (eq_attr "model_wbuf" "yes") - (eq_attr "type" "store4")) 11 6) - -;;-------------------------------------------------------------------- ;; Write blockage unit -;;-------------------------------------------------------------------- +; ; The write_blockage unit models (partially), the fact that reads will stall ; until the write buffer empties. ; The f_mem_r and r_mem_f could also block, but they are to the stack, ; so we don't model them here -(define_function_unit "write_blockage" 1 0 (and (eq_attr "model_wbuf" "yes") - (eq_attr "type" "store1")) 5 5 - [(eq_attr "write_conflict" "yes")]) -(define_function_unit "write_blockage" 1 0 (and (eq_attr "model_wbuf" "yes") - (eq_attr "type" "store2")) 7 7 - [(eq_attr "write_conflict" "yes")]) -(define_function_unit "write_blockage" 1 0 (and (eq_attr "model_wbuf" "yes") - (eq_attr "type" "store3")) 9 9 - [(eq_attr "write_conflict" "yes")]) -(define_function_unit "write_blockage" 1 0 - (and (eq_attr "model_wbuf" "yes") (eq_attr "type" "store4")) 11 11 - [(eq_attr "write_conflict" "yes")]) -(define_function_unit "write_blockage" 1 0 - (and (eq_attr "model_wbuf" "yes") - (eq_attr "write_conflict" "yes")) 1 1) - -;;-------------------------------------------------------------------- -;; Core unit -;;-------------------------------------------------------------------- -; Everything must spend at least one cycle in the core unit -(define_function_unit "core" 1 0 (eq_attr "core_cycles" "single") 1 1) - -(define_function_unit "core" 1 0 - (and (eq_attr "ldsched" "yes") (eq_attr "type" "store1")) 1 1) - -(define_function_unit "core" 1 0 - (and (eq_attr "ldsched" "yes") (eq_attr "type" "load")) 2 1) - -;; We do not need to conditionalize the define_function_unit immediately -;; above. This one will be ignored for anything other than xscale -;; compiles and for xscale compiles it provides a larger delay -;; and the scheduler will DTRT. -;; FIXME: this test needs to be revamped to not depend on this feature -;; of the scheduler. - -(define_function_unit "core" 1 0 - (and (and (eq_attr "ldsched" "yes") (eq_attr "type" "load")) - (eq_attr "is_xscale" "yes")) - 3 1) +(define_cpu_unit "write_blockage" "arm") -(define_function_unit "core" 1 0 - (and (eq_attr "ldsched" "!yes") (eq_attr "type" "load,store1")) 2 2) +;; Core +; +(define_cpu_unit "core" "arm") -(define_function_unit "core" 1 0 - (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_load")) 3 3) +(define_insn_reservation "r_mem_f_wbuf" 5 + (and (eq_attr "model_wbuf" "yes") + (eq_attr "type" "r_mem_f")) + "core+write_buf*3") -(define_function_unit "core" 1 0 - (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_store")) 4 4) +(define_insn_reservation "store1_wbuf" 5 + (and (eq_attr "model_wbuf" "yes") + (eq_attr "type" "store1")) + "core+write_buf*3+write_blockage*5") -(define_function_unit "core" 1 0 - (and (eq_attr "fpu" "fpa") (eq_attr "type" "r_mem_f")) 6 6) +(define_insn_reservation "store2_wbuf" 7 + (and (eq_attr "model_wbuf" "yes") + (eq_attr "type" "store2")) + "core+write_buf*4+write_blockage*7") -(define_function_unit "core" 1 0 - (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_mem_r")) 7 7) +(define_insn_reservation "store3_wbuf" 9 + (and (eq_attr "model_wbuf" "yes") + (eq_attr "type" "store3")) + "core+write_buf*5+write_blockage*9") -(define_function_unit "core" 1 0 - (and (eq_attr "ldsched" "no") (eq_attr "type" "mult")) 16 16) +(define_insn_reservation "store4_wbuf" 11 + (and (eq_attr "model_wbuf" "yes") + (eq_attr "type" "store4")) + "core+write_buf*6+write_blockage*11") -(define_function_unit "core" 1 0 - (and (and (eq_attr "ldsched" "yes") (eq_attr "is_strongarm" "no")) - (eq_attr "type" "mult")) 4 4) +(define_insn_reservation "store2" 3 + (and (eq_attr "model_wbuf" "no") + (eq_attr "type" "store2")) + "core*3") -(define_function_unit "core" 1 0 - (and (and (eq_attr "ldsched" "yes") (eq_attr "is_strongarm" "yes")) - (eq_attr "type" "mult")) 3 2) +(define_insn_reservation "store3" 4 + (and (eq_attr "model_wbuf" "no") + (eq_attr "type" "store3")) + "core*4") -(define_function_unit "core" 1 0 (eq_attr "type" "store2") 3 3) +(define_insn_reservation "store4" 5 + (and (eq_attr "model_wbuf" "no") + (eq_attr "type" "store4")) + "core*5") -(define_function_unit "core" 1 0 (eq_attr "type" "store3") 4 4) +(define_insn_reservation "store1_ldsched" 1 + (and (eq_attr "ldsched" "yes") (eq_attr "type" "store1")) + "core") -(define_function_unit "core" 1 0 (eq_attr "type" "store4") 5 5) +(define_insn_reservation "load_ldsched_xscale" 3 + (and (and (eq_attr "ldsched" "yes") (eq_attr "type" "load")) + (eq_attr "is_xscale" "yes")) + "core") + +(define_insn_reservation "load_ldsched" 2 + (and (and (eq_attr "ldsched" "yes") (eq_attr "type" "load")) + (eq_attr "is_xscale" "no")) + "core") + +(define_insn_reservation "load_or_store" 2 + (and (eq_attr "ldsched" "!yes") (eq_attr "type" "load,store1")) + "core*2") + +(define_insn_reservation "mult" 16 + (and (eq_attr "ldsched" "no") (eq_attr "type" "mult")) + "core*16") + +(define_insn_reservation "mult_ldsched_strongarm" 3 + (and (and (eq_attr "ldsched" "yes") (eq_attr "is_strongarm" "yes")) + (eq_attr "type" "mult")) + "core*2") + +(define_insn_reservation "mult_ldsched" 4 + (and (and (eq_attr "ldsched" "yes") (eq_attr "is_strongarm" "no")) + (eq_attr "type" "mult")) + "core*4") -(define_function_unit "core" 1 0 +(define_insn_reservation "multi_cycle" 32 (and (eq_attr "core_cycles" "multi") - (eq_attr "type" "!mult,load,store1,store2,store3,store4")) 32 32) + (eq_attr "type" "!mult,load,store1,store2,store3,store4")) + "core*32") + +(define_insn_reservation "single_cycle" 1 + (eq_attr "core_cycles" "single") + "core") + ;;--------------------------------------------------------------------------- ;; Insn patterns @@ -405,6 +386,8 @@ ;; Note: For DImode insns, there is normally no reason why operands should ;; not be in the same register, what we don't want is for something being ;; written to partially overlap something that is an input. +;; Cirrus 64bit additions should not be split because we have a native +;; 64bit addition instructions. (define_expand "adddi3" [(parallel @@ -414,6 +397,16 @@ (clobber (reg:CC CC_REGNUM))])] "TARGET_EITHER" " + if (TARGET_CIRRUS) + { + if (!cirrus_fp_register (operands[0], DImode)) + operands[0] = force_reg (DImode, operands[0]); + if (!cirrus_fp_register (operands[1], DImode)) + operands[1] = force_reg (DImode, operands[1]); + emit_insn (gen_cirrus_adddi3 (operands[0], operands[1], operands[2])); + DONE; + } + if (TARGET_THUMB) { if (GET_CODE (operands[1]) != REG) @@ -440,7 +433,7 @@ (plus:DI (match_operand:DI 1 "s_register_operand" "%0, 0") (match_operand:DI 2 "s_register_operand" "r, 0"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM" + "TARGET_ARM && !TARGET_CIRRUS" "#" "TARGET_ARM && reload_completed" [(parallel [(set (reg:CC_C CC_REGNUM) @@ -468,7 +461,7 @@ (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:DI 1 "s_register_operand" "r,0"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM" + "TARGET_ARM && !TARGET_CIRRUS" "#" "TARGET_ARM && reload_completed" [(parallel [(set (reg:CC_C CC_REGNUM) @@ -497,7 +490,7 @@ (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:DI 1 "s_register_operand" "r,0"))) (clobber (reg:CC CC_REGNUM))] - "TARGET_ARM" + "TARGET_ARM && !TARGET_CIRRUS" "#" "TARGET_ARM && reload_completed" [(parallel [(set (reg:CC_C CC_REGNUM) @@ -534,7 +527,7 @@ " ) -; If there is a scratch available, this will be faster than synthesising the +; If there is a scratch available, this will be faster than synthesizing the ; addition. (define_peephole2 [(match_scratch:SI 3 "r") @@ -674,6 +667,60 @@ [(set_attr "conds" "set")] ) +;; This is the canonicalization of addsi3_compare0_for_combiner when the +;; addend is a constant. +(define_insn "*cmpsi2_addneg" + [(set (reg:CC CC_REGNUM) + (compare:CC + (match_operand:SI 1 "s_register_operand" "r,r") + (match_operand:SI 2 "arm_addimm_operand" "I,L"))) + (set (match_operand:SI 0 "s_register_operand" "=r,r") + (plus:SI (match_dup 1) + (match_operand:SI 3 "arm_addimm_operand" "L,I")))] + "TARGET_ARM && INTVAL (operands[2]) == -INTVAL (operands[3])" + "@ + sub%?s\\t%0, %1, %2 + add%?s\\t%0, %1, #%n2" + [(set_attr "conds" "set")] +) + +;; Convert the sequence +;; sub rd, rn, #1 +;; cmn rd, #1 (equivalent to cmp rd, #-1) +;; bne dest +;; into +;; subs rd, rn, #1 +;; bcs dest ((unsigned)rn >= 1) +;; similarly for the beq variant using bcc. +;; This is a common looping idiom (while (n--)) +(define_peephole2 + [(set (match_operand:SI 0 "s_register_operand" "") + (plus:SI (match_operand:SI 1 "s_register_operand" "") + (const_int -1))) + (set (match_operand 2 "cc_register" "") + (compare (match_dup 0) (const_int -1))) + (set (pc) + (if_then_else (match_operator 3 "equality_operator" + [(match_dup 2) (const_int 0)]) + (match_operand 4 "" "") + (match_operand 5 "" "")))] + "TARGET_ARM && peep2_reg_dead_p (3, operands[2])" + [(parallel[ + (set (match_dup 2) + (compare:CC + (match_dup 1) (const_int 1))) + (set (match_dup 0) (plus:SI (match_dup 1) (const_int -1)))]) + (set (pc) + (if_then_else (match_op_dup 3 [(match_dup 2) (const_int 0)]) + (match_dup 4) + (match_dup 5)))] + "operands[2] = gen_rtx_REG (CCmode, CC_REGNUM); + operands[3] = gen_rtx_fmt_ee ((GET_CODE (operands[3]) == NE + ? GEU : LTU), + VOIDmode, + operands[2], const0_rtx);" +) + ;; The next four insns work because they compare the result with one of ;; the operands, and we know that the use of the condition code is ;; either GEU or LTU, so we can use the carry flag from the addition @@ -745,13 +792,13 @@ ) (define_insn "*addsi3_carryin_shift" - [(set (match_operand:SI 0 "s_register_operand" "") + [(set (match_operand:SI 0 "s_register_operand" "=r") (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)) (plus:SI (match_operator:SI 2 "shift_operator" - [(match_operand:SI 3 "s_register_operand" "") - (match_operand:SI 4 "reg_or_int_operand" "")]) - (match_operand:SI 1 "s_register_operand" ""))))] + [(match_operand:SI 3 "s_register_operand" "r") + (match_operand:SI 4 "reg_or_int_operand" "rM")]) + (match_operand:SI 1 "s_register_operand" "r"))))] "TARGET_ARM" "adc%?\\t%0, %1, %3%S2" [(set_attr "conds" "use")] @@ -800,77 +847,41 @@ (set_attr "length" "4,8")] ) -(define_insn "addsf3" - [(set (match_operand:SF 0 "s_register_operand" "=f,f") - (plus:SF (match_operand:SF 1 "s_register_operand" "%f,f") - (match_operand:SF 2 "fpu_add_operand" "fG,H")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "@ - adf%?s\\t%0, %1, %2 - suf%?s\\t%0, %1, #%N2" - [(set_attr "type" "farith") - (set_attr "predicable" "yes")] -) - -(define_insn "adddf3" - [(set (match_operand:DF 0 "s_register_operand" "=f,f") - (plus:DF (match_operand:DF 1 "s_register_operand" "%f,f") - (match_operand:DF 2 "fpu_add_operand" "fG,H")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "@ - adf%?d\\t%0, %1, %2 - suf%?d\\t%0, %1, #%N2" - [(set_attr "type" "farith") - (set_attr "predicable" "yes")] -) - -(define_insn "*adddf_esfdf_df" - [(set (match_operand:DF 0 "s_register_operand" "=f,f") - (plus:DF (float_extend:DF - (match_operand:SF 1 "s_register_operand" "f,f")) - (match_operand:DF 2 "fpu_add_operand" "fG,H")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "@ - adf%?d\\t%0, %1, %2 - suf%?d\\t%0, %1, #%N2" - [(set_attr "type" "farith") - (set_attr "predicable" "yes")] -) - -(define_insn "*adddf_df_esfdf" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (plus:DF (match_operand:DF 1 "s_register_operand" "f") - (float_extend:DF - (match_operand:SF 2 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "adf%?d\\t%0, %1, %2" - [(set_attr "type" "farith") - (set_attr "predicable" "yes")] -) +; transform ((x << y) - 1) to ~(~(x-1) << y) Where X is a constant. +(define_split + [(set (match_operand:SI 0 "s_register_operand" "") + (plus:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "") + (match_operand:SI 2 "s_register_operand" "")) + (const_int -1))) + (clobber (match_operand:SI 3 "s_register_operand" ""))] + "TARGET_ARM" + [(set (match_dup 3) (match_dup 1)) + (set (match_dup 0) (not:SI (ashift:SI (match_dup 3) (match_dup 2))))] + " + operands[1] = GEN_INT (~(INTVAL (operands[1]) - 1)); +") -(define_insn "*adddf_esfdf_esfdf" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (plus:DF (float_extend:DF - (match_operand:SF 1 "s_register_operand" "f")) - (float_extend:DF - (match_operand:SF 2 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "adf%?d\\t%0, %1, %2" - [(set_attr "type" "farith") - (set_attr "predicable" "yes")] -) +(define_expand "addsf3" + [(set (match_operand:SF 0 "s_register_operand" "") + (plus:SF (match_operand:SF 1 "s_register_operand" "") + (match_operand:SF 2 "fpa_add_operand" "")))] + "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + " + if (TARGET_CIRRUS + && !cirrus_fp_register (operands[2], SFmode)) + operands[2] = force_reg (SFmode, operands[2]); +") -(define_insn "addxf3" - [(set (match_operand:XF 0 "s_register_operand" "=f,f") - (plus:XF (match_operand:XF 1 "s_register_operand" "f,f") - (match_operand:XF 2 "fpu_add_operand" "fG,H")))] - "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" - "@ - adf%?e\\t%0, %1, %2 - suf%?e\\t%0, %1, #%N2" - [(set_attr "type" "farith") - (set_attr "predicable" "yes")] -) +(define_expand "adddf3" + [(set (match_operand:DF 0 "s_register_operand" "") + (plus:DF (match_operand:DF 1 "s_register_operand" "") + (match_operand:DF 2 "fpa_add_operand" "")))] + "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + " + if (TARGET_CIRRUS + && !cirrus_fp_register (operands[2], DFmode)) + operands[2] = force_reg (DFmode, operands[2]); +") (define_expand "subdi3" [(parallel @@ -880,6 +891,15 @@ (clobber (reg:CC CC_REGNUM))])] "TARGET_EITHER" " + if (TARGET_CIRRUS + && TARGET_ARM + && cirrus_fp_register (operands[0], DImode) + && cirrus_fp_register (operands[1], DImode)) + { + emit_insn (gen_cirrus_subdi3 (operands[0], operands[1], operands[2])); + DONE; + } + if (TARGET_THUMB) { if (GET_CODE (operands[1]) != REG) @@ -1065,76 +1085,36 @@ (set_attr "length" "*,8")] ) -(define_insn "subsf3" - [(set (match_operand:SF 0 "s_register_operand" "=f,f") - (minus:SF (match_operand:SF 1 "fpu_rhs_operand" "f,G") - (match_operand:SF 2 "fpu_rhs_operand" "fG,f")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "@ - suf%?s\\t%0, %1, %2 - rsf%?s\\t%0, %2, %1" - [(set_attr "type" "farith")] -) - -(define_insn "subdf3" - [(set (match_operand:DF 0 "s_register_operand" "=f,f") - (minus:DF (match_operand:DF 1 "fpu_rhs_operand" "f,G") - (match_operand:DF 2 "fpu_rhs_operand" "fG,f")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "@ - suf%?d\\t%0, %1, %2 - rsf%?d\\t%0, %2, %1" - [(set_attr "type" "farith") - (set_attr "predicable" "yes")] -) - -(define_insn "*subdf_esfdf_df" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (minus:DF (float_extend:DF - (match_operand:SF 1 "s_register_operand" "f")) - (match_operand:DF 2 "fpu_rhs_operand" "fG")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "suf%?d\\t%0, %1, %2" - [(set_attr "type" "farith") - (set_attr "predicable" "yes")] -) - -(define_insn "*subdf_df_esfdf" - [(set (match_operand:DF 0 "s_register_operand" "=f,f") - (minus:DF (match_operand:DF 1 "fpu_rhs_operand" "f,G") - (float_extend:DF - (match_operand:SF 2 "s_register_operand" "f,f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "@ - suf%?d\\t%0, %1, %2 - rsf%?d\\t%0, %2, %1" - [(set_attr "type" "farith") - (set_attr "predicable" "yes")] -) +(define_expand "subsf3" + [(set (match_operand:SF 0 "s_register_operand" "") + (minus:SF (match_operand:SF 1 "fpa_rhs_operand" "") + (match_operand:SF 2 "fpa_rhs_operand" "")))] + "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + " + if (TARGET_CIRRUS) + { + if (!cirrus_fp_register (operands[1], SFmode)) + operands[1] = force_reg (SFmode, operands[1]); + if (!cirrus_fp_register (operands[2], SFmode)) + operands[2] = force_reg (SFmode, operands[2]); + } +") -(define_insn "*subdf_esfdf_esfdf" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (minus:DF (float_extend:DF - (match_operand:SF 1 "s_register_operand" "f")) - (float_extend:DF - (match_operand:SF 2 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "suf%?d\\t%0, %1, %2" - [(set_attr "type" "farith") - (set_attr "predicable" "yes")] -) +(define_expand "subdf3" + [(set (match_operand:DF 0 "s_register_operand" "") + (minus:DF (match_operand:DF 1 "fpa_rhs_operand" "") + (match_operand:DF 2 "fpa_rhs_operand" "")))] + "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + " + if (TARGET_CIRRUS) + { + if (!cirrus_fp_register (operands[1], DFmode)) + operands[1] = force_reg (DFmode, operands[1]); + if (!cirrus_fp_register (operands[2], DFmode)) + operands[2] = force_reg (DFmode, operands[2]); + } +") -(define_insn "subxf3" - [(set (match_operand:XF 0 "s_register_operand" "=f,f") - (minus:XF (match_operand:XF 1 "fpu_rhs_operand" "f,G") - (match_operand:XF 2 "fpu_rhs_operand" "fG,f")))] - "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" - "@ - suf%?e\\t%0, %1, %2 - rsf%?e\\t%0, %2, %1" - [(set_attr "type" "farith") - (set_attr "predicable" "yes")] -) ;; Multiplication insns @@ -1185,7 +1165,7 @@ (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=&r,&r") (mult:SI (match_dup 2) (match_dup 1)))] - "TARGET_ARM && !arm_is_xscale" + "TARGET_ARM && !arm_arch_xscale" "mul%?s\\t%0, %2, %1" [(set_attr "conds" "set") (set_attr "type" "mult")] @@ -1198,7 +1178,7 @@ (match_operand:SI 1 "s_register_operand" "%?r,0")) (const_int 0))) (clobber (match_scratch:SI 0 "=&r,&r"))] - "TARGET_ARM && !arm_is_xscale" + "TARGET_ARM && !arm_arch_xscale" "mul%?s\\t%0, %2, %1" [(set_attr "conds" "set") (set_attr "type" "mult")] @@ -1229,7 +1209,7 @@ (set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r,&r") (plus:SI (mult:SI (match_dup 2) (match_dup 1)) (match_dup 3)))] - "TARGET_ARM && !arm_is_xscale" + "TARGET_ARM && !arm_arch_xscale" "mla%?s\\t%0, %2, %1, %3" [(set_attr "conds" "set") (set_attr "type" "mult")] @@ -1244,13 +1224,13 @@ (match_operand:SI 3 "s_register_operand" "?r,r,0,0")) (const_int 0))) (clobber (match_scratch:SI 0 "=&r,&r,&r,&r"))] - "TARGET_ARM && !arm_is_xscale" + "TARGET_ARM && !arm_arch_xscale" "mla%?s\\t%0, %2, %1, %3" [(set_attr "conds" "set") (set_attr "type" "mult")] ) -;; Unnamed template to match long long multiply-accumlate (smlal) +;; Unnamed template to match long long multiply-accumulate (smlal) (define_insn "*mulsidi3adddi" [(set (match_operand:DI 0 "s_register_operand" "=&r") @@ -1287,7 +1267,7 @@ (set_attr "predicable" "yes")] ) -;; Unnamed template to match long long unsigned multiply-accumlate (umlal) +;; Unnamed template to match long long unsigned multiply-accumulate (umlal) (define_insn "*umulsidi3adddi" [(set (match_operand:DI 0 "s_register_operand" "=&r") @@ -1338,9 +1318,50 @@ (match_operand:HI 1 "s_register_operand" "%r")) (sign_extend:SI (match_operand:HI 2 "s_register_operand" "r"))))] - "TARGET_ARM && arm_is_xscale" + "TARGET_ARM && arm_arch5e" "smulbb%?\\t%0, %1, %2" - [(set_attr "type" "mult")] + [(set_attr "type" "mult") + (set_attr "predicable" "yes")] +) + +(define_insn "*mulhisi3tb" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (mult:SI (ashiftrt:SI + (match_operand:SI 1 "s_register_operand" "r") + (const_int 16)) + (sign_extend:SI + (match_operand:HI 2 "s_register_operand" "r"))))] + "TARGET_ARM && arm_arch5e" + "smultb%?\\t%0, %1, %2" + [(set_attr "type" "mult") + (set_attr "predicable" "yes")] +) + +(define_insn "*mulhisi3bt" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (mult:SI (sign_extend:SI + (match_operand:HI 1 "s_register_operand" "r")) + (ashiftrt:SI + (match_operand:SI 2 "s_register_operand" "r") + (const_int 16))))] + "TARGET_ARM && arm_arch5e" + "smulbt%?\\t%0, %1, %2" + [(set_attr "type" "mult") + (set_attr "predicable" "yes")] +) + +(define_insn "*mulhisi3tt" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (mult:SI (ashiftrt:SI + (match_operand:SI 1 "s_register_operand" "r") + (const_int 16)) + (ashiftrt:SI + (match_operand:SI 2 "s_register_operand" "r") + (const_int 16))))] + "TARGET_ARM && arm_arch5e" + "smultt%?\\t%0, %1, %2" + [(set_attr "type" "mult") + (set_attr "predicable" "yes")] ) (define_insn "*mulhisi3addsi" @@ -1350,9 +1371,10 @@ (match_operand:HI 2 "s_register_operand" "%r")) (sign_extend:SI (match_operand:HI 3 "s_register_operand" "r")))))] - "TARGET_ARM && arm_is_xscale" + "TARGET_ARM && arm_arch5e" "smlabb%?\\t%0, %2, %3, %1" - [(set_attr "type" "mult")] + [(set_attr "type" "mult") + (set_attr "predicable" "yes")] ) (define_insn "*mulhidi3adddi" @@ -1363,210 +1385,64 @@ (match_operand:HI 2 "s_register_operand" "%r")) (sign_extend:DI (match_operand:HI 3 "s_register_operand" "r")))))] - "TARGET_ARM && arm_is_xscale" + "TARGET_ARM && arm_arch5e" "smlalbb%?\\t%Q0, %R0, %2, %3" -[(set_attr "type" "mult")]) - -(define_insn "mulsf3" - [(set (match_operand:SF 0 "s_register_operand" "=f") - (mult:SF (match_operand:SF 1 "s_register_operand" "f") - (match_operand:SF 2 "fpu_rhs_operand" "fG")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "fml%?s\\t%0, %1, %2" - [(set_attr "type" "ffmul") - (set_attr "predicable" "yes")] -) - -(define_insn "muldf3" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (mult:DF (match_operand:DF 1 "s_register_operand" "f") - (match_operand:DF 2 "fpu_rhs_operand" "fG")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "muf%?d\\t%0, %1, %2" - [(set_attr "type" "fmul") - (set_attr "predicable" "yes")] -) - -(define_insn "*muldf_esfdf_df" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (mult:DF (float_extend:DF - (match_operand:SF 1 "s_register_operand" "f")) - (match_operand:DF 2 "fpu_rhs_operand" "fG")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "muf%?d\\t%0, %1, %2" - [(set_attr "type" "fmul") - (set_attr "predicable" "yes")] -) - -(define_insn "*muldf_df_esfdf" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (mult:DF (match_operand:DF 1 "s_register_operand" "f") - (float_extend:DF - (match_operand:SF 2 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "muf%?d\\t%0, %1, %2" - [(set_attr "type" "fmul") - (set_attr "predicable" "yes")] -) + [(set_attr "type" "mult") + (set_attr "predicable" "yes")]) -(define_insn "*muldf_esfdf_esfdf" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (mult:DF - (float_extend:DF (match_operand:SF 1 "s_register_operand" "f")) - (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "muf%?d\\t%0, %1, %2" - [(set_attr "type" "fmul") - (set_attr "predicable" "yes")] -) +(define_expand "mulsf3" + [(set (match_operand:SF 0 "s_register_operand" "") + (mult:SF (match_operand:SF 1 "s_register_operand" "") + (match_operand:SF 2 "fpa_rhs_operand" "")))] + "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + " + if (TARGET_CIRRUS + && !cirrus_fp_register (operands[2], SFmode)) + operands[2] = force_reg (SFmode, operands[2]); +") -(define_insn "mulxf3" - [(set (match_operand:XF 0 "s_register_operand" "=f") - (mult:XF (match_operand:XF 1 "s_register_operand" "f") - (match_operand:XF 2 "fpu_rhs_operand" "fG")))] - "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" - "muf%?e\\t%0, %1, %2" - [(set_attr "type" "fmul") - (set_attr "predicable" "yes")] -) +(define_expand "muldf3" + [(set (match_operand:DF 0 "s_register_operand" "") + (mult:DF (match_operand:DF 1 "s_register_operand" "") + (match_operand:DF 2 "fpa_rhs_operand" "")))] + "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + " + if (TARGET_CIRRUS + && !cirrus_fp_register (operands[2], DFmode)) + operands[2] = force_reg (DFmode, operands[2]); +") ;; Division insns -(define_insn "divsf3" - [(set (match_operand:SF 0 "s_register_operand" "=f,f") - (div:SF (match_operand:SF 1 "fpu_rhs_operand" "f,G") - (match_operand:SF 2 "fpu_rhs_operand" "fG,f")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "@ - fdv%?s\\t%0, %1, %2 - frd%?s\\t%0, %2, %1" - [(set_attr "type" "fdivs") - (set_attr "predicable" "yes")] -) - -(define_insn "divdf3" - [(set (match_operand:DF 0 "s_register_operand" "=f,f") - (div:DF (match_operand:DF 1 "fpu_rhs_operand" "f,G") - (match_operand:DF 2 "fpu_rhs_operand" "fG,f")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "@ - dvf%?d\\t%0, %1, %2 - rdf%?d\\t%0, %2, %1" - [(set_attr "type" "fdivd") - (set_attr "predicable" "yes")] -) - -(define_insn "*divdf_esfdf_df" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (div:DF (float_extend:DF - (match_operand:SF 1 "s_register_operand" "f")) - (match_operand:DF 2 "fpu_rhs_operand" "fG")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "dvf%?d\\t%0, %1, %2" - [(set_attr "type" "fdivd") - (set_attr "predicable" "yes")] -) - -(define_insn "*divdf_df_esfdf" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (div:DF (match_operand:DF 1 "fpu_rhs_operand" "fG") - (float_extend:DF - (match_operand:SF 2 "s_register_operand" "f"))))] +(define_expand "divsf3" + [(set (match_operand:SF 0 "s_register_operand" "") + (div:SF (match_operand:SF 1 "fpa_rhs_operand" "") + (match_operand:SF 2 "fpa_rhs_operand" "")))] "TARGET_ARM && TARGET_HARD_FLOAT" - "rdf%?d\\t%0, %2, %1" - [(set_attr "type" "fdivd") - (set_attr "predicable" "yes")] -) + "") -(define_insn "*divdf_esfdf_esfdf" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (div:DF (float_extend:DF - (match_operand:SF 1 "s_register_operand" "f")) - (float_extend:DF - (match_operand:SF 2 "s_register_operand" "f"))))] +(define_expand "divdf3" + [(set (match_operand:DF 0 "s_register_operand" "") + (div:DF (match_operand:DF 1 "fpa_rhs_operand" "") + (match_operand:DF 2 "fpa_rhs_operand" "")))] "TARGET_ARM && TARGET_HARD_FLOAT" - "dvf%?d\\t%0, %1, %2" - [(set_attr "type" "fdivd") - (set_attr "predicable" "yes")] -) - -(define_insn "divxf3" - [(set (match_operand:XF 0 "s_register_operand" "=f,f") - (div:XF (match_operand:XF 1 "fpu_rhs_operand" "f,G") - (match_operand:XF 2 "fpu_rhs_operand" "fG,f")))] - "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" - "@ - dvf%?e\\t%0, %1, %2 - rdf%?e\\t%0, %2, %1" - [(set_attr "type" "fdivx") - (set_attr "predicable" "yes")] -) + "") ;; Modulo insns -(define_insn "modsf3" - [(set (match_operand:SF 0 "s_register_operand" "=f") - (mod:SF (match_operand:SF 1 "s_register_operand" "f") - (match_operand:SF 2 "fpu_rhs_operand" "fG")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "rmf%?s\\t%0, %1, %2" - [(set_attr "type" "fdivs") - (set_attr "predicable" "yes")] -) - -(define_insn "moddf3" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (mod:DF (match_operand:DF 1 "s_register_operand" "f") - (match_operand:DF 2 "fpu_rhs_operand" "fG")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "rmf%?d\\t%0, %1, %2" - [(set_attr "type" "fdivd") - (set_attr "predicable" "yes")] -) - -(define_insn "*moddf_esfdf_df" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (mod:DF (float_extend:DF - (match_operand:SF 1 "s_register_operand" "f")) - (match_operand:DF 2 "fpu_rhs_operand" "fG")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "rmf%?d\\t%0, %1, %2" - [(set_attr "type" "fdivd") - (set_attr "predicable" "yes")] -) - -(define_insn "*moddf_df_esfdf" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (mod:DF (match_operand:DF 1 "s_register_operand" "f") - (float_extend:DF - (match_operand:SF 2 "s_register_operand" "f"))))] +(define_expand "modsf3" + [(set (match_operand:SF 0 "s_register_operand" "") + (mod:SF (match_operand:SF 1 "s_register_operand" "") + (match_operand:SF 2 "fpa_rhs_operand" "")))] "TARGET_ARM && TARGET_HARD_FLOAT" - "rmf%?d\\t%0, %1, %2" - [(set_attr "type" "fdivd") - (set_attr "predicable" "yes")] -) + "") -(define_insn "*moddf_esfdf_esfdf" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (mod:DF (float_extend:DF - (match_operand:SF 1 "s_register_operand" "f")) - (float_extend:DF - (match_operand:SF 2 "s_register_operand" "f"))))] +(define_expand "moddf3" + [(set (match_operand:DF 0 "s_register_operand" "") + (mod:DF (match_operand:DF 1 "s_register_operand" "") + (match_operand:DF 2 "fpa_rhs_operand" "")))] "TARGET_ARM && TARGET_HARD_FLOAT" - "rmf%?d\\t%0, %1, %2" - [(set_attr "type" "fdivd") - (set_attr "predicable" "yes")] -) - -(define_insn "modxf3" - [(set (match_operand:XF 0 "s_register_operand" "=f") - (mod:XF (match_operand:XF 1 "s_register_operand" "f") - (match_operand:XF 2 "fpu_rhs_operand" "fG")))] - "ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" - "rmf%?e\\t%0, %1, %2" - [(set_attr "type" "fdivx") - (set_attr "predicable" "yes")] -) + "") ;; Boolean and,ior,xor insns @@ -1579,7 +1455,7 @@ (match_operator:DI 6 "logical_binary_operator" [(match_operand:DI 1 "s_register_operand" "") (match_operand:DI 2 "s_register_operand" "")]))] - "TARGET_ARM && reload_completed" + "TARGET_ARM && reload_completed && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))" [(set (match_dup 0) (match_op_dup:SI 6 [(match_dup 1) (match_dup 2)])) (set (match_dup 3) (match_op_dup:SI 6 [(match_dup 4) (match_dup 5)]))] " @@ -1656,7 +1532,7 @@ [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (and:DI (match_operand:DI 1 "s_register_operand" "%0,r") (match_operand:DI 2 "s_register_operand" "r,r")))] - "TARGET_ARM" + "TARGET_ARM && ! TARGET_IWMMXT" "#" [(set_attr "length" "8")] ) @@ -1859,6 +1735,83 @@ (set_attr "length" "8")] ) +(define_split + [(set (match_operand:SI 0 "s_register_operand" "") + (zero_extract:SI (match_operand:SI 1 "s_register_operand" "") + (match_operand:SI 2 "const_int_operand" "") + (match_operand:SI 3 "const_int_operand" ""))) + (clobber (match_operand:SI 4 "s_register_operand" ""))] + "TARGET_THUMB" + [(set (match_dup 4) (ashift:SI (match_dup 1) (match_dup 2))) + (set (match_dup 0) (lshiftrt:SI (match_dup 4) (match_dup 3)))] + "{ + HOST_WIDE_INT temp = INTVAL (operands[2]); + + operands[2] = GEN_INT (32 - temp - INTVAL (operands[3])); + operands[3] = GEN_INT (32 - temp); + }" +) + +(define_split + [(set (match_operand:SI 0 "s_register_operand" "") + (match_operator:SI 1 "shiftable_operator" + [(zero_extract:SI (match_operand:SI 2 "s_register_operand" "") + (match_operand:SI 3 "const_int_operand" "") + (match_operand:SI 4 "const_int_operand" "")) + (match_operand:SI 5 "s_register_operand" "")])) + (clobber (match_operand:SI 6 "s_register_operand" ""))] + "TARGET_ARM" + [(set (match_dup 6) (ashift:SI (match_dup 2) (match_dup 3))) + (set (match_dup 0) + (match_op_dup 1 + [(lshiftrt:SI (match_dup 6) (match_dup 4)) + (match_dup 5)]))] + "{ + HOST_WIDE_INT temp = INTVAL (operands[3]); + + operands[3] = GEN_INT (32 - temp - INTVAL (operands[4])); + operands[4] = GEN_INT (32 - temp); + }" +) + +(define_split + [(set (match_operand:SI 0 "s_register_operand" "") + (sign_extract:SI (match_operand:SI 1 "s_register_operand" "") + (match_operand:SI 2 "const_int_operand" "") + (match_operand:SI 3 "const_int_operand" "")))] + "TARGET_THUMB" + [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2))) + (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 3)))] + "{ + HOST_WIDE_INT temp = INTVAL (operands[2]); + + operands[2] = GEN_INT (32 - temp - INTVAL (operands[3])); + operands[3] = GEN_INT (32 - temp); + }" +) + +(define_split + [(set (match_operand:SI 0 "s_register_operand" "") + (match_operator:SI 1 "shiftable_operator" + [(sign_extract:SI (match_operand:SI 2 "s_register_operand" "") + (match_operand:SI 3 "const_int_operand" "") + (match_operand:SI 4 "const_int_operand" "")) + (match_operand:SI 5 "s_register_operand" "")])) + (clobber (match_operand:SI 6 "s_register_operand" ""))] + "TARGET_ARM" + [(set (match_dup 6) (ashift:SI (match_dup 2) (match_dup 3))) + (set (match_dup 0) + (match_op_dup 1 + [(ashiftrt:SI (match_dup 6) (match_dup 4)) + (match_dup 5)]))] + "{ + HOST_WIDE_INT temp = INTVAL (operands[3]); + + operands[3] = GEN_INT (32 - temp - INTVAL (operands[4])); + operands[4] = GEN_INT (32 - temp); + }" +) + ;;; ??? This pattern is bogus. If operand3 has bits outside the range ;;; represented by the bitfield, then this will produce incorrect results. ;;; Somewhere, the value needs to be truncated. On targets like the m68k, @@ -1918,7 +1871,7 @@ /* A Trick, since we are setting the bottom bits in the word, we can shift operand[3] up, operand[0] down, OR them together and rotate the result back again. This takes 3 insns, and - the third might be mergable into another op. */ + the third might be mergeable into another op. */ /* The shift up copes with the possibility that operand[3] is wider than the bitfield. */ rtx op0 = gen_reg_rtx (SImode); @@ -2010,7 +1963,7 @@ (match_operand:DI 2 "s_register_operand" "0,r")))] "TARGET_ARM" "#" - "TARGET_ARM && reload_completed" + "TARGET_ARM && reload_completed && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))" [(set (match_dup 0) (and:SI (not:SI (match_dup 1)) (match_dup 2))) (set (match_dup 3) (and:SI (not:SI (match_dup 4)) (match_dup 5)))] " @@ -2136,7 +2089,7 @@ [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (ior:DI (match_operand:DI 1 "s_register_operand" "%0,r") (match_operand:DI 2 "s_register_operand" "r,r")))] - "TARGET_ARM" + "TARGET_ARM && ! TARGET_IWMMXT" "#" [(set_attr "length" "8") (set_attr "predicable" "yes")] @@ -2258,7 +2211,7 @@ [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (xor:DI (match_operand:DI 1 "s_register_operand" "%0,r") (match_operand:DI 2 "s_register_operand" "r,r")))] - "TARGET_ARM" + "TARGET_ARM && !TARGET_IWMMXT" "#" [(set_attr "length" "8") (set_attr "predicable" "yes")] @@ -2367,6 +2320,109 @@ (set_attr "predicable" "yes")] ) +(define_split + [(set (match_operand:SI 0 "s_register_operand" "") + (match_operator:SI 1 "logical_binary_operator" + [(zero_extract:SI (match_operand:SI 2 "s_register_operand" "") + (match_operand:SI 3 "const_int_operand" "") + (match_operand:SI 4 "const_int_operand" "")) + (match_operator:SI 9 "logical_binary_operator" + [(lshiftrt:SI (match_operand:SI 5 "s_register_operand" "") + (match_operand:SI 6 "const_int_operand" "")) + (match_operand:SI 7 "s_register_operand" "")])])) + (clobber (match_operand:SI 8 "s_register_operand" ""))] + "TARGET_ARM + && GET_CODE (operands[1]) == GET_CODE (operands[9]) + && INTVAL (operands[3]) == 32 - INTVAL (operands[6])" + [(set (match_dup 8) + (match_op_dup 1 + [(ashift:SI (match_dup 2) (match_dup 4)) + (match_dup 5)])) + (set (match_dup 0) + (match_op_dup 1 + [(lshiftrt:SI (match_dup 8) (match_dup 6)) + (match_dup 7)]))] + " + operands[4] = GEN_INT (32 - (INTVAL (operands[3]) + INTVAL (operands[4]))); +") + +(define_split + [(set (match_operand:SI 0 "s_register_operand" "") + (match_operator:SI 1 "logical_binary_operator" + [(match_operator:SI 9 "logical_binary_operator" + [(lshiftrt:SI (match_operand:SI 5 "s_register_operand" "") + (match_operand:SI 6 "const_int_operand" "")) + (match_operand:SI 7 "s_register_operand" "")]) + (zero_extract:SI (match_operand:SI 2 "s_register_operand" "") + (match_operand:SI 3 "const_int_operand" "") + (match_operand:SI 4 "const_int_operand" ""))])) + (clobber (match_operand:SI 8 "s_register_operand" ""))] + "TARGET_ARM + && GET_CODE (operands[1]) == GET_CODE (operands[9]) + && INTVAL (operands[3]) == 32 - INTVAL (operands[6])" + [(set (match_dup 8) + (match_op_dup 1 + [(ashift:SI (match_dup 2) (match_dup 4)) + (match_dup 5)])) + (set (match_dup 0) + (match_op_dup 1 + [(lshiftrt:SI (match_dup 8) (match_dup 6)) + (match_dup 7)]))] + " + operands[4] = GEN_INT (32 - (INTVAL (operands[3]) + INTVAL (operands[4]))); +") + +(define_split + [(set (match_operand:SI 0 "s_register_operand" "") + (match_operator:SI 1 "logical_binary_operator" + [(sign_extract:SI (match_operand:SI 2 "s_register_operand" "") + (match_operand:SI 3 "const_int_operand" "") + (match_operand:SI 4 "const_int_operand" "")) + (match_operator:SI 9 "logical_binary_operator" + [(ashiftrt:SI (match_operand:SI 5 "s_register_operand" "") + (match_operand:SI 6 "const_int_operand" "")) + (match_operand:SI 7 "s_register_operand" "")])])) + (clobber (match_operand:SI 8 "s_register_operand" ""))] + "TARGET_ARM + && GET_CODE (operands[1]) == GET_CODE (operands[9]) + && INTVAL (operands[3]) == 32 - INTVAL (operands[6])" + [(set (match_dup 8) + (match_op_dup 1 + [(ashift:SI (match_dup 2) (match_dup 4)) + (match_dup 5)])) + (set (match_dup 0) + (match_op_dup 1 + [(ashiftrt:SI (match_dup 8) (match_dup 6)) + (match_dup 7)]))] + " + operands[4] = GEN_INT (32 - (INTVAL (operands[3]) + INTVAL (operands[4]))); +") + +(define_split + [(set (match_operand:SI 0 "s_register_operand" "") + (match_operator:SI 1 "logical_binary_operator" + [(match_operator:SI 9 "logical_binary_operator" + [(ashiftrt:SI (match_operand:SI 5 "s_register_operand" "") + (match_operand:SI 6 "const_int_operand" "")) + (match_operand:SI 7 "s_register_operand" "")]) + (sign_extract:SI (match_operand:SI 2 "s_register_operand" "") + (match_operand:SI 3 "const_int_operand" "") + (match_operand:SI 4 "const_int_operand" ""))])) + (clobber (match_operand:SI 8 "s_register_operand" ""))] + "TARGET_ARM + && GET_CODE (operands[1]) == GET_CODE (operands[9]) + && INTVAL (operands[3]) == 32 - INTVAL (operands[6])" + [(set (match_dup 8) + (match_op_dup 1 + [(ashift:SI (match_dup 2) (match_dup 4)) + (match_dup 5)])) + (set (match_dup 0) + (match_op_dup 1 + [(ashiftrt:SI (match_dup 8) (match_dup 6)) + (match_dup 7)]))] + " + operands[4] = GEN_INT (32 - (INTVAL (operands[3]) + INTVAL (operands[4]))); +") ;; Minimum and maximum insns @@ -2596,6 +2652,19 @@ [(set_attr "length" "2")] ) +(define_expand "ashldi3" + [(set (match_operand:DI 0 "s_register_operand" "") + (ashift:DI (match_operand:DI 1 "general_operand" "") + (match_operand:SI 2 "general_operand" "")))] + "TARGET_ARM && (TARGET_IWMMXT || TARGET_CIRRUS)" + " + if (! s_register_operand (operands[1], DImode)) + operands[1] = copy_to_mode_reg (DImode, operands[1]); + if (! s_register_operand (operands[2], SImode)) + operands[2] = copy_to_mode_reg (SImode, operands[2]); + " +) + (define_insn "*arm_shiftsi3" [(set (match_operand:SI 0 "s_register_operand" "=r") (match_operator:SI 3 "shift_operator" @@ -2769,49 +2838,33 @@ [(set_attr "length" "2")] ) -(define_insn "negsf2" - [(set (match_operand:SF 0 "s_register_operand" "=f") - (neg:SF (match_operand:SF 1 "s_register_operand" "f")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "mnf%?s\\t%0, %1" - [(set_attr "type" "ffarith") - (set_attr "predicable" "yes")] -) - -(define_insn "negdf2" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (neg:DF (match_operand:DF 1 "s_register_operand" "f")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "mnf%?d\\t%0, %1" - [(set_attr "type" "ffarith") - (set_attr "predicable" "yes")] -) - -(define_insn "*negdf_esfdf" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (neg:DF (float_extend:DF - (match_operand:SF 1 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "mnf%?d\\t%0, %1" - [(set_attr "type" "ffarith") - (set_attr "predicable" "yes")] +(define_expand "negsf2" + [(set (match_operand:SF 0 "s_register_operand" "") + (neg:SF (match_operand:SF 1 "s_register_operand" "")))] + "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "" ) -(define_insn "negxf2" - [(set (match_operand:XF 0 "s_register_operand" "=f") - (neg:XF (match_operand:XF 1 "s_register_operand" "f")))] - "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" - "mnf%?e\\t%0, %1" - [(set_attr "type" "ffarith") - (set_attr "predicable" "yes")] -) +(define_expand "negdf2" + [(set (match_operand:DF 0 "s_register_operand" "") + (neg:DF (match_operand:DF 1 "s_register_operand" "")))] + "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "") ;; abssi2 doesn't really clobber the condition codes if a different register ;; is being set. To keep things simple, assume during rtl manipulations that ;; it does, but tell the final scan operator the truth. Similarly for ;; (neg (abs...)) -(define_insn "abssi2" +(define_expand "abssi2" + [(parallel + [(set (match_operand:SI 0 "s_register_operand" "") + (abs:SI (match_operand:SI 1 "s_register_operand" ""))) + (clobber (reg:CC CC_REGNUM))])] + "TARGET_ARM" + "") + +(define_insn "*arm_abssi2" [(set (match_operand:SI 0 "s_register_operand" "=r,&r") (abs:SI (match_operand:SI 1 "s_register_operand" "0,r"))) (clobber (reg:CC CC_REGNUM))] @@ -2839,147 +2892,29 @@ (set_attr "length" "8")] ) -(define_insn "abssf2" - [(set (match_operand:SF 0 "s_register_operand" "=f") - (abs:SF (match_operand:SF 1 "s_register_operand" "f")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "abs%?s\\t%0, %1" - [(set_attr "type" "ffarith") - (set_attr "predicable" "yes")] -) - -(define_insn "absdf2" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (abs:DF (match_operand:DF 1 "s_register_operand" "f")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "abs%?d\\t%0, %1" - [(set_attr "type" "ffarith") - (set_attr "predicable" "yes")] -) - -(define_insn "*absdf_esfdf" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (abs:DF (float_extend:DF - (match_operand:SF 1 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "abs%?d\\t%0, %1" - [(set_attr "type" "ffarith") - (set_attr "predicable" "yes")] -) - -(define_insn "absxf2" - [(set (match_operand:XF 0 "s_register_operand" "=f") - (abs:XF (match_operand:XF 1 "s_register_operand" "f")))] - "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" - "abs%?e\\t%0, %1" - [(set_attr "type" "ffarith") - (set_attr "predicable" "yes")] -) +(define_expand "abssf2" + [(set (match_operand:SF 0 "s_register_operand" "") + (abs:SF (match_operand:SF 1 "s_register_operand" "")))] + "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "") -(define_insn "sqrtsf2" - [(set (match_operand:SF 0 "s_register_operand" "=f") - (sqrt:SF (match_operand:SF 1 "s_register_operand" "f")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "sqt%?s\\t%0, %1" - [(set_attr "type" "float_em") - (set_attr "predicable" "yes")] -) +(define_expand "absdf2" + [(set (match_operand:DF 0 "s_register_operand" "") + (abs:DF (match_operand:DF 1 "s_register_operand" "")))] + "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "") -(define_insn "sqrtdf2" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (sqrt:DF (match_operand:DF 1 "s_register_operand" "f")))] +(define_expand "sqrtsf2" + [(set (match_operand:SF 0 "s_register_operand" "") + (sqrt:SF (match_operand:SF 1 "s_register_operand" "")))] "TARGET_ARM && TARGET_HARD_FLOAT" - "sqt%?d\\t%0, %1" - [(set_attr "type" "float_em") - (set_attr "predicable" "yes")] -) + "") -(define_insn "*sqrtdf_esfdf" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (sqrt:DF (float_extend:DF - (match_operand:SF 1 "s_register_operand" "f"))))] +(define_expand "sqrtdf2" + [(set (match_operand:DF 0 "s_register_operand" "") + (sqrt:DF (match_operand:DF 1 "s_register_operand" "")))] "TARGET_ARM && TARGET_HARD_FLOAT" - "sqt%?d\\t%0, %1" - [(set_attr "type" "float_em") - (set_attr "predicable" "yes")] -) - -(define_insn "sqrtxf2" - [(set (match_operand:XF 0 "s_register_operand" "=f") - (sqrt:XF (match_operand:XF 1 "s_register_operand" "f")))] - "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" - "sqt%?e\\t%0, %1" - [(set_attr "type" "float_em") - (set_attr "predicable" "yes")] -) - -;; SIN COS TAN and family are always emulated, so it's probably better -;; to always call a library function. -;(define_insn "sinsf2" -; [(set (match_operand:SF 0 "s_register_operand" "=f") -; (unspec:SF [(match_operand:SF 1 "s_register_operand" "f")] -; UNSPEC_SIN))] -; "TARGET_ARM && TARGET_HARD_FLOAT" -; "sin%?s\\t%0, %1" -;[(set_attr "type" "float_em")]) -; -;(define_insn "sindf2" -; [(set (match_operand:DF 0 "s_register_operand" "=f") -; (unspec:DF [(match_operand:DF 1 "s_register_operand" "f")] -; UNSPEC_SIN))] -; "TARGET_ARM && TARGET_HARD_FLOAT" -; "sin%?d\\t%0, %1" -;[(set_attr "type" "float_em")]) -; -;(define_insn "*sindf_esfdf" -; [(set (match_operand:DF 0 "s_register_operand" "=f") -; (unspec:DF [(float_extend:DF -; (match_operand:SF 1 "s_register_operand" "f"))] -; UNSPEC_SIN))] -; "TARGET_ARM && TARGET_HARD_FLOAT" -; "sin%?d\\t%0, %1" -;[(set_attr "type" "float_em")]) -; -;(define_insn "sinxf2" -; [(set (match_operand:XF 0 "s_register_operand" "=f") -; (unspec:XF [(match_operand:XF 1 "s_register_operand" "f")] -; UNSPEC_SIN))] -; "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" -; "sin%?e\\t%0, %1" -;[(set_attr "type" "float_em")]) -; -;(define_insn "cossf2" -; [(set (match_operand:SF 0 "s_register_operand" "=f") -; (unspec:SF [(match_operand:SF 1 "s_register_operand" "f")] -; UNSPEC_COS))] -; "TARGET_ARM && TARGET_HARD_FLOAT" -; "cos%?s\\t%0, %1" -;[(set_attr "type" "float_em")]) -; -;(define_insn "cosdf2" -; [(set (match_operand:DF 0 "s_register_operand" "=f") -; (unspec:DF [(match_operand:DF 1 "s_register_operand" "f")] -; UNSPEC_COS))] -; "TARGET_ARM && TARGET_HARD_FLOAT" -; "cos%?d\\t%0, %1" -;[(set_attr "type" "float_em")]) -; -;(define_insn "*cosdf_esfdf" -; [(set (match_operand:DF 0 "s_register_operand" "=f") -; (unspec:DF [(float_extend:DF -; (match_operand:SF 1 "s_register_operand" "f"))] -; UNSPEC_COS))] -; "TARGET_ARM && TARGET_HARD_FLOAT" -; "cos%?d\\t%0, %1" -;[(set_attr "type" "float_em")]) -; -;(define_insn "cosxf2" -; [(set (match_operand:XF 0 "s_register_operand" "=f") -; (unspec:XF [(match_operand:XF 1 "s_register_operand" "f")] -; UNSEPC_COS))] -; "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" -; "cos%?e\\t%0, %1" -;[(set_attr "type" "float_em")]) + "") (define_insn_and_split "one_cmpldi2" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") @@ -3046,90 +2981,68 @@ ;; Fixed <--> Floating conversion insns -(define_insn "floatsisf2" - [(set (match_operand:SF 0 "s_register_operand" "=f") - (float:SF (match_operand:SI 1 "s_register_operand" "r")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "flt%?s\\t%0, %1" - [(set_attr "type" "r_2_f") - (set_attr "predicable" "yes")] -) - -(define_insn "floatsidf2" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (float:DF (match_operand:SI 1 "s_register_operand" "r")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "flt%?d\\t%0, %1" - [(set_attr "type" "r_2_f") - (set_attr "predicable" "yes")] -) - -(define_insn "floatsixf2" - [(set (match_operand:XF 0 "s_register_operand" "=f") - (float:XF (match_operand:SI 1 "s_register_operand" "r")))] - "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" - "flt%?e\\t%0, %1" - [(set_attr "type" "r_2_f") - (set_attr "predicable" "yes")] -) +(define_expand "floatsisf2" + [(set (match_operand:SF 0 "s_register_operand" "") + (float:SF (match_operand:SI 1 "s_register_operand" "")))] + "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + " + if (TARGET_CIRRUS) + { + emit_insn (gen_cirrus_floatsisf2 (operands[0], operands[1])); + DONE; + } +") -(define_insn "fix_truncsfsi2" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (fix:SI (match_operand:SF 1 "s_register_operand" "f")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "fix%?z\\t%0, %1" - [(set_attr "type" "f_2_r") - (set_attr "predicable" "yes")] -) +(define_expand "floatsidf2" + [(set (match_operand:DF 0 "s_register_operand" "") + (float:DF (match_operand:SI 1 "s_register_operand" "")))] + "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + " + if (TARGET_CIRRUS) + { + emit_insn (gen_cirrus_floatsidf2 (operands[0], operands[1])); + DONE; + } +") -(define_insn "fix_truncdfsi2" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (fix:SI (match_operand:DF 1 "s_register_operand" "f")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "fix%?z\\t%0, %1" - [(set_attr "type" "f_2_r") - (set_attr "predicable" "yes")] -) +(define_expand "fix_truncsfsi2" + [(set (match_operand:SI 0 "s_register_operand" "") + (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" ""))))] + "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + " + if (TARGET_CIRRUS) + { + if (!cirrus_fp_register (operands[0], SImode)) + operands[0] = force_reg (SImode, operands[0]); + if (!cirrus_fp_register (operands[1], SFmode)) + operands[1] = force_reg (SFmode, operands[0]); + emit_insn (gen_cirrus_truncsfsi2 (operands[0], operands[1])); + DONE; + } +") -(define_insn "fix_truncxfsi2" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (fix:SI (match_operand:XF 1 "s_register_operand" "f")))] - "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" - "fix%?z\\t%0, %1" - [(set_attr "type" "f_2_r") - (set_attr "predicable" "yes")] -) +(define_expand "fix_truncdfsi2" + [(set (match_operand:SI 0 "s_register_operand" "") + (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" ""))))] + "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + " + if (TARGET_CIRRUS) + { + if (!cirrus_fp_register (operands[1], DFmode)) + operands[1] = force_reg (DFmode, operands[0]); + emit_insn (gen_cirrus_truncdfsi2 (operands[0], operands[1])); + DONE; + } +") ;; Truncation insns -(define_insn "truncdfsf2" - [(set (match_operand:SF 0 "s_register_operand" "=f") - (float_truncate:SF - (match_operand:DF 1 "s_register_operand" "f")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "mvf%?s\\t%0, %1" - [(set_attr "type" "ffarith") - (set_attr "predicable" "yes")] -) - -(define_insn "truncxfsf2" - [(set (match_operand:SF 0 "s_register_operand" "=f") +(define_expand "truncdfsf2" + [(set (match_operand:SF 0 "s_register_operand" "") (float_truncate:SF - (match_operand:XF 1 "s_register_operand" "f")))] - "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" - "mvf%?s\\t%0, %1" - [(set_attr "type" "ffarith") - (set_attr "predicable" "yes")] -) - -(define_insn "truncxfdf2" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (float_truncate:DF - (match_operand:XF 1 "s_register_operand" "f")))] - "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" - "mvf%?d\\t%0, %1" - [(set_attr "type" "ffarith") - (set_attr "predicable" "yes")] + (match_operand:DF 1 "s_register_operand" "")))] + "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "" ) ;; Zero and sign extension instructions. @@ -3632,7 +3545,7 @@ (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))] "TARGET_ARM && arm_arch4" "* - /* If the address is invalid, this will split the instruction into two. */ + /* If the address is invalid, this will split the instruction into two. */ if (bad_signed_byte_operand (operands[1], VOIDmode)) return \"#\"; return \"ldr%?sb\\t%0, %1\"; @@ -3668,7 +3581,7 @@ XEXP (operands[2], 0) = plus_constant (operands[3], low); operands[1] = plus_constant (XEXP (operands[1], 0), offset - low); } - /* Ensure the sum is in correct canonical form */ + /* Ensure the sum is in correct canonical form. */ else if (GET_CODE (operands[1]) == PLUS && GET_CODE (XEXP (operands[1], 1)) != CONST_INT && !s_register_operand (XEXP (operands[1], 1), VOIDmode)) @@ -3730,7 +3643,7 @@ (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] "TARGET_ARM && arm_arch4" "* - /* If the address is invalid, this will split the instruction into two. */ + /* If the address is invalid, this will split the instruction into two. */ if (bad_signed_byte_operand (operands[1], VOIDmode)) return \"#\"; return \"ldr%?sb\\t%0, %1\"; @@ -3765,7 +3678,7 @@ XEXP (operands[2], 0) = plus_constant (operands[0], low); operands[1] = plus_constant (XEXP (operands[1], 0), offset - low); } - /* Ensure the sum is in correct canonical form */ + /* Ensure the sum is in correct canonical form. */ else if (GET_CODE (operands[1]) == PLUS && GET_CODE (XEXP (operands[1], 1)) != CONST_INT && !s_register_operand (XEXP (operands[1], 1), VOIDmode)) @@ -3854,33 +3767,12 @@ (set_attr "pool_range" "32,32")] ) -(define_insn "extendsfdf2" - [(set (match_operand:DF 0 "s_register_operand" "=f") - (float_extend:DF (match_operand:SF 1 "s_register_operand" "f")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "mvf%?d\\t%0, %1" - [(set_attr "type" "ffarith") - (set_attr "predicable" "yes")] -) - -(define_insn "extendsfxf2" - [(set (match_operand:XF 0 "s_register_operand" "=f") - (float_extend:XF (match_operand:SF 1 "s_register_operand" "f")))] - "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" - "mvf%?e\\t%0, %1" - [(set_attr "type" "ffarith") - (set_attr "predicable" "yes")] -) - -(define_insn "extenddfxf2" - [(set (match_operand:XF 0 "s_register_operand" "=f") - (float_extend:XF (match_operand:DF 1 "s_register_operand" "f")))] - "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" - "mvf%?e\\t%0, %1" - [(set_attr "type" "ffarith") - (set_attr "predicable" "yes")] +(define_expand "extendsfdf2" + [(set (match_operand:DF 0 "s_register_operand" "") + (float_extend:DF (match_operand:SF 1 "s_register_operand" "")))] + "TARGET_ARM && TARGET_ANY_HARD_FLOAT" + "" ) - ;; Move insns (including loads and stores) @@ -3962,7 +3854,7 @@ (define_insn "*arm_movdi" [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, o<>") (match_operand:DI 1 "di_operand" "rIK,mi,r"))] - "TARGET_ARM" + "TARGET_ARM && !TARGET_CIRRUS && ! TARGET_IWMMXT" "* return (output_move_double (operands)); " @@ -3980,6 +3872,7 @@ [(set (match_operand:DI 0 "nonimmediate_operand" "=l,l,l,l,>,l, m,*r") (match_operand:DI 1 "general_operand" "l, I,J,>,l,mi,l,*r"))] "TARGET_THUMB + && !TARGET_CIRRUS && ( register_operand (operands[0], DImode) || register_operand (operands[1], DImode))" "* @@ -4025,7 +3918,7 @@ " if (TARGET_ARM) { - /* Everything except mem = const or mem = mem can be done easily */ + /* Everything except mem = const or mem = mem can be done easily. */ if (GET_CODE (operands[0]) == MEM) operands[1] = force_reg (SImode, operands[1]); if (GET_CODE (operands[1]) == CONST_INT @@ -4039,7 +3932,7 @@ DONE; } } - else /* TARGET_THUMB.... */ + else /* TARGET_THUMB.... */ { if (!no_new_pseudos) { @@ -4060,7 +3953,7 @@ (define_insn "*arm_movsi_insn" [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m") (match_operand:SI 1 "general_operand" "rI,K,mi,r"))] - "TARGET_ARM + "TARGET_ARM && ! TARGET_IWMMXT && ( register_operand (operands[0], SImode) || register_operand (operands[1], SImode))" "@ @@ -4174,7 +4067,7 @@ ;; This variant is used for AOF assembly, since it needs to mention the ;; pic register in the rtl. (define_expand "pic_load_addr_based" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "") (unspec:SI [(match_operand 1 "" "") (match_dup 2)] UNSPEC_PIC_SYM))] "TARGET_ARM && flag_pic" "operands[2] = pic_offset_table_rtx;" @@ -4212,7 +4105,7 @@ (use (label_ref (match_operand 1 "" "")))] "TARGET_THUMB && flag_pic" "* - ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", + (*targetm.asm_out.internal_label) (asm_out_file, \"L\", CODE_LABEL_NUMBER (operands[1])); return \"add\\t%0, %|pc\"; " @@ -4227,7 +4120,7 @@ (use (label_ref (match_operand 1 "" "")))] "TARGET_ARM && flag_pic" "* - ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", + (*targetm.asm_out.internal_label) (asm_out_file, \"L\", CODE_LABEL_NUMBER (operands[1])); return \"add%?\\t%0, %|pc, %0\"; " @@ -4275,7 +4168,7 @@ (set (match_dup 2) (ashiftrt:SI (match_operand 0 "" "") (const_int 8))) ;; store the high byte - (set (match_dup 4) (subreg:QI (match_dup 2) 0))] ;explicit subreg safe + (set (match_dup 4) (match_dup 5))] "TARGET_ARM" " { @@ -4291,7 +4184,8 @@ operands[1] = adjust_address (operands[1], QImode, 0); operands[3] = gen_lowpart (QImode, operands[0]); operands[0] = gen_lowpart (SImode, operands[0]); - operands[2] = gen_reg_rtx (SImode); + operands[2] = gen_reg_rtx (SImode); + operands[5] = gen_lowpart (QImode, operands[2]); }" ) @@ -4299,7 +4193,7 @@ [(set (match_dup 4) (match_dup 3)) (set (match_dup 2) (ashiftrt:SI (match_operand 0 "" "") (const_int 8))) - (set (match_operand 1 "" "") (subreg:QI (match_dup 2) 3))] + (set (match_operand 1 "" "") (match_dup 5))] "TARGET_ARM" " { @@ -4316,13 +4210,14 @@ operands[3] = gen_lowpart (QImode, operands[0]); operands[0] = gen_lowpart (SImode, operands[0]); operands[2] = gen_reg_rtx (SImode); + operands[5] = gen_lowpart (QImode, operands[2]); }" ) ;; Subroutine to store a half word integer constant into memory. (define_expand "storeinthi" [(set (match_operand 0 "" "") - (subreg:QI (match_operand 1 "" "") 0)) + (match_operand 1 "" "")) (set (match_dup 3) (match_dup 2))] "TARGET_ARM" " @@ -4363,6 +4258,7 @@ operands[3] = adjust_address (op0, QImode, 1); operands[0] = adjust_address (operands[0], QImode, 0); operands[2] = gen_lowpart (QImode, operands[2]); + operands[1] = gen_lowpart (QImode, operands[1]); }" ) @@ -4523,7 +4419,7 @@ } } } - /* Handle loading a large integer during reload */ + /* Handle loading a large integer during reload. */ else if (GET_CODE (operands[1]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[1])) && !const_ok_for_arm (~INTVAL (operands[1]))) @@ -4567,7 +4463,7 @@ = replace_equiv_address (operands[1], copy_to_reg (XEXP (operands[1], 0))); } - /* Handle loading a large integer during reload */ + /* Handle loading a large integer during reload. */ else if (GET_CODE (operands[1]) == CONST_INT && !CONST_OK_FOR_THUMB_LETTER (INTVAL (operands[1]), 'I')) { @@ -4585,8 +4481,8 @@ ) (define_insn "*thumb_movhi_insn" - [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l, m,*r,*h,l") - (match_operand:HI 1 "general_operand" "l,mn,l,*h,*r,I"))] + [(set (match_operand:HI 0 "nonimmediate_operand" "=l,l,m,*r,*h,l") + (match_operand:HI 1 "general_operand" "l,m,l,*h,*r,I"))] "TARGET_THUMB && ( register_operand (operands[0], HImode) || register_operand (operands[1], HImode))" @@ -4618,8 +4514,7 @@ return \"ldrh %0, %1\"; }" [(set_attr "length" "2,4,2,2,2,2") - (set_attr "type" "*,load,store1,*,*,*") - (set_attr "pool_range" "*,64,*,*,*,*")] + (set_attr "type" "*,load,store1,*,*,*")] ) @@ -4683,11 +4578,12 @@ (set (match_dup 3) (ashiftrt:SI (match_dup 2) (const_int 16))) (set (match_operand:HI 0 "s_register_operand" "") - (subreg:HI (match_dup 3) 0))] + (match_dup 4))] "TARGET_ARM" " operands[2] = gen_reg_rtx (SImode); operands[3] = gen_reg_rtx (SImode); + operands[4] = gen_lowpart (HImode, operands[3]); " ) @@ -4871,7 +4767,7 @@ = replace_equiv_address (operands[1], copy_to_reg (XEXP (operands[1], 0))); } - /* Handle loading a large integer during reload */ + /* Handle loading a large integer during reload. */ else if (GET_CODE (operands[1]) == CONST_INT && !CONST_OK_FOR_LETTER_P (INTVAL (operands[1]), 'I')) { @@ -4959,39 +4855,11 @@ " ) -(define_insn "*arm_movsf_hard_insn" - [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f, m,f,r,r,r, m") - (match_operand:SF 1 "general_operand" "fG,H,mE,f,r,f,r,mE,r"))] - "TARGET_ARM - && TARGET_HARD_FLOAT - && (GET_CODE (operands[0]) != MEM - || register_operand (operands[1], SFmode))" - "@ - mvf%?s\\t%0, %1 - mnf%?s\\t%0, #%N1 - ldf%?s\\t%0, %1 - stf%?s\\t%1, %0 - str%?\\t%1, [%|sp, #-4]!\;ldf%?s\\t%0, [%|sp], #4 - stf%?s\\t%1, [%|sp, #-4]!\;ldr%?\\t%0, [%|sp], #4 - mov%?\\t%0, %1 - ldr%?\\t%0, %1\\t%@ float - str%?\\t%1, %0\\t%@ float" - [(set_attr "length" "4,4,4,4,8,8,4,4,4") - (set_attr "predicable" "yes") - (set_attr "type" - "ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*,load,store1") - (set_attr "pool_range" "*,*,1024,*,*,*,*,4096,*") - (set_attr "neg_pool_range" "*,*,1012,*,*,*,*,4084,*")] -) - -;; Exactly the same as above, except that all `f' cases are deleted. -;; This is necessary to prevent reload from ever trying to use a `f' reg -;; when -msoft-float. - (define_insn "*arm_movsf_soft_insn" [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m") (match_operand:SF 1 "general_operand" "r,mE,r"))] "TARGET_ARM + && !TARGET_CIRRUS && TARGET_SOFT_FLOAT && (GET_CODE (operands[0]) != MEM || register_operand (operands[1], SFmode))" @@ -5090,48 +4958,11 @@ }" ) -(define_insn "*movdf_hard_insn" - [(set (match_operand:DF 0 "nonimmediate_operand" - "=r,Q,r,m,r, f, f,f, m,!f,!r") - (match_operand:DF 1 "general_operand" - "Q, r,r,r,mF,fG,H,mF,f,r, f"))] - "TARGET_ARM - && TARGET_HARD_FLOAT - && (GET_CODE (operands[0]) != MEM - || register_operand (operands[1], DFmode))" - "* - { - switch (which_alternative) - { - default: - case 0: return \"ldm%?ia\\t%m1, %M0\\t%@ double\"; - case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\"; - case 2: case 3: case 4: return output_move_double (operands); - case 5: return \"mvf%?d\\t%0, %1\"; - case 6: return \"mnf%?d\\t%0, #%N1\"; - case 7: return \"ldf%?d\\t%0, %1\"; - case 8: return \"stf%?d\\t%1, %0\"; - case 9: return output_mov_double_fpu_from_arm (operands); - case 10: return output_mov_double_arm_from_fpu (operands); - } - } - " - [(set_attr "length" "4,4,8,8,8,4,4,4,4,8,8") - (set_attr "predicable" "yes") - (set_attr "type" - "load,store2,*,store2,load,ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r") - (set_attr "pool_range" "*,*,*,*,1020,*,*,1024,*,*,*") - (set_attr "neg_pool_range" "*,*,*,*,1008,*,*,1008,*,*,*")] -) - -;; Software floating point version. This is essentially the same as movdi. -;; Do not use `f' as a constraint to prevent reload from ever trying to use -;; an `f' reg. - (define_insn "*movdf_soft_insn" [(set (match_operand:DF 0 "nonimmediate_soft_df_operand" "=r,r,m") (match_operand:DF 1 "soft_df_operand" "r,mF,r"))] "TARGET_ARM && TARGET_SOFT_FLOAT + && !TARGET_CIRRUS " "* return output_move_double (operands);" [(set_attr "length" "8,8,8") @@ -5180,39 +5011,27 @@ (set_attr "pool_range" "*,*,*,1020,*,*")] ) +;; Vector Moves +(define_expand "movv2si" + [(set (match_operand:V2SI 0 "nonimmediate_operand" "") + (match_operand:V2SI 1 "general_operand" ""))] + "TARGET_REALLY_IWMMXT" +{ +}) -(define_expand "movxf" - [(set (match_operand:XF 0 "general_operand" "") - (match_operand:XF 1 "general_operand" ""))] - "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" - "") - -;; Even when the XFmode patterns aren't enabled, we enable this after -;; reloading so that we can push floating point registers in the prologue. +(define_expand "movv4hi" + [(set (match_operand:V4HI 0 "nonimmediate_operand" "") + (match_operand:V4HI 1 "general_operand" ""))] + "TARGET_REALLY_IWMMXT" +{ +}) -(define_insn "*movxf_hard_insn" - [(set (match_operand:XF 0 "nonimmediate_operand" "=f,f,f,m,f,r,r") - (match_operand:XF 1 "general_operand" "fG,H,m,f,r,f,r"))] - "TARGET_ARM && TARGET_HARD_FLOAT && (ENABLE_XF_PATTERNS || reload_completed)" - "* - switch (which_alternative) - { - default: - case 0: return \"mvf%?e\\t%0, %1\"; - case 1: return \"mnf%?e\\t%0, #%N1\"; - case 2: return \"ldf%?e\\t%0, %1\"; - case 3: return \"stf%?e\\t%1, %0\"; - case 4: return output_mov_long_double_fpu_from_arm (operands); - case 5: return output_mov_long_double_arm_from_fpu (operands); - case 6: return output_mov_long_double_arm_from_arm (operands); - } - " - [(set_attr "length" "4,4,4,4,8,8,12") - (set_attr "predicable" "yes") - (set_attr "type" "ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*") - (set_attr "pool_range" "*,*,1024,*,*,*,*") - (set_attr "neg_pool_range" "*,*,1004,*,*,*,*")] -) +(define_expand "movv8qi" + [(set (match_operand:V8QI 0 "nonimmediate_operand" "") + (match_operand:V8QI 1 "general_operand" ""))] + "TARGET_REALLY_IWMMXT" +{ +}) ;; load- and store-multiple insns @@ -5347,7 +5166,7 @@ (use (match_operand:SI 2 "" ""))])] "TARGET_ARM" " - /* Support only fixed point registers */ + /* Support only fixed point registers. */ if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 14 || INTVAL (operands[2]) < 2 @@ -5538,7 +5357,7 @@ ;; Compare & branch insns -;; The range calcualations are based as follows: +;; The range calculations are based as follows: ;; For forward branches, the address calculation returns the address of ;; the next instruction. This is 2 beyond the branch instruction. ;; For backward branches, the address calculation returns the address of @@ -5554,17 +5373,36 @@ ;; For a 'b' pos_range = 2046, neg_range = -2048 giving (-2040->2048). ;; For a 'b<cond>' pos_range = 254, neg_range = -256 giving (-250 ->256). -(define_insn "cbranchsi4" - [(set (pc) - (if_then_else - (match_operator 0 "arm_comparison_operator" - [(match_operand:SI 1 "register_operand" "l,r") - (match_operand:SI 2 "nonmemory_operand" "rI,r")]) - (label_ref (match_operand 3 "" "")) - (pc)))] +(define_expand "cbranchsi4" + [(set (pc) (if_then_else + (match_operator 0 "arm_comparison_operator" + [(match_operand:SI 1 "s_register_operand" "") + (match_operand:SI 2 "nonmemory_operand" "")]) + (label_ref (match_operand 3 "" "")) + (pc)))] + "TARGET_THUMB" + " + if (thumb_cmpneg_operand (operands[2], SImode)) + { + emit_jump_insn (gen_cbranchsi4_scratch (NULL, operands[1], operands[2], + operands[3], operands[0])); + DONE; + } + if (!thumb_cmp_operand (operands[2], SImode)) + operands[2] = force_reg (SImode, operands[2]); + ") + +(define_insn "*cbranchsi4_insn" + [(set (pc) (if_then_else + (match_operator 0 "arm_comparison_operator" + [(match_operand:SI 1 "s_register_operand" "l,*h") + (match_operand:SI 2 "thumb_cmp_operand" "lI*h,*r")]) + (label_ref (match_operand 3 "" "")) + (pc)))] "TARGET_THUMB" "* output_asm_insn (\"cmp\\t%1, %2\", operands); + switch (get_attr_length (insn)) { case 4: return \"b%d0\\t%l3\"; @@ -5589,13 +5427,111 @@ (const_int 8))))] ) +(define_insn "cbranchsi4_scratch" + [(set (pc) (if_then_else + (match_operator 4 "arm_comparison_operator" + [(match_operand:SI 1 "s_register_operand" "l,0") + (match_operand:SI 2 "thumb_cmpneg_operand" "L,J")]) + (label_ref (match_operand 3 "" "")) + (pc))) + (clobber (match_scratch:SI 0 "=l,l"))] + "TARGET_THUMB" + "* + output_asm_insn (\"add\\t%0, %1, #%n2\", operands); + + switch (get_attr_length (insn)) + { + case 4: return \"b%d4\\t%l3\"; + case 6: return \"b%D4\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; + default: return \"b%D4\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; + } + " + [(set (attr "far_jump") + (if_then_else + (eq_attr "length" "8") + (const_string "yes") + (const_string "no"))) + (set (attr "length") + (if_then_else + (and (ge (minus (match_dup 3) (pc)) (const_int -250)) + (le (minus (match_dup 3) (pc)) (const_int 256))) + (const_int 4) + (if_then_else + (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) + (le (minus (match_dup 3) (pc)) (const_int 2048))) + (const_int 6) + (const_int 8))))] +) +(define_insn "*movsi_cbranchsi4" + [(set (pc) + (if_then_else + (match_operator 3 "arm_comparison_operator" + [(match_operand:SI 1 "s_register_operand" "0,l,l,l") + (const_int 0)]) + (label_ref (match_operand 2 "" "")) + (pc))) + (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,l,*h,*m") + (match_dup 1))] + "TARGET_THUMB" + "*{ + if (which_alternative == 0) + output_asm_insn (\"cmp\t%0, #0\", operands); + else if (which_alternative == 1) + output_asm_insn (\"sub\t%0, %1, #0\", operands); + else + { + output_asm_insn (\"cmp\t%1, #0\", operands); + if (which_alternative == 2) + output_asm_insn (\"mov\t%0, %1\", operands); + else + output_asm_insn (\"str\t%1, %0\", operands); + } + switch (get_attr_length (insn) - ((which_alternative > 1) ? 2 : 0)) + { + case 4: return \"b%d3\\t%l2\"; + case 6: return \"b%D3\\t.LCB%=\;b\\t%l2\\t%@long jump\\n.LCB%=:\"; + default: return \"b%D3\\t.LCB%=\;bl\\t%l2\\t%@far jump\\n.LCB%=:\"; + } + }" + [(set (attr "far_jump") + (if_then_else + (ior (and (gt (symbol_ref ("which_alternative")) + (const_int 1)) + (eq_attr "length" "8")) + (eq_attr "length" "10")) + (const_string "yes") + (const_string "no"))) + (set (attr "length") + (if_then_else + (le (symbol_ref ("which_alternative")) + (const_int 1)) + (if_then_else + (and (ge (minus (match_dup 2) (pc)) (const_int -250)) + (le (minus (match_dup 2) (pc)) (const_int 256))) + (const_int 4) + (if_then_else + (and (ge (minus (match_dup 2) (pc)) (const_int -2040)) + (le (minus (match_dup 2) (pc)) (const_int 2048))) + (const_int 6) + (const_int 8))) + (if_then_else + (and (ge (minus (match_dup 2) (pc)) (const_int -248)) + (le (minus (match_dup 2) (pc)) (const_int 256))) + (const_int 6) + (if_then_else + (and (ge (minus (match_dup 2) (pc)) (const_int -2038)) + (le (minus (match_dup 2) (pc)) (const_int 2048))) + (const_int 8) + (const_int 10)))))] +) + (define_insn "*negated_cbranchsi4" [(set (pc) (if_then_else - (match_operator 0 "arm_comparison_operator" - [(match_operand:SI 1 "register_operand" "l") - (neg:SI (match_operand:SI 2 "nonmemory_operand" "l"))]) - (label_ref (match_operand 3 "" "")) + (match_operator 0 "arm_comparison_operator" + [(match_operand:SI 1 "s_register_operand" "l") + (neg:SI (match_operand:SI 2 "s_register_operand" "l"))]) + (label_ref (match_operand 3 "" "")) (pc)))] "TARGET_THUMB" "* @@ -5624,6 +5560,836 @@ (const_int 8))))] ) +(define_insn "*tbit_cbranch" + [(set (pc) + (if_then_else + (match_operator 0 "equality_operator" + [(zero_extract:SI (match_operand:SI 1 "s_register_operand" "l") + (const_int 1) + (match_operand:SI 2 "const_int_operand" "i")) + (const_int 0)]) + (label_ref (match_operand 3 "" "")) + (pc))) + (clobber (match_scratch:SI 4 "=l"))] + "TARGET_THUMB" + "* + { + rtx op[3]; + op[0] = operands[4]; + op[1] = operands[1]; + op[2] = GEN_INT (32 - 1 - INTVAL (operands[2])); + + output_asm_insn (\"lsl\\t%0, %1, %2\", op); + switch (get_attr_length (insn)) + { + case 4: return \"b%d0\\t%l3\"; + case 6: return \"b%D0\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; + default: return \"b%D0\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; + } + }" + [(set (attr "far_jump") + (if_then_else + (eq_attr "length" "8") + (const_string "yes") + (const_string "no"))) + (set (attr "length") + (if_then_else + (and (ge (minus (match_dup 3) (pc)) (const_int -250)) + (le (minus (match_dup 3) (pc)) (const_int 256))) + (const_int 4) + (if_then_else + (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) + (le (minus (match_dup 3) (pc)) (const_int 2048))) + (const_int 6) + (const_int 8))))] +) + +(define_insn "*tstsi3_cbranch" + [(set (pc) + (if_then_else + (match_operator 3 "equality_operator" + [(and:SI (match_operand:SI 0 "s_register_operand" "%l") + (match_operand:SI 1 "s_register_operand" "l")) + (const_int 0)]) + (label_ref (match_operand 2 "" "")) + (pc)))] + "TARGET_THUMB" + "* + { + output_asm_insn (\"tst\\t%0, %1\", operands); + switch (get_attr_length (insn)) + { + case 4: return \"b%d3\\t%l2\"; + case 6: return \"b%D3\\t.LCB%=\;b\\t%l2\\t%@long jump\\n.LCB%=:\"; + default: return \"b%D3\\t.LCB%=\;bl\\t%l2\\t%@far jump\\n.LCB%=:\"; + } + }" + [(set (attr "far_jump") + (if_then_else + (eq_attr "length" "8") + (const_string "yes") + (const_string "no"))) + (set (attr "length") + (if_then_else + (and (ge (minus (match_dup 2) (pc)) (const_int -250)) + (le (minus (match_dup 2) (pc)) (const_int 256))) + (const_int 4) + (if_then_else + (and (ge (minus (match_dup 2) (pc)) (const_int -2040)) + (le (minus (match_dup 2) (pc)) (const_int 2048))) + (const_int 6) + (const_int 8))))] +) + +(define_insn "*andsi3_cbranch" + [(set (pc) + (if_then_else + (match_operator 5 "equality_operator" + [(and:SI (match_operand:SI 2 "s_register_operand" "%0,1,1,1") + (match_operand:SI 3 "s_register_operand" "l,l,l,l")) + (const_int 0)]) + (label_ref (match_operand 4 "" "")) + (pc))) + (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m") + (and:SI (match_dup 2) (match_dup 3))) + (clobber (match_scratch:SI 1 "=X,l,&l,&l"))] + "TARGET_THUMB" + "* + { + if (which_alternative == 0) + output_asm_insn (\"and\\t%0, %3\", operands); + else if (which_alternative == 1) + { + output_asm_insn (\"and\\t%1, %3\", operands); + output_asm_insn (\"mov\\t%0, %1\", operands); + } + else + { + output_asm_insn (\"and\\t%1, %3\", operands); + output_asm_insn (\"str\\t%1, %0\", operands); + } + + switch (get_attr_length (insn) - (which_alternative ? 2 : 0)) + { + case 4: return \"b%d5\\t%l4\"; + case 6: return \"b%D5\\t.LCB%=\;b\\t%l4\\t%@long jump\\n.LCB%=:\"; + default: return \"b%D5\\t.LCB%=\;bl\\t%l4\\t%@far jump\\n.LCB%=:\"; + } + }" + [(set (attr "far_jump") + (if_then_else + (ior (and (eq (symbol_ref ("which_alternative")) + (const_int 0)) + (eq_attr "length" "8")) + (eq_attr "length" "10")) + (const_string "yes") + (const_string "no"))) + (set (attr "length") + (if_then_else + (eq (symbol_ref ("which_alternative")) + (const_int 0)) + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -250)) + (le (minus (match_dup 4) (pc)) (const_int 256))) + (const_int 4) + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -2040)) + (le (minus (match_dup 4) (pc)) (const_int 2048))) + (const_int 6) + (const_int 8))) + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -248)) + (le (minus (match_dup 4) (pc)) (const_int 256))) + (const_int 6) + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -2038)) + (le (minus (match_dup 4) (pc)) (const_int 2048))) + (const_int 8) + (const_int 10)))))] +) + +(define_insn "*orrsi3_cbranch_scratch" + [(set (pc) + (if_then_else + (match_operator 4 "equality_operator" + [(ior:SI (match_operand:SI 1 "s_register_operand" "%0") + (match_operand:SI 2 "s_register_operand" "l")) + (const_int 0)]) + (label_ref (match_operand 3 "" "")) + (pc))) + (clobber (match_scratch:SI 0 "=l"))] + "TARGET_THUMB" + "* + { + output_asm_insn (\"orr\\t%0, %2\", operands); + switch (get_attr_length (insn)) + { + case 4: return \"b%d4\\t%l3\"; + case 6: return \"b%D4\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; + default: return \"b%D4\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; + } + }" + [(set (attr "far_jump") + (if_then_else + (eq_attr "length" "8") + (const_string "yes") + (const_string "no"))) + (set (attr "length") + (if_then_else + (and (ge (minus (match_dup 3) (pc)) (const_int -250)) + (le (minus (match_dup 3) (pc)) (const_int 256))) + (const_int 4) + (if_then_else + (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) + (le (minus (match_dup 3) (pc)) (const_int 2048))) + (const_int 6) + (const_int 8))))] +) + +(define_insn "*orrsi3_cbranch" + [(set (pc) + (if_then_else + (match_operator 5 "equality_operator" + [(ior:SI (match_operand:SI 2 "s_register_operand" "%0,1,1,1") + (match_operand:SI 3 "s_register_operand" "l,l,l,l")) + (const_int 0)]) + (label_ref (match_operand 4 "" "")) + (pc))) + (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m") + (ior:SI (match_dup 2) (match_dup 3))) + (clobber (match_scratch:SI 1 "=X,l,&l,&l"))] + "TARGET_THUMB" + "* + { + if (which_alternative == 0) + output_asm_insn (\"orr\\t%0, %3\", operands); + else if (which_alternative == 1) + { + output_asm_insn (\"orr\\t%1, %3\", operands); + output_asm_insn (\"mov\\t%0, %1\", operands); + } + else + { + output_asm_insn (\"orr\\t%1, %3\", operands); + output_asm_insn (\"str\\t%1, %0\", operands); + } + + switch (get_attr_length (insn) - (which_alternative ? 2 : 0)) + { + case 4: return \"b%d5\\t%l4\"; + case 6: return \"b%D5\\t.LCB%=\;b\\t%l4\\t%@long jump\\n.LCB%=:\"; + default: return \"b%D5\\t.LCB%=\;bl\\t%l4\\t%@far jump\\n.LCB%=:\"; + } + }" + [(set (attr "far_jump") + (if_then_else + (ior (and (eq (symbol_ref ("which_alternative")) + (const_int 0)) + (eq_attr "length" "8")) + (eq_attr "length" "10")) + (const_string "yes") + (const_string "no"))) + (set (attr "length") + (if_then_else + (eq (symbol_ref ("which_alternative")) + (const_int 0)) + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -250)) + (le (minus (match_dup 4) (pc)) (const_int 256))) + (const_int 4) + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -2040)) + (le (minus (match_dup 4) (pc)) (const_int 2048))) + (const_int 6) + (const_int 8))) + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -248)) + (le (minus (match_dup 4) (pc)) (const_int 256))) + (const_int 6) + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -2038)) + (le (minus (match_dup 4) (pc)) (const_int 2048))) + (const_int 8) + (const_int 10)))))] +) + +(define_insn "*xorsi3_cbranch_scratch" + [(set (pc) + (if_then_else + (match_operator 4 "equality_operator" + [(xor:SI (match_operand:SI 1 "s_register_operand" "%0") + (match_operand:SI 2 "s_register_operand" "l")) + (const_int 0)]) + (label_ref (match_operand 3 "" "")) + (pc))) + (clobber (match_scratch:SI 0 "=l"))] + "TARGET_THUMB" + "* + { + output_asm_insn (\"eor\\t%0, %2\", operands); + switch (get_attr_length (insn)) + { + case 4: return \"b%d4\\t%l3\"; + case 6: return \"b%D4\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; + default: return \"b%D4\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; + } + }" + [(set (attr "far_jump") + (if_then_else + (eq_attr "length" "8") + (const_string "yes") + (const_string "no"))) + (set (attr "length") + (if_then_else + (and (ge (minus (match_dup 3) (pc)) (const_int -250)) + (le (minus (match_dup 3) (pc)) (const_int 256))) + (const_int 4) + (if_then_else + (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) + (le (minus (match_dup 3) (pc)) (const_int 2048))) + (const_int 6) + (const_int 8))))] +) + +(define_insn "*xorsi3_cbranch" + [(set (pc) + (if_then_else + (match_operator 5 "equality_operator" + [(xor:SI (match_operand:SI 2 "s_register_operand" "%0,1,1,1") + (match_operand:SI 3 "s_register_operand" "l,l,l,l")) + (const_int 0)]) + (label_ref (match_operand 4 "" "")) + (pc))) + (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m") + (xor:SI (match_dup 2) (match_dup 3))) + (clobber (match_scratch:SI 1 "=X,l,&l,&l"))] + "TARGET_THUMB" + "* + { + if (which_alternative == 0) + output_asm_insn (\"eor\\t%0, %3\", operands); + else if (which_alternative == 1) + { + output_asm_insn (\"eor\\t%1, %3\", operands); + output_asm_insn (\"mov\\t%0, %1\", operands); + } + else + { + output_asm_insn (\"eor\\t%1, %3\", operands); + output_asm_insn (\"str\\t%1, %0\", operands); + } + + switch (get_attr_length (insn) - (which_alternative ? 2 : 0)) + { + case 4: return \"b%d5\\t%l4\"; + case 6: return \"b%D5\\t.LCB%=\;b\\t%l4\\t%@long jump\\n.LCB%=:\"; + default: return \"b%D5\\t.LCB%=\;bl\\t%l4\\t%@far jump\\n.LCB%=:\"; + } + }" + [(set (attr "far_jump") + (if_then_else + (ior (and (eq (symbol_ref ("which_alternative")) + (const_int 0)) + (eq_attr "length" "8")) + (eq_attr "length" "10")) + (const_string "yes") + (const_string "no"))) + (set (attr "length") + (if_then_else + (eq (symbol_ref ("which_alternative")) + (const_int 0)) + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -250)) + (le (minus (match_dup 4) (pc)) (const_int 256))) + (const_int 4) + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -2040)) + (le (minus (match_dup 4) (pc)) (const_int 2048))) + (const_int 6) + (const_int 8))) + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -248)) + (le (minus (match_dup 4) (pc)) (const_int 256))) + (const_int 6) + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -2038)) + (le (minus (match_dup 4) (pc)) (const_int 2048))) + (const_int 8) + (const_int 10)))))] +) + +(define_insn "*bicsi3_cbranch_scratch" + [(set (pc) + (if_then_else + (match_operator 4 "equality_operator" + [(and:SI (not:SI (match_operand:SI 2 "s_register_operand" "l")) + (match_operand:SI 1 "s_register_operand" "0")) + (const_int 0)]) + (label_ref (match_operand 3 "" "")) + (pc))) + (clobber (match_scratch:SI 0 "=l"))] + "TARGET_THUMB" + "* + { + output_asm_insn (\"bic\\t%0, %2\", operands); + switch (get_attr_length (insn)) + { + case 4: return \"b%d4\\t%l3\"; + case 6: return \"b%D4\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; + default: return \"b%D4\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; + } + }" + [(set (attr "far_jump") + (if_then_else + (eq_attr "length" "8") + (const_string "yes") + (const_string "no"))) + (set (attr "length") + (if_then_else + (and (ge (minus (match_dup 3) (pc)) (const_int -250)) + (le (minus (match_dup 3) (pc)) (const_int 256))) + (const_int 4) + (if_then_else + (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) + (le (minus (match_dup 3) (pc)) (const_int 2048))) + (const_int 6) + (const_int 8))))] +) + +(define_insn "*bicsi3_cbranch" + [(set (pc) + (if_then_else + (match_operator 5 "equality_operator" + [(and:SI (not:SI (match_operand:SI 3 "s_register_operand" "l,l,l,l")) + (match_operand:SI 2 "s_register_operand" "0,1,1,1")) + (const_int 0)]) + (label_ref (match_operand 4 "" "")) + (pc))) + (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m") + (and:SI (not:SI (match_dup 3)) (match_dup 2))) + (clobber (match_scratch:SI 1 "=X,l,&l,&l"))] + "TARGET_THUMB" + "* + { + if (which_alternative == 0) + output_asm_insn (\"bic\\t%0, %3\", operands); + else if (which_alternative == 1) + { + output_asm_insn (\"bic\\t%1, %3\", operands); + output_asm_insn (\"mov\\t%0, %1\", operands); + } + else + { + output_asm_insn (\"bic\\t%1, %3\", operands); + output_asm_insn (\"str\\t%1, %0\", operands); + } + + switch (get_attr_length (insn) - (which_alternative ? 2 : 0)) + { + case 4: return \"b%d5\\t%l4\"; + case 6: return \"b%D5\\t.LCB%=\;b\\t%l4\\t%@long jump\\n.LCB%=:\"; + default: return \"b%D5\\t.LCB%=\;bl\\t%l4\\t%@far jump\\n.LCB%=:\"; + } + }" + [(set (attr "far_jump") + (if_then_else + (ior (and (eq (symbol_ref ("which_alternative")) + (const_int 0)) + (eq_attr "length" "8")) + (eq_attr "length" "10")) + (const_string "yes") + (const_string "no"))) + (set (attr "length") + (if_then_else + (eq (symbol_ref ("which_alternative")) + (const_int 0)) + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -250)) + (le (minus (match_dup 4) (pc)) (const_int 256))) + (const_int 4) + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -2040)) + (le (minus (match_dup 4) (pc)) (const_int 2048))) + (const_int 6) + (const_int 8))) + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -248)) + (le (minus (match_dup 4) (pc)) (const_int 256))) + (const_int 6) + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -2038)) + (le (minus (match_dup 4) (pc)) (const_int 2048))) + (const_int 8) + (const_int 10)))))] +) + +(define_insn "*cbranchne_decr1" + [(set (pc) + (if_then_else (match_operator 3 "equality_operator" + [(match_operand:SI 2 "s_register_operand" "l,l,1,l") + (const_int 0)]) + (label_ref (match_operand 4 "" "")) + (pc))) + (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m") + (plus:SI (match_dup 2) (const_int -1))) + (clobber (match_scratch:SI 1 "=X,l,&l,&l"))] + "TARGET_THUMB" + "* + { + rtx cond[2]; + cond[0] = gen_rtx_fmt_ee ((GET_CODE (operands[3]) == NE + ? GEU : LTU), + VOIDmode, operands[2], const1_rtx); + cond[1] = operands[4]; + + if (which_alternative == 0) + output_asm_insn (\"sub\\t%0, %2, #1\", operands); + else if (which_alternative == 1) + { + /* We must provide an alternative for a hi reg because reload + cannot handle output reloads on a jump instruction, but we + can't subtract into that. Fortunately a mov from lo to hi + does not clobber the condition codes. */ + output_asm_insn (\"sub\\t%1, %2, #1\", operands); + output_asm_insn (\"mov\\t%0, %1\", operands); + } + else + { + /* Similarly, but the target is memory. */ + output_asm_insn (\"sub\\t%1, %2, #1\", operands); + output_asm_insn (\"str\\t%1, %0\", operands); + } + + switch (get_attr_length (insn) - (which_alternative ? 2 : 0)) + { + case 4: + output_asm_insn (\"b%d0\\t%l1\", cond); + return \"\"; + case 6: + output_asm_insn (\"b%D0\\t.LCB%=\", cond); + return \"b\\t%l4\\t%@long jump\\n.LCB%=:\"; + default: + output_asm_insn (\"b%D0\\t.LCB%=\", cond); + return \"bl\\t%l4\\t%@far jump\\n.LCB%=:\"; + } + } + " + [(set (attr "far_jump") + (if_then_else + (ior (and (eq (symbol_ref ("which_alternative")) + (const_int 0)) + (eq_attr "length" "8")) + (eq_attr "length" "10")) + (const_string "yes") + (const_string "no"))) + (set_attr_alternative "length" + [ + ;; Alternative 0 + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -250)) + (le (minus (match_dup 4) (pc)) (const_int 256))) + (const_int 4) + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -2040)) + (le (minus (match_dup 4) (pc)) (const_int 2048))) + (const_int 6) + (const_int 8))) + ;; Alternative 1 + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -248)) + (le (minus (match_dup 4) (pc)) (const_int 256))) + (const_int 6) + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -2038)) + (le (minus (match_dup 4) (pc)) (const_int 2048))) + (const_int 8) + (const_int 10))) + ;; Alternative 2 + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -248)) + (le (minus (match_dup 4) (pc)) (const_int 256))) + (const_int 6) + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -2038)) + (le (minus (match_dup 4) (pc)) (const_int 2048))) + (const_int 8) + (const_int 10))) + ;; Alternative 3 + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -248)) + (le (minus (match_dup 4) (pc)) (const_int 256))) + (const_int 6) + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -2038)) + (le (minus (match_dup 4) (pc)) (const_int 2048))) + (const_int 8) + (const_int 10)))])] +) + +(define_insn "*addsi3_cbranch" + [(set (pc) + (if_then_else + (match_operator 4 "comparison_operator" + [(plus:SI + (match_operand:SI 2 "s_register_operand" "%l,0,*0,1,1,1") + (match_operand:SI 3 "reg_or_int_operand" "lL,IJ,*r,lIJ,lIJ,lIJ")) + (const_int 0)]) + (label_ref (match_operand 5 "" "")) + (pc))) + (set + (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,l,*!h,*?h,*?m,*?m") + (plus:SI (match_dup 2) (match_dup 3))) + (clobber (match_scratch:SI 1 "=X,X,X,l,&l,&l"))] + "TARGET_THUMB + && (GET_CODE (operands[4]) == EQ + || GET_CODE (operands[4]) == NE + || GET_CODE (operands[4]) == GE + || GET_CODE (operands[4]) == LT)" + "* + { + rtx cond[3]; + + + cond[0] = (which_alternative < 3) ? operands[0] : operands[1]; + cond[1] = operands[2]; + cond[2] = operands[3]; + + if (GET_CODE (cond[2]) == CONST_INT && INTVAL (cond[2]) < 0) + output_asm_insn (\"sub\\t%0, %1, #%n2\", cond); + else + output_asm_insn (\"add\\t%0, %1, %2\", cond); + + if (which_alternative >= 3 + && which_alternative < 4) + output_asm_insn (\"mov\\t%0, %1\", operands); + else if (which_alternative >= 4) + output_asm_insn (\"str\\t%1, %0\", operands); + + switch (get_attr_length (insn) - ((which_alternative >= 3) ? 2 : 0)) + { + case 4: + return \"b%d4\\t%l5\"; + case 6: + return \"b%D4\\t.LCB%=\;b\\t%l5\\t%@long jump\\n.LCB%=:\"; + default: + return \"b%D4\\t.LCB%=\;bl\\t%l5\\t%@far jump\\n.LCB%=:\"; + } + } + " + [(set (attr "far_jump") + (if_then_else + (ior (and (lt (symbol_ref ("which_alternative")) + (const_int 3)) + (eq_attr "length" "8")) + (eq_attr "length" "10")) + (const_string "yes") + (const_string "no"))) + (set (attr "length") + (if_then_else + (lt (symbol_ref ("which_alternative")) + (const_int 3)) + (if_then_else + (and (ge (minus (match_dup 5) (pc)) (const_int -250)) + (le (minus (match_dup 5) (pc)) (const_int 256))) + (const_int 4) + (if_then_else + (and (ge (minus (match_dup 5) (pc)) (const_int -2040)) + (le (minus (match_dup 5) (pc)) (const_int 2048))) + (const_int 6) + (const_int 8))) + (if_then_else + (and (ge (minus (match_dup 5) (pc)) (const_int -248)) + (le (minus (match_dup 5) (pc)) (const_int 256))) + (const_int 6) + (if_then_else + (and (ge (minus (match_dup 5) (pc)) (const_int -2038)) + (le (minus (match_dup 5) (pc)) (const_int 2048))) + (const_int 8) + (const_int 10)))))] +) + +(define_insn "*addsi3_cbranch_scratch" + [(set (pc) + (if_then_else + (match_operator 3 "comparison_operator" + [(plus:SI + (match_operand:SI 1 "s_register_operand" "%l,l,l,0") + (match_operand:SI 2 "reg_or_int_operand" "J,l,I,L")) + (const_int 0)]) + (label_ref (match_operand 4 "" "")) + (pc))) + (clobber (match_scratch:SI 0 "=X,X,l,l"))] + "TARGET_THUMB + && (GET_CODE (operands[3]) == EQ + || GET_CODE (operands[3]) == NE + || GET_CODE (operands[3]) == GE + || GET_CODE (operands[3]) == LT)" + "* + { + switch (which_alternative) + { + case 0: + output_asm_insn (\"cmp\t%1, #%n2\", operands); + break; + case 1: + output_asm_insn (\"cmn\t%1, %2\", operands); + break; + case 3: + output_asm_insn (\"add\t%0, %1, %2\", operands); + break; + case 4: + output_asm_insn (\"add\t%0, %0, %2\", operands); + break; + } + + switch (get_attr_length (insn)) + { + case 4: + return \"b%d3\\t%l4\"; + case 6: + return \"b%D3\\t.LCB%=\;b\\t%l4\\t%@long jump\\n.LCB%=:\"; + default: + return \"b%D3\\t.LCB%=\;bl\\t%l4\\t%@far jump\\n.LCB%=:\"; + } + } + " + [(set (attr "far_jump") + (if_then_else + (eq_attr "length" "8") + (const_string "yes") + (const_string "no"))) + (set (attr "length") + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -250)) + (le (minus (match_dup 4) (pc)) (const_int 256))) + (const_int 4) + (if_then_else + (and (ge (minus (match_dup 4) (pc)) (const_int -2040)) + (le (minus (match_dup 4) (pc)) (const_int 2048))) + (const_int 6) + (const_int 8))))] +) + +(define_insn "*subsi3_cbranch" + [(set (pc) + (if_then_else + (match_operator 4 "comparison_operator" + [(minus:SI + (match_operand:SI 2 "s_register_operand" "l,l,1,l") + (match_operand:SI 3 "s_register_operand" "l,l,l,l")) + (const_int 0)]) + (label_ref (match_operand 5 "" "")) + (pc))) + (set (match_operand:SI 0 "thumb_cbrch_target_operand" "=l,*?h,*?m,*?m") + (minus:SI (match_dup 2) (match_dup 3))) + (clobber (match_scratch:SI 1 "=X,l,&l,&l"))] + "TARGET_THUMB + && (GET_CODE (operands[4]) == EQ + || GET_CODE (operands[4]) == NE + || GET_CODE (operands[4]) == GE + || GET_CODE (operands[4]) == LT)" + "* + { + if (which_alternative == 0) + output_asm_insn (\"sub\\t%0, %2, %3\", operands); + else if (which_alternative == 1) + { + /* We must provide an alternative for a hi reg because reload + cannot handle output reloads on a jump instruction, but we + can't subtract into that. Fortunately a mov from lo to hi + does not clobber the condition codes. */ + output_asm_insn (\"sub\\t%1, %2, %3\", operands); + output_asm_insn (\"mov\\t%0, %1\", operands); + } + else + { + /* Similarly, but the target is memory. */ + output_asm_insn (\"sub\\t%1, %2, %3\", operands); + output_asm_insn (\"str\\t%1, %0\", operands); + } + + switch (get_attr_length (insn) - ((which_alternative != 0) ? 2 : 0)) + { + case 4: + return \"b%d4\\t%l5\"; + case 6: + return \"b%D4\\t.LCB%=\;b\\t%l5\\t%@long jump\\n.LCB%=:\"; + default: + return \"b%D4\\t.LCB%=\;bl\\t%l5\\t%@far jump\\n.LCB%=:\"; + } + } + " + [(set (attr "far_jump") + (if_then_else + (ior (and (eq (symbol_ref ("which_alternative")) + (const_int 0)) + (eq_attr "length" "8")) + (eq_attr "length" "10")) + (const_string "yes") + (const_string "no"))) + (set (attr "length") + (if_then_else + (eq (symbol_ref ("which_alternative")) + (const_int 0)) + (if_then_else + (and (ge (minus (match_dup 5) (pc)) (const_int -250)) + (le (minus (match_dup 5) (pc)) (const_int 256))) + (const_int 4) + (if_then_else + (and (ge (minus (match_dup 5) (pc)) (const_int -2040)) + (le (minus (match_dup 5) (pc)) (const_int 2048))) + (const_int 6) + (const_int 8))) + (if_then_else + (and (ge (minus (match_dup 5) (pc)) (const_int -248)) + (le (minus (match_dup 5) (pc)) (const_int 256))) + (const_int 6) + (if_then_else + (and (ge (minus (match_dup 5) (pc)) (const_int -2038)) + (le (minus (match_dup 5) (pc)) (const_int 2048))) + (const_int 8) + (const_int 10)))))] +) + +(define_insn "*subsi3_cbranch_scratch" + [(set (pc) + (if_then_else + (match_operator 0 "arm_comparison_operator" + [(minus:SI (match_operand:SI 1 "register_operand" "l") + (match_operand:SI 2 "nonmemory_operand" "l")) + (const_int 0)]) + (label_ref (match_operand 3 "" "")) + (pc)))] + "TARGET_THUMB + && (GET_CODE (operands[0]) == EQ + || GET_CODE (operands[0]) == NE + || GET_CODE (operands[0]) == GE + || GET_CODE (operands[0]) == LT)" + "* + output_asm_insn (\"cmp\\t%1, %2\", operands); + switch (get_attr_length (insn)) + { + case 4: return \"b%d0\\t%l3\"; + case 6: return \"b%D0\\t.LCB%=\;b\\t%l3\\t%@long jump\\n.LCB%=:\"; + default: return \"b%D0\\t.LCB%=\;bl\\t%l3\\t%@far jump\\n.LCB%=:\"; + } + " + [(set (attr "far_jump") + (if_then_else + (eq_attr "length" "8") + (const_string "yes") + (const_string "no"))) + (set (attr "length") + (if_then_else + (and (ge (minus (match_dup 3) (pc)) (const_int -250)) + (le (minus (match_dup 3) (pc)) (const_int 256))) + (const_int 4) + (if_then_else + (and (ge (minus (match_dup 3) (pc)) (const_int -2040)) + (le (minus (match_dup 3) (pc)) (const_int 2048))) + (const_int 6) + (const_int 8))))] +) ;; Comparison and test insns @@ -5640,9 +6406,12 @@ (define_expand "cmpsf" [(match_operand:SF 0 "s_register_operand" "") - (match_operand:SF 1 "fpu_rhs_operand" "")] - "TARGET_ARM && TARGET_HARD_FLOAT" + (match_operand:SF 1 "fpa_rhs_operand" "")] + "TARGET_ARM && TARGET_ANY_HARD_FLOAT" " + if (TARGET_CIRRUS && !cirrus_fp_register (operands[1], SFmode)) + operands[1] = force_reg (SFmode, operands[1]); + arm_compare_op0 = operands[0]; arm_compare_op1 = operands[1]; DONE; @@ -5651,20 +6420,12 @@ (define_expand "cmpdf" [(match_operand:DF 0 "s_register_operand" "") - (match_operand:DF 1 "fpu_rhs_operand" "")] - "TARGET_ARM && TARGET_HARD_FLOAT" - " - arm_compare_op0 = operands[0]; - arm_compare_op1 = operands[1]; - DONE; + (match_operand:DF 1 "fpa_rhs_operand" "")] + "TARGET_ARM && TARGET_ANY_HARD_FLOAT" " -) + if (TARGET_CIRRUS && !cirrus_fp_register (operands[1], DFmode)) + operands[1] = force_reg (DFmode, operands[1]); -(define_expand "cmpxf" - [(match_operand:XF 0 "s_register_operand" "") - (match_operand:XF 1 "fpu_rhs_operand" "")] - "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" - " arm_compare_op0 = operands[0]; arm_compare_op1 = operands[1]; DONE; @@ -5721,124 +6482,47 @@ ] ) -(define_insn "*cmpsf_insn" - [(set (reg:CCFP CC_REGNUM) - (compare:CCFP (match_operand:SF 0 "s_register_operand" "f,f") - (match_operand:SF 1 "fpu_add_operand" "fG,H")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "@ - cmf%?\\t%0, %1 - cnf%?\\t%0, #%N1" - [(set_attr "conds" "set") - (set_attr "type" "f_2_r")] -) - -(define_insn "*cmpdf_insn" - [(set (reg:CCFP CC_REGNUM) - (compare:CCFP (match_operand:DF 0 "s_register_operand" "f,f") - (match_operand:DF 1 "fpu_add_operand" "fG,H")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "@ - cmf%?\\t%0, %1 - cnf%?\\t%0, #%N1" - [(set_attr "conds" "set") - (set_attr "type" "f_2_r")] -) - -(define_insn "*cmpesfdf_df" - [(set (reg:CCFP CC_REGNUM) - (compare:CCFP (float_extend:DF - (match_operand:SF 0 "s_register_operand" "f,f")) - (match_operand:DF 1 "fpu_add_operand" "fG,H")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "@ - cmf%?\\t%0, %1 - cnf%?\\t%0, #%N1" - [(set_attr "conds" "set") - (set_attr "type" "f_2_r")] -) - -(define_insn "*cmpdf_esfdf" +;; Cirrus SF compare instruction +(define_insn "*cirrus_cmpsf" [(set (reg:CCFP CC_REGNUM) - (compare:CCFP (match_operand:DF 0 "s_register_operand" "f") - (float_extend:DF - (match_operand:SF 1 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "cmf%?\\t%0, %1" - [(set_attr "conds" "set") - (set_attr "type" "f_2_r")] + (compare:CCFP (match_operand:SF 0 "cirrus_fp_register" "v") + (match_operand:SF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfcmps%?\\tr15, %V0, %V1" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "compare")] ) -(define_insn "*cmpxf_insn" +;; Cirrus DF compare instruction +(define_insn "*cirrus_cmpdf" [(set (reg:CCFP CC_REGNUM) - (compare:CCFP (match_operand:XF 0 "s_register_operand" "f,f") - (match_operand:XF 1 "fpu_add_operand" "fG,H")))] - "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" - "@ - cmf%?\\t%0, %1 - cnf%?\\t%0, #%N1" - [(set_attr "conds" "set") - (set_attr "type" "f_2_r")] -) - -(define_insn "*cmpsf_trap" - [(set (reg:CCFPE CC_REGNUM) - (compare:CCFPE (match_operand:SF 0 "s_register_operand" "f,f") - (match_operand:SF 1 "fpu_add_operand" "fG,H")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "@ - cmf%?e\\t%0, %1 - cnf%?e\\t%0, #%N1" - [(set_attr "conds" "set") - (set_attr "type" "f_2_r")] -) - -(define_insn "*cmpdf_trap" - [(set (reg:CCFPE CC_REGNUM) - (compare:CCFPE (match_operand:DF 0 "s_register_operand" "f,f") - (match_operand:DF 1 "fpu_add_operand" "fG,H")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "@ - cmf%?e\\t%0, %1 - cnf%?e\\t%0, #%N1" - [(set_attr "conds" "set") - (set_attr "type" "f_2_r")] -) - -(define_insn "*cmp_esfdf_df_trap" - [(set (reg:CCFPE CC_REGNUM) - (compare:CCFPE (float_extend:DF - (match_operand:SF 0 "s_register_operand" "f,f")) - (match_operand:DF 1 "fpu_add_operand" "fG,H")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "@ - cmf%?e\\t%0, %1 - cnf%?e\\t%0, #%N1" - [(set_attr "conds" "set") - (set_attr "type" "f_2_r")] -) - -(define_insn "*cmp_df_esfdf_trap" - [(set (reg:CCFPE CC_REGNUM) - (compare:CCFPE (match_operand:DF 0 "s_register_operand" "f") - (float_extend:DF - (match_operand:SF 1 "s_register_operand" "f"))))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "cmf%?e\\t%0, %1" - [(set_attr "conds" "set") - (set_attr "type" "f_2_r")] -) + (compare:CCFP (match_operand:DF 0 "cirrus_fp_register" "v") + (match_operand:DF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfcmpd%?\\tr15, %V0, %V1" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "compare")] +) + +;; Cirrus DI compare instruction +(define_expand "cmpdi" + [(match_operand:DI 0 "cirrus_fp_register" "") + (match_operand:DI 1 "cirrus_fp_register" "")] + "TARGET_ARM && TARGET_CIRRUS" + "{ + arm_compare_op0 = operands[0]; + arm_compare_op1 = operands[1]; + DONE; + }") -(define_insn "*cmpxf_trap" - [(set (reg:CCFPE CC_REGNUM) - (compare:CCFPE (match_operand:XF 0 "s_register_operand" "f,f") - (match_operand:XF 1 "fpu_add_operand" "fG,H")))] - "TARGET_ARM && ENABLE_XF_PATTERNS && TARGET_HARD_FLOAT" - "@ - cmf%?e\\t%0, %1 - cnf%?e\\t%0, #%N1" - [(set_attr "conds" "set") - (set_attr "type" "f_2_r")] +(define_insn "*cirrus_cmpdi" + [(set (reg:CC CC_REGNUM) + (compare:CC (match_operand:DI 0 "cirrus_fp_register" "v") + (match_operand:DI 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfcmp64%?\\tr15, %V0, %V1" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "compare")] ) ; This insn allows redundant compares to be removed by cse, nothing should @@ -6137,77 +6821,77 @@ ; scc insns (define_expand "seq" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "") (eq:SI (match_dup 1) (const_int 0)))] "TARGET_ARM" "operands[1] = arm_gen_compare_reg (EQ, arm_compare_op0, arm_compare_op1);" ) (define_expand "sne" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "") (ne:SI (match_dup 1) (const_int 0)))] "TARGET_ARM" "operands[1] = arm_gen_compare_reg (NE, arm_compare_op0, arm_compare_op1);" ) (define_expand "sgt" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "") (gt:SI (match_dup 1) (const_int 0)))] "TARGET_ARM" "operands[1] = arm_gen_compare_reg (GT, arm_compare_op0, arm_compare_op1);" ) (define_expand "sle" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "") (le:SI (match_dup 1) (const_int 0)))] "TARGET_ARM" "operands[1] = arm_gen_compare_reg (LE, arm_compare_op0, arm_compare_op1);" ) (define_expand "sge" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "") (ge:SI (match_dup 1) (const_int 0)))] "TARGET_ARM" "operands[1] = arm_gen_compare_reg (GE, arm_compare_op0, arm_compare_op1);" ) (define_expand "slt" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "") (lt:SI (match_dup 1) (const_int 0)))] "TARGET_ARM" "operands[1] = arm_gen_compare_reg (LT, arm_compare_op0, arm_compare_op1);" ) (define_expand "sgtu" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "") (gtu:SI (match_dup 1) (const_int 0)))] "TARGET_ARM" "operands[1] = arm_gen_compare_reg (GTU, arm_compare_op0, arm_compare_op1);" ) (define_expand "sleu" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "") (leu:SI (match_dup 1) (const_int 0)))] "TARGET_ARM" "operands[1] = arm_gen_compare_reg (LEU, arm_compare_op0, arm_compare_op1);" ) (define_expand "sgeu" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "") (geu:SI (match_dup 1) (const_int 0)))] "TARGET_ARM" "operands[1] = arm_gen_compare_reg (GEU, arm_compare_op0, arm_compare_op1);" ) (define_expand "sltu" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "") (ltu:SI (match_dup 1) (const_int 0)))] "TARGET_ARM" "operands[1] = arm_gen_compare_reg (LTU, arm_compare_op0, arm_compare_op1);" ) (define_expand "sunordered" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "") (unordered:SI (match_dup 1) (const_int 0)))] "TARGET_ARM && TARGET_HARD_FLOAT" "operands[1] = arm_gen_compare_reg (UNORDERED, arm_compare_op0, @@ -6215,7 +6899,7 @@ ) (define_expand "sordered" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "") (ordered:SI (match_dup 1) (const_int 0)))] "TARGET_ARM && TARGET_HARD_FLOAT" "operands[1] = arm_gen_compare_reg (ORDERED, arm_compare_op0, @@ -6223,7 +6907,7 @@ ) (define_expand "sungt" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "") (ungt:SI (match_dup 1) (const_int 0)))] "TARGET_ARM && TARGET_HARD_FLOAT" "operands[1] = arm_gen_compare_reg (UNGT, arm_compare_op0, @@ -6231,7 +6915,7 @@ ) (define_expand "sunge" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "") (unge:SI (match_dup 1) (const_int 0)))] "TARGET_ARM && TARGET_HARD_FLOAT" "operands[1] = arm_gen_compare_reg (UNGE, arm_compare_op0, @@ -6239,7 +6923,7 @@ ) (define_expand "sunlt" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "") (unlt:SI (match_dup 1) (const_int 0)))] "TARGET_ARM && TARGET_HARD_FLOAT" "operands[1] = arm_gen_compare_reg (UNLT, arm_compare_op0, @@ -6247,7 +6931,7 @@ ) (define_expand "sunle" - [(set (match_operand:SI 0 "s_register_operand" "=r") + [(set (match_operand:SI 0 "s_register_operand" "") (unle:SI (match_dup 1) (const_int 0)))] "TARGET_ARM && TARGET_HARD_FLOAT" "operands[1] = arm_gen_compare_reg (UNLE, arm_compare_op0, @@ -6258,14 +6942,14 @@ ;;; simple ARM instructions. ; ; (define_expand "suneq" -; [(set (match_operand:SI 0 "s_register_operand" "=r") +; [(set (match_operand:SI 0 "s_register_operand" "") ; (uneq:SI (match_dup 1) (const_int 0)))] ; "TARGET_ARM && TARGET_HARD_FLOAT" ; "abort ();" ; ) ; ; (define_expand "sltgt" -; [(set (match_operand:SI 0 "s_register_operand" "=r") +; [(set (match_operand:SI 0 "s_register_operand" "") ; (ltgt:SI (match_dup 1) (const_int 0)))] ; "TARGET_ARM && TARGET_HARD_FLOAT" ; "abort ();" @@ -6338,9 +7022,9 @@ FAIL; /* When compiling for SOFT_FLOAT, ensure both arms are in registers. - Otherwise, ensure it is a valid FP add operand */ + Otherwise, ensure it is a valid FP add operand. */ if ((!TARGET_HARD_FLOAT) - || (!fpu_add_operand (operands[3], SFmode))) + || (!fpa_add_operand (operands[3], SFmode))) operands[3] = force_reg (SFmode, operands[3]); ccreg = arm_gen_compare_reg (code, arm_compare_op0, arm_compare_op1); @@ -6352,7 +7036,7 @@ [(set (match_operand:DF 0 "s_register_operand" "") (if_then_else:DF (match_operand 1 "arm_comparison_operator" "") (match_operand:DF 2 "s_register_operand" "") - (match_operand:DF 3 "fpu_add_operand" "")))] + (match_operand:DF 3 "fpa_add_operand" "")))] "TARGET_ARM && TARGET_HARD_FLOAT" " { @@ -6388,28 +7072,6 @@ (set_attr "conds" "use")] ) -(define_insn "*movsfcc_hard_insn" - [(set (match_operand:SF 0 "s_register_operand" "=f,f,f,f,f,f,f,f") - (if_then_else:SF - (match_operator 3 "arm_comparison_operator" - [(match_operand 4 "cc_register" "") (const_int 0)]) - (match_operand:SF 1 "fpu_add_operand" "0,0,fG,H,fG,fG,H,H") - (match_operand:SF 2 "fpu_add_operand" "fG,H,0,0,fG,H,fG,H")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "@ - mvf%D3s\\t%0, %2 - mnf%D3s\\t%0, #%N2 - mvf%d3s\\t%0, %1 - mnf%d3s\\t%0, #%N1 - mvf%d3s\\t%0, %1\;mvf%D3s\\t%0, %2 - mvf%d3s\\t%0, %1\;mnf%D3s\\t%0, #%N2 - mnf%d3s\\t%0, #%N1\;mvf%D3s\\t%0, %2 - mnf%d3s\\t%0, #%N1\;mnf%D3s\\t%0, #%N2" - [(set_attr "length" "4,4,4,4,8,8,8,8") - (set_attr "type" "ffarith") - (set_attr "conds" "use")] -) - (define_insn "*movsfcc_soft_insn" [(set (match_operand:SF 0 "s_register_operand" "=r,r") (if_then_else:SF (match_operator 3 "arm_comparison_operator" @@ -6423,28 +7085,6 @@ [(set_attr "conds" "use")] ) -(define_insn "*movdfcc_insn" - [(set (match_operand:DF 0 "s_register_operand" "=f,f,f,f,f,f,f,f") - (if_then_else:DF - (match_operator 3 "arm_comparison_operator" - [(match_operand 4 "cc_register" "") (const_int 0)]) - (match_operand:DF 1 "fpu_add_operand" "0,0,fG,H,fG,fG,H,H") - (match_operand:DF 2 "fpu_add_operand" "fG,H,0,0,fG,H,fG,H")))] - "TARGET_ARM && TARGET_HARD_FLOAT" - "@ - mvf%D3d\\t%0, %2 - mnf%D3d\\t%0, #%N2 - mvf%d3d\\t%0, %1 - mnf%d3d\\t%0, #%N1 - mvf%d3d\\t%0, %1\;mvf%D3d\\t%0, %2 - mvf%d3d\\t%0, %1\;mnf%D3d\\t%0, #%N2 - mnf%d3d\\t%0, #%N1\;mvf%D3d\\t%0, %2 - mnf%d3d\\t%0, #%N1\;mnf%D3d\\t%0, #%N2" - [(set_attr "length" "4,4,4,4,8,8,8,8") - (set_attr "type" "ffarith") - (set_attr "conds" "use")] -) - ;; Jump and linkage insns @@ -6570,7 +7210,7 @@ ) (define_insn "*call_value_indirect" - [(set (match_operand 0 "" "=l") + [(set (match_operand 0 "" "") (call (mem:SI (match_operand:SI 1 "register_operand" "l*r")) (match_operand 2 "" ""))) (use (match_operand 3 "" "")) @@ -6609,8 +7249,8 @@ ) (define_insn "*call_value_reg" - [(set (match_operand 0 "" "=r,f") - (call (mem:SI (match_operand:SI 1 "s_register_operand" "r,r")) + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:SI 1 "s_register_operand" "r")) (match_operand 2 "" ""))) (use (match_operand 3 "" "")) (clobber (reg:SI LR_REGNUM))] @@ -6623,8 +7263,8 @@ ) (define_insn "*call_value_mem" - [(set (match_operand 0 "" "=r,f") - (call (mem:SI (match_operand:SI 1 "memory_operand" "m,m")) + [(set (match_operand 0 "" "") + (call (mem:SI (match_operand:SI 1 "memory_operand" "m")) (match_operand 2 "" ""))) (use (match_operand 3 "" "")) (clobber (reg:SI LR_REGNUM))] @@ -6640,7 +7280,7 @@ ;; The 'a' causes the operand to be treated as an address, i.e. no '#' output. (define_insn "*call_symbol" - [(call (mem:SI (match_operand:SI 0 "" "X")) + [(call (mem:SI (match_operand:SI 0 "" "")) (match_operand 1 "" "")) (use (match_operand 2 "" "")) (clobber (reg:SI LR_REGNUM))] @@ -6655,8 +7295,8 @@ ) (define_insn "*call_value_symbol" - [(set (match_operand 0 "s_register_operand" "=r,f") - (call (mem:SI (match_operand:SI 1 "" "X,X")) + [(set (match_operand 0 "s_register_operand" "") + (call (mem:SI (match_operand:SI 1 "" "")) (match_operand:SI 2 "" ""))) (use (match_operand 3 "" "")) (clobber (reg:SI LR_REGNUM))] @@ -6671,7 +7311,7 @@ ) (define_insn "*call_insn" - [(call (mem:SI (match_operand:SI 0 "" "X")) + [(call (mem:SI (match_operand:SI 0 "" "")) (match_operand:SI 1 "" "")) (use (match_operand 2 "" "")) (clobber (reg:SI LR_REGNUM))] @@ -6684,8 +7324,8 @@ ) (define_insn "*call_value_insn" - [(set (match_operand 0 "register_operand" "=l") - (call (mem:SI (match_operand 1 "" "X")) + [(set (match_operand 0 "register_operand" "") + (call (mem:SI (match_operand 1 "" "")) (match_operand 2 "" ""))) (use (match_operand 3 "" "")) (clobber (reg:SI LR_REGNUM))] @@ -6738,8 +7378,8 @@ ) (define_insn "*sibcall_value_insn" - [(set (match_operand 0 "s_register_operand" "=r,f") - (call (mem:SI (match_operand:SI 1 "" "X,X")) + [(set (match_operand 0 "s_register_operand" "") + (call (mem:SI (match_operand:SI 1 "" "X")) (match_operand 2 "" ""))) (return) (use (match_operand 3 "" ""))] @@ -6764,6 +7404,7 @@ return output_return_instruction (const_true_rtx, TRUE, FALSE); }" [(set_attr "type" "load") + (set_attr "length" "12") (set_attr "predicable" "yes")] ) @@ -6784,6 +7425,7 @@ return output_return_instruction (operands[0], TRUE, FALSE); }" [(set_attr "conds" "use") + (set_attr "length" "12") (set_attr "type" "load")] ) @@ -6821,7 +7463,7 @@ (const_int 67108860)))] ; 0x03fffffc "TARGET_ARM" " - operands[1] = gen_rtx_REG (CC_NOOVmode, 24); + operands[1] = gen_rtx_REG (CC_NOOVmode, CC_REGNUM); ") (define_insn "*check_arch2" @@ -6997,6 +7639,24 @@ ] ) +(define_split + [(set (match_operand:SI 0 "s_register_operand" "") + (match_operator:SI 1 "shiftable_operator" + [(match_operator:SI 2 "shiftable_operator" + [(match_operator:SI 3 "shift_operator" + [(match_operand:SI 4 "s_register_operand" "") + (match_operand:SI 5 "reg_or_int_operand" "")]) + (match_operand:SI 6 "s_register_operand" "")]) + (match_operand:SI 7 "arm_rhs_operand" "")])) + (clobber (match_operand:SI 8 "s_register_operand" ""))] + "TARGET_ARM" + [(set (match_dup 8) + (match_op_dup 2 [(match_op_dup 3 [(match_dup 4) (match_dup 5)]) + (match_dup 6)])) + (set (match_dup 0) + (match_op_dup 1 [(match_dup 8) (match_dup 7)]))] + "") + (define_insn "*arith_shiftsi_compare0" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV (match_operator:SI 1 "shiftable_operator" @@ -7112,11 +7772,17 @@ (clobber (reg:CC CC_REGNUM))] "TARGET_ARM" "* - if (GET_CODE (operands[1]) == LT && operands[3] == const0_rtx) - return \"mov\\t%0, %2, lsr #31\"; + if (operands[3] == const0_rtx) + { + if (GET_CODE (operands[1]) == LT) + return \"mov\\t%0, %2, lsr #31\"; + + if (GET_CODE (operands[1]) == GE) + return \"mvn\\t%0, %2\;mov\\t%0, %0, lsr #31\"; - if (GET_CODE (operands[1]) == GE && operands[3] == const0_rtx) - return \"mvn\\t%0, %2\;mov\\t%0, %0, lsr #31\"; + if (GET_CODE (operands[1]) == EQ) + return \"rsbs\\t%0, %2, #1\;movcc\\t%0, #0\"; + } if (GET_CODE (operands[1]) == NE) { @@ -7347,6 +8013,192 @@ (set_attr "length" "8")] ) +(define_insn_and_split "*ior_scc_scc" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (ior:SI (match_operator:SI 3 "arm_comparison_operator" + [(match_operand:SI 1 "s_register_operand" "r") + (match_operand:SI 2 "arm_add_operand" "rIL")]) + (match_operator:SI 6 "arm_comparison_operator" + [(match_operand:SI 4 "s_register_operand" "r") + (match_operand:SI 5 "arm_add_operand" "rIL")]))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM + && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_OR_Y) + != CCmode)" + "#" + "TARGET_ARM && reload_completed" + [(set (match_dup 7) + (compare + (ior:SI + (match_op_dup 3 [(match_dup 1) (match_dup 2)]) + (match_op_dup 6 [(match_dup 4) (match_dup 5)])) + (const_int 0))) + (set (match_dup 0) (ne:SI (match_dup 7) (const_int 0)))] + "operands[7] + = gen_rtx_REG (arm_select_dominance_cc_mode (operands[3], operands[6], + DOM_CC_X_OR_Y), + CC_REGNUM);" + [(set_attr "conds" "clob") + (set_attr "length" "16")]) + +; If the above pattern is followed by a CMP insn, then the compare is +; redundant, since we can rework the conditional instruction that follows. +(define_insn_and_split "*ior_scc_scc_cmp" + [(set (match_operand 0 "dominant_cc_register" "") + (compare (ior:SI (match_operator:SI 3 "arm_comparison_operator" + [(match_operand:SI 1 "s_register_operand" "r") + (match_operand:SI 2 "arm_add_operand" "rIL")]) + (match_operator:SI 6 "arm_comparison_operator" + [(match_operand:SI 4 "s_register_operand" "r") + (match_operand:SI 5 "arm_add_operand" "rIL")])) + (const_int 0))) + (set (match_operand:SI 7 "s_register_operand" "=r") + (ior:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)]) + (match_op_dup 6 [(match_dup 4) (match_dup 5)])))] + "TARGET_ARM" + "#" + "TARGET_ARM && reload_completed" + [(set (match_dup 0) + (compare + (ior:SI + (match_op_dup 3 [(match_dup 1) (match_dup 2)]) + (match_op_dup 6 [(match_dup 4) (match_dup 5)])) + (const_int 0))) + (set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))] + "" + [(set_attr "conds" "set") + (set_attr "length" "16")]) + +(define_insn_and_split "*and_scc_scc" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (and:SI (match_operator:SI 3 "arm_comparison_operator" + [(match_operand:SI 1 "s_register_operand" "r") + (match_operand:SI 2 "arm_add_operand" "rIL")]) + (match_operator:SI 6 "arm_comparison_operator" + [(match_operand:SI 4 "s_register_operand" "r") + (match_operand:SI 5 "arm_add_operand" "rIL")]))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM + && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y) + != CCmode)" + "#" + "TARGET_ARM && reload_completed + && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y) + != CCmode)" + [(set (match_dup 7) + (compare + (and:SI + (match_op_dup 3 [(match_dup 1) (match_dup 2)]) + (match_op_dup 6 [(match_dup 4) (match_dup 5)])) + (const_int 0))) + (set (match_dup 0) (ne:SI (match_dup 7) (const_int 0)))] + "operands[7] + = gen_rtx_REG (arm_select_dominance_cc_mode (operands[3], operands[6], + DOM_CC_X_AND_Y), + CC_REGNUM);" + [(set_attr "conds" "clob") + (set_attr "length" "16")]) + +; If the above pattern is followed by a CMP insn, then the compare is +; redundant, since we can rework the conditional instruction that follows. +(define_insn_and_split "*and_scc_scc_cmp" + [(set (match_operand 0 "dominant_cc_register" "") + (compare (and:SI (match_operator:SI 3 "arm_comparison_operator" + [(match_operand:SI 1 "s_register_operand" "r") + (match_operand:SI 2 "arm_add_operand" "rIL")]) + (match_operator:SI 6 "arm_comparison_operator" + [(match_operand:SI 4 "s_register_operand" "r") + (match_operand:SI 5 "arm_add_operand" "rIL")])) + (const_int 0))) + (set (match_operand:SI 7 "s_register_operand" "=r") + (and:SI (match_op_dup 3 [(match_dup 1) (match_dup 2)]) + (match_op_dup 6 [(match_dup 4) (match_dup 5)])))] + "TARGET_ARM" + "#" + "TARGET_ARM && reload_completed" + [(set (match_dup 0) + (compare + (and:SI + (match_op_dup 3 [(match_dup 1) (match_dup 2)]) + (match_op_dup 6 [(match_dup 4) (match_dup 5)])) + (const_int 0))) + (set (match_dup 7) (ne:SI (match_dup 0) (const_int 0)))] + "" + [(set_attr "conds" "set") + (set_attr "length" "16")]) + +;; If there is no dominance in the comparison, then we can still save an +;; instruction in the AND case, since we can know that the second compare +;; need only zero the value if false (if true, then the value is already +;; correct). +(define_insn_and_split "*and_scc_scc_nodom" + [(set (match_operand:SI 0 "s_register_operand" "=&r,&r,&r") + (and:SI (match_operator:SI 3 "arm_comparison_operator" + [(match_operand:SI 1 "s_register_operand" "r,r,0") + (match_operand:SI 2 "arm_add_operand" "rIL,0,rIL")]) + (match_operator:SI 6 "arm_comparison_operator" + [(match_operand:SI 4 "s_register_operand" "r,r,r") + (match_operand:SI 5 "arm_add_operand" "rIL,rIL,rIL")]))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM + && (arm_select_dominance_cc_mode (operands[3], operands[6], DOM_CC_X_AND_Y) + == CCmode)" + "#" + "TARGET_ARM && reload_completed" + [(parallel [(set (match_dup 0) + (match_op_dup 3 [(match_dup 1) (match_dup 2)])) + (clobber (reg:CC CC_REGNUM))]) + (set (match_dup 7) (match_op_dup 8 [(match_dup 4) (match_dup 5)])) + (set (match_dup 0) + (if_then_else:SI (match_op_dup 6 [(match_dup 7) (const_int 0)]) + (match_dup 0) + (const_int 0)))] + "operands[7] = gen_rtx_REG (SELECT_CC_MODE (GET_CODE (operands[6]), + operands[4], operands[5]), + CC_REGNUM); + operands[8] = gen_rtx_COMPARE (GET_MODE (operands[7]), operands[4], + operands[5]);" + [(set_attr "conds" "clob") + (set_attr "length" "20")]) + +(define_split + [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV (ior:SI + (and:SI (match_operand:SI 0 "s_register_operand" "") + (const_int 1)) + (match_operator:SI 1 "comparison_operator" + [(match_operand:SI 2 "s_register_operand" "") + (match_operand:SI 3 "arm_add_operand" "")])) + (const_int 0))) + (clobber (match_operand:SI 4 "s_register_operand" ""))] + "TARGET_ARM" + [(set (match_dup 4) + (ior:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) + (match_dup 0))) + (set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV (and:SI (match_dup 4) (const_int 1)) + (const_int 0)))] + "") + +(define_split + [(set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV (ior:SI + (match_operator:SI 1 "comparison_operator" + [(match_operand:SI 2 "s_register_operand" "") + (match_operand:SI 3 "arm_add_operand" "")]) + (and:SI (match_operand:SI 0 "s_register_operand" "") + (const_int 1))) + (const_int 0))) + (clobber (match_operand:SI 4 "s_register_operand" ""))] + "TARGET_ARM" + [(set (match_dup 4) + (ior:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) + (match_dup 0))) + (set (reg:CC_NOOV CC_REGNUM) + (compare:CC_NOOV (and:SI (match_dup 4) (const_int 1)) + (const_int 0)))] + "") + (define_insn "*negscc" [(set (match_operand:SI 0 "s_register_operand" "=r") (neg:SI (match_operator 3 "arm_comparison_operator" @@ -7399,7 +8251,7 @@ return \"bics\\t%0, %2, %3, asr #32\;movcs\\t%0, %1\"; } /* The only case that falls through to here is when both ops 1 & 2 - are constants */ + are constants. */ } if (GET_CODE (operands[5]) == GE @@ -7418,7 +8270,7 @@ return \"ands\\t%0, %2, %3, asr #32\;movcc\\t%0, %1\"; } /* The only case that falls through to here is when both ops 1 & 2 - are constants */ + are constants. */ } if (GET_CODE (operands[4]) == CONST_INT && !const_ok_for_arm (INTVAL (operands[4]))) @@ -7555,7 +8407,7 @@ "* /* If we have an operation where (op x 0) is the identity operation and the conditional operator is LT or GE and we are comparing against zero and - everything is in registers then we can do this in two instructions */ + everything is in registers then we can do this in two instructions. */ if (operands[3] == const0_rtx && GET_CODE (operands[7]) != AND && GET_CODE (operands[5]) == REG @@ -8536,6 +9388,9 @@ (set (reg:CC CC_REGNUM) (compare:CC (match_dup 1) (const_int 0)))] "TARGET_ARM + && (!TARGET_CIRRUS + || (!cirrus_fp_register (operands[0], SImode) + && !cirrus_fp_register (operands[1], SImode))) " [(parallel [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 1) (const_int 0))) (set (match_dup 0) (match_dup 1))])] @@ -8699,9 +9554,9 @@ (unspec_volatile [(return)] VUNSPEC_EPILOGUE)])] "TARGET_ARM" "* - if (USE_RETURN_INSN (FALSE)) + if (use_return_insn (FALSE, next_nonnote_insn (insn))) return output_return_instruction (const_true_rtx, FALSE, FALSE); - return arm_output_epilogue (FALSE); + return arm_output_epilogue (next_nonnote_insn (insn)); " ;; Length is absolute worst case [(set_attr "length" "44") @@ -8717,7 +9572,7 @@ "TARGET_EITHER" "* if (TARGET_ARM) - return arm_output_epilogue (TRUE); + return arm_output_epilogue (NULL); else /* TARGET_THUMB */ return thumb_unexpanded_epilogue (); " @@ -8731,9 +9586,9 @@ ) (define_expand "eh_epilogue" - [(use (match_operand:SI 0 "register_operand" "r")) - (use (match_operand:SI 1 "register_operand" "r")) - (use (match_operand:SI 2 "register_operand" "r"))] + [(use (match_operand:SI 0 "register_operand" "")) + (use (match_operand:SI 1 "register_operand" "")) + (use (match_operand:SI 2 "register_operand" ""))] "TARGET_EITHER" " { @@ -9000,6 +9855,15 @@ " ) +(define_insn "align_8" + [(unspec_volatile [(const_int 0)] VUNSPEC_ALIGN8)] + "TARGET_REALLY_IWMMXT" + "* + assemble_align (64); + return \"\"; + " +) + (define_insn "consttable_end" [(unspec_volatile [(const_int 0)] VUNSPEC_POOL_END)] "TARGET_EITHER" @@ -9084,7 +9948,7 @@ ;; Miscellaneous Thumb patterns (define_expand "tablejump" - [(parallel [(set (pc) (match_operand:SI 0 "register_operand" "l*r")) + [(parallel [(set (pc) (match_operand:SI 0 "register_operand" "")) (use (label_ref (match_operand 1 "" "")))])] "TARGET_THUMB" " @@ -9110,12 +9974,12 @@ ;; V5 Instructions, -(define_insn "clz" - [(set (match_operand:SI 0 "s_register_operand" "=r") - (unspec:SI [(match_operand:SI 1 "s_register_operand" "r")] - UNSPEC_CLZ))] +(define_insn "clzsi2" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (clz:SI (match_operand:SI 1 "s_register_operand" "r")))] "TARGET_ARM && arm_arch5" - "clz\\t%0, %1") + "clz%?\\t%0, %1" + [(set_attr "predicable" "yes")]) (define_expand "ffssi2" [(set (match_operand:SI 0 "s_register_operand" "") @@ -9131,12 +9995,32 @@ emit_insn (gen_negsi2 (t1, operands[1])); emit_insn (gen_andsi3 (t2, operands[1], t1)); - emit_insn (gen_clz (t3, t2)); + emit_insn (gen_clzsi2 (t3, t2)); emit_insn (gen_subsi3 (operands[0], GEN_INT (32), t3)); DONE; }" ) +(define_expand "ctzsi2" + [(set (match_operand:SI 0 "s_register_operand" "") + (ctz:SI (match_operand:SI 1 "s_register_operand" "")))] + "TARGET_ARM && arm_arch5" + " + { + rtx t1, t2, t3; + + t1 = gen_reg_rtx (SImode); + t2 = gen_reg_rtx (SImode); + t3 = gen_reg_rtx (SImode); + + emit_insn (gen_negsi2 (t1, operands[1])); + emit_insn (gen_andsi3 (t2, operands[1], t1)); + emit_insn (gen_clzsi2 (t3, t2)); + emit_insn (gen_subsi3 (operands[0], GEN_INT (31), t3)); + DONE; + }" +) + ;; V5E instructions. (define_insn "prefetch" @@ -9161,3 +10045,10 @@ "" "%@ %0 needed for prologue" ) + +;; Load the FPA co-processor patterns +(include "fpa.md") +;; Load the Maverick co-processor patterns +(include "cirrus.md") +;; Load the Intel Wireless Multimedia Extension patterns +(include "iwmmxt.md") diff --git a/contrib/gcc/config/arm/cirrus.md b/contrib/gcc/config/arm/cirrus.md new file mode 100644 index 0000000..0da8469 --- /dev/null +++ b/contrib/gcc/config/arm/cirrus.md @@ -0,0 +1,478 @@ +;; Cirrus EP9312 "Maverick" ARM floating point co-processor description. +;; Copyright (C) 2003 Free Software Foundation, Inc. +;; Contributed by Red Hat. +;; Written by Aldy Hernandez (aldyh@redhat.com) + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING. If not, write to +;; the Free Software Foundation, 59 Temple Place - Suite 330, +;; Boston, MA 02111-1307, USA. + + +; Cirrus types for invalid insn combinations +; not Not a cirrus insn +; normal Any Cirrus insn not covered by the special cases below +; double cfldrd, cfldr64, cfstrd, cfstr64 +; compare cfcmps, cfcmpd, cfcmp32, cfcmp64 +; move cfmvdlr, cfmvdhr, cfmvsr, cfmv64lr, cfmv64hr +(define_attr "cirrus" "not,normal,double,compare,move" (const_string "not")) + + +(define_insn "cirrus_adddi3" + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (plus:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:DI 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfadd64%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] +) + +(define_insn "*cirrus_addsi3" + [(set (match_operand:SI 0 "cirrus_fp_register" "=v") + (plus:SI (match_operand:SI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS && 0" + "cfadd32%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] +) + +(define_insn "*cirrus_addsf3" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (plus:SF (match_operand:SF 1 "cirrus_fp_register" "v") + (match_operand:SF 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfadds%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] +) + +(define_insn "*cirrus_adddf3" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (plus:DF (match_operand:DF 1 "cirrus_fp_register" "v") + (match_operand:DF 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfaddd%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] +) + +(define_insn "cirrus_subdi3" + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (minus:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:DI 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfsub64%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] +) + +(define_insn "*cirrus_subsi3_insn" + [(set (match_operand:SI 0 "cirrus_fp_register" "=v") + (minus:SI (match_operand:SI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS && 0" + "cfsub32%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] +) + +(define_insn "*cirrus_subsf3" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (minus:SF (match_operand:SF 1 "cirrus_fp_register" "v") + (match_operand:SF 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfsubs%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] +) + +(define_insn "*cirrus_subdf3" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (minus:DF (match_operand:DF 1 "cirrus_fp_register" "v") + (match_operand:DF 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfsubd%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] +) + +(define_insn "*cirrus_mulsi3" + [(set (match_operand:SI 0 "cirrus_fp_register" "=v") + (mult:SI (match_operand:SI 2 "cirrus_fp_register" "v") + (match_operand:SI 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS && 0" + "cfmul32%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] +) + +(define_insn "muldi3" + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (mult:DI (match_operand:DI 2 "cirrus_fp_register" "v") + (match_operand:DI 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfmul64%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_dmult") + (set_attr "cirrus" "normal")] +) + +(define_insn "*cirrus_mulsi3addsi" + [(set (match_operand:SI 0 "cirrus_fp_register" "=v") + (plus:SI + (mult:SI (match_operand:SI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "cirrus_fp_register" "v")) + (match_operand:SI 3 "cirrus_fp_register" "0")))] + "TARGET_ARM && TARGET_CIRRUS && 0" + "cfmac32%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] +) + +;; Cirrus SI multiply-subtract +(define_insn "*cirrus_mulsi3subsi" + [(set (match_operand:SI 0 "cirrus_fp_register" "=v") + (minus:SI + (match_operand:SI 1 "cirrus_fp_register" "0") + (mult:SI (match_operand:SI 2 "cirrus_fp_register" "v") + (match_operand:SI 3 "cirrus_fp_register" "v"))))] + "0 && TARGET_ARM && TARGET_CIRRUS" + "cfmsc32%?\\t%V0, %V2, %V3" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] +) + +(define_insn "*cirrus_mulsf3" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (mult:SF (match_operand:SF 1 "cirrus_fp_register" "v") + (match_operand:SF 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfmuls%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_farith") + (set_attr "cirrus" "normal")] +) + +(define_insn "*cirrus_muldf3" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (mult:DF (match_operand:DF 1 "cirrus_fp_register" "v") + (match_operand:DF 2 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfmuld%?\\t%V0, %V1, %V2" + [(set_attr "type" "mav_dmult") + (set_attr "cirrus" "normal")] +) + +(define_insn "cirrus_ashl_const" + [(set (match_operand:SI 0 "cirrus_fp_register" "=v") + (ashift:SI (match_operand:SI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "cirrus_shift_const" "")))] + "TARGET_ARM && TARGET_CIRRUS && 0" + "cfsh32%?\\t%V0, %V1, #%s2" + [(set_attr "cirrus" "normal")] +) + +(define_insn "cirrus_ashiftrt_const" + [(set (match_operand:SI 0 "cirrus_fp_register" "=v") + (ashiftrt:SI (match_operand:SI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "cirrus_shift_const" "")))] + "TARGET_ARM && TARGET_CIRRUS && 0" + "cfsh32%?\\t%V0, %V1, #-%s2" + [(set_attr "cirrus" "normal")] +) + +(define_insn "cirrus_ashlsi3" + [(set (match_operand:SI 0 "cirrus_fp_register" "=v") + (ashift:SI (match_operand:SI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "register_operand" "r")))] + "TARGET_ARM && TARGET_CIRRUS && 0" + "cfrshl32%?\\t%V1, %V0, %s2" + [(set_attr "cirrus" "normal")] +) + +(define_insn "ashldi3_cirrus" + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "register_operand" "r")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfrshl64%?\\t%V1, %V0, %s2" + [(set_attr "cirrus" "normal")] +) + +(define_insn "cirrus_ashldi_const" + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (ashift:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "cirrus_shift_const" "")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfsh64%?\\t%V0, %V1, #%s2" + [(set_attr "cirrus" "normal")] +) + +(define_insn "cirrus_ashiftrtdi_const" + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (ashiftrt:DI (match_operand:DI 1 "cirrus_fp_register" "v") + (match_operand:SI 2 "cirrus_shift_const" "")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfsh64%?\\t%V0, %V1, #-%s2" + [(set_attr "cirrus" "normal")] +) + +(define_insn "*cirrus_absdi2" + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (abs:DI (match_operand:DI 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfabs64%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] +) + +;; This doesn't really clobber ``cc''. Fixme: aldyh. +(define_insn "*cirrus_negdi2" + [(set (match_operand:DI 0 "cirrus_fp_register" "=v") + (neg:DI (match_operand:DI 1 "cirrus_fp_register" "v"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM && TARGET_CIRRUS" + "cfneg64%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] +) + +(define_insn "*cirrus_negsi2" + [(set (match_operand:SI 0 "cirrus_fp_register" "=v") + (neg:SI (match_operand:SI 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS && 0" + "cfneg32%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] +) + +(define_insn "*cirrus_negsf2" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (neg:SF (match_operand:SF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfnegs%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] +) + +(define_insn "*cirrus_negdf2" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (neg:DF (match_operand:DF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfnegd%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] +) + +;; This doesn't really clobber the condition codes either. +(define_insn "*cirrus_abssi2" + [(set (match_operand:SI 0 "cirrus_fp_register" "=v") + (abs:SI (match_operand:SI 1 "cirrus_fp_register" "v"))) + (clobber (reg:CC CC_REGNUM))] + "TARGET_ARM && TARGET_CIRRUS && 0" + "cfabs32%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] +) + +(define_insn "*cirrus_abssf2" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (abs:SF (match_operand:SF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfabss%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] +) + +(define_insn "*cirrus_absdf2" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (abs:DF (match_operand:DF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfabsd%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] +) + +;; Convert Cirrus-SI to Cirrus-SF +(define_insn "cirrus_floatsisf2" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (float:SF (match_operand:SI 1 "s_register_operand" "r"))) + (clobber (match_scratch:DF 2 "=v"))] + "TARGET_ARM && TARGET_CIRRUS" + "cfmv64lr%?\\t%Z2, %1\;cfcvt32s%?\\t%V0, %Y2" + [(set_attr "length" "8") + (set_attr "cirrus" "move")] +) + +(define_insn "cirrus_floatsidf2" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (float:DF (match_operand:SI 1 "s_register_operand" "r"))) + (clobber (match_scratch:DF 2 "=v"))] + "TARGET_ARM && TARGET_CIRRUS" + "cfmv64lr%?\\t%Z2, %1\;cfcvt32d%?\\t%V0, %Y2" + [(set_attr "length" "8") + (set_attr "cirrus" "move")] +) + +(define_insn "floatdisf2" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (float:SF (match_operand:DI 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfcvt64s%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")]) + +(define_insn "floatdidf2" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (float:DF (match_operand:DI 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfcvt64d%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")]) + +(define_insn "cirrus_truncsfsi2" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (fix:SI (fix:SF (match_operand:SF 1 "cirrus_fp_register" "v")))) + (clobber (match_scratch:DF 2 "=v"))] + "TARGET_ARM && TARGET_CIRRUS" + "cftruncs32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" + [(set_attr "length" "8") + (set_attr "cirrus" "normal")] +) + +(define_insn "cirrus_truncdfsi2" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (fix:SI (fix:DF (match_operand:DF 1 "cirrus_fp_register" "v")))) + (clobber (match_scratch:DF 2 "=v"))] + "TARGET_ARM && TARGET_CIRRUS" + "cftruncd32%?\\t%Y2, %V1\;cfmvr64l%?\\t%0, %Z2" + [(set_attr "length" "8")] +) + +(define_insn "*cirrus_truncdfsf2" + [(set (match_operand:SF 0 "cirrus_fp_register" "=v") + (float_truncate:SF + (match_operand:DF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfcvtds%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] +) + +(define_insn "*cirrus_extendsfdf2" + [(set (match_operand:DF 0 "cirrus_fp_register" "=v") + (float_extend:DF (match_operand:SF 1 "cirrus_fp_register" "v")))] + "TARGET_ARM && TARGET_CIRRUS" + "cfcvtsd%?\\t%V0, %V1" + [(set_attr "cirrus" "normal")] +) + +(define_insn "*cirrus_arm_movdi" + [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r,r,o<>,v,r,v,m,v") + (match_operand:DI 1 "di_operand" "rIK,mi,r,r,v,m,v,v"))] + "TARGET_ARM && TARGET_CIRRUS" + "* + { + switch (which_alternative) + { + case 0: + case 1: + case 2: + return (output_move_double (operands)); + + case 3: return \"cfmv64lr%?\\t%V0, %Q1\;cfmv64hr%?\\t%V0, %R1\"; + case 4: return \"cfmvr64l%?\\t%Q0, %V1\;cfmvr64h%?\\t%R0, %V1\"; + + case 5: return \"cfldr64%?\\t%V0, %1\"; + case 6: return \"cfstr64%?\\t%V1, %0\"; + + /* Shifting by 0 will just copy %1 into %0. */ + case 7: return \"cfsh64%?\\t%V0, %V1, #0\"; + + default: abort (); + } + }" + [(set_attr "length" " 8, 8, 8, 8, 8, 4, 4, 4") + (set_attr "type" " *,load,store2, *, *, load,store2, *") + (set_attr "pool_range" " *,1020, *, *, *, *, *, *") + (set_attr "neg_pool_range" " *,1012, *, *, *, *, *, *") + (set_attr "cirrus" "not, not, not,move,normal,double,double,normal")] +) + +;; Cirrus SI values have been outlawed. Look in arm.h for the comment +;; on HARD_REGNO_MODE_OK. + +(define_insn "*cirrus_arm_movsi_insn" + [(set (match_operand:SI 0 "general_operand" "=r,r,r,m,*v,r,*v,T,*v") + (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,*v,T,*v,*v"))] + "TARGET_ARM && TARGET_CIRRUS && 0 + && (register_operand (operands[0], SImode) + || register_operand (operands[1], SImode))" + "@ + mov%?\\t%0, %1 + mvn%?\\t%0, #%B1 + ldr%?\\t%0, %1 + str%?\\t%1, %0 + cfmv64lr%?\\t%Z0, %1 + cfmvr64l%?\\t%0, %Z1 + cfldr32%?\\t%V0, %1 + cfstr32%?\\t%V1, %0 + cfsh32%?\\t%V0, %V1, #0" + [(set_attr "type" "*, *, load,store1, *, *, load,store1, *") + (set_attr "pool_range" "*, *, 4096, *, *, *, 1024, *, *") + (set_attr "neg_pool_range" "*, *, 4084, *, *, *, 1012, *, *") + (set_attr "cirrus" "not,not, not, not,move,normal,normal,normal,normal")] +) + +(define_insn "*cirrus_movsf_hard_insn" + [(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m") + (match_operand:SF 1 "general_operand" "v,m,r,v,v,r,mE,r"))] + "TARGET_ARM && TARGET_CIRRUS + && (GET_CODE (operands[0]) != MEM + || register_operand (operands[1], SFmode))" + "@ + cfcpys%?\\t%V0, %V1 + cfldrs%?\\t%V0, %1 + cfmvsr%?\\t%V0, %1 + cfmvrs%?\\t%0, %V1 + cfstrs%?\\t%V1, %0 + mov%?\\t%0, %1 + ldr%?\\t%0, %1\\t%@ float + str%?\\t%1, %0\\t%@ float" + [(set_attr "length" " *, *, *, *, *, 4, 4, 4") + (set_attr "type" " *, load, *, *,store1, *,load,store1") + (set_attr "pool_range" " *, *, *, *, *, *,4096, *") + (set_attr "neg_pool_range" " *, *, *, *, *, *,4084, *") + (set_attr "cirrus" "normal,normal,move,normal,normal,not, not, not")] +) + +(define_insn "*cirrus_movdf_hard_insn" + [(set (match_operand:DF 0 "nonimmediate_operand" "=r,Q,r,m,r,v,v,v,r,m") + (match_operand:DF 1 "general_operand" "Q,r,r,r,mF,v,m,r,v,v"))] + "TARGET_ARM + && TARGET_CIRRUS + && (GET_CODE (operands[0]) != MEM + || register_operand (operands[1], DFmode))" + "* + { + switch (which_alternative) + { + case 0: return \"ldm%?ia\\t%m1, %M0\\t%@ double\"; + case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\"; + case 2: case 3: case 4: return output_move_double (operands); + case 5: return \"cfcpyd%?\\t%V0, %V1\"; + case 6: return \"cfldrd%?\\t%V0, %1\"; + case 7: return \"cfmvdlr\\t%V0, %Q1\;cfmvdhr%?\\t%V0, %R1\"; + case 8: return \"cfmvrdl%?\\t%Q0, %V1\;cfmvrdh%?\\t%R0, %V1\"; + case 9: return \"cfstrd%?\\t%V1, %0\"; + default: abort (); + } + }" + [(set_attr "type" "load,store2, *,store2,load, *, load, *, *,store2") + (set_attr "length" " 4, 4, 8, 8, 8, 4, 4, 8, 8, 4") + (set_attr "pool_range" " *, *, *, *, 252, *, *, *, *, *") + (set_attr "neg_pool_range" " *, *, *, *, 244, *, *, *, *, *") + (set_attr "cirrus" " not, not,not, not, not,normal,double,move,normal,double")] +) + diff --git a/contrib/gcc/config/arm/coff.h b/contrib/gcc/config/arm/coff.h index 0a78268..d6a6651 100644 --- a/contrib/gcc/config/arm/coff.h +++ b/contrib/gcc/config/arm/coff.h @@ -1,28 +1,27 @@ /* Definitions of target machine for GNU compiler. For ARM with COFF object format. - Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2002 + Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2002, 2003 Free Software Foundation, Inc. Contributed by Doug Evans (devans@cygnus.com). -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ - -/* Note - it is important that this definition matches the one in tcoff.h */ +/* Note - it is important that this definition matches the one in tcoff.h. */ #undef USER_LABEL_PREFIX #define USER_LABEL_PREFIX "_" @@ -32,7 +31,7 @@ Boston, MA 02111-1307, USA. */ #define TARGET_VERSION fputs (" (ARM/coff)", stderr) #undef TARGET_DEFAULT -#define TARGET_DEFAULT (ARM_FLAG_SOFT_FLOAT | ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME) +#define TARGET_DEFAULT (ARM_FLAG_SOFT_FLOAT | ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME | ARM_FLAG_MMU_TRAPS) #ifndef MULTILIB_DEFAULTS #define MULTILIB_DEFAULTS \ @@ -44,23 +43,8 @@ Boston, MA 02111-1307, USA. */ #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG -#include "dbxcoff.h" -/* A C statement to output assembler commands which will identify the - object file as having been compiled with GNU CC (or another GNU - compiler). */ - -/* This outputs a lot of .req's to define alias for various registers. - Let's try to avoid this. */ -#undef ASM_FILE_START -#define ASM_FILE_START(STREAM) \ - do \ - { \ - fprintf (STREAM, "%s Generated by gcc %s for ARM/coff\n", \ - ASM_COMMENT_START, version_string); \ - fprintf (STREAM, ASM_APP_OFF); \ - } \ - while (0) +#define TARGET_ASM_FILE_START_APP_OFF true /* Switch into a generic section. */ #define TARGET_ASM_NAMED_SECTION default_coff_asm_named_section diff --git a/contrib/gcc/config/arm/crtn.asm b/contrib/gcc/config/arm/crtn.asm index 2f4b542..9ad75e3 100644 --- a/contrib/gcc/config/arm/crtn.asm +++ b/contrib/gcc/config/arm/crtn.asm @@ -39,7 +39,7 @@ # in crti.asm. If you change this macro you must also change # that macro match. # - # Note - we do not try any fancy optimisations of the return + # Note - we do not try any fancy optimizations of the return # sequences here, it is just not worth it. Instead keep things # simple. Restore all the save resgisters, including the link # register and then perform the correct function return instruction. diff --git a/contrib/gcc/config/arm/ecos-elf.h b/contrib/gcc/config/arm/ecos-elf.h index f1377a9..d57fe8b 100644 --- a/contrib/gcc/config/arm/ecos-elf.h +++ b/contrib/gcc/config/arm/ecos-elf.h @@ -1,22 +1,22 @@ /* Definitions for ecos based ARM systems using ELF Copyright (C) 1998, 2001 Free Software Foundation, Inc. -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with this program; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ /* Run-time Target Specification. */ #undef TARGET_VERSION diff --git a/contrib/gcc/config/arm/elf.h b/contrib/gcc/config/arm/elf.h index 0ad23f8..cb38264 100644 --- a/contrib/gcc/config/arm/elf.h +++ b/contrib/gcc/config/arm/elf.h @@ -5,22 +5,22 @@ Contributed by Philip Blundell <philb@gnu.org> and Catherine Moore <clm@cygnus.com> -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ #ifndef OBJECT_FORMAT_ELF #error elf.h included before elfos.h @@ -46,7 +46,7 @@ Boston, MA 02111-1307, USA. */ #ifndef SUBTARGET_ASM_FLOAT_SPEC #define SUBTARGET_ASM_FLOAT_SPEC "\ -%{mapcs-float:-mfloat} %{msoft-float:-mno-fpu}" +%{mapcs-float:-mfloat} %{msoft-float:-mfpu=softfpa}" #endif #ifndef ASM_SPEC @@ -106,7 +106,7 @@ Boston, MA 02111-1307, USA. */ #endif #ifndef TARGET_DEFAULT -#define TARGET_DEFAULT (ARM_FLAG_SOFT_FLOAT | ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME) +#define TARGET_DEFAULT (ARM_FLAG_SOFT_FLOAT | ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME | ARM_FLAG_MMU_TRAPS) #endif #ifndef MULTILIB_DEFAULTS @@ -114,53 +114,12 @@ Boston, MA 02111-1307, USA. */ { "marm", "mlittle-endian", "msoft-float", "mapcs-32", "mno-thumb-interwork", "fno-leading-underscore" } #endif - -/* This outputs a lot of .req's to define alias for various registers. - Let's try to avoid this. */ -#ifndef ASM_FILE_START -#define ASM_FILE_START(STREAM) \ - do \ - { \ - fprintf (STREAM, "%s Generated by gcc %s for ARM/elf\n", \ - ASM_COMMENT_START, version_string); \ - output_file_directive (STREAM, main_input_filename); \ - fprintf (STREAM, ASM_APP_OFF); \ - } \ - while (0) -#endif - -/* Output an internal label definition. */ -#undef ASM_OUTPUT_INTERNAL_LABEL -#define ASM_OUTPUT_INTERNAL_LABEL(STREAM, PREFIX, NUM) \ - do \ - { \ - char * s = (char *) alloca (40 + strlen (PREFIX)); \ - extern int arm_target_label, arm_ccfsm_state; \ - extern rtx arm_target_insn; \ - \ - if (arm_ccfsm_state == 3 && arm_target_label == (NUM) \ - && !strcmp (PREFIX, "L")) \ - { \ - arm_ccfsm_state = 0; \ - arm_target_insn = NULL; \ - } \ - ASM_GENERATE_INTERNAL_LABEL (s, (PREFIX), (NUM)); \ - ASM_OUTPUT_LABEL (STREAM, s); \ - } \ - while (0) +#define TARGET_ASM_FILE_START_APP_OFF true +#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true #undef TARGET_ASM_NAMED_SECTION #define TARGET_ASM_NAMED_SECTION arm_elf_asm_named_section -#undef ASM_OUTPUT_ALIGNED_COMMON -#define ASM_OUTPUT_ALIGNED_COMMON(STREAM, NAME, SIZE, ALIGN) \ - do \ - { \ - fprintf (STREAM, "\t.comm\t"); \ - assemble_name (STREAM, NAME); \ - fprintf (STREAM, ", %d, %d\n", SIZE, ALIGN); \ - } \ - while (0) /* For PIC code we need to explicitly specify (PLT) and (GOT) relocs. */ #define NEED_PLT_RELOC flag_pic diff --git a/contrib/gcc/config/arm/fpa.md b/contrib/gcc/config/arm/fpa.md new file mode 100644 index 0000000..3b6efbf --- /dev/null +++ b/contrib/gcc/config/arm/fpa.md @@ -0,0 +1,752 @@ +;;- Machine description for FPA co-processor for ARM cpus. +;; Copyright 1991, 1993, 1994, 1995, 1996, 1996, 1997, 1998, 1999, 2000, +;; 2001, 2002, 2003 Free Software Foundation, Inc. +;; Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) +;; and Martin Simmons (@harleqn.co.uk). +;; More major hacks by Richard Earnshaw (rearnsha@arm.com). + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 2, or (at your +;; option) any later version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING. If not, write to +;; the Free Software Foundation, 59 Temple Place - Suite 330, +;; Boston, MA 02111-1307, USA. + +;; FPA automaton. +(define_automaton "armfp") + +;; Floating point unit (FPA) +(define_cpu_unit "fpa" "armfp") + +; The fpa10 doesn't really have a memory read unit, but it can start +; to speculatively execute the instruction in the pipeline, provided +; the data is already loaded, so pretend reads have a delay of 2 (and +; that the pipeline is infinite). +(define_cpu_unit "fpa_mem" "arm") + +(define_insn_reservation "fdivx" 71 + (and (eq_attr "fpu" "fpa") + (eq_attr "type" "fdivx")) + "core+fpa*69") + +(define_insn_reservation "fdivd" 59 + (and (eq_attr "fpu" "fpa") + (eq_attr "type" "fdivd")) + "core+fpa*57") + +(define_insn_reservation "fdivs" 31 + (and (eq_attr "fpu" "fpa") + (eq_attr "type" "fdivs")) + "core+fpa*29") + +(define_insn_reservation "fmul" 9 + (and (eq_attr "fpu" "fpa") + (eq_attr "type" "fmul")) + "core+fpa*7") + +(define_insn_reservation "ffmul" 6 + (and (eq_attr "fpu" "fpa") + (eq_attr "type" "ffmul")) + "core+fpa*4") + +(define_insn_reservation "farith" 4 + (and (eq_attr "fpu" "fpa") + (eq_attr "type" "farith")) + "core+fpa*2") + +(define_insn_reservation "ffarith" 2 + (and (eq_attr "fpu" "fpa") + (eq_attr "type" "ffarith")) + "core+fpa*2") + +(define_insn_reservation "r_2_f" 5 + (and (eq_attr "fpu" "fpa") + (eq_attr "type" "r_2_f")) + "core+fpa*3") + +(define_insn_reservation "f_2_r" 1 + (and (eq_attr "fpu" "fpa") + (eq_attr "type" "f_2_r")) + "core+fpa*2") + +(define_insn_reservation "f_load" 3 + (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_load")) + "fpa_mem+core*3") + +(define_insn_reservation "f_store" 4 + (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_store")) + "core*4") + +(define_insn_reservation "r_mem_f" 6 + (and (eq_attr "model_wbuf" "no") + (and (eq_attr "fpu" "fpa") (eq_attr "type" "r_mem_f"))) + "core*6") + +(define_insn_reservation "f_mem_r" 7 + (and (eq_attr "fpu" "fpa") (eq_attr "type" "f_mem_r")) + "core*7") + + +(define_insn "*addsf3_fpa" + [(set (match_operand:SF 0 "s_register_operand" "=f,f") + (plus:SF (match_operand:SF 1 "s_register_operand" "%f,f") + (match_operand:SF 2 "fpa_add_operand" "fG,H")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "@ + adf%?s\\t%0, %1, %2 + suf%?s\\t%0, %1, #%N2" + [(set_attr "type" "farith") + (set_attr "predicable" "yes")] +) + +(define_insn "*adddf3_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f,f") + (plus:DF (match_operand:DF 1 "s_register_operand" "%f,f") + (match_operand:DF 2 "fpa_add_operand" "fG,H")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "@ + adf%?d\\t%0, %1, %2 + suf%?d\\t%0, %1, #%N2" + [(set_attr "type" "farith") + (set_attr "predicable" "yes")] +) + +(define_insn "*adddf_esfdf_df_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f,f") + (plus:DF (float_extend:DF + (match_operand:SF 1 "s_register_operand" "f,f")) + (match_operand:DF 2 "fpa_add_operand" "fG,H")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "@ + adf%?d\\t%0, %1, %2 + suf%?d\\t%0, %1, #%N2" + [(set_attr "type" "farith") + (set_attr "predicable" "yes")] +) + +(define_insn "*adddf_df_esfdf_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f") + (plus:DF (match_operand:DF 1 "s_register_operand" "f") + (float_extend:DF + (match_operand:SF 2 "s_register_operand" "f"))))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "adf%?d\\t%0, %1, %2" + [(set_attr "type" "farith") + (set_attr "predicable" "yes")] +) + +(define_insn "*adddf_esfdf_esfdf_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f") + (plus:DF (float_extend:DF + (match_operand:SF 1 "s_register_operand" "f")) + (float_extend:DF + (match_operand:SF 2 "s_register_operand" "f"))))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "adf%?d\\t%0, %1, %2" + [(set_attr "type" "farith") + (set_attr "predicable" "yes")] +) + +(define_insn "*subsf3_fpa" + [(set (match_operand:SF 0 "s_register_operand" "=f,f") + (minus:SF (match_operand:SF 1 "fpa_rhs_operand" "f,G") + (match_operand:SF 2 "fpa_rhs_operand" "fG,f")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "@ + suf%?s\\t%0, %1, %2 + rsf%?s\\t%0, %2, %1" + [(set_attr "type" "farith")] +) + +(define_insn "*subdf3_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f,f") + (minus:DF (match_operand:DF 1 "fpa_rhs_operand" "f,G") + (match_operand:DF 2 "fpa_rhs_operand" "fG,f")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "@ + suf%?d\\t%0, %1, %2 + rsf%?d\\t%0, %2, %1" + [(set_attr "type" "farith") + (set_attr "predicable" "yes")] +) + +(define_insn "*subdf_esfdf_df_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f") + (minus:DF (float_extend:DF + (match_operand:SF 1 "s_register_operand" "f")) + (match_operand:DF 2 "fpa_rhs_operand" "fG")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "suf%?d\\t%0, %1, %2" + [(set_attr "type" "farith") + (set_attr "predicable" "yes")] +) + +(define_insn "*subdf_df_esfdf_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f,f") + (minus:DF (match_operand:DF 1 "fpa_rhs_operand" "f,G") + (float_extend:DF + (match_operand:SF 2 "s_register_operand" "f,f"))))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "@ + suf%?d\\t%0, %1, %2 + rsf%?d\\t%0, %2, %1" + [(set_attr "type" "farith") + (set_attr "predicable" "yes")] +) + +(define_insn "*subdf_esfdf_esfdf_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f") + (minus:DF (float_extend:DF + (match_operand:SF 1 "s_register_operand" "f")) + (float_extend:DF + (match_operand:SF 2 "s_register_operand" "f"))))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "suf%?d\\t%0, %1, %2" + [(set_attr "type" "farith") + (set_attr "predicable" "yes")] +) + +(define_insn "*mulsf3_fpa" + [(set (match_operand:SF 0 "s_register_operand" "=f") + (mult:SF (match_operand:SF 1 "s_register_operand" "f") + (match_operand:SF 2 "fpa_rhs_operand" "fG")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "fml%?s\\t%0, %1, %2" + [(set_attr "type" "ffmul") + (set_attr "predicable" "yes")] +) + +(define_insn "*muldf3_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f") + (mult:DF (match_operand:DF 1 "s_register_operand" "f") + (match_operand:DF 2 "fpa_rhs_operand" "fG")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "muf%?d\\t%0, %1, %2" + [(set_attr "type" "fmul") + (set_attr "predicable" "yes")] +) + +(define_insn "*muldf_esfdf_df_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f") + (mult:DF (float_extend:DF + (match_operand:SF 1 "s_register_operand" "f")) + (match_operand:DF 2 "fpa_rhs_operand" "fG")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "muf%?d\\t%0, %1, %2" + [(set_attr "type" "fmul") + (set_attr "predicable" "yes")] +) + +(define_insn "*muldf_df_esfdf_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f") + (mult:DF (match_operand:DF 1 "s_register_operand" "f") + (float_extend:DF + (match_operand:SF 2 "s_register_operand" "f"))))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "muf%?d\\t%0, %1, %2" + [(set_attr "type" "fmul") + (set_attr "predicable" "yes")] +) + +(define_insn "*muldf_esfdf_esfdf_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f") + (mult:DF + (float_extend:DF (match_operand:SF 1 "s_register_operand" "f")) + (float_extend:DF (match_operand:SF 2 "s_register_operand" "f"))))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "muf%?d\\t%0, %1, %2" + [(set_attr "type" "fmul") + (set_attr "predicable" "yes")] +) + +;; Division insns + +(define_insn "*divsf3_fpa" + [(set (match_operand:SF 0 "s_register_operand" "=f,f") + (div:SF (match_operand:SF 1 "fpa_rhs_operand" "f,G") + (match_operand:SF 2 "fpa_rhs_operand" "fG,f")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "@ + fdv%?s\\t%0, %1, %2 + frd%?s\\t%0, %2, %1" + [(set_attr "type" "fdivs") + (set_attr "predicable" "yes")] +) + +(define_insn "*divdf3_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f,f") + (div:DF (match_operand:DF 1 "fpa_rhs_operand" "f,G") + (match_operand:DF 2 "fpa_rhs_operand" "fG,f")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "@ + dvf%?d\\t%0, %1, %2 + rdf%?d\\t%0, %2, %1" + [(set_attr "type" "fdivd") + (set_attr "predicable" "yes")] +) + +(define_insn "*divdf_esfdf_df_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f") + (div:DF (float_extend:DF + (match_operand:SF 1 "s_register_operand" "f")) + (match_operand:DF 2 "fpa_rhs_operand" "fG")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "dvf%?d\\t%0, %1, %2" + [(set_attr "type" "fdivd") + (set_attr "predicable" "yes")] +) + +(define_insn "*divdf_df_esfdf_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f") + (div:DF (match_operand:DF 1 "fpa_rhs_operand" "fG") + (float_extend:DF + (match_operand:SF 2 "s_register_operand" "f"))))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "rdf%?d\\t%0, %2, %1" + [(set_attr "type" "fdivd") + (set_attr "predicable" "yes")] +) + +(define_insn "*divdf_esfdf_esfdf_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f") + (div:DF (float_extend:DF + (match_operand:SF 1 "s_register_operand" "f")) + (float_extend:DF + (match_operand:SF 2 "s_register_operand" "f"))))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "dvf%?d\\t%0, %1, %2" + [(set_attr "type" "fdivd") + (set_attr "predicable" "yes")] +) + +(define_insn "*modsf3_fpa" + [(set (match_operand:SF 0 "s_register_operand" "=f") + (mod:SF (match_operand:SF 1 "s_register_operand" "f") + (match_operand:SF 2 "fpa_rhs_operand" "fG")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "rmf%?s\\t%0, %1, %2" + [(set_attr "type" "fdivs") + (set_attr "predicable" "yes")] +) + +(define_insn "*moddf3_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f") + (mod:DF (match_operand:DF 1 "s_register_operand" "f") + (match_operand:DF 2 "fpa_rhs_operand" "fG")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "rmf%?d\\t%0, %1, %2" + [(set_attr "type" "fdivd") + (set_attr "predicable" "yes")] +) + +(define_insn "*moddf_esfdf_df_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f") + (mod:DF (float_extend:DF + (match_operand:SF 1 "s_register_operand" "f")) + (match_operand:DF 2 "fpa_rhs_operand" "fG")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "rmf%?d\\t%0, %1, %2" + [(set_attr "type" "fdivd") + (set_attr "predicable" "yes")] +) + +(define_insn "*moddf_df_esfdf_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f") + (mod:DF (match_operand:DF 1 "s_register_operand" "f") + (float_extend:DF + (match_operand:SF 2 "s_register_operand" "f"))))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "rmf%?d\\t%0, %1, %2" + [(set_attr "type" "fdivd") + (set_attr "predicable" "yes")] +) + +(define_insn "*moddf_esfdf_esfdf_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f") + (mod:DF (float_extend:DF + (match_operand:SF 1 "s_register_operand" "f")) + (float_extend:DF + (match_operand:SF 2 "s_register_operand" "f"))))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "rmf%?d\\t%0, %1, %2" + [(set_attr "type" "fdivd") + (set_attr "predicable" "yes")] +) + +(define_insn "*negsf2_fpa" + [(set (match_operand:SF 0 "s_register_operand" "=f") + (neg:SF (match_operand:SF 1 "s_register_operand" "f")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "mnf%?s\\t%0, %1" + [(set_attr "type" "ffarith") + (set_attr "predicable" "yes")] +) + +(define_insn "*negdf2_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f") + (neg:DF (match_operand:DF 1 "s_register_operand" "f")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "mnf%?d\\t%0, %1" + [(set_attr "type" "ffarith") + (set_attr "predicable" "yes")] +) + +(define_insn "*negdf_esfdf_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f") + (neg:DF (float_extend:DF + (match_operand:SF 1 "s_register_operand" "f"))))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "mnf%?d\\t%0, %1" + [(set_attr "type" "ffarith") + (set_attr "predicable" "yes")] +) + +(define_insn "*abssf2_fpa" + [(set (match_operand:SF 0 "s_register_operand" "=f") + (abs:SF (match_operand:SF 1 "s_register_operand" "f")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "abs%?s\\t%0, %1" + [(set_attr "type" "ffarith") + (set_attr "predicable" "yes")] +) + +(define_insn "*absdf2_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f") + (abs:DF (match_operand:DF 1 "s_register_operand" "f")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "abs%?d\\t%0, %1" + [(set_attr "type" "ffarith") + (set_attr "predicable" "yes")] +) + +(define_insn "*absdf_esfdf_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f") + (abs:DF (float_extend:DF + (match_operand:SF 1 "s_register_operand" "f"))))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "abs%?d\\t%0, %1" + [(set_attr "type" "ffarith") + (set_attr "predicable" "yes")] +) + +(define_insn "*sqrtsf2_fpa" + [(set (match_operand:SF 0 "s_register_operand" "=f") + (sqrt:SF (match_operand:SF 1 "s_register_operand" "f")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "sqt%?s\\t%0, %1" + [(set_attr "type" "float_em") + (set_attr "predicable" "yes")] +) + +(define_insn "*sqrtdf2_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f") + (sqrt:DF (match_operand:DF 1 "s_register_operand" "f")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "sqt%?d\\t%0, %1" + [(set_attr "type" "float_em") + (set_attr "predicable" "yes")] +) + +(define_insn "*sqrtdf_esfdf_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f") + (sqrt:DF (float_extend:DF + (match_operand:SF 1 "s_register_operand" "f"))))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "sqt%?d\\t%0, %1" + [(set_attr "type" "float_em") + (set_attr "predicable" "yes")] +) + +(define_insn "*floatsisf2_fpa" + [(set (match_operand:SF 0 "s_register_operand" "=f") + (float:SF (match_operand:SI 1 "s_register_operand" "r")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "flt%?s\\t%0, %1" + [(set_attr "type" "r_2_f") + (set_attr "predicable" "yes")] +) + +(define_insn "*floatsidf2_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f") + (float:DF (match_operand:SI 1 "s_register_operand" "r")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "flt%?d\\t%0, %1" + [(set_attr "type" "r_2_f") + (set_attr "predicable" "yes")] +) + +(define_insn "*fix_truncsfsi2_fpa" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (fix:SI (fix:SF (match_operand:SF 1 "s_register_operand" "f"))))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "fix%?z\\t%0, %1" + [(set_attr "type" "f_2_r") + (set_attr "predicable" "yes")] +) + +(define_insn "*fix_truncdfsi2_fpa" + [(set (match_operand:SI 0 "s_register_operand" "=r") + (fix:SI (fix:DF (match_operand:DF 1 "s_register_operand" "f"))))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "fix%?z\\t%0, %1" + [(set_attr "type" "f_2_r") + (set_attr "predicable" "yes")] +) + +(define_insn "*truncdfsf2_fpa" + [(set (match_operand:SF 0 "s_register_operand" "=f") + (float_truncate:SF + (match_operand:DF 1 "s_register_operand" "f")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "mvf%?s\\t%0, %1" + [(set_attr "type" "ffarith") + (set_attr "predicable" "yes")] +) + +(define_insn "*extendsfdf2_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f") + (float_extend:DF (match_operand:SF 1 "s_register_operand" "f")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "mvf%?d\\t%0, %1" + [(set_attr "type" "ffarith") + (set_attr "predicable" "yes")] +) + +(define_insn "*movsf_fpa" + [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f, m,f,r,r,r, m") + (match_operand:SF 1 "general_operand" "fG,H,mE,f,r,f,r,mE,r"))] + "TARGET_ARM + && TARGET_HARD_FLOAT + && (GET_CODE (operands[0]) != MEM + || register_operand (operands[1], SFmode))" + "@ + mvf%?s\\t%0, %1 + mnf%?s\\t%0, #%N1 + ldf%?s\\t%0, %1 + stf%?s\\t%1, %0 + str%?\\t%1, [%|sp, #-4]!\;ldf%?s\\t%0, [%|sp], #4 + stf%?s\\t%1, [%|sp, #-4]!\;ldr%?\\t%0, [%|sp], #4 + mov%?\\t%0, %1 + ldr%?\\t%0, %1\\t%@ float + str%?\\t%1, %0\\t%@ float" + [(set_attr "length" "4,4,4,4,8,8,4,4,4") + (set_attr "predicable" "yes") + (set_attr "type" + "ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*,load,store1") + (set_attr "pool_range" "*,*,1024,*,*,*,*,4096,*") + (set_attr "neg_pool_range" "*,*,1012,*,*,*,*,4084,*")] +) + +(define_insn "*movdf_fpa" + [(set (match_operand:DF 0 "nonimmediate_operand" + "=r,Q,r,m,r, f, f,f, m,!f,!r") + (match_operand:DF 1 "general_operand" + "Q, r,r,r,mF,fG,H,mF,f,r, f"))] + "TARGET_ARM + && TARGET_HARD_FLOAT + && (GET_CODE (operands[0]) != MEM + || register_operand (operands[1], DFmode))" + "* + { + switch (which_alternative) + { + default: + case 0: return \"ldm%?ia\\t%m1, %M0\\t%@ double\"; + case 1: return \"stm%?ia\\t%m0, %M1\\t%@ double\"; + case 2: case 3: case 4: return output_move_double (operands); + case 5: return \"mvf%?d\\t%0, %1\"; + case 6: return \"mnf%?d\\t%0, #%N1\"; + case 7: return \"ldf%?d\\t%0, %1\"; + case 8: return \"stf%?d\\t%1, %0\"; + case 9: return output_mov_double_fpa_from_arm (operands); + case 10: return output_mov_double_arm_from_fpa (operands); + } + } + " + [(set_attr "length" "4,4,8,8,8,4,4,4,4,8,8") + (set_attr "predicable" "yes") + (set_attr "type" + "load,store2,*,store2,load,ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r") + (set_attr "pool_range" "*,*,*,*,1020,*,*,1024,*,*,*") + (set_attr "neg_pool_range" "*,*,*,*,1008,*,*,1008,*,*,*")] +) + +;; Saving and restoring the floating point registers in the prologue should +;; be done in XFmode, even though we don't support that for anything else +;; (Well, strictly it's 'internal representation', but that's effectively +;; XFmode). + +(define_insn "*movxf_fpa" + [(set (match_operand:XF 0 "nonimmediate_operand" "=f,f,f,m,f,r,r") + (match_operand:XF 1 "general_operand" "fG,H,m,f,r,f,r"))] + "TARGET_ARM && TARGET_HARD_FLOAT && reload_completed" + "* + switch (which_alternative) + { + default: + case 0: return \"mvf%?e\\t%0, %1\"; + case 1: return \"mnf%?e\\t%0, #%N1\"; + case 2: return \"ldf%?e\\t%0, %1\"; + case 3: return \"stf%?e\\t%1, %0\"; + case 4: return output_mov_long_double_fpa_from_arm (operands); + case 5: return output_mov_long_double_arm_from_fpa (operands); + case 6: return output_mov_long_double_arm_from_arm (operands); + } + " + [(set_attr "length" "4,4,4,4,8,8,12") + (set_attr "predicable" "yes") + (set_attr "type" "ffarith,ffarith,f_load,f_store,r_mem_f,f_mem_r,*") + (set_attr "pool_range" "*,*,1024,*,*,*,*") + (set_attr "neg_pool_range" "*,*,1004,*,*,*,*")] +) + +(define_insn "*cmpsf_fpa" + [(set (reg:CCFP CC_REGNUM) + (compare:CCFP (match_operand:SF 0 "s_register_operand" "f,f") + (match_operand:SF 1 "fpa_add_operand" "fG,H")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "@ + cmf%?\\t%0, %1 + cnf%?\\t%0, #%N1" + [(set_attr "conds" "set") + (set_attr "type" "f_2_r")] +) + +(define_insn "*cmpdf_fpa" + [(set (reg:CCFP CC_REGNUM) + (compare:CCFP (match_operand:DF 0 "s_register_operand" "f,f") + (match_operand:DF 1 "fpa_add_operand" "fG,H")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "@ + cmf%?\\t%0, %1 + cnf%?\\t%0, #%N1" + [(set_attr "conds" "set") + (set_attr "type" "f_2_r")] +) + +(define_insn "*cmpesfdf_df_fpa" + [(set (reg:CCFP CC_REGNUM) + (compare:CCFP (float_extend:DF + (match_operand:SF 0 "s_register_operand" "f,f")) + (match_operand:DF 1 "fpa_add_operand" "fG,H")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "@ + cmf%?\\t%0, %1 + cnf%?\\t%0, #%N1" + [(set_attr "conds" "set") + (set_attr "type" "f_2_r")] +) + +(define_insn "*cmpdf_esfdf_fpa" + [(set (reg:CCFP CC_REGNUM) + (compare:CCFP (match_operand:DF 0 "s_register_operand" "f") + (float_extend:DF + (match_operand:SF 1 "s_register_operand" "f"))))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "cmf%?\\t%0, %1" + [(set_attr "conds" "set") + (set_attr "type" "f_2_r")] +) + +(define_insn "*cmpsf_trap_fpa" + [(set (reg:CCFPE CC_REGNUM) + (compare:CCFPE (match_operand:SF 0 "s_register_operand" "f,f") + (match_operand:SF 1 "fpa_add_operand" "fG,H")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "@ + cmf%?e\\t%0, %1 + cnf%?e\\t%0, #%N1" + [(set_attr "conds" "set") + (set_attr "type" "f_2_r")] +) + +(define_insn "*cmpdf_trap_fpa" + [(set (reg:CCFPE CC_REGNUM) + (compare:CCFPE (match_operand:DF 0 "s_register_operand" "f,f") + (match_operand:DF 1 "fpa_add_operand" "fG,H")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "@ + cmf%?e\\t%0, %1 + cnf%?e\\t%0, #%N1" + [(set_attr "conds" "set") + (set_attr "type" "f_2_r")] +) + +(define_insn "*cmp_esfdf_df_trap_fpa" + [(set (reg:CCFPE CC_REGNUM) + (compare:CCFPE (float_extend:DF + (match_operand:SF 0 "s_register_operand" "f,f")) + (match_operand:DF 1 "fpa_add_operand" "fG,H")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "@ + cmf%?e\\t%0, %1 + cnf%?e\\t%0, #%N1" + [(set_attr "conds" "set") + (set_attr "type" "f_2_r")] +) + +(define_insn "*cmp_df_esfdf_trap_fpa" + [(set (reg:CCFPE CC_REGNUM) + (compare:CCFPE (match_operand:DF 0 "s_register_operand" "f") + (float_extend:DF + (match_operand:SF 1 "s_register_operand" "f"))))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "cmf%?e\\t%0, %1" + [(set_attr "conds" "set") + (set_attr "type" "f_2_r")] +) + +(define_insn "*movsfcc_fpa" + [(set (match_operand:SF 0 "s_register_operand" "=f,f,f,f,f,f,f,f") + (if_then_else:SF + (match_operator 3 "arm_comparison_operator" + [(match_operand 4 "cc_register" "") (const_int 0)]) + (match_operand:SF 1 "fpa_add_operand" "0,0,fG,H,fG,fG,H,H") + (match_operand:SF 2 "fpa_add_operand" "fG,H,0,0,fG,H,fG,H")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "@ + mvf%D3s\\t%0, %2 + mnf%D3s\\t%0, #%N2 + mvf%d3s\\t%0, %1 + mnf%d3s\\t%0, #%N1 + mvf%d3s\\t%0, %1\;mvf%D3s\\t%0, %2 + mvf%d3s\\t%0, %1\;mnf%D3s\\t%0, #%N2 + mnf%d3s\\t%0, #%N1\;mvf%D3s\\t%0, %2 + mnf%d3s\\t%0, #%N1\;mnf%D3s\\t%0, #%N2" + [(set_attr "length" "4,4,4,4,8,8,8,8") + (set_attr "type" "ffarith") + (set_attr "conds" "use")] +) + +(define_insn "*movdfcc_fpa" + [(set (match_operand:DF 0 "s_register_operand" "=f,f,f,f,f,f,f,f") + (if_then_else:DF + (match_operator 3 "arm_comparison_operator" + [(match_operand 4 "cc_register" "") (const_int 0)]) + (match_operand:DF 1 "fpa_add_operand" "0,0,fG,H,fG,fG,H,H") + (match_operand:DF 2 "fpa_add_operand" "fG,H,0,0,fG,H,fG,H")))] + "TARGET_ARM && TARGET_HARD_FLOAT" + "@ + mvf%D3d\\t%0, %2 + mnf%D3d\\t%0, #%N2 + mvf%d3d\\t%0, %1 + mnf%d3d\\t%0, #%N1 + mvf%d3d\\t%0, %1\;mvf%D3d\\t%0, %2 + mvf%d3d\\t%0, %1\;mnf%D3d\\t%0, #%N2 + mnf%d3d\\t%0, #%N1\;mvf%D3d\\t%0, %2 + mnf%d3d\\t%0, #%N1\;mnf%D3d\\t%0, #%N2" + [(set_attr "length" "4,4,4,4,8,8,8,8") + (set_attr "type" "ffarith") + (set_attr "conds" "use")] +) + diff --git a/contrib/gcc/config/arm/freebsd.h b/contrib/gcc/config/arm/freebsd.h index 0d417a2..cc3f727 100644 --- a/contrib/gcc/config/arm/freebsd.h +++ b/contrib/gcc/config/arm/freebsd.h @@ -1,28 +1,46 @@ /* Definitions for StrongARM running FreeBSD using the ELF format - Copyright (C) 2001 Free Software Foundation, Inc. + Copyright (C) 2001, 2004 Free Software Foundation, Inc. Contributed by David E. O'Brien <obrien@FreeBSD.org> and BSDi. -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ +#undef SUBTARGET_EXTRA_SPECS +#define SUBTARGET_EXTRA_SPECS \ + { "fbsd_dynamic_linker", FBSD_DYNAMIC_LINKER } + #undef SUBTARGET_CPP_SPEC #define SUBTARGET_CPP_SPEC FBSD_CPP_SPEC +#undef LINK_SPEC +#define LINK_SPEC " \ + %{p:%nconsider using `-pg' instead of `-p' with gprof(1) } \ + %{Wl,*:%*} \ + %{v:-V} \ + %{assert*} %{R*} %{rpath*} %{defsym*} \ + %{shared:-Bshareable %{h*} %{soname*}} \ + %{!shared: \ + %{!static: \ + %{rdynamic:-export-dynamic} \ + %{!dynamic-linker:-dynamic-linker %(fbsd_dynamic_linker) }} \ + %{static:-Bstatic}} \ + %{symbolic:-Bsymbolic}" + /************************[ Target stuff ]***********************************/ @@ -47,8 +65,5 @@ Boston, MA 02111-1307, USA. */ #undef SUBTARGET_CPU_DEFAULT #define SUBTARGET_CPU_DEFAULT TARGET_CPU_strongarm -#undef ARM_OS_NAME -#define ARM_OS_NAME "FreeBSD" - #undef TARGET_VERSION #define TARGET_VERSION fprintf (stderr, " (FreeBSD/StrongARM ELF)"); diff --git a/contrib/gcc/config/arm/ieee754-df.S b/contrib/gcc/config/arm/ieee754-df.S new file mode 100644 index 0000000..6a7aab8 --- /dev/null +++ b/contrib/gcc/config/arm/ieee754-df.S @@ -0,0 +1,1224 @@ +/* ieee754-df.S double-precision floating point support for ARM + + Copyright (C) 2003, 2004 Free Software Foundation, Inc. + Contributed by Nicolas Pitre (nico@cam.org) + + This file is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + In addition to the permissions in the GNU General Public License, the + Free Software Foundation gives you unlimited permission to link the + compiled version of this file into combinations with other programs, + and to distribute those combinations without any restriction coming + from the use of this file. (The General Public License restrictions + do apply in other respects; for example, they cover modification of + the file, and distribution when not linked into a combine + executable.) + + This file is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +/* + * Notes: + * + * The goal of this code is to be as fast as possible. This is + * not meant to be easy to understand for the casual reader. + * For slightly simpler code please see the single precision version + * of this file. + * + * Only the default rounding mode is intended for best performances. + * Exceptions aren't supported yet, but that can be added quite easily + * if necessary without impacting performances. + */ + + +@ For FPA, float words are always big-endian. +@ For VFP, floats words follow the memory system mode. +#if defined(__VFP_FP__) && !defined(__ARMEB__) +#define xl r0 +#define xh r1 +#define yl r2 +#define yh r3 +#else +#define xh r0 +#define xl r1 +#define yh r2 +#define yl r3 +#endif + + +#ifdef L_negdf2 + +ARM_FUNC_START negdf2 + @ flip sign bit + eor xh, xh, #0x80000000 + RET + + FUNC_END negdf2 + +#endif + +#ifdef L_addsubdf3 + +ARM_FUNC_START subdf3 + @ flip sign bit of second arg + eor yh, yh, #0x80000000 +#if defined(__thumb__) && !defined(__THUMB_INTERWORK__) + b 1f @ Skip Thumb-code prologue +#endif + +ARM_FUNC_START adddf3 + +1: @ Compare both args, return zero if equal but the sign. + teq xl, yl + eoreq ip, xh, yh + teqeq ip, #0x80000000 + beq LSYM(Lad_z) + + @ If first arg is 0 or -0, return second arg. + @ If second arg is 0 or -0, return first arg. + orrs ip, xl, xh, lsl #1 + moveq xl, yl + moveq xh, yh + orrnes ip, yl, yh, lsl #1 + RETc(eq) + + stmfd sp!, {r4, r5, lr} + + @ Mask out exponents. + mov ip, #0x7f000000 + orr ip, ip, #0x00f00000 + and r4, xh, ip + and r5, yh, ip + + @ If either of them is 0x7ff, result will be INF or NAN + teq r4, ip + teqne r5, ip + beq LSYM(Lad_i) + + @ Compute exponent difference. Make largest exponent in r4, + @ corresponding arg in xh-xl, and positive exponent difference in r5. + subs r5, r5, r4 + rsblt r5, r5, #0 + ble 1f + add r4, r4, r5 + eor yl, xl, yl + eor yh, xh, yh + eor xl, yl, xl + eor xh, yh, xh + eor yl, xl, yl + eor yh, xh, yh +1: + + @ If exponent difference is too large, return largest argument + @ already in xh-xl. We need up to 54 bit to handle proper rounding + @ of 0x1p54 - 1.1. + cmp r5, #(54 << 20) + RETLDM "r4, r5" hi + + @ Convert mantissa to signed integer. + tst xh, #0x80000000 + bic xh, xh, ip, lsl #1 + orr xh, xh, #0x00100000 + beq 1f + rsbs xl, xl, #0 + rsc xh, xh, #0 +1: + tst yh, #0x80000000 + bic yh, yh, ip, lsl #1 + orr yh, yh, #0x00100000 + beq 1f + rsbs yl, yl, #0 + rsc yh, yh, #0 +1: + @ If exponent == difference, one or both args were denormalized. + @ Since this is not common case, rescale them off line. + teq r4, r5 + beq LSYM(Lad_d) +LSYM(Lad_x): + @ Scale down second arg with exponent difference. + @ Apply shift one bit left to first arg and the rest to second arg + @ to simplify things later, but only if exponent does not become 0. + mov ip, #0 + movs r5, r5, lsr #20 + beq 3f + teq r4, #(1 << 20) + beq 1f + movs xl, xl, lsl #1 + adc xh, ip, xh, lsl #1 + sub r4, r4, #(1 << 20) + subs r5, r5, #1 + beq 3f + + @ Shift yh-yl right per r5, keep leftover bits into ip. +1: rsbs lr, r5, #32 + blt 2f + mov ip, yl, lsl lr + mov yl, yl, lsr r5 + orr yl, yl, yh, lsl lr + mov yh, yh, asr r5 + b 3f +2: sub r5, r5, #32 + add lr, lr, #32 + cmp yl, #1 + adc ip, ip, yh, lsl lr + mov yl, yh, asr r5 + mov yh, yh, asr #32 +3: + @ the actual addition + adds xl, xl, yl + adc xh, xh, yh + + @ We now have a result in xh-xl-ip. + @ Keep absolute value in xh-xl-ip, sign in r5. + ands r5, xh, #0x80000000 + bpl LSYM(Lad_p) + rsbs ip, ip, #0 + rscs xl, xl, #0 + rsc xh, xh, #0 + + @ Determine how to normalize the result. +LSYM(Lad_p): + cmp xh, #0x00100000 + bcc LSYM(Lad_l) + cmp xh, #0x00200000 + bcc LSYM(Lad_r0) + cmp xh, #0x00400000 + bcc LSYM(Lad_r1) + + @ Result needs to be shifted right. + movs xh, xh, lsr #1 + movs xl, xl, rrx + movs ip, ip, rrx + orrcs ip, ip, #1 + add r4, r4, #(1 << 20) +LSYM(Lad_r1): + movs xh, xh, lsr #1 + movs xl, xl, rrx + movs ip, ip, rrx + orrcs ip, ip, #1 + add r4, r4, #(1 << 20) + + @ Our result is now properly aligned into xh-xl, remaining bits in ip. + @ Round with MSB of ip. If halfway between two numbers, round towards + @ LSB of xl = 0. +LSYM(Lad_r0): + adds xl, xl, ip, lsr #31 + adc xh, xh, #0 + teq ip, #0x80000000 + biceq xl, xl, #1 + + @ One extreme rounding case may add a new MSB. Adjust exponent. + @ That MSB will be cleared when exponent is merged below. + tst xh, #0x00200000 + addne r4, r4, #(1 << 20) + + @ Make sure we did not bust our exponent. + adds ip, r4, #(1 << 20) + bmi LSYM(Lad_o) + + @ Pack final result together. +LSYM(Lad_e): + bic xh, xh, #0x00300000 + orr xh, xh, r4 + orr xh, xh, r5 + RETLDM "r4, r5" + +LSYM(Lad_l): + @ Result must be shifted left and exponent adjusted. + @ No rounding necessary since ip will always be 0. +#if __ARM_ARCH__ < 5 + + teq xh, #0 + movne r3, #-11 + moveq r3, #21 + moveq xh, xl + moveq xl, #0 + mov r2, xh + movs ip, xh, lsr #16 + moveq r2, r2, lsl #16 + addeq r3, r3, #16 + tst r2, #0xff000000 + moveq r2, r2, lsl #8 + addeq r3, r3, #8 + tst r2, #0xf0000000 + moveq r2, r2, lsl #4 + addeq r3, r3, #4 + tst r2, #0xc0000000 + moveq r2, r2, lsl #2 + addeq r3, r3, #2 + tst r2, #0x80000000 + addeq r3, r3, #1 + +#else + + teq xh, #0 + moveq xh, xl + moveq xl, #0 + clz r3, xh + addeq r3, r3, #32 + sub r3, r3, #11 + +#endif + + @ determine how to shift the value. + subs r2, r3, #32 + bge 2f + adds r2, r2, #12 + ble 1f + + @ shift value left 21 to 31 bits, or actually right 11 to 1 bits + @ since a register switch happened above. + add ip, r2, #20 + rsb r2, r2, #12 + mov xl, xh, lsl ip + mov xh, xh, lsr r2 + b 3f + + @ actually shift value left 1 to 20 bits, which might also represent + @ 32 to 52 bits if counting the register switch that happened earlier. +1: add r2, r2, #20 +2: rsble ip, r2, #32 + mov xh, xh, lsl r2 + orrle xh, xh, xl, lsr ip + movle xl, xl, lsl r2 + + @ adjust exponent accordingly. +3: subs r4, r4, r3, lsl #20 + bgt LSYM(Lad_e) + + @ Exponent too small, denormalize result. + @ Find out proper shift value. + mvn r4, r4, asr #20 + subs r4, r4, #30 + bge 2f + adds r4, r4, #12 + bgt 1f + + @ shift result right of 1 to 20 bits, sign is in r5. + add r4, r4, #20 + rsb r2, r4, #32 + mov xl, xl, lsr r4 + orr xl, xl, xh, lsl r2 + orr xh, r5, xh, lsr r4 + RETLDM "r4, r5" + + @ shift result right of 21 to 31 bits, or left 11 to 1 bits after + @ a register switch from xh to xl. +1: rsb r4, r4, #12 + rsb r2, r4, #32 + mov xl, xl, lsr r2 + orr xl, xl, xh, lsl r4 + mov xh, r5 + RETLDM "r4, r5" + + @ Shift value right of 32 to 64 bits, or 0 to 32 bits after a switch + @ from xh to xl. +2: mov xl, xh, lsr r4 + mov xh, r5 + RETLDM "r4, r5" + + @ Adjust exponents for denormalized arguments. +LSYM(Lad_d): + teq r4, #0 + eoreq xh, xh, #0x00100000 + addeq r4, r4, #(1 << 20) + eor yh, yh, #0x00100000 + subne r5, r5, #(1 << 20) + b LSYM(Lad_x) + + @ Result is x - x = 0, unless x = INF or NAN. +LSYM(Lad_z): + sub ip, ip, #0x00100000 @ ip becomes 0x7ff00000 + and r2, xh, ip + teq r2, ip + orreq xh, ip, #0x00080000 + movne xh, #0 + mov xl, #0 + RET + + @ Overflow: return INF. +LSYM(Lad_o): + orr xh, r5, #0x7f000000 + orr xh, xh, #0x00f00000 + mov xl, #0 + RETLDM "r4, r5" + + @ At least one of x or y is INF/NAN. + @ if xh-xl != INF/NAN: return yh-yl (which is INF/NAN) + @ if yh-yl != INF/NAN: return xh-xl (which is INF/NAN) + @ if either is NAN: return NAN + @ if opposite sign: return NAN + @ return xh-xl (which is INF or -INF) +LSYM(Lad_i): + teq r4, ip + movne xh, yh + movne xl, yl + teqeq r5, ip + RETLDM "r4, r5" ne + + orrs r4, xl, xh, lsl #12 + orreqs r4, yl, yh, lsl #12 + teqeq xh, yh + orrne xh, r5, #0x00080000 + movne xl, #0 + RETLDM "r4, r5" + + FUNC_END subdf3 + FUNC_END adddf3 + +ARM_FUNC_START floatunsidf + teq r0, #0 + moveq r1, #0 + RETc(eq) + stmfd sp!, {r4, r5, lr} + mov r4, #(0x400 << 20) @ initial exponent + add r4, r4, #((52-1) << 20) + mov r5, #0 @ sign bit is 0 + mov xl, r0 + mov xh, #0 + b LSYM(Lad_l) + + FUNC_END floatunsidf + +ARM_FUNC_START floatsidf + teq r0, #0 + moveq r1, #0 + RETc(eq) + stmfd sp!, {r4, r5, lr} + mov r4, #(0x400 << 20) @ initial exponent + add r4, r4, #((52-1) << 20) + ands r5, r0, #0x80000000 @ sign bit in r5 + rsbmi r0, r0, #0 @ absolute value + mov xl, r0 + mov xh, #0 + b LSYM(Lad_l) + + FUNC_END floatsidf + +ARM_FUNC_START extendsfdf2 + movs r2, r0, lsl #1 + beq 1f @ value is 0.0 or -0.0 + mov xh, r2, asr #3 @ stretch exponent + mov xh, xh, rrx @ retrieve sign bit + mov xl, r2, lsl #28 @ retrieve remaining bits + ands r2, r2, #0xff000000 @ isolate exponent + beq 2f @ exponent was 0 but not mantissa + teq r2, #0xff000000 @ check if INF or NAN + eorne xh, xh, #0x38000000 @ fixup exponent otherwise. + RET + +1: mov xh, r0 + mov xl, #0 + RET + +2: @ value was denormalized. We can normalize it now. + stmfd sp!, {r4, r5, lr} + mov r4, #(0x380 << 20) @ setup corresponding exponent + add r4, r4, #(1 << 20) + and r5, xh, #0x80000000 @ move sign bit in r5 + bic xh, xh, #0x80000000 + b LSYM(Lad_l) + + FUNC_END extendsfdf2 + +#endif /* L_addsubdf3 */ + +#ifdef L_muldivdf3 + +ARM_FUNC_START muldf3 + + stmfd sp!, {r4, r5, r6, lr} + + @ Mask out exponents. + mov ip, #0x7f000000 + orr ip, ip, #0x00f00000 + and r4, xh, ip + and r5, yh, ip + + @ Trap any INF/NAN. + teq r4, ip + teqne r5, ip + beq LSYM(Lml_s) + + @ Trap any multiplication by 0. + orrs r6, xl, xh, lsl #1 + orrnes r6, yl, yh, lsl #1 + beq LSYM(Lml_z) + + @ Shift exponents right one bit to make room for overflow bit. + @ If either of them is 0, scale denormalized arguments off line. + @ Then add both exponents together. + movs r4, r4, lsr #1 + teqne r5, #0 + beq LSYM(Lml_d) +LSYM(Lml_x): + add r4, r4, r5, asr #1 + + @ Preserve final sign in r4 along with exponent for now. + teq xh, yh + orrmi r4, r4, #0x8000 + + @ Convert mantissa to unsigned integer. + bic xh, xh, ip, lsl #1 + bic yh, yh, ip, lsl #1 + orr xh, xh, #0x00100000 + orr yh, yh, #0x00100000 + +#if __ARM_ARCH__ < 4 + + @ Well, no way to make it shorter without the umull instruction. + @ We must perform that 53 x 53 bit multiplication by hand. + stmfd sp!, {r7, r8, r9, sl, fp} + mov r7, xl, lsr #16 + mov r8, yl, lsr #16 + mov r9, xh, lsr #16 + mov sl, yh, lsr #16 + bic xl, xl, r7, lsl #16 + bic yl, yl, r8, lsl #16 + bic xh, xh, r9, lsl #16 + bic yh, yh, sl, lsl #16 + mul ip, xl, yl + mul fp, xl, r8 + mov lr, #0 + adds ip, ip, fp, lsl #16 + adc lr, lr, fp, lsr #16 + mul fp, r7, yl + adds ip, ip, fp, lsl #16 + adc lr, lr, fp, lsr #16 + mul fp, xl, sl + mov r5, #0 + adds lr, lr, fp, lsl #16 + adc r5, r5, fp, lsr #16 + mul fp, r7, yh + adds lr, lr, fp, lsl #16 + adc r5, r5, fp, lsr #16 + mul fp, xh, r8 + adds lr, lr, fp, lsl #16 + adc r5, r5, fp, lsr #16 + mul fp, r9, yl + adds lr, lr, fp, lsl #16 + adc r5, r5, fp, lsr #16 + mul fp, xh, sl + mul r6, r9, sl + adds r5, r5, fp, lsl #16 + adc r6, r6, fp, lsr #16 + mul fp, r9, yh + adds r5, r5, fp, lsl #16 + adc r6, r6, fp, lsr #16 + mul fp, xl, yh + adds lr, lr, fp + mul fp, r7, sl + adcs r5, r5, fp + mul fp, xh, yl + adc r6, r6, #0 + adds lr, lr, fp + mul fp, r9, r8 + adcs r5, r5, fp + mul fp, r7, r8 + adc r6, r6, #0 + adds lr, lr, fp + mul fp, xh, yh + adcs r5, r5, fp + adc r6, r6, #0 + ldmfd sp!, {r7, r8, r9, sl, fp} + +#else + + @ Here is the actual multiplication: 53 bits * 53 bits -> 106 bits. + umull ip, lr, xl, yl + mov r5, #0 + umlal lr, r5, xl, yh + umlal lr, r5, xh, yl + mov r6, #0 + umlal r5, r6, xh, yh + +#endif + + @ The LSBs in ip are only significant for the final rounding. + @ Fold them into one bit of lr. + teq ip, #0 + orrne lr, lr, #1 + + @ Put final sign in xh. + mov xh, r4, lsl #16 + bic r4, r4, #0x8000 + + @ Adjust result if one extra MSB appeared (one of four times). + tst r6, #(1 << 9) + beq 1f + add r4, r4, #(1 << 19) + movs r6, r6, lsr #1 + movs r5, r5, rrx + movs lr, lr, rrx + orrcs lr, lr, #1 +1: + @ Scale back to 53 bits. + @ xh contains sign bit already. + orr xh, xh, r6, lsl #12 + orr xh, xh, r5, lsr #20 + mov xl, r5, lsl #12 + orr xl, xl, lr, lsr #20 + + @ Apply exponent bias, check range for underflow. + sub r4, r4, #0x00f80000 + subs r4, r4, #0x1f000000 + ble LSYM(Lml_u) + + @ Round the result. + movs lr, lr, lsl #12 + bpl 1f + adds xl, xl, #1 + adc xh, xh, #0 + teq lr, #0x80000000 + biceq xl, xl, #1 + + @ Rounding may have produced an extra MSB here. + @ The extra bit is cleared before merging the exponent below. + tst xh, #0x00200000 + addne r4, r4, #(1 << 19) +1: + @ Check exponent for overflow. + adds ip, r4, #(1 << 19) + tst ip, #(1 << 30) + bne LSYM(Lml_o) + + @ Add final exponent. + bic xh, xh, #0x00300000 + orr xh, xh, r4, lsl #1 + RETLDM "r4, r5, r6" + + @ Result is 0, but determine sign anyway. +LSYM(Lml_z): + eor xh, xh, yh +LSYM(Ldv_z): + bic xh, xh, #0x7fffffff + mov xl, #0 + RETLDM "r4, r5, r6" + + @ Check if denormalized result is possible, otherwise return signed 0. +LSYM(Lml_u): + cmn r4, #(53 << 19) + movle xl, #0 + bicle xh, xh, #0x7fffffff + RETLDM "r4, r5, r6" le + + @ Find out proper shift value. +LSYM(Lml_r): + mvn r4, r4, asr #19 + subs r4, r4, #30 + bge 2f + adds r4, r4, #12 + bgt 1f + + @ shift result right of 1 to 20 bits, preserve sign bit, round, etc. + add r4, r4, #20 + rsb r5, r4, #32 + mov r3, xl, lsl r5 + mov xl, xl, lsr r4 + orr xl, xl, xh, lsl r5 + movs xh, xh, lsl #1 + mov xh, xh, lsr r4 + mov xh, xh, rrx + adds xl, xl, r3, lsr #31 + adc xh, xh, #0 + teq lr, #0 + teqeq r3, #0x80000000 + biceq xl, xl, #1 + RETLDM "r4, r5, r6" + + @ shift result right of 21 to 31 bits, or left 11 to 1 bits after + @ a register switch from xh to xl. Then round. +1: rsb r4, r4, #12 + rsb r5, r4, #32 + mov r3, xl, lsl r4 + mov xl, xl, lsr r5 + orr xl, xl, xh, lsl r4 + bic xh, xh, #0x7fffffff + adds xl, xl, r3, lsr #31 + adc xh, xh, #0 + teq lr, #0 + teqeq r3, #0x80000000 + biceq xl, xl, #1 + RETLDM "r4, r5, r6" + + @ Shift value right of 32 to 64 bits, or 0 to 32 bits after a switch + @ from xh to xl. Leftover bits are in r3-r6-lr for rounding. +2: rsb r5, r4, #32 + mov r6, xl, lsl r5 + mov r3, xl, lsr r4 + orr r3, r3, xh, lsl r5 + mov xl, xh, lsr r4 + bic xh, xh, #0x7fffffff + bic xl, xl, xh, lsr r4 + add xl, xl, r3, lsr #31 + orrs r6, r6, lr + teqeq r3, #0x80000000 + biceq xl, xl, #1 + RETLDM "r4, r5, r6" + + @ One or both arguments are denormalized. + @ Scale them leftwards and preserve sign bit. +LSYM(Lml_d): + mov lr, #0 + teq r4, #0 + bne 2f + and r6, xh, #0x80000000 +1: movs xl, xl, lsl #1 + adc xh, lr, xh, lsl #1 + tst xh, #0x00100000 + subeq r4, r4, #(1 << 19) + beq 1b + orr xh, xh, r6 + teq r5, #0 + bne LSYM(Lml_x) +2: and r6, yh, #0x80000000 +3: movs yl, yl, lsl #1 + adc yh, lr, yh, lsl #1 + tst yh, #0x00100000 + subeq r5, r5, #(1 << 20) + beq 3b + orr yh, yh, r6 + b LSYM(Lml_x) + + @ One or both args are INF or NAN. +LSYM(Lml_s): + orrs r6, xl, xh, lsl #1 + orrnes r6, yl, yh, lsl #1 + beq LSYM(Lml_n) @ 0 * INF or INF * 0 -> NAN + teq r4, ip + bne 1f + orrs r6, xl, xh, lsl #12 + bne LSYM(Lml_n) @ NAN * <anything> -> NAN +1: teq r5, ip + bne LSYM(Lml_i) + orrs r6, yl, yh, lsl #12 + bne LSYM(Lml_n) @ <anything> * NAN -> NAN + + @ Result is INF, but we need to determine its sign. +LSYM(Lml_i): + eor xh, xh, yh + + @ Overflow: return INF (sign already in xh). +LSYM(Lml_o): + and xh, xh, #0x80000000 + orr xh, xh, #0x7f000000 + orr xh, xh, #0x00f00000 + mov xl, #0 + RETLDM "r4, r5, r6" + + @ Return NAN. +LSYM(Lml_n): + mov xh, #0x7f000000 + orr xh, xh, #0x00f80000 + RETLDM "r4, r5, r6" + + FUNC_END muldf3 + +ARM_FUNC_START divdf3 + + stmfd sp!, {r4, r5, r6, lr} + + @ Mask out exponents. + mov ip, #0x7f000000 + orr ip, ip, #0x00f00000 + and r4, xh, ip + and r5, yh, ip + + @ Trap any INF/NAN or zeroes. + teq r4, ip + teqne r5, ip + orrnes r6, xl, xh, lsl #1 + orrnes r6, yl, yh, lsl #1 + beq LSYM(Ldv_s) + + @ Shift exponents right one bit to make room for overflow bit. + @ If either of them is 0, scale denormalized arguments off line. + @ Then substract divisor exponent from dividend''s. + movs r4, r4, lsr #1 + teqne r5, #0 + beq LSYM(Ldv_d) +LSYM(Ldv_x): + sub r4, r4, r5, asr #1 + + @ Preserve final sign into lr. + eor lr, xh, yh + + @ Convert mantissa to unsigned integer. + @ Dividend -> r5-r6, divisor -> yh-yl. + mov r5, #0x10000000 + mov yh, yh, lsl #12 + orr yh, r5, yh, lsr #4 + orr yh, yh, yl, lsr #24 + movs yl, yl, lsl #8 + mov xh, xh, lsl #12 + teqeq yh, r5 + beq LSYM(Ldv_1) + orr r5, r5, xh, lsr #4 + orr r5, r5, xl, lsr #24 + mov r6, xl, lsl #8 + + @ Initialize xh with final sign bit. + and xh, lr, #0x80000000 + + @ Ensure result will land to known bit position. + cmp r5, yh + cmpeq r6, yl + bcs 1f + sub r4, r4, #(1 << 19) + movs yh, yh, lsr #1 + mov yl, yl, rrx +1: + @ Apply exponent bias, check range for over/underflow. + add r4, r4, #0x1f000000 + add r4, r4, #0x00f80000 + cmn r4, #(53 << 19) + ble LSYM(Ldv_z) + cmp r4, ip, lsr #1 + bge LSYM(Lml_o) + + @ Perform first substraction to align result to a nibble. + subs r6, r6, yl + sbc r5, r5, yh + movs yh, yh, lsr #1 + mov yl, yl, rrx + mov xl, #0x00100000 + mov ip, #0x00080000 + + @ The actual division loop. +1: subs lr, r6, yl + sbcs lr, r5, yh + subcs r6, r6, yl + movcs r5, lr + orrcs xl, xl, ip + movs yh, yh, lsr #1 + mov yl, yl, rrx + subs lr, r6, yl + sbcs lr, r5, yh + subcs r6, r6, yl + movcs r5, lr + orrcs xl, xl, ip, lsr #1 + movs yh, yh, lsr #1 + mov yl, yl, rrx + subs lr, r6, yl + sbcs lr, r5, yh + subcs r6, r6, yl + movcs r5, lr + orrcs xl, xl, ip, lsr #2 + movs yh, yh, lsr #1 + mov yl, yl, rrx + subs lr, r6, yl + sbcs lr, r5, yh + subcs r6, r6, yl + movcs r5, lr + orrcs xl, xl, ip, lsr #3 + + orrs lr, r5, r6 + beq 2f + mov r5, r5, lsl #4 + orr r5, r5, r6, lsr #28 + mov r6, r6, lsl #4 + mov yh, yh, lsl #3 + orr yh, yh, yl, lsr #29 + mov yl, yl, lsl #3 + movs ip, ip, lsr #4 + bne 1b + + @ We are done with a word of the result. + @ Loop again for the low word if this pass was for the high word. + tst xh, #0x00100000 + bne 3f + orr xh, xh, xl + mov xl, #0 + mov ip, #0x80000000 + b 1b +2: + @ Be sure result starts in the high word. + tst xh, #0x00100000 + orreq xh, xh, xl + moveq xl, #0 +3: + @ Check if denormalized result is needed. + cmp r4, #0 + ble LSYM(Ldv_u) + + @ Apply proper rounding. + subs ip, r5, yh + subeqs ip, r6, yl + adcs xl, xl, #0 + adc xh, xh, #0 + teq ip, #0 + biceq xl, xl, #1 + + @ Add exponent to result. + bic xh, xh, #0x00100000 + orr xh, xh, r4, lsl #1 + RETLDM "r4, r5, r6" + + @ Division by 0x1p*: shortcut a lot of code. +LSYM(Ldv_1): + and lr, lr, #0x80000000 + orr xh, lr, xh, lsr #12 + add r4, r4, #0x1f000000 + add r4, r4, #0x00f80000 + cmp r4, ip, lsr #1 + bge LSYM(Lml_o) + cmp r4, #0 + orrgt xh, xh, r4, lsl #1 + RETLDM "r4, r5, r6" gt + + cmn r4, #(53 << 19) + ble LSYM(Ldv_z) + orr xh, xh, #0x00100000 + mov lr, #0 + b LSYM(Lml_r) + + @ Result must be denormalized: put remainder in lr for + @ rounding considerations. +LSYM(Ldv_u): + orr lr, r5, r6 + b LSYM(Lml_r) + + @ One or both arguments are denormalized. + @ Scale them leftwards and preserve sign bit. +LSYM(Ldv_d): + mov lr, #0 + teq r4, #0 + bne 2f + and r6, xh, #0x80000000 +1: movs xl, xl, lsl #1 + adc xh, lr, xh, lsl #1 + tst xh, #0x00100000 + subeq r4, r4, #(1 << 19) + beq 1b + orr xh, xh, r6 + teq r5, #0 + bne LSYM(Ldv_x) +2: and r6, yh, #0x80000000 +3: movs yl, yl, lsl #1 + adc yh, lr, yh, lsl #1 + tst yh, #0x00100000 + subeq r5, r5, #(1 << 20) + beq 3b + orr yh, yh, r6 + b LSYM(Ldv_x) + + @ One or both arguments is either INF, NAN or zero. +LSYM(Ldv_s): + teq r4, ip + teqeq r5, ip + beq LSYM(Lml_n) @ INF/NAN / INF/NAN -> NAN + teq r4, ip + bne 1f + orrs r4, xl, xh, lsl #12 + bne LSYM(Lml_n) @ NAN / <anything> -> NAN + b LSYM(Lml_i) @ INF / <anything> -> INF +1: teq r5, ip + bne 2f + orrs r5, yl, yh, lsl #12 + bne LSYM(Lml_n) @ <anything> / NAN -> NAN + b LSYM(Lml_z) @ <anything> / INF -> 0 +2: @ One or both arguments are 0. + orrs r4, xl, xh, lsl #1 + bne LSYM(Lml_i) @ <non_zero> / 0 -> INF + orrs r5, yl, yh, lsl #1 + bne LSYM(Lml_z) @ 0 / <non_zero> -> 0 + b LSYM(Lml_n) @ 0 / 0 -> NAN + + FUNC_END divdf3 + +#endif /* L_muldivdf3 */ + +#ifdef L_cmpdf2 + +ARM_FUNC_START gtdf2 +ARM_FUNC_ALIAS gedf2 gtdf2 + mov ip, #-1 + b 1f + +ARM_FUNC_START ltdf2 +ARM_FUNC_ALIAS ledf2 ltdf2 + mov ip, #1 + b 1f + +ARM_FUNC_START cmpdf2 +ARM_FUNC_ALIAS nedf2 cmpdf2 +ARM_FUNC_ALIAS eqdf2 cmpdf2 + mov ip, #1 @ how should we specify unordered here? + +1: stmfd sp!, {r4, r5, lr} + + @ Trap any INF/NAN first. + mov lr, #0x7f000000 + orr lr, lr, #0x00f00000 + and r4, xh, lr + and r5, yh, lr + teq r4, lr + teqne r5, lr + beq 3f + + @ Test for equality. + @ Note that 0.0 is equal to -0.0. +2: orrs ip, xl, xh, lsl #1 @ if x == 0.0 or -0.0 + orreqs ip, yl, yh, lsl #1 @ and y == 0.0 or -0.0 + teqne xh, yh @ or xh == yh + teqeq xl, yl @ and xl == yl + moveq r0, #0 @ then equal. + RETLDM "r4, r5" eq + + @ Check for sign difference. + teq xh, yh + movmi r0, xh, asr #31 + orrmi r0, r0, #1 + RETLDM "r4, r5" mi + + @ Compare exponents. + cmp r4, r5 + + @ Compare mantissa if exponents are equal. + moveq xh, xh, lsl #12 + cmpeq xh, yh, lsl #12 + cmpeq xl, yl + movcs r0, yh, asr #31 + mvncc r0, yh, asr #31 + orr r0, r0, #1 + RETLDM "r4, r5" + + @ Look for a NAN. +3: teq r4, lr + bne 4f + orrs xl, xl, xh, lsl #12 + bne 5f @ x is NAN +4: teq r5, lr + bne 2b + orrs yl, yl, yh, lsl #12 + beq 2b @ y is not NAN +5: mov r0, ip @ return unordered code from ip + RETLDM "r4, r5" + + FUNC_END gedf2 + FUNC_END gtdf2 + FUNC_END ledf2 + FUNC_END ltdf2 + FUNC_END nedf2 + FUNC_END eqdf2 + FUNC_END cmpdf2 + +#endif /* L_cmpdf2 */ + +#ifdef L_unorddf2 + +ARM_FUNC_START unorddf2 + str lr, [sp, #-4]! + mov ip, #0x7f000000 + orr ip, ip, #0x00f00000 + and lr, xh, ip + teq lr, ip + bne 1f + orrs xl, xl, xh, lsl #12 + bne 3f @ x is NAN +1: and lr, yh, ip + teq lr, ip + bne 2f + orrs yl, yl, yh, lsl #12 + bne 3f @ y is NAN +2: mov r0, #0 @ arguments are ordered. + RETLDM + +3: mov r0, #1 @ arguments are unordered. + RETLDM + + FUNC_END unorddf2 + +#endif /* L_unorddf2 */ + +#ifdef L_fixdfsi + +ARM_FUNC_START fixdfsi + orrs ip, xl, xh, lsl #1 + beq 1f @ value is 0. + + mov r3, r3, rrx @ preserve C flag (the actual sign) + + @ check exponent range. + mov ip, #0x7f000000 + orr ip, ip, #0x00f00000 + and r2, xh, ip + teq r2, ip + beq 2f @ value is INF or NAN + bic ip, ip, #0x40000000 + cmp r2, ip + bcc 1f @ value is too small + add ip, ip, #(31 << 20) + cmp r2, ip + bcs 3f @ value is too large + + rsb r2, r2, ip + mov ip, xh, lsl #11 + orr ip, ip, #0x80000000 + orr ip, ip, xl, lsr #21 + mov r2, r2, lsr #20 + tst r3, #0x80000000 @ the sign bit + mov r0, ip, lsr r2 + rsbne r0, r0, #0 + RET + +1: mov r0, #0 + RET + +2: orrs xl, xl, xh, lsl #12 + bne 4f @ r0 is NAN. +3: ands r0, r3, #0x80000000 @ the sign bit + moveq r0, #0x7fffffff @ maximum signed positive si + RET + +4: mov r0, #0 @ How should we convert NAN? + RET + + FUNC_END fixdfsi + +#endif /* L_fixdfsi */ + +#ifdef L_fixunsdfsi + +ARM_FUNC_START fixunsdfsi + orrs ip, xl, xh, lsl #1 + movcss r0, #0 @ value is negative + RETc(eq) @ or 0 (xl, xh overlap r0) + + @ check exponent range. + mov ip, #0x7f000000 + orr ip, ip, #0x00f00000 + and r2, xh, ip + teq r2, ip + beq 2f @ value is INF or NAN + bic ip, ip, #0x40000000 + cmp r2, ip + bcc 1f @ value is too small + add ip, ip, #(31 << 20) + cmp r2, ip + bhi 3f @ value is too large + + rsb r2, r2, ip + mov ip, xh, lsl #11 + orr ip, ip, #0x80000000 + orr ip, ip, xl, lsr #21 + mov r2, r2, lsr #20 + mov r0, ip, lsr r2 + RET + +1: mov r0, #0 + RET + +2: orrs xl, xl, xh, lsl #12 + bne 4f @ value is NAN. +3: mov r0, #0xffffffff @ maximum unsigned si + RET + +4: mov r0, #0 @ How should we convert NAN? + RET + + FUNC_END fixunsdfsi + +#endif /* L_fixunsdfsi */ + +#ifdef L_truncdfsf2 + +ARM_FUNC_START truncdfsf2 + orrs r2, xl, xh, lsl #1 + moveq r0, r2, rrx + RETc(eq) @ value is 0.0 or -0.0 + + @ check exponent range. + mov ip, #0x7f000000 + orr ip, ip, #0x00f00000 + and r2, ip, xh + teq r2, ip + beq 2f @ value is INF or NAN + bic xh, xh, ip + cmp r2, #(0x380 << 20) + bls 4f @ value is too small + + @ shift and round mantissa +1: movs r3, xl, lsr #29 + adc r3, r3, xh, lsl #3 + + @ if halfway between two numbers, round towards LSB = 0. + mov xl, xl, lsl #3 + teq xl, #0x80000000 + biceq r3, r3, #1 + + @ rounding might have created an extra MSB. If so adjust exponent. + tst r3, #0x00800000 + addne r2, r2, #(1 << 20) + bicne r3, r3, #0x00800000 + + @ check exponent for overflow + mov ip, #(0x400 << 20) + orr ip, ip, #(0x07f << 20) + cmp r2, ip + bcs 3f @ overflow + + @ adjust exponent, merge with sign bit and mantissa. + movs xh, xh, lsl #1 + mov r2, r2, lsl #4 + orr r0, r3, r2, rrx + eor r0, r0, #0x40000000 + RET + +2: @ chech for NAN + orrs xl, xl, xh, lsl #12 + movne r0, #0x7f000000 + orrne r0, r0, #0x00c00000 + RETc(ne) @ return NAN + +3: @ return INF with sign + and r0, xh, #0x80000000 + orr r0, r0, #0x7f000000 + orr r0, r0, #0x00800000 + RET + +4: @ check if denormalized value is possible + subs r2, r2, #((0x380 - 24) << 20) + andle r0, xh, #0x80000000 @ too small, return signed 0. + RETc(le) + + @ denormalize value so we can resume with the code above afterwards. + orr xh, xh, #0x00100000 + mov r2, r2, lsr #20 + rsb r2, r2, #25 + cmp r2, #20 + bgt 6f + + rsb ip, r2, #32 + mov r3, xl, lsl ip + mov xl, xl, lsr r2 + orr xl, xl, xh, lsl ip + movs xh, xh, lsl #1 + mov xh, xh, lsr r2 + mov xh, xh, rrx +5: teq r3, #0 @ fold r3 bits into the LSB + orrne xl, xl, #1 @ for rounding considerations. + mov r2, #(0x380 << 20) @ equivalent to the 0 float exponent + b 1b + +6: rsb r2, r2, #(12 + 20) + rsb ip, r2, #32 + mov r3, xl, lsl r2 + mov xl, xl, lsr ip + orr xl, xl, xh, lsl r2 + and xh, xh, #0x80000000 + b 5b + + FUNC_END truncdfsf2 + +#endif /* L_truncdfsf2 */ diff --git a/contrib/gcc/config/arm/ieee754-sf.S b/contrib/gcc/config/arm/ieee754-sf.S new file mode 100644 index 0000000..5c97245 --- /dev/null +++ b/contrib/gcc/config/arm/ieee754-sf.S @@ -0,0 +1,816 @@ +/* ieee754-sf.S single-precision floating point support for ARM + + Copyright (C) 2003, 2004 Free Software Foundation, Inc. + Contributed by Nicolas Pitre (nico@cam.org) + + This file is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + In addition to the permissions in the GNU General Public License, the + Free Software Foundation gives you unlimited permission to link the + compiled version of this file into combinations with other programs, + and to distribute those combinations without any restriction coming + from the use of this file. (The General Public License restrictions + do apply in other respects; for example, they cover modification of + the file, and distribution when not linked into a combine + executable.) + + This file is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +/* + * Notes: + * + * The goal of this code is to be as fast as possible. This is + * not meant to be easy to understand for the casual reader. + * + * Only the default rounding mode is intended for best performances. + * Exceptions aren't supported yet, but that can be added quite easily + * if necessary without impacting performances. + */ + +#ifdef L_negsf2 + +ARM_FUNC_START negsf2 + eor r0, r0, #0x80000000 @ flip sign bit + RET + + FUNC_END negsf2 + +#endif + +#ifdef L_addsubsf3 + +ARM_FUNC_START subsf3 + eor r1, r1, #0x80000000 @ flip sign bit of second arg +#if defined(__thumb__) && !defined(__THUMB_INTERWORK__) + b 1f @ Skip Thumb-code prologue +#endif + +ARM_FUNC_START addsf3 + +1: @ Compare both args, return zero if equal but the sign. + eor r2, r0, r1 + teq r2, #0x80000000 + beq LSYM(Lad_z) + + @ If first arg is 0 or -0, return second arg. + @ If second arg is 0 or -0, return first arg. + bics r2, r0, #0x80000000 + moveq r0, r1 + bicnes r2, r1, #0x80000000 + RETc(eq) + + @ Mask out exponents. + mov ip, #0xff000000 + and r2, r0, ip, lsr #1 + and r3, r1, ip, lsr #1 + + @ If either of them is 255, result will be INF or NAN + teq r2, ip, lsr #1 + teqne r3, ip, lsr #1 + beq LSYM(Lad_i) + + @ Compute exponent difference. Make largest exponent in r2, + @ corresponding arg in r0, and positive exponent difference in r3. + subs r3, r3, r2 + addgt r2, r2, r3 + eorgt r1, r0, r1 + eorgt r0, r1, r0 + eorgt r1, r0, r1 + rsblt r3, r3, #0 + + @ If exponent difference is too large, return largest argument + @ already in r0. We need up to 25 bit to handle proper rounding + @ of 0x1p25 - 1.1. + cmp r3, #(25 << 23) + RETc(hi) + + @ Convert mantissa to signed integer. + tst r0, #0x80000000 + orr r0, r0, #0x00800000 + bic r0, r0, #0xff000000 + rsbne r0, r0, #0 + tst r1, #0x80000000 + orr r1, r1, #0x00800000 + bic r1, r1, #0xff000000 + rsbne r1, r1, #0 + + @ If exponent == difference, one or both args were denormalized. + @ Since this is not common case, rescale them off line. + teq r2, r3 + beq LSYM(Lad_d) +LSYM(Lad_x): + + @ Scale down second arg with exponent difference. + @ Apply shift one bit left to first arg and the rest to second arg + @ to simplify things later, but only if exponent does not become 0. + movs r3, r3, lsr #23 + teqne r2, #(1 << 23) + movne r0, r0, lsl #1 + subne r2, r2, #(1 << 23) + subne r3, r3, #1 + + @ Shift second arg into ip, keep leftover bits into r1. + mov ip, r1, asr r3 + rsb r3, r3, #32 + mov r1, r1, lsl r3 + + add r0, r0, ip @ the actual addition + + @ We now have a 64 bit result in r0-r1. + @ Keep absolute value in r0-r1, sign in r3. + ands r3, r0, #0x80000000 + bpl LSYM(Lad_p) + rsbs r1, r1, #0 + rsc r0, r0, #0 + + @ Determine how to normalize the result. +LSYM(Lad_p): + cmp r0, #0x00800000 + bcc LSYM(Lad_l) + cmp r0, #0x01000000 + bcc LSYM(Lad_r0) + cmp r0, #0x02000000 + bcc LSYM(Lad_r1) + + @ Result needs to be shifted right. + movs r0, r0, lsr #1 + mov r1, r1, rrx + add r2, r2, #(1 << 23) +LSYM(Lad_r1): + movs r0, r0, lsr #1 + mov r1, r1, rrx + add r2, r2, #(1 << 23) + + @ Our result is now properly aligned into r0, remaining bits in r1. + @ Round with MSB of r1. If halfway between two numbers, round towards + @ LSB of r0 = 0. +LSYM(Lad_r0): + add r0, r0, r1, lsr #31 + teq r1, #0x80000000 + biceq r0, r0, #1 + + @ Rounding may have added a new MSB. Adjust exponent. + @ That MSB will be cleared when exponent is merged below. + tst r0, #0x01000000 + addne r2, r2, #(1 << 23) + + @ Make sure we did not bust our exponent. + cmp r2, #(254 << 23) + bhi LSYM(Lad_o) + + @ Pack final result together. +LSYM(Lad_e): + bic r0, r0, #0x01800000 + orr r0, r0, r2 + orr r0, r0, r3 + RET + + @ Result must be shifted left. + @ No rounding necessary since r1 will always be 0. +LSYM(Lad_l): + +#if __ARM_ARCH__ < 5 + + movs ip, r0, lsr #12 + moveq r0, r0, lsl #12 + subeq r2, r2, #(12 << 23) + tst r0, #0x00ff0000 + moveq r0, r0, lsl #8 + subeq r2, r2, #(8 << 23) + tst r0, #0x00f00000 + moveq r0, r0, lsl #4 + subeq r2, r2, #(4 << 23) + tst r0, #0x00c00000 + moveq r0, r0, lsl #2 + subeq r2, r2, #(2 << 23) + tst r0, #0x00800000 + moveq r0, r0, lsl #1 + subeq r2, r2, #(1 << 23) + cmp r2, #0 + bgt LSYM(Lad_e) + +#else + + clz ip, r0 + sub ip, ip, #8 + mov r0, r0, lsl ip + subs r2, r2, ip, lsl #23 + bgt LSYM(Lad_e) + +#endif + + @ Exponent too small, denormalize result. + mvn r2, r2, asr #23 + add r2, r2, #2 + orr r0, r3, r0, lsr r2 + RET + + @ Fixup and adjust bit position for denormalized arguments. + @ Note that r2 must not remain equal to 0. +LSYM(Lad_d): + teq r2, #0 + eoreq r0, r0, #0x00800000 + addeq r2, r2, #(1 << 23) + eor r1, r1, #0x00800000 + subne r3, r3, #(1 << 23) + b LSYM(Lad_x) + + @ Result is x - x = 0, unless x is INF or NAN. +LSYM(Lad_z): + mov ip, #0xff000000 + and r2, r0, ip, lsr #1 + teq r2, ip, lsr #1 + moveq r0, ip, asr #2 + movne r0, #0 + RET + + @ Overflow: return INF. +LSYM(Lad_o): + orr r0, r3, #0x7f000000 + orr r0, r0, #0x00800000 + RET + + @ At least one of r0/r1 is INF/NAN. + @ if r0 != INF/NAN: return r1 (which is INF/NAN) + @ if r1 != INF/NAN: return r0 (which is INF/NAN) + @ if r0 or r1 is NAN: return NAN + @ if opposite sign: return NAN + @ return r0 (which is INF or -INF) +LSYM(Lad_i): + teq r2, ip, lsr #1 + movne r0, r1 + teqeq r3, ip, lsr #1 + RETc(ne) + movs r2, r0, lsl #9 + moveqs r2, r1, lsl #9 + teqeq r0, r1 + orrne r0, r3, #0x00400000 @ NAN + RET + + FUNC_END addsf3 + FUNC_END subsf3 + +ARM_FUNC_START floatunsisf + mov r3, #0 + b 1f + +ARM_FUNC_START floatsisf + ands r3, r0, #0x80000000 + rsbmi r0, r0, #0 + +1: teq r0, #0 + RETc(eq) + + mov r1, #0 + mov r2, #((127 + 23) << 23) + tst r0, #0xfc000000 + beq LSYM(Lad_p) + + @ We need to scale the value a little before branching to code above. + tst r0, #0xf0000000 + movne r1, r0, lsl #28 + movne r0, r0, lsr #4 + addne r2, r2, #(4 << 23) + tst r0, #0x0c000000 + beq LSYM(Lad_p) + mov r1, r1, lsr #2 + orr r1, r1, r0, lsl #30 + mov r0, r0, lsr #2 + add r2, r2, #(2 << 23) + b LSYM(Lad_p) + + FUNC_END floatsisf + FUNC_END floatunsisf + +#endif /* L_addsubsf3 */ + +#ifdef L_muldivsf3 + +ARM_FUNC_START mulsf3 + + @ Mask out exponents. + mov ip, #0xff000000 + and r2, r0, ip, lsr #1 + and r3, r1, ip, lsr #1 + + @ Trap any INF/NAN. + teq r2, ip, lsr #1 + teqne r3, ip, lsr #1 + beq LSYM(Lml_s) + + @ Trap any multiplication by 0. + bics ip, r0, #0x80000000 + bicnes ip, r1, #0x80000000 + beq LSYM(Lml_z) + + @ Shift exponents right one bit to make room for overflow bit. + @ If either of them is 0, scale denormalized arguments off line. + @ Then add both exponents together. + movs r2, r2, lsr #1 + teqne r3, #0 + beq LSYM(Lml_d) +LSYM(Lml_x): + add r2, r2, r3, asr #1 + + @ Preserve final sign in r2 along with exponent for now. + teq r0, r1 + orrmi r2, r2, #0x8000 + + @ Convert mantissa to unsigned integer. + bic r0, r0, #0xff000000 + bic r1, r1, #0xff000000 + orr r0, r0, #0x00800000 + orr r1, r1, #0x00800000 + +#if __ARM_ARCH__ < 4 + + @ Well, no way to make it shorter without the umull instruction. + @ We must perform that 24 x 24 -> 48 bit multiplication by hand. + stmfd sp!, {r4, r5} + mov r4, r0, lsr #16 + mov r5, r1, lsr #16 + bic r0, r0, #0x00ff0000 + bic r1, r1, #0x00ff0000 + mul ip, r4, r5 + mul r3, r0, r1 + mul r0, r5, r0 + mla r0, r4, r1, r0 + adds r3, r3, r0, lsl #16 + adc ip, ip, r0, lsr #16 + ldmfd sp!, {r4, r5} + +#else + + umull r3, ip, r0, r1 @ The actual multiplication. + +#endif + + @ Put final sign in r0. + mov r0, r2, lsl #16 + bic r2, r2, #0x8000 + + @ Adjust result if one extra MSB appeared. + @ The LSB may be lost but this never changes the result in this case. + tst ip, #(1 << 15) + addne r2, r2, #(1 << 22) + movnes ip, ip, lsr #1 + movne r3, r3, rrx + + @ Apply exponent bias, check range for underflow. + subs r2, r2, #(127 << 22) + ble LSYM(Lml_u) + + @ Scale back to 24 bits with rounding. + @ r0 contains sign bit already. + orrs r0, r0, r3, lsr #23 + adc r0, r0, ip, lsl #9 + + @ If halfway between two numbers, rounding should be towards LSB = 0. + mov r3, r3, lsl #9 + teq r3, #0x80000000 + biceq r0, r0, #1 + + @ Note: rounding may have produced an extra MSB here. + @ The extra bit is cleared before merging the exponent below. + tst r0, #0x01000000 + addne r2, r2, #(1 << 22) + + @ Check for exponent overflow + cmp r2, #(255 << 22) + bge LSYM(Lml_o) + + @ Add final exponent. + bic r0, r0, #0x01800000 + orr r0, r0, r2, lsl #1 + RET + + @ Result is 0, but determine sign anyway. +LSYM(Lml_z): + eor r0, r0, r1 + bic r0, r0, #0x7fffffff + RET + + @ Check if denormalized result is possible, otherwise return signed 0. +LSYM(Lml_u): + cmn r2, #(24 << 22) + RETc(le) + + @ Find out proper shift value. + mvn r1, r2, asr #22 + subs r1, r1, #7 + bgt LSYM(Lml_ur) + + @ Shift value left, round, etc. + add r1, r1, #32 + orrs r0, r0, r3, lsr r1 + rsb r1, r1, #32 + adc r0, r0, ip, lsl r1 + mov ip, r3, lsl r1 + teq ip, #0x80000000 + biceq r0, r0, #1 + RET + + @ Shift value right, round, etc. + @ Note: r1 must not be 0 otherwise carry does not get set. +LSYM(Lml_ur): + orrs r0, r0, ip, lsr r1 + adc r0, r0, #0 + rsb r1, r1, #32 + mov ip, ip, lsl r1 + teq r3, #0 + teqeq ip, #0x80000000 + biceq r0, r0, #1 + RET + + @ One or both arguments are denormalized. + @ Scale them leftwards and preserve sign bit. +LSYM(Lml_d): + teq r2, #0 + and ip, r0, #0x80000000 +1: moveq r0, r0, lsl #1 + tsteq r0, #0x00800000 + subeq r2, r2, #(1 << 22) + beq 1b + orr r0, r0, ip + teq r3, #0 + and ip, r1, #0x80000000 +2: moveq r1, r1, lsl #1 + tsteq r1, #0x00800000 + subeq r3, r3, #(1 << 23) + beq 2b + orr r1, r1, ip + b LSYM(Lml_x) + + @ One or both args are INF or NAN. +LSYM(Lml_s): + teq r0, #0x0 + teqne r1, #0x0 + teqne r0, #0x80000000 + teqne r1, #0x80000000 + beq LSYM(Lml_n) @ 0 * INF or INF * 0 -> NAN + teq r2, ip, lsr #1 + bne 1f + movs r2, r0, lsl #9 + bne LSYM(Lml_n) @ NAN * <anything> -> NAN +1: teq r3, ip, lsr #1 + bne LSYM(Lml_i) + movs r3, r1, lsl #9 + bne LSYM(Lml_n) @ <anything> * NAN -> NAN + + @ Result is INF, but we need to determine its sign. +LSYM(Lml_i): + eor r0, r0, r1 + + @ Overflow: return INF (sign already in r0). +LSYM(Lml_o): + and r0, r0, #0x80000000 + orr r0, r0, #0x7f000000 + orr r0, r0, #0x00800000 + RET + + @ Return NAN. +LSYM(Lml_n): + mov r0, #0x7f000000 + orr r0, r0, #0x00c00000 + RET + + FUNC_END mulsf3 + +ARM_FUNC_START divsf3 + + @ Mask out exponents. + mov ip, #0xff000000 + and r2, r0, ip, lsr #1 + and r3, r1, ip, lsr #1 + + @ Trap any INF/NAN or zeroes. + teq r2, ip, lsr #1 + teqne r3, ip, lsr #1 + bicnes ip, r0, #0x80000000 + bicnes ip, r1, #0x80000000 + beq LSYM(Ldv_s) + + @ Shift exponents right one bit to make room for overflow bit. + @ If either of them is 0, scale denormalized arguments off line. + @ Then substract divisor exponent from dividend''s. + movs r2, r2, lsr #1 + teqne r3, #0 + beq LSYM(Ldv_d) +LSYM(Ldv_x): + sub r2, r2, r3, asr #1 + + @ Preserve final sign into ip. + eor ip, r0, r1 + + @ Convert mantissa to unsigned integer. + @ Dividend -> r3, divisor -> r1. + mov r3, #0x10000000 + movs r1, r1, lsl #9 + mov r0, r0, lsl #9 + beq LSYM(Ldv_1) + orr r1, r3, r1, lsr #4 + orr r3, r3, r0, lsr #4 + + @ Initialize r0 (result) with final sign bit. + and r0, ip, #0x80000000 + + @ Ensure result will land to known bit position. + cmp r3, r1 + subcc r2, r2, #(1 << 22) + movcc r3, r3, lsl #1 + + @ Apply exponent bias, check range for over/underflow. + add r2, r2, #(127 << 22) + cmn r2, #(24 << 22) + RETc(le) + cmp r2, #(255 << 22) + bge LSYM(Lml_o) + + @ The actual division loop. + mov ip, #0x00800000 +1: cmp r3, r1 + subcs r3, r3, r1 + orrcs r0, r0, ip + cmp r3, r1, lsr #1 + subcs r3, r3, r1, lsr #1 + orrcs r0, r0, ip, lsr #1 + cmp r3, r1, lsr #2 + subcs r3, r3, r1, lsr #2 + orrcs r0, r0, ip, lsr #2 + cmp r3, r1, lsr #3 + subcs r3, r3, r1, lsr #3 + orrcs r0, r0, ip, lsr #3 + movs r3, r3, lsl #4 + movnes ip, ip, lsr #4 + bne 1b + + @ Check if denormalized result is needed. + cmp r2, #0 + ble LSYM(Ldv_u) + + @ Apply proper rounding. + cmp r3, r1 + addcs r0, r0, #1 + biceq r0, r0, #1 + + @ Add exponent to result. + bic r0, r0, #0x00800000 + orr r0, r0, r2, lsl #1 + RET + + @ Division by 0x1p*: let''s shortcut a lot of code. +LSYM(Ldv_1): + and ip, ip, #0x80000000 + orr r0, ip, r0, lsr #9 + add r2, r2, #(127 << 22) + cmp r2, #(255 << 22) + bge LSYM(Lml_o) + cmp r2, #0 + orrgt r0, r0, r2, lsl #1 + RETc(gt) + cmn r2, #(24 << 22) + movle r0, ip + RETc(le) + orr r0, r0, #0x00800000 + mov r3, #0 + + @ Result must be denormalized: prepare parameters to use code above. + @ r3 already contains remainder for rounding considerations. +LSYM(Ldv_u): + bic ip, r0, #0x80000000 + and r0, r0, #0x80000000 + mvn r1, r2, asr #22 + add r1, r1, #2 + b LSYM(Lml_ur) + + @ One or both arguments are denormalized. + @ Scale them leftwards and preserve sign bit. +LSYM(Ldv_d): + teq r2, #0 + and ip, r0, #0x80000000 +1: moveq r0, r0, lsl #1 + tsteq r0, #0x00800000 + subeq r2, r2, #(1 << 22) + beq 1b + orr r0, r0, ip + teq r3, #0 + and ip, r1, #0x80000000 +2: moveq r1, r1, lsl #1 + tsteq r1, #0x00800000 + subeq r3, r3, #(1 << 23) + beq 2b + orr r1, r1, ip + b LSYM(Ldv_x) + + @ One or both arguments is either INF, NAN or zero. +LSYM(Ldv_s): + mov ip, #0xff000000 + teq r2, ip, lsr #1 + teqeq r3, ip, lsr #1 + beq LSYM(Lml_n) @ INF/NAN / INF/NAN -> NAN + teq r2, ip, lsr #1 + bne 1f + movs r2, r0, lsl #9 + bne LSYM(Lml_n) @ NAN / <anything> -> NAN + b LSYM(Lml_i) @ INF / <anything> -> INF +1: teq r3, ip, lsr #1 + bne 2f + movs r3, r1, lsl #9 + bne LSYM(Lml_n) @ <anything> / NAN -> NAN + b LSYM(Lml_z) @ <anything> / INF -> 0 +2: @ One or both arguments are 0. + bics r2, r0, #0x80000000 + bne LSYM(Lml_i) @ <non_zero> / 0 -> INF + bics r3, r1, #0x80000000 + bne LSYM(Lml_z) @ 0 / <non_zero> -> 0 + b LSYM(Lml_n) @ 0 / 0 -> NAN + + FUNC_END divsf3 + +#endif /* L_muldivsf3 */ + +#ifdef L_cmpsf2 + +ARM_FUNC_START gtsf2 +ARM_FUNC_ALIAS gesf2 gtsf2 + mov r3, #-1 + b 1f + +ARM_FUNC_START ltsf2 +ARM_FUNC_ALIAS lesf2 ltsf2 + mov r3, #1 + b 1f + +ARM_FUNC_START cmpsf2 +ARM_FUNC_ALIAS nesf2 cmpsf2 +ARM_FUNC_ALIAS eqsf2 cmpsf2 + mov r3, #1 @ how should we specify unordered here? + +1: @ Trap any INF/NAN first. + mov ip, #0xff000000 + and r2, r1, ip, lsr #1 + teq r2, ip, lsr #1 + and r2, r0, ip, lsr #1 + teqne r2, ip, lsr #1 + beq 3f + + @ Test for equality. + @ Note that 0.0 is equal to -0.0. +2: orr r3, r0, r1 + bics r3, r3, #0x80000000 @ either 0.0 or -0.0 + teqne r0, r1 @ or both the same + moveq r0, #0 + RETc(eq) + + @ Check for sign difference. The N flag is set if it is the case. + @ If so, return sign of r0. + movmi r0, r0, asr #31 + orrmi r0, r0, #1 + RETc(mi) + + @ Compare exponents. + and r3, r1, ip, lsr #1 + cmp r2, r3 + + @ Compare mantissa if exponents are equal + moveq r0, r0, lsl #9 + cmpeq r0, r1, lsl #9 + movcs r0, r1, asr #31 + mvncc r0, r1, asr #31 + orr r0, r0, #1 + RET + + @ Look for a NAN. +3: and r2, r1, ip, lsr #1 + teq r2, ip, lsr #1 + bne 4f + movs r2, r1, lsl #9 + bne 5f @ r1 is NAN +4: and r2, r0, ip, lsr #1 + teq r2, ip, lsr #1 + bne 2b + movs ip, r0, lsl #9 + beq 2b @ r0 is not NAN +5: mov r0, r3 @ return unordered code from r3. + RET + + FUNC_END gesf2 + FUNC_END gtsf2 + FUNC_END lesf2 + FUNC_END ltsf2 + FUNC_END nesf2 + FUNC_END eqsf2 + FUNC_END cmpsf2 + +#endif /* L_cmpsf2 */ + +#ifdef L_unordsf2 + +ARM_FUNC_START unordsf2 + mov ip, #0xff000000 + and r2, r1, ip, lsr #1 + teq r2, ip, lsr #1 + bne 1f + movs r2, r1, lsl #9 + bne 3f @ r1 is NAN +1: and r2, r0, ip, lsr #1 + teq r2, ip, lsr #1 + bne 2f + movs r2, r0, lsl #9 + bne 3f @ r0 is NAN +2: mov r0, #0 @ arguments are ordered. + RET +3: mov r0, #1 @ arguments are unordered. + RET + + FUNC_END unordsf2 + +#endif /* L_unordsf2 */ + +#ifdef L_fixsfsi + +ARM_FUNC_START fixsfsi + movs r0, r0, lsl #1 + RETc(eq) @ value is 0. + + mov r1, r1, rrx @ preserve C flag (the actual sign) + + @ check exponent range. + and r2, r0, #0xff000000 + cmp r2, #(127 << 24) + movcc r0, #0 @ value is too small + RETc(cc) + cmp r2, #((127 + 31) << 24) + bcs 1f @ value is too large + + mov r0, r0, lsl #7 + orr r0, r0, #0x80000000 + mov r2, r2, lsr #24 + rsb r2, r2, #(127 + 31) + tst r1, #0x80000000 @ the sign bit + mov r0, r0, lsr r2 + rsbne r0, r0, #0 + RET + +1: teq r2, #0xff000000 + bne 2f + movs r0, r0, lsl #8 + bne 3f @ r0 is NAN. +2: ands r0, r1, #0x80000000 @ the sign bit + moveq r0, #0x7fffffff @ the maximum signed positive si + RET + +3: mov r0, #0 @ What should we convert NAN to? + RET + + FUNC_END fixsfsi + +#endif /* L_fixsfsi */ + +#ifdef L_fixunssfsi + +ARM_FUNC_START fixunssfsi + movs r0, r0, lsl #1 + movcss r0, #0 @ value is negative... + RETc(eq) @ ... or 0. + + + @ check exponent range. + and r2, r0, #0xff000000 + cmp r2, #(127 << 24) + movcc r0, #0 @ value is too small + RETc(cc) + cmp r2, #((127 + 32) << 24) + bcs 1f @ value is too large + + mov r0, r0, lsl #7 + orr r0, r0, #0x80000000 + mov r2, r2, lsr #24 + rsb r2, r2, #(127 + 31) + mov r0, r0, lsr r2 + RET + +1: teq r2, #0xff000000 + bne 2f + movs r0, r0, lsl #8 + bne 3f @ r0 is NAN. +2: mov r0, #0xffffffff @ maximum unsigned si + RET + +3: mov r0, #0 @ What should we convert NAN to? + RET + + FUNC_END fixunssfsi + +#endif /* L_fixunssfsi */ diff --git a/contrib/gcc/config/arm/iwmmxt.md b/contrib/gcc/config/arm/iwmmxt.md new file mode 100644 index 0000000..f8070a8 --- /dev/null +++ b/contrib/gcc/config/arm/iwmmxt.md @@ -0,0 +1,1524 @@ +;; Patterns for the Intel Wireless MMX technology architecture. +;; Copyright (C) 2003 Free Software Foundation, Inc. +;; Contributed by Red Hat. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify it under +;; the terms of the GNU General Public License as published by the Free +;; Software Foundation; either version 2, or (at your option) any later +;; version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING. If not, write to +;; the Free Software Foundation, 59 Temple Place - Suite 330, +;; Boston, MA 02111-1307, USA. + +(define_insn "iwmmxt_iordi3" + [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r") + (ior:DI (match_operand:DI 1 "register_operand" "%y,0,r") + (match_operand:DI 2 "register_operand" "y,r,r")))] + "TARGET_REALLY_IWMMXT" + "@ + wor%?\\t%0, %1, %2 + # + #" + [(set_attr "predicable" "yes") + (set_attr "length" "4,8,8")]) + +(define_insn "iwmmxt_xordi3" + [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r") + (xor:DI (match_operand:DI 1 "register_operand" "%y,0,r") + (match_operand:DI 2 "register_operand" "y,r,r")))] + "TARGET_REALLY_IWMMXT" + "@ + wxor%?\\t%0, %1, %2 + # + #" + [(set_attr "predicable" "yes") + (set_attr "length" "4,8,8")]) + +(define_insn "iwmmxt_anddi3" + [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r") + (and:DI (match_operand:DI 1 "register_operand" "%y,0,r") + (match_operand:DI 2 "register_operand" "y,r,r")))] + "TARGET_REALLY_IWMMXT" + "@ + wand%?\\t%0, %1, %2 + # + #" + [(set_attr "predicable" "yes") + (set_attr "length" "4,8,8")]) + +(define_insn "iwmmxt_nanddi3" + [(set (match_operand:DI 0 "register_operand" "=y") + (and:DI (match_operand:DI 1 "register_operand" "y") + (not:DI (match_operand:DI 2 "register_operand" "y"))))] + "TARGET_REALLY_IWMMXT" + "wandn%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "*iwmmxt_arm_movdi" + [(set (match_operand:DI 0 "nonimmediate_di_operand" "=r, r, o<>,y,y,yr,y,yrm") + (match_operand:DI 1 "di_operand" "rIK,mi,r ,y,yr,y,yrm,y"))] + "TARGET_REALLY_IWMMXT" + "* +{ + switch (which_alternative) + { + default: + return output_move_double (operands); + case 3: + return \"wmov%?\\t%0,%1\"; + case 4: + return \"tmcrr%?\\t%0,%Q1,%R1\"; + case 5: + return \"tmrrc%?\\t%Q0,%R0,%1\"; + case 6: + return \"wldrd%?\\t%0,%1\"; + case 7: + return \"wstrd%?\\t%1,%0\"; + } +}" + [(set_attr "length" "8,8,8,4,4,4,4,4") + (set_attr "type" "*,load,store2,*,*,*,*,*") + (set_attr "pool_range" "*,1020,*,*,*,*,*,*") + (set_attr "neg_pool_range" "*,1012,*,*,*,*,*,*")] +) + +(define_insn "*iwmmxt_movsi_insn" + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r,?z,m,z") + (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,z,m,z,z"))] + "TARGET_REALLY_IWMMXT + && ( register_operand (operands[0], SImode) + || register_operand (operands[1], SImode))" + "* + switch (which_alternative) + { + case 0: return \"mov\\t%0, %1\"; + case 1: return \"mvn\\t%0, #%B1\"; + case 2: return \"ldr\\t%0, %1\"; + case 3: return \"str\\t%1, %0\"; + case 4: return \"tmcr\\t%0, %1\"; + case 5: return \"tmrc\\t%0, %1\"; + case 6: return arm_output_load_gr (operands); + case 7: return \"wstrw\\t%1, %0\"; + default:return \"wstrw\\t%1, [sp, #-4]!\;wldrw\\t%0, [sp], #4\\t@move CG reg\"; + }" + [(set_attr "type" "*,*,load,store1,*,*,load,store1,*") + (set_attr "length" "*,*,*, *,*,*, 16, *,8") + (set_attr "pool_range" "*,*,4096, *,*,*,1024, *,*") + (set_attr "neg_pool_range" "*,*,4084, *,*,*, *, 1012,*") + ;; Note - the "predicable" attribute is not allowed to have alternatives. + ;; Since the wSTRw wCx instruction is not predicable, we cannot support + ;; predicating any of the alternatives in this template. Instead, + ;; we do the predication ourselves, in cond_iwmmxt_movsi_insn. + (set_attr "predicable" "no") + ;; Also - we have to pretend that these insns clobber the condition code + ;; bits as otherwise arm_final_prescan_insn() will try to conditionalize + ;; them. + (set_attr "conds" "clob")] +) + +;; Because iwmmxt_movsi_insn is not predicable, we provide the +;; cond_exec version explicitly, with appropriate constraints. + +(define_insn "*cond_iwmmxt_movsi_insn" + [(cond_exec + (match_operator 2 "arm_comparison_operator" + [(match_operand 3 "cc_register" "") + (const_int 0)]) + (set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r") + (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,z")))] + "TARGET_REALLY_IWMMXT + && ( register_operand (operands[0], SImode) + || register_operand (operands[1], SImode))" + "* + switch (which_alternative) + { + case 0: return \"mov%?\\t%0, %1\"; + case 1: return \"mvn%?\\t%0, #%B1\"; + case 2: return \"ldr%?\\t%0, %1\"; + case 3: return \"str%?\\t%1, %0\"; + case 4: return \"tmcr%?\\t%0, %1\"; + default: return \"tmrc%?\\t%0, %1\"; + }" + [(set_attr "type" "*,*,load,store1,*,*") + (set_attr "pool_range" "*,*,4096, *,*,*") + (set_attr "neg_pool_range" "*,*,4084, *,*,*")] +) + +(define_insn "movv8qi_internal" + [(set (match_operand:V8QI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r") + (match_operand:V8QI 1 "general_operand" "y,y,m,y,r,i"))] + "TARGET_REALLY_IWMMXT" + "* + switch (which_alternative) + { + case 0: return \"wmov%?\\t%0, %1\"; + case 1: return \"wstrd%?\\t%1, %0\"; + case 2: return \"wldrd%?\\t%0, %1\"; + case 3: return \"tmrrc%?\\t%Q0, %R0, %1\"; + case 4: return \"tmcrr%?\\t%0, %Q1, %R1\"; + default: return output_move_double (operands); + }" + [(set_attr "predicable" "yes") + (set_attr "length" "4, 4, 4,4,4, 8") + (set_attr "type" "*,store1,load,*,*,load") + (set_attr "pool_range" "*, *, 256,*,*, 256") + (set_attr "neg_pool_range" "*, *, 244,*,*, 244")]) + +(define_insn "movv4hi_internal" + [(set (match_operand:V4HI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r") + (match_operand:V4HI 1 "general_operand" "y,y,m,y,r,i"))] + "TARGET_REALLY_IWMMXT" + "* + switch (which_alternative) + { + case 0: return \"wmov%?\\t%0, %1\"; + case 1: return \"wstrd%?\\t%1, %0\"; + case 2: return \"wldrd%?\\t%0, %1\"; + case 3: return \"tmrrc%?\\t%Q0, %R0, %1\"; + case 4: return \"tmcrr%?\\t%0, %Q1, %R1\"; + default: return output_move_double (operands); + }" + [(set_attr "predicable" "yes") + (set_attr "length" "4, 4, 4,4,4, 8") + (set_attr "type" "*,store1,load,*,*,load") + (set_attr "pool_range" "*, *, 256,*,*, 256") + (set_attr "neg_pool_range" "*, *, 244,*,*, 244")]) + +(define_insn "movv2si_internal" + [(set (match_operand:V2SI 0 "nonimmediate_operand" "=y,m,y,?r,?y,?r") + (match_operand:V2SI 1 "general_operand" "y,y,m,y,r,i"))] + "TARGET_REALLY_IWMMXT" + "* + switch (which_alternative) + { + case 0: return \"wmov%?\\t%0, %1\"; + case 1: return \"wstrd%?\\t%1, %0\"; + case 2: return \"wldrd%?\\t%0, %1\"; + case 3: return \"tmrrc%?\\t%Q0, %R0, %1\"; + case 4: return \"tmcrr%?\\t%0, %Q1, %R1\"; + default: return output_move_double (operands); + }" + [(set_attr "predicable" "yes") + (set_attr "length" "4, 4, 4,4,4, 24") + (set_attr "type" "*,store1,load,*,*,load") + (set_attr "pool_range" "*, *, 256,*,*, 256") + (set_attr "neg_pool_range" "*, *, 244,*,*, 244")]) + +;; This pattern should not be needed. It is to match a +;; wierd case generated by GCC when no optimizations are +;; enabled. (Try compiling gcc/testsuite/gcc.c-torture/ +;; compile/simd-5.c at -O0). The mode for operands[1] is +;; deliberately omitted. +(define_insn "movv2si_internal_2" + [(set (match_operand:V2SI 0 "nonimmediate_operand" "=?r") + (match_operand 1 "immediate_operand" "i"))] + "TARGET_REALLY_IWMMXT" + "* return output_move_double (operands);" + [(set_attr "predicable" "yes") + (set_attr "length" "8") + (set_attr "type" "load") + (set_attr "pool_range" "256") + (set_attr "neg_pool_range" "244")]) + +;; Vector add/subtract + +(define_insn "addv8qi3" + [(set (match_operand:V8QI 0 "register_operand" "=y") + (plus:V8QI (match_operand:V8QI 1 "register_operand" "y") + (match_operand:V8QI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "waddb%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "addv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (plus:V4HI (match_operand:V4HI 1 "register_operand" "y") + (match_operand:V4HI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "waddh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "addv2si3" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (plus:V2SI (match_operand:V2SI 1 "register_operand" "y") + (match_operand:V2SI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "waddw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "ssaddv8qi3" + [(set (match_operand:V8QI 0 "register_operand" "=y") + (ss_plus:V8QI (match_operand:V8QI 1 "register_operand" "y") + (match_operand:V8QI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "waddbss%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "ssaddv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (ss_plus:V4HI (match_operand:V4HI 1 "register_operand" "y") + (match_operand:V4HI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "waddhss%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "ssaddv2si3" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (ss_plus:V2SI (match_operand:V2SI 1 "register_operand" "y") + (match_operand:V2SI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "waddwss%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "usaddv8qi3" + [(set (match_operand:V8QI 0 "register_operand" "=y") + (us_plus:V8QI (match_operand:V8QI 1 "register_operand" "y") + (match_operand:V8QI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "waddbus%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "usaddv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (us_plus:V4HI (match_operand:V4HI 1 "register_operand" "y") + (match_operand:V4HI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "waddhus%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "usaddv2si3" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (us_plus:V2SI (match_operand:V2SI 1 "register_operand" "y") + (match_operand:V2SI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "waddwus%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "subv8qi3" + [(set (match_operand:V8QI 0 "register_operand" "=y") + (minus:V8QI (match_operand:V8QI 1 "register_operand" "y") + (match_operand:V8QI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wsubb%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "subv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (minus:V4HI (match_operand:V4HI 1 "register_operand" "y") + (match_operand:V4HI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wsubh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "subv2si3" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (minus:V2SI (match_operand:V2SI 1 "register_operand" "y") + (match_operand:V2SI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wsubw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "sssubv8qi3" + [(set (match_operand:V8QI 0 "register_operand" "=y") + (ss_minus:V8QI (match_operand:V8QI 1 "register_operand" "y") + (match_operand:V8QI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wsubbss%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "sssubv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (ss_minus:V4HI (match_operand:V4HI 1 "register_operand" "y") + (match_operand:V4HI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wsubhss%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "sssubv2si3" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (ss_minus:V2SI (match_operand:V2SI 1 "register_operand" "y") + (match_operand:V2SI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wsubwss%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "ussubv8qi3" + [(set (match_operand:V8QI 0 "register_operand" "=y") + (us_minus:V8QI (match_operand:V8QI 1 "register_operand" "y") + (match_operand:V8QI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wsubbus%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "ussubv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (us_minus:V4HI (match_operand:V4HI 1 "register_operand" "y") + (match_operand:V4HI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wsubhus%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "ussubv2si3" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (us_minus:V2SI (match_operand:V2SI 1 "register_operand" "y") + (match_operand:V2SI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wsubwus%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "mulv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (mult:V4HI (match_operand:V4HI 1 "register_operand" "y") + (match_operand:V4HI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wmulul%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "smulv4hi3_highpart" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (truncate:V4HI + (lshiftrt:V4SI + (mult:V4SI (sign_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) + (sign_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) + (const_int 16))))] + "TARGET_REALLY_IWMMXT" + "wmulsm%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "umulv4hi3_highpart" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (truncate:V4HI + (lshiftrt:V4SI + (mult:V4SI (zero_extend:V4SI (match_operand:V4HI 1 "register_operand" "y")) + (zero_extend:V4SI (match_operand:V4HI 2 "register_operand" "y"))) + (const_int 16))))] + "TARGET_REALLY_IWMMXT" + "wmulum%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wmacs" + [(set (match_operand:DI 0 "register_operand" "=y") + (unspec:DI [(match_operand:DI 1 "register_operand" "0") + (match_operand:V4HI 2 "register_operand" "y") + (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACS))] + "TARGET_REALLY_IWMMXT" + "wmacs%?\\t%0, %2, %3" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wmacsz" + [(set (match_operand:DI 0 "register_operand" "=y") + (unspec:DI [(match_operand:V4HI 1 "register_operand" "y") + (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACSZ))] + "TARGET_REALLY_IWMMXT" + "wmacsz%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wmacu" + [(set (match_operand:DI 0 "register_operand" "=y") + (unspec:DI [(match_operand:DI 1 "register_operand" "0") + (match_operand:V4HI 2 "register_operand" "y") + (match_operand:V4HI 3 "register_operand" "y")] UNSPEC_WMACU))] + "TARGET_REALLY_IWMMXT" + "wmacu%?\\t%0, %2, %3" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wmacuz" + [(set (match_operand:DI 0 "register_operand" "=y") + (unspec:DI [(match_operand:V4HI 1 "register_operand" "y") + (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMACUZ))] + "TARGET_REALLY_IWMMXT" + "wmacuz%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +;; Same as xordi3, but don't show input operands so that we don't think +;; they are live. +(define_insn "iwmmxt_clrdi" + [(set (match_operand:DI 0 "register_operand" "=y") + (unspec:DI [(const_int 0)] UNSPEC_CLRDI))] + "TARGET_REALLY_IWMMXT" + "wxor%?\\t%0, %0, %0" + [(set_attr "predicable" "yes")]) + +;; Seems like cse likes to generate these, so we have to support them. + +(define_insn "*iwmmxt_clrv8qi" + [(set (match_operand:V8QI 0 "register_operand" "=y") + (const_vector:V8QI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0) + (const_int 0) (const_int 0)]))] + "TARGET_REALLY_IWMMXT" + "wxor%?\\t%0, %0, %0" + [(set_attr "predicable" "yes")]) + +(define_insn "*iwmmxt_clrv4hi" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (const_vector:V4HI [(const_int 0) (const_int 0) + (const_int 0) (const_int 0)]))] + "TARGET_REALLY_IWMMXT" + "wxor%?\\t%0, %0, %0" + [(set_attr "predicable" "yes")]) + +(define_insn "*iwmmxt_clrv2si" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (const_vector:V2SI [(const_int 0) (const_int 0)]))] + "TARGET_REALLY_IWMMXT" + "wxor%?\\t%0, %0, %0" + [(set_attr "predicable" "yes")]) + +;; Unsigned averages/sum of absolute differences + +(define_insn "iwmmxt_uavgrndv8qi3" + [(set (match_operand:V8QI 0 "register_operand" "=y") + (ashiftrt:V8QI + (plus:V8QI (plus:V8QI + (match_operand:V8QI 1 "register_operand" "y") + (match_operand:V8QI 2 "register_operand" "y")) + (const_vector:V8QI [(const_int 1) + (const_int 1) + (const_int 1) + (const_int 1) + (const_int 1) + (const_int 1) + (const_int 1) + (const_int 1)])) + (const_int 1)))] + "TARGET_REALLY_IWMMXT" + "wavg2br%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_uavgrndv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (ashiftrt:V4HI + (plus:V4HI (plus:V4HI + (match_operand:V4HI 1 "register_operand" "y") + (match_operand:V4HI 2 "register_operand" "y")) + (const_vector:V4HI [(const_int 1) + (const_int 1) + (const_int 1) + (const_int 1)])) + (const_int 1)))] + "TARGET_REALLY_IWMMXT" + "wavg2hr%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + + +(define_insn "iwmmxt_uavgv8qi3" + [(set (match_operand:V8QI 0 "register_operand" "=y") + (ashiftrt:V8QI (plus:V8QI + (match_operand:V8QI 1 "register_operand" "y") + (match_operand:V8QI 2 "register_operand" "y")) + (const_int 1)))] + "TARGET_REALLY_IWMMXT" + "wavg2b%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_uavgv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (ashiftrt:V4HI (plus:V4HI + (match_operand:V4HI 1 "register_operand" "y") + (match_operand:V4HI 2 "register_operand" "y")) + (const_int 1)))] + "TARGET_REALLY_IWMMXT" + "wavg2h%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_psadbw" + [(set (match_operand:V8QI 0 "register_operand" "=y") + (abs:V8QI (minus:V8QI (match_operand:V8QI 1 "register_operand" "y") + (match_operand:V8QI 2 "register_operand" "y"))))] + "TARGET_REALLY_IWMMXT" + "psadbw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + + +;; Insert/extract/shuffle + +(define_insn "iwmmxt_tinsrb" + [(set (match_operand:V8QI 0 "register_operand" "=y") + (vec_merge:V8QI (match_operand:V8QI 1 "register_operand" "0") + (vec_duplicate:V8QI + (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r"))) + (match_operand:SI 3 "immediate_operand" "i")))] + "TARGET_REALLY_IWMMXT" + "tinsrb%?\\t%0, %2, %3" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_tinsrh" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (vec_merge:V4HI (match_operand:V4HI 1 "register_operand" "0") + (vec_duplicate:V4HI + (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r"))) + (match_operand:SI 3 "immediate_operand" "i")))] + "TARGET_REALLY_IWMMXT" + "tinsrh%?\\t%0, %2, %3" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_tinsrw" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (vec_merge:V2SI (match_operand:V2SI 1 "register_operand" "0") + (vec_duplicate:V2SI + (match_operand:SI 2 "nonimmediate_operand" "r")) + (match_operand:SI 3 "immediate_operand" "i")))] + "TARGET_REALLY_IWMMXT" + "tinsrw%?\\t%0, %2, %3" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_textrmub" + [(set (match_operand:SI 0 "register_operand" "=r") + (zero_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y") + (parallel + [(match_operand:SI 2 "immediate_operand" "i")]))))] + "TARGET_REALLY_IWMMXT" + "textrmub%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_textrmsb" + [(set (match_operand:SI 0 "register_operand" "=r") + (sign_extend:SI (vec_select:QI (match_operand:V8QI 1 "register_operand" "y") + (parallel + [(match_operand:SI 2 "immediate_operand" "i")]))))] + "TARGET_REALLY_IWMMXT" + "textrmsb%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_textrmuh" + [(set (match_operand:SI 0 "register_operand" "=r") + (zero_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y") + (parallel + [(match_operand:SI 2 "immediate_operand" "i")]))))] + "TARGET_REALLY_IWMMXT" + "textrmuh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_textrmsh" + [(set (match_operand:SI 0 "register_operand" "=r") + (sign_extend:SI (vec_select:HI (match_operand:V4HI 1 "register_operand" "y") + (parallel + [(match_operand:SI 2 "immediate_operand" "i")]))))] + "TARGET_REALLY_IWMMXT" + "textrmsh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +;; There are signed/unsigned variants of this instruction, but they are +;; pointless. +(define_insn "iwmmxt_textrmw" + [(set (match_operand:SI 0 "register_operand" "=r") + (vec_select:SI (match_operand:V2SI 1 "register_operand" "y") + (parallel [(match_operand:SI 2 "immediate_operand" "i")])))] + "TARGET_REALLY_IWMMXT" + "textrmsw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wshufh" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") + (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_WSHUFH))] + "TARGET_REALLY_IWMMXT" + "wshufh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +;; Mask-generating comparisons +;; +;; Note - you cannot use patterns like these here: +;; +;; (set:<vector> (match:<vector>) (<comparator>:<vector> (match:<vector>) (match:<vector>))) +;; +;; Because GCC will assume that the truth value (1 or 0) is installed +;; into the entire destination vector, (with the '1' going into the least +;; significant element of the vector). This is not how these instructions +;; behave. +;; +;; Unfortunately the current patterns are illegal. They are SET insns +;; without a SET in them. They work in most cases for ordinary code +;; generation, but there are circumstances where they can cause gcc to fail. +;; XXX - FIXME. + +(define_insn "eqv8qi3" + [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y") + (match_operand:V8QI 1 "register_operand" "y") + (match_operand:V8QI 2 "register_operand" "y")] + VUNSPEC_WCMP_EQ)] + "TARGET_REALLY_IWMMXT" + "wcmpeqb%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "eqv4hi3" + [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y") + (match_operand:V4HI 1 "register_operand" "y") + (match_operand:V4HI 2 "register_operand" "y")] + VUNSPEC_WCMP_EQ)] + "TARGET_REALLY_IWMMXT" + "wcmpeqh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "eqv2si3" + [(unspec_volatile:V2SI [(match_operand:V2SI 0 "register_operand" "=y") + (match_operand:V2SI 1 "register_operand" "y") + (match_operand:V2SI 2 "register_operand" "y")] + VUNSPEC_WCMP_EQ)] + "TARGET_REALLY_IWMMXT" + "wcmpeqw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "gtuv8qi3" + [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y") + (match_operand:V8QI 1 "register_operand" "y") + (match_operand:V8QI 2 "register_operand" "y")] + VUNSPEC_WCMP_GTU)] + "TARGET_REALLY_IWMMXT" + "wcmpgtub%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "gtuv4hi3" + [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y") + (match_operand:V4HI 1 "register_operand" "y") + (match_operand:V4HI 2 "register_operand" "y")] + VUNSPEC_WCMP_GTU)] + "TARGET_REALLY_IWMMXT" + "wcmpgtuh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "gtuv2si3" + [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y") + (match_operand:V2SI 1 "register_operand" "y") + (match_operand:V2SI 2 "register_operand" "y")] + VUNSPEC_WCMP_GTU)] + "TARGET_REALLY_IWMMXT" + "wcmpgtuw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "gtv8qi3" + [(unspec_volatile [(match_operand:V8QI 0 "register_operand" "=y") + (match_operand:V8QI 1 "register_operand" "y") + (match_operand:V8QI 2 "register_operand" "y")] + VUNSPEC_WCMP_GT)] + "TARGET_REALLY_IWMMXT" + "wcmpgtsb%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "gtv4hi3" + [(unspec_volatile [(match_operand:V4HI 0 "register_operand" "=y") + (match_operand:V4HI 1 "register_operand" "y") + (match_operand:V4HI 2 "register_operand" "y")] + VUNSPEC_WCMP_GT)] + "TARGET_REALLY_IWMMXT" + "wcmpgtsh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "gtv2si3" + [(unspec_volatile [(match_operand:V2SI 0 "register_operand" "=y") + (match_operand:V2SI 1 "register_operand" "y") + (match_operand:V2SI 2 "register_operand" "y")] + VUNSPEC_WCMP_GT)] + "TARGET_REALLY_IWMMXT" + "wcmpgtsw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +;; Max/min insns + +(define_insn "smaxv8qi3" + [(set (match_operand:V8QI 0 "register_operand" "=y") + (smax:V8QI (match_operand:V8QI 1 "register_operand" "y") + (match_operand:V8QI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wmaxsb%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "umaxv8qi3" + [(set (match_operand:V8QI 0 "register_operand" "=y") + (umax:V8QI (match_operand:V8QI 1 "register_operand" "y") + (match_operand:V8QI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wmaxub%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "smaxv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (smax:V4HI (match_operand:V4HI 1 "register_operand" "y") + (match_operand:V4HI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wmaxsh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "umaxv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (umax:V4HI (match_operand:V4HI 1 "register_operand" "y") + (match_operand:V4HI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wmaxuh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "smaxv2si3" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (smax:V2SI (match_operand:V2SI 1 "register_operand" "y") + (match_operand:V2SI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wmaxsw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "umaxv2si3" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (umax:V2SI (match_operand:V2SI 1 "register_operand" "y") + (match_operand:V2SI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wmaxuw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "sminv8qi3" + [(set (match_operand:V8QI 0 "register_operand" "=y") + (smin:V8QI (match_operand:V8QI 1 "register_operand" "y") + (match_operand:V8QI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wminsb%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "uminv8qi3" + [(set (match_operand:V8QI 0 "register_operand" "=y") + (umin:V8QI (match_operand:V8QI 1 "register_operand" "y") + (match_operand:V8QI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wminub%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "sminv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (smin:V4HI (match_operand:V4HI 1 "register_operand" "y") + (match_operand:V4HI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wminsh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "uminv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (umin:V4HI (match_operand:V4HI 1 "register_operand" "y") + (match_operand:V4HI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wminuh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "sminv2si3" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (smin:V2SI (match_operand:V2SI 1 "register_operand" "y") + (match_operand:V2SI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wminsw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "uminv2si3" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (umin:V2SI (match_operand:V2SI 1 "register_operand" "y") + (match_operand:V2SI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wminuw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +;; Pack/unpack insns. + +(define_insn "iwmmxt_wpackhss" + [(set (match_operand:V8QI 0 "register_operand" "=y") + (vec_concat:V8QI + (ss_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y")) + (ss_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))] + "TARGET_REALLY_IWMMXT" + "wpackhss%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wpackwss" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (vec_concat:V4HI + (ss_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y")) + (ss_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))] + "TARGET_REALLY_IWMMXT" + "wpackwss%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wpackdss" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (vec_concat:V2SI + (ss_truncate:SI (match_operand:DI 1 "register_operand" "y")) + (ss_truncate:SI (match_operand:DI 2 "register_operand" "y"))))] + "TARGET_REALLY_IWMMXT" + "wpackdss%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wpackhus" + [(set (match_operand:V8QI 0 "register_operand" "=y") + (vec_concat:V8QI + (us_truncate:V4QI (match_operand:V4HI 1 "register_operand" "y")) + (us_truncate:V4QI (match_operand:V4HI 2 "register_operand" "y"))))] + "TARGET_REALLY_IWMMXT" + "wpackhus%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wpackwus" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (vec_concat:V4HI + (us_truncate:V2HI (match_operand:V2SI 1 "register_operand" "y")) + (us_truncate:V2HI (match_operand:V2SI 2 "register_operand" "y"))))] + "TARGET_REALLY_IWMMXT" + "wpackwus%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wpackdus" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (vec_concat:V2SI + (us_truncate:SI (match_operand:DI 1 "register_operand" "y")) + (us_truncate:SI (match_operand:DI 2 "register_operand" "y"))))] + "TARGET_REALLY_IWMMXT" + "wpackdus%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + + +(define_insn "iwmmxt_wunpckihb" + [(set (match_operand:V8QI 0 "register_operand" "=y") + (vec_merge:V8QI + (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y") + (parallel [(const_int 4) + (const_int 0) + (const_int 5) + (const_int 1) + (const_int 6) + (const_int 2) + (const_int 7) + (const_int 3)])) + (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y") + (parallel [(const_int 0) + (const_int 4) + (const_int 1) + (const_int 5) + (const_int 2) + (const_int 6) + (const_int 3) + (const_int 7)])) + (const_int 85)))] + "TARGET_REALLY_IWMMXT" + "wunpckihb%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wunpckihh" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (vec_merge:V4HI + (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y") + (parallel [(const_int 0) + (const_int 2) + (const_int 1) + (const_int 3)])) + (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") + (parallel [(const_int 2) + (const_int 0) + (const_int 3) + (const_int 1)])) + (const_int 5)))] + "TARGET_REALLY_IWMMXT" + "wunpckihh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wunpckihw" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (vec_merge:V2SI + (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y") + (parallel [(const_int 0) + (const_int 1)])) + (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y") + (parallel [(const_int 1) + (const_int 0)])) + (const_int 1)))] + "TARGET_REALLY_IWMMXT" + "wunpckihw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wunpckilb" + [(set (match_operand:V8QI 0 "register_operand" "=y") + (vec_merge:V8QI + (vec_select:V8QI (match_operand:V8QI 1 "register_operand" "y") + (parallel [(const_int 0) + (const_int 4) + (const_int 1) + (const_int 5) + (const_int 2) + (const_int 6) + (const_int 3) + (const_int 7)])) + (vec_select:V8QI (match_operand:V8QI 2 "register_operand" "y") + (parallel [(const_int 4) + (const_int 0) + (const_int 5) + (const_int 1) + (const_int 6) + (const_int 2) + (const_int 7) + (const_int 3)])) + (const_int 85)))] + "TARGET_REALLY_IWMMXT" + "wunpckilb%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wunpckilh" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (vec_merge:V4HI + (vec_select:V4HI (match_operand:V4HI 1 "register_operand" "y") + (parallel [(const_int 2) + (const_int 0) + (const_int 3) + (const_int 1)])) + (vec_select:V4HI (match_operand:V4HI 2 "register_operand" "y") + (parallel [(const_int 0) + (const_int 2) + (const_int 1) + (const_int 3)])) + (const_int 5)))] + "TARGET_REALLY_IWMMXT" + "wunpckilh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wunpckilw" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (vec_merge:V2SI + (vec_select:V2SI (match_operand:V2SI 1 "register_operand" "y") + (parallel [(const_int 1) + (const_int 0)])) + (vec_select:V2SI (match_operand:V2SI 2 "register_operand" "y") + (parallel [(const_int 0) + (const_int 1)])) + (const_int 1)))] + "TARGET_REALLY_IWMMXT" + "wunpckilw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wunpckehub" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (zero_extend:V4HI + (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y") + (parallel [(const_int 4) (const_int 5) + (const_int 6) (const_int 7)]))))] + "TARGET_REALLY_IWMMXT" + "wunpckehub%?\\t%0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wunpckehuh" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (zero_extend:V2SI + (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y") + (parallel [(const_int 2) (const_int 3)]))))] + "TARGET_REALLY_IWMMXT" + "wunpckehuh%?\\t%0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wunpckehuw" + [(set (match_operand:DI 0 "register_operand" "=y") + (zero_extend:DI + (vec_select:SI (match_operand:V2SI 1 "register_operand" "y") + (parallel [(const_int 1)]))))] + "TARGET_REALLY_IWMMXT" + "wunpckehuw%?\\t%0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wunpckehsb" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (sign_extend:V4HI + (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y") + (parallel [(const_int 4) (const_int 5) + (const_int 6) (const_int 7)]))))] + "TARGET_REALLY_IWMMXT" + "wunpckehsb%?\\t%0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wunpckehsh" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (sign_extend:V2SI + (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y") + (parallel [(const_int 2) (const_int 3)]))))] + "TARGET_REALLY_IWMMXT" + "wunpckehsh%?\\t%0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wunpckehsw" + [(set (match_operand:DI 0 "register_operand" "=y") + (sign_extend:DI + (vec_select:SI (match_operand:V2SI 1 "register_operand" "y") + (parallel [(const_int 1)]))))] + "TARGET_REALLY_IWMMXT" + "wunpckehsw%?\\t%0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wunpckelub" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (zero_extend:V4HI + (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y") + (parallel [(const_int 0) (const_int 1) + (const_int 2) (const_int 3)]))))] + "TARGET_REALLY_IWMMXT" + "wunpckelub%?\\t%0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wunpckeluh" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (zero_extend:V2SI + (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y") + (parallel [(const_int 0) (const_int 1)]))))] + "TARGET_REALLY_IWMMXT" + "wunpckeluh%?\\t%0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wunpckeluw" + [(set (match_operand:DI 0 "register_operand" "=y") + (zero_extend:DI + (vec_select:SI (match_operand:V2SI 1 "register_operand" "y") + (parallel [(const_int 0)]))))] + "TARGET_REALLY_IWMMXT" + "wunpckeluw%?\\t%0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wunpckelsb" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (sign_extend:V4HI + (vec_select:V4QI (match_operand:V8QI 1 "register_operand" "y") + (parallel [(const_int 0) (const_int 1) + (const_int 2) (const_int 3)]))))] + "TARGET_REALLY_IWMMXT" + "wunpckelsb%?\\t%0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wunpckelsh" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (sign_extend:V2SI + (vec_select:V2HI (match_operand:V4HI 1 "register_operand" "y") + (parallel [(const_int 0) (const_int 1)]))))] + "TARGET_REALLY_IWMMXT" + "wunpckelsh%?\\t%0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wunpckelsw" + [(set (match_operand:DI 0 "register_operand" "=y") + (sign_extend:DI + (vec_select:SI (match_operand:V2SI 1 "register_operand" "y") + (parallel [(const_int 0)]))))] + "TARGET_REALLY_IWMMXT" + "wunpckelsw%?\\t%0, %1" + [(set_attr "predicable" "yes")]) + +;; Shifts + +(define_insn "rorv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y") + (match_operand:SI 2 "register_operand" "z")))] + "TARGET_REALLY_IWMMXT" + "wrorhg%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "rorv2si3" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y") + (match_operand:SI 2 "register_operand" "z")))] + "TARGET_REALLY_IWMMXT" + "wrorwg%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "rordi3" + [(set (match_operand:DI 0 "register_operand" "=y") + (rotatert:DI (match_operand:DI 1 "register_operand" "y") + (match_operand:SI 2 "register_operand" "z")))] + "TARGET_REALLY_IWMMXT" + "wrordg%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "ashrv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y") + (match_operand:SI 2 "register_operand" "z")))] + "TARGET_REALLY_IWMMXT" + "wsrahg%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "ashrv2si3" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y") + (match_operand:SI 2 "register_operand" "z")))] + "TARGET_REALLY_IWMMXT" + "wsrawg%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "ashrdi3" + [(set (match_operand:DI 0 "register_operand" "=y") + (ashiftrt:DI (match_operand:DI 1 "register_operand" "y") + (match_operand:SI 2 "register_operand" "z")))] + "TARGET_REALLY_IWMMXT" + "wsradg%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "lshrv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y") + (match_operand:SI 2 "register_operand" "z")))] + "TARGET_REALLY_IWMMXT" + "wsrlhg%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "lshrv2si3" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y") + (match_operand:SI 2 "register_operand" "z")))] + "TARGET_REALLY_IWMMXT" + "wsrlwg%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "lshrdi3" + [(set (match_operand:DI 0 "register_operand" "=y") + (lshiftrt:DI (match_operand:DI 1 "register_operand" "y") + (match_operand:SI 2 "register_operand" "z")))] + "TARGET_REALLY_IWMMXT" + "wsrldg%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "ashlv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y") + (match_operand:SI 2 "register_operand" "z")))] + "TARGET_REALLY_IWMMXT" + "wsllhg%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "ashlv2si3" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y") + (match_operand:SI 2 "register_operand" "z")))] + "TARGET_REALLY_IWMMXT" + "wsllwg%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "ashldi3_iwmmxt" + [(set (match_operand:DI 0 "register_operand" "=y") + (ashift:DI (match_operand:DI 1 "register_operand" "y") + (match_operand:SI 2 "register_operand" "z")))] + "TARGET_REALLY_IWMMXT" + "wslldg%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "rorv4hi3_di" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (rotatert:V4HI (match_operand:V4HI 1 "register_operand" "y") + (match_operand:DI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wrorh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "rorv2si3_di" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (rotatert:V2SI (match_operand:V2SI 1 "register_operand" "y") + (match_operand:DI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wrorw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "rordi3_di" + [(set (match_operand:DI 0 "register_operand" "=y") + (rotatert:DI (match_operand:DI 1 "register_operand" "y") + (match_operand:DI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wrord%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "ashrv4hi3_di" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (ashiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y") + (match_operand:DI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wsrah%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "ashrv2si3_di" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (ashiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y") + (match_operand:DI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wsraw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "ashrdi3_di" + [(set (match_operand:DI 0 "register_operand" "=y") + (ashiftrt:DI (match_operand:DI 1 "register_operand" "y") + (match_operand:DI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wsrad%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "lshrv4hi3_di" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (lshiftrt:V4HI (match_operand:V4HI 1 "register_operand" "y") + (match_operand:DI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wsrlh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "lshrv2si3_di" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (lshiftrt:V2SI (match_operand:V2SI 1 "register_operand" "y") + (match_operand:DI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wsrlw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "lshrdi3_di" + [(set (match_operand:DI 0 "register_operand" "=y") + (lshiftrt:DI (match_operand:DI 1 "register_operand" "y") + (match_operand:DI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wsrld%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "ashlv4hi3_di" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (ashift:V4HI (match_operand:V4HI 1 "register_operand" "y") + (match_operand:DI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wsllh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "ashlv2si3_di" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (ashift:V2SI (match_operand:V2SI 1 "register_operand" "y") + (match_operand:DI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wsllw%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "ashldi3_di" + [(set (match_operand:DI 0 "register_operand" "=y") + (ashift:DI (match_operand:DI 1 "register_operand" "y") + (match_operand:DI 2 "register_operand" "y")))] + "TARGET_REALLY_IWMMXT" + "wslld%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wmadds" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") + (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDS))] + "TARGET_REALLY_IWMMXT" + "wmadds%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wmaddu" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") + (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WMADDU))] + "TARGET_REALLY_IWMMXT" + "wmaddu%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_tmia" + [(set (match_operand:DI 0 "register_operand" "=y") + (plus:DI (match_operand:DI 1 "register_operand" "0") + (mult:DI (sign_extend:DI + (match_operand:SI 2 "register_operand" "r")) + (sign_extend:DI + (match_operand:SI 3 "register_operand" "r")))))] + "TARGET_REALLY_IWMMXT" + "tmia%?\\t%0, %2, %3" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_tmiaph" + [(set (match_operand:DI 0 "register_operand" "=y") + (plus:DI (match_operand:DI 1 "register_operand" "0") + (plus:DI + (mult:DI (sign_extend:DI + (truncate:HI (match_operand:SI 2 "register_operand" "r"))) + (sign_extend:DI + (truncate:HI (match_operand:SI 3 "register_operand" "r")))) + (mult:DI (sign_extend:DI + (truncate:HI (ashiftrt:SI (match_dup 2) (const_int 16)))) + (sign_extend:DI + (truncate:HI (ashiftrt:SI (match_dup 3) (const_int 16))))))))] + "TARGET_REALLY_IWMMXT" + "tmiaph%?\\t%0, %2, %3" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_tmiabb" + [(set (match_operand:DI 0 "register_operand" "=y") + (plus:DI (match_operand:DI 1 "register_operand" "0") + (mult:DI (sign_extend:DI + (truncate:HI (match_operand:SI 2 "register_operand" "r"))) + (sign_extend:DI + (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))] + "TARGET_REALLY_IWMMXT" + "tmiabb%?\\t%0, %2, %3" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_tmiatb" + [(set (match_operand:DI 0 "register_operand" "=y") + (plus:DI (match_operand:DI 1 "register_operand" "0") + (mult:DI (sign_extend:DI + (truncate:HI (ashiftrt:SI + (match_operand:SI 2 "register_operand" "r") + (const_int 16)))) + (sign_extend:DI + (truncate:HI (match_operand:SI 3 "register_operand" "r"))))))] + "TARGET_REALLY_IWMMXT" + "tmiatb%?\\t%0, %2, %3" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_tmiabt" + [(set (match_operand:DI 0 "register_operand" "=y") + (plus:DI (match_operand:DI 1 "register_operand" "0") + (mult:DI (sign_extend:DI + (truncate:HI (match_operand:SI 2 "register_operand" "r"))) + (sign_extend:DI + (truncate:HI (ashiftrt:SI + (match_operand:SI 3 "register_operand" "r") + (const_int 16)))))))] + "TARGET_REALLY_IWMMXT" + "tmiabt%?\\t%0, %2, %3" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_tmiatt" + [(set (match_operand:DI 0 "register_operand" "=y") + (plus:DI (match_operand:DI 1 "register_operand" "0") + (mult:DI (sign_extend:DI + (truncate:HI (ashiftrt:SI + (match_operand:SI 2 "register_operand" "r") + (const_int 16)))) + (sign_extend:DI + (truncate:HI (ashiftrt:SI + (match_operand:SI 3 "register_operand" "r") + (const_int 16)))))))] + "TARGET_REALLY_IWMMXT" + "tmiatt%?\\t%0, %2, %3" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_tbcstqi" + [(set (match_operand:V8QI 0 "register_operand" "=y") + (vec_duplicate:V8QI (match_operand:QI 1 "register_operand" "r")))] + "TARGET_REALLY_IWMMXT" + "tbcstb%?\\t%0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_tbcsthi" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (vec_duplicate:V4HI (match_operand:HI 1 "register_operand" "r")))] + "TARGET_REALLY_IWMMXT" + "tbcsth%?\\t%0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_tbcstsi" + [(set (match_operand:V2SI 0 "register_operand" "=y") + (vec_duplicate:V2SI (match_operand:SI 1 "register_operand" "r")))] + "TARGET_REALLY_IWMMXT" + "tbcstw%?\\t%0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_tmovmskb" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_TMOVMSK))] + "TARGET_REALLY_IWMMXT" + "tmovmskb%?\\t%0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_tmovmskh" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_TMOVMSK))] + "TARGET_REALLY_IWMMXT" + "tmovmskh%?\\t%0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_tmovmskw" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_TMOVMSK))] + "TARGET_REALLY_IWMMXT" + "tmovmskw%?\\t%0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_waccb" + [(set (match_operand:DI 0 "register_operand" "=y") + (unspec:DI [(match_operand:V8QI 1 "register_operand" "y")] UNSPEC_WACC))] + "TARGET_REALLY_IWMMXT" + "waccb%?\\t%0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wacch" + [(set (match_operand:DI 0 "register_operand" "=y") + (unspec:DI [(match_operand:V4HI 1 "register_operand" "y")] UNSPEC_WACC))] + "TARGET_REALLY_IWMMXT" + "wacch%?\\t%0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_waccw" + [(set (match_operand:DI 0 "register_operand" "=y") + (unspec:DI [(match_operand:V2SI 1 "register_operand" "y")] UNSPEC_WACC))] + "TARGET_REALLY_IWMMXT" + "waccw%?\\t%0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_walign" + [(set (match_operand:V8QI 0 "register_operand" "=y,y") + (subreg:V8QI (ashiftrt:TI + (subreg:TI (vec_concat:V16QI + (match_operand:V8QI 1 "register_operand" "y,y") + (match_operand:V8QI 2 "register_operand" "y,y")) 0) + (mult:SI + (match_operand:SI 3 "nonmemory_operand" "i,z") + (const_int 8))) 0))] + "TARGET_REALLY_IWMMXT" + "@ + waligni%?\\t%0, %1, %2, %3 + walignr%U3%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_tmrc" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")] + VUNSPEC_TMRC))] + "TARGET_REALLY_IWMMXT" + "tmrc%?\\t%0, %w1" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_tmcr" + [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i") + (match_operand:SI 1 "register_operand" "r")] + VUNSPEC_TMCR)] + "TARGET_REALLY_IWMMXT" + "tmcr%?\\t%w0, %1" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wsadb" + [(set (match_operand:V8QI 0 "register_operand" "=y") + (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") + (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSAD))] + "TARGET_REALLY_IWMMXT" + "wsadb%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wsadh" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") + (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSAD))] + "TARGET_REALLY_IWMMXT" + "wsadh%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wsadbz" + [(set (match_operand:V8QI 0 "register_operand" "=y") + (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "y") + (match_operand:V8QI 2 "register_operand" "y")] UNSPEC_WSADZ))] + "TARGET_REALLY_IWMMXT" + "wsadbz%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + +(define_insn "iwmmxt_wsadhz" + [(set (match_operand:V4HI 0 "register_operand" "=y") + (unspec:V4HI [(match_operand:V4HI 1 "register_operand" "y") + (match_operand:V4HI 2 "register_operand" "y")] UNSPEC_WSADZ))] + "TARGET_REALLY_IWMMXT" + "wsadhz%?\\t%0, %1, %2" + [(set_attr "predicable" "yes")]) + diff --git a/contrib/gcc/config/arm/kaos-arm.h b/contrib/gcc/config/arm/kaos-arm.h new file mode 100644 index 0000000..0d3bf2d --- /dev/null +++ b/contrib/gcc/config/arm/kaos-arm.h @@ -0,0 +1,24 @@ +/* Definitions of target machine for GNU compiler. + kaOS on arm architecture version. + Copyright (C) 2003 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#undef TARGET_VERSION +#define TARGET_VERSION fputs (" (ARM/kaOS[ELF])", stderr); + diff --git a/contrib/gcc/config/arm/kaos-strongarm.h b/contrib/gcc/config/arm/kaos-strongarm.h new file mode 100644 index 0000000..8eb9473 --- /dev/null +++ b/contrib/gcc/config/arm/kaos-strongarm.h @@ -0,0 +1,24 @@ +/* Definitions of target machine for GNU compiler. + kaOS on strongarm architecture version. + Copyright (C) 2003 Free Software Foundation, Inc. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#undef TARGET_VERSION +#define TARGET_VERSION fputs (" (StrongARM/kaOS[ELF])", stderr); + diff --git a/contrib/gcc/config/arm/lib1funcs.asm b/contrib/gcc/config/arm/lib1funcs.asm index ec706ec..e72af6c 100644 --- a/contrib/gcc/config/arm/lib1funcs.asm +++ b/contrib/gcc/config/arm/lib1funcs.asm @@ -1,7 +1,8 @@ @ libgcc routines for ARM cpu. @ Division routines, written by Richard Earnshaw, (rearnsha@armltd.co.uk) -/* Copyright 1995, 1996, 1998, 1999, 2000 Free Software Foundation, Inc. +/* Copyright 1995, 1996, 1998, 1999, 2000, 2003, 2004 + Free Software Foundation, Inc. This file is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the @@ -51,74 +52,117 @@ Boston, MA 02111-1307, USA. */ #endif #define TYPE(x) .type SYM(x),function #define SIZE(x) .size SYM(x), . - SYM(x) +#define LSYM(x) .x #else #define __PLT__ #define TYPE(x) #define SIZE(x) +#define LSYM(x) x #endif /* Function end macros. Variants for 26 bit APCS and interworking. */ +@ This selects the minimum architecture level required. +#define __ARM_ARCH__ 3 + +#if defined(__ARM_ARCH_3M__) || defined(__ARM_ARCH_4__) \ + || defined(__ARM_ARCH_4T__) +/* We use __ARM_ARCH__ set to 4 here, but in reality it's any processor with + long multiply instructions. That includes v3M. */ +# undef __ARM_ARCH__ +# define __ARM_ARCH__ 4 +#endif + +#if defined(__ARM_ARCH_5__) || defined(__ARM_ARCH_5T__) \ + || defined(__ARM_ARCH_5TE__) +# undef __ARM_ARCH__ +# define __ARM_ARCH__ 5 +#endif + +/* How to return from a function call depends on the architecture variant. */ + #ifdef __APCS_26__ + # define RET movs pc, lr # define RETc(x) mov##x##s pc, lr -# define RETCOND ^ + +#elif (__ARM_ARCH__ > 4) || defined(__ARM_ARCH_4T__) + +# define RET bx lr +# define RETc(x) bx##x lr + +# if (__ARM_ARCH__ == 4) \ + && (defined(__thumb__) || defined(__THUMB_INTERWORK__)) +# define __INTERWORKING__ +# endif + +#else + +# define RET mov pc, lr +# define RETc(x) mov##x pc, lr + +#endif + +/* Don't pass dirn, it's there just to get token pasting right. */ + +.macro RETLDM regs=, cond=, dirn=ia +#ifdef __APCS_26__ + .ifc "\regs","" + ldm\cond\dirn sp!, {pc}^ + .else + ldm\cond\dirn sp!, {\regs, pc}^ + .endif +#elif defined (__INTERWORKING__) + .ifc "\regs","" + ldr\cond lr, [sp], #4 + .else + ldm\cond\dirn sp!, {\regs, lr} + .endif + bx\cond lr +#else + .ifc "\regs","" + ldr\cond pc, [sp], #4 + .else + ldm\cond\dirn sp!, {\regs, pc} + .endif +#endif +.endm + + .macro ARM_LDIV0 -Ldiv0: +LSYM(Ldiv0): str lr, [sp, #-4]! bl SYM (__div0) __PLT__ mov r0, #0 @ About as wrong as it could be. - ldmia sp!, {pc}^ + RETLDM .endm -#else -# ifdef __THUMB_INTERWORK__ -# define RET bx lr -# define RETc(x) bx##x lr + + .macro THUMB_LDIV0 -Ldiv0: +LSYM(Ldiv0): push { lr } bl SYM (__div0) mov r0, #0 @ About as wrong as it could be. +#if defined (__INTERWORKING__) pop { r1 } bx r1 -.endm -.macro ARM_LDIV0 -Ldiv0: - str lr, [sp, #-4]! - bl SYM (__div0) __PLT__ - mov r0, #0 @ About as wrong as it could be. - ldr lr, [sp], #4 - bx lr -.endm -# else -# define RET mov pc, lr -# define RETc(x) mov##x pc, lr -.macro THUMB_LDIV0 -Ldiv0: - push { lr } - bl SYM (__div0) - mov r0, #0 @ About as wrong as it could be. +#else pop { pc } -.endm -.macro ARM_LDIV0 -Ldiv0: - str lr, [sp, #-4]! - bl SYM (__div0) __PLT__ - mov r0, #0 @ About as wrong as it could be. - ldmia sp!, {pc} -.endm -# endif -# define RETCOND #endif +.endm .macro FUNC_END name -Ldiv0: + SIZE (__\name) +.endm + +.macro DIV_FUNC_END name +LSYM(Ldiv0): #ifdef __thumb__ THUMB_LDIV0 #else ARM_LDIV0 #endif - SIZE (__\name) + FUNC_END \name .endm .macro THUMB_FUNC_START name @@ -147,7 +191,37 @@ SYM (\name): THUMB_FUNC SYM (__\name): .endm - + +/* Special function that will always be coded in ARM assembly, even if + in Thumb-only compilation. */ + +#if defined(__thumb__) && !defined(__THUMB_INTERWORK__) +.macro ARM_FUNC_START name + FUNC_START \name + bx pc + nop + .arm +_L__\name: /* A hook to tell gdb that we've switched to ARM */ +.endm +#define EQUIV .thumb_set +#else +.macro ARM_FUNC_START name + .text + .globl SYM (__\name) + TYPE (__\name) + .align 0 + .arm +SYM (__\name): +.endm +#define EQUIV .set +#endif + +.macro ARM_FUNC_ALIAS new old + .globl SYM (__\new) + EQUIV SYM (__\new), SYM (__\old) +.endm + +#ifdef __thumb__ /* Register aliases. */ work .req r4 @ XXXX is this safe ? @@ -156,133 +230,212 @@ divisor .req r1 overdone .req r2 result .req r2 curbit .req r3 +#endif +#if 0 ip .req r12 sp .req r13 lr .req r14 pc .req r15 +#endif /* ------------------------------------------------------------------------ */ -/* Bodies of the divsion and modulo routines. */ +/* Bodies of the division and modulo routines. */ /* ------------------------------------------------------------------------ */ -.macro ARM_DIV_MOD_BODY modulo -Loop1: +.macro ARM_DIV_BODY dividend, divisor, result, curbit + +#if __ARM_ARCH__ >= 5 + + clz \curbit, \divisor + clz \result, \dividend + sub \result, \curbit, \result + mov \curbit, #1 + mov \divisor, \divisor, lsl \result + mov \curbit, \curbit, lsl \result + mov \result, #0 + +#else + + @ Initially shift the divisor left 3 bits if possible, + @ set curbit accordingly. This allows for curbit to be located + @ at the left end of each 4 bit nibbles in the division loop + @ to save one loop in most cases. + tst \divisor, #0xe0000000 + moveq \divisor, \divisor, lsl #3 + moveq \curbit, #8 + movne \curbit, #1 + @ Unless the divisor is very big, shift it up in multiples of @ four bits, since this is the amount of unwinding in the main @ division loop. Continue shifting until the divisor is @ larger than the dividend. - cmp divisor, #0x10000000 - cmplo divisor, dividend - movlo divisor, divisor, lsl #4 - movlo curbit, curbit, lsl #4 - blo Loop1 +1: cmp \divisor, #0x10000000 + cmplo \divisor, \dividend + movlo \divisor, \divisor, lsl #4 + movlo \curbit, \curbit, lsl #4 + blo 1b -Lbignum: @ For very big divisors, we must shift it a bit at a time, or @ we will be in danger of overflowing. - cmp divisor, #0x80000000 - cmplo divisor, dividend - movlo divisor, divisor, lsl #1 - movlo curbit, curbit, lsl #1 - blo Lbignum +1: cmp \divisor, #0x80000000 + cmplo \divisor, \dividend + movlo \divisor, \divisor, lsl #1 + movlo \curbit, \curbit, lsl #1 + blo 1b + + mov \result, #0 + +#endif + + @ Division loop +1: cmp \dividend, \divisor + subhs \dividend, \dividend, \divisor + orrhs \result, \result, \curbit + cmp \dividend, \divisor, lsr #1 + subhs \dividend, \dividend, \divisor, lsr #1 + orrhs \result, \result, \curbit, lsr #1 + cmp \dividend, \divisor, lsr #2 + subhs \dividend, \dividend, \divisor, lsr #2 + orrhs \result, \result, \curbit, lsr #2 + cmp \dividend, \divisor, lsr #3 + subhs \dividend, \dividend, \divisor, lsr #3 + orrhs \result, \result, \curbit, lsr #3 + cmp \dividend, #0 @ Early termination? + movnes \curbit, \curbit, lsr #4 @ No, any more bits to do? + movne \divisor, \divisor, lsr #4 + bne 1b + +.endm +/* ------------------------------------------------------------------------ */ +.macro ARM_DIV2_ORDER divisor, order + +#if __ARM_ARCH__ >= 5 + + clz \order, \divisor + rsb \order, \order, #31 + +#else -Loop3: - @ Test for possible subtractions. On the final pass, this may - @ subtract too much from the dividend ... + cmp \divisor, #(1 << 16) + movhs \divisor, \divisor, lsr #16 + movhs \order, #16 + movlo \order, #0 + + cmp \divisor, #(1 << 8) + movhs \divisor, \divisor, lsr #8 + addhs \order, \order, #8 + + cmp \divisor, #(1 << 4) + movhs \divisor, \divisor, lsr #4 + addhs \order, \order, #4 + + cmp \divisor, #(1 << 2) + addhi \order, \order, #3 + addls \order, \order, \divisor, lsr #1 + +#endif + +.endm +/* ------------------------------------------------------------------------ */ +.macro ARM_MOD_BODY dividend, divisor, order, spare + +#if __ARM_ARCH__ >= 5 + + clz \order, \divisor + clz \spare, \dividend + sub \order, \order, \spare + mov \divisor, \divisor, lsl \order - .if \modulo - @ ... so keep track of which subtractions are done in OVERDONE. - @ We can fix them up afterwards. - mov overdone, #0 - cmp dividend, divisor - subhs dividend, dividend, divisor - cmp dividend, divisor, lsr #1 - subhs dividend, dividend, divisor, lsr #1 - orrhs overdone, overdone, curbit, ror #1 - cmp dividend, divisor, lsr #2 - subhs dividend, dividend, divisor, lsr #2 - orrhs overdone, overdone, curbit, ror #2 - cmp dividend, divisor, lsr #3 - subhs dividend, dividend, divisor, lsr #3 - orrhs overdone, overdone, curbit, ror #3 - mov ip, curbit - .else - @ ... so keep track of which subtractions are done in RESULT. - @ The result will be ok, since the "bit" will have been - @ shifted out at the bottom. - cmp dividend, divisor - subhs dividend, dividend, divisor - orrhs result, result, curbit - cmp dividend, divisor, lsr #1 - subhs dividend, dividend, divisor, lsr #1 - orrhs result, result, curbit, lsr #1 - cmp dividend, divisor, lsr #2 - subhs dividend, dividend, divisor, lsr #2 - orrhs result, result, curbit, lsr #2 - cmp dividend, divisor, lsr #3 - subhs dividend, dividend, divisor, lsr #3 - orrhs result, result, curbit, lsr #3 - .endif +#else - cmp dividend, #0 @ Early termination? - movnes curbit, curbit, lsr #4 @ No, any more bits to do? - movne divisor, divisor, lsr #4 - bne Loop3 + mov \order, #0 - .if \modulo -Lfixup_dividend: - @ Any subtractions that we should not have done will be recorded in - @ the top three bits of OVERDONE. Exactly which were not needed - @ are governed by the position of the bit, stored in IP. - ands overdone, overdone, #0xe0000000 - @ If we terminated early, because dividend became zero, then the - @ bit in ip will not be in the bottom nibble, and we should not - @ perform the additions below. We must test for this though - @ (rather relying upon the TSTs to prevent the additions) since - @ the bit in ip could be in the top two bits which might then match - @ with one of the smaller RORs. - tstne ip, #0x7 - beq Lgot_result - tst overdone, ip, ror #3 - addne dividend, dividend, divisor, lsr #3 - tst overdone, ip, ror #2 - addne dividend, dividend, divisor, lsr #2 - tst overdone, ip, ror #1 - addne dividend, dividend, divisor, lsr #1 - .endif + @ Unless the divisor is very big, shift it up in multiples of + @ four bits, since this is the amount of unwinding in the main + @ division loop. Continue shifting until the divisor is + @ larger than the dividend. +1: cmp \divisor, #0x10000000 + cmplo \divisor, \dividend + movlo \divisor, \divisor, lsl #4 + addlo \order, \order, #4 + blo 1b -Lgot_result: + @ For very big divisors, we must shift it a bit at a time, or + @ we will be in danger of overflowing. +1: cmp \divisor, #0x80000000 + cmplo \divisor, \dividend + movlo \divisor, \divisor, lsl #1 + addlo \order, \order, #1 + blo 1b + +#endif + + @ Perform all needed substractions to keep only the reminder. + @ Do comparisons in batch of 4 first. + subs \order, \order, #3 @ yes, 3 is intended here + blt 2f + +1: cmp \dividend, \divisor + subhs \dividend, \dividend, \divisor + cmp \dividend, \divisor, lsr #1 + subhs \dividend, \dividend, \divisor, lsr #1 + cmp \dividend, \divisor, lsr #2 + subhs \dividend, \dividend, \divisor, lsr #2 + cmp \dividend, \divisor, lsr #3 + subhs \dividend, \dividend, \divisor, lsr #3 + cmp \dividend, #1 + mov \divisor, \divisor, lsr #4 + subges \order, \order, #4 + bge 1b + + tst \order, #3 + teqne \dividend, #0 + beq 5f + + @ Either 1, 2 or 3 comparison/substractions are left. +2: cmn \order, #2 + blt 4f + beq 3f + cmp \dividend, \divisor + subhs \dividend, \dividend, \divisor + mov \divisor, \divisor, lsr #1 +3: cmp \dividend, \divisor + subhs \dividend, \dividend, \divisor + mov \divisor, \divisor, lsr #1 +4: cmp \dividend, \divisor + subhs \dividend, \dividend, \divisor +5: .endm /* ------------------------------------------------------------------------ */ .macro THUMB_DIV_MOD_BODY modulo @ Load the constant 0x10000000 into our work register. mov work, #1 lsl work, #28 -Loop1: +LSYM(Loop1): @ Unless the divisor is very big, shift it up in multiples of @ four bits, since this is the amount of unwinding in the main @ division loop. Continue shifting until the divisor is @ larger than the dividend. cmp divisor, work - bhs Lbignum + bhs LSYM(Lbignum) cmp divisor, dividend - bhs Lbignum + bhs LSYM(Lbignum) lsl divisor, #4 lsl curbit, #4 - b Loop1 -Lbignum: + b LSYM(Loop1) +LSYM(Lbignum): @ Set work to 0x80000000 lsl work, #3 -Loop2: +LSYM(Loop2): @ For very big divisors, we must shift it a bit at a time, or @ we will be in danger of overflowing. cmp divisor, work - bhs Loop3 + bhs LSYM(Loop3) cmp divisor, dividend - bhs Loop3 + bhs LSYM(Loop3) lsl divisor, #1 lsl curbit, #1 - b Loop2 -Loop3: + b LSYM(Loop2) +LSYM(Loop3): @ Test for possible subtractions ... .if \modulo @ ... On the final pass, this may subtract too much from the dividend, @@ -290,79 +443,79 @@ Loop3: @ afterwards. mov overdone, #0 cmp dividend, divisor - blo Lover1 + blo LSYM(Lover1) sub dividend, dividend, divisor -Lover1: +LSYM(Lover1): lsr work, divisor, #1 cmp dividend, work - blo Lover2 + blo LSYM(Lover2) sub dividend, dividend, work mov ip, curbit mov work, #1 ror curbit, work orr overdone, curbit mov curbit, ip -Lover2: +LSYM(Lover2): lsr work, divisor, #2 cmp dividend, work - blo Lover3 + blo LSYM(Lover3) sub dividend, dividend, work mov ip, curbit mov work, #2 ror curbit, work orr overdone, curbit mov curbit, ip -Lover3: +LSYM(Lover3): lsr work, divisor, #3 cmp dividend, work - blo Lover4 + blo LSYM(Lover4) sub dividend, dividend, work mov ip, curbit mov work, #3 ror curbit, work orr overdone, curbit mov curbit, ip -Lover4: +LSYM(Lover4): mov ip, curbit .else @ ... and note which bits are done in the result. On the final pass, @ this may subtract too much from the dividend, but the result will be ok, @ since the "bit" will have been shifted out at the bottom. cmp dividend, divisor - blo Lover1 + blo LSYM(Lover1) sub dividend, dividend, divisor orr result, result, curbit -Lover1: +LSYM(Lover1): lsr work, divisor, #1 cmp dividend, work - blo Lover2 + blo LSYM(Lover2) sub dividend, dividend, work lsr work, curbit, #1 orr result, work -Lover2: +LSYM(Lover2): lsr work, divisor, #2 cmp dividend, work - blo Lover3 + blo LSYM(Lover3) sub dividend, dividend, work lsr work, curbit, #2 orr result, work -Lover3: +LSYM(Lover3): lsr work, divisor, #3 cmp dividend, work - blo Lover4 + blo LSYM(Lover4) sub dividend, dividend, work lsr work, curbit, #3 orr result, work -Lover4: +LSYM(Lover4): .endif cmp dividend, #0 @ Early termination? - beq Lover5 + beq LSYM(Lover5) lsr curbit, #4 @ No, any more bits to do? - beq Lover5 + beq LSYM(Lover5) lsr divisor, #4 - b Loop3 -Lover5: + b LSYM(Loop3) +LSYM(Lover5): .if \modulo @ Any subtractions that we should not have done will be recorded in @ the top three bits of "overdone". Exactly which were not needed @@ -370,7 +523,7 @@ Lover5: mov work, #0xe lsl work, #28 and overdone, work - beq Lgot_result + beq LSYM(Lgot_result) @ If we terminated early, because dividend became zero, then the @ bit in ip will not be in the bottom nibble, and we should not @@ -381,33 +534,33 @@ Lover5: mov curbit, ip mov work, #0x7 tst curbit, work - beq Lgot_result + beq LSYM(Lgot_result) mov curbit, ip mov work, #3 ror curbit, work tst overdone, curbit - beq Lover6 + beq LSYM(Lover6) lsr work, divisor, #3 add dividend, work -Lover6: +LSYM(Lover6): mov curbit, ip mov work, #2 ror curbit, work tst overdone, curbit - beq Lover7 + beq LSYM(Lover7) lsr work, divisor, #2 add dividend, work -Lover7: +LSYM(Lover7): mov curbit, ip mov work, #1 ror curbit, work tst overdone, curbit - beq Lgot_result + beq LSYM(Lgot_result) lsr work, divisor, #1 add dividend, work .endif -Lgot_result: +LSYM(Lgot_result): .endm /* ------------------------------------------------------------------------ */ /* Start of the Real Functions */ @@ -419,13 +572,13 @@ Lgot_result: #ifdef __thumb__ cmp divisor, #0 - beq Ldiv0 + beq LSYM(Ldiv0) mov curbit, #1 mov result, #0 push { work } cmp dividend, divisor - blo Lgot_result + blo LSYM(Lgot_result) THUMB_DIV_MOD_BODY 0 @@ -434,22 +587,32 @@ Lgot_result: RET #else /* ARM version. */ + + subs r2, r1, #1 + RETc(eq) + bcc LSYM(Ldiv0) + cmp r0, r1 + bls 11f + tst r1, r2 + beq 12f - cmp divisor, #0 - beq Ldiv0 - mov curbit, #1 - mov result, #0 - cmp dividend, divisor - blo Lgot_result - - ARM_DIV_MOD_BODY 0 + ARM_DIV_BODY r0, r1, r2, r3 - mov r0, result + mov r0, r2 RET +11: moveq r0, #1 + movne r0, #0 + RET + +12: ARM_DIV2_ORDER r1, r2 + + mov r0, r0, lsr r2 + RET + #endif /* ARM version */ - FUNC_END udivsi3 + DIV_FUNC_END udivsi3 #endif /* L_udivsi3 */ /* ------------------------------------------------------------------------ */ @@ -460,13 +623,13 @@ Lgot_result: #ifdef __thumb__ cmp divisor, #0 - beq Ldiv0 + beq LSYM(Ldiv0) mov curbit, #1 cmp dividend, divisor - bhs Lover10 + bhs LSYM(Lover10) RET -Lover10: +LSYM(Lover10): push { work } THUMB_DIV_MOD_BODY 1 @@ -476,21 +639,21 @@ Lover10: #else /* ARM version. */ - cmp divisor, #0 - beq Ldiv0 - cmp divisor, #1 - cmpne dividend, divisor - moveq dividend, #0 - RETc(lo) - mov curbit, #1 + subs r2, r1, #1 @ compare divisor with 1 + bcc LSYM(Ldiv0) + cmpne r0, r1 @ compare dividend with divisor + moveq r0, #0 + tsthi r1, r2 @ see if divisor is power of 2 + andeq r0, r0, r2 + RETc(ls) - ARM_DIV_MOD_BODY 1 + ARM_MOD_BODY r0, r1, r2, r3 RET #endif /* ARM version. */ - FUNC_END umodsi3 + DIV_FUNC_END umodsi3 #endif /* L_umodsi3 */ /* ------------------------------------------------------------------------ */ @@ -500,7 +663,7 @@ Lover10: #ifdef __thumb__ cmp divisor, #0 - beq Ldiv0 + beq LSYM(Ldiv0) push { work } mov work, dividend @@ -509,50 +672,67 @@ Lover10: mov curbit, #1 mov result, #0 cmp divisor, #0 - bpl Lover10 + bpl LSYM(Lover10) neg divisor, divisor @ Loops below use unsigned. -Lover10: +LSYM(Lover10): cmp dividend, #0 - bpl Lover11 + bpl LSYM(Lover11) neg dividend, dividend -Lover11: +LSYM(Lover11): cmp dividend, divisor - blo Lgot_result + blo LSYM(Lgot_result) THUMB_DIV_MOD_BODY 0 mov r0, result mov work, ip cmp work, #0 - bpl Lover12 + bpl LSYM(Lover12) neg r0, r0 -Lover12: +LSYM(Lover12): pop { work } RET #else /* ARM version. */ - eor ip, dividend, divisor @ Save the sign of the result. - mov curbit, #1 - mov result, #0 - cmp divisor, #0 - rsbmi divisor, divisor, #0 @ Loops below use unsigned. - beq Ldiv0 - cmp dividend, #0 - rsbmi dividend, dividend, #0 - cmp dividend, divisor - blo Lgot_result - - ARM_DIV_MOD_BODY 0 + cmp r1, #0 + eor ip, r0, r1 @ save the sign of the result. + beq LSYM(Ldiv0) + rsbmi r1, r1, #0 @ loops below use unsigned. + subs r2, r1, #1 @ division by 1 or -1 ? + beq 10f + movs r3, r0 + rsbmi r3, r0, #0 @ positive dividend value + cmp r3, r1 + bls 11f + tst r1, r2 @ divisor is power of 2 ? + beq 12f + + ARM_DIV_BODY r3, r1, r0, r2 - mov r0, result cmp ip, #0 rsbmi r0, r0, #0 RET +10: teq ip, r0 @ same sign ? + rsbmi r0, r0, #0 + RET + +11: movlo r0, #0 + moveq r0, ip, asr #31 + orreq r0, r0, #1 + RET + +12: ARM_DIV2_ORDER r1, r2 + + cmp ip, #0 + mov r0, r3, lsr r2 + rsbmi r0, r0, #0 + RET + #endif /* ARM version */ - FUNC_END divsi3 + DIV_FUNC_END divsi3 #endif /* L_divsi3 */ /* ------------------------------------------------------------------------ */ @@ -564,56 +744,55 @@ Lover12: mov curbit, #1 cmp divisor, #0 - beq Ldiv0 - bpl Lover10 + beq LSYM(Ldiv0) + bpl LSYM(Lover10) neg divisor, divisor @ Loops below use unsigned. -Lover10: +LSYM(Lover10): push { work } @ Need to save the sign of the dividend, unfortunately, we need @ work later on. Must do this after saving the original value of @ the work register, because we will pop this value off first. push { dividend } cmp dividend, #0 - bpl Lover11 + bpl LSYM(Lover11) neg dividend, dividend -Lover11: +LSYM(Lover11): cmp dividend, divisor - blo Lgot_result + blo LSYM(Lgot_result) THUMB_DIV_MOD_BODY 1 pop { work } cmp work, #0 - bpl Lover12 + bpl LSYM(Lover12) neg dividend, dividend -Lover12: +LSYM(Lover12): pop { work } RET #else /* ARM version. */ - cmp divisor, #0 - rsbmi divisor, divisor, #0 @ Loops below use unsigned. - beq Ldiv0 - @ Need to save the sign of the dividend, unfortunately, we need - @ ip later on; this is faster than pushing lr and using that. - str dividend, [sp, #-4]! - cmp dividend, #0 @ Test dividend against zero - rsbmi dividend, dividend, #0 @ If negative make positive - cmp dividend, divisor @ else if zero return zero - blo Lgot_result @ if smaller return dividend - mov curbit, #1 - - ARM_DIV_MOD_BODY 1 - - ldr ip, [sp], #4 - cmp ip, #0 - rsbmi dividend, dividend, #0 + cmp r1, #0 + beq LSYM(Ldiv0) + rsbmi r1, r1, #0 @ loops below use unsigned. + movs ip, r0 @ preserve sign of dividend + rsbmi r0, r0, #0 @ if negative make positive + subs r2, r1, #1 @ compare divisor with 1 + cmpne r0, r1 @ compare dividend with divisor + moveq r0, #0 + tsthi r1, r2 @ see if divisor is power of 2 + andeq r0, r0, r2 + bls 10f + + ARM_MOD_BODY r0, r1, r2, r3 + +10: cmp ip, #0 + rsbmi r0, r0, #0 RET #endif /* ARM version */ - FUNC_END modsi3 + DIV_FUNC_END modsi3 #endif /* L_modsi3 */ /* ------------------------------------------------------------------------ */ @@ -623,7 +802,7 @@ Lover12: RET - SIZE (__div0) + FUNC_END div0 #endif /* L_divmodsi_tools */ /* ------------------------------------------------------------------------ */ @@ -636,22 +815,18 @@ Lover12: #define __NR_getpid (__NR_SYSCALL_BASE+ 20) #define __NR_kill (__NR_SYSCALL_BASE+ 37) + .code 32 FUNC_START div0 stmfd sp!, {r1, lr} swi __NR_getpid cmn r0, #1000 - ldmhsfd sp!, {r1, pc}RETCOND @ not much we can do + RETLDM r1 hs mov r1, #SIGFPE swi __NR_kill -#ifdef __THUMB_INTERWORK__ - ldmfd sp!, {r1, lr} - bx lr -#else - ldmfd sp!, {r1, pc}RETCOND -#endif + RETLDM r1 - SIZE (__div0) + FUNC_END div0 #endif /* L_dvmd_lnx */ /* ------------------------------------------------------------------------ */ @@ -720,24 +895,23 @@ Lover12: .code 32 .globl _arm_return -_arm_return: - ldmia r13!, {r12} - bx r12 +_arm_return: + RETLDM .code 16 -.macro interwork register - .code 16 +.macro interwork register + .code 16 THUMB_FUNC_START _interwork_call_via_\register - bx pc + bx pc nop - - .code 32 - .globl .Lchange_\register -.Lchange_\register: + + .code 32 + .globl LSYM(Lchange_\register) +LSYM(Lchange_\register): tst \register, #1 - stmeqdb r13!, {lr} + streq lr, [sp, #-4]! adreq lr, _arm_return bx \register @@ -779,3 +953,7 @@ _arm_return: SIZE (_interwork_call_via_lr) #endif /* L_interwork_call_via_rX */ + +#include "ieee754-df.S" +#include "ieee754-sf.S" + diff --git a/contrib/gcc/config/arm/linux-elf.h b/contrib/gcc/config/arm/linux-elf.h index 8cc812f..9f291c0 100644 --- a/contrib/gcc/config/arm/linux-elf.h +++ b/contrib/gcc/config/arm/linux-elf.h @@ -1,24 +1,24 @@ /* Definitions for ARM running Linux-based GNU systems using ELF - Copyright (C) 1993, 1994, 1997, 1998, 1999, 2000, 2001, 2002 + Copyright (C) 1993, 1994, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. Contributed by Philip Blundell <philb@gnu.org> -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with this program; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ /* elfos.h should have already been included. Now just override any conflicting definitions and add any extras. */ @@ -34,6 +34,8 @@ Boston, MA 02111-1307, USA. */ #undef TARGET_DEFAULT #define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_MMU_TRAPS) +#define SUBTARGET_CPU_DEFAULT TARGET_CPU_arm6 + #define SUBTARGET_EXTRA_LINK_SPEC " -m armelf_linux -p" #undef MULTILIB_DEFAULTS @@ -47,6 +49,7 @@ Boston, MA 02111-1307, USA. */ #define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)" /* Now we define the strings used to build the spec file. */ +#undef LIB_SPEC #define LIB_SPEC \ "%{pthread:-lpthread} \ %{shared:-lc} \ @@ -57,7 +60,7 @@ Boston, MA 02111-1307, USA. */ /* Provide a STARTFILE_SPEC appropriate for GNU/Linux. Here we add the GNU/Linux magical crtbegin.o file (see crtstuff.c) which provides part of the support for getting C++ file-scope static - object constructed before entering `main'. */ + object constructed before entering `main'. */ #undef STARTFILE_SPEC #define STARTFILE_SPEC \ @@ -89,15 +92,7 @@ Boston, MA 02111-1307, USA. */ %{mbig-endian:-EB}" \ SUBTARGET_EXTRA_LINK_SPEC -#define TARGET_OS_CPP_BUILTINS() \ - do { \ - builtin_define_std ("unix"); \ - builtin_define_std ("linux"); \ - builtin_define ("__gnu_linux__"); \ - builtin_define ("__ELF__"); \ - builtin_assert ("system=unix"); \ - builtin_assert ("system=posix"); \ - } while (0) +#define TARGET_OS_CPP_BUILTINS() LINUX_TARGET_OS_CPP_BUILTINS() /* This is how we tell the assembler that two symbols have the same value. */ #define ASM_OUTPUT_DEF(FILE, NAME1, NAME2) \ @@ -111,8 +106,8 @@ Boston, MA 02111-1307, USA. */ while (0) /* NWFPE always understands FPA instructions. */ -#undef FP_DEFAULT -#define FP_DEFAULT FP_SOFT3 +#undef FPUTYPE_DEFAULT +#define FPUTYPE_DEFAULT FPUTYPE_FPA_EMU3 /* Call the function profiler with a given profile label. */ #undef ARM_FUNCTION_PROFILER @@ -121,6 +116,11 @@ Boston, MA 02111-1307, USA. */ fprintf (STREAM, "\tbl\tmcount%s\n", NEED_PLT_RELOC ? "(PLT)" : ""); \ } +/* The linux profiler clobbers the link register. Make sure the + prologue knows to save it. */ +#define PROFILE_HOOK(X) \ + emit_insn (gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, LR_REGNUM))) + #undef CC1_SPEC #define CC1_SPEC "%{profile:-p}" diff --git a/contrib/gcc/config/arm/linux-gas.h b/contrib/gcc/config/arm/linux-gas.h index 5e8ddf9..6911284 100644 --- a/contrib/gcc/config/arm/linux-gas.h +++ b/contrib/gcc/config/arm/linux-gas.h @@ -3,35 +3,31 @@ Copyright (C) 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. Contributed by Russell King <rmk92@ecs.soton.ac.uk>. -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with this program; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ /* This is how we tell the assembler that a symbol is weak. GAS always supports weak symbols. */ -/* This is used in ASM_FILE_START. */ -#undef ARM_OS_NAME -#define ARM_OS_NAME "Linux" - /* Unsigned chars produces much better code than signed. */ #define DEFAULT_SIGNED_CHAR 0 #undef SUBTARGET_CPP_SPEC -#define SUBTARGET_CPP_SPEC "%{posix:-D_POSIX_SOURCE} %{fPIC:-D__PIC__ -D__pic__} %{fpic:-D__PIC__ -D__pic__}" +#define SUBTARGET_CPP_SPEC "%{posix:-D_POSIX_SOURCE} %{fPIC|fPIE:-D__PIC__ -D__pic__} %{fpic|fpie:-D__PIC__ -D__pic__}" #undef SIZE_TYPE #define SIZE_TYPE "unsigned int" diff --git a/contrib/gcc/config/arm/mmintrin.h b/contrib/gcc/config/arm/mmintrin.h new file mode 100644 index 0000000..4dc1d45 --- /dev/null +++ b/contrib/gcc/config/arm/mmintrin.h @@ -0,0 +1,1257 @@ +/* Copyright (C) 2002, 2003 Free Software Foundation, Inc. + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to the Free + Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +/* As a special exception, if you include this header file into source + files compiled by GCC, this header file does not by itself cause + the resulting executable to be covered by the GNU General Public + License. This exception does not however invalidate any other + reasons why the executable file might be covered by the GNU General + Public License. */ + +#ifndef _MMINTRIN_H_INCLUDED +#define _MMINTRIN_H_INCLUDED + +/* The data type intended for user use. */ +typedef unsigned long long __m64, __int64; + +/* Internal data types for implementing the intrinsics. */ +typedef int __v2si __attribute__ ((__mode__ (__V2SI__))); +typedef int __v4hi __attribute__ ((__mode__ (__V4HI__))); +typedef int __v8qi __attribute__ ((__mode__ (__V8QI__))); + +/* "Convert" __m64 and __int64 into each other. */ +static __inline __m64 +_mm_cvtsi64_m64 (__int64 __i) +{ + return __i; +} + +static __inline __int64 +_mm_cvtm64_si64 (__m64 __i) +{ + return __i; +} + +static __inline int +_mm_cvtsi64_si32 (__int64 __i) +{ + return __i; +} + +static __inline __int64 +_mm_cvtsi32_si64 (int __i) +{ + return __i; +} + +/* Pack the four 16-bit values from M1 into the lower four 8-bit values of + the result, and the four 16-bit values from M2 into the upper four 8-bit + values of the result, all with signed saturation. */ +static __inline __m64 +_mm_packs_pi16 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wpackhss ((__v4hi)__m1, (__v4hi)__m2); +} + +/* Pack the two 32-bit values from M1 in to the lower two 16-bit values of + the result, and the two 32-bit values from M2 into the upper two 16-bit + values of the result, all with signed saturation. */ +static __inline __m64 +_mm_packs_pi32 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wpackwss ((__v2si)__m1, (__v2si)__m2); +} + +/* Copy the 64-bit value from M1 into the lower 32-bits of the result, and + the 64-bit value from M2 into the upper 32-bits of the result, all with + signed saturation for values that do not fit exactly into 32-bits. */ +static __inline __m64 +_mm_packs_pi64 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wpackdss ((long long)__m1, (long long)__m2); +} + +/* Pack the four 16-bit values from M1 into the lower four 8-bit values of + the result, and the four 16-bit values from M2 into the upper four 8-bit + values of the result, all with unsigned saturation. */ +static __inline __m64 +_mm_packs_pu16 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wpackhus ((__v4hi)__m1, (__v4hi)__m2); +} + +/* Pack the two 32-bit values from M1 into the lower two 16-bit values of + the result, and the two 32-bit values from M2 into the upper two 16-bit + values of the result, all with unsigned saturation. */ +static __inline __m64 +_mm_packs_pu32 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wpackwus ((__v2si)__m1, (__v2si)__m2); +} + +/* Copy the 64-bit value from M1 into the lower 32-bits of the result, and + the 64-bit value from M2 into the upper 32-bits of the result, all with + unsigned saturation for values that do not fit exactly into 32-bits. */ +static __inline __m64 +_mm_packs_pu64 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wpackdus ((long long)__m1, (long long)__m2); +} + +/* Interleave the four 8-bit values from the high half of M1 with the four + 8-bit values from the high half of M2. */ +static __inline __m64 +_mm_unpackhi_pi8 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wunpckihb ((__v8qi)__m1, (__v8qi)__m2); +} + +/* Interleave the two 16-bit values from the high half of M1 with the two + 16-bit values from the high half of M2. */ +static __inline __m64 +_mm_unpackhi_pi16 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wunpckihh ((__v4hi)__m1, (__v4hi)__m2); +} + +/* Interleave the 32-bit value from the high half of M1 with the 32-bit + value from the high half of M2. */ +static __inline __m64 +_mm_unpackhi_pi32 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wunpckihw ((__v2si)__m1, (__v2si)__m2); +} + +/* Interleave the four 8-bit values from the low half of M1 with the four + 8-bit values from the low half of M2. */ +static __inline __m64 +_mm_unpacklo_pi8 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wunpckilb ((__v8qi)__m1, (__v8qi)__m2); +} + +/* Interleave the two 16-bit values from the low half of M1 with the two + 16-bit values from the low half of M2. */ +static __inline __m64 +_mm_unpacklo_pi16 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wunpckilh ((__v4hi)__m1, (__v4hi)__m2); +} + +/* Interleave the 32-bit value from the low half of M1 with the 32-bit + value from the low half of M2. */ +static __inline __m64 +_mm_unpacklo_pi32 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wunpckilw ((__v2si)__m1, (__v2si)__m2); +} + +/* Take the four 8-bit values from the low half of M1, sign extend them, + and return the result as a vector of four 16-bit quantities. */ +static __inline __m64 +_mm_unpackel_pi8 (__m64 __m1) +{ + return (__m64) __builtin_arm_wunpckelsb ((__v8qi)__m1); +} + +/* Take the two 16-bit values from the low half of M1, sign extend them, + and return the result as a vector of two 32-bit quantities. */ +static __inline __m64 +_mm_unpackel_pi16 (__m64 __m1) +{ + return (__m64) __builtin_arm_wunpckelsh ((__v4hi)__m1); +} + +/* Take the 32-bit value from the low half of M1, and return it sign extended + to 64 bits. */ +static __inline __m64 +_mm_unpackel_pi32 (__m64 __m1) +{ + return (__m64) __builtin_arm_wunpckelsw ((__v2si)__m1); +} + +/* Take the four 8-bit values from the high half of M1, sign extend them, + and return the result as a vector of four 16-bit quantities. */ +static __inline __m64 +_mm_unpackeh_pi8 (__m64 __m1) +{ + return (__m64) __builtin_arm_wunpckehsb ((__v8qi)__m1); +} + +/* Take the two 16-bit values from the high half of M1, sign extend them, + and return the result as a vector of two 32-bit quantities. */ +static __inline __m64 +_mm_unpackeh_pi16 (__m64 __m1) +{ + return (__m64) __builtin_arm_wunpckehsh ((__v4hi)__m1); +} + +/* Take the 32-bit value from the high half of M1, and return it sign extended + to 64 bits. */ +static __inline __m64 +_mm_unpackeh_pi32 (__m64 __m1) +{ + return (__m64) __builtin_arm_wunpckehsw ((__v2si)__m1); +} + +/* Take the four 8-bit values from the low half of M1, zero extend them, + and return the result as a vector of four 16-bit quantities. */ +static __inline __m64 +_mm_unpackel_pu8 (__m64 __m1) +{ + return (__m64) __builtin_arm_wunpckelub ((__v8qi)__m1); +} + +/* Take the two 16-bit values from the low half of M1, zero extend them, + and return the result as a vector of two 32-bit quantities. */ +static __inline __m64 +_mm_unpackel_pu16 (__m64 __m1) +{ + return (__m64) __builtin_arm_wunpckeluh ((__v4hi)__m1); +} + +/* Take the 32-bit value from the low half of M1, and return it zero extended + to 64 bits. */ +static __inline __m64 +_mm_unpackel_pu32 (__m64 __m1) +{ + return (__m64) __builtin_arm_wunpckeluw ((__v2si)__m1); +} + +/* Take the four 8-bit values from the high half of M1, zero extend them, + and return the result as a vector of four 16-bit quantities. */ +static __inline __m64 +_mm_unpackeh_pu8 (__m64 __m1) +{ + return (__m64) __builtin_arm_wunpckehub ((__v8qi)__m1); +} + +/* Take the two 16-bit values from the high half of M1, zero extend them, + and return the result as a vector of two 32-bit quantities. */ +static __inline __m64 +_mm_unpackeh_pu16 (__m64 __m1) +{ + return (__m64) __builtin_arm_wunpckehuh ((__v4hi)__m1); +} + +/* Take the 32-bit value from the high half of M1, and return it zero extended + to 64 bits. */ +static __inline __m64 +_mm_unpackeh_pu32 (__m64 __m1) +{ + return (__m64) __builtin_arm_wunpckehuw ((__v2si)__m1); +} + +/* Add the 8-bit values in M1 to the 8-bit values in M2. */ +static __inline __m64 +_mm_add_pi8 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_waddb ((__v8qi)__m1, (__v8qi)__m2); +} + +/* Add the 16-bit values in M1 to the 16-bit values in M2. */ +static __inline __m64 +_mm_add_pi16 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_waddh ((__v4hi)__m1, (__v4hi)__m2); +} + +/* Add the 32-bit values in M1 to the 32-bit values in M2. */ +static __inline __m64 +_mm_add_pi32 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_waddw ((__v2si)__m1, (__v2si)__m2); +} + +/* Add the 8-bit values in M1 to the 8-bit values in M2 using signed + saturated arithmetic. */ +static __inline __m64 +_mm_adds_pi8 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_waddbss ((__v8qi)__m1, (__v8qi)__m2); +} + +/* Add the 16-bit values in M1 to the 16-bit values in M2 using signed + saturated arithmetic. */ +static __inline __m64 +_mm_adds_pi16 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_waddhss ((__v4hi)__m1, (__v4hi)__m2); +} + +/* Add the 32-bit values in M1 to the 32-bit values in M2 using signed + saturated arithmetic. */ +static __inline __m64 +_mm_adds_pi32 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_waddwss ((__v2si)__m1, (__v2si)__m2); +} + +/* Add the 8-bit values in M1 to the 8-bit values in M2 using unsigned + saturated arithmetic. */ +static __inline __m64 +_mm_adds_pu8 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_waddbus ((__v8qi)__m1, (__v8qi)__m2); +} + +/* Add the 16-bit values in M1 to the 16-bit values in M2 using unsigned + saturated arithmetic. */ +static __inline __m64 +_mm_adds_pu16 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_waddhus ((__v4hi)__m1, (__v4hi)__m2); +} + +/* Add the 32-bit values in M1 to the 32-bit values in M2 using unsigned + saturated arithmetic. */ +static __inline __m64 +_mm_adds_pu32 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_waddwus ((__v2si)__m1, (__v2si)__m2); +} + +/* Subtract the 8-bit values in M2 from the 8-bit values in M1. */ +static __inline __m64 +_mm_sub_pi8 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wsubb ((__v8qi)__m1, (__v8qi)__m2); +} + +/* Subtract the 16-bit values in M2 from the 16-bit values in M1. */ +static __inline __m64 +_mm_sub_pi16 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wsubh ((__v4hi)__m1, (__v4hi)__m2); +} + +/* Subtract the 32-bit values in M2 from the 32-bit values in M1. */ +static __inline __m64 +_mm_sub_pi32 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wsubw ((__v2si)__m1, (__v2si)__m2); +} + +/* Subtract the 8-bit values in M2 from the 8-bit values in M1 using signed + saturating arithmetic. */ +static __inline __m64 +_mm_subs_pi8 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wsubbss ((__v8qi)__m1, (__v8qi)__m2); +} + +/* Subtract the 16-bit values in M2 from the 16-bit values in M1 using + signed saturating arithmetic. */ +static __inline __m64 +_mm_subs_pi16 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wsubhss ((__v4hi)__m1, (__v4hi)__m2); +} + +/* Subtract the 32-bit values in M2 from the 32-bit values in M1 using + signed saturating arithmetic. */ +static __inline __m64 +_mm_subs_pi32 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wsubwss ((__v2si)__m1, (__v2si)__m2); +} + +/* Subtract the 8-bit values in M2 from the 8-bit values in M1 using + unsigned saturating arithmetic. */ +static __inline __m64 +_mm_subs_pu8 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wsubbus ((__v8qi)__m1, (__v8qi)__m2); +} + +/* Subtract the 16-bit values in M2 from the 16-bit values in M1 using + unsigned saturating arithmetic. */ +static __inline __m64 +_mm_subs_pu16 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wsubhus ((__v4hi)__m1, (__v4hi)__m2); +} + +/* Subtract the 32-bit values in M2 from the 32-bit values in M1 using + unsigned saturating arithmetic. */ +static __inline __m64 +_mm_subs_pu32 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wsubwus ((__v2si)__m1, (__v2si)__m2); +} + +/* Multiply four 16-bit values in M1 by four 16-bit values in M2 producing + four 32-bit intermediate results, which are then summed by pairs to + produce two 32-bit results. */ +static __inline __m64 +_mm_madd_pi16 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wmadds ((__v4hi)__m1, (__v4hi)__m2); +} + +/* Multiply four 16-bit values in M1 by four 16-bit values in M2 producing + four 32-bit intermediate results, which are then summed by pairs to + produce two 32-bit results. */ +static __inline __m64 +_mm_madd_pu16 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wmaddu ((__v4hi)__m1, (__v4hi)__m2); +} + +/* Multiply four signed 16-bit values in M1 by four signed 16-bit values in + M2 and produce the high 16 bits of the 32-bit results. */ +static __inline __m64 +_mm_mulhi_pi16 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wmulsh ((__v4hi)__m1, (__v4hi)__m2); +} + +/* Multiply four signed 16-bit values in M1 by four signed 16-bit values in + M2 and produce the high 16 bits of the 32-bit results. */ +static __inline __m64 +_mm_mulhi_pu16 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wmuluh ((__v4hi)__m1, (__v4hi)__m2); +} + +/* Multiply four 16-bit values in M1 by four 16-bit values in M2 and produce + the low 16 bits of the results. */ +static __inline __m64 +_mm_mullo_pi16 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wmulul ((__v4hi)__m1, (__v4hi)__m2); +} + +/* Shift four 16-bit values in M left by COUNT. */ +static __inline __m64 +_mm_sll_pi16 (__m64 __m, __m64 __count) +{ + return (__m64) __builtin_arm_wsllh ((__v4hi)__m, __count); +} + +static __inline __m64 +_mm_slli_pi16 (__m64 __m, int __count) +{ + return (__m64) __builtin_arm_wsllhi ((__v4hi)__m, __count); +} + +/* Shift two 32-bit values in M left by COUNT. */ +static __inline __m64 +_mm_sll_pi32 (__m64 __m, __m64 __count) +{ + return (__m64) __builtin_arm_wsllw ((__v2si)__m, __count); +} + +static __inline __m64 +_mm_slli_pi32 (__m64 __m, int __count) +{ + return (__m64) __builtin_arm_wsllwi ((__v2si)__m, __count); +} + +/* Shift the 64-bit value in M left by COUNT. */ +static __inline __m64 +_mm_sll_si64 (__m64 __m, __m64 __count) +{ + return (__m64) __builtin_arm_wslld (__m, __count); +} + +static __inline __m64 +_mm_slli_si64 (__m64 __m, int __count) +{ + return (__m64) __builtin_arm_wslldi (__m, __count); +} + +/* Shift four 16-bit values in M right by COUNT; shift in the sign bit. */ +static __inline __m64 +_mm_sra_pi16 (__m64 __m, __m64 __count) +{ + return (__m64) __builtin_arm_wsrah ((__v4hi)__m, __count); +} + +static __inline __m64 +_mm_srai_pi16 (__m64 __m, int __count) +{ + return (__m64) __builtin_arm_wsrahi ((__v4hi)__m, __count); +} + +/* Shift two 32-bit values in M right by COUNT; shift in the sign bit. */ +static __inline __m64 +_mm_sra_pi32 (__m64 __m, __m64 __count) +{ + return (__m64) __builtin_arm_wsraw ((__v2si)__m, __count); +} + +static __inline __m64 +_mm_srai_pi32 (__m64 __m, int __count) +{ + return (__m64) __builtin_arm_wsrawi ((__v2si)__m, __count); +} + +/* Shift the 64-bit value in M right by COUNT; shift in the sign bit. */ +static __inline __m64 +_mm_sra_si64 (__m64 __m, __m64 __count) +{ + return (__m64) __builtin_arm_wsrad (__m, __count); +} + +static __inline __m64 +_mm_srai_si64 (__m64 __m, int __count) +{ + return (__m64) __builtin_arm_wsradi (__m, __count); +} + +/* Shift four 16-bit values in M right by COUNT; shift in zeros. */ +static __inline __m64 +_mm_srl_pi16 (__m64 __m, __m64 __count) +{ + return (__m64) __builtin_arm_wsrlh ((__v4hi)__m, __count); +} + +static __inline __m64 +_mm_srli_pi16 (__m64 __m, int __count) +{ + return (__m64) __builtin_arm_wsrlhi ((__v4hi)__m, __count); +} + +/* Shift two 32-bit values in M right by COUNT; shift in zeros. */ +static __inline __m64 +_mm_srl_pi32 (__m64 __m, __m64 __count) +{ + return (__m64) __builtin_arm_wsrlw ((__v2si)__m, __count); +} + +static __inline __m64 +_mm_srli_pi32 (__m64 __m, int __count) +{ + return (__m64) __builtin_arm_wsrlwi ((__v2si)__m, __count); +} + +/* Shift the 64-bit value in M left by COUNT; shift in zeros. */ +static __inline __m64 +_mm_srl_si64 (__m64 __m, __m64 __count) +{ + return (__m64) __builtin_arm_wsrld (__m, __count); +} + +static __inline __m64 +_mm_srli_si64 (__m64 __m, int __count) +{ + return (__m64) __builtin_arm_wsrldi (__m, __count); +} + +/* Rotate four 16-bit values in M right by COUNT. */ +static __inline __m64 +_mm_ror_pi16 (__m64 __m, __m64 __count) +{ + return (__m64) __builtin_arm_wrorh ((__v4hi)__m, __count); +} + +static __inline __m64 +_mm_rori_pi16 (__m64 __m, int __count) +{ + return (__m64) __builtin_arm_wrorhi ((__v4hi)__m, __count); +} + +/* Rotate two 32-bit values in M right by COUNT. */ +static __inline __m64 +_mm_ror_pi32 (__m64 __m, __m64 __count) +{ + return (__m64) __builtin_arm_wrorw ((__v2si)__m, __count); +} + +static __inline __m64 +_mm_rori_pi32 (__m64 __m, int __count) +{ + return (__m64) __builtin_arm_wrorwi ((__v2si)__m, __count); +} + +/* Rotate two 64-bit values in M right by COUNT. */ +static __inline __m64 +_mm_ror_si64 (__m64 __m, __m64 __count) +{ + return (__m64) __builtin_arm_wrord (__m, __count); +} + +static __inline __m64 +_mm_rori_si64 (__m64 __m, int __count) +{ + return (__m64) __builtin_arm_wrordi (__m, __count); +} + +/* Bit-wise AND the 64-bit values in M1 and M2. */ +static __inline __m64 +_mm_and_si64 (__m64 __m1, __m64 __m2) +{ + return __builtin_arm_wand (__m1, __m2); +} + +/* Bit-wise complement the 64-bit value in M1 and bit-wise AND it with the + 64-bit value in M2. */ +static __inline __m64 +_mm_andnot_si64 (__m64 __m1, __m64 __m2) +{ + return __builtin_arm_wandn (__m1, __m2); +} + +/* Bit-wise inclusive OR the 64-bit values in M1 and M2. */ +static __inline __m64 +_mm_or_si64 (__m64 __m1, __m64 __m2) +{ + return __builtin_arm_wor (__m1, __m2); +} + +/* Bit-wise exclusive OR the 64-bit values in M1 and M2. */ +static __inline __m64 +_mm_xor_si64 (__m64 __m1, __m64 __m2) +{ + return __builtin_arm_wxor (__m1, __m2); +} + +/* Compare eight 8-bit values. The result of the comparison is 0xFF if the + test is true and zero if false. */ +static __inline __m64 +_mm_cmpeq_pi8 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wcmpeqb ((__v8qi)__m1, (__v8qi)__m2); +} + +static __inline __m64 +_mm_cmpgt_pi8 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wcmpgtsb ((__v8qi)__m1, (__v8qi)__m2); +} + +static __inline __m64 +_mm_cmpgt_pu8 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wcmpgtub ((__v8qi)__m1, (__v8qi)__m2); +} + +/* Compare four 16-bit values. The result of the comparison is 0xFFFF if + the test is true and zero if false. */ +static __inline __m64 +_mm_cmpeq_pi16 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wcmpeqh ((__v4hi)__m1, (__v4hi)__m2); +} + +static __inline __m64 +_mm_cmpgt_pi16 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wcmpgtsh ((__v4hi)__m1, (__v4hi)__m2); +} + +static __inline __m64 +_mm_cmpgt_pu16 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wcmpgtuh ((__v4hi)__m1, (__v4hi)__m2); +} + +/* Compare two 32-bit values. The result of the comparison is 0xFFFFFFFF if + the test is true and zero if false. */ +static __inline __m64 +_mm_cmpeq_pi32 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wcmpeqw ((__v2si)__m1, (__v2si)__m2); +} + +static __inline __m64 +_mm_cmpgt_pi32 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wcmpgtsw ((__v2si)__m1, (__v2si)__m2); +} + +static __inline __m64 +_mm_cmpgt_pu32 (__m64 __m1, __m64 __m2) +{ + return (__m64) __builtin_arm_wcmpgtuw ((__v2si)__m1, (__v2si)__m2); +} + +/* Element-wise multiplication of unsigned 16-bit values __B and __C, followed + by accumulate across all elements and __A. */ +static __inline __m64 +_mm_mac_pu16 (__m64 __A, __m64 __B, __m64 __C) +{ + return __builtin_arm_wmacu (__A, (__v4hi)__B, (__v4hi)__C); +} + +/* Element-wise multiplication of signed 16-bit values __B and __C, followed + by accumulate across all elements and __A. */ +static __inline __m64 +_mm_mac_pi16 (__m64 __A, __m64 __B, __m64 __C) +{ + return __builtin_arm_wmacs (__A, (__v4hi)__B, (__v4hi)__C); +} + +/* Element-wise multiplication of unsigned 16-bit values __B and __C, followed + by accumulate across all elements. */ +static __inline __m64 +_mm_macz_pu16 (__m64 __A, __m64 __B) +{ + return __builtin_arm_wmacuz ((__v4hi)__A, (__v4hi)__B); +} + +/* Element-wise multiplication of signed 16-bit values __B and __C, followed + by accumulate across all elements. */ +static __inline __m64 +_mm_macz_pi16 (__m64 __A, __m64 __B) +{ + return __builtin_arm_wmacsz ((__v4hi)__A, (__v4hi)__B); +} + +/* Accumulate across all unsigned 8-bit values in __A. */ +static __inline __m64 +_mm_acc_pu8 (__m64 __A) +{ + return __builtin_arm_waccb ((__v8qi)__A); +} + +/* Accumulate across all unsigned 16-bit values in __A. */ +static __inline __m64 +_mm_acc_pu16 (__m64 __A) +{ + return __builtin_arm_wacch ((__v4hi)__A); +} + +/* Accumulate across all unsigned 32-bit values in __A. */ +static __inline __m64 +_mm_acc_pu32 (__m64 __A) +{ + return __builtin_arm_waccw ((__v2si)__A); +} + +static __inline __m64 +_mm_mia_si64 (__m64 __A, int __B, int __C) +{ + return __builtin_arm_tmia (__A, __B, __C); +} + +static __inline __m64 +_mm_miaph_si64 (__m64 __A, int __B, int __C) +{ + return __builtin_arm_tmiaph (__A, __B, __C); +} + +static __inline __m64 +_mm_miabb_si64 (__m64 __A, int __B, int __C) +{ + return __builtin_arm_tmiabb (__A, __B, __C); +} + +static __inline __m64 +_mm_miabt_si64 (__m64 __A, int __B, int __C) +{ + return __builtin_arm_tmiabt (__A, __B, __C); +} + +static __inline __m64 +_mm_miatb_si64 (__m64 __A, int __B, int __C) +{ + return __builtin_arm_tmiatb (__A, __B, __C); +} + +static __inline __m64 +_mm_miatt_si64 (__m64 __A, int __B, int __C) +{ + return __builtin_arm_tmiatt (__A, __B, __C); +} + +/* Extract one of the elements of A and sign extend. The selector N must + be immediate. */ +#define _mm_extract_pi8(A, N) __builtin_arm_textrmsb ((__v8qi)(A), (N)) +#define _mm_extract_pi16(A, N) __builtin_arm_textrmsh ((__v4hi)(A), (N)) +#define _mm_extract_pi32(A, N) __builtin_arm_textrmsw ((__v2si)(A), (N)) + +/* Extract one of the elements of A and zero extend. The selector N must + be immediate. */ +#define _mm_extract_pu8(A, N) __builtin_arm_textrmub ((__v8qi)(A), (N)) +#define _mm_extract_pu16(A, N) __builtin_arm_textrmuh ((__v4hi)(A), (N)) +#define _mm_extract_pu32(A, N) __builtin_arm_textrmuw ((__v2si)(A), (N)) + +/* Inserts word D into one of the elements of A. The selector N must be + immediate. */ +#define _mm_insert_pi8(A, D, N) \ + ((__m64) __builtin_arm_tinsrb ((__v8qi)(A), (D), (N))) +#define _mm_insert_pi16(A, D, N) \ + ((__m64) __builtin_arm_tinsrh ((__v4hi)(A), (D), (N))) +#define _mm_insert_pi32(A, D, N) \ + ((__m64) __builtin_arm_tinsrw ((__v2si)(A), (D), (N))) + +/* Compute the element-wise maximum of signed 8-bit values. */ +static __inline __m64 +_mm_max_pi8 (__m64 __A, __m64 __B) +{ + return (__m64) __builtin_arm_wmaxsb ((__v8qi)__A, (__v8qi)__B); +} + +/* Compute the element-wise maximum of signed 16-bit values. */ +static __inline __m64 +_mm_max_pi16 (__m64 __A, __m64 __B) +{ + return (__m64) __builtin_arm_wmaxsh ((__v4hi)__A, (__v4hi)__B); +} + +/* Compute the element-wise maximum of signed 32-bit values. */ +static __inline __m64 +_mm_max_pi32 (__m64 __A, __m64 __B) +{ + return (__m64) __builtin_arm_wmaxsw ((__v2si)__A, (__v2si)__B); +} + +/* Compute the element-wise maximum of unsigned 8-bit values. */ +static __inline __m64 +_mm_max_pu8 (__m64 __A, __m64 __B) +{ + return (__m64) __builtin_arm_wmaxub ((__v8qi)__A, (__v8qi)__B); +} + +/* Compute the element-wise maximum of unsigned 16-bit values. */ +static __inline __m64 +_mm_max_pu16 (__m64 __A, __m64 __B) +{ + return (__m64) __builtin_arm_wmaxuh ((__v4hi)__A, (__v4hi)__B); +} + +/* Compute the element-wise maximum of unsigned 32-bit values. */ +static __inline __m64 +_mm_max_pu32 (__m64 __A, __m64 __B) +{ + return (__m64) __builtin_arm_wmaxuw ((__v2si)__A, (__v2si)__B); +} + +/* Compute the element-wise minimum of signed 16-bit values. */ +static __inline __m64 +_mm_min_pi8 (__m64 __A, __m64 __B) +{ + return (__m64) __builtin_arm_wminsb ((__v8qi)__A, (__v8qi)__B); +} + +/* Compute the element-wise minimum of signed 16-bit values. */ +static __inline __m64 +_mm_min_pi16 (__m64 __A, __m64 __B) +{ + return (__m64) __builtin_arm_wminsh ((__v4hi)__A, (__v4hi)__B); +} + +/* Compute the element-wise minimum of signed 32-bit values. */ +static __inline __m64 +_mm_min_pi32 (__m64 __A, __m64 __B) +{ + return (__m64) __builtin_arm_wminsw ((__v2si)__A, (__v2si)__B); +} + +/* Compute the element-wise minimum of unsigned 16-bit values. */ +static __inline __m64 +_mm_min_pu8 (__m64 __A, __m64 __B) +{ + return (__m64) __builtin_arm_wminub ((__v8qi)__A, (__v8qi)__B); +} + +/* Compute the element-wise minimum of unsigned 16-bit values. */ +static __inline __m64 +_mm_min_pu16 (__m64 __A, __m64 __B) +{ + return (__m64) __builtin_arm_wminuh ((__v4hi)__A, (__v4hi)__B); +} + +/* Compute the element-wise minimum of unsigned 32-bit values. */ +static __inline __m64 +_mm_min_pu32 (__m64 __A, __m64 __B) +{ + return (__m64) __builtin_arm_wminuw ((__v2si)__A, (__v2si)__B); +} + +/* Create an 8-bit mask of the signs of 8-bit values. */ +static __inline int +_mm_movemask_pi8 (__m64 __A) +{ + return __builtin_arm_tmovmskb ((__v8qi)__A); +} + +/* Create an 8-bit mask of the signs of 16-bit values. */ +static __inline int +_mm_movemask_pi16 (__m64 __A) +{ + return __builtin_arm_tmovmskh ((__v4hi)__A); +} + +/* Create an 8-bit mask of the signs of 32-bit values. */ +static __inline int +_mm_movemask_pi32 (__m64 __A) +{ + return __builtin_arm_tmovmskw ((__v2si)__A); +} + +/* Return a combination of the four 16-bit values in A. The selector + must be an immediate. */ +#define _mm_shuffle_pi16(A, N) \ + ((__m64) __builtin_arm_wshufh ((__v4hi)(A), (N))) + + +/* Compute the rounded averages of the unsigned 8-bit values in A and B. */ +static __inline __m64 +_mm_avg_pu8 (__m64 __A, __m64 __B) +{ + return (__m64) __builtin_arm_wavg2br ((__v8qi)__A, (__v8qi)__B); +} + +/* Compute the rounded averages of the unsigned 16-bit values in A and B. */ +static __inline __m64 +_mm_avg_pu16 (__m64 __A, __m64 __B) +{ + return (__m64) __builtin_arm_wavg2hr ((__v4hi)__A, (__v4hi)__B); +} + +/* Compute the averages of the unsigned 8-bit values in A and B. */ +static __inline __m64 +_mm_avg2_pu8 (__m64 __A, __m64 __B) +{ + return (__m64) __builtin_arm_wavg2b ((__v8qi)__A, (__v8qi)__B); +} + +/* Compute the averages of the unsigned 16-bit values in A and B. */ +static __inline __m64 +_mm_avg2_pu16 (__m64 __A, __m64 __B) +{ + return (__m64) __builtin_arm_wavg2h ((__v4hi)__A, (__v4hi)__B); +} + +/* Compute the sum of the absolute differences of the unsigned 8-bit + values in A and B. Return the value in the lower 16-bit word; the + upper words are cleared. */ +static __inline __m64 +_mm_sad_pu8 (__m64 __A, __m64 __B) +{ + return (__m64) __builtin_arm_wsadb ((__v8qi)__A, (__v8qi)__B); +} + +/* Compute the sum of the absolute differences of the unsigned 16-bit + values in A and B. Return the value in the lower 32-bit word; the + upper words are cleared. */ +static __inline __m64 +_mm_sad_pu16 (__m64 __A, __m64 __B) +{ + return (__m64) __builtin_arm_wsadh ((__v4hi)__A, (__v4hi)__B); +} + +/* Compute the sum of the absolute differences of the unsigned 8-bit + values in A and B. Return the value in the lower 16-bit word; the + upper words are cleared. */ +static __inline __m64 +_mm_sadz_pu8 (__m64 __A, __m64 __B) +{ + return (__m64) __builtin_arm_wsadbz ((__v8qi)__A, (__v8qi)__B); +} + +/* Compute the sum of the absolute differences of the unsigned 16-bit + values in A and B. Return the value in the lower 32-bit word; the + upper words are cleared. */ +static __inline __m64 +_mm_sadz_pu16 (__m64 __A, __m64 __B) +{ + return (__m64) __builtin_arm_wsadhz ((__v4hi)__A, (__v4hi)__B); +} + +static __inline __m64 +_mm_align_si64 (__m64 __A, __m64 __B, int __C) +{ + return (__m64) __builtin_arm_walign ((__v8qi)__A, (__v8qi)__B, __C); +} + +/* Creates a 64-bit zero. */ +static __inline __m64 +_mm_setzero_si64 (void) +{ + return __builtin_arm_wzero (); +} + +/* Set and Get arbitrary iWMMXt Control registers. + Note only registers 0-3 and 8-11 are currently defined, + the rest are reserved. */ + +static __inline void +_mm_setwcx (const int __regno, const int __value) +{ + switch (__regno) + { + case 0: __builtin_arm_setwcx (0, __value); break; + case 1: __builtin_arm_setwcx (1, __value); break; + case 2: __builtin_arm_setwcx (2, __value); break; + case 3: __builtin_arm_setwcx (3, __value); break; + case 8: __builtin_arm_setwcx (8, __value); break; + case 9: __builtin_arm_setwcx (9, __value); break; + case 10: __builtin_arm_setwcx (10, __value); break; + case 11: __builtin_arm_setwcx (11, __value); break; + default: break; + } +} + +static __inline int +_mm_getwcx (const int __regno) +{ + switch (__regno) + { + case 0: return __builtin_arm_getwcx (0); + case 1: return __builtin_arm_getwcx (1); + case 2: return __builtin_arm_getwcx (2); + case 3: return __builtin_arm_getwcx (3); + case 8: return __builtin_arm_getwcx (8); + case 9: return __builtin_arm_getwcx (9); + case 10: return __builtin_arm_getwcx (10); + case 11: return __builtin_arm_getwcx (11); + default: return 0; + } +} + +/* Creates a vector of two 32-bit values; I0 is least significant. */ +static __inline __m64 +_mm_set_pi32 (int __i1, int __i0) +{ + union { + __m64 __q; + struct { + unsigned int __i0; + unsigned int __i1; + } __s; + } __u; + + __u.__s.__i0 = __i0; + __u.__s.__i1 = __i1; + + return __u.__q; +} + +/* Creates a vector of four 16-bit values; W0 is least significant. */ +static __inline __m64 +_mm_set_pi16 (short __w3, short __w2, short __w1, short __w0) +{ + unsigned int __i1 = (unsigned short)__w3 << 16 | (unsigned short)__w2; + unsigned int __i0 = (unsigned short)__w1 << 16 | (unsigned short)__w0; + return _mm_set_pi32 (__i1, __i0); + +} + +/* Creates a vector of eight 8-bit values; B0 is least significant. */ +static __inline __m64 +_mm_set_pi8 (char __b7, char __b6, char __b5, char __b4, + char __b3, char __b2, char __b1, char __b0) +{ + unsigned int __i1, __i0; + + __i1 = (unsigned char)__b7; + __i1 = __i1 << 8 | (unsigned char)__b6; + __i1 = __i1 << 8 | (unsigned char)__b5; + __i1 = __i1 << 8 | (unsigned char)__b4; + + __i0 = (unsigned char)__b3; + __i0 = __i0 << 8 | (unsigned char)__b2; + __i0 = __i0 << 8 | (unsigned char)__b1; + __i0 = __i0 << 8 | (unsigned char)__b0; + + return _mm_set_pi32 (__i1, __i0); +} + +/* Similar, but with the arguments in reverse order. */ +static __inline __m64 +_mm_setr_pi32 (int __i0, int __i1) +{ + return _mm_set_pi32 (__i1, __i0); +} + +static __inline __m64 +_mm_setr_pi16 (short __w0, short __w1, short __w2, short __w3) +{ + return _mm_set_pi16 (__w3, __w2, __w1, __w0); +} + +static __inline __m64 +_mm_setr_pi8 (char __b0, char __b1, char __b2, char __b3, + char __b4, char __b5, char __b6, char __b7) +{ + return _mm_set_pi8 (__b7, __b6, __b5, __b4, __b3, __b2, __b1, __b0); +} + +/* Creates a vector of two 32-bit values, both elements containing I. */ +static __inline __m64 +_mm_set1_pi32 (int __i) +{ + return _mm_set_pi32 (__i, __i); +} + +/* Creates a vector of four 16-bit values, all elements containing W. */ +static __inline __m64 +_mm_set1_pi16 (short __w) +{ + unsigned int __i = (unsigned short)__w << 16 | (unsigned short)__w; + return _mm_set1_pi32 (__i); +} + +/* Creates a vector of four 16-bit values, all elements containing B. */ +static __inline __m64 +_mm_set1_pi8 (char __b) +{ + unsigned int __w = (unsigned char)__b << 8 | (unsigned char)__b; + unsigned int __i = __w << 16 | __w; + return _mm_set1_pi32 (__i); +} + +/* Convert an integer to a __m64 object. */ +static __inline __m64 +_m_from_int (int __a) +{ + return (__m64)__a; +} + +#define _m_packsswb _mm_packs_pi16 +#define _m_packssdw _mm_packs_pi32 +#define _m_packuswb _mm_packs_pu16 +#define _m_packusdw _mm_packs_pu32 +#define _m_packssqd _mm_packs_pi64 +#define _m_packusqd _mm_packs_pu64 +#define _mm_packs_si64 _mm_packs_pi64 +#define _mm_packs_su64 _mm_packs_pu64 +#define _m_punpckhbw _mm_unpackhi_pi8 +#define _m_punpckhwd _mm_unpackhi_pi16 +#define _m_punpckhdq _mm_unpackhi_pi32 +#define _m_punpcklbw _mm_unpacklo_pi8 +#define _m_punpcklwd _mm_unpacklo_pi16 +#define _m_punpckldq _mm_unpacklo_pi32 +#define _m_punpckehsbw _mm_unpackeh_pi8 +#define _m_punpckehswd _mm_unpackeh_pi16 +#define _m_punpckehsdq _mm_unpackeh_pi32 +#define _m_punpckehubw _mm_unpackeh_pu8 +#define _m_punpckehuwd _mm_unpackeh_pu16 +#define _m_punpckehudq _mm_unpackeh_pu32 +#define _m_punpckelsbw _mm_unpackel_pi8 +#define _m_punpckelswd _mm_unpackel_pi16 +#define _m_punpckelsdq _mm_unpackel_pi32 +#define _m_punpckelubw _mm_unpackel_pu8 +#define _m_punpckeluwd _mm_unpackel_pu16 +#define _m_punpckeludq _mm_unpackel_pu32 +#define _m_paddb _mm_add_pi8 +#define _m_paddw _mm_add_pi16 +#define _m_paddd _mm_add_pi32 +#define _m_paddsb _mm_adds_pi8 +#define _m_paddsw _mm_adds_pi16 +#define _m_paddsd _mm_adds_pi32 +#define _m_paddusb _mm_adds_pu8 +#define _m_paddusw _mm_adds_pu16 +#define _m_paddusd _mm_adds_pu32 +#define _m_psubb _mm_sub_pi8 +#define _m_psubw _mm_sub_pi16 +#define _m_psubd _mm_sub_pi32 +#define _m_psubsb _mm_subs_pi8 +#define _m_psubsw _mm_subs_pi16 +#define _m_psubuw _mm_subs_pi32 +#define _m_psubusb _mm_subs_pu8 +#define _m_psubusw _mm_subs_pu16 +#define _m_psubusd _mm_subs_pu32 +#define _m_pmaddwd _mm_madd_pi16 +#define _m_pmadduwd _mm_madd_pu16 +#define _m_pmulhw _mm_mulhi_pi16 +#define _m_pmulhuw _mm_mulhi_pu16 +#define _m_pmullw _mm_mullo_pi16 +#define _m_pmacsw _mm_mac_pi16 +#define _m_pmacuw _mm_mac_pu16 +#define _m_pmacszw _mm_macz_pi16 +#define _m_pmacuzw _mm_macz_pu16 +#define _m_paccb _mm_acc_pu8 +#define _m_paccw _mm_acc_pu16 +#define _m_paccd _mm_acc_pu32 +#define _m_pmia _mm_mia_si64 +#define _m_pmiaph _mm_miaph_si64 +#define _m_pmiabb _mm_miabb_si64 +#define _m_pmiabt _mm_miabt_si64 +#define _m_pmiatb _mm_miatb_si64 +#define _m_pmiatt _mm_miatt_si64 +#define _m_psllw _mm_sll_pi16 +#define _m_psllwi _mm_slli_pi16 +#define _m_pslld _mm_sll_pi32 +#define _m_pslldi _mm_slli_pi32 +#define _m_psllq _mm_sll_si64 +#define _m_psllqi _mm_slli_si64 +#define _m_psraw _mm_sra_pi16 +#define _m_psrawi _mm_srai_pi16 +#define _m_psrad _mm_sra_pi32 +#define _m_psradi _mm_srai_pi32 +#define _m_psraq _mm_sra_si64 +#define _m_psraqi _mm_srai_si64 +#define _m_psrlw _mm_srl_pi16 +#define _m_psrlwi _mm_srli_pi16 +#define _m_psrld _mm_srl_pi32 +#define _m_psrldi _mm_srli_pi32 +#define _m_psrlq _mm_srl_si64 +#define _m_psrlqi _mm_srli_si64 +#define _m_prorw _mm_ror_pi16 +#define _m_prorwi _mm_rori_pi16 +#define _m_prord _mm_ror_pi32 +#define _m_prordi _mm_rori_pi32 +#define _m_prorq _mm_ror_si64 +#define _m_prorqi _mm_rori_si64 +#define _m_pand _mm_and_si64 +#define _m_pandn _mm_andnot_si64 +#define _m_por _mm_or_si64 +#define _m_pxor _mm_xor_si64 +#define _m_pcmpeqb _mm_cmpeq_pi8 +#define _m_pcmpeqw _mm_cmpeq_pi16 +#define _m_pcmpeqd _mm_cmpeq_pi32 +#define _m_pcmpgtb _mm_cmpgt_pi8 +#define _m_pcmpgtub _mm_cmpgt_pu8 +#define _m_pcmpgtw _mm_cmpgt_pi16 +#define _m_pcmpgtuw _mm_cmpgt_pu16 +#define _m_pcmpgtd _mm_cmpgt_pi32 +#define _m_pcmpgtud _mm_cmpgt_pu32 +#define _m_pextrb _mm_extract_pi8 +#define _m_pextrw _mm_extract_pi16 +#define _m_pextrd _mm_extract_pi32 +#define _m_pextrub _mm_extract_pu8 +#define _m_pextruw _mm_extract_pu16 +#define _m_pextrud _mm_extract_pu32 +#define _m_pinsrb _mm_insert_pi8 +#define _m_pinsrw _mm_insert_pi16 +#define _m_pinsrd _mm_insert_pi32 +#define _m_pmaxsb _mm_max_pi8 +#define _m_pmaxsw _mm_max_pi16 +#define _m_pmaxsd _mm_max_pi32 +#define _m_pmaxub _mm_max_pu8 +#define _m_pmaxuw _mm_max_pu16 +#define _m_pmaxud _mm_max_pu32 +#define _m_pminsb _mm_min_pi8 +#define _m_pminsw _mm_min_pi16 +#define _m_pminsd _mm_min_pi32 +#define _m_pminub _mm_min_pu8 +#define _m_pminuw _mm_min_pu16 +#define _m_pminud _mm_min_pu32 +#define _m_pmovmskb _mm_movemask_pi8 +#define _m_pmovmskw _mm_movemask_pi16 +#define _m_pmovmskd _mm_movemask_pi32 +#define _m_pshufw _mm_shuffle_pi16 +#define _m_pavgb _mm_avg_pu8 +#define _m_pavgw _mm_avg_pu16 +#define _m_pavg2b _mm_avg2_pu8 +#define _m_pavg2w _mm_avg2_pu16 +#define _m_psadbw _mm_sad_pu8 +#define _m_psadwd _mm_sad_pu16 +#define _m_psadzbw _mm_sadz_pu8 +#define _m_psadzwd _mm_sadz_pu16 +#define _m_paligniq _mm_align_si64 +#define _m_cvt_si2pi _mm_cvtsi64_m64 +#define _m_cvt_pi2si _mm_cvtm64_si64 + +#endif /* _MMINTRIN_H_INCLUDED */ diff --git a/contrib/gcc/config/arm/netbsd-elf.h b/contrib/gcc/config/arm/netbsd-elf.h index 0d5b798..a8b43f6 100644 --- a/contrib/gcc/config/arm/netbsd-elf.h +++ b/contrib/gcc/config/arm/netbsd-elf.h @@ -1,32 +1,28 @@ /* Definitions of target machine for GNU compiler, NetBSD/arm ELF version. - Copyright (C) 2002 Free Software Foundation, Inc. + Copyright (C) 2002, 2003 Free Software Foundation, Inc. Contributed by Wasabi Systems, Inc. -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ /* Run-time Target Specification. */ #undef TARGET_VERSION #define TARGET_VERSION fputs (" (NetBSD/arm ELF)", stderr); -/* This is used in ASM_FILE_START. */ -#undef ARM_OS_NAME -#define ARM_OS_NAME "NetBSD" - /* arm.h defaults to ARM6 CPU. */ /* This defaults us to little-endian. */ @@ -59,7 +55,7 @@ Boston, MA 02111-1307, USA. */ #undef SUBTARGET_EXTRA_ASM_SPEC #define SUBTARGET_EXTRA_ASM_SPEC \ - "-matpcs %{fpic:-k} %{fPIC:-k}" + "-matpcs %{fpic|fpie:-k} %{fPIC|fPIE:-k}" /* Default floating point model is soft-VFP. FIXME: -mhard-float currently implies FPA. */ @@ -127,7 +123,7 @@ Boston, MA 02111-1307, USA. */ This has several side effects that should be considered. 1. Structures will only be aligned to the size of the largest member. i.e. structures containing only bytes will be byte aligned. - structures containing shorts will be half word alinged. + structures containing shorts will be half word aligned. structures containing ints will be word aligned. This means structures should be padded to a word boundary if diff --git a/contrib/gcc/config/arm/netbsd.h b/contrib/gcc/config/arm/netbsd.h index 38ccc3f..71763e6 100644 --- a/contrib/gcc/config/arm/netbsd.h +++ b/contrib/gcc/config/arm/netbsd.h @@ -1,32 +1,28 @@ /* NetBSD/arm a.out version. - Copyright (C) 1993, 1994, 1997, 1998 Free Software Foundation, Inc. + Copyright (C) 1993, 1994, 1997, 1998, 2003 Free Software Foundation, Inc. Contributed by Mark Brinicombe (amb@physig.ph.kcl.ac.uk) -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ /* Run-time Target Specification. */ #undef TARGET_VERSION #define TARGET_VERSION fputs (" (ARM/NetBSD)", stderr); -/* This is used in ASM_FILE_START. */ -#undef ARM_OS_NAME -#define ARM_OS_NAME "NetBSD" - /* Unsigned chars produces much better code than signed. */ #define DEFAULT_SIGNED_CHAR 0 @@ -40,7 +36,7 @@ Boston, MA 02111-1307, USA. */ /* Default is to use APCS-32 mode. */ #undef TARGET_DEFAULT -#define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_SOFT_FLOAT | ARM_FLAG_APCS_FRAME) +#define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_SOFT_FLOAT | ARM_FLAG_APCS_FRAME | ARM_FLAG_MMU_TRAPS) /* Some defines for CPP. arm32 is the NetBSD port name, so we always define arm32 and __arm32__. */ @@ -103,7 +99,7 @@ Boston, MA 02111-1307, USA. */ #undef TYPE_OPERAND_FMT #define TYPE_OPERAND_FMT "%%%s" -/* NetBSD uses the old PCC style aggregate returning conventions. */ +/* NetBSD uses the old PCC style aggregate returning conventions. */ #undef DEFAULT_PCC_STRUCT_RETURN #define DEFAULT_PCC_STRUCT_RETURN 1 @@ -130,7 +126,7 @@ Boston, MA 02111-1307, USA. */ This has several side effects that should be considered. 1. Structures will only be aligned to the size of the largest member. i.e. structures containing only bytes will be byte aligned. - structures containing shorts will be half word alinged. + structures containing shorts will be half word aligned. structures containing ints will be word aligned. This means structures should be padded to a word boundary if diff --git a/contrib/gcc/config/arm/pe.c b/contrib/gcc/config/arm/pe.c index ee3da8f..d25fd0d 100644 --- a/contrib/gcc/config/arm/pe.c +++ b/contrib/gcc/config/arm/pe.c @@ -2,25 +2,27 @@ Copyright (C) 1995, 1996, 2000, 2001, 2002 Free Software Foundation, Inc. Contributed by Doug Evans (dje@cygnus.com). -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ #include "config.h" #include "system.h" +#include "coretypes.h" +#include "tm.h" #include "rtl.h" #include "output.h" #include "flags.h" @@ -165,7 +167,7 @@ arm_mark_dllimport (decl) && !DECL_VIRTUAL_P (decl) && DECL_INITIAL (decl)) { - error_with_decl (decl, "initialized variable `%s' is marked dllimport"); + error ("%Jinitialized variable '%D' is marked dllimport", decl, decl); return; } /* Nor can they be static. */ @@ -174,7 +176,7 @@ arm_mark_dllimport (decl) && !DECL_VIRTUAL_P (decl) && 0 /*???*/) { - error_with_decl (decl, "static variable `%s' is marked dllimport"); + error ("%Jstatic variable '%D' is marked dllimport", decl, decl); return; } @@ -205,18 +207,15 @@ arm_mark_dllimport (decl) } void -arm_pe_encode_section_info (decl, first) +arm_pe_encode_section_info (decl, rtl, first) tree decl; + rtx rtl; int first ATTRIBUTE_UNUSED; { /* This bit is copied from arm_encode_section_info. */ if (optimize > 0 && TREE_CONSTANT (decl) && (!flag_writable_strings || TREE_CODE (decl) != STRING_CST)) - { - rtx rtl = (TREE_CODE_CLASS (TREE_CODE (decl)) != 'd' - ? TREE_CST_RTL (decl) : DECL_RTL (decl)); - SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; - } + SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1; /* Mark the decl so we can tell from the rtl whether the object is dllexport'd or dllimport'd. */ diff --git a/contrib/gcc/config/arm/pe.h b/contrib/gcc/config/arm/pe.h index 38727da..e83f97b 100644 --- a/contrib/gcc/config/arm/pe.h +++ b/contrib/gcc/config/arm/pe.h @@ -1,23 +1,23 @@ /* Definitions of target machine for GNU compiler, for ARM with PE obj format. - Copyright (C) 1995, 1996, 1999, 2000, 2002 Free Software Foundation, Inc. + Copyright (C) 1995, 1996, 1999, 2000, 2002, 2003 Free Software Foundation, Inc. Contributed by Doug Evans (dje@cygnus.com). -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ /* Enable PE specific code. */ #define ARM_PE 1 @@ -65,34 +65,30 @@ Boston, MA 02111-1307, USA. */ N_("Ignore dllimport attribute for functions") }, \ { "no-nop-fun-dllimport", - TARGET_FLAG_NOP_FUN, "" }, +/* Defaulting to APCS-26 support is a legacy issue. It has been done + that way for a long time, so changing it will probably break some + people's worlds. Support for APCS-32 is now enabled as a multilib, + and at some point in the future APCS-32 may become the default. + Possibly when chips that support APCS-26 are no longer made. */ + #undef TARGET_DEFAULT -#define TARGET_DEFAULT (ARM_FLAG_SOFT_FLOAT | TARGET_FLAG_NOP_FUN) +#define TARGET_DEFAULT (ARM_FLAG_SOFT_FLOAT | TARGET_FLAG_NOP_FUN | ARM_FLAG_MMU_TRAPS) +#undef MULTILIB_DEFAULTS +#define MULTILIB_DEFAULTS \ + { "marm", "mlittle-endian", "msoft-float", "mapcs-26", "mno-thumb-interwork" } #undef WCHAR_TYPE #define WCHAR_TYPE "short unsigned int" #undef WCHAR_TYPE_SIZE #define WCHAR_TYPE_SIZE 16 -/* Same as arm.h except r10 is call-saved, not fixed. */ -#undef FIXED_REGISTERS -#define FIXED_REGISTERS \ -{ \ - 0,0,0,0,0,0,0,0, \ - 0,0,0,1,0,1,0,1, \ - 0,0,0,0,0,0,0,0, \ - 1,1,1 \ -} +/* r11 is fixed. */ +#undef SUBTARGET_CONDITIONAL_REGISTER_USAGE +#define SUBTARGET_CONDITIONAL_REGISTER_USAGE \ + fixed_regs [11] = 1; \ + call_used_regs [11] = 1; -/* Same as arm.h except r10 is call-saved, not fixed. */ -#undef CALL_USED_REGISTERS -#define CALL_USED_REGISTERS \ -{ \ - 1,1,1,1,0,0,0,0, \ - 0,0,0,1,1,1,1,1, \ - 1,1,1,1,0,0,0,0, \ - 1,1,1 \ -} /* Define this macro if in some cases global symbols from one translation unit may not be bound to undefined symbols in another translation unit @@ -105,20 +101,10 @@ Boston, MA 02111-1307, USA. */ #define SUPPORTS_ONE_ONLY 1 /* Switch into a generic section. */ -#undef TARGET_ASM_NAMED_SECTION +#undef TARGET_ASM_NAMED_SECTION #define TARGET_ASM_NAMED_SECTION default_pe_asm_named_section -/* This outputs a lot of .req's to define alias for various registers. - Let's try to avoid this. */ -#undef ASM_FILE_START -#define ASM_FILE_START(STREAM) \ - do \ - { \ - asm_fprintf (STREAM, "%@ Generated by gcc %s for ARM/pe\n",\ - version_string); \ - output_file_directive ((STREAM), main_input_filename); \ - } \ - while (0) +#define TARGET_ASM_FILE_START_FILE_DIRECTIVE true /* Output a reference to a label. */ #undef ASM_OUTPUT_LABELREF @@ -160,7 +146,7 @@ Boston, MA 02111-1307, USA. */ fprintf ((STREAM), "\t.comm\t"); \ assemble_name ((STREAM), (NAME)); \ asm_fprintf ((STREAM), ", %d\t%@ %d\n", \ - (ROUNDED), (SIZE)); \ + (int)(ROUNDED), (int)(SIZE)); \ } \ } \ while (0) @@ -201,7 +187,7 @@ Boston, MA 02111-1307, USA. */ #define DRECTVE_SECTION_FUNCTION \ void \ -drectve_section () \ +drectve_section (void) \ { \ if (in_section != in_drectve) \ { \ @@ -217,11 +203,8 @@ drectve_section () \ ASM_DECLARE_OBJECT_NAME and then switch back to the original section afterwards. */ #define SWITCH_TO_SECTION_FUNCTION \ -static void switch_to_section PARAMS ((enum in_section, tree)); \ static void \ -switch_to_section (section, decl) \ - enum in_section section; \ - tree decl; \ +switch_to_section (enum in_section section, tree decl) \ { \ switch (section) \ { \ @@ -235,3 +218,4 @@ switch_to_section (section, decl) \ default: abort (); break; \ } \ } + diff --git a/contrib/gcc/config/arm/rtems-elf.h b/contrib/gcc/config/arm/rtems-elf.h index 27928db..a736ee1 100644 --- a/contrib/gcc/config/arm/rtems-elf.h +++ b/contrib/gcc/config/arm/rtems-elf.h @@ -1,22 +1,22 @@ /* Definitions for RTEMS based ARM systems using ELF Copyright (C) 2000, 2002 Free Software Foundation, Inc. -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with this program; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ /* Run-time Target Specification. */ #undef TARGET_VERSION @@ -27,6 +27,5 @@ Boston, MA 02111-1307, USA. */ #define TARGET_OS_CPP_BUILTINS() \ do { \ builtin_define ("__rtems__"); \ - builtin_define ("__ELF__"); \ builtin_assert ("system=rtems"); \ } while (0) diff --git a/contrib/gcc/config/arm/semi.h b/contrib/gcc/config/arm/semi.h index 2e1abd4..2ab06cb 100644 --- a/contrib/gcc/config/arm/semi.h +++ b/contrib/gcc/config/arm/semi.h @@ -2,22 +2,22 @@ Copyright (C) 1994, 1995, 1996, 1997, 2001 Free Software Foundation, Inc. Contributed by Richard Earnshaw (richard.earnshaw@arm.com) -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ #define STARTFILE_SPEC "crt0.o%s" @@ -38,7 +38,7 @@ Boston, MA 02111-1307, USA. */ #endif #ifndef TARGET_DEFAULT -#define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME) +#define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME | ARM_FLAG_MMU_TRAPS) #endif #ifndef SUBTARGET_EXTRA_SPECS @@ -59,12 +59,12 @@ Boston, MA 02111-1307, USA. */ binutils can't. */ #ifndef ASM_SPEC #define ASM_SPEC "\ -%{fpic: -k} %{fPIC: -k} \ +%{fpic|fpie: -k} %{fPIC|fPIE: -k} \ %{mbig-endian:-EB} \ %{mcpu=*:-mcpu=%*} \ %{march=*:-march=%*} \ %{mapcs-float:-mfloat} \ -%{msoft-float:-mno-fpu} \ +%{msoft-float:-mfpu=softfpa} \ %{mthumb-interwork:-mthumb-interwork} \ %(subtarget_extra_asm_spec)" #endif diff --git a/contrib/gcc/config/arm/semiaof.h b/contrib/gcc/config/arm/semiaof.h index 6ee17ef..19a6cf8 100644 --- a/contrib/gcc/config/arm/semiaof.h +++ b/contrib/gcc/config/arm/semiaof.h @@ -3,22 +3,22 @@ Copyright (C) 1995, 1996, 1997 Free Software Foundation, Inc. Contributed by Richard Earnshaw (richard.earnshaw@armltd.co.uk) -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ #define TARGET_OS_CPP_BUILTINS() \ do { \ @@ -33,9 +33,9 @@ Boston, MA 02111-1307, USA. */ #define TARGET_VERSION fputs (" (ARM/semi-hosted)", stderr); -#define TARGET_DEFAULT ARM_FLAG_APCS_32 +#define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_MMU_TRAPS) -/* The Norcroft C library defines size_t as "unsigned int" */ +/* The Norcroft C library defines size_t as "unsigned int". */ #define SIZE_TYPE "unsigned int" #undef CPP_APCS_PC_DEFAULT_SPEC diff --git a/contrib/gcc/config/arm/strongarm-coff.h b/contrib/gcc/config/arm/strongarm-coff.h index 4d2f292..77dab37 100644 --- a/contrib/gcc/config/arm/strongarm-coff.h +++ b/contrib/gcc/config/arm/strongarm-coff.h @@ -2,22 +2,22 @@ Copyright (C) 1999 Free Software Foundation, Inc. Contributed by Catherine Moore <clm@cygnus.com> -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with this program; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ /* Run-time Target Specification. */ #ifndef SUBTARGET_CPU_DEFAULT diff --git a/contrib/gcc/config/arm/strongarm-elf.h b/contrib/gcc/config/arm/strongarm-elf.h index 3fc8487..476b2e4 100644 --- a/contrib/gcc/config/arm/strongarm-elf.h +++ b/contrib/gcc/config/arm/strongarm-elf.h @@ -2,22 +2,22 @@ Copyright (C) 1999, 2001 Free Software Foundation, Inc. Contributed by Catherine Moore <clm@cygnus.com> -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with this program; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ /* Run-time Target Specification. */ #ifndef TARGET_VERSION diff --git a/contrib/gcc/config/arm/strongarm-pe.h b/contrib/gcc/config/arm/strongarm-pe.h index 2938d3e..bb123e5 100644 --- a/contrib/gcc/config/arm/strongarm-pe.h +++ b/contrib/gcc/config/arm/strongarm-pe.h @@ -2,22 +2,22 @@ Copyright (C) 1999 Free Software Foundation, Inc. Contributed by Doug Evans (dje@cygnus.com). -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ #undef TARGET_VERSION #define TARGET_VERSION fputs (" (StrongARM/PE)", stderr); diff --git a/contrib/gcc/config/arm/t-arm-coff b/contrib/gcc/config/arm/t-arm-coff index bf37a37..8eef976 100644 --- a/contrib/gcc/config/arm/t-arm-coff +++ b/contrib/gcc/config/arm/t-arm-coff @@ -28,7 +28,7 @@ EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o LIBGCC = stmp-multilib INSTALL_LIBGCC = install-multilib -# Currently there is a bug somwehere in GCC's alias analysis +# Currently there is a bug somewhere in GCC's alias analysis # or scheduling code that is breaking _fpmul_parts in fp-bit.c. # Disabling function inlining is a workaround for this problem. TARGET_LIBGCC2_CFLAGS = -Dinhibit_libc -fno-inline diff --git a/contrib/gcc/config/arm/t-arm-elf b/contrib/gcc/config/arm/t-arm-elf index 0011b2a..3f48f8b 100644 --- a/contrib/gcc/config/arm/t-arm-elf +++ b/contrib/gcc/config/arm/t-arm-elf @@ -1,34 +1,22 @@ LIB1ASMSRC = arm/lib1funcs.asm -LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_tls _bb_init_func _call_via_rX _interwork_call_via_rX +LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_tls _bb_init_func \ + _call_via_rX _interwork_call_via_rX \ + _negdf2 _addsubdf3 _muldivdf3 _cmpdf2 _unorddf2 _fixdfsi _fixunsdfsi \ + _truncdfsf2 _negsf2 _addsubsf3 _muldivsf3 _cmpsf2 _unordsf2 \ + _fixsfsi _fixunssfsi -# We want fine grained libraries, so use the new code to build the -# floating point emulation libraries. -FPBIT = fp-bit.c -DPBIT = dp-bit.c - -fp-bit.c: $(srcdir)/config/fp-bit.c - echo '#define FLOAT' > fp-bit.c - echo '#ifndef __ARMEB__' >> fp-bit.c - echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c - echo '#endif' >> fp-bit.c - cat $(srcdir)/config/fp-bit.c >> fp-bit.c - -dp-bit.c: $(srcdir)/config/fp-bit.c - echo '#ifndef __ARMEB__' > dp-bit.c - echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c - echo '#define FLOAT_WORD_ORDER_MISMATCH' >> dp-bit.c - echo '#endif' >> dp-bit.c - cat $(srcdir)/config/fp-bit.c >> dp-bit.c - - MULTILIB_OPTIONS = marm/mthumb MULTILIB_DIRNAMES = arm thumb MULTILIB_EXCEPTIONS = +MULTILIB_MATCHES = + +# MULTILIB_OPTIONS += mcpu=ep9312 +# MULTILIB_DIRNAMES += ep9312 +# MULTILIB_EXCEPTIONS += *mthumb/*mcpu=ep9312* # MULTILIB_OPTIONS += mlittle-endian/mbig-endian # MULTILIB_DIRNAMES += le be -# MULTILIB_EXCEPTIONS = -# MULTILIB_MATCHES = mbig-endian=mbe mlittle-endian=mle +# MULTILIB_MATCHES += mbig-endian=mbe mlittle-endian=mle # # MULTILIB_OPTIONS += mhard-float/msoft-float # MULTILIB_DIRNAMES += fpu soft @@ -93,3 +81,4 @@ $(T)crti.o: $(srcdir)/config/arm/crti.asm $(GCC_PASSES) $(T)crtn.o: $(srcdir)/config/arm/crtn.asm $(GCC_PASSES) $(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \ -c -o $(T)crtn.o -x assembler-with-cpp $(srcdir)/config/arm/crtn.asm + diff --git a/contrib/gcc/config/arm/t-linux b/contrib/gcc/config/arm/t-linux index 7dbd0c0..1c5f48a 100644 --- a/contrib/gcc/config/arm/t-linux +++ b/contrib/gcc/config/arm/t-linux @@ -3,9 +3,6 @@ TARGET_LIBGCC2_CFLAGS = -fomit-frame-pointer -fPIC LIBGCC2_DEBUG_CFLAGS = -g0 -# Don't build enquire -ENQUIRE= - LIB1ASMSRC = arm/lib1funcs.asm LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_lnx diff --git a/contrib/gcc/config/arm/t-netbsd b/contrib/gcc/config/arm/t-netbsd index 76e431b..77e6227 100644 --- a/contrib/gcc/config/arm/t-netbsd +++ b/contrib/gcc/config/arm/t-netbsd @@ -19,8 +19,3 @@ SHLIB_LINK = $(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) -shared -nodefaultlibs \ SHLIB_INSTALL = $(INSTALL_DATA) $(SHLIB_NAME) $$(DESTDIR)$$(slibdir)/$(SHLIB_SONAME); \ rm -f $$(DESTDIR)$$(slibdir)/$(SHLIB_NAME); \ $(LN_S) $(SHLIB_SONAME) $$(DESTDIR)$$(slibdir)/$(SHLIB_NAME) - -# Don't build enquire -ENQUIRE= - - diff --git a/contrib/gcc/config/arm/t-pe b/contrib/gcc/config/arm/t-pe index f559bd2..4c20b31 100644 --- a/contrib/gcc/config/arm/t-pe +++ b/contrib/gcc/config/arm/t-pe @@ -20,12 +20,12 @@ dp-bit.c: $(srcdir)/config/fp-bit.c echo '#endif' >> dp-bit.c cat $(srcdir)/config/fp-bit.c >> dp-bit.c -pe.o: $(srcdir)/config/arm/pe.c $(CONFIG_H) $(SYSTEM_H) $(RTL_H) output.h \ - flags.h $(TREE_H) $(EXPR_H) toplev.h $(TM_P_H) +pe.o: $(srcdir)/config/arm/pe.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ + $(RTL_H) output.h flags.h $(TREE_H) expr.h toplev.h $(TM_P_H) $(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $(srcdir)/config/arm/pe.c -MULTILIB_OPTIONS = mhard-float mthumb -MULTILIB_DIRNAMES = fpu thumb +MULTILIB_OPTIONS = mhard-float mthumb mapcs-32 +MULTILIB_DIRNAMES = fpu thumb apcs32 LIBGCC = stmp-multilib INSTALL_LIBGCC = install-multilib diff --git a/contrib/gcc/config/arm/t-semi b/contrib/gcc/config/arm/t-semi index ce39460..abd642c 100644 --- a/contrib/gcc/config/arm/t-semi +++ b/contrib/gcc/config/arm/t-semi @@ -3,15 +3,9 @@ TARGET_LIBGCC2_CFLAGS = -fomit-frame-pointer LIBGCC2_DEBUG_CFLAGS = -g0 -# Don't build enquire -ENQUIRE= - LIB1ASMSRC = arm/lib1funcs.asm LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_tls _call_via_rX _interwork_call_via_rX -#Don't try to run fixproto -STMP_FIXPROTO = - # We want fine grained libraries, so use the new code to build the # floating point emulation libraries. FPBIT = fp-bit.c diff --git a/contrib/gcc/config/arm/t-strongarm-pe b/contrib/gcc/config/arm/t-strongarm-pe index 6a44132..e401666 100644 --- a/contrib/gcc/config/arm/t-strongarm-pe +++ b/contrib/gcc/config/arm/t-strongarm-pe @@ -20,7 +20,8 @@ dp-bit.c: $(srcdir)/config/fp-bit.c echo '#endif' >> dp-bit.c cat $(srcdir)/config/fp-bit.c >> dp-bit.c -pe.o: $(srcdir)/config/arm/pe.c +pe.o: $(srcdir)/config/arm/pe.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ + $(RTL_H) output.h flags.h $(TREE_H) expr.h toplev.h $(TM_P_H) $(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $(srcdir)/config/arm/pe.c MULTILIB_OPTIONS = mhard-float/msoft-float @@ -31,7 +32,7 @@ EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o LIBGCC = stmp-multilib INSTALL_LIBGCC = install-multilib -# Currently there is a bug somwehere in GCC's alias analysis +# Currently there is a bug somewhere in GCC's alias analysis # or scheduling code that is breaking _fpmul_parts in fp-bit.c. # Disabling function inlining is a workaround for this problem. TARGET_LIBGCC2_CFLAGS = -Dinhibit_libc -fno-inline diff --git a/contrib/gcc/config/arm/t-vxworks b/contrib/gcc/config/arm/t-vxworks new file mode 100644 index 0000000..e620cfd --- /dev/null +++ b/contrib/gcc/config/arm/t-vxworks @@ -0,0 +1,10 @@ +# Multilibs for VxWorks. + +MULTILIB_OPTIONS = \ + t4/t4be/t4t/t4tbe/t5/t5be/t5t/t5tbe/txscale/txscalebe + +MULTILIB_DIRNAMES = \ + ARMARCH4gnu ARMARCH4gnube ARMARCH4_Tgnu ARMARCH4_Tgnube \ + ARMARCH5gnu ARMARCH5gnube ARMARCH5_Tgnu ARMARCH5_Tgnube \ + XSCALEgnu XSCALEgnube + diff --git a/contrib/gcc/config/arm/t-wince-pe b/contrib/gcc/config/arm/t-wince-pe new file mode 100644 index 0000000..9537a7f --- /dev/null +++ b/contrib/gcc/config/arm/t-wince-pe @@ -0,0 +1,37 @@ +LIB1ASMSRC = arm/lib1funcs.asm +LIB1ASMFUNCS = _udivsi3 _divsi3 _umodsi3 _modsi3 _dvmd_tls _call_via_rX _interwork_call_via_rX + +# We want fine grained libraries, so use the new code to build the +# floating point emulation libraries. +FPBIT = fp-bit.c +DPBIT = dp-bit.c + +fp-bit.c: $(srcdir)/config/fp-bit.c + echo '#define FLOAT' > fp-bit.c + echo '#ifndef __ARMEB__' >> fp-bit.c + echo '#define FLOAT_BIT_ORDER_MISMATCH' >> fp-bit.c + echo '#endif' >> fp-bit.c + cat $(srcdir)/config/fp-bit.c >> fp-bit.c + +dp-bit.c: $(srcdir)/config/fp-bit.c + echo '#ifndef __ARMEB__' > dp-bit.c + echo '#define FLOAT_BIT_ORDER_MISMATCH' >> dp-bit.c + echo '#define FLOAT_WORD_ORDER_MISMATCH' >> dp-bit.c + echo '#endif' >> dp-bit.c + cat $(srcdir)/config/fp-bit.c >> dp-bit.c + +pe.o: $(srcdir)/config/arm/pe.c $(CONFIG_H) $(SYSTEM_H) coretypes.h $(TM_H) \ + $(RTL_H) output.h flags.h $(TREE_H) expr.h toplev.h $(TM_P_H) + $(CC) -c $(ALL_CFLAGS) $(ALL_CPPFLAGS) $(INCLUDES) $(srcdir)/config/arm/pe.c + +MULTILIB_OPTIONS = mhard-float mapcs-26 +MULTILIB_DIRNAMES = fpu apcs26 +# Note - Thumb multilib omitted because Thumb apcs32 support for +# arm-wince-pe target does not appear to be working in binutils +# yet... +# MULTILIB_OPTIONS += thumb +# MULTILIB_DIRNAMES += thumb + +LIBGCC = stmp-multilib +INSTALL_LIBGCC = install-multilib +TARGET_LIBGCC2_CFLAGS = -Dinhibit_libc diff --git a/contrib/gcc/config/arm/t-xscale-elf b/contrib/gcc/config/arm/t-xscale-elf index 0efc1d5..b72c21c 100644 --- a/contrib/gcc/config/arm/t-xscale-elf +++ b/contrib/gcc/config/arm/t-xscale-elf @@ -37,6 +37,10 @@ MULTILIB_EXCEPTIONS += *mhard-float/*mthumb* MULTILIB_REDUNDANT_DIRS = interwork/thumb=thumb +MULTILIB_OPTIONS += mcpu=iwmmxt +MULTILIB_DIRNAMES += iwmmxt +MULTILIB_REDUNDANT_DIRS += interwork/thumb/iwmmxt=thumb + EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crti.o crtn.o LIBGCC = stmp-multilib diff --git a/contrib/gcc/config/arm/uclinux-elf.h b/contrib/gcc/config/arm/uclinux-elf.h index cad61b7..e3cd48d 100644 --- a/contrib/gcc/config/arm/uclinux-elf.h +++ b/contrib/gcc/config/arm/uclinux-elf.h @@ -2,22 +2,22 @@ Copyright (C) 1999, 2001 Free Software Foundation, Inc. Contributed by Philip Blundell <pb@nexus.co.uk> -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with this program; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ /* We don't want a PLT. */ #undef NEED_PLT_RELOC diff --git a/contrib/gcc/config/arm/unknown-elf.h b/contrib/gcc/config/arm/unknown-elf.h index 7f9211b..1af7994 100644 --- a/contrib/gcc/config/arm/unknown-elf.h +++ b/contrib/gcc/config/arm/unknown-elf.h @@ -1,23 +1,24 @@ /* Definitions for non-Linux based ARM systems using ELF - Copyright (C) 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 + Free Software Foundation, Inc. Contributed by Catherine Moore <clm@cygnus.com> -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with this program; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ /* elfos.h should have already been included. Now just override any conflicting definitions and add any extras. */ @@ -29,7 +30,7 @@ Boston, MA 02111-1307, USA. */ /* Default to using APCS-32 and software floating point. */ #ifndef TARGET_DEFAULT -#define TARGET_DEFAULT (ARM_FLAG_SOFT_FLOAT | ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME) +#define TARGET_DEFAULT (ARM_FLAG_SOFT_FLOAT | ARM_FLAG_APCS_32 | ARM_FLAG_APCS_FRAME | ARM_FLAG_MMU_TRAPS) #endif /* Now we define the strings used to build the spec file. */ @@ -42,7 +43,7 @@ Boston, MA 02111-1307, USA. */ /* The __USES_INITFINI__ define is tested in newlib/libc/sys/arm/crt0.S to see if it needs to invoked _init() and _fini(). */ #undef SUBTARGET_CPP_SPEC -#define SUBTARGET_CPP_SPEC "-D__ELF__ -D__USES_INITFINI__" +#define SUBTARGET_CPP_SPEC "-D__USES_INITFINI__" #undef PREFERRED_DEBUGGING_TYPE #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG @@ -61,13 +62,11 @@ Boston, MA 02111-1307, USA. */ else \ bss_section (); \ \ - (*targetm.asm_out.globalize_label) (FILE, NAME); \ - \ ASM_OUTPUT_ALIGN (FILE, floor_log2 (ALIGN / BITS_PER_UNIT)); \ \ last_assemble_variable_decl = DECL; \ ASM_DECLARE_OBJECT_NAME (FILE, NAME, DECL); \ - ASM_OUTPUT_SKIP (FILE, SIZE ? SIZE : 1); \ + ASM_OUTPUT_SKIP (FILE, SIZE ? (int)(SIZE) : 1); \ } \ while (0) @@ -82,7 +81,7 @@ Boston, MA 02111-1307, USA. */ \ ASM_OUTPUT_ALIGN (FILE, floor_log2 (ALIGN / BITS_PER_UNIT)); \ ASM_OUTPUT_LABEL (FILE, NAME); \ - fprintf (FILE, "\t.space\t%d\n", SIZE ? SIZE : 1); \ + fprintf (FILE, "\t.space\t%d\n", SIZE ? (int)(SIZE) : 1); \ } \ while (0) diff --git a/contrib/gcc/config/arm/vxworks.h b/contrib/gcc/config/arm/vxworks.h new file mode 100644 index 0000000..afe6b70 --- /dev/null +++ b/contrib/gcc/config/arm/vxworks.h @@ -0,0 +1,95 @@ +/* Definitions of target machine for GCC, + for ARM with targetting the VXWorks run time environment. + Copyright (C) 1999, 2000, 2003 Free Software Foundation, Inc. + + Contributed by: Mike Stump <mrs@wrs.com> + Brought up to date by CodeSourcery, LLC. + +This file is part of GCC. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + + +#define TARGET_OS_CPP_BUILTINS() \ + do { \ + builtin_define ("__vxworks"); \ + if (TARGET_BIG_END) \ + builtin_define ("ARMEB"); \ + else \ + builtin_define ("ARMEL"); \ + \ + if (arm_is_xscale) \ + builtin_define ("CPU=XSCALE"); \ + else if (arm_arch5) \ + builtin_define ("CPU=ARMARCH5"); \ + else if (arm_arch4) \ + { \ + if (thumb_code) \ + builtin_define ("CPU=ARMARCH4_T"); \ + else \ + builtin_define ("CPU=ARMARCH4"); \ + } \ + } while (0) + +#undef CC1_SPEC +#define CC1_SPEC \ +"%{t4: -mapcs-32 -mlittle-endian -march=armv4 ; \ + t4be: -mapcs-32 -mbig-endian -march=armv4 ; \ + t4t: -mthumb -mthumb-interwork -mlittle-endian -march=armv4t ; \ + t4tbe: -mthumb -mthumb-interwork -mbig-endian -march=armv4t ; \ + t5: -mapcs-32 -mlittle-endian -march=armv5 ; \ + t5be: -mapcs-32 -mbig-endian -march=armv5 ; \ + t5t: -mthumb -mthumb-interwork -mlittle-endian -march=armv5 ; \ + t5tbe: -mthumb -mthumb-interwork -mbig-endian -march=armv5 ; \ + txscale: -mapcs-32 -mlittle-endian -mcpu=xscale ; \ + txscalebe: -mapcs-32 -mbig-endian -mcpu=xscale ; \ + : -march=armv4}" + +/* The -Q options from svr4.h aren't understood and must be removed. */ +#undef ASM_SPEC +#define ASM_SPEC \ + "%{v:-V} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*}" + +/* VxWorks does all the library stuff itself. */ +#undef LIB_SPEC +#define LIB_SPEC "" + +/* VxWorks uses object files, not loadable images. make linker just + combine objects. */ +#undef LINK_SPEC +#define LINK_SPEC "-r" + +/* VxWorks provides the functionality of crt0.o and friends itself. */ +#undef STARTFILE_SPEC +#define STARTFILE_SPEC "" + +#undef ENDFILE_SPEC +#define ENDFILE_SPEC "" + +#undef TARGET_VERSION +#define TARGET_VERSION fputs (" (ARM/VxWorks)", stderr); + +/* There is no default multilib. */ +#undef MULTILIB_DEFAULTS + +#undef ASM_FILE_START +#define ASM_FILE_START(STREAM) \ + do \ + { \ + fprintf (STREAM, "%s Generated by GCC %s for ARM/VxWorks\n", \ + ASM_COMMENT_START, version_string); \ + } \ + while (0) diff --git a/contrib/gcc/config/arm/wince-pe.h b/contrib/gcc/config/arm/wince-pe.h new file mode 100644 index 0000000..fb47485 --- /dev/null +++ b/contrib/gcc/config/arm/wince-pe.h @@ -0,0 +1,29 @@ +/* Definitions of target machine for GNU compiler, for ARM with WINCE-PE obj format. + Copyright (C) 2003 Free Software Foundation, Inc. + Contributed by Nick Clifton <nickc@redhat.com> + + This file is part of GCC. + + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. + + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with GCC; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +/* Override arm/pe.h's default apcs26 support. */ + +#undef TARGET_DEFAULT +#define TARGET_DEFAULT (ARM_FLAG_APCS_32 | ARM_FLAG_SOFT_FLOAT | TARGET_FLAG_NOP_FUN | ARM_FLAG_MMU_TRAPS) + +#undef MULTILIB_DEFAULTS +#define MULTILIB_DEFAULTS \ + { "marm", "mlittle-endian", "msoft-float", "mapcs-32", "mno-thumb-interwork" } diff --git a/contrib/gcc/config/arm/xscale-elf.h b/contrib/gcc/config/arm/xscale-elf.h index 8ea3588..aea8360 100644 --- a/contrib/gcc/config/arm/xscale-elf.h +++ b/contrib/gcc/config/arm/xscale-elf.h @@ -2,22 +2,22 @@ Copyright (C) 1999, 2000, 2001 Free Software Foundation, Inc. Contributed by Catherine Moore <clm@cygnus.com> -This file is part of GNU CC. + This file is part of GCC. -GNU CC is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2, or (at your option) -any later version. + GCC is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published + by the Free Software Foundation; either version 2, or (at your + option) any later version. -GNU CC is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + GCC is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. -You should have received a copy of the GNU General Public License -along with this program; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, -Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this program; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ /* Run-time Target Specification. */ #ifndef TARGET_VERSION @@ -28,7 +28,30 @@ Boston, MA 02111-1307, USA. */ #define SUBTARGET_CPU_DEFAULT TARGET_CPU_xscale #endif -#define SUBTARGET_EXTRA_ASM_SPEC "%{!mcpu=*:-mcpu=xscale} %{!mhard-float:-mno-fpu}" +/* Note - there are three possible -mfpu= arguments that can be passed to + the assembler: + + -mfpu=softvfp This is the default. It indicates thats doubles are + stored in a format compatible with the VFP + specification. This is the newer double format, whereby + the endian-ness of the doubles matches the endian-ness + of the memory architecture. + + -mfpu=fpa This is when -mhard-float is specified. + [It is not known if any XScale's have been made with + hardware floating point support, but nevertheless this + is what happens]. + + -mfpu=softfpa This is when -msoft-float is specified. + This is the normal behavior of other arm configurations, + which for backwards compatibility purposes default to + supporting the old FPA format which was always big + endian, regardless of the endian-ness of the memory + system. */ + +#define SUBTARGET_EXTRA_ASM_SPEC "%{!mcpu=*:-mcpu=xscale} \ + %{mhard-float:-mfpu=fpa} \ + %{!mhard-float: %{msoft-float:-mfpu=softfpa;:-mfpu=softvfp}}" #ifndef MULTILIB_DEFAULTS #define MULTILIB_DEFAULTS \ |
