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| author | kan <kan@FreeBSD.org> | 2003-07-11 03:40:53 +0000 |
|---|---|---|
| committer | kan <kan@FreeBSD.org> | 2003-07-11 03:40:53 +0000 |
| commit | 0d580365624a5c68f9e5e130f0e54fe4c8b96822 (patch) | |
| tree | c88ded260c2df3d4e9e8c72b19fd37a187d8c7af /contrib/gcc/config/alpha | |
| parent | 9404c74f6c7843b012abf90228de7908fba1093a (diff) | |
| parent | b2a8872fbe1ec1c49094559ac7b78e6ea4ab7180 (diff) | |
| download | FreeBSD-src-0d580365624a5c68f9e5e130f0e54fe4c8b96822.zip FreeBSD-src-0d580365624a5c68f9e5e130f0e54fe4c8b96822.tar.gz | |
This commit was generated by cvs2svn to compensate for changes in r117395,
which included commits to RCS files with non-trunk default branches.
Diffstat (limited to 'contrib/gcc/config/alpha')
24 files changed, 2224 insertions, 1044 deletions
diff --git a/contrib/gcc/config/alpha/alpha-interix.h b/contrib/gcc/config/alpha/alpha-interix.h index 4dc2186..3f1580d 100644 --- a/contrib/gcc/config/alpha/alpha-interix.h +++ b/contrib/gcc/config/alpha/alpha-interix.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for DEC Alpha running Windows/NT. - Copyright (C) 1995, 1996, 1999, 2000 Free Software Foundation, Inc. + Copyright (C) 1995, 1996, 1999, 2000, 2002 Free Software Foundation, Inc. Donn Terry, Softway Systems, Inc. From code @@ -25,15 +25,18 @@ Boston, MA 02111-1307, USA. */ /* cpp handles __STDC__ */ /* The three "Alpha" defines on the first such line are from the CLAXP spec */ -#undef CPP_PREDEFINES -#define CPP_PREDEFINES " \ - -D__INTERIX \ - -D__OPENNT \ - -D__Alpha_AXP -D_M_ALPHA -D_ALPHA_ \ - -D__alpha -D__alpha__\ - -D__stdcall= \ - -D__cdecl= \ - -Asystem=unix -Asystem=interix -Acpu=alpha -Amachine=alpha" +#define TARGET_OS_CPP_BUILTINS() \ + do { \ + builtin_define ("__INTERIX"); \ + builtin_define ("__OPENNT"); \ + builtin_define ("__Alpha_AXP"); \ + builtin_define ("_M_ALPHA"); \ + builtin_define ("_ALPHA_"); \ + builtin_define ("__stdcall="); \ + builtin_define ("__cdecl="); \ + builtin_assert ("system=unix"); \ + builtin_assert ("system=interix"); \ + } while (0) #undef CPP_SUBTARGET_SPEC #define CPP_SUBTARGET_SPEC "\ @@ -64,17 +67,9 @@ Boston, MA 02111-1307, USA. */ /* The following are needed for C++, but also needed for profiling */ -/* Support const sections and the ctors and dtors sections for g++. - Note that there appears to be two different ways to support const - sections at the moment. You can either #define the symbol - READONLY_DATA_SECTION (giving it some code which switches to the - readonly data section) or else you can #define the symbols - EXTRA_SECTIONS, EXTRA_SECTION_FUNCTIONS, SELECT_SECTION, and - SELECT_RTX_SECTION. We do both here just to be on the safe side. */ +/* Support const sections and the ctors and dtors sections for g++. */ -#define USE_CONST_SECTION 1 - -#define CONST_SECTION_ASM_OP "\t.rdata" +#define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* Define the pseudo-ops used to switch to the .ctors and .dtors sections. @@ -94,38 +89,6 @@ Boston, MA 02111-1307, USA. */ #define CTORS_SECTION_ASM_OP "\t.ctors" #define DTORS_SECTION_ASM_OP "\t.dtors" -/* A default list of other sections which we might be "in" at any given - time. For targets that use additional sections (e.g. .tdesc) you - should override this definition in the target-specific file which - includes this file. */ - -#undef EXTRA_SECTIONS -#define EXTRA_SECTIONS in_const - -/* A default list of extra section function definitions. For targets - that use additional sections (e.g. .tdesc) you should override this - definition in the target-specific file which includes this file. */ - -#undef EXTRA_SECTION_FUNCTIONS -#define EXTRA_SECTION_FUNCTIONS \ - CONST_SECTION_FUNCTION - -#undef READONLY_DATA_SECTION -#define READONLY_DATA_SECTION() const_section () - -#define CONST_SECTION_FUNCTION \ -void \ -const_section () \ -{ \ - if (!USE_CONST_SECTION) \ - text_section(); \ - else if (in_section != in_const) \ - { \ - fprintf (asm_out_file, "%s\n", CONST_SECTION_ASM_OP); \ - in_section = in_const; \ - } \ -} - /* The linker will take care of this, and having them causes problems with ld -r (specifically -rU). */ #define CTOR_LISTS_DEFINED_EXTERNALLY 1 @@ -185,15 +148,3 @@ while (0) fprintf (FILE, "\t.globl\t__fltused\n"); \ ASM_OUTPUT_SOURCE_FILENAME (FILE, main_input_filename); \ } - -/* The current Interix assembler (consistent with the DEC documentation) - uses a=b NOT .set a,b; .set is for assembler options. */ -#undef ASM_OUTPUT_DEFINE_LABEL_DIFFERENCE_SYMBOL -#define ASM_OUTPUT_DEFINE_LABEL_DIFFERENCE_SYMBOL(FILE, SY, HI, LO) \ - do { \ - assemble_name (FILE, SY); \ - fputc ('=', FILE); \ - assemble_name (FILE, HI); \ - fputc ('-', FILE); \ - assemble_name (FILE, LO); \ - } while (0) diff --git a/contrib/gcc/config/alpha/alpha-protos.h b/contrib/gcc/config/alpha/alpha-protos.h index c6fdd04..fe4943b 100644 --- a/contrib/gcc/config/alpha/alpha-protos.h +++ b/contrib/gcc/config/alpha/alpha-protos.h @@ -1,5 +1,5 @@ /* Prototypes for alpha.c functions used in the md file & elsewhere. - Copyright (C) 1999, 2000 Free Software Foundation, Inc. + Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc. This file is part of GNU CC. @@ -34,10 +34,10 @@ extern void alpha_expand_epilogue PARAMS ((void)); extern void alpha_output_filename PARAMS ((FILE *, const char *)); extern void alpha_output_lineno PARAMS ((FILE *, int)); -#ifdef RTX_CODE extern int reg_or_0_operand PARAMS ((rtx, enum machine_mode)); extern int reg_or_6bit_operand PARAMS ((rtx, enum machine_mode)); extern int reg_or_8bit_operand PARAMS ((rtx, enum machine_mode)); +extern int reg_or_const_int_operand PARAMS ((rtx, enum machine_mode)); extern int cint8_operand PARAMS ((rtx, enum machine_mode)); extern int add_operand PARAMS ((rtx, enum machine_mode)); extern int sext_add_operand PARAMS ((rtx, enum machine_mode)); @@ -47,8 +47,7 @@ extern int or_operand PARAMS ((rtx, enum machine_mode)); extern int mode_width_operand PARAMS ((rtx, enum machine_mode)); extern int mode_mask_operand PARAMS ((rtx, enum machine_mode)); extern int mul8_operand PARAMS ((rtx, enum machine_mode)); -extern int fp0_operand PARAMS ((rtx, enum machine_mode)); -extern int reg_or_fp0_operand PARAMS ((rtx, enum machine_mode)); +extern int const0_operand PARAMS ((rtx, enum machine_mode)); extern int hard_fp_register_operand PARAMS ((rtx, enum machine_mode)); extern int hard_int_register_operand PARAMS ((rtx, enum machine_mode)); extern int reg_or_cint_operand PARAMS ((rtx, enum machine_mode)); @@ -61,6 +60,12 @@ extern int local_symbolic_operand PARAMS ((rtx, enum machine_mode)); extern int small_symbolic_operand PARAMS ((rtx, enum machine_mode)); extern int some_small_symbolic_operand PARAMS ((rtx, enum machine_mode)); extern int global_symbolic_operand PARAMS ((rtx, enum machine_mode)); +extern int dtp16_symbolic_operand PARAMS ((rtx, enum machine_mode)); +extern int dtp32_symbolic_operand PARAMS ((rtx, enum machine_mode)); +extern int gotdtp_symbolic_operand PARAMS ((rtx, enum machine_mode)); +extern int tp16_symbolic_operand PARAMS ((rtx, enum machine_mode)); +extern int tp32_symbolic_operand PARAMS ((rtx, enum machine_mode)); +extern int gottp_symbolic_operand PARAMS ((rtx, enum machine_mode)); extern int call_operand PARAMS ((rtx, enum machine_mode)); extern int symbolic_operand PARAMS ((rtx, enum machine_mode)); extern int alpha_comparison_operator PARAMS ((rtx, enum machine_mode)); @@ -108,13 +113,7 @@ extern rtx alpha_emit_set_long_const PARAMS ((rtx, HOST_WIDE_INT, extern bool alpha_expand_mov PARAMS ((enum machine_mode, rtx *)); extern bool alpha_expand_mov_nobwx PARAMS ((enum machine_mode, rtx *)); extern void alpha_emit_floatuns PARAMS ((rtx[])); -extern rtx alpha_emit_conditional_branch PARAMS ((enum rtx_code)); -extern rtx alpha_emit_setcc PARAMS ((enum rtx_code)); extern rtx alpha_emit_conditional_move PARAMS ((rtx, enum machine_mode)); -extern int alpha_split_conditional_move PARAMS ((enum rtx_code, rtx, rtx, - rtx, rtx)); -extern void alpha_emit_xfloating_arith PARAMS ((enum rtx_code, rtx[])); -extern void alpha_emit_xfloating_cvt PARAMS ((enum rtx_code, rtx[])); extern void alpha_split_tfmode_pair PARAMS ((rtx[])); extern void alpha_split_tfmode_frobsign PARAMS ((rtx[], rtx (*)(rtx, rtx, rtx))); @@ -124,61 +123,55 @@ extern void alpha_expand_unaligned_store PARAMS ((rtx, rtx, HOST_WIDE_INT, HOST_WIDE_INT)); extern int alpha_expand_block_move PARAMS ((rtx [])); extern int alpha_expand_block_clear PARAMS ((rtx [])); +extern rtx alpha_expand_zap_mask PARAMS ((HOST_WIDE_INT)); +extern void alpha_expand_builtin_vector_binop PARAMS ((rtx (*)(rtx, rtx, rtx), + enum machine_mode, + rtx, rtx, rtx)); extern rtx alpha_return_addr PARAMS ((int, rtx)); extern rtx alpha_gp_save_rtx PARAMS ((void)); extern void print_operand PARAMS ((FILE *, rtx, int)); extern void print_operand_address PARAMS ((FILE *, rtx)); extern void alpha_initialize_trampoline PARAMS ((rtx, rtx, rtx, int, int, int)); extern void alpha_reorg PARAMS ((rtx)); -#endif /* RTX_CODE */ + +extern tree alpha_build_va_list PARAMS ((void)); +extern void alpha_va_start PARAMS ((tree, rtx)); +extern rtx alpha_va_arg PARAMS ((tree, tree)); +extern rtx function_arg PARAMS ((CUMULATIVE_ARGS, enum machine_mode, + tree, int)); +extern void alpha_start_function PARAMS ((FILE *, const char *, tree)); +extern void alpha_end_function PARAMS ((FILE *, const char *, tree)); + +extern int alpha_find_lo_sum_using_gp PARAMS ((rtx)); #ifdef REAL_VALUE_TYPE extern int check_float_value PARAMS ((enum machine_mode, - REAL_VALUE_TYPE *, int)); + REAL_VALUE_TYPE *, int)); #endif -#if TARGET_ABI_OPEN_VMS -#ifdef HAVE_MACHINE_MODES -extern enum avms_arg_type alpha_arg_type PARAMS ((enum machine_mode)); -#endif #ifdef RTX_CODE -extern rtx alpha_arg_info_reg_val PARAMS ((CUMULATIVE_ARGS)); -#endif -#ifdef BUFSIZ -extern void alpha_write_linkage PARAMS ((FILE *)); +extern rtx alpha_emit_conditional_branch PARAMS ((enum rtx_code)); +extern rtx alpha_emit_setcc PARAMS ((enum rtx_code)); +extern int alpha_split_conditional_move PARAMS ((enum rtx_code, rtx, rtx, + rtx, rtx)); +extern void alpha_emit_xfloating_arith PARAMS ((enum rtx_code, rtx[])); +extern void alpha_emit_xfloating_cvt PARAMS ((enum rtx_code, rtx[])); #endif -#endif /* TARGET_ABI_OPEN_VMS */ -#ifdef RTX_CODE extern rtx alpha_need_linkage PARAMS ((const char *, int)); -#endif +extern rtx alpha_use_linkage PARAMS ((rtx, tree, int, int)); -#ifdef TREE_CODE -extern tree alpha_build_va_list PARAMS ((void)); -#ifdef RTX_CODE -extern void alpha_va_start PARAMS ((int, tree, rtx)); -extern rtx alpha_va_arg PARAMS ((tree, tree)); -extern rtx function_arg PARAMS ((CUMULATIVE_ARGS, enum machine_mode, - tree, int)); +#if TARGET_ABI_OPEN_VMS +#ifdef HAVE_MACHINE_MODES +extern enum avms_arg_type alpha_arg_type PARAMS ((enum machine_mode)); #endif -extern void alpha_start_function PARAMS ((FILE *, const char *, tree)); -extern void alpha_end_function PARAMS ((FILE *, const char *, tree)); -extern void alpha_output_mi_thunk_osf PARAMS ((FILE *, tree, - HOST_WIDE_INT, tree)); -extern void alpha_encode_section_info PARAMS ((tree)); -#endif /* TREE CODE */ +extern rtx alpha_arg_info_reg_val PARAMS ((CUMULATIVE_ARGS)); +#endif /* TARGET_ABI_OPEN_VMS */ -#ifdef RTX_CODE extern rtx unicosmk_add_call_info_word PARAMS ((rtx)); -#endif #if TARGET_ABI_UNICOSMK -#ifdef RTX_CODE extern void unicosmk_defer_case_vector PARAMS ((rtx, rtx)); -#endif -#ifdef TREE_CODE -extern void unicosmk_unique_section PARAMS ((tree, int)); -#endif extern void unicosmk_add_extern PARAMS ((const char *)); extern void unicosmk_output_align PARAMS ((FILE *, int)); extern char * unicosmk_text_section PARAMS ((void)); diff --git a/contrib/gcc/config/alpha/alpha.h b/contrib/gcc/config/alpha/alpha.h index 4410a86..b933ea3 100644 --- a/contrib/gcc/config/alpha/alpha.h +++ b/contrib/gcc/config/alpha/alpha.h @@ -20,24 +20,81 @@ along with GNU CC; see the file COPYING. If not, write to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +/* Target CPU builtins. */ +#define TARGET_CPU_CPP_BUILTINS() \ + do \ + { \ + builtin_define ("__alpha"); \ + builtin_define ("__alpha__"); \ + builtin_assert ("cpu=alpha"); \ + builtin_assert ("machine=alpha"); \ + if (TARGET_CIX) \ + { \ + builtin_define ("__alpha_cix__"); \ + builtin_assert ("cpu=cix"); \ + } \ + if (TARGET_FIX) \ + { \ + builtin_define ("__alpha_fix__"); \ + builtin_assert ("cpu=fix"); \ + } \ + if (TARGET_BWX) \ + { \ + builtin_define ("__alpha_bwx__"); \ + builtin_assert ("cpu=bwx"); \ + } \ + if (TARGET_MAX) \ + { \ + builtin_define ("__alpha_max__"); \ + builtin_assert ("cpu=max"); \ + } \ + if (TARGET_CPU_EV6) \ + { \ + builtin_define ("__alpha_ev6__"); \ + builtin_assert ("cpu=ev6"); \ + } \ + else if (TARGET_CPU_EV5) \ + { \ + builtin_define ("__alpha_ev5__"); \ + builtin_assert ("cpu=ev5"); \ + } \ + else /* Presumably ev4. */ \ + { \ + builtin_define ("__alpha_ev4__"); \ + builtin_assert ("cpu=ev4"); \ + } \ + if (TARGET_IEEE || TARGET_IEEE_WITH_INEXACT) \ + builtin_define ("_IEEE_FP"); \ + if (TARGET_IEEE_WITH_INEXACT) \ + builtin_define ("_IEEE_FP_INEXACT"); \ + \ + /* Macros dependent on the C dialect. */ \ + SUBTARGET_LANGUAGE_CPP_BUILTINS(); \ +} while (0) + +#ifndef SUBTARGET_LANGUAGE_CPP_BUILTINS +#define SUBTARGET_LANGUAGE_CPP_BUILTINS() \ + do \ + { \ + if (preprocessing_asm_p ()) \ + builtin_define_std ("LANGUAGE_ASSEMBLY"); \ + else if (c_language == clk_c) \ + builtin_define_std ("LANGUAGE_C"); \ + else if (c_language == clk_cplusplus) \ + { \ + builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \ + builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \ + } \ + if (flag_objc) \ + { \ + builtin_define ("__LANGUAGE_OBJECTIVE_C"); \ + builtin_define ("__LANGUAGE_OBJECTIVE_C__"); \ + } \ + } \ + while (0) +#endif -/* For C++ we need to ensure that __LANGUAGE_C_PLUS_PLUS is defined independent - of the source file extension. */ -#define CPLUSPLUS_CPP_SPEC "\ --D__LANGUAGE_C_PLUS_PLUS__ -D__LANGUAGE_C_PLUS_PLUS -D__cplusplus \ -%(cpp) \ -" - -/* Write out the correct language type definition for the header files. - Unless we have assembler language, write out the symbols for C. */ -#define CPP_SPEC "\ -%{!undef:\ -%{.S:-D__LANGUAGE_ASSEMBLY__ -D__LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY }}\ -%{.m:-D__LANGUAGE_OBJECTIVE_C__ -D__LANGUAGE_OBJECTIVE_C }\ -%{!.S:%{!.cc:%{!.cxx:%{!.cpp:%{!.cp:%{!.c++:%{!.C:%{!.m:-D__LANGUAGE_C__ -D__LANGUAGE_C %{!ansi:-DLANGUAGE_C }}}}}}}}}\ -%{mieee:-D_IEEE_FP }\ -%{mieee-with-inexact:-D_IEEE_FP -D_IEEE_FP_INEXACT }}\ -%(cpp_cpu) %(cpp_subtarget)" +#define CPP_SPEC "%(cpp_subtarget)" #ifndef CPP_SUBTARGET_SPEC #define CPP_SUBTARGET_SPEC "" @@ -89,6 +146,7 @@ extern int target_flags; extern enum alpha_trap_precision alpha_tp; extern enum alpha_fp_rounding_mode alpha_fprm; extern enum alpha_fp_trap_mode alpha_fptm; +extern int alpha_tls_size; /* This means that floating-point support exists in the target implementation of the Alpha architecture. This is usually the default. */ @@ -160,6 +218,10 @@ extern enum alpha_fp_trap_mode alpha_fptm; #define MASK_SMALL_DATA (1 << 13) #define TARGET_SMALL_DATA (target_flags & MASK_SMALL_DATA) +/* This means emit thread pointer loads for kernel not user. */ +#define MASK_TLS_KERNEL (1 << 14) +#define TARGET_TLS_KERNEL (target_flags & MASK_TLS_KERNEL) + /* This means that the processor is an EV5, EV56, or PCA56. Unlike alpha_cpu this is not affected by -mtune= setting. */ #define MASK_CPU_EV5 (1 << 28) @@ -203,6 +265,9 @@ extern enum alpha_fp_trap_mode alpha_fptm; #ifndef TARGET_FIXUP_EV5_PREFETCH #define TARGET_FIXUP_EV5_PREFETCH 0 #endif +#ifndef HAVE_AS_TLS +#define HAVE_AS_TLS 0 +#endif /* Macro to define tables used to set the flags. This is a list in braces of pairs in braces, @@ -245,6 +310,8 @@ extern enum alpha_fp_trap_mode alpha_fptm; N_("Emit 16-bit relocations to the small data areas")}, \ {"large-data", -MASK_SMALL_DATA, \ N_("Emit 32-bit relocations to the small data areas")}, \ + {"tls-kernel", MASK_TLS_KERNEL, \ + N_("Emit rdval instead of rduniq for thread pointer")}, \ {"", TARGET_DEFAULT | TARGET_CPU_DEFAULT \ | TARGET_DEFAULT_EXPLICIT_RELOCS, ""} } @@ -268,6 +335,7 @@ extern const char *alpha_fprm_string; /* For -mfp-rounding-mode=[n|m|c|d] */ extern const char *alpha_fptm_string; /* For -mfp-trap-mode=[n|u|su|sui] */ extern const char *alpha_tp_string; /* For -mtrap-precision=[p|f|i] */ extern const char *alpha_mlat_string; /* For -mmemory-latency= */ +extern const char *alpha_tls_size_string; /* For -mtls-size= */ #define TARGET_OPTIONS \ { \ @@ -283,67 +351,10 @@ extern const char *alpha_mlat_string; /* For -mmemory-latency= */ N_("Control the precision given to fp exceptions")}, \ {"memory-latency=", &alpha_mlat_string, \ N_("Tune expected memory latency")}, \ + {"tls-size=", &alpha_tls_size_string, \ + N_("Specify bit size of immediate TLS offsets")}, \ } -/* Attempt to describe CPU characteristics to the preprocessor. */ - -/* Corresponding to amask... */ -#define CPP_AM_BWX_SPEC "-D__alpha_bwx__ -Acpu=bwx" -#define CPP_AM_MAX_SPEC "-D__alpha_max__ -Acpu=max" -#define CPP_AM_FIX_SPEC "-D__alpha_fix__ -Acpu=fix" -#define CPP_AM_CIX_SPEC "-D__alpha_cix__ -Acpu=cix" - -/* Corresponding to implver... */ -#define CPP_IM_EV4_SPEC "-D__alpha_ev4__ -Acpu=ev4" -#define CPP_IM_EV5_SPEC "-D__alpha_ev5__ -Acpu=ev5" -#define CPP_IM_EV6_SPEC "-D__alpha_ev6__ -Acpu=ev6" - -/* Common combinations. */ -#define CPP_CPU_EV4_SPEC "%(cpp_im_ev4)" -#define CPP_CPU_EV5_SPEC "%(cpp_im_ev5)" -#define CPP_CPU_EV56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx)" -#define CPP_CPU_PCA56_SPEC "%(cpp_im_ev5) %(cpp_am_bwx) %(cpp_am_max)" -#define CPP_CPU_EV6_SPEC \ - "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_fix)" -#define CPP_CPU_EV67_SPEC \ - "%(cpp_im_ev6) %(cpp_am_bwx) %(cpp_am_max) %(cpp_am_fix) %(cpp_am_cix)" - -#ifndef CPP_CPU_DEFAULT_SPEC -# if TARGET_CPU_DEFAULT & MASK_CPU_EV6 -# if TARGET_CPU_DEFAULT & MASK_CIX -# define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV67_SPEC -# else -# define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV6_SPEC -# endif -# else -# if TARGET_CPU_DEFAULT & MASK_CPU_EV5 -# if TARGET_CPU_DEFAULT & MASK_MAX -# define CPP_CPU_DEFAULT_SPEC CPP_CPU_PCA56_SPEC -# else -# if TARGET_CPU_DEFAULT & MASK_BWX -# define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV56_SPEC -# else -# define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV5_SPEC -# endif -# endif -# else -# define CPP_CPU_DEFAULT_SPEC CPP_CPU_EV4_SPEC -# endif -# endif -#endif /* CPP_CPU_DEFAULT_SPEC */ - -#ifndef CPP_CPU_SPEC -#define CPP_CPU_SPEC "\ -%{!undef:-Acpu=alpha -Amachine=alpha -D__alpha -D__alpha__ \ -%{mcpu=ev4|mcpu=21064:%(cpp_cpu_ev4) }\ -%{mcpu=ev5|mcpu=21164:%(cpp_cpu_ev5) }\ -%{mcpu=ev56|mcpu=21164a:%(cpp_cpu_ev56) }\ -%{mcpu=pca56|mcpu=21164pc|mcpu=21164PC:%(cpp_cpu_pca56) }\ -%{mcpu=ev6|mcpu=21264:%(cpp_cpu_ev6) }\ -%{mcpu=ev67|mcpu=21264a:%(cpp_cpu_ev67) }\ -%{!mcpu*:%(cpp_cpu_default) }}" -#endif - /* This macro defines names of additional specifications to put in the specs that can be used in various specifications like CC1_SPEC. Its definition is an initializer with a subgrouping for each command option. @@ -359,21 +370,6 @@ extern const char *alpha_mlat_string; /* For -mmemory-latency= */ #endif #define EXTRA_SPECS \ - { "cpp_am_bwx", CPP_AM_BWX_SPEC }, \ - { "cpp_am_max", CPP_AM_MAX_SPEC }, \ - { "cpp_am_fix", CPP_AM_FIX_SPEC }, \ - { "cpp_am_cix", CPP_AM_CIX_SPEC }, \ - { "cpp_im_ev4", CPP_IM_EV4_SPEC }, \ - { "cpp_im_ev5", CPP_IM_EV5_SPEC }, \ - { "cpp_im_ev6", CPP_IM_EV6_SPEC }, \ - { "cpp_cpu_ev4", CPP_CPU_EV4_SPEC }, \ - { "cpp_cpu_ev5", CPP_CPU_EV5_SPEC }, \ - { "cpp_cpu_ev56", CPP_CPU_EV56_SPEC }, \ - { "cpp_cpu_pca56", CPP_CPU_PCA56_SPEC }, \ - { "cpp_cpu_ev6", CPP_CPU_EV6_SPEC }, \ - { "cpp_cpu_ev67", CPP_CPU_EV67_SPEC }, \ - { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ - { "cpp_cpu", CPP_CPU_SPEC }, \ { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ SUBTARGET_EXTRA_SPECS @@ -409,15 +405,16 @@ extern const char *alpha_mlat_string; /* For -mmemory-latency= */ /* target machine storage layout */ -/* Define to enable software floating point emulation. */ -#define REAL_ARITHMETIC - /* Define the size of `int'. The default is the same as the word size. */ #define INT_TYPE_SIZE 32 /* Define the size of `long long'. The default is the twice the word size. */ #define LONG_LONG_TYPE_SIZE 64 +/* We're IEEE unless someone says to use VAX. */ +#define TARGET_FLOAT_FORMAT \ + (TARGET_FLOAT_VAX ? VAX_FLOAT_FORMAT : IEEE_FLOAT_FORMAT) + /* The two floating-point formats we support are S-floating, which is 4 bytes, and T-floating, which is 8 bytes. `float' is S and `double' and `long double' are T. */ @@ -474,15 +471,6 @@ extern const char *alpha_mlat_string; /* For -mmemory-latency= */ for them. Might as well be consistent with bytes. */ #define WORDS_BIG_ENDIAN 0 -/* number of bits in an addressable storage unit */ -#define BITS_PER_UNIT 8 - -/* Width in bits of a "word", which is the contents of a machine register. - Note that this is not necessarily the width of data type `int'; - if using 16-bit ints on a 68000, this would still be 32. - But on a machine with 16-bit registers, this would be 16. */ -#define BITS_PER_WORD 64 - /* Width of a word, in units (bytes). */ #define UNITS_PER_WORD 8 @@ -505,7 +493,7 @@ extern const char *alpha_mlat_string; /* For -mmemory-latency= */ /* Every structure's size must be a multiple of this. */ #define STRUCTURE_SIZE_BOUNDARY 8 -/* A bitfield declared as `int' forces `int' alignment for the struct. */ +/* A bit-field declared as `int' forces `int' alignment for the struct. */ #define PCC_BITFIELD_TYPE_MATTERS 1 /* No data type wants to be aligned rounder than this. */ @@ -524,14 +512,14 @@ extern const char *alpha_mlat_string; /* For -mmemory-latency= */ #define DATA_ALIGNMENT(EXP, ALIGN) MAX ((ALIGN), BITS_PER_WORD) #endif -/* Set this non-zero if move instructions will actually fail to work +/* Set this nonzero if move instructions will actually fail to work when given unaligned data. Since we get an error message when we do one, call them invalid. */ #define STRICT_ALIGNMENT 1 -/* Set this non-zero if unaligned move instructions are extremely slow. +/* Set this nonzero if unaligned move instructions are extremely slow. On the Alpha, they trap. */ @@ -640,6 +628,12 @@ extern const char *alpha_mlat_string; /* For -mmemory-latency= */ ? GET_MODE_UNIT_SIZE (MODE) == 8 || GET_MODE_UNIT_SIZE (MODE) == 4 \ : 1) +/* Value is 1 if MODE is a supported vector mode. */ + +#define VECTOR_MODE_SUPPORTED_P(MODE) \ + (TARGET_MAX \ + && ((MODE) == V8QImode || (MODE) == V4HImode || (MODE) == V2SImode)) + /* A C expression that is nonzero if a value of mode MODE1 is accessible in mode MODE2 without copying. @@ -719,7 +713,7 @@ extern const char *alpha_mlat_string; /* For -mmemory-latency= */ class that represents their union. */ enum reg_class { - NO_REGS, R24_REG, R25_REG, R27_REG, + NO_REGS, R0_REG, R24_REG, R25_REG, R27_REG, GENERAL_REGS, FLOAT_REGS, ALL_REGS, LIM_REG_CLASSES }; @@ -728,8 +722,8 @@ enum reg_class { /* Give names of register classes as strings for dump file. */ -#define REG_CLASS_NAMES \ - {"NO_REGS", "R24_REG", "R25_REG", "R27_REG", \ +#define REG_CLASS_NAMES \ + {"NO_REGS", "R0_REG", "R24_REG", "R25_REG", "R27_REG", \ "GENERAL_REGS", "FLOAT_REGS", "ALL_REGS" } /* Define which registers fit in which classes. @@ -738,6 +732,7 @@ enum reg_class { #define REG_CLASS_CONTENTS \ { {0x00000000, 0x00000000}, /* NO_REGS */ \ + {0x00000001, 0x00000000}, /* R0_REG */ \ {0x01000000, 0x00000000}, /* R24_REG */ \ {0x02000000, 0x00000000}, /* R25_REG */ \ {0x08000000, 0x00000000}, /* R27_REG */ \ @@ -751,7 +746,8 @@ enum reg_class { or could index an array. */ #define REGNO_REG_CLASS(REGNO) \ - ((REGNO) == 24 ? R24_REG \ + ((REGNO) == 0 ? R0_REG \ + : (REGNO) == 24 ? R24_REG \ : (REGNO) == 25 ? R25_REG \ : (REGNO) == 27 ? R27_REG \ : (REGNO) >= 32 && (REGNO) <= 62 ? FLOAT_REGS \ @@ -768,6 +764,7 @@ enum reg_class { : (C) == 'b' ? R25_REG \ : (C) == 'c' ? R27_REG \ : (C) == 'f' ? FLOAT_REGS \ + : (C) == 'v' ? R0_REG \ : NO_REGS) /* Define this macro to change register usage conditional on target flags. */ @@ -811,7 +808,9 @@ enum reg_class { 'T' is a HIGH. - 'U' is a symbolic operand. */ + 'U' is a symbolic operand. + + 'W' is a vector zero. */ #define EXTRA_CONSTRAINT alpha_extra_constraint @@ -858,15 +857,11 @@ enum reg_class { #define CLASS_MAX_NREGS(CLASS, MODE) \ ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) -/* If defined, gives a class of registers that cannot be used as the - operand of a SUBREG that changes the mode of the object illegally. */ - -#define CLASS_CANNOT_CHANGE_MODE FLOAT_REGS +/* Return the class of registers that cannot change mode from FROM to TO. */ -/* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */ - -#define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \ - (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO)) +#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ + (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ + ? reg_classes_intersect_p (FLOAT_REGS, CLASS) : 0) /* Define the cost of moving between registers of various classes. Moving between FLOAT_REGS and anything else except float regs is expensive. @@ -1172,12 +1167,11 @@ extern int alpha_memory_latency; /* We do not allow indirect calls to be optimized into sibling calls, nor can we allow a call to a function in a different compilation unit to - be optimized into a sibcall. Except if the function is known not to - return, in which case our caller doesn't care what the gp is. */ + be optimized into a sibcall. */ #define FUNCTION_OK_FOR_SIBCALL(DECL) \ (DECL \ - && ((TREE_ASM_WRITTEN (DECL) && !flag_pic) \ - || ! TREE_PUBLIC (DECL))) + && (! TREE_PUBLIC (DECL) \ + || (TREE_ASM_WRITTEN (DECL) && (*targetm.binds_local_p) (DECL)))) /* Try to output insns to set TARGET equal to the constant C if it can be done in less than N insns. Do all computations in MODE. Returns the place @@ -1474,7 +1468,7 @@ do { \ #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) /* Nonzero if access to memory by bytes is no faster than for words. - Also non-zero if doing byte operations (specifically shifts) in registers + Also nonzero if doing byte operations (specifically shifts) in registers is undesirable. On the Alpha, we want to not use the byte operation and instead use @@ -1730,60 +1724,6 @@ do { \ #define DATA_SECTION_ASM_OP "\t.data" -/* Define an extra section for read-only data, a routine to enter it, and - indicate that it is for read-only data. - - The first time we enter the readonly data section for a file, we write - eight bytes of zero. This works around a bug in DEC's assembler in - some versions of OSF/1 V3.x. */ - -#define EXTRA_SECTIONS readonly_data - -#define EXTRA_SECTION_FUNCTIONS \ -void \ -literal_section () \ -{ \ - if (in_section != readonly_data) \ - { \ - static int firsttime = 1; \ - \ - fprintf (asm_out_file, "%s\n", READONLY_DATA_SECTION_ASM_OP); \ - if (firsttime) \ - { \ - firsttime = 0; \ - assemble_aligned_integer (8, const0_rtx); \ - } \ - \ - in_section = readonly_data; \ - } \ -} \ - -#define READONLY_DATA_SECTION literal_section - -/* Define this macro if references to a symbol must be treated differently - depending on something about the variable or function named by the symbol - (such as what section it is in). */ - -#define ENCODE_SECTION_INFO(DECL) alpha_encode_section_info (DECL) - -/* If a variable is weakened, made one only or moved into a different - section, it may be necessary to redo the section info to move the - variable out of sdata. */ - -#define REDO_SECTION_INFO_P(DECL) \ - ((TREE_CODE (DECL) == VAR_DECL) \ - && (DECL_ONE_ONLY (DECL) || DECL_WEAK (DECL) || DECL_COMMON (DECL) \ - || DECL_SECTION_NAME (DECL) != 0)) - -#define STRIP_NAME_ENCODING(VAR,SYMBOL_NAME) \ -do { \ - (VAR) = (SYMBOL_NAME); \ - if ((VAR)[0] == '@') \ - (VAR) += 2; \ - if ((VAR)[0] == '*') \ - (VAR)++; \ -} while (0) - /* How to refer to registers in assembler output. This sequence is indexed by compiler's hard-register-number (see above). */ @@ -1802,7 +1742,7 @@ do { \ #define ASM_OUTPUT_LABELREF(STREAM, NAME) \ do { \ const char *name_ = NAME; \ - if (*name_ == '@') \ + if (*name_ == '@' || *name_ == '%') \ name_ += 2; \ if (*name_ == '*') \ name_++; \ @@ -1811,17 +1751,8 @@ do { \ fputs (name_, STREAM); \ } while (0) -/* This is how to output the definition of a user-level label named NAME, - such as the label on a static function or variable NAME. */ - -#define ASM_OUTPUT_LABEL(FILE,NAME) \ - do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) - -/* This is how to output a command to make the user-level label named NAME - defined for reference from other files. */ - -#define ASM_GLOBALIZE_LABEL(FILE,NAME) \ - do { fputs ("\t.globl ", FILE); assemble_name (FILE, NAME); fputs ("\n", FILE);} while (0) +/* Globalizing directive for a label. */ +#define GLOBAL_ASM_OP "\t.globl " /* The prefix to add to user-visible assembler symbols. */ @@ -1848,11 +1779,6 @@ do { \ #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ sprintf ((LABEL), "*$%s%ld", (PREFIX), (long)(NUM)) -/* Check a floating-point value for validity for a particular machine mode. */ - -#define CHECK_FLOAT_VALUE(MODE, D, OVERFLOW) \ - ((OVERFLOW) = check_float_value (MODE, &D, OVERFLOW)) - /* We use the default ASCII-output routine, except that we don't write more than 50 characters since the assembler doesn't support very long lines. */ @@ -1985,7 +1911,7 @@ do { \ #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ ((CODE) == '/' || (CODE) == ',' || (CODE) == '-' || (CODE) == '~' \ - || (CODE) == '#' || (CODE) == '*') + || (CODE) == '#' || (CODE) == '*' || (CODE) == '&') /* Print a memory address as an operand to reference that memory location. */ @@ -1995,9 +1921,11 @@ do { \ /* Define the codes that are matched by predicates in alpha.c. */ #define PREDICATE_CODES \ - {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \ + {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE, \ + CONST_VECTOR}}, \ {"reg_or_6bit_operand", {SUBREG, REG, CONST_INT}}, \ {"reg_or_8bit_operand", {SUBREG, REG, CONST_INT}}, \ + {"reg_or_const_int_operand", {SUBREG, REG, CONST_INT}}, \ {"cint8_operand", {CONST_INT}}, \ {"reg_or_cint_operand", {SUBREG, REG, CONST_INT}}, \ {"add_operand", {SUBREG, REG, CONST_INT}}, \ @@ -2008,24 +1936,29 @@ do { \ {"mode_mask_operand", {CONST_INT}}, \ {"mul8_operand", {CONST_INT}}, \ {"mode_width_operand", {CONST_INT}}, \ - {"reg_or_fp0_operand", {SUBREG, REG, CONST_DOUBLE}}, \ {"alpha_comparison_operator", {EQ, LE, LT, LEU, LTU}}, \ {"alpha_zero_comparison_operator", {EQ, NE, LE, LT, LEU, LTU}}, \ {"alpha_swapped_comparison_operator", {EQ, GE, GT, GEU, GTU}}, \ {"signed_comparison_operator", {EQ, NE, LE, LT, GE, GT}}, \ {"alpha_fp_comparison_operator", {EQ, LE, LT, UNORDERED}}, \ {"divmod_operator", {DIV, MOD, UDIV, UMOD}}, \ - {"fp0_operand", {CONST_DOUBLE}}, \ + {"const0_operand", {CONST_INT, CONST_DOUBLE, CONST_VECTOR}}, \ {"current_file_function_operand", {SYMBOL_REF}}, \ {"direct_call_operand", {SYMBOL_REF}}, \ {"local_symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \ {"small_symbolic_operand", {SYMBOL_REF, CONST}}, \ {"global_symbolic_operand", {SYMBOL_REF, CONST}}, \ + {"dtp16_symbolic_operand", {CONST}}, \ + {"dtp32_symbolic_operand", {CONST}}, \ + {"gotdtp_symbolic_operand", {CONST}}, \ + {"tp16_symbolic_operand", {CONST}}, \ + {"tp32_symbolic_operand", {CONST}}, \ + {"gottp_symbolic_operand", {CONST}}, \ {"call_operand", {REG, SYMBOL_REF}}, \ {"input_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \ - SYMBOL_REF, CONST, LABEL_REF, HIGH}}, \ + CONST_VECTOR, SYMBOL_REF, CONST, LABEL_REF, HIGH}},\ {"some_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \ - SYMBOL_REF, CONST, LABEL_REF, HIGH}}, \ + CONST_VECTOR, SYMBOL_REF, CONST, LABEL_REF, HIGH}}, \ {"some_ni_operand", {SUBREG, REG, MEM}}, \ {"aligned_memory_operand", {MEM}}, \ {"unaligned_memory_operand", {MEM}}, \ @@ -2045,8 +1978,8 @@ do { \ (VALIST) = alpha_build_va_list () /* Implement `va_start' for varargs and stdarg. */ -#define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \ - alpha_va_start (stdarg, valist, nextarg) +#define EXPAND_BUILTIN_VA_START(valist, nextarg) \ + alpha_va_start (valist, nextarg) /* Implement `va_arg'. */ #define EXPAND_BUILTIN_VA_ARG(valist, type) \ @@ -2061,9 +1994,9 @@ do { \ /* Definitions for debugging. */ -#define SDB_DEBUGGING_INFO /* generate info for mips-tfile */ -#define DBX_DEBUGGING_INFO /* generate embedded stabs */ -#define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */ +#define SDB_DEBUGGING_INFO 1 /* generate info for mips-tfile */ +#define DBX_DEBUGGING_INFO 1 /* generate embedded stabs */ +#define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */ #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */ #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG @@ -2201,8 +2134,3 @@ do { \ /* Generate calls to memcpy, etc., not bcopy, etc. */ #define TARGET_MEM_FUNCTIONS 1 - -/* Output code to add DELTA to the first argument, and then jump to FUNCTION. - Used for C++ multiple inheritance. */ -#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \ - alpha_output_mi_thunk_osf (FILE, THUNK_FNDECL, DELTA, FUNCTION) diff --git a/contrib/gcc/config/alpha/alpha.md b/contrib/gcc/config/alpha/alpha.md index 1875b80..a4c0ae6 100644 --- a/contrib/gcc/config/alpha/alpha.md +++ b/contrib/gcc/config/alpha/alpha.md @@ -1,6 +1,6 @@ ;; Machine description for DEC Alpha for GNU C compiler ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, -;; 2000, 2001 Free Software Foundation, Inc. +;; 2000, 2001, 2002, 2003 Free Software Foundation, Inc. ;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) ;; ;; This file is part of GNU CC. @@ -40,6 +40,24 @@ (UNSPEC_LITUSE 12) (UNSPEC_SIBCALL 13) (UNSPEC_SYMBOL 14) + + ;; TLS Support + (UNSPEC_TLSGD_CALL 15) + (UNSPEC_TLSLDM_CALL 16) + (UNSPEC_TLSGD 17) + (UNSPEC_TLSLDM 18) + (UNSPEC_DTPREL 19) + (UNSPEC_TPREL 20) + (UNSPEC_TP 21) + + ;; Builtins + (UNSPEC_CMPBGE 22) + (UNSPEC_ZAP 23) + (UNSPEC_AMASK 24) + (UNSPEC_IMPLVER 25) + (UNSPEC_PERR 26) + (UNSPEC_CTLZ 27) + (UNSPEC_CTPOP 28) ]) ;; UNSPEC_VOLATILE: @@ -57,6 +75,8 @@ (UNSPECV_FORCE_MOV 9) (UNSPECV_LDGP1 10) (UNSPECV_PLDGP2 11) ; prologue ldgp + (UNSPECV_SET_TP 12) + (UNSPECV_RPCC 13) ]) ;; Where necessary, the suffixes _le and _be are used to distinguish between @@ -77,8 +97,8 @@ ;; separately. (define_attr "type" - "ild,fld,ldsym,ist,fst,ibr,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,\ -fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" + "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov,icmp,imul,\ +fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi,none" (const_string "iadd")) ;; Describe a user's asm statement. @@ -122,314 +142,24 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_attr "length" "" (const_int 4)) - -;; On EV4 there are two classes of resources to consider: resources needed -;; to issue, and resources needed to execute. IBUS[01] are in the first -;; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second. -;; (There are a few other register-like resources, but ...) - -; First, describe all of the issue constraints with single cycle delays. -; All insns need a bus, but all except loads require one or the other. -(define_function_unit "ev4_ibus0" 1 0 - (and (eq_attr "cpu" "ev4") - (eq_attr "type" "fst,fbr,iadd,imul,ilog,shift,icmov,icmp")) - 1 1) - -(define_function_unit "ev4_ibus1" 1 0 - (and (eq_attr "cpu" "ev4") - (eq_attr "type" "ist,ibr,jsr,fadd,fcmov,fcpys,fmul,fdiv,misc")) - 1 1) - -; Memory delivers its result in three cycles. Actually return one and -; take care of this in adjust_cost, since we want to handle user-defined -; memory latencies. -(define_function_unit "ev4_abox" 1 0 - (and (eq_attr "cpu" "ev4") - (eq_attr "type" "ild,fld,ldsym,ist,fst")) - 1 1) - -; Branches have no delay cost, but do tie up the unit for two cycles. -(define_function_unit "ev4_bbox" 1 1 - (and (eq_attr "cpu" "ev4") - (eq_attr "type" "ibr,fbr,jsr")) - 2 2) - -; Arithmetic insns are normally have their results available after -; two cycles. There are a number of exceptions. They are encoded in -; ADJUST_COST. Some of the other insns have similar exceptions. -(define_function_unit "ev4_ebox" 1 0 - (and (eq_attr "cpu" "ev4") - (eq_attr "type" "iadd,ilog,shift,icmov,icmp,misc")) - 2 1) - -(define_function_unit "imul" 1 0 - (and (eq_attr "cpu" "ev4") - (and (eq_attr "type" "imul") - (eq_attr "opsize" "si"))) - 21 19) - -(define_function_unit "imul" 1 0 - (and (eq_attr "cpu" "ev4") - (and (eq_attr "type" "imul") - (eq_attr "opsize" "!si"))) - 23 21) - -(define_function_unit "ev4_fbox" 1 0 - (and (eq_attr "cpu" "ev4") - (eq_attr "type" "fadd,fmul,fcpys,fcmov")) - 6 1) - -(define_function_unit "fdiv" 1 0 - (and (eq_attr "cpu" "ev4") - (and (eq_attr "type" "fdiv") - (eq_attr "opsize" "si"))) - 34 30) - -(define_function_unit "fdiv" 1 0 - (and (eq_attr "cpu" "ev4") - (and (eq_attr "type" "fdiv") - (eq_attr "opsize" "di"))) - 63 59) - -;; EV5 scheduling. EV5 can issue 4 insns per clock. -;; -;; EV5 has two asymetric integer units. Model this with E0 & E1 along -;; with the combined resource EBOX. - -(define_function_unit "ev5_ebox" 2 0 - (and (eq_attr "cpu" "ev5") - (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv")) - 1 1) - -; Memory takes at least 2 clocks. Return one from here and fix up with -; user-defined latencies in adjust_cost. -(define_function_unit "ev5_ebox" 2 0 - (and (eq_attr "cpu" "ev5") - (eq_attr "type" "ild,fld,ldsym")) - 1 1) - -; Loads can dual issue with one another, but loads and stores do not mix. -(define_function_unit "ev5_e0" 1 0 - (and (eq_attr "cpu" "ev5") - (eq_attr "type" "ild,fld,ldsym")) - 1 1 - [(eq_attr "type" "ist,fst")]) - -; Stores, shifts, multiplies can only issue to E0 -(define_function_unit "ev5_e0" 1 0 - (and (eq_attr "cpu" "ev5") - (eq_attr "type" "ist,fst,shift,imul")) - 1 1) - -; Motion video insns also issue only to E0, and take two ticks. -(define_function_unit "ev5_e0" 1 0 - (and (eq_attr "cpu" "ev5") - (eq_attr "type" "mvi")) - 2 1) - -; Conditional moves always take 2 ticks. -(define_function_unit "ev5_ebox" 2 0 - (and (eq_attr "cpu" "ev5") - (eq_attr "type" "icmov")) - 2 1) - -; Branches can only issue to E1 -(define_function_unit "ev5_e1" 1 0 - (and (eq_attr "cpu" "ev5") - (eq_attr "type" "ibr,jsr")) - 1 1) - -; Multiplies also use the integer multiplier. -; ??? How to: "No instruction can be issued to pipe E0 exactly two -; cycles before an integer multiplication completes." -(define_function_unit "imul" 1 0 - (and (eq_attr "cpu" "ev5") - (and (eq_attr "type" "imul") - (eq_attr "opsize" "si"))) - 8 4) - -(define_function_unit "imul" 1 0 - (and (eq_attr "cpu" "ev5") - (and (eq_attr "type" "imul") - (eq_attr "opsize" "di"))) - 12 8) - -(define_function_unit "imul" 1 0 - (and (eq_attr "cpu" "ev5") - (and (eq_attr "type" "imul") - (eq_attr "opsize" "udi"))) - 14 8) - -;; Similarly for the FPU we have two asymetric units. But fcpys can issue -;; on either so we have to play the game again. - -(define_function_unit "ev5_fbox" 2 0 - (and (eq_attr "cpu" "ev5") - (eq_attr "type" "fadd,fcmov,fmul,fcpys,fbr,fdiv")) - 4 1) - -(define_function_unit "ev5_fm" 1 0 - (and (eq_attr "cpu" "ev5") - (eq_attr "type" "fmul")) - 4 1) - -; Add and cmov as you would expect; fbr never produces a result; -; fdiv issues through fa to the divider, -(define_function_unit "ev5_fa" 1 0 - (and (eq_attr "cpu" "ev5") - (eq_attr "type" "fadd,fcmov,fbr,fdiv")) - 4 1) - -; ??? How to: "No instruction can be issued to pipe FA exactly five -; cycles before a floating point divide completes." -(define_function_unit "fdiv" 1 0 - (and (eq_attr "cpu" "ev5") - (and (eq_attr "type" "fdiv") - (eq_attr "opsize" "si"))) - 15 15) ; 15 to 31 data dependent - -(define_function_unit "fdiv" 1 0 - (and (eq_attr "cpu" "ev5") - (and (eq_attr "type" "fdiv") - (eq_attr "opsize" "di"))) - 22 22) ; 22 to 60 data dependent - -;; EV6 scheduling. EV6 can issue 4 insns per clock. -;; -;; EV6 has two symmetric pairs ("clusters") of two asymetric integer units -;; ("upper" and "lower"), yielding pipe names U0, U1, L0, L1. - -;; Conditional moves decompose into two independent primitives, each -;; taking one cycle. Since ev6 is out-of-order, we can't see anything -;; but two cycles. -(define_function_unit "ev6_ebox" 4 0 - (and (eq_attr "cpu" "ev6") - (eq_attr "type" "icmov")) - 2 1) - -(define_function_unit "ev6_ebox" 4 0 - (and (eq_attr "cpu" "ev6") - (eq_attr "type" "!fbr,fcmov,fadd,fmul,fcpys,fdiv,fsqrt")) - 1 1) - -;; Integer loads take at least 3 clocks, and only issue to lower units. -;; Return one from here and fix up with user-defined latencies in adjust_cost. -(define_function_unit "ev6_l" 2 0 - (and (eq_attr "cpu" "ev6") - (eq_attr "type" "ild,ldsym,ist,fst")) - 1 1) - -;; FP loads take at least 4 clocks. Return two from here... -(define_function_unit "ev6_l" 2 0 - (and (eq_attr "cpu" "ev6") - (eq_attr "type" "fld")) - 2 1) - -;; Motion video insns also issue only to U0, and take three ticks. -(define_function_unit "ev6_u0" 1 0 - (and (eq_attr "cpu" "ev6") - (eq_attr "type" "mvi")) - 3 1) - -(define_function_unit "ev6_u" 2 0 - (and (eq_attr "cpu" "ev6") - (eq_attr "type" "mvi")) - 3 1) - -;; Shifts issue to either upper pipe. -(define_function_unit "ev6_u" 2 0 - (and (eq_attr "cpu" "ev6") - (eq_attr "type" "shift")) - 1 1) - -;; Multiplies issue only to U1, and all take 7 ticks. -;; Rather than create a new function unit just for U1, reuse IMUL -(define_function_unit "imul" 1 0 - (and (eq_attr "cpu" "ev6") - (eq_attr "type" "imul")) - 7 1) - -(define_function_unit "ev6_u" 2 0 - (and (eq_attr "cpu" "ev6") - (eq_attr "type" "imul")) - 7 1) - -;; Branches issue to either upper pipe -(define_function_unit "ev6_u" 2 0 - (and (eq_attr "cpu" "ev6") - (eq_attr "type" "ibr")) - 3 1) - -;; Calls only issue to L0. -(define_function_unit "ev6_l0" 1 0 - (and (eq_attr "cpu" "ev6") - (eq_attr "type" "jsr")) - 1 1) - -(define_function_unit "ev6_l" 2 0 - (and (eq_attr "cpu" "ev6") - (eq_attr "type" "jsr")) - 1 1) - -;; Ftoi/itof only issue to lower pipes -(define_function_unit "ev6_l" 2 0 - (and (eq_attr "cpu" "ev6") - (eq_attr "type" "ftoi")) - 3 1) - -(define_function_unit "ev6_l" 2 0 - (and (eq_attr "cpu" "ev6") - (eq_attr "type" "itof")) - 4 1) - -;; For the FPU we are very similar to EV5, except there's no insn that -;; can issue to fm & fa, so we get to leave that out. - -(define_function_unit "ev6_fm" 1 0 - (and (eq_attr "cpu" "ev6") - (eq_attr "type" "fmul")) - 4 1) - -(define_function_unit "ev6_fa" 1 0 - (and (eq_attr "cpu" "ev6") - (eq_attr "type" "fadd,fcpys,fbr,fdiv,fsqrt")) - 4 1) - -(define_function_unit "ev6_fa" 1 0 - (and (eq_attr "cpu" "ev6") - (eq_attr "type" "fcmov")) - 8 1) - -(define_function_unit "fdiv" 1 0 - (and (eq_attr "cpu" "ev6") - (and (eq_attr "type" "fdiv") - (eq_attr "opsize" "si"))) - 12 10) - -(define_function_unit "fdiv" 1 0 - (and (eq_attr "cpu" "ev6") - (and (eq_attr "type" "fdiv") - (eq_attr "opsize" "di"))) - 15 13) - -(define_function_unit "fsqrt" 1 0 - (and (eq_attr "cpu" "ev6") - (and (eq_attr "type" "fsqrt") - (eq_attr "opsize" "si"))) - 16 14) - -(define_function_unit "fsqrt" 1 0 - (and (eq_attr "cpu" "ev6") - (and (eq_attr "type" "fsqrt") - (eq_attr "opsize" "di"))) - 32 30) - -; ??? The FPU communicates with memory and the integer register file -; via two fp store units. We need a slot in the fst immediately, and -; a slot in LOW after the operand data is ready. At which point the -; data may be moved either to the store queue or the integer register -; file and the insn retired. +;; The USEGP attribute marks instructions that have relocations that use +;; the GP. + +(define_attr "usegp" "no,yes" + (cond [(eq_attr "type" "ldsym,jsr") + (const_string "yes") + (eq_attr "type" "ild,fld,ist,fst") + (symbol_ref "alpha_find_lo_sum_using_gp(insn)") + ] + (const_string "no"))) + + +;; Include scheduling descriptions. + +(include "ev4.md") +(include "ev5.md") +(include "ev6.md") ;; First define the arithmetic insns. Note that the 32-bit forms also ;; sign-extend. @@ -453,7 +183,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,m")))] "! TARGET_FIX" "@ - addl %1,$31,%0 + addl $31,%1,%0 ldl %0,%1 cvtlq %1,%0 lds %0,%1\;cvtlq %0,%0" @@ -466,7 +196,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (match_operand:SI 1 "nonimmediate_operand" "r,m,*f,*f,m")))] "TARGET_FIX" "@ - addl %1,$31,%0 + addl $31,%1,%0 ldl %0,%1 ftois %1,%0 cvtlq %1,%0 @@ -637,12 +367,55 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" "" "") +(define_insn "*adddi_er_lo16_dtp" + [(set (match_operand:DI 0 "register_operand" "=r") + (lo_sum:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "dtp16_symbolic_operand" "")))] + "HAVE_AS_TLS" + "lda %0,%2(%1)\t\t!dtprel") + +(define_insn "*adddi_er_hi32_dtp" + [(set (match_operand:DI 0 "register_operand" "=r") + (plus:DI (match_operand:DI 1 "register_operand" "r") + (high:DI (match_operand:DI 2 "dtp32_symbolic_operand" ""))))] + "HAVE_AS_TLS" + "ldah %0,%2(%1)\t\t!dtprelhi") + +(define_insn "*adddi_er_lo32_dtp" + [(set (match_operand:DI 0 "register_operand" "=r") + (lo_sum:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "dtp32_symbolic_operand" "")))] + "HAVE_AS_TLS" + "lda %0,%2(%1)\t\t!dtprello") + +(define_insn "*adddi_er_lo16_tp" + [(set (match_operand:DI 0 "register_operand" "=r") + (lo_sum:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "tp16_symbolic_operand" "")))] + "HAVE_AS_TLS" + "lda %0,%2(%1)\t\t!tprel") + +(define_insn "*adddi_er_hi32_tp" + [(set (match_operand:DI 0 "register_operand" "=r") + (plus:DI (match_operand:DI 1 "register_operand" "r") + (high:DI (match_operand:DI 2 "tp32_symbolic_operand" ""))))] + "HAVE_AS_TLS" + "ldah %0,%2(%1)\t\t!tprelhi") + +(define_insn "*adddi_er_lo32_tp" + [(set (match_operand:DI 0 "register_operand" "=r") + (lo_sum:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "tp32_symbolic_operand" "")))] + "HAVE_AS_TLS" + "lda %0,%2(%1)\t\t!tprello") + (define_insn "*adddi_er_high_l" [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI (match_operand:DI 1 "register_operand" "r") (high:DI (match_operand:DI 2 "local_symbolic_operand" ""))))] "TARGET_EXPLICIT_RELOCS" - "ldah %0,%2(%1)\t\t!gprelhigh") + "ldah %0,%2(%1)\t\t!gprelhigh" + [(set_attr "usegp" "yes")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -977,17 +750,31 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" "mulqv %r1,%2,%0" [(set_attr "type" "imul")]) -(define_insn "umuldi3_highpart" +(define_expand "umuldi3_highpart" + [(set (match_operand:DI 0 "register_operand" "") + (truncate:DI + (lshiftrt:TI + (mult:TI (zero_extend:TI + (match_operand:DI 1 "register_operand" "")) + (match_operand:DI 2 "reg_or_8bit_operand" "")) + (const_int 64))))] + "" +{ + if (REG_P (operands[2])) + operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]); +}) + +(define_insn "*umuldi3_highpart_reg" [(set (match_operand:DI 0 "register_operand" "=r") (truncate:DI (lshiftrt:TI (mult:TI (zero_extend:TI - (match_operand:DI 1 "reg_or_0_operand" "%rJ")) + (match_operand:DI 1 "register_operand" "r")) (zero_extend:TI - (match_operand:DI 2 "reg_or_8bit_operand" "rI"))) + (match_operand:DI 2 "register_operand" "r"))) (const_int 64))))] "" - "umulh %r1,%2,%0" + "umulh %1,%2,%0" [(set_attr "type" "imul") (set_attr "opsize" "udi")]) @@ -1973,7 +1760,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" "ext%M2l %r1,%3,%0" [(set_attr "type" "shift")]) -;; Combine has some strange notion of preserving existing undefined behaviour +;; Combine has some strange notion of preserving existing undefined behavior ;; in shifts larger than a word size. So capture these patterns that it ;; should have turned into zero_extracts. @@ -2346,35 +2133,35 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "abssf2" [(set (match_operand:SF 0 "register_operand" "=f") - (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))] + (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))] "TARGET_FP" "cpys $f31,%R1,%0" [(set_attr "type" "fcpys")]) (define_insn "*nabssf2" [(set (match_operand:SF 0 "register_operand" "=f") - (neg:SF (abs:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))] + (neg:SF (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG"))))] "TARGET_FP" "cpysn $f31,%R1,%0" [(set_attr "type" "fadd")]) (define_insn "absdf2" [(set (match_operand:DF 0 "register_operand" "=f") - (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))] + (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))] "TARGET_FP" "cpys $f31,%R1,%0" [(set_attr "type" "fcpys")]) (define_insn "*nabsdf2" [(set (match_operand:DF 0 "register_operand" "=f") - (neg:DF (abs:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG"))))] + (neg:DF (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG"))))] "TARGET_FP" "cpysn $f31,%R1,%0" [(set_attr "type" "fadd")]) (define_expand "abstf2" [(parallel [(set (match_operand:TF 0 "register_operand" "") - (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" ""))) + (abs:TF (match_operand:TF 1 "reg_or_0_operand" ""))) (use (match_dup 2))])] "TARGET_HAS_XFLOATING_LIBS" { @@ -2387,7 +2174,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn_and_split "*abstf_internal" [(set (match_operand:TF 0 "register_operand" "=r") - (abs:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG"))) + (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG"))) (use (match_operand:DI 2 "register_operand" "r"))] "TARGET_HAS_XFLOATING_LIBS" "#" @@ -2397,21 +2184,21 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "negsf2" [(set (match_operand:SF 0 "register_operand" "=f") - (neg:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))] + (neg:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))] "TARGET_FP" "cpysn %R1,%R1,%0" [(set_attr "type" "fadd")]) (define_insn "negdf2" [(set (match_operand:DF 0 "register_operand" "=f") - (neg:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))] + (neg:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))] "TARGET_FP" "cpysn %R1,%R1,%0" [(set_attr "type" "fadd")]) (define_expand "negtf2" [(parallel [(set (match_operand:TF 0 "register_operand" "") - (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" ""))) + (neg:TF (match_operand:TF 1 "reg_or_0_operand" ""))) (use (match_dup 2))])] "TARGET_HAS_XFLOATING_LIBS" { @@ -2424,7 +2211,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn_and_split "*negtf_internal" [(set (match_operand:TF 0 "register_operand" "=r") - (neg:TF (match_operand:TF 1 "reg_or_fp0_operand" "rG"))) + (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG"))) (use (match_operand:DI 2 "register_operand" "r"))] "TARGET_HAS_XFLOATING_LIBS" "#" @@ -2434,8 +2221,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*addsf_ieee" [(set (match_operand:SF 0 "register_operand" "=&f") - (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG") - (match_operand:SF 2 "reg_or_fp0_operand" "fG")))] + (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG") + (match_operand:SF 2 "reg_or_0_operand" "fG")))] "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" "add%,%/ %R1,%R2,%0" [(set_attr "type" "fadd") @@ -2445,8 +2232,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "addsf3" [(set (match_operand:SF 0 "register_operand" "=f") - (plus:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG") - (match_operand:SF 2 "reg_or_fp0_operand" "fG")))] + (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG") + (match_operand:SF 2 "reg_or_0_operand" "fG")))] "TARGET_FP" "add%,%/ %R1,%R2,%0" [(set_attr "type" "fadd") @@ -2456,8 +2243,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*adddf_ieee" [(set (match_operand:DF 0 "register_operand" "=&f") - (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG") - (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] + (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG") + (match_operand:DF 2 "reg_or_0_operand" "fG")))] "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" "add%-%/ %R1,%R2,%0" [(set_attr "type" "fadd") @@ -2467,8 +2254,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "adddf3" [(set (match_operand:DF 0 "register_operand" "=f") - (plus:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG") - (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] + (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG") + (match_operand:DF 2 "reg_or_0_operand" "fG")))] "TARGET_FP" "add%-%/ %R1,%R2,%0" [(set_attr "type" "fadd") @@ -2479,8 +2266,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*adddf_ext1" [(set (match_operand:DF 0 "register_operand" "=f") (plus:DF (float_extend:DF - (match_operand:SF 1 "reg_or_fp0_operand" "fG")) - (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] + (match_operand:SF 1 "reg_or_0_operand" "fG")) + (match_operand:DF 2 "reg_or_0_operand" "fG")))] "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" "add%-%/ %R1,%R2,%0" [(set_attr "type" "fadd") @@ -2491,9 +2278,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*adddf_ext2" [(set (match_operand:DF 0 "register_operand" "=f") (plus:DF (float_extend:DF - (match_operand:SF 1 "reg_or_fp0_operand" "%fG")) + (match_operand:SF 1 "reg_or_0_operand" "%fG")) (float_extend:DF - (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))] + (match_operand:SF 2 "reg_or_0_operand" "fG"))))] "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" "add%-%/ %R1,%R2,%0" [(set_attr "type" "fadd") @@ -2519,7 +2306,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*cvtql" [(set (match_operand:SI 0 "register_operand" "=f") - (unspec:SI [(match_operand:DI 1 "reg_or_fp0_operand" "fG")] + (unspec:SI [(match_operand:DI 1 "reg_or_0_operand" "fG")] UNSPEC_CVTQL))] "TARGET_FP" "cvtql%/ %R1,%0" @@ -2529,7 +2316,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn_and_split "*fix_truncdfsi_ieee" [(set (match_operand:SI 0 "memory_operand" "=m") - (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0)) + (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")) 0)) (clobber (match_scratch:DI 2 "=&f")) (clobber (match_scratch:SI 3 "=&f"))] "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" @@ -2544,7 +2331,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn_and_split "*fix_truncdfsi_internal" [(set (match_operand:SI 0 "memory_operand" "=m") - (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")) 0)) + (subreg:SI (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")) 0)) (clobber (match_scratch:DI 2 "=f"))] "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" "#" @@ -2559,7 +2346,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*fix_truncdfdi_ieee" [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f") - (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))] + (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")))] "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" "cvt%-q%/ %R1,%0" [(set_attr "type" "fadd") @@ -2569,7 +2356,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "fix_truncdfdi2" [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f") - (fix:DI (match_operand:DF 1 "reg_or_fp0_operand" "fG")))] + (fix:DI (match_operand:DF 1 "reg_or_0_operand" "fG")))] "TARGET_FP" "cvt%-q%/ %R1,%0" [(set_attr "type" "fadd") @@ -2582,7 +2369,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn_and_split "*fix_truncsfsi_ieee" [(set (match_operand:SI 0 "memory_operand" "=m") (subreg:SI (fix:DI (float_extend:DF - (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0)) + (match_operand:SF 1 "reg_or_0_operand" "fG"))) 0)) (clobber (match_scratch:DI 2 "=&f")) (clobber (match_scratch:SI 3 "=&f"))] "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" @@ -2598,7 +2385,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn_and_split "*fix_truncsfsi_internal" [(set (match_operand:SI 0 "memory_operand" "=m") (subreg:SI (fix:DI (float_extend:DF - (match_operand:SF 1 "reg_or_fp0_operand" "fG"))) 0)) + (match_operand:SF 1 "reg_or_0_operand" "fG"))) 0)) (clobber (match_scratch:DI 2 "=f"))] "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" "#" @@ -2614,7 +2401,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*fix_truncsfdi_ieee" [(set (match_operand:DI 0 "reg_no_subreg_operand" "=&f") (fix:DI (float_extend:DF - (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))] + (match_operand:SF 1 "reg_or_0_operand" "fG"))))] "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" "cvt%-q%/ %R1,%0" [(set_attr "type" "fadd") @@ -2625,7 +2412,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "fix_truncsfdi2" [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f") (fix:DI (float_extend:DF - (match_operand:SF 1 "reg_or_fp0_operand" "fG"))))] + (match_operand:SF 1 "reg_or_0_operand" "fG"))))] "TARGET_FP" "cvt%-q%/ %R1,%0" [(set_attr "type" "fadd") @@ -2752,7 +2539,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*truncdfsf2_ieee" [(set (match_operand:SF 0 "register_operand" "=&f") - (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))] + (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))] "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" "cvt%-%,%/ %R1,%0" [(set_attr "type" "fadd") @@ -2762,7 +2549,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "truncdfsf2" [(set (match_operand:SF 0 "register_operand" "=f") - (float_truncate:SF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))] + (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG")))] "TARGET_FP" "cvt%-%,%/ %R1,%0" [(set_attr "type" "fadd") @@ -2804,8 +2591,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*divsf3_ieee" [(set (match_operand:SF 0 "register_operand" "=&f") - (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG") - (match_operand:SF 2 "reg_or_fp0_operand" "fG")))] + (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG") + (match_operand:SF 2 "reg_or_0_operand" "fG")))] "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" "div%,%/ %R1,%R2,%0" [(set_attr "type" "fdiv") @@ -2816,8 +2603,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "divsf3" [(set (match_operand:SF 0 "register_operand" "=f") - (div:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG") - (match_operand:SF 2 "reg_or_fp0_operand" "fG")))] + (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG") + (match_operand:SF 2 "reg_or_0_operand" "fG")))] "TARGET_FP" "div%,%/ %R1,%R2,%0" [(set_attr "type" "fdiv") @@ -2828,8 +2615,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*divdf3_ieee" [(set (match_operand:DF 0 "register_operand" "=&f") - (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG") - (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] + (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG") + (match_operand:DF 2 "reg_or_0_operand" "fG")))] "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" "div%-%/ %R1,%R2,%0" [(set_attr "type" "fdiv") @@ -2839,8 +2626,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "divdf3" [(set (match_operand:DF 0 "register_operand" "=f") - (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG") - (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] + (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG") + (match_operand:DF 2 "reg_or_0_operand" "fG")))] "TARGET_FP" "div%-%/ %R1,%R2,%0" [(set_attr "type" "fdiv") @@ -2850,8 +2637,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*divdf_ext1" [(set (match_operand:DF 0 "register_operand" "=f") - (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG")) - (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] + (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG")) + (match_operand:DF 2 "reg_or_0_operand" "fG")))] "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" "div%-%/ %R1,%R2,%0" [(set_attr "type" "fdiv") @@ -2861,9 +2648,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*divdf_ext2" [(set (match_operand:DF 0 "register_operand" "=f") - (div:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG") + (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG") (float_extend:DF - (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))] + (match_operand:SF 2 "reg_or_0_operand" "fG"))))] "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" "div%-%/ %R1,%R2,%0" [(set_attr "type" "fdiv") @@ -2873,8 +2660,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*divdf_ext3" [(set (match_operand:DF 0 "register_operand" "=f") - (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG")) - (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))] + (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG")) + (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))] "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" "div%-%/ %R1,%R2,%0" [(set_attr "type" "fdiv") @@ -2891,8 +2678,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*mulsf3_ieee" [(set (match_operand:SF 0 "register_operand" "=&f") - (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG") - (match_operand:SF 2 "reg_or_fp0_operand" "fG")))] + (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG") + (match_operand:SF 2 "reg_or_0_operand" "fG")))] "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" "mul%,%/ %R1,%R2,%0" [(set_attr "type" "fmul") @@ -2902,8 +2689,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "mulsf3" [(set (match_operand:SF 0 "register_operand" "=f") - (mult:SF (match_operand:SF 1 "reg_or_fp0_operand" "%fG") - (match_operand:SF 2 "reg_or_fp0_operand" "fG")))] + (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG") + (match_operand:SF 2 "reg_or_0_operand" "fG")))] "TARGET_FP" "mul%,%/ %R1,%R2,%0" [(set_attr "type" "fmul") @@ -2913,8 +2700,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*muldf3_ieee" [(set (match_operand:DF 0 "register_operand" "=&f") - (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG") - (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] + (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG") + (match_operand:DF 2 "reg_or_0_operand" "fG")))] "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" "mul%-%/ %R1,%R2,%0" [(set_attr "type" "fmul") @@ -2924,8 +2711,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "muldf3" [(set (match_operand:DF 0 "register_operand" "=f") - (mult:DF (match_operand:DF 1 "reg_or_fp0_operand" "%fG") - (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] + (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG") + (match_operand:DF 2 "reg_or_0_operand" "fG")))] "TARGET_FP" "mul%-%/ %R1,%R2,%0" [(set_attr "type" "fmul") @@ -2936,8 +2723,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*muldf_ext1" [(set (match_operand:DF 0 "register_operand" "=f") (mult:DF (float_extend:DF - (match_operand:SF 1 "reg_or_fp0_operand" "fG")) - (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] + (match_operand:SF 1 "reg_or_0_operand" "fG")) + (match_operand:DF 2 "reg_or_0_operand" "fG")))] "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" "mul%-%/ %R1,%R2,%0" [(set_attr "type" "fmul") @@ -2948,9 +2735,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*muldf_ext2" [(set (match_operand:DF 0 "register_operand" "=f") (mult:DF (float_extend:DF - (match_operand:SF 1 "reg_or_fp0_operand" "%fG")) + (match_operand:SF 1 "reg_or_0_operand" "%fG")) (float_extend:DF - (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))] + (match_operand:SF 2 "reg_or_0_operand" "fG"))))] "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" "mul%-%/ %R1,%R2,%0" [(set_attr "type" "fmul") @@ -2967,8 +2754,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*subsf3_ieee" [(set (match_operand:SF 0 "register_operand" "=&f") - (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG") - (match_operand:SF 2 "reg_or_fp0_operand" "fG")))] + (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG") + (match_operand:SF 2 "reg_or_0_operand" "fG")))] "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" "sub%,%/ %R1,%R2,%0" [(set_attr "type" "fadd") @@ -2978,8 +2765,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "subsf3" [(set (match_operand:SF 0 "register_operand" "=f") - (minus:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG") - (match_operand:SF 2 "reg_or_fp0_operand" "fG")))] + (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG") + (match_operand:SF 2 "reg_or_0_operand" "fG")))] "TARGET_FP" "sub%,%/ %R1,%R2,%0" [(set_attr "type" "fadd") @@ -2989,8 +2776,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*subdf3_ieee" [(set (match_operand:DF 0 "register_operand" "=&f") - (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG") - (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] + (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG") + (match_operand:DF 2 "reg_or_0_operand" "fG")))] "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" "sub%-%/ %R1,%R2,%0" [(set_attr "type" "fadd") @@ -3000,8 +2787,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "subdf3" [(set (match_operand:DF 0 "register_operand" "=f") - (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG") - (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] + (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG") + (match_operand:DF 2 "reg_or_0_operand" "fG")))] "TARGET_FP" "sub%-%/ %R1,%R2,%0" [(set_attr "type" "fadd") @@ -3012,8 +2799,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*subdf_ext1" [(set (match_operand:DF 0 "register_operand" "=f") (minus:DF (float_extend:DF - (match_operand:SF 1 "reg_or_fp0_operand" "fG")) - (match_operand:DF 2 "reg_or_fp0_operand" "fG")))] + (match_operand:SF 1 "reg_or_0_operand" "fG")) + (match_operand:DF 2 "reg_or_0_operand" "fG")))] "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" "sub%-%/ %R1,%R2,%0" [(set_attr "type" "fadd") @@ -3023,9 +2810,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*subdf_ext2" [(set (match_operand:DF 0 "register_operand" "=f") - (minus:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG") + (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG") (float_extend:DF - (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))] + (match_operand:SF 2 "reg_or_0_operand" "fG"))))] "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" "sub%-%/ %R1,%R2,%0" [(set_attr "type" "fadd") @@ -3036,9 +2823,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*subdf_ext3" [(set (match_operand:DF 0 "register_operand" "=f") (minus:DF (float_extend:DF - (match_operand:SF 1 "reg_or_fp0_operand" "fG")) + (match_operand:SF 1 "reg_or_0_operand" "fG")) (float_extend:DF - (match_operand:SF 2 "reg_or_fp0_operand" "fG"))))] + (match_operand:SF 2 "reg_or_0_operand" "fG"))))] "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" "sub%-%/ %R1,%R2,%0" [(set_attr "type" "fadd") @@ -3055,7 +2842,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*sqrtsf2_ieee" [(set (match_operand:SF 0 "register_operand" "=&f") - (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))] + (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))] "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU" "sqrt%,%/ %R1,%0" [(set_attr "type" "fsqrt") @@ -3066,7 +2853,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "sqrtsf2" [(set (match_operand:SF 0 "register_operand" "=f") - (sqrt:SF (match_operand:SF 1 "reg_or_fp0_operand" "fG")))] + (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))] "TARGET_FP && TARGET_FIX" "sqrt%,%/ %R1,%0" [(set_attr "type" "fsqrt") @@ -3077,7 +2864,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*sqrtdf2_ieee" [(set (match_operand:DF 0 "register_operand" "=&f") - (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))] + (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))] "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU" "sqrt%-%/ %R1,%0" [(set_attr "type" "fsqrt") @@ -3087,9 +2874,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "sqrtdf2" [(set (match_operand:DF 0 "register_operand" "=f") - (sqrt:DF (match_operand:DF 1 "reg_or_fp0_operand" "fG")))] + (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))] "TARGET_FP && TARGET_FIX" - "sqrt%-%/ %1,%0" + "sqrt%-%/ %R1,%0" [(set_attr "type" "fsqrt") (set_attr "trap" "yes") (set_attr "round_suffix" "normal") @@ -3462,7 +3249,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (match_operand:HI 2 "reg_or_8bit_operand" "rI")))] "TARGET_MAX" "maxuw4 %r1,%2,%0" - [(set_attr "type" "shift")]) + [(set_attr "type" "mvi")]) (define_expand "smaxdi3" [(set (match_dup 3) @@ -3647,8 +3434,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*cmpdf_ieee" [(set (match_operand:DF 0 "register_operand" "=&f") (match_operator:DF 1 "alpha_fp_comparison_operator" - [(match_operand:DF 2 "reg_or_fp0_operand" "fG") - (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))] + [(match_operand:DF 2 "reg_or_0_operand" "fG") + (match_operand:DF 3 "reg_or_0_operand" "fG")]))] "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" "cmp%-%C1%/ %R2,%R3,%0" [(set_attr "type" "fadd") @@ -3658,8 +3445,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*cmpdf_internal" [(set (match_operand:DF 0 "register_operand" "=f") (match_operator:DF 1 "alpha_fp_comparison_operator" - [(match_operand:DF 2 "reg_or_fp0_operand" "fG") - (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))] + [(match_operand:DF 2 "reg_or_0_operand" "fG") + (match_operand:DF 3 "reg_or_0_operand" "fG")]))] "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" "cmp%-%C1%/ %R2,%R3,%0" [(set_attr "type" "fadd") @@ -3670,8 +3457,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" [(set (match_operand:DF 0 "register_operand" "=&f") (match_operator:DF 1 "alpha_fp_comparison_operator" [(float_extend:DF - (match_operand:SF 2 "reg_or_fp0_operand" "fG")) - (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))] + (match_operand:SF 2 "reg_or_0_operand" "fG")) + (match_operand:DF 3 "reg_or_0_operand" "fG")]))] "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" "cmp%-%C1%/ %R2,%R3,%0" [(set_attr "type" "fadd") @@ -3682,8 +3469,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" [(set (match_operand:DF 0 "register_operand" "=f") (match_operator:DF 1 "alpha_fp_comparison_operator" [(float_extend:DF - (match_operand:SF 2 "reg_or_fp0_operand" "fG")) - (match_operand:DF 3 "reg_or_fp0_operand" "fG")]))] + (match_operand:SF 2 "reg_or_0_operand" "fG")) + (match_operand:DF 3 "reg_or_0_operand" "fG")]))] "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" "cmp%-%C1%/ %R2,%R3,%0" [(set_attr "type" "fadd") @@ -3693,9 +3480,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*cmpdf_ieee_ext2" [(set (match_operand:DF 0 "register_operand" "=&f") (match_operator:DF 1 "alpha_fp_comparison_operator" - [(match_operand:DF 2 "reg_or_fp0_operand" "fG") + [(match_operand:DF 2 "reg_or_0_operand" "fG") (float_extend:DF - (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))] + (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" "cmp%-%C1%/ %R2,%R3,%0" [(set_attr "type" "fadd") @@ -3705,9 +3492,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_insn "*cmpdf_ext2" [(set (match_operand:DF 0 "register_operand" "=f") (match_operator:DF 1 "alpha_fp_comparison_operator" - [(match_operand:DF 2 "reg_or_fp0_operand" "fG") + [(match_operand:DF 2 "reg_or_0_operand" "fG") (float_extend:DF - (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))] + (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" "cmp%-%C1%/ %R2,%R3,%0" [(set_attr "type" "fadd") @@ -3718,9 +3505,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" [(set (match_operand:DF 0 "register_operand" "=&f") (match_operator:DF 1 "alpha_fp_comparison_operator" [(float_extend:DF - (match_operand:SF 2 "reg_or_fp0_operand" "fG")) + (match_operand:SF 2 "reg_or_0_operand" "fG")) (float_extend:DF - (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))] + (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" "cmp%-%C1%/ %R2,%R3,%0" [(set_attr "type" "fadd") @@ -3731,9 +3518,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" [(set (match_operand:DF 0 "register_operand" "=f") (match_operator:DF 1 "alpha_fp_comparison_operator" [(float_extend:DF - (match_operand:SF 2 "reg_or_fp0_operand" "fG")) + (match_operand:SF 2 "reg_or_0_operand" "fG")) (float_extend:DF - (match_operand:SF 3 "reg_or_fp0_operand" "fG"))]))] + (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" "cmp%-%C1%/ %R2,%R3,%0" [(set_attr "type" "fadd") @@ -3744,10 +3531,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" [(set (match_operand:DF 0 "register_operand" "=f,f") (if_then_else:DF (match_operator 3 "signed_comparison_operator" - [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG") - (match_operand:DF 2 "fp0_operand" "G,G")]) - (match_operand:DF 1 "reg_or_fp0_operand" "fG,0") - (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))] + [(match_operand:DF 4 "reg_or_0_operand" "fG,fG") + (match_operand:DF 2 "const0_operand" "G,G")]) + (match_operand:DF 1 "reg_or_0_operand" "fG,0") + (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] "TARGET_FP" "@ fcmov%C3 %R4,%R1,%0 @@ -3758,10 +3545,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" [(set (match_operand:SF 0 "register_operand" "=f,f") (if_then_else:SF (match_operator 3 "signed_comparison_operator" - [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG") - (match_operand:DF 2 "fp0_operand" "G,G")]) - (match_operand:SF 1 "reg_or_fp0_operand" "fG,0") - (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))] + [(match_operand:DF 4 "reg_or_0_operand" "fG,fG") + (match_operand:DF 2 "const0_operand" "G,G")]) + (match_operand:SF 1 "reg_or_0_operand" "fG,0") + (match_operand:SF 5 "reg_or_0_operand" "0,fG")))] "TARGET_FP" "@ fcmov%C3 %R4,%R1,%0 @@ -3772,10 +3559,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" [(set (match_operand:DF 0 "register_operand" "=f,f") (if_then_else:DF (match_operator 3 "signed_comparison_operator" - [(match_operand:DF 4 "reg_or_fp0_operand" "fG,fG") - (match_operand:DF 2 "fp0_operand" "G,G")]) - (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")) - (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))] + [(match_operand:DF 4 "reg_or_0_operand" "fG,fG") + (match_operand:DF 2 "const0_operand" "G,G")]) + (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0")) + (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] "TARGET_FP" "@ fcmov%C3 %R4,%R1,%0 @@ -3787,10 +3574,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (if_then_else:DF (match_operator 3 "signed_comparison_operator" [(float_extend:DF - (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG")) - (match_operand:DF 2 "fp0_operand" "G,G")]) - (match_operand:DF 1 "reg_or_fp0_operand" "fG,0") - (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))] + (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) + (match_operand:DF 2 "const0_operand" "G,G")]) + (match_operand:DF 1 "reg_or_0_operand" "fG,0") + (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] "TARGET_FP" "@ fcmov%C3 %R4,%R1,%0 @@ -3802,10 +3589,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (if_then_else:SF (match_operator 3 "signed_comparison_operator" [(float_extend:DF - (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG")) - (match_operand:DF 2 "fp0_operand" "G,G")]) - (match_operand:SF 1 "reg_or_fp0_operand" "fG,0") - (match_operand:SF 5 "reg_or_fp0_operand" "0,fG")))] + (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) + (match_operand:DF 2 "const0_operand" "G,G")]) + (match_operand:SF 1 "reg_or_0_operand" "fG,0") + (match_operand:SF 5 "reg_or_0_operand" "0,fG")))] "TARGET_FP" "@ fcmov%C3 %R4,%R1,%0 @@ -3817,10 +3604,10 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (if_then_else:DF (match_operator 3 "signed_comparison_operator" [(float_extend:DF - (match_operand:SF 4 "reg_or_fp0_operand" "fG,fG")) - (match_operand:DF 2 "fp0_operand" "G,G")]) - (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "fG,0")) - (match_operand:DF 5 "reg_or_fp0_operand" "0,fG")))] + (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) + (match_operand:DF 2 "const0_operand" "G,G")]) + (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0")) + (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] "TARGET_FP" "@ fcmov%C3 %R4,%R1,%0 @@ -3829,8 +3616,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_expand "maxdf3" [(set (match_dup 3) - (le:DF (match_operand:DF 1 "reg_or_fp0_operand" "") - (match_operand:DF 2 "reg_or_fp0_operand" ""))) + (le:DF (match_operand:DF 1 "reg_or_0_operand" "") + (match_operand:DF 2 "reg_or_0_operand" ""))) (set (match_operand:DF 0 "register_operand" "") (if_then_else:DF (eq (match_dup 3) (match_dup 4)) (match_dup 1) (match_dup 2)))] @@ -3842,8 +3629,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_expand "mindf3" [(set (match_dup 3) - (lt:DF (match_operand:DF 1 "reg_or_fp0_operand" "") - (match_operand:DF 2 "reg_or_fp0_operand" ""))) + (lt:DF (match_operand:DF 1 "reg_or_0_operand" "") + (match_operand:DF 2 "reg_or_0_operand" ""))) (set (match_operand:DF 0 "register_operand" "") (if_then_else:DF (ne (match_dup 3) (match_dup 4)) (match_dup 1) (match_dup 2)))] @@ -3855,8 +3642,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_expand "maxsf3" [(set (match_dup 3) - (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "")) - (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "")))) + (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "")) + (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "")))) (set (match_operand:SF 0 "register_operand" "") (if_then_else:SF (eq (match_dup 3) (match_dup 4)) (match_dup 1) (match_dup 2)))] @@ -3868,8 +3655,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (define_expand "minsf3" [(set (match_dup 3) - (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_fp0_operand" "")) - (float_extend:DF (match_operand:SF 2 "reg_or_fp0_operand" "")))) + (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "")) + (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "")))) (set (match_operand:SF 0 "register_operand" "") (if_then_else:SF (ne (match_dup 3) (match_dup 4)) (match_dup 1) (match_dup 2)))] @@ -3883,8 +3670,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" [(set (pc) (if_then_else (match_operator 1 "signed_comparison_operator" - [(match_operand:DF 2 "reg_or_fp0_operand" "fG") - (match_operand:DF 3 "fp0_operand" "G")]) + [(match_operand:DF 2 "reg_or_0_operand" "fG") + (match_operand:DF 3 "const0_operand" "G")]) (label_ref (match_operand 0 "" "")) (pc)))] "TARGET_FP" @@ -3896,8 +3683,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (if_then_else (match_operator 1 "signed_comparison_operator" [(float_extend:DF - (match_operand:SF 2 "reg_or_fp0_operand" "fG")) - (match_operand:DF 3 "fp0_operand" "G")]) + (match_operand:SF 2 "reg_or_0_operand" "fG")) + (match_operand:DF 3 "const0_operand" "G")]) (label_ref (match_operand 0 "" "")) (pc)))] "TARGET_FP" @@ -3908,8 +3695,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" ;; and compares. (define_expand "cmpdf" - [(set (cc0) (compare (match_operand:DF 0 "reg_or_fp0_operand" "") - (match_operand:DF 1 "reg_or_fp0_operand" "")))] + [(set (cc0) (compare (match_operand:DF 0 "reg_or_0_operand" "") + (match_operand:DF 1 "reg_or_0_operand" "")))] "TARGET_FP" { alpha_compare.op0 = operands[0]; @@ -4669,11 +4456,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]); if (GET_CODE (operands[0]) == SYMBOL_REF) { - rtx linkage = alpha_need_linkage (XSTR (operands[0], 0), 0); + alpha_need_linkage (XSTR (operands[0], 0), 0); - emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage)); - operands[2] - = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8))); + operands[2] = const0_rtx; } else { @@ -4771,11 +4556,9 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]); if (GET_CODE (operands[1]) == SYMBOL_REF) { - rtx linkage = alpha_need_linkage (XSTR (operands[1], 0), 0); + alpha_need_linkage (XSTR (operands[1], 0), 0); - emit_move_insn (gen_rtx_REG (Pmode, 26), gen_rtx_MEM (Pmode, linkage)); - operands[3] - = validize_mem (gen_rtx_MEM (Pmode, plus_constant (linkage, 8))); + operands[3] = const0_rtx; } else { @@ -4960,17 +4743,31 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" [(set_attr "type" "jsr") (set_attr "length" "*,*,12")]) +; GAS relies on the order and position of instructions output below in order +; to generate relocs for VMS link to potentially optimize the call. +; Please do not molest. (define_insn "*call_vms_1" [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s")) (match_operand 1 "" "")) - (use (match_operand:DI 2 "nonimmediate_operand" "r,m")) + (use (match_operand:DI 2 "nonmemory_operand" "r,n")) (use (reg:DI 25)) (use (reg:DI 26)) (clobber (reg:DI 27))] "TARGET_ABI_OPEN_VMS" - "@ - mov %2,$27\;jsr $26,0\;ldq $27,0($29) - ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)" + "* +{ + switch (which_alternative) + { + case 0: + return \"mov %2,$27\;jsr $26,0\;ldq $27,0($29)\"; + case 1: + operands [2] = alpha_use_linkage (operands [0], cfun->decl, 1, 0); + operands [3] = alpha_use_linkage (operands [0], cfun->decl, 0, 0); + return \"ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)\"; + default: + abort(); + } +}" [(set_attr "type" "jsr") (set_attr "length" "12,16")]) @@ -5018,7 +4815,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] "" "" - [(set_attr "length" "0")]) + [(set_attr "length" "0") + (set_attr "type" "none")]) (define_insn "jump" [(set (pc) @@ -5095,7 +4893,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" [(unspec_volatile [(const_int 0)] UNSPECV_IMB)] "" "call_pal 0x86" - [(set_attr "type" "ibr")]) + [(set_attr "type" "callpal")]) ;; BUGCHK is documented common to OSF/1 and VMS PALcode. ;; NT does not document anything at 0x81 -- presumably it would generate @@ -5105,7 +4903,44 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" [(trap_if (const_int 1) (const_int 0))] "!TARGET_ABI_WINDOWS_NT" "call_pal 0x81" - [(set_attr "type" "ibr")]) + [(set_attr "type" "callpal")]) + +;; For userland, we load the thread pointer from the TCB. +;; For the kernel, we load the per-cpu private value. + +(define_insn "load_tp" + [(set (match_operand:DI 0 "register_operand" "=v") + (unspec:DI [(const_int 0)] UNSPEC_TP))] + "TARGET_ABI_OSF" +{ + if (TARGET_TLS_KERNEL) + return "call_pal 0x32"; + else + return "call_pal 0x9e"; +} + [(set_attr "type" "callpal")]) + +;; For completeness, and possibly a __builtin function, here's how to +;; set the thread pointer. Since we don't describe enough of this +;; quantity for CSE, we have to use a volatile unspec, and then there's +;; not much point in creating an R16_REG register class. + +(define_expand "set_tp" + [(set (reg:DI 16) (match_operand:DI 0 "input_operand" "")) + (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)] + "TARGET_ABI_OSF" + "") + +(define_insn "*set_tp" + [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)] + "TARGET_ABI_OSF" +{ + if (TARGET_TLS_KERNEL) + return "call_pal 0x31"; + else + return "call_pal 0x9f"; +} + [(set_attr "type" "callpal")]) ;; Finally, we have the basic data motion insns. The byte and word insns ;; are done via define_expand. Start with the floating-point insns, since @@ -5116,7 +4951,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r"))] "TARGET_FPREGS && ! TARGET_FIX && (register_operand (operands[0], SFmode) - || reg_or_fp0_operand (operands[1], SFmode))" + || reg_or_0_operand (operands[1], SFmode))" "@ cpys %R1,%R1,%0 ld%, %0,%1 @@ -5131,7 +4966,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))] "TARGET_FPREGS && TARGET_FIX && (register_operand (operands[0], SFmode) - || reg_or_fp0_operand (operands[1], SFmode))" + || reg_or_0_operand (operands[1], SFmode))" "@ cpys %R1,%R1,%0 ld%, %0,%1 @@ -5148,7 +4983,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (match_operand:SF 1 "input_operand" "rG,m,r"))] "! TARGET_FPREGS && (register_operand (operands[0], SFmode) - || reg_or_fp0_operand (operands[1], SFmode))" + || reg_or_0_operand (operands[1], SFmode))" "@ bis $31,%r1,%0 ldl %0,%1 @@ -5160,7 +4995,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r"))] "TARGET_FPREGS && ! TARGET_FIX && (register_operand (operands[0], DFmode) - || reg_or_fp0_operand (operands[1], DFmode))" + || reg_or_0_operand (operands[1], DFmode))" "@ cpys %R1,%R1,%0 ld%- %0,%1 @@ -5175,7 +5010,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))] "TARGET_FPREGS && TARGET_FIX && (register_operand (operands[0], DFmode) - || reg_or_fp0_operand (operands[1], DFmode))" + || reg_or_0_operand (operands[1], DFmode))" "@ cpys %R1,%R1,%0 ld%- %0,%1 @@ -5192,7 +5027,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (match_operand:DF 1 "input_operand" "rG,m,r"))] "! TARGET_FPREGS && (register_operand (operands[0], DFmode) - || reg_or_fp0_operand (operands[1], DFmode))" + || reg_or_0_operand (operands[1], DFmode))" "@ bis $31,%r1,%0 ldq %0,%1 @@ -5206,7 +5041,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o") (match_operand:TF 1 "input_operand" "roG,rG"))] "register_operand (operands[0], TFmode) - || reg_or_fp0_operand (operands[1], TFmode)" + || reg_or_0_operand (operands[1], TFmode)" "#" "reload_completed" [(set (match_dup 0) (match_dup 2)) @@ -5227,7 +5062,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" "" { if (GET_CODE (operands[0]) == MEM - && ! reg_or_fp0_operand (operands[1], SFmode)) + && ! reg_or_0_operand (operands[1], SFmode)) operands[1] = force_reg (SFmode, operands[1]); }) @@ -5237,7 +5072,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" "" { if (GET_CODE (operands[0]) == MEM - && ! reg_or_fp0_operand (operands[1], DFmode)) + && ! reg_or_0_operand (operands[1], DFmode)) operands[1] = force_reg (DFmode, operands[1]); }) @@ -5247,7 +5082,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" "" { if (GET_CODE (operands[0]) == MEM - && ! reg_or_fp0_operand (operands[1], TFmode)) + && ! reg_or_0_operand (operands[1], TFmode)) operands[1] = force_reg (TFmode, operands[1]); }) @@ -5497,7 +5332,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" return "lda %0,%2(%1)\t\t!gprel"; else return "lda %0,%2(%1)\t\t!gprellow"; -}) +} + [(set_attr "usegp" "yes")]) (define_split [(set (match_operand:DI 0 "register_operand" "") @@ -5523,10 +5359,12 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" [(match_dup 0)] "operands[0] = split_small_symbolic_operand (operands[0]);") +;; Accepts any symbolic, not just global, since function calls that +;; don't go via bsr still use !literal in hopes of linker relaxation. (define_insn "movdi_er_high_g" [(set (match_operand:DI 0 "register_operand" "=r") (unspec:DI [(match_operand:DI 1 "register_operand" "r") - (match_operand:DI 2 "global_symbolic_operand" "") + (match_operand:DI 2 "symbolic_operand" "") (match_operand 3 "const_int_operand" "")] UNSPEC_LITERAL))] "TARGET_EXPLICIT_RELOCS" @@ -5583,6 +5421,77 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" } }) +(define_insn "movdi_er_tlsgd" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "symbolic_operand" "") + (match_operand 3 "const_int_operand" "")] + UNSPEC_TLSGD))] + "HAVE_AS_TLS" +{ + if (INTVAL (operands[3]) == 0) + return "lda %0,%2(%1)\t\t!tlsgd"; + else + return "lda %0,%2(%1)\t\t!tlsgd!%3"; +}) + +(define_insn "movdi_er_tlsldm" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand 2 "const_int_operand" "")] + UNSPEC_TLSLDM))] + "HAVE_AS_TLS" +{ + if (INTVAL (operands[2]) == 0) + return "lda %0,%&(%1)\t\t!tlsldm"; + else + return "lda %0,%&(%1)\t\t!tlsldm!%2"; +}) + +(define_insn "*movdi_er_gotdtp" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "symbolic_operand" "")] + UNSPEC_DTPREL))] + "HAVE_AS_TLS" + "ldq %0,%2(%1)\t\t!gotdtprel" + [(set_attr "type" "ild") + (set_attr "usegp" "yes")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "gotdtp_symbolic_operand" ""))] + "HAVE_AS_TLS && reload_completed" + [(set (match_dup 0) + (unspec:DI [(match_dup 2) + (match_dup 1)] UNSPEC_DTPREL))] +{ + operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0); + operands[2] = pic_offset_table_rtx; +}) + +(define_insn "*movdi_er_gottp" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "symbolic_operand" "")] + UNSPEC_TPREL))] + "HAVE_AS_TLS" + "ldq %0,%2(%1)\t\t!gottprel" + [(set_attr "type" "ild") + (set_attr "usegp" "yes")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "gottp_symbolic_operand" ""))] + "HAVE_AS_TLS && reload_completed" + [(set (match_dup 0) + (unspec:DI [(match_dup 2) + (match_dup 1)] UNSPEC_TPREL))] +{ + operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0); + operands[2] = pic_offset_table_rtx; +}) + (define_insn "*movdi_er_nofix" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,r,m,*f,*f,Q") (match_operand:DI 1 "input_operand" "rJ,K,L,T,s,m,rJ,*fJ,Q,*f"))] @@ -5600,7 +5509,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" fmov %R1,%0 ldt %0,%1 stt %R1,%0" - [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst")]) + [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst") + (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*")]) ;; The 'U' constraint matches symbolic operands on Unicos/Mk. Those should ;; have been split up by the rules above but we shouldn't reject the @@ -5647,7 +5557,8 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" stt %R1,%0 ftoit %1,%0 itoft %1,%0" - [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof")]) + [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof") + (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*")]) (define_insn "*movdi_fix" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,r,m,*f,*f,Q,r,*f") @@ -6254,6 +6165,195 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" DONE; }) +;; Vector operations + +(define_expand "movv8qi" + [(set (match_operand:V8QI 0 "nonimmediate_operand" "") + (match_operand:V8QI 1 "general_operand" ""))] + "" +{ + if (alpha_expand_mov (V8QImode, operands)) + DONE; +}) + +(define_insn "*movv8qi_fix" + [(set (match_operand:V8QI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f") + (match_operand:V8QI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))] + "TARGET_FIX + && (register_operand (operands[0], V8QImode) + || reg_or_0_operand (operands[1], V8QImode))" + "@ + bis $31,%r1,%0 + ldq %0,%1 + stq %r1,%0 + cpys %R1,%R1,%0 + ldt %0,%1 + stt %R1,%0 + ftoit %1,%0 + itoft %1,%0" + [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")]) + +(define_insn "*movv8qi_nofix" + [(set (match_operand:V8QI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m") + (match_operand:V8QI 1 "input_operand" "rW,m,rW,*fW,m,*f"))] + "! TARGET_FIX + && (register_operand (operands[0], V8QImode) + || reg_or_0_operand (operands[1], V8QImode))" + "@ + bis $31,%r1,%0 + ldq %0,%1 + stq %r1,%0 + cpys %R1,%R1,%0 + ldt %0,%1 + stt %R1,%0" + [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")]) + +(define_expand "movv4hi" + [(set (match_operand:V4HI 0 "nonimmediate_operand" "") + (match_operand:V4HI 1 "general_operand" ""))] + "" +{ + if (alpha_expand_mov (V4HImode, operands)) + DONE; +}) + +(define_insn "*movv4hi_fix" + [(set (match_operand:V4HI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f") + (match_operand:V4HI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))] + "TARGET_FIX + && (register_operand (operands[0], V4HImode) + || reg_or_0_operand (operands[1], V4HImode))" + "@ + bis $31,%r1,%0 + ldq %0,%1 + stq %r1,%0 + cpys %R1,%R1,%0 + ldt %0,%1 + stt %R1,%0 + ftoit %1,%0 + itoft %1,%0" + [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")]) + +(define_insn "*movv4hi_nofix" + [(set (match_operand:V4HI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m") + (match_operand:V4HI 1 "input_operand" "rW,m,rW,*fW,m,*f"))] + "! TARGET_FIX + && (register_operand (operands[0], V4HImode) + || reg_or_0_operand (operands[1], V4HImode))" + "@ + bis $31,%r1,%0 + ldq %0,%1 + stq %r1,%0 + cpys %R1,%R1,%0 + ldt %0,%1 + stt %R1,%0" + [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")]) + +(define_expand "movv2si" + [(set (match_operand:V2SI 0 "nonimmediate_operand" "") + (match_operand:V2SI 1 "general_operand" ""))] + "" +{ + if (alpha_expand_mov (V2SImode, operands)) + DONE; +}) + +(define_insn "*movv2si_fix" + [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m,r,*f") + (match_operand:V2SI 1 "input_operand" "rW,m,rW,*fW,m,*f,*f,r"))] + "TARGET_FIX + && (register_operand (operands[0], V2SImode) + || reg_or_0_operand (operands[1], V2SImode))" + "@ + bis $31,%r1,%0 + ldq %0,%1 + stq %r1,%0 + cpys %R1,%R1,%0 + ldt %0,%1 + stt %R1,%0 + ftoit %1,%0 + itoft %1,%0" + [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst,ftoi,itof")]) + +(define_insn "*movv2si_nofix" + [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r,r,m,*f,*f,m") + (match_operand:V2SI 1 "input_operand" "rW,m,rW,*fW,m,*f"))] + "! TARGET_FIX + && (register_operand (operands[0], V2SImode) + || reg_or_0_operand (operands[1], V2SImode))" + "@ + bis $31,%r1,%0 + ldq %0,%1 + stq %r1,%0 + cpys %R1,%R1,%0 + ldt %0,%1 + stt %R1,%0" + [(set_attr "type" "ilog,ild,ist,fcpys,fld,fst")]) + +(define_insn "uminv8qi3" + [(set (match_operand:V8QI 0 "register_operand" "=r") + (umin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") + (match_operand:V8QI 2 "reg_or_0_operand" "rW")))] + "TARGET_MAX" + "minub8 %r1,%r2,%0" + [(set_attr "type" "mvi")]) + +(define_insn "sminv8qi3" + [(set (match_operand:V8QI 0 "register_operand" "=r") + (smin:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") + (match_operand:V8QI 2 "reg_or_0_operand" "rW")))] + "TARGET_MAX" + "minsb8 %r1,%r2,%0" + [(set_attr "type" "mvi")]) + +(define_insn "uminv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=r") + (umin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW") + (match_operand:V4HI 2 "reg_or_0_operand" "rW")))] + "TARGET_MAX" + "minuw4 %r1,%r2,%0" + [(set_attr "type" "mvi")]) + +(define_insn "sminv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=r") + (smin:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW") + (match_operand:V4HI 2 "reg_or_0_operand" "rW")))] + "TARGET_MAX" + "minsw4 %r1,%r2,%0" + [(set_attr "type" "mvi")]) + +(define_insn "umaxv8qi3" + [(set (match_operand:V8QI 0 "register_operand" "=r") + (umax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") + (match_operand:V8QI 2 "reg_or_0_operand" "rW")))] + "TARGET_MAX" + "maxub8 %r1,%r2,%0" + [(set_attr "type" "mvi")]) + +(define_insn "smaxv8qi3" + [(set (match_operand:V8QI 0 "register_operand" "=r") + (smax:V8QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") + (match_operand:V8QI 2 "reg_or_0_operand" "rW")))] + "TARGET_MAX" + "maxsb8 %r1,%r2,%0" + [(set_attr "type" "mvi")]) + +(define_insn "umaxv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=r") + (umax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW") + (match_operand:V4HI 2 "reg_or_0_operand" "rW")))] + "TARGET_MAX" + "maxuw4 %r1,%r2,%0" + [(set_attr "type" "mvi")]) + +(define_insn "smaxv4hi3" + [(set (match_operand:V4HI 0 "register_operand" "=r") + (smax:V4HI (match_operand:V4HI 1 "reg_or_0_operand" "rW") + (match_operand:V4HI 2 "reg_or_0_operand" "rW")))] + "TARGET_MAX" + "maxsw4 %r1,%r2,%0" + [(set_attr "type" "mvi")]) + ;; Bit field extract patterns which use ext[wlq][lh] (define_expand "extv" @@ -6684,7 +6784,11 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && prev_nonnote_insn (insn) == operands[0]" [(const_int 0)] - "DONE;") + " +{ + emit_note (NULL, NOTE_INSN_DELETED); + DONE; +}") (define_insn "*builtin_setjmp_receiver_1" [(unspec_volatile [(label_ref (match_operand 0 "" ""))] UNSPECV_SETJMPR)] @@ -6864,12 +6968,12 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" and leave the LRU eviction counter pointing to that block. */ static const char * const alt[2][2] = { { - "lds $f31,%a0", /* read, evict next */ + "ldq $31,%a0", /* read, evict next */ "ldl $31,%a0", /* read, evict last */ }, { "ldt $f31,%a0", /* write, evict next */ - "ldq $31,%a0", /* write, evict last */ + "lds $f31,%a0", /* write, evict last */ } }; @@ -6922,7 +7026,687 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" else return ".align %0 #realign"; }) + +;; Instructions to be emitted from __builtins. + +(define_insn "builtin_cmpbge" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ") + (match_operand:DI 2 "reg_or_8bit_operand" "rI")] + UNSPEC_CMPBGE))] + "" + "cmpbge %r1,%2,%0" + ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't + ;; actually differentiate between ILOG and ICMP in the schedule. + [(set_attr "type" "icmp")]) + +(define_expand "builtin_extbl" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 2 "reg_or_8bit_operand" "")] + "" +{ + rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx)); + if (WORDS_BIG_ENDIAN) + gen = gen_extxl_be; + else + gen = gen_extxl_le; + emit_insn ((*gen) (operands[0], operands[1], GEN_INT (8), operands[2])); + DONE; +}) + +(define_expand "builtin_extwl" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 2 "reg_or_8bit_operand" "")] + "" +{ + rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx)); + if (WORDS_BIG_ENDIAN) + gen = gen_extxl_be; + else + gen = gen_extxl_le; + emit_insn ((*gen) (operands[0], operands[1], GEN_INT (16), operands[2])); + DONE; +}) + +(define_expand "builtin_extll" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 2 "reg_or_8bit_operand" "")] + "" +{ + rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx)); + if (WORDS_BIG_ENDIAN) + gen = gen_extxl_be; + else + gen = gen_extxl_le; + emit_insn ((*gen) (operands[0], operands[1], GEN_INT (32), operands[2])); + DONE; +}) + +(define_expand "builtin_extql" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 2 "reg_or_8bit_operand" "")] + "" +{ + rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx)); + if (WORDS_BIG_ENDIAN) + gen = gen_extxl_be; + else + gen = gen_extxl_le; + emit_insn ((*gen) (operands[0], operands[1], GEN_INT (64), operands[2])); + DONE; +}) + +(define_expand "builtin_extwh" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 2 "reg_or_8bit_operand" "")] + "" +{ + rtx (*gen) PARAMS ((rtx, rtx, rtx)); + if (WORDS_BIG_ENDIAN) + gen = gen_extwh_be; + else + gen = gen_extwh_le; + emit_insn ((*gen) (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "builtin_extlh" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 2 "reg_or_8bit_operand" "")] + "" +{ + rtx (*gen) PARAMS ((rtx, rtx, rtx)); + if (WORDS_BIG_ENDIAN) + gen = gen_extlh_be; + else + gen = gen_extlh_le; + emit_insn ((*gen) (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "builtin_extqh" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 2 "reg_or_8bit_operand" "")] + "" +{ + rtx (*gen) PARAMS ((rtx, rtx, rtx)); + if (WORDS_BIG_ENDIAN) + gen = gen_extqh_be; + else + gen = gen_extqh_le; + emit_insn ((*gen) (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "builtin_insbl" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 2 "reg_or_8bit_operand" "")] + "" +{ + rtx (*gen) PARAMS ((rtx, rtx, rtx)); + if (WORDS_BIG_ENDIAN) + gen = gen_insbl_be; + else + gen = gen_insbl_le; + operands[1] = gen_lowpart (QImode, operands[1]); + emit_insn ((*gen) (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "builtin_inswl" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 2 "reg_or_8bit_operand" "")] + "" +{ + rtx (*gen) PARAMS ((rtx, rtx, rtx)); + if (WORDS_BIG_ENDIAN) + gen = gen_inswl_be; + else + gen = gen_inswl_le; + operands[1] = gen_lowpart (HImode, operands[1]); + emit_insn ((*gen) (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "builtin_insll" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 2 "reg_or_8bit_operand" "")] + "" +{ + rtx (*gen) PARAMS ((rtx, rtx, rtx)); + if (WORDS_BIG_ENDIAN) + gen = gen_insll_be; + else + gen = gen_insll_le; + operands[1] = gen_lowpart (SImode, operands[1]); + emit_insn ((*gen) (operands[0], operands[1], operands[2])); + emit_insn ((*gen) (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "builtin_insql" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 2 "reg_or_8bit_operand" "")] + "" +{ + rtx (*gen) PARAMS ((rtx, rtx, rtx)); + if (WORDS_BIG_ENDIAN) + gen = gen_insql_be; + else + gen = gen_insql_le; + emit_insn ((*gen) (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "builtin_inswh" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "reg_or_8bit_operand" "")] + "" +{ + emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2])); + DONE; +}) + +(define_expand "builtin_inslh" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "reg_or_8bit_operand" "")] + "" +{ + emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2])); + DONE; +}) + +(define_expand "builtin_insqh" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "reg_or_8bit_operand" "")] + "" +{ + emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2])); + DONE; +}) + +(define_expand "builtin_mskbl" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 2 "reg_or_8bit_operand" "")] + "" +{ + rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx)); + rtx mask; + if (WORDS_BIG_ENDIAN) + gen = gen_mskxl_be; + else + gen = gen_mskxl_le; + mask = GEN_INT (0xff); + emit_insn ((*gen) (operands[0], operands[1], mask, operands[2])); + DONE; +}) + +(define_expand "builtin_mskwl" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 2 "reg_or_8bit_operand" "")] + "" +{ + rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx)); + rtx mask; + if (WORDS_BIG_ENDIAN) + gen = gen_mskxl_be; + else + gen = gen_mskxl_le; + mask = GEN_INT (0xffff); + emit_insn ((*gen) (operands[0], operands[1], mask, operands[2])); + DONE; +}) + +(define_expand "builtin_mskll" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 2 "reg_or_8bit_operand" "")] + "" +{ + rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx)); + rtx mask; + if (WORDS_BIG_ENDIAN) + gen = gen_mskxl_be; + else + gen = gen_mskxl_le; + mask = immed_double_const (0xffffffff, 0, DImode); + emit_insn ((*gen) (operands[0], operands[1], mask, operands[2])); + DONE; +}) + +(define_expand "builtin_mskql" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 2 "reg_or_8bit_operand" "")] + "" +{ + rtx (*gen) PARAMS ((rtx, rtx, rtx, rtx)); + rtx mask; + if (WORDS_BIG_ENDIAN) + gen = gen_mskxl_be; + else + gen = gen_mskxl_le; + mask = constm1_rtx; + emit_insn ((*gen) (operands[0], operands[1], mask, operands[2])); + DONE; +}) + +(define_expand "builtin_mskwh" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "reg_or_8bit_operand" "")] + "" +{ + emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2])); + DONE; +}) + +(define_expand "builtin_msklh" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "reg_or_8bit_operand" "")] + "" +{ + emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2])); + DONE; +}) + +(define_expand "builtin_mskqh" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "register_operand" "") + (match_operand:DI 2 "reg_or_8bit_operand" "")] + "" +{ + emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2])); + DONE; +}) + +(define_expand "builtin_zap" + [(set (match_operand:DI 0 "register_operand" "") + (and:DI (unspec:DI + [(match_operand:DI 2 "reg_or_const_int_operand" "")] + UNSPEC_ZAP) + (match_operand:DI 1 "reg_or_const_int_operand" "")))] + "" +{ + if (GET_CODE (operands[2]) == CONST_INT) + { + rtx mask = alpha_expand_zap_mask (INTVAL (operands[2])); + + if (mask == const0_rtx) + { + emit_move_insn (operands[0], const0_rtx); + DONE; + } + if (mask == constm1_rtx) + { + emit_move_insn (operands[0], operands[1]); + DONE; + } + + operands[1] = force_reg (DImode, operands[1]); + emit_insn (gen_anddi3 (operands[0], operands[1], mask)); + DONE; + } + + operands[1] = force_reg (DImode, operands[1]); + operands[2] = gen_lowpart (QImode, operands[2]); +}) + +(define_insn "*builtin_zap_1" + [(set (match_operand:DI 0 "register_operand" "=r,r,r,r") + (and:DI (unspec:DI + [(match_operand:QI 2 "reg_or_const_int_operand" "n,n,r,r")] + UNSPEC_ZAP) + (match_operand:DI 1 "reg_or_const_int_operand" "n,r,J,r")))] + "" + "@ + # + # + bis $31,$31,%0 + zap %r1,%2,%0" + [(set_attr "type" "shift,shift,ilog,shift")]) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (and:DI (unspec:DI + [(match_operand:QI 2 "const_int_operand" "")] + UNSPEC_ZAP) + (match_operand:DI 1 "const_int_operand" "")))] + "" + [(const_int 0)] +{ + rtx mask = alpha_expand_zap_mask (INTVAL (operands[2])); + if (HOST_BITS_PER_WIDE_INT >= 64 || GET_CODE (mask) == CONST_INT) + operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode); + else + { + HOST_WIDE_INT c_lo = INTVAL (operands[1]); + HOST_WIDE_INT c_hi = (c_lo < 0 ? -1 : 0); + operands[1] = immed_double_const (c_lo & CONST_DOUBLE_LOW (mask), + c_hi & CONST_DOUBLE_HIGH (mask), + DImode); + } + emit_move_insn (operands[0], operands[1]); + DONE; +}) + +(define_split + [(set (match_operand:DI 0 "register_operand" "") + (and:DI (unspec:DI + [(match_operand:QI 2 "const_int_operand" "")] + UNSPEC_ZAP) + (match_operand:DI 1 "register_operand" "")))] + "" + [(set (match_dup 0) + (and:DI (match_dup 1) (match_dup 2)))] +{ + operands[2] = alpha_expand_zap_mask (INTVAL (operands[2])); + if (operands[2] == const0_rtx) + { + emit_move_insn (operands[0], const0_rtx); + DONE; + } + if (operands[2] == constm1_rtx) + { + emit_move_insn (operands[0], operands[1]); + DONE; + } +}) + +(define_expand "builtin_zapnot" + [(set (match_operand:DI 0 "register_operand" "") + (and:DI (unspec:DI + [(not:QI (match_operand:DI 2 "reg_or_const_int_operand" ""))] + UNSPEC_ZAP) + (match_operand:DI 1 "reg_or_const_int_operand" "")))] + "" +{ + if (GET_CODE (operands[2]) == CONST_INT) + { + rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2])); + + if (mask == const0_rtx) + { + emit_move_insn (operands[0], const0_rtx); + DONE; + } + if (mask == constm1_rtx) + { + emit_move_insn (operands[0], operands[1]); + DONE; + } + operands[1] = force_reg (DImode, operands[1]); + emit_insn (gen_anddi3 (operands[0], operands[1], mask)); + DONE; + } + + operands[1] = force_reg (DImode, operands[1]); + operands[2] = gen_lowpart (QImode, operands[2]); +}) + +(define_insn "*builtin_zapnot_1" + [(set (match_operand:DI 0 "register_operand" "=r") + (and:DI (unspec:DI + [(not:QI (match_operand:QI 2 "register_operand" "r"))] + UNSPEC_ZAP) + (match_operand:DI 1 "reg_or_0_operand" "rJ")))] + "" + "zapnot %r1,%2,%0" + [(set_attr "type" "shift")]) + +(define_insn "builtin_amask" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")] + UNSPEC_AMASK))] + "" + "amask %1,%0" + [(set_attr "type" "ilog")]) + +(define_insn "builtin_implver" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))] + "" + "implver %0" + [(set_attr "type" "ilog")]) + +(define_insn "builtin_rpcc" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))] + "" + "rpcc %0" + [(set_attr "type" "ilog")]) + +(define_expand "builtin_minub8" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 2 "reg_or_0_operand" "")] + "TARGET_MAX" +{ + alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0], + operands[1], operands[2]); + DONE; +}) + +(define_expand "builtin_minsb8" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 2 "reg_or_0_operand" "")] + "TARGET_MAX" +{ + alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0], + operands[1], operands[2]); + DONE; +}) + +(define_expand "builtin_minuw4" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 2 "reg_or_0_operand" "")] + "TARGET_MAX" +{ + alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0], + operands[1], operands[2]); + DONE; +}) + +(define_expand "builtin_minsw4" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 2 "reg_or_0_operand" "")] + "TARGET_MAX" +{ + alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0], + operands[1], operands[2]); + DONE; +}) + +(define_expand "builtin_maxub8" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 2 "reg_or_0_operand" "")] + "TARGET_MAX" +{ + alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0], + operands[1], operands[2]); + DONE; +}) + +(define_expand "builtin_maxsb8" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 2 "reg_or_0_operand" "")] + "TARGET_MAX" +{ + alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0], + operands[1], operands[2]); + DONE; +}) + +(define_expand "builtin_maxuw4" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 2 "reg_or_0_operand" "")] + "TARGET_MAX" +{ + alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0], + operands[1], operands[2]); + DONE; +}) + +(define_expand "builtin_maxsw4" + [(match_operand:DI 0 "register_operand" "") + (match_operand:DI 1 "reg_or_0_operand" "") + (match_operand:DI 2 "reg_or_0_operand" "")] + "TARGET_MAX" +{ + alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0], + operands[1], operands[2]); + DONE; +}) + +(define_insn "builtin_perr" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ") + (match_operand:DI 2 "reg_or_8bit_operand" "rJ")] + UNSPEC_PERR))] + "TARGET_MAX" + "perr %r1,%r2,%0" + [(set_attr "type" "mvi")]) + +(define_expand "builtin_pklb" + [(set (match_operand:DI 0 "register_operand" "") + (vec_concat:V8QI + (vec_concat:V4QI + (truncate:V2QI (match_operand:DI 1 "register_operand" "")) + (match_dup 2)) + (match_dup 3)))] + "TARGET_MAX" +{ + operands[0] = gen_lowpart (V8QImode, operands[0]); + operands[1] = gen_lowpart (V2SImode, operands[1]); + operands[2] = CONST0_RTX (V2QImode); + operands[3] = CONST0_RTX (V4QImode); +}) + +(define_insn "*pklb" + [(set (match_operand:V8QI 0 "register_operand" "=r") + (vec_concat:V8QI + (vec_concat:V4QI + (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r")) + (match_operand:V2QI 2 "const0_operand" "")) + (match_operand:V4QI 3 "const0_operand" "")))] + "TARGET_MAX" + "pklb %r1,%0" + [(set_attr "type" "mvi")]) + +(define_expand "builtin_pkwb" + [(set (match_operand:DI 0 "register_operand" "") + (vec_concat:V8QI + (truncate:V4QI (match_operand:DI 1 "register_operand" "")) + (match_dup 2)))] + "TARGET_MAX" +{ + operands[0] = gen_lowpart (V8QImode, operands[0]); + operands[1] = gen_lowpart (V4HImode, operands[1]); + operands[2] = CONST0_RTX (V4QImode); +}) + +(define_insn "*pkwb" + [(set (match_operand:V8QI 0 "register_operand" "=r") + (vec_concat:V8QI + (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r")) + (match_operand:V4QI 2 "const0_operand" "")))] + "TARGET_MAX" + "pkwb %r1,%0" + [(set_attr "type" "mvi")]) + +(define_expand "builtin_unpkbl" + [(set (match_operand:DI 0 "register_operand" "") + (zero_extend:V2SI + (vec_select:V2QI (match_operand:DI 1 "register_operand" "") + (parallel [(const_int 0) (const_int 1)]))))] + "TARGET_MAX" +{ + operands[0] = gen_lowpart (V2SImode, operands[0]); + operands[1] = gen_lowpart (V8QImode, operands[1]); +}) + +(define_insn "*unpkbl" + [(set (match_operand:V2SI 0 "register_operand" "=r") + (zero_extend:V2SI + (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") + (parallel [(const_int 0) (const_int 1)]))))] + "TARGET_MAX" + "unpkbl %r1,%0" + [(set_attr "type" "mvi")]) + +(define_expand "builtin_unpkbw" + [(set (match_operand:DI 0 "register_operand" "") + (zero_extend:V4HI + (vec_select:V4QI (match_operand:DI 1 "register_operand" "") + (parallel [(const_int 0) + (const_int 1) + (const_int 2) + (const_int 3)]))))] + "TARGET_MAX" +{ + operands[0] = gen_lowpart (V4HImode, operands[0]); + operands[1] = gen_lowpart (V8QImode, operands[1]); +}) + +(define_insn "*unpkbw" + [(set (match_operand:V4HI 0 "register_operand" "=r") + (zero_extend:V4HI + (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") + (parallel [(const_int 0) + (const_int 1) + (const_int 2) + (const_int 3)]))))] + "TARGET_MAX" + "unpkbw %r1,%0" + [(set_attr "type" "mvi")]) + +(define_expand "builtin_cttz" + [(set (match_operand:DI 0 "register_operand" "") + (unspec:DI [(match_operand:DI 1 "register_operand" "")] + UNSPEC_CTTZ))] + "TARGET_CIX" + "") + +(define_insn "builtin_ctlz" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_CTLZ))] + "TARGET_CIX" + "ctlz %1,%0" + [(set_attr "type" "mvi")]) + +(define_insn "builtin_ctpop" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_CTPOP))] + "TARGET_CIX" + "ctpop %1,%0" + [(set_attr "type" "mvi")]) + ;; The call patterns are at the end of the file because their ;; wildcard operand0 interferes with nice recognition. @@ -7021,7 +7805,7 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" (plus:DI (pc) (const_int 4))) (unspec_volatile [(reg:DI 29)] UNSPECV_BLOCKAGE) (use (match_operand 3 "" "")) - (use (match_operand 4 "const_int_operand" ""))] + (use (match_operand 4 "" ""))] "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" "jsr $26,(%1),%3%J4" [(set_attr "type" "jsr")]) @@ -7041,6 +7825,70 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" [(set_attr "type" "jsr") (set_attr "length" "*,*,8")]) +(define_insn_and_split "call_value_osf_tlsgd" + [(set (match_operand 0 "" "") + (call (mem:DI (match_operand:DI 1 "symbolic_operand" "")) + (const_int 0))) + (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSGD_CALL) + (use (reg:DI 29)) + (clobber (reg:DI 26))] + "HAVE_AS_TLS" + "#" + "&& reload_completed" + [(set (match_dup 3) + (unspec:DI [(match_dup 5) + (match_dup 1) + (match_dup 2)] UNSPEC_LITERAL)) + (parallel [(set (match_dup 0) + (call (mem:DI (match_dup 3)) + (const_int 0))) + (set (reg:DI 26) (plus:DI (pc) (const_int 4))) + (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE) + (use (match_dup 1)) + (use (unspec [(match_dup 2)] UNSPEC_TLSGD_CALL))]) + (set (match_dup 5) + (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1)) + (set (match_dup 5) + (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))] +{ + operands[3] = gen_rtx_REG (Pmode, 27); + operands[4] = GEN_INT (alpha_next_sequence_number++); + operands[5] = pic_offset_table_rtx; +} + [(set_attr "type" "multi")]) + +(define_insn_and_split "call_value_osf_tlsldm" + [(set (match_operand 0 "" "") + (call (mem:DI (match_operand:DI 1 "symbolic_operand" "")) + (const_int 0))) + (unspec [(match_operand:DI 2 "const_int_operand" "")] UNSPEC_TLSLDM_CALL) + (use (reg:DI 29)) + (clobber (reg:DI 26))] + "HAVE_AS_TLS" + "#" + "&& reload_completed" + [(set (match_dup 3) + (unspec:DI [(match_dup 5) + (match_dup 1) + (match_dup 2)] UNSPEC_LITERAL)) + (parallel [(set (match_dup 0) + (call (mem:DI (match_dup 3)) + (const_int 0))) + (set (reg:DI 26) (plus:DI (pc) (const_int 4))) + (unspec_volatile [(match_dup 5)] UNSPECV_BLOCKAGE) + (use (match_dup 1)) + (use (unspec [(match_dup 2)] UNSPEC_TLSLDM_CALL))]) + (set (reg:DI 29) + (unspec_volatile:DI [(reg:DI 26) (match_dup 4)] UNSPECV_LDGP1)) + (set (reg:DI 29) + (unspec:DI [(reg:DI 29) (match_dup 4)] UNSPEC_LDGP2))] +{ + operands[3] = gen_rtx_REG (Pmode, 27); + operands[4] = GEN_INT (alpha_next_sequence_number++); + operands[5] = pic_offset_table_rtx; +} + [(set_attr "type" "multi")]) + (define_insn "*call_value_osf_1" [(set (match_operand 0 "" "") (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) @@ -7092,18 +7940,32 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" [(set_attr "type" "jsr") (set_attr "length" "*,*,12")]) +; GAS relies on the order and position of instructions output below in order +; to generate relocs for VMS link to potentially optimize the call. +; Please do not molest. (define_insn "*call_value_vms_1" [(set (match_operand 0 "" "") (call (mem:DI (match_operand:DI 1 "call_operand" "r,s")) (match_operand 2 "" ""))) - (use (match_operand:DI 3 "nonimmediate_operand" "r,m")) + (use (match_operand:DI 3 "nonmemory_operand" "r,n")) (use (reg:DI 25)) (use (reg:DI 26)) (clobber (reg:DI 27))] "TARGET_ABI_OPEN_VMS" - "@ - mov %3,$27\;jsr $26,0\;ldq $27,0($29) - ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)" + "* +{ + switch (which_alternative) + { + case 0: + return \"mov %3,$27\;jsr $26,0\;ldq $27,0($29)\"; + case 1: + operands [3] = alpha_use_linkage (operands [1], cfun->decl, 1, 0); + operands [4] = alpha_use_linkage (operands [1], cfun->decl, 0, 0); + return \"ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)\"; + default: + abort(); + } +}" [(set_attr "type" "jsr") (set_attr "length" "12,16")]) @@ -7116,4 +7978,3 @@ fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,multi" "TARGET_ABI_UNICOSMK" "jsr $26,(%1)" [(set_attr "type" "jsr")]) - diff --git a/contrib/gcc/config/alpha/ev4.md b/contrib/gcc/config/alpha/ev4.md new file mode 100644 index 0000000..41e1efd --- /dev/null +++ b/contrib/gcc/config/alpha/ev4.md @@ -0,0 +1,147 @@ +;; Scheduling description for Alpha EV4. +;; Copyright (C) 2002 Free Software Foundation, Inc. +;; +;; This file is part of GNU CC. +;; +;; GNU CC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. +;; +;; GNU CC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GNU CC; see the file COPYING. If not, write to +;; the Free Software Foundation, 59 Temple Place - Suite 330, +;; Boston, MA 02111-1307, USA. + +; On EV4 there are two classes of resources to consider: resources needed +; to issue, and resources needed to execute. IBUS[01] are in the first +; category. ABOX, BBOX, EBOX, FBOX, IMUL & FDIV make up the second. +; (There are a few other register-like resources, but ...) + +(define_automaton "ev4_0,ev4_1,ev4_2") +(define_cpu_unit "ev4_ib0,ev4_ib1,ev4_abox,ev4_bbox" "ev4_0") +(define_cpu_unit "ev4_ebox,ev4_imul" "ev4_1") +(define_cpu_unit "ev4_fbox,ev4_fdiv" "ev4_2") +(define_reservation "ev4_ib01" "ev4_ib0|ev4_ib1") + +; Assume type "multi" single issues. +(define_insn_reservation "ev4_multi" 1 + (and (eq_attr "cpu" "ev4") + (eq_attr "type" "multi")) + "ev4_ib0+ev4_ib1") + +; Loads from L0 completes in three cycles. adjust_cost still factors +; in user-specified memory latency, so return 1 here. +(define_insn_reservation "ev4_ld" 1 + (and (eq_attr "cpu" "ev4") + (eq_attr "type" "ild,fld,ldsym")) + "ev4_ib01+ev4_abox") + +; Stores can issue before the data (but not address) is ready. +(define_insn_reservation "ev4_ist" 1 + (and (eq_attr "cpu" "ev4") + (eq_attr "type" "ist")) + "ev4_ib1+ev4_abox") + +(define_insn_reservation "ev4_fst" 1 + (and (eq_attr "cpu" "ev4") + (eq_attr "type" "fst")) + "ev4_ib0+ev4_abox") + +; Branches have no delay cost, but do tie up the unit for two cycles. +(define_insn_reservation "ev4_ibr" 2 + (and (eq_attr "cpu" "ev4") + (eq_attr "type" "ibr,jsr")) + "ev4_ib1+ev4_bbox,ev4_bbox") + +(define_insn_reservation "ev4_callpal" 2 + (and (eq_attr "cpu" "ev4") + (eq_attr "type" "callpal")) + "ev4_ib1+ev4_bbox,ev4_bbox") + +(define_insn_reservation "ev4_fbr" 2 + (and (eq_attr "cpu" "ev4") + (eq_attr "type" "fbr")) + "ev4_ib0+ev4_bbox,ev4_bbox") + +; Arithmetic insns are normally have their results available after +; two cycles. There are a number of exceptions. + +(define_insn_reservation "ev4_iaddlog" 2 + (and (eq_attr "cpu" "ev4") + (eq_attr "type" "iadd,ilog")) + "ev4_ib0+ev4_ebox") + +(define_bypass 1 + "ev4_iaddlog" + "ev4_ibr,ev4_iaddlog,ev4_shiftcm,ev4_icmp,ev4_imulsi,ev4_imuldi") + +(define_insn_reservation "ev4_shiftcm" 2 + (and (eq_attr "cpu" "ev4") + (eq_attr "type" "shift,icmov")) + "ev4_ib0+ev4_ebox") + +(define_insn_reservation "ev4_icmp" 2 + (and (eq_attr "cpu" "ev4") + (eq_attr "type" "icmp")) + "ev4_ib0+ev4_ebox") + +(define_bypass 1 "ev4_icmp" "ev4_ibr") + +(define_bypass 0 + "ev4_iaddlog,ev4_shiftcm,ev4_icmp" + "ev4_ist" + "store_data_bypass_p") + +; Multiplies use a non-piplined imul unit. Also, "no [ebox] insn can +; be issued exactly three cycles before an integer multiply completes". + +(define_insn_reservation "ev4_imulsi" 21 + (and (eq_attr "cpu" "ev4") + (and (eq_attr "type" "imul") + (eq_attr "opsize" "si"))) + "ev4_ib0+ev4_imul,ev4_imul*18,ev4_ebox") + +(define_bypass 20 "ev4_imulsi" "ev4_ist" "store_data_bypass_p") + +(define_insn_reservation "ev4_imuldi" 23 + (and (eq_attr "cpu" "ev4") + (and (eq_attr "type" "imul") + (eq_attr "opsize" "!si"))) + "ev4_ib0+ev4_imul,ev4_imul*20,ev4_ebox") + +(define_bypass 22 "ev4_imuldi" "ev4_ist" "store_data_bypass_p") + +; Most FP insns have a 6 cycle latency, but with a 4 cycle bypass back in. +(define_insn_reservation "ev4_fpop" 6 + (and (eq_attr "cpu" "ev4") + (eq_attr "type" "fadd,fmul,fcpys,fcmov")) + "ev4_ib1+ev4_fbox") + +(define_bypass 4 "ev4_fpop" "ev4_fpop") + +; The floating point divider is not pipelined. Also, "no FPOP insn can be +; issued exactly five or exactly six cycles before an fdiv insn completes". + +(define_insn_reservation "ev4_fdivsf" 34 + (and (eq_attr "cpu" "ev4") + (and (eq_attr "type" "fdiv") + (eq_attr "opsize" "si"))) + "ev4_ib1+ev4_fdiv,ev4_fdiv*28,ev4_fdiv+ev4_fbox,ev4_fbox") + +(define_insn_reservation "ev4_fdivdf" 63 + (and (eq_attr "cpu" "ev4") + (and (eq_attr "type" "fdiv") + (eq_attr "opsize" "di"))) + "ev4_ib1+ev4_fdiv,ev4_fdiv*57,ev4_fdiv+ev4_fbox,ev4_fbox") + +; Traps don't consume or produce data. +(define_insn_reservation "ev4_misc" 1 + (and (eq_attr "cpu" "ev4") + (eq_attr "type" "misc")) + "ev4_ib1") diff --git a/contrib/gcc/config/alpha/ev5.md b/contrib/gcc/config/alpha/ev5.md new file mode 100644 index 0000000..832cf6b --- /dev/null +++ b/contrib/gcc/config/alpha/ev5.md @@ -0,0 +1,190 @@ +;; Scheduling description for Alpha EV5. +;; Copyright (C) 2002 Free Software Foundation, Inc. +;; +;; This file is part of GNU CC. +;; +;; GNU CC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. +;; +;; GNU CC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GNU CC; see the file COPYING. If not, write to +;; the Free Software Foundation, 59 Temple Place - Suite 330, +;; Boston, MA 02111-1307, USA. + +;; EV5 has two asymetric integer units, E0 and E1, plus separate +;; FP add and multiply units. + +(define_automaton "ev5_0,ev5_1") +(define_cpu_unit "ev5_e0,ev5_e1,ev5_fa,ev5_fm" "ev5_0") +(define_reservation "ev5_e01" "ev5_e0|ev5_e1") +(define_reservation "ev5_fam" "ev5_fa|ev5_fm") +(define_cpu_unit "ev5_imul" "ev5_0") +(define_cpu_unit "ev5_fdiv" "ev5_1") + +; Assume type "multi" single issues. +(define_insn_reservation "ev5_multi" 1 + (and (eq_attr "cpu" "ev5") + (eq_attr "type" "multi")) + "ev5_e0+ev5_e1+ev5_fa+ev5_fm") + +; Stores can only issue to E0, and may not issue with loads. +; Model this with some fake units. + +(define_cpu_unit "ev5_l0,ev5_l1,ev5_st" "ev5_0") +(define_reservation "ev5_ld" "ev5_l0|ev5_l1") +(exclusion_set "ev5_l0,ev5_l1" "ev5_st") + +(define_insn_reservation "ev5_st" 1 + (and (eq_attr "cpu" "ev5") + (eq_attr "type" "ist,fst")) + "ev5_e0+ev5_st") + +; Loads from L0 complete in two cycles. adjust_cost still factors +; in user-specified memory latency, so return 1 here. +(define_insn_reservation "ev5_ld" 1 + (and (eq_attr "cpu" "ev5") + (eq_attr "type" "ild,fld,ldsym")) + "ev5_e01+ev5_ld") + +; Integer branches slot only to E1. +(define_insn_reservation "ev5_ibr" 1 + (and (eq_attr "cpu" "ev5") + (eq_attr "type" "ibr")) + "ev5_e1") + +(define_insn_reservation "ev5_callpal" 1 + (and (eq_attr "cpu" "ev5") + (eq_attr "type" "callpal")) + "ev5_e1") + +(define_insn_reservation "ev5_jsr" 1 + (and (eq_attr "cpu" "ev5") + (eq_attr "type" "jsr")) + "ev5_e1") + +(define_insn_reservation "ev5_shift" 1 + (and (eq_attr "cpu" "ev5") + (eq_attr "type" "shift")) + "ev5_e0") + +(define_insn_reservation "ev5_mvi" 2 + (and (eq_attr "cpu" "ev5") + (eq_attr "type" "mvi")) + "ev5_e0") + +(define_insn_reservation "ev5_cmov" 2 + (and (eq_attr "cpu" "ev5") + (eq_attr "type" "icmov")) + "ev5_e01") + +(define_insn_reservation "ev5_iadd" 1 + (and (eq_attr "cpu" "ev5") + (eq_attr "type" "iadd")) + "ev5_e01") + +(define_insn_reservation "ev5_ilogcmp" 1 + (and (eq_attr "cpu" "ev5") + (eq_attr "type" "ilog,icmp")) + "ev5_e01") + +; Conditional move and branch can issue the same cycle as the test. +(define_bypass 0 "ev5_ilogcmp" "ev5_ibr,ev5_cmov" "if_test_bypass_p") + +; Multiplies use a non-piplined imul unit. Also, "no insn can be issued +; to E0 exactly two cycles before an integer multiply completes". + +(define_insn_reservation "ev5_imull" 8 + (and (eq_attr "cpu" "ev5") + (and (eq_attr "type" "imul") + (eq_attr "opsize" "si"))) + "ev5_e0+ev5_imul,ev5_imul*3,nothing,ev5_e0") + +(define_insn_reservation "ev5_imulq" 12 + (and (eq_attr "cpu" "ev5") + (and (eq_attr "type" "imul") + (eq_attr "opsize" "di"))) + "ev5_e0+ev5_imul,ev5_imul*7,nothing,ev5_e0") + +(define_insn_reservation "ev5_imulh" 14 + (and (eq_attr "cpu" "ev5") + (and (eq_attr "type" "imul") + (eq_attr "opsize" "udi"))) + "ev5_e0+ev5_imul,ev5_imul*7,nothing*3,ev5_e0") + +; The multiplier is unable to receive data from Ebox bypass paths. The +; instruction issues at the expected time, but its latency is increased +; by the time it takes for the input data to become available to the +; multiplier. For example, an IMULL instruction issued one cycle later +; than an ADDL instruction, which produced one of its operands, has a +; latency of 10 (8 + 2). If the IMULL instruction is issued two cycles +; later than the ADDL instruction, the latency is 9 (8 + 1). +; +; Model this instead with increased latency on the input instruction. + +(define_bypass 3 + "ev5_ld,ev5_shift,ev5_mvi,ev5_cmov,ev5_iadd,ev5_ilogcmp" + "ev5_imull,ev5_imulq,ev5_imulh") + +(define_bypass 9 "ev5_imull" "ev5_imull,ev5_imulq,ev5_imulh") +(define_bypass 13 "ev5_imulq" "ev5_imull,ev5_imulq,ev5_imulh") +(define_bypass 15 "ev5_imulh" "ev5_imull,ev5_imulq,ev5_imulh") + +; Similarly for the FPU we have two asymetric units. + +(define_insn_reservation "ev5_fadd" 4 + (and (eq_attr "cpu" "ev5") + (eq_attr "type" "fadd,fcmov")) + "ev5_fa") + +(define_insn_reservation "ev5_fbr" 1 + (and (eq_attr "cpu" "ev5") + (eq_attr "type" "fbr")) + "ev5_fa") + +(define_insn_reservation "ev5_fcpys" 4 + (and (eq_attr "cpu" "ev5") + (eq_attr "type" "fcpys")) + "ev5_fam") + +(define_insn_reservation "ev5_fmul" 4 + (and (eq_attr "cpu" "ev5") + (eq_attr "type" "fmul")) + "ev5_fm") + +; The floating point divider is not pipelined. Also, "no insn can be issued +; to FA exactly five before an fdiv insn completes". +; +; ??? Do not model this late reservation due to the enormously increased +; size of the resulting DFA. +; +; ??? Putting ev5_fa and ev5_fdiv alone into the same automata produces +; a DFA of acceptable size, but putting ev5_fm and ev5_fa into separate +; automata produces incorrect results for insns that can choose one or +; the other, i.e. ev5_fcpys. + +(define_insn_reservation "ev5_fdivsf" 15 + (and (eq_attr "cpu" "ev5") + (and (eq_attr "type" "fdiv") + (eq_attr "opsize" "si"))) + ; "ev5_fa+ev5_fdiv,ev5_fdiv*9,ev5_fa+ev5_fdiv,ev5_fdiv*4" + "ev5_fa+ev5_fdiv,ev5_fdiv*14") + +(define_insn_reservation "ev5_fdivdf" 22 + (and (eq_attr "cpu" "ev5") + (and (eq_attr "type" "fdiv") + (eq_attr "opsize" "di"))) + ; "ev5_fa+ev5_fdiv,ev5_fdiv*17,ev5_fa+ev5_fdiv,ev5_fdiv*4" + "ev5_fa+ev5_fdiv,ev5_fdiv*21") + +; Traps don't consume or produce data; rpcc is latency 2 if we ever add it. +(define_insn_reservation "ev5_misc" 2 + (and (eq_attr "cpu" "ev5") + (eq_attr "type" "misc")) + "ev5_e0") diff --git a/contrib/gcc/config/alpha/ev6.md b/contrib/gcc/config/alpha/ev6.md new file mode 100644 index 0000000..12204b6 --- /dev/null +++ b/contrib/gcc/config/alpha/ev6.md @@ -0,0 +1,173 @@ +;; Scheduling description for Alpha EV6. +;; Copyright (C) 2002 Free Software Foundation, Inc. +;; +;; This file is part of GNU CC. +;; +;; GNU CC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 2, or (at your option) +;; any later version. +;; +;; GNU CC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. +;; +;; You should have received a copy of the GNU General Public License +;; along with GNU CC; see the file COPYING. If not, write to +;; the Free Software Foundation, 59 Temple Place - Suite 330, +;; Boston, MA 02111-1307, USA. + +; EV6 can issue 4 insns per clock. It's out-of-order, so this isn't +; expected to help over-much, but a precise description can be important +; for software pipelining. +; +; EV6 has two symmetric pairs ("clusters") of two asymetric integer +; units ("upper" and "lower"), yielding pipe names U0, U1, L0, L1. +; +; ??? The clusters have independent register files that are re-synced +; every cycle. Thus there is one additional cycle of latency between +; insns issued on different clusters. Possibly model that by duplicating +; all EBOX insn_reservations that can issue to either cluster, increasing +; all latencies by one, and adding bypasses within the cluster. +; +; ??? In addition, instruction order affects cluster issue. + +(define_automaton "ev6_0,ev6_1") +(define_cpu_unit "ev6_u0,ev6_u1,ev6_l0,ev6_l1" "ev6_0") +(define_reservation "ev6_u" "ev6_u0|ev6_u1") +(define_reservation "ev6_l" "ev6_l0|ev6_l1") +(define_reservation "ev6_ebox" "ev6_u|ev6_l") + +(define_cpu_unit "ev6_fa" "ev6_1") +(define_cpu_unit "ev6_fm,ev6_fst0,ev6_fst1" "ev6_0") +(define_reservation "ev6_fst" "ev6_fst0|ev6_fst1") + +; Assume type "multi" single issues. +(define_insn_reservation "ev6_multi" 1 + (and (eq_attr "cpu" "ev6") + (eq_attr "type" "multi")) + "ev6_u0+ev6_u1+ev6_l0+ev6_l1+ev6_fa+ev6_fm+ev6_fst0+ev6_fst1") + +; Integer loads take at least 3 clocks, and only issue to lower units. +; adjust_cost still factors in user-specified memory latency, so return 1 here. +(define_insn_reservation "ev6_ild" 1 + (and (eq_attr "cpu" "ev6") + (eq_attr "type" "ild,ldsym")) + "ev6_l") + +(define_insn_reservation "ev6_ist" 1 + (and (eq_attr "cpu" "ev6") + (eq_attr "type" "ist")) + "ev6_l") + +; FP loads take at least 4 clocks. adjust_cost still factors +; in user-specified memory latency, so return 2 here. +(define_insn_reservation "ev6_fld" 2 + (and (eq_attr "cpu" "ev6") + (eq_attr "type" "fld")) + "ev6_l") + +; The FPU communicates with memory and the integer register file +; via two fp store units. We need a slot in the fst immediately, and +; a slot in LOW after the operand data is ready. At which point the +; data may be moved either to the store queue or the integer register +; file and the insn retired. + +(define_insn_reservation "ev6_fst" 3 + (and (eq_attr "cpu" "ev6") + (eq_attr "type" "fst")) + "ev6_fst,nothing,ev6_l") + +; Arithmetic goes anywhere. +(define_insn_reservation "ev6_arith" 1 + (and (eq_attr "cpu" "ev6") + (eq_attr "type" "iadd,ilog,icmp")) + "ev6_ebox") + +; Motion video insns also issue only to U0, and take three ticks. +(define_insn_reservation "ev6_mvi" 3 + (and (eq_attr "cpu" "ev6") + (eq_attr "type" "mvi")) + "ev6_u0") + +; Shifts issue to upper units. +(define_insn_reservation "ev6_shift" 1 + (and (eq_attr "cpu" "ev6") + (eq_attr "type" "shift")) + "ev6_u") + +; Multiplies issue only to U1, and all take 7 ticks. +(define_insn_reservation "ev6_imul" 7 + (and (eq_attr "cpu" "ev6") + (eq_attr "type" "imul")) + "ev6_u1") + +; Conditional moves decompose into two independent primitives, each taking +; one cycle. Since ev6 is out-of-order, we can't see anything but two cycles. +(define_insn_reservation "ev6_icmov" 2 + (and (eq_attr "cpu" "ev6") + (eq_attr "type" "icmov")) + "ev6_ebox,ev6_ebox") + +; Integer branches issue to upper units +(define_insn_reservation "ev6_ibr" 1 + (and (eq_attr "cpu" "ev6") + (eq_attr "type" "ibr,callpal")) + "ev6_u") + +; Calls only issue to L0. +(define_insn_reservation "ev6_jsr" 1 + (and (eq_attr "cpu" "ev6") + (eq_attr "type" "jsr")) + "ev6_l0") + +; Ftoi/itof only issue to lower pipes. +(define_insn_reservation "ev6_itof" 3 + (and (eq_attr "cpu" "ev6") + (eq_attr "type" "itof")) + "ev6_l") + +(define_insn_reservation "ev6_ftoi" 3 + (and (eq_attr "cpu" "ev6") + (eq_attr "type" "ftoi")) + "ev6_fst,nothing,ev6_l") + +(define_insn_reservation "ev6_fmul" 4 + (and (eq_attr "cpu" "ev6") + (eq_attr "type" "fmul")) + "ev6_fm") + +(define_insn_reservation "ev6_fadd" 4 + (and (eq_attr "cpu" "ev6") + (eq_attr "type" "fadd,fcpys,fbr")) + "ev6_fa") + +(define_insn_reservation "ev6_fcmov" 8 + (and (eq_attr "cpu" "ev6") + (eq_attr "type" "fcmov")) + "ev6_fa,nothing*3,ev6_fa") + +(define_insn_reservation "ev6_fdivsf" 12 + (and (eq_attr "cpu" "ev6") + (and (eq_attr "type" "fdiv") + (eq_attr "opsize" "si"))) + "ev6_fa*9") + +(define_insn_reservation "ev6_fdivdf" 15 + (and (eq_attr "cpu" "ev6") + (and (eq_attr "type" "fdiv") + (eq_attr "opsize" "di"))) + "ev6_fa*12") + +(define_insn_reservation "ev6_sqrtsf" 18 + (and (eq_attr "cpu" "ev6") + (and (eq_attr "type" "fsqrt") + (eq_attr "opsize" "si"))) + "ev6_fa*15") + +(define_insn_reservation "ev6_sqrtdf" 33 + (and (eq_attr "cpu" "ev6") + (and (eq_attr "type" "fsqrt") + (eq_attr "opsize" "di"))) + "ev6_fa*30") diff --git a/contrib/gcc/config/alpha/gnu.h b/contrib/gcc/config/alpha/gnu.h new file mode 100644 index 0000000..9b25daf --- /dev/null +++ b/contrib/gcc/config/alpha/gnu.h @@ -0,0 +1,30 @@ +/* Configuration for an Alpha running GNU with ELF as the target machine. */ + +#undef TARGET_VERSION +#define TARGET_VERSION fprintf (stderr, " (Alpha GNU)"); + +#undef TARGET_OS_CPP_BUILTINS /* config.gcc includes alpha/linux.h. */ +#define TARGET_OS_CPP_BUILTINS() \ + do { \ + builtin_define ("__GNU__"); \ + builtin_define ("__ELF__"); \ + builtin_define ("__gnu_hurd__"); \ + builtin_define ("_LONGLONG"); \ + builtin_define_std ("unix"); \ + builtin_assert ("system=gnu"); \ + } while (0) + +#undef ELF_DYNAMIC_LINKER +#define ELF_DYNAMIC_LINKER "/lib/ld.so" + +#undef STARTFILE_SPEC +#define STARTFILE_SPEC \ + "%{!shared: \ + %{!static: \ + %{pg:gcrt1.o%s} %{!pg:%{p:gcrt1.o%s} %{!p:crt1.o%s}}} \ + %{static:crt0.o%s}} \ + crti.o%s \ + %{!static:%{!shared:crtbegin.o%s} %{shared:crtbeginS.o%s}}" + +/* FIXME: Is a Hurd-specific fallback mechanism necessary? */ +#undef MD_FALLBACK_FRAME_STATE_FOR diff --git a/contrib/gcc/config/alpha/linux-elf.h b/contrib/gcc/config/alpha/linux-elf.h index 6430059..49f5181 100644 --- a/contrib/gcc/config/alpha/linux-elf.h +++ b/contrib/gcc/config/alpha/linux-elf.h @@ -27,17 +27,23 @@ Boston, MA 02111-1307, USA. */ #define SUBTARGET_EXTRA_SPECS \ { "elf_dynamic_linker", ELF_DYNAMIC_LINKER }, -#undef SUB_CPP_PREDEFINES -#define SUB_CPP_PREDEFINES "-D__ELF__" - #ifdef USE_GNULIBC_1 #define ELF_DYNAMIC_LINKER "/lib/ld.so.1" #else #define ELF_DYNAMIC_LINKER "/lib/ld-linux.so.2" #endif +#define LINK_SPEC "-m elf64alpha %{G*} %{relax:-relax} \ + %{O*:-O3} %{!O*:-O1} \ + %{shared:-shared} \ + %{!shared: \ + %{!static: \ + %{rdynamic:-export-dynamic} \ + %{!dynamic-linker:-dynamic-linker %(elf_dynamic_linker)}} \ + %{static:-static}}" + #ifndef USE_GNULIBC_1 #undef LIB_SPEC #define LIB_SPEC \ -"%{shared:-lc}%{!shared:%{pthread:-lpthread }%{profile:-lc_p}%{!profile:-lc}} " +"%{pthread:-lpthread }%{shared:-lc}%{!shared:%{profile:-lc_p}%{!profile:-lc}} " #endif diff --git a/contrib/gcc/config/alpha/linux.h b/contrib/gcc/config/alpha/linux.h index 912d7b26..0c53344 100644 --- a/contrib/gcc/config/alpha/linux.h +++ b/contrib/gcc/config/alpha/linux.h @@ -23,20 +23,23 @@ Boston, MA 02111-1307, USA. */ #undef TARGET_DEFAULT #define TARGET_DEFAULT (MASK_FP | MASK_FPREGS | MASK_GAS) -#undef CPP_PREDEFINES -#define CPP_PREDEFINES \ -"-D__gnu_linux__ -Dlinux -Dunix -Asystem=linux -D_LONGLONG -D__alpha__ " \ -SUB_CPP_PREDEFINES - -/* The GNU C++ standard library requires that these macros be defined. */ -#undef CPLUSPLUS_CPP_SPEC -#define CPLUSPLUS_CPP_SPEC "-D_GNU_SOURCE %(cpp)" +#define TARGET_OS_CPP_BUILTINS() \ + do { \ + builtin_define ("__gnu_linux__"); \ + builtin_define ("_LONGLONG"); \ + builtin_define_std ("linux"); \ + builtin_define_std ("unix"); \ + builtin_assert ("system=linux"); \ + /* The GNU C++ standard library requires this. */ \ + if (c_language == clk_cplusplus) \ + builtin_define ("_GNU_SOURCE"); \ + } while (0) #undef LIB_SPEC #define LIB_SPEC \ - "%{shared: -lc} \ - %{!shared: %{pthread:-lpthread} \ - %{profile:-lc_p} %{!profile: -lc}}" + "%{pthread:-lpthread} \ + %{shared:-lc} \ + %{!shared: %{profile:-lc_p}%{!profile:-lc}}" /* Show that we need a GP when profiling. */ #undef TARGET_PROFILING_NEEDS_GP @@ -56,6 +59,8 @@ SUB_CPP_PREDEFINES /* Define this so that all GNU/Linux targets handle the same pragmas. */ #define HANDLE_PRAGMA_PACK_PUSH_POP +#define TARGET_HAS_F_SETLKW + /* Do code reading to identify a signal frame, and set the frame state data appropriately. See unwind-dw2.c for the structs. */ diff --git a/contrib/gcc/config/alpha/netbsd.h b/contrib/gcc/config/alpha/netbsd.h index 9a54c3a..e1da9cf 100644 --- a/contrib/gcc/config/alpha/netbsd.h +++ b/contrib/gcc/config/alpha/netbsd.h @@ -22,9 +22,16 @@ Boston, MA 02111-1307, USA. */ #undef TARGET_DEFAULT #define TARGET_DEFAULT (MASK_FP | MASK_FPREGS | MASK_GAS) -#undef CPP_PREDEFINES -#define CPP_PREDEFINES \ - "-D__NetBSD__ -D__ELF__ -D_LP64 -Asystem=unix -Asystem=NetBSD" +#define TARGET_OS_CPP_BUILTINS() \ + do { \ + NETBSD_OS_CPP_BUILTINS_ELF(); \ + NETBSD_OS_CPP_BUILTINS_LP64(); \ + } while (0) + + +/* NetBSD doesn't use the LANGUAGE* built-ins. */ +#undef SUBTARGET_LANGUAGE_CPP_BUILTINS +#define SUBTARGET_LANGUAGE_CPP_BUILTINS() /* nothing */ /* Show that we need a GP when profiling. */ @@ -32,39 +39,28 @@ Boston, MA 02111-1307, USA. */ #define TARGET_PROFILING_NEEDS_GP 1 -/* Provide a CPP_SPEC appropriate for NetBSD/alpha. In addition to - the standard NetBSD specs, we also handle Alpha FP mode indications. */ - -#undef CPP_SPEC -#define CPP_SPEC \ - "%{mieee:-D_IEEE_FP} \ - %{mieee-with-inexact:-D_IEEE_FP -D_IEEE_FP_INEXACT} \ - %(cpp_cpu) %(cpp_subtarget)" +/* Provide a CPP_SUBTARGET_SPEC appropriate for NetBSD/alpha. We use + this to pull in CPP specs that all NetBSD configurations need. */ #undef CPP_SUBTARGET_SPEC -#define CPP_SUBTARGET_SPEC \ - "%{posix:-D_POSIX_SOURCE}" +#define CPP_SUBTARGET_SPEC NETBSD_CPP_SPEC + +#undef SUBTARGET_EXTRA_SPECS +#define SUBTARGET_EXTRA_SPECS \ + { "netbsd_link_spec", NETBSD_LINK_SPEC_ELF }, \ + { "netbsd_entry_point", NETBSD_ENTRY_POINT }, \ + { "netbsd_endfile_spec", NETBSD_ENDFILE_SPEC }, -/* Provide a LINK_SPEC appropriate for a NetBSD/alpha ELF target. - This is a copy of LINK_SPEC from <netbsd-elf.h> tweaked for - the alpha target. */ +/* Provide a LINK_SPEC appropriate for a NetBSD/alpha ELF target. */ #undef LINK_SPEC -#define LINK_SPEC \ - "%{G*} %{relax:-relax} \ - %{O*:-O3} %{!O*:-O1} \ - %{assert*} %{R*} \ - %{shared:-shared} \ - %{!shared: \ - -dc -dp \ - %{!nostdlib: \ - %{!r*: \ - %{!e*:-e __start}}} \ - %{!static: \ - %{rdynamic:-export-dynamic} \ - %{!dynamic-linker:-dynamic-linker /usr/libexec/ld.elf_so}} \ - %{static:-static}}" +#define LINK_SPEC \ + "%{G*} %{relax:-relax} \ + %{O*:-O3} %{!O*:-O1} \ + %(netbsd_link_spec)" + +#define NETBSD_ENTRY_POINT "__start" /* Provide an ENDFILE_SPEC appropriate for NetBSD/alpha ELF. Here we @@ -76,7 +72,12 @@ Boston, MA 02111-1307, USA. */ #undef ENDFILE_SPEC #define ENDFILE_SPEC \ "%{ffast-math|funsafe-math-optimizations:crtfm%O%s} \ - %{!shared:crtend%O%s} %{shared:crtendS%O%s}" + %(netbsd_endfile_spec)" + + +/* Attempt to enable execute permissions on the stack. */ + +#define TRANSFER_FROM_TRAMPOLINE NETBSD_ENABLE_EXECUTE_STACK #undef TARGET_VERSION diff --git a/contrib/gcc/config/alpha/openbsd.h b/contrib/gcc/config/alpha/openbsd.h index 3424112..b82b66d 100644 --- a/contrib/gcc/config/alpha/openbsd.h +++ b/contrib/gcc/config/alpha/openbsd.h @@ -21,8 +21,6 @@ Boston, MA 02111-1307, USA. */ /* We settle for little endian for now. */ #define TARGET_ENDIAN_DEFAULT 0 -#include <alpha/alpha.h> - #define OBSD_NO_DYNAMIC_LIBRARIES #define OBSD_HAS_DECLARE_FUNCTION_NAME #define OBSD_HAS_DECLARE_FUNCTION_SIZE @@ -41,8 +39,13 @@ Boston, MA 02111-1307, USA. */ "%{!nostdlib:%{!r*:%{!e*:-e __start}}} -dc -dp %{assert*}" /* run-time target specifications */ -#define CPP_PREDEFINES "-D__unix__ -D__ANSI_COMPAT -Asystem=unix \ --D__OpenBSD__ -D__alpha__ -D__alpha" +#define TARGET_OS_CPP_BUILTINS() \ + do { \ + builtin_define ("__OpenBSD__"); \ + builtin_define ("__ANSI_COMPAT"); \ + builtin_define ("__unix__"); \ + builtin_assert ("system=unix"); \ + } while (0) /* Layout of source language data types. */ diff --git a/contrib/gcc/config/alpha/osf.h b/contrib/gcc/config/alpha/osf.h index efb0a16..2be2a42 100644 --- a/contrib/gcc/config/alpha/osf.h +++ b/contrib/gcc/config/alpha/osf.h @@ -1,5 +1,5 @@ /* Definitions of target machine for GNU compiler, for DEC Alpha on OSF/1. - Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2001 + Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2001, 2002, 2003 Free Software Foundation, Inc. Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) @@ -32,14 +32,24 @@ Boston, MA 02111-1307, USA. */ /* Names to predefine in the preprocessor for this target machine. */ -#define CPP_PREDEFINES "\ --Dunix -D__osf__ -D_LONGLONG -DSYSTYPE_BSD \ --D_SYSTYPE_BSD -Asystem=unix -Asystem=xpg4" - -/* Tru64 UNIX V5 requires additional definitions for 16 byte long double - support. Empty by default. */ - -#define CPP_XFLOAT_SPEC "" +#define TARGET_OS_CPP_BUILTINS() \ + do { \ + builtin_define_std ("unix"); \ + builtin_define_std ("SYSTYPE_BSD"); \ + builtin_define ("_SYSTYPE_BSD"); \ + builtin_define ("__osf__"); \ + builtin_define ("__digital__"); \ + builtin_define ("__arch64__"); \ + builtin_define ("_LONGLONG"); \ + builtin_define ("__PRAGMA_EXTERN_PREFIX"); \ + builtin_assert ("system=unix"); \ + builtin_assert ("system=xpg4"); \ + /* Tru64 UNIX V5 has a 16 byte long \ + double type and requires __X_FLOAT \ + to be defined for <math.h>. */ \ + if (LONG_DOUBLE_TYPE_SIZE == 128) \ + builtin_define ("__X_FLOAT"); \ + } while (0) /* Accept DEC C flags for multithreaded programs. We use _PTHREAD_USE_D4 instead of PTHREAD_USE_D4 since both have the same effect and the former @@ -47,8 +57,7 @@ Boston, MA 02111-1307, USA. */ #undef CPP_SUBTARGET_SPEC #define CPP_SUBTARGET_SPEC \ -"%{pthread|threads:-D_REENTRANT} %{threads:-D_PTHREAD_USE_D4} %(cpp_xfloat) \ --D__EXTERN_PREFIX" +"%{pthread|threads:-D_REENTRANT} %{threads:-D_PTHREAD_USE_D4}" /* Under OSF4, -p and -pg require -lprof1, and -lprof1 requires -lpdf. */ @@ -136,9 +145,7 @@ Boston, MA 02111-1307, USA. */ #endif #undef SUBTARGET_EXTRA_SPECS -#define SUBTARGET_EXTRA_SPECS \ - { "cpp_xfloat", CPP_XFLOAT_SPEC }, \ - { "asm_oldas", ASM_OLDAS_SPEC } +#define SUBTARGET_EXTRA_SPECS { "asm_oldas", ASM_OLDAS_SPEC } /* Indicate that we have a stamp.h to use. */ #ifndef CROSS_COMPILE @@ -193,7 +200,7 @@ __enable_execute_stack (addr) \ #define ASM_OUTPUT_WEAK_ALIAS(FILE, NAME, VALUE) \ do \ { \ - ASM_GLOBALIZE_LABEL (FILE, NAME); \ + (*targetm.asm_out.globalize_label) (FILE, NAME); \ fputs ("\t.weakext\t", FILE); \ assemble_name (FILE, NAME); \ if (VALUE) \ @@ -208,7 +215,6 @@ __enable_execute_stack (addr) \ #define ASM_WEAKEN_LABEL(FILE, NAME) ASM_OUTPUT_WEAK_ALIAS(FILE, NAME, 0) /* Handle #pragma weak and #pragma pack. */ -#undef HANDLE_SYSV_PRAGMA #define HANDLE_SYSV_PRAGMA 1 /* Handle #pragma extern_prefix. Technically only needed for Tru64 5.x, diff --git a/contrib/gcc/config/alpha/osf5.h b/contrib/gcc/config/alpha/osf5.h index c832c57..e483124 100644 --- a/contrib/gcc/config/alpha/osf5.h +++ b/contrib/gcc/config/alpha/osf5.h @@ -18,15 +18,12 @@ the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +/* Tru64 5.1 uses IEEE QUAD format. */ +/* ??? However, since there is no support for VAX H_floating, we must + drop back to a 64-bit long double to avoid a crash looking for the + format associated with TFmode. */ #undef LONG_DOUBLE_TYPE_SIZE -#define LONG_DOUBLE_TYPE_SIZE 128 - -/* Tru64 UNIX V5 has a 16 byte long double type and requires __X_FLOAT to be - defined to get the appropriate prototypes for the long double functions - in <math.h>. */ - -#undef CPP_XFLOAT_SPEC -#define CPP_XFLOAT_SPEC "-D__X_FLOAT" +#define LONG_DOUBLE_TYPE_SIZE (TARGET_FLOAT_VAX ? 64 : 128) /* In Tru64 UNIX V5.1, Compaq introduced a new assembler (/usr/lib/cmplrs/cc/adu) which currently (versions between 3.04.29 and diff --git a/contrib/gcc/config/alpha/t-crtfm b/contrib/gcc/config/alpha/t-crtfm index 7076b51..5ca8c3f 100644 --- a/contrib/gcc/config/alpha/t-crtfm +++ b/contrib/gcc/config/alpha/t-crtfm @@ -1,4 +1,5 @@ EXTRA_PARTS += crtfastmath.o crtfastmath.o: $(srcdir)/config/alpha/crtfastmath.c $(GCC_PASSES) - $(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) -c -o crtfastmath.o $(srcdir)/config/alpha/crtfastmath.c + $(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) -frandom-seed=gcc-crtfastmath -c \ + -o crtfastmath.o $(srcdir)/config/alpha/crtfastmath.c diff --git a/contrib/gcc/config/alpha/unicosmk.h b/contrib/gcc/config/alpha/unicosmk.h index 6dbe1a3..8f7b53d 100644 --- a/contrib/gcc/config/alpha/unicosmk.h +++ b/contrib/gcc/config/alpha/unicosmk.h @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for DEC Alpha on Cray T3E running Unicos/Mk. - Copyright (C) 2001 + Copyright (C) 2001, 2002 Free Software Foundation, Inc. Contributed by Roman Lechtchinsky (rl@cs.tu-berlin.de) @@ -32,15 +32,18 @@ Boston, MA 02111-1307, USA. */ /* The following defines are necessary for the standard headers to work correctly. */ -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "-D__unix=1 -D_UNICOS=205 -D_CRAY=1 -D_CRAYT3E=1 -D_CRAYMPP=1 -D_CRAYIEEE=1 -D_ADDR64=1 -D_LD64=1 -D__UNICOSMK__ -D__INT_MAX__=9223372036854775807 -D__SHRT_MAX__=2147483647" - -/* Disable software floating point emulation because it requires a 16-bit - type which we do not have. */ - -#ifndef __GNUC__ -#undef REAL_ARITHMETIC -#endif +#define TARGET_OS_CPP_BUILTINS() \ + do { \ + builtin_define ("__unix"); \ + builtin_define ("_UNICOS=205"); \ + builtin_define ("_CRAY"); \ + builtin_define ("_CRAYT3E"); \ + builtin_define ("_CRAYMPP"); \ + builtin_define ("_CRAYIEEE"); \ + builtin_define ("_ADDR64"); \ + builtin_define ("_LD64"); \ + builtin_define ("__UNICOSMK__"); \ + } while (0) #define SHORT_TYPE_SIZE 32 @@ -234,10 +237,7 @@ do { \ On Unicos/Mk, the standard subroutine __T3E_MISMATCH stores all register arguments on the stack. Unfortunately, it doesn't always store the first one (i.e. the one that arrives in $16 or $f16). This is not a problem - with stdargs as we always have at least one named argument there. This is - not always the case when varargs.h is used, however. In such cases, we - have to store the first argument ourselves. We use the information from - the CIW to determine whether the first argument arrives in $16 or $f16. */ + with stdargs as we always have at least one named argument there. */ #undef SETUP_INCOMING_VARARGS #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \ @@ -245,36 +245,9 @@ do { \ { \ if (! (NO_RTL)) \ { \ - int start; \ - \ - start = (CUM).num_reg_words; \ - if (!current_function_varargs || start == 0) \ - ++start; \ + int start = (CUM).num_reg_words + 1; \ \ emit_insn (gen_umk_mismatch_args (GEN_INT (start))); \ - if (current_function_varargs && (CUM).num_reg_words == 0) \ - { \ - rtx tmp; \ - rtx int_label, end_label; \ - \ - tmp = gen_reg_rtx (DImode); \ - emit_move_insn (tmp, \ - gen_rtx_ZERO_EXTRACT (DImode, \ - gen_rtx_REG (DImode, 2),\ - (GEN_INT (1)), \ - (GEN_INT (7)))); \ - int_label = gen_label_rtx (); \ - end_label = gen_label_rtx (); \ - emit_insn (gen_cmpdi (tmp, GEN_INT (0))); \ - emit_jump_insn (gen_beq (int_label)); \ - emit_move_insn (gen_rtx_MEM (DFmode, virtual_incoming_args_rtx),\ - gen_rtx_REG (DFmode, 48)); \ - emit_jump (end_label); \ - emit_label (int_label); \ - emit_move_insn (gen_rtx_MEM (DImode, virtual_incoming_args_rtx),\ - gen_rtx_REG (DImode, 16)); \ - emit_label (end_label); \ - } \ emit_insn (gen_arg_home_umk ()); \ } \ \ @@ -288,19 +261,6 @@ do { \ #undef EPILOGUE_USES #define EPILOGUE_USES(REGNO) ((REGNO) == 26 || (REGNO) == 15) -/* Machine-specific function data. */ - -struct machine_function -{ - /* List of call information words for calls from this function. */ - struct rtx_def *first_ciw; - struct rtx_def *last_ciw; - int ciw_count; - - /* List of deferred case vectors. */ - struct rtx_def *addr_list; -}; - /* Would have worked, only the stack doesn't seem to be executable #undef TRAMPOLINE_TEMPLATE #define TRAMPOLINE_TEMPLATE(FILE) \ @@ -342,9 +302,9 @@ do { fprintf (FILE, "\tbr $1,0\n"); \ #undef DATA_SECTION_ASM_OP #define DATA_SECTION_ASM_OP unicosmk_data_section () -/* There are ni read-only sections on Unicos/Mk. */ +/* There are no read-only sections on Unicos/Mk. */ -#undef READONLY_DATA_SECTION +#undef READONLY_DATA_SECTION_ASM_OP #define READONLY_DATA_SECTION data_section /* Define extra sections for common data and SSIBs (static subroutine @@ -375,16 +335,6 @@ ssib_section () \ in_section = in_ssib; \ } -/* A C expression which evaluates to true if declshould be placed into a - unique section for some target-specific reason. On Unicos/Mk, functions - and public variables are always placed in unique sections. */ - -/* -#define UNIQUE_SECTION_P(DECL) (TREE_PUBLIC (DECL) \ - || TREE_CODE (DECL) == FUNCTION_DECL) -*/ -#define UNIQUE_SECTION(DECL, RELOC) unicosmk_unique_section (DECL, RELOC) - /* This outputs text to go at the start of an assembler file. */ #undef ASM_FILE_START @@ -399,12 +349,6 @@ ssib_section () \ #undef ASM_OUTPUT_SOURCE_FILENAME -/* There is no directive for declaring a label as global. Instead, an - additional colon must be appended when the label is defined. */ - -#undef ASM_GLOBALIZE_LABEL -#define ASM_GLOBALIZE_LABEL(FILE,NAME) - /* This is how to output a label for a jump table. Arguments are the same as for ASM_OUTPUT_INTERNAL_LABEL, except the insn for the jump table is passed. */ @@ -568,38 +512,6 @@ ssib_section () \ #undef ASM_OUTPUT_MAX_SKIP_ALIGN #define ASM_OUTPUT_MAX_SKIP_ALIGN(STREAM,POWER,MAXSKIP) -/* We have to define these because we do not use the floating-point - emulation. Unfortunately, atof does not accept hex literals. */ - -#ifndef REAL_ARITHMETIC -#define REAL_VALUE_ATOF(x,s) atof(x) -#define REAL_VALUE_HTOF(x,s) atof(x) - -#define REAL_VALUE_TO_TARGET_SINGLE(IN, OUT) \ -do { \ - union { \ - float f; \ - HOST_WIDE_INT l; \ - } u; \ - \ - u.f = (IN); \ - (OUT) = (u.l >> 32) & 0xFFFFFFFF; \ -} while (0) - -#define REAL_VALUE_TO_TARGET_DOUBLE(IN, OUT) \ -do { \ - union { \ - REAL_VALUE_TYPE f; \ - HOST_WIDE_INT l; \ - } u; \ - \ - u.f = (IN); \ - (OUT)[0] = (u.l >> 32) & 0xFFFFFFFF; \ - (OUT)[1] = (u.l & 0xFFFFFFFF); \ -} while (0) - -#endif - #undef NM_FLAGS #undef OBJECT_FORMAT_COFF diff --git a/contrib/gcc/config/alpha/vms-cc.c b/contrib/gcc/config/alpha/vms-cc.c index a171b1c..26c3ae3 100644 --- a/contrib/gcc/config/alpha/vms-cc.c +++ b/contrib/gcc/config/alpha/vms-cc.c @@ -109,16 +109,11 @@ preprocess_args (p_argc, argv) if (strcmp (argv[i], "-o") == 0) { char *buff, *ptr; - int out_len; i++; ptr = to_host_file_spec (argv[i]); objfilename = xstrdup (ptr); - out_len = strlen (ptr); - buff = xmalloc (out_len + 6); - - strcpy (buff, "/obj="); - strcat (buff, ptr); + buff = concat ("/obj=", ptr, NULL); addarg (buff); } } @@ -202,11 +197,8 @@ main (argc, argv) strncpy (cwdev, cwd, devlen); cwdev [devlen] = '\0'; - search_dirs = xmalloc (strlen (system_search_dirs) + 1); - strcpy (search_dirs, system_search_dirs); - - defines = xmalloc (strlen (default_defines) + 1); - strcpy (defines, default_defines); + search_dirs = xstrdup (system_search_dirs); + defines = xstrdup (default_defines); addarg ("cc"); preprocess_args (&argc , argv); @@ -251,7 +243,6 @@ main (argc, argv) { /* Assume filename arg */ char buff [256], *ptr; - int buff_len; ptr = to_host_file_spec (argv[i]); arg_len = strlen (ptr); @@ -263,10 +254,7 @@ main (argc, argv) else sprintf (buff, "%s%s", cwd, ptr); - buff_len = strlen (buff); - ptr = xmalloc (buff_len + 1); - - strcpy (ptr, buff); + ptr = xstrdup (buff); addarg (ptr); } } diff --git a/contrib/gcc/config/alpha/vms-crt0-64.c b/contrib/gcc/config/alpha/vms-crt0-64.c index 4120a6b..82ba322 100644 --- a/contrib/gcc/config/alpha/vms-crt0-64.c +++ b/contrib/gcc/config/alpha/vms-crt0-64.c @@ -32,7 +32,7 @@ Boston, MA 02111-1307, USA. */ You Lose! This file can only be compiled with DEC C. #else -/* This file can only be compiled with DEC C, due the the call to +/* This file can only be compiled with DEC C, due to the call to lib$establish and the pragmas pointer_size. */ #pragma __pointer_size short diff --git a/contrib/gcc/config/alpha/vms-crt0.c b/contrib/gcc/config/alpha/vms-crt0.c index e75bc02..b7665f9 100644 --- a/contrib/gcc/config/alpha/vms-crt0.c +++ b/contrib/gcc/config/alpha/vms-crt0.c @@ -32,7 +32,7 @@ Boston, MA 02111-1307, USA. */ You Lose! This file can only be compiled with DEC C. #else -/* This file can only be compiled with DEC C, due the the call to +/* This file can only be compiled with DEC C, due to the call to lib$establish. */ #include <stdlib.h> diff --git a/contrib/gcc/config/alpha/vms-ld.c b/contrib/gcc/config/alpha/vms-ld.c index 83ceaf9..e5688d8 100644 --- a/contrib/gcc/config/alpha/vms-ld.c +++ b/contrib/gcc/config/alpha/vms-ld.c @@ -396,8 +396,7 @@ main (argc, argv) strncpy (cwdev, cwd, devlen); cwdev [devlen] = '\0'; - search_dirs = xmalloc (strlen (system_search_dirs) + 1); - strcpy (search_dirs, system_search_dirs); + search_dirs = xstrdup (system_search_dirs); addarg ("link"); diff --git a/contrib/gcc/config/alpha/vms-psxcrt0-64.c b/contrib/gcc/config/alpha/vms-psxcrt0-64.c index be3e70d..b16e8b4 100644 --- a/contrib/gcc/config/alpha/vms-psxcrt0-64.c +++ b/contrib/gcc/config/alpha/vms-psxcrt0-64.c @@ -32,7 +32,7 @@ Boston, MA 02111-1307, USA. */ You Lose! This file can only be compiled with DEC C. #else -/* This file can only be compiled with DEC C, due the the call to +/* This file can only be compiled with DEC C, due to the call to lib$establish and the pragmas pointer_size. */ #pragma __pointer_size short diff --git a/contrib/gcc/config/alpha/vms-psxcrt0.c b/contrib/gcc/config/alpha/vms-psxcrt0.c index cdf5ced..c4140b4 100644 --- a/contrib/gcc/config/alpha/vms-psxcrt0.c +++ b/contrib/gcc/config/alpha/vms-psxcrt0.c @@ -32,7 +32,7 @@ Boston, MA 02111-1307, USA. */ You Lose! This file can only be compiled with DEC C. #else -/* This file can only be compiled with DEC C, due the the call to +/* This file can only be compiled with DEC C, due to the call to lib$establish. */ #include <stdlib.h> diff --git a/contrib/gcc/config/alpha/vms.h b/contrib/gcc/config/alpha/vms.h index ffc3275..8df6156 100644 --- a/contrib/gcc/config/alpha/vms.h +++ b/contrib/gcc/config/alpha/vms.h @@ -29,17 +29,17 @@ Boston, MA 02111-1307, USA. */ #define NO_EXTERNAL_INDIRECT_ADDRESS -#include "alpha/alpha.h" - -#undef CPP_PREDEFINES -#define CPP_PREDEFINES \ -"-D__ALPHA -Dvms -DVMS -D__vms__ -D__VMS__ -Asystem=vms" - -#undef CPP_SUBTARGET_SPEC -#define CPP_SUBTARGET_SPEC "\ -%{mfloat-ieee:-D__IEEE_FLOAT} \ -%{mfloat-vax:-D__G_FLOAT} \ -%{!mfloat-vax:-D__IEEE_FLOAT}" +#define TARGET_OS_CPP_BUILTINS() \ + do { \ + builtin_define_std ("vms"); \ + builtin_define_std ("VMS"); \ + builtin_define ("__ALPHA"); \ + builtin_assert ("system=vms"); \ + if (TARGET_FLOAT_VAX) \ + builtin_define ("__G_FLOAT"); \ + else \ + builtin_define ("__IEEE_FLOAT"); \ + } while (0) /* By default, allow $ to be part of an identifier. */ #define DOLLARS_IN_IDENTIFIERS 2 @@ -261,26 +261,17 @@ typedef struct {int num_args; enum avms_arg_type atypes[6];} avms_arg_info; } #define LINK_SECTION_ASM_OP "\t.link" -#define READONLY_SECTION_ASM_OP "\t.rdata" +#define READONLY_DATA_SECTION_ASM_OP "\t.rdata" #define LITERALS_SECTION_ASM_OP "\t.literals" #define CTORS_SECTION_ASM_OP "\t.ctors" #define DTORS_SECTION_ASM_OP "\t.dtors" #undef EXTRA_SECTIONS -#define EXTRA_SECTIONS in_link, in_rdata, in_literals +#define EXTRA_SECTIONS in_link, in_literals #undef EXTRA_SECTION_FUNCTIONS #define EXTRA_SECTION_FUNCTIONS \ void \ -readonly_section () \ -{ \ - if (in_section != in_rdata) \ - { \ - fprintf (asm_out_file, "%s\n", READONLY_SECTION_ASM_OP); \ - in_section = in_rdata; \ - } \ -} \ -void \ link_section () \ { \ if (in_section != in_link) \ @@ -299,7 +290,6 @@ literals_section () \ } \ } -extern void readonly_section PARAMS ((void)); extern void link_section PARAMS ((void)); extern void literals_section PARAMS ((void)); @@ -310,11 +300,6 @@ extern void literals_section PARAMS ((void)); #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ fprintf (FILE, "\t.quad $L%d\n", (VALUE)) -#undef READONLY_DATA_SECTION -#define READONLY_DATA_SECTION readonly_section - -#define ASM_FILE_END(FILE) alpha_write_linkage (FILE); - #undef CASE_VECTOR_MODE #define CASE_VECTOR_MODE DImode #undef CASE_VECTOR_PC_RELATIVE @@ -379,8 +364,8 @@ do { \ #undef MIPS_DEBUGGING_INFO #undef DBX_DEBUGGING_INFO -#define DWARF2_DEBUGGING_INFO -#define VMS_DEBUGGING_INFO +#define DWARF2_DEBUGGING_INFO 1 +#define VMS_DEBUGGING_INFO 1 #define DWARF2_UNWIND_INFO 1 @@ -469,7 +454,7 @@ do { \ sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO))) /* ??? VMS uses different linkage. */ -#undef ASM_OUTPUT_MI_THUNK +#undef TARGET_ASM_OUTPUT_MI_THUNK #undef ASM_SPEC #undef ASM_FINAL_SPEC diff --git a/contrib/gcc/config/alpha/vxworks.h b/contrib/gcc/config/alpha/vxworks.h index 2f711ce..a27c645 100644 --- a/contrib/gcc/config/alpha/vxworks.h +++ b/contrib/gcc/config/alpha/vxworks.h @@ -26,10 +26,14 @@ Boston, MA 02111-1307, USA. */ %{!mvxsim: %{!mcpu*|mcpu=21064:-DCPU=21064} %{mcpu=21164:-DCPU=21164}} \ %{posix: -D_POSIX_SOURCE}" -#undef CPP_PREDEFINES -#define CPP_PREDEFINES "\ --D__vxworks -D__alpha_vxworks -Asystem=vxworks \ --Asystem=embedded -D_LONGLONG" +#define TARGET_OS_CPP_BUILTINS() \ + do { \ + builtin_define ("__vxworks"); \ + builtin_define ("__alpha_vxworks"); \ + builtin_define ("_LONGLONG"); \ + builtin_assert ("system=vxworks"); \ + builtin_assert ("system=embedded"); \ + } while (0) /* VxWorks does all the library stuff itself. */ |
