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authorandrew <andrew@FreeBSD.org>2014-12-02 18:12:16 +0000
committerandrew <andrew@FreeBSD.org>2014-12-02 18:12:16 +0000
commit341bb536911855475788d88d8ae286ab7c9bab95 (patch)
tree9748ff5cbc237786991f43d2bb75e888db2f5e63 /contrib/binutils
parentc6eaca622d0df6795d15c9201f60eafee663bb3a (diff)
downloadFreeBSD-src-341bb536911855475788d88d8ae286ab7c9bab95.zip
FreeBSD-src-341bb536911855475788d88d8ae286ab7c9bab95.tar.gz
Allow the UAL APSR_nzcv format for the mrc and mrc2 instructions. The clang
integrated assembler only allows these forms so binutils will need to support them. MFC after: 1 Week Sponsored by: AB Systems Ltd
Diffstat (limited to 'contrib/binutils')
-rw-r--r--contrib/binutils/gas/config/tc-arm.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/contrib/binutils/gas/config/tc-arm.c b/contrib/binutils/gas/config/tc-arm.c
index 37c2a90..184c8a9 100644
--- a/contrib/binutils/gas/config/tc-arm.c
+++ b/contrib/binutils/gas/config/tc-arm.c
@@ -15055,7 +15055,7 @@ static const struct asm_opcode insns[] =
TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
- TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
+ TCE(mrc, e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
#undef ARM_VARIANT
#define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */
@@ -15114,7 +15114,7 @@ static const struct asm_opcode insns[] =
TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc),
TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp),
TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
- TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg),
+ TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg),
#undef ARM_VARIANT
#define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */
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