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authornwhitehorn <nwhitehorn@FreeBSD.org>2015-02-22 20:52:29 +0000
committernwhitehorn <nwhitehorn@FreeBSD.org>2015-02-22 20:52:29 +0000
commit2a7963a7ec9f4cf4eeaf47a02f2126c04249cdd1 (patch)
tree6dceb8d75a5ca35f5c5570b7908ca2255bf31601 /contrib/binutils
parent83dbf494553bec0234b9023f0cf24ff5c1fa3714 (diff)
downloadFreeBSD-src-2a7963a7ec9f4cf4eeaf47a02f2126c04249cdd1.zip
FreeBSD-src-2a7963a7ec9f4cf4eeaf47a02f2126c04249cdd1.tar.gz
Add some opcodes for assembling forthcoming VSX (Vector-Scalar eXtension)
support in the kernel. Userspace programs are expected to rely on LLVM's integrated assembler or newer binutils.
Diffstat (limited to 'contrib/binutils')
-rw-r--r--contrib/binutils/opcodes/ppc-opc.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/contrib/binutils/opcodes/ppc-opc.c b/contrib/binutils/opcodes/ppc-opc.c
index 5995f81..cfd9d30 100644
--- a/contrib/binutils/opcodes/ppc-opc.c
+++ b/contrib/binutils/opcodes/ppc-opc.c
@@ -4268,6 +4268,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{ "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } },
{ "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } },
+/* New VSX opcodes in POWER ISA 2.06 */
+/* XXX: only enough opcodes for FreeBSD kernel, remove and replace with real info */
+{ "stxvw4x", X(31, 908), X_MASK, PPCVEC, { FRS, RA0, RB } },
+{ "lxvw4x", X(31, 780), X_MASK, PPCVEC, { FRT, RA0, RB } },
+
/* New load/store left/right index vector instructions that are in the Cell only. */
{ "lvlx", X(31, 519), X_MASK, CELL, { VD, RA0, RB } },
{ "lvlxl", X(31, 775), X_MASK, CELL, { VD, RA0, RB } },
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