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| author | obrien <obrien@FreeBSD.org> | 2003-03-02 19:10:30 +0000 |
|---|---|---|
| committer | obrien <obrien@FreeBSD.org> | 2003-03-02 19:10:30 +0000 |
| commit | e084c5b388862d943d7dd25c9502ade33f8b9d1a (patch) | |
| tree | 93d316a7580417af5861fb407bbd1b36a557a7cd /contrib/binutils | |
| parent | ecae3c4f95ba7c7ee8f027517f4bda25518ed2cf (diff) | |
| download | FreeBSD-src-e084c5b388862d943d7dd25c9502ade33f8b9d1a.zip FreeBSD-src-e084c5b388862d943d7dd25c9502ade33f8b9d1a.tar.gz | |
Things that never should have been imported.
Diffstat (limited to 'contrib/binutils')
36 files changed, 0 insertions, 12979 deletions
diff --git a/contrib/binutils/include/coff/tic30.h b/contrib/binutils/include/coff/tic30.h deleted file mode 100644 index 30bf9dc..0000000 --- a/contrib/binutils/include/coff/tic30.h +++ /dev/null @@ -1,50 +0,0 @@ -/* coff information for Texas Instruments TMS320C3X - - Copyright 2001 Free Software Foundation, Inc. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#define L_LNNO_SIZE 4 -#include "coff/external.h" - -#define TIC30MAGIC 0xC000 - -#define TIC30BADMAG(x) (((x).f_magic != TIC30MAGIC)) - -/********************** RELOCATION DIRECTIVES **********************/ - -/* The external reloc has an offset field, because some of the reloc - types on the z8k don't have room in the instruction for the entire - offset - eg with segments */ - -struct external_reloc -{ - char r_vaddr[4]; - char r_symndx[4]; - char r_offset[4]; - char r_type[2]; - char r_stuff[2]; -}; - -#define RELOC struct external_reloc -#define RELSZ 16 - -/* TMS320C30 relocation types. */ - -#define R_TIC30_ABS16 0x100 /* 16 bit absolute. */ -#define R_TIC30_ABS24 0x101 /* 24 bit absolute. */ -#define R_TIC30_ABS32 0x102 /* 32 bit absolute. */ -#define R_TIC30_LDP 0x103 /* LDP bits 23-16 to 7-0. */ -#define R_TIC30_PC16 0x104 /* 16 bit pc relative. */ diff --git a/contrib/binutils/include/opcode/arc.h b/contrib/binutils/include/opcode/arc.h deleted file mode 100644 index b137840..0000000 --- a/contrib/binutils/include/opcode/arc.h +++ /dev/null @@ -1,321 +0,0 @@ -/* Opcode table for the ARC. - Copyright 1994, 1995, 1997, 2001 Free Software Foundation, Inc. - Contributed by Doug Evans (dje@cygnus.com). - - This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and - the GNU Binutils. - - GAS/GDB is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - GAS/GDB is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with GAS or GDB; see the file COPYING. If not, write to - the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - - -/* List of the various cpu types. - The tables currently use bit masks to say whether the instruction or - whatever is supported by a particular cpu. This lets us have one entry - apply to several cpus. - - The `base' cpu must be 0. The cpu type is treated independently of - endianness. The complete `mach' number includes endianness. - These values are internal to opcodes/bfd/binutils/gas. */ -#define ARC_MACH_5 0 -#define ARC_MACH_6 1 -#define ARC_MACH_7 2 -#define ARC_MACH_8 4 - -/* Additional cpu values can be inserted here and ARC_MACH_BIG moved down. */ -#define ARC_MACH_BIG 16 - -/* Mask of number of bits necessary to record cpu type. */ -#define ARC_MACH_CPU_MASK (ARC_MACH_BIG - 1) - -/* Mask of number of bits necessary to record cpu type + endianness. */ -#define ARC_MACH_MASK ((ARC_MACH_BIG << 1) - 1) - -/* Type to denote an ARC instruction (at least a 32 bit unsigned int). */ - -typedef unsigned int arc_insn; - -struct arc_opcode { - char *syntax; /* syntax of insn */ - unsigned long mask, value; /* recognize insn if (op&mask) == value */ - int flags; /* various flag bits */ - -/* Values for `flags'. */ - -/* Return CPU number, given flag bits. */ -#define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) - -/* Return MACH number, given flag bits. */ -#define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK) - -/* First opcode flag bit available after machine mask. */ -#define ARC_OPCODE_FLAG_START (ARC_MACH_MASK + 1) - -/* This insn is a conditional branch. */ -#define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START) -#define SYNTAX_3OP (ARC_OPCODE_COND_BRANCH << 1) -#define SYNTAX_LENGTH (SYNTAX_3OP ) -#define SYNTAX_2OP (SYNTAX_3OP << 1) -#define OP1_MUST_BE_IMM (SYNTAX_2OP << 1) -#define OP1_IMM_IMPLIED (OP1_MUST_BE_IMM << 1) -#define SYNTAX_VALID (OP1_IMM_IMPLIED << 1) - -#define I(x) (((x) & 31) << 27) -#define A(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGA) -#define B(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGB) -#define C(x) (((x) & ARC_MASK_REG) << ARC_SHIFT_REGC) -#define R(x,b,m) (((x) & (m)) << (b)) /* value X, mask M, at bit B */ - -/* These values are used to optimize assembly and disassembly. Each insn - is on a list of related insns (same first letter for assembly, same - insn code for disassembly). */ - - struct arc_opcode *next_asm; /* Next instr to try during assembly. */ - struct arc_opcode *next_dis; /* Next instr to try during disassembly. */ - -/* Macros to create the hash values for the lists. */ -#define ARC_HASH_OPCODE(string) \ - ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26) -#define ARC_HASH_ICODE(insn) \ - ((unsigned int) (insn) >> 27) - - /* Macros to access `next_asm', `next_dis' so users needn't care about the - underlying mechanism. */ -#define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm) -#define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis) -}; - -/* this is an "insert at front" linked list per Metaware spec - that new definitions override older ones. */ -struct arc_opcode *arc_ext_opcodes; - -struct arc_operand_value { - char *name; /* eg: "eq" */ - short value; /* eg: 1 */ - unsigned char type; /* index into `arc_operands' */ - unsigned char flags; /* various flag bits */ - -/* Values for `flags'. */ - -/* Return CPU number, given flag bits. */ -#define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) -/* Return MACH number, given flag bits. */ -#define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK) -}; - -struct arc_ext_operand_value { - struct arc_ext_operand_value *next; - struct arc_operand_value operand; -} *arc_ext_operands; - -struct arc_operand { -/* One of the insn format chars. */ - unsigned char fmt; - -/* The number of bits in the operand (may be unused for a modifier). */ - unsigned char bits; - -/* How far the operand is left shifted in the instruction, or - the modifier's flag bit (may be unused for a modifier. */ - unsigned char shift; - -/* Various flag bits. */ - int flags; - -/* Values for `flags'. */ - -/* This operand is a suffix to the opcode. */ -#define ARC_OPERAND_SUFFIX 1 - -/* This operand is a relative branch displacement. The disassembler - prints these symbolically if possible. */ -#define ARC_OPERAND_RELATIVE_BRANCH 2 - -/* This operand is an absolute branch address. The disassembler - prints these symbolically if possible. */ -#define ARC_OPERAND_ABSOLUTE_BRANCH 4 - -/* This operand is an address. The disassembler - prints these symbolically if possible. */ -#define ARC_OPERAND_ADDRESS 8 - -/* This operand is a long immediate value. */ -#define ARC_OPERAND_LIMM 0x10 - -/* This operand takes signed values. */ -#define ARC_OPERAND_SIGNED 0x20 - -/* This operand takes signed values, but also accepts a full positive - range of values. That is, if bits is 16, it takes any value from - -0x8000 to 0xffff. */ -#define ARC_OPERAND_SIGNOPT 0x40 - -/* This operand should be regarded as a negative number for the - purposes of overflow checking (i.e., the normal most negative - number is disallowed and one more than the normal most positive - number is allowed). This flag will only be set for a signed - operand. */ -#define ARC_OPERAND_NEGATIVE 0x80 - -/* This operand doesn't really exist. The program uses these operands - in special ways. */ -#define ARC_OPERAND_FAKE 0x100 - -/* separate flags operand for j and jl instructions */ -#define ARC_OPERAND_JUMPFLAGS 0x200 - -/* allow warnings and errors to be issued after call to insert_xxxxxx */ -#define ARC_OPERAND_WARN 0x400 -#define ARC_OPERAND_ERROR 0x800 - -/* this is a load operand */ -#define ARC_OPERAND_LOAD 0x8000 - -/* this is a store operand */ -#define ARC_OPERAND_STORE 0x10000 - -/* Modifier values. */ -/* A dot is required before a suffix. Eg: .le */ -#define ARC_MOD_DOT 0x1000 - -/* A normal register is allowed (not used, but here for completeness). */ -#define ARC_MOD_REG 0x2000 - -/* An auxiliary register name is expected. */ -#define ARC_MOD_AUXREG 0x4000 - -/* Sum of all ARC_MOD_XXX bits. */ -#define ARC_MOD_BITS 0x7000 - -/* Non-zero if the operand type is really a modifier. */ -#define ARC_MOD_P(X) ((X) & ARC_MOD_BITS) - -/* enforce read/write only register restrictions */ -#define ARC_REGISTER_READONLY 0x01 -#define ARC_REGISTER_WRITEONLY 0x02 -#define ARC_REGISTER_NOSHORT_CUT 0x04 - -/* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. - - If it is NULL, execute - i |= (p & ((1 << o->bits) - 1)) << o->shift; - (I is the instruction which we are filling in, O is a pointer to - this structure, and OP is the opcode value; this assumes twos - complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged. - - REG is non-NULL when inserting a register value. */ - - arc_insn (*insert) PARAMS ((arc_insn insn, - const struct arc_operand *operand, int mods, - const struct arc_operand_value *reg, long value, - const char **errmsg)); - -/* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. - - If it is NULL, compute - op = ((i) >> o->shift) & ((1 << o->bits) - 1); - if ((o->flags & ARC_OPERAND_SIGNED) != 0 - && (op & (1 << (o->bits - 1))) != 0) - op -= 1 << o->bits; - (I is the instruction, O is a pointer to this structure, and OP - is the result; this assumes twos complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. - - INSN is a pointer to an array of two `arc_insn's. The first element is - the insn, the second is the limm if present. - - Operands that have a printable form like registers and suffixes have - their struct arc_operand_value pointer stored in OPVAL. */ - - long (*extract) PARAMS ((arc_insn *insn, - const struct arc_operand *operand, - int mods, const struct arc_operand_value **opval, - int *invalid)); -}; - -/* Bits that say what version of cpu we have. These should be passed to - arc_init_opcode_tables. At present, all there is is the cpu type. */ - -/* CPU number, given value passed to `arc_init_opcode_tables'. */ -#define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK) -/* MACH number, given value passed to `arc_init_opcode_tables'. */ -#define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK) - -/* Special register values: */ -#define ARC_REG_SHIMM_UPDATE 61 -#define ARC_REG_SHIMM 63 -#define ARC_REG_LIMM 62 - -/* Non-zero if REG is a constant marker. */ -#define ARC_REG_CONSTANT_P(REG) ((REG) >= 61) - -/* Positions and masks of various fields: */ -#define ARC_SHIFT_REGA 21 -#define ARC_SHIFT_REGB 15 -#define ARC_SHIFT_REGC 9 -#define ARC_MASK_REG 63 - -/* Delay slot types. */ -#define ARC_DELAY_NONE 0 /* no delay slot */ -#define ARC_DELAY_NORMAL 1 /* delay slot in both cases */ -#define ARC_DELAY_JUMP 2 /* delay slot only if branch taken */ - -/* Non-zero if X will fit in a signed 9 bit field. */ -#define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255) - -extern const struct arc_operand arc_operands[]; -extern const int arc_operand_count; -extern struct arc_opcode arc_opcodes[]; -extern const int arc_opcodes_count; -extern const struct arc_operand_value arc_suffixes[]; -extern const int arc_suffixes_count; -extern const struct arc_operand_value arc_reg_names[]; -extern const int arc_reg_names_count; -extern unsigned char arc_operand_map[]; - -/* Utility fns in arc-opc.c. */ -int arc_get_opcode_mach PARAMS ((int, int)); - -/* `arc_opcode_init_tables' must be called before `arc_xxx_supported'. */ -void arc_opcode_init_tables PARAMS ((int)); -void arc_opcode_init_insert PARAMS ((void)); -void arc_opcode_init_extract PARAMS ((void)); -const struct arc_opcode *arc_opcode_lookup_asm PARAMS ((const char *)); -const struct arc_opcode *arc_opcode_lookup_dis PARAMS ((unsigned int)); -int arc_opcode_limm_p PARAMS ((long *)); -const struct arc_operand_value *arc_opcode_lookup_suffix - PARAMS ((const struct arc_operand *type, int value)); -int arc_opcode_supported PARAMS ((const struct arc_opcode *)); -int arc_opval_supported PARAMS ((const struct arc_operand_value *)); -int arc_limm_fixup_adjust PARAMS ((arc_insn)); -int arc_insn_is_j PARAMS ((arc_insn)); -int arc_insn_not_jl PARAMS ((arc_insn)); -int arc_operand_type PARAMS ((int)); -struct arc_operand_value *get_ext_suffix PARAMS ((char *)); -int arc_get_noshortcut_flag PARAMS ((void)); diff --git a/contrib/binutils/include/opcode/convex.h b/contrib/binutils/include/opcode/convex.h deleted file mode 100644 index ccf5568..0000000 --- a/contrib/binutils/include/opcode/convex.h +++ /dev/null @@ -1,1707 +0,0 @@ -/* Information for instruction disassembly on the Convex. - Copyright 1989, 1993, 2002 Free Software Foundation, Inc. - -This file is part of GDB. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#define xxx 0 -#define rrr 1 -#define rr 2 -#define rxr 3 -#define r 4 -#define nops 5 -#define nr 6 -#define pcrel 7 -#define lr 8 -#define rxl 9 -#define rlr 10 -#define rrl 11 -#define iml 12 -#define imr 13 -#define a1r 14 -#define a1l 15 -#define a2r 16 -#define a2l 17 -#define a3 18 -#define a4 19 -#define a5 20 -#define V 1 -#define S 2 -#define VM 3 -#define A 4 -#define VL 5 -#define VS 6 -#define VLS 7 -#define PSW 8 -/* Prevent an error during "make depend". */ -#if !defined (PC) -#define PC 9 -#endif -#define ITR 10 -#define VV 11 -#define ITSR 12 -#define TOC 13 -#define CIR 14 -#define TTR 15 -#define VMU 16 -#define VML 17 -#define ICR 18 -#define TCPU 19 -#define CPUID 20 -#define TID 21 - -const char *op[] = { - "", - "v0\0v1\0v2\0v3\0v4\0v5\0v6\0v7", - "s0\0s1\0s2\0s3\0s4\0s5\0s6\0s7", - "vm", - "sp\0a1\0a2\0a3\0a4\0a5\0ap\0fp", - "vl", - "vs", - "vls", - "psw", - "pc", - "itr", - "vv", - "itsr", - "toc", - "cir", - "ttr", - "vmu", - "vml", - "icr", - "tcpu", - "cpuid", - "tid", -}; - -const struct formstr format0[] = { - {0,0,rrr,V,S,S}, /* mov */ - {0,0,rrr,S,S,V}, /* mov */ - {1,1,rrr,V,V,V}, /* merg.t */ - {2,1,rrr,V,V,V}, /* mask.t */ - {1,2,rrr,V,S,V}, /* merg.f */ - {2,2,rrr,V,S,V}, /* mask.f */ - {1,1,rrr,V,S,V}, /* merg.t */ - {2,1,rrr,V,S,V}, /* mask.t */ - {3,3,rrr,V,V,V}, /* mul.s */ - {3,4,rrr,V,V,V}, /* mul.d */ - {4,3,rrr,V,V,V}, /* div.s */ - {4,4,rrr,V,V,V}, /* div.d */ - {3,3,rrr,V,S,V}, /* mul.s */ - {3,4,rrr,V,S,V}, /* mul.d */ - {4,3,rrr,V,S,V}, /* div.s */ - {4,4,rrr,V,S,V}, /* div.d */ - {5,0,rrr,V,V,V}, /* and */ - {6,0,rrr,V,V,V}, /* or */ - {7,0,rrr,V,V,V}, /* xor */ - {8,0,rrr,V,V,V}, /* shf */ - {5,0,rrr,V,S,V}, /* and */ - {6,0,rrr,V,S,V}, /* or */ - {7,0,rrr,V,S,V}, /* xor */ - {8,0,rrr,V,S,V}, /* shf */ - {9,3,rrr,V,V,V}, /* add.s */ - {9,4,rrr,V,V,V}, /* add.d */ - {10,3,rrr,V,V,V}, /* sub.s */ - {10,4,rrr,V,V,V}, /* sub.d */ - {9,3,rrr,V,S,V}, /* add.s */ - {9,4,rrr,V,S,V}, /* add.d */ - {10,3,rrr,V,S,V}, /* sub.s */ - {10,4,rrr,V,S,V}, /* sub.d */ - {9,5,rrr,V,V,V}, /* add.b */ - {9,6,rrr,V,V,V}, /* add.h */ - {9,7,rrr,V,V,V}, /* add.w */ - {9,8,rrr,V,V,V}, /* add.l */ - {9,5,rrr,V,S,V}, /* add.b */ - {9,6,rrr,V,S,V}, /* add.h */ - {9,7,rrr,V,S,V}, /* add.w */ - {9,8,rrr,V,S,V}, /* add.l */ - {10,5,rrr,V,V,V}, /* sub.b */ - {10,6,rrr,V,V,V}, /* sub.h */ - {10,7,rrr,V,V,V}, /* sub.w */ - {10,8,rrr,V,V,V}, /* sub.l */ - {10,5,rrr,V,S,V}, /* sub.b */ - {10,6,rrr,V,S,V}, /* sub.h */ - {10,7,rrr,V,S,V}, /* sub.w */ - {10,8,rrr,V,S,V}, /* sub.l */ - {3,5,rrr,V,V,V}, /* mul.b */ - {3,6,rrr,V,V,V}, /* mul.h */ - {3,7,rrr,V,V,V}, /* mul.w */ - {3,8,rrr,V,V,V}, /* mul.l */ - {3,5,rrr,V,S,V}, /* mul.b */ - {3,6,rrr,V,S,V}, /* mul.h */ - {3,7,rrr,V,S,V}, /* mul.w */ - {3,8,rrr,V,S,V}, /* mul.l */ - {4,5,rrr,V,V,V}, /* div.b */ - {4,6,rrr,V,V,V}, /* div.h */ - {4,7,rrr,V,V,V}, /* div.w */ - {4,8,rrr,V,V,V}, /* div.l */ - {4,5,rrr,V,S,V}, /* div.b */ - {4,6,rrr,V,S,V}, /* div.h */ - {4,7,rrr,V,S,V}, /* div.w */ - {4,8,rrr,V,S,V}, /* div.l */ -}; - -const struct formstr format1[] = { - {11,0,xxx,0,0,0}, /* exit */ - {12,0,a3,0,0,0}, /* jmp */ - {13,2,a3,0,0,0}, /* jmpi.f */ - {13,1,a3,0,0,0}, /* jmpi.t */ - {14,2,a3,0,0,0}, /* jmpa.f */ - {14,1,a3,0,0,0}, /* jmpa.t */ - {15,2,a3,0,0,0}, /* jmps.f */ - {15,1,a3,0,0,0}, /* jmps.t */ - {16,0,a3,0,0,0}, /* tac */ - {17,0,a1r,A,0,0}, /* ldea */ - {18,8,a1l,VLS,0,0}, /* ld.l */ - {18,9,a1l,VM,0,0}, /* ld.x */ - {19,0,a3,0,0,0}, /* tas */ - {20,0,a3,0,0,0}, /* pshea */ - {21,8,a2l,VLS,0,0}, /* st.l */ - {21,9,a2l,VM,0,0}, /* st.x */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {22,0,a3,0,0,0}, /* call */ - {23,0,a3,0,0,0}, /* calls */ - {24,0,a3,0,0,0}, /* callq */ - {25,0,a1r,A,0,0}, /* pfork */ - {26,5,a2r,S,0,0}, /* ste.b */ - {26,6,a2r,S,0,0}, /* ste.h */ - {26,7,a2r,S,0,0}, /* ste.w */ - {26,8,a2r,S,0,0}, /* ste.l */ - {18,5,a1r,A,0,0}, /* ld.b */ - {18,6,a1r,A,0,0}, /* ld.h */ - {18,7,a1r,A,0,0}, /* ld.w */ - {27,7,a1r,A,0,0}, /* incr.w */ - {21,5,a2r,A,0,0}, /* st.b */ - {21,6,a2r,A,0,0}, /* st.h */ - {21,7,a2r,A,0,0}, /* st.w */ - {27,8,a1r,S,0,0}, /* incr.l */ - {18,5,a1r,S,0,0}, /* ld.b */ - {18,6,a1r,S,0,0}, /* ld.h */ - {18,7,a1r,S,0,0}, /* ld.w */ - {18,8,a1r,S,0,0}, /* ld.l */ - {21,5,a2r,S,0,0}, /* st.b */ - {21,6,a2r,S,0,0}, /* st.h */ - {21,7,a2r,S,0,0}, /* st.w */ - {21,8,a2r,S,0,0}, /* st.l */ - {18,5,a1r,V,0,0}, /* ld.b */ - {18,6,a1r,V,0,0}, /* ld.h */ - {18,7,a1r,V,0,0}, /* ld.w */ - {18,8,a1r,V,0,0}, /* ld.l */ - {21,5,a2r,V,0,0}, /* st.b */ - {21,6,a2r,V,0,0}, /* st.h */ - {21,7,a2r,V,0,0}, /* st.w */ - {21,8,a2r,V,0,0}, /* st.l */ -}; - -const struct formstr format2[] = { - {28,5,rr,A,A,0}, /* cvtw.b */ - {28,6,rr,A,A,0}, /* cvtw.h */ - {29,7,rr,A,A,0}, /* cvtb.w */ - {30,7,rr,A,A,0}, /* cvth.w */ - {28,5,rr,S,S,0}, /* cvtw.b */ - {28,6,rr,S,S,0}, /* cvtw.h */ - {29,7,rr,S,S,0}, /* cvtb.w */ - {30,7,rr,S,S,0}, /* cvth.w */ - {28,3,rr,S,S,0}, /* cvtw.s */ - {31,7,rr,S,S,0}, /* cvts.w */ - {32,3,rr,S,S,0}, /* cvtd.s */ - {31,4,rr,S,S,0}, /* cvts.d */ - {31,8,rr,S,S,0}, /* cvts.l */ - {32,8,rr,S,S,0}, /* cvtd.l */ - {33,3,rr,S,S,0}, /* cvtl.s */ - {33,4,rr,S,S,0}, /* cvtl.d */ - {34,0,rr,A,A,0}, /* ldpa */ - {8,0,nr,A,0,0}, /* shf */ - {18,6,nr,A,0,0}, /* ld.h */ - {18,7,nr,A,0,0}, /* ld.w */ - {33,7,rr,S,S,0}, /* cvtl.w */ - {28,8,rr,S,S,0}, /* cvtw.l */ - {35,1,rr,S,S,0}, /* plc.t */ - {36,0,rr,S,S,0}, /* tzc */ - {37,6,rr,A,A,0}, /* eq.h */ - {37,7,rr,A,A,0}, /* eq.w */ - {37,6,nr,A,0,0}, /* eq.h */ - {37,7,nr,A,0,0}, /* eq.w */ - {37,5,rr,S,S,0}, /* eq.b */ - {37,6,rr,S,S,0}, /* eq.h */ - {37,7,rr,S,S,0}, /* eq.w */ - {37,8,rr,S,S,0}, /* eq.l */ - {38,6,rr,A,A,0}, /* leu.h */ - {38,7,rr,A,A,0}, /* leu.w */ - {38,6,nr,A,0,0}, /* leu.h */ - {38,7,nr,A,0,0}, /* leu.w */ - {38,5,rr,S,S,0}, /* leu.b */ - {38,6,rr,S,S,0}, /* leu.h */ - {38,7,rr,S,S,0}, /* leu.w */ - {38,8,rr,S,S,0}, /* leu.l */ - {39,6,rr,A,A,0}, /* ltu.h */ - {39,7,rr,A,A,0}, /* ltu.w */ - {39,6,nr,A,0,0}, /* ltu.h */ - {39,7,nr,A,0,0}, /* ltu.w */ - {39,5,rr,S,S,0}, /* ltu.b */ - {39,6,rr,S,S,0}, /* ltu.h */ - {39,7,rr,S,S,0}, /* ltu.w */ - {39,8,rr,S,S,0}, /* ltu.l */ - {40,6,rr,A,A,0}, /* le.h */ - {40,7,rr,A,A,0}, /* le.w */ - {40,6,nr,A,0,0}, /* le.h */ - {40,7,nr,A,0,0}, /* le.w */ - {40,5,rr,S,S,0}, /* le.b */ - {40,6,rr,S,S,0}, /* le.h */ - {40,7,rr,S,S,0}, /* le.w */ - {40,8,rr,S,S,0}, /* le.l */ - {41,6,rr,A,A,0}, /* lt.h */ - {41,7,rr,A,A,0}, /* lt.w */ - {41,6,nr,A,0,0}, /* lt.h */ - {41,7,nr,A,0,0}, /* lt.w */ - {41,5,rr,S,S,0}, /* lt.b */ - {41,6,rr,S,S,0}, /* lt.h */ - {41,7,rr,S,S,0}, /* lt.w */ - {41,8,rr,S,S,0}, /* lt.l */ - {9,7,rr,S,A,0}, /* add.w */ - {8,0,rr,A,A,0}, /* shf */ - {0,0,rr,A,A,0}, /* mov */ - {0,0,rr,S,A,0}, /* mov */ - {0,7,rr,S,S,0}, /* mov.w */ - {8,0,rr,S,S,0}, /* shf */ - {0,0,rr,S,S,0}, /* mov */ - {0,0,rr,A,S,0}, /* mov */ - {5,0,rr,A,A,0}, /* and */ - {6,0,rr,A,A,0}, /* or */ - {7,0,rr,A,A,0}, /* xor */ - {42,0,rr,A,A,0}, /* not */ - {5,0,rr,S,S,0}, /* and */ - {6,0,rr,S,S,0}, /* or */ - {7,0,rr,S,S,0}, /* xor */ - {42,0,rr,S,S,0}, /* not */ - {40,3,rr,S,S,0}, /* le.s */ - {40,4,rr,S,S,0}, /* le.d */ - {41,3,rr,S,S,0}, /* lt.s */ - {41,4,rr,S,S,0}, /* lt.d */ - {9,3,rr,S,S,0}, /* add.s */ - {9,4,rr,S,S,0}, /* add.d */ - {10,3,rr,S,S,0}, /* sub.s */ - {10,4,rr,S,S,0}, /* sub.d */ - {37,3,rr,S,S,0}, /* eq.s */ - {37,4,rr,S,S,0}, /* eq.d */ - {43,6,rr,A,A,0}, /* neg.h */ - {43,7,rr,A,A,0}, /* neg.w */ - {3,3,rr,S,S,0}, /* mul.s */ - {3,4,rr,S,S,0}, /* mul.d */ - {4,3,rr,S,S,0}, /* div.s */ - {4,4,rr,S,S,0}, /* div.d */ - {9,6,rr,A,A,0}, /* add.h */ - {9,7,rr,A,A,0}, /* add.w */ - {9,6,nr,A,0,0}, /* add.h */ - {9,7,nr,A,0,0}, /* add.w */ - {9,5,rr,S,S,0}, /* add.b */ - {9,6,rr,S,S,0}, /* add.h */ - {9,7,rr,S,S,0}, /* add.w */ - {9,8,rr,S,S,0}, /* add.l */ - {10,6,rr,A,A,0}, /* sub.h */ - {10,7,rr,A,A,0}, /* sub.w */ - {10,6,nr,A,0,0}, /* sub.h */ - {10,7,nr,A,0,0}, /* sub.w */ - {10,5,rr,S,S,0}, /* sub.b */ - {10,6,rr,S,S,0}, /* sub.h */ - {10,7,rr,S,S,0}, /* sub.w */ - {10,8,rr,S,S,0}, /* sub.l */ - {3,6,rr,A,A,0}, /* mul.h */ - {3,7,rr,A,A,0}, /* mul.w */ - {3,6,nr,A,0,0}, /* mul.h */ - {3,7,nr,A,0,0}, /* mul.w */ - {3,5,rr,S,S,0}, /* mul.b */ - {3,6,rr,S,S,0}, /* mul.h */ - {3,7,rr,S,S,0}, /* mul.w */ - {3,8,rr,S,S,0}, /* mul.l */ - {4,6,rr,A,A,0}, /* div.h */ - {4,7,rr,A,A,0}, /* div.w */ - {4,6,nr,A,0,0}, /* div.h */ - {4,7,nr,A,0,0}, /* div.w */ - {4,5,rr,S,S,0}, /* div.b */ - {4,6,rr,S,S,0}, /* div.h */ - {4,7,rr,S,S,0}, /* div.w */ - {4,8,rr,S,S,0}, /* div.l */ -}; - -const struct formstr format3[] = { - {32,3,rr,V,V,0}, /* cvtd.s */ - {31,4,rr,V,V,0}, /* cvts.d */ - {33,4,rr,V,V,0}, /* cvtl.d */ - {32,8,rr,V,V,0}, /* cvtd.l */ - {0,0,rrl,S,S,VM}, /* mov */ - {0,0,rlr,S,VM,S}, /* mov */ - {0,0,0,0,0,0}, - {44,0,rr,S,S,0}, /* lop */ - {36,0,rr,V,V,0}, /* tzc */ - {44,0,rr,V,V,0}, /* lop */ - {0,0,0,0,0,0}, - {42,0,rr,V,V,0}, /* not */ - {8,0,rr,S,V,0}, /* shf */ - {35,1,rr,V,V,0}, /* plc.t */ - {45,2,rr,V,V,0}, /* cprs.f */ - {45,1,rr,V,V,0}, /* cprs.t */ - {37,3,rr,V,V,0}, /* eq.s */ - {37,4,rr,V,V,0}, /* eq.d */ - {43,3,rr,V,V,0}, /* neg.s */ - {43,4,rr,V,V,0}, /* neg.d */ - {37,3,rr,S,V,0}, /* eq.s */ - {37,4,rr,S,V,0}, /* eq.d */ - {43,3,rr,S,S,0}, /* neg.s */ - {43,4,rr,S,S,0}, /* neg.d */ - {40,3,rr,V,V,0}, /* le.s */ - {40,4,rr,V,V,0}, /* le.d */ - {41,3,rr,V,V,0}, /* lt.s */ - {41,4,rr,V,V,0}, /* lt.d */ - {40,3,rr,S,V,0}, /* le.s */ - {40,4,rr,S,V,0}, /* le.d */ - {41,3,rr,S,V,0}, /* lt.s */ - {41,4,rr,S,V,0}, /* lt.d */ - {37,5,rr,V,V,0}, /* eq.b */ - {37,6,rr,V,V,0}, /* eq.h */ - {37,7,rr,V,V,0}, /* eq.w */ - {37,8,rr,V,V,0}, /* eq.l */ - {37,5,rr,S,V,0}, /* eq.b */ - {37,6,rr,S,V,0}, /* eq.h */ - {37,7,rr,S,V,0}, /* eq.w */ - {37,8,rr,S,V,0}, /* eq.l */ - {40,5,rr,V,V,0}, /* le.b */ - {40,6,rr,V,V,0}, /* le.h */ - {40,7,rr,V,V,0}, /* le.w */ - {40,8,rr,V,V,0}, /* le.l */ - {40,5,rr,S,V,0}, /* le.b */ - {40,6,rr,S,V,0}, /* le.h */ - {40,7,rr,S,V,0}, /* le.w */ - {40,8,rr,S,V,0}, /* le.l */ - {41,5,rr,V,V,0}, /* lt.b */ - {41,6,rr,V,V,0}, /* lt.h */ - {41,7,rr,V,V,0}, /* lt.w */ - {41,8,rr,V,V,0}, /* lt.l */ - {41,5,rr,S,V,0}, /* lt.b */ - {41,6,rr,S,V,0}, /* lt.h */ - {41,7,rr,S,V,0}, /* lt.w */ - {41,8,rr,S,V,0}, /* lt.l */ - {43,5,rr,V,V,0}, /* neg.b */ - {43,6,rr,V,V,0}, /* neg.h */ - {43,7,rr,V,V,0}, /* neg.w */ - {43,8,rr,V,V,0}, /* neg.l */ - {43,5,rr,S,S,0}, /* neg.b */ - {43,6,rr,S,S,0}, /* neg.h */ - {43,7,rr,S,S,0}, /* neg.w */ - {43,8,rr,S,S,0}, /* neg.l */ -}; - -const struct formstr format4[] = { - {46,0,nops,0,0,0}, /* nop */ - {47,0,pcrel,0,0,0}, /* br */ - {48,2,pcrel,0,0,0}, /* bri.f */ - {48,1,pcrel,0,0,0}, /* bri.t */ - {49,2,pcrel,0,0,0}, /* bra.f */ - {49,1,pcrel,0,0,0}, /* bra.t */ - {50,2,pcrel,0,0,0}, /* brs.f */ - {50,1,pcrel,0,0,0}, /* brs.t */ -}; - -const struct formstr format5[] = { - {51,5,rr,V,V,0}, /* ldvi.b */ - {51,6,rr,V,V,0}, /* ldvi.h */ - {51,7,rr,V,V,0}, /* ldvi.w */ - {51,8,rr,V,V,0}, /* ldvi.l */ - {28,3,rr,V,V,0}, /* cvtw.s */ - {31,7,rr,V,V,0}, /* cvts.w */ - {28,8,rr,V,V,0}, /* cvtw.l */ - {33,7,rr,V,V,0}, /* cvtl.w */ - {52,5,rxr,V,V,0}, /* stvi.b */ - {52,6,rxr,V,V,0}, /* stvi.h */ - {52,7,rxr,V,V,0}, /* stvi.w */ - {52,8,rxr,V,V,0}, /* stvi.l */ - {52,5,rxr,S,V,0}, /* stvi.b */ - {52,6,rxr,S,V,0}, /* stvi.h */ - {52,7,rxr,S,V,0}, /* stvi.w */ - {52,8,rxr,S,V,0}, /* stvi.l */ -}; - -const struct formstr format6[] = { - {53,0,r,A,0,0}, /* ldsdr */ - {54,0,r,A,0,0}, /* ldkdr */ - {55,3,r,S,0,0}, /* ln.s */ - {55,4,r,S,0,0}, /* ln.d */ - {56,0,nops,0,0,0}, /* patu */ - {57,0,r,A,0,0}, /* pate */ - {58,0,nops,0,0,0}, /* pich */ - {59,0,nops,0,0,0}, /* plch */ - {0,0,lr,PSW,A,0}, /* mov */ - {0,0,rxl,A,PSW,0}, /* mov */ - {0,0,lr,PC,A,0}, /* mov */ - {60,0,r,S,0,0}, /* idle */ - {0,0,lr,ITR,S,0}, /* mov */ - {0,0,rxl,S,ITR,0}, /* mov */ - {0,0,0,0,0,0}, - {0,0,rxl,S,ITSR,0}, /* mov */ - {61,0,nops,0,0,0}, /* rtnq */ - {62,0,nops,0,0,0}, /* cfork */ - {63,0,nops,0,0,0}, /* rtn */ - {64,0,nops,0,0,0}, /* wfork */ - {65,0,nops,0,0,0}, /* join */ - {66,0,nops,0,0,0}, /* rtnc */ - {67,3,r,S,0,0}, /* exp.s */ - {67,4,r,S,0,0}, /* exp.d */ - {68,3,r,S,0,0}, /* sin.s */ - {68,4,r,S,0,0}, /* sin.d */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {69,3,r,S,0,0}, /* cos.s */ - {69,4,r,S,0,0}, /* cos.d */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {70,7,r,A,0,0}, /* psh.w */ - {0,0,0,0,0,0}, - {71,7,r,A,0,0}, /* pop.w */ - {0,0,0,0,0,0}, - {70,7,r,S,0,0}, /* psh.w */ - {70,8,r,S,0,0}, /* psh.l */ - {71,7,r,S,0,0}, /* pop.w */ - {71,8,r,S,0,0}, /* pop.l */ - {72,0,nops,0,0,0}, /* eni */ - {73,0,nops,0,0,0}, /* dsi */ - {74,0,nops,0,0,0}, /* bkpt */ - {75,0,nops,0,0,0}, /* msync */ - {76,0,r,S,0,0}, /* mski */ - {77,0,r,S,0,0}, /* xmti */ - {0,0,rxl,S,VV,0}, /* mov */ - {78,0,nops,0,0,0}, /* tstvv */ - {0,0,lr,VS,A,0}, /* mov */ - {0,0,rxl,A,VS,0}, /* mov */ - {0,0,lr,VL,A,0}, /* mov */ - {0,0,rxl,A,VL,0}, /* mov */ - {0,7,lr,VS,S,0}, /* mov.w */ - {0,7,rxl,S,VS,0}, /* mov.w */ - {0,7,lr,VL,S,0}, /* mov.w */ - {0,7,rxl,S,VL,0}, /* mov.w */ - {79,0,r,A,0,0}, /* diag */ - {80,0,nops,0,0,0}, /* pbkpt */ - {81,3,r,S,0,0}, /* sqrt.s */ - {81,4,r,S,0,0}, /* sqrt.d */ - {82,0,nops,0,0,0}, /* casr */ - {0,0,0,0,0,0}, - {83,3,r,S,0,0}, /* atan.s */ - {83,4,r,S,0,0}, /* atan.d */ -}; - -const struct formstr format7[] = { - {84,5,r,V,0,0}, /* sum.b */ - {84,6,r,V,0,0}, /* sum.h */ - {84,7,r,V,0,0}, /* sum.w */ - {84,8,r,V,0,0}, /* sum.l */ - {85,0,r,V,0,0}, /* all */ - {86,0,r,V,0,0}, /* any */ - {87,0,r,V,0,0}, /* parity */ - {0,0,0,0,0,0}, - {88,5,r,V,0,0}, /* max.b */ - {88,6,r,V,0,0}, /* max.h */ - {88,7,r,V,0,0}, /* max.w */ - {88,8,r,V,0,0}, /* max.l */ - {89,5,r,V,0,0}, /* min.b */ - {89,6,r,V,0,0}, /* min.h */ - {89,7,r,V,0,0}, /* min.w */ - {89,8,r,V,0,0}, /* min.l */ - {84,3,r,V,0,0}, /* sum.s */ - {84,4,r,V,0,0}, /* sum.d */ - {90,3,r,V,0,0}, /* prod.s */ - {90,4,r,V,0,0}, /* prod.d */ - {88,3,r,V,0,0}, /* max.s */ - {88,4,r,V,0,0}, /* max.d */ - {89,3,r,V,0,0}, /* min.s */ - {89,4,r,V,0,0}, /* min.d */ - {90,5,r,V,0,0}, /* prod.b */ - {90,6,r,V,0,0}, /* prod.h */ - {90,7,r,V,0,0}, /* prod.w */ - {90,8,r,V,0,0}, /* prod.l */ - {35,2,lr,VM,S,0}, /* plc.f */ - {35,1,lr,VM,S,0}, /* plc.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr formatx[] = { - {0,0,0,0,0,0}, -}; - -const struct formstr format1a[] = { - {91,0,imr,A,0,0}, /* halt */ - {92,0,a4,0,0,0}, /* sysc */ - {18,6,imr,A,0,0}, /* ld.h */ - {18,7,imr,A,0,0}, /* ld.w */ - {5,0,imr,A,0,0}, /* and */ - {6,0,imr,A,0,0}, /* or */ - {7,0,imr,A,0,0}, /* xor */ - {8,0,imr,A,0,0}, /* shf */ - {9,6,imr,A,0,0}, /* add.h */ - {9,7,imr,A,0,0}, /* add.w */ - {10,6,imr,A,0,0}, /* sub.h */ - {10,7,imr,A,0,0}, /* sub.w */ - {3,6,imr,A,0,0}, /* mul.h */ - {3,7,imr,A,0,0}, /* mul.w */ - {4,6,imr,A,0,0}, /* div.h */ - {4,7,imr,A,0,0}, /* div.w */ - {18,7,iml,VL,0,0}, /* ld.w */ - {18,7,iml,VS,0,0}, /* ld.w */ - {0,0,0,0,0,0}, - {8,7,imr,S,0,0}, /* shf.w */ - {93,0,a5,0,0,0}, /* trap */ - {0,0,0,0,0,0}, - {37,6,imr,A,0,0}, /* eq.h */ - {37,7,imr,A,0,0}, /* eq.w */ - {38,6,imr,A,0,0}, /* leu.h */ - {38,7,imr,A,0,0}, /* leu.w */ - {39,6,imr,A,0,0}, /* ltu.h */ - {39,7,imr,A,0,0}, /* ltu.w */ - {40,6,imr,A,0,0}, /* le.h */ - {40,7,imr,A,0,0}, /* le.w */ - {41,6,imr,A,0,0}, /* lt.h */ - {41,7,imr,A,0,0}, /* lt.w */ -}; - -const struct formstr format1b[] = { - {18,4,imr,S,0,0}, /* ld.d */ - {18,10,imr,S,0,0}, /* ld.u */ - {18,8,imr,S,0,0}, /* ld.l */ - {18,7,imr,S,0,0}, /* ld.w */ - {5,0,imr,S,0,0}, /* and */ - {6,0,imr,S,0,0}, /* or */ - {7,0,imr,S,0,0}, /* xor */ - {8,0,imr,S,0,0}, /* shf */ - {9,6,imr,S,0,0}, /* add.h */ - {9,7,imr,S,0,0}, /* add.w */ - {10,6,imr,S,0,0}, /* sub.h */ - {10,7,imr,S,0,0}, /* sub.w */ - {3,6,imr,S,0,0}, /* mul.h */ - {3,7,imr,S,0,0}, /* mul.w */ - {4,6,imr,S,0,0}, /* div.h */ - {4,7,imr,S,0,0}, /* div.w */ - {9,3,imr,S,0,0}, /* add.s */ - {10,3,imr,S,0,0}, /* sub.s */ - {3,3,imr,S,0,0}, /* mul.s */ - {4,3,imr,S,0,0}, /* div.s */ - {40,3,imr,S,0,0}, /* le.s */ - {41,3,imr,S,0,0}, /* lt.s */ - {37,6,imr,S,0,0}, /* eq.h */ - {37,7,imr,S,0,0}, /* eq.w */ - {38,6,imr,S,0,0}, /* leu.h */ - {38,7,imr,S,0,0}, /* leu.w */ - {39,6,imr,S,0,0}, /* ltu.h */ - {39,7,imr,S,0,0}, /* ltu.w */ - {40,6,imr,S,0,0}, /* le.h */ - {40,7,imr,S,0,0}, /* le.w */ - {41,6,imr,S,0,0}, /* lt.h */ - {41,7,imr,S,0,0}, /* lt.w */ -}; - -const struct formstr e0_format0[] = { - {10,3,rrr,S,V,V}, /* sub.s */ - {10,4,rrr,S,V,V}, /* sub.d */ - {4,3,rrr,S,V,V}, /* div.s */ - {4,4,rrr,S,V,V}, /* div.d */ - {10,11,rrr,S,V,V}, /* sub.s.f */ - {10,12,rrr,S,V,V}, /* sub.d.f */ - {4,11,rrr,S,V,V}, /* div.s.f */ - {4,12,rrr,S,V,V}, /* div.d.f */ - {3,11,rrr,V,V,V}, /* mul.s.f */ - {3,12,rrr,V,V,V}, /* mul.d.f */ - {4,11,rrr,V,V,V}, /* div.s.f */ - {4,12,rrr,V,V,V}, /* div.d.f */ - {3,11,rrr,V,S,V}, /* mul.s.f */ - {3,12,rrr,V,S,V}, /* mul.d.f */ - {4,11,rrr,V,S,V}, /* div.s.f */ - {4,12,rrr,V,S,V}, /* div.d.f */ - {5,2,rrr,V,V,V}, /* and.f */ - {6,2,rrr,V,V,V}, /* or.f */ - {7,2,rrr,V,V,V}, /* xor.f */ - {8,2,rrr,V,V,V}, /* shf.f */ - {5,2,rrr,V,S,V}, /* and.f */ - {6,2,rrr,V,S,V}, /* or.f */ - {7,2,rrr,V,S,V}, /* xor.f */ - {8,2,rrr,V,S,V}, /* shf.f */ - {9,11,rrr,V,V,V}, /* add.s.f */ - {9,12,rrr,V,V,V}, /* add.d.f */ - {10,11,rrr,V,V,V}, /* sub.s.f */ - {10,12,rrr,V,V,V}, /* sub.d.f */ - {9,11,rrr,V,S,V}, /* add.s.f */ - {9,12,rrr,V,S,V}, /* add.d.f */ - {10,11,rrr,V,S,V}, /* sub.s.f */ - {10,12,rrr,V,S,V}, /* sub.d.f */ - {9,13,rrr,V,V,V}, /* add.b.f */ - {9,14,rrr,V,V,V}, /* add.h.f */ - {9,15,rrr,V,V,V}, /* add.w.f */ - {9,16,rrr,V,V,V}, /* add.l.f */ - {9,13,rrr,V,S,V}, /* add.b.f */ - {9,14,rrr,V,S,V}, /* add.h.f */ - {9,15,rrr,V,S,V}, /* add.w.f */ - {9,16,rrr,V,S,V}, /* add.l.f */ - {10,13,rrr,V,V,V}, /* sub.b.f */ - {10,14,rrr,V,V,V}, /* sub.h.f */ - {10,15,rrr,V,V,V}, /* sub.w.f */ - {10,16,rrr,V,V,V}, /* sub.l.f */ - {10,13,rrr,V,S,V}, /* sub.b.f */ - {10,14,rrr,V,S,V}, /* sub.h.f */ - {10,15,rrr,V,S,V}, /* sub.w.f */ - {10,16,rrr,V,S,V}, /* sub.l.f */ - {3,13,rrr,V,V,V}, /* mul.b.f */ - {3,14,rrr,V,V,V}, /* mul.h.f */ - {3,15,rrr,V,V,V}, /* mul.w.f */ - {3,16,rrr,V,V,V}, /* mul.l.f */ - {3,13,rrr,V,S,V}, /* mul.b.f */ - {3,14,rrr,V,S,V}, /* mul.h.f */ - {3,15,rrr,V,S,V}, /* mul.w.f */ - {3,16,rrr,V,S,V}, /* mul.l.f */ - {4,13,rrr,V,V,V}, /* div.b.f */ - {4,14,rrr,V,V,V}, /* div.h.f */ - {4,15,rrr,V,V,V}, /* div.w.f */ - {4,16,rrr,V,V,V}, /* div.l.f */ - {4,13,rrr,V,S,V}, /* div.b.f */ - {4,14,rrr,V,S,V}, /* div.h.f */ - {4,15,rrr,V,S,V}, /* div.w.f */ - {4,16,rrr,V,S,V}, /* div.l.f */ -}; - -const struct formstr e0_format1[] = { - {0,0,0,0,0,0}, - {94,0,a3,0,0,0}, /* tst */ - {95,0,a3,0,0,0}, /* lck */ - {96,0,a3,0,0,0}, /* ulk */ - {17,0,a1r,S,0,0}, /* ldea */ - {97,0,a1r,A,0,0}, /* spawn */ - {98,0,a1r,A,0,0}, /* ldcmr */ - {99,0,a2r,A,0,0}, /* stcmr */ - {100,0,a1r,A,0,0}, /* popr */ - {101,0,a2r,A,0,0}, /* pshr */ - {102,7,a1r,A,0,0}, /* rcvr.w */ - {103,7,a2r,A,0,0}, /* matm.w */ - {104,7,a2r,A,0,0}, /* sndr.w */ - {104,8,a2r,S,0,0}, /* sndr.l */ - {102,8,a1r,S,0,0}, /* rcvr.l */ - {103,8,a2r,S,0,0}, /* matm.l */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {105,7,a2r,A,0,0}, /* putr.w */ - {105,8,a2r,S,0,0}, /* putr.l */ - {106,7,a1r,A,0,0}, /* getr.w */ - {106,8,a1r,S,0,0}, /* getr.l */ - {26,13,a2r,S,0,0}, /* ste.b.f */ - {26,14,a2r,S,0,0}, /* ste.h.f */ - {26,15,a2r,S,0,0}, /* ste.w.f */ - {26,16,a2r,S,0,0}, /* ste.l.f */ - {107,7,a2r,A,0,0}, /* matr.w */ - {108,7,a2r,A,0,0}, /* mat.w */ - {109,7,a1r,A,0,0}, /* get.w */ - {110,7,a1r,A,0,0}, /* rcv.w */ - {0,0,0,0,0,0}, - {111,7,a1r,A,0,0}, /* inc.w */ - {112,7,a2r,A,0,0}, /* put.w */ - {113,7,a2r,A,0,0}, /* snd.w */ - {107,8,a2r,S,0,0}, /* matr.l */ - {108,8,a2r,S,0,0}, /* mat.l */ - {109,8,a1r,S,0,0}, /* get.l */ - {110,8,a1r,S,0,0}, /* rcv.l */ - {0,0,0,0,0,0}, - {111,8,a1r,S,0,0}, /* inc.l */ - {112,8,a2r,S,0,0}, /* put.l */ - {113,8,a2r,S,0,0}, /* snd.l */ - {18,13,a1r,V,0,0}, /* ld.b.f */ - {18,14,a1r,V,0,0}, /* ld.h.f */ - {18,15,a1r,V,0,0}, /* ld.w.f */ - {18,16,a1r,V,0,0}, /* ld.l.f */ - {21,13,a2r,V,0,0}, /* st.b.f */ - {21,14,a2r,V,0,0}, /* st.h.f */ - {21,15,a2r,V,0,0}, /* st.w.f */ - {21,16,a2r,V,0,0}, /* st.l.f */ -}; - -const struct formstr e0_format2[] = { - {28,5,rr,V,V,0}, /* cvtw.b */ - {28,6,rr,V,V,0}, /* cvtw.h */ - {29,7,rr,V,V,0}, /* cvtb.w */ - {30,7,rr,V,V,0}, /* cvth.w */ - {28,13,rr,V,V,0}, /* cvtw.b.f */ - {28,14,rr,V,V,0}, /* cvtw.h.f */ - {29,15,rr,V,V,0}, /* cvtb.w.f */ - {30,15,rr,V,V,0}, /* cvth.w.f */ - {31,8,rr,V,V,0}, /* cvts.l */ - {32,7,rr,V,V,0}, /* cvtd.w */ - {33,3,rr,V,V,0}, /* cvtl.s */ - {28,4,rr,V,V,0}, /* cvtw.d */ - {31,16,rr,V,V,0}, /* cvts.l.f */ - {32,15,rr,V,V,0}, /* cvtd.w.f */ - {33,11,rr,V,V,0}, /* cvtl.s.f */ - {28,12,rr,V,V,0}, /* cvtw.d.f */ - {114,0,rr,S,S,0}, /* enal */ - {8,7,rr,S,S,0}, /* shf.w */ - {115,0,rr,S,S,0}, /* enag */ - {0,0,0,0,0,0}, - {28,4,rr,S,S,0}, /* cvtw.d */ - {32,7,rr,S,S,0}, /* cvtd.w */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {116,3,rr,S,S,0}, /* frint.s */ - {116,4,rr,S,S,0}, /* frint.d */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {116,3,rr,V,V,0}, /* frint.s */ - {116,4,rr,V,V,0}, /* frint.d */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {116,11,rr,V,V,0}, /* frint.s.f */ - {116,12,rr,V,V,0}, /* frint.d.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {81,3,rr,V,V,0}, /* sqrt.s */ - {81,4,rr,V,V,0}, /* sqrt.d */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {81,11,rr,V,V,0}, /* sqrt.s.f */ - {81,12,rr,V,V,0}, /* sqrt.d.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e0_format3[] = { - {32,11,rr,V,V,0}, /* cvtd.s.f */ - {31,12,rr,V,V,0}, /* cvts.d.f */ - {33,12,rr,V,V,0}, /* cvtl.d.f */ - {32,16,rr,V,V,0}, /* cvtd.l.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {36,2,rr,V,V,0}, /* tzc.f */ - {44,2,rr,V,V,0}, /* lop.f */ - {117,2,rr,V,V,0}, /* xpnd.f */ - {42,2,rr,V,V,0}, /* not.f */ - {8,2,rr,S,V,0}, /* shf.f */ - {35,17,rr,V,V,0}, /* plc.t.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {37,11,rr,V,V,0}, /* eq.s.f */ - {37,12,rr,V,V,0}, /* eq.d.f */ - {43,11,rr,V,V,0}, /* neg.s.f */ - {43,12,rr,V,V,0}, /* neg.d.f */ - {37,11,rr,S,V,0}, /* eq.s.f */ - {37,12,rr,S,V,0}, /* eq.d.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {40,11,rr,V,V,0}, /* le.s.f */ - {40,12,rr,V,V,0}, /* le.d.f */ - {41,11,rr,V,V,0}, /* lt.s.f */ - {41,12,rr,V,V,0}, /* lt.d.f */ - {40,11,rr,S,V,0}, /* le.s.f */ - {40,12,rr,S,V,0}, /* le.d.f */ - {41,11,rr,S,V,0}, /* lt.s.f */ - {41,12,rr,S,V,0}, /* lt.d.f */ - {37,13,rr,V,V,0}, /* eq.b.f */ - {37,14,rr,V,V,0}, /* eq.h.f */ - {37,15,rr,V,V,0}, /* eq.w.f */ - {37,16,rr,V,V,0}, /* eq.l.f */ - {37,13,rr,S,V,0}, /* eq.b.f */ - {37,14,rr,S,V,0}, /* eq.h.f */ - {37,15,rr,S,V,0}, /* eq.w.f */ - {37,16,rr,S,V,0}, /* eq.l.f */ - {40,13,rr,V,V,0}, /* le.b.f */ - {40,14,rr,V,V,0}, /* le.h.f */ - {40,15,rr,V,V,0}, /* le.w.f */ - {40,16,rr,V,V,0}, /* le.l.f */ - {40,13,rr,S,V,0}, /* le.b.f */ - {40,14,rr,S,V,0}, /* le.h.f */ - {40,15,rr,S,V,0}, /* le.w.f */ - {40,16,rr,S,V,0}, /* le.l.f */ - {41,13,rr,V,V,0}, /* lt.b.f */ - {41,14,rr,V,V,0}, /* lt.h.f */ - {41,15,rr,V,V,0}, /* lt.w.f */ - {41,16,rr,V,V,0}, /* lt.l.f */ - {41,13,rr,S,V,0}, /* lt.b.f */ - {41,14,rr,S,V,0}, /* lt.h.f */ - {41,15,rr,S,V,0}, /* lt.w.f */ - {41,16,rr,S,V,0}, /* lt.l.f */ - {43,13,rr,V,V,0}, /* neg.b.f */ - {43,14,rr,V,V,0}, /* neg.h.f */ - {43,15,rr,V,V,0}, /* neg.w.f */ - {43,16,rr,V,V,0}, /* neg.l.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e0_format4[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e0_format5[] = { - {51,13,rr,V,V,0}, /* ldvi.b.f */ - {51,14,rr,V,V,0}, /* ldvi.h.f */ - {51,15,rr,V,V,0}, /* ldvi.w.f */ - {51,16,rr,V,V,0}, /* ldvi.l.f */ - {28,11,rr,V,V,0}, /* cvtw.s.f */ - {31,15,rr,V,V,0}, /* cvts.w.f */ - {28,16,rr,V,V,0}, /* cvtw.l.f */ - {33,15,rr,V,V,0}, /* cvtl.w.f */ - {52,13,rxr,V,V,0}, /* stvi.b.f */ - {52,14,rxr,V,V,0}, /* stvi.h.f */ - {52,15,rxr,V,V,0}, /* stvi.w.f */ - {52,16,rxr,V,V,0}, /* stvi.l.f */ - {52,13,rxr,S,V,0}, /* stvi.b.f */ - {52,14,rxr,S,V,0}, /* stvi.h.f */ - {52,15,rxr,S,V,0}, /* stvi.w.f */ - {52,16,rxr,S,V,0}, /* stvi.l.f */ -}; - -const struct formstr e0_format6[] = { - {0,0,rxl,S,CIR,0}, /* mov */ - {0,0,lr,CIR,S,0}, /* mov */ - {0,0,lr,TOC,S,0}, /* mov */ - {0,0,lr,CPUID,S,0}, /* mov */ - {0,0,rxl,S,TTR,0}, /* mov */ - {0,0,lr,TTR,S,0}, /* mov */ - {118,0,nops,0,0,0}, /* ctrsl */ - {119,0,nops,0,0,0}, /* ctrsg */ - {0,0,rxl,S,VMU,0}, /* mov */ - {0,0,lr,VMU,S,0}, /* mov */ - {0,0,rxl,S,VML,0}, /* mov */ - {0,0,lr,VML,S,0}, /* mov */ - {0,0,rxl,S,ICR,0}, /* mov */ - {0,0,lr,ICR,S,0}, /* mov */ - {0,0,rxl,S,TCPU,0}, /* mov */ - {0,0,lr,TCPU,S,0}, /* mov */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {120,0,nops,0,0,0}, /* stop */ - {0,0,0,0,0,0}, - {0,0,rxl,S,TID,0}, /* mov */ - {0,0,lr,TID,S,0}, /* mov */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e0_format7[] = { - {84,13,r,V,0,0}, /* sum.b.f */ - {84,14,r,V,0,0}, /* sum.h.f */ - {84,15,r,V,0,0}, /* sum.w.f */ - {84,16,r,V,0,0}, /* sum.l.f */ - {85,2,r,V,0,0}, /* all.f */ - {86,2,r,V,0,0}, /* any.f */ - {87,2,r,V,0,0}, /* parity.f */ - {0,0,0,0,0,0}, - {88,13,r,V,0,0}, /* max.b.f */ - {88,14,r,V,0,0}, /* max.h.f */ - {88,15,r,V,0,0}, /* max.w.f */ - {88,16,r,V,0,0}, /* max.l.f */ - {89,13,r,V,0,0}, /* min.b.f */ - {89,14,r,V,0,0}, /* min.h.f */ - {89,15,r,V,0,0}, /* min.w.f */ - {89,16,r,V,0,0}, /* min.l.f */ - {84,11,r,V,0,0}, /* sum.s.f */ - {84,12,r,V,0,0}, /* sum.d.f */ - {90,11,r,V,0,0}, /* prod.s.f */ - {90,12,r,V,0,0}, /* prod.d.f */ - {88,11,r,V,0,0}, /* max.s.f */ - {88,12,r,V,0,0}, /* max.d.f */ - {89,11,r,V,0,0}, /* min.s.f */ - {89,12,r,V,0,0}, /* min.d.f */ - {90,13,r,V,0,0}, /* prod.b.f */ - {90,14,r,V,0,0}, /* prod.h.f */ - {90,15,r,V,0,0}, /* prod.w.f */ - {90,16,r,V,0,0}, /* prod.l.f */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e1_format0[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {10,18,rrr,S,V,V}, /* sub.s.t */ - {10,19,rrr,S,V,V}, /* sub.d.t */ - {4,18,rrr,S,V,V}, /* div.s.t */ - {4,19,rrr,S,V,V}, /* div.d.t */ - {3,18,rrr,V,V,V}, /* mul.s.t */ - {3,19,rrr,V,V,V}, /* mul.d.t */ - {4,18,rrr,V,V,V}, /* div.s.t */ - {4,19,rrr,V,V,V}, /* div.d.t */ - {3,18,rrr,V,S,V}, /* mul.s.t */ - {3,19,rrr,V,S,V}, /* mul.d.t */ - {4,18,rrr,V,S,V}, /* div.s.t */ - {4,19,rrr,V,S,V}, /* div.d.t */ - {5,1,rrr,V,V,V}, /* and.t */ - {6,1,rrr,V,V,V}, /* or.t */ - {7,1,rrr,V,V,V}, /* xor.t */ - {8,1,rrr,V,V,V}, /* shf.t */ - {5,1,rrr,V,S,V}, /* and.t */ - {6,1,rrr,V,S,V}, /* or.t */ - {7,1,rrr,V,S,V}, /* xor.t */ - {8,1,rrr,V,S,V}, /* shf.t */ - {9,18,rrr,V,V,V}, /* add.s.t */ - {9,19,rrr,V,V,V}, /* add.d.t */ - {10,18,rrr,V,V,V}, /* sub.s.t */ - {10,19,rrr,V,V,V}, /* sub.d.t */ - {9,18,rrr,V,S,V}, /* add.s.t */ - {9,19,rrr,V,S,V}, /* add.d.t */ - {10,18,rrr,V,S,V}, /* sub.s.t */ - {10,19,rrr,V,S,V}, /* sub.d.t */ - {9,20,rrr,V,V,V}, /* add.b.t */ - {9,21,rrr,V,V,V}, /* add.h.t */ - {9,22,rrr,V,V,V}, /* add.w.t */ - {9,23,rrr,V,V,V}, /* add.l.t */ - {9,20,rrr,V,S,V}, /* add.b.t */ - {9,21,rrr,V,S,V}, /* add.h.t */ - {9,22,rrr,V,S,V}, /* add.w.t */ - {9,23,rrr,V,S,V}, /* add.l.t */ - {10,20,rrr,V,V,V}, /* sub.b.t */ - {10,21,rrr,V,V,V}, /* sub.h.t */ - {10,22,rrr,V,V,V}, /* sub.w.t */ - {10,23,rrr,V,V,V}, /* sub.l.t */ - {10,20,rrr,V,S,V}, /* sub.b.t */ - {10,21,rrr,V,S,V}, /* sub.h.t */ - {10,22,rrr,V,S,V}, /* sub.w.t */ - {10,23,rrr,V,S,V}, /* sub.l.t */ - {3,20,rrr,V,V,V}, /* mul.b.t */ - {3,21,rrr,V,V,V}, /* mul.h.t */ - {3,22,rrr,V,V,V}, /* mul.w.t */ - {3,23,rrr,V,V,V}, /* mul.l.t */ - {3,20,rrr,V,S,V}, /* mul.b.t */ - {3,21,rrr,V,S,V}, /* mul.h.t */ - {3,22,rrr,V,S,V}, /* mul.w.t */ - {3,23,rrr,V,S,V}, /* mul.l.t */ - {4,20,rrr,V,V,V}, /* div.b.t */ - {4,21,rrr,V,V,V}, /* div.h.t */ - {4,22,rrr,V,V,V}, /* div.w.t */ - {4,23,rrr,V,V,V}, /* div.l.t */ - {4,20,rrr,V,S,V}, /* div.b.t */ - {4,21,rrr,V,S,V}, /* div.h.t */ - {4,22,rrr,V,S,V}, /* div.w.t */ - {4,23,rrr,V,S,V}, /* div.l.t */ -}; - -const struct formstr e1_format1[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {26,20,a2r,S,0,0}, /* ste.b.t */ - {26,21,a2r,S,0,0}, /* ste.h.t */ - {26,22,a2r,S,0,0}, /* ste.w.t */ - {26,23,a2r,S,0,0}, /* ste.l.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {18,20,a1r,V,0,0}, /* ld.b.t */ - {18,21,a1r,V,0,0}, /* ld.h.t */ - {18,22,a1r,V,0,0}, /* ld.w.t */ - {18,23,a1r,V,0,0}, /* ld.l.t */ - {21,20,a2r,V,0,0}, /* st.b.t */ - {21,21,a2r,V,0,0}, /* st.h.t */ - {21,22,a2r,V,0,0}, /* st.w.t */ - {21,23,a2r,V,0,0}, /* st.l.t */ -}; - -const struct formstr e1_format2[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {28,20,rr,V,V,0}, /* cvtw.b.t */ - {28,21,rr,V,V,0}, /* cvtw.h.t */ - {29,22,rr,V,V,0}, /* cvtb.w.t */ - {30,22,rr,V,V,0}, /* cvth.w.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {31,23,rr,V,V,0}, /* cvts.l.t */ - {32,22,rr,V,V,0}, /* cvtd.w.t */ - {33,18,rr,V,V,0}, /* cvtl.s.t */ - {28,19,rr,V,V,0}, /* cvtw.d.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {116,18,rr,V,V,0}, /* frint.s.t */ - {116,19,rr,V,V,0}, /* frint.d.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {81,18,rr,V,V,0}, /* sqrt.s.t */ - {81,19,rr,V,V,0}, /* sqrt.d.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e1_format3[] = { - {32,18,rr,V,V,0}, /* cvtd.s.t */ - {31,19,rr,V,V,0}, /* cvts.d.t */ - {33,19,rr,V,V,0}, /* cvtl.d.t */ - {32,23,rr,V,V,0}, /* cvtd.l.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {36,1,rr,V,V,0}, /* tzc.t */ - {44,1,rr,V,V,0}, /* lop.t */ - {117,1,rr,V,V,0}, /* xpnd.t */ - {42,1,rr,V,V,0}, /* not.t */ - {8,1,rr,S,V,0}, /* shf.t */ - {35,24,rr,V,V,0}, /* plc.t.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {37,18,rr,V,V,0}, /* eq.s.t */ - {37,19,rr,V,V,0}, /* eq.d.t */ - {43,18,rr,V,V,0}, /* neg.s.t */ - {43,19,rr,V,V,0}, /* neg.d.t */ - {37,18,rr,S,V,0}, /* eq.s.t */ - {37,19,rr,S,V,0}, /* eq.d.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {40,18,rr,V,V,0}, /* le.s.t */ - {40,19,rr,V,V,0}, /* le.d.t */ - {41,18,rr,V,V,0}, /* lt.s.t */ - {41,19,rr,V,V,0}, /* lt.d.t */ - {40,18,rr,S,V,0}, /* le.s.t */ - {40,19,rr,S,V,0}, /* le.d.t */ - {41,18,rr,S,V,0}, /* lt.s.t */ - {41,19,rr,S,V,0}, /* lt.d.t */ - {37,20,rr,V,V,0}, /* eq.b.t */ - {37,21,rr,V,V,0}, /* eq.h.t */ - {37,22,rr,V,V,0}, /* eq.w.t */ - {37,23,rr,V,V,0}, /* eq.l.t */ - {37,20,rr,S,V,0}, /* eq.b.t */ - {37,21,rr,S,V,0}, /* eq.h.t */ - {37,22,rr,S,V,0}, /* eq.w.t */ - {37,23,rr,S,V,0}, /* eq.l.t */ - {40,20,rr,V,V,0}, /* le.b.t */ - {40,21,rr,V,V,0}, /* le.h.t */ - {40,22,rr,V,V,0}, /* le.w.t */ - {40,23,rr,V,V,0}, /* le.l.t */ - {40,20,rr,S,V,0}, /* le.b.t */ - {40,21,rr,S,V,0}, /* le.h.t */ - {40,22,rr,S,V,0}, /* le.w.t */ - {40,23,rr,S,V,0}, /* le.l.t */ - {41,20,rr,V,V,0}, /* lt.b.t */ - {41,21,rr,V,V,0}, /* lt.h.t */ - {41,22,rr,V,V,0}, /* lt.w.t */ - {41,23,rr,V,V,0}, /* lt.l.t */ - {41,20,rr,S,V,0}, /* lt.b.t */ - {41,21,rr,S,V,0}, /* lt.h.t */ - {41,22,rr,S,V,0}, /* lt.w.t */ - {41,23,rr,S,V,0}, /* lt.l.t */ - {43,20,rr,V,V,0}, /* neg.b.t */ - {43,21,rr,V,V,0}, /* neg.h.t */ - {43,22,rr,V,V,0}, /* neg.w.t */ - {43,23,rr,V,V,0}, /* neg.l.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e1_format4[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e1_format5[] = { - {51,20,rr,V,V,0}, /* ldvi.b.t */ - {51,21,rr,V,V,0}, /* ldvi.h.t */ - {51,22,rr,V,V,0}, /* ldvi.w.t */ - {51,23,rr,V,V,0}, /* ldvi.l.t */ - {28,18,rr,V,V,0}, /* cvtw.s.t */ - {31,22,rr,V,V,0}, /* cvts.w.t */ - {28,23,rr,V,V,0}, /* cvtw.l.t */ - {33,22,rr,V,V,0}, /* cvtl.w.t */ - {52,20,rxr,V,V,0}, /* stvi.b.t */ - {52,21,rxr,V,V,0}, /* stvi.h.t */ - {52,22,rxr,V,V,0}, /* stvi.w.t */ - {52,23,rxr,V,V,0}, /* stvi.l.t */ - {52,20,rxr,S,V,0}, /* stvi.b.t */ - {52,21,rxr,S,V,0}, /* stvi.h.t */ - {52,22,rxr,S,V,0}, /* stvi.w.t */ - {52,23,rxr,S,V,0}, /* stvi.l.t */ -}; - -const struct formstr e1_format6[] = { - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -const struct formstr e1_format7[] = { - {84,20,r,V,0,0}, /* sum.b.t */ - {84,21,r,V,0,0}, /* sum.h.t */ - {84,22,r,V,0,0}, /* sum.w.t */ - {84,23,r,V,0,0}, /* sum.l.t */ - {85,1,r,V,0,0}, /* all.t */ - {86,1,r,V,0,0}, /* any.t */ - {87,1,r,V,0,0}, /* parity.t */ - {0,0,0,0,0,0}, - {88,20,r,V,0,0}, /* max.b.t */ - {88,21,r,V,0,0}, /* max.h.t */ - {88,22,r,V,0,0}, /* max.w.t */ - {88,23,r,V,0,0}, /* max.l.t */ - {89,20,r,V,0,0}, /* min.b.t */ - {89,21,r,V,0,0}, /* min.h.t */ - {89,22,r,V,0,0}, /* min.w.t */ - {89,23,r,V,0,0}, /* min.l.t */ - {84,18,r,V,0,0}, /* sum.s.t */ - {84,19,r,V,0,0}, /* sum.d.t */ - {90,18,r,V,0,0}, /* prod.s.t */ - {90,19,r,V,0,0}, /* prod.d.t */ - {88,18,r,V,0,0}, /* max.s.t */ - {88,19,r,V,0,0}, /* max.d.t */ - {89,18,r,V,0,0}, /* min.s.t */ - {89,19,r,V,0,0}, /* min.d.t */ - {90,20,r,V,0,0}, /* prod.b.t */ - {90,21,r,V,0,0}, /* prod.h.t */ - {90,22,r,V,0,0}, /* prod.w.t */ - {90,23,r,V,0,0}, /* prod.l.t */ - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, - {0,0,0,0,0,0}, -}; - -char *lop[] = { - "mov", /* 0 */ - "merg", /* 1 */ - "mask", /* 2 */ - "mul", /* 3 */ - "div", /* 4 */ - "and", /* 5 */ - "or", /* 6 */ - "xor", /* 7 */ - "shf", /* 8 */ - "add", /* 9 */ - "sub", /* 10 */ - "exit", /* 11 */ - "jmp", /* 12 */ - "jmpi", /* 13 */ - "jmpa", /* 14 */ - "jmps", /* 15 */ - "tac", /* 16 */ - "ldea", /* 17 */ - "ld", /* 18 */ - "tas", /* 19 */ - "pshea", /* 20 */ - "st", /* 21 */ - "call", /* 22 */ - "calls", /* 23 */ - "callq", /* 24 */ - "pfork", /* 25 */ - "ste", /* 26 */ - "incr", /* 27 */ - "cvtw", /* 28 */ - "cvtb", /* 29 */ - "cvth", /* 30 */ - "cvts", /* 31 */ - "cvtd", /* 32 */ - "cvtl", /* 33 */ - "ldpa", /* 34 */ - "plc", /* 35 */ - "tzc", /* 36 */ - "eq", /* 37 */ - "leu", /* 38 */ - "ltu", /* 39 */ - "le", /* 40 */ - "lt", /* 41 */ - "not", /* 42 */ - "neg", /* 43 */ - "lop", /* 44 */ - "cprs", /* 45 */ - "nop", /* 46 */ - "br", /* 47 */ - "bri", /* 48 */ - "bra", /* 49 */ - "brs", /* 50 */ - "ldvi", /* 51 */ - "stvi", /* 52 */ - "ldsdr", /* 53 */ - "ldkdr", /* 54 */ - "ln", /* 55 */ - "patu", /* 56 */ - "pate", /* 57 */ - "pich", /* 58 */ - "plch", /* 59 */ - "idle", /* 60 */ - "rtnq", /* 61 */ - "cfork", /* 62 */ - "rtn", /* 63 */ - "wfork", /* 64 */ - "join", /* 65 */ - "rtnc", /* 66 */ - "exp", /* 67 */ - "sin", /* 68 */ - "cos", /* 69 */ - "psh", /* 70 */ - "pop", /* 71 */ - "eni", /* 72 */ - "dsi", /* 73 */ - "bkpt", /* 74 */ - "msync", /* 75 */ - "mski", /* 76 */ - "xmti", /* 77 */ - "tstvv", /* 78 */ - "diag", /* 79 */ - "pbkpt", /* 80 */ - "sqrt", /* 81 */ - "casr", /* 82 */ - "atan", /* 83 */ - "sum", /* 84 */ - "all", /* 85 */ - "any", /* 86 */ - "parity", /* 87 */ - "max", /* 88 */ - "min", /* 89 */ - "prod", /* 90 */ - "halt", /* 91 */ - "sysc", /* 92 */ - "trap", /* 93 */ - "tst", /* 94 */ - "lck", /* 95 */ - "ulk", /* 96 */ - "spawn", /* 97 */ - "ldcmr", /* 98 */ - "stcmr", /* 99 */ - "popr", /* 100 */ - "pshr", /* 101 */ - "rcvr", /* 102 */ - "matm", /* 103 */ - "sndr", /* 104 */ - "putr", /* 105 */ - "getr", /* 106 */ - "matr", /* 107 */ - "mat", /* 108 */ - "get", /* 109 */ - "rcv", /* 110 */ - "inc", /* 111 */ - "put", /* 112 */ - "snd", /* 113 */ - "enal", /* 114 */ - "enag", /* 115 */ - "frint", /* 116 */ - "xpnd", /* 117 */ - "ctrsl", /* 118 */ - "ctrsg", /* 119 */ - "stop", /* 120 */ -}; - -char *rop[] = { - "", /* 0 */ - ".t", /* 1 */ - ".f", /* 2 */ - ".s", /* 3 */ - ".d", /* 4 */ - ".b", /* 5 */ - ".h", /* 6 */ - ".w", /* 7 */ - ".l", /* 8 */ - ".x", /* 9 */ - ".u", /* 10 */ - ".s.f", /* 11 */ - ".d.f", /* 12 */ - ".b.f", /* 13 */ - ".h.f", /* 14 */ - ".w.f", /* 15 */ - ".l.f", /* 16 */ - ".t.f", /* 17 */ - ".s.t", /* 18 */ - ".d.t", /* 19 */ - ".b.t", /* 20 */ - ".h.t", /* 21 */ - ".w.t", /* 22 */ - ".l.t", /* 23 */ - ".t.t", /* 24 */ -}; diff --git a/contrib/binutils/include/opcode/mips.h b/contrib/binutils/include/opcode/mips.h deleted file mode 100644 index 1469e10..0000000 --- a/contrib/binutils/include/opcode/mips.h +++ /dev/null @@ -1,789 +0,0 @@ -/* mips.h. Mips opcode list for GDB, the GNU debugger. - Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001 - Free Software Foundation, Inc. - Contributed by Ralph Campbell and OSF - Commented and modified by Ian Lance Taylor, Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#ifndef _MIPS_H_ -#define _MIPS_H_ - -/* These are bit masks and shift counts to use to access the various - fields of an instruction. To retrieve the X field of an - instruction, use the expression - (i >> OP_SH_X) & OP_MASK_X - To set the same field (to j), use - i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X) - - Make sure you use fields that are appropriate for the instruction, - of course. - - The 'i' format uses OP, RS, RT and IMMEDIATE. - - The 'j' format uses OP and TARGET. - - The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT. - - The 'b' format uses OP, RS, RT and DELTA. - - The floating point 'i' format uses OP, RS, RT and IMMEDIATE. - - The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT. - - A breakpoint instruction uses OP, CODE and SPEC (10 bits of the - breakpoint instruction are not defined; Kane says the breakpoint - code field in BREAK is 20 bits; yet MIPS assemblers and debuggers - only use ten bits). An optional two-operand form of break/sdbbp - allows the lower ten bits to be set too, and MIPS32 and later - architectures allow 20 bits to be set with a signal operand - (using CODE20). - - The syscall instruction uses CODE20. - - The general coprocessor instructions use COPZ. */ - -#define OP_MASK_OP 0x3f -#define OP_SH_OP 26 -#define OP_MASK_RS 0x1f -#define OP_SH_RS 21 -#define OP_MASK_FR 0x1f -#define OP_SH_FR 21 -#define OP_MASK_FMT 0x1f -#define OP_SH_FMT 21 -#define OP_MASK_BCC 0x7 -#define OP_SH_BCC 18 -#define OP_MASK_CODE 0x3ff -#define OP_SH_CODE 16 -#define OP_MASK_CODE2 0x3ff -#define OP_SH_CODE2 6 -#define OP_MASK_RT 0x1f -#define OP_SH_RT 16 -#define OP_MASK_FT 0x1f -#define OP_SH_FT 16 -#define OP_MASK_CACHE 0x1f -#define OP_SH_CACHE 16 -#define OP_MASK_RD 0x1f -#define OP_SH_RD 11 -#define OP_MASK_FS 0x1f -#define OP_SH_FS 11 -#define OP_MASK_PREFX 0x1f -#define OP_SH_PREFX 11 -#define OP_MASK_CCC 0x7 -#define OP_SH_CCC 8 -#define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */ -#define OP_SH_CODE20 6 -#define OP_MASK_SHAMT 0x1f -#define OP_SH_SHAMT 6 -#define OP_MASK_FD 0x1f -#define OP_SH_FD 6 -#define OP_MASK_TARGET 0x3ffffff -#define OP_SH_TARGET 0 -#define OP_MASK_COPZ 0x1ffffff -#define OP_SH_COPZ 0 -#define OP_MASK_IMMEDIATE 0xffff -#define OP_SH_IMMEDIATE 0 -#define OP_MASK_DELTA 0xffff -#define OP_SH_DELTA 0 -#define OP_MASK_FUNCT 0x3f -#define OP_SH_FUNCT 0 -#define OP_MASK_SPEC 0x3f -#define OP_SH_SPEC 0 -#define OP_SH_LOCC 8 /* FP condition code. */ -#define OP_SH_HICC 18 /* FP condition code. */ -#define OP_MASK_CC 0x7 -#define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */ -#define OP_MASK_COP1NORM 0x1 /* a single bit. */ -#define OP_SH_COP1SPEC 21 /* COP1 encodings. */ -#define OP_MASK_COP1SPEC 0xf -#define OP_MASK_COP1SCLR 0x4 -#define OP_MASK_COP1CMP 0x3 -#define OP_SH_COP1CMP 4 -#define OP_SH_FORMAT 21 /* FP short format field. */ -#define OP_MASK_FORMAT 0x7 -#define OP_SH_TRUE 16 -#define OP_MASK_TRUE 0x1 -#define OP_SH_GE 17 -#define OP_MASK_GE 0x01 -#define OP_SH_UNSIGNED 16 -#define OP_MASK_UNSIGNED 0x1 -#define OP_SH_HINT 16 -#define OP_MASK_HINT 0x1f -#define OP_SH_MMI 0 /* Multimedia (parallel) op. */ -#define OP_MASK_MMI 0x3f -#define OP_SH_MMISUB 6 -#define OP_MASK_MMISUB 0x1f -#define OP_MASK_PERFREG 0x1f /* Performance monitoring. */ -#define OP_SH_PERFREG 1 -#define OP_SH_SEL 0 /* Coprocessor select field. */ -#define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */ -#define OP_SH_CODE19 6 /* 19 bit wait code. */ -#define OP_MASK_CODE19 0x7ffff - -/* This structure holds information for a particular instruction. */ - -struct mips_opcode -{ - /* The name of the instruction. */ - const char *name; - /* A string describing the arguments for this instruction. */ - const char *args; - /* The basic opcode for the instruction. When assembling, this - opcode is modified by the arguments to produce the actual opcode - that is used. If pinfo is INSN_MACRO, then this is 0. */ - unsigned long match; - /* If pinfo is not INSN_MACRO, then this is a bit mask for the - relevant portions of the opcode when disassembling. If the - actual opcode anded with the match field equals the opcode field, - then we have found the correct instruction. If pinfo is - INSN_MACRO, then this field is the macro identifier. */ - unsigned long mask; - /* For a macro, this is INSN_MACRO. Otherwise, it is a collection - of bits describing the instruction, notably any relevant hazard - information. */ - unsigned long pinfo; - /* A collection of bits describing the instruction sets of which this - instruction or macro is a member. */ - unsigned long membership; -}; - -/* These are the characters which may appears in the args field of an - instruction. They appear in the order in which the fields appear - when the instruction is used. Commas and parentheses in the args - string are ignored when assembling, and written into the output - when disassembling. - - Each of these characters corresponds to a mask field defined above. - - "<" 5 bit shift amount (OP_*_SHAMT) - ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) - "a" 26 bit target address (OP_*_TARGET) - "b" 5 bit base register (OP_*_RS) - "c" 10 bit breakpoint code (OP_*_CODE) - "d" 5 bit destination register specifier (OP_*_RD) - "h" 5 bit prefx hint (OP_*_PREFX) - "i" 16 bit unsigned immediate (OP_*_IMMEDIATE) - "j" 16 bit signed immediate (OP_*_DELTA) - "k" 5 bit cache opcode in target register position (OP_*_CACHE) - "o" 16 bit signed offset (OP_*_DELTA) - "p" 16 bit PC relative branch target address (OP_*_DELTA) - "q" 10 bit extra breakpoint code (OP_*_CODE2) - "r" 5 bit same register used as both source and target (OP_*_RS) - "s" 5 bit source register specifier (OP_*_RS) - "t" 5 bit target register (OP_*_RT) - "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE) - "v" 5 bit same register used as both source and destination (OP_*_RS) - "w" 5 bit same register used as both target and destination (OP_*_RT) - "U" 5 bit same destination register in both OP_*_RD and OP_*_RT - (used by clo and clz) - "C" 25 bit coprocessor function code (OP_*_COPZ) - "B" 20 bit syscall/breakpoint function code (OP_*_CODE20) - "J" 19 bit wait function code (OP_*_CODE19) - "x" accept and ignore register name - "z" must be zero register - - Floating point instructions: - "D" 5 bit destination register (OP_*_FD) - "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up) - "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up) - "S" 5 bit fs source 1 register (OP_*_FS) - "T" 5 bit ft source 2 register (OP_*_FT) - "R" 5 bit fr source 3 register (OP_*_FR) - "V" 5 bit same register used as floating source and destination (OP_*_FS) - "W" 5 bit same register used as floating target and destination (OP_*_FT) - - Coprocessor instructions: - "E" 5 bit target register (OP_*_RT) - "G" 5 bit destination register (OP_*_RD) - "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) - "P" 5 bit performance-monitor register (OP_*_PERFREG) - - Macro instructions: - "A" General 32 bit expression - "I" 32 bit immediate - "F" 64 bit floating point constant in .rdata - "L" 64 bit floating point constant in .lit8 - "f" 32 bit floating point constant - "l" 32 bit floating point constant in .lit4 - - Other: - "()" parens surrounding optional value - "," separates operands - - Characters used so far, for quick reference when adding more: - "<>()," - "ABCDEFGHIJLMNPRSTUVW" - "abcdfhijklopqrstuvwxz" -*/ - -/* These are the bits which may be set in the pinfo field of an - instructions, if it is not equal to INSN_MACRO. */ - -/* Modifies the general purpose register in OP_*_RD. */ -#define INSN_WRITE_GPR_D 0x00000001 -/* Modifies the general purpose register in OP_*_RT. */ -#define INSN_WRITE_GPR_T 0x00000002 -/* Modifies general purpose register 31. */ -#define INSN_WRITE_GPR_31 0x00000004 -/* Modifies the floating point register in OP_*_FD. */ -#define INSN_WRITE_FPR_D 0x00000008 -/* Modifies the floating point register in OP_*_FS. */ -#define INSN_WRITE_FPR_S 0x00000010 -/* Modifies the floating point register in OP_*_FT. */ -#define INSN_WRITE_FPR_T 0x00000020 -/* Reads the general purpose register in OP_*_RS. */ -#define INSN_READ_GPR_S 0x00000040 -/* Reads the general purpose register in OP_*_RT. */ -#define INSN_READ_GPR_T 0x00000080 -/* Reads the floating point register in OP_*_FS. */ -#define INSN_READ_FPR_S 0x00000100 -/* Reads the floating point register in OP_*_FT. */ -#define INSN_READ_FPR_T 0x00000200 -/* Reads the floating point register in OP_*_FR. */ -#define INSN_READ_FPR_R 0x00000400 -/* Modifies coprocessor condition code. */ -#define INSN_WRITE_COND_CODE 0x00000800 -/* Reads coprocessor condition code. */ -#define INSN_READ_COND_CODE 0x00001000 -/* TLB operation. */ -#define INSN_TLB 0x00002000 -/* Reads coprocessor register other than floating point register. */ -#define INSN_COP 0x00004000 -/* Instruction loads value from memory, requiring delay. */ -#define INSN_LOAD_MEMORY_DELAY 0x00008000 -/* Instruction loads value from coprocessor, requiring delay. */ -#define INSN_LOAD_COPROC_DELAY 0x00010000 -/* Instruction has unconditional branch delay slot. */ -#define INSN_UNCOND_BRANCH_DELAY 0x00020000 -/* Instruction has conditional branch delay slot. */ -#define INSN_COND_BRANCH_DELAY 0x00040000 -/* Conditional branch likely: if branch not taken, insn nullified. */ -#define INSN_COND_BRANCH_LIKELY 0x00080000 -/* Moves to coprocessor register, requiring delay. */ -#define INSN_COPROC_MOVE_DELAY 0x00100000 -/* Loads coprocessor register from memory, requiring delay. */ -#define INSN_COPROC_MEMORY_DELAY 0x00200000 -/* Reads the HI register. */ -#define INSN_READ_HI 0x00400000 -/* Reads the LO register. */ -#define INSN_READ_LO 0x00800000 -/* Modifies the HI register. */ -#define INSN_WRITE_HI 0x01000000 -/* Modifies the LO register. */ -#define INSN_WRITE_LO 0x02000000 -/* Takes a trap (easier to keep out of delay slot). */ -#define INSN_TRAP 0x04000000 -/* Instruction stores value into memory. */ -#define INSN_STORE_MEMORY 0x08000000 -/* Instruction uses single precision floating point. */ -#define FP_S 0x10000000 -/* Instruction uses double precision floating point. */ -#define FP_D 0x20000000 -/* Instruction is part of the tx39's integer multiply family. */ -#define INSN_MULT 0x40000000 -/* Instruction synchronize shared memory. */ -#define INSN_SYNC 0x80000000 - -/* Instruction is actually a macro. It should be ignored by the - disassembler, and requires special treatment by the assembler. */ -#define INSN_MACRO 0xffffffff - -/* Masks used to mark instructions to indicate which MIPS ISA level - they were introduced in. ISAs, as defined below, are logical - ORs of these bits, indicatingthat they support the instructions - defined at the given level. */ - -#define INSN_ISA_MASK 0x00000fff -#define INSN_ISA1 0x00000010 -#define INSN_ISA2 0x00000020 -#define INSN_ISA3 0x00000040 -#define INSN_ISA4 0x00000080 -#define INSN_ISA5 0x00000100 -#define INSN_ISA32 0x00000200 -#define INSN_ISA64 0x00000400 - -/* Chip specific instructions. These are bitmasks. */ - -/* MIPS R4650 instruction. */ -#define INSN_4650 0x00010000 -/* LSI R4010 instruction. */ -#define INSN_4010 0x00020000 -/* NEC VR4100 instruction. */ -#define INSN_4100 0x00040000 -/* Toshiba R3900 instruction. */ -#define INSN_3900 0x00080000 -/* MIPS R10000 instruction. */ -#define INSN_10000 0x00100000 -/* Broadcom SB-1 instruction. */ -#define INSN_SB1 0x00200000 - -/* MIPS ISA defines, use instead of hardcoding ISA level. */ - -#define ISA_UNKNOWN 0 /* Gas internal use. */ -#define ISA_MIPS1 (INSN_ISA1) -#define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2) -#define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3) -#define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4) -#define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5) -#define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32) -#define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64) - -/* CPU defines, use instead of hardcoding processor number. Keep this - in sync with bfd/archures.c in order for machine selection to work. */ -#define CPU_UNKNOWN 0 /* Gas internal use. */ -#define CPU_R2000 2000 -#define CPU_R3000 3000 -#define CPU_R3900 3900 -#define CPU_R4000 4000 -#define CPU_R4010 4010 -#define CPU_VR4100 4100 -#define CPU_R4111 4111 -#define CPU_R4300 4300 -#define CPU_R4400 4400 -#define CPU_R4600 4600 -#define CPU_R4650 4650 -#define CPU_R5000 5000 -#define CPU_R6000 6000 -#define CPU_R8000 8000 -#define CPU_R10000 10000 -#define CPU_R12000 12000 -#define CPU_MIPS16 16 -#define CPU_MIPS32 32 -#define CPU_MIPS5 5 -#define CPU_MIPS64 64 -#define CPU_SB1 12310201 /* octal 'SB', 01. */ - -/* Test for membership in an ISA including chip specific ISAs. - INSN is pointer to an element of the opcode table; ISA is the - specified ISA to test against; and CPU is the CPU specific ISA - to test, or zero if no CPU specific ISA test is desired. */ - -#define OPCODE_IS_MEMBER(insn, isa, cpu) \ - (((insn)->membership & isa) != 0 \ - || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ - || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ - || ((cpu == CPU_VR4100 || cpu == CPU_R4111) \ - && ((insn)->membership & INSN_4100) != 0) \ - || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ - || ((cpu == CPU_R10000 || cpu == CPU_R12000) \ - && ((insn)->membership & INSN_10000) != 0) \ - || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \ - || 0) /* Please keep this term for easier source merging. */ - -/* This is a list of macro expanded instructions. - - _I appended means immediate - _A appended means address - _AB appended means address with base register - _D appended means 64 bit floating point constant - _S appended means 32 bit floating point constant. */ - -enum -{ - M_ABS, - M_ADD_I, - M_ADDU_I, - M_AND_I, - M_BEQ, - M_BEQ_I, - M_BEQL_I, - M_BGE, - M_BGEL, - M_BGE_I, - M_BGEL_I, - M_BGEU, - M_BGEUL, - M_BGEU_I, - M_BGEUL_I, - M_BGT, - M_BGTL, - M_BGT_I, - M_BGTL_I, - M_BGTU, - M_BGTUL, - M_BGTU_I, - M_BGTUL_I, - M_BLE, - M_BLEL, - M_BLE_I, - M_BLEL_I, - M_BLEU, - M_BLEUL, - M_BLEU_I, - M_BLEUL_I, - M_BLT, - M_BLTL, - M_BLT_I, - M_BLTL_I, - M_BLTU, - M_BLTUL, - M_BLTU_I, - M_BLTUL_I, - M_BNE, - M_BNE_I, - M_BNEL_I, - M_DABS, - M_DADD_I, - M_DADDU_I, - M_DDIV_3, - M_DDIV_3I, - M_DDIVU_3, - M_DDIVU_3I, - M_DIV_3, - M_DIV_3I, - M_DIVU_3, - M_DIVU_3I, - M_DLA_AB, - M_DLI, - M_DMUL, - M_DMUL_I, - M_DMULO, - M_DMULO_I, - M_DMULOU, - M_DMULOU_I, - M_DREM_3, - M_DREM_3I, - M_DREMU_3, - M_DREMU_3I, - M_DSUB_I, - M_DSUBU_I, - M_DSUBU_I_2, - M_J_A, - M_JAL_1, - M_JAL_2, - M_JAL_A, - M_L_DOB, - M_L_DAB, - M_LA_AB, - M_LB_A, - M_LB_AB, - M_LBU_A, - M_LBU_AB, - M_LD_A, - M_LD_OB, - M_LD_AB, - M_LDC1_AB, - M_LDC2_AB, - M_LDC3_AB, - M_LDL_AB, - M_LDR_AB, - M_LH_A, - M_LH_AB, - M_LHU_A, - M_LHU_AB, - M_LI, - M_LI_D, - M_LI_DD, - M_LI_S, - M_LI_SS, - M_LL_AB, - M_LLD_AB, - M_LS_A, - M_LW_A, - M_LW_AB, - M_LWC0_A, - M_LWC0_AB, - M_LWC1_A, - M_LWC1_AB, - M_LWC2_A, - M_LWC2_AB, - M_LWC3_A, - M_LWC3_AB, - M_LWL_A, - M_LWL_AB, - M_LWR_A, - M_LWR_AB, - M_LWU_AB, - M_MOVE, - M_MUL, - M_MUL_I, - M_MULO, - M_MULO_I, - M_MULOU, - M_MULOU_I, - M_NOR_I, - M_OR_I, - M_REM_3, - M_REM_3I, - M_REMU_3, - M_REMU_3I, - M_ROL, - M_ROL_I, - M_ROR, - M_ROR_I, - M_S_DA, - M_S_DOB, - M_S_DAB, - M_S_S, - M_SC_AB, - M_SCD_AB, - M_SD_A, - M_SD_OB, - M_SD_AB, - M_SDC1_AB, - M_SDC2_AB, - M_SDC3_AB, - M_SDL_AB, - M_SDR_AB, - M_SEQ, - M_SEQ_I, - M_SGE, - M_SGE_I, - M_SGEU, - M_SGEU_I, - M_SGT, - M_SGT_I, - M_SGTU, - M_SGTU_I, - M_SLE, - M_SLE_I, - M_SLEU, - M_SLEU_I, - M_SLT_I, - M_SLTU_I, - M_SNE, - M_SNE_I, - M_SB_A, - M_SB_AB, - M_SH_A, - M_SH_AB, - M_SW_A, - M_SW_AB, - M_SWC0_A, - M_SWC0_AB, - M_SWC1_A, - M_SWC1_AB, - M_SWC2_A, - M_SWC2_AB, - M_SWC3_A, - M_SWC3_AB, - M_SWL_A, - M_SWL_AB, - M_SWR_A, - M_SWR_AB, - M_SUB_I, - M_SUBU_I, - M_SUBU_I_2, - M_TEQ_I, - M_TGE_I, - M_TGEU_I, - M_TLT_I, - M_TLTU_I, - M_TNE_I, - M_TRUNCWD, - M_TRUNCWS, - M_ULD, - M_ULD_A, - M_ULH, - M_ULH_A, - M_ULHU, - M_ULHU_A, - M_ULW, - M_ULW_A, - M_USH, - M_USH_A, - M_USW, - M_USW_A, - M_USD, - M_USD_A, - M_XOR_I, - M_COP0, - M_COP1, - M_COP2, - M_COP3, - M_NUM_MACROS -}; - - -/* The order of overloaded instructions matters. Label arguments and - register arguments look the same. Instructions that can have either - for arguments must apear in the correct order in this table for the - assembler to pick the right one. In other words, entries with - immediate operands must apear after the same instruction with - registers. - - Many instructions are short hand for other instructions (i.e., The - jal <register> instruction is short for jalr <register>). */ - -extern const struct mips_opcode mips_builtin_opcodes[]; -extern const int bfd_mips_num_builtin_opcodes; -extern struct mips_opcode *mips_opcodes; -extern int bfd_mips_num_opcodes; -#define NUMOPCODES bfd_mips_num_opcodes - - -/* The rest of this file adds definitions for the mips16 TinyRISC - processor. */ - -/* These are the bitmasks and shift counts used for the different - fields in the instruction formats. Other than OP, no masks are - provided for the fixed portions of an instruction, since they are - not needed. - - The I format uses IMM11. - - The RI format uses RX and IMM8. - - The RR format uses RX, and RY. - - The RRI format uses RX, RY, and IMM5. - - The RRR format uses RX, RY, and RZ. - - The RRI_A format uses RX, RY, and IMM4. - - The SHIFT format uses RX, RY, and SHAMT. - - The I8 format uses IMM8. - - The I8_MOVR32 format uses RY and REGR32. - - The IR_MOV32R format uses REG32R and MOV32Z. - - The I64 format uses IMM8. - - The RI64 format uses RY and IMM5. - */ - -#define MIPS16OP_MASK_OP 0x1f -#define MIPS16OP_SH_OP 11 -#define MIPS16OP_MASK_IMM11 0x7ff -#define MIPS16OP_SH_IMM11 0 -#define MIPS16OP_MASK_RX 0x7 -#define MIPS16OP_SH_RX 8 -#define MIPS16OP_MASK_IMM8 0xff -#define MIPS16OP_SH_IMM8 0 -#define MIPS16OP_MASK_RY 0x7 -#define MIPS16OP_SH_RY 5 -#define MIPS16OP_MASK_IMM5 0x1f -#define MIPS16OP_SH_IMM5 0 -#define MIPS16OP_MASK_RZ 0x7 -#define MIPS16OP_SH_RZ 2 -#define MIPS16OP_MASK_IMM4 0xf -#define MIPS16OP_SH_IMM4 0 -#define MIPS16OP_MASK_REGR32 0x1f -#define MIPS16OP_SH_REGR32 0 -#define MIPS16OP_MASK_REG32R 0x1f -#define MIPS16OP_SH_REG32R 3 -#define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18)) -#define MIPS16OP_MASK_MOVE32Z 0x7 -#define MIPS16OP_SH_MOVE32Z 0 -#define MIPS16OP_MASK_IMM6 0x3f -#define MIPS16OP_SH_IMM6 5 - -/* These are the characters which may appears in the args field of an - instruction. They appear in the order in which the fields appear - when the instruction is used. Commas and parentheses in the args - string are ignored when assembling, and written into the output - when disassembling. - - "y" 3 bit register (MIPS16OP_*_RY) - "x" 3 bit register (MIPS16OP_*_RX) - "z" 3 bit register (MIPS16OP_*_RZ) - "Z" 3 bit register (MIPS16OP_*_MOVE32Z) - "v" 3 bit same register as source and destination (MIPS16OP_*_RX) - "w" 3 bit same register as source and destination (MIPS16OP_*_RY) - "0" zero register ($0) - "S" stack pointer ($sp or $29) - "P" program counter - "R" return address register ($ra or $31) - "X" 5 bit MIPS register (MIPS16OP_*_REGR32) - "Y" 5 bit MIPS register (MIPS16OP_*_REG32R) - "6" 6 bit unsigned break code (MIPS16OP_*_IMM6) - "a" 26 bit jump address - "e" 11 bit extension value - "l" register list for entry instruction - "L" register list for exit instruction - - The remaining codes may be extended. Except as otherwise noted, - the full extended operand is a 16 bit signed value. - "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) - ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned) - "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) - "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) - "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) - "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) - "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) - "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) - "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) - "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5) - "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) - "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8) - "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8) - "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned) - "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8) - "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8) - "p" 8 bit conditional branch address (MIPS16OP_*_IMM8) - "q" 11 bit branch address (MIPS16OP_*_IMM11) - "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8) - "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5) - "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5) - */ - -/* For the mips16, we use the same opcode table format and a few of - the same flags. However, most of the flags are different. */ - -/* Modifies the register in MIPS16OP_*_RX. */ -#define MIPS16_INSN_WRITE_X 0x00000001 -/* Modifies the register in MIPS16OP_*_RY. */ -#define MIPS16_INSN_WRITE_Y 0x00000002 -/* Modifies the register in MIPS16OP_*_RZ. */ -#define MIPS16_INSN_WRITE_Z 0x00000004 -/* Modifies the T ($24) register. */ -#define MIPS16_INSN_WRITE_T 0x00000008 -/* Modifies the SP ($29) register. */ -#define MIPS16_INSN_WRITE_SP 0x00000010 -/* Modifies the RA ($31) register. */ -#define MIPS16_INSN_WRITE_31 0x00000020 -/* Modifies the general purpose register in MIPS16OP_*_REG32R. */ -#define MIPS16_INSN_WRITE_GPR_Y 0x00000040 -/* Reads the register in MIPS16OP_*_RX. */ -#define MIPS16_INSN_READ_X 0x00000080 -/* Reads the register in MIPS16OP_*_RY. */ -#define MIPS16_INSN_READ_Y 0x00000100 -/* Reads the register in MIPS16OP_*_MOVE32Z. */ -#define MIPS16_INSN_READ_Z 0x00000200 -/* Reads the T ($24) register. */ -#define MIPS16_INSN_READ_T 0x00000400 -/* Reads the SP ($29) register. */ -#define MIPS16_INSN_READ_SP 0x00000800 -/* Reads the RA ($31) register. */ -#define MIPS16_INSN_READ_31 0x00001000 -/* Reads the program counter. */ -#define MIPS16_INSN_READ_PC 0x00002000 -/* Reads the general purpose register in MIPS16OP_*_REGR32. */ -#define MIPS16_INSN_READ_GPR_X 0x00004000 -/* Is a branch insn. */ -#define MIPS16_INSN_BRANCH 0x00010000 - -/* The following flags have the same value for the mips16 opcode - table: - INSN_UNCOND_BRANCH_DELAY - INSN_COND_BRANCH_DELAY - INSN_COND_BRANCH_LIKELY (never used) - INSN_READ_HI - INSN_READ_LO - INSN_WRITE_HI - INSN_WRITE_LO - INSN_TRAP - INSN_ISA3 - */ - -extern const struct mips_opcode mips16_opcodes[]; -extern const int bfd_mips16_num_opcodes; - -#endif /* _MIPS_H_ */ diff --git a/contrib/binutils/include/opcode/np1.h b/contrib/binutils/include/opcode/np1.h deleted file mode 100644 index c3f7e29..0000000 --- a/contrib/binutils/include/opcode/np1.h +++ /dev/null @@ -1,422 +0,0 @@ -/* Print GOULD NPL instructions for GDB, the GNU debugger. - Copyright 1986, 1987, 1989, 1991 Free Software Foundation, Inc. - -This file is part of GDB. - -GDB is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 1, or (at your option) -any later version. - -GDB is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GDB; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -struct gld_opcode -{ - char *name; - unsigned long opcode; - unsigned long mask; - char *args; - int length; -}; - -/* We store four bytes of opcode for all opcodes because that - is the most any of them need. The actual length of an instruction - is always at least 2 bytes, and at most four. The length of the - instruction is based on the opcode. - - The mask component is a mask saying which bits must match - particular opcode in order for an instruction to be an instance - of that opcode. - - The args component is a string containing characters - that are used to format the arguments to the instruction. */ - -/* Kinds of operands: - r Register in first field - R Register in second field - b Base register in first field - B Base register in second field - v Vector register in first field - V Vector register in first field - A Optional address register (base register) - X Optional index register - I Immediate data (16bits signed) - O Offset field (16bits signed) - h Offset field (15bits signed) - d Offset field (14bits signed) - S Shift count field - - any other characters are printed as is... -*/ - -/* The assembler requires that this array be sorted as follows: - all instances of the same mnemonic must be consecutive. - All instances of the same mnemonic with the same number of operands - must be consecutive. - */ -struct gld_opcode gld_opcodes[] = -{ -{ "lb", 0xb4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lnb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lbs", 0xec080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lh", 0xb4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "lnh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "lw", 0xb4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lnw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "ld", 0xb4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "lnd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "li", 0xf8000000, 0xfc7f0000, "r,I", 4 }, -{ "lpa", 0x50080000, 0xfc080000, "r,xOA,X", 4 }, -{ "la", 0x50000000, 0xfc080000, "r,xOA,X", 4 }, -{ "labr", 0x58080000, 0xfc080000, "b,xOA,X", 4 }, -{ "lbp", 0x90080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lhp", 0x90000001, 0xfc080001, "r,xOA,X", 4 }, -{ "lwp", 0x90000000, 0xfc080000, "r,xOA,X", 4 }, -{ "ldp", 0x90000002, 0xfc080002, "r,xOA,X", 4 }, -{ "suabr", 0x58000000, 0xfc080000, "b,xOA,X", 4 }, -{ "lf", 0xbc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lfbr", 0xbc080000, 0xfc080000, "b,xOA,X", 4 }, -{ "lwbr", 0x5c000000, 0xfc080000, "b,xOA,X", 4 }, -{ "stb", 0xd4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "sth", 0xd4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "stw", 0xd4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "std", 0xd4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "stf", 0xdc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "stfbr", 0xdc080000, 0xfc080000, "b,xOA,X", 4 }, -{ "stwbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 }, -{ "zmb", 0xd8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "zmh", 0xd8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "zmw", 0xd8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "zmd", 0xd8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "stbp", 0x94080000, 0xfc080000, "r,xOA,X", 4 }, -{ "sthp", 0x94000001, 0xfc080001, "r,xOA,X", 4 }, -{ "stwp", 0x94000000, 0xfc080000, "r,xOA,X", 4 }, -{ "stdp", 0x94000002, 0xfc080002, "r,xOA,X", 4 }, -{ "lil", 0xf80b0000, 0xfc7f0000, "r,D", 4 }, -{ "lwsl1", 0xec000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lwsl2", 0xfc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lwsl3", 0xfc080000, 0xfc080000, "r,xOA,X", 4 }, - -{ "lvb", 0xb0080000, 0xfc080000, "v,xOA,X", 4 }, -{ "lvh", 0xb0000001, 0xfc080001, "v,xOA,X", 4 }, -{ "lvw", 0xb0000000, 0xfc080000, "v,xOA,X", 4 }, -{ "lvd", 0xb0000002, 0xfc080002, "v,xOA,X", 4 }, -{ "liv", 0x3c040000, 0xfc0f0000, "v,R", 2 }, -{ "livf", 0x3c080000, 0xfc0f0000, "v,R", 2 }, -{ "stvb", 0xd0080000, 0xfc080000, "v,xOA,X", 4 }, -{ "stvh", 0xd0000001, 0xfc080001, "v,xOA,X", 4 }, -{ "stvw", 0xd0000000, 0xfc080000, "v,xOA,X", 4 }, -{ "stvd", 0xd0000002, 0xfc080002, "v,xOA,X", 4 }, - -{ "trr", 0x2c000000, 0xfc0f0000, "r,R", 2 }, -{ "trn", 0x2c040000, 0xfc0f0000, "r,R", 2 }, -{ "trnd", 0x2c0c0000, 0xfc0f0000, "r,R", 2 }, -{ "trabs", 0x2c010000, 0xfc0f0000, "r,R", 2 }, -{ "trabsd", 0x2c090000, 0xfc0f0000, "r,R", 2 }, -{ "trc", 0x2c030000, 0xfc0f0000, "r,R", 2 }, -{ "xcr", 0x28040000, 0xfc0f0000, "r,R", 2 }, -{ "cxcr", 0x2c060000, 0xfc0f0000, "r,R", 2 }, -{ "cxcrd", 0x2c0e0000, 0xfc0f0000, "r,R", 2 }, -{ "tbrr", 0x2c020000, 0xfc0f0000, "r,B", 2 }, -{ "trbr", 0x28030000, 0xfc0f0000, "b,R", 2 }, -{ "xcbr", 0x28020000, 0xfc0f0000, "b,B", 2 }, -{ "tbrbr", 0x28010000, 0xfc0f0000, "b,B", 2 }, - -{ "trvv", 0x28050000, 0xfc0f0000, "v,V", 2 }, -{ "trvvn", 0x2c050000, 0xfc0f0000, "v,V", 2 }, -{ "trvvnd", 0x2c0d0000, 0xfc0f0000, "v,V", 2 }, -{ "trvab", 0x2c070000, 0xfc0f0000, "v,V", 2 }, -{ "trvabd", 0x2c0f0000, 0xfc0f0000, "v,V", 2 }, -{ "cmpv", 0x14060000, 0xfc0f0000, "v,V", 2 }, -{ "expv", 0x14070000, 0xfc0f0000, "v,V", 2 }, -{ "mrvvlt", 0x10030000, 0xfc0f0000, "v,V", 2 }, -{ "mrvvle", 0x10040000, 0xfc0f0000, "v,V", 2 }, -{ "mrvvgt", 0x14030000, 0xfc0f0000, "v,V", 2 }, -{ "mrvvge", 0x14040000, 0xfc0f0000, "v,V", 2 }, -{ "mrvveq", 0x10050000, 0xfc0f0000, "v,V", 2 }, -{ "mrvvne", 0x10050000, 0xfc0f0000, "v,V", 2 }, -{ "mrvrlt", 0x100d0000, 0xfc0f0000, "v,R", 2 }, -{ "mrvrle", 0x100e0000, 0xfc0f0000, "v,R", 2 }, -{ "mrvrgt", 0x140d0000, 0xfc0f0000, "v,R", 2 }, -{ "mrvrge", 0x140e0000, 0xfc0f0000, "v,R", 2 }, -{ "mrvreq", 0x100f0000, 0xfc0f0000, "v,R", 2 }, -{ "mrvrne", 0x140f0000, 0xfc0f0000, "v,R", 2 }, -{ "trvr", 0x140b0000, 0xfc0f0000, "r,V", 2 }, -{ "trrv", 0x140c0000, 0xfc0f0000, "v,R", 2 }, - -{ "bu", 0x40000000, 0xff880000, "xOA,X", 4 }, -{ "bns", 0x70080000, 0xff880000, "xOA,X", 4 }, -{ "bnco", 0x70880000, 0xff880000, "xOA,X", 4 }, -{ "bge", 0x71080000, 0xff880000, "xOA,X", 4 }, -{ "bne", 0x71880000, 0xff880000, "xOA,X", 4 }, -{ "bunge", 0x72080000, 0xff880000, "xOA,X", 4 }, -{ "bunle", 0x72880000, 0xff880000, "xOA,X", 4 }, -{ "bgt", 0x73080000, 0xff880000, "xOA,X", 4 }, -{ "bnany", 0x73880000, 0xff880000, "xOA,X", 4 }, -{ "bs" , 0x70000000, 0xff880000, "xOA,X", 4 }, -{ "bco", 0x70800000, 0xff880000, "xOA,X", 4 }, -{ "blt", 0x71000000, 0xff880000, "xOA,X", 4 }, -{ "beq", 0x71800000, 0xff880000, "xOA,X", 4 }, -{ "buge", 0x72000000, 0xff880000, "xOA,X", 4 }, -{ "bult", 0x72800000, 0xff880000, "xOA,X", 4 }, -{ "ble", 0x73000000, 0xff880000, "xOA,X", 4 }, -{ "bany", 0x73800000, 0xff880000, "xOA,X", 4 }, -{ "brlnk", 0x44000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bib", 0x48000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bih", 0x48080000, 0xfc080000, "r,xOA,X", 4 }, -{ "biw", 0x4c000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bid", 0x4c080000, 0xfc080000, "r,xOA,X", 4 }, -{ "bivb", 0x60000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bivh", 0x60080000, 0xfc080000, "r,xOA,X", 4 }, -{ "bivw", 0x64000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bivd", 0x64080000, 0xfc080000, "r,xOA,X", 4 }, -{ "bvsb", 0x68000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bvsh", 0x68080000, 0xfc080000, "r,xOA,X", 4 }, -{ "bvsw", 0x6c000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bvsd", 0x6c080000, 0xfc080000, "r,xOA,X", 4 }, - -{ "camb", 0x80080000, 0xfc080000, "r,xOA,X", 4 }, -{ "camh", 0x80000001, 0xfc080001, "r,xOA,X", 4 }, -{ "camw", 0x80000000, 0xfc080000, "r,xOA,X", 4 }, -{ "camd", 0x80000002, 0xfc080002, "r,xOA,X", 4 }, -{ "car", 0x10000000, 0xfc0f0000, "r,R", 2 }, -{ "card", 0x14000000, 0xfc0f0000, "r,R", 2 }, -{ "ci", 0xf8050000, 0xfc7f0000, "r,I", 4 }, -{ "chkbnd", 0x5c080000, 0xfc080000, "r,xOA,X", 4 }, - -{ "cavv", 0x10010000, 0xfc0f0000, "v,V", 2 }, -{ "cavr", 0x10020000, 0xfc0f0000, "v,R", 2 }, -{ "cavvd", 0x10090000, 0xfc0f0000, "v,V", 2 }, -{ "cavrd", 0x100b0000, 0xfc0f0000, "v,R", 2 }, - -{ "anmb", 0x84080000, 0xfc080000, "r,xOA,X", 4 }, -{ "anmh", 0x84000001, 0xfc080001, "r,xOA,X", 4 }, -{ "anmw", 0x84000000, 0xfc080000, "r,xOA,X", 4 }, -{ "anmd", 0x84000002, 0xfc080002, "r,xOA,X", 4 }, -{ "anr", 0x04000000, 0xfc0f0000, "r,R", 2 }, -{ "ani", 0xf8080000, 0xfc7f0000, "r,I", 4 }, -{ "ormb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "ormh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "ormw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "ormd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "orr", 0x08000000, 0xfc0f0000, "r,R", 2 }, -{ "oi", 0xf8090000, 0xfc7f0000, "r,I", 4 }, -{ "eomb", 0x8c080000, 0xfc080000, "r,xOA,X", 4 }, -{ "eomh", 0x8c000001, 0xfc080001, "r,xOA,X", 4 }, -{ "eomw", 0x8c000000, 0xfc080000, "r,xOA,X", 4 }, -{ "eomd", 0x8c000002, 0xfc080002, "r,xOA,X", 4 }, -{ "eor", 0x0c000000, 0xfc0f0000, "r,R", 2 }, -{ "eoi", 0xf80a0000, 0xfc7f0000, "r,I", 4 }, - -{ "anvv", 0x04010000, 0xfc0f0000, "v,V", 2 }, -{ "anvr", 0x04020000, 0xfc0f0000, "v,R", 2 }, -{ "orvv", 0x08010000, 0xfc0f0000, "v,V", 2 }, -{ "orvr", 0x08020000, 0xfc0f0000, "v,R", 2 }, -{ "eovv", 0x0c010000, 0xfc0f0000, "v,V", 2 }, -{ "eovr", 0x0c020000, 0xfc0f0000, "v,R", 2 }, - -{ "sacz", 0x100c0000, 0xfc0f0000, "r,R", 2 }, -{ "sla", 0x1c400000, 0xfc600000, "r,S", 2 }, -{ "sll", 0x1c600000, 0xfc600000, "r,S", 2 }, -{ "slc", 0x24400000, 0xfc600000, "r,S", 2 }, -{ "slad", 0x20400000, 0xfc600000, "r,S", 2 }, -{ "slld", 0x20600000, 0xfc600000, "r,S", 2 }, -{ "sra", 0x1c000000, 0xfc600000, "r,S", 2 }, -{ "srl", 0x1c200000, 0xfc600000, "r,S", 2 }, -{ "src", 0x24000000, 0xfc600000, "r,S", 2 }, -{ "srad", 0x20000000, 0xfc600000, "r,S", 2 }, -{ "srld", 0x20200000, 0xfc600000, "r,S", 2 }, -{ "sda", 0x3c030000, 0xfc0f0000, "r,R", 2 }, -{ "sdl", 0x3c020000, 0xfc0f0000, "r,R", 2 }, -{ "sdc", 0x3c010000, 0xfc0f0000, "r,R", 2 }, -{ "sdad", 0x3c0b0000, 0xfc0f0000, "r,R", 2 }, -{ "sdld", 0x3c0a0000, 0xfc0f0000, "r,R", 2 }, - -{ "svda", 0x3c070000, 0xfc0f0000, "v,R", 2 }, -{ "svdl", 0x3c060000, 0xfc0f0000, "v,R", 2 }, -{ "svdc", 0x3c050000, 0xfc0f0000, "v,R", 2 }, -{ "svdad", 0x3c0e0000, 0xfc0f0000, "v,R", 2 }, -{ "svdld", 0x3c0d0000, 0xfc0f0000, "v,R", 2 }, - -{ "sbm", 0xac080000, 0xfc080000, "f,xOA,X", 4 }, -{ "zbm", 0xac000000, 0xfc080000, "f,xOA,X", 4 }, -{ "tbm", 0xa8080000, 0xfc080000, "f,xOA,X", 4 }, -{ "incmb", 0xa0000000, 0xfc080000, "xOA,X", 4 }, -{ "incmh", 0xa0080000, 0xfc080000, "xOA,X", 4 }, -{ "incmw", 0xa4000000, 0xfc080000, "xOA,X", 4 }, -{ "incmd", 0xa4080000, 0xfc080000, "xOA,X", 4 }, -{ "sbmd", 0x7c080000, 0xfc080000, "r,xOA,X", 4 }, -{ "zbmd", 0x7c000000, 0xfc080000, "r,xOA,X", 4 }, -{ "tbmd", 0x78080000, 0xfc080000, "r,xOA,X", 4 }, - -{ "ssm", 0x9c080000, 0xfc080000, "f,xOA,X", 4 }, -{ "zsm", 0x9c000000, 0xfc080000, "f,xOA,X", 4 }, -{ "tsm", 0x98080000, 0xfc080000, "f,xOA,X", 4 }, - -{ "admb", 0xc8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "admh", 0xc8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "admw", 0xc8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "admd", 0xc8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "adr", 0x38000000, 0xfc0f0000, "r,R", 2 }, -{ "armb", 0xe8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "armh", 0xe8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "armw", 0xe8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "armd", 0xe8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "adi", 0xf8010000, 0xfc0f0000, "r,I", 4 }, -{ "sumb", 0xcc080000, 0xfc080000, "r,xOA,X", 4 }, -{ "sumh", 0xcc000001, 0xfc080001, "r,xOA,X", 4 }, -{ "sumw", 0xcc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "sumd", 0xcc000002, 0xfc080002, "r,xOA,X", 4 }, -{ "sur", 0x3c000000, 0xfc0f0000, "r,R", 2 }, -{ "sui", 0xf8020000, 0xfc0f0000, "r,I", 4 }, -{ "mpmb", 0xc0080000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpmh", 0xc0000001, 0xfc080001, "r,xOA,X", 4 }, -{ "mpmw", 0xc0000000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpr", 0x38020000, 0xfc0f0000, "r,R", 2 }, -{ "mprd", 0x3c0f0000, 0xfc0f0000, "r,R", 2 }, -{ "mpi", 0xf8030000, 0xfc0f0000, "r,I", 4 }, -{ "dvmb", 0xc4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "dvmh", 0xc4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "dvmw", 0xc4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "dvr", 0x380a0000, 0xfc0f0000, "r,R", 2 }, -{ "dvi", 0xf8040000, 0xfc0f0000, "r,I", 4 }, -{ "exs", 0x38080000, 0xfc0f0000, "r,R", 2 }, - -{ "advv", 0x30000000, 0xfc0f0000, "v,V", 2 }, -{ "advvd", 0x30080000, 0xfc0f0000, "v,V", 2 }, -{ "adrv", 0x34000000, 0xfc0f0000, "v,R", 2 }, -{ "adrvd", 0x34080000, 0xfc0f0000, "v,R", 2 }, -{ "suvv", 0x30010000, 0xfc0f0000, "v,V", 2 }, -{ "suvvd", 0x30090000, 0xfc0f0000, "v,V", 2 }, -{ "surv", 0x34010000, 0xfc0f0000, "v,R", 2 }, -{ "survd", 0x34090000, 0xfc0f0000, "v,R", 2 }, -{ "mpvv", 0x30020000, 0xfc0f0000, "v,V", 2 }, -{ "mprv", 0x34020000, 0xfc0f0000, "v,R", 2 }, - -{ "adfw", 0xe0080000, 0xfc080000, "r,xOA,X", 4 }, -{ "adfd", 0xe0080002, 0xfc080002, "r,xOA,X", 4 }, -{ "adrfw", 0x38010000, 0xfc0f0000, "r,R", 2 }, -{ "adrfd", 0x38090000, 0xfc0f0000, "r,R", 2 }, -{ "surfw", 0xe0000000, 0xfc080000, "r,xOA,X", 4 }, -{ "surfd", 0xe0000002, 0xfc080002, "r,xOA,X", 4 }, -{ "surfw", 0x38030000, 0xfc0f0000, "r,R", 2 }, -{ "surfd", 0x380b0000, 0xfc0f0000, "r,R", 2 }, -{ "mpfw", 0xe4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpfd", 0xe4080002, 0xfc080002, "r,xOA,X", 4 }, -{ "mprfw", 0x38060000, 0xfc0f0000, "r,R", 2 }, -{ "mprfd", 0x380e0000, 0xfc0f0000, "r,R", 2 }, -{ "rfw", 0xe4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "rfd", 0xe4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "rrfw", 0x0c0e0000, 0xfc0f0000, "r", 2 }, -{ "rrfd", 0x0c0f0000, 0xfc0f0000, "r", 2 }, - -{ "advvfw", 0x30040000, 0xfc0f0000, "v,V", 2 }, -{ "advvfd", 0x300c0000, 0xfc0f0000, "v,V", 2 }, -{ "adrvfw", 0x34040000, 0xfc0f0000, "v,R", 2 }, -{ "adrvfd", 0x340c0000, 0xfc0f0000, "v,R", 2 }, -{ "suvvfw", 0x30050000, 0xfc0f0000, "v,V", 2 }, -{ "suvvfd", 0x300d0000, 0xfc0f0000, "v,V", 2 }, -{ "survfw", 0x34050000, 0xfc0f0000, "v,R", 2 }, -{ "survfd", 0x340d0000, 0xfc0f0000, "v,R", 2 }, -{ "mpvvfw", 0x30060000, 0xfc0f0000, "v,V", 2 }, -{ "mpvvfd", 0x300e0000, 0xfc0f0000, "v,V", 2 }, -{ "mprvfw", 0x34060000, 0xfc0f0000, "v,R", 2 }, -{ "mprvfd", 0x340e0000, 0xfc0f0000, "v,R", 2 }, -{ "rvfw", 0x30070000, 0xfc0f0000, "v", 2 }, -{ "rvfd", 0x300f0000, 0xfc0f0000, "v", 2 }, - -{ "fltw", 0x38070000, 0xfc0f0000, "r,R", 2 }, -{ "fltd", 0x380f0000, 0xfc0f0000, "r,R", 2 }, -{ "fixw", 0x38050000, 0xfc0f0000, "r,R", 2 }, -{ "fixd", 0x380d0000, 0xfc0f0000, "r,R", 2 }, -{ "cfpds", 0x3c090000, 0xfc0f0000, "r,R", 2 }, - -{ "fltvw", 0x080d0000, 0xfc0f0000, "v,V", 2 }, -{ "fltvd", 0x080f0000, 0xfc0f0000, "v,V", 2 }, -{ "fixvw", 0x080c0000, 0xfc0f0000, "v,V", 2 }, -{ "fixvd", 0x080e0000, 0xfc0f0000, "v,V", 2 }, -{ "cfpvds", 0x0c0d0000, 0xfc0f0000, "v,V", 2 }, - -{ "orvrn", 0x000a0000, 0xfc0f0000, "r,V", 2 }, -{ "andvrn", 0x00080000, 0xfc0f0000, "r,V", 2 }, -{ "frsteq", 0x04090000, 0xfc0f0000, "r,V", 2 }, -{ "sigma", 0x0c080000, 0xfc0f0000, "r,V", 2 }, -{ "sigmad", 0x0c0a0000, 0xfc0f0000, "r,V", 2 }, -{ "sigmf", 0x08080000, 0xfc0f0000, "r,V", 2 }, -{ "sigmfd", 0x080a0000, 0xfc0f0000, "r,V", 2 }, -{ "prodf", 0x04080000, 0xfc0f0000, "r,V", 2 }, -{ "prodfd", 0x040a0000, 0xfc0f0000, "r,V", 2 }, -{ "maxv", 0x10080000, 0xfc0f0000, "r,V", 2 }, -{ "maxvd", 0x100a0000, 0xfc0f0000, "r,V", 2 }, -{ "minv", 0x14080000, 0xfc0f0000, "r,V", 2 }, -{ "minvd", 0x140a0000, 0xfc0f0000, "r,V", 2 }, - -{ "lpsd", 0xf0000000, 0xfc080000, "xOA,X", 4 }, -{ "ldc", 0xf0080000, 0xfc080000, "xOA,X", 4 }, -{ "spm", 0x040c0000, 0xfc0f0000, "r", 2 }, -{ "rpm", 0x040d0000, 0xfc0f0000, "r", 2 }, -{ "tritr", 0x00070000, 0xfc0f0000, "r", 2 }, -{ "trrit", 0x00060000, 0xfc0f0000, "r", 2 }, -{ "rpswt", 0x04080000, 0xfc0f0000, "r", 2 }, -{ "exr", 0xf8070000, 0xfc0f0000, "", 4 }, -{ "halt", 0x00000000, 0xfc0f0000, "", 2 }, -{ "wait", 0x00010000, 0xfc0f0000, "", 2 }, -{ "nop", 0x00020000, 0xfc0f0000, "", 2 }, -{ "eiae", 0x00030000, 0xfc0f0000, "", 2 }, -{ "efae", 0x000d0000, 0xfc0f0000, "", 2 }, -{ "diae", 0x000e0000, 0xfc0f0000, "", 2 }, -{ "dfae", 0x000f0000, 0xfc0f0000, "", 2 }, -{ "spvc", 0xf8060000, 0xfc0f0000, "r,T,N", 4 }, -{ "rdsts", 0x00090000, 0xfc0f0000, "r", 2 }, -{ "setcpu", 0x000c0000, 0xfc0f0000, "r", 2 }, -{ "cmc", 0x000b0000, 0xfc0f0000, "r", 2 }, -{ "trrcu", 0x00040000, 0xfc0f0000, "r", 2 }, -{ "attnio", 0x00050000, 0xfc0f0000, "", 2 }, -{ "fudit", 0x28080000, 0xfc0f0000, "", 2 }, -{ "break", 0x28090000, 0xfc0f0000, "", 2 }, -{ "frzss", 0x280a0000, 0xfc0f0000, "", 2 }, -{ "ripi", 0x04040000, 0xfc0f0000, "r,R", 2 }, -{ "xcp", 0x04050000, 0xfc0f0000, "r", 2 }, -{ "block", 0x04060000, 0xfc0f0000, "", 2 }, -{ "unblock", 0x04070000, 0xfc0f0000, "", 2 }, -{ "trsc", 0x08060000, 0xfc0f0000, "r,R", 2 }, -{ "tscr", 0x08070000, 0xfc0f0000, "r,R", 2 }, -{ "fq", 0x04080000, 0xfc0f0000, "r", 2 }, -{ "flupte", 0x2c080000, 0xfc0f0000, "r", 2 }, -{ "rviu", 0x040f0000, 0xfc0f0000, "", 2 }, -{ "ldel", 0x280c0000, 0xfc0f0000, "r,R", 2 }, -{ "ldu", 0x280d0000, 0xfc0f0000, "r,R", 2 }, -{ "stdecc", 0x280b0000, 0xfc0f0000, "r,R", 2 }, -{ "trpc", 0x08040000, 0xfc0f0000, "r", 2 }, -{ "tpcr", 0x08050000, 0xfc0f0000, "r", 2 }, -{ "ghalt", 0x0c050000, 0xfc0f0000, "r", 2 }, -{ "grun", 0x0c040000, 0xfc0f0000, "", 2 }, -{ "tmpr", 0x2c0a0000, 0xfc0f0000, "r,R", 2 }, -{ "trmp", 0x2c0b0000, 0xfc0f0000, "r,R", 2 }, - -{ "trrve", 0x28060000, 0xfc0f0000, "r", 2 }, -{ "trver", 0x28070000, 0xfc0f0000, "r", 2 }, -{ "trvlr", 0x280f0000, 0xfc0f0000, "r", 2 }, - -{ "linkfl", 0x18000000, 0xfc0f0000, "r,R", 2 }, -{ "linkbl", 0x18020000, 0xfc0f0000, "r,R", 2 }, -{ "linkfp", 0x18010000, 0xfc0f0000, "r,R", 2 }, -{ "linkbp", 0x18030000, 0xfc0f0000, "r,R", 2 }, -{ "linkpl", 0x18040000, 0xfc0f0000, "r,R", 2 }, -{ "ulinkl", 0x18080000, 0xfc0f0000, "r,R", 2 }, -{ "ulinkp", 0x18090000, 0xfc0f0000, "r,R", 2 }, -{ "ulinktl", 0x180a0000, 0xfc0f0000, "r,R", 2 }, -{ "ulinktp", 0x180b0000, 0xfc0f0000, "r,R", 2 }, -}; - -int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]); - -struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) / - sizeof(gld_opcodes[0]); diff --git a/contrib/binutils/include/opcode/pn.h b/contrib/binutils/include/opcode/pn.h deleted file mode 100644 index 8c427a2..0000000 --- a/contrib/binutils/include/opcode/pn.h +++ /dev/null @@ -1,282 +0,0 @@ -/* Print GOULD PN (PowerNode) instructions for GDB, the GNU debugger. - Copyright 1986, 1987, 1989, 1991 Free Software Foundation, Inc. - -This file is part of GDB. - -GDB is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 1, or (at your option) -any later version. - -GDB is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GDB; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -struct gld_opcode -{ - char *name; - unsigned long opcode; - unsigned long mask; - char *args; - int length; -}; - -/* We store four bytes of opcode for all opcodes because that - is the most any of them need. The actual length of an instruction - is always at least 2 bytes, and at most four. The length of the - instruction is based on the opcode. - - The mask component is a mask saying which bits must match - particular opcode in order for an instruction to be an instance - of that opcode. - - The args component is a string containing characters - that are used to format the arguments to the instruction. */ - -/* Kinds of operands: - r Register in first field - R Register in second field - b Base register in first field - B Base register in second field - v Vector register in first field - V Vector register in first field - A Optional address register (base register) - X Optional index register - I Immediate data (16bits signed) - O Offset field (16bits signed) - h Offset field (15bits signed) - d Offset field (14bits signed) - S Shift count field - - any other characters are printed as is... -*/ - -/* The assembler requires that this array be sorted as follows: - all instances of the same mnemonic must be consecutive. - All instances of the same mnemonic with the same number of operands - must be consecutive. - */ -struct gld_opcode gld_opcodes[] = -{ -{ "abm", 0xa0080000, 0xfc080000, "f,xOA,X", 4 }, -{ "abr", 0x18080000, 0xfc0c0000, "r,f", 2 }, -{ "aci", 0xfc770000, 0xfc7f8000, "r,I", 4 }, -{ "adfd", 0xe0080002, 0xfc080002, "r,xOA,X", 4 }, -{ "adfw", 0xe0080000, 0xfc080000, "r,xOA,X", 4 }, -{ "adi", 0xc8010000, 0xfc7f0000, "r,I", 4 }, -{ "admb", 0xb8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "admd", 0xb8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "admh", 0xb8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "admw", 0xb8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "adr", 0x38000000, 0xfc0f0000, "r,R", 2 }, -{ "adrfd", 0x38090000, 0xfc0f0000, "r,R", 2 }, -{ "adrfw", 0x38010000, 0xfc0f0000, "r,R", 2 }, -{ "adrm", 0x38080000, 0xfc0f0000, "r,R", 2 }, -{ "ai", 0xfc030000, 0xfc07ffff, "I", 4 }, -{ "anmb", 0x84080000, 0xfc080000, "r,xOA,X", 4 }, -{ "anmd", 0x84000002, 0xfc080002, "r,xOA,X", 4 }, -{ "anmh", 0x84000001, 0xfc080001, "r,xOA,X", 4 }, -{ "anmw", 0x84000000, 0xfc080000, "r,xOA,X", 4 }, -{ "anr", 0x04000000, 0xfc0f0000, "r,R", 2 }, -{ "armb", 0xe8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "armd", 0xe8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "armh", 0xe8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "armw", 0xe8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "bcf", 0xf0000000, 0xfc080000, "I,xOA,X", 4 }, -{ "bct", 0xec000000, 0xfc080000, "I,xOA,X", 4 }, -{ "bei", 0x00060000, 0xffff0000, "", 2 }, -{ "bft", 0xf0000000, 0xff880000, "xOA,X", 4 }, -{ "bib", 0xf4000000, 0xfc780000, "r,xOA", 4 }, -{ "bid", 0xf4600000, 0xfc780000, "r,xOA", 4 }, -{ "bih", 0xf4200000, 0xfc780000, "r,xOA", 4 }, -{ "biw", 0xf4400000, 0xfc780000, "r,xOA", 4 }, -{ "bl", 0xf8800000, 0xff880000, "xOA,X", 4 }, -{ "bsub", 0x5c080000, 0xff8f0000, "", 2 }, -{ "bsubm", 0x28080000, 0xfc080000, "", 4 }, -{ "bu", 0xec000000, 0xff880000, "xOA,X", 4 }, -{ "call", 0x28080000, 0xfc0f0000, "", 2 }, -{ "callm", 0x5c080000, 0xff880000, "", 4 }, -{ "camb", 0x90080000, 0xfc080000, "r,xOA,X", 4 }, -{ "camd", 0x90000002, 0xfc080002, "r,xOA,X", 4 }, -{ "camh", 0x90000001, 0xfc080001, "r,xOA,X", 4 }, -{ "camw", 0x90000000, 0xfc080000, "r.xOA,X", 4 }, -{ "car", 0x10000000, 0xfc0f0000, "r,R", 2 }, -{ "cd", 0xfc060000, 0xfc070000, "r,f", 4 }, -{ "cea", 0x000f0000, 0xffff0000, "", 2 }, -{ "ci", 0xc8050000, 0xfc7f0000, "r,I", 4 }, -{ "cmc", 0x040a0000, 0xfc7f0000, "r", 2 }, -{ "cmmb", 0x94080000, 0xfc080000, "r,xOA,X", 4 }, -{ "cmmd", 0x94000002, 0xfc080002, "r,xOA,X", 4 }, -{ "cmmh", 0x94000001, 0xfc080001, "r,xOA,X", 4 }, -{ "cmmw", 0x94000000, 0xfc080000, "r,xOA,X", 4 }, -{ "cmr", 0x14000000, 0xfc0f0000, "r,R", 2 }, -{ "daci", 0xfc7f0000, 0xfc7f8000, "r,I", 4 }, -{ "dae", 0x000e0000, 0xffff0000, "", 2 }, -{ "dai", 0xfc040000, 0xfc07ffff, "I", 4 }, -{ "dci", 0xfc6f0000, 0xfc7f8000, "r,I", 4 }, -{ "di", 0xfc010000, 0xfc07ffff, "I", 4 }, -{ "dvfd", 0xe4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "dvfw", 0xe4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "dvi", 0xc8040000, 0xfc7f0000, "r,I", 4 }, -{ "dvmb", 0xc4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "dvmh", 0xc4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "dvmw", 0xc4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "dvr", 0x380a0000, 0xfc0f0000, "r,R", 2 }, -{ "dvrfd", 0x380c0000, 0xfc0f0000, "r,R", 4 }, -{ "dvrfw", 0x38040000, 0xfc0f0000, "r,xOA,X", 4 }, -{ "eae", 0x00080000, 0xffff0000, "", 2 }, -{ "eci", 0xfc670000, 0xfc7f8080, "r,I", 4 }, -{ "ecwcs", 0xfc4f0000, 0xfc7f8000, "", 4 }, -{ "ei", 0xfc000000, 0xfc07ffff, "I", 4 }, -{ "eomb", 0x8c080000, 0xfc080000, "r,xOA,X", 4 }, -{ "eomd", 0x8c000002, 0xfc080002, "r,xOA,X", 4 }, -{ "eomh", 0x8c000001, 0xfc080001, "r,xOA,X", 4 }, -{ "eomw", 0x8c000000, 0xfc080000, "r,xOA,X", 4 }, -{ "eor", 0x0c000000, 0xfc0f0000, "r,R", 2 }, -{ "eorm", 0x0c080000, 0xfc0f0000, "r,R", 2 }, -{ "es", 0x00040000, 0xfc7f0000, "r", 2 }, -{ "exm", 0xa8000000, 0xff880000, "xOA,X", 4 }, -{ "exr", 0xc8070000, 0xfc7f0000, "r", 2 }, -{ "exrr", 0xc8070002, 0xfc7f0002, "r", 2 }, -{ "fixd", 0x380d0000, 0xfc0f0000, "r,R", 2 }, -{ "fixw", 0x38050000, 0xfc0f0000, "r,R", 2 }, -{ "fltd", 0x380f0000, 0xfc0f0000, "r,R", 2 }, -{ "fltw", 0x38070000, 0xfc0f0000, "r,R", 2 }, -{ "grio", 0xfc3f0000, 0xfc7f8000, "r,I", 4 }, -{ "halt", 0x00000000, 0xffff0000, "", 2 }, -{ "hio", 0xfc370000, 0xfc7f8000, "r,I", 4 }, -{ "jwcs", 0xfa080000, 0xff880000, "xOA,X", 4 }, -{ "la", 0x50000000, 0xfc000000, "r,xOA,X", 4 }, -{ "labr", 0x58080000, 0xfc080000, "b,xOA,X", 4 }, -{ "lb", 0xac080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lcs", 0x00030000, 0xfc7f0000, "r", 2 }, -{ "ld", 0xac000002, 0xfc080002, "r,xOA,X", 4 }, -{ "lear", 0x80000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lf", 0xcc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lfbr", 0xcc080000, 0xfc080000, "b,xOA,X", 4 }, -{ "lh", 0xac000001, 0xfc080001, "r,xOA,X", 4 }, -{ "li", 0xc8000000, 0xfc7f0000, "r,I", 4 }, -{ "lmap", 0x2c070000, 0xfc7f0000, "r", 2 }, -{ "lmb", 0xb0080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lmd", 0xb0000002, 0xfc080002, "r,xOA,X", 4 }, -{ "lmh", 0xb0000001, 0xfc080001, "r,xOA,X", 4 }, -{ "lmw", 0xb0000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lnb", 0xb4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "lnd", 0xb4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "lnh", 0xb4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "lnw", 0xb4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lpsd", 0xf9800000, 0xff880000, "r,xOA,X", 4 }, -{ "lpsdcm", 0xfa800000, 0xff880000, "r,xOA,X", 4 }, -{ "lw", 0xac000000, 0xfc080000, "r,xOA,X", 4 }, -{ "lwbr", 0x5c000000, 0xfc080000, "b,xOA,X", 4 }, -{ "mpfd", 0xe4080002, 0xfc080002, "r,xOA,X", 4 }, -{ "mpfw", 0xe4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpi", 0xc8030000, 0xfc7f0000, "r,I", 4 }, -{ "mpmb", 0xc0080000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpmh", 0xc0000001, 0xfc080001, "r,xOA,X", 4 }, -{ "mpmw", 0xc0000000, 0xfc080000, "r,xOA,X", 4 }, -{ "mpr", 0x38020000, 0xfc0f0000, "r,R", 2 }, -{ "mprfd", 0x380e0000, 0xfc0f0000, "r,R", 2 }, -{ "mprfw", 0x38060000, 0xfc0f0000, "r,R", 2 }, -{ "nop", 0x00020000, 0xffff0000, "", 2 }, -{ "ormb", 0x88080000, 0xfc080000, "r,xOA,X", 4 }, -{ "ormd", 0x88000002, 0xfc080002, "r,xOA,X", 4 }, -{ "ormh", 0x88000001, 0xfc080001, "r,xOA,X", 4 }, -{ "ormw", 0x88000000, 0xfc080000, "r,xOA,X", 4 }, -{ "orr", 0x08000000, 0xfc0f0000, "r,R", 2 }, -{ "orrm", 0x08080000, 0xfc0f0000, "r,R", 2 }, -{ "rdsts", 0x00090000, 0xfc7f0000, "r", 2 }, -{ "return", 0x280e0000, 0xfc7f0000, "", 2 }, -{ "ri", 0xfc020000, 0xfc07ffff, "I", 4 }, -{ "rnd", 0x00050000, 0xfc7f0000, "r", 2 }, -{ "rpswt", 0x040b0000, 0xfc7f0000, "r", 2 }, -{ "rschnl", 0xfc2f0000, 0xfc7f8000, "r,I", 4 }, -{ "rsctl", 0xfc470000, 0xfc7f8000, "r,I", 4 }, -{ "rwcs", 0x000b0000, 0xfc0f0000, "r,R", 2 }, -{ "sacz", 0x10080000, 0xfc0f0000, "r,R", 2 }, -{ "sbm", 0x98080000, 0xfc080000, "f,xOA,X", 4 }, -{ "sbr", 0x18000000, 0xfc0c0000, "r,f", 4 }, -{ "sea", 0x000d0000, 0xffff0000, "", 2 }, -{ "setcpu", 0x2c090000, 0xfc7f0000, "r", 2 }, -{ "sio", 0xfc170000, 0xfc7f8000, "r,I", 4 }, -{ "sipu", 0x000a0000, 0xffff0000, "", 2 }, -{ "sla", 0x1c400000, 0xfc600000, "r,S", 2 }, -{ "slad", 0x20400000, 0xfc600000, "r,S", 2 }, -{ "slc", 0x24400000, 0xfc600000, "r,S", 2 }, -{ "sll", 0x1c600000, 0xfc600000, "r,S", 2 }, -{ "slld", 0x20600000, 0xfc600000, "r,S", 2 }, -{ "smc", 0x04070000, 0xfc070000, "", 2 }, -{ "sra", 0x1c000000, 0xfc600000, "r,S", 2 }, -{ "srad", 0x20000000, 0xfc600000, "r,S", 2 }, -{ "src", 0x24000000, 0xfc600000, "r,S", 2 }, -{ "srl", 0x1c200000, 0xfc600000, "r,S", 2 }, -{ "srld", 0x20200000, 0xfc600000, "r,S", 2 }, -{ "stb", 0xd4080000, 0xfc080000, "r,xOA,X", 4 }, -{ "std", 0xd4000002, 0xfc080002, "r,xOA,X", 4 }, -{ "stf", 0xdc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "stfbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 }, -{ "sth", 0xd4000001, 0xfc080001, "r,xOA,X", 4 }, -{ "stmb", 0xd8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "stmd", 0xd8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "stmh", 0xd8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "stmw", 0xd8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "stpio", 0xfc270000, 0xfc7f8000, "r,I", 4 }, -{ "stw", 0xd4000000, 0xfc080000, "r,xOA,X", 4 }, -{ "stwbr", 0x54000000, 0xfc080000, "b,xOA,X", 4 }, -{ "suabr", 0x58000000, 0xfc080000, "b,xOA,X", 4 }, -{ "sufd", 0xe0000002, 0xfc080002, "r,xOA,X", 4 }, -{ "sufw", 0xe0000000, 0xfc080000, "r,xOA,X", 4 }, -{ "sui", 0xc8020000, 0xfc7f0000, "r,I", 4 }, -{ "sumb", 0xbc080000, 0xfc080000, "r,xOA,X", 4 }, -{ "sumd", 0xbc000002, 0xfc080002, "r,xOA,X", 4 }, -{ "sumh", 0xbc000001, 0xfc080001, "r,xOA,X", 4 }, -{ "sumw", 0xbc000000, 0xfc080000, "r,xOA,X", 4 }, -{ "sur", 0x3c000000, 0xfc0f0000, "r,R", 2 }, -{ "surfd", 0x380b0000, 0xfc0f0000, "r,xOA,X", 4 }, -{ "surfw", 0x38030000, 0xfc0f0000, "r,R", 2 }, -{ "surm", 0x3c080000, 0xfc0f0000, "r,R", 2 }, -{ "svc", 0xc8060000, 0xffff0000, "", 4 }, -{ "tbm", 0xa4080000, 0xfc080000, "f,xOA,X", 4 }, -{ "tbr", 0x180c0000, 0xfc0c0000, "r,f", 2 }, -{ "tbrr", 0x2c020000, 0xfc0f0000, "r,B", 2 }, -{ "tccr", 0x28040000, 0xfc7f0000, "", 2 }, -{ "td", 0xfc050000, 0xfc070000, "r,f", 4 }, -{ "tio", 0xfc1f0000, 0xfc7f8000, "r,I", 4 }, -{ "tmapr", 0x2c0a0000, 0xfc0f0000, "r,R", 2 }, -{ "tpcbr", 0x280c0000, 0xfc7f0000, "r", 2 }, -{ "trbr", 0x2c010000, 0xfc0f0000, "b,R", 2 }, -{ "trc", 0x2c030000, 0xfc0f0000, "r,R", 2 }, -{ "trcc", 0x28050000, 0xfc7f0000, "", 2 }, -{ "trcm", 0x2c0b0000, 0xfc0f0000, "r,R", 2 }, -{ "trn", 0x2c040000, 0xfc0f0000, "r,R", 2 }, -{ "trnm", 0x2c0c0000, 0xfc0f0000, "r,R", 2 }, -{ "trr", 0x2c000000, 0xfc0f0000, "r,R", 2 }, -{ "trrm", 0x2c080000, 0xfc0f0000, "r,R", 2 }, -{ "trsc", 0x2c0e0000, 0xfc0f0000, "r,R", 2 }, -{ "trsw", 0x28000000, 0xfc7f0000, "r", 2 }, -{ "tscr", 0x2c0f0000, 0xfc0f0000, "r,R", 2 }, -{ "uei", 0x00070000, 0xffff0000, "", 2 }, -{ "wait", 0x00010000, 0xffff0000, "", 2 }, -{ "wcwcs", 0xfc5f0000, 0xfc7f8000, "", 4 }, -{ "wwcs", 0x000c0000, 0xfc0f0000, "r,R", 2 }, -{ "xcbr", 0x28020000, 0xfc0f0000, "b,B", 2 }, -{ "xcr", 0x2c050000, 0xfc0f0000, "r,R", 2 }, -{ "xcrm", 0x2c0d0000, 0xfc0f0000, "r,R", 2 }, -{ "zbm", 0x9c080000, 0xfc080000, "f,xOA,X", 4 }, -{ "zbr", 0x18040000, 0xfc0c0000, "r,f", 2 }, -{ "zmb", 0xf8080000, 0xfc080000, "r,xOA,X", 4 }, -{ "zmd", 0xf8000002, 0xfc080002, "r,xOA,X", 4 }, -{ "zmh", 0xf8000001, 0xfc080001, "r,xOA,X", 4 }, -{ "zmw", 0xf8000000, 0xfc080000, "r,xOA,X", 4 }, -{ "zr", 0x0c000000, 0xfc0f0000, "r", 2 }, -}; - -int numopcodes = sizeof(gld_opcodes) / sizeof(gld_opcodes[0]); - -struct gld_opcode *endop = gld_opcodes + sizeof(gld_opcodes) / - sizeof(gld_opcodes[0]); diff --git a/contrib/binutils/include/opcode/tic30.h b/contrib/binutils/include/opcode/tic30.h deleted file mode 100644 index a700275..0000000 --- a/contrib/binutils/include/opcode/tic30.h +++ /dev/null @@ -1,691 +0,0 @@ -/* tic30.h -- Header file for TI TMS320C30 opcode table - Copyright 1998 Free Software Foundation, Inc. - Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA -02111-1307, USA. */ - -/* FIXME: The opcode table should be in opcodes/tic30-opc.c, not in a - header file. */ - -#ifndef _TMS320_H_ -#define _TMS320_H_ - -struct _register -{ - char *name; - unsigned char opcode; - unsigned char regtype; -}; - -typedef struct _register reg; - -#define REG_Rn 0x01 -#define REG_ARn 0x02 -#define REG_DP 0x03 -#define REG_OTHER 0x04 - -static const reg tic30_regtab[] = { - { "r0", 0x00, REG_Rn }, - { "r1", 0x01, REG_Rn }, - { "r2", 0x02, REG_Rn }, - { "r3", 0x03, REG_Rn }, - { "r4", 0x04, REG_Rn }, - { "r5", 0x05, REG_Rn }, - { "r6", 0x06, REG_Rn }, - { "r7", 0x07, REG_Rn }, - { "ar0",0x08, REG_ARn }, - { "ar1",0x09, REG_ARn }, - { "ar2",0x0A, REG_ARn }, - { "ar3",0x0B, REG_ARn }, - { "ar4",0x0C, REG_ARn }, - { "ar5",0x0D, REG_ARn }, - { "ar6",0x0E, REG_ARn }, - { "ar7",0x0F, REG_ARn }, - { "dp", 0x10, REG_DP }, - { "ir0",0x11, REG_OTHER }, - { "ir1",0x12, REG_OTHER }, - { "bk", 0x13, REG_OTHER }, - { "sp", 0x14, REG_OTHER }, - { "st", 0x15, REG_OTHER }, - { "ie", 0x16, REG_OTHER }, - { "if", 0x17, REG_OTHER }, - { "iof",0x18, REG_OTHER }, - { "rs", 0x19, REG_OTHER }, - { "re", 0x1A, REG_OTHER }, - { "rc", 0x1B, REG_OTHER }, - { "R0", 0x00, REG_Rn }, - { "R1", 0x01, REG_Rn }, - { "R2", 0x02, REG_Rn }, - { "R3", 0x03, REG_Rn }, - { "R4", 0x04, REG_Rn }, - { "R5", 0x05, REG_Rn }, - { "R6", 0x06, REG_Rn }, - { "R7", 0x07, REG_Rn }, - { "AR0",0x08, REG_ARn }, - { "AR1",0x09, REG_ARn }, - { "AR2",0x0A, REG_ARn }, - { "AR3",0x0B, REG_ARn }, - { "AR4",0x0C, REG_ARn }, - { "AR5",0x0D, REG_ARn }, - { "AR6",0x0E, REG_ARn }, - { "AR7",0x0F, REG_ARn }, - { "DP", 0x10, REG_DP }, - { "IR0",0x11, REG_OTHER }, - { "IR1",0x12, REG_OTHER }, - { "BK", 0x13, REG_OTHER }, - { "SP", 0x14, REG_OTHER }, - { "ST", 0x15, REG_OTHER }, - { "IE", 0x16, REG_OTHER }, - { "IF", 0x17, REG_OTHER }, - { "IOF",0x18, REG_OTHER }, - { "RS", 0x19, REG_OTHER }, - { "RE", 0x1A, REG_OTHER }, - { "RC", 0x1B, REG_OTHER }, - { "", 0, 0 } -}; - -static const reg *const tic30_regtab_end - = tic30_regtab + sizeof(tic30_regtab)/sizeof(tic30_regtab[0]); - -/* Indirect Addressing Modes Modification Fields */ -/* Indirect Addressing with Displacement */ -#define PreDisp_Add 0x00 -#define PreDisp_Sub 0x01 -#define PreDisp_Add_Mod 0x02 -#define PreDisp_Sub_Mod 0x03 -#define PostDisp_Add_Mod 0x04 -#define PostDisp_Sub_Mod 0x05 -#define PostDisp_Add_Circ 0x06 -#define PostDisp_Sub_Circ 0x07 -/* Indirect Addressing with Index Register IR0 */ -#define PreIR0_Add 0x08 -#define PreIR0_Sub 0x09 -#define PreIR0_Add_Mod 0x0A -#define PreIR0_Sub_Mod 0x0B -#define PostIR0_Add_Mod 0x0C -#define PostIR0_Sub_Mod 0x0D -#define PostIR0_Add_Circ 0x0E -#define PostIR0_Sub_Circ 0x0F -/* Indirect Addressing with Index Register IR1 */ -#define PreIR1_Add 0x10 -#define PreIR1_Sub 0x11 -#define PreIR1_Add_Mod 0x12 -#define PreIR1_Sub_Mod 0x13 -#define PostIR1_Add_Mod 0x14 -#define PostIR1_Sub_Mod 0x15 -#define PostIR1_Add_Circ 0x16 -#define PostIR1_Sub_Circ 0x17 -/* Indirect Addressing (Special Cases) */ -#define IndirectOnly 0x18 -#define PostIR0_Add_BitRev 0x19 - -typedef struct { - char *syntax; - unsigned char modfield; - unsigned char displacement; -} ind_addr_type; - -#define IMPLIED_DISP 0x01 -#define DISP_REQUIRED 0x02 -#define NO_DISP 0x03 - -static const ind_addr_type tic30_indaddr_tab[] = { - { "*+ar", PreDisp_Add, IMPLIED_DISP }, - { "*-ar", PreDisp_Sub, IMPLIED_DISP }, - { "*++ar", PreDisp_Add_Mod, IMPLIED_DISP }, - { "*--ar", PreDisp_Sub_Mod, IMPLIED_DISP }, - { "*ar++", PostDisp_Add_Mod, IMPLIED_DISP }, - { "*ar--", PostDisp_Sub_Mod, IMPLIED_DISP }, - { "*ar++%", PostDisp_Add_Circ, IMPLIED_DISP }, - { "*ar--%", PostDisp_Sub_Circ, IMPLIED_DISP }, - { "*+ar()", PreDisp_Add, DISP_REQUIRED }, - { "*-ar()", PreDisp_Sub, DISP_REQUIRED }, - { "*++ar()", PreDisp_Add_Mod, DISP_REQUIRED }, - { "*--ar()", PreDisp_Sub_Mod, DISP_REQUIRED }, - { "*ar++()", PostDisp_Add_Mod, DISP_REQUIRED }, - { "*ar--()", PostDisp_Sub_Mod, DISP_REQUIRED }, - { "*ar++()%", PostDisp_Add_Circ, DISP_REQUIRED }, - { "*ar--()%", PostDisp_Sub_Circ, DISP_REQUIRED }, - { "*+ar(ir0)", PreIR0_Add, NO_DISP }, - { "*-ar(ir0)", PreIR0_Sub, NO_DISP }, - { "*++ar(ir0)", PreIR0_Add_Mod, NO_DISP }, - { "*--ar(ir0)", PreIR0_Sub_Mod, NO_DISP }, - { "*ar++(ir0)", PostIR0_Add_Mod, NO_DISP }, - { "*ar--(ir0)", PostIR0_Sub_Mod, NO_DISP }, - { "*ar++(ir0)%",PostIR0_Add_Circ, NO_DISP }, - { "*ar--(ir0)%",PostIR0_Sub_Circ, NO_DISP }, - { "*+ar(ir1)", PreIR1_Add, NO_DISP }, - { "*-ar(ir1)", PreIR1_Sub, NO_DISP }, - { "*++ar(ir1)", PreIR1_Add_Mod, NO_DISP }, - { "*--ar(ir1)", PreIR1_Sub_Mod, NO_DISP }, - { "*ar++(ir1)", PostIR1_Add_Mod, NO_DISP }, - { "*ar--(ir1)", PostIR1_Sub_Mod, NO_DISP }, - { "*ar++(ir1)%",PostIR1_Add_Circ, NO_DISP }, - { "*ar--(ir1)%",PostIR1_Sub_Circ, NO_DISP }, - { "*ar", IndirectOnly, NO_DISP }, - { "*ar++(ir0)b",PostIR0_Add_BitRev, NO_DISP }, - { "", 0,0 } -}; - -static const ind_addr_type *const tic30_indaddrtab_end - = tic30_indaddr_tab + sizeof(tic30_indaddr_tab)/sizeof(tic30_indaddr_tab[0]); - -/* Possible operand types */ -/* Register types */ -#define Rn 0x0001 -#define ARn 0x0002 -#define DPReg 0x0004 -#define OtherReg 0x0008 -/* Addressing mode types */ -#define Direct 0x0010 -#define Indirect 0x0020 -#define Imm16 0x0040 -#define Disp 0x0080 -#define Imm24 0x0100 -#define Abs24 0x0200 -/* 3 operand addressing mode types */ -#define op3T1 0x0400 -#define op3T2 0x0800 -/* Interrupt vector */ -#define IVector 0x1000 -/* Not required */ -#define NotReq 0x2000 - -#define GAddr1 Rn | Direct | Indirect | Imm16 -#define GAddr2 GAddr1 | AllReg -#define TAddr1 op3T1 | Rn | Indirect -#define TAddr2 op3T2 | Rn | Indirect -#define Reg Rn | ARn -#define AllReg Reg | DPReg | OtherReg - -typedef struct _template -{ - char *name; - unsigned int operands; /* how many operands */ - unsigned int base_opcode; /* base_opcode is the fundamental opcode byte */ - /* the bits in opcode_modifier are used to generate the final opcode from - the base_opcode. These bits also are used to detect alternate forms of - the same instruction */ - unsigned int opcode_modifier; - - /* opcode_modifier bits: */ -#define AddressMode 0x00600000 -#define PCRel 0x02000000 -#define StackOp 0x001F0000 -#define Rotate StackOp - - /* operand_types[i] describes the type of operand i. This is made - by OR'ing together all of the possible type masks. (e.g. - 'operand_types[i] = Reg|Imm' specifies that operand i can be - either a register or an immediate operand */ - unsigned int operand_types[3]; - /* This defines the number type of an immediate argument to an instruction. */ - int imm_arg_type; -#define Imm_None 0 -#define Imm_Float 1 -#define Imm_SInt 2 -#define Imm_UInt 3 -} -template; - -static const template tic30_optab[] = { - { "absf" ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "absi" ,2,0x00800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "addc" ,2,0x01000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "addc3" ,3,0x20000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "addf" ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "addf3" ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, - { "addi" ,2,0x02000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "addi3" ,3,0x21000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "and" ,2,0x02800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "and3" ,3,0x21800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "andn" ,2,0x03000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "andn3" ,3,0x22000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "ash" ,2,0x03800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ash3" ,3,0x22800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bls" ,1,0x68020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bhi" ,1,0x68030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bhs" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "beq" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bne" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blt" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "ble" ,1,0x68080000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bgt" ,1,0x68090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bge" ,1,0x680A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bz" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnz" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bp" ,1,0x68090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bn" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnn" ,1,0x680A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnv" ,1,0x680C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bv" ,1,0x680D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnuf" ,1,0x680E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "buf" ,1,0x680F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnc" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bc" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnlv" ,1,0x68100000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blv" ,1,0x68110000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnluf" ,1,0x68120000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bluf" ,1,0x68130000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bzuf" ,1,0x68140000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bd" ,1,0x68200000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bud" ,1,0x68200000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blod" ,1,0x68210000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blsd" ,1,0x68220000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bhid" ,1,0x68230000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bhsd" ,1,0x68240000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "beqd" ,1,0x68250000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bned" ,1,0x68260000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bltd" ,1,0x68270000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bled" ,1,0x68280000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bgtd" ,1,0x68290000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bged" ,1,0x682A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bzd" ,1,0x68250000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnzd" ,1,0x68260000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bpd" ,1,0x68290000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnd" ,1,0x68270000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnnd" ,1,0x682A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnvd" ,1,0x682C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bvd" ,1,0x682D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnufd" ,1,0x682E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bufd" ,1,0x682F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bncd" ,1,0x68240000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bcd" ,1,0x68210000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnlvd" ,1,0x68300000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blvd" ,1,0x68310000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bnlufd" ,1,0x68320000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "blufd" ,1,0x68330000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "bzufd" ,1,0x68340000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }, - { "br" ,1,0x60000000,0, { Imm24, 0, 0 }, Imm_UInt }, - { "brd" ,1,0x61000000,0, { Imm24, 0, 0 }, Imm_UInt }, - { "call" ,1,0x62000000,0, { Imm24, 0, 0 }, Imm_UInt }, - { "callu" ,1,0x70000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calllo" ,1,0x70010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callls" ,1,0x70020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callhi" ,1,0x70030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callhs" ,1,0x70040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calleq" ,1,0x70050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callne" ,1,0x70060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calllt" ,1,0x70070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callle" ,1,0x70080000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callgt" ,1,0x70090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callge" ,1,0x700A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callz" ,1,0x70050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnz" ,1,0x70060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callp" ,1,0x70090000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calln" ,1,0x70070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnn" ,1,0x700A0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnv" ,1,0x700C0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callv" ,1,0x700D0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnuf",1,0x700E0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calluf" ,1,0x700F0000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnc" ,1,0x70040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callc" ,1,0x70010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnlv",1,0x70100000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "calllv" ,1,0x70110000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callnluf",1,0x70120000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callluf",1,0x70130000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "callzuf",1,0x70140000,PCRel, { AllReg|Disp, 0, 0 }, Imm_UInt }, - { "cmpf" ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "cmpf3" ,2,0x23000000,AddressMode, { TAddr1, TAddr2, 0 }, Imm_None }, - { "cmpi" ,2,0x04800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "cmpi3" ,2,0x23800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None }, - { "db" ,2,0x6C000000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbu" ,2,0x6C000000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblo" ,2,0x6C010000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbls" ,2,0x6C020000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbhi" ,2,0x6C030000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbhs" ,2,0x6C040000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbeq" ,2,0x6C050000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbne" ,2,0x6C060000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblt" ,2,0x6C070000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dble" ,2,0x6C080000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbgt" ,2,0x6C090000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbge" ,2,0x6C0A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbz" ,2,0x6C050000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnz" ,2,0x6C060000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbp" ,2,0x6C090000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbn" ,2,0x6C070000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnn" ,2,0x6C0A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnv" ,2,0x6C0C0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbv" ,2,0x6C0D0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnuf" ,2,0x6C0E0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbuf" ,2,0x6C0F0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnc" ,2,0x6C040000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbc" ,2,0x6C010000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnlv" ,2,0x6C100000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblv" ,2,0x6C110000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnluf" ,2,0x6C120000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbluf" ,2,0x6C130000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbzuf" ,2,0x6C140000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbd" ,2,0x6C200000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbud" ,2,0x6C200000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblod" ,2,0x6C210000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblsd" ,2,0x6C220000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbhid" ,2,0x6C230000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbhsd" ,2,0x6C240000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbeqd" ,2,0x6C250000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbned" ,2,0x6C260000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbltd" ,2,0x6C270000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbled" ,2,0x6C280000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbgtd" ,2,0x6C290000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbged" ,2,0x6C2A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbzd" ,2,0x6C250000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnzd" ,2,0x6C260000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbpd" ,2,0x6C290000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnd" ,2,0x6C270000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnnd" ,2,0x6C2A0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnvd" ,2,0x6C2C0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbvd" ,2,0x6C2D0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnufd" ,2,0x6C2E0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbufd" ,2,0x6C2F0000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbncd" ,2,0x6C240000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbcd" ,2,0x6C210000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnlvd" ,2,0x6C300000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblvd" ,2,0x6C310000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbnlufd",2,0x6C320000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dblufd" ,2,0x6C330000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "dbzufd" ,2,0x6C340000,PCRel, { ARn, AllReg|Disp, 0 }, Imm_None }, - { "fix" ,2,0x05000000,AddressMode, { GAddr1, AllReg, 0 }, Imm_Float }, - { "float" ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt }, - { "iack" ,1,0x1B000000,AddressMode, { Direct|Indirect, 0, 0 }, Imm_None }, - { "idle" ,0,0x06000000,0, { 0, 0, 0 }, Imm_None }, - { "idle2" ,0,0x06000001,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ - { "lde" ,2,0x06800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldf" ,2,0x07000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfu" ,2,0x40000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldflo" ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfls" ,2,0x41000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfhi" ,2,0x41800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfhs" ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfeq" ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfne" ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldflt" ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfle" ,2,0x44000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfgt" ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfge" ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfz" ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnz" ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfp" ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfn" ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnn" ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnv" ,2,0x46000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfv" ,2,0x46800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnuf" ,2,0x47000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfuf" ,2,0x47800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnc" ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfc" ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnlv" ,2,0x48000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldflv" ,2,0x48800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfnluf",2,0x49000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfluf" ,2,0x49800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfzuf" ,2,0x4A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldfi" ,2,0x07800000,AddressMode, { Direct|Indirect, Rn, 0 }, Imm_None }, - { "ldi" ,2,0x08000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldiu" ,2,0x50000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldilo" ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldils" ,2,0x51000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldihi" ,2,0x51800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldihs" ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldieq" ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldine" ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldilt" ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldile" ,2,0x54000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldigt" ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldige" ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldiz" ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinz" ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldip" ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldin" ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinn" ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinv" ,2,0x56000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldiv" ,2,0x56800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinuf" ,2,0x57000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldiuf" ,2,0x57800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinc" ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldic" ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinlv" ,2,0x58000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldilv" ,2,0x58800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldinluf",2,0x59000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldiluf" ,2,0x59800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldizuf" ,2,0x5A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "ldii" ,2,0x08800000,AddressMode, { Direct|Indirect, AllReg, 0 }, Imm_None }, - { "ldm" ,2,0x09000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "ldp" ,2,0x08700000,0, { Abs24|Direct, DPReg|NotReq, 0 }, Imm_UInt }, - { "lopower",0,0x10800001,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ - { "lsh" ,2,0x09800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "lsh3" ,3,0x24000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "maxspeed",0,0x10800000,0, { 0, 0, 0 }, Imm_None }, /* LC31 Only */ - { "mpyf" ,2,0x0A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "mpyf3" ,3,0x24800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, - { "mpyi" ,2,0x0A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "mpyi3" ,3,0x25000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "negb" ,2,0x0B000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "negf" ,2,0x0B800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "negi" ,2,0x0C000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "nop" ,1,0x0C800000,AddressMode, { AllReg|Indirect|NotReq, 0, 0 }, Imm_None }, - { "norm" ,2,0x0D000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, /*Check another source*/ - { "not" ,2,0x0D800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "or" ,2,0x10000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "or3" ,3,0x25800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "pop" ,1,0x0E200000,StackOp, { AllReg, 0, 0 }, Imm_None }, - { "popf" ,1,0x0EA00000,StackOp, { Rn, 0, 0 }, Imm_None }, - { "push" ,1,0x0F200000,StackOp, { AllReg, 0, 0 }, Imm_None }, - { "pushf" ,1,0x0FA00000,StackOp, { Rn, 0, 0 }, Imm_None }, - { "reti" ,0,0x78000000,0, { 0, 0, 0 }, Imm_None }, - { "retiu" ,0,0x78000000,0, { 0, 0, 0 }, Imm_None }, - { "retilo" ,0,0x78010000,0, { 0, 0, 0 }, Imm_None }, - { "retils" ,0,0x78020000,0, { 0, 0, 0 }, Imm_None }, - { "retihi" ,0,0x78030000,0, { 0, 0, 0 }, Imm_None }, - { "retihs" ,0,0x78040000,0, { 0, 0, 0 }, Imm_None }, - { "retieq" ,0,0x78050000,0, { 0, 0, 0 }, Imm_None }, - { "retine" ,0,0x78060000,0, { 0, 0, 0 }, Imm_None }, - { "retilt" ,0,0x78070000,0, { 0, 0, 0 }, Imm_None }, - { "retile" ,0,0x78080000,0, { 0, 0, 0 }, Imm_None }, - { "retigt" ,0,0x78090000,0, { 0, 0, 0 }, Imm_None }, - { "retige" ,0,0x780A0000,0, { 0, 0, 0 }, Imm_None }, - { "retiz" ,0,0x78050000,0, { 0, 0, 0 }, Imm_None }, - { "retinz" ,0,0x78060000,0, { 0, 0, 0 }, Imm_None }, - { "retip" ,0,0x78090000,0, { 0, 0, 0 }, Imm_None }, - { "retin" ,0,0x78070000,0, { 0, 0, 0 }, Imm_None }, - { "retinn" ,0,0x780A0000,0, { 0, 0, 0 }, Imm_None }, - { "retinv" ,0,0x780C0000,0, { 0, 0, 0 }, Imm_None }, - { "retiv" ,0,0x780D0000,0, { 0, 0, 0 }, Imm_None }, - { "retinuf",0,0x780E0000,0, { 0, 0, 0 }, Imm_None }, - { "retiuf" ,0,0x780F0000,0, { 0, 0, 0 }, Imm_None }, - { "retinc" ,0,0x78040000,0, { 0, 0, 0 }, Imm_None }, - { "retic" ,0,0x78010000,0, { 0, 0, 0 }, Imm_None }, - { "retinlv",0,0x78100000,0, { 0, 0, 0 }, Imm_None }, - { "retilv" ,0,0x78110000,0, { 0, 0, 0 }, Imm_None }, - { "retinluf",0,0x78120000,0, { 0, 0, 0 }, Imm_None }, - { "retiluf",0,0x78130000,0, { 0, 0, 0 }, Imm_None }, - { "retizuf",0,0x78140000,0, { 0, 0, 0 }, Imm_None }, - { "rets" ,0,0x78800000,0, { 0, 0, 0 }, Imm_None }, - { "retsu" ,0,0x78800000,0, { 0, 0, 0 }, Imm_None }, - { "retslo" ,0,0x78810000,0, { 0, 0, 0 }, Imm_None }, - { "retsls" ,0,0x78820000,0, { 0, 0, 0 }, Imm_None }, - { "retshi" ,0,0x78830000,0, { 0, 0, 0 }, Imm_None }, - { "retshs" ,0,0x78840000,0, { 0, 0, 0 }, Imm_None }, - { "retseq" ,0,0x78850000,0, { 0, 0, 0 }, Imm_None }, - { "retsne" ,0,0x78860000,0, { 0, 0, 0 }, Imm_None }, - { "retslt" ,0,0x78870000,0, { 0, 0, 0 }, Imm_None }, - { "retsle" ,0,0x78880000,0, { 0, 0, 0 }, Imm_None }, - { "retsgt" ,0,0x78890000,0, { 0, 0, 0 }, Imm_None }, - { "retsge" ,0,0x788A0000,0, { 0, 0, 0 }, Imm_None }, - { "retsz" ,0,0x78850000,0, { 0, 0, 0 }, Imm_None }, - { "retsnz" ,0,0x78860000,0, { 0, 0, 0 }, Imm_None }, - { "retsp" ,0,0x78890000,0, { 0, 0, 0 }, Imm_None }, - { "retsn" ,0,0x78870000,0, { 0, 0, 0 }, Imm_None }, - { "retsnn" ,0,0x788A0000,0, { 0, 0, 0 }, Imm_None }, - { "retsnv" ,0,0x788C0000,0, { 0, 0, 0 }, Imm_None }, - { "retsv" ,0,0x788D0000,0, { 0, 0, 0 }, Imm_None }, - { "retsnuf",0,0x788E0000,0, { 0, 0, 0 }, Imm_None }, - { "retsuf" ,0,0x788F0000,0, { 0, 0, 0 }, Imm_None }, - { "retsnc" ,0,0x78840000,0, { 0, 0, 0 }, Imm_None }, - { "retsc" ,0,0x78810000,0, { 0, 0, 0 }, Imm_None }, - { "retsnlv",0,0x78900000,0, { 0, 0, 0 }, Imm_None }, - { "retslv" ,0,0x78910000,0, { 0, 0, 0 }, Imm_None }, - { "retsnluf",0,0x78920000,0, { 0, 0, 0 }, Imm_None }, - { "retsluf",0,0x78930000,0, { 0, 0, 0 }, Imm_None }, - { "retszuf",0,0x78940000,0, { 0, 0, 0 }, Imm_None }, - { "rnd" ,2,0x11000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "rol" ,1,0x11E00001,Rotate, { AllReg, 0, 0 }, Imm_None }, - { "rolc" ,1,0x12600001,Rotate, { AllReg, 0, 0 }, Imm_None }, - { "ror" ,1,0x12E0FFFF,Rotate, { AllReg, 0, 0 }, Imm_None }, - { "rorc" ,1,0x1360FFFF,Rotate, { AllReg, 0, 0 }, Imm_None }, - { "rptb" ,1,0x64000000,0, { Imm24, 0, 0 }, Imm_UInt }, - { "rpts" ,1,0x139B0000,AddressMode, { GAddr2, 0, 0 }, Imm_UInt }, - { "sigi" ,0,0x16000000,0, { 0, 0, 0 }, Imm_None }, - { "stf" ,2,0x14000000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float }, - { "stfi" ,2,0x14800000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float }, - { "sti" ,2,0x15000000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt }, - { "stii" ,2,0x15800000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt }, - { "subb" ,2,0x16800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "subb3" ,3,0x26000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "subc" ,2,0x17000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "subf" ,2,0x17800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "subf3" ,3,0x26800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None }, - { "subi" ,2,0x18000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "subi3" ,3,0x27000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "subrb" ,2,0x18800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "subrf" ,2,0x19000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, - { "subri" ,2,0x19800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt }, - { "swi" ,0,0x66000000,0, { 0, 0, 0 }, Imm_None }, - { "trap" ,1,0x74800020,0, { IVector, 0, 0 }, Imm_None }, - { "trapu" ,1,0x74800020,0, { IVector, 0, 0 }, Imm_None }, - { "traplo" ,1,0x74810020,0, { IVector, 0, 0 }, Imm_None }, - { "trapls" ,1,0x74820020,0, { IVector, 0, 0 }, Imm_None }, - { "traphi" ,1,0x74830020,0, { IVector, 0, 0 }, Imm_None }, - { "traphs" ,1,0x74840020,0, { IVector, 0, 0 }, Imm_None }, - { "trapeq" ,1,0x74850020,0, { IVector, 0, 0 }, Imm_None }, - { "trapne" ,1,0x74860020,0, { IVector, 0, 0 }, Imm_None }, - { "traplt" ,1,0x74870020,0, { IVector, 0, 0 }, Imm_None }, - { "traple" ,1,0x74880020,0, { IVector, 0, 0 }, Imm_None }, - { "trapgt" ,1,0x74890020,0, { IVector, 0, 0 }, Imm_None }, - { "trapge" ,1,0x748A0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapz" ,1,0x74850020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnz" ,1,0x74860020,0, { IVector, 0, 0 }, Imm_None }, - { "trapp" ,1,0x74890020,0, { IVector, 0, 0 }, Imm_None }, - { "trapn" ,1,0x74870020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnn" ,1,0x748A0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnv" ,1,0x748C0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapv" ,1,0x748D0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnuf",1,0x748E0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapuf" ,1,0x748F0020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnc" ,1,0x74840020,0, { IVector, 0, 0 }, Imm_None }, - { "trapc" ,1,0x74810020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnlv",1,0x74900020,0, { IVector, 0, 0 }, Imm_None }, - { "traplv" ,1,0x74910020,0, { IVector, 0, 0 }, Imm_None }, - { "trapnluf",1,0x74920020,0, { IVector, 0, 0 }, Imm_None }, - { "trapluf",1,0x74930020,0, { IVector, 0, 0 }, Imm_None }, - { "trapzuf",1,0x74940020,0, { IVector, 0, 0 }, Imm_None }, - { "tstb" ,2,0x1A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "tstb3" ,2,0x27800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None }, - { "xor" ,2,0x1A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt }, - { "xor3" ,3,0x28000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None }, - { "" ,0,0x00000000,0, { 0, 0, 0 }, 0 } -}; - -static const template *const tic30_optab_end = - tic30_optab + sizeof(tic30_optab)/sizeof(tic30_optab[0]); - -typedef struct { - char *name; - unsigned int operands_1; - unsigned int operands_2; - unsigned int base_opcode; - unsigned int operand_types[2][3]; - /* Which operand fits into which part of the final opcode word. */ - int oporder; -} partemplate; - -/* oporder defines - not very descriptive. */ -#define OO_4op1 0 -#define OO_4op2 1 -#define OO_4op3 2 -#define OO_5op1 3 -#define OO_5op2 4 -#define OO_PField 5 - -static const partemplate tic30_paroptab[] = { - { "q_absf_stf", 2,2,0xC8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_absi_sti", 2,2,0xCA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_addf3_stf", 3,2,0xCC000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_addi3_sti", 3,2,0xCE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_and3_sti", 3,2,0xD0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_ash3_sti", 3,2,0xD2000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, - OO_5op2 }, - { "q_fix_sti", 2,2,0xD4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_float_stf", 2,2,0xD6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_ldf_ldf", 2,2,0xC4000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } }, - OO_4op2 }, - { "q_ldf_stf", 2,2,0xD8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_ldi_ldi", 2,2,0xC6000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } }, - OO_4op2 }, - { "q_ldi_sti", 2,2,0xDA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_lsh3_sti", 3,2,0xDC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, - OO_5op2 }, - { "q_mpyf3_addf3",3,3,0x80000000, { { Rn | Indirect, Rn | Indirect, Rn }, - { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, - { "q_mpyf3_stf", 3,2,0xDE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_mpyf3_subf3",3,3,0x84000000, { { Rn | Indirect, Rn | Indirect, Rn }, - { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, - { "q_mpyi3_addi3",3,3,0x88000000, { { Rn | Indirect, Rn | Indirect, Rn }, - { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, - { "q_mpyi3_sti", 3,2,0xE0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_mpyi3_subi3",3,3,0x8C000000, { { Rn | Indirect, Rn | Indirect, Rn }, - { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField }, - { "q_negf_stf", 2,2,0xE2000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_negi_sti", 2,2,0xE4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_not_sti", 2,2,0xE6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } }, - OO_4op1 }, - { "q_or3_sti", 3,2,0xE8000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "q_stf_stf", 2,2,0xC0000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } }, - OO_4op3 }, - { "q_sti_sti", 2,2,0xC2000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } }, - OO_4op3 }, - { "q_subf3_stf", 3,2,0xEA000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, - OO_5op2 }, - { "q_subi3_sti", 3,2,0xEC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } }, - OO_5op2 }, - { "q_xor3_sti", 3,2,0xEE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } }, - OO_5op1 }, - { "", 0,0,0x00000000, { { 0, 0, 0 }, { 0, 0, 0 } }, 0 } -}; - -static const partemplate *const tic30_paroptab_end = - tic30_paroptab + sizeof(tic30_paroptab)/sizeof(tic30_paroptab[0]); - -#endif diff --git a/contrib/binutils/include/opcode/v850.h b/contrib/binutils/include/opcode/v850.h deleted file mode 100644 index 2183bc8..0000000 --- a/contrib/binutils/include/opcode/v850.h +++ /dev/null @@ -1,165 +0,0 @@ -/* v850.h -- Header file for NEC V850 opcode table - Copyright 1996, 1997, 2001 Free Software Foundation, Inc. - Written by J.T. Conklin, Cygnus Support - -This file is part of GDB, GAS, and the GNU binutils. - -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -1, or (at your option) any later version. - -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#ifndef V850_H -#define V850_H - -/* The opcode table is an array of struct v850_opcode. */ - -struct v850_opcode -{ - /* The opcode name. */ - const char *name; - - /* The opcode itself. Those bits which will be filled in with - operands are zeroes. */ - unsigned long opcode; - - /* The opcode mask. This is used by the disassembler. This is a - mask containing ones indicating those bits which must match the - opcode field, and zeroes indicating those bits which need not - match (and are presumably filled in by operands). */ - unsigned long mask; - - /* An array of operand codes. Each code is an index into the - operand table. They appear in the order which the operands must - appear in assembly code, and are terminated by a zero. */ - unsigned char operands[8]; - - /* Which (if any) operand is a memory operand. */ - unsigned int memop; - - /* Target processor(s). A bit field of processors which support - this instruction. Note a bit field is used as some instructions - are available on multiple, different processor types, whereas - other instructions are only available on one specific type. */ - unsigned int processors; -}; - -/* Values for the processors field in the v850_opcode structure. */ -#define PROCESSOR_V850 (1 << 0) /* Just the V850. */ -#define PROCESSOR_ALL -1 /* Any processor. */ -#define PROCESSOR_V850E (1 << 1) /* Just the V850E. */ -#define PROCESSOR_NOT_V850 (~ PROCESSOR_V850) /* Any processor except the V850. */ -#define PROCESSOR_V850EA (1 << 2) /* Just the V850EA. */ - -/* The table itself is sorted by major opcode number, and is otherwise - in the order in which the disassembler should consider - instructions. */ -extern const struct v850_opcode v850_opcodes[]; -extern const int v850_num_opcodes; - - -/* The operands table is an array of struct v850_operand. */ - -struct v850_operand -{ - /* The number of bits in the operand. */ - /* If this value is -1 then the operand's bits are in a discontinous distribution in the instruction. */ - int bits; - - /* (bits >= 0): How far the operand is left shifted in the instruction. */ - /* (bits == -1): Bit mask of the bits in the operand. */ - int shift; - - /* Insertion function. This is used by the assembler. To insert an - operand value into an instruction, check this field. - - If it is NULL, execute - i |= (op & ((1 << o->bits) - 1)) << o->shift; - (i is the instruction which we are filling in, o is a pointer to - this structure, and op is the opcode value; this assumes twos - complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction and the operand value. It will return the new value - of the instruction. If the ERRMSG argument is not NULL, then if - the operand value is illegal, *ERRMSG will be set to a warning - string (the operand will be inserted in any case). If the - operand value is legal, *ERRMSG will be unchanged (most operands - can accept any value). */ - unsigned long (* insert) PARAMS ((unsigned long instruction, long op, - const char ** errmsg)); - - /* Extraction function. This is used by the disassembler. To - extract this operand type from an instruction, check this field. - - If it is NULL, compute - op = o->bits == -1 ? ((i) & o->shift) : ((i) >> o->shift) & ((1 << o->bits) - 1); - if (o->flags & V850_OPERAND_SIGNED) - op = (op << (32 - o->bits)) >> (32 - o->bits); - (i is the instruction, o is a pointer to this structure, and op - is the result; this assumes twos complement arithmetic). - - If this field is not NULL, then simply call it with the - instruction value. It will return the value of the operand. If - the INVALID argument is not NULL, *INVALID will be set to - non-zero if this operand type can not actually be extracted from - this operand (i.e., the instruction does not match). If the - operand is valid, *INVALID will not be changed. */ - unsigned long (* extract) PARAMS ((unsigned long instruction, int * invalid)); - - /* One bit syntax flags. */ - int flags; -}; - -/* Elements in the table are retrieved by indexing with values from - the operands field of the v850_opcodes table. */ - -extern const struct v850_operand v850_operands[]; - -/* Values defined for the flags field of a struct v850_operand. */ - -/* This operand names a general purpose register */ -#define V850_OPERAND_REG 0x01 - -/* This operand names a system register */ -#define V850_OPERAND_SRG 0x02 - -/* This operand names a condition code used in the setf instruction */ -#define V850_OPERAND_CC 0x04 - -/* This operand takes signed values */ -#define V850_OPERAND_SIGNED 0x08 - -/* This operand is the ep register. */ -#define V850_OPERAND_EP 0x10 - -/* This operand is a PC displacement */ -#define V850_OPERAND_DISP 0x20 - -/* This is a relaxable operand. Only used for D9->D22 branch relaxing - right now. We may need others in the future (or maybe handle them like - promoted operands on the mn10300?) */ -#define V850_OPERAND_RELAX 0x40 - -/* The register specified must not be r0 */ -#define V850_NOT_R0 0x80 - -/* push/pop type instruction, V850E specific. */ -#define V850E_PUSH_POP 0x100 - -/* 16 bit immediate follows instruction, V850E specific. */ -#define V850E_IMMEDIATE16 0x200 - -/* 32 bit immediate follows instruction, V850E specific. */ -#define V850E_IMMEDIATE32 0x400 - -#endif /* V850_H */ diff --git a/contrib/binutils/ld/emulparams/arcelf.sh b/contrib/binutils/ld/emulparams/arcelf.sh deleted file mode 100644 index b1c9c17..0000000 --- a/contrib/binutils/ld/emulparams/arcelf.sh +++ /dev/null @@ -1,11 +0,0 @@ -SCRIPT_NAME=elf -OUTPUT_FORMAT="elf32-littlearc" -LITTLE_OUTPUT_FORMAT="elf32-littlearc" -BIG_OUTPUT_FORMAT="elf32-bigarc" -TEXT_START_ADDR=0x0 -MAXPAGESIZE=0x1000 -NONPAGED_TEXT_START_ADDR=0x0 -ARCH=arc -MACHINE= -ENTRY=start -#TEMPLATE_NAME=elf32 diff --git a/contrib/binutils/ld/emulparams/elf32b4300.sh b/contrib/binutils/ld/emulparams/elf32b4300.sh deleted file mode 100644 index 4bfdd6e..0000000 --- a/contrib/binutils/ld/emulparams/elf32b4300.sh +++ /dev/null @@ -1,10 +0,0 @@ -# If you change this file, please also look at files which source this one: -# elf32l4300.sh - -EMBEDDED=yes -. ${srcdir}/emulparams/elf32bmip.sh -TEXT_START_ADDR=0xa0020000 -unset NONPAGED_TEXT_START_ADDR -unset SHLIB_TEXT_START_ADDR -EXECUTABLE_SYMBOLS='_DYNAMIC_LINK = 0;' -DYNAMIC_LINK=false diff --git a/contrib/binutils/ld/emulparams/elf32bmip.sh b/contrib/binutils/ld/emulparams/elf32bmip.sh deleted file mode 100644 index fa7d671..0000000 --- a/contrib/binutils/ld/emulparams/elf32bmip.sh +++ /dev/null @@ -1,36 +0,0 @@ -# If you change this file, please also look at files which source this one: -# elf32b4300.sh elf32bsmip.sh elf32btsmip.sh elf32ebmip.sh elf32lmip.sh - -SCRIPT_NAME=elf -OUTPUT_FORMAT="elf32-bigmips" -BIG_OUTPUT_FORMAT="elf32-bigmips" -LITTLE_OUTPUT_FORMAT="elf32-littlemips" -TEXT_START_ADDR=0x0400000 -test -n "${EMBEDDED}" || DATA_ADDR=0x10000000 -MAXPAGESIZE=0x40000 -NONPAGED_TEXT_START_ADDR=0x0400000 -SHLIB_TEXT_START_ADDR=0x5ffe0000 -test -n "${EMBEDDED}" || TEXT_DYNAMIC= -INITIAL_READONLY_SECTIONS=" - .reginfo ${RELOCATING-0} : { *(.reginfo) } -" -OTHER_TEXT_SECTIONS='*(.mips16.fn.*) *(.mips16.call.*)' -OTHER_GOT_SYMBOLS=' - _gp = ALIGN(16) + 0x7ff0; -' -OTHER_SDATA_SECTIONS=" - .lit8 ${RELOCATING-0} : { *(.lit8) } - .lit4 ${RELOCATING-0} : { *(.lit4) } -" -TEXT_START_SYMBOLS='_ftext = . ;' -DATA_START_SYMBOLS='_fdata = . ;' -OTHER_BSS_SYMBOLS='_fbss = .;' -OTHER_SECTIONS=' - .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } - .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } -' -ARCH=mips -MACHINE= -TEMPLATE_NAME=elf32 -EXTRA_EM_FILE=mipself -GENERATE_SHLIB_SCRIPT=yes diff --git a/contrib/binutils/ld/emulparams/elf32bmipn32.sh b/contrib/binutils/ld/emulparams/elf32bmipn32.sh deleted file mode 100755 index 8dc1735..0000000 --- a/contrib/binutils/ld/emulparams/elf32bmipn32.sh +++ /dev/null @@ -1,71 +0,0 @@ -# If you change this file, please also look at files which source this one: -# elf64bmip.sh elf64btsmip.sh - -# This is an ELF platform. -SCRIPT_NAME=elf - -# Handle both big- and little-ended 32-bit MIPS objects. -ARCH=mips -OUTPUT_FORMAT="elf32-bigmips" -BIG_OUTPUT_FORMAT="elf32-bigmips" -LITTLE_OUTPUT_FORMAT="elf32-littlemips" - -TEMPLATE_NAME=elf32 - -TEXT_START_ADDR=0x10000000 -MAXPAGESIZE=0x100000 -ENTRY=__start - -# GOT-related settings. -OTHER_GOT_SYMBOLS=' - _gp = ALIGN(16) + 0x7ff0; -' -OTHER_SDATA_SECTIONS=" - .lit8 ${RELOCATING-0} : { *(.lit8) } - .lit4 ${RELOCATING-0} : { *(.lit4) } - .srdata ${RELOCATING-0} : { *(.srdata) } -" - -# Magic symbols. -TEXT_START_SYMBOLS='_ftext = . ;' -DATA_START_SYMBOLS='_fdata = . ;' -OTHER_BSS_SYMBOLS='_fbss = .;' -# IRIX6 defines these symbols. 0x34 is the size of the ELF header. -EXECUTABLE_SYMBOLS=" - __dso_displacement = 0; - __elf_header = ${TEXT_START_ADDR}; - __program_header_table = ${TEXT_START_ADDR} + 0x34; -" - -# There are often dynamic relocations against the .rodata section. -# Setting DT_TEXTREL in the .dynamic section does not convince the -# IRIX6 linker to permit relocations against the text segment. -# Following the IRIX linker, we simply put .rodata in the data -# segment. -WRITABLE_RODATA= - -OTHER_SECTIONS=" - .MIPS.events.text ${RELOCATING-0} : - { - *(.MIPS.events.text${RELOCATING+ .MIPS.events.gnu.linkonce.t*}) - } - .MIPS.content.text ${RELOCATING-0} : - { - *(.MIPS.content.text${RELOCATING+ .MIPS.content.gnu.linkonce.t*}) - } - .MIPS.events.data ${RELOCATING-0} : - { - *(.MIPS.events.data${RELOCATING+ .MIPS.events.gnu.linkonce.d*}) - } - .MIPS.content.data ${RELOCATING-0} : - { - *(.MIPS.content.data${RELOCATING+ .MIPS.content.gnu.linkonce.d*}) - } - .MIPS.events.rodata ${RELOCATING-0} : - { - *(.MIPS.events.rodata${RELOCATING+ .MIPS.events.gnu.linkonce.r*}) - } - .MIPS.content.rodata ${RELOCATING-0} : - { - *(.MIPS.content.rodata${RELOCATING+ .MIPS.content.gnu.linkonce.r*}) - }" diff --git a/contrib/binutils/ld/emulparams/elf32bsmip.sh b/contrib/binutils/ld/emulparams/elf32bsmip.sh deleted file mode 100755 index 5b2939a..0000000 --- a/contrib/binutils/ld/emulparams/elf32bsmip.sh +++ /dev/null @@ -1,2 +0,0 @@ -. ${srcdir}/emulparams/elf32bmip.sh -ENTRY=__start diff --git a/contrib/binutils/ld/emulparams/elf32ebmip.sh b/contrib/binutils/ld/emulparams/elf32ebmip.sh deleted file mode 100644 index 704b43e..0000000 --- a/contrib/binutils/ld/emulparams/elf32ebmip.sh +++ /dev/null @@ -1,2 +0,0 @@ -EMBEDDED=yes -. ${srcdir}/emulparams/elf32bmip.sh diff --git a/contrib/binutils/ld/emulparams/elf32elmip.sh b/contrib/binutils/ld/emulparams/elf32elmip.sh deleted file mode 100644 index c94e503..0000000 --- a/contrib/binutils/ld/emulparams/elf32elmip.sh +++ /dev/null @@ -1,2 +0,0 @@ -EMBEDDED=yes -. ${srcdir}/emulparams/elf32lmip.sh diff --git a/contrib/binutils/ld/emulparams/elf32l4300.sh b/contrib/binutils/ld/emulparams/elf32l4300.sh deleted file mode 100644 index 865792a..0000000 --- a/contrib/binutils/ld/emulparams/elf32l4300.sh +++ /dev/null @@ -1,4 +0,0 @@ -. ${srcdir}/emulparams/elf32b4300.sh -OUTPUT_FORMAT="elf32-littlemips" -BIG_OUTPUT_FORMAT="elf32-bigmips" -LITTLE_OUTPUT_FORMAT="elf32-littlemips" diff --git a/contrib/binutils/ld/emulparams/elf32lmip.sh b/contrib/binutils/ld/emulparams/elf32lmip.sh deleted file mode 100644 index 14d4ded..0000000 --- a/contrib/binutils/ld/emulparams/elf32lmip.sh +++ /dev/null @@ -1,7 +0,0 @@ -# If you change this file, please also look at files which source this one: -# elf32elmip.sh elf32lsmip.sh - -. ${srcdir}/emulparams/elf32bmip.sh -OUTPUT_FORMAT="elf32-littlemips" -BIG_OUTPUT_FORMAT="elf32-bigmips" -LITTLE_OUTPUT_FORMAT="elf32-littlemips" diff --git a/contrib/binutils/ld/emulparams/elf32lsmip.sh b/contrib/binutils/ld/emulparams/elf32lsmip.sh deleted file mode 100755 index 62e4f98..0000000 --- a/contrib/binutils/ld/emulparams/elf32lsmip.sh +++ /dev/null @@ -1,2 +0,0 @@ -. ${srcdir}/emulparams/elf32lmip.sh -ENTRY=__start diff --git a/contrib/binutils/ld/emulparams/elf64bmip.sh b/contrib/binutils/ld/emulparams/elf64bmip.sh deleted file mode 100755 index 990fcb6..0000000 --- a/contrib/binutils/ld/emulparams/elf64bmip.sh +++ /dev/null @@ -1,12 +0,0 @@ -. ${srcdir}/emulparams/elf32bmipn32.sh -OUTPUT_FORMAT="elf64-bigmips" -BIG_OUTPUT_FORMAT="elf64-bigmips" -LITTLE_OUTPUT_FORMAT="elf64-littlemips" -ELFSIZE=64 - -# IRIX6 defines these symbols. 0x40 is the size of the ELF header. -EXECUTABLE_SYMBOLS=" - __dso_displacement = 0; - __elf_header = ${TEXT_START_ADDR}; - __program_header_table = ${TEXT_START_ADDR} + 0x40; -" diff --git a/contrib/binutils/ld/emulparams/sh.sh b/contrib/binutils/ld/emulparams/sh.sh deleted file mode 100644 index 52d1443..0000000 --- a/contrib/binutils/ld/emulparams/sh.sh +++ /dev/null @@ -1,8 +0,0 @@ -# If you change this file, please also look at files which source this one: -# shl.sh - -SCRIPT_NAME=sh -OUTPUT_FORMAT="coff-sh" -TEXT_START_ADDR=0x8000 -TARGET_PAGE_SIZE=128 -ARCH=sh diff --git a/contrib/binutils/ld/emulparams/shelf.sh b/contrib/binutils/ld/emulparams/shelf.sh deleted file mode 100755 index 5c0c9d6..0000000 --- a/contrib/binutils/ld/emulparams/shelf.sh +++ /dev/null @@ -1,32 +0,0 @@ -# If you change this file, please also look at files which source this one: -# shlelf.sh, shelf_nbsd.sh - -SCRIPT_NAME=elf -OUTPUT_FORMAT="elf32-sh" -TEXT_START_ADDR=0x1000 -MAXPAGESIZE=128 -ARCH=sh -MACHINE= -TEMPLATE_NAME=elf32 -GENERATE_SHLIB_SCRIPT=yes -EMBEDDED=yes - -# These are for compatibility with the COFF toolchain. -ENTRY=start -CTOR_START='___ctors = .;' -CTOR_END='___ctors_end = .;' -DTOR_START='___dtors = .;' -DTOR_END='___dtors_end = .;' -# This is like setting STACK_ADDR to 0x30000, except that the setting can -# be overridden, e.g. --defsym _stack=0x0f00, and that we put an extra -# sentinal value at the bottom. -# N.B. We can't use PROVIDE to set the default value in a symbol because -# the address is needed to place the .stack section, which in turn is needed -# to hold the sentinel value(s). -OTHER_SECTIONS=" .stack ${RELOCATING-0}${RELOCATING+(DEFINED(_stack) ? _stack : 0x30000)} : - { - ${RELOCATING+_stack = .;} - *(.stack) - LONG(0xdeaddead) - }" - diff --git a/contrib/binutils/ld/emulparams/shelf_linux.sh b/contrib/binutils/ld/emulparams/shelf_linux.sh deleted file mode 100644 index b841bef..0000000 --- a/contrib/binutils/ld/emulparams/shelf_linux.sh +++ /dev/null @@ -1,2 +0,0 @@ -. ${srcdir}/emulparams/shlelf_linux.sh -OUTPUT_FORMAT="elf32-shbig-linux" diff --git a/contrib/binutils/ld/emulparams/shl.sh b/contrib/binutils/ld/emulparams/shl.sh deleted file mode 100644 index 5fbb165..0000000 --- a/contrib/binutils/ld/emulparams/shl.sh +++ /dev/null @@ -1,2 +0,0 @@ -. ${srcdir}/emulparams/sh.sh -OUTPUT_FORMAT="coff-shl" diff --git a/contrib/binutils/ld/emulparams/shlelf.sh b/contrib/binutils/ld/emulparams/shlelf.sh deleted file mode 100755 index e19678b..0000000 --- a/contrib/binutils/ld/emulparams/shlelf.sh +++ /dev/null @@ -1,2 +0,0 @@ -. ${srcdir}/emulparams/shelf.sh -OUTPUT_FORMAT="elf32-shl" diff --git a/contrib/binutils/ld/emulparams/tic30aout.sh b/contrib/binutils/ld/emulparams/tic30aout.sh deleted file mode 100755 index 2a4c13f..0000000 --- a/contrib/binutils/ld/emulparams/tic30aout.sh +++ /dev/null @@ -1,7 +0,0 @@ -SCRIPT_NAME=tic30aout -OUTPUT_FORMAT="a.out-tic30" -OUTPUT_ARCH="tms320c30" -TEXT_START_ADDR=0x0 -TARGET_PAGE_SIZE=128 -ARCH=tms320c30 -BIG=1 diff --git a/contrib/binutils/ld/emulparams/tic30coff.sh b/contrib/binutils/ld/emulparams/tic30coff.sh deleted file mode 100755 index df77943..0000000 --- a/contrib/binutils/ld/emulparams/tic30coff.sh +++ /dev/null @@ -1,7 +0,0 @@ -SCRIPT_NAME=tic30coff -OUTPUT_FORMAT="coff-tic30" -OUTPUT_ARCH="tms320c30" -TEXT_START_ADDR=0x0 -TARGET_PAGE_SIZE=128 -ARCH=tms320c30 -BIG=1 diff --git a/contrib/binutils/ld/emulparams/v850.sh b/contrib/binutils/ld/emulparams/v850.sh deleted file mode 100644 index 78bfbd3..0000000 --- a/contrib/binutils/ld/emulparams/v850.sh +++ /dev/null @@ -1,14 +0,0 @@ -MACHINE= -SCRIPT_NAME=v850 -OUTPUT_FORMAT="elf32-v850" -TEXT_START_ADDR=0x100000 -ZDATA_START_ADDR=0x160 -ROZDATA_START_ADDR="ALIGN (4)" -SDATA_START_ADDR="ALIGN (4)" -ROSDATA_START_ADDR="ALIGN (4)" -TDATA_START_ADDR="ALIGN (4)" -CALL_TABLE_START_ADDR="ALIGN (4)" -ARCH=v850 -MAXPAGESIZE=256 -ENTRY=_start -EMBEDDED=yes diff --git a/contrib/binutils/ld/emulparams/vsta.sh b/contrib/binutils/ld/emulparams/vsta.sh deleted file mode 100644 index cc6249b..0000000 --- a/contrib/binutils/ld/emulparams/vsta.sh +++ /dev/null @@ -1,8 +0,0 @@ -SCRIPT_NAME=aout -OUTPUT_FORMAT="a.out-i386" -TEXT_START_ADDR=0x1020 -TARGET_PAGE_SIZE=0x1000 -SEGMENT_SIZE=0x400000 -NONPAGED_TEXT_START_ADDR=0x0 -ARCH=i386 - diff --git a/contrib/binutils/ld/emulparams/z8001.sh b/contrib/binutils/ld/emulparams/z8001.sh deleted file mode 100644 index 63645c3..0000000 --- a/contrib/binutils/ld/emulparams/z8001.sh +++ /dev/null @@ -1,7 +0,0 @@ -SCRIPT_NAME=z8000 -OUTPUT_FORMAT="coff-z8k" -OUTPUT_ARCH="z8001" -TEXT_START_ADDR=0x0 -TARGET_PAGE_SIZE=128 -ARCH=z8k -BIG=1 diff --git a/contrib/binutils/ld/emulparams/z8002.sh b/contrib/binutils/ld/emulparams/z8002.sh deleted file mode 100644 index 299b5f5..0000000 --- a/contrib/binutils/ld/emulparams/z8002.sh +++ /dev/null @@ -1,6 +0,0 @@ -SCRIPT_NAME=z8000 -OUTPUT_FORMAT="coff-z8k" -OUTPUT_ARCH="z8002" -TEXT_START_ADDR=0x0 -TARGET_PAGE_SIZE=128 -ARCH=z8002 diff --git a/contrib/binutils/opcodes/tic30-dis.c b/contrib/binutils/opcodes/tic30-dis.c deleted file mode 100644 index 67956f7..0000000 --- a/contrib/binutils/opcodes/tic30-dis.c +++ /dev/null @@ -1,710 +0,0 @@ -/* Disassembly routines for TMS320C30 architecture - Copyright 1998, 1999, 2000 Free Software Foundation, Inc. - Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au) - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA - 02111-1307, USA. */ - -#include <errno.h> -#include <math.h> -#include "sysdep.h" -#include "dis-asm.h" -#include "opcode/tic30.h" - -#define NORMAL_INSN 1 -#define PARALLEL_INSN 2 - -/* Gets the type of instruction based on the top 2 or 3 bits of the - instruction word. */ -#define GET_TYPE(insn) (insn & 0x80000000 ? insn & 0xC0000000 : insn & 0xE0000000) - -/* Instruction types. */ -#define TWO_OPERAND_1 0x00000000 -#define TWO_OPERAND_2 0x40000000 -#define THREE_OPERAND 0x20000000 -#define PAR_STORE 0xC0000000 -#define MUL_ADDS 0x80000000 -#define BRANCHES 0x60000000 - -/* Specific instruction id bits. */ -#define NORMAL_IDEN 0x1F800000 -#define PAR_STORE_IDEN 0x3E000000 -#define MUL_ADD_IDEN 0x2C000000 -#define BR_IMM_IDEN 0x1F000000 -#define BR_COND_IDEN 0x1C3F0000 - -/* Addressing modes. */ -#define AM_REGISTER 0x00000000 -#define AM_DIRECT 0x00200000 -#define AM_INDIRECT 0x00400000 -#define AM_IMM 0x00600000 - -#define P_FIELD 0x03000000 - -#define REG_AR0 0x08 -#define LDP_INSN 0x08700000 - -/* TMS320C30 program counter for current instruction. */ -static unsigned int _pc; - -struct instruction -{ - int type; - template *tm; - partemplate *ptm; -}; - -int get_tic30_instruction PARAMS ((unsigned long, struct instruction *)); -int print_two_operand - PARAMS ((disassemble_info *, unsigned long, struct instruction *)); -int print_three_operand - PARAMS ((disassemble_info *, unsigned long, struct instruction *)); -int print_par_insn - PARAMS ((disassemble_info *, unsigned long, struct instruction *)); -int print_branch - PARAMS ((disassemble_info *, unsigned long, struct instruction *)); -int get_indirect_operand PARAMS ((unsigned short, int, char *)); -int get_register_operand PARAMS ((unsigned char, char *)); -int cnvt_tmsfloat_ieee PARAMS ((unsigned long, int, float *)); - -int -print_insn_tic30 (pc, info) - bfd_vma pc; - disassemble_info *info; -{ - unsigned long insn_word; - struct instruction insn = { 0, NULL, NULL }; - bfd_vma bufaddr = pc - info->buffer_vma; - /* Obtain the current instruction word from the buffer. */ - insn_word = (*(info->buffer + bufaddr) << 24) | (*(info->buffer + bufaddr + 1) << 16) | - (*(info->buffer + bufaddr + 2) << 8) | *(info->buffer + bufaddr + 3); - _pc = pc / 4; - /* Get the instruction refered to by the current instruction word - and print it out based on its type. */ - if (!get_tic30_instruction (insn_word, &insn)) - return -1; - switch (GET_TYPE (insn_word)) - { - case TWO_OPERAND_1: - case TWO_OPERAND_2: - if (!print_two_operand (info, insn_word, &insn)) - return -1; - break; - case THREE_OPERAND: - if (!print_three_operand (info, insn_word, &insn)) - return -1; - break; - case PAR_STORE: - case MUL_ADDS: - if (!print_par_insn (info, insn_word, &insn)) - return -1; - break; - case BRANCHES: - if (!print_branch (info, insn_word, &insn)) - return -1; - break; - } - return 4; -} - -int -get_tic30_instruction (insn_word, insn) - unsigned long insn_word; - struct instruction *insn; -{ - switch (GET_TYPE (insn_word)) - { - case TWO_OPERAND_1: - case TWO_OPERAND_2: - case THREE_OPERAND: - insn->type = NORMAL_INSN; - { - template *current_optab = (template *) tic30_optab; - for (; current_optab < tic30_optab_end; current_optab++) - { - if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) - { - if (current_optab->operands == 0) - { - if (current_optab->base_opcode == insn_word) - { - insn->tm = current_optab; - break; - } - } - else if ((current_optab->base_opcode & NORMAL_IDEN) == (insn_word & NORMAL_IDEN)) - { - insn->tm = current_optab; - break; - } - } - } - } - break; - case PAR_STORE: - insn->type = PARALLEL_INSN; - { - partemplate *current_optab = (partemplate *) tic30_paroptab; - for (; current_optab < tic30_paroptab_end; current_optab++) - { - if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) - { - if ((current_optab->base_opcode & PAR_STORE_IDEN) == (insn_word & PAR_STORE_IDEN)) - { - insn->ptm = current_optab; - break; - } - } - } - } - break; - case MUL_ADDS: - insn->type = PARALLEL_INSN; - { - partemplate *current_optab = (partemplate *) tic30_paroptab; - for (; current_optab < tic30_paroptab_end; current_optab++) - { - if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) - { - if ((current_optab->base_opcode & MUL_ADD_IDEN) == (insn_word & MUL_ADD_IDEN)) - { - insn->ptm = current_optab; - break; - } - } - } - } - break; - case BRANCHES: - insn->type = NORMAL_INSN; - { - template *current_optab = (template *) tic30_optab; - for (; current_optab < tic30_optab_end; current_optab++) - { - if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word)) - { - if (current_optab->operand_types[0] & Imm24) - { - if ((current_optab->base_opcode & BR_IMM_IDEN) == (insn_word & BR_IMM_IDEN)) - { - insn->tm = current_optab; - break; - } - } - else if (current_optab->operands > 0) - { - if ((current_optab->base_opcode & BR_COND_IDEN) == (insn_word & BR_COND_IDEN)) - { - insn->tm = current_optab; - break; - } - } - else - { - if ((current_optab->base_opcode & (BR_COND_IDEN | 0x00800000)) == (insn_word & (BR_COND_IDEN | 0x00800000))) - { - insn->tm = current_optab; - break; - } - } - } - } - } - break; - default: - return 0; - } - return 1; -} - -int -print_two_operand (info, insn_word, insn) - disassemble_info *info; - unsigned long insn_word; - struct instruction *insn; -{ - char name[12]; - char operand[2][13] = - { - {0}, - {0}}; - float f_number; - - if (insn->tm == NULL) - return 0; - strcpy (name, insn->tm->name); - if (insn->tm->opcode_modifier == AddressMode) - { - int src_op, dest_op; - /* Determine whether instruction is a store or a normal instruction. */ - if ((insn->tm->operand_types[1] & (Direct | Indirect)) == (Direct | Indirect)) - { - src_op = 1; - dest_op = 0; - } - else - { - src_op = 0; - dest_op = 1; - } - /* Get the destination register. */ - if (insn->tm->operands == 2) - get_register_operand ((insn_word & 0x001F0000) >> 16, operand[dest_op]); - /* Get the source operand based on addressing mode. */ - switch (insn_word & AddressMode) - { - case AM_REGISTER: - /* Check for the NOP instruction before getting the operand. */ - if ((insn->tm->operand_types[0] & NotReq) == 0) - get_register_operand ((insn_word & 0x0000001F), operand[src_op]); - break; - case AM_DIRECT: - sprintf (operand[src_op], "@0x%lX", (insn_word & 0x0000FFFF)); - break; - case AM_INDIRECT: - get_indirect_operand ((insn_word & 0x0000FFFF), 2, operand[src_op]); - break; - case AM_IMM: - /* Get the value of the immediate operand based on variable type. */ - switch (insn->tm->imm_arg_type) - { - case Imm_Float: - cnvt_tmsfloat_ieee ((insn_word & 0x0000FFFF), 2, &f_number); - sprintf (operand[src_op], "%2.2f", f_number); - break; - case Imm_SInt: - sprintf (operand[src_op], "%d", (short) (insn_word & 0x0000FFFF)); - break; - case Imm_UInt: - sprintf (operand[src_op], "%lu", (insn_word & 0x0000FFFF)); - break; - default: - return 0; - } - /* Handle special case for LDP instruction. */ - if ((insn_word & 0xFFFFFF00) == LDP_INSN) - { - strcpy (name, "ldp"); - sprintf (operand[0], "0x%06lX", (insn_word & 0x000000FF) << 16); - operand[1][0] = '\0'; - } - } - } - /* Handle case for stack and rotate instructions. */ - else if (insn->tm->operands == 1) - { - if (insn->tm->opcode_modifier == StackOp) - { - get_register_operand ((insn_word & 0x001F0000) >> 16, operand[0]); - } - } - /* Output instruction to stream. */ - info->fprintf_func (info->stream, " %s %s%c%s", name, - operand[0][0] ? operand[0] : "", - operand[1][0] ? ',' : ' ', - operand[1][0] ? operand[1] : ""); - return 1; -} - -int -print_three_operand (info, insn_word, insn) - disassemble_info *info; - unsigned long insn_word; - struct instruction *insn; -{ - char operand[3][13] = - { - {0}, - {0}, - {0}}; - - if (insn->tm == NULL) - return 0; - switch (insn_word & AddressMode) - { - case AM_REGISTER: - get_register_operand ((insn_word & 0x000000FF), operand[0]); - get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]); - break; - case AM_DIRECT: - get_register_operand ((insn_word & 0x000000FF), operand[0]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]); - break; - case AM_INDIRECT: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]); - get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]); - break; - case AM_IMM: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]); - break; - default: - return 0; - } - if (insn->tm->operands == 3) - get_register_operand ((insn_word & 0x001F0000) >> 16, operand[2]); - info->fprintf_func (info->stream, " %s %s,%s%c%s", insn->tm->name, - operand[0], operand[1], - operand[2][0] ? ',' : ' ', - operand[2][0] ? operand[2] : ""); - return 1; -} - -int -print_par_insn (info, insn_word, insn) - disassemble_info *info; - unsigned long insn_word; - struct instruction *insn; -{ - size_t i, len; - char *name1, *name2; - char operand[2][3][13] = - { - { - {0}, - {0}, - {0}}, - { - {0}, - {0}, - {0}}}; - - if (insn->ptm == NULL) - return 0; - /* Parse out the names of each of the parallel instructions from the - q_insn1_insn2 format. */ - name1 = (char *) strdup (insn->ptm->name + 2); - name2 = ""; - len = strlen (name1); - for (i = 0; i < len; i++) - { - if (name1[i] == '_') - { - name2 = &name1[i + 1]; - name1[i] = '\0'; - break; - } - } - /* Get the operands of the instruction based on the operand order. */ - switch (insn->ptm->oporder) - { - case OO_4op1: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); - get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); - get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]); - break; - case OO_4op2: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]); - get_register_operand ((insn_word >> 19) & 0x07, operand[1][1]); - get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]); - break; - case OO_4op3: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); - get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); - get_register_operand ((insn_word >> 22) & 0x07, operand[0][0]); - break; - case OO_5op1: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); - get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); - get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]); - get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]); - break; - case OO_5op2: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]); - get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); - get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]); - get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]); - break; - case OO_PField: - if (insn_word & 0x00800000) - get_register_operand (0x01, operand[0][2]); - else - get_register_operand (0x00, operand[0][2]); - if (insn_word & 0x00400000) - get_register_operand (0x03, operand[1][2]); - else - get_register_operand (0x02, operand[1][2]); - switch (insn_word & P_FIELD) - { - case 0x00000000: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]); - get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]); - get_register_operand ((insn_word >> 19) & 0x07, operand[1][0]); - break; - case 0x01000000: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][0]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]); - get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]); - get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]); - break; - case 0x02000000: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]); - get_register_operand ((insn_word >> 16) & 0x07, operand[0][1]); - get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]); - break; - case 0x03000000: - get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]); - get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]); - get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]); - get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]); - break; - } - break; - default: - return 0; - } - info->fprintf_func (info->stream, " %s %s,%s%c%s", name1, - operand[0][0], operand[0][1], - operand[0][2][0] ? ',' : ' ', - operand[0][2][0] ? operand[0][2] : ""); - info->fprintf_func (info->stream, "\n\t\t\t|| %s %s,%s%c%s", name2, - operand[1][0], operand[1][1], - operand[1][2][0] ? ',' : ' ', - operand[1][2][0] ? operand[1][2] : ""); - free (name1); - return 1; -} - -int -print_branch (info, insn_word, insn) - disassemble_info *info; - unsigned long insn_word; - struct instruction *insn; -{ - char operand[2][13] = - { - {0}, - {0}}; - unsigned long address; - int print_label = 0; - - if (insn->tm == NULL) - return 0; - /* Get the operands for 24-bit immediate jumps. */ - if (insn->tm->operand_types[0] & Imm24) - { - address = insn_word & 0x00FFFFFF; - sprintf (operand[0], "0x%lX", address); - print_label = 1; - } - /* Get the operand for the trap instruction. */ - else if (insn->tm->operand_types[0] & IVector) - { - address = insn_word & 0x0000001F; - sprintf (operand[0], "0x%lX", address); - } - else - { - address = insn_word & 0x0000FFFF; - /* Get the operands for the DB instructions. */ - if (insn->tm->operands == 2) - { - get_register_operand (((insn_word & 0x01C00000) >> 22) + REG_AR0, operand[0]); - if (insn_word & PCRel) - { - sprintf (operand[1], "%d", (short) address); - print_label = 1; - } - else - get_register_operand (insn_word & 0x0000001F, operand[1]); - } - /* Get the operands for the standard branches. */ - else if (insn->tm->operands == 1) - { - if (insn_word & PCRel) - { - address = (short) address; - sprintf (operand[0], "%ld", address); - print_label = 1; - } - else - get_register_operand (insn_word & 0x0000001F, operand[0]); - } - } - info->fprintf_func (info->stream, " %s %s%c%s", insn->tm->name, - operand[0][0] ? operand[0] : "", - operand[1][0] ? ',' : ' ', - operand[1][0] ? operand[1] : ""); - /* Print destination of branch in relation to current symbol. */ - if (print_label && info->symbols) - { - asymbol *sym = *info->symbols; - - if ((insn->tm->opcode_modifier == PCRel) && (insn_word & PCRel)) - { - address = (_pc + 1 + (short) address) - ((sym->section->vma + sym->value) / 4); - /* Check for delayed instruction, if so adjust destination. */ - if (insn_word & 0x00200000) - address += 2; - } - else - { - address -= ((sym->section->vma + sym->value) / 4); - } - if (address == 0) - info->fprintf_func (info->stream, " <%s>", sym->name); - else - info->fprintf_func (info->stream, " <%s %c %d>", sym->name, - ((short) address < 0) ? '-' : '+', - abs (address)); - } - return 1; -} - -int -get_indirect_operand (fragment, size, buffer) - unsigned short fragment; - int size; - char *buffer; -{ - unsigned char mod; - unsigned arnum; - unsigned char disp; - - if (buffer == NULL) - return 0; - /* Determine which bits identify the sections of the indirect - operand based on the size in bytes. */ - switch (size) - { - case 1: - mod = (fragment & 0x00F8) >> 3; - arnum = (fragment & 0x0007); - disp = 0; - break; - case 2: - mod = (fragment & 0xF800) >> 11; - arnum = (fragment & 0x0700) >> 8; - disp = (fragment & 0x00FF); - break; - default: - return 0; - } - { - const ind_addr_type *current_ind = tic30_indaddr_tab; - for (; current_ind < tic30_indaddrtab_end; current_ind++) - { - if (current_ind->modfield == mod) - { - if (current_ind->displacement == IMPLIED_DISP && size == 2) - { - continue; - } - else - { - size_t i, len; - int bufcnt; - - len = strlen (current_ind->syntax); - for (i = 0, bufcnt = 0; i < len; i++, bufcnt++) - { - buffer[bufcnt] = current_ind->syntax[i]; - if (buffer[bufcnt - 1] == 'a' && buffer[bufcnt] == 'r') - buffer[++bufcnt] = arnum + '0'; - if (buffer[bufcnt] == '(' - && current_ind->displacement == DISP_REQUIRED) - { - sprintf (&buffer[bufcnt + 1], "%u", disp); - bufcnt += strlen (&buffer[bufcnt + 1]); - } - } - buffer[bufcnt + 1] = '\0'; - break; - } - } - } - } - return 1; -} - -int -get_register_operand (fragment, buffer) - unsigned char fragment; - char *buffer; -{ - const reg *current_reg = tic30_regtab; - - if (buffer == NULL) - return 0; - for (; current_reg < tic30_regtab_end; current_reg++) - { - if ((fragment & 0x1F) == current_reg->opcode) - { - strcpy (buffer, current_reg->name); - return 1; - } - } - return 0; -} - -int -cnvt_tmsfloat_ieee (tmsfloat, size, ieeefloat) - unsigned long tmsfloat; - int size; - float *ieeefloat; -{ - unsigned long exp, sign, mant; - - if (size == 2) - { - if ((tmsfloat & 0x0000F000) == 0x00008000) - tmsfloat = 0x80000000; - else - { - tmsfloat <<= 16; - tmsfloat = (long) tmsfloat >> 4; - } - } - exp = tmsfloat & 0xFF000000; - if (exp == 0x80000000) - { - *ieeefloat = 0.0; - return 1; - } - exp += 0x7F000000; - sign = (tmsfloat & 0x00800000) << 8; - mant = tmsfloat & 0x007FFFFF; - if (exp == 0xFF000000) - { - if (mant == 0) - *ieeefloat = ERANGE; - if (sign == 0) - *ieeefloat = 1.0 / 0.0; - else - *ieeefloat = -1.0 / 0.0; - return 1; - } - exp >>= 1; - if (sign) - { - mant = (~mant) & 0x007FFFFF; - mant += 1; - exp += mant & 0x00800000; - exp &= 0x7F800000; - mant &= 0x007FFFFF; - } - if (tmsfloat == 0x80000000) - sign = mant = exp = 0; - tmsfloat = sign | exp | mant; - *ieeefloat = *((float *) &tmsfloat); - return 1; -} diff --git a/contrib/binutils/opcodes/v850-dis.c b/contrib/binutils/opcodes/v850-dis.c deleted file mode 100644 index e72b1e8..0000000 --- a/contrib/binutils/opcodes/v850-dis.c +++ /dev/null @@ -1,384 +0,0 @@ -/* Disassemble V850 instructions. - Copyright 1996, 1997, 1998, 2000, 2001 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - - -#include <stdio.h> - -#include "sysdep.h" -#include "opcode/v850.h" -#include "dis-asm.h" -#include "opintl.h" - -static const char *const v850_reg_names[] = -{ "r0", "r1", "r2", "sp", "gp", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", - "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", - "r24", "r25", "r26", "r27", "r28", "r29", "ep", "lp" }; - -static const char *const v850_sreg_names[] = -{ "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7", - "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15", - "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "sr21", "sr22", "sr23", - "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31", - "sr16", "sr17", "sr18", "sr19", "sr20", "sr21", "sr22", "sr23", - "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31" }; - -static const char *const v850_cc_names[] = -{ "v", "c/l", "z", "nh", "s/n", "t", "lt", "le", - "nv", "nc/nl", "nz", "h", "ns/p", "sa", "ge", "gt" }; - -static int disassemble - PARAMS ((bfd_vma, struct disassemble_info *, unsigned long)); - -static int -disassemble (memaddr, info, insn) - bfd_vma memaddr; - struct disassemble_info *info; - unsigned long insn; -{ - struct v850_opcode * op = (struct v850_opcode *)v850_opcodes; - const struct v850_operand * operand; - int match = 0; - int short_op = ((insn & 0x0600) != 0x0600); - int bytes_read; - int target_processor; - - /* Special case: 32 bit MOV */ - if ((insn & 0xffe0) == 0x0620) - short_op = true; - - bytes_read = short_op ? 2 : 4; - - /* If this is a two byte insn, then mask off the high bits. */ - if (short_op) - insn &= 0xffff; - - switch (info->mach) - { - case 0: - default: - target_processor = PROCESSOR_V850; - break; - - case bfd_mach_v850e: - target_processor = PROCESSOR_V850E; - break; - - case bfd_mach_v850ea: - target_processor = PROCESSOR_V850EA; - break; - } - - /* Find the opcode. */ - while (op->name) - { - if ((op->mask & insn) == op->opcode - && (op->processors & target_processor)) - { - const unsigned char * opindex_ptr; - unsigned int opnum; - unsigned int memop; - - match = 1; - (*info->fprintf_func) (info->stream, "%s\t", op->name); -/*fprintf (stderr, "match: mask: %x insn: %x, opcode: %x, name: %s\n", op->mask, insn, op->opcode, op->name );*/ - - memop = op->memop; - /* Now print the operands. - - MEMOP is the operand number at which a memory - address specification starts, or zero if this - instruction has no memory addresses. - - A memory address is always two arguments. - - This information allows us to determine when to - insert commas into the output stream as well as - when to insert disp[reg] expressions onto the - output stream. */ - - for (opindex_ptr = op->operands, opnum = 1; - *opindex_ptr != 0; - opindex_ptr++, opnum++) - { - long value; - int flag; - int status; - bfd_byte buffer[ 4 ]; - - operand = &v850_operands[*opindex_ptr]; - - if (operand->extract) - value = (operand->extract) (insn, 0); - else - { - if (operand->bits == -1) - value = (insn & operand->shift); - else - value = (insn >> operand->shift) & ((1 << operand->bits) - 1); - - if (operand->flags & V850_OPERAND_SIGNED) - value = ((long)(value << (32 - operand->bits)) - >> (32 - operand->bits)); - } - - /* The first operand is always output without any - special handling. - - For the following arguments: - - If memop && opnum == memop + 1, then we need '[' since - we're about to output the register used in a memory - reference. - - If memop && opnum == memop + 2, then we need ']' since - we just finished the register in a memory reference. We - also need a ',' before this operand. - - Else we just need a comma. - - We may need to output a trailing ']' if the last operand - in an instruction is the register for a memory address. - - The exception (and there's always an exception) is the - "jmp" insn which needs square brackets around it's only - register argument. */ - - if (memop && opnum == memop + 1) info->fprintf_func (info->stream, "["); - else if (memop && opnum == memop + 2) info->fprintf_func (info->stream, "],"); - else if (memop == 1 && opnum == 1 - && (operand->flags & V850_OPERAND_REG)) - info->fprintf_func (info->stream, "["); - else if (opnum > 1) info->fprintf_func (info->stream, ", "); - - /* extract the flags, ignorng ones which do not effect disassembly output. */ - flag = operand->flags; - flag &= ~ V850_OPERAND_SIGNED; - flag &= ~ V850_OPERAND_RELAX; - flag &= - flag; - - switch (flag) - { - case V850_OPERAND_REG: info->fprintf_func (info->stream, "%s", v850_reg_names[value]); break; - case V850_OPERAND_SRG: info->fprintf_func (info->stream, "%s", v850_sreg_names[value]); break; - case V850_OPERAND_CC: info->fprintf_func (info->stream, "%s", v850_cc_names[value]); break; - case V850_OPERAND_EP: info->fprintf_func (info->stream, "ep"); break; - default: info->fprintf_func (info->stream, "%d", value); break; - case V850_OPERAND_DISP: - { - bfd_vma addr = value + memaddr; - - /* On the v850 the top 8 bits of an address are used by an overlay manager. - Thus it may happen that when we are looking for a symbol to match - against an address with some of its top bits set, the search fails to - turn up an exact match. In this case we try to find an exact match - against a symbol in the lower address space, and if we find one, we - use that address. We only do this for JARL instructions however, as - we do not want to misinterpret branch instructions. */ - if (operand->bits == 22) - { - if ( ! info->symbol_at_address_func (addr, info) - && ((addr & 0xFF000000) != 0) - && info->symbol_at_address_func (addr & 0x00FFFFFF, info)) - { - addr &= 0x00FFFFFF; - } - } - info->print_address_func (addr, info); - break; - } - - case V850E_PUSH_POP: - { - static int list12_regs[32] = { 30, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 }; - static int list18_h_regs[32] = { 19, 18, 17, 16, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, 30, 31, 29, 28, 23, 22, 21, 20, 27, 26, 25, 24 }; - static int list18_l_regs[32] = { 3, 2, 1, -2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, -1, 14, 15, 13, 12, 7, 6, 5, 4, 11, 10, 9, 8 }; - int * regs; - int i; - unsigned long int mask = 0; - int pc = false; - int sr = false; - - - switch (operand->shift) - { - case 0xffe00001: regs = list12_regs; break; - case 0xfff8000f: regs = list18_h_regs; break; - case 0xfff8001f: regs = list18_l_regs; value &= ~0x10; break; /* Do not include magic bit */ - default: - /* xgettext:c-format */ - fprintf (stderr, _("unknown operand shift: %x\n"), operand->shift ); - abort(); - } - - for (i = 0; i < 32; i++) - { - if (value & (1 << i)) - { - switch (regs[ i ]) - { - default: mask |= (1 << regs[ i ]); break; - /* xgettext:c-format */ - case 0: fprintf (stderr, _("unknown pop reg: %d\n"), i ); abort(); - case -1: pc = true; break; - case -2: sr = true; break; - } - } - } - - info->fprintf_func (info->stream, "{"); - - if (mask || pc || sr) - { - if (mask) - { - unsigned int bit; - int shown_one = false; - - for (bit = 0; bit < 32; bit++) - if (mask & (1 << bit)) - { - unsigned long int first = bit; - unsigned long int last; - - if (shown_one) - info->fprintf_func (info->stream, ", "); - else - shown_one = true; - - info->fprintf_func (info->stream, v850_reg_names[first]); - - for (bit++; bit < 32; bit++) - if ((mask & (1 << bit)) == 0) - break; - - last = bit; - - if (last > first + 1) - { - info->fprintf_func (info->stream, " - %s", v850_reg_names[ last - 1 ]); - } - } - } - - if (pc) - info->fprintf_func (info->stream, "%sPC", mask ? ", " : ""); - if (sr) - info->fprintf_func (info->stream, "%sSR", (mask || pc) ? ", " : ""); - } - - info->fprintf_func (info->stream, "}"); - } - break; - - case V850E_IMMEDIATE16: - status = info->read_memory_func (memaddr + bytes_read, buffer, 2, info); - if (status == 0) - { - bytes_read += 2; - value = bfd_getl16 (buffer); - - /* If this is a DISPOSE instruction with ff set to 0x10, then shift value up by 16. */ - if ((insn & 0x001fffc0) == 0x00130780) - value <<= 16; - - info->fprintf_func (info->stream, "0x%x", value); - } - else - { - info->memory_error_func (status, memaddr + bytes_read, info); - } - break; - - case V850E_IMMEDIATE32: - status = info->read_memory_func (memaddr + bytes_read, buffer, 4, info); - if (status == 0) - { - bytes_read += 4; - value = bfd_getl32 (buffer); - info->fprintf_func (info->stream, "0x%lx", value); - } - else - { - info->memory_error_func (status, memaddr + bytes_read, info); - } - break; - } - - /* Handle jmp correctly. */ - if (memop == 1 && opnum == 1 - && ((operand->flags & V850_OPERAND_REG) != 0)) - (*info->fprintf_func) (info->stream, "]"); - } - - /* Close any square bracket we left open. */ - if (memop && opnum == memop + 2) - (*info->fprintf_func) (info->stream, "]"); - - /* All done. */ - break; - } - op++; - } - - if (!match) - { - if (short_op) - info->fprintf_func (info->stream, ".short\t0x%04x", insn); - else - info->fprintf_func (info->stream, ".long\t0x%08x", insn); - } - - return bytes_read; -} - -int -print_insn_v850 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info * info; -{ - int status; - bfd_byte buffer[ 4 ]; - unsigned long insn = 0; - - /* First figure out how big the opcode is. */ - - status = info->read_memory_func (memaddr, buffer, 2, info); - if (status == 0) - { - insn = bfd_getl16 (buffer); - - if ( (insn & 0x0600) == 0x0600 - && (insn & 0xffe0) != 0x0620) - { - /* If this is a 4 byte insn, read 4 bytes of stuff. */ - status = info->read_memory_func (memaddr, buffer, 4, info); - - if (status == 0) - insn = bfd_getl32 (buffer); - } - } - - if (status != 0) - { - info->memory_error_func (status, memaddr, info); - return -1; - } - - /* Make sure we tell our caller how many bytes we consumed. */ - return disassemble (memaddr, info, insn); -} diff --git a/contrib/binutils/opcodes/v850-opc.c b/contrib/binutils/opcodes/v850-opc.c deleted file mode 100644 index 43ce2f1..0000000 --- a/contrib/binutils/opcodes/v850-opc.c +++ /dev/null @@ -1,813 +0,0 @@ -/* Assemble V850 instructions. - Copyright 1996, 1997, 1998, 2000, 2001 Free Software Foundation, Inc. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include "opcode/v850.h" -#include <stdio.h> -#include "opintl.h" - -/* regular opcode */ -#define OP(x) ((x & 0x3f) << 5) -#define OP_MASK OP (0x3f) - -/* conditional branch opcode */ -#define BOP(x) ((0x0b << 7) | (x & 0x0f)) -#define BOP_MASK ((0x0f << 7) | 0x0f) - -/* one-word opcodes */ -#define one(x) ((unsigned int) (x)) - -/* two-word opcodes */ -#define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16)) - -static long unsigned insert_d9 PARAMS ((long unsigned, long, const char **)); -static long unsigned extract_d9 PARAMS ((long unsigned, int *)); -static long unsigned insert_d22 PARAMS ((long unsigned, long, const char **)); -static long unsigned extract_d22 PARAMS ((long unsigned, int *)); -static long unsigned insert_d16_15 PARAMS ((long unsigned, long, const char **)); -static long unsigned extract_d16_15 PARAMS ((long unsigned, int *)); -static long unsigned insert_d8_7 PARAMS ((long unsigned, long, const char **)); -static long unsigned extract_d8_7 PARAMS ((long unsigned, int *)); -static long unsigned insert_d8_6 PARAMS ((long unsigned, long, const char **)); -static long unsigned extract_d8_6 PARAMS ((long unsigned, int *)); -static long unsigned insert_d5_4 PARAMS ((long unsigned, long, const char **)); -static long unsigned extract_d5_4 PARAMS ((long unsigned, int *)); -static long unsigned insert_d16_16 PARAMS ((long unsigned, long, const char **)); -static long unsigned extract_d16_16 PARAMS ((long unsigned, int *)); -static long unsigned insert_i9 PARAMS ((long unsigned, long, const char **)); -static long unsigned extract_i9 PARAMS ((long unsigned, int *)); -static long unsigned insert_u9 PARAMS ((long unsigned, long, const char **)); -static long unsigned extract_u9 PARAMS ((long unsigned, int *)); -static long unsigned insert_spe PARAMS ((long unsigned, long, const char **)); -static long unsigned extract_spe PARAMS ((long unsigned, int *)); -static long unsigned insert_i5div PARAMS ((long unsigned, long, const char **)); -static long unsigned extract_i5div PARAMS ((long unsigned, int *)); - - -/* The functions used to insert and extract complicated operands. */ - -/* Note: There is a conspiracy between these functions and - v850_insert_operand() in gas/config/tc-v850.c. Error messages - containing the string 'out of range' will be ignored unless a - specific command line option is given to GAS. */ - -static const char * not_valid = N_ ("displacement value is not in range and is not aligned"); -static const char * out_of_range = N_ ("displacement value is out of range"); -static const char * not_aligned = N_ ("displacement value is not aligned"); - -static const char * immediate_out_of_range = N_ ("immediate value is out of range"); - -static unsigned long -insert_d9 (insn, value, errmsg) - unsigned long insn; - long value; - const char ** errmsg; -{ - if (value > 0xff || value < -0x100) - { - if ((value % 2) != 0) - * errmsg = _("branch value not in range and to odd offset"); - else - * errmsg = _("branch value out of range"); - } - else if ((value % 2) != 0) - * errmsg = _("branch to odd offset"); - - return (insn | ((value & 0x1f0) << 7) | ((value & 0x0e) << 3)); -} - -static unsigned long -extract_d9 (insn, invalid) - unsigned long insn; - int * invalid ATTRIBUTE_UNUSED; -{ - unsigned long ret = ((insn & 0xf800) >> 7) | ((insn & 0x0070) >> 3); - - if ((insn & 0x8000) != 0) - ret -= 0x0200; - - return ret; -} - -static unsigned long -insert_d22 (insn, value, errmsg) - unsigned long insn; - long value; - const char ** errmsg; -{ - if (value > 0x1fffff || value < -0x200000) - { - if ((value % 2) != 0) - * errmsg = _("branch value not in range and to an odd offset"); - else - * errmsg = _("branch value out of range"); - } - else if ((value % 2) != 0) - * errmsg = _("branch to odd offset"); - - return (insn | ((value & 0xfffe) << 16) | ((value & 0x3f0000) >> 16)); -} - -static unsigned long -extract_d22 (insn, invalid) - unsigned long insn; - int * invalid ATTRIBUTE_UNUSED; -{ - signed long ret = ((insn & 0xfffe0000) >> 16) | ((insn & 0x3f) << 16); - - return (unsigned long) ((ret << 10) >> 10); -} - -static unsigned long -insert_d16_15 (insn, value, errmsg) - unsigned long insn; - long value; - const char ** errmsg; -{ - if (value > 0x7fff || value < -0x8000) - { - if ((value % 2) != 0) - * errmsg = _(not_valid); - else - * errmsg = _(out_of_range); - } - else if ((value % 2) != 0) - * errmsg = _(not_aligned); - - return insn | ((value & 0xfffe) << 16); -} - -static unsigned long -extract_d16_15 (insn, invalid) - unsigned long insn; - int * invalid ATTRIBUTE_UNUSED; -{ - signed long ret = (insn & 0xfffe0000); - - return ret >> 16; -} - -static unsigned long -insert_d8_7 (insn, value, errmsg) - unsigned long insn; - long value; - const char ** errmsg; -{ - if (value > 0xff || value < 0) - { - if ((value % 2) != 0) - * errmsg = _(not_valid); - else - * errmsg = _(out_of_range); - } - else if ((value % 2) != 0) - * errmsg = _(not_aligned); - - value >>= 1; - - return (insn | (value & 0x7f)); -} - -static unsigned long -extract_d8_7 (insn, invalid) - unsigned long insn; - int * invalid ATTRIBUTE_UNUSED; -{ - unsigned long ret = (insn & 0x7f); - - return ret << 1; -} - -static unsigned long -insert_d8_6 (insn, value, errmsg) - unsigned long insn; - long value; - const char ** errmsg; -{ - if (value > 0xff || value < 0) - { - if ((value % 4) != 0) - *errmsg = _(not_valid); - else - * errmsg = _(out_of_range); - } - else if ((value % 4) != 0) - * errmsg = _(not_aligned); - - value >>= 1; - - return (insn | (value & 0x7e)); -} - -static unsigned long -extract_d8_6 (insn, invalid) - unsigned long insn; - int * invalid ATTRIBUTE_UNUSED; -{ - unsigned long ret = (insn & 0x7e); - - return ret << 1; -} - -static unsigned long -insert_d5_4 (insn, value, errmsg) - unsigned long insn; - long value; - const char ** errmsg; -{ - if (value > 0x1f || value < 0) - { - if (value & 1) - * errmsg = _(not_valid); - else - *errmsg = _(out_of_range); - } - else if (value & 1) - * errmsg = _(not_aligned); - - value >>= 1; - - return (insn | (value & 0x0f)); -} - -static unsigned long -extract_d5_4 (insn, invalid) - unsigned long insn; - int * invalid ATTRIBUTE_UNUSED; -{ - unsigned long ret = (insn & 0x0f); - - return ret << 1; -} - -static unsigned long -insert_d16_16 (insn, value, errmsg) - unsigned long insn; - signed long value; - const char ** errmsg; -{ - if (value > 0x7fff || value < -0x8000) - * errmsg = _(out_of_range); - - return (insn | ((value & 0xfffe) << 16) | ((value & 1) << 5)); -} - -static unsigned long -extract_d16_16 (insn, invalid) - unsigned long insn; - int * invalid ATTRIBUTE_UNUSED; -{ - signed long ret = insn & 0xfffe0000; - - ret >>= 16; - - ret |= ((insn & 0x20) >> 5); - - return ret; -} - -static unsigned long -insert_i9 (insn, value, errmsg) - unsigned long insn; - signed long value; - const char ** errmsg; -{ - if (value > 0xff || value < -0x100) - * errmsg = _(immediate_out_of_range); - - return insn | ((value & 0x1e0) << 13) | (value & 0x1f); -} - -static unsigned long -extract_i9 (insn, invalid) - unsigned long insn; - int * invalid ATTRIBUTE_UNUSED; -{ - signed long ret = insn & 0x003c0000; - - ret <<= 10; - ret >>= 23; - - ret |= (insn & 0x1f); - - return ret; -} - -static unsigned long -insert_u9 (insn, v, errmsg) - unsigned long insn; - long v; - const char ** errmsg; -{ - unsigned long value = (unsigned long) v; - if (value > 0x1ff) - * errmsg = _(immediate_out_of_range); - - return insn | ((value & 0x1e0) << 13) | (value & 0x1f); -} - -static unsigned long -extract_u9 (insn, invalid) - unsigned long insn; - int * invalid ATTRIBUTE_UNUSED; -{ - unsigned long ret = insn & 0x003c0000; - - ret >>= 13; - - ret |= (insn & 0x1f); - - return ret; -} - -static unsigned long -insert_spe (insn, v, errmsg) - unsigned long insn; - long v; - const char ** errmsg; -{ - unsigned long value = (unsigned long) v; - - if (value != 3) - * errmsg = _("invalid register for stack adjustment"); - - return insn & (~ 0x180000); -} - -static unsigned long -extract_spe (insn, invalid) - unsigned long insn ATTRIBUTE_UNUSED; - int * invalid ATTRIBUTE_UNUSED; -{ - return 3; -} - -static unsigned long -insert_i5div (insn, v, errmsg) - unsigned long insn; - long v; - const char ** errmsg; -{ - unsigned long value = (unsigned long) v; - - if (value > 0x1ff) - { - if (value & 1) - * errmsg = _("immediate value not in range and not even"); - else - * errmsg = _(immediate_out_of_range); - } - else if (value & 1) - * errmsg = _("immediate value must be even"); - - value = 32 - value; - - return insn | ((value & 0x1e) << 17); -} - -static unsigned long -extract_i5div (insn, invalid) - unsigned long insn; - int * invalid ATTRIBUTE_UNUSED; -{ - unsigned long ret = insn & 0x3c0000; - - ret >>= 17; - - ret = 32 - ret; - - return ret; -} - - -/* Warning: code in gas/config/tc-v850.c examines the contents of this array. - If you change any of the values here, be sure to look for side effects in - that code. */ -const struct v850_operand v850_operands[] = -{ -#define UNUSED 0 - { 0, 0, NULL, NULL, 0 }, - -/* The R1 field in a format 1, 6, 7, or 9 insn. */ -#define R1 (UNUSED + 1) - { 5, 0, NULL, NULL, V850_OPERAND_REG }, - -/* As above, but register 0 is not allowed. */ -#define R1_NOTR0 (R1 + 1) - { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, - -/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */ -#define R2 (R1_NOTR0 + 1) - { 5, 11, NULL, NULL, V850_OPERAND_REG }, - -/* As above, but register 0 is not allowed. */ -#define R2_NOTR0 (R2 + 1) - { 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, - -/* The imm5 field in a format 2 insn. */ -#define I5 (R2_NOTR0 + 1) - { 5, 0, NULL, NULL, V850_OPERAND_SIGNED }, - -/* The unsigned imm5 field in a format 2 insn. */ -#define I5U (I5 + 1) - { 5, 0, NULL, NULL, 0 }, - -/* The imm16 field in a format 6 insn. */ -#define I16 (I5U + 1) - { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, - -/* The signed disp7 field in a format 4 insn. */ -#define D7 (I16 + 1) - { 7, 0, NULL, NULL, 0}, - -/* The disp16 field in a format 6 insn. */ -#define D16_15 (D7 + 1) - { 15, 17, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED }, - -/* The 3 bit immediate field in format 8 insn. */ -#define B3 (D16_15 + 1) - { 3, 11, NULL, NULL, 0 }, - -/* The 4 bit condition code in a setf instruction */ -#define CCCC (B3 + 1) - { 4, 0, NULL, NULL, V850_OPERAND_CC }, - -/* The unsigned DISP8 field in a format 4 insn. */ -#define D8_7 (CCCC + 1) - { 7, 0, insert_d8_7, extract_d8_7, 0 }, - -/* The unsigned DISP8 field in a format 4 insn. */ -#define D8_6 (D8_7 + 1) - { 6, 1, insert_d8_6, extract_d8_6, 0 }, - -/* System register operands. */ -#define SR1 (D8_6 + 1) - { 5, 0, NULL, NULL, V850_OPERAND_SRG }, - -/* EP Register. */ -#define EP (SR1 + 1) - { 0, 0, NULL, NULL, V850_OPERAND_EP }, - -/* The imm16 field (unsigned) in a format 6 insn. */ -#define I16U (EP + 1) - { 16, 16, NULL, NULL, 0}, - -/* The R2 field as a system register. */ -#define SR2 (I16U + 1) - { 5, 11, NULL, NULL, V850_OPERAND_SRG }, - -/* The disp16 field in a format 8 insn. */ -#define D16 (SR2 + 1) - { 16, 16, NULL, NULL, V850_OPERAND_SIGNED }, - -/* The DISP9 field in a format 3 insn, relaxable. */ -#define D9_RELAX (D16 + 1) - { 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP }, - -/* The DISP22 field in a format 4 insn, relaxable. - This _must_ follow D9_RELAX; the assembler assumes that the longer - version immediately follows the shorter version for relaxing. */ -#define D22 (D9_RELAX + 1) - { 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP }, - -/* The signed disp4 field in a format 4 insn. */ -#define D4 (D22 + 1) - { 4, 0, NULL, NULL, 0}, - -/* The unsigned disp5 field in a format 4 insn. */ -#define D5_4 (D4 + 1) - { 4, 0, insert_d5_4, extract_d5_4, 0 }, - -/* The disp16 field in an format 7 unsigned byte load insn. */ -#define D16_16 (D5_4 + 1) - { -1, 0xfffe0020, insert_d16_16, extract_d16_16, 0 }, - -/* Third register in conditional moves. */ -#define R3 (D16_16 + 1) - { 5, 27, NULL, NULL, V850_OPERAND_REG }, - -/* Condition code in conditional moves. */ -#define MOVCC (R3 + 1) - { 4, 17, NULL, NULL, V850_OPERAND_CC }, - -/* The imm9 field in a multiply word. */ -#define I9 (MOVCC + 1) - { 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED }, - -/* The unsigned imm9 field in a multiply word. */ -#define U9 (I9 + 1) - { 9, 0, insert_u9, extract_u9, 0 }, - -/* A list of registers in a prepare/dispose instruction. */ -#define LIST12 (U9 + 1) - { -1, 0xffe00001, NULL, NULL, V850E_PUSH_POP }, - -/* The IMM6 field in a call instruction. */ -#define I6 (LIST12 + 1) - { 6, 0, NULL, NULL, 0 }, - -/* The 16 bit immediate following a 32 bit instruction. */ -#define IMM16 (I6 + 1) - { 16, 16, NULL, NULL, V850_OPERAND_SIGNED | V850E_IMMEDIATE16 }, - -/* The 32 bit immediate following a 32 bit instruction. */ -#define IMM32 (IMM16 + 1) - { 0, 0, NULL, NULL, V850E_IMMEDIATE32 }, - -/* The imm5 field in a push/pop instruction. */ -#define IMM5 (IMM32 + 1) - { 5, 1, NULL, NULL, 0 }, - -/* Reg2 in dispose instruction. */ -#define R2DISPOSE (IMM5 + 1) - { 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 }, - -/* Stack pointer in prepare instruction. */ -#define SP (R2DISPOSE + 1) - { 2, 19, insert_spe, extract_spe, V850_OPERAND_REG }, - -/* The IMM5 field in a divide N step instruction. */ -#define I5DIV (SP + 1) - { 9, 0, insert_i5div, extract_i5div, V850_OPERAND_SIGNED }, - - /* The list of registers in a PUSHMH/POPMH instruction. */ -#define LIST18_H (I5DIV + 1) - { -1, 0xfff8000f, NULL, NULL, V850E_PUSH_POP }, - - /* The list of registers in a PUSHML/POPML instruction. */ -#define LIST18_L (LIST18_H + 1) - { -1, 0xfff8001f, NULL, NULL, V850E_PUSH_POP }, /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c */ -} ; - - -/* reg-reg instruction format (Format I) */ -#define IF1 {R1, R2} - -/* imm-reg instruction format (Format II) */ -#define IF2 {I5, R2} - -/* conditional branch instruction format (Format III) */ -#define IF3 {D9_RELAX} - -/* 3 operand instruction (Format VI) */ -#define IF6 {I16, R1, R2} - -/* 3 operand instruction (Format VI) */ -#define IF6U {I16U, R1, R2} - - - -/* The opcode table. - - The format of the opcode table is: - - NAME OPCODE MASK { OPERANDS } MEMOP PROCESSOR - - NAME is the name of the instruction. - OPCODE is the instruction opcode. - MASK is the opcode mask; this is used to tell the disassembler - which bits in the actual opcode must match OPCODE. - OPERANDS is the list of operands. - MEMOP specifies which operand (if any) is a memory operand. - PROCESSORS specifies which CPU(s) support the opcode. - - The disassembler reads the table in order and prints the first - instruction which matches, so this table is sorted to put more - specific instructions before more general instructions. It is also - sorted by major opcode. - - The table is also sorted by name. This is used by the assembler. - When parsing an instruction the assembler finds the first occurance - of the name of the instruciton in this table and then attempts to - match the instruction's arguments with description of the operands - associated with the entry it has just found in this table. If the - match fails the assembler looks at the next entry in this table. - If that entry has the same name as the previous entry, then it - tries to match the instruction against that entry and so on. This - is how the assembler copes with multiple, different formats of the - same instruction. */ - -const struct v850_opcode v850_opcodes[] = -{ -{ "breakpoint", 0xffff, 0xffff, {UNUSED}, 0, PROCESSOR_ALL }, - -{ "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL }, - -/* load/store instructions */ -{ "sld.bu", one (0x0300), one (0x0780), {D7, EP, R2_NOTR0}, 1, PROCESSOR_V850EA }, -{ "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2_NOTR0}, 1, PROCESSOR_V850E }, - -{ "sld.hu", one (0x0400), one (0x0780), {D8_7, EP, R2_NOTR0}, 1, PROCESSOR_V850EA }, -{ "sld.hu", one (0x0070), one (0x07f0), {D5_4, EP, R2_NOTR0}, 1, PROCESSOR_V850E }, - -{ "sld.b", one (0x0060), one (0x07f0), {D4, EP, R2}, 1, PROCESSOR_V850EA }, -{ "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850E }, -{ "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850 }, - -{ "sld.h", one (0x0070), one (0x07f0), {D5_4, EP, R2}, 1, PROCESSOR_V850EA }, -{ "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850E }, -{ "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850 }, -{ "sld.w", one (0x0500), one (0x0781), {D8_6, EP, R2}, 1, PROCESSOR_ALL }, -{ "sst.b", one (0x0380), one (0x0780), {R2, D7, EP}, 2, PROCESSOR_ALL }, -{ "sst.h", one (0x0480), one (0x0780), {R2, D8_7, EP}, 2, PROCESSOR_ALL }, -{ "sst.w", one (0x0501), one (0x0781), {R2, D8_6, EP}, 2, PROCESSOR_ALL }, - -{ "pushml", two (0x07e0, 0x0001), two (0xfff0, 0x0007), {LIST18_L}, 0, PROCESSOR_V850EA }, -{ "pushmh", two (0x07e0, 0x0003), two (0xfff0, 0x0007), {LIST18_H}, 0, PROCESSOR_V850EA }, -{ "popml", two (0x07f0, 0x0001), two (0xfff0, 0x0007), {LIST18_L}, 0, PROCESSOR_V850EA }, -{ "popmh", two (0x07f0, 0x0003), two (0xfff0, 0x0007), {LIST18_H}, 0, PROCESSOR_V850EA }, -{ "prepare", two (0x0780, 0x0003), two (0xffc0, 0x001f), {LIST12, IMM5, SP}, 0, PROCESSOR_NOT_V850 }, -{ "prepare", two (0x0780, 0x000b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16}, 0, PROCESSOR_NOT_V850 }, -{ "prepare", two (0x0780, 0x0013), two (0xffc0, 0x001f), {LIST12, IMM5, IMM16}, 0, PROCESSOR_NOT_V850 }, -{ "prepare", two (0x0780, 0x001b), two (0xffc0, 0x001f), {LIST12, IMM5, IMM32}, 0, PROCESSOR_NOT_V850 }, -{ "prepare", two (0x0780, 0x0001), two (0xffc0, 0x001f), {LIST12, IMM5}, 0, PROCESSOR_NOT_V850 }, -{ "dispose", one (0x0640), one (0xffc0), {IMM5, LIST12, R2DISPOSE},0, PROCESSOR_NOT_V850 }, -{ "dispose", two (0x0640, 0x0000), two (0xffc0, 0x001f), {IMM5, LIST12}, 0, PROCESSOR_NOT_V850 }, - -{ "ld.b", two (0x0700, 0x0000), two (0x07e0, 0x0000), {D16, R1, R2}, 1, PROCESSOR_ALL }, -{ "ld.h", two (0x0720, 0x0000), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1, PROCESSOR_ALL }, -{ "ld.w", two (0x0720, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2}, 1, PROCESSOR_ALL }, -{ "ld.bu", two (0x0780, 0x0001), two (0x07c0, 0x0001), {D16_16, R1, R2_NOTR0}, 1, PROCESSOR_NOT_V850 }, -{ "ld.hu", two (0x07e0, 0x0001), two (0x07e0, 0x0001), {D16_15, R1, R2_NOTR0}, 1, PROCESSOR_NOT_V850 }, -{ "st.b", two (0x0740, 0x0000), two (0x07e0, 0x0000), {R2, D16, R1}, 2, PROCESSOR_ALL }, -{ "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL }, -{ "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL }, - -/* byte swap/extend instructions */ -{ "zxb", one (0x0080), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, -{ "zxh", one (0x00c0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, -{ "sxb", one (0x00a0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, -{ "sxh", one (0x00e0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, -{ "bsh", two (0x07e0, 0x0342), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 }, - -/* jump table instructions */ -{ "switch", one (0x0040), one (0xffe0), {R1}, 1, PROCESSOR_NOT_V850 }, -{ "callt", one (0x0200), one (0xffc0), {I6}, 0, PROCESSOR_NOT_V850 }, -{ "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 }, - -/* arithmetic operation instructions */ -{ "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_ALL }, -{ "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 }, - -{ "mul", two (0x07e0, 0x0220), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "mul", two (0x07e0, 0x0240), two (0x07e0, 0x07c3), {I9, R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "mulu", two (0x07e0, 0x0222), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "mulu", two (0x07e0, 0x0242), two (0x07e0, 0x07c3), {U9, R2, R3}, 0, PROCESSOR_NOT_V850 }, - -{ "div", two (0x07e0, 0x02c0), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "divu", two (0x07e0, 0x02c2), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "divhu", two (0x07e0, 0x0282), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "divh", two (0x07e0, 0x0280), two (0x07e0, 0x07ff), {R1, R2, R3}, 0, PROCESSOR_NOT_V850 }, -{ "divh", OP (0x02), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, - -{ "divhn", two (0x07e0, 0x0280), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, -{ "divhun", two (0x07e0, 0x0282), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, -{ "divn", two (0x07e0, 0x02c0), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, -{ "divun", two (0x07e0, 0x02c2), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, -{ "sdivhn", two (0x07e0, 0x0180), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, -{ "sdivhun", two (0x07e0, 0x0182), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, -{ "sdivn", two (0x07e0, 0x01c0), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, -{ "sdivun", two (0x07e0, 0x01c2), two (0x07e0, 0x07c3), {I5DIV, R1, R2, R3}, 0, PROCESSOR_V850EA }, - -{ "nop", one (0x00), one (0xffff), {0}, 0, PROCESSOR_ALL }, -{ "mov", OP (0x10), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "mov", one (0x0620), one (0xffe0), {IMM32, R1_NOTR0}, 0, PROCESSOR_NOT_V850 }, -{ "mov", OP (0x00), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "movea", OP (0x31), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "movhi", OP (0x32), OP_MASK, {I16U, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "add", OP (0x0e), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "add", OP (0x12), OP_MASK, IF2, 0, PROCESSOR_ALL }, -{ "addi", OP (0x30), OP_MASK, IF6, 0, PROCESSOR_ALL }, -{ "sub", OP (0x0d), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "subr", OP (0x0c), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "mulh", OP (0x17), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "mulh", OP (0x07), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "mulhi", OP (0x37), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL }, - -/* saturated operation instructions */ -{ "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL }, -{ "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL }, - -/* logical operation instructions */ -{ "tst", OP (0x0b), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "or", OP (0x08), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "ori", OP (0x34), OP_MASK, IF6U, 0, PROCESSOR_ALL }, -{ "and", OP (0x0a), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "andi", OP (0x36), OP_MASK, IF6U, 0, PROCESSOR_ALL }, -{ "xor", OP (0x09), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "xori", OP (0x35), OP_MASK, IF6U, 0, PROCESSOR_ALL }, -{ "not", OP (0x01), OP_MASK, IF1, 0, PROCESSOR_ALL }, -{ "sar", OP (0x15), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, -{ "sar", two (0x07e0, 0x00a0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, -{ "shl", OP (0x16), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, -{ "shl", two (0x07e0, 0x00c0), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, -{ "shr", OP (0x14), OP_MASK, {I5U, R2}, 0, PROCESSOR_ALL }, -{ "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL }, -{ "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_NOT_V850 }, - -/* branch instructions */ - /* signed integer */ -{ "bgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "blt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "ble", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* unsigned integer */ -{ "bh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* common */ -{ "be", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* others */ -{ "bv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "br", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "bsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - -/* Branch macros. - - We use the short form in the opcode/mask fields. The assembler - will twiddle bits as necessary if the long form is needed. */ - - /* signed integer */ -{ "jgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jlt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jle", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* unsigned integer */ -{ "jh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* common */ -{ "je", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - /* others */ -{ "jv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jp", BOP (0xc), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jc", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jnc", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jz", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jnz", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jsa", BOP (0xd), BOP_MASK, IF3, 0, PROCESSOR_ALL }, -{ "jbr", BOP (0x5), BOP_MASK, IF3, 0, PROCESSOR_ALL }, - -{ "jr", one (0x0780), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL }, -{ "jarl", one (0x0780), two (0x07c0, 0x0001), {D22, R2}, 0, PROCESSOR_ALL}, - -/* bit manipulation instructions */ -{ "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, -{ "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, -{ "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, -{ "not1", two (0x07e0, 0x00e2), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, -{ "clr1", two (0x87c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, -{ "clr1", two (0x07e0, 0x00e4), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, -{ "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL }, -{ "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 }, - -/* special instructions */ -{ "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, -{ "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, -{ "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, -{ "reti", two (0x07e0, 0x0140), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL }, -{ "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0, PROCESSOR_ALL }, -{ "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0xffff), {R1, SR2}, 0, PROCESSOR_ALL }, -{ "stsr", two (0x07e0, 0x0040), two (0x07e0, 0xffff), {SR1, R2}, 0, PROCESSOR_ALL }, -{ 0, 0, 0, {0}, 0, 0 }, - -} ; - -const int v850_num_opcodes = - sizeof (v850_opcodes) / sizeof (v850_opcodes[0]); - diff --git a/contrib/binutils/opcodes/z8k-dis.c b/contrib/binutils/opcodes/z8k-dis.c deleted file mode 100644 index 091d937..0000000 --- a/contrib/binutils/opcodes/z8k-dis.c +++ /dev/null @@ -1,587 +0,0 @@ -/* Disassemble z8000 code. - Copyright 1992, 1993, 1998, 2000, 2001 - Free Software Foundation, Inc. - -This file is part of GNU Binutils. - -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -#include "sysdep.h" -#include "dis-asm.h" - -#define DEFINE_TABLE -#include "z8k-opc.h" - -#include <setjmp.h> - -typedef struct { - /* These are all indexed by nibble number (i.e only every other entry - of bytes is used, and every 4th entry of words). */ - unsigned char nibbles[24]; - unsigned char bytes[24]; - unsigned short words[24]; - - /* Nibble number of first word not yet fetched. */ - int max_fetched; - bfd_vma insn_start; - jmp_buf bailout; - - long tabl_index; - char instr_asmsrc[80]; - unsigned long arg_reg[0x0f]; - unsigned long immediate; - unsigned long displacement; - unsigned long address; - unsigned long cond_code; - unsigned long ctrl_code; - unsigned long flags; - unsigned long interrupts; -} instr_data_s; - -static int fetch_data PARAMS ((struct disassemble_info *, int)); - - -/* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) - to ADDR (exclusive) are valid. Returns 1 for success, longjmps - on error. */ -#define FETCH_DATA(info, nibble) \ - ((nibble) < ((instr_data_s *) (info->private_data))->max_fetched \ - ? 1 : fetch_data ((info), (nibble))) - -static int -fetch_data (info, nibble) - struct disassemble_info *info; - int nibble; -{ - unsigned char mybuf[20]; - int status; - instr_data_s *priv = (instr_data_s *) info->private_data; - - if ((nibble % 4) != 0) - abort (); - - status = (*info->read_memory_func) (priv->insn_start, - (bfd_byte *) mybuf, - nibble / 2, - info); - if (status != 0) - { - (*info->memory_error_func) (status, priv->insn_start, info); - longjmp (priv->bailout, 1); - } - - { - int i; - unsigned char *p = mybuf; - - for (i = 0; i < nibble;) - { - priv->words[i] = (p[0] << 8) | p[1]; - - priv->bytes[i] = *p; - priv->nibbles[i++] = *p >> 4; - priv->nibbles[i++] = *p & 0xf; - - ++p; - priv->bytes[i] = *p; - priv->nibbles[i++] = *p >> 4; - priv->nibbles[i++] = *p & 0xf; - - ++p; - } - } - priv->max_fetched = nibble; - return 1; -} - -static char *codes[16] = { - "f", - "lt", - "le", - "ule", - "ov/pe", - "mi", - "eq", - "c/ult", - "t", - "ge", - "gt", - "ugt", - "nov/po", - "pl", - "ne", - "nc/uge" -}; - -static char *ctrl_names[8] = { - "<invld>", - "flags", - "fcw", - "refresh", - "psapseg", - "psapoff", - "nspseg", - "nspoff" -}; - -static int seg_length; -static int print_insn_z8k PARAMS ((bfd_vma, disassemble_info *, int)); -int z8k_lookup_instr PARAMS ((unsigned char *, disassemble_info *)); -static void output_instr - PARAMS ((instr_data_s *, unsigned long, disassemble_info *)); -static void unpack_instr PARAMS ((instr_data_s *, int, disassemble_info *)); -static void unparse_instr PARAMS ((instr_data_s *, int)); - -static int -print_insn_z8k (addr, info, is_segmented) - bfd_vma addr; - disassemble_info *info; - int is_segmented; -{ - instr_data_s instr_data; - - info->private_data = (PTR) &instr_data; - instr_data.max_fetched = 0; - instr_data.insn_start = addr; - if (setjmp (instr_data.bailout) != 0) - /* Error return. */ - return -1; - - instr_data.tabl_index = z8k_lookup_instr (instr_data.nibbles, info); - if (instr_data.tabl_index > 0) - { - unpack_instr (&instr_data, is_segmented, info); - unparse_instr (&instr_data, is_segmented); - output_instr (&instr_data, addr, info); - return z8k_table[instr_data.tabl_index].length + seg_length; - } - else - { - FETCH_DATA (info, 4); - (*info->fprintf_func) (info->stream, ".word %02x%02x", - instr_data.bytes[0], instr_data.bytes[2]); - return 2; - } -} - -int -print_insn_z8001 (addr, info) - bfd_vma addr; - disassemble_info *info; -{ - return print_insn_z8k (addr, info, 1); -} - -int -print_insn_z8002 (addr, info) - bfd_vma addr; - disassemble_info *info; -{ - return print_insn_z8k (addr, info, 0); -} - -int -z8k_lookup_instr (nibbles, info) - unsigned char *nibbles; - disassemble_info *info; -{ - - int nibl_index, tabl_index; - int nibl_matched; - unsigned short instr_nibl; - unsigned short tabl_datum, datum_class, datum_value; - - nibl_matched = 0; - tabl_index = 0; - while (!nibl_matched && z8k_table[tabl_index].name) - { - nibl_matched = 1; - for (nibl_index = 0; - nibl_index < z8k_table[tabl_index].length * 2 && nibl_matched; - nibl_index++) - { - if ((nibl_index % 4) == 0) - /* Fetch one word at a time. */ - FETCH_DATA (info, nibl_index + 4); - instr_nibl = nibbles[nibl_index]; - - tabl_datum = z8k_table[tabl_index].byte_info[nibl_index]; - datum_class = tabl_datum & CLASS_MASK; - datum_value = ~CLASS_MASK & tabl_datum; - - switch (datum_class) - { - case CLASS_BIT: - if (datum_value != instr_nibl) - nibl_matched = 0; - break; - case CLASS_00II: - if (!((~instr_nibl) & 0x4)) - nibl_matched = 0; - break; - case CLASS_01II: - if (!(instr_nibl & 0x4)) - nibl_matched = 0; - break; - case CLASS_0CCC: - if (!((~instr_nibl) & 0x8)) - nibl_matched = 0; - break; - case CLASS_1CCC: - if (!(instr_nibl & 0x8)) - nibl_matched = 0; - break; - case CLASS_0DISP7: - if (!((~instr_nibl) & 0x8)) - nibl_matched = 0; - nibl_index += 1; - break; - case CLASS_1DISP7: - if (!(instr_nibl & 0x8)) - nibl_matched = 0; - nibl_index += 1; - break; - case CLASS_REGN0: - if (instr_nibl == 0) - nibl_matched = 0; - break; - case CLASS_BIT_1OR2: - if ((instr_nibl | 0x2) != (datum_value | 0x2)) - nibl_matched = 0; - break; - default: - break; - } - } - if (nibl_matched) - { - return tabl_index; - } - - tabl_index++; - } - return -1; -} - -static void -output_instr (instr_data, addr, info) - instr_data_s *instr_data; - unsigned long addr ATTRIBUTE_UNUSED; - disassemble_info *info; -{ - int loop, loop_limit; - char tmp_str[20]; - char out_str[100]; - - strcpy (out_str, "\t"); - - loop_limit = (z8k_table[instr_data->tabl_index].length + seg_length) * 2; - FETCH_DATA (info, loop_limit); - for (loop = 0; loop < loop_limit; loop++) - { - sprintf (tmp_str, "%x", instr_data->nibbles[loop]); - strcat (out_str, tmp_str); - } - - while (loop++ < 8) - { - strcat (out_str, " "); - } - - strcat (out_str, instr_data->instr_asmsrc); - - (*info->fprintf_func) (info->stream, "%s", out_str); -} - -static void -unpack_instr (instr_data, is_segmented, info) - instr_data_s *instr_data; - int is_segmented; - disassemble_info *info; -{ - int nibl_count, loop; - unsigned short instr_nibl, instr_byte, instr_word; - long instr_long; - unsigned int tabl_datum, datum_class; - unsigned short datum_value; - - nibl_count = 0; - loop = 0; - seg_length = 0; - while (z8k_table[instr_data->tabl_index].byte_info[loop] != 0) - { - FETCH_DATA (info, nibl_count + 4 - (nibl_count % 4)); - instr_nibl = instr_data->nibbles[nibl_count]; - instr_byte = instr_data->bytes[nibl_count & ~1]; - instr_word = instr_data->words[nibl_count & ~3]; - - tabl_datum = z8k_table[instr_data->tabl_index].byte_info[loop]; - datum_class = tabl_datum & CLASS_MASK; - datum_value = tabl_datum & ~CLASS_MASK; - - switch (datum_class) - { - case CLASS_DISP: - switch (datum_value) - { - case ARG_DISP16: - instr_data->displacement = instr_data->insn_start + 4 - + (signed short) (instr_word & 0xffff); - nibl_count += 3; - break; - case ARG_DISP12: - if (instr_word & 0x800) - { - /* neg. 12 bit displacement */ - instr_data->displacement = instr_data->insn_start + 2 - - (signed short) ((instr_word & 0xfff) | 0xf000) * 2; - } - else - { - instr_data->displacement = instr_data->insn_start + 2 - - (instr_word & 0x0fff) * 2; - } - nibl_count += 2; - break; - default: - break; - } - break; - case CLASS_IMM: - switch (datum_value) - { - case ARG_IMM4: - instr_data->immediate = instr_nibl; - break; - case ARG_NIM8: - instr_data->immediate = (-instr_byte); - nibl_count += 1; - break; - case ARG_IMM8: - instr_data->immediate = instr_byte; - nibl_count += 1; - break; - case ARG_IMM16: - instr_data->immediate = instr_word; - nibl_count += 3; - break; - case ARG_IMM32: - FETCH_DATA (info, nibl_count + 8); - instr_long = (instr_data->words[nibl_count] << 16) - | (instr_data->words[nibl_count + 4]); - instr_data->immediate = instr_long; - nibl_count += 7; - break; - case ARG_IMMN: - instr_data->immediate = instr_nibl - 1; - break; - case ARG_IMM4M1: - instr_data->immediate = instr_nibl + 1; - break; - case ARG_IMM_1: - instr_data->immediate = 1; - break; - case ARG_IMM_2: - instr_data->immediate = 2; - break; - case ARG_IMM2: - instr_data->immediate = instr_nibl & 0x3; - break; - default: - break; - } - break; - case CLASS_CC: - instr_data->cond_code = instr_nibl; - break; - case CLASS_ADDRESS: - if (is_segmented) - { - if (instr_nibl & 0x8) - { - FETCH_DATA (info, nibl_count + 8); - instr_long = (instr_data->words[nibl_count] << 16) - | (instr_data->words[nibl_count + 4]); - instr_data->address = ((instr_word & 0x7f00) << 8) - + (instr_long & 0xffff); - nibl_count += 7; - seg_length = 2; - } - else - { - instr_data->address = ((instr_word & 0x7f00) << 8) - + (instr_word & 0x00ff); - nibl_count += 3; - } - } - else - { - instr_data->address = instr_word; - nibl_count += 3; - } - break; - case CLASS_0CCC: - case CLASS_1CCC: - instr_data->ctrl_code = instr_nibl & 0x7; - break; - case CLASS_0DISP7: - instr_data->displacement = - instr_data->insn_start + 2 - (instr_byte & 0x7f) * 2; - nibl_count += 1; - break; - case CLASS_1DISP7: - instr_data->displacement = - instr_data->insn_start + 2 - (instr_byte & 0x7f) * 2; - nibl_count += 1; - break; - case CLASS_01II: - instr_data->interrupts = instr_nibl & 0x3; - break; - case CLASS_00II: - instr_data->interrupts = instr_nibl & 0x3; - break; - case CLASS_BIT: - instr_data->ctrl_code = instr_nibl & 0x7; - break; - case CLASS_FLAGS: - instr_data->flags = instr_nibl; - break; - case CLASS_REG: - instr_data->arg_reg[datum_value] = instr_nibl; - break; - case CLASS_REGN0: - instr_data->arg_reg[datum_value] = instr_nibl; - break; - case CLASS_DISP8: - instr_data->displacement = - instr_data->insn_start + 2 + (signed char) instr_byte * 2; - nibl_count += 1; - break; - default: - abort (); - break; - } - - loop += 1; - nibl_count += 1; - } -} - -static void -unparse_instr (instr_data, is_segmented) - instr_data_s *instr_data; - int is_segmented; -{ - unsigned short datum_value; - unsigned int tabl_datum, datum_class; - int loop, loop_limit; - char out_str[80], tmp_str[25]; - - sprintf (out_str, "\t%s\t", z8k_table[instr_data->tabl_index].name); - - loop_limit = z8k_table[instr_data->tabl_index].noperands; - for (loop = 0; loop < loop_limit; loop++) - { - if (loop) - strcat (out_str, ","); - - tabl_datum = z8k_table[instr_data->tabl_index].arg_info[loop]; - datum_class = tabl_datum & CLASS_MASK; - datum_value = tabl_datum & ~CLASS_MASK; - - switch (datum_class) - { - case CLASS_X: - sprintf (tmp_str, "0x%0lx(R%ld)", instr_data->address, - instr_data->arg_reg[datum_value]); - strcat (out_str, tmp_str); - break; - case CLASS_BA: - sprintf (tmp_str, "r%ld(#%lx)", instr_data->arg_reg[datum_value], - instr_data->immediate); - strcat (out_str, tmp_str); - break; - case CLASS_BX: - sprintf (tmp_str, "r%ld(R%ld)", instr_data->arg_reg[datum_value], - instr_data->arg_reg[ARG_RX]); - strcat (out_str, tmp_str); - break; - case CLASS_DISP: - sprintf (tmp_str, "0x%0lx", instr_data->displacement); - strcat (out_str, tmp_str); - break; - case CLASS_IMM: - sprintf (tmp_str, "#0x%0lx", instr_data->immediate); - strcat (out_str, tmp_str); - break; - case CLASS_CC: - sprintf (tmp_str, "%s", codes[instr_data->cond_code]); - strcat (out_str, tmp_str); - break; - case CLASS_CTRL: - sprintf (tmp_str, "%s", ctrl_names[instr_data->ctrl_code]); - strcat (out_str, tmp_str); - break; - case CLASS_DA: - case CLASS_ADDRESS: - sprintf (tmp_str, "0x%0lx", instr_data->address); - strcat (out_str, tmp_str); - break; - case CLASS_IR: - if (is_segmented) - sprintf (tmp_str, "@rr%ld", instr_data->arg_reg[datum_value]); - else - sprintf (tmp_str, "@r%ld", instr_data->arg_reg[datum_value]); - strcat (out_str, tmp_str); - break; - case CLASS_FLAGS: - sprintf (tmp_str, "0x%0lx", instr_data->flags); - strcat (out_str, tmp_str); - break; - case CLASS_REG_BYTE: - if (instr_data->arg_reg[datum_value] >= 0x8) - sprintf (tmp_str, "rl%ld", - instr_data->arg_reg[datum_value] - 0x8); - else - sprintf (tmp_str, "rh%ld", instr_data->arg_reg[datum_value]); - strcat (out_str, tmp_str); - break; - case CLASS_REG_WORD: - sprintf (tmp_str, "r%ld", instr_data->arg_reg[datum_value]); - strcat (out_str, tmp_str); - break; - case CLASS_REG_QUAD: - sprintf (tmp_str, "rq%ld", instr_data->arg_reg[datum_value]); - strcat (out_str, tmp_str); - break; - case CLASS_REG_LONG: - sprintf (tmp_str, "rr%ld", instr_data->arg_reg[datum_value]); - strcat (out_str, tmp_str); - break; - case CLASS_PR: - if (is_segmented) - sprintf (tmp_str, "rr%ld", instr_data->arg_reg[datum_value]); - else - sprintf (tmp_str, "r%ld", instr_data->arg_reg[datum_value]); - strcat (out_str, tmp_str); - break; - default: - abort (); - break; - } - } - - strcpy (instr_data->instr_asmsrc, out_str); -} diff --git a/contrib/binutils/opcodes/z8k-opc.h b/contrib/binutils/opcodes/z8k-opc.h deleted file mode 100644 index c62867c..0000000 --- a/contrib/binutils/opcodes/z8k-opc.h +++ /dev/null @@ -1,4479 +0,0 @@ - /* THIS FILE IS AUTOMAGICALLY GENERATED, DON'T EDIT IT */ -#define ARG_MASK 0x0f -#define ARG_SRC 0x01 -#define ARG_DST 0x02 -#define ARG_RS 0x01 -#define ARG_RD 0x02 -#define ARG_RA 0x03 -#define ARG_RB 0x04 -#define ARG_RR 0x05 -#define ARG_RX 0x06 -#define ARG_IMM4 0x01 -#define ARG_IMM8 0x02 -#define ARG_IMM16 0x03 -#define ARG_IMM32 0x04 -#define ARG_IMMN 0x05 -#define ARG_IMMNMINUS1 0x05 -#define ARG_IMM_1 0x06 -#define ARG_IMM_2 0x07 -#define ARG_DISP16 0x08 -#define ARG_NIM8 0x09 -#define ARG_IMM2 0x0a -#define ARG_IMM1OR2 0x0b -#define ARG_DISP12 0x0b -#define ARG_DISP8 0x0c -#define ARG_IMM4M1 0x0d -#define CLASS_MASK 0x1fff0 -#define CLASS_X 0x10 -#define CLASS_BA 0x20 -#define CLASS_DA 0x30 -#define CLASS_BX 0x40 -#define CLASS_DISP 0x50 -#define CLASS_IMM 0x60 -#define CLASS_CC 0x70 -#define CLASS_CTRL 0x80 -#define CLASS_ADDRESS 0xd0 -#define CLASS_0CCC 0xe0 -#define CLASS_1CCC 0xf0 -#define CLASS_0DISP7 0x100 -#define CLASS_1DISP7 0x200 -#define CLASS_01II 0x300 -#define CLASS_00II 0x400 -#define CLASS_BIT 0x500 -#define CLASS_FLAGS 0x600 -#define CLASS_IR 0x700 -#define CLASS_DISP8 0x800 -#define CLASS_BIT_1OR2 0x900 -#define CLASS_REG 0x7000 -#define CLASS_REG_BYTE 0x2000 -#define CLASS_REG_WORD 0x3000 -#define CLASS_REG_QUAD 0x4000 -#define CLASS_REG_LONG 0x5000 -#define CLASS_REGN0 0x8000 -#define CLASS_PR 0x10000 -#define OPC_adc 0 -#define OPC_adcb 1 -#define OPC_add 2 -#define OPC_addb 3 -#define OPC_addl 4 -#define OPC_and 5 -#define OPC_andb 6 -#define OPC_bit 7 -#define OPC_bitb 8 -#define OPC_call 9 -#define OPC_calr 10 -#define OPC_clr 11 -#define OPC_clrb 12 -#define OPC_com 13 -#define OPC_comb 14 -#define OPC_comflg 15 -#define OPC_cp 16 -#define OPC_cpb 17 -#define OPC_cpd 18 -#define OPC_cpdb 19 -#define OPC_cpdr 20 -#define OPC_cpdrb 21 -#define OPC_cpi 22 -#define OPC_cpib 23 -#define OPC_cpir 24 -#define OPC_cpirb 25 -#define OPC_cpl 26 -#define OPC_cpsd 27 -#define OPC_cpsdb 28 -#define OPC_cpsdr 29 -#define OPC_cpsdrb 30 -#define OPC_cpsi 31 -#define OPC_cpsib 32 -#define OPC_cpsir 33 -#define OPC_cpsirb 34 -#define OPC_dab 35 -#define OPC_dbjnz 36 -#define OPC_dec 37 -#define OPC_decb 38 -#define OPC_di 39 -#define OPC_div 40 -#define OPC_divl 41 -#define OPC_djnz 42 -#define OPC_ei 43 -#define OPC_ex 44 -#define OPC_exb 45 -#define OPC_exts 46 -#define OPC_extsb 47 -#define OPC_extsl 48 -#define OPC_halt 49 -#define OPC_in 50 -#define OPC_inb 51 -#define OPC_inc 52 -#define OPC_incb 53 -#define OPC_ind 54 -#define OPC_indb 55 -#define OPC_inib 56 -#define OPC_inibr 57 -#define OPC_iret 58 -#define OPC_jp 59 -#define OPC_jr 60 -#define OPC_ld 61 -#define OPC_lda 62 -#define OPC_ldar 63 -#define OPC_ldb 64 -#define OPC_ldctl 65 -#define OPC_ldir 66 -#define OPC_ldirb 67 -#define OPC_ldk 68 -#define OPC_ldl 69 -#define OPC_ldm 70 -#define OPC_ldps 71 -#define OPC_ldr 72 -#define OPC_ldrb 73 -#define OPC_ldrl 74 -#define OPC_mbit 75 -#define OPC_mreq 76 -#define OPC_mres 77 -#define OPC_mset 78 -#define OPC_mult 79 -#define OPC_multl 80 -#define OPC_neg 81 -#define OPC_negb 82 -#define OPC_nop 83 -#define OPC_or 84 -#define OPC_orb 85 -#define OPC_out 86 -#define OPC_outb 87 -#define OPC_outd 88 -#define OPC_outdb 89 -#define OPC_outib 90 -#define OPC_outibr 91 -#define OPC_pop 92 -#define OPC_popl 93 -#define OPC_push 94 -#define OPC_pushl 95 -#define OPC_res 96 -#define OPC_resb 97 -#define OPC_resflg 98 -#define OPC_ret 99 -#define OPC_rl 100 -#define OPC_rlb 101 -#define OPC_rlc 102 -#define OPC_rlcb 103 -#define OPC_rldb 104 -#define OPC_rr 105 -#define OPC_rrb 106 -#define OPC_rrc 107 -#define OPC_rrcb 108 -#define OPC_rrdb 109 -#define OPC_sbc 110 -#define OPC_sbcb 111 -#define OPC_sda 112 -#define OPC_sdab 113 -#define OPC_sdal 114 -#define OPC_sdl 115 -#define OPC_sdlb 116 -#define OPC_sdll 117 -#define OPC_set 118 -#define OPC_setb 119 -#define OPC_setflg 120 -#define OPC_sinb 121 -#define OPC_sind 122 -#define OPC_sindb 123 -#define OPC_sinib 124 -#define OPC_sinibr 125 -#define OPC_sla 126 -#define OPC_slab 127 -#define OPC_slal 128 -#define OPC_sll 129 -#define OPC_sllb 130 -#define OPC_slll 131 -#define OPC_sout 132 -#define OPC_soutb 133 -#define OPC_soutd 134 -#define OPC_soutdb 135 -#define OPC_soutib 136 -#define OPC_soutibr 137 -#define OPC_sra 138 -#define OPC_srab 139 -#define OPC_sral 140 -#define OPC_srl 141 -#define OPC_srlb 142 -#define OPC_srll 143 -#define OPC_sub 144 -#define OPC_subb 145 -#define OPC_subl 146 -#define OPC_tcc 147 -#define OPC_tccb 148 -#define OPC_test 149 -#define OPC_testb 150 -#define OPC_testl 151 -#define OPC_trdb 152 -#define OPC_trdrb 153 -#define OPC_trib 154 -#define OPC_trirb 155 -#define OPC_trtdrb 156 -#define OPC_trtib 157 -#define OPC_trtirb 158 -#define OPC_trtrb 159 -#define OPC_tset 160 -#define OPC_tsetb 161 -#define OPC_xor 162 -#define OPC_xorb 163 -#define OPC_ldd 164 -#define OPC_lddb 165 -#define OPC_lddr 166 -#define OPC_lddrb 167 -#define OPC_ldi 168 -#define OPC_ldib 169 -#define OPC_sc 170 -#define OPC_bpt 171 -#define OPC_ext0e 172 -#define OPC_ext0f 172 -#define OPC_ext8e 172 -#define OPC_ext8f 172 -#define OPC_rsvd36 172 -#define OPC_rsvd38 172 -#define OPC_rsvd78 172 -#define OPC_rsvd7e 172 -#define OPC_rsvd9d 172 -#define OPC_rsvd9f 172 -#define OPC_rsvdb9 172 -#define OPC_rsvdbf 172 -#define OPC_outi 173 -#define OPC_ldctlb 174 -#define OPC_sin 175 -#define OPC_trtdb 176 -typedef struct { -#ifdef NICENAMES -char *nicename; -int type; -int cycles; -int flags; -#endif -char *name; -unsigned char opcode; -void (*func) PARAMS ((void)); -unsigned int arg_info[4]; -unsigned int byte_info[10]; -int noperands; -int length; -int idx; -} opcode_entry_type; -#ifdef DEFINE_TABLE -opcode_entry_type z8k_table[] = { - - -/* 1011 0101 ssss dddd *** adc rd,rs */ -{ -#ifdef NICENAMES -"adc rd,rs",16,5, -0x3c, -#endif -"adc",OPC_adc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+5,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,0}, - - -/* 1011 0100 ssss dddd *** adcb rbd,rbs */ -{ -#ifdef NICENAMES -"adcb rbd,rbs",8,5, -0x3f, -#endif -"adcb",OPC_adcb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+4,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,1}, - - -/* 0000 0001 ssN0 dddd *** add rd,@rs */ -{ -#ifdef NICENAMES -"add rd,@rs",16,7, -0x3c, -#endif -"add",OPC_add,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,2}, - - -/* 0100 0001 0000 dddd address_src *** add rd,address_src */ -{ -#ifdef NICENAMES -"add rd,address_src",16,9, -0x3c, -#endif -"add",OPC_add,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,3}, - - -/* 0100 0001 ssN0 dddd address_src *** add rd,address_src(rs) */ -{ -#ifdef NICENAMES -"add rd,address_src(rs)",16,10, -0x3c, -#endif -"add",OPC_add,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,4}, - - -/* 0000 0001 0000 dddd imm16 *** add rd,imm16 */ -{ -#ifdef NICENAMES -"add rd,imm16",16,7, -0x3c, -#endif -"add",OPC_add,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,5}, - - -/* 1000 0001 ssss dddd *** add rd,rs */ -{ -#ifdef NICENAMES -"add rd,rs",16,4, -0x3c, -#endif -"add",OPC_add,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+1,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,6}, - - -/* 0000 0000 ssN0 dddd *** addb rbd,@rs */ -{ -#ifdef NICENAMES -"addb rbd,@rs",8,7, -0x3f, -#endif -"addb",OPC_addb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,7}, - - -/* 0100 0000 0000 dddd address_src *** addb rbd,address_src */ -{ -#ifdef NICENAMES -"addb rbd,address_src",8,9, -0x3f, -#endif -"addb",OPC_addb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,8}, - - -/* 0100 0000 ssN0 dddd address_src *** addb rbd,address_src(rs) */ -{ -#ifdef NICENAMES -"addb rbd,address_src(rs)",8,10, -0x3f, -#endif -"addb",OPC_addb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,9}, - - -/* 0000 0000 0000 dddd imm8 imm8 *** addb rbd,imm8 */ -{ -#ifdef NICENAMES -"addb rbd,imm8",8,7, -0x3f, -#endif -"addb",OPC_addb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,10}, - - -/* 1000 0000 ssss dddd *** addb rbd,rbs */ -{ -#ifdef NICENAMES -"addb rbd,rbs",8,4, -0x3f, -#endif -"addb",OPC_addb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,11}, - - -/* 0001 0110 ssN0 dddd *** addl rrd,@rs */ -{ -#ifdef NICENAMES -"addl rrd,@rs",32,14, -0x3c, -#endif -"addl",OPC_addl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,12}, - - -/* 0101 0110 0000 dddd address_src *** addl rrd,address_src */ -{ -#ifdef NICENAMES -"addl rrd,address_src",32,15, -0x3c, -#endif -"addl",OPC_addl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,13}, - - -/* 0101 0110 ssN0 dddd address_src *** addl rrd,address_src(rs) */ -{ -#ifdef NICENAMES -"addl rrd,address_src(rs)",32,16, -0x3c, -#endif -"addl",OPC_addl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,14}, - - -/* 0001 0110 0000 dddd imm32 *** addl rrd,imm32 */ -{ -#ifdef NICENAMES -"addl rrd,imm32",32,14, -0x3c, -#endif -"addl",OPC_addl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, - {CLASS_BIT+1,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,15}, - - -/* 1001 0110 ssss dddd *** addl rrd,rrs */ -{ -#ifdef NICENAMES -"addl rrd,rrs",32,8, -0x3c, -#endif -"addl",OPC_addl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+6,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,16}, - - -/* 0000 0111 ssN0 dddd *** and rd,@rs */ -{ -#ifdef NICENAMES -"and rd,@rs",16,7, -0x18, -#endif -"and",OPC_and,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,17}, - - -/* 0100 0111 0000 dddd address_src *** and rd,address_src */ -{ -#ifdef NICENAMES -"and rd,address_src",16,9, -0x18, -#endif -"and",OPC_and,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,18}, - - -/* 0100 0111 ssN0 dddd address_src *** and rd,address_src(rs) */ -{ -#ifdef NICENAMES -"and rd,address_src(rs)",16,10, -0x18, -#endif -"and",OPC_and,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,19}, - - -/* 0000 0111 0000 dddd imm16 *** and rd,imm16 */ -{ -#ifdef NICENAMES -"and rd,imm16",16,7, -0x18, -#endif -"and",OPC_and,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,20}, - - -/* 1000 0111 ssss dddd *** and rd,rs */ -{ -#ifdef NICENAMES -"and rd,rs",16,4, -0x18, -#endif -"and",OPC_and,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+7,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,21}, - - -/* 0000 0110 ssN0 dddd *** andb rbd,@rs */ -{ -#ifdef NICENAMES -"andb rbd,@rs",8,7, -0x1c, -#endif -"andb",OPC_andb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,22}, - - -/* 0100 0110 0000 dddd address_src *** andb rbd,address_src */ -{ -#ifdef NICENAMES -"andb rbd,address_src",8,9, -0x1c, -#endif -"andb",OPC_andb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,23}, - - -/* 0100 0110 ssN0 dddd address_src *** andb rbd,address_src(rs) */ -{ -#ifdef NICENAMES -"andb rbd,address_src(rs)",8,10, -0x1c, -#endif -"andb",OPC_andb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,24}, - - -/* 0000 0110 0000 dddd imm8 imm8 *** andb rbd,imm8 */ -{ -#ifdef NICENAMES -"andb rbd,imm8",8,7, -0x1c, -#endif -"andb",OPC_andb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,25}, - - -/* 1000 0110 ssss dddd *** andb rbd,rbs */ -{ -#ifdef NICENAMES -"andb rbd,rbs",8,4, -0x1c, -#endif -"andb",OPC_andb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+6,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,26}, - - -/* 0010 0111 ddN0 imm4 *** bit @rd,imm4 */ -{ -#ifdef NICENAMES -"bit @rd,imm4",16,8, -0x10, -#endif -"bit",OPC_bit,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,27}, - - -/* 0110 0111 ddN0 imm4 address_dst *** bit address_dst(rd),imm4 */ -{ -#ifdef NICENAMES -"bit address_dst(rd),imm4",16,11, -0x10, -#endif -"bit",OPC_bit,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,28}, - - -/* 0110 0111 0000 imm4 address_dst *** bit address_dst,imm4 */ -{ -#ifdef NICENAMES -"bit address_dst,imm4",16,10, -0x10, -#endif -"bit",OPC_bit,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+7,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,29}, - - -/* 1010 0111 dddd imm4 *** bit rd,imm4 */ -{ -#ifdef NICENAMES -"bit rd,imm4",16,4, -0x10, -#endif -"bit",OPC_bit,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+0xa,CLASS_BIT+7,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,30}, - - -/* 0010 0111 0000 ssss 0000 dddd 0000 0000 *** bit rd,rs */ -{ -#ifdef NICENAMES -"bit rd,rs",16,10, -0x10, -#endif -"bit",OPC_bit,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,31}, - - -/* 0010 0110 ddN0 imm4 *** bitb @rd,imm4 */ -{ -#ifdef NICENAMES -"bitb @rd,imm4",8,8, -0x10, -#endif -"bitb",OPC_bitb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+6,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,32}, - - -/* 0110 0110 ddN0 imm4 address_dst *** bitb address_dst(rd),imm4 */ -{ -#ifdef NICENAMES -"bitb address_dst(rd),imm4",8,11, -0x10, -#endif -"bitb",OPC_bitb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+6,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,33}, - - -/* 0110 0110 0000 imm4 address_dst *** bitb address_dst,imm4 */ -{ -#ifdef NICENAMES -"bitb address_dst,imm4",8,10, -0x10, -#endif -"bitb",OPC_bitb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+6,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,34}, - - -/* 1010 0110 dddd imm4 *** bitb rbd,imm4 */ -{ -#ifdef NICENAMES -"bitb rbd,imm4",8,4, -0x10, -#endif -"bitb",OPC_bitb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+0xa,CLASS_BIT+6,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,35}, - - -/* 0010 0110 0000 ssss 0000 dddd 0000 0000 *** bitb rbd,rs */ -{ -#ifdef NICENAMES -"bitb rbd,rs",8,10, -0x10, -#endif -"bitb",OPC_bitb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,36}, - - -/* 0011 0110 0000 0000 *** bpt */ -{ -#ifdef NICENAMES -"bpt",8,2, -0x00, -#endif -"bpt",OPC_bpt,0,{0}, - {CLASS_BIT+3,CLASS_BIT+6,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},0,2,37}, - - -/* 0001 1111 ddN0 0000 *** call @rd */ -{ -#ifdef NICENAMES -"call @rd",32,10, -0x00, -#endif -"call",OPC_call,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+1,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,38}, - - -/* 0101 1111 0000 0000 address_dst *** call address_dst */ -{ -#ifdef NICENAMES -"call address_dst",32,12, -0x00, -#endif -"call",OPC_call,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+5,CLASS_BIT+0xf,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,39}, - - -/* 0101 1111 ddN0 0000 address_dst *** call address_dst(rd) */ -{ -#ifdef NICENAMES -"call address_dst(rd)",32,13, -0x00, -#endif -"call",OPC_call,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+5,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,40}, - - -/* 1101 disp12 *** calr disp12 */ -{ -#ifdef NICENAMES -"calr disp12",16,10, -0x00, -#endif -"calr",OPC_calr,0,{CLASS_DISP,}, - {CLASS_BIT+0xd,CLASS_DISP+(ARG_DISP12),0,0,0,0,0,0,0,},1,2,41}, - - -/* 0000 1101 ddN0 1000 *** clr @rd */ -{ -#ifdef NICENAMES -"clr @rd",16,8, -0x00, -#endif -"clr",OPC_clr,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,42}, - - -/* 0100 1101 0000 1000 address_dst *** clr address_dst */ -{ -#ifdef NICENAMES -"clr address_dst",16,11, -0x00, -#endif -"clr",OPC_clr,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,43}, - - -/* 0100 1101 ddN0 1000 address_dst *** clr address_dst(rd) */ -{ -#ifdef NICENAMES -"clr address_dst(rd)",16,12, -0x00, -#endif -"clr",OPC_clr,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,44}, - - -/* 1000 1101 dddd 1000 *** clr rd */ -{ -#ifdef NICENAMES -"clr rd",16,7, -0x00, -#endif -"clr",OPC_clr,0,{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,45}, - - -/* 0000 1100 ddN0 1000 *** clrb @rd */ -{ -#ifdef NICENAMES -"clrb @rd",8,8, -0x00, -#endif -"clrb",OPC_clrb,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,46}, - - -/* 0100 1100 0000 1000 address_dst *** clrb address_dst */ -{ -#ifdef NICENAMES -"clrb address_dst",8,11, -0x00, -#endif -"clrb",OPC_clrb,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,47}, - - -/* 0100 1100 ddN0 1000 address_dst *** clrb address_dst(rd) */ -{ -#ifdef NICENAMES -"clrb address_dst(rd)",8,12, -0x00, -#endif -"clrb",OPC_clrb,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,48}, - - -/* 1000 1100 dddd 1000 *** clrb rbd */ -{ -#ifdef NICENAMES -"clrb rbd",8,7, -0x00, -#endif -"clrb",OPC_clrb,0,{CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,49}, - - -/* 0000 1101 ddN0 0000 *** com @rd */ -{ -#ifdef NICENAMES -"com @rd",16,12, -0x18, -#endif -"com",OPC_com,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,50}, - - -/* 0100 1101 0000 0000 address_dst *** com address_dst */ -{ -#ifdef NICENAMES -"com address_dst",16,15, -0x18, -#endif -"com",OPC_com,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,51}, - - -/* 0100 1101 ddN0 0000 address_dst *** com address_dst(rd) */ -{ -#ifdef NICENAMES -"com address_dst(rd)",16,16, -0x18, -#endif -"com",OPC_com,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,52}, - - -/* 1000 1101 dddd 0000 *** com rd */ -{ -#ifdef NICENAMES -"com rd",16,7, -0x18, -#endif -"com",OPC_com,0,{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,53}, - - -/* 0000 1100 ddN0 0000 *** comb @rd */ -{ -#ifdef NICENAMES -"comb @rd",8,12, -0x1c, -#endif -"comb",OPC_comb,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,54}, - - -/* 0100 1100 0000 0000 address_dst *** comb address_dst */ -{ -#ifdef NICENAMES -"comb address_dst",8,15, -0x1c, -#endif -"comb",OPC_comb,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,55}, - - -/* 0100 1100 ddN0 0000 address_dst *** comb address_dst(rd) */ -{ -#ifdef NICENAMES -"comb address_dst(rd)",8,16, -0x1c, -#endif -"comb",OPC_comb,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,56}, - - -/* 1000 1100 dddd 0000 *** comb rbd */ -{ -#ifdef NICENAMES -"comb rbd",8,7, -0x1c, -#endif -"comb",OPC_comb,0,{CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,57}, - - -/* 1000 1101 flags 0101 *** comflg flags */ -{ -#ifdef NICENAMES -"comflg flags",16,7, -0x3c, -#endif -"comflg",OPC_comflg,0,{CLASS_FLAGS,}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_FLAGS,CLASS_BIT+5,0,0,0,0,0,},1,2,58}, - - -/* 0000 1101 ddN0 0001 imm16 *** cp @rd,imm16 */ -{ -#ifdef NICENAMES -"cp @rd,imm16",16,11, -0x3c, -#endif -"cp",OPC_cp,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,59}, - - -/* 0100 1101 ddN0 0001 address_dst imm16 *** cp address_dst(rd),imm16 */ -{ -#ifdef NICENAMES -"cp address_dst(rd),imm16",16,15, -0x3c, -#endif -"cp",OPC_cp,0,{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,60}, - - -/* 0100 1101 0000 0001 address_dst imm16 *** cp address_dst,imm16 */ -{ -#ifdef NICENAMES -"cp address_dst,imm16",16,14, -0x3c, -#endif -"cp",OPC_cp,0,{CLASS_DA+(ARG_DST),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,61}, - - -/* 0000 1011 ssN0 dddd *** cp rd,@rs */ -{ -#ifdef NICENAMES -"cp rd,@rs",16,7, -0x3c, -#endif -"cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,62}, - - -/* 0100 1011 0000 dddd address_src *** cp rd,address_src */ -{ -#ifdef NICENAMES -"cp rd,address_src",16,9, -0x3c, -#endif -"cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,63}, - - -/* 0100 1011 ssN0 dddd address_src *** cp rd,address_src(rs) */ -{ -#ifdef NICENAMES -"cp rd,address_src(rs)",16,10, -0x3c, -#endif -"cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,64}, - - -/* 0000 1011 0000 dddd imm16 *** cp rd,imm16 */ -{ -#ifdef NICENAMES -"cp rd,imm16",16,7, -0x3c, -#endif -"cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,65}, - - -/* 1000 1011 ssss dddd *** cp rd,rs */ -{ -#ifdef NICENAMES -"cp rd,rs",16,4, -0x3c, -#endif -"cp",OPC_cp,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,66}, - - -/* 0000 1100 ddN0 0001 imm8 imm8 *** cpb @rd,imm8 */ -{ -#ifdef NICENAMES -"cpb @rd,imm8",8,11, -0x3c, -#endif -"cpb",OPC_cpb,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,67}, - - -/* 0100 1100 ddN0 0001 address_dst imm8 imm8 *** cpb address_dst(rd),imm8 */ -{ -#ifdef NICENAMES -"cpb address_dst(rd),imm8",8,15, -0x3c, -#endif -"cpb",OPC_cpb,0,{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,68}, - - -/* 0100 1100 0000 0001 address_dst imm8 imm8 *** cpb address_dst,imm8 */ -{ -#ifdef NICENAMES -"cpb address_dst,imm8",8,14, -0x3c, -#endif -"cpb",OPC_cpb,0,{CLASS_DA+(ARG_DST),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+1,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,69}, - - -/* 0000 1010 ssN0 dddd *** cpb rbd,@rs */ -{ -#ifdef NICENAMES -"cpb rbd,@rs",8,7, -0x3c, -#endif -"cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,70}, - - -/* 0100 1010 0000 dddd address_src *** cpb rbd,address_src */ -{ -#ifdef NICENAMES -"cpb rbd,address_src",8,9, -0x3c, -#endif -"cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,71}, - - -/* 0100 1010 ssN0 dddd address_src *** cpb rbd,address_src(rs) */ -{ -#ifdef NICENAMES -"cpb rbd,address_src(rs)",8,10, -0x3c, -#endif -"cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,72}, - - -/* 0000 1010 0000 dddd imm8 imm8 *** cpb rbd,imm8 */ -{ -#ifdef NICENAMES -"cpb rbd,imm8",8,7, -0x3c, -#endif -"cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,73}, - - -/* 1000 1010 ssss dddd *** cpb rbd,rbs */ -{ -#ifdef NICENAMES -"cpb rbd,rbs",8,4, -0x3c, -#endif -"cpb",OPC_cpb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,74}, - - -/* 1011 1011 ssN0 1000 0000 rrrr dddd cccc *** cpd rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpd rd,@rs,rr,cc",16,11, -0x3c, -#endif -"cpd",OPC_cpd,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,75}, - - -/* 1011 1010 ssN0 1000 0000 rrrr dddd cccc *** cpdb rbd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpdb rbd,@rs,rr,cc",8,11, -0x3c, -#endif -"cpdb",OPC_cpdb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,76}, - - -/* 1011 1011 ssN0 1100 0000 rrrr dddd cccc *** cpdr rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpdr rd,@rs,rr,cc",16,11, -0x3c, -#endif -"cpdr",OPC_cpdr,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,77}, - - -/* 1011 1010 ssN0 1100 0000 rrrr dddd cccc *** cpdrb rbd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpdrb rbd,@rs,rr,cc",8,11, -0x3c, -#endif -"cpdrb",OPC_cpdrb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,78}, - - -/* 1011 1011 ssN0 0000 0000 rrrr dddd cccc *** cpi rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpi rd,@rs,rr,cc",16,11, -0x3c, -#endif -"cpi",OPC_cpi,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,79}, - - -/* 1011 1010 ssN0 0000 0000 rrrr dddd cccc *** cpib rbd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpib rbd,@rs,rr,cc",8,11, -0x3c, -#endif -"cpib",OPC_cpib,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,80}, - - -/* 1011 1011 ssN0 0100 0000 rrrr dddd cccc *** cpir rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpir rd,@rs,rr,cc",16,11, -0x3c, -#endif -"cpir",OPC_cpir,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,81}, - - -/* 1011 1010 ssN0 0100 0000 rrrr dddd cccc *** cpirb rbd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpirb rbd,@rs,rr,cc",8,11, -0x3c, -#endif -"cpirb",OPC_cpirb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REG+(ARG_RD),CLASS_CC,0,},4,4,82}, - - -/* 0001 0000 ssN0 dddd *** cpl rrd,@rs */ -{ -#ifdef NICENAMES -"cpl rrd,@rs",32,14, -0x3c, -#endif -"cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,83}, - - -/* 0101 0000 0000 dddd address_src *** cpl rrd,address_src */ -{ -#ifdef NICENAMES -"cpl rrd,address_src",32,15, -0x3c, -#endif -"cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,84}, - - -/* 0101 0000 ssN0 dddd address_src *** cpl rrd,address_src(rs) */ -{ -#ifdef NICENAMES -"cpl rrd,address_src(rs)",32,16, -0x3c, -#endif -"cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,85}, - - -/* 0001 0000 0000 dddd imm32 *** cpl rrd,imm32 */ -{ -#ifdef NICENAMES -"cpl rrd,imm32",32,14, -0x3c, -#endif -"cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, - {CLASS_BIT+1,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,86}, - - -/* 1001 0000 ssss dddd *** cpl rrd,rrs */ -{ -#ifdef NICENAMES -"cpl rrd,rrs",32,8, -0x3c, -#endif -"cpl",OPC_cpl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,87}, - - -/* 1011 1011 ssN0 1010 0000 rrrr ddN0 cccc *** cpsd @rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpsd @rd,@rs,rr,cc",16,11, -0x3c, -#endif -"cpsd",OPC_cpsd,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,88}, - - -/* 1011 1010 ssN0 1010 0000 rrrr ddN0 cccc *** cpsdb @rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpsdb @rd,@rs,rr,cc",8,11, -0x3c, -#endif -"cpsdb",OPC_cpsdb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,89}, - - -/* 1011 1011 ssN0 1110 0000 rrrr ddN0 cccc *** cpsdr @rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpsdr @rd,@rs,rr,cc",16,11, -0x3c, -#endif -"cpsdr",OPC_cpsdr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,90}, - - -/* 1011 1010 ssN0 1110 0000 rrrr ddN0 cccc *** cpsdrb @rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpsdrb @rd,@rs,rr,cc",8,11, -0x3c, -#endif -"cpsdrb",OPC_cpsdrb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,91}, - - -/* 1011 1011 ssN0 0010 0000 rrrr ddN0 cccc *** cpsi @rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpsi @rd,@rs,rr,cc",16,11, -0x3c, -#endif -"cpsi",OPC_cpsi,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,92}, - - -/* 1011 1010 ssN0 0010 0000 rrrr ddN0 cccc *** cpsib @rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpsib @rd,@rs,rr,cc",8,11, -0x3c, -#endif -"cpsib",OPC_cpsib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,93}, - - -/* 1011 1011 ssN0 0110 0000 rrrr ddN0 cccc *** cpsir @rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpsir @rd,@rs,rr,cc",16,11, -0x3c, -#endif -"cpsir",OPC_cpsir,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,94}, - - -/* 1011 1010 ssN0 0110 0000 rrrr ddN0 cccc *** cpsirb @rd,@rs,rr,cc */ -{ -#ifdef NICENAMES -"cpsirb @rd,@rs,rr,cc",8,11, -0x3c, -#endif -"cpsirb",OPC_cpsirb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),CLASS_CC,}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_CC,0,},4,4,95}, - - -/* 1011 0000 dddd 0000 *** dab rbd */ -{ -#ifdef NICENAMES -"dab rbd",8,5, -0x38, -#endif -"dab",OPC_dab,0,{CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,96}, - - -/* 1111 dddd 0disp7 *** dbjnz rbd,disp7 */ -{ -#ifdef NICENAMES -"dbjnz rbd,disp7",16,11, -0x00, -#endif -"dbjnz",OPC_dbjnz,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+0xf,CLASS_REG+(ARG_RD),CLASS_0DISP7,0,0,0,0,0,0,},2,2,97}, - - -/* 0010 1011 ddN0 imm4m1 *** dec @rd,imm4m1 */ -{ -#ifdef NICENAMES -"dec @rd,imm4m1",16,11, -0x1c, -#endif -"dec",OPC_dec,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+2,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,98}, - - -/* 0110 1011 ddN0 imm4m1 address_dst *** dec address_dst(rd),imm4m1 */ -{ -#ifdef NICENAMES -"dec address_dst(rd),imm4m1",16,14, -0x1c, -#endif -"dec",OPC_dec,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,99}, - - -/* 0110 1011 0000 imm4m1 address_dst *** dec address_dst,imm4m1 */ -{ -#ifdef NICENAMES -"dec address_dst,imm4m1",16,13, -0x1c, -#endif -"dec",OPC_dec,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,100}, - - -/* 1010 1011 dddd imm4m1 *** dec rd,imm4m1 */ -{ -#ifdef NICENAMES -"dec rd,imm4m1",16,4, -0x1c, -#endif -"dec",OPC_dec,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+0xa,CLASS_BIT+0xb,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,101}, - - -/* 0010 1010 ddN0 imm4m1 *** decb @rd,imm4m1 */ -{ -#ifdef NICENAMES -"decb @rd,imm4m1",8,11, -0x1c, -#endif -"decb",OPC_decb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+2,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,102}, - - -/* 0110 1010 ddN0 imm4m1 address_dst *** decb address_dst(rd),imm4m1 */ -{ -#ifdef NICENAMES -"decb address_dst(rd),imm4m1",8,14, -0x1c, -#endif -"decb",OPC_decb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,103}, - - -/* 0110 1010 0000 imm4m1 address_dst *** decb address_dst,imm4m1 */ -{ -#ifdef NICENAMES -"decb address_dst,imm4m1",8,13, -0x1c, -#endif -"decb",OPC_decb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,104}, - - -/* 1010 1010 dddd imm4m1 *** decb rbd,imm4m1 */ -{ -#ifdef NICENAMES -"decb rbd,imm4m1",8,4, -0x1c, -#endif -"decb",OPC_decb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+0xa,CLASS_BIT+0xa,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,105}, - - -/* 0111 1100 0000 00ii *** di i2 */ -{ -#ifdef NICENAMES -"di i2",16,7, -0x00, -#endif -"di",OPC_di,0,{CLASS_IMM+(ARG_IMM2),}, - {CLASS_BIT+7,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_00II,0,0,0,0,0,},1,2,106}, - - -/* 0001 1011 ssN0 dddd *** div rrd,@rs */ -{ -#ifdef NICENAMES -"div rrd,@rs",16,107, -0x3c, -#endif -"div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,107}, - - -/* 0101 1011 0000 dddd address_src *** div rrd,address_src */ -{ -#ifdef NICENAMES -"div rrd,address_src",16,107, -0x3c, -#endif -"div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,108}, - - -/* 0101 1011 ssN0 dddd address_src *** div rrd,address_src(rs) */ -{ -#ifdef NICENAMES -"div rrd,address_src(rs)",16,107, -0x3c, -#endif -"div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,109}, - - -/* 0001 1011 0000 dddd imm16 *** div rrd,imm16 */ -{ -#ifdef NICENAMES -"div rrd,imm16",16,107, -0x3c, -#endif -"div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+1,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,110}, - - -/* 1001 1011 ssss dddd *** div rrd,rs */ -{ -#ifdef NICENAMES -"div rrd,rs",16,107, -0x3c, -#endif -"div",OPC_div,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,111}, - - -/* 0001 1010 ssN0 dddd *** divl rqd,@rs */ -{ -#ifdef NICENAMES -"divl rqd,@rs",32,744, -0x3c, -#endif -"divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,112}, - - -/* 0101 1010 0000 dddd address_src *** divl rqd,address_src */ -{ -#ifdef NICENAMES -"divl rqd,address_src",32,745, -0x3c, -#endif -"divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,113}, - - -/* 0101 1010 ssN0 dddd address_src *** divl rqd,address_src(rs) */ -{ -#ifdef NICENAMES -"divl rqd,address_src(rs)",32,746, -0x3c, -#endif -"divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,114}, - - -/* 0001 1010 0000 dddd imm32 *** divl rqd,imm32 */ -{ -#ifdef NICENAMES -"divl rqd,imm32",32,744, -0x3c, -#endif -"divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, - {CLASS_BIT+1,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,115}, - - -/* 1001 1010 ssss dddd *** divl rqd,rrs */ -{ -#ifdef NICENAMES -"divl rqd,rrs",32,744, -0x3c, -#endif -"divl",OPC_divl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,116}, - - -/* 1111 dddd 1disp7 *** djnz rd,disp7 */ -{ -#ifdef NICENAMES -"djnz rd,disp7",16,11, -0x00, -#endif -"djnz",OPC_djnz,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+0xf,CLASS_REG+(ARG_RD),CLASS_1DISP7,0,0,0,0,0,0,},2,2,117}, - - -/* 0111 1100 0000 01ii *** ei i2 */ -{ -#ifdef NICENAMES -"ei i2",16,7, -0x00, -#endif -"ei",OPC_ei,0,{CLASS_IMM+(ARG_IMM2),}, - {CLASS_BIT+7,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_01II,0,0,0,0,0,},1,2,118}, - - -/* 0010 1101 ssN0 dddd *** ex rd,@rs */ -{ -#ifdef NICENAMES -"ex rd,@rs",16,12, -0x00, -#endif -"ex",OPC_ex,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,119}, - - -/* 0110 1101 0000 dddd address_src *** ex rd,address_src */ -{ -#ifdef NICENAMES -"ex rd,address_src",16,15, -0x00, -#endif -"ex",OPC_ex,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+6,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,120}, - - -/* 0110 1101 ssN0 dddd address_src *** ex rd,address_src(rs) */ -{ -#ifdef NICENAMES -"ex rd,address_src(rs)",16,16, -0x00, -#endif -"ex",OPC_ex,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,121}, - - -/* 1010 1101 ssss dddd *** ex rd,rs */ -{ -#ifdef NICENAMES -"ex rd,rs",16,6, -0x00, -#endif -"ex",OPC_ex,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xa,CLASS_BIT+0xd,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,122}, - - -/* 0010 1100 ssN0 dddd *** exb rbd,@rs */ -{ -#ifdef NICENAMES -"exb rbd,@rs",8,12, -0x00, -#endif -"exb",OPC_exb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,123}, - - -/* 0110 1100 0000 dddd address_src *** exb rbd,address_src */ -{ -#ifdef NICENAMES -"exb rbd,address_src",8,15, -0x00, -#endif -"exb",OPC_exb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+6,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,124}, - - -/* 0110 1100 ssN0 dddd address_src *** exb rbd,address_src(rs) */ -{ -#ifdef NICENAMES -"exb rbd,address_src(rs)",8,16, -0x00, -#endif -"exb",OPC_exb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,125}, - - -/* 1010 1100 ssss dddd *** exb rbd,rbs */ -{ -#ifdef NICENAMES -"exb rbd,rbs",8,6, -0x00, -#endif -"exb",OPC_exb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+0xa,CLASS_BIT+0xc,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,126}, - - -/* 0000 1110 imm8 *** ext0e imm8 */ -{ -#ifdef NICENAMES -"ext0e imm8",8,10, -0x00, -#endif -"ext0e",OPC_ext0e,0,{CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+0xe,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,127}, - - -/* 0000 1111 imm8 *** ext0f imm8 */ -{ -#ifdef NICENAMES -"ext0f imm8",8,10, -0x00, -#endif -"ext0f",OPC_ext0f,0,{CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,128}, - - -/* 1000 1110 imm8 *** ext8e imm8 */ -{ -#ifdef NICENAMES -"ext8e imm8",8,10, -0x00, -#endif -"ext8e",OPC_ext8e,0,{CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+8,CLASS_BIT+0xe,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,129}, - - -/* 1000 1111 imm8 *** ext8f imm8 */ -{ -#ifdef NICENAMES -"ext8f imm8",8,10, -0x00, -#endif -"ext8f",OPC_ext8f,0,{CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+8,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,130}, - - -/* 1011 0001 dddd 1010 *** exts rrd */ -{ -#ifdef NICENAMES -"exts rrd",16,11, -0x00, -#endif -"exts",OPC_exts,0,{CLASS_REG_LONG+(ARG_RD),}, - {CLASS_BIT+0xb,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+0xa,0,0,0,0,0,},1,2,131}, - - -/* 1011 0001 dddd 0000 *** extsb rd */ -{ -#ifdef NICENAMES -"extsb rd",8,11, -0x00, -#endif -"extsb",OPC_extsb,0,{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+0xb,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+0,0,0,0,0,0,},1,2,132}, - - -/* 1011 0001 dddd 0111 *** extsl rqd */ -{ -#ifdef NICENAMES -"extsl rqd",32,11, -0x00, -#endif -"extsl",OPC_extsl,0,{CLASS_REG_QUAD+(ARG_RD),}, - {CLASS_BIT+0xb,CLASS_BIT+1,CLASS_REG+(ARG_RD),CLASS_BIT+7,0,0,0,0,0,},1,2,133}, - - -/* 0111 1010 0000 0000 *** halt */ -{ -#ifdef NICENAMES -"halt",16,8, -0x00, -#endif -"halt",OPC_halt,0,{0}, - {CLASS_BIT+7,CLASS_BIT+0xa,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},0,2,134}, - - -/* 0011 1101 ssN0 dddd *** in rd,@rs */ -{ -#ifdef NICENAMES -"in rd,@rs",16,10, -0x00, -#endif -"in",OPC_in,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,135}, - - -/* 0011 1101 dddd 0100 imm16 *** in rd,imm16 */ -{ -#ifdef NICENAMES -"in rd,imm16",16,12, -0x00, -#endif -"in",OPC_in,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+3,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+4,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,136}, - - -/* 0011 1100 ssN0 dddd *** inb rbd,@rs */ -{ -#ifdef NICENAMES -"inb rbd,@rs",8,12, -0x00, -#endif -"inb",OPC_inb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,137}, - - -/* 0011 1010 dddd 0100 imm16 *** inb rbd,imm16 */ -{ -#ifdef NICENAMES -"inb rbd,imm16",8,10, -0x00, -#endif -"inb",OPC_inb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RD),CLASS_BIT+4,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,138}, - - -/* 0010 1001 ddN0 imm4m1 *** inc @rd,imm4m1 */ -{ -#ifdef NICENAMES -"inc @rd,imm4m1",16,11, -0x1c, -#endif -"inc",OPC_inc,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+2,CLASS_BIT+9,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,139}, - - -/* 0110 1001 ddN0 imm4m1 address_dst *** inc address_dst(rd),imm4m1 */ -{ -#ifdef NICENAMES -"inc address_dst(rd),imm4m1",16,14, -0x1c, -#endif -"inc",OPC_inc,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+9,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,140}, - - -/* 0110 1001 0000 imm4m1 address_dst *** inc address_dst,imm4m1 */ -{ -#ifdef NICENAMES -"inc address_dst,imm4m1",16,13, -0x1c, -#endif -"inc",OPC_inc,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+9,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,141}, - - -/* 1010 1001 dddd imm4m1 *** inc rd,imm4m1 */ -{ -#ifdef NICENAMES -"inc rd,imm4m1",16,4, -0x1c, -#endif -"inc",OPC_inc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+0xa,CLASS_BIT+9,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,142}, - - -/* 0010 1000 ddN0 imm4m1 *** incb @rd,imm4m1 */ -{ -#ifdef NICENAMES -"incb @rd,imm4m1",8,11, -0x1c, -#endif -"incb",OPC_incb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+2,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,143}, - - -/* 0110 1000 ddN0 imm4m1 address_dst *** incb address_dst(rd),imm4m1 */ -{ -#ifdef NICENAMES -"incb address_dst(rd),imm4m1",8,14, -0x1c, -#endif -"incb",OPC_incb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,144}, - - -/* 0110 1000 0000 imm4m1 address_dst *** incb address_dst,imm4m1 */ -{ -#ifdef NICENAMES -"incb address_dst,imm4m1",8,13, -0x1c, -#endif -"incb",OPC_incb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+6,CLASS_BIT+8,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4M1),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,145}, - - -/* 1010 1000 dddd imm4m1 *** incb rbd,imm4m1 */ -{ -#ifdef NICENAMES -"incb rbd,imm4m1",8,4, -0x1c, -#endif -"incb",OPC_incb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4M1),}, - {CLASS_BIT+0xa,CLASS_BIT+8,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4M1),0,0,0,0,0,},2,2,146}, - - -/* 0011 1011 ssN0 1000 0000 aaaa ddN0 1000 *** ind @rd,@rs,ra */ -{ -#ifdef NICENAMES -"ind @rd,@rs,ra",16,21, -0x04, -#endif -"ind",OPC_ind,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,147}, - - -/* 0011 1010 ssN0 1000 0000 aaaa ddN0 1000 *** indb @rd,@rs,rba */ -{ -#ifdef NICENAMES -"indb @rd,@rs,rba",8,21, -0x04, -#endif -"indb",OPC_indb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,148}, - - -/* 0011 1010 ssN0 0000 0000 aaaa ddN0 1000 *** inib @rd,@rs,ra */ -{ -#ifdef NICENAMES -"inib @rd,@rs,ra",8,21, -0x04, -#endif -"inib",OPC_inib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,149}, - - -/* 0011 1010 ssN0 0000 0000 aaaa ddN0 0000 *** inibr @rd,@rs,ra */ -{ -#ifdef NICENAMES -"inibr @rd,@rs,ra",16,21, -0x04, -#endif -"inibr",OPC_inibr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,150}, - - -/* 0111 1011 0000 0000 *** iret */ -{ -#ifdef NICENAMES -"iret",16,13, -0x3f, -#endif -"iret",OPC_iret,0,{0}, - {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+0,0,0,0,0,0,},0,2,151}, - - -/* 0001 1110 ddN0 cccc *** jp cc,@rd */ -{ -#ifdef NICENAMES -"jp cc,@rd",16,10, -0x00, -#endif -"jp",OPC_jp,0,{CLASS_CC,CLASS_IR+(ARG_RD),}, - {CLASS_BIT+1,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,152}, - - -/* 0101 1110 0000 cccc address_dst *** jp cc,address_dst */ -{ -#ifdef NICENAMES -"jp cc,address_dst",16,7, -0x00, -#endif -"jp",OPC_jp,0,{CLASS_CC,CLASS_DA+(ARG_DST),}, - {CLASS_BIT+5,CLASS_BIT+0xe,CLASS_BIT+0,CLASS_CC,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,153}, - - -/* 0101 1110 ddN0 cccc address_dst *** jp cc,address_dst(rd) */ -{ -#ifdef NICENAMES -"jp cc,address_dst(rd)",16,8, -0x00, -#endif -"jp",OPC_jp,0,{CLASS_CC,CLASS_X+(ARG_RD),}, - {CLASS_BIT+5,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_CC,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,154}, - - -/* 1110 cccc disp8 *** jr cc,disp8 */ -{ -#ifdef NICENAMES -"jr cc,disp8",16,6, -0x00, -#endif -"jr",OPC_jr,0,{CLASS_CC,CLASS_DISP,}, - {CLASS_BIT+0xe,CLASS_CC,CLASS_DISP8,0,0,0,0,0,0,},2,2,155}, - - -/* 0000 1101 ddN0 0101 imm16 *** ld @rd,imm16 */ -{ -#ifdef NICENAMES -"ld @rd,imm16",16,7, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,156}, - - -/* 0010 1111 ddN0 ssss *** ld @rd,rs */ -{ -#ifdef NICENAMES -"ld @rd,rs",16,8, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,157}, - - -/* 0100 1101 ddN0 0101 address_dst imm16 *** ld address_dst(rd),imm16 */ -{ -#ifdef NICENAMES -"ld address_dst(rd),imm16",16,15, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,158}, - - -/* 0110 1111 ddN0 ssss address_dst *** ld address_dst(rd),rs */ -{ -#ifdef NICENAMES -"ld address_dst(rd),rs",16,12, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_X+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,159}, - - -/* 0100 1101 0000 0101 address_dst imm16 *** ld address_dst,imm16 */ -{ -#ifdef NICENAMES -"ld address_dst,imm16",16,14, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_DA+(ARG_DST),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM16),0,0,0,},2,6,160}, - - -/* 0110 1111 0000 ssss address_dst *** ld address_dst,rs */ -{ -#ifdef NICENAMES -"ld address_dst,rs",16,11, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_DA+(ARG_DST),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+0xf,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,161}, - - -/* 0011 0011 ddN0 ssss imm16 *** ld rd(imm16),rs */ -{ -#ifdef NICENAMES -"ld rd(imm16),rs",16,14, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_BA+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,162}, - - -/* 0111 0011 ddN0 ssss 0000 xxxx 0000 0000 *** ld rd(rx),rs */ -{ -#ifdef NICENAMES -"ld rd(rx),rs",16,14, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_BX+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,163}, - - -/* 0010 0001 ssN0 dddd *** ld rd,@rs */ -{ -#ifdef NICENAMES -"ld rd,@rs",16,7, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,164}, - - -/* 0110 0001 0000 dddd address_src *** ld rd,address_src */ -{ -#ifdef NICENAMES -"ld rd,address_src",16,9, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+6,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,165}, - - -/* 0110 0001 ssN0 dddd address_src *** ld rd,address_src(rs) */ -{ -#ifdef NICENAMES -"ld rd,address_src(rs)",16,10, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,166}, - - -/* 0010 0001 0000 dddd imm16 *** ld rd,imm16 */ -{ -#ifdef NICENAMES -"ld rd,imm16",16,7, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+2,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,167}, - - -/* 1010 0001 ssss dddd *** ld rd,rs */ -{ -#ifdef NICENAMES -"ld rd,rs",16,3, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xa,CLASS_BIT+1,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,168}, - - -/* 0011 0001 ssN0 dddd imm16 *** ld rd,rs(imm16) */ -{ -#ifdef NICENAMES -"ld rd,rs(imm16)",16,14, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_BA+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,169}, - - -/* 0111 0001 ssN0 dddd 0000 xxxx 0000 0000 *** ld rd,rs(rx) */ -{ -#ifdef NICENAMES -"ld rd,rs(rx)",16,14, -0x00, -#endif -"ld",OPC_ld,0,{CLASS_REG_WORD+(ARG_RD),CLASS_BX+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+1,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,170}, - - -/* 0111 0110 0000 dddd address_src *** lda prd,address_src */ -{ -#ifdef NICENAMES -"lda prd,address_src",16,12, -0x00, -#endif -"lda",OPC_lda,0,{CLASS_PR+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+7,CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,171}, - - -/* 0111 0110 ssN0 dddd address_src *** lda prd,address_src(rs) */ -{ -#ifdef NICENAMES -"lda prd,address_src(rs)",16,13, -0x00, -#endif -"lda",OPC_lda,0,{CLASS_PR+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+6,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,172}, - - -/* 0011 0100 ssN0 dddd imm16 *** lda prd,rs(imm16) */ -{ -#ifdef NICENAMES -"lda prd,rs(imm16)",16,15, -0x00, -#endif -"lda",OPC_lda,0,{CLASS_PR+(ARG_RD),CLASS_BA+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,173}, - - -/* 0111 0100 ssN0 dddd 0000 xxxx 0000 0000 *** lda prd,rs(rx) */ -{ -#ifdef NICENAMES -"lda prd,rs(rx)",16,15, -0x00, -#endif -"lda",OPC_lda,0,{CLASS_PR+(ARG_RD),CLASS_BX+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,174}, - - -/* 0011 0100 0000 dddd disp16 *** ldar prd,disp16 */ -{ -#ifdef NICENAMES -"ldar prd,disp16",16,15, -0x00, -#endif -"ldar",OPC_ldar,0,{CLASS_PR+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+3,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,175}, - - -/* 0000 1100 ddN0 0101 imm8 imm8 *** ldb @rd,imm8 */ -{ -#ifdef NICENAMES -"ldb @rd,imm8",8,7, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,176}, - - -/* 0010 1110 ddN0 ssss *** ldb @rd,rbs */ -{ -#ifdef NICENAMES -"ldb @rd,rbs",8,8, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_IR+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,177}, - - -/* 0100 1100 ddN0 0101 address_dst imm8 imm8 *** ldb address_dst(rd),imm8 */ -{ -#ifdef NICENAMES -"ldb address_dst(rd),imm8",8,15, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_X+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,178}, - - -/* 0110 1110 ddN0 ssss address_dst *** ldb address_dst(rd),rbs */ -{ -#ifdef NICENAMES -"ldb address_dst(rd),rbs",8,12, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_X+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,179}, - - -/* 0100 1100 0000 0101 address_dst imm8 imm8 *** ldb address_dst,imm8 */ -{ -#ifdef NICENAMES -"ldb address_dst,imm8",8,14, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_DA+(ARG_DST),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+5,CLASS_ADDRESS+(ARG_DST),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,},2,6,180}, - - -/* 0110 1110 0000 ssss address_dst *** ldb address_dst,rbs */ -{ -#ifdef NICENAMES -"ldb address_dst,rbs",8,11, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_DA+(ARG_DST),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,181}, - - -/* 0010 0000 ssN0 dddd *** ldb rbd,@rs */ -{ -#ifdef NICENAMES -"ldb rbd,@rs",8,7, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,182}, - - -/* 0110 0000 0000 dddd address_src *** ldb rbd,address_src */ -{ -#ifdef NICENAMES -"ldb rbd,address_src",8,9, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+6,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,183}, - - -/* 0110 0000 ssN0 dddd address_src *** ldb rbd,address_src(rs) */ -{ -#ifdef NICENAMES -"ldb rbd,address_src(rs)",8,10, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+6,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,184}, - - -/* 1100 dddd imm8 *** ldb rbd,imm8 */ -{ -#ifdef NICENAMES -"ldb rbd,imm8",8,5, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},2,2,185}, - - -/* 1010 0000 ssss dddd *** ldb rbd,rbs */ -{ -#ifdef NICENAMES -"ldb rbd,rbs",8,3, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,186}, - - -/* 0011 0000 ssN0 dddd imm16 *** ldb rbd,rs(imm16) */ -{ -#ifdef NICENAMES -"ldb rbd,rs(imm16)",8,14, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_BA+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,187}, - - -/* 0111 0000 ssN0 dddd 0000 xxxx 0000 0000 *** ldb rbd,rs(rx) */ -{ -#ifdef NICENAMES -"ldb rbd,rs(rx)",8,14, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_BX+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+0,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,188}, - - -/* 0011 0010 ddN0 ssss imm16 *** ldb rd(imm16),rbs */ -{ -#ifdef NICENAMES -"ldb rd(imm16),rbs",8,14, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_BA+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,189}, - - -/* 0111 0010 ddN0 ssss 0000 xxxx 0000 0000 *** ldb rd(rx),rbs */ -{ -#ifdef NICENAMES -"ldb rd(rx),rbs",8,14, -0x00, -#endif -"ldb",OPC_ldb,0,{CLASS_BX+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,190}, - - -/* 0111 1101 ssss 1ccc *** ldctl ctrl,rs */ -{ -#ifdef NICENAMES -"ldctl ctrl,rs",32,7, -0x00, -#endif -"ldctl",OPC_ldctl,0,{CLASS_CTRL,CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+0xd,CLASS_REG+(ARG_RS),CLASS_1CCC,0,0,0,0,0,},2,2,191}, - - -/* 0111 1101 dddd 0ccc *** ldctl rd,ctrl */ -{ -#ifdef NICENAMES -"ldctl rd,ctrl",32,7, -0x00, -#endif -"ldctl",OPC_ldctl,0,{CLASS_REG_WORD+(ARG_RD),CLASS_CTRL,}, - {CLASS_BIT+7,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_0CCC,0,0,0,0,0,},2,2,192}, - - -/* 1000 1100 ssss 1001 *** ldctlb ctrl,rbs */ -{ -#ifdef NICENAMES -"ldctlb ctrl,rbs",32,7, -0x3f, -#endif -"ldctlb",OPC_ldctlb,0,{CLASS_CTRL,CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RS),CLASS_BIT+9,0,0,0,0,0,},2,2,193}, - - -/* 1000 1100 dddd 0001 *** ldctlb rbd,ctrl */ -{ -#ifdef NICENAMES -"ldctlb rbd,ctrl",32,7, -0x00, -#endif -"ldctlb",OPC_ldctlb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_CTRL,}, - {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+1,0,0,0,0,0,},2,2,194}, - - -/* 1011 1011 ssN0 1001 0000 rrrr ddN0 1000 *** ldd @rd,@rs,rr */ -{ -#ifdef NICENAMES -"ldd @rd,@rs,rr",16,11, -0x04, -#endif -"ldd",OPC_ldd,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,195}, - - -/* 1011 1010 ssN0 1001 0000 rrrr ddN0 1000 *** lddb @rd,@rs,rr */ -{ -#ifdef NICENAMES -"lddb @rd,@rs,rr",8,11, -0x04, -#endif -"lddb",OPC_lddb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,196}, - - -/* 1011 1011 ssN0 1001 0000 rrrr ddN0 0000 *** lddr @rd,@rs,rr */ -{ -#ifdef NICENAMES -"lddr @rd,@rs,rr",16,11, -0x04, -#endif -"lddr",OPC_lddr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,197}, - - -/* 1011 1010 ssN0 1001 0000 rrrr ddN0 0000 *** lddrb @rd,@rs,rr */ -{ -#ifdef NICENAMES -"lddrb @rd,@rs,rr",8,11, -0x04, -#endif -"lddrb",OPC_lddrb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,198}, - - -/* 1011 1011 ssN0 0001 0000 rrrr ddN0 1000 *** ldi @rd,@rs,rr */ -{ -#ifdef NICENAMES -"ldi @rd,@rs,rr",16,11, -0x04, -#endif -"ldi",OPC_ldi,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,199}, - - -/* 1011 1010 ssN0 0001 0000 rrrr ddN0 1000 *** ldib @rd,@rs,rr */ -{ -#ifdef NICENAMES -"ldib @rd,@rs,rr",8,11, -0x04, -#endif -"ldib",OPC_ldib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,200}, - - -/* 1011 1011 ssN0 0001 0000 rrrr ddN0 0000 *** ldir @rd,@rs,rr */ -{ -#ifdef NICENAMES -"ldir @rd,@rs,rr",16,11, -0x04, -#endif -"ldir",OPC_ldir,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,201}, - - -/* 1011 1010 ssN0 0001 0000 rrrr ddN0 0000 *** ldirb @rd,@rs,rr */ -{ -#ifdef NICENAMES -"ldirb @rd,@rs,rr",8,11, -0x04, -#endif -"ldirb",OPC_ldirb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,202}, - - -/* 1011 1101 dddd imm4 *** ldk rd,imm4 */ -{ -#ifdef NICENAMES -"ldk rd,imm4",16,5, -0x00, -#endif -"ldk",OPC_ldk,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+0xb,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,203}, - - -/* 0001 1101 ddN0 ssss *** ldl @rd,rrs */ -{ -#ifdef NICENAMES -"ldl @rd,rrs",32,11, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_IR+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,204}, - - -/* 0101 1101 ddN0 ssss address_dst *** ldl address_dst(rd),rrs */ -{ -#ifdef NICENAMES -"ldl address_dst(rd),rrs",32,14, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_X+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,205}, - - -/* 0101 1101 0000 ssss address_dst *** ldl address_dst,rrs */ -{ -#ifdef NICENAMES -"ldl address_dst,rrs",32,15, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_DA+(ARG_DST),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,206}, - - -/* 0011 0111 ddN0 ssss imm16 *** ldl rd(imm16),rrs */ -{ -#ifdef NICENAMES -"ldl rd(imm16),rrs",32,17, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_BA+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,207}, - - -/* 0111 0111 ddN0 ssss 0000 xxxx 0000 0000 *** ldl rd(rx),rrs */ -{ -#ifdef NICENAMES -"ldl rd(rx),rrs",32,17, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_BX+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+7,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,208}, - - -/* 0001 0100 ssN0 dddd *** ldl rrd,@rs */ -{ -#ifdef NICENAMES -"ldl rrd,@rs",32,11, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,209}, - - -/* 0101 0100 0000 dddd address_src *** ldl rrd,address_src */ -{ -#ifdef NICENAMES -"ldl rrd,address_src",32,12, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,210}, - - -/* 0101 0100 ssN0 dddd address_src *** ldl rrd,address_src(rs) */ -{ -#ifdef NICENAMES -"ldl rrd,address_src(rs)",32,13, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,211}, - - -/* 0001 0100 0000 dddd imm32 *** ldl rrd,imm32 */ -{ -#ifdef NICENAMES -"ldl rrd,imm32",32,11, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, - {CLASS_BIT+1,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,212}, - - -/* 1001 0100 ssss dddd *** ldl rrd,rrs */ -{ -#ifdef NICENAMES -"ldl rrd,rrs",32,5, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+4,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,213}, - - -/* 0011 0101 ssN0 dddd imm16 *** ldl rrd,rs(imm16) */ -{ -#ifdef NICENAMES -"ldl rrd,rs(imm16)",32,17, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_BA+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,214}, - - -/* 0111 0101 ssN0 dddd 0000 xxxx 0000 0000 *** ldl rrd,rs(rx) */ -{ -#ifdef NICENAMES -"ldl rrd,rs(rx)",32,17, -0x00, -#endif -"ldl",OPC_ldl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_BX+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_REG+(ARG_RX),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,215}, - - -/* 0001 1100 ddN0 1001 0000 ssss 0000 nminus1 *** ldm @rd,rs,n */ -{ -#ifdef NICENAMES -"ldm @rd,rs,n",16,11, -0x00, -#endif -"ldm",OPC_ldm,0,{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMMN),}, - {CLASS_BIT+1,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),0,},3,4,216}, - - -/* 0101 1100 ddN0 1001 0000 ssss 0000 nminus1 address_dst *** ldm address_dst(rd),rs,n */ -{ -#ifdef NICENAMES -"ldm address_dst(rd),rs,n",16,15, -0x00, -#endif -"ldm",OPC_ldm,0,{CLASS_X+(ARG_RD),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMMN),}, - {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),CLASS_ADDRESS+(ARG_DST),},3,6,217}, - - -/* 0101 1100 0000 1001 0000 ssss 0000 nminus1 address_dst *** ldm address_dst,rs,n */ -{ -#ifdef NICENAMES -"ldm address_dst,rs,n",16,14, -0x00, -#endif -"ldm",OPC_ldm,0,{CLASS_DA+(ARG_DST),CLASS_REG_WORD+(ARG_RS),CLASS_IMM + (ARG_IMMN),}, - {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),CLASS_ADDRESS+(ARG_DST),},3,6,218}, - - -/* 0001 1100 ssN0 0001 0000 dddd 0000 nminus1 *** ldm rd,@rs,n */ -{ -#ifdef NICENAMES -"ldm rd,@rs,n",16,11, -0x00, -#endif -"ldm",OPC_ldm,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_IMM + (ARG_IMMN),}, - {CLASS_BIT+1,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),0,},3,4,219}, - - -/* 0101 1100 ssN0 0001 0000 dddd 0000 nminus1 address_src *** ldm rd,address_src(rs),n */ -{ -#ifdef NICENAMES -"ldm rd,address_src(rs),n",16,15, -0x00, -#endif -"ldm",OPC_ldm,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),CLASS_IMM + (ARG_IMMN),}, - {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),CLASS_ADDRESS+(ARG_SRC),},3,6,220}, - - -/* 0101 1100 0000 0001 0000 dddd 0000 nminus1 address_src *** ldm rd,address_src,n */ -{ -#ifdef NICENAMES -"ldm rd,address_src,n",16,14, -0x00, -#endif -"ldm",OPC_ldm,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),CLASS_IMM + (ARG_IMMN),}, - {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_IMM+(ARG_IMMNMINUS1),CLASS_ADDRESS+(ARG_SRC),},3,6,221}, - - -/* 0011 1001 ssN0 0000 *** ldps @rs */ -{ -#ifdef NICENAMES -"ldps @rs",16,12, -0x3f, -#endif -"ldps",OPC_ldps,0,{CLASS_IR+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,0,0,0,0,},1,2,222}, - - -/* 0111 1001 0000 0000 address_src *** ldps address_src */ -{ -#ifdef NICENAMES -"ldps address_src",16,16, -0x3f, -#endif -"ldps",OPC_ldps,0,{CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+7,CLASS_BIT+9,CLASS_BIT+0,CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},1,4,223}, - - -/* 0111 1001 ssN0 0000 address_src *** ldps address_src(rs) */ -{ -#ifdef NICENAMES -"ldps address_src(rs)",16,17, -0x3f, -#endif -"ldps",OPC_ldps,0,{CLASS_X+(ARG_RS),}, - {CLASS_BIT+7,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},1,4,224}, - - -/* 0011 0011 0000 ssss disp16 *** ldr disp16,rs */ -{ -#ifdef NICENAMES -"ldr disp16,rs",16,14, -0x00, -#endif -"ldr",OPC_ldr,0,{CLASS_DISP,CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,225}, - - -/* 0011 0001 0000 dddd disp16 *** ldr rd,disp16 */ -{ -#ifdef NICENAMES -"ldr rd,disp16",16,14, -0x00, -#endif -"ldr",OPC_ldr,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+3,CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,226}, - - -/* 0011 0010 0000 ssss disp16 *** ldrb disp16,rbs */ -{ -#ifdef NICENAMES -"ldrb disp16,rbs",8,14, -0x00, -#endif -"ldrb",OPC_ldrb,0,{CLASS_DISP,CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,227}, - - -/* 0011 0000 0000 dddd disp16 *** ldrb rbd,disp16 */ -{ -#ifdef NICENAMES -"ldrb rbd,disp16",8,14, -0x00, -#endif -"ldrb",OPC_ldrb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+3,CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,228}, - - -/* 0011 0111 0000 ssss disp16 *** ldrl disp16,rrs */ -{ -#ifdef NICENAMES -"ldrl disp16,rrs",32,17, -0x00, -#endif -"ldrl",OPC_ldrl,0,{CLASS_DISP,CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,229}, - - -/* 0011 0101 0000 dddd disp16 *** ldrl rrd,disp16 */ -{ -#ifdef NICENAMES -"ldrl rrd,disp16",32,17, -0x00, -#endif -"ldrl",OPC_ldrl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DISP,}, - {CLASS_BIT+3,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_DISP+(ARG_DISP16),0,0,0,0,},2,4,230}, - - -/* 0111 1011 0000 1010 *** mbit */ -{ -#ifdef NICENAMES -"mbit",16,7, -0x38, -#endif -"mbit",OPC_mbit,0,{0}, - {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+0xa,0,0,0,0,0,},0,2,231}, - - -/* 0111 1011 dddd 1101 *** mreq rd */ -{ -#ifdef NICENAMES -"mreq rd",16,12, -0x18, -#endif -"mreq",OPC_mreq,0,{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_REG+(ARG_RD),CLASS_BIT+0xd,0,0,0,0,0,},1,2,232}, - - -/* 0111 1011 0000 1001 *** mres */ -{ -#ifdef NICENAMES -"mres",16,5, -0x00, -#endif -"mres",OPC_mres,0,{0}, - {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+9,0,0,0,0,0,},0,2,233}, - - -/* 0111 1011 0000 1000 *** mset */ -{ -#ifdef NICENAMES -"mset",16,5, -0x00, -#endif -"mset",OPC_mset,0,{0}, - {CLASS_BIT+7,CLASS_BIT+0xb,CLASS_BIT+0,CLASS_BIT+8,0,0,0,0,0,},0,2,234}, - - -/* 0001 1001 ssN0 dddd *** mult rrd,@rs */ -{ -#ifdef NICENAMES -"mult rrd,@rs",16,70, -0x3c, -#endif -"mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,235}, - - -/* 0101 1001 0000 dddd address_src *** mult rrd,address_src */ -{ -#ifdef NICENAMES -"mult rrd,address_src",16,70, -0x3c, -#endif -"mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,236}, - - -/* 0101 1001 ssN0 dddd address_src *** mult rrd,address_src(rs) */ -{ -#ifdef NICENAMES -"mult rrd,address_src(rs)",16,70, -0x3c, -#endif -"mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,237}, - - -/* 0001 1001 0000 dddd imm16 *** mult rrd,imm16 */ -{ -#ifdef NICENAMES -"mult rrd,imm16",16,70, -0x3c, -#endif -"mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+1,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,238}, - - -/* 1001 1001 ssss dddd *** mult rrd,rs */ -{ -#ifdef NICENAMES -"mult rrd,rs",16,70, -0x3c, -#endif -"mult",OPC_mult,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+9,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,239}, - - -/* 0001 1000 ssN0 dddd *** multl rqd,@rs */ -{ -#ifdef NICENAMES -"multl rqd,@rs",32,282, -0x3c, -#endif -"multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,240}, - - -/* 0101 1000 0000 dddd address_src *** multl rqd,address_src */ -{ -#ifdef NICENAMES -"multl rqd,address_src",32,282, -0x3c, -#endif -"multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,241}, - - -/* 0101 1000 ssN0 dddd address_src *** multl rqd,address_src(rs) */ -{ -#ifdef NICENAMES -"multl rqd,address_src(rs)",32,282, -0x3c, -#endif -"multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,242}, - - -/* 0001 1000 0000 dddd imm32 *** multl rqd,imm32 */ -{ -#ifdef NICENAMES -"multl rqd,imm32",32,282, -0x3c, -#endif -"multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, - {CLASS_BIT+1,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,243}, - - -/* 1001 1000 ssss dddd *** multl rqd,rrs */ -{ -#ifdef NICENAMES -"multl rqd,rrs",32,282, -0x3c, -#endif -"multl",OPC_multl,0,{CLASS_REG_QUAD+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+8,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,244}, - - -/* 0000 1101 ddN0 0010 *** neg @rd */ -{ -#ifdef NICENAMES -"neg @rd",16,12, -0x3c, -#endif -"neg",OPC_neg,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,245}, - - -/* 0100 1101 0000 0010 address_dst *** neg address_dst */ -{ -#ifdef NICENAMES -"neg address_dst",16,15, -0x3c, -#endif -"neg",OPC_neg,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,246}, - - -/* 0100 1101 ddN0 0010 address_dst *** neg address_dst(rd) */ -{ -#ifdef NICENAMES -"neg address_dst(rd)",16,16, -0x3c, -#endif -"neg",OPC_neg,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,247}, - - -/* 1000 1101 dddd 0010 *** neg rd */ -{ -#ifdef NICENAMES -"neg rd",16,7, -0x3c, -#endif -"neg",OPC_neg,0,{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,248}, - - -/* 0000 1100 ddN0 0010 *** negb @rd */ -{ -#ifdef NICENAMES -"negb @rd",8,12, -0x3c, -#endif -"negb",OPC_negb,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,249}, - - -/* 0100 1100 0000 0010 address_dst *** negb address_dst */ -{ -#ifdef NICENAMES -"negb address_dst",8,15, -0x3c, -#endif -"negb",OPC_negb,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,250}, - - -/* 0100 1100 ddN0 0010 address_dst *** negb address_dst(rd) */ -{ -#ifdef NICENAMES -"negb address_dst(rd)",8,16, -0x3c, -#endif -"negb",OPC_negb,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+2,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,251}, - - -/* 1000 1100 dddd 0010 *** negb rbd */ -{ -#ifdef NICENAMES -"negb rbd",8,7, -0x3c, -#endif -"negb",OPC_negb,0,{CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+2,0,0,0,0,0,},1,2,252}, - - -/* 1000 1101 0000 0111 *** nop */ -{ -#ifdef NICENAMES -"nop",16,7, -0x00, -#endif -"nop",OPC_nop,0,{0}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+7,0,0,0,0,0,},0,2,253}, - - -/* 0000 0101 ssN0 dddd *** or rd,@rs */ -{ -#ifdef NICENAMES -"or rd,@rs",16,7, -0x38, -#endif -"or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,254}, - - -/* 0100 0101 0000 dddd address_src *** or rd,address_src */ -{ -#ifdef NICENAMES -"or rd,address_src",16,9, -0x38, -#endif -"or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,255}, - - -/* 0100 0101 ssN0 dddd address_src *** or rd,address_src(rs) */ -{ -#ifdef NICENAMES -"or rd,address_src(rs)",16,10, -0x38, -#endif -"or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,256}, - - -/* 0000 0101 0000 dddd imm16 *** or rd,imm16 */ -{ -#ifdef NICENAMES -"or rd,imm16",16,7, -0x38, -#endif -"or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,257}, - - -/* 1000 0101 ssss dddd *** or rd,rs */ -{ -#ifdef NICENAMES -"or rd,rs",16,4, -0x38, -#endif -"or",OPC_or,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+5,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,258}, - - -/* 0000 0100 ssN0 dddd *** orb rbd,@rs */ -{ -#ifdef NICENAMES -"orb rbd,@rs",8,7, -0x3c, -#endif -"orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,259}, - - -/* 0100 0100 0000 dddd address_src *** orb rbd,address_src */ -{ -#ifdef NICENAMES -"orb rbd,address_src",8,9, -0x3c, -#endif -"orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,260}, - - -/* 0100 0100 ssN0 dddd address_src *** orb rbd,address_src(rs) */ -{ -#ifdef NICENAMES -"orb rbd,address_src(rs)",8,10, -0x3c, -#endif -"orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+4,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,261}, - - -/* 0000 0100 0000 dddd imm8 imm8 *** orb rbd,imm8 */ -{ -#ifdef NICENAMES -"orb rbd,imm8",8,7, -0x3c, -#endif -"orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,262}, - - -/* 1000 0100 ssss dddd *** orb rbd,rbs */ -{ -#ifdef NICENAMES -"orb rbd,rbs",8,4, -0x3c, -#endif -"orb",OPC_orb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+4,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,263}, - - -/* 0011 1111 ddN0 ssss *** out @rd,rs */ -{ -#ifdef NICENAMES -"out @rd,rs",16,0, -0x04, -#endif -"out",OPC_out,0,{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xf,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,264}, - - -/* 0011 1011 ssss 0110 imm16 *** out imm16,rs */ -{ -#ifdef NICENAMES -"out imm16,rs",16,0, -0x04, -#endif -"out",OPC_out,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+6,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,265}, - - -/* 0011 1110 ddN0 ssss *** outb @rd,rbs */ -{ -#ifdef NICENAMES -"outb @rd,rbs",8,0, -0x04, -#endif -"outb",OPC_outb,0,{CLASS_IR+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xe,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,266}, - - -/* 0011 1010 ssss 0110 imm16 *** outb imm16,rbs */ -{ -#ifdef NICENAMES -"outb imm16,rbs",8,0, -0x04, -#endif -"outb",OPC_outb,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+6,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,267}, - - -/* 0011 1011 ssN0 1010 0000 aaaa ddN0 1000 *** outd @rd,@rs,ra */ -{ -#ifdef NICENAMES -"outd @rd,@rs,ra",16,0, -0x04, -#endif -"outd",OPC_outd,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,268}, - - -/* 0011 1010 ssN0 1010 0000 aaaa ddN0 1000 *** outdb @rd,@rs,rba */ -{ -#ifdef NICENAMES -"outdb @rd,@rs,rba",16,0, -0x04, -#endif -"outdb",OPC_outdb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,269}, - - -/* 0011 1011 ssN0 0010 0000 aaaa ddN0 1000 *** outi @rd,@rs,ra */ -{ -#ifdef NICENAMES -"outi @rd,@rs,ra",16,0, -0x04, -#endif -"outi",OPC_outi,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,270}, - - -/* 0011 1010 ssN0 0010 0000 aaaa ddN0 1000 *** outib @rd,@rs,ra */ -{ -#ifdef NICENAMES -"outib @rd,@rs,ra",16,0, -0x04, -#endif -"outib",OPC_outib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,271}, - - -/* 0011 1010 ssN0 0010 0000 aaaa ddN0 0000 *** outibr @rd,@rs,ra */ -{ -#ifdef NICENAMES -"outibr @rd,@rs,ra",16,0, -0x04, -#endif -"outibr",OPC_outibr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,272}, - - -/* 0001 0111 ssN0 ddN0 *** pop @rd,@rs */ -{ -#ifdef NICENAMES -"pop @rd,@rs",16,12, -0x00, -#endif -"pop",OPC_pop,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),0,0,0,0,0,},2,2,273}, - - -/* 0101 0111 ssN0 ddN0 address_dst *** pop address_dst(rd),@rs */ -{ -#ifdef NICENAMES -"pop address_dst(rd),@rs",16,16, -0x00, -#endif -"pop",OPC_pop,0,{CLASS_X+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,274}, - - -/* 0101 0111 ssN0 0000 address_dst *** pop address_dst,@rs */ -{ -#ifdef NICENAMES -"pop address_dst,@rs",16,16, -0x00, -#endif -"pop",OPC_pop,0,{CLASS_DA+(ARG_DST),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,275}, - - -/* 1001 0111 ssN0 dddd *** pop rd,@rs */ -{ -#ifdef NICENAMES -"pop rd,@rs",16,8, -0x00, -#endif -"pop",OPC_pop,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+7,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,276}, - - -/* 0001 0101 ssN0 ddN0 *** popl @rd,@rs */ -{ -#ifdef NICENAMES -"popl @rd,@rs",32,19, -0x00, -#endif -"popl",OPC_popl,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),0,0,0,0,0,},2,2,277}, - - -/* 0101 0101 ssN0 ddN0 address_dst *** popl address_dst(rd),@rs */ -{ -#ifdef NICENAMES -"popl address_dst(rd),@rs",32,23, -0x00, -#endif -"popl",OPC_popl,0,{CLASS_X+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REGN0+(ARG_RD),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,278}, - - -/* 0101 0101 ssN0 0000 address_dst *** popl address_dst,@rs */ -{ -#ifdef NICENAMES -"popl address_dst,@rs",32,23, -0x00, -#endif -"popl",OPC_popl,0,{CLASS_DA+(ARG_DST),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_BIT+0,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,279}, - - -/* 1001 0101 ssN0 dddd *** popl rrd,@rs */ -{ -#ifdef NICENAMES -"popl rrd,@rs",32,12, -0x00, -#endif -"popl",OPC_popl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+5,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,280}, - - -/* 0001 0011 ddN0 ssN0 *** push @rd,@rs */ -{ -#ifdef NICENAMES -"push @rd,@rs",16,13, -0x00, -#endif -"push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),0,0,0,0,0,},2,2,281}, - - -/* 0101 0011 ddN0 0000 address_src *** push @rd,address_src */ -{ -#ifdef NICENAMES -"push @rd,address_src",16,14, -0x00, -#endif -"push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,282}, - - -/* 0101 0011 ddN0 ssN0 address_src *** push @rd,address_src(rs) */ -{ -#ifdef NICENAMES -"push @rd,address_src(rs)",16,14, -0x00, -#endif -"push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,283}, - - -/* 0000 1101 ddN0 1001 imm16 *** push @rd,imm16 */ -{ -#ifdef NICENAMES -"push @rd,imm16",16,12, -0x00, -#endif -"push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+9,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,284}, - - -/* 1001 0011 ddN0 ssss *** push @rd,rs */ -{ -#ifdef NICENAMES -"push @rd,rs",16,9, -0x00, -#endif -"push",OPC_push,0,{CLASS_IR+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,285}, - - -/* 0001 0001 ddN0 ssN0 *** pushl @rd,@rs */ -{ -#ifdef NICENAMES -"pushl @rd,@rs",32,20, -0x00, -#endif -"pushl",OPC_pushl,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),0,0,0,0,0,},2,2,286}, - - -/* 0101 0001 ddN0 0000 address_src *** pushl @rd,address_src */ -{ -#ifdef NICENAMES -"pushl @rd,address_src",32,21, -0x00, -#endif -"pushl",OPC_pushl,0,{CLASS_IR+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,287}, - - -/* 0101 0001 ddN0 ssN0 address_src *** pushl @rd,address_src(rs) */ -{ -#ifdef NICENAMES -"pushl @rd,address_src(rs)",32,21, -0x00, -#endif -"pushl",OPC_pushl,0,{CLASS_IR+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REGN0+(ARG_RS),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,288}, - - -/* 1001 0001 ddN0 ssss *** pushl @rd,rrs */ -{ -#ifdef NICENAMES -"pushl @rd,rrs",32,12, -0x00, -#endif -"pushl",OPC_pushl,0,{CLASS_IR+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+1,CLASS_REGN0+(ARG_RD),CLASS_REG+(ARG_RS),0,0,0,0,0,},2,2,289}, - - -/* 0010 0011 ddN0 imm4 *** res @rd,imm4 */ -{ -#ifdef NICENAMES -"res @rd,imm4",16,11, -0x00, -#endif -"res",OPC_res,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,290}, - - -/* 0110 0011 ddN0 imm4 address_dst *** res address_dst(rd),imm4 */ -{ -#ifdef NICENAMES -"res address_dst(rd),imm4",16,14, -0x00, -#endif -"res",OPC_res,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+3,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,291}, - - -/* 0110 0011 0000 imm4 address_dst *** res address_dst,imm4 */ -{ -#ifdef NICENAMES -"res address_dst,imm4",16,13, -0x00, -#endif -"res",OPC_res,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+3,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,292}, - - -/* 1010 0011 dddd imm4 *** res rd,imm4 */ -{ -#ifdef NICENAMES -"res rd,imm4",16,4, -0x00, -#endif -"res",OPC_res,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+0xa,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,293}, - - -/* 0010 0011 0000 ssss 0000 dddd 0000 0000 *** res rd,rs */ -{ -#ifdef NICENAMES -"res rd,rs",16,10, -0x00, -#endif -"res",OPC_res,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,294}, - - -/* 0010 0010 ddN0 imm4 *** resb @rd,imm4 */ -{ -#ifdef NICENAMES -"resb @rd,imm4",8,11, -0x00, -#endif -"resb",OPC_resb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,295}, - - -/* 0110 0010 ddN0 imm4 address_dst *** resb address_dst(rd),imm4 */ -{ -#ifdef NICENAMES -"resb address_dst(rd),imm4",8,14, -0x00, -#endif -"resb",OPC_resb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+2,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,296}, - - -/* 0110 0010 0000 imm4 address_dst *** resb address_dst,imm4 */ -{ -#ifdef NICENAMES -"resb address_dst,imm4",8,13, -0x00, -#endif -"resb",OPC_resb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+2,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,297}, - - -/* 1010 0010 dddd imm4 *** resb rbd,imm4 */ -{ -#ifdef NICENAMES -"resb rbd,imm4",8,4, -0x00, -#endif -"resb",OPC_resb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+0xa,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,298}, - - -/* 0010 0010 0000 ssss 0000 dddd 0000 0000 *** resb rbd,rs */ -{ -#ifdef NICENAMES -"resb rbd,rs",8,10, -0x00, -#endif -"resb",OPC_resb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,299}, - - -/* 1000 1101 flags 0011 *** resflg flags */ -{ -#ifdef NICENAMES -"resflg flags",16,7, -0x3c, -#endif -"resflg",OPC_resflg,0,{CLASS_FLAGS,}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_FLAGS,CLASS_BIT+3,0,0,0,0,0,},1,2,300}, - - -/* 1001 1110 0000 cccc *** ret cc */ -{ -#ifdef NICENAMES -"ret cc",16,10, -0x00, -#endif -"ret",OPC_ret,0,{CLASS_CC,}, - {CLASS_BIT+9,CLASS_BIT+0xe,CLASS_BIT+0,CLASS_CC,0,0,0,0,0,},1,2,301}, - - -/* 1011 0011 dddd 00I0 *** rl rd,imm1or2 */ -{ -#ifdef NICENAMES -"rl rd,imm1or2",16,6, -0x3c, -#endif -"rl",OPC_rl,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0,0,0,0,0,0,},2,2,302}, - - -/* 1011 0010 dddd 00I0 *** rlb rbd,imm1or2 */ -{ -#ifdef NICENAMES -"rlb rbd,imm1or2",8,6, -0x3c, -#endif -"rlb",OPC_rlb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0,0,0,0,0,0,},2,2,303}, - - -/* 1011 0011 dddd 10I0 *** rlc rd,imm1or2 */ -{ -#ifdef NICENAMES -"rlc rd,imm1or2",16,6, -0x3c, -#endif -"rlc",OPC_rlc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+8,0,0,0,0,0,},2,2,304}, - - -/* 1011 0010 dddd 10I0 *** rlcb rbd,imm1or2 */ -{ -#ifdef NICENAMES -"rlcb rbd,imm1or2",8,9, -0x10, -#endif -"rlcb",OPC_rlcb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+8,0,0,0,0,0,},2,2,305}, - - -/* 1011 1110 aaaa bbbb *** rldb rbb,rba */ -{ -#ifdef NICENAMES -"rldb rbb,rba",8,9, -0x10, -#endif -"rldb",OPC_rldb,0,{CLASS_REG_BYTE+(ARG_RB),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+0xb,CLASS_BIT+0xe,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RB),0,0,0,0,0,},2,2,306}, - - -/* 1011 0011 dddd 01I0 *** rr rd,imm1or2 */ -{ -#ifdef NICENAMES -"rr rd,imm1or2",16,6, -0x3c, -#endif -"rr",OPC_rr,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+4,0,0,0,0,0,},2,2,307}, - - -/* 1011 0010 dddd 01I0 *** rrb rbd,imm1or2 */ -{ -#ifdef NICENAMES -"rrb rbd,imm1or2",8,6, -0x3c, -#endif -"rrb",OPC_rrb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+4,0,0,0,0,0,},2,2,308}, - - -/* 1011 0011 dddd 11I0 *** rrc rd,imm1or2 */ -{ -#ifdef NICENAMES -"rrc rd,imm1or2",16,6, -0x3c, -#endif -"rrc",OPC_rrc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0xc,0,0,0,0,0,},2,2,309}, - - -/* 1011 0010 dddd 11I0 *** rrcb rbd,imm1or2 */ -{ -#ifdef NICENAMES -"rrcb rbd,imm1or2",8,9, -0x10, -#endif -"rrcb",OPC_rrcb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM1OR2),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT_1OR2+0xc,0,0,0,0,0,},2,2,310}, - - -/* 1011 1100 aaaa bbbb *** rrdb rbb,rba */ -{ -#ifdef NICENAMES -"rrdb rbb,rba",8,9, -0x10, -#endif -"rrdb",OPC_rrdb,0,{CLASS_REG_BYTE+(ARG_RB),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+0xb,CLASS_BIT+0xc,CLASS_REG+(ARG_RA),CLASS_REG+(ARG_RB),0,0,0,0,0,},2,2,311}, - - -/* 0011 0110 imm8 *** rsvd36 */ -{ -#ifdef NICENAMES -"rsvd36",8,10, -0x00, -#endif -"rsvd36",OPC_rsvd36,0,{0}, - {CLASS_BIT+3,CLASS_BIT+6,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,312}, - - -/* 0011 1000 imm8 *** rsvd38 */ -{ -#ifdef NICENAMES -"rsvd38",8,10, -0x00, -#endif -"rsvd38",OPC_rsvd38,0,{0}, - {CLASS_BIT+3,CLASS_BIT+8,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,313}, - - -/* 0111 1000 imm8 *** rsvd78 */ -{ -#ifdef NICENAMES -"rsvd78",8,10, -0x00, -#endif -"rsvd78",OPC_rsvd78,0,{0}, - {CLASS_BIT+7,CLASS_BIT+8,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,314}, - - -/* 0111 1110 imm8 *** rsvd7e */ -{ -#ifdef NICENAMES -"rsvd7e",8,10, -0x00, -#endif -"rsvd7e",OPC_rsvd7e,0,{0}, - {CLASS_BIT+7,CLASS_BIT+0xe,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,315}, - - -/* 1001 1101 imm8 *** rsvd9d */ -{ -#ifdef NICENAMES -"rsvd9d",8,10, -0x00, -#endif -"rsvd9d",OPC_rsvd9d,0,{0}, - {CLASS_BIT+9,CLASS_BIT+0xd,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,316}, - - -/* 1001 1111 imm8 *** rsvd9f */ -{ -#ifdef NICENAMES -"rsvd9f",8,10, -0x00, -#endif -"rsvd9f",OPC_rsvd9f,0,{0}, - {CLASS_BIT+9,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,317}, - - -/* 1011 1001 imm8 *** rsvdb9 */ -{ -#ifdef NICENAMES -"rsvdb9",8,10, -0x00, -#endif -"rsvdb9",OPC_rsvdb9,0,{0}, - {CLASS_BIT+0xb,CLASS_BIT+9,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,318}, - - -/* 1011 1111 imm8 *** rsvdbf */ -{ -#ifdef NICENAMES -"rsvdbf",8,10, -0x00, -#endif -"rsvdbf",OPC_rsvdbf,0,{0}, - {CLASS_BIT+0xb,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},0,2,319}, - - -/* 1011 0111 ssss dddd *** sbc rd,rs */ -{ -#ifdef NICENAMES -"sbc rd,rs",16,5, -0x3c, -#endif -"sbc",OPC_sbc,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+7,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,320}, - - -/* 1011 0110 ssss dddd *** sbcb rbd,rbs */ -{ -#ifdef NICENAMES -"sbcb rbd,rbs",8,5, -0x3f, -#endif -"sbcb",OPC_sbcb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+6,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,321}, - - -/* 0111 1111 imm8 *** sc imm8 */ -{ -#ifdef NICENAMES -"sc imm8",8,33, -0x3f, -#endif -"sc",OPC_sc,0,{CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+7,CLASS_BIT+0xf,CLASS_IMM+(ARG_IMM8),0,0,0,0,0,0,},1,2,322}, - - -/* 1011 0011 dddd 1011 0000 ssss 0000 0000 *** sda rd,rs */ -{ -#ifdef NICENAMES -"sda rd,rs",16,15, -0x3c, -#endif -"sda",OPC_sda,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,323}, - - -/* 1011 0010 dddd 1011 0000 ssss 0000 0000 *** sdab rbd,rs */ -{ -#ifdef NICENAMES -"sdab rbd,rs",8,15, -0x3c, -#endif -"sdab",OPC_sdab,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,324}, - - -/* 1011 0011 dddd 1111 0000 ssss 0000 0000 *** sdal rrd,rs */ -{ -#ifdef NICENAMES -"sdal rrd,rs",32,15, -0x3c, -#endif -"sdal",OPC_sdal,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xf,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,325}, - - -/* 1011 0011 dddd 0011 0000 ssss 0000 0000 *** sdl rd,rs */ -{ -#ifdef NICENAMES -"sdl rd,rs",16,15, -0x38, -#endif -"sdl",OPC_sdl,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,326}, - - -/* 1011 0010 dddd 0011 0000 ssss 0000 0000 *** sdlb rbd,rs */ -{ -#ifdef NICENAMES -"sdlb rbd,rs",8,15, -0x38, -#endif -"sdlb",OPC_sdlb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,327}, - - -/* 1011 0011 dddd 0111 0000 ssss 0000 0000 *** sdll rrd,rs */ -{ -#ifdef NICENAMES -"sdll rrd,rs",32,15, -0x38, -#endif -"sdll",OPC_sdll,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+7,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,328}, - - -/* 0010 0101 ddN0 imm4 *** set @rd,imm4 */ -{ -#ifdef NICENAMES -"set @rd,imm4",16,11, -0x00, -#endif -"set",OPC_set,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+5,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,329}, - - -/* 0110 0101 ddN0 imm4 address_dst *** set address_dst(rd),imm4 */ -{ -#ifdef NICENAMES -"set address_dst(rd),imm4",16,14, -0x00, -#endif -"set",OPC_set,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+5,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,330}, - - -/* 0110 0101 0000 imm4 address_dst *** set address_dst,imm4 */ -{ -#ifdef NICENAMES -"set address_dst,imm4",16,13, -0x00, -#endif -"set",OPC_set,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+5,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,331}, - - -/* 1010 0101 dddd imm4 *** set rd,imm4 */ -{ -#ifdef NICENAMES -"set rd,imm4",16,4, -0x00, -#endif -"set",OPC_set,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+0xa,CLASS_BIT+5,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,332}, - - -/* 0010 0101 0000 ssss 0000 dddd 0000 0000 *** set rd,rs */ -{ -#ifdef NICENAMES -"set rd,rs",16,10, -0x00, -#endif -"set",OPC_set,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+5,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,333}, - - -/* 0010 0100 ddN0 imm4 *** setb @rd,imm4 */ -{ -#ifdef NICENAMES -"setb @rd,imm4",8,11, -0x00, -#endif -"setb",OPC_setb,0,{CLASS_IR+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+2,CLASS_BIT+4,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,334}, - - -/* 0110 0100 ddN0 imm4 address_dst *** setb address_dst(rd),imm4 */ -{ -#ifdef NICENAMES -"setb address_dst(rd),imm4",8,14, -0x00, -#endif -"setb",OPC_setb,0,{CLASS_X+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+4,CLASS_REGN0+(ARG_RD),CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,335}, - - -/* 0110 0100 0000 imm4 address_dst *** setb address_dst,imm4 */ -{ -#ifdef NICENAMES -"setb address_dst,imm4",8,13, -0x00, -#endif -"setb",OPC_setb,0,{CLASS_DA+(ARG_DST),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+6,CLASS_BIT+4,CLASS_BIT+0,CLASS_IMM+(ARG_IMM4),CLASS_ADDRESS+(ARG_DST),0,0,0,0,},2,4,336}, - - -/* 1010 0100 dddd imm4 *** setb rbd,imm4 */ -{ -#ifdef NICENAMES -"setb rbd,imm4",8,4, -0x00, -#endif -"setb",OPC_setb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM +(ARG_IMM4),}, - {CLASS_BIT+0xa,CLASS_BIT+4,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM4),0,0,0,0,0,},2,2,337}, - - -/* 0010 0100 0000 ssss 0000 dddd 0000 0000 *** setb rbd,rs */ -{ -#ifdef NICENAMES -"setb rbd,rs",8,10, -0x00, -#endif -"setb",OPC_setb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+2,CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RS),CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,0,},2,4,338}, - - -/* 1000 1101 flags 0001 *** setflg flags */ -{ -#ifdef NICENAMES -"setflg flags",16,7, -0x3c, -#endif -"setflg",OPC_setflg,0,{CLASS_FLAGS,}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_FLAGS,CLASS_BIT+1,0,0,0,0,0,},1,2,339}, - - -/* 0011 1011 dddd 0101 imm16 *** sin rd,imm16 */ -{ -#ifdef NICENAMES -"sin rd,imm16",8,0, -0x00, -#endif -"sin",OPC_sin,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,340}, - - -/* 0011 1010 dddd 0101 imm16 *** sinb rbd,imm16 */ -{ -#ifdef NICENAMES -"sinb rbd,imm16",8,0, -0x00, -#endif -"sinb",OPC_sinb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,341}, - - -/* 0011 1011 ssN0 1000 0001 aaaa ddN0 1000 *** sind @rd,@rs,ra */ -{ -#ifdef NICENAMES -"sind @rd,@rs,ra",16,0, -0x00, -#endif -"sind",OPC_sind,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+1,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,342}, - - -/* 0011 1010 ssN0 1000 0001 aaaa ddN0 1000 *** sindb @rd,@rs,rba */ -{ -#ifdef NICENAMES -"sindb @rd,@rs,rba",8,0, -0x00, -#endif -"sindb",OPC_sindb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+8,CLASS_BIT+1,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,343}, - - -/* 0011 1010 ssN0 0001 0000 aaaa ddN0 1000 *** sinib @rd,@rs,ra */ -{ -#ifdef NICENAMES -"sinib @rd,@rs,ra",8,0, -0x00, -#endif -"sinib",OPC_sinib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,344}, - - -/* 0011 1010 ssN0 0001 0000 aaaa ddN0 0000 *** sinibr @rd,@rs,ra */ -{ -#ifdef NICENAMES -"sinibr @rd,@rs,ra",16,0, -0x00, -#endif -"sinibr",OPC_sinibr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+1,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,345}, - - -/* 1011 0011 dddd 1001 0000 0000 imm8 *** sla rd,imm8 */ -{ -#ifdef NICENAMES -"sla rd,imm8",16,13, -0x3c, -#endif -"sla",OPC_sla,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,346}, - - -/* 1011 0010 dddd 1001 0000 0000 imm8 *** slab rbd,imm8 */ -{ -#ifdef NICENAMES -"slab rbd,imm8",8,13, -0x3c, -#endif -"slab",OPC_slab,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,347}, - - -/* 1011 0011 dddd 1101 0000 0000 imm8 *** slal rrd,imm8 */ -{ -#ifdef NICENAMES -"slal rrd,imm8",32,13, -0x3c, -#endif -"slal",OPC_slal,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,348}, - - -/* 1011 0011 dddd 0001 0000 0000 imm8 *** sll rd,imm8 */ -{ -#ifdef NICENAMES -"sll rd,imm8",16,13, -0x38, -#endif -"sll",OPC_sll,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,349}, - - -/* 1011 0010 dddd 0001 0000 0000 imm8 *** sllb rbd,imm8 */ -{ -#ifdef NICENAMES -"sllb rbd,imm8",8,13, -0x38, -#endif -"sllb",OPC_sllb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,350}, - - -/* 1011 0011 dddd 0101 0000 0000 imm8 *** slll rrd,imm8 */ -{ -#ifdef NICENAMES -"slll rrd,imm8",32,13, -0x38, -#endif -"slll",OPC_slll,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_IMM8),0,0,},2,4,351}, - - -/* 0011 1011 ssss 0111 imm16 *** sout imm16,rs */ -{ -#ifdef NICENAMES -"sout imm16,rs",16,0, -0x00, -#endif -"sout",OPC_sout,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REG+(ARG_RS),CLASS_BIT+7,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,352}, - - -/* 0011 1010 ssss 0111 imm16 *** soutb imm16,rbs */ -{ -#ifdef NICENAMES -"soutb imm16,rbs",8,0, -0x00, -#endif -"soutb",OPC_soutb,0,{CLASS_IMM+(ARG_IMM16),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REG+(ARG_RS),CLASS_BIT+7,CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,353}, - - -/* 0011 1011 ssN0 1011 0000 aaaa ddN0 1000 *** soutd @rd,@rs,ra */ -{ -#ifdef NICENAMES -"soutd @rd,@rs,ra",16,0, -0x00, -#endif -"soutd",OPC_soutd,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xb,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,354}, - - -/* 0011 1010 ssN0 1011 0000 aaaa ddN0 1000 *** soutdb @rd,@rs,rba */ -{ -#ifdef NICENAMES -"soutdb @rd,@rs,rba",8,0, -0x00, -#endif -"soutdb",OPC_soutdb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+0xb,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,355}, - - -/* 0011 1010 ssN0 0011 0000 aaaa ddN0 1000 *** soutib @rd,@rs,ra */ -{ -#ifdef NICENAMES -"soutib @rd,@rs,ra",8,0, -0x00, -#endif -"soutib",OPC_soutib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,},3,4,356}, - - -/* 0011 1010 ssN0 0011 0000 aaaa ddN0 0000 *** soutibr @rd,@rs,ra */ -{ -#ifdef NICENAMES -"soutibr @rd,@rs,ra",16,0, -0x00, -#endif -"soutibr",OPC_soutibr,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_WORD+(ARG_RA),}, - {CLASS_BIT+3,CLASS_BIT+0xa,CLASS_REGN0+(ARG_RS),CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RD),CLASS_BIT+0,0,},3,4,357}, - - -/* 1011 0011 dddd 1001 1111 1111 nim8 *** sra rd,imm8 */ -{ -#ifdef NICENAMES -"sra rd,imm8",16,13, -0x3c, -#endif -"sra",OPC_sra,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,358}, - - -/* 1011 0010 dddd 1001 0000 0000 nim8 *** srab rbd,imm8 */ -{ -#ifdef NICENAMES -"srab rbd,imm8",8,13, -0x3c, -#endif -"srab",OPC_srab,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+9,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_NIM8),0,0,},2,4,359}, - - -/* 1011 0011 dddd 1101 1111 1111 nim8 *** sral rrd,imm8 */ -{ -#ifdef NICENAMES -"sral rrd,imm8",32,13, -0x3c, -#endif -"sral",OPC_sral,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+0xd,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,360}, - - -/* 1011 0011 dddd 0001 1111 1111 nim8 *** srl rd,imm8 */ -{ -#ifdef NICENAMES -"srl rd,imm8",16,13, -0x3c, -#endif -"srl",OPC_srl,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,361}, - - -/* 1011 0010 dddd 0001 0000 0000 nim8 *** srlb rbd,imm8 */ -{ -#ifdef NICENAMES -"srlb rbd,imm8",8,13, -0x3c, -#endif -"srlb",OPC_srlb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+2,CLASS_REG+(ARG_RD),CLASS_BIT+1,CLASS_BIT+0,CLASS_BIT+0,CLASS_IMM+(ARG_NIM8),0,0,},2,4,362}, - - -/* 1011 0011 dddd 0101 1111 1111 nim8 *** srll rrd,imm8 */ -{ -#ifdef NICENAMES -"srll rrd,imm8",32,13, -0x3c, -#endif -"srll",OPC_srll,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0xb,CLASS_BIT+3,CLASS_REG+(ARG_RD),CLASS_BIT+5,CLASS_BIT+0xf,CLASS_BIT+0xf,CLASS_IMM+(ARG_NIM8),0,0,},2,4,363}, - - -/* 0000 0011 ssN0 dddd *** sub rd,@rs */ -{ -#ifdef NICENAMES -"sub rd,@rs",16,7, -0x3c, -#endif -"sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+3,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,364}, - - -/* 0100 0011 0000 dddd address_src *** sub rd,address_src */ -{ -#ifdef NICENAMES -"sub rd,address_src",16,9, -0x3c, -#endif -"sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,365}, - - -/* 0100 0011 ssN0 dddd address_src *** sub rd,address_src(rs) */ -{ -#ifdef NICENAMES -"sub rd,address_src(rs)",16,10, -0x3c, -#endif -"sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+3,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,366}, - - -/* 0000 0011 0000 dddd imm16 *** sub rd,imm16 */ -{ -#ifdef NICENAMES -"sub rd,imm16",16,7, -0x3c, -#endif -"sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+3,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,367}, - - -/* 1000 0011 ssss dddd *** sub rd,rs */ -{ -#ifdef NICENAMES -"sub rd,rs",16,4, -0x3c, -#endif -"sub",OPC_sub,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+3,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,368}, - - -/* 0000 0010 ssN0 dddd *** subb rbd,@rs */ -{ -#ifdef NICENAMES -"subb rbd,@rs",8,7, -0x3f, -#endif -"subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,369}, - - -/* 0100 0010 0000 dddd address_src *** subb rbd,address_src */ -{ -#ifdef NICENAMES -"subb rbd,address_src",8,9, -0x3f, -#endif -"subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,370}, - - -/* 0100 0010 ssN0 dddd address_src *** subb rbd,address_src(rs) */ -{ -#ifdef NICENAMES -"subb rbd,address_src(rs)",8,10, -0x3f, -#endif -"subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,371}, - - -/* 0000 0010 0000 dddd imm8 imm8 *** subb rbd,imm8 */ -{ -#ifdef NICENAMES -"subb rbd,imm8",8,7, -0x3f, -#endif -"subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,372}, - - -/* 1000 0010 ssss dddd *** subb rbd,rbs */ -{ -#ifdef NICENAMES -"subb rbd,rbs",8,4, -0x3f, -#endif -"subb",OPC_subb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+2,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,373}, - - -/* 0001 0010 ssN0 dddd *** subl rrd,@rs */ -{ -#ifdef NICENAMES -"subl rrd,@rs",32,14, -0x3c, -#endif -"subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+1,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,374}, - - -/* 0101 0010 0000 dddd address_src *** subl rrd,address_src */ -{ -#ifdef NICENAMES -"subl rrd,address_src",32,15, -0x3c, -#endif -"subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+5,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,375}, - - -/* 0101 0010 ssN0 dddd address_src *** subl rrd,address_src(rs) */ -{ -#ifdef NICENAMES -"subl rrd,address_src(rs)",32,16, -0x3c, -#endif -"subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+5,CLASS_BIT+2,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,376}, - - -/* 0001 0010 0000 dddd imm32 *** subl rrd,imm32 */ -{ -#ifdef NICENAMES -"subl rrd,imm32",32,14, -0x3c, -#endif -"subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_IMM+(ARG_IMM32),}, - {CLASS_BIT+1,CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM32),0,0,0,0,},2,6,377}, - - -/* 1001 0010 ssss dddd *** subl rrd,rrs */ -{ -#ifdef NICENAMES -"subl rrd,rrs",32,8, -0x3c, -#endif -"subl",OPC_subl,0,{CLASS_REG_LONG+(ARG_RD),CLASS_REG_LONG+(ARG_RS),}, - {CLASS_BIT+9,CLASS_BIT+2,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,378}, - - -/* 1010 1111 dddd cccc *** tcc cc,rd */ -{ -#ifdef NICENAMES -"tcc cc,rd",16,5, -0x00, -#endif -"tcc",OPC_tcc,0,{CLASS_CC,CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+0xa,CLASS_BIT+0xf,CLASS_REG+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,379}, - - -/* 1010 1110 dddd cccc *** tccb cc,rbd */ -{ -#ifdef NICENAMES -"tccb cc,rbd",8,5, -0x00, -#endif -"tccb",OPC_tccb,0,{CLASS_CC,CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+0xa,CLASS_BIT+0xe,CLASS_REG+(ARG_RD),CLASS_CC,0,0,0,0,0,},2,2,380}, - - -/* 0000 1101 ddN0 0100 *** test @rd */ -{ -#ifdef NICENAMES -"test @rd",16,8, -0x18, -#endif -"test",OPC_test,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,381}, - - -/* 0100 1101 0000 0100 address_dst *** test address_dst */ -{ -#ifdef NICENAMES -"test address_dst",16,11, -0x00, -#endif -"test",OPC_test,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,382}, - - -/* 0100 1101 ddN0 0100 address_dst *** test address_dst(rd) */ -{ -#ifdef NICENAMES -"test address_dst(rd)",16,12, -0x00, -#endif -"test",OPC_test,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,383}, - - -/* 1000 1101 dddd 0100 *** test rd */ -{ -#ifdef NICENAMES -"test rd",16,7, -0x00, -#endif -"test",OPC_test,0,{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,384}, - - -/* 0000 1100 ddN0 0100 *** testb @rd */ -{ -#ifdef NICENAMES -"testb @rd",8,8, -0x1c, -#endif -"testb",OPC_testb,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,385}, - - -/* 0100 1100 0000 0100 address_dst *** testb address_dst */ -{ -#ifdef NICENAMES -"testb address_dst",8,11, -0x1c, -#endif -"testb",OPC_testb,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,386}, - - -/* 0100 1100 ddN0 0100 address_dst *** testb address_dst(rd) */ -{ -#ifdef NICENAMES -"testb address_dst(rd)",8,12, -0x1c, -#endif -"testb",OPC_testb,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,387}, - - -/* 1000 1100 dddd 0100 *** testb rbd */ -{ -#ifdef NICENAMES -"testb rbd",8,7, -0x1c, -#endif -"testb",OPC_testb,0,{CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+4,0,0,0,0,0,},1,2,388}, - - -/* 0001 1100 ddN0 1000 *** testl @rd */ -{ -#ifdef NICENAMES -"testl @rd",32,13, -0x18, -#endif -"testl",OPC_testl,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+1,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,389}, - - -/* 0101 1100 0000 1000 address_dst *** testl address_dst */ -{ -#ifdef NICENAMES -"testl address_dst",32,16, -0x18, -#endif -"testl",OPC_testl,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,390}, - - -/* 0101 1100 ddN0 1000 address_dst *** testl address_dst(rd) */ -{ -#ifdef NICENAMES -"testl address_dst(rd)",32,17, -0x18, -#endif -"testl",OPC_testl,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+5,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,391}, - - -/* 1001 1100 dddd 1000 *** testl rrd */ -{ -#ifdef NICENAMES -"testl rrd",32,13, -0x18, -#endif -"testl",OPC_testl,0,{CLASS_REG_LONG+(ARG_RD),}, - {CLASS_BIT+9,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+8,0,0,0,0,0,},1,2,392}, - - -/* 1011 1000 ddN0 1000 0000 aaaa ssN0 0000 *** trdb @rd,@rs,rba */ -{ -#ifdef NICENAMES -"trdb @rd,@rs,rba",8,25, -0x1c, -#endif -"trdb",OPC_trdb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,393}, - - -/* 1011 1000 ddN0 1100 0000 aaaa ssN0 0000 *** trdrb @rd,@rs,rba */ -{ -#ifdef NICENAMES -"trdrb @rd,@rs,rba",8,25, -0x1c, -#endif -"trdrb",OPC_trdrb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RA),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+0xc,CLASS_BIT+0,CLASS_REG+(ARG_RA),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,394}, - - -/* 1011 1000 ddN0 0000 0000 rrrr ssN0 0000 *** trib @rd,@rs,rbr */ -{ -#ifdef NICENAMES -"trib @rd,@rs,rbr",8,25, -0x1c, -#endif -"trib",OPC_trib,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+0,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,395}, - - -/* 1011 1000 ddN0 0100 0000 rrrr ssN0 0000 *** trirb @rd,@rs,rbr */ -{ -#ifdef NICENAMES -"trirb @rd,@rs,rbr",8,25, -0x1c, -#endif -"trirb",OPC_trirb,0,{CLASS_IR+(ARG_RD),CLASS_IR+(ARG_RS),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RD),CLASS_BIT+4,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RS),CLASS_BIT+0,0,},3,4,396}, - - -/* 1011 1000 aaN0 1010 0000 rrrr bbN0 0000 *** trtdb @ra,@rb,rbr */ -{ -#ifdef NICENAMES -"trtdb @ra,@rb,rbr",8,25, -0x1c, -#endif -"trtdb",OPC_trtdb,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0,0,},3,4,397}, - - -/* 1011 1000 aaN0 1110 0000 rrrr bbN0 1110 *** trtdrb @ra,@rb,rbr */ -{ -#ifdef NICENAMES -"trtdrb @ra,@rb,rbr",8,25, -0x1c, -#endif -"trtdrb",OPC_trtdrb,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+0xe,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0xe,0,},3,4,398}, - - -/* 1011 1000 aaN0 0010 0000 rrrr bbN0 0000 *** trtib @ra,@rb,rbr */ -{ -#ifdef NICENAMES -"trtib @ra,@rb,rbr",8,25, -0x1c, -#endif -"trtib",OPC_trtib,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+2,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0,0,},3,4,399}, - - -/* 1011 1000 aaN0 0110 0000 rrrr bbN0 1110 *** trtirb @ra,@rb,rbr */ -{ -#ifdef NICENAMES -"trtirb @ra,@rb,rbr",8,25, -0x1c, -#endif -"trtirb",OPC_trtirb,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+6,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0xe,0,},3,4,400}, - - -/* 1011 1000 aaN0 1010 0000 rrrr bbN0 0000 *** trtrb @ra,@rb,rbr */ -{ -#ifdef NICENAMES -"trtrb @ra,@rb,rbr",8,25, -0x1c, -#endif -"trtrb",OPC_trtrb,0,{CLASS_IR+(ARG_RA),CLASS_IR+(ARG_RB),CLASS_REG_BYTE+(ARG_RR),}, - {CLASS_BIT+0xb,CLASS_BIT+8,CLASS_REGN0+(ARG_RA),CLASS_BIT+0xa,CLASS_BIT+0,CLASS_REG+(ARG_RR),CLASS_REGN0+(ARG_RB),CLASS_BIT+0,0,},3,4,401}, - - -/* 0000 1101 ddN0 0110 *** tset @rd */ -{ -#ifdef NICENAMES -"tset @rd",16,11, -0x08, -#endif -"tset",OPC_tset,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,402}, - - -/* 0100 1101 0000 0110 address_dst *** tset address_dst */ -{ -#ifdef NICENAMES -"tset address_dst",16,14, -0x08, -#endif -"tset",OPC_tset,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_BIT+0,CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,403}, - - -/* 0100 1101 ddN0 0110 address_dst *** tset address_dst(rd) */ -{ -#ifdef NICENAMES -"tset address_dst(rd)",16,15, -0x08, -#endif -"tset",OPC_tset,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xd,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,404}, - - -/* 1000 1101 dddd 0110 *** tset rd */ -{ -#ifdef NICENAMES -"tset rd",16,7, -0x08, -#endif -"tset",OPC_tset,0,{CLASS_REG_WORD+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xd,CLASS_REG+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,405}, - - -/* 0000 1100 ddN0 0110 *** tsetb @rd */ -{ -#ifdef NICENAMES -"tsetb @rd",8,11, -0x08, -#endif -"tsetb",OPC_tsetb,0,{CLASS_IR+(ARG_RD),}, - {CLASS_BIT+0,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,406}, - - -/* 0100 1100 0000 0110 address_dst *** tsetb address_dst */ -{ -#ifdef NICENAMES -"tsetb address_dst",8,14, -0x08, -#endif -"tsetb",OPC_tsetb,0,{CLASS_DA+(ARG_DST),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_BIT+0,CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,407}, - - -/* 0100 1100 ddN0 0110 address_dst *** tsetb address_dst(rd) */ -{ -#ifdef NICENAMES -"tsetb address_dst(rd)",8,15, -0x08, -#endif -"tsetb",OPC_tsetb,0,{CLASS_X+(ARG_RD),}, - {CLASS_BIT+4,CLASS_BIT+0xc,CLASS_REGN0+(ARG_RD),CLASS_BIT+6,CLASS_ADDRESS+(ARG_DST),0,0,0,0,},1,4,408}, - - -/* 1000 1100 dddd 0110 *** tsetb rbd */ -{ -#ifdef NICENAMES -"tsetb rbd",8,7, -0x08, -#endif -"tsetb",OPC_tsetb,0,{CLASS_REG_BYTE+(ARG_RD),}, - {CLASS_BIT+8,CLASS_BIT+0xc,CLASS_REG+(ARG_RD),CLASS_BIT+6,0,0,0,0,0,},1,2,409}, - - -/* 0000 1001 ssN0 dddd *** xor rd,@rs */ -{ -#ifdef NICENAMES -"xor rd,@rs",16,7, -0x18, -#endif -"xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,410}, - - -/* 0100 1001 0000 dddd address_src *** xor rd,address_src */ -{ -#ifdef NICENAMES -"xor rd,address_src",16,9, -0x18, -#endif -"xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,411}, - - -/* 0100 1001 ssN0 dddd address_src *** xor rd,address_src(rs) */ -{ -#ifdef NICENAMES -"xor rd,address_src(rs)",16,10, -0x18, -#endif -"xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+9,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,412}, - - -/* 0000 1001 0000 dddd imm16 *** xor rd,imm16 */ -{ -#ifdef NICENAMES -"xor rd,imm16",16,7, -0x18, -#endif -"xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_IMM+(ARG_IMM16),}, - {CLASS_BIT+0,CLASS_BIT+9,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM16),0,0,0,0,},2,4,413}, - - -/* 1000 1001 ssss dddd *** xor rd,rs */ -{ -#ifdef NICENAMES -"xor rd,rs",16,4, -0x18, -#endif -"xor",OPC_xor,0,{CLASS_REG_WORD+(ARG_RD),CLASS_REG_WORD+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+9,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,414}, - - -/* 0000 1000 ssN0 dddd *** xorb rbd,@rs */ -{ -#ifdef NICENAMES -"xorb rbd,@rs",8,7, -0x1c, -#endif -"xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IR+(ARG_RS),}, - {CLASS_BIT+0,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,415}, - - -/* 0100 1000 0000 dddd address_src *** xorb rbd,address_src */ -{ -#ifdef NICENAMES -"xorb rbd,address_src",8,9, -0x1c, -#endif -"xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_DA+(ARG_SRC),}, - {CLASS_BIT+4,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,416}, - - -/* 0100 1000 ssN0 dddd address_src *** xorb rbd,address_src(rs) */ -{ -#ifdef NICENAMES -"xorb rbd,address_src(rs)",8,10, -0x1c, -#endif -"xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_X+(ARG_RS),}, - {CLASS_BIT+4,CLASS_BIT+8,CLASS_REGN0+(ARG_RS),CLASS_REG+(ARG_RD),CLASS_ADDRESS+(ARG_SRC),0,0,0,0,},2,4,417}, - - -/* 0000 1000 0000 dddd imm8 imm8 *** xorb rbd,imm8 */ -{ -#ifdef NICENAMES -"xorb rbd,imm8",8,7, -0x1c, -#endif -"xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_IMM+(ARG_IMM8),}, - {CLASS_BIT+0,CLASS_BIT+8,CLASS_BIT+0,CLASS_REG+(ARG_RD),CLASS_IMM+(ARG_IMM8),CLASS_IMM+(ARG_IMM8),0,0,0,},2,4,418}, - - -/* 1000 1000 ssss dddd *** xorb rbd,rbs */ -{ -#ifdef NICENAMES -"xorb rbd,rbs",8,4, -0x1c, -#endif -"xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+8,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,419}, - - -/* 1000 1000 ssss dddd *** xorb rbd,rbs */ -{ -#ifdef NICENAMES -"xorb rbd,rbs",8,4, -0x01, -#endif -"xorb",OPC_xorb,0,{CLASS_REG_BYTE+(ARG_RD),CLASS_REG_BYTE+(ARG_RS),}, - {CLASS_BIT+8,CLASS_BIT+8,CLASS_REG+(ARG_RS),CLASS_REG+(ARG_RD),0,0,0,0,0,},2,2,420}, - -/* end marker */ -{ -#ifdef NICENAMES -NULL,0,0, -0, -#endif -NULL,0,0,{0,0,0,0},{0,0,0,0,0,0,0,0,0,0},0,0,0} -}; -#endif diff --git a/contrib/binutils/opcodes/z8kgen.c b/contrib/binutils/opcodes/z8kgen.c deleted file mode 100644 index f171724..0000000 --- a/contrib/binutils/opcodes/z8kgen.c +++ /dev/null @@ -1,1325 +0,0 @@ -/* - Copyright 2001 Free Software Foundation, Inc. - - This file is part of GNU Binutils. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -/* This program generates z8k-opc.h */ - -#include <stdio.h> -#include "sysdep.h" - -#define BYTE_INFO_LEN 10 - -struct op -{ - char *flags; - int cycles; - char type; - char *bits; - char *name; - char *flavor; -}; - -#define iswhite(x) ((x) == ' ' || (x) == '\t') -struct op opt[] = -{ - "------", 10, 8, "0000 1110 imm8", "ext0e imm8", 0, - "------", 10, 8, "0000 1111 imm8", "ext0f imm8", 0, - "------", 10, 8, "1000 1110 imm8", "ext8e imm8", 0, - "------", 10, 8, "1000 1111 imm8", "ext8f imm8", 0, - - "------", 10, 8, "0011 0110 imm8", "rsvd36", 0, - "------", 10, 8, "0011 1000 imm8", "rsvd38", 0, - "------", 10, 8, "0111 1000 imm8", "rsvd78", 0, - "------", 10, 8, "0111 1110 imm8", "rsvd7e", 0, - - "------", 10, 8, "1001 1101 imm8", "rsvd9d", 0, - "------", 10, 8, "1001 1111 imm8", "rsvd9f", 0, - - "------", 10, 8, "1011 1001 imm8", "rsvdb9", 0, - "------", 10, 8, "1011 1111 imm8", "rsvdbf", 0, - - "---V--", 11, 16, "1011 1011 ssN0 1001 0000 rrrr ddN0 1000", "ldd @rd,@rs,rr", 0, - "---V--", 11, 16, "1011 1011 ssN0 1001 0000 rrrr ddN0 0000", "lddr @rd,@rs,rr", 0, - "---V--", 11, 8, "1011 1010 ssN0 1001 0000 rrrr ddN0 0000", "lddrb @rd,@rs,rr", 0, - "---V--", 11, 16, "1011 1011 ssN0 0001 0000 rrrr ddN0 0000", "ldir @rd,@rs,rr", 0, - "CZSV--", 11, 16, "1011 1011 ssN0 0000 0000 rrrr dddd cccc", "cpi rd,@rs,rr,cc", 0, - "CZSV--", 11, 16, "1011 1011 ssN0 0100 0000 rrrr dddd cccc", "cpir rd,@rs,rr,cc", 0, - "CZSV--", 11, 16, "1011 1011 ssN0 1100 0000 rrrr dddd cccc", "cpdr rd,@rs,rr,cc", 0, - "---V--", 11, 16, "1011 1011 ssN0 0001 0000 rrrr ddN0 1000", "ldi @rd,@rs,rr", 0, - "CZSV--", 11, 16, "1011 1011 ssN0 1000 0000 rrrr dddd cccc", "cpd rd,@rs,rr,cc", 0, - "---V--", 11, 8, "1011 1010 ssN0 0001 0000 rrrr ddN0 0000", "ldirb @rd,@rs,rr", 0, - "---V--", 11, 8, "1011 1010 ssN0 1001 0000 rrrr ddN0 1000", "lddb @rd,@rs,rr", 0, - "---V--", 11, 8, "1011 1010 ssN0 0001 0000 rrrr ddN0 1000", "ldib @rd,@rs,rr", 0, - "CZSV--", 11, 8, "1011 1010 ssN0 1000 0000 rrrr dddd cccc", "cpdb rbd,@rs,rr,cc", 0, - "CZSV--", 11, 8, "1011 1010 ssN0 1100 0000 rrrr dddd cccc", "cpdrb rbd,@rs,rr,cc", 0, - "CZSV--", 11, 8, "1011 1010 ssN0 0000 0000 rrrr dddd cccc", "cpib rbd,@rs,rr,cc", 0, - "CZSV--", 11, 8, "1011 1010 ssN0 0100 0000 rrrr dddd cccc", "cpirb rbd,@rs,rr,cc", 0, - "CZSV--", 11, 16, "1011 1011 ssN0 1010 0000 rrrr ddN0 cccc", "cpsd @rd,@rs,rr,cc", 0, - "CZSV--", 11, 8, "1011 1010 ssN0 1010 0000 rrrr ddN0 cccc", "cpsdb @rd,@rs,rr,cc", 0, - "CZSV--", 11, 16, "1011 1011 ssN0 1110 0000 rrrr ddN0 cccc", "cpsdr @rd,@rs,rr,cc", 0, - "CZSV--", 11, 8, "1011 1010 ssN0 1110 0000 rrrr ddN0 cccc", "cpsdrb @rd,@rs,rr,cc", 0, - "CZSV--", 11, 16, "1011 1011 ssN0 0010 0000 rrrr ddN0 cccc", "cpsi @rd,@rs,rr,cc", 0, - "CZSV--", 11, 8, "1011 1010 ssN0 0010 0000 rrrr ddN0 cccc", "cpsib @rd,@rs,rr,cc", 0, - "CZSV--", 11, 16, "1011 1011 ssN0 0110 0000 rrrr ddN0 cccc", "cpsir @rd,@rs,rr,cc", 0, - "CZSV--", 11, 8, "1011 1010 ssN0 0110 0000 rrrr ddN0 cccc", "cpsirb @rd,@rs,rr,cc", 0, - - "------", 2, 8, "0011 0110 0000 0000", "bpt", 0, - "CZSV--", 5, 16, "1011 0101 ssss dddd", "adc rd,rs", 0, - "CZSVDH", 5, 8, "1011 0100 ssss dddd", "adcb rbd,rbs", 0, - "CZSV--", 7, 16, "0000 0001 ssN0 dddd", "add rd,@rs", 0, - "CZSV--", 9, 16, "0100 0001 0000 dddd address_src", "add rd,address_src", 0, - "CZSV--", 10, 16, "0100 0001 ssN0 dddd address_src", "add rd,address_src(rs)", 0, - "CZSV--", 7, 16, "0000 0001 0000 dddd imm16", "add rd,imm16", 0, - "CZSV--", 4, 16, "1000 0001 ssss dddd", "add rd,rs", 0, - "CZSVDH", 7, 8, "0000 0000 ssN0 dddd", "addb rbd,@rs", 0, - "CZSVDH", 9, 8, "0100 0000 0000 dddd address_src", "addb rbd,address_src", 0, - "CZSVDH", 10, 8, "0100 0000 ssN0 dddd address_src", "addb rbd,address_src(rs)", 0, - "CZSVDH", 7, 8, "0000 0000 0000 dddd imm8 imm8", "addb rbd,imm8", 0, - "CZSVDH", 4, 8, "1000 0000 ssss dddd", "addb rbd,rbs", 0, - "CZSV--", 14, 32, "0001 0110 ssN0 dddd", "addl rrd,@rs", 0, - "CZSV--", 15, 32, "0101 0110 0000 dddd address_src", "addl rrd,address_src", 0, - "CZSV--", 16, 32, "0101 0110 ssN0 dddd address_src", "addl rrd,address_src(rs)", 0, - "CZSV--", 14, 32, "0001 0110 0000 dddd imm32", "addl rrd,imm32", 0, - "CZSV--", 8, 32, "1001 0110 ssss dddd", "addl rrd,rrs", 0, - - "-ZS---", 7, 16, "0000 0111 ssN0 dddd", "and rd,@rs", 0, - "-ZS---", 9, 16, "0100 0111 0000 dddd address_src", "and rd,address_src", 0, - "-ZS---", 10, 16, "0100 0111 ssN0 dddd address_src", "and rd,address_src(rs)", 0, - "-ZS---", 7, 16, "0000 0111 0000 dddd imm16", "and rd,imm16", 0, - "-ZS---", 4, 16, "1000 0111 ssss dddd", "and rd,rs", 0, - "-ZSP--", 7, 8, "0000 0110 ssN0 dddd", "andb rbd,@rs", 0, - "-ZSP--", 9, 8, "0100 0110 0000 dddd address_src", "andb rbd,address_src", 0, - "-ZSP--", 10, 8, "0100 0110 ssN0 dddd address_src", "andb rbd,address_src(rs)", 0, - "-ZSP--", 7, 8, "0000 0110 0000 dddd imm8 imm8", "andb rbd,imm8", 0, - "-ZSP--", 4, 8, "1000 0110 ssss dddd", "andb rbd,rbs", 0, - - "-Z----", 8, 16, "0010 0111 ddN0 imm4", "bit @rd,imm4", 0, - "-Z----", 11, 16, "0110 0111 ddN0 imm4 address_dst", "bit address_dst(rd),imm4", 0, - "-Z----", 10, 16, "0110 0111 0000 imm4 address_dst", "bit address_dst,imm4", 0, - "-Z----", 4, 16, "1010 0111 dddd imm4", "bit rd,imm4", 0, - "-Z----", 10, 16, "0010 0111 0000 ssss 0000 dddd 0000 0000", "bit rd,rs", 0, - - "-Z----", 8, 8, "0010 0110 ddN0 imm4", "bitb @rd,imm4", 0, - "-Z----", 11, 8, "0110 0110 ddN0 imm4 address_dst", "bitb address_dst(rd),imm4", 0, - "-Z----", 10, 8, "0110 0110 0000 imm4 address_dst", "bitb address_dst,imm4", 0, - "-Z----", 4, 8, "1010 0110 dddd imm4", "bitb rbd,imm4", 0, - "-Z----", 10, 8, "0010 0110 0000 ssss 0000 dddd 0000 0000", "bitb rbd,rs", 0, - - "------", 10, 32, "0001 1111 ddN0 0000", "call @rd", 0, - "------", 12, 32, "0101 1111 0000 0000 address_dst", "call address_dst", 0, - "------", 13, 32, "0101 1111 ddN0 0000 address_dst", "call address_dst(rd)", 0, - "------", 10, 16, "1101 disp12", "calr disp12", 0, - - "------", 8, 16, "0000 1101 ddN0 1000", "clr @rd", 0, - "------", 11, 16, "0100 1101 0000 1000 address_dst", "clr address_dst", 0, - "------", 12, 16, "0100 1101 ddN0 1000 address_dst", "clr address_dst(rd)", 0, - "------", 7, 16, "1000 1101 dddd 1000", "clr rd", 0, - "------", 8, 8, "0000 1100 ddN0 1000", "clrb @rd", 0, - "------", 11, 8, "0100 1100 0000 1000 address_dst", "clrb address_dst", 0, - "------", 12, 8, "0100 1100 ddN0 1000 address_dst", "clrb address_dst(rd)", 0, - "------", 7, 8, "1000 1100 dddd 1000", "clrb rbd", 0, - "-ZS---", 12, 16, "0000 1101 ddN0 0000", "com @rd", 0, - "-ZS---", 15, 16, "0100 1101 0000 0000 address_dst", "com address_dst", 0, - "-ZS---", 16, 16, "0100 1101 ddN0 0000 address_dst", "com address_dst(rd)", 0, - "-ZS---", 7, 16, "1000 1101 dddd 0000", "com rd", 0, - "-ZSP--", 12, 8, "0000 1100 ddN0 0000", "comb @rd", 0, - "-ZSP--", 15, 8, "0100 1100 0000 0000 address_dst", "comb address_dst", 0, - "-ZSP--", 16, 8, "0100 1100 ddN0 0000 address_dst", "comb address_dst(rd)", 0, - "-ZSP--", 7, 8, "1000 1100 dddd 0000", "comb rbd", 0, - "CZSP--", 7, 16, "1000 1101 flags 0101", "comflg flags", 0, - - "CZSV--", 11, 16, "0000 1101 ddN0 0001 imm16", "cp @rd,imm16", 0, - "CZSV--", 15, 16, "0100 1101 ddN0 0001 address_dst imm16", "cp address_dst(rd),imm16", 0, - "CZSV--", 14, 16, "0100 1101 0000 0001 address_dst imm16", "cp address_dst,imm16", 0, - - "CZSV--", 7, 16, "0000 1011 ssN0 dddd", "cp rd,@rs", 0, - "CZSV--", 9, 16, "0100 1011 0000 dddd address_src", "cp rd,address_src", 0, - "CZSV--", 10, 16, "0100 1011 ssN0 dddd address_src", "cp rd,address_src(rs)", 0, - "CZSV--", 7, 16, "0000 1011 0000 dddd imm16", "cp rd,imm16", 0, - "CZSV--", 4, 16, "1000 1011 ssss dddd", "cp rd,rs", 0, - - "CZSV--", 11, 8, "0000 1100 ddN0 0001 imm8 imm8", "cpb @rd,imm8", 0, - "CZSV--", 15, 8, "0100 1100 ddN0 0001 address_dst imm8 imm8", "cpb address_dst(rd),imm8", 0, - "CZSV--", 14, 8, "0100 1100 0000 0001 address_dst imm8 imm8", "cpb address_dst,imm8", 0, - "CZSV--", 7, 8, "0000 1010 ssN0 dddd", "cpb rbd,@rs", 0, - "CZSV--", 9, 8, "0100 1010 0000 dddd address_src", "cpb rbd,address_src", 0, - "CZSV--", 10, 8, "0100 1010 ssN0 dddd address_src", "cpb rbd,address_src(rs)", 0, - "CZSV--", 7, 8, "0000 1010 0000 dddd imm8 imm8", "cpb rbd,imm8", 0, - "CZSV--", 4, 8, "1000 1010 ssss dddd", "cpb rbd,rbs", 0, - - "CZSV--", 14, 32, "0001 0000 ssN0 dddd", "cpl rrd,@rs", 0, - "CZSV--", 15, 32, "0101 0000 0000 dddd address_src", "cpl rrd,address_src", 0, - "CZSV--", 16, 32, "0101 0000 ssN0 dddd address_src", "cpl rrd,address_src(rs)", 0, - "CZSV--", 14, 32, "0001 0000 0000 dddd imm32", "cpl rrd,imm32", 0, - "CZSV--", 8, 32, "1001 0000 ssss dddd", "cpl rrd,rrs", 0, - - "CZS---", 5, 8, "1011 0000 dddd 0000", "dab rbd", 0, - "------", 11, 16, "1111 dddd 0disp7", "dbjnz rbd,disp7", 0, - "-ZSV--", 11, 16, "0010 1011 ddN0 imm4m1", "dec @rd,imm4m1", 0, - "-ZSV--", 14, 16, "0110 1011 ddN0 imm4m1 address_dst", "dec address_dst(rd),imm4m1", 0, - "-ZSV--", 13, 16, "0110 1011 0000 imm4m1 address_dst", "dec address_dst,imm4m1", 0, - "-ZSV--", 4, 16, "1010 1011 dddd imm4m1", "dec rd,imm4m1", 0, - "-ZSV--", 11, 8, "0010 1010 ddN0 imm4m1", "decb @rd,imm4m1", 0, - "-ZSV--", 14, 8, "0110 1010 ddN0 imm4m1 address_dst", "decb address_dst(rd),imm4m1", 0, - "-ZSV--", 13, 8, "0110 1010 0000 imm4m1 address_dst", "decb address_dst,imm4m1", 0, - "-ZSV--", 4, 8, "1010 1010 dddd imm4m1", "decb rbd,imm4m1", 0, - - "------", 7, 16, "0111 1100 0000 00ii", "di i2", 0, - "CZSV--", 107, 16, "0001 1011 ssN0 dddd", "div rrd,@rs", 0, - "CZSV--", 107, 16, "0101 1011 0000 dddd address_src", "div rrd,address_src", 0, - "CZSV--", 107, 16, "0101 1011 ssN0 dddd address_src", "div rrd,address_src(rs)", 0, - "CZSV--", 107, 16, "0001 1011 0000 dddd imm16", "div rrd,imm16", 0, - "CZSV--", 107, 16, "1001 1011 ssss dddd", "div rrd,rs", 0, - "CZSV--", 744, 32, "0001 1010 ssN0 dddd", "divl rqd,@rs", 0, - "CZSV--", 745, 32, "0101 1010 0000 dddd address_src", "divl rqd,address_src", 0, - "CZSV--", 746, 32, "0101 1010 ssN0 dddd address_src", "divl rqd,address_src(rs)", 0, - "CZSV--", 744, 32, "0001 1010 0000 dddd imm32", "divl rqd,imm32", 0, - "CZSV--", 744, 32, "1001 1010 ssss dddd", "divl rqd,rrs", 0, - - "------", 11, 16, "1111 dddd 1disp7", "djnz rd,disp7", 0, - "------", 7, 16, "0111 1100 0000 01ii", "ei i2", 0, - "------", 6, 16, "1010 1101 ssss dddd", "ex rd,rs", 0, - "------", 12, 16, "0010 1101 ssN0 dddd", "ex rd,@rs", 0, - "------", 15, 16, "0110 1101 0000 dddd address_src", "ex rd,address_src", 0, - "------", 16, 16, "0110 1101 ssN0 dddd address_src", "ex rd,address_src(rs)", 0, - - "------", 12, 8, "0010 1100 ssN0 dddd", "exb rbd,@rs", 0, - "------", 15, 8, "0110 1100 0000 dddd address_src", "exb rbd,address_src", 0, - "------", 16, 8, "0110 1100 ssN0 dddd address_src", "exb rbd,address_src(rs)", 0, - "------", 6, 8, "1010 1100 ssss dddd", "exb rbd,rbs", 0, - - "------", 11, 16, "1011 0001 dddd 1010", "exts rrd", 0, - "------", 11, 8, "1011 0001 dddd 0000", "extsb rd", 0, - "------", 11, 32, "1011 0001 dddd 0111", "extsl rqd", 0, - - "------", 8, 16, "0111 1010 0000 0000", "halt", 0, - "------", 10, 16, "0011 1101 ssN0 dddd", "in rd,@rs", 0, - "------", 12, 16, "0011 1101 dddd 0100 imm16", "in rd,imm16", 0, - "------", 12, 8, "0011 1100 ssN0 dddd", "inb rbd,@rs", 0, - "------", 10, 8, "0011 1010 dddd 0100 imm16", "inb rbd,imm16", 0, - "-ZSV--", 11, 16, "0010 1001 ddN0 imm4m1", "inc @rd,imm4m1", 0, - "-ZSV--", 14, 16, "0110 1001 ddN0 imm4m1 address_dst", "inc address_dst(rd),imm4m1", 0, - "-ZSV--", 13, 16, "0110 1001 0000 imm4m1 address_dst", "inc address_dst,imm4m1", 0, - "-ZSV--", 4, 16, "1010 1001 dddd imm4m1", "inc rd,imm4m1", 0, - "-ZSV--", 11, 8, "0010 1000 ddN0 imm4m1", "incb @rd,imm4m1", 0, - "-ZSV--", 14, 8, "0110 1000 ddN0 imm4m1 address_dst", "incb address_dst(rd),imm4m1", 0, - "-ZSV--", 13, 8, "0110 1000 0000 imm4m1 address_dst", "incb address_dst,imm4m1", 0, - "-ZSV--", 4, 8, "1010 1000 dddd imm4m1", "incb rbd,imm4m1", 0, - "---V--", 21, 16, "0011 1011 ssN0 1000 0000 aaaa ddN0 1000", "ind @rd,@rs,ra", 0, - "---V--", 21, 8, "0011 1010 ssN0 1000 0000 aaaa ddN0 1000", "indb @rd,@rs,rba", 0, - "---V--", 21, 8, "0011 1010 ssN0 0000 0000 aaaa ddN0 1000", "inib @rd,@rs,ra", 0, - "---V--", 21, 16, "0011 1010 ssN0 0000 0000 aaaa ddN0 0000", "inibr @rd,@rs,ra", 0, - "CZSVDH", 13, 16, "0111 1011 0000 0000", "iret", 0, - "------", 10, 16, "0001 1110 ddN0 cccc", "jp cc,@rd", 0, - "------", 7, 16, "0101 1110 0000 cccc address_dst", "jp cc,address_dst", 0, - "------", 8, 16, "0101 1110 ddN0 cccc address_dst", "jp cc,address_dst(rd)", 0, - "------", 6, 16, "1110 cccc disp8", "jr cc,disp8", 0, - - "------", 7, 16, "0000 1101 ddN0 0101 imm16", "ld @rd,imm16", 0, - "------", 8, 16, "0010 1111 ddN0 ssss", "ld @rd,rs", 0, - "------", 15, 16, "0100 1101 ddN0 0101 address_dst imm16", "ld address_dst(rd),imm16", 0, - "------", 12, 16, "0110 1111 ddN0 ssss address_dst", "ld address_dst(rd),rs", 0, - "------", 14, 16, "0100 1101 0000 0101 address_dst imm16", "ld address_dst,imm16", 0, - "------", 11, 16, "0110 1111 0000 ssss address_dst", "ld address_dst,rs", 0, - "------", 14, 16, "0011 0011 ddN0 ssss imm16", "ld rd(imm16),rs", 0, - "------", 14, 16, "0111 0011 ddN0 ssss 0000 xxxx 0000 0000", "ld rd(rx),rs", 0, - "------", 7, 16, "0010 0001 ssN0 dddd", "ld rd,@rs", 0, - "------", 9, 16, "0110 0001 0000 dddd address_src", "ld rd,address_src", 0, - "------", 10, 16, "0110 0001 ssN0 dddd address_src", "ld rd,address_src(rs)", 0, - "------", 7, 16, "0010 0001 0000 dddd imm16", "ld rd,imm16", 0, - "------", 3, 16, "1010 0001 ssss dddd", "ld rd,rs", 0, - "------", 14, 16, "0011 0001 ssN0 dddd imm16", "ld rd,rs(imm16)", 0, - "------", 14, 16, "0111 0001 ssN0 dddd 0000 xxxx 0000 0000", "ld rd,rs(rx)", 0, - - "------", 7, 8, "0000 1100 ddN0 0101 imm8 imm8", "ldb @rd,imm8", 0, - "------", 8, 8, "0010 1110 ddN0 ssss", "ldb @rd,rbs", 0, - "------", 15, 8, "0100 1100 ddN0 0101 address_dst imm8 imm8", "ldb address_dst(rd),imm8", 0, - "------", 12, 8, "0110 1110 ddN0 ssss address_dst", "ldb address_dst(rd),rbs", 0, - "------", 14, 8, "0100 1100 0000 0101 address_dst imm8 imm8", "ldb address_dst,imm8", 0, - "------", 11, 8, "0110 1110 0000 ssss address_dst", "ldb address_dst,rbs", 0, - "------", 14, 8, "0011 0010 ddN0 ssss imm16", "ldb rd(imm16),rbs", 0, - "------", 14, 8, "0111 0010 ddN0 ssss 0000 xxxx 0000 0000", "ldb rd(rx),rbs", 0, - "------", 7, 8, "0010 0000 ssN0 dddd", "ldb rbd,@rs", 0, - "------", 9, 8, "0110 0000 0000 dddd address_src", "ldb rbd,address_src", 0, - "------", 10, 8, "0110 0000 ssN0 dddd address_src", "ldb rbd,address_src(rs)", 0, - "------", 5, 8, "1100 dddd imm8", "ldb rbd,imm8", 0, - "------", 3, 8, "1010 0000 ssss dddd", "ldb rbd,rbs", 0, - "------", 14, 8, "0011 0000 ssN0 dddd imm16", "ldb rbd,rs(imm16)", 0, - "------", 14, 8, "0111 0000 ssN0 dddd 0000 xxxx 0000 0000", "ldb rbd,rs(rx)", 0, - - "------", 11, 32, "0001 1101 ddN0 ssss", "ldl @rd,rrs", 0, - "------", 14, 32, "0101 1101 ddN0 ssss address_dst", "ldl address_dst(rd),rrs", 0, - "------", 15, 32, "0101 1101 0000 ssss address_dst", "ldl address_dst,rrs", 0, - "------", 17, 32, "0011 0111 ddN0 ssss imm16", "ldl rd(imm16),rrs", 0, - "------", 17, 32, "0111 0111 ddN0 ssss 0000 xxxx 0000 0000", "ldl rd(rx),rrs", 0, - "------", 11, 32, "0001 0100 ssN0 dddd", "ldl rrd,@rs", 0, - "------", 12, 32, "0101 0100 0000 dddd address_src", "ldl rrd,address_src", 0, - "------", 13, 32, "0101 0100 ssN0 dddd address_src", "ldl rrd,address_src(rs)", 0, - "------", 11, 32, "0001 0100 0000 dddd imm32", "ldl rrd,imm32", 0, - "------", 5, 32, "1001 0100 ssss dddd", "ldl rrd,rrs", 0, - "------", 17, 32, "0011 0101 ssN0 dddd imm16", "ldl rrd,rs(imm16)", 0, - "------", 17, 32, "0111 0101 ssN0 dddd 0000 xxxx 0000 0000", "ldl rrd,rs(rx)", 0, - - "------", 12, 16, "0111 0110 0000 dddd address_src", "lda prd,address_src", 0, - "------", 13, 16, "0111 0110 ssN0 dddd address_src", "lda prd,address_src(rs)", 0, - "------", 15, 16, "0011 0100 ssN0 dddd imm16", "lda prd,rs(imm16)", 0, - "------", 15, 16, "0111 0100 ssN0 dddd 0000 xxxx 0000 0000", "lda prd,rs(rx)", 0, - "------", 15, 16, "0011 0100 0000 dddd disp16", "ldar prd,disp16", 0, - "------", 7, 32, "0111 1101 ssss 1ccc", "ldctl ctrl,rs", 0, - "------", 7, 32, "0111 1101 dddd 0ccc", "ldctl rd,ctrl", 0, - - "------", 5, 16, "1011 1101 dddd imm4", "ldk rd,imm4", 0, - - "------", 11, 16, "0001 1100 ddN0 1001 0000 ssss 0000 nminus1", "ldm @rd,rs,n", 0, - "------", 15, 16, "0101 1100 ddN0 1001 0000 ssss 0000 nminus1 address_dst", "ldm address_dst(rd),rs,n", 0, - "------", 14, 16, "0101 1100 0000 1001 0000 ssss 0000 nminus1 address_dst", "ldm address_dst,rs,n", 0, - "------", 11, 16, "0001 1100 ssN0 0001 0000 dddd 0000 nminus1", "ldm rd,@rs,n", 0, - "------", 15, 16, "0101 1100 ssN0 0001 0000 dddd 0000 nminus1 address_src", "ldm rd,address_src(rs),n", 0, - "------", 14, 16, "0101 1100 0000 0001 0000 dddd 0000 nminus1 address_src", "ldm rd,address_src,n", 0, - - "CZSVDH", 12, 16, "0011 1001 ssN0 0000", "ldps @rs", 0, - "CZSVDH", 16, 16, "0111 1001 0000 0000 address_src", "ldps address_src", 0, - "CZSVDH", 17, 16, "0111 1001 ssN0 0000 address_src", "ldps address_src(rs)", 0, - - "------", 14, 16, "0011 0011 0000 ssss disp16", "ldr disp16,rs", 0, - "------", 14, 16, "0011 0001 0000 dddd disp16", "ldr rd,disp16", 0, - "------", 14, 8, "0011 0010 0000 ssss disp16", "ldrb disp16,rbs", 0, - "------", 14, 8, "0011 0000 0000 dddd disp16", "ldrb rbd,disp16", 0, - "------", 17, 32, "0011 0111 0000 ssss disp16", "ldrl disp16,rrs", 0, - "------", 17, 32, "0011 0101 0000 dddd disp16", "ldrl rrd,disp16", 0, - - "CZS---", 7, 16, "0111 1011 0000 1010", "mbit", 0, - "-ZS---", 12, 16, "0111 1011 dddd 1101", "mreq rd", 0, - "------", 5, 16, "0111 1011 0000 1001", "mres", 0, - "------", 5, 16, "0111 1011 0000 1000", "mset", 0, - - "CZSV--", 70, 16, "0001 1001 ssN0 dddd", "mult rrd,@rs", 0, - "CZSV--", 70, 16, "0101 1001 0000 dddd address_src", "mult rrd,address_src", 0, - "CZSV--", 70, 16, "0101 1001 ssN0 dddd address_src", "mult rrd,address_src(rs)", 0, - "CZSV--", 70, 16, "0001 1001 0000 dddd imm16", "mult rrd,imm16", 0, - "CZSV--", 70, 16, "1001 1001 ssss dddd", "mult rrd,rs", 0, - "CZSV--", 282, 32, "0001 1000 ssN0 dddd", "multl rqd,@rs", 0, - "CZSV--", 282, 32, "0101 1000 0000 dddd address_src", "multl rqd,address_src", 0, - "CZSV--", 282, 32, "0101 1000 ssN0 dddd address_src", "multl rqd,address_src(rs)", 0, - "CZSV--", 282, 32, "0001 1000 0000 dddd imm32", "multl rqd,imm32", 0, - "CZSV--", 282, 32, "1001 1000 ssss dddd", "multl rqd,rrs", 0, - "CZSV--", 12, 16, "0000 1101 ddN0 0010", "neg @rd", 0, - "CZSV--", 15, 16, "0100 1101 0000 0010 address_dst", "neg address_dst", 0, - "CZSV--", 16, 16, "0100 1101 ddN0 0010 address_dst", "neg address_dst(rd)", 0, - "CZSV--", 7, 16, "1000 1101 dddd 0010", "neg rd", 0, - "CZSV--", 12, 8, "0000 1100 ddN0 0010", "negb @rd", 0, - "CZSV--", 15, 8, "0100 1100 0000 0010 address_dst", "negb address_dst", 0, - "CZSV--", 16, 8, "0100 1100 ddN0 0010 address_dst", "negb address_dst(rd)", 0, - "CZSV--", 7, 8, "1000 1100 dddd 0010", "negb rbd", 0, - - "------", 7, 16, "1000 1101 0000 0111", "nop", 0, - - "CZS---", 7, 16, "0000 0101 ssN0 dddd", "or rd,@rs", 0, - "CZS---", 9, 16, "0100 0101 0000 dddd address_src", "or rd,address_src", 0, - "CZS---", 10, 16, "0100 0101 ssN0 dddd address_src", "or rd,address_src(rs)", 0, - "CZS---", 7, 16, "0000 0101 0000 dddd imm16", "or rd,imm16", 0, - "CZS---", 4, 16, "1000 0101 ssss dddd", "or rd,rs", 0, - - "CZSP--", 7, 8, "0000 0100 ssN0 dddd", "orb rbd,@rs", 0, - "CZSP--", 9, 8, "0100 0100 0000 dddd address_src", "orb rbd,address_src", 0, - "CZSP--", 10, 8, "0100 0100 ssN0 dddd address_src", "orb rbd,address_src(rs)", 0, - "CZSP--", 7, 8, "0000 0100 0000 dddd imm8 imm8", "orb rbd,imm8", 0, - "CZSP--", 4, 8, "1000 0100 ssss dddd", "orb rbd,rbs", 0, - - "---V--", 0, 16, "0011 1111 ddN0 ssss", "out @rd,rs", 0, - "---V--", 0, 16, "0011 1011 ssss 0110 imm16", "out imm16,rs", 0, - "---V--", 0, 8, "0011 1110 ddN0 ssss", "outb @rd,rbs", 0, - "---V--", 0, 8, "0011 1010 ssss 0110 imm16", "outb imm16,rbs", 0, - "---V--", 0, 16, "0011 1011 ssN0 1010 0000 aaaa ddN0 1000", "outd @rd,@rs,ra", 0, - "---V--", 0, 16, "0011 1010 ssN0 1010 0000 aaaa ddN0 1000", "outdb @rd,@rs,rba", 0, - "---V--", 0, 16, "0011 1011 ssN0 0010 0000 aaaa ddN0 1000", "outi @rd,@rs,ra", 0, - "---V--", 0, 16, "0011 1010 ssN0 0010 0000 aaaa ddN0 1000", "outib @rd,@rs,ra", 0, - "---V--", 0, 16, "0011 1010 ssN0 0010 0000 aaaa ddN0 0000", "outibr @rd,@rs,ra", 0, - - "------", 12, 16, "0001 0111 ssN0 ddN0", "pop @rd,@rs", 0, - "------", 16, 16, "0101 0111 ssN0 ddN0 address_dst", "pop address_dst(rd),@rs", 0, - "------", 16, 16, "0101 0111 ssN0 0000 address_dst", "pop address_dst,@rs", 0, - "------", 8, 16, "1001 0111 ssN0 dddd", "pop rd,@rs", 0, - - "------", 19, 32, "0001 0101 ssN0 ddN0", "popl @rd,@rs", 0, - "------", 23, 32, "0101 0101 ssN0 ddN0 address_dst", "popl address_dst(rd),@rs", 0, - "------", 23, 32, "0101 0101 ssN0 0000 address_dst", "popl address_dst,@rs", 0, - "------", 12, 32, "1001 0101 ssN0 dddd", "popl rrd,@rs", 0, - - "------", 13, 16, "0001 0011 ddN0 ssN0", "push @rd,@rs", 0, - "------", 14, 16, "0101 0011 ddN0 0000 address_src", "push @rd,address_src", 0, - "------", 14, 16, "0101 0011 ddN0 ssN0 address_src", "push @rd,address_src(rs)", 0, - "------", 12, 16, "0000 1101 ddN0 1001 imm16", "push @rd,imm16", 0, - "------", 9, 16, "1001 0011 ddN0 ssss", "push @rd,rs", 0, - - "------", 20, 32, "0001 0001 ddN0 ssN0", "pushl @rd,@rs", 0, - "------", 21, 32, "0101 0001 ddN0 ssN0 address_src", "pushl @rd,address_src(rs)", 0, - "------", 21, 32, "0101 0001 ddN0 0000 address_src", "pushl @rd,address_src", 0, - "------", 12, 32, "1001 0001 ddN0 ssss", "pushl @rd,rrs", 0, - - "------", 11, 16, "0010 0011 ddN0 imm4", "res @rd,imm4", 0, - "------", 14, 16, "0110 0011 ddN0 imm4 address_dst", "res address_dst(rd),imm4", 0, - "------", 13, 16, "0110 0011 0000 imm4 address_dst", "res address_dst,imm4", 0, - "------", 4, 16, "1010 0011 dddd imm4", "res rd,imm4", 0, - "------", 10, 16, "0010 0011 0000 ssss 0000 dddd 0000 0000", "res rd,rs", 0, - - "------", 11, 8, "0010 0010 ddN0 imm4", "resb @rd,imm4", 0, - "------", 14, 8, "0110 0010 ddN0 imm4 address_dst", "resb address_dst(rd),imm4", 0, - "------", 13, 8, "0110 0010 0000 imm4 address_dst", "resb address_dst,imm4", 0, - "------", 4, 8, "1010 0010 dddd imm4", "resb rbd,imm4", 0, - "------", 10, 8, "0010 0010 0000 ssss 0000 dddd 0000 0000", "resb rbd,rs", 0, - - "CZSV--", 7, 16, "1000 1101 flags 0011", "resflg flags", 0, - "------", 10, 16, "1001 1110 0000 cccc", "ret cc", 0, - - "CZSV--", 6, 16, "1011 0011 dddd 00I0", "rl rd,imm1or2", 0, - "CZSV--", 6, 8, "1011 0010 dddd 00I0", "rlb rbd,imm1or2", 0, - "CZSV--", 6, 16, "1011 0011 dddd 10I0", "rlc rd,imm1or2", 0, - - "-Z----", 9, 8, "1011 0010 dddd 10I0", "rlcb rbd,imm1or2", 0, - "-Z----", 9, 8, "1011 1110 aaaa bbbb", "rldb rbb,rba", 0, - - "CZSV--", 6, 16, "1011 0011 dddd 01I0", "rr rd,imm1or2", 0, - "CZSV--", 6, 8, "1011 0010 dddd 01I0", "rrb rbd,imm1or2", 0, - "CZSV--", 6, 16, "1011 0011 dddd 11I0", "rrc rd,imm1or2", 0, - - "-Z----", 9, 8, "1011 0010 dddd 11I0", "rrcb rbd,imm1or2", 0, - "-Z----", 9, 8, "1011 1100 aaaa bbbb", "rrdb rbb,rba", 0, - "CZSV--", 5, 16, "1011 0111 ssss dddd", "sbc rd,rs", 0, - "CZSVDH", 5, 8, "1011 0110 ssss dddd", "sbcb rbd,rbs", 0, - - "CZSVDH", 33, 8, "0111 1111 imm8", "sc imm8", 0, - - "CZSV--", 15, 16, "1011 0011 dddd 1011 0000 ssss 0000 0000", "sda rd,rs", 0, - "CZSV--", 15, 8, "1011 0010 dddd 1011 0000 ssss 0000 0000", "sdab rbd,rs", 0, - "CZSV--", 15, 32, "1011 0011 dddd 1111 0000 ssss 0000 0000", "sdal rrd,rs", 0, - - "CZS---", 15, 16, "1011 0011 dddd 0011 0000 ssss 0000 0000", "sdl rd,rs", 0, - "CZS---", 15, 8, "1011 0010 dddd 0011 0000 ssss 0000 0000", "sdlb rbd,rs", 0, - "CZS---", 15, 32, "1011 0011 dddd 0111 0000 ssss 0000 0000", "sdll rrd,rs", 0, - - "------", 11, 16, "0010 0101 ddN0 imm4", "set @rd,imm4", 0, - "------", 14, 16, "0110 0101 ddN0 imm4 address_dst", "set address_dst(rd),imm4", 0, - "------", 13, 16, "0110 0101 0000 imm4 address_dst", "set address_dst,imm4", 0, - "------", 4, 16, "1010 0101 dddd imm4", "set rd,imm4", 0, - "------", 10, 16, "0010 0101 0000 ssss 0000 dddd 0000 0000", "set rd,rs", 0, - "------", 11, 8, "0010 0100 ddN0 imm4", "setb @rd,imm4", 0, - "------", 14, 8, "0110 0100 ddN0 imm4 address_dst", "setb address_dst(rd),imm4", 0, - "------", 13, 8, "0110 0100 0000 imm4 address_dst", "setb address_dst,imm4", 0, - "------", 4, 8, "1010 0100 dddd imm4", "setb rbd,imm4", 0, - "------", 10, 8, "0010 0100 0000 ssss 0000 dddd 0000 0000", "setb rbd,rs", 0, - - "CZSV--", 7, 16, "1000 1101 flags 0001", "setflg flags", 0, - - "------", 0, 8, "0011 1010 dddd 0101 imm16", "sinb rbd,imm16", 0, - "------", 0, 8, "0011 1011 dddd 0101 imm16", "sin rd,imm16", 0, - "------", 0, 16, "0011 1011 ssN0 1000 0001 aaaa ddN0 1000", "sind @rd,@rs,ra", 0, - "------", 0, 8, "0011 1010 ssN0 1000 0001 aaaa ddN0 1000", "sindb @rd,@rs,rba", 0, - "------", 0, 8, "0011 1010 ssN0 0001 0000 aaaa ddN0 1000", "sinib @rd,@rs,ra", 0, - "------", 0, 16, "0011 1010 ssN0 0001 0000 aaaa ddN0 0000", "sinibr @rd,@rs,ra", 0, - - "CZSV--", 13, 16, "1011 0011 dddd 1001 0000 0000 imm8", "sla rd,imm8", 0, - "CZSV--", 13, 8, "1011 0010 dddd 1001 0000 0000 imm8", "slab rbd,imm8", 0, - "CZSV--", 13, 32, "1011 0011 dddd 1101 0000 0000 imm8", "slal rrd,imm8", 0, - - "CZS---", 13, 16, "1011 0011 dddd 0001 0000 0000 imm8", "sll rd,imm8", 0, - "CZS---", 13, 8, "1011 0010 dddd 0001 0000 0000 imm8", "sllb rbd,imm8", 0, - "CZS---", 13, 32, "1011 0011 dddd 0101 0000 0000 imm8", "slll rrd,imm8", 0, - - "------", 0, 16, "0011 1011 ssss 0111 imm16", "sout imm16,rs", 0, - "------", 0, 8, "0011 1010 ssss 0111 imm16", "soutb imm16,rbs", 0, - "------", 0, 16, "0011 1011 ssN0 1011 0000 aaaa ddN0 1000", "soutd @rd,@rs,ra", 0, - "------", 0, 8, "0011 1010 ssN0 1011 0000 aaaa ddN0 1000", "soutdb @rd,@rs,rba", 0, - "------", 0, 8, "0011 1010 ssN0 0011 0000 aaaa ddN0 1000", "soutib @rd,@rs,ra", 0, - "------", 0, 16, "0011 1010 ssN0 0011 0000 aaaa ddN0 0000", "soutibr @rd,@rs,ra", 0, - - "CZSV--", 13, 16, "1011 0011 dddd 1001 1111 1111 nim8", "sra rd,imm8", 0, - "CZSV--", 13, 8, "1011 0010 dddd 1001 0000 0000 nim8", "srab rbd,imm8", 0, - "CZSV--", 13, 32, "1011 0011 dddd 1101 1111 1111 nim8", "sral rrd,imm8", 0, - - "CZSV--", 13, 16, "1011 0011 dddd 0001 1111 1111 nim8", "srl rd,imm8", 0, - "CZSV--", 13, 8, "1011 0010 dddd 0001 0000 0000 nim8", "srlb rbd,imm8", 0, - "CZSV--", 13, 32, "1011 0011 dddd 0101 1111 1111 nim8", "srll rrd,imm8", 0, - - "CZSV--", 7, 16, "0000 0011 ssN0 dddd", "sub rd,@rs", 0, - "CZSV--", 9, 16, "0100 0011 0000 dddd address_src", "sub rd,address_src", 0, - "CZSV--", 10, 16, "0100 0011 ssN0 dddd address_src", "sub rd,address_src(rs)", 0, - "CZSV--", 7, 16, "0000 0011 0000 dddd imm16", "sub rd,imm16", 0, - "CZSV--", 4, 16, "1000 0011 ssss dddd", "sub rd,rs", 0, - - "CZSVDH", 7, 8, "0000 0010 ssN0 dddd", "subb rbd,@rs", 0, - "CZSVDH", 9, 8, "0100 0010 0000 dddd address_src", "subb rbd,address_src", 0, - "CZSVDH", 10, 8, "0100 0010 ssN0 dddd address_src", "subb rbd,address_src(rs)", 0, - "CZSVDH", 7, 8, "0000 0010 0000 dddd imm8 imm8", "subb rbd,imm8", 0, - "CZSVDH", 4, 8, "1000 0010 ssss dddd", "subb rbd,rbs", 0, - - "CZSV--", 14, 32, "0001 0010 ssN0 dddd", "subl rrd,@rs", 0, - "CZSV--", 15, 32, "0101 0010 0000 dddd address_src", "subl rrd,address_src", 0, - "CZSV--", 16, 32, "0101 0010 ssN0 dddd address_src", "subl rrd,address_src(rs)", 0, - "CZSV--", 14, 32, "0001 0010 0000 dddd imm32", "subl rrd,imm32", 0, - "CZSV--", 8, 32, "1001 0010 ssss dddd", "subl rrd,rrs", 0, - - "------", 5, 16, "1010 1111 dddd cccc", "tcc cc,rd", 0, - "------", 5, 8, "1010 1110 dddd cccc", "tccb cc,rbd", 0, - - "-ZS---", 8, 16, "0000 1101 ddN0 0100", "test @rd", 0, - "------", 11, 16, "0100 1101 0000 0100 address_dst", "test address_dst", 0, - "------", 12, 16, "0100 1101 ddN0 0100 address_dst", "test address_dst(rd)", 0, - "------", 7, 16, "1000 1101 dddd 0100", "test rd", 0, - - "-ZSP--", 8, 8, "0000 1100 ddN0 0100", "testb @rd", 0, - "-ZSP--", 11, 8, "0100 1100 0000 0100 address_dst", "testb address_dst", 0, - "-ZSP--", 12, 8, "0100 1100 ddN0 0100 address_dst", "testb address_dst(rd)", 0, - "-ZSP--", 7, 8, "1000 1100 dddd 0100", "testb rbd", 0, - - "-ZS---", 13, 32, "0001 1100 ddN0 1000", "testl @rd", 0, - "-ZS---", 16, 32, "0101 1100 0000 1000 address_dst", "testl address_dst", 0, - "-ZS---", 17, 32, "0101 1100 ddN0 1000 address_dst", "testl address_dst(rd)", 0, - "-ZS---", 13, 32, "1001 1100 dddd 1000", "testl rrd", 0, - - "-ZSV--", 25, 8, "1011 1000 ddN0 1000 0000 aaaa ssN0 0000", "trdb @rd,@rs,rba", 0, - "-ZSV--", 25, 8, "1011 1000 ddN0 1100 0000 aaaa ssN0 0000", "trdrb @rd,@rs,rba", 0, - "-ZSV--", 25, 8, "1011 1000 ddN0 0000 0000 rrrr ssN0 0000", "trib @rd,@rs,rbr", 0, - "-ZSV--", 25, 8, "1011 1000 ddN0 0100 0000 rrrr ssN0 0000", "trirb @rd,@rs,rbr", 0, - "-ZSV--", 25, 8, "1011 1000 aaN0 1010 0000 rrrr bbN0 0000", "trtdb @ra,@rb,rbr", 0, - "-ZSV--", 25, 8, "1011 1000 aaN0 1110 0000 rrrr bbN0 1110", "trtdrb @ra,@rb,rbr", 0, - "-ZSV--", 25, 8, "1011 1000 aaN0 0010 0000 rrrr bbN0 0000", "trtib @ra,@rb,rbr", 0, - "-ZSV--", 25, 8, "1011 1000 aaN0 0110 0000 rrrr bbN0 1110", "trtirb @ra,@rb,rbr", 0, - "-ZSV--", 25, 8, "1011 1000 aaN0 1010 0000 rrrr bbN0 0000", "trtrb @ra,@rb,rbr", 0, - - "--S---", 11, 16, "0000 1101 ddN0 0110", "tset @rd", 0, - "--S---", 14, 16, "0100 1101 0000 0110 address_dst", "tset address_dst", 0, - "--S---", 15, 16, "0100 1101 ddN0 0110 address_dst", "tset address_dst(rd)", 0, - "--S---", 7, 16, "1000 1101 dddd 0110", "tset rd", 0, - - "--S---", 11, 8, "0000 1100 ddN0 0110", "tsetb @rd", 0, - "--S---", 14, 8, "0100 1100 0000 0110 address_dst", "tsetb address_dst", 0, - "--S---", 15, 8, "0100 1100 ddN0 0110 address_dst", "tsetb address_dst(rd)", 0, - "--S---", 7, 8, "1000 1100 dddd 0110", "tsetb rbd", 0, - - "-ZS---", 7, 16, "0000 1001 ssN0 dddd", "xor rd,@rs", 0, - "-ZS---", 9, 16, "0100 1001 0000 dddd address_src", "xor rd,address_src", 0, - "-ZS---", 10, 16, "0100 1001 ssN0 dddd address_src", "xor rd,address_src(rs)", 0, - "-ZS---", 7, 16, "0000 1001 0000 dddd imm16", "xor rd,imm16", 0, - "-ZS---", 4, 16, "1000 1001 ssss dddd", "xor rd,rs", 0, - - "-ZSP--", 7, 8, "0000 1000 ssN0 dddd", "xorb rbd,@rs", 0, - "-ZSP--", 9, 8, "0100 1000 0000 dddd address_src", "xorb rbd,address_src", 0, - "-ZSP--", 10, 8, "0100 1000 ssN0 dddd address_src", "xorb rbd,address_src(rs)", 0, - "-ZSP--", 7, 8, "0000 1000 0000 dddd imm8 imm8", "xorb rbd,imm8", 0, - "-ZSP--", 4, 8, "1000 1000 ssss dddd", "xorb rbd,rbs", 0, - - "------", 7, 32, "1000 1100 dddd 0001", "ldctlb rbd,ctrl", 0, - "CZSVDH", 7, 32, "1000 1100 ssss 1001", "ldctlb ctrl,rbs", 0, - - "*", 4, 8, "1000 1000 ssss dddd", "xorb rbd,rbs", 0, - "*", 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -}; - -int -count () -{ - struct op *p = opt; - int r = 0; - - while (p->name) - { - r++; - p++; - } - return r; - -} - -static -int -func (a, b) - struct op *a; - struct op *b; -{ - return strcmp ((a)->name, (b)->name); -} - - -/* opcode - - literal 0000 nnnn insert nnn into stream - operand 0001 nnnn insert operand reg nnn into stream -*/ - -struct tok_struct -{ - - char *match; - char *token; - int length; -}; - -struct tok_struct args[] = -{ - - {"address_src(rs)", "CLASS_X+(ARG_RS)",}, - {"address_dst(rd)", "CLASS_X+(ARG_RD)",}, - - {"rs(imm16)", "CLASS_BA+(ARG_RS)",}, - {"rd(imm16)", "CLASS_BA+(ARG_RD)",}, - {"prd", "CLASS_PR+(ARG_RD)",}, - {"address_src", "CLASS_DA+(ARG_SRC)",}, - {"address_dst", "CLASS_DA+(ARG_DST)",}, - {"rd(rx)", "CLASS_BX+(ARG_RD)",}, - {"rs(rx)", "CLASS_BX+(ARG_RS)",}, - - {"disp16", "CLASS_DISP",}, - {"disp12", "CLASS_DISP",}, - {"disp7", "CLASS_DISP",}, - {"disp8", "CLASS_DISP",}, - {"flags", "CLASS_FLAGS",}, - - {"imm16", "CLASS_IMM+(ARG_IMM16)",}, - {"imm1or2", "CLASS_IMM+(ARG_IMM1OR2)",}, - {"imm32", "CLASS_IMM+(ARG_IMM32)",}, - {"imm4m1", "CLASS_IMM +(ARG_IMM4M1)",}, - {"imm4", "CLASS_IMM +(ARG_IMM4)",}, - {"n", "CLASS_IMM + (ARG_IMMN)",}, - {"ctrl", "CLASS_CTRL",}, - {"rba", "CLASS_REG_BYTE+(ARG_RA)",}, - {"rbb", "CLASS_REG_BYTE+(ARG_RB)",}, - {"rbd", "CLASS_REG_BYTE+(ARG_RD)",}, - {"rbs", "CLASS_REG_BYTE+(ARG_RS)",}, - {"rbr", "CLASS_REG_BYTE+(ARG_RR)",}, - - {"rrd", "CLASS_REG_LONG+(ARG_RD)",}, - {"rrs", "CLASS_REG_LONG+(ARG_RS)",}, - - {"rqd", "CLASS_REG_QUAD+(ARG_RD)",}, - - {"rd", "CLASS_REG_WORD+(ARG_RD)",}, - {"rs", "CLASS_REG_WORD+(ARG_RS)",}, - - {"@rd", "CLASS_IR+(ARG_RD)",}, - {"@ra", "CLASS_IR+(ARG_RA)",}, - {"@rb", "CLASS_IR+(ARG_RB)",}, - {"@rs", "CLASS_IR+(ARG_RS)",}, - - {"imm8", "CLASS_IMM+(ARG_IMM8)",}, - {"i2", "CLASS_IMM+(ARG_IMM2)",}, - {"cc", "CLASS_CC",}, - - {"rr", "CLASS_REG_WORD+(ARG_RR)",}, - {"ra", "CLASS_REG_WORD+(ARG_RA)",}, - {"rs", "CLASS_REG_WORD+(ARG_RS)",}, - - {"1", "CLASS_IMM+(ARG_IMM_1)",}, - {"2", "CLASS_IMM+(ARG_IMM_2)",}, - - 0, 0 -}; - -struct tok_struct toks[] = -{ - "0000", "CLASS_BIT+0", 1, - "0001", "CLASS_BIT+1", 1, - "0010", "CLASS_BIT+2", 1, - "0011", "CLASS_BIT+3", 1, - "0100", "CLASS_BIT+4", 1, - "0101", "CLASS_BIT+5", 1, - "0110", "CLASS_BIT+6", 1, - "0111", "CLASS_BIT+7", 1, - "1000", "CLASS_BIT+8", 1, - "1001", "CLASS_BIT+9", 1, - "1010", "CLASS_BIT+0xa", 1, - "1011", "CLASS_BIT+0xb", 1, - "1100", "CLASS_BIT+0xc", 1, - "1101", "CLASS_BIT+0xd", 1, - "1110", "CLASS_BIT+0xe", 1, - "1111", "CLASS_BIT+0xf", 1, - - "00I0", "CLASS_BIT_1OR2+0", 1, - "00I0", "CLASS_BIT_1OR2+1", 1, - "00I0", "CLASS_BIT_1OR2+2", 1, - "00I0", "CLASS_BIT_1OR2+3", 1, - "01I0", "CLASS_BIT_1OR2+4", 1, - "01I0", "CLASS_BIT_1OR2+5", 1, - "01I0", "CLASS_BIT_1OR2+6", 1, - "01I0", "CLASS_BIT_1OR2+7", 1, - "10I0", "CLASS_BIT_1OR2+8", 1, - "10I0", "CLASS_BIT_1OR2+9", 1, - "10I0", "CLASS_BIT_1OR2+0xa", 1, - "10I0", "CLASS_BIT_1OR2+0xb", 1, - "11I0", "CLASS_BIT_1OR2+0xc", 1, - "11I0", "CLASS_BIT_1OR2+0xd", 1, - "11I0", "CLASS_BIT_1OR2+0xe", 1, - "11I0", "CLASS_BIT_1OR2+0xf", 1, - - "ssss", "CLASS_REG+(ARG_RS)", 1, - "dddd", "CLASS_REG+(ARG_RD)", 1, - "aaaa", "CLASS_REG+(ARG_RA)", 1, - "bbbb", "CLASS_REG+(ARG_RB)", 1, - "rrrr", "CLASS_REG+(ARG_RR)", 1, - - "ssN0", "CLASS_REGN0+(ARG_RS)", 1, - "ddN0", "CLASS_REGN0+(ARG_RD)", 1, - "aaN0", "CLASS_REGN0+(ARG_RA)", 1, - "bbN0", "CLASS_REGN0+(ARG_RB)", 1, - "rrN0", "CLASS_REGN0+(ARG_RR)", 1, - - "cccc", "CLASS_CC", 1, - "nnnn", "CLASS_IMM+(ARG_IMMN)", 1, - "xxxx", "CLASS_REG+(ARG_RX)", 1, - "xxN0", "CLASS_REGN0+(ARG_RX)", 1, - "nminus1", "CLASS_IMM+(ARG_IMMNMINUS1)", 1, - - "disp16", "CLASS_DISP+(ARG_DISP16)", 4, - "disp12", "CLASS_DISP+(ARG_DISP12)", 3, - "flags", "CLASS_FLAGS", 1, - "address_dst", "CLASS_ADDRESS+(ARG_DST)", 4, - "address_src", "CLASS_ADDRESS+(ARG_SRC)", 4, - "imm4m1", "CLASS_IMM+(ARG_IMM4M1)", 1, - "imm4", "CLASS_IMM+(ARG_IMM4)", 1, - - "imm8", "CLASS_IMM+(ARG_IMM8)", 2, - "imm16", "CLASS_IMM+(ARG_IMM16)", 4, - "imm32", "CLASS_IMM+(ARG_IMM32)", 8, - "nim8", "CLASS_IMM+(ARG_NIM8)", 2, - "0ccc", "CLASS_0CCC", 1, - "1ccc", "CLASS_1CCC", 1, - "disp8", "CLASS_DISP8", 2, - "0disp7", "CLASS_0DISP7", 2, - "1disp7", "CLASS_1DISP7", 2, - "01ii", "CLASS_01II", 1, - "00ii", "CLASS_00II", 1, - 0, 0 -}; - -char * -translate (table, x, length) - struct tok_struct *table; - char *x; - int *length; -{ - - int found; - - found = 0; - while (table->match) - { - int l = strlen (table->match); - - if (strncmp (table->match, x, l) == 0) - { - /* Got a hit */ - printf ("%s", table->token); - *length += table->length; - return x + l; - } - - table++; - } - fprintf (stderr, "Can't find %s\n", x); - printf ("**** Can't find %s\n", x); - while (*x) - x++; - return x; -} - -void -chewbits (bits, length) - char *bits; - int *length; -{ - int n = 0; - - *length = 0; - printf ("{"); - while (*bits) - { - while (*bits == ' ') - { - bits++; - } - bits = translate (toks, bits, length); - n++; - printf (","); - - } - while (n < BYTE_INFO_LEN - 1) - { - printf ("0,"); - n++; - } - printf ("}"); -} - - -static -int -chewname (name) - char *name; -{ - char *n; - int nargs = 0; - - n = name; - printf ("\""); - while (*n && !iswhite (*n)) - { - printf ("%c", *n); - n++; - } - printf ("\","); /* Scan the operands and make entires for - them -remember indirect things */ - - n = name; - printf ("OPC_"); - while (*n && !iswhite (*n)) - { - printf ("%c", *n); - n++; - } - printf (",0,{"); - - while (*n) - { - int d; - - while (*n == ',' || iswhite (*n)) - n++; - nargs++; - n = translate (args, n, &d); - printf (","); - } - if (nargs == 0) - { - printf ("0"); - } - printf ("},"); - return nargs; -} - -static -void -sub (x, c) - char *x; - char c; -{ - while (*x) - { - if (x[0] == c && x[1] == c && - x[2] == c && x[3] == c) - { - x[2] = 'N'; - x[3] = '0'; - } - x++; - } -} - - -#if 0 -#define D(x) ((x) == '1' || (x) =='0') -#define M(y) (strncmp(y,x,4)==0) -printmangled (x) - char *x; -{ - return; - while (*x) - { - if (D (x[0]) && D (x[1]) && D (x[2]) && D (x[3])) - { - printf ("XXXX"); - } - else if (M ("ssss")) - { - printf ("ssss"); - } - else if (M ("dddd")) - { - printf ("dddd"); - } - else - printf ("____"); - - x += 4; - - if (x[0] == ' ') - { - printf ("_"); - x++; - } - } - -} - -#endif -/*#define WORK_TYPE*/ -void -print_type (n) - struct op *n; -{ -#ifdef WORK_TYPE - while (*s && !iswhite (*s)) - { - l = *s; - s++; - } - switch (l) - { - case 'l': - printf ("32,"); - break; - case 'b': - printf ("8,"); - break; - default: - printf ("16,"); - break; - } -#else - printf ("%2d,", n->type); -#endif -} - - -void -internal () -{ - int c = count (); - struct op *new = (struct op *) xmalloc (sizeof (struct op) * c); - struct op *p = opt; - memcpy (new, p, c * sizeof (struct op)); - - /* sort all names in table alphabetically */ - qsort (new, c, sizeof (struct op), func); - - p = new; - while (p->flags[0] != '*') - { - /* If there are any @rs, sub the ssss into a ssn0, - (rs), (ssn0) - */ - int loop = 1; - - printf ("\"%s\",%2d, ", p->flags, p->cycles); - while (loop) - { - char *s = p->name; - - loop = 0; - while (*s) - { - if (s[0] == '@') - { - char c; - - /* skip the r and sub the string */ - s++; - c = s[1]; - sub (p->bits, c); - } - if (s[0] == '(' && s[3] == ')') - { - sub (p->bits, s[2]); - } - if (s[0] == '(') - { - sub (p->bits, s[-1]); - } - - s++; - } - - } - print_type (p); - printf ("\"%s\",\"%s\",0,\n", p->bits, p->name); - p++; - } -} - -static -void -gas () -{ - int c = count (); - struct op *p = opt; - int idx = 0; - char *oldname = ""; - struct op *new = (struct op *) xmalloc (sizeof (struct op) * c); - - memcpy (new, p, c * sizeof (struct op)); - - /* sort all names in table alphabetically */ - qsort (new, c, sizeof (struct op), func); - - printf (" /* THIS FILE IS AUTOMAGICALLY GENERATED, DON'T EDIT IT */\n"); - - printf ("#define ARG_MASK 0x0f\n"); - - printf ("#define ARG_SRC 0x01\n"); - printf ("#define ARG_DST 0x02\n"); - - printf ("#define ARG_RS 0x01\n"); - printf ("#define ARG_RD 0x02\n"); - printf ("#define ARG_RA 0x03\n"); - printf ("#define ARG_RB 0x04\n"); - printf ("#define ARG_RR 0x05\n"); - printf ("#define ARG_RX 0x06\n"); - printf ("#define ARG_IMM4 0x01\n"); - printf ("#define ARG_IMM8 0x02\n"); - printf ("#define ARG_IMM16 0x03\n"); - printf ("#define ARG_IMM32 0x04\n"); - printf ("#define ARG_IMMN 0x05\n"); - printf ("#define ARG_IMMNMINUS1 0x05\n"); - printf ("#define ARG_IMM_1 0x06\n"); - printf ("#define ARG_IMM_2 0x07\n"); - printf ("#define ARG_DISP16 0x08\n"); - printf ("#define ARG_NIM8 0x09\n"); - printf ("#define ARG_IMM2 0x0a\n"); - printf ("#define ARG_IMM1OR2 0x0b\n"); - - printf ("#define ARG_DISP12 0x0b\n"); - printf ("#define ARG_DISP8 0x0c\n"); - printf ("#define ARG_IMM4M1 0x0d\n"); - printf ("#define CLASS_MASK 0x1fff0\n"); - printf ("#define CLASS_X 0x10\n"); - printf ("#define CLASS_BA 0x20\n"); - printf ("#define CLASS_DA 0x30\n"); - printf ("#define CLASS_BX 0x40\n"); - printf ("#define CLASS_DISP 0x50\n"); - printf ("#define CLASS_IMM 0x60\n"); - printf ("#define CLASS_CC 0x70\n"); - printf ("#define CLASS_CTRL 0x80\n"); - printf ("#define CLASS_ADDRESS 0xd0\n"); - printf ("#define CLASS_0CCC 0xe0\n"); - printf ("#define CLASS_1CCC 0xf0\n"); - printf ("#define CLASS_0DISP7 0x100\n"); - printf ("#define CLASS_1DISP7 0x200\n"); - printf ("#define CLASS_01II 0x300\n"); - printf ("#define CLASS_00II 0x400\n"); - printf ("#define CLASS_BIT 0x500\n"); - printf ("#define CLASS_FLAGS 0x600\n"); - printf ("#define CLASS_IR 0x700\n"); - printf ("#define CLASS_DISP8 0x800\n"); - - printf ("#define CLASS_BIT_1OR2 0x900\n"); - printf ("#define CLASS_REG 0x7000\n"); - printf ("#define CLASS_REG_BYTE 0x2000\n"); - printf ("#define CLASS_REG_WORD 0x3000\n"); - printf ("#define CLASS_REG_QUAD 0x4000\n"); - printf ("#define CLASS_REG_LONG 0x5000\n"); - printf ("#define CLASS_REGN0 0x8000\n"); - printf ("#define CLASS_PR 0x10000\n"); - - printf ("#define OPC_adc 0\n"); - printf ("#define OPC_adcb 1\n"); - printf ("#define OPC_add 2\n"); - printf ("#define OPC_addb 3\n"); - printf ("#define OPC_addl 4\n"); - printf ("#define OPC_and 5\n"); - printf ("#define OPC_andb 6\n"); - printf ("#define OPC_bit 7\n"); - printf ("#define OPC_bitb 8\n"); - printf ("#define OPC_call 9\n"); - printf ("#define OPC_calr 10\n"); - printf ("#define OPC_clr 11\n"); - printf ("#define OPC_clrb 12\n"); - printf ("#define OPC_com 13\n"); - printf ("#define OPC_comb 14\n"); - printf ("#define OPC_comflg 15\n"); - printf ("#define OPC_cp 16\n"); - printf ("#define OPC_cpb 17\n"); - printf ("#define OPC_cpd 18\n"); - printf ("#define OPC_cpdb 19\n"); - printf ("#define OPC_cpdr 20\n"); - printf ("#define OPC_cpdrb 21\n"); - printf ("#define OPC_cpi 22\n"); - printf ("#define OPC_cpib 23\n"); - printf ("#define OPC_cpir 24\n"); - printf ("#define OPC_cpirb 25\n"); - printf ("#define OPC_cpl 26\n"); - printf ("#define OPC_cpsd 27\n"); - printf ("#define OPC_cpsdb 28\n"); - printf ("#define OPC_cpsdr 29\n"); - printf ("#define OPC_cpsdrb 30\n"); - printf ("#define OPC_cpsi 31\n"); - printf ("#define OPC_cpsib 32\n"); - printf ("#define OPC_cpsir 33\n"); - printf ("#define OPC_cpsirb 34\n"); - printf ("#define OPC_dab 35\n"); - printf ("#define OPC_dbjnz 36\n"); - printf ("#define OPC_dec 37\n"); - printf ("#define OPC_decb 38\n"); - printf ("#define OPC_di 39\n"); - printf ("#define OPC_div 40\n"); - printf ("#define OPC_divl 41\n"); - printf ("#define OPC_djnz 42\n"); - printf ("#define OPC_ei 43\n"); - printf ("#define OPC_ex 44\n"); - printf ("#define OPC_exb 45\n"); - printf ("#define OPC_exts 46\n"); - printf ("#define OPC_extsb 47\n"); - printf ("#define OPC_extsl 48\n"); - printf ("#define OPC_halt 49\n"); - printf ("#define OPC_in 50\n"); - printf ("#define OPC_inb 51\n"); - printf ("#define OPC_inc 52\n"); - printf ("#define OPC_incb 53\n"); - printf ("#define OPC_ind 54\n"); - printf ("#define OPC_indb 55\n"); - printf ("#define OPC_inib 56\n"); - printf ("#define OPC_inibr 57\n"); - printf ("#define OPC_iret 58\n"); - printf ("#define OPC_jp 59\n"); - printf ("#define OPC_jr 60\n"); - printf ("#define OPC_ld 61\n"); - printf ("#define OPC_lda 62\n"); - printf ("#define OPC_ldar 63\n"); - printf ("#define OPC_ldb 64\n"); - printf ("#define OPC_ldctl 65\n"); - printf ("#define OPC_ldir 66\n"); - printf ("#define OPC_ldirb 67\n"); - printf ("#define OPC_ldk 68\n"); - printf ("#define OPC_ldl 69\n"); - printf ("#define OPC_ldm 70\n"); - printf ("#define OPC_ldps 71\n"); - printf ("#define OPC_ldr 72\n"); - printf ("#define OPC_ldrb 73\n"); - printf ("#define OPC_ldrl 74\n"); - printf ("#define OPC_mbit 75\n"); - printf ("#define OPC_mreq 76\n"); - printf ("#define OPC_mres 77\n"); - printf ("#define OPC_mset 78\n"); - printf ("#define OPC_mult 79\n"); - printf ("#define OPC_multl 80\n"); - printf ("#define OPC_neg 81\n"); - printf ("#define OPC_negb 82\n"); - printf ("#define OPC_nop 83\n"); - printf ("#define OPC_or 84\n"); - printf ("#define OPC_orb 85\n"); - printf ("#define OPC_out 86\n"); - printf ("#define OPC_outb 87\n"); - printf ("#define OPC_outd 88\n"); - printf ("#define OPC_outdb 89\n"); - printf ("#define OPC_outib 90\n"); - printf ("#define OPC_outibr 91\n"); - printf ("#define OPC_pop 92\n"); - printf ("#define OPC_popl 93\n"); - printf ("#define OPC_push 94\n"); - printf ("#define OPC_pushl 95\n"); - printf ("#define OPC_res 96\n"); - printf ("#define OPC_resb 97\n"); - printf ("#define OPC_resflg 98\n"); - printf ("#define OPC_ret 99\n"); - printf ("#define OPC_rl 100\n"); - printf ("#define OPC_rlb 101\n"); - printf ("#define OPC_rlc 102\n"); - printf ("#define OPC_rlcb 103\n"); - printf ("#define OPC_rldb 104\n"); - printf ("#define OPC_rr 105\n"); - printf ("#define OPC_rrb 106\n"); - printf ("#define OPC_rrc 107\n"); - printf ("#define OPC_rrcb 108\n"); - printf ("#define OPC_rrdb 109\n"); - printf ("#define OPC_sbc 110\n"); - printf ("#define OPC_sbcb 111\n"); - printf ("#define OPC_sda 112\n"); - printf ("#define OPC_sdab 113\n"); - printf ("#define OPC_sdal 114\n"); - printf ("#define OPC_sdl 115\n"); - printf ("#define OPC_sdlb 116\n"); - printf ("#define OPC_sdll 117\n"); - printf ("#define OPC_set 118\n"); - printf ("#define OPC_setb 119\n"); - printf ("#define OPC_setflg 120\n"); - printf ("#define OPC_sinb 121\n"); - printf ("#define OPC_sind 122\n"); - printf ("#define OPC_sindb 123\n"); - printf ("#define OPC_sinib 124\n"); - printf ("#define OPC_sinibr 125\n"); - printf ("#define OPC_sla 126\n"); - printf ("#define OPC_slab 127\n"); - printf ("#define OPC_slal 128\n"); - printf ("#define OPC_sll 129\n"); - printf ("#define OPC_sllb 130\n"); - printf ("#define OPC_slll 131\n"); - printf ("#define OPC_sout 132\n"); - printf ("#define OPC_soutb 133\n"); - printf ("#define OPC_soutd 134\n"); - printf ("#define OPC_soutdb 135\n"); - printf ("#define OPC_soutib 136\n"); - printf ("#define OPC_soutibr 137\n"); - printf ("#define OPC_sra 138\n"); - printf ("#define OPC_srab 139\n"); - printf ("#define OPC_sral 140\n"); - printf ("#define OPC_srl 141\n"); - printf ("#define OPC_srlb 142\n"); - printf ("#define OPC_srll 143\n"); - printf ("#define OPC_sub 144\n"); - printf ("#define OPC_subb 145\n"); - printf ("#define OPC_subl 146\n"); - printf ("#define OPC_tcc 147\n"); - printf ("#define OPC_tccb 148\n"); - printf ("#define OPC_test 149\n"); - printf ("#define OPC_testb 150\n"); - printf ("#define OPC_testl 151\n"); - printf ("#define OPC_trdb 152\n"); - printf ("#define OPC_trdrb 153\n"); - printf ("#define OPC_trib 154\n"); - printf ("#define OPC_trirb 155\n"); - printf ("#define OPC_trtdrb 156\n"); - printf ("#define OPC_trtib 157\n"); - printf ("#define OPC_trtirb 158\n"); - printf ("#define OPC_trtrb 159\n"); - printf ("#define OPC_tset 160\n"); - printf ("#define OPC_tsetb 161\n"); - printf ("#define OPC_xor 162\n"); - printf ("#define OPC_xorb 163\n"); - - printf ("#define OPC_ldd 164 \n"); - printf ("#define OPC_lddb 165 \n"); - printf ("#define OPC_lddr 166 \n"); - printf ("#define OPC_lddrb 167 \n"); - printf ("#define OPC_ldi 168 \n"); - printf ("#define OPC_ldib 169 \n"); - printf ("#define OPC_sc 170\n"); - printf ("#define OPC_bpt 171\n"); - printf ("#define OPC_ext0e 172\n"); - printf ("#define OPC_ext0f 172\n"); - printf ("#define OPC_ext8e 172\n"); - printf ("#define OPC_ext8f 172\n"); - printf ("#define OPC_rsvd36 172\n"); - printf ("#define OPC_rsvd38 172\n"); - printf ("#define OPC_rsvd78 172\n"); - printf ("#define OPC_rsvd7e 172\n"); - printf ("#define OPC_rsvd9d 172\n"); - printf ("#define OPC_rsvd9f 172\n"); - printf ("#define OPC_rsvdb9 172\n"); - printf ("#define OPC_rsvdbf 172\n"); - printf ("#define OPC_outi 173\n"); - printf ("#define OPC_ldctlb 174\n"); - printf ("#define OPC_sin 175\n"); - printf ("#define OPC_trtdb 176\n"); -#if 0 - for (i = 0; toks[i].token; i++) - printf ("#define %s\t0x%x\n", toks[i].token, i * 16); -#endif - printf ("typedef struct {\n"); - - printf ("#ifdef NICENAMES\n"); - printf ("char *nicename;\n"); - printf ("int type;\n"); - printf ("int cycles;\n"); - printf ("int flags;\n"); - printf ("#endif\n"); - printf ("char *name;\n"); - printf ("unsigned char opcode;\n"); - printf ("void (*func) PARAMS ((void));\n"); - printf ("unsigned int arg_info[4];\n"); - printf ("unsigned int byte_info[%d];\n", BYTE_INFO_LEN); - printf ("int noperands;\n"); - printf ("int length;\n"); - printf ("int idx;\n"); - printf ("} opcode_entry_type;\n"); - printf ("#ifdef DEFINE_TABLE\n"); - printf ("opcode_entry_type z8k_table[] = {\n"); - - while (new->flags && new->flags[0]) - { - int nargs; - int length; - - printf ("\n\n/* %s *** %s */\n", new->bits, new->name); - printf ("{\n"); - - printf ("#ifdef NICENAMES\n"); - printf ("\"%s\",%d,%d,\n", new->name, new->type, new->cycles); - { - int answer = 0; - char *p = new->flags; - - while (*p) - { - answer <<= 1; - - if (*p != '-') - answer |= 1; - p++; - } - printf ("0x%02x,\n", answer); - } - - printf ("#endif\n"); - - nargs = chewname (new->name); - - printf ("\n\t"); - chewbits (new->bits, &length); - length /= 2; - if (length & 1) - abort(); - - printf (",%d,%d,%d", nargs, length, idx); - idx++; - oldname = new->name; - printf ("},\n"); - new++; - } - printf ("\n/* end marker */\n"); - printf ("{\n#ifdef NICENAMES\nNULL,0,0,\n0,\n#endif\n"); - printf ("NULL,0,0,{0,0,0,0},{0,0,0,0,0,0,0,0,0,0},0,0,0}\n};\n"); - printf ("#endif\n"); -} - - -int -main (ac, av) - int ac; - char **av; -{ - struct op *p = opt; - - if (ac == 2 && strcmp (av[1], "-t") == 0) - { - internal (); - } - else if (ac == 2 && strcmp (av[1], "-h") == 0) - { - while (p->name) - { - printf ("%-25s\t%s\n", p->name, p->bits); - p++; - } - } - - else if (ac == 2 && strcmp (av[1], "-a") == 0) - { - gas (); - } - else if (ac == 2 && strcmp (av[1], "-d") == 0) - { - /*dis();*/ - } - else - { - printf ("Usage: %s -t\n", av[0]); - printf ("-t : generate new z8.c internal table\n"); - printf ("-a : generate new table for gas\n"); - printf ("-d : generate new table for disassemble\n"); - printf ("-h : generate new table for humans\n"); - } - return 0; -} |
