diff options
| author | obrien <obrien@FreeBSD.org> | 2002-01-27 12:00:11 +0000 |
|---|---|---|
| committer | obrien <obrien@FreeBSD.org> | 2002-01-27 12:00:11 +0000 |
| commit | fc89183cdc6be5afa8deb7250fd15a20832ab528 (patch) | |
| tree | 5c493199a70976c54e1b9c6a7804a3de85b43e84 /contrib/binutils/opcodes | |
| parent | 94820fd8060f6f43089d1a3ddb8a482402e7e494 (diff) | |
| download | FreeBSD-src-fc89183cdc6be5afa8deb7250fd15a20832ab528.zip FreeBSD-src-fc89183cdc6be5afa8deb7250fd15a20832ab528.tar.gz | |
Enlist the FreeBSD-CURRENT users as testers of what is to become Binutils
version 2.12.0. These bits are taken from the FSF anoncvs repo on
27-January-2002 03:41 PST.
Diffstat (limited to 'contrib/binutils/opcodes')
33 files changed, 4518 insertions, 1854 deletions
diff --git a/contrib/binutils/opcodes/ChangeLog b/contrib/binutils/opcodes/ChangeLog index ad0dc07..f4489d4 100644 --- a/contrib/binutils/opcodes/ChangeLog +++ b/contrib/binutils/opcodes/ChangeLog @@ -1,6 +1,395 @@ -2001-10-24 Richard Henderson <rth@redhat.com> +2002-01-26 Nick Clifton <nickc@cambridge.redhat.com> - * ia64-asmtab.c: Regenerate. + * po/fr.po: Updated version. + +2002-01-25 Nick Clifton <nickc@cambridge.redhat.com> + + * po/es.po: Updated version. + +2002-01-24 Nick Clifton <nickc@cambridge.redhat.com> + + * po/da.po: New version. + +2002-01-23 Nick Clifton <nickc@cambridge.redhat.com> + + * po/da.po: New file: Spanish translation. + * configure.in (ALL_LINGUAS): Add da. + * configure: Regenerate. + +2002-01-22 Graydon Hoare <graydon@redhat.com> + + * fr30-asm.c: Regenerate. + * fr30-desc.c: Likewise. + * fr30-desc.h: Likewise. + * fr30-dis.c: Likewise. + * fr30-ibld.c: Likewise. + * fr30-opc.c: Likewise. + * fr30-opc.h: Likewise. + * m32r-asm.c: Likewise. + * m32r-desc.c: Likewise. + * m32r-desc.h: Likewise. + * m32r-dis.c: Likewise. + * m32r-ibld.c: Likewise. + * m32r-opc.c: Likewise. + * m32r-opc.h: Likewise. + * m32r-opinst.c: Likewise. + * openrisc-asm.c: Likewise. + * openrisc-desc.c: Likewise. + * openrisc-desc.h: Likewise. + * openrisc-dis.c: Likewise. + * openrisc-ibld.c: Likewise. + * openrisc-opc.c: Likewise. + * openrisc-opc.h: Likewise. + * xstormy16-desc.c: Likewise. + +2002-01-22 Richard Henderson <rth@redhat.com> + + * alpha-dis.c (print_insn_alpha): Also mask the base opcode for + comparison. + +2002-01-22 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * opcodes/po/POTFILES.in: Regenerate. + +2002-01-19 Richard Earnshaw <rearnsha@arm.com> + + * arm-opc.h (arm_opcodes): Use generic rule %5?hb instead of %h. + * arm-dis.c (print_insn_arm): Don't handle 'h' case. + +2002-01-18 Keith Walker <keith.walker@arm.com> + + * arm-opc.h (arm_opcodes): Add bxj instruction. + +2002-01-17 Nick Clifton <nickc@cambridge.redhat.com> + + * po/opcodes.pot: Regenerate. + * po/fr.po: Regenerate. + * po/sv.po: Regenerate. + * po/tr.po: Regenerate. + +2002-01-16 Nick Clifton <nickc@cambridge.redhat.com> + + * po/tr.po: Import new version. + +2002-01-15 Richard Earnshaw <rearnsha@arm.com> + + * arm-opc.h (arm_opcodes): Add patterns for VFP instructions. + * arm-dis.c (print_insn_arm): Support new disassembly qualifiers for + VFP bitfields. + +2002-01-10 matthew green <mrg@redhat.com> + + * xstormy16-asm.c: Regenerate. + * xstormy16-desc.c: Likewise. + * xstormy16-desc.h: Likewise. + * xstormy16-dis.c: Likewise. + * xstormy16-opc.c: Likewise. + * xstormy16-opc.h: Likewise. + +2002-01-07 Nick Clifton <nickc@cambridge.redhat.com> + + * po/es.po: New file: Spanish translation. + * configure.in (ALL_LINGUAS): Add es. + * configure: Regenerate. + +2001-12-31 Jeffrey A Law (law@redhat.com) + + * hppa-dis.c (print_insn_hppa): Handle new 'c' mode completers, + 'X', 'M', and 'A'. No longer emit a space after 'x' or 's'. + Always emit a space after 'H'. + +2001-12-18 matthew green <mrg@redhat.com> + + * ppc-opc.c (PPCVEC): Include PPC_OPCODE_ANY. + +2001-12-17 Richard Henderson <rth@redhat.com> + + * alpha-opc.c (unop): Encode with RB as $sp. + +2001-12-07 Geoffrey Keating <geoffk@redhat.com> + + * Makefile.am: Add support for xstormy16. + * Makefile.in: Regenerate. + * configure.in: Add support for xstormy16. + * configure: Regenerate. + * disassemble.c: Add support for xstormy16. + * xstormy16-asm.c: New generated file. + * xstormy16-desc.c: New generated file. + * xstormy16-desc.h: New generated file. + * xstormy16-dis.c: New generated file. + * xstormy16-ibld.c: New generated file. + * xstormy16-opc.c: New generated file. + * xstormy16-opc.h: New generated file. + +2001-12-06 Richard Henderson <rth@redhat.com> + + * alpha-opc.c (alpha_opcodes): Add wh64en. + +2001-12-04 Alexandre Oliva <aoliva@redhat.com> + + * d10v-opc.c (d10v_predefined_registers): Remove warnings + introduced in Nov 29's patch. + + * d10v-dis.c (print_operand): Apply REGISTER_MASK to `num' of + unmatched register. + + * d10v-dis.c (print_operand): Disregard OPERAND_SP in register + predefined value. + + * d10v-opc.c (RSRC_NOSP): New macro. + (d10v_operands): Add it. + (d10v_opcodes): Use RSRC_NOSP in post-decrement "st" and "st2w". + +2001-11-29 Alexandre Oliva <aoliva@redhat.com> + + * d10v-opc.c (d10v_predefined_registers): Mark `sp' as OPERAND_SP. + (RSRC_SP): New macro. + (d10v_operands): Add it. + (d10v_opcodes): Adjust "st" and "st2w" to use RSRC_SP. + +2001-11-23 Lars Brinkhoff <lars@nocrew.org> + + * pdp11-dis.c (print_insn_pdp11): Handle illegal instructions. + Also, break out of the loop as soon as an instruction has been + printed. + +2001-11-17 matthew green <mrg@redhat.com> + + * ppc-opc.c (mfvrsave, mtvrsave): New instructions. + +2001-11-15 Alan Modra <amodra@bigpond.net.au> + + * po/POTFILES.in: Regenerate. + + * ppc-opc.c (PPC64): Revert 2001-10-12. Do include PPC_OPCODE_PPC. + (insert_bat, extract_bat, insert_bba, extract_bba, + insert_bd, extract_bd, insert_bdm, extract_bdm, + insert_bdp, extract_bdp, valid_bo, + insert_bo, extract_bo, insert_boe, extract_boe, + insert_ds, extract_ds, insert_de, extract_de, + insert_des, extract_des, insert_li, extract_li, + insert_mbe, extract_mbe, insert_mb6, extract_mb6, + insert_nb, extract_nb, insert_nsi, extract_nsi, + insert_ral, insert_ram, insert_ras, + insert_rbs, extract_rbs, insert_sh6, extract_sh6, + insert_spr, extract_spr, insert_tbr, extract_tbr): Add dialect param. + (extract_bd, extract_bdm, extract_bdp, + extract_ds, extract_des, + extract_li, extract_nsi): Implement sign extension without conditional. + (insert_bdm, extract_bdm, + insert_bdp, extract_bdp, valid_bo): Handle 64 bit branch hints. + (extract_bdm, extract_bdp): Correct 32 bit validation. + (AT1_MASK, AT2_MASK): Define. + (BBOAT_MASK): Define. + (BBOATCB_MASK, BBOAT2CB_MASK, BBOATBI_MASK): Define. + (BOFM64, BOFP64, BOTM64, BOTP64): Define. + (BODNZM64, BODNZP64, BODZM64, BODZP64): Define. + (PPCCOM32, PPCCOM64): Define. + (powerpc_opcodes): Modify existing 32 bit insns with branch hints + and add new patterns to implement 64 bit branches with hints. Move + booke instructions so they match before ppc64. + + * ppc-dis.c (powerpc_dialect): Set PPC_OPCODE_64 in dialect for + 64 bit default targets, and parse "32" and "64" in options. + Formatting fixes. + (print_insn_powerpc): Pass dialect to operand->extract. + +2001-11-14 Dave Brolley <brolley@redhat.com> + + * cgen-dis.c (count_decodable_bits): New function. + (add_insn_to_hash_chain): New function. + (hash_insn_array): Call add_insn_to_hash_chain. + (hash_insn_list): Call add_insn_to_hash_chain. + * m32r-dis.c: Regenerated. + * fr30-dis.c: Regenerated. + +2001-11-14 Andreas Jaeger <aj@suse.de> + + * i386-dis.c (print_insn): Use x86-64 as option. + +2001-11-14 Alan Modra <amodra@bigpond.net.au> + + * disassemble.c (disassembler): Call print_insn_i386. + * i386-dis.c (SUFFIX_ALWAYS): Define. + (struct dis_private): Add orig_sizeflag. + (print_insn_i386): Make it a wrapper, calling.. + (print_insn): ..The old body of print_insn_i386. Avoid longjmp + warning without using volatile by moving orig_sizeflag to priv, + and removing inbuf. Parse disassembler_options. + (print_insn_i386_att, print_insn_i386_intel): Move initialisation + code to print_insn. + (putop): Remove #ifdef SUFFIX_ALWAYS. + +2001-11-11 Timothy Wall <twall@alum.mit.edu> + + * tic54x-dis.c: Use revised opcode structure. Export opcode + template lookup. + (has_lkaddr): Don't forget about Lmem insns. + * tic54x-opc.c: Add emulation trap. Parallel table now uses + standard opcode templates. + +2001-11-13 Zack Weinberg <zack@codesourcery.com> + + * i386-dis.c (grps): Change "sldt", "str", and "smsw" entries + to "sldtQ", "strQ", "smswQ" respectively; all with Ev operand + category instead of Ew. + +2001-11-12 Niraj Gupta <ngupta@zumanetworks.com> + + * m68k-opc.c: Fix definitions of wddata[bwl]. + +2001-11-09 Richard Sandiford <rsandifo@redhat.com> + + * cgen-asm.c (cgen_parse_keyword): If the keyword is too big to + fit in the buffer, try to match the empty keyword. + +2001-11-09 Nick Clifton <nickc@cambridge.redhat.com> + + * cgen-ibld.in (extract_1): Fix badly placed #if 0. + * fr30-ibld.c: Regenerate. + * m32r-ibld.c: Regenerate. + * openrisc-ibld.c: Regenerate. + +2001-11-04 Chris Demetriou <cgd@broadcom.com> + + * mips-dis.c (print_insn_mips): Remove spaces at end of line. + +2001-11-02 Nick Clifton <nickc@cambridge.redhat.com> + + * configure.in (ALL_LINGUAS): Add "fr", "sv" and "tr". + * configure: Regernate. + * po/fr.po: New file. + * po/sv.po: New file. + * po/tr.po: New file. + +2001-11-01 Stephane Carrez <Stephane.Carrez@worldnet.fr> + + * m68hc11-dis.c (print_insn): Fix disassembly of movb with a + constant as source. + +2001-10-30 Hans-Peter Nilsson <hp@bitrange.com> + + * Makefile.am (CFILES): Add mmix-dis.c and mmix-opc.c. Regenerate + dependencies. + * Makefile.in: Regenerate. + * mmix-dis.c, mmix-opc.c: New files. + +2001-10-29 Kazu Hirata <kazu@hxi.com> + + * d30v-dis.c: Fix a comment typo. + +2001-10-23 Chris Demetriou <cgd@broadcom.com> + + * mips-opc.c (mips_builtin_opcodes): Mark "bgezall" and + "bltzall" as writing GPR 31 (since they do). + + * mips-dis.c (print_insn_arg): Calculate info->target + where appropriate. + (print_insn_mips): Fill in instruction info. + (print_mips16_insn_arg): Remove unneded variable 'val'. + Removed duplicated instruction target calculations, + calculate once and print that result. Use same idiom for + masking the jump segment bits as is used in print_insn_arg. + +2001-10-20 Alan Modra <amodra@bigpond.net.au> + + * ppc-opc.c (CT): Make it an optional operand. + +2001-10-17 Chris Demetriou <cgd@broadcom.com> + + * mips-dis.c (mips_isa_type): Make the ISA used to disassemble + SB-1 binaries include instructions specific to the SB-1. + * mips-opc.c (SB1): New definition. + (mips_builtin_opcodes): Add SB-1 extension opcodes "div.ps", + "recip.ps", "rsqrt.ps", and "sqrt.ps". + +2001-10-17 matthew green <mrg@redhat.com> + + * ppc-opc.c (STRM): New AltiVec operand. + (XDSS): New AltiVec instruction form. + (mtvscr): Correct operand list. + (dst, dstt, dstst, dststt, dss, dssall): AltiVec instructions. + +2001-10-17 Alan Modra <amodra@bigpond.net.au> + + * po/POTFILES.in: Regenerate. + +2001-10-13 matthew green <mrg@redhat.com> + + * ppc-opc.c (MO): New macro for MO field of mbar instruction. + (powerpc_opcodes): Add rfci, wrtee, wrteei, mfdcrx, mfdcr, + mtdcrx, mtdcr, msync, dcba and mbar as BookE instructions. + +2001-10-13 Nick Clifton <nickc@cambridge.redhat.com> + + * cgen-ibld.in: Include safe-ctype.h in preference to + ctype.h. + * cgen-asm.in: Include safe-ctype.h in preference to + ctype.h. Fix formatting. Use ISSPACE instead of isspace and + TOLOWER instead of tolower. + (@arch@_cgen_build_insn_regex): Remove duplication of syntax + string elements in constructed regular expression. + * fr30-asm.c: Regenerate. + * fr30-desc.c: Regenerate. + * fr30-ibld.c: Regenerate. + * m32r-asm.c: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-ibld.c: Regenerate. + * openrisc-asm.c: Regenerate. + * openrisc-desc.c: Regenerate. + * openrisc-ibld.c: Regenerate. + * po/opcodes.pot: Regenerate. + +2001-10-12 matthew green <mrg@redhat.com> + + * ppc-opc.c (insert_de, extract_de, insert_des, extract_des): New + instruction field instruction/extraction functions for new BookE + DE form instructions. + (CT): New macro for CT field in an X form instruction. + (DE, DES, DEO, DE_MASK): New macros for DE/DES fields in DE form + instructions. + (PPC64): Don't include PPC_OPCODE_PPC. + (403): New opcode macro for PPC403 processors. + (BOOKE): New opcode macro for BookE processors. + (bce, bcel, bcea, bcela, bclre, bclrel: New BookE instructions. + (bcctre, bcctrel, be, bel, bea, bela, icbt, icbte, lwzxe): Likewise. + (dcbste, lwzuxe, luxe, dcbfe, lbzxe, lwarxe, lbzuxe): Likewise. + (stwcxe, stwxe, stxe, stwuxe, stuxe, stbxe, dcbtste, stbuxe): Likewise. + (mfapidi, dcbte, lhzxe, lhzuxe, lhaxe, lhauxe, subfe64): Likewise. + (subfeo64, adde64, addeo64, sthxe, sthuxe, subfze64): Likewise. + (subfzeo64, addze64, addzeo64, dcbie, subfme64, subfmeo64): Likewise. + (addme64, addmeo64, stdcxe., mcrxr64, lwbrxe, lfsxe, lfsuxe): Likewise. + (lfdxe, lfduxe, stwbrxe, stfsxe, stfsuxe, stfdxe, dcbae): Likewise. + (stfduxe, tlbivax, tlbivaxe, lhbrxe, ldxe, lduxe, tlbsx): Likewise. + (tlbsxe, sthbrxe, stdxe, stduxe, icbie, stfiwxe, dcbze, lbze): Likewise. + (lbzue, ldue, lhze, lhzue, lhae, lhaue, lwze, lwzue): Likewise. + (stbe, stbue, sthe, sthue, stwe, stwue, lfse, lfsue, lfde): Likewise. + (lfdue, stde, stdue, stfse, stfsue, stfde, stfdue): Likewise. + + * ppc-dis.c (print_insn_big_powerpc, print_insn_little_powerpc): Look + for a disassembler option of `booke', `booke32' or `booke64' to enable + BookE support in the disassembler. + +2001-10-12 John Healy <jhealy@redhat.com> + + * cgen-dis.in (print_insn): Use min (cd->base_insn_bitsize, buflen*8) + for the length when extracting the base part of the insn. + +2001-10-09 Bruno Haible <haible@clisp.cons.org> + + * cgen-asm.in (*_cgen_build_insn_regex): Generate a case sensitive + regular expression. Fix some formatting problems. + * fr30-asm.c: Regenerate. + * openrisc-asm.c: Regenerate. + * m32r-asm.c: Regenerate. + +2001-10-09 Christian Groessler <cpg@aladdin.de> + + * z8k-dis.c (unparse_instr): Fixed formatting. Change disassembly + of indirect register memory accesses to be same format the + assembler accepts. 2001-10-09 Nick Clifton <nickc@cambridge.redhat.com> @@ -8,32 +397,443 @@ DSP single data transfer instructions. * sh-dis.c (print_insn_shx): Fix decoding of As opcode in DSP - instructions. + instructions. + +2001-10-08 Nick Clifton <nickc@cambridge.redhat.com> + + * cgen-asm.in: Fix compile time warning messages in generated + C files. + * cgen-dis.in: The same. + * cgen-ibld.in: The same. + * fr30-asm.c: Regenerate. + * fr30-desc.c: Regenerate. + * fr30-dis.c: Regenerate. + * fr30-ibld.c: Regenerate. + * fr30-opc.c: Regenerate. + * m32r-asm.c: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-dis.c: Regenerate. + * m32r-ibld.c: Regenerate. + * m32r-opc.c: Regenerate. + * m32r-opinst.c Regenerate. + * openrisc-asm.c: Regenerate. + * openrisc-desc.c: Regenerate. + * openrisc-dis.c: Regenerate. + * openrisc-ibld.c: Regenerate. + * openrisc-opc.c: Regenerate. + * openrisc-opc.h: Regenerate. + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + * po/opcodes.pot: Regenerate. + +2001-10-08 Aldy Hernandez <aldyh@redhat.com> + + * arm-opc.h (arm_opcodes): Add cirrus insns. + + * arm-dis.c (print_insn_arm): Add 'I' case. + +2001-10-03 Alan Modra <amodra@bigpond.net.au> + + * po/POTFILES.in: Regenerate. + * configure: Regenerate. + +2001-10-02 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am (Makefile): Depend on bfd/configure.in. + Run "make dep-am". + * Makefile.in: Regenerate. + +2001-09-30 John Healy <jhealy@redhat.com> + + * cgen-ibld.in (insert_1): Switched bfd_get_bits and bfd_set_bits + calls to cgen_get_insn_value and cgen_put_insn_value calls. + (extract_1): Switched bfd_get_bits call to cgen_get_insn_value call. + +2001-09-30 Hans-Peter Nilsson <hp@bitrange.com> + + * Makefile.am: Update dependencies with "make dep-am". + * Makefile.in: Regenerate. + +2001-09-26 Alan Modra <amodra@bigpond.net.au> + + * arc-dis.c: Formatting fixes. + (my_sprintf): Define using VPARAMS, VA_OPEN, VA_FIXEDARG, VA_CLOSE. + +2001-09-21 Bruno Haible <haible@clisp.cons.org> + + * arc-dis.c: Don't include <ctype.h>. + * openrisc-desc.c: Likewise. + * openrisc-ibld.c: Likewise. + +2001-09-20 Nick Clifton <nickc@cambridge.redhat.com> + + * fr30-opc.c: Fix compile time warning messages. + * i370-opc.c: Fix compile time warning messages. + * i960-dis.c: Fix compile time warning messages. + * m32r-asm.c: Fix compile time warning messages. + * m32r-desc.c: Fix compile time warning messages. + * m32r-dis.c: Fix compile time warning messages. + * m32r-ibld.c: Fix compile time warning messages. + * m32r-opc.c: Fix compile time warning messages. + * m32r-opinst.c: Fix compile time warning messages. + * ns32k-dis.c: Fix compile time warning messages. + * openrisc-asm.c: Fix compile time warning messages. + * openrisc-desc.c: Fix compile time warning messages. + * openrisc-dis.c: Fix compile time warning messages. + * openrisc-ibld.c: Fix compile time warning messages. + * openrisc-opc.c: Fix compile time warning messages. + * pdp11-dis.c: Fix compile time warning messages. + * tic54x-dis.c: Fix compile time warning messages. + * v850-opc.c: Fix compile time warning messages. + * vax-dis.c: Fix compile time warning messages. + * w65-opc.h: Fix compile time warning messages. + * z8k-opc.h: Fix compile time warning messages. + * z8kgen.c: Fix compile time warning messages. + +2001-09-19 Nick Clifton <nickc@cambridge.redhat.com> + + * arm-dis.c: Fix compile time warning messages. + * cgen-asm.c: Fix compile time warning messages. + * cgen-dis.c: Fix compile time warning messages. + * cris-dis.c: Fix compile time warning messages. + * d10v-dis.c: Fix compile time warning messages. + * fr30-asm.c: Fix compile time warning messages. + * fr30-desc.c: Fix compile time warning messages. + * fr30-dis.c: Fix compile time warning messages. + * fr30-ibld.c: Fix compile time warning messages. + +2001-09-18 Bruno Haible <haible@clisp.cons.org> + + * cgen-asm.c: Include "safe-ctype.h" instead of <ctype.h>. + (cgen_parse_keyword): Use ISALNUM instead of isalnum. + * cgen-opc.c: Include "safe-ctype.h" instead of <ctype.h>. + (cgen_keyword_lookup_name): Use ISALPHA/TOLOWER instead of + isalpha/tolower. + (cgen_keyword_add): Use ISALNUM instead of isalnum. + (hash_keyword_name): Use TOLOWER instead of tolower. + * fr30-asm.c: Include "safe-ctype.h" instead of <ctype.h>. + (parse_insn_normal): Use TOLOWER/ISSPACE instead of + tolower/isspace. + (fr30_cgen_assemble_insn): Use ISSPACE instead of isspace. + * fr30-desc.c: Don't include <ctype.h>. + * fr30-ibld.c: Likewise. + * ia64-gen.c: Include "safe-ctype.h" instead of <ctype.h>. + (load_insn_classes, parse_resource_users, load_depfile): Use + ISSPACE instead of isspace. + * m32r-asm.c: Include "safe-ctype.h" instead of <ctype.h>. + (parse_insn_normal): Use TOLOWER/ISSPACE instead of + tolower/isspace. + (m32r_cgen_assemble_insn): Use ISSPACE instead of isspace. + * m32r-desc.c: Don't include <ctype.h>. + * m32r-ibld.c: Likewise. + * openrisc-asm.c: Include "safe-ctype.h" instead of <ctype.h>. + (parse_insn_normal): Use TOLOWER/ISSPACE instead of + tolower/isspace. + (openrisc_cgen_assemble_insn): Use ISSPACE instead of isspace. + +2001-09-18 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * Makefile.am: Add rules and dependencies to create the s/390 opcode + table out of s390-opc.txt automatically. + * configure.in: Add BFD_CC_FOR_BUILD to allow CC_FOR_BUILD to be used. + * s390-mkopc.c (dumpTable): Change output to create a complete file. + * s390-opc.c: New improved opcode format macros and remove the + pregenerated opcode table. + * s390-opc.txt: Adapt to new improved opcode format macros. + +2001-09-14 David Schleef <ds@schleef.org> + + * ppc-opc.c (VXA, VXA_MASK): Fix mask bits. 2001-09-04 Alan Modra <amodra@bigpond.net.au> * i386-dis.c (grps): Don't print the implicit al/ax/eax register for opcode 0xf6 or 0xf7 forms of mul, imul, div, idiv insns. - Merge from mainline. - 2001-07-28 Kazu Hirata <kazu@hxi.com> +2001-08-31 Eric Christopher <echristo@redhat.com> + Jason Eckhardt <jle@redhat.com> + + * mips-dis.c: Add support for bfd_mach_mipsisa32 and + bfd_mach_mipsisa64. Remove bfd_mach_mips32, bfd_mach_mips32_4k, + bfd_mach_mips64. + +2001-08-31 Andreas Jaeger <aj@suse.de> + + * tic54x-opc.c: Add default initializers to avoid warnings. + + * arc-opc.c: Include "sysdep.h" to get stdio.h as include file. + * arc-ext.c: Likewise. + +2001-08-28 matthew gren <mrg@redhat.com> + + * ppc-opc.c (icbt): Order correctly. + +2001-08-27 David Edelsohn <dje@watson.ibm.com> + Torbjorn Granlund <tege@swox.com> + + * ppc-opc.c (DS): Add PPC_OPERAND_DS flag. + (LS): Define. + (insert_ds): Complain if not a multiple of 4. + (XSYNC): Define. + (XSYNC_MASK): Define. + (powerpc_opcodes): Add "slbmte", "lwsync", "ptesync", "slbmfev", + "slbmfee". Modify "sync" to use XSYNC_MASK and LS. + +2001-08-26 Andreas Jaeger <aj@suse.de> + + * h8500-opc.h: Add default initializers to h8500_table to shut up + GCC warnings. + +2001-08-25 Andreas Jaeger <aj@suse.de> + + * tic54x-dis.c: Add unused attributes where needed. + + * z8k-dis.c (output_instr): Add unused attribute. + + * h8300-dis.c: Add missing prototypes. + (bfd_h8_disassemble): Make static. + + * cris-dis.c: Add missing prototype. + * h8500-dis.c: Likewise. + * m68hc11-dis.c: Likewise. + * pj-dis.c: Likewise. + * tic54x-dis.c: Likewise. + * v850-dis.c: Likewise. + * vax-dis.c: Likewise. + * w65-dis.c: Likewise. + * z8k-dis.c: Likewise. + + * d10v-dis.c: Add missing prototype. + (dis_long): Remove unused variable. + (dis_2_short): Likewise. + + * sh-dis.c: Add missing prototypes. + * v850-opc.c: Likewise. + Add unused attributes where needed. + + * ns32k-dis.c: Add missing prototypes. + (bit_extract_simple): Remove unused variable. + +2001-08-23 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * opcodes/s390-opc.c: Add "low or high" and "not low or high" + branch instructions for gcc 3.0. + * opcodes/s390-opc.txt: Likewise. + +2001-08-21 Andreas Jaeger <aj@suse.de> + + * i960-dis.c: Add parameters for prototypes + (ctrl): Add unused attributes. + (cobr): Likewise. + (put_abs): Likewise. + + * mips-dis.c: Add missing prototypes. + * a29k-dis.c: Likewise. + * arc-dis.c: Likewise. + * ia64-opc.c: Likewise. + + * s390-dis.c: Add missing prototypes. + (init_disasm): Remove unused attribute since the parameter is + used. + +2001-08-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips-opc.c (M1): Define. Reformatted Code. + (mips_builtin_opcodes): Added performance counter opcodes mfpc, mfps, + mtps, mtps. Typo. + +2001-08-16 Jonathan Larmour <jlarmour@redhat.com> + + * mips-opc.c: R3900s can support all branch likely INSN_MACROs where + the corresponding non-likely insn is in MIPS I. + +2001-08-13 Kazu Hirata <kazu@hxi.com> + + * mcore-dis.c: Fix formatting. + * mips-dis.c: Likewise. + * pj-dis.c: Likewise. + * z8k-dis.c: Likewise. + +2001-08-12 Richard Henderson <rth@redhat.com> + + * cgen-ibld.in (extract_normal): Match type of VALUE and MASK + to *VALUEP. Regenerate all cgen files. + +2001-08-10 Richard Sandiford <rsandifo@redhat.com> + + * mips-dis.c (print_insn_mips): Remove OPCODE_IS_MEMBER's gp32 + argument. + * mips-opc.c (G6): Undefine. + (mips_builtin_opcodes): Remove gp32 entry for "move". Add macro + as the first "move" alternative. + +2001-08-10 Andreas Jaeger <aj@suse.de> + + * configure.in: Add -Wstrict-prototypes and -Wmissing-prototypes + to build warnings. + * configure: Regenerate. + +2001-08-10 Alan Modra <amodra@bigpond.net.au> + + * ppc-opc.c: Revert 2001-08-08. + +2001-08-09 Alan Modra <amodra@bigpond.net.au> + + * dis-buf.c (generic_strcat_address): Add missing prototype. + #if 0 the functions as it is unused. + +2001-08-08 Alan Modra <amodra@bigpond.net.au> + + 1999-10-25 Torbjorn Granlund <tege@swox.com> + * ppc-opc.c: Include "bfd.h". + (powerpc_operands): Add new field for reloc type. + +2001-07-21 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips-dis.c (print_insn_arg): Don't use software integer registers + for coprocessor registers. + (get_mips_isa): Removed. + (is_newabi): New function, checks if NewABI is used. + (_print_insn_mips): Get distinction between old ABI and new ABI right. + +2001-08-01 Christian Groessler <cpg@aladdin.de> + + * z8kgen.c: Fixed indentation of opt[] array. Include stdio.h to + get stderr definition. + (internal, gas): Removed warnings. + (gas): Create a correct final entry for created array. + * z8k-opc.h: Recreated with new z8kgen. + +2001-07-28 Kazu Hirata <kazu@hxi.com> + * i386-dis.c: Fix formatting. - 2001-07-28 Matthias Kramm <kramm@quiss.org> +2001-07-28 Matthias Kramm <kramm@quiss.org> + * i386-dis.c: Change formatting conventions for architecture i386:intel to better match the format of various intel i386 assemblers, like nasm, tasm or masm. - 2001-07-18 Alan Modra <amodra@bigpond.net.au> +2001-07-24 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am: Update dependencies with "make dep-am". + * Makefile.in: Regenerate + +2001-07-24 Kazu Hirata <kazu@hxi.com> + + * alpha-dis.c: Fix formatting. + * cris-dis.c: Likewise. + * d10v-dis.c: Likewise. + * d30v-dis.c: Likewise. + * m10300-dis.c: Likewise. + * tic54x-dis.c: Likewise. + +2001-07-23 Kazu Hirata <kazu@hxi.com> + + * m68k-dis.c: Fix formatting. + * pj-dis.c: Likewise. + * s390-dis.c: Likewise. + * z8k-dis.c: Likewise. + +2001-07-21 Chris Demetriou <cgd@broadcom.com> + + * mips-opc.c (mips_builtin_opcodes): Sort c.le.s and c.lt.s + into the rest of the surrounding definitions. + +2001-07-18 Alan Modra <amodra@bigpond.net.au> + * i386-dis.c (grps): Print l or w suffix, and require mem modrm for lgdt, lidt, sgdt, sidt. - 2001-07-09 Andreas Jaeger <aj@suse.de>, Karsten Keil <kkeil@suse.de> +2001-07-13 Philip Blundell <philb@gnu.org> + + * arm-dis.c (print_insn_arm): Use decimal for offsets in LDR/STR. + +2001-07-12 Jeff Johnston <jjohnstn@redhat.com> + + * cgen-asm.in: Include "xregex.h" always to enable the libiberty + regex support. + (@arch@_cgen_build_insn_regex): New routine from Graydon. + (@arch@_cgen_assemble_insn): Add Graydon's code to use regex + to verify if it is worth parsing the insn as insn "x". Also update + error message when insn is not a recognized format of the insn vs + when the insn is completely unrecognized. + +2001-07-11 Frank Ch. Eigler <fche@redhat.com> + + * cgen-dis.in (print_insn): Use cgen_get_insn_value instead of + bfd_get_bits. + * cgen-opc.c (cgen_get_insn_value, cgen_put_insn_value): Respect + non-zero CGEN_CPU_DESC->insn_chunk_bitsize. + +2001-07-09 Andreas Jaeger <aj@suse.de>, Karsten Keil <kkeil@suse.de> + * i386-dis.c (set_op): Handle 64 bit and 32 bit mode. (OP_J): Use bfd_vma for mask to work properly with 64 bits. (op_address,op_riprel): Use bfd_vma to handle 64 bits. - 2001-06-11 Alan Modra <amodra@bigpond.net.au> +2001-07-05 Ben Elliston <bje@redhat.com> + + * Makefile.am (CPUDIR): Define. + (stamp-m32r): Update dependencies. + (stamp-fr30): Ditto. + (stamp-openrisc): Ditto. + * Makefile.in: Regenerate. + +2001-07-03 Zoltan Hidvegi <hzoli@hzoli.2y.net> + + * ppc-opc.c: Fix encoding of 'clf' instruction. + +2001-06-30 Geoffrey Keating <geoffk@redhat.com> + + * cgen-ibld.in (insert_normal): Support CGEN_IFLD_SIGN_OPT. + +2001-06-28 Geoffrey Keating <geoffk@redhat.com> + + * cgen-asm.c (cgen_parse_keyword): Allow any first character. + * cgen-opc.c (cgen_keyword_add): Ignore special first + character when building nonalpha_chars field. + +2001-06-24 Ben Elliston <bje@redhat.com> + + * m88k-dis.c: Format to conform to GNU coding standards. + +2001-06-23 Andreas Jaeger <aj@suse.de> + + * disassemble.c (disassembler_usage): Add unused attribute. + +2001-06-22 Eric Christopher <echristo@redhat.com> + + * mips-opc.c: Move prefx to start of the table. + +2001-06-22 Stacey Sheldon <ssheldon@Catena.com> + + * arc-opc.c (insert_st_syntax): Fix over-optimisation of ST + instruction. + +2001-06-22 Pauli <pauli@moreton.com.au> + + * m68k-opc.c: Add wdebug instruction. + +2001-06-15 Aldy Hernandez <aldyh@redhat.com> + + * m10300-opc.c (mn10300_opcodes): Change opcode for AM33 subc. + +2001-06-14 Geoffrey Keating <geoffk@redhat.com> + + * cgen-asm.c (cgen_parse_keyword): When looking for the + boundaries of a keyword, allow any special characters + that are actually in one of the allowed keyword. + * cgen-opc.c (cgen_keyword_add): Add any special characters + to the nonalpha_chars field. + +2001-06-12 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * s390-opc.c: Add lgh instruction. + * s390-opc.txt: Likewise. + +2001-06-11 Alan Modra <amodra@bigpond.net.au> + * i386-dis.c: Group function prototypes in one place. (FLOATCODE): Redefine as 1. (USE_GROUPS): Redefine as 2. @@ -64,7 +864,11 @@ (OP_ST, OP_STi, OP_SEG, OP_DIR, OP_OFF, OP_OFF64, OP_MMX): Rename 'ignore'/'ignored' to 'bytemode'. - 2001-06-10 Alan Modra <amodra@bigpond.net.au> +2001-06-10 Alan Modra <amodra@bigpond.net.au> + + * configure.in: Sort 'ta' case statement. + * configure: Regenerate. + * i386-dis.c (dis386_att): Add 'H' to conditional branch and loop,jcxz insns. (disx86_64_att): Likewise. @@ -73,23 +877,25 @@ (putop): 'H' macro prints branch hints. (get64): Kill compile warnings. -2001-07-16 Philip Blundell <philb@gnu.org> +2001-06-09 Alexandre Oliva <aoliva@redhat.com> - * arm-dis.c (print_insn_arm): Use decimal for offsets in LDR/STR. + * sh-opc.h (sh_table): Don't use empty initializers. -2001-07-03 Zoltan Hidvegi <hzoli@hzoli.2y.net> +2001-06-06 Christian Groessler <cpg@aladdin.de> - * ppc-opc.c: Fix encoding of 'clf' instruction. + * z8k-dis.c: Fix formatting. + (unpack_instr): Remove unused cases in switch statement. Add + safety abort() in default case. + (unparse_instr): Add safety abort() in default case. -2001-06-11 Alan Modra <amodra@bigpond.net.au> +2001-06-06 Peter Jakubek <pjak@snafu.de> - Merge from mainline. - 2001-06-06 Peter Jakubek <pjak@snafu.de> * m68k-dis.c (print_insn_m68k): Fix typo. * m68k-opc.c (m68k_opcodes): Correct allowed operands for mcf (ColdFire) div, rem and moveb instructions. - 2001-06-06 Alan Modra <amodra@bigpond.net.au> +2001-06-06 Alan Modra <amodra@bigpond.net.au> + * i386-dis.c (cond_jump_flag, loop_jcxz_flag): Define. (cond_jump_mode, loop_jcxz_mode): Define. (dis386_att): Add cond_jump_flag and loop_jcxz_flag as @@ -102,10 +908,30 @@ (putop): Handle 'F', and mark PREFIX_ADDR used for case 'E'. (OP_J): Don't make PREFIX_DATA used. - 2001-05-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> +2001-06-04 Alexandre Oliva <aoliva@redhat.com> + + * sh-opc.h (sh_table): Complete last element entry to avoid + compiler warning. + +2001-05-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + * mips-dis.c (mips_isa_type): Add MIPS r12k support. - 2001-05-15 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> +2001-05-23 Alan Modra <amodra@one.net.au> + + * arc-opc.c: Whitespace changes. + +2001-05-18 Hans-Peter Nilsson <hp@axis.com> + + * cris-opc.c (cris_spec_regs): Add missing initializer field for + last element. + +2001-05-15 Frank Ch. Eigler <fche@redhat.com> + + * cgen-dis.in (extract_normal): Complete support for min<base case. + +2001-05-15 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + * mips-dis.c (INSNLEN): Rename MAXLEN. (std_reg_names): Replace by mips32_reg_names and mips64_reg_names. (print_insn_arg): Remove $ prefix of register names. @@ -120,58 +946,19 @@ (print_mips16_insn_arg): Remove $ prefix of register names. Print error message before abort. - 2001-05-14 J.T. Conklin <jtc@redback.com> +2001-05-14 J.T. Conklin <jtc@redback.com> + * ppc-opc.c (powerpc_opcodes): Fixed extended opcode field of - simplified mnemonics used for setting PPC750-specific special + simplified mnemonics used for setting PPC750-specific special purpose registers. - 2001-03-23 Nick Clifton <nickc@redhat.com> - * mips-opc.c: Remove extraneous whitespace. - * mips-dis.c: Remove extraneous whitespace. - - 2001-03-06 Igor Shevlyakov <igor@windriver.com> - * m68k-dis.c (print_insn_m68k): Recognize Coldfire CPUs - so command line switches will work. - - 2001-02-28 Igor Shevlyakov <igor@windriver.com> - * m68k-opc.c: fix cpushl according to Motorola. Enable - bunch of instructions for Coldfire 5407 and add all new. - - 2001-02-27 Alan Modra <alan@linuxcare.com.au> - * configure.in (BFD_VERSION): Do without grep. - * configure: Regenerate. - * Makefile.am: Run "make dep-am". - * Makefile.in: Regenerate. - - 2001-02-20 H.J. Lu <hjl@gnu.org> - * Makefile.am (ia64-ic.tbl): Remove the target. - (ia64-raw.tbl): Likewise. - (ia64-waw.tbl): Likewise. - (ia64-war.tbl): Likewise. - (ia64-asmtab.c): Generate it in the source directory. - * Makefile.in: Regenerated. - - 2001-02-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl> - * mips-dis.c (print_insn_arg): Use top four bits of the address of - the following instruction not of the jump itself for the jump - target. - (print_mips16_insn_arg): Likewise. - - 2001-02-11 Michael Sokolov <msokolov@ivan.Harhan.ORG> - * Makefile.am (stamp-lib): ranlib the libopcodes.a in the build - directory. - * Makefile.in: Regenerate. - -2001-06-07 Alan Modra <amodra@bigpond.net.au> - - * Many files: Update copyright notices. +2001-05-12 H.J. Lu <hjl@gnu.org> -2001-05-23 Alan Modra <amodra@one.net.au> + * i386-dis.c (print_insn_i386): Always set `mod', `reg' and + `rm'. - * arc-opc.c: Whitespace changes. +2001-05-12 Peter Targett <peter.targett@arccores.com> - Merge from mainline - 2001-05-12 Peter Targett <peter.targett@arccores.com> * arc-opc.c (arc_reg_names): Correct attribute for lp_count register to r/w. Formatting fixes throughout file. @@ -187,6 +974,27 @@ (OP_EM): Likewise. (OP_EX): Likewise. +2001-05-07 Frank Ch. Eigler <fche@redhat.com> + + * cgen-dis.in (default_print_insn): Tolerate min<base instructions + even at end of a section. + * cgen-ibld.in (extract_normal): Tolerate min!=base!=max instructions + by ignoring precariously-unpacked insn_value in favor of raw buffer. + +2001-05-03 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * disassemble.c (disassembler_usage): Remove unused attribute. + +2001-05-04 Frank Ch. Eigler <fche@redhat.com> + + * m32r-dis.c, -asm.c, -ibld.c: Regenerated with disassembler fixes. + +2001-05-04 Frank Ch. Eigler <fche@redhat.com> + + * cgen-dis.in (print_insn): Remove call to read_insn. Instead, + assume incoming buffer already has the base insn loaded. Handle + smaller-than-base instructions for variable-length case. + 2001-05-04 Alan Modra <amodra@one.net.au> * i386-dis.c (Ev, Ed): Remove duplicate define. @@ -198,7 +1006,37 @@ (dis386_twobyte_intel): Likewise. (prefix_user_table): Use MS for maskmovq operand. - Merge mainline: 2001-04-06 Andreas Jaeger <aj@suse.de> +2001-04-27 Johan Rydberg <jrydberg@opencores.org> + + * Makefile.am: Add OpenRISC target. + * Makefile.in: Regenerated. + + * disassemble.c (disassembler): Recognize the OpenRISC disassembly. + + * configure.in (bfd_openrisc_arch): Add target. + * configure: Regenerated. + + * openrisc-asm.c: New file. + * openrisc-desc.c: Likewise. + * openrisc-desc.h: Likewise. + * openrisc-dis.c: Likewise. + * openrisc-ibld.c: Likewise. + * openrisc-opc.c: Likewise. + * openrisc-opc.h: Likewise. + +2001-04-24 Christian Groessler <cpg@aladdin.de> + + * z8k-dis.c: add names of control registers (ctrl_names); + (seg_length): provides instruction length fixup for segmented + mode; (unpack_instr): correctly handle ARG_DISP16, ARG_DISP12, + CLASS_0DISP7, CLASS_1DISP7, CLASS_DISP8 and CLASS_PR cases; + (unparse_intr): handle CLASS_PR, print addresses without '#' + * z8k-opc.h: re-created with new z8kgen + * z8kgen.c: merged in fixes which were in existing z8k-opc.h; new + entries for ldctl/ldctlb instruction + +2001-04-06 Andreas Jaeger <aj@suse.de> + * i386-dis.c: Add ffreep instruction. 2001-03-30 Alexandre Oliva <aoliva@redhat.com> @@ -218,12 +1056,41 @@ (prefix_user_table <maskmovdqu>): XM operand, not MX. (prefix_user_table): Cosmetic changes to "bad" entries. +2001-03-23 Nick Clifton <nickc@redhat.com> + + * mips-opc.c: Remove extraneous whitespace. + * mips-dis.c: Remove extraneous whitespace. + +2001-03-22 Ben Elliston <bje@redhat.com> + + * cgen-asm.in (@arch@_cgen_assemble_insn): Move tmp_errmsg + declaration inside CGEN_VERBOSE_ASSEMBLER_ERRORS conditional. + * cgen-ibld.in (put_insn_int_value): Mark cd parameter as unused + to allay a compiler warning. + 2001-03-22 Alan Modra <alan@linuxcare.com.au> * i386-dis.c (dis386_twobyte_att): Add entries for paddq, psubq. (dis386_twobyte_intel): Likewise. (twobyte_has_modrm): Set entry for paddq, psubq. +2001-03-20 Patrick Macdonald <patrickm@redhat.com> + + * cgen-dis.in (print_insn_@arch@): Add support for target machine + determination via CGEN_COMPUTE_MACH. + * fr30-desc.c: Regenerate. + * fr30-dis.c: Regenerate. + * fr30-opc.h: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-dis.c: Regenerate. + * m32r-opc.h: Regenerate. + * m32r-opinst.c: Regenerate. + +2001-03-20 H.J. Lu <hjl@gnu.org> + + * configure.in: Remove the redundent AC_ARG_PROGRAM. + * configure: Rebuild. + 2001-03-19 Jim Wilson <wilson@redhat.com> * ia64-gen.c (fetch_insn_class): If xsect, then ignore comment and @@ -236,6 +1103,52 @@ * vax-dis.c (print_insn_vax): Only fetch two bytes if the info buffer has more than one byte left to read. +2001-03-16 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * s390-opc.c: Add new opcodes. Smooth out formatting. + * s390-opc.txt: Add new opcodes. + +2001-03-06 Nick Clifton <nickc@redhat.com> + + * arm-dis.c (print_insn_thumb): Compute destination address + of BLX(1) instruction by taking bit 1 from PC and not from bit + 0 of the offset. + +2001-03-06 Igor Shevlyakov <igor@windriver.com> + + * m68k-dis.c (print_insn_m68k): Recognize Coldfire CPUs + so command line switches will work. + +2001-03-05 Dave Brolley <brolley@redhat.com> + + * fr30-asm.c: Regenerate. + * fr30-desc.c: Regenerate. + * fr30-desc.h: Regenerate. + * fr30-dis.c: Regenerate. + * fr30-ibld.c: Regenerate. + * fr30-opc.c: Regenerate. + * fr30-opc.h: Regenerate. + * m32r-asm.c: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-desc.h: Regenerate. + * m32r-dis.c: Regenerate. + * m32r-ibld.c: Regenerate. + * m32r-opc.c: Regenerate. + * m32r-opc.h: Regenerate. + * m32r-opinst.c: Regenerate. + +2001-02-28 Igor Shevlyakov <igor@windriver.com> + + * m68k-opc.c: fix cpushl according to Motorola. Enable + bunch of instructions for Coldfire 5407 and add all new. + +2001-02-27 Alan Modra <alan@linuxcare.com.au> + + * configure.in (BFD_VERSION): Do without grep. + * configure: Regenerate. + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + 2001-02-23 David Mosberger <davidm@hpl.hp.com> * ia64-opc-a.c: Add missing pseudo-ops for "cmp" and "cmp4". @@ -246,25 +1159,75 @@ * ia64-opc-d.c (ia64_opcodes_d): Break the "add" pattern into two separate variants: one for IMM22 and the other for IMM14. * ia64-asmtab.c: Regenerate. - + +2001-02-21 Greg McGary <greg@mcgary.org> + + * cgen-opc.c (cgen_get_insn_value): Add missing `return'. + +2001-02-20 H.J. Lu <hjl@gnu.org> + + * Makefile.am (ia64-ic.tbl): Remove the target. + (ia64-raw.tbl): Likewise. + (ia64-waw.tbl): Likewise. + (ia64-war.tbl): Likewise. + (ia64-asmtab.c): Generate it in the source directory. + * Makefile.in: Regenerated. + +2001-02-18 lars brinkhoff <lars@nocrew.org> + + * Makefile.am: Add PDP-11 target. + * configure.in: Likewise. + * disassemble.c: Likewise. + * pdp11-dis.c: New file. + * pdp11-opc.c: New file. + 2001-02-14 Jim Wilson <wilson@redhat.com> * ia64-ic.tbl: Update from Intel. Add setf to fr-writers. * ia64-asmtab.c: Regenerate. -Mon Feb 12 17:38:59 CET 2001 Jan Hubicka <jh@suse.cz> +Mon Feb 12 17:41:26 CET 2001 Jan Hubicka <jh@suse.cz> * i386-dis.c (prefix_user_t): Add 'Y' to SSE ineger converison instructions. (putop): Handle 'Y' +2001-02-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl> + + * mips-dis.c (print_insn_arg): Use top four bits of the address of + the following instruction not of the jump itself for the jump + target. + (print_mips16_insn_arg): Likewise. + +2001-02-11 Michael Sokolov <msokolov@ivan.Harhan.ORG> + + * Makefile.am (stamp-lib): ranlib the libopcodes.a in the build + directory. + * Makefile.in: Regenerate. + +2001-02-09 Schwidefsky <schwidefsky@de.ibm.com> + + * Makefile.am: Add linux target for S/390. + * Makefile.in: Likewise. + * configure.in: Likewise. + * disassemble.c: Likewise. + * s390-dis.c: New file. + * s390-mkopc.c: New file. + * s390-opc.c: New file. + * s390-opc.txt: New file. + 2001-02-05 Jim Wilson <wilson@redhat.com> * ia64-asmtab.c: Revert 2000-12-16 change. -Thu Feb 1 16:41:58 MET 2001 Jan Hubicka <jh@suse.cz> +2001-02-02 Patrick Macdonald <patrickm@redhat.com> + + * fr30-desc.h: Regenerate with CGEN_MAX_SYNTAX_ELEMENTS. + * m32r-desc.h: Regenerate. + +Thu Feb 1 16:29:06 MET 2001 Jan Hubicka <jh@suse.cz> - * i387-dis.c (dis386_att, grps): Use 'T' for push/pop + * i386-dis.c (dis386_att, grps): Use 'T' for push/pop (putop): Handle 'T', alphabetize order, fix 'I' handling in Intel syntax 2001-01-14 Alan Modra <alan@linuxcare.com.au> diff --git a/contrib/binutils/opcodes/ChangeLog-9297 b/contrib/binutils/opcodes/ChangeLog-9297 index 5fa3fa0..799457e 100644 --- a/contrib/binutils/opcodes/ChangeLog-9297 +++ b/contrib/binutils/opcodes/ChangeLog-9297 @@ -1480,7 +1480,7 @@ Wed Oct 2 23:28:42 1996 Jeffrey A Law (law@cygnus.com) * mn10x00-opc.c, mn10x00-dis.c: New files for Matsushita MN10x00 processors. - * disassemble (ARCH_mn10x00): Define. + * disassemble.c (ARCH_mn10x00): Define. (disassembler): Handle bfd_arch_mn10x00. * configure.in: Recognize bfd_mn10x00_arch. * configure: Rebuilt. @@ -2982,7 +2982,7 @@ Wed Jul 13 18:01:58 1994 Ken Raeburn (raeburn@cujo.cygnus.com) Sun Jul 10 00:27:47 1994 Ian Dall (dall@hfrd.dsto.gov.au) - * opcodes/ns32k-dis.c: Semi-new file. Had apparently been dropped + * ns32k-dis.c: Semi-new file. Had apparently been dropped from distribution. A ns32k-dis.c from a previous distribution has been brought up to date and supports the new interface. @@ -3217,7 +3217,7 @@ Wed Jan 5 11:56:21 1994 David J. Mackenzie (djm@thepub.cygnus.com) Wed Nov 17 17:20:12 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) - * mips-opc.h: Use macro for j instruction, to support SVR4 PIC. + * mips-opc.c: Use macro for j instruction, to support SVR4 PIC. Removed t,A case for la; always use t,A(b) case. Mon Nov 8 12:37:36 1993 Ian Lance Taylor (ian@tweedledumb.cygnus.com) @@ -3618,7 +3618,7 @@ Wed Mar 31 10:07:04 1993 Jim Kingdon (kingdon@lioth.cygnus.com) for a preceding `sethi' in order to print an absolute address. * (print_insn): Disassembly prefers real instructions. (is_delayed_branch): Speed up. - * sparc-opcode.h: Add ALIAS bit to aliases. Fix up opcode tables. + * sparc-opc.c: Add ALIAS bit to aliases. Fix up opcode tables. Still missing some float ops, and needs testing. * sparc-pinsn.c (print_insn): Eliminate 'set' test, subsumed by F_ALIAS. Use printf, not fprintf, when not passing a file @@ -3735,7 +3735,7 @@ Wed Sep 30 07:42:17 1992 Steve Chamberlain (sac@thepub.cygnus.com) Tue Sep 29 12:20:21 1992 Steve Chamberlain (sac@thepub.cygnus.com) * z8k-dis.c (unparse_instr): prettier tabs - * z8kgen.c -> z8k-opc.h: bug fixes in tables + * z8kgen.c z8k-opc.h: bug fixes in tables Fri Sep 25 12:50:32 1992 Stu Grossman (grossman at cygnus.com) @@ -3785,6 +3785,12 @@ Mon Aug 31 13:47:35 1992 Steve Chamberlain (sac@thepub.cygnus.com) * z8k-dis.c: knows how to disassemble z8k stuff * z8k-opc.h: new file full of z8000 opcodes +Fri Aug 28 15:38:03 1992 Ken Raeburn (raeburn@cygnus.com) + + * Renamed opc-sparc.c to sparc-opc.c for systems with short + filename constraints. + * Makefile.in: Updated to reflect change. + Local Variables: version-control: never diff --git a/contrib/binutils/opcodes/ChangeLog-9899 b/contrib/binutils/opcodes/ChangeLog-9899 index 8588f0a..3f8bf77 100644 --- a/contrib/binutils/opcodes/ChangeLog-9899 +++ b/contrib/binutils/opcodes/ChangeLog-9899 @@ -86,9 +86,9 @@ Thu Oct 7 00:12:43 MDT 1999 Diego Novillo <dnovillo@cygnus.com> 1999-10-04 Doug Evans <devans@casey.cygnus.com> - * fr30-asm.c,fr30-desc.h: Rebuild. - * m32r-asm.c,m32r-desc.c,m32r-desc.h: Rebuild. Add m32rx support. - * m32r-dis.c,m32r-ibld.c,m32r-opc.c,m32r-opc.h,m32r-opinst.c: Ditto. + * fr30-asm.c, fr30-desc.h: Rebuild. + * m32r-asm.c, m32r-desc.c, m32r-desc.h: Rebuild. Add m32rx support. + * m32r-dis.c, m32r-ibld.c, m32r-opc.c, m32r-opc.h, m32r-opinst.c: Ditto. 1999-09-29 Nick Clifton <nickc@cygnus.com> @@ -178,8 +178,8 @@ Mon Aug 30 18:56:14 1999 Richard Henderson <rth@cygnus.com> 1999-08-04 Doug Evans <devans@casey.cygnus.com> - * fr30-asm.c,fr30-desc.h,fr30-dis.c,fr30-ibld.c,fr30-opc.c: Rebuild. - * m32r-asm.c,m32r-desc.h,m32r-dis.c,m32r-ibld.c,m32r-opc.c: Rebuild. + * fr30-asm.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c, fr30-opc.c: Rebuild. + * m32r-asm.c, m32r-desc.h, m32r-dis.c, m32r-ibld.c, m32r-opc.c: Rebuild. * m32r-opinst.c: Rebuild. Sat Aug 28 00:27:24 1999 Jerry Quinn <jquinn@nortelnetworks.com> @@ -446,8 +446,8 @@ Mon Jun 7 12:04:52 1999 Andreas Schwab <schwab@issan.cs.uni-dortmund.de> 1999-04-14 Doug Evans <devans@casey.cygnus.com> - * fr30-desc.c,fr30-desc.h,fr30-dis.c,fr30-ibld.c,fr30-opc.c: Rebuild. - * m32r-desc.c,m32r-desc.h,m32r-dis.c,m32r-ibld.c,m32r-opc.c: Rebuild. + * fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c, fr30-opc.c: Rebuild. + * m32r-desc.c, m32r-desc.h, m32r-dis.c, m32r-ibld.c, m32r-opc.c: Rebuild. Mon Apr 12 23:46:17 1999 Jeffrey A Law (law@cygnus.com) @@ -456,8 +456,8 @@ Mon Apr 12 23:46:17 1999 Jeffrey A Law (law@cygnus.com) 1999-04-10 Doug Evans <devans@casey.cygnus.com> - * fr30-desc.c,fr30-desc.h,fr30-ibld.c: Rebuild. - * m32r-desc.c,m32r-desc.h,m32r-opinst.c: Rebuild. + * fr30-desc.c, fr30-desc.h, fr30-ibld.c: Rebuild. + * m32r-desc.c, m32r-desc.h, m32r-opinst.c: Rebuild. 1999-04-06 Ian Lance Taylor <ian@zembu.com> @@ -484,10 +484,10 @@ Mon Apr 12 23:46:17 1999 Jeffrey A Law (law@cygnus.com) * cgen-opc.c (cgen_set_cpu): Delete. (cgen_lookup_insn): max_insn_size renamed to max_insn_bitsize. - * fr30-desc.c,fr30-desc.h,fr30-dis.c,fr30-ibld.c,fr30-opc.c,fr30-opc.h: - Rebuild. - * m32r-desc.c,m32r-desc.h,m32r-dis.c,m32r-ibld.c,m32r-opc.c,m32r-opc.h: - Rebuild. + * fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c, fr30-opc.c, + fr30-opc.h: Rebuild. + * m32r-desc.c, m32r-desc.h, m32r-dis.c, m32r-ibld.c, m32r-opc.c, + m32r-opc.h: Rebuild. * po/opcodes.pot: Rebuild. 1999-03-16 Martin Hunt <hunt@cygnus.com> @@ -499,16 +499,16 @@ Mon Apr 12 23:46:17 1999 Jeffrey A Law (law@cygnus.com) * cgen-opc.c (cgen_set_cpu): New arg `isa'. All callers updated. (cgen_operand_lookup_by_name,cgen_operand_lookup_by_num): New fns. (cgen_get_insn_operands): Rewrite test for hardcoded/operand index. - * fr30-asm.c,fr30-desc.c,fr30-desc.h,fr30-dis.c,fr30-ibld.c: Rebuild. - * m32r-asm.c,m32r-desc.c,m32r-desc.h,m32r-dis.c,m32r-ibld.c: Rebuild. + * fr30-asm.c, fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c: Rebuild. + * m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c, m32r-ibld.c: Rebuild. * m32r-opinst.c: Rebuild. 1999-02-25 Doug Evans <devans@casey.cygnus.com> * cgen-opc.c (cgen_hw_lookup_by_name): Rewrite. (cgen_hw_lookup_by_num): Rewrite. - * fr30-desc.c,fr30-desc.h,fr30-dis.c,fr30-ibld.c,fr30-opc.c: Rebuild. - * m32r-desc.c,m32r-desc.h,m32r-dis.c,m32r-ibld.c,m32r-opc.c: Rebuild. + * fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c, fr30-opc.c: Rebuild. + * m32r-desc.c, m32r-desc.h, m32r-dis.c, m32r-ibld.c, m32r-opc.c: Rebuild. * m32r-opinst.c: Rebuild. Sat Feb 13 14:06:19 1999 Richard Henderson <rth@cygnus.com> @@ -523,11 +523,11 @@ Sat Feb 13 14:06:19 1999 Richard Henderson <rth@cygnus.com> 1999-02-09 Doug Evans <devans@casey.cygnus.com> - * i960c-asm.c,i960c-dis.c,i960c-opc.c,i960c-opc.h: Delete. + * i960c-asm.c, i960c-dis.c, i960c-opc.c, i960c-opc.h: Delete. * i960-dis.c (print_insn_i960): Rename from print_insn_i960_orig. * Makefile.am: Remove references to them. - (HFILES): Add fr30-desc.h,m32r-desc.h. - (CFILES): Add fr30-desc.c,fr30-ibld.c,m32r-desc.c,m32r-ibld.c, + (HFILES): Add fr30-desc.h, m32r-desc.h. + (CFILES): Add fr30-desc.c, fr30-ibld.c, m32r-desc.c, m32r-ibld.c, m32r-opinst.c. (ALL_MACHINES): Update. * configure.in: Redo handling of cgen_files. @@ -540,8 +540,8 @@ Sat Feb 13 14:06:19 1999 Richard Henderson <rth@cygnus.com> * cgen-opc.c (*): CGEN_OPCODE_DESC renamed to CGEN_CPU_DESC. (cgen_lookup_insn,cgen_get_insn_operands): Define here. (cgen_lookup_get_insn_operands): Ditto. - * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerate. - * m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate. + * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerate. + * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: Regenerate. * po/POTFILES.in: Rebuild. * po/opcodes.pot: Rebuild. @@ -592,8 +592,8 @@ Mon Feb 1 20:54:36 1999 Catherine Moore <clm@cygnus.com> 1999-01-27 Doug Evans <devans@casey.cygnus.com> - * fr30-opc.h,fr30-opc.c: Rebuild. - * i960c-opc.h,i960c-opc.c: Rebuild. + * fr30-opc.h, fr30-opc.c: Rebuild. + * i960c-opc.h, i960c-opc.c: Rebuild. * m32r-opc.c: Rebuild. Tue Jan 19 18:01:54 1999 David Taylor <taylor@texas.cygnus.com> @@ -612,7 +612,7 @@ Tue Jan 19 10:51:01 1999 David Taylor <taylor@texas.cygnus.com> 1999-01-12 Doug Evans <devans@casey.cygnus.com> - * fr30-opc.c,i960c-opc.c: Regenerate. + * fr30-opc.c, i960c-opc.c: Regenerate. 1999-01-11 Doug Evans <devans@casey.cygnus.com> @@ -624,9 +624,9 @@ Tue Jan 19 10:51:01 1999 David Taylor <taylor@texas.cygnus.com> 1999-01-05 Doug Evans <devans@casey.cygnus.com> - * fr30-asm.c,fr30-dis.c,fr30-opc.h,fr30-opc.c: Regenerate. - * i960c-asm.c,i960c-dis.c,i960c-opc.h,i960c-opc.c: Regenerate. - * m32r-asm.c,m32r-dis.c,m32r-opc.h,m32r-opc.c: Regenerate. + * fr30-asm.c, fr30-dis.c, fr30-opc.h, fr30-opc.c: Regenerate. + * i960c-asm.c, i960c-dis.c, i960c-opc.h, i960c-opc.c: Regenerate. + * m32r-asm.c, m32r-dis.c, m32r-opc.h, m32r-opc.c: Regenerate. 1999-01-04 Jason Molenda (jsm@bugshack.cygnus.com) @@ -646,15 +646,15 @@ Wed Dec 16 16:17:49 1998 Dave Brolley <brolley@cygnus.com> 1998-12-15 Dave Brolley <brolley@cygnus.com> - * fr30-opc.c,fr30-opc.h: Regenerated. + * fr30-opc.c, fr30-opc.h: Regenerated. 1998-12-14 Dave Brolley <brolley@cygnus.com> - * fr30-opc.c,fr30-opc.h: Regenerated. + * fr30-opc.c, fr30-opc.h: Regenerated. Thu Dec 10 18:39:46 1998 Dave Brolley <brolley@cygnus.com> - * fr30-opc.c,fr30-opc.h: Regenerated. + * fr30-opc.c, fr30-opc.h: Regenerated. Thu Dec 10 12:49:24 1998 Doug Evans <devans@canuck.cygnus.com> @@ -667,7 +667,7 @@ Tue Dec 8 13:56:18 1998 David Taylor <taylor@texas.cygnus.com> Tue Dec 8 13:12:44 1998 Dave Brolley <brolley@cygnus.com> - * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated. + * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerated. Tue Dec 8 10:50:46 1998 David Taylor <taylor@texas.cygnus.com> @@ -715,7 +715,7 @@ Tue Dec 8 10:50:46 1998 David Taylor <taylor@texas.cygnus.com> Mon Dec 7 14:33:44 1998 Dave Brolley <brolley@cygnus.com> - * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated. + * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerated. Sun Dec 6 14:06:48 1998 Ian Lance Taylor <ian@cygnus.com> @@ -730,34 +730,34 @@ Fri Dec 4 17:45:51 1998 Doug Evans <devans@canuck.cygnus.com> Fri Dec 4 17:08:08 1998 Dave Brolley <brolley@cygnus.com> - * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated. + * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerated. Thu Dec 3 14:26:20 1998 Dave Brolley <brolley@cygnus.com> - * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated. + * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerated. Thu Dec 3 00:09:17 1998 Doug Evans <devans@canuck.cygnus.com> - * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerate. + * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerate. 1998-11-30 Doug Evans <devans@casey.cygnus.com> * cgen-dis.c (hash_insn_array): CGEN_INSN_VALUE -> CGEN_INSN_BASE_VALUE. - * m32r-opc.c,m32r-opc.h,m32r-asm.c,m32r-dis.c: Regenerate. - * fr30-opc.c,fr30-opc.h,fr30-asm.c,fr30-dis.c: Regenerate. + * m32r-opc.c, m32r-opc.h, m32r-asm.c, m32r-dis.c: Regenerate. + * fr30-opc.c, fr30-opc.h, fr30-asm.c, fr30-dis.c: Regenerate. Thu Nov 26 11:26:32 1998 Dave Brolley <brolley@cygnus.com> - * fr30-asm.c,fr30-dis.c,fr30-opc.c: Regenerated. + * fr30-asm.c, fr30-dis.c, fr30-opc.c: Regenerated. Tue Nov 24 11:20:54 1998 Dave Brolley <brolley@cygnus.com> - * fr30-asm.c,fr30-dis.c: Regenerated. + * fr30-asm.c, fr30-dis.c: Regenerated. Mon Nov 23 18:28:48 1998 Dave Brolley <brolley@cygnus.com> - * fr30-asm.c,fr30-dis.c,fr30-opc.c,fr30-opc.h: Regenerated. + * fr30-asm.c, fr30-dis.c, fr30-opc.c, fr30-opc.h: Regenerated. 1998-11-20 Doug Evans <devans@tobor.to.cygnus.com> @@ -785,8 +785,8 @@ Wed Nov 18 21:36:37 1998 Dave Brolley <brolley@cygnus.com> 1998-11-18 Doug Evans <devans@casey.cygnus.com> - * m32r-asm.c,m32r-dis.c,m32r-opc.c: Rebuild. - * fr30-asm.c,fr30-dis.c,fr30-opc.c: Rebuild. + * m32r-asm.c, m32r-dis.c, m32r-opc.c: Rebuild. + * fr30-asm.c, fr30-dis.c, fr30-opc.c: Rebuild. Wed Nov 18 11:30:04 1998 Dave Brolley <brolley@cygnus.com> @@ -813,8 +813,8 @@ Tue Nov 10 15:26:27 1998 Nick Clifton <nickc@cygnus.com> Tue Nov 10 11:00:04 1998 Doug Evans <devans@canuck.cygnus.com> - * m32r-dis.c,m32r-opc.c,m32r-opc.h: Rebuild. - * fr30-dis.c,fr30-opc.c,fr30-opc.h: Rebuild. + * m32r-dis.c, m32r-opc.c, m32r-opc.h: Rebuild. + * fr30-dis.c, fr30-opc.c, fr30-opc.h: Rebuild. Mon Nov 9 18:22:55 1998 Dave Brolley <brolley@cygnus.com> @@ -852,11 +852,11 @@ Tue Oct 27 08:58:37 1998 Gavin Romig-Koch <gavin@cygnus.com> Mon Oct 19 13:03:19 1998 Doug Evans <devans@seba.cygnus.com> - * m32r-opc.c,m32r-opc.h,m32r-asm.c,m32r-dis.c: Regenerate. + * m32r-opc.c, m32r-opc.h, m32r-asm.c, m32r-dis.c: Regenerate. Fri Oct 9 14:01:56 1998 Doug Evans <devans@seba.cygnus.com> - * m32r-opc.h,m32r-opc.c: Regenerate. + * m32r-opc.h, m32r-opc.c: Regenerate. Sun Oct 4 21:01:44 1998 Alan Modra <alan@spri.levels.unisa.edu.au> @@ -894,7 +894,7 @@ Tue Sep 22 17:55:14 1998 Nick Clifton <nickc@cygnus.com> Tue Sep 15 15:14:45 1998 Doug Evans <devans@canuck.cygnus.com> - * m32r-opc.h,m32r-opc.c: Add bbpc,bbpsw support. + * m32r-opc.h, m32r-opc.c: Add bbpc,bbpsw support. 1998-09-09 Michael Meissner <meissner@cygnus.com> @@ -969,7 +969,7 @@ Mon Aug 3 12:43:16 1998 Doug Evans <devans@seba.cygnus.com> (cgen_dis_init): Delete. * cgen-opc.c (all fns): New first arg of opcode table descriptor. (cgen_current_{opcode_table_mach,endian}): Delete. - * m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate. + * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: Regenerate. Thu Jul 30 21:41:10 1998 Frank Ch. Eigler <fche@cygnus.com> @@ -983,11 +983,11 @@ Tue Jul 28 11:00:09 1998 Jeffrey A Law (law@cygnus.com) Fri Jul 24 11:41:37 1998 Doug Evans <devans@canuck.cygnus.com> - * m32r-asm.c,m32r-opc.c: Regenerate (-Wall cleanups). + * m32r-asm.c, m32r-opc.c: Regenerate (-Wall cleanups). Tue Jul 21 13:41:07 1998 Doug Evans <devans@seba.cygnus.com> - * m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate. + * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. Mon Jul 13 14:53:59 1998 Alan Modra <alan@spri.levels.unisa.edu.au> @@ -1004,7 +1004,7 @@ Thu Jul 2 17:11:27 1998 Doug Evans <devans@seba.cygnus.com> Wed Jul 1 16:11:16 1998 Doug Evans <devans@seba.cygnus.com> - * m32r-asm.c,m32r-dis.c,m32r-opc.c,m32r-opc.h: Regenerate. + * m32r-asm.c, m32r-dis.c, m32r-opc.c, m32r-opc.h: Regenerate. Fri Jun 26 11:08:55 1998 Jeffrey A Law (law@cygnus.com) @@ -1197,7 +1197,7 @@ Tue May 26 16:14:39 1998 Nick Clifton <nickc@cygnus.com> Fri May 22 16:00:00 1998 Doug Evans <devans@canuck.cygnus.com> - * m32r-asm.c,m32r-dis.c: Regenerate. + * m32r-asm.c, m32r-dis.c: Regenerate. Tue May 19 17:36:08 1998 Ian Lance Taylor <ian@cygnus.com> @@ -1329,7 +1329,7 @@ Mon Apr 27 10:33:56 1998 Doug Evans <devans@seba.cygnus.com> (hash_insn_array,hash_insn_list): New functions. (build_asm_hash_table): Use them. Hash macro insns as well. (cgen_asm_lookup_insn): Update. - * cgen_dis.c (cgen_current_opcode_table): Renamed from ..._data. + * cgen-dis.c (cgen_current_opcode_table): Renamed from ..._data. (dis_hash_table_entries): New variable. (cgen_dis_init): Free dis_hash_table_entries. (hash_insn_array,hash_insn_list): New functions. @@ -1338,7 +1338,7 @@ Mon Apr 27 10:33:56 1998 Doug Evans <devans@seba.cygnus.com> * cgen-opc.c (cgen_current_opcode_table): Renamed from ..._data. (cgen_set_cpu,cgen_hw_lookup,cgen_insn_count): Update. (cgen_macro_insn_count): New function. - * m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate. + * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. Fri Apr 24 16:07:57 1998 Alan Modra <alan@spri.levels.unisa.edu.au> @@ -1497,7 +1497,7 @@ Sat Mar 14 23:47:14 1998 Doug Evans <devans@seba.cygnus.com> Wed Mar 4 12:08:14 1998 Doug Evans <devans@canuck.cygnus.com> - * m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate. + * m32r-opc.h, m32r-opc.c, m32r-asm.c, m32r-dis.c: Regenerate. Sat Feb 28 16:02:34 1998 Nick Clifton <nickc@cygnus.com> @@ -1529,8 +1529,8 @@ Tue Feb 24 11:06:18 1998 Nick Clifton <nickc@cygnus.com> Mon Feb 23 13:16:17 1998 Doug Evans <devans@seba.cygnus.com> * cgen-asm.c: Include symcat.h. - * cgen-dis.c,cgen-opc.c: Ditto. - * m32r-asm.c,m32r-dis.c,m32r-opc.h,m32r-opc.c: Regenerate. + * cgen-dis.c, cgen-opc.c: Ditto. + * m32r-asm.c, m32r-dis.c, m32r-opc.h, m32r-opc.c: Regenerate. Mon Feb 23 10:34:58 1998 Jeffrey A Law (law@cygnus.com) @@ -1544,7 +1544,7 @@ Tue Feb 17 17:14:50 1998 Doug Evans <devans@seba.cygnus.com> * cgen-asm.c (cgen_parse_{signed,unsigned}_integer): Delete min,max arguments. Don't perform validation here. - * m32r-asm.c,m32r-dis.c,m32r-opc.c: Regenerate. + * m32r-asm.c, m32r-dis.c, m32r-opc.c: Regenerate. Fri Feb 13 14:26:06 1998 Doug Evans <devans@canuck.cygnus.com> diff --git a/contrib/binutils/opcodes/Makefile.am b/contrib/binutils/opcodes/Makefile.am index ad2330b..7c9da2e 100644 --- a/contrib/binutils/opcodes/Makefile.am +++ b/contrib/binutils/opcodes/Makefile.am @@ -26,11 +26,13 @@ HFILES = \ h8500-opc.h \ m32r-desc.h m32r-opc.h \ mcore-opc.h \ + openrisc-desc.h openrisc-opc.h \ sh-opc.h \ sysdep.h \ ia64-asmtab.h \ ia64-opc.h \ w65-opc.h \ + xstormy16-desc.h xstormy16-opc.h \ z8k-opc.h # C source files that correspond to .o's. @@ -96,11 +98,23 @@ CFILES = \ m10200-opc.c \ m10300-dis.c \ m10300-opc.c \ + mmix-dis.c \ + mmix-opc.c \ ns32k-dis.c \ + openrisc-asm.c \ + openrisc-desc.c \ + openrisc-dis.c \ + openrisc-ibld.c \ + openrisc-opc.c \ + pdp11-dis.c \ + pdp11-opc.c \ pj-dis.c \ pj-opc.c \ ppc-dis.c \ ppc-opc.c \ + s390-mkopc.c \ + s390-opc.c \ + s390-dis.c \ sh-dis.c \ sparc-dis.c \ sparc-opc.c \ @@ -113,6 +127,11 @@ CFILES = \ v850-opc.c \ vax-dis.c \ w65-dis.c \ + xstormy16-asm.c \ + xstormy16-desc.c \ + xstormy16-dis.c \ + xstormy16-ibld.c \ + xstormy16-opc.c \ z8k-dis.c \ z8kgen.c @@ -168,11 +187,22 @@ ALL_MACHINES = \ mips-dis.lo \ mips-opc.lo \ mips16-opc.lo \ + mmix-dis.lo \ + mmix-opc.lo \ ns32k-dis.lo \ + openrisc-asm.lo \ + openrisc-desc.lo \ + openrisc-dis.lo \ + openrisc-ibld.lo \ + openrisc-opc.lo \ + pdp11-dis.lo \ + pdp11-opc.lo \ pj-dis.lo \ pj-opc.lo \ ppc-dis.lo \ ppc-opc.lo \ + s390-dis.lo \ + s390-opc.lo \ sh-dis.lo \ sparc-dis.lo \ sparc-opc.lo \ @@ -185,6 +215,11 @@ ALL_MACHINES = \ v850-opc.lo \ vax-dis.lo \ w65-dis.lo \ + xstormy16-asm.lo \ + xstormy16-desc.lo \ + xstormy16-dis.lo \ + xstormy16-ibld.lo \ + xstormy16-opc.lo \ z8k-dis.lo OFILES = @BFD_MACHINES@ @@ -228,11 +263,13 @@ config.status: $(srcdir)/configure $(srcdir)/../bfd/configure.in $(SHELL) ./config.status --recheck CLEANFILES = \ - stamp-m32r stamp-fr30 \ + stamp-m32r stamp-fr30 stamp-openrisc \ + stamp-xstormy16 \ libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 CGENDIR = @cgendir@ +CPUDIR = $(CGENDIR)/cpu CGEN = `if test -f ../guile/libguile/guile ; then echo ../guile/libguile/guile; else echo guile ; fi` CGENFLAGS = -v @@ -246,9 +283,13 @@ CGENDEPS = ../cgen/stamp-cgen \ if CGEN_MAINT M32R_DEPS = stamp-m32r FR30_DEPS = stamp-fr30 +OPENRISC_DEPS = stamp-openrisc +XSTORMY16_DEPS = stamp-xstormy16 else M32R_DEPS = FR30_DEPS = +OPENRISC_DEPS = +XSTORMY16_DEPS = endif run-cgen: @@ -261,14 +302,24 @@ run-cgen: # For now, require developers to configure with --enable-cgen-maint. $(srcdir)/m32r-desc.h $(srcdir)/m32r-desc.c $(srcdir)/m32r-opc.h $(srcdir)/m32r-opc.c $(srcdir)/m32r-ibld.c $(srcdir)/m32r-opinst.c $(srcdir)/m32r-asm.c $(srcdir)/m32r-dis.c: $(M32R_DEPS) @true -stamp-m32r: $(CGENDEPS) $(CGENDIR)/m32r.cpu $(CGENDIR)/m32r.opc +stamp-m32r: $(CGENDEPS) $(CPUDIR)/m32r.cpu $(CPUDIR)/m32r.opc $(MAKE) run-cgen arch=m32r prefix=m32r options=opinst extrafiles=opinst $(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-opc.c $(srcdir)/fr30-ibld.c $(srcdir)/fr30-asm.c $(srcdir)/fr30-dis.c: $(FR30_DEPS) @true -stamp-fr30: $(CGENDEPS) $(CGENDIR)/fr30.cpu $(CGENDIR)/fr30.opc +stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc $(MAKE) run-cgen arch=fr30 prefix=fr30 options= extrafiles= +$(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS) + @true +stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc + $(MAKE) run-cgen arch=openrisc prefix=openrisc options= extrafiles= + +$(srcdir)/xstormy16-desc.h $(srcdir)/xstormy16-desc.c $(srcdir)/xstormy16-opc.h $(srcdir)/xstormy16-opc.c $(srcdir)/xstormy16-ibld.c $(srcdir)/xstormy16-asm.c $(srcdir)/xstormy16-dis.c: $(XSTORMY16_DEPS) + @true +stamp-xstormy16: $(CGENDEPS) $(CPUDIR)/xstormy16.cpu $(CPUDIR)/xstormy16.opc + $(MAKE) run-cgen arch=xstormy16 prefix=xstormy16 options= extrafiles= + ia64-gen: ia64-gen.o $(LINK) ia64-gen.o $(LIBIBERTY) @@ -278,6 +329,14 @@ ia64-gen.o: ia64-gen.c ia64-opc.c ia64-opc-a.c ia64-opc-b.c ia64-opc-f.c \ ia64-asmtab.c: @MAINT@ ia64-gen ia64-ic.tbl ia64-raw.tbl ia64-waw.tbl ia64-war.tbl here=`pwd`; cd $(srcdir); $$here/ia64-gen > ia64-asmtab.c +s390-mkopc: s390-mkopc.c + $(CC_FOR_BUILD) -o s390-mkopc $(srcdir)/s390-mkopc.c + +s390-opc.tab: s390-mkopc s390-opc.txt + ./s390-mkopc < $(srcdir)/s390-opc.txt > s390-opc.tab + +Makefile: $(BFDDIR)/configure.in + # This dependency stuff is copied from BFD. DEP: dep.sed $(CFILES) $(HFILES) config.h @@ -326,53 +385,60 @@ dep-am: DEP # DO NOT DELETE THIS LINE -- mkdep uses it. # DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY. a29k-dis.lo: a29k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/a29k.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/a29k.h alpha-dis.lo: alpha-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/alpha.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/alpha.h alpha-opc.lo: alpha-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/opcode/alpha.h $(BFD_H) opintl.h + $(INCDIR)/opcode/alpha.h $(BFD_H) $(INCDIR)/symcat.h \ + opintl.h arc-dis.lo: arc-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/opcode/arc.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \ - $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \ - $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h opintl.h \ - arc-dis.h arc-ext.h -arc-opc.lo: arc-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/arc.h -arc-ext.lo: arc-ext.c $(BFD_H) $(INCDIR)/ansidecl.h \ - arc-ext.h $(INCDIR)/libiberty.h -arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) arm-opc.h $(INCDIR)/coff/internal.h \ - $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h opintl.h $(BFDDIR)/elf-bfd.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h $(BFDDIR)/elf-bfd.h \ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ - $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h + $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h \ + opintl.h arc-dis.h arc-ext.h +arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/arc.h +arc-ext.lo: arc-ext.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h arc-ext.h $(INCDIR)/libiberty.h +arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h arm-opc.h \ + $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \ + opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \ + $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/arm.h \ + $(INCDIR)/elf/reloc-macros.h avr-dis.lo: avr-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) opintl.h $(INCDIR)/opcode/avr.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h \ + $(INCDIR)/opcode/avr.h cgen-asm.lo: cgen-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/libiberty.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h \ - opintl.h + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h $(BFD_H) \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h opintl.h cgen-dis.lo: cgen-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/libiberty.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h cgen-opc.lo: cgen-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/libiberty.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h $(BFD_H) \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h cris-dis.lo: cris-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/ansidecl.h sysdep.h config.h $(INCDIR)/opcode/cris.h \ - $(INCDIR)/libiberty.h + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \ + $(INCDIR)/opcode/cris.h $(INCDIR)/libiberty.h cris-opc.lo: cris-opc.c $(INCDIR)/opcode/cris.h d10v-dis.lo: d10v-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/opcode/d10v.h $(INCDIR)/dis-asm.h $(BFD_H) + $(INCDIR)/opcode/d10v.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h d10v-opc.lo: d10v-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/d10v.h d30v-dis.lo: d30v-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/d30v.h $(INCDIR)/dis-asm.h $(BFD_H) \ - opintl.h + $(INCDIR)/symcat.h opintl.h d30v-opc.lo: d30v-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/d30v.h dis-buf.lo: dis-buf.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) opintl.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h disassemble.lo: disassemble.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h fr30-asm.lo: fr30-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \ - fr30-opc.h opintl.h + fr30-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h fr30-desc.lo: fr30-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \ fr30-opc.h opintl.h $(INCDIR)/libiberty.h @@ -381,29 +447,32 @@ fr30-dis.lo: fr30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h fr30-ibld.lo: fr30-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h \ - $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h + $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h $(INCDIR)/safe-ctype.h fr30-opc.lo: fr30-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \ fr30-opc.h $(INCDIR)/libiberty.h h8300-dis.lo: h8300-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/h8300.h $(INCDIR)/dis-asm.h $(BFD_H) \ - opintl.h + $(INCDIR)/symcat.h opintl.h h8500-dis.lo: h8500-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - h8500-opc.h $(INCDIR)/dis-asm.h $(BFD_H) opintl.h + h8500-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ + opintl.h hppa-dis.lo: hppa-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(BFDDIR)/libhppa.h $(INCDIR)/opcode/hppa.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(BFDDIR)/libhppa.h \ + $(INCDIR)/opcode/hppa.h i370-dis.lo: i370-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/i370.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/i370.h i370-opc.lo: i370-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/i370.h i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/ansidecl.h sysdep.h config.h opintl.h + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \ + opintl.h i860-dis.lo: i860-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/ansidecl.h $(INCDIR)/opcode/i860.h + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/i860.h i960-dis.lo: i960-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h ia64-dis.lo: ia64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/ansidecl.h $(INCDIR)/opcode/ia64.h + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/ia64.h ia64-opc-a.lo: ia64-opc-a.c ia64-opc.h $(INCDIR)/opcode/ia64.h ia64-opc-b.lo: ia64-opc-b.c ia64-opc.h $(INCDIR)/opcode/ia64.h ia64-opc-f.lo: ia64-opc-f.c ia64-opc.h $(INCDIR)/opcode/ia64.h @@ -414,13 +483,14 @@ ia64-opc.lo: ia64-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ sysdep.h config.h ia64-asmtab.h $(INCDIR)/opcode/ia64.h \ ia64-asmtab.c ia64-gen.lo: ia64-gen.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ - sysdep.h config.h ia64-opc.h $(INCDIR)/opcode/ia64.h \ - ia64-opc-a.c ia64-opc-i.c ia64-opc-m.c ia64-opc-b.c \ - ia64-opc-f.c ia64-opc-x.c ia64-opc-d.c + $(INCDIR)/safe-ctype.h sysdep.h config.h ia64-opc.h \ + $(INCDIR)/opcode/ia64.h ia64-opc-a.c ia64-opc-i.c ia64-opc-m.c \ + ia64-opc-b.c ia64-opc-f.c ia64-opc-x.c ia64-opc-d.c ia64-asmtab.lo: ia64-asmtab.c m32r-asm.lo: m32r-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ - m32r-opc.h opintl.h + m32r-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h m32r-desc.lo: m32r-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ m32r-opc.h opintl.h $(INCDIR)/libiberty.h @@ -429,7 +499,7 @@ m32r-dis.lo: m32r-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/cgen.h m32r-opc.h opintl.h m32r-ibld.lo: m32r-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h \ - $(INCDIR)/opcode/cgen.h m32r-opc.h opintl.h + $(INCDIR)/opcode/cgen.h m32r-opc.h opintl.h $(INCDIR)/safe-ctype.h m32r-opc.lo: m32r-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ m32r-opc.h $(INCDIR)/libiberty.h @@ -437,21 +507,22 @@ m32r-opinst.lo: m32r-opinst.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ m32r-opc.h m68hc11-dis.lo: m68hc11-dis.c $(INCDIR)/ansidecl.h \ - $(INCDIR)/opcode/m68hc11.h $(INCDIR)/dis-asm.h $(BFD_H) + $(INCDIR)/opcode/m68hc11.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h m68hc11-opc.lo: m68hc11-opc.c $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/m68hc11.h m68k-dis.lo: m68k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/floatformat.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/floatformat.h \ opintl.h $(INCDIR)/opcode/m68k.h m68k-opc.lo: m68k-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/m68k.h m88k-dis.lo: m88k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/m88k.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/m88k.h \ opintl.h mcore-dis.lo: mcore-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - mcore-opc.h $(INCDIR)/dis-asm.h $(BFD_H) + mcore-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h mips-dis.lo: mips-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/mips.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/mips.h \ opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \ $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \ $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h @@ -461,53 +532,104 @@ mips16-opc.lo: mips16-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/mips.h m10200-dis.lo: m10200-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/mn10200.h $(INCDIR)/dis-asm.h $(BFD_H) \ - opintl.h + $(INCDIR)/symcat.h opintl.h m10200-opc.lo: m10200-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/mn10200.h m10300-dis.lo: m10300-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/mn10300.h $(INCDIR)/dis-asm.h $(BFD_H) \ - opintl.h + $(INCDIR)/symcat.h opintl.h m10300-opc.lo: m10300-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/mn10300.h -ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \ - sysdep.h config.h $(INCDIR)/dis-asm.h $(INCDIR)/opcode/ns32k.h \ +mmix-dis.lo: mmix-dis.c $(INCDIR)/opcode/mmix.h $(INCDIR)/dis-asm.h \ + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ opintl.h +mmix-opc.lo: mmix-opc.c $(INCDIR)/opcode/mmix.h $(INCDIR)/symcat.h +ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h sysdep.h config.h $(INCDIR)/dis-asm.h \ + $(INCDIR)/opcode/ns32k.h opintl.h +openrisc-asm.lo: openrisc-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h openrisc-desc.h $(INCDIR)/opcode/cgen.h \ + openrisc-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +openrisc-desc.lo: openrisc-desc.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h openrisc-desc.h \ + $(INCDIR)/opcode/cgen.h openrisc-opc.h opintl.h $(INCDIR)/libiberty.h +openrisc-dis.lo: openrisc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h openrisc-desc.h \ + $(INCDIR)/opcode/cgen.h openrisc-opc.h opintl.h +openrisc-ibld.lo: openrisc-ibld.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ + openrisc-desc.h $(INCDIR)/opcode/cgen.h openrisc-opc.h \ + opintl.h $(INCDIR)/safe-ctype.h +openrisc-opc.lo: openrisc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h openrisc-desc.h $(INCDIR)/opcode/cgen.h \ + openrisc-opc.h $(INCDIR)/libiberty.h +pdp11-dis.lo: pdp11-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/pdp11.h +pdp11-opc.lo: pdp11-opc.c $(INCDIR)/opcode/pdp11.h pj-dis.lo: pj-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/opcode/pj.h $(INCDIR)/dis-asm.h $(BFD_H) + $(INCDIR)/opcode/pj.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h pj-opc.lo: pj-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/pj.h ppc-dis.lo: ppc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/ppc.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/ppc.h ppc-opc.lo: ppc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/ppc.h opintl.h +s390-mkopc.lo: s390-mkopc.c +s390-opc.lo: s390-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/s390.h \ + s390-opc.tab +s390-dis.lo: s390-dis.c $(INCDIR)/ansidecl.h sysdep.h \ + config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ + $(INCDIR)/opcode/s390.h sh-dis.lo: sh-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - sh-opc.h $(INCDIR)/dis-asm.h $(BFD_H) + sh-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h sparc-dis.lo: sparc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/sparc.h $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/libiberty.h opintl.h + $(INCDIR)/symcat.h $(INCDIR)/libiberty.h opintl.h sparc-opc.lo: sparc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/sparc.h tic30-dis.lo: tic30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/tic30.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/tic30.h tic54x-dis.lo: tic54x-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/tic54x.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/tic54x.h \ $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h tic54x-opc.lo: tic54x-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/opcode/tic54x.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/tic54x.h tic80-dis.lo: tic80-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/opcode/tic80.h $(INCDIR)/dis-asm.h $(BFD_H) + $(INCDIR)/opcode/tic80.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h tic80-opc.lo: tic80-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/tic80.h v850-dis.lo: v850-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/v850.h $(INCDIR)/dis-asm.h $(BFD_H) \ - opintl.h + $(INCDIR)/symcat.h opintl.h v850-opc.lo: v850-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/v850.h opintl.h vax-dis.lo: vax-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/opcode/vax.h $(INCDIR)/dis-asm.h $(BFD_H) + $(INCDIR)/opcode/vax.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h w65-dis.lo: w65-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - w65-opc.h $(INCDIR)/dis-asm.h $(BFD_H) + w65-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h +xstormy16-asm.lo: xstormy16-asm.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \ + $(INCDIR)/opcode/cgen.h xstormy16-opc.h opintl.h $(INCDIR)/xregex.h \ + $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +xstormy16-desc.lo: xstormy16-desc.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \ + $(INCDIR)/opcode/cgen.h xstormy16-opc.h opintl.h $(INCDIR)/libiberty.h +xstormy16-dis.lo: xstormy16-dis.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ + xstormy16-desc.h $(INCDIR)/opcode/cgen.h xstormy16-opc.h \ + opintl.h +xstormy16-ibld.lo: xstormy16-ibld.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ + xstormy16-desc.h $(INCDIR)/opcode/cgen.h xstormy16-opc.h \ + opintl.h $(INCDIR)/safe-ctype.h +xstormy16-opc.lo: xstormy16-opc.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \ + $(INCDIR)/opcode/cgen.h xstormy16-opc.h $(INCDIR)/libiberty.h z8k-dis.lo: z8k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) z8k-opc.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h z8k-opc.h z8kgen.lo: z8kgen.c sysdep.h config.h $(INCDIR)/ansidecl.h # IF YOU PUT ANYTHING HERE IT WILL GO AWAY diff --git a/contrib/binutils/opcodes/Makefile.in b/contrib/binutils/opcodes/Makefile.in index 07be307..8cc2744 100644 --- a/contrib/binutils/opcodes/Makefile.in +++ b/contrib/binutils/opcodes/Makefile.in @@ -136,11 +136,13 @@ HFILES = \ h8500-opc.h \ m32r-desc.h m32r-opc.h \ mcore-opc.h \ + openrisc-desc.h openrisc-opc.h \ sh-opc.h \ sysdep.h \ ia64-asmtab.h \ ia64-opc.h \ w65-opc.h \ + xstormy16-desc.h xstormy16-opc.h \ z8k-opc.h @@ -207,11 +209,23 @@ CFILES = \ m10200-opc.c \ m10300-dis.c \ m10300-opc.c \ + mmix-dis.c \ + mmix-opc.c \ ns32k-dis.c \ + openrisc-asm.c \ + openrisc-desc.c \ + openrisc-dis.c \ + openrisc-ibld.c \ + openrisc-opc.c \ + pdp11-dis.c \ + pdp11-opc.c \ pj-dis.c \ pj-opc.c \ ppc-dis.c \ ppc-opc.c \ + s390-mkopc.c \ + s390-opc.c \ + s390-dis.c \ sh-dis.c \ sparc-dis.c \ sparc-opc.c \ @@ -224,6 +238,11 @@ CFILES = \ v850-opc.c \ vax-dis.c \ w65-dis.c \ + xstormy16-asm.c \ + xstormy16-desc.c \ + xstormy16-dis.c \ + xstormy16-ibld.c \ + xstormy16-opc.c \ z8k-dis.c \ z8kgen.c @@ -280,11 +299,22 @@ ALL_MACHINES = \ mips-dis.lo \ mips-opc.lo \ mips16-opc.lo \ + mmix-dis.lo \ + mmix-opc.lo \ ns32k-dis.lo \ + openrisc-asm.lo \ + openrisc-desc.lo \ + openrisc-dis.lo \ + openrisc-ibld.lo \ + openrisc-opc.lo \ + pdp11-dis.lo \ + pdp11-opc.lo \ pj-dis.lo \ pj-opc.lo \ ppc-dis.lo \ ppc-opc.lo \ + s390-dis.lo \ + s390-opc.lo \ sh-dis.lo \ sparc-dis.lo \ sparc-opc.lo \ @@ -297,6 +327,11 @@ ALL_MACHINES = \ v850-opc.lo \ vax-dis.lo \ w65-dis.lo \ + xstormy16-asm.lo \ + xstormy16-desc.lo \ + xstormy16-dis.lo \ + xstormy16-ibld.lo \ + xstormy16-opc.lo \ z8k-dis.lo @@ -319,11 +354,13 @@ noinst_LIBRARIES = libopcodes.a POTFILES = $(HFILES) $(CFILES) CLEANFILES = \ - stamp-m32r stamp-fr30 \ + stamp-m32r stamp-fr30 stamp-openrisc \ + stamp-xstormy16 \ libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 CGENDIR = @cgendir@ +CPUDIR = $(CGENDIR)/cpu CGEN = `if test -f ../guile/libguile/guile ; then echo ../guile/libguile/guile; else echo guile ; fi` CGENFLAGS = -v @@ -338,6 +375,10 @@ CGENDEPS = ../cgen/stamp-cgen \ @CGEN_MAINT_FALSE@M32R_DEPS = @CGEN_MAINT_TRUE@FR30_DEPS = @CGEN_MAINT_TRUE@stamp-fr30 @CGEN_MAINT_FALSE@FR30_DEPS = +@CGEN_MAINT_TRUE@OPENRISC_DEPS = @CGEN_MAINT_TRUE@stamp-openrisc +@CGEN_MAINT_FALSE@OPENRISC_DEPS = +@CGEN_MAINT_TRUE@XSTORMY16_DEPS = @CGEN_MAINT_TRUE@stamp-xstormy16 +@CGEN_MAINT_FALSE@XSTORMY16_DEPS = ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 mkinstalldirs = $(SHELL) $(top_srcdir)/../mkinstalldirs CONFIG_HEADER = config.h @@ -772,14 +813,24 @@ run-cgen: # For now, require developers to configure with --enable-cgen-maint. $(srcdir)/m32r-desc.h $(srcdir)/m32r-desc.c $(srcdir)/m32r-opc.h $(srcdir)/m32r-opc.c $(srcdir)/m32r-ibld.c $(srcdir)/m32r-opinst.c $(srcdir)/m32r-asm.c $(srcdir)/m32r-dis.c: $(M32R_DEPS) @true -stamp-m32r: $(CGENDEPS) $(CGENDIR)/m32r.cpu $(CGENDIR)/m32r.opc +stamp-m32r: $(CGENDEPS) $(CPUDIR)/m32r.cpu $(CPUDIR)/m32r.opc $(MAKE) run-cgen arch=m32r prefix=m32r options=opinst extrafiles=opinst $(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-opc.c $(srcdir)/fr30-ibld.c $(srcdir)/fr30-asm.c $(srcdir)/fr30-dis.c: $(FR30_DEPS) @true -stamp-fr30: $(CGENDEPS) $(CGENDIR)/fr30.cpu $(CGENDIR)/fr30.opc +stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc $(MAKE) run-cgen arch=fr30 prefix=fr30 options= extrafiles= +$(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS) + @true +stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc + $(MAKE) run-cgen arch=openrisc prefix=openrisc options= extrafiles= + +$(srcdir)/xstormy16-desc.h $(srcdir)/xstormy16-desc.c $(srcdir)/xstormy16-opc.h $(srcdir)/xstormy16-opc.c $(srcdir)/xstormy16-ibld.c $(srcdir)/xstormy16-asm.c $(srcdir)/xstormy16-dis.c: $(XSTORMY16_DEPS) + @true +stamp-xstormy16: $(CGENDEPS) $(CPUDIR)/xstormy16.cpu $(CPUDIR)/xstormy16.opc + $(MAKE) run-cgen arch=xstormy16 prefix=xstormy16 options= extrafiles= + ia64-gen: ia64-gen.o $(LINK) ia64-gen.o $(LIBIBERTY) @@ -789,6 +840,14 @@ ia64-gen.o: ia64-gen.c ia64-opc.c ia64-opc-a.c ia64-opc-b.c ia64-opc-f.c \ ia64-asmtab.c: @MAINT@ ia64-gen ia64-ic.tbl ia64-raw.tbl ia64-waw.tbl ia64-war.tbl here=`pwd`; cd $(srcdir); $$here/ia64-gen > ia64-asmtab.c +s390-mkopc: s390-mkopc.c + $(CC_FOR_BUILD) -o s390-mkopc $(srcdir)/s390-mkopc.c + +s390-opc.tab: s390-mkopc s390-opc.txt + ./s390-mkopc < $(srcdir)/s390-opc.txt > s390-opc.tab + +Makefile: $(BFDDIR)/configure.in + # This dependency stuff is copied from BFD. DEP: dep.sed $(CFILES) $(HFILES) config.h @@ -837,53 +896,60 @@ dep-am: DEP # DO NOT DELETE THIS LINE -- mkdep uses it. # DO NOT PUT ANYTHING AFTER THIS LINE, IT WILL GO AWAY. a29k-dis.lo: a29k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/a29k.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/a29k.h alpha-dis.lo: alpha-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/alpha.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/alpha.h alpha-opc.lo: alpha-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/opcode/alpha.h $(BFD_H) opintl.h + $(INCDIR)/opcode/alpha.h $(BFD_H) $(INCDIR)/symcat.h \ + opintl.h arc-dis.lo: arc-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/opcode/arc.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \ - $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \ - $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h opintl.h \ - arc-dis.h arc-ext.h -arc-opc.lo: arc-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/arc.h -arc-ext.lo: arc-ext.c $(BFD_H) $(INCDIR)/ansidecl.h \ - arc-ext.h $(INCDIR)/libiberty.h -arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) arm-opc.h $(INCDIR)/coff/internal.h \ - $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h opintl.h $(BFDDIR)/elf-bfd.h \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h $(BFDDIR)/elf-bfd.h \ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ - $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h + $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h $(INCDIR)/elf/reloc-macros.h \ + opintl.h arc-dis.h arc-ext.h +arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/opcode/arc.h +arc-ext.lo: arc-ext.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h arc-ext.h $(INCDIR)/libiberty.h +arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h arm-opc.h \ + $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \ + opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \ + $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/arm.h \ + $(INCDIR)/elf/reloc-macros.h avr-dis.lo: avr-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) opintl.h $(INCDIR)/opcode/avr.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h \ + $(INCDIR)/opcode/avr.h cgen-asm.lo: cgen-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/libiberty.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h \ - opintl.h + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h $(BFD_H) \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h opintl.h cgen-dis.lo: cgen-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/libiberty.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h cgen-opc.lo: cgen-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/libiberty.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h $(BFD_H) \ + $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h cris-dis.lo: cris-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/ansidecl.h sysdep.h config.h $(INCDIR)/opcode/cris.h \ - $(INCDIR)/libiberty.h + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \ + $(INCDIR)/opcode/cris.h $(INCDIR)/libiberty.h cris-opc.lo: cris-opc.c $(INCDIR)/opcode/cris.h d10v-dis.lo: d10v-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/opcode/d10v.h $(INCDIR)/dis-asm.h $(BFD_H) + $(INCDIR)/opcode/d10v.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h d10v-opc.lo: d10v-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/d10v.h d30v-dis.lo: d30v-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/d30v.h $(INCDIR)/dis-asm.h $(BFD_H) \ - opintl.h + $(INCDIR)/symcat.h opintl.h d30v-opc.lo: d30v-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/d30v.h dis-buf.lo: dis-buf.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) opintl.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h disassemble.lo: disassemble.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h fr30-asm.lo: fr30-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \ - fr30-opc.h opintl.h + fr30-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h fr30-desc.lo: fr30-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \ fr30-opc.h opintl.h $(INCDIR)/libiberty.h @@ -892,29 +958,32 @@ fr30-dis.lo: fr30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h fr30-ibld.lo: fr30-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h \ - $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h + $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h $(INCDIR)/safe-ctype.h fr30-opc.lo: fr30-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \ fr30-opc.h $(INCDIR)/libiberty.h h8300-dis.lo: h8300-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/h8300.h $(INCDIR)/dis-asm.h $(BFD_H) \ - opintl.h + $(INCDIR)/symcat.h opintl.h h8500-dis.lo: h8500-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - h8500-opc.h $(INCDIR)/dis-asm.h $(BFD_H) opintl.h + h8500-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ + opintl.h hppa-dis.lo: hppa-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(BFDDIR)/libhppa.h $(INCDIR)/opcode/hppa.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(BFDDIR)/libhppa.h \ + $(INCDIR)/opcode/hppa.h i370-dis.lo: i370-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/i370.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/i370.h i370-opc.lo: i370-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/i370.h i386-dis.lo: i386-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/ansidecl.h sysdep.h config.h opintl.h + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \ + opintl.h i860-dis.lo: i860-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/ansidecl.h $(INCDIR)/opcode/i860.h + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/i860.h i960-dis.lo: i960-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h ia64-dis.lo: ia64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/ansidecl.h $(INCDIR)/opcode/ia64.h + $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/opcode/ia64.h ia64-opc-a.lo: ia64-opc-a.c ia64-opc.h $(INCDIR)/opcode/ia64.h ia64-opc-b.lo: ia64-opc-b.c ia64-opc.h $(INCDIR)/opcode/ia64.h ia64-opc-f.lo: ia64-opc-f.c ia64-opc.h $(INCDIR)/opcode/ia64.h @@ -925,13 +994,14 @@ ia64-opc.lo: ia64-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ sysdep.h config.h ia64-asmtab.h $(INCDIR)/opcode/ia64.h \ ia64-asmtab.c ia64-gen.lo: ia64-gen.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ - sysdep.h config.h ia64-opc.h $(INCDIR)/opcode/ia64.h \ - ia64-opc-a.c ia64-opc-i.c ia64-opc-m.c ia64-opc-b.c \ - ia64-opc-f.c ia64-opc-x.c ia64-opc-d.c + $(INCDIR)/safe-ctype.h sysdep.h config.h ia64-opc.h \ + $(INCDIR)/opcode/ia64.h ia64-opc-a.c ia64-opc-i.c ia64-opc-m.c \ + ia64-opc-b.c ia64-opc-f.c ia64-opc-x.c ia64-opc-d.c ia64-asmtab.lo: ia64-asmtab.c m32r-asm.lo: m32r-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ - m32r-opc.h opintl.h + m32r-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h m32r-desc.lo: m32r-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ m32r-opc.h opintl.h $(INCDIR)/libiberty.h @@ -940,7 +1010,7 @@ m32r-dis.lo: m32r-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/cgen.h m32r-opc.h opintl.h m32r-ibld.lo: m32r-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h \ - $(INCDIR)/opcode/cgen.h m32r-opc.h opintl.h + $(INCDIR)/opcode/cgen.h m32r-opc.h opintl.h $(INCDIR)/safe-ctype.h m32r-opc.lo: m32r-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ m32r-opc.h $(INCDIR)/libiberty.h @@ -948,21 +1018,22 @@ m32r-opinst.lo: m32r-opinst.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ m32r-opc.h m68hc11-dis.lo: m68hc11-dis.c $(INCDIR)/ansidecl.h \ - $(INCDIR)/opcode/m68hc11.h $(INCDIR)/dis-asm.h $(BFD_H) + $(INCDIR)/opcode/m68hc11.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h m68hc11-opc.lo: m68hc11-opc.c $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/m68hc11.h m68k-dis.lo: m68k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/floatformat.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/floatformat.h \ opintl.h $(INCDIR)/opcode/m68k.h m68k-opc.lo: m68k-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/m68k.h m88k-dis.lo: m88k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/m88k.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/m88k.h \ opintl.h mcore-dis.lo: mcore-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - mcore-opc.h $(INCDIR)/dis-asm.h $(BFD_H) + mcore-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h mips-dis.lo: mips-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/mips.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/mips.h \ opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \ $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \ $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h @@ -972,54 +1043,105 @@ mips16-opc.lo: mips16-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/mips.h m10200-dis.lo: m10200-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/mn10200.h $(INCDIR)/dis-asm.h $(BFD_H) \ - opintl.h + $(INCDIR)/symcat.h opintl.h m10200-opc.lo: m10200-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/mn10200.h m10300-dis.lo: m10300-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/mn10300.h $(INCDIR)/dis-asm.h $(BFD_H) \ - opintl.h + $(INCDIR)/symcat.h opintl.h m10300-opc.lo: m10300-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/mn10300.h -ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \ - sysdep.h config.h $(INCDIR)/dis-asm.h $(INCDIR)/opcode/ns32k.h \ +mmix-dis.lo: mmix-dis.c $(INCDIR)/opcode/mmix.h $(INCDIR)/dis-asm.h \ + $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ opintl.h +mmix-opc.lo: mmix-opc.c $(INCDIR)/opcode/mmix.h $(INCDIR)/symcat.h +ns32k-dis.lo: ns32k-dis.c $(BFD_H) $(INCDIR)/ansidecl.h \ + $(INCDIR)/symcat.h sysdep.h config.h $(INCDIR)/dis-asm.h \ + $(INCDIR)/opcode/ns32k.h opintl.h +openrisc-asm.lo: openrisc-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h openrisc-desc.h $(INCDIR)/opcode/cgen.h \ + openrisc-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +openrisc-desc.lo: openrisc-desc.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h openrisc-desc.h \ + $(INCDIR)/opcode/cgen.h openrisc-opc.h opintl.h $(INCDIR)/libiberty.h +openrisc-dis.lo: openrisc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h openrisc-desc.h \ + $(INCDIR)/opcode/cgen.h openrisc-opc.h opintl.h +openrisc-ibld.lo: openrisc-ibld.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ + openrisc-desc.h $(INCDIR)/opcode/cgen.h openrisc-opc.h \ + opintl.h $(INCDIR)/safe-ctype.h +openrisc-opc.lo: openrisc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h openrisc-desc.h $(INCDIR)/opcode/cgen.h \ + openrisc-opc.h $(INCDIR)/libiberty.h +pdp11-dis.lo: pdp11-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/pdp11.h +pdp11-opc.lo: pdp11-opc.c $(INCDIR)/opcode/pdp11.h pj-dis.lo: pj-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/opcode/pj.h $(INCDIR)/dis-asm.h $(BFD_H) + $(INCDIR)/opcode/pj.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h pj-opc.lo: pj-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/pj.h ppc-dis.lo: ppc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/ppc.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/ppc.h ppc-opc.lo: ppc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/ppc.h opintl.h +s390-mkopc.lo: s390-mkopc.c +s390-opc.lo: s390-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/opcode/s390.h \ + s390-opc.tab +s390-dis.lo: s390-dis.c $(INCDIR)/ansidecl.h sysdep.h \ + config.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ + $(INCDIR)/opcode/s390.h sh-dis.lo: sh-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - sh-opc.h $(INCDIR)/dis-asm.h $(BFD_H) + sh-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h sparc-dis.lo: sparc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/sparc.h $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/libiberty.h opintl.h + $(INCDIR)/symcat.h $(INCDIR)/libiberty.h opintl.h sparc-opc.lo: sparc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/sparc.h tic30-dis.lo: tic30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/tic30.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/tic30.h tic54x-dis.lo: tic54x-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/opcode/tic54x.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/tic54x.h \ $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h tic54x-opc.lo: tic54x-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/opcode/tic54x.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/tic54x.h tic80-dis.lo: tic80-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/opcode/tic80.h $(INCDIR)/dis-asm.h $(BFD_H) + $(INCDIR)/opcode/tic80.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h tic80-opc.lo: tic80-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/tic80.h v850-dis.lo: v850-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/v850.h $(INCDIR)/dis-asm.h $(BFD_H) \ - opintl.h + $(INCDIR)/symcat.h opintl.h v850-opc.lo: v850-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/v850.h opintl.h vax-dis.lo: vax-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/opcode/vax.h $(INCDIR)/dis-asm.h $(BFD_H) + $(INCDIR)/opcode/vax.h $(INCDIR)/dis-asm.h $(BFD_H) \ + $(INCDIR)/symcat.h w65-dis.lo: w65-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - w65-opc.h $(INCDIR)/dis-asm.h $(BFD_H) + w65-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h +xstormy16-asm.lo: xstormy16-asm.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \ + $(INCDIR)/opcode/cgen.h xstormy16-opc.h opintl.h $(INCDIR)/xregex.h \ + $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +xstormy16-desc.lo: xstormy16-desc.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \ + $(INCDIR)/opcode/cgen.h xstormy16-opc.h opintl.h $(INCDIR)/libiberty.h +xstormy16-dis.lo: xstormy16-dis.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ + xstormy16-desc.h $(INCDIR)/opcode/cgen.h xstormy16-opc.h \ + opintl.h +xstormy16-ibld.lo: xstormy16-ibld.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ + xstormy16-desc.h $(INCDIR)/opcode/cgen.h xstormy16-opc.h \ + opintl.h $(INCDIR)/safe-ctype.h +xstormy16-opc.lo: xstormy16-opc.c sysdep.h config.h \ + $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \ + $(INCDIR)/opcode/cgen.h xstormy16-opc.h $(INCDIR)/libiberty.h z8k-dis.lo: z8k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) z8k-opc.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h z8k-opc.h z8kgen.lo: z8kgen.c sysdep.h config.h $(INCDIR)/ansidecl.h # IF YOU PUT ANYTHING HERE IT WILL GO AWAY diff --git a/contrib/binutils/opcodes/aclocal.m4 b/contrib/binutils/opcodes/aclocal.m4 index a3aa924..2a4c03d 100644 --- a/contrib/binutils/opcodes/aclocal.m4 +++ b/contrib/binutils/opcodes/aclocal.m4 @@ -28,6 +28,24 @@ AC_DEFUN([CY_WITH_NLS],) AC_SUBST(INTLLIBS) ]) +#serial 1 +# This test replaces the one in autoconf. +# Currently this macro should have the same name as the autoconf macro +# because gettext's gettext.m4 (distributed in the automake package) +# still uses it. Otherwise, the use in gettext.m4 makes autoheader +# give these diagnostics: +# configure.in:556: AC_TRY_COMPILE was called before AC_ISC_POSIX +# configure.in:556: AC_TRY_RUN was called before AC_ISC_POSIX + +undefine([AC_ISC_POSIX]) + +AC_DEFUN(AC_ISC_POSIX, + [ + dnl This test replaces the obsolescent AC_ISC_POSIX kludge. + AC_CHECK_LIB(cposix, strerror, [LIBS="$LIBS -lcposix"]) + ] +) + # Do all the work for Automake. This macro actually does too much -- # some checks are only needed if your package does certain things. # But this isn't really a big deal. diff --git a/contrib/binutils/opcodes/alpha-dis.c b/contrib/binutils/opcodes/alpha-dis.c index 8633d7b..49b5f20 100644 --- a/contrib/binutils/opcodes/alpha-dis.c +++ b/contrib/binutils/opcodes/alpha-dis.c @@ -1,5 +1,5 @@ /* alpha-dis.c -- Disassemble Alpha AXP instructions - Copyright 1996, 1998, 1999, 2000 Free Software Foundation, Inc. + Copyright 1996, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. Contributed by Richard Henderson <rth@tamu.edu>, patterned after the PPC opcode handling written by Ian Lance Taylor. @@ -27,8 +27,7 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA /* OSF register names. */ -static const char * const osf_regnames[64] = -{ +static const char * const osf_regnames[64] = { "v0", "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", "s0", "s1", "s2", "s3", "s4", "s5", "fp", "a0", "a1", "a2", "a3", "a4", "a5", "t8", "t9", @@ -41,8 +40,7 @@ static const char * const osf_regnames[64] = /* VMS register names. */ -static const char * const vms_regnames[64] = -{ +static const char * const vms_regnames[64] = { "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", "R16", "R17", "R18", "R19", "R20", "R21", "R22", "R23", @@ -74,11 +72,11 @@ print_insn_alpha (memaddr, info) opcode_end = opcode + alpha_num_opcodes; for (op = 0; op < AXP_NOPS; ++op) - { - opcode_index[op] = opcode; - while (opcode < opcode_end && op == AXP_OP (opcode->opcode)) + { + opcode_index[op] = opcode; + while (opcode < opcode_end && op == AXP_OP (opcode->opcode)) ++opcode; - } + } opcode_index[op] = opcode; } @@ -107,8 +105,8 @@ print_insn_alpha (memaddr, info) int status = (*info->read_memory_func) (memaddr, buffer, 4, info); if (status != 0) { - (*info->memory_error_func) (status, memaddr, info); - return -1; + (*info->memory_error_func) (status, memaddr, info); + return -1; } insn = bfd_getl32 (buffer); } @@ -117,10 +115,10 @@ print_insn_alpha (memaddr, info) op = AXP_OP (insn); /* Find the first match in the opcode table. */ - opcode_end = opcode_index[op+1]; + opcode_end = opcode_index[op + 1]; for (opcode = opcode_index[op]; opcode < opcode_end; ++opcode) { - if ((insn & opcode->mask) != opcode->opcode) + if ((insn ^ opcode->opcode) & opcode->mask) continue; if (!(opcode->flags & isa_mask)) @@ -130,14 +128,14 @@ print_insn_alpha (memaddr, info) have extraction functions, and, if they do, make sure the instruction is valid. */ { - int invalid = 0; - for (opindex = opcode->operands; *opindex != 0; opindex++) + int invalid = 0; + for (opindex = opcode->operands; *opindex != 0; opindex++) { - const struct alpha_operand *operand = alpha_operands + *opindex; + const struct alpha_operand *operand = alpha_operands + *opindex; if (operand->extract) (*operand->extract) (insn, &invalid); } - if (invalid) + if (invalid) continue; } @@ -147,7 +145,7 @@ print_insn_alpha (memaddr, info) /* No instruction found */ (*info->fprintf_func) (info->stream, ".long %#08x", insn); - + return 4; found: @@ -182,7 +180,7 @@ found: } if (need_comma && - ((operand->flags & (AXP_OPERAND_PARENS|AXP_OPERAND_COMMA)) + ((operand->flags & (AXP_OPERAND_PARENS | AXP_OPERAND_COMMA)) != AXP_OPERAND_PARENS)) { (*info->fprintf_func) (info->stream, ","); @@ -194,7 +192,7 @@ found: if (operand->flags & AXP_OPERAND_IR) (*info->fprintf_func) (info->stream, "%s", regnames[value]); else if (operand->flags & AXP_OPERAND_FPR) - (*info->fprintf_func) (info->stream, "%s", regnames[value+32]); + (*info->fprintf_func) (info->stream, "%s", regnames[value + 32]); else if (operand->flags & AXP_OPERAND_RELATIVE) (*info->print_address_func) (memaddr + 4 + value, info); else if (operand->flags & AXP_OPERAND_SIGNED) diff --git a/contrib/binutils/opcodes/alpha-opc.c b/contrib/binutils/opcodes/alpha-opc.c index 7680f47..7a20a55 100644 --- a/contrib/binutils/opcodes/alpha-opc.c +++ b/contrib/binutils/opcodes/alpha-opc.c @@ -30,10 +30,10 @@ almost all of the extended instruction mnemonics. This permits the disassembler to use them, and simplifies the assembler logic, at the cost of increasing the table size. The table is strictly constant - data, so the compiler should be able to put it in the .text section. + data, so the compiler should be able to put it in the text segment. This file also holds the operand table. All knowledge about inserting - operands into instructions and vice-versa is kept in this file. + and extracting operands from instructions is kept in this file. The information for the base instruction set was compiled from the _Alpha Architecture Handbook_, Digital Order Number EC-QD2KB-TE, @@ -542,7 +542,8 @@ const struct alpha_opcode alpha_opcodes[] = { { "lda", MEM(0x08), BASE, ARG_MEM }, { "ldah", MEM(0x09), BASE, ARG_MEM }, { "ldbu", MEM(0x0A), BWX, ARG_MEM }, - { "unop", MEM(0x0B), BASE, { ZA } }, /* pseudo */ + { "unop", MEM_(0x0B) | (30 << 16), + MEM_MASK, BASE, { ZA } }, /* pseudo */ { "ldq_u", MEM(0x0B), BASE, ARG_MEM }, { "ldwu", MEM(0x0C), BWX, ARG_MEM }, { "stw", MEM(0x0D), BWX, ARG_MEM }, @@ -1103,6 +1104,7 @@ const struct alpha_opcode alpha_opcodes[] = { { "ecb", MFC(0x18,0xE800), BASE, { ZA, PRB } }, /* ev56 una */ { "rs", MFC(0x18,0xF000), BASE, { RA } }, { "wh64", MFC(0x18,0xF800), BASE, { ZA, PRB } }, /* ev56 una */ + { "wh64en", MFC(0x18,0xFC00), BASE, { ZA, PRB } }, /* ev7 una */ { "hw_mfpr", OPR(0x19,0x00), EV4, { RA, RBA, EV4EXTHWINDEX } }, { "hw_mfpr", OP(0x19), OP_MASK, EV5, { RA, RBA, EV5HWINDEX } }, diff --git a/contrib/binutils/opcodes/arc-dis.c b/contrib/binutils/opcodes/arc-dis.c index 18325a9..d38e2fa 100644 --- a/contrib/binutils/opcodes/arc-dis.c +++ b/contrib/binutils/opcodes/arc-dis.c @@ -26,7 +26,6 @@ #include <string.h> #include "opintl.h" -#include <ctype.h> #include <stdarg.h> #include "arc-dis.h" #include "arc-ext.h" @@ -35,24 +34,24 @@ #define dbg (0) #endif -#define BIT(word,n) ((word) & (1 << n)) -#define BITS(word,s,e) (((word) << (31 - e)) >> (s + (31 - e))) -#define OPCODE(word) (BITS ((word), 27, 31)) -#define FIELDA(word) (BITS ((word), 21, 26)) -#define FIELDB(word) (BITS ((word), 15, 20)) -#define FIELDC(word) (BITS ((word), 9, 14)) +#define BIT(word,n) ((word) & (1 << n)) +#define BITS(word,s,e) (((word) << (31 - e)) >> (s + (31 - e))) +#define OPCODE(word) (BITS ((word), 27, 31)) +#define FIELDA(word) (BITS ((word), 21, 26)) +#define FIELDB(word) (BITS ((word), 15, 20)) +#define FIELDC(word) (BITS ((word), 9, 14)) /* FIELD D is signed in all of its uses, so we make sure argument is treated as signed for bit shifting purposes: */ -#define FIELDD(word) (BITS (((signed int)word), 0, 8)) - -#define PUT_NEXT_WORD_IN(a) \ - do \ - { \ - if (is_limm == 1 && !NEXT_WORD (1)) \ - mwerror (state, _("Illegal limm reference in last instruction!\n")); \ - a = state->words[1]; \ - } \ +#define FIELDD(word) (BITS (((signed int)word), 0, 8)) + +#define PUT_NEXT_WORD_IN(a) \ + do \ + { \ + if (is_limm == 1 && !NEXT_WORD (1)) \ + mwerror (state, _("Illegal limm reference in last instruction!\n")); \ + a = state->words[1]; \ + } \ while (0) #define CHECK_FLAG_COND_NULLIFY() \ @@ -98,7 +97,7 @@ #define CHECK_FIELD_A() \ do \ { \ - fieldA = FIELDA(state->words[0]); \ + fieldA = FIELDA (state->words[0]); \ if (fieldA > 60) \ { \ fieldAisReg = 0; \ @@ -136,20 +135,35 @@ (IS_REG (x) ? cb1"%r"ca1 : \ usesAuxReg ? cb"%a"ca : \ IS_SMALL (x) ? cb"%d"ca : cb"%h"ca)) -#define WRITE_FORMAT_RB() strcat (formatString, "]") +#define WRITE_FORMAT_RB() strcat (formatString, "]") #define WRITE_COMMENT(str) (state->comm[state->commNum++] = (str)) -#define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT ("nop"); +#define WRITE_NOP_COMMENT() if (!fieldAisReg && !flag) WRITE_COMMENT ("nop"); -#define NEXT_WORD(x) (offset += 4, state->words[x]) +#define NEXT_WORD(x) (offset += 4, state->words[x]) -#define add_target(x) (state->targets[state->tcnt++] = (x)) +#define add_target(x) (state->targets[state->tcnt++] = (x)) static char comment_prefix[] = "\t; "; +static const char *core_reg_name PARAMS ((struct arcDisState *, int)); +static const char *aux_reg_name PARAMS ((struct arcDisState *, int)); +static const char *cond_code_name PARAMS ((struct arcDisState *, int)); +static const char *instruction_name + PARAMS ((struct arcDisState *, int, int, int *)); +static void mwerror PARAMS ((struct arcDisState *, const char *)); +static const char *post_address PARAMS ((struct arcDisState *, int)); +static void write_comments_ + PARAMS ((struct arcDisState *, int, int, long int)); +static void write_instr_name_ + PARAMS ((struct arcDisState *, const char *, int, int, int, int, int, int)); +static int dsmOneArcInst PARAMS ((bfd_vma, struct arcDisState *)); +static const char *_coreRegName PARAMS ((void *, int)); +static int decodeInstr PARAMS ((bfd_vma, disassemble_info *)); + static const char * core_reg_name (state, val) struct arcDisState * state; - int val; + int val; { if (state->coreRegName) return (*state->coreRegName)(state->_this, val); @@ -159,7 +173,7 @@ core_reg_name (state, val) static const char * aux_reg_name (state, val) struct arcDisState * state; - int val; + int val; { if (state->auxRegName) return (*state->auxRegName)(state->_this, val); @@ -169,7 +183,7 @@ aux_reg_name (state, val) static const char * cond_code_name (state, val) struct arcDisState * state; - int val; + int val; { if (state->condCodeName) return (*state->condCodeName)(state->_this, val); @@ -181,7 +195,7 @@ instruction_name (state, op1, op2, flags) struct arcDisState * state; int op1; int op2; - int * flags; + int * flags; { if (state->instName) return (*state->instName)(state->_this, op1, op2, flags); @@ -191,7 +205,7 @@ instruction_name (state, op1, op2, flags) static void mwerror (state, msg) struct arcDisState * state; - const char * msg; + const char * msg; { if (state->err != 0) (*state->err)(state->_this, (msg)); @@ -200,7 +214,7 @@ mwerror (state, msg) static const char * post_address (state, addr) struct arcDisState * state; - int addr; + int addr; { static char id[3 * ARRAY_SIZE (state->addresses)]; int j, i = state->acnt; @@ -213,47 +227,49 @@ post_address (state, addr) id[j+0] = '@'; id[j+1] = '0'+i; id[j+2] = 0; - + return id + j; } return ""; } -static void -my_sprintf ( - struct arcDisState * state, - char * buf, - const char * format, - ...) +static void my_sprintf PARAMS ((struct arcDisState *, char *, const char *, + ...)); + +static void +my_sprintf VPARAMS ((struct arcDisState *state, char *buf, const char *format, + ...)) { - char *bp; + char *bp; const char *p; int size, leading_zero, regMap[2]; long auxNum; - va_list ap; - - va_start (ap, format); - - bp = buf; + + VA_OPEN (ap, format); + VA_FIXEDARG (ap, struct arcDisState *, state); + VA_FIXEDARG (ap, char *, buf); + VA_FIXEDARG (ap, const char *, format); + + bp = buf; *bp = 0; p = format; auxNum = -1; regMap[0] = 0; regMap[1] = 0; - - while (1) + + while (1) switch (*p++) { - case 0: - goto DOCOMM; /* (return) */ - default: - *bp++ = p[-1]; + case 0: + goto DOCOMM; /* (return) */ + default: + *bp++ = p[-1]; break; case '%': size = 0; leading_zero = 0; RETRY: ; - switch (*p++) + switch (*p++) { case '0': case '1': @@ -279,25 +295,25 @@ my_sprintf ( } #define inc_bp() bp = bp + strlen (bp) - case 'h': + case 'h': { unsigned u = va_arg (ap, int); /* Hex. We can change the format to 0x%08x in one place, here, if we wish. We add underscores for easy reading. */ - if (u > 65536) + if (u > 65536) sprintf (bp, "0x%x_%04x", u >> 16, u & 0xffff); - else + else sprintf (bp, "0x%x", u); inc_bp (); - } + } break; - case 'X': case 'x': + case 'X': case 'x': { int val = va_arg (ap, int); - if (size != 0) + if (size != 0) if (leading_zero) sprintf (bp, "%0*x", size, val); else @@ -307,10 +323,10 @@ my_sprintf ( inc_bp (); } break; - case 'd': + case 'd': { int val = va_arg (ap, int); - + if (size != 0) sprintf (bp, "%*d", size, val); else @@ -318,15 +334,15 @@ my_sprintf ( inc_bp (); } break; - case 'r': + case 'r': { /* Register. */ int val = va_arg (ap, int); - + #define REG2NAME(num, name) case num: sprintf (bp, ""name); \ regMap[(num < 32) ? 0 : 1] |= 1 << (num - ((num < 32) ? 0 : 32)); break; - - switch (val) + + switch (val) { REG2NAME (26, "gp"); REG2NAME (27, "fp"); @@ -349,15 +365,15 @@ my_sprintf ( } inc_bp (); } break; - - case 'a': + + case 'a': { /* Aux Register. */ int val = va_arg (ap, int); #define AUXREG2NAME(num, name) case num: sprintf (bp,name); break; - switch (val) + switch (val) { AUXREG2NAME (0x0, "status"); AUXREG2NAME (0x1, "semaphore"); @@ -380,14 +396,14 @@ my_sprintf ( inc_bp (); } break; - - case 's': + + case 's': { sprintf (bp, "%s", va_arg (ap, char *)); inc_bp (); } break; - + default: fprintf (stderr, "?? format %c\n", p[-1]); break; @@ -395,33 +411,35 @@ my_sprintf ( } DOCOMM: *bp = 0; + VA_CLOSE (ap); } -static void +static void write_comments_(state, shimm, is_limm, limm_value) struct arcDisState * state; int shimm; int is_limm; long limm_value; { - if (state->commentBuffer != 0) + if (state->commentBuffer != 0) { int i; - if (is_limm) + if (is_limm) { const char *name = post_address (state, limm_value + shimm); if (*name != 0) WRITE_COMMENT (name); } - for (i = 0; i < state->commNum; i++) + for (i = 0; i < state->commNum; i++) { if (i == 0) strcpy (state->commentBuffer, comment_prefix); else - strcat (state->commentBuffer, ", "); - strncat (state->commentBuffer, state->comm[i], sizeof (state->commentBuffer)); + strcat (state->commentBuffer, ", "); + strncat (state->commentBuffer, state->comm[i], + sizeof (state->commentBuffer)); } } } @@ -431,11 +449,11 @@ write_comments_(state, shimm, is_limm, limm_value) static const char *condName[] = { /* 0..15. */ - "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" , + "" , "z" , "nz" , "p" , "n" , "c" , "nc" , "v" , "nv" , "gt" , "ge" , "lt" , "le" , "hi" , "ls" , "pnz" }; -static void +static void write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend, addrWriteBack, directMem) struct arcDisState * state; const char * instrName; @@ -448,7 +466,7 @@ write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend { strcpy (state->instrBuffer, instrName); - if (cond > 0) + if (cond > 0) { const char *cc = 0; @@ -469,7 +487,7 @@ write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend if (flag) strcat (state->instrBuffer, ".f"); - switch (state->nullifyMode) + switch (state->nullifyMode) { case BR_exec_always: strcat (state->instrBuffer, ".d"); @@ -498,16 +516,16 @@ write_instr_name_(state, instrName, cond, condCodeIsPartOfName, flag, signExtend } \ while (0) -enum { - op_LD0 = 0, op_LD1 = 1, op_ST = 2, op_3 = 3, +enum { + op_LD0 = 0, op_LD1 = 1, op_ST = 2, op_3 = 3, op_BC = 4, op_BLC = 5, op_LPC = 6, op_JC = 7, - op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11, + op_ADD = 8, op_ADC = 9, op_SUB = 10, op_SBC = 11, op_AND = 12, op_OR = 13, op_BIC = 14, op_XOR = 15 }; extern disassemble_info tm_print_insn_info; -static int +static int dsmOneArcInst (addr, state) bfd_vma addr; struct arcDisState * state; @@ -536,22 +554,22 @@ dsmOneArcInst (addr, state) int flags; int ignoreFirstOpd; char formatString[60]; - + state->instructionLen = 4; state->nullifyMode = BR_exec_when_no_jump; state->opWidth = 12; state->isBranch = 0; - + state->_mem_load = 0; state->_ea_present = 0; state->_load_len = 0; state->ea_reg1 = no_reg; state->ea_reg2 = no_reg; state->_offset = 0; - + if (! NEXT_WORD (0)) return 0; - + state->_opcode = OPCODE (state->words[0]); instrName = 0; decodingClass = 0; /* default! */ @@ -566,10 +584,10 @@ dsmOneArcInst (addr, state) if (state->commentBuffer) state->commentBuffer[0] = '\0'; - switch (state->_opcode) + switch (state->_opcode) { - case op_LD0: - switch (BITS (state->words[0],1,2)) + case op_LD0: + switch (BITS (state->words[0],1,2)) { case 0: instrName = "ld"; @@ -584,22 +602,22 @@ dsmOneArcInst (addr, state) state->_load_len = 2; break; default: - instrName = "??? (0[3])"; + instrName = "??? (0[3])"; state->flow = invalid_instr; break; } - decodingClass = 5; + decodingClass = 5; break; - - case op_LD1: - if (BIT (state->words[0],13)) + + case op_LD1: + if (BIT (state->words[0],13)) { - instrName = "lr"; + instrName = "lr"; decodingClass = 10; } - else + else { - switch (BITS (state->words[0],10,11)) + switch (BITS (state->words[0],10,11)) { case 0: instrName = "ld"; @@ -614,23 +632,23 @@ dsmOneArcInst (addr, state) state->_load_len = 2; break; default: - instrName = "??? (1[3])"; + instrName = "??? (1[3])"; state->flow = invalid_instr; break; } decodingClass = 6; } break; - + case op_ST: - if (BIT (state->words[0],25)) + if (BIT (state->words[0],25)) { instrName = "sr"; decodingClass = 8; } - else + else { - switch (BITS (state->words[0],22,23)) + switch (BITS (state->words[0],22,23)) { case 0: instrName = "st"; @@ -642,20 +660,20 @@ dsmOneArcInst (addr, state) instrName = "stw"; break; default: - instrName = "??? (2[3])"; + instrName = "??? (2[3])"; state->flow = invalid_instr; break; } decodingClass = 7; } break; - + case op_3: decodingClass = 1; /* default for opcode 3... */ - switch (FIELDC (state->words[0])) + switch (FIELDC (state->words[0])) { case 0: - instrName = "flag"; + instrName = "flag"; decodingClass = 2; break; case 1: @@ -682,10 +700,10 @@ dsmOneArcInst (addr, state) case 8: instrName = "extw"; break; - case 0x3f: + case 0x3f: { decodingClass = 9; - switch( FIELDD (state->words[0]) ) + switch( FIELDD (state->words[0]) ) { case 0: instrName = "brk"; @@ -703,14 +721,14 @@ dsmOneArcInst (addr, state) } } break; - + /* ARC Extension Library Instructions NOTE: We assume that extension codes are these instrs. */ default: instrName = instruction_name (state, state->_opcode, FIELDC (state->words[0]), - & flags); + &flags); if (!instrName) { instrName = "???"; @@ -723,24 +741,24 @@ dsmOneArcInst (addr, state) break; case op_BC: - instrName = "b"; + instrName = "b"; case op_BLC: if (!instrName) - instrName = "bl"; + instrName = "bl"; case op_LPC: if (!instrName) - instrName = "lp"; + instrName = "lp"; case op_JC: if (!instrName) { - if (BITS (state->words[0],9,9)) + if (BITS (state->words[0],9,9)) { - instrName = "jl"; + instrName = "jl"; is_linked = 1; } - else + else { - instrName = "j"; + instrName = "j"; is_linked = 0; } } @@ -748,14 +766,14 @@ dsmOneArcInst (addr, state) decodingClass = ((state->_opcode == op_JC) ? 4 : 3); state->isBranch = 1; break; - + case op_ADD: case op_ADC: case op_AND: repeatsOp = (FIELDC (state->words[0]) == FIELDB (state->words[0])); decodingClass = 0; - switch (state->_opcode) + switch (state->_opcode) { case op_ADD: instrName = (repeatsOp ? "asl" : "add"); @@ -768,7 +786,7 @@ dsmOneArcInst (addr, state) break; } break; - + case op_SUB: instrName = "sub"; break; case op_SBC: instrName = "sbc"; @@ -785,10 +803,10 @@ dsmOneArcInst (addr, state) instrName = "nop"; decodingClass = 9; } - else + else instrName = "xor"; break; - + default: instrName = instruction_name (state,state->_opcode,0,&flags); /* if (instrName) printf("FLAGS=0x%x\n", flags); */ @@ -801,14 +819,14 @@ dsmOneArcInst (addr, state) ignoreFirstOpd = 1; break; } - + fieldAisReg = fieldBisReg = fieldCisReg = 1; /* Assume regs for now. */ flag = cond = is_shimm = is_limm = 0; state->nullifyMode = BR_exec_when_no_jump; /* 0 */ signExtend = addrWriteBack = directMem = 0; usesAuxReg = 0; - - switch (decodingClass) + + switch (decodingClass) { case 0: CHECK_FIELD_A (); @@ -816,83 +834,87 @@ dsmOneArcInst (addr, state) if (!repeatsOp) CHECK_FIELD_C (); CHECK_FLAG_COND_NULLIFY (); - + write_instr_name (); - if (!ignoreFirstOpd) + if (!ignoreFirstOpd) { WRITE_FORMAT_x (A); WRITE_FORMAT_COMMA_x (B); if (!repeatsOp) WRITE_FORMAT_COMMA_x (C); WRITE_NOP_COMMENT (); - my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); + my_sprintf (state, state->operandBuffer, formatString, + fieldA, fieldB, fieldC); } - else + else { WRITE_FORMAT_x (B); if (!repeatsOp) WRITE_FORMAT_COMMA_x (C); - my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldC); + my_sprintf (state, state->operandBuffer, formatString, + fieldB, fieldC); } write_comments (); break; - + case 1: CHECK_FIELD_A (); CHECK_FIELD_B (); CHECK_FLAG_COND_NULLIFY (); - + write_instr_name (); - if (!ignoreFirstOpd) + if (!ignoreFirstOpd) { WRITE_FORMAT_x (A); WRITE_FORMAT_COMMA_x (B); WRITE_NOP_COMMENT (); - my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB); + my_sprintf (state, state->operandBuffer, formatString, + fieldA, fieldB); } - else + else { WRITE_FORMAT_x (B); - my_sprintf (state, state->operandBuffer, formatString, fieldB); + my_sprintf (state, state->operandBuffer, formatString, fieldB); } write_comments (); break; - + case 2: CHECK_FIELD_B (); CHECK_FLAG_COND_NULLIFY (); flag = 0; /* this is the FLAG instruction -- it's redundant */ - + write_instr_name (); WRITE_FORMAT_x (B); my_sprintf (state, state->operandBuffer, formatString, fieldB); write_comments (); break; - + case 3: fieldA = BITS (state->words[0],7,26) << 2; fieldA = (fieldA << 10) >> 10; /* make it signed */ fieldA += addr + 4; CHECK_FLAG_COND_NULLIFY (); flag = 0; - + write_instr_name (); /* This address could be a label we know. Convert it. */ - if (state->_opcode != op_LPC /* LP */) + if (state->_opcode != op_LPC /* LP */) { - add_target (fieldA); /* For debugger. */ - state->flow = state->_opcode == op_BLC /* BL */ - ? direct_call - : direct_jump; - /* indirect calls are achieved by "lr blink,[status]; - lr dest<- func addr; j [dest]" */ - } - + add_target (fieldA); /* For debugger. */ + state->flow = state->_opcode == op_BLC /* BL */ + ? direct_call + : direct_jump; + /* indirect calls are achieved by "lr blink,[status]; + lr dest<- func addr; j [dest]" */ + } + strcat (formatString, "%s"); /* address/label name */ - my_sprintf (state, state->operandBuffer, formatString, post_address (state, fieldA)); + my_sprintf (state, state->operandBuffer, formatString, + post_address (state, fieldA)); write_comments (); break; - + case 4: /* For op_JC -- jump to address specified. Also covers jump and link--bit 9 of the instr. word @@ -900,8 +922,8 @@ dsmOneArcInst (addr, state) fieldA = 0; CHECK_FIELD_B (); CHECK_FLAG_COND_NULLIFY (); - - if (!fieldBisReg) + + if (!fieldBisReg) { fieldAisReg = 0; fieldA = (fieldB >> 25) & 0x7F; /* flags */ @@ -913,7 +935,7 @@ dsmOneArcInst (addr, state) if (is_linked && state->nullifyMode == BR_exec_when_jump) state->nullifyMode = BR_exec_when_no_jump; } - else + else { state->flow = is_linked ? indirect_call : indirect_jump; /* We should also treat this as indirect call if NOT linked @@ -922,11 +944,11 @@ dsmOneArcInst (addr, state) * For now we can't detect such. */ state->register_for_indirect_jump = fieldB; } - + write_instr_name (); - strcat (formatString, + strcat (formatString, IS_REG (B) ? "[%r]" : "%s"); /* address/label name */ - if (fieldA != 0) + if (fieldA != 0) { fieldAisReg = 0; WRITE_FORMAT_COMMA_x (A); @@ -934,11 +956,11 @@ dsmOneArcInst (addr, state) if (IS_REG (B)) my_sprintf (state, state->operandBuffer, formatString, fieldB, fieldA); else - my_sprintf (state, state->operandBuffer, formatString, + my_sprintf (state, state->operandBuffer, formatString, post_address (state, fieldB), fieldA); write_comments (); break; - + case 5: /* LD instruction. B and C can be regs, or one (both?) can be limm. */ @@ -959,29 +981,30 @@ dsmOneArcInst (addr, state) else state->_offset += fieldC; state->_mem_load = 1; - + directMem = BIT (state->words[0],5); addrWriteBack = BIT (state->words[0],3); signExtend = BIT (state->words[0],0); - + write_instr_name (); WRITE_FORMAT_x_COMMA_LB(A); if (fieldBisReg || fieldB != 0) WRITE_FORMAT_x_COMMA (B); else fieldB = fieldC; - + WRITE_FORMAT_x_RB (C); - my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); + my_sprintf (state, state->operandBuffer, formatString, + fieldA, fieldB, fieldC); write_comments (); break; - + case 6: /* LD instruction. */ CHECK_FIELD_B (); CHECK_FIELD_A (); fieldC = FIELDD (state->words[0]); - + if (dbg) printf ("6:b reg %d %d c 0x%x \n", fieldBisReg, fieldB, fieldC); @@ -994,22 +1017,22 @@ dsmOneArcInst (addr, state) Say ea is not present, so only one of us will do the name lookup. */ else state->_offset += fieldB, state->_ea_present = 0; - + directMem = BIT (state->words[0],14); addrWriteBack = BIT (state->words[0],12); signExtend = BIT (state->words[0],9); - + write_instr_name (); WRITE_FORMAT_x_COMMA_LB (A); - if (!fieldBisReg) + if (!fieldBisReg) { fieldB = state->_offset; WRITE_FORMAT_x_RB (B); } - else + else { WRITE_FORMAT_x (B); - if (fieldC != 0 && !BIT (state->words[0],13)) + if (fieldC != 0 && !BIT (state->words[0],13)) { fieldCisReg = 0; WRITE_FORMAT_COMMA_x_RB (C); @@ -1017,44 +1040,45 @@ dsmOneArcInst (addr, state) else WRITE_FORMAT_RB (); } - my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB, fieldC); + my_sprintf (state, state->operandBuffer, formatString, + fieldA, fieldB, fieldC); write_comments (); break; - + case 7: /* ST instruction. */ CHECK_FIELD_B(); CHECK_FIELD_C(); fieldA = FIELDD(state->words[0]); /* shimm */ - + /* [B,A offset] */ if (dbg) printf("7:b reg %d %x off %x\n", - fieldBisReg,fieldB,fieldA); + fieldBisReg,fieldB,fieldA); state->_ea_present = 1; state->_offset = fieldA; if (fieldBisReg) state->ea_reg1 = fieldB; - /* field B is either a shimm (same as fieldA) or limm (different!) + /* field B is either a shimm (same as fieldA) or limm (different!) Say ea is not present, so only one of us will do the name lookup. (for is_limm we do the name translation here). */ - else + else state->_offset += fieldB, state->_ea_present = 0; - + directMem = BIT(state->words[0],26); addrWriteBack = BIT(state->words[0],24); - + write_instr_name(); WRITE_FORMAT_x_COMMA_LB(C); - - if (!fieldBisReg) + + if (!fieldBisReg) { fieldB = state->_offset; WRITE_FORMAT_x_RB(B); } - else + else { WRITE_FORMAT_x(B); - if (fieldBisReg && fieldA != 0) + if (fieldBisReg && fieldA != 0) { fieldAisReg = 0; WRITE_FORMAT_COMMA_x_RB(A); @@ -1062,14 +1086,15 @@ dsmOneArcInst (addr, state) else WRITE_FORMAT_RB(); } - my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB, fieldA); + my_sprintf (state, state->operandBuffer, formatString, + fieldC, fieldB, fieldA); write_comments2(fieldA); break; case 8: /* SR instruction */ CHECK_FIELD_B(); CHECK_FIELD_C(); - + write_instr_name(); WRITE_FORMAT_x_COMMA_LB(C); /* Try to print B as an aux reg if it is not a core reg. */ @@ -1079,17 +1104,17 @@ dsmOneArcInst (addr, state) my_sprintf (state, state->operandBuffer, formatString, fieldC, fieldB); write_comments(); break; - + case 9: write_instr_name(); state->operandBuffer[0] = '\0'; break; - + case 10: /* LR instruction */ CHECK_FIELD_A(); CHECK_FIELD_B(); - + write_instr_name(); WRITE_FORMAT_x_COMMA_LB(A); /* Try to print B as an aux reg if it is not a core reg. */ @@ -1099,18 +1124,18 @@ dsmOneArcInst (addr, state) my_sprintf (state, state->operandBuffer, formatString, fieldA, fieldB); write_comments(); break; - + case 11: CHECK_COND(); write_instr_name(); state->operandBuffer[0] = '\0'; break; - + default: mwerror (state, "Bad decoding class in ARC disassembler"); break; } - + state->_cond = cond; return state->instructionLen = offset; } @@ -1129,7 +1154,7 @@ _coreRegName(arg, regval) static const char * _auxRegName(void *_this ATTRIBUTE_UNUSED, int regval) { - return arcExtMap_auxRegName(regval); + return arcExtMap_auxRegName(regval); } @@ -1137,14 +1162,14 @@ _auxRegName(void *_this ATTRIBUTE_UNUSED, int regval) static const char * _condCodeName(void *_this ATTRIBUTE_UNUSED, int regval) { - return arcExtMap_condCodeName(regval); + return arcExtMap_condCodeName(regval); } /* Returns the name the user specified extension instruction. */ static const char * _instName (void *_this ATTRIBUTE_UNUSED, int majop, int minop, int *flags) { - return arcExtMap_instName(majop, minop, flags); + return arcExtMap_instName(majop, minop, flags); } /* Decode an instruction returning the size of the instruction @@ -1158,11 +1183,11 @@ decodeInstr (address, info) bfd_byte buffer[4]; struct arcDisState s; /* ARC Disassembler state */ void *stream = info->stream; /* output stream */ - fprintf_ftype func = info->fprintf_func; + fprintf_ftype func = info->fprintf_func; int bytes; - + memset (&s, 0, sizeof(struct arcDisState)); - + /* read first instruction */ status = (*info->read_memory_func) (address, buffer, 4, info); if (status != 0) @@ -1195,9 +1220,9 @@ decodeInstr (address, info) /* display the disassembly instruction */ (*func) (stream, "%08x ", s.words[0]); (*func) (stream, " "); - + (*func) (stream, "%-10s ", s.instrBuffer); - + if (__TRANSLATION_REQUIRED(s)) { bfd_vma addr = s.addresses[s.operandBuffer[1] - '0']; diff --git a/contrib/binutils/opcodes/arc-ext.c b/contrib/binutils/opcodes/arc-ext.c index 1a53da9..fd43d29 100644 --- a/contrib/binutils/opcodes/arc-ext.c +++ b/contrib/binutils/opcodes/arc-ext.c @@ -1,4 +1,4 @@ -/* ARC target-dependent stuff. Extension structure access functions +/* ARC target-dependent stuff. Extension structure access functions Copyright 1995, 1997, 2000, 2001 Free Software Foundation, Inc. This file is part of GDB. @@ -17,6 +17,7 @@ along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#include "sysdep.h" #include <stdlib.h> #include <stdio.h> #include "bfd.h" @@ -29,9 +30,9 @@ static struct arcExtMap arc_extension_map; /* Get the name of an extension instruction. */ const char * -arcExtMap_instName(int opcode, int minor, int *flags) +arcExtMap_instName(int opcode, int minor, int *flags) { - if (opcode == 3) + if (opcode == 3) { /* FIXME: ??? need to also check 0/1/2 in bit0 for (3f) brk/sleep/swi */ if (minor < 0x09 || minor == 0x3f) @@ -53,7 +54,7 @@ arcExtMap_instName(int opcode, int minor, int *flags) /* Get the name of an extension core register. */ const char * -arcExtMap_coreRegName(int value) +arcExtMap_coreRegName(int value) { if (value < 32) return 0; @@ -63,7 +64,7 @@ arcExtMap_coreRegName(int value) /* Get the name of an extension condition code. */ const char * -arcExtMap_condCodeName(int value) +arcExtMap_condCodeName(int value) { if (value < 16) return 0; @@ -88,7 +89,7 @@ arcExtMap_auxRegName(long address) /* Recursively free auxilliary register strcture pointers until the list is empty. */ -static void +static void clean_aux_registers(struct ExtAuxRegister *r) { if (r -> next) @@ -98,14 +99,14 @@ clean_aux_registers(struct ExtAuxRegister *r) free(r -> next); r ->next = NULL; } - else + else free(r -> name); } - + /* Free memory that has been allocated for the extensions. */ -static void -cleanup_ext_map(void) +static void +cleanup_ext_map(void) { struct ExtAuxRegister *r; struct ExtInstruction *insn; @@ -113,45 +114,45 @@ cleanup_ext_map(void) /* clean aux reg structure */ r = arc_extension_map.auxRegisters; - if (r) + if (r) { (clean_aux_registers(r)); free(r); } - + /* clean instructions */ - for (i = 0; i < NUM_EXT_INST; i++) + for (i = 0; i < NUM_EXT_INST; i++) { insn = arc_extension_map.instructions[i]; if (insn) free(insn->name); } - + /* clean core reg struct */ - for (i = 0; i < NUM_EXT_CORE; i++) + for (i = 0; i < NUM_EXT_CORE; i++) { if (arc_extension_map.coreRegisters[i]) free(arc_extension_map.coreRegisters[i]); } - + for (i = 0; i < NUM_EXT_COND; i++) { if (arc_extension_map.condCodes[i]) free(arc_extension_map.condCodes[i]); } - - memset(&arc_extension_map, 0, sizeof(struct arcExtMap)); + + memset(&arc_extension_map, 0, sizeof(struct arcExtMap)); } -int -arcExtMap_add(void *base, unsigned long length) +int +arcExtMap_add(void *base, unsigned long length) { unsigned char *block = base; unsigned char *p = block; - + /* Clean up and reset everything if needed. */ cleanup_ext_map(); - while (p && p < (block + length)) + while (p && p < (block + length)) { /* p[0] == length of record p[1] == type of record @@ -170,7 +171,7 @@ arcExtMap_add(void *base, unsigned long length) if (p[0] == 0) return -1; - + switch (p[1]) { case EXT_INSTRUCTION: @@ -178,9 +179,9 @@ arcExtMap_add(void *base, unsigned long length) char opcode = p[2]; char minor = p[3]; char * insn_name = (char *) xmalloc(( (int)*p-5) * sizeof(char)); - struct ExtInstruction * insn = + struct ExtInstruction * insn = (struct ExtInstruction *) xmalloc(sizeof(struct ExtInstruction)); - + if (opcode==3) opcode = 0x1f - 0x10 + minor - 0x09 + 1; else @@ -191,8 +192,8 @@ arcExtMap_add(void *base, unsigned long length) arc_extension_map.instructions[(int) opcode] = insn; } break; - - case EXT_CORE_REGISTER: + + case EXT_CORE_REGISTER: { char * core_name = (char *) xmalloc(((int)*p-3) * sizeof(char)); @@ -200,19 +201,19 @@ arcExtMap_add(void *base, unsigned long length) arc_extension_map.coreRegisters[p[2]-32] = core_name; } break; - - case EXT_COND_CODE: + + case EXT_COND_CODE: { char * cc_name = (char *) xmalloc( ((int)*p-3) * sizeof(char)); strcpy(cc_name, (p+3)); arc_extension_map.condCodes[p[2]-16] = cc_name; - } + } break; - - case EXT_AUX_REGISTER: + + case EXT_AUX_REGISTER: { /* trickier -- need to store linked list to these */ - struct ExtAuxRegister *newAuxRegister = + struct ExtAuxRegister *newAuxRegister = (struct ExtAuxRegister *)malloc(sizeof(struct ExtAuxRegister)); char * aux_name = (char *) xmalloc ( ((int)*p-6) * sizeof(char)); @@ -223,14 +224,14 @@ arcExtMap_add(void *base, unsigned long length) arc_extension_map.auxRegisters = newAuxRegister; } break; - + default: return -1; - + } p += p[0]; /* move to next record */ } - + return 0; } diff --git a/contrib/binutils/opcodes/arc-opc.c b/contrib/binutils/opcodes/arc-opc.c index c67cd88..b7afb86 100644 --- a/contrib/binutils/opcodes/arc-opc.c +++ b/contrib/binutils/opcodes/arc-opc.c @@ -17,6 +17,7 @@ along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +#include "sysdep.h" #include <stdio.h> #include "ansidecl.h" #include "opcode/arc.h" @@ -1149,14 +1150,6 @@ insert_st_syntax (insn, operand, mods, reg, value, errmsg) { limm += arc_limm_fixup_adjust(insn); } - if (ST_SYNTAX(OP_LIMM,OP_SHIMM,OP_SHIMM) && (shimm * 2 == limm)) - { - insn &= ~C(-1); - limm_p = 0; - limm = 0; - insn |= C(ARC_REG_SHIMM); - ls_operand[LS_VALUE] = OP_SHIMM; - } if (!(ST_SYNTAX(OP_REG,OP_REG,OP_NONE) || ST_SYNTAX(OP_REG,OP_LIMM,OP_NONE) || ST_SYNTAX(OP_REG,OP_REG,OP_SHIMM) diff --git a/contrib/binutils/opcodes/arm-dis.c b/contrib/binutils/opcodes/arm-dis.c index eaebe34..7e9b330 100644 --- a/contrib/binutils/opcodes/arm-dis.c +++ b/contrib/binutils/opcodes/arm-dis.c @@ -390,13 +390,6 @@ print_insn_arm (pc, info, given) func (stream, "t"); break; - case 'h': - if ((given & 0x00000020) == 0x00000020) - func (stream, "h"); - else - func (stream, "b"); - break; - case 'A': func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); if ((given & 0x01000000) != 0) @@ -445,6 +438,25 @@ print_insn_arm (pc, info, given) } break; + case 'I': + /* Print a Cirrus/DSP shift immediate. */ + /* Immediates are 7bit signed ints with bits 0..3 in + bits 0..3 of opcode and bits 4..6 in bits 5..7 + of opcode. */ + { + int imm; + + imm = (given & 0xf) | ((given & 0xe0) >> 1); + + /* Is ``imm'' a negative number? */ + if (imm & 0x40) + imm |= (-1 << 7); + + func (stream, "%d", imm); + } + + break; + case 'C': func (stream, "_"); if (given & 0x80000) @@ -611,7 +623,85 @@ print_insn_arm (pc, info, given) abort (); } break; - + + case 'y': + case 'z': + { + int single = *c == 'y'; + int regno; + + switch (bitstart) + { + case 4: /* Sm pair */ + func (stream, "{"); + /* Fall through. */ + case 0: /* Sm, Dm */ + regno = given & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 5) & 1; + } + break; + + case 1: /* Sd, Dd */ + regno = (given >> 12) & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 22) & 1; + } + break; + + case 2: /* Sn, Dn */ + regno = (given >> 16) & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 7) & 1; + } + break; + + case 3: /* List */ + func (stream, "{"); + regno = (given >> 12) & 0x0000000f; + if (single) + { + regno <<= 1; + regno += (given >> 22) & 1; + } + break; + + + default: + abort (); + } + + func (stream, "%c%d", single ? 's' : 'd', regno); + + if (bitstart == 3) + { + int count = given & 0xff; + + if (single == 0) + count >>= 1; + + if (--count) + { + func (stream, "-%c%d", + single ? 's' : 'd', + regno + count); + } + + func (stream, "}"); + } + else if (bitstart == 4) + func (stream, ", %c%d}", single ? 's' : 'd', + regno + 1); + + break; + } + case '`': c++; if ((given & (1 << bitstart)) == 0) @@ -669,15 +759,32 @@ print_insn_thumb (pc, info, given) /* Special processing for Thumb 2 instruction BL sequence: */ if (!*c) /* Check for empty (not NULL) assembler string. */ { + long offset; + info->bytes_per_chunk = 4; info->bytes_per_line = 4; + + offset = BDISP23 (given); if ((given & 0x10000000) == 0) - func (stream, "blx\t"); + { + func (stream, "blx\t"); + + /* The spec says that bit 1 of the branch's destination + address comes from bit 1 of the instruction's + address and not from the offset in the instruction. */ + if (offset & 0x1) + { + /* func (stream, "*malformed!* "); */ + offset &= ~ 0x1; + } + + offset |= ((pc & 0x2) >> 1); + } else - func (stream, "bl\t"); - - info->print_address_func (BDISP23 (given) * 2 + pc + 4, info); + func (stream, "bl\t"); + + info->print_address_func (offset * 2 + pc + 4, info); return 4; } else @@ -1088,7 +1195,7 @@ the -M switch:\n")); for (i = NUM_ARM_REGNAMES; i--;) fprintf (stream, " reg-names-%s %*c%s\n", regnames[i].name, - 14 - strlen (regnames[i].name), ' ', + (int)(14 - strlen (regnames[i].name)), ' ', regnames[i].description); fprintf (stream, " force-thumb Assume all insns are Thumb insns\n"); diff --git a/contrib/binutils/opcodes/arm-opc.h b/contrib/binutils/opcodes/arm-opc.h index 36b1809..85f611d 100644 --- a/contrib/binutils/opcodes/arm-opc.h +++ b/contrib/binutils/opcodes/arm-opc.h @@ -38,6 +38,10 @@ struct thumb_opcode %<bitfield>r print as an ARM register %<bitfield>f print a floating point constant if >7 else a floating point register + %<code>y print a single precision VFP reg. + Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair + %<code>z print a double precision VFP reg + Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list %c print condition code (always bits 28-31) %P print floating point precision in arithmetic insn %Q print floating point precision in ldf/stf insn @@ -47,7 +51,6 @@ struct thumb_opcode %<bitnum>?ab print a if bit is one else print b %p print 'p' iff bits 12-15 are 15 %t print 't' iff bit 21 set and bit 24 clear - %h print 'h' iff bit 5 set, else print 'b' %o print operand2 (immediate or register + shift) %a print address for ldr/str instruction %s print address for ldr/str halfword/signextend instruction @@ -66,6 +69,7 @@ Thumb specific format options: %N print Thumb register mask (with LR) %O print Thumb register mask (with PC) %T print Thumb condition code (always bits 8-11) + %I print cirrus signed shift immediate: bits 0..3|4..6 %<bitfield>B print Thumb branch destination (signed displacement) %<bitfield>W print (bitfield * 4) as a decimal %<bitfield>H print (bitfield * 2) as a decimal @@ -86,6 +90,9 @@ static struct arm_opcode arm_opcodes[] = {0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, {0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, + /* V5J instruction. */ + {0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"}, + /* XScale instructions. */ {0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"}, {0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"}, @@ -138,8 +145,8 @@ static struct arm_opcode arm_opcodes[] = {0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, /* ARM Instructions. */ - {0x00000090, 0x0e100090, "str%c%6's%h\t%12-15r, %s"}, - {0x00100090, 0x0e100090, "ldr%c%6's%h\t%12-15r, %s"}, + {0x00000090, 0x0e100090, "str%c%6's%5?hb\t%12-15r, %s"}, + {0x00100090, 0x0e100090, "ldr%c%6's%5?hb\t%12-15r, %s"}, {0x00000000, 0x0de00000, "and%c%20's\t%12-15r, %16-19r, %o"}, {0x00200000, 0x0de00000, "eor%c%20's\t%12-15r, %16-19r, %o"}, {0x00400000, 0x0de00000, "sub%c%20's\t%12-15r, %16-19r, %o"}, @@ -168,7 +175,7 @@ static struct arm_opcode arm_opcodes[] = {0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, {0x0f000000, 0x0f000000, "swi%c\t%0-23x"}, - /* Floating point coprocessor instructions */ + /* Floating point coprocessor (FPA) instructions */ {0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, {0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, {0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, @@ -213,6 +220,167 @@ static struct arm_opcode arm_opcodes[] = {0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, {0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, + /* Floating point coprocessor (VFP) instructions */ + {0x0eb00bc0, 0x0fff0ff0, "fabsd%c\t%1z, %0z"}, + {0x0eb00ac0, 0x0fbf0fd0, "fabss%c\t%1y, %0y"}, + {0x0e300b00, 0x0ff00ff0, "faddd%c\t%1z, %2z, %0z"}, + {0x0e300a00, 0x0fb00f50, "fadds%c\t%1y, %2y, %1y"}, + {0x0eb40b40, 0x0fff0f70, "fcmp%7'ed%c\t%1z, %0z"}, + {0x0eb40a40, 0x0fbf0f50, "fcmp%7'es%c\t%1y, %0y"}, + {0x0eb50b40, 0x0fff0f70, "fcmp%7'ezd%c\t%1z"}, + {0x0eb50a40, 0x0fbf0f70, "fcmp%7'ezs%c\t%1y"}, + {0x0eb00b40, 0x0fff0ff0, "fcpyd%c\t%1z, %0z"}, + {0x0eb00a40, 0x0fbf0fd0, "fcpys%c\t%1y, %0y"}, + {0x0eb70ac0, 0x0fff0fd0, "fcvtds%c\t%1z, %0y"}, + {0x0eb70bc0, 0x0fbf0ff0, "fcvtsd%c\t%1y, %0z"}, + {0x0e800b00, 0x0ff00ff0, "fdivd%c\t%1z, %2z, %0z"}, + {0x0e800a00, 0x0fb00f50, "fdivs%c\t%1y, %2y, %0y"}, + {0x0d100b00, 0x0f700f00, "fldd%c\t%1z, %A"}, + {0x0c900b00, 0x0fd00f00, "fldmia%0?xd%c\t%16-19r%21'!, %3z"}, + {0x0d300b00, 0x0ff00f00, "fldmdb%0?xd%c\t%16-19r!, %3z"}, + {0x0d100a00, 0x0f300f00, "flds%c\t%1y, %A"}, + {0x0c900a00, 0x0f900f00, "fldmias%c\t%16-19r%21'!, %3y"}, + {0x0d300a00, 0x0fb00f00, "fldmdbs%c\t%16-19r!, %3y"}, + {0x0e000b00, 0x0ff00ff0, "fmacd%c\t%1z, %2z, %0z"}, + {0x0e000a00, 0x0fb00f50, "fmacs%c\t%1y, %2y, %0y"}, + {0x0e200b10, 0x0ff00fff, "fmdhr%c\t%2z, %12-15r"}, + {0x0e000b10, 0x0ff00fff, "fmdlr%c\t%2z, %12-15r"}, + {0x0c400b10, 0x0ff00ff0, "fmdrr%c\t%0z, %12-15r, %16-19r"}, + {0x0e300b10, 0x0ff00fff, "fmrdh%c\t%12-15r, %2z"}, + {0x0e100b10, 0x0ff00fff, "fmrdl%c\t%12-15r, %2z"}, + {0x0c500b10, 0x0ff00ff0, "fmrrd%c\t%12-15r, %16-19r, %0z"}, + {0x0c500a10, 0x0ff00fd0, "fmrrs%c\t%12-15r, %16-19r, %4y"}, + {0x0e100a10, 0x0ff00f7f, "fmrs%c\t%12-15r, %2y"}, + {0x0ef1fa10, 0x0fffffff, "fmstat%c"}, + {0x0ef00a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpsid"}, + {0x0ef10a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpscr"}, + {0x0ef80a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpexc"}, + {0x0ef90a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst\t@ Impl def"}, + {0x0efa0a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst2\t@ Impl def"}, + {0x0ef00a10, 0x0ff00fff, "fmrx%c\t%12-15r, <impl def 0x%16-19x>"}, + {0x0e100b00, 0x0ff00ff0, "fmscd%c\t%1z, %2z, %0z"}, + {0x0e100a00, 0x0fb00f50, "fmscs%c\t%1y, %2y, %0y"}, + {0x0e000a10, 0x0ff00f7f, "fmsr%c\t%2y, %12-15r"}, + {0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%12-15r, %16-19r, %4y"}, + {0x0e200b00, 0x0ff00ff0, "fmuld%c\t%1z, %2z, %0z"}, + {0x0e200a00, 0x0fb00f50, "fmuls%c\t%1y, %2y, %0y"}, + {0x0ee00a10, 0x0fff0fff, "fmxr%c\tfpsid, %12-15r"}, + {0x0ee10a10, 0x0fff0fff, "fmxr%c\tfpscr, %12-15r"}, + {0x0ee80a10, 0x0fff0fff, "fmxr%c\tfpexc, %12-15r"}, + {0x0ee90a10, 0x0fff0fff, "fmxr%c\tfpinst, %12-15r\t@ Impl def"}, + {0x0eea0a10, 0x0fff0fff, "fmxr%c\tfpinst2, %12-15r\t@ Impl def"}, + {0x0ee00a10, 0x0ff00fff, "fmxr%c\t<impl def 0x%16-19x>, %12-15r"}, + {0x0eb10b40, 0x0fff0ff0, "fnegd%c\t%1z, %0z"}, + {0x0eb10a40, 0x0fbf0fd0, "fnegs%c\t%1y, %0y"}, + {0x0e000b40, 0x0ff00ff0, "fnmacd%c\t%1z, %2z, %0z"}, + {0x0e000a40, 0x0fb00f50, "fnmacs%c\t%1y, %2y, %0y"}, + {0x0e100b40, 0x0ff00ff0, "fnmscd%c\t%1z, %2z, %0z"}, + {0x0e100a40, 0x0fb00f50, "fnmscs%c\t%1y, %2y, %0y"}, + {0x0e200b40, 0x0ff00ff0, "fnmuld%c\t%1z, %2z, %0z"}, + {0x0e200a40, 0x0fb00f50, "fnmuls%c\t%1y, %2y, %0y"}, + {0x0eb80bc0, 0x0fff0fd0, "fsitod%c\t%1z, %0y"}, + {0x0eb80ac0, 0x0fbf0fd0, "fsitos%c\t%1y, %0y"}, + {0x0eb10bc0, 0x0fff0ff0, "fsqrtd%c\t%1z, %0z"}, + {0x0eb10ac0, 0x0fbf0fd0, "fsqrts%c\t%1y, %0y"}, + {0x0d000b00, 0x0f700f00, "fstd%c\t%1z, %A"}, + {0x0c800b00, 0x0fd00f00, "fstmia%0?xd%c\t%16-19r%21'!, %3z"}, + {0x0d200b00, 0x0ff00f00, "fstmdb%0?xd%c\t%16-19r!, %3z"}, + {0x0d000a00, 0x0f300f00, "fsts%c\t%1y, %A"}, + {0x0c800a00, 0x0f900f00, "fstmias%c\t%16-19r%21'!, %3y"}, + {0x0d200a00, 0x0fb00f00, "fstmdbs%c\t%16-19r!, %3y"}, + {0x0e300b40, 0x0ff00ff0, "fsubd%c\t%1z, %2z, %0z"}, + {0x0e300a40, 0x0fb00f50, "fsubs%c\t%1y, %2y, %0y"}, + {0x0ebc0b40, 0x0fbe0f70, "fto%16?sui%7'zd%c\t%1y, %0z"}, + {0x0ebc0a40, 0x0fbe0f50, "fto%16?sui%7'zs%c\t%1y, %0y"}, + {0x0eb80b40, 0x0fff0fd0, "fuitod%c\t%1z, %0y"}, + {0x0eb80a40, 0x0fbf0fd0, "fuitos%c\t%1y, %0y"}, + + /* Cirrus coprocessor instructions. */ + {0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, + {0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, + {0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, + {0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, + {0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, + {0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, + {0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, + {0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, + {0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, + {0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, + {0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, + {0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, + {0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, + {0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, + {0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, + {0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, + {0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"}, + {0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"}, + {0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"}, + {0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"}, + {0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"}, + {0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"}, + {0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"}, + {0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"}, + {0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"}, + {0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"}, + {0x0e100610, 0x0ff0fff0, "cfmval32%c\tmvax%0-3d, mvfx%16-19d"}, + {0x0e000610, 0x0ff0fff0, "cfmv32al%c\tmvfx%0-3d, mvax%16-19d"}, + {0x0e100630, 0x0ff0fff0, "cfmvam32%c\tmvax%0-3d, mvfx%16-19d"}, + {0x0e000630, 0x0ff0fff0, "cfmv32am%c\tmvfx%0-3d, mvax%16-19d"}, + {0x0e100650, 0x0ff0fff0, "cfmvah32%c\tmvax%0-3d, mvfx%16-19d"}, + {0x0e000650, 0x0ff0fff0, "cfmv32ah%c\tmvfx%0-3d, mvax%16-19d"}, + {0x0e000670, 0x0ff0fff0, "cfmv32a%c\tmvfx%0-3d, mvax%16-19d"}, + {0x0e100670, 0x0ff0fff0, "cfmva32%c\tmvax%0-3d, mvfx%16-19d"}, + {0x0e000690, 0x0ff0fff0, "cfmv64a%c\tmvdx%0-3d, mvax%16-19d"}, + {0x0e100690, 0x0ff0fff0, "cfmva64%c\tmvax%0-3d, mvdx%16-19d"}, + {0x0e1006b0, 0x0ff0fff0, "cfmvsc32%c\tdspsc, mvfx%16-19d"}, + {0x0e0006b0, 0x0ff0fff0, "cfmv32sc%c\tmvfx%0-3d, dspsc"}, + {0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"}, + {0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"}, + {0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"}, + {0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"}, + {0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"}, + {0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"}, + {0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"}, + {0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"}, + {0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"}, + {0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"}, + {0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"}, + {0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"}, + {0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"}, + {0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"}, + {0x0e000500, 0x0ff00f00, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"}, + {0x0e200500, 0x0ff00f00, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"}, + {0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"}, + {0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"}, + {0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"}, + {0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"}, + {0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"}, + {0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"}, + {0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"}, + {0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"}, + {0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, + {0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, + {0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, + {0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, + {0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, + {0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, + {0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"}, + {0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"}, + {0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"}, + {0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"}, + {0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, + {0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, + {0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, + {0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {0x0e000600, 0x0ff00f00, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {0x0e100600, 0x0ff00f00, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {0x0e200600, 0x0ff00f00, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, + {0x0e300600, 0x0ff00f00, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, + /* Generic coprocessor instructions */ {0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, {0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, diff --git a/contrib/binutils/opcodes/cgen-asm.c b/contrib/binutils/opcodes/cgen-asm.c index a8d6ff8..05b62bf 100644 --- a/contrib/binutils/opcodes/cgen-asm.c +++ b/contrib/binutils/opcodes/cgen-asm.c @@ -1,6 +1,6 @@ /* CGEN generic assembler support code. - Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -20,14 +20,18 @@ #include "sysdep.h" #include <stdio.h> -#include <ctype.h> #include "ansidecl.h" #include "libiberty.h" +#include "safe-ctype.h" #include "bfd.h" #include "symcat.h" #include "opcode/cgen.h" #include "opintl.h" +static CGEN_INSN_LIST * hash_insn_array PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, int, int, CGEN_INSN_LIST **, CGEN_INSN_LIST *)); +static CGEN_INSN_LIST * hash_insn_list PARAMS ((CGEN_CPU_DESC, const CGEN_INSN_LIST *, CGEN_INSN_LIST **, CGEN_INSN_LIST *)); +static void build_asm_hash_table PARAMS ((CGEN_CPU_DESC)); + /* Set the cgen_parse_operand_fn callback. */ void @@ -207,24 +211,34 @@ cgen_parse_keyword (cd, strp, keyword_table, valuep) char buf[256]; const char *p,*start; + if (keyword_table->name_hash_table == NULL) + (void) cgen_keyword_search_init (keyword_table, NULL); + p = start = *strp; - /* Allow any first character. - Note that this allows recognizing ",a" for the annul flag in sparc - even though "," is subsequently not a valid keyword char. */ + /* Allow any first character. This is to make life easier for + the fairly common case of suffixes, eg. 'ld.b.w', where the first + character of the suffix ('.') is special. */ if (*p) ++p; - - /* Now allow letters, digits, and _. */ + + /* Allow letters, digits, and any special characters. */ while (((p - start) < (int) sizeof (buf)) - && (isalnum ((unsigned char) *p) || *p == '_')) + && *p + && (ISALNUM (*p) || strchr (keyword_table->nonalpha_chars, *p))) ++p; if (p - start >= (int) sizeof (buf)) - return _("unrecognized keyword/register name"); - - memcpy (buf, start, p - start); - buf[p - start] = 0; + { + /* All non-empty CGEN keywords can fit into BUF. The only thing + we can match here is the empty keyword. */ + buf[0] = 0; + } + else + { + memcpy (buf, start, p - start); + buf[p - start] = 0; + } ke = cgen_keyword_lookup_name (keyword_table, buf); diff --git a/contrib/binutils/opcodes/cgen-asm.in b/contrib/binutils/opcodes/cgen-asm.in index 7249708..475a4f1 100644 --- a/contrib/binutils/opcodes/cgen-asm.in +++ b/contrib/binutils/opcodes/cgen-asm.in @@ -26,7 +26,6 @@ along with this program; if not, write to the Free Software Foundation, Inc., Keep that in mind. */ #include "sysdep.h" -#include <ctype.h> #include <stdio.h> #include "ansidecl.h" #include "bfd.h" @@ -34,16 +33,142 @@ along with this program; if not, write to the Free Software Foundation, Inc., #include "@prefix@-desc.h" #include "@prefix@-opc.h" #include "opintl.h" +#include "xregex.h" +#include "libiberty.h" +#include "safe-ctype.h" -#undef min +#undef min #define min(a,b) ((a) < (b) ? (a) : (b)) -#undef max +#undef max #define max(a,b) ((a) > (b) ? (a) : (b)) static const char * parse_insn_normal PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); -/* -- assembler routines inserted here */ +/* -- assembler routines inserted here. */ + + +/* Regex construction routine. + + This translates an opcode syntax string into a regex string, + by replacing any non-character syntax element (such as an + opcode) with the pattern '.*' + + It then compiles the regex and stores it in the opcode, for + later use by @arch@_cgen_assemble_insn + + Returns NULL for success, an error message for failure. */ + +char * +@arch@_cgen_build_insn_regex (insn) + CGEN_INSN *insn; +{ + CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); + const char *mnem = CGEN_INSN_MNEMONIC (insn); + char rxbuf[CGEN_MAX_RX_ELEMENTS]; + char *rx = rxbuf; + const CGEN_SYNTAX_CHAR_TYPE *syn; + int reg_err; + + syn = CGEN_SYNTAX_STRING (CGEN_OPCODE_SYNTAX (opc)); + + /* Mnemonics come first in the syntax string. */ + if (! CGEN_SYNTAX_MNEMONIC_P (* syn)) + return _("missing mnemonic in syntax string"); + ++syn; + + /* Generate a case sensitive regular expression that emulates case + insensitive matching in the "C" locale. We cannot generate a case + insensitive regular expression because in Turkish locales, 'i' and 'I' + are not equal modulo case conversion. */ + + /* Copy the literal mnemonic out of the insn. */ + for (; *mnem; mnem++) + { + char c = *mnem; + + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + } + + /* Copy any remaining literals from the syntax string into the rx. */ + for(; * syn != 0 && rx <= rxbuf + (CGEN_MAX_RX_ELEMENTS - 7 - 4); ++syn) + { + if (CGEN_SYNTAX_CHAR_P (* syn)) + { + char c = CGEN_SYNTAX_CHAR (* syn); + + switch (c) + { + /* Escape any regex metacharacters in the syntax. */ + case '.': case '[': case '\\': + case '*': case '^': case '$': + +#ifdef CGEN_ESCAPE_EXTENDED_REGEX + case '?': case '{': case '}': + case '(': case ')': case '*': + case '|': case '+': case ']': +#endif + *rx++ = '\\'; + *rx++ = c; + break; + + default: + if (ISALPHA (c)) + { + *rx++ = '['; + *rx++ = TOLOWER (c); + *rx++ = TOUPPER (c); + *rx++ = ']'; + } + else + *rx++ = c; + break; + } + } + else + { + /* Replace non-syntax fields with globs. */ + *rx++ = '.'; + *rx++ = '*'; + } + } + + /* Trailing whitespace ok. */ + * rx++ = '['; + * rx++ = ' '; + * rx++ = '\t'; + * rx++ = ']'; + * rx++ = '*'; + + /* But anchor it after that. */ + * rx++ = '$'; + * rx = '\0'; + + CGEN_INSN_RX (insn) = xmalloc (sizeof (regex_t)); + reg_err = regcomp ((regex_t *) CGEN_INSN_RX (insn), rxbuf, REG_NOSUB); + + if (reg_err == 0) + return NULL; + else + { + static char msg[80]; + + regerror (reg_err, (regex_t *) CGEN_INSN_RX (insn), msg, 80); + regfree ((regex_t *) CGEN_INSN_RX (insn)); + free (CGEN_INSN_RX (insn)); + (CGEN_INSN_RX (insn)) = NULL; + return msg; + } +} + /* Default insn parser. @@ -56,8 +181,7 @@ static const char * parse_insn_normal but that can be handled there. Not handling backtracking here may get expensive in the case of the m68k. Deal with later. - Returns NULL for success, an error message for failure. -*/ + Returns NULL for success, an error message for failure. */ static const char * parse_insn_normal (cd, insn, strp, fields) @@ -82,14 +206,14 @@ parse_insn_normal (cd, insn, strp, fields) GAS's input scrubber will ensure mnemonics are lowercase, but we may not be called from GAS. */ p = CGEN_INSN_MNEMONIC (insn); - while (*p && tolower (*p) == tolower (*str)) + while (*p && TOLOWER (*p) == TOLOWER (*str)) ++p, ++str; if (* p) return _("unrecognized instruction"); #ifndef CGEN_MNEMONIC_OPERANDS - if (* str && !isspace (* str)) + if (* str && ! ISSPACE (* str)) return _("unrecognized instruction"); #endif @@ -118,7 +242,7 @@ parse_insn_normal (cd, insn, strp, fields) first char after the mnemonic part is a space. */ /* FIXME: We also take inappropriate advantage of the fact that GAS's input scrubber will remove extraneous blanks. */ - if (tolower (*str) == tolower (CGEN_SYNTAX_CHAR (* syn))) + if (TOLOWER (*str) == TOLOWER (CGEN_SYNTAX_CHAR (* syn))) { #ifdef CGEN_MNEMONIC_OPERANDS if (CGEN_SYNTAX_CHAR(* syn) == ' ') @@ -131,6 +255,7 @@ parse_insn_normal (cd, insn, strp, fields) { /* Syntax char didn't match. Can't be this insn. */ static char msg [80]; + /* xgettext:c-format */ sprintf (msg, _("syntax error (expected char `%c', found `%c')"), CGEN_SYNTAX_CHAR(*syn), *str); @@ -140,6 +265,7 @@ parse_insn_normal (cd, insn, strp, fields) { /* Ran out of input. */ static char msg [80]; + /* xgettext:c-format */ sprintf (msg, _("syntax error (expected char `%c', found end of instruction)"), CGEN_SYNTAX_CHAR(*syn)); @@ -165,7 +291,7 @@ parse_insn_normal (cd, insn, strp, fields) blanks now. IE: We needn't try again with a longer version of the insn and it is assumed that longer versions of insns appear before shorter ones (eg: lsr r2,r3,1 vs lsr r2,r3). */ - while (isspace (* str)) + while (ISSPACE (* str)) ++ str; if (* str != '\0') @@ -211,9 +337,10 @@ const CGEN_INSN * CGEN_INSN_LIST *ilist; const char *parse_errmsg = NULL; const char *insert_errmsg = NULL; + int recognized_mnemonic = 0; /* Skip leading white space. */ - while (isspace (* str)) + while (ISSPACE (* str)) ++ str; /* The instructions are stored in hashed lists. @@ -221,19 +348,19 @@ const CGEN_INSN * ilist = CGEN_ASM_LOOKUP_INSN (cd, str); /* Keep looking until we find a match. */ - start = str; for ( ; ilist != NULL ; ilist = CGEN_ASM_NEXT_INSN (ilist)) { const CGEN_INSN *insn = ilist->insn; + recognized_mnemonic = 1; #ifdef CGEN_VALIDATE_INSN_SUPPORTED - /* not usually needed as unsupported opcodes shouldn't be in the hash lists */ + /* Not usually needed as unsupported opcodes + shouldn't be in the hash lists. */ /* Is this insn supported by the selected cpu? */ if (! @arch@_cgen_insn_supported (cd, insn)) continue; #endif - /* If the RELAX attribute is set, this is an insn that shouldn't be chosen immediately. Instead, it is used during assembler/linker relaxation if possible. */ @@ -242,6 +369,11 @@ const CGEN_INSN * str = start; + /* Skip this insn if str doesn't look right lexically. */ + if (CGEN_INSN_RX (insn) != NULL && + regexec ((regex_t *) CGEN_INSN_RX (insn), str, 0, NULL, 0) == REG_NOMATCH) + continue; + /* Allow parse/insert handlers to obtain length of insn. */ CGEN_FIELDS_BITSIZE (fields) = CGEN_INSN_BITSIZE (insn); @@ -249,7 +381,7 @@ const CGEN_INSN * if (parse_errmsg != NULL) continue; - /* ??? 0 is passed for `pc' */ + /* ??? 0 is passed for `pc'. */ insert_errmsg = CGEN_INSERT_FN (cd, insn) (cd, insn, fields, buf, (bfd_vma) 0); if (insert_errmsg != NULL) @@ -262,13 +394,15 @@ const CGEN_INSN * { static char errbuf[150]; +#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS const char *tmp_errmsg; -#ifdef CGEN_VERBOSE_ASSEMBLER_ERRORS /* If requesting verbose error messages, use insert_errmsg. - Failing that, use parse_errmsg */ + Failing that, use parse_errmsg. */ tmp_errmsg = (insert_errmsg ? insert_errmsg : parse_errmsg ? parse_errmsg : + recognized_mnemonic ? + _("unrecognized form of instruction") : _("unrecognized instruction")); if (strlen (start) > 50) diff --git a/contrib/binutils/opcodes/cgen-dis.c b/contrib/binutils/opcodes/cgen-dis.c index b4297bb..4622c8c 100644 --- a/contrib/binutils/opcodes/cgen-dis.c +++ b/contrib/binutils/opcodes/cgen-dis.c @@ -27,6 +27,61 @@ #include "symcat.h" #include "opcode/cgen.h" +static CGEN_INSN_LIST * hash_insn_array PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, int, int, CGEN_INSN_LIST **, CGEN_INSN_LIST *)); +static CGEN_INSN_LIST * hash_insn_list PARAMS ((CGEN_CPU_DESC, const CGEN_INSN_LIST *, CGEN_INSN_LIST **, CGEN_INSN_LIST *)); +static void build_dis_hash_table PARAMS ((CGEN_CPU_DESC)); + +/* Return the number of decodable bits in this insn. */ +static int +count_decodable_bits (insn) + const CGEN_INSN *insn; +{ + unsigned mask = CGEN_INSN_BASE_MASK (insn); + int bits = 0; + int m; + for (m = 1; m != 0; m <<= 1) + { + if (mask & m) + ++bits; + } + return bits; +} + +/* Add an instruction to the hash chain. */ +static void +add_insn_to_hash_chain (hentbuf, insn, htable, hash) + CGEN_INSN_LIST *hentbuf; + const CGEN_INSN *insn; + CGEN_INSN_LIST **htable; + unsigned int hash; +{ + CGEN_INSN_LIST *current_buf; + CGEN_INSN_LIST *previous_buf; + int insn_decodable_bits; + + /* Add insns sorted by the number of decodable bits, in decreasing order. + This ensures that any insn which is a special case of another will be + checked first. */ + insn_decodable_bits = count_decodable_bits (insn); + previous_buf = NULL; + for (current_buf = htable[hash]; current_buf != NULL; + current_buf = current_buf->next) + { + int current_decodable_bits = count_decodable_bits (current_buf->insn); + if (insn_decodable_bits >= current_decodable_bits) + break; + previous_buf = current_buf; + } + + /* Now insert the new insn. */ + hentbuf->insn = insn; + hentbuf->next = current_buf; + if (previous_buf == NULL) + htable[hash] = hentbuf; + else + previous_buf->next = hentbuf; +} + /* Subroutine of build_dis_hash_table to add INSNS to the hash table. COUNT is the number of elements in INSNS. @@ -70,9 +125,7 @@ hash_insn_array (cd, insns, count, entsize, htable, hentbuf) CGEN_INSN_MASK_BITSIZE (insn), big_p); hash = (* cd->dis_hash) (buf, value); - hentbuf->next = htable[hash]; - hentbuf->insn = insn; - htable[hash] = hentbuf; + add_insn_to_hash_chain (hentbuf, insn, htable, hash); } return hentbuf; @@ -110,9 +163,7 @@ hash_insn_list (cd, insns, htable, hentbuf) CGEN_INSN_MASK_BITSIZE (ilist->insn), big_p); hash = (* cd->dis_hash) (buf, value); - hentbuf->next = htable [hash]; - hentbuf->insn = ilist->insn; - htable [hash] = hentbuf; + add_insn_to_hash_chain (hentbuf, ilist->insn, htable, hash); } return hentbuf; diff --git a/contrib/binutils/opcodes/cgen-dis.in b/contrib/binutils/opcodes/cgen-dis.in index 0e7c35a..f2c9dd5 100644 --- a/contrib/binutils/opcodes/cgen-dis.in +++ b/contrib/binutils/opcodes/cgen-dis.in @@ -47,10 +47,13 @@ static void print_keyword static void print_insn_normal PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int)); -static int print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, - disassemble_info *, char *, int)); +static int print_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); static int default_print_insn PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); +static int read_insn + PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, + CGEN_EXTRACT_INFO *, unsigned long *)); /* -- disassembler routines inserted here */ @@ -58,21 +61,12 @@ static int default_print_insn static void print_normal (cd, dis_info, value, attrs, pc, length) -#ifdef CGEN_PRINT_NORMAL - CGEN_CPU_DESC cd; -#else CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; -#endif PTR dis_info; long value; unsigned int attrs; -#ifdef CGEN_PRINT_NORMAL - bfd_vma pc; - int length; -#else bfd_vma pc ATTRIBUTE_UNUSED; int length ATTRIBUTE_UNUSED; -#endif { disassemble_info *info = (disassemble_info *) dis_info; @@ -93,21 +87,12 @@ print_normal (cd, dis_info, value, attrs, pc, length) static void print_address (cd, dis_info, value, attrs, pc, length) -#ifdef CGEN_PRINT_NORMAL - CGEN_CPU_DESC cd; -#else CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; -#endif PTR dis_info; bfd_vma value; unsigned int attrs; -#ifdef CGEN_PRINT_NORMAL - bfd_vma pc; - int length; -#else bfd_vma pc ATTRIBUTE_UNUSED; int length ATTRIBUTE_UNUSED; -#endif { disassemble_info *info = (disassemble_info *) dis_info; @@ -190,9 +175,10 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length) /* Subroutine of print_insn. Reads an insn into the given buffers and updates the extract info. Returns 0 if all is well, non-zero otherwise. */ + static int read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) - CGEN_CPU_DESC cd; + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; bfd_vma pc; disassemble_info *info; char *buf; @@ -227,15 +213,25 @@ print_insn (cd, pc, info, buf, buflen) bfd_vma pc; disassemble_info *info; char *buf; - int buflen; + unsigned int buflen; { - unsigned long insn_value; + CGEN_INSN_INT insn_value; const CGEN_INSN_LIST *insn_list; CGEN_EXTRACT_INFO ex_info; + int basesize; + + /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ + basesize = cd->base_insn_bitsize < buflen * 8 ? + cd->base_insn_bitsize : buflen * 8; + insn_value = cgen_get_insn_value (cd, buf, basesize); - int rc = read_insn (cd, pc, info, buf, buflen, & ex_info, & insn_value); - if (rc != 0) - return rc; + + /* Fill in ex_info fields like read_insn would. Don't actually call + read_insn, since the incoming buffer is already read (and possibly + modified a la m32r). */ + ex_info.valid = (1 << buflen) - 1; + ex_info.dis_info = info; + ex_info.insn_bytes = buf; /* The instructions are stored in hash lists. Pick the first one and keep trying until we find the right one. */ @@ -246,9 +242,10 @@ print_insn (cd, pc, info, buf, buflen) const CGEN_INSN *insn = insn_list->insn; CGEN_FIELDS fields; int length; + unsigned long insn_value_cropped; #ifdef CGEN_VALIDATE_INSN_SUPPORTED - /* not needed as insn shouldn't be in hash lists if not supported */ + /* Not needed as insn shouldn't be in hash lists if not supported. */ /* Supported by this cpu? */ if (! @arch@_cgen_insn_supported (cd, insn)) { @@ -260,7 +257,17 @@ print_insn (cd, pc, info, buf, buflen) /* Basic bit mask must be correct. */ /* ??? May wish to allow target to defer this check until the extract handler. */ - if ((insn_value & CGEN_INSN_BASE_MASK (insn)) + + /* Base size may exceed this instruction's size. Extract the + relevant part from the buffer. */ + if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), + info->endian == BFD_ENDIAN_BIG); + else + insn_value_cropped = insn_value; + + if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) == CGEN_INSN_BASE_VALUE (insn)) { /* Printing is handled in two passes. The first pass parses the @@ -269,8 +276,8 @@ print_insn (cd, pc, info, buf, buflen) /* Make sure the entire insn is loaded into insn_value, if it can fit. */ - if (CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize && - (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) + if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && + (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) { unsigned long full_insn_value; int rc = read_insn (cd, pc, info, buf, @@ -283,7 +290,7 @@ print_insn (cd, pc, info, buf, buflen) } else length = CGEN_EXTRACT_FN (cd, insn) - (cd, insn, &ex_info, insn_value, &fields, pc); + (cd, insn, &ex_info, insn_value_cropped, &fields, pc); /* length < 0 -> error */ if (length < 0) @@ -317,18 +324,27 @@ default_print_insn (cd, pc, info) disassemble_info *info; { char buf[CGEN_MAX_INSN_SIZE]; + int buflen; int status; - /* Read the base part of the insn. */ + /* Attempt to read the base part of the insn. */ + buflen = cd->base_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + + /* Try again with the minimum part, if min < base. */ + if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) + { + buflen = cd->min_insn_bitsize / 8; + status = (*info->read_memory_func) (pc, buf, buflen, info); + } - status = (*info->read_memory_func) (pc, buf, cd->base_insn_bitsize / 8, info); if (status != 0) { (*info->memory_error_func) (status, pc, info); return -1; } - return print_insn (cd, pc, info, buf, cd->base_insn_bitsize / 8); + return print_insn (cd, pc, info, buf, buflen); } /* Main entry point. @@ -358,17 +374,21 @@ print_insn_@arch@ (pc, info) arch = info->arch; if (arch == bfd_arch_unknown) arch = CGEN_BFD_ARCH; - - /* There's no standard way to compute the isa number (e.g. for arm thumb) + + /* There's no standard way to compute the machine or isa number so we leave it to the target. */ +#ifdef CGEN_COMPUTE_MACH + mach = CGEN_COMPUTE_MACH (info); +#else + mach = info->mach; +#endif + #ifdef CGEN_COMPUTE_ISA isa = CGEN_COMPUTE_ISA (info); #else isa = 0; #endif - mach = info->mach; - /* If we've switched cpu's, close the current table and open a new one. */ if (cd && (isa != prev_isa diff --git a/contrib/binutils/opcodes/cgen-ibld.in b/contrib/binutils/opcodes/cgen-ibld.in index 6921a53..d2bfd02 100644 --- a/contrib/binutils/opcodes/cgen-ibld.in +++ b/contrib/binutils/opcodes/cgen-ibld.in @@ -25,7 +25,6 @@ along with this program; if not, write to the Free Software Foundation, Inc., Keep that in mind. */ #include "sysdep.h" -#include <ctype.h> #include <stdio.h> #include "ansidecl.h" #include "dis-asm.h" @@ -34,6 +33,7 @@ along with this program; if not, write to the Free Software Foundation, Inc., #include "@prefix@-desc.h" #include "@prefix@-opc.h" #include "opintl.h" +#include "safe-ctype.h" #undef min #define min(a,b) ((a) < (b) ? (a) : (b)) @@ -49,7 +49,6 @@ static const char * insert_normal static const char * insert_insn_normal PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); - static int extract_normal PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, unsigned int, unsigned int, unsigned int, unsigned int, @@ -57,9 +56,19 @@ static int extract_normal static int extract_insn_normal PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); +#if CGEN_INT_INSN_P static void put_insn_int_value PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); - +#endif +#if ! CGEN_INT_INSN_P +static CGEN_INLINE void insert_1 + PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *)); +static CGEN_INLINE int fill_cache + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); +static CGEN_INLINE long extract_1 + PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, + unsigned char *, bfd_vma)); +#endif /* Operand insertion. */ @@ -76,9 +85,8 @@ insert_1 (cd, value, start, length, word_length, bufp) { unsigned long x,mask; int shift; - int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; - x = bfd_get_bits (bufp, word_length, big_p); + x = cgen_get_insn_value (cd, bufp, word_length); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -88,7 +96,7 @@ insert_1 (cd, value, start, length, word_length, bufp) shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - bfd_put_bits ((bfd_vma) x, bufp, word_length, big_p); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); } #endif /* ! CGEN_INT_INSN_P */ @@ -145,7 +153,22 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length, } /* Ensure VALUE will fit. */ - if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) + if (CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGN_OPT)) + { + long minval = - (1L << (length - 1)); + unsigned long maxval = mask; + + if ((value > 0 && (unsigned long) value > maxval) + || value < minval) + { + /* xgettext:c-format */ + sprintf (errbuf, + _("operand out of range (%ld not between %ld and %lu)"), + value, minval, maxval); + return errbuf; + } + } + else if (! CGEN_BOOL_ATTR (attrs, CGEN_IFLD_SIGNED)) { unsigned long maxval = mask; @@ -202,10 +225,10 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length, } /* Default insn builder (insert handler). - The instruction is recorded in CGEN_INT_INSN_P byte order - (meaning that if CGEN_INT_INSN_P BUFFER is an int * and thus the value is - recorded in host byte order, otherwise BUFFER is an array of bytes and the - value is recorded in target byte order). + The instruction is recorded in CGEN_INT_INSN_P byte order (meaning + that if CGEN_INSN_BYTES_PTR is an int * and thus, the value is + recorded in host byte order, otherwise BUFFER is an array of bytes + and the value is recorded in target byte order). The result is an error message or NULL if success. */ static const char * @@ -233,8 +256,8 @@ insert_insn_normal (cd, insn, fields, buffer, pc) #else - cgen_put_insn_value (cd, buffer, min (cd->base_insn_bitsize, - CGEN_FIELDS_BITSIZE (fields)), + cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, + (unsigned) CGEN_FIELDS_BITSIZE (fields)), value); #endif /* ! CGEN_INT_INSN_P */ @@ -260,12 +283,13 @@ insert_insn_normal (cd, insn, fields, buffer, pc) return NULL; } +#if CGEN_INT_INSN_P /* Cover function to store an insn value into an integral insn. Must go here because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ static void put_insn_int_value (cd, buf, length, insn_length, value) - CGEN_CPU_DESC cd; + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; CGEN_INSN_BYTES_PTR buf; int length; int insn_length; @@ -283,6 +307,7 @@ put_insn_int_value (cd, buf, length, insn_length, value) *buf = (*buf & ~(mask << shift)) | ((value & mask) << shift); } } +#endif /* Operand extraction. */ @@ -296,14 +321,14 @@ put_insn_int_value (cd, buf, length, insn_length, value) static CGEN_INLINE int fill_cache (cd, ex_info, offset, bytes, pc) - CGEN_CPU_DESC cd; + CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; CGEN_EXTRACT_INFO *ex_info; int offset, bytes; bfd_vma pc; { /* It's doubtful that the middle part has already been fetched so we don't optimize that case. kiss. */ - int mask; + unsigned int mask; disassemble_info *info = (disassemble_info *) ex_info->dis_info; /* First do a quick check. */ @@ -341,16 +366,17 @@ fill_cache (cd, ex_info, offset, bytes, pc) static CGEN_INLINE long extract_1 (cd, ex_info, start, length, word_length, bufp, pc) CGEN_CPU_DESC cd; - CGEN_EXTRACT_INFO *ex_info; + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; int start,length,word_length; unsigned char *bufp; - bfd_vma pc; + bfd_vma pc ATTRIBUTE_UNUSED; { unsigned long x; int shift; +#if 0 int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG; - - x = bfd_get_bits (bufp, word_length, big_p); +#endif + x = cgen_get_insn_value (cd, bufp, word_length); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; @@ -400,7 +426,7 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, #endif long *valuep; { - CGEN_INSN_INT value, mask; + long value, mask; /* If LENGTH is zero, this operand doesn't contribute to the value so give it a standard value of zero. */ @@ -428,9 +454,9 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, word_length = total_length; } - /* Does the value reside in INSN_VALUE? */ + /* Does the value reside in INSN_VALUE, and at the right alignment? */ - if (CGEN_INT_INSN_P || word_offset == 0) + if (CGEN_INT_INSN_P || (word_offset == 0 && word_length == total_length)) { if (CGEN_INSN_LSB0_P) value = insn_value >> ((word_offset + start + 1) - length); diff --git a/contrib/binutils/opcodes/cgen-opc.c b/contrib/binutils/opcodes/cgen-opc.c index e55482c..06544ca 100644 --- a/contrib/binutils/opcodes/cgen-opc.c +++ b/contrib/binutils/opcodes/cgen-opc.c @@ -20,10 +20,10 @@ 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "sysdep.h" -#include <ctype.h> #include <stdio.h> #include "ansidecl.h" #include "libiberty.h" +#include "safe-ctype.h" #include "bfd.h" #include "symcat.h" #include "opcode/cgen.h" @@ -69,9 +69,7 @@ cgen_keyword_lookup_name (kt, name) while (*p && (*p == *n - || (isalpha ((unsigned char) *p) - && (tolower ((unsigned char) *p) - == tolower ((unsigned char) *n))))) + || (ISALPHA (*p) && (TOLOWER (*p) == TOLOWER (*n))))) ++n, ++p; if (!*p && !*n) @@ -118,6 +116,7 @@ cgen_keyword_add (kt, ke) CGEN_KEYWORD_ENTRY *ke; { unsigned int hash; + size_t i; if (kt->name_hash_table == NULL) build_keyword_hash_tables (kt); @@ -132,6 +131,21 @@ cgen_keyword_add (kt, ke) if (ke->name[0] == 0) kt->null_entry = ke; + + for (i = 1; i < strlen (ke->name); i++) + if (! ISALNUM (ke->name[i]) + && ! strchr (kt->nonalpha_chars, ke->name[i])) + { + size_t idx = strlen (kt->nonalpha_chars); + + /* If you hit this limit, please don't just + increase the size of the field, instead + look for a better algorithm. */ + if (idx >= sizeof (kt->nonalpha_chars) - 1) + abort (); + kt->nonalpha_chars[idx] = ke->name[i]; + kt->nonalpha_chars[idx+1] = 0; + } } /* FIXME: Need function to return count of keywords. */ @@ -216,7 +230,7 @@ hash_keyword_name (kt, name, case_sensitive_p) hash = (hash * 97) + (unsigned char) *name; else for (hash = 0; *name; ++name) - hash = (hash * 97) + (unsigned char) tolower (*name); + hash = (hash * 97) + (unsigned char) TOLOWER (*name); return hash % kt->hash_table_size; } @@ -375,7 +389,35 @@ cgen_get_insn_value (cd, buf, length) unsigned char *buf; int length; { - bfd_get_bits (buf, length, cd->insn_endian == CGEN_ENDIAN_BIG); + int big_p = (cd->insn_endian == CGEN_ENDIAN_BIG); + int insn_chunk_bitsize = cd->insn_chunk_bitsize; + CGEN_INSN_INT value = 0; + + if (insn_chunk_bitsize != 0 && insn_chunk_bitsize < length) + { + /* We need to divide up the incoming value into insn_chunk_bitsize-length + segments, and endian-convert them, one at a time. */ + int i; + + /* Enforce divisibility. */ + if ((length % insn_chunk_bitsize) != 0) + abort (); + + for (i = 0; i < length; i += insn_chunk_bitsize) /* NB: i == bits */ + { + int index; + bfd_vma this_value; + index = i; /* NB: not dependent on endianness; opposite of cgen_put_insn_value! */ + this_value = bfd_get_bits (& buf[index / 8], insn_chunk_bitsize, big_p); + value = (value << insn_chunk_bitsize) | this_value; + } + } + else + { + value = bfd_get_bits (buf, length, cd->insn_endian == CGEN_ENDIAN_BIG); + } + + return value; } /* Cover function to store an insn value properly byteswapped. */ @@ -387,8 +429,31 @@ cgen_put_insn_value (cd, buf, length, value) int length; CGEN_INSN_INT value; { - bfd_put_bits ((bfd_vma) value, buf, length, - cd->insn_endian == CGEN_ENDIAN_BIG); + int big_p = (cd->insn_endian == CGEN_ENDIAN_BIG); + int insn_chunk_bitsize = cd->insn_chunk_bitsize; + + if (insn_chunk_bitsize != 0 && insn_chunk_bitsize < length) + { + /* We need to divide up the incoming value into insn_chunk_bitsize-length + segments, and endian-convert them, one at a time. */ + int i; + + /* Enforce divisibility. */ + if ((length % insn_chunk_bitsize) != 0) + abort (); + + for (i = 0; i < length; i += insn_chunk_bitsize) /* NB: i == bits */ + { + int index; + index = (length - insn_chunk_bitsize - i); /* NB: not dependent on endianness! */ + bfd_put_bits ((bfd_vma) value, & buf[index / 8], insn_chunk_bitsize, big_p); + value >>= insn_chunk_bitsize; + } + } + else + { + bfd_put_bits ((bfd_vma) value, buf, length, big_p); + } } /* Look up instruction INSN_*_VALUE and extract its fields. diff --git a/contrib/binutils/opcodes/config.in b/contrib/binutils/opcodes/config.in index c60a321..5caef55 100644 --- a/contrib/binutils/opcodes/config.in +++ b/contrib/binutils/opcodes/config.in @@ -25,9 +25,6 @@ /* Define to `long' if <sys/types.h> doesn't define. */ #undef off_t -/* Define if you need to in order for stat and other things to work. */ -#undef _POSIX_SOURCE - /* Define to `unsigned' if <sys/types.h> doesn't define. */ #undef size_t diff --git a/contrib/binutils/opcodes/configure b/contrib/binutils/opcodes/configure index 946e38a..baa5fbd 100755 --- a/contrib/binutils/opcodes/configure +++ b/contrib/binutils/opcodes/configure @@ -55,7 +55,6 @@ program_suffix=NONE program_transform_name=s,x,x, silent= site= -sitefile= srcdir= target=NONE verbose= @@ -170,7 +169,6 @@ Configuration: --help print this message --no-create do not create output files --quiet, --silent do not print \`checking...' messages - --site-file=FILE use FILE as the site file --version print the version of autoconf that created configure Directory and file names: --prefix=PREFIX install architecture-independent files in PREFIX @@ -341,11 +339,6 @@ EOF -site=* | --site=* | --sit=*) site="$ac_optarg" ;; - -site-file | --site-file | --site-fil | --site-fi | --site-f) - ac_prev=sitefile ;; - -site-file=* | --site-file=* | --site-fil=* | --site-fi=* | --site-f=*) - sitefile="$ac_optarg" ;; - -srcdir | --srcdir | --srcdi | --srcd | --src | --sr) ac_prev=srcdir ;; -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*) @@ -511,16 +504,12 @@ fi srcdir=`echo "${srcdir}" | sed 's%\([^/]\)/*$%\1%'` # Prefer explicitly selected file to automatically selected ones. -if test -z "$sitefile"; then - if test -z "$CONFIG_SITE"; then - if test "x$prefix" != xNONE; then - CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site" - else - CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site" - fi +if test -z "$CONFIG_SITE"; then + if test "x$prefix" != xNONE; then + CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site" + else + CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site" fi -else - CONFIG_SITE="$sitefile" fi for ac_site_file in $CONFIG_SITE; do if test -r "$ac_site_file"; then @@ -559,12 +548,12 @@ else fi echo $ac_n "checking for Cygwin environment""... $ac_c" 1>&6 -echo "configure:563: checking for Cygwin environment" >&5 +echo "configure:552: checking for Cygwin environment" >&5 if eval "test \"`echo '$''{'ac_cv_cygwin'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 568 "configure" +#line 557 "configure" #include "confdefs.h" int main() { @@ -575,7 +564,7 @@ int main() { return __CYGWIN__; ; return 0; } EOF -if { (eval echo configure:579: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:568: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* ac_cv_cygwin=yes else @@ -592,19 +581,19 @@ echo "$ac_t""$ac_cv_cygwin" 1>&6 CYGWIN= test "$ac_cv_cygwin" = yes && CYGWIN=yes echo $ac_n "checking for mingw32 environment""... $ac_c" 1>&6 -echo "configure:596: checking for mingw32 environment" >&5 +echo "configure:585: checking for mingw32 environment" >&5 if eval "test \"`echo '$''{'ac_cv_mingw32'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 601 "configure" +#line 590 "configure" #include "confdefs.h" int main() { return __MINGW32__; ; return 0; } EOF -if { (eval echo configure:608: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:597: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* ac_cv_mingw32=yes else @@ -669,7 +658,7 @@ else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; } fi echo $ac_n "checking host system type""... $ac_c" 1>&6 -echo "configure:673: checking host system type" >&5 +echo "configure:662: checking host system type" >&5 host_alias=$host case "$host_alias" in @@ -690,7 +679,7 @@ host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` echo "$ac_t""$host" 1>&6 echo $ac_n "checking target system type""... $ac_c" 1>&6 -echo "configure:694: checking target system type" >&5 +echo "configure:683: checking target system type" >&5 target_alias=$target case "$target_alias" in @@ -708,7 +697,7 @@ target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` echo "$ac_t""$target" 1>&6 echo $ac_n "checking build system type""... $ac_c" 1>&6 -echo "configure:712: checking build system type" >&5 +echo "configure:701: checking build system type" >&5 build_alias=$build case "$build_alias" in @@ -730,249 +719,49 @@ test "$host_alias" != "$target_alias" && NONENONEs,x,x, && program_prefix=${target_alias}- -# Extract the first word of "gcc", so it can be a program name with args. -set dummy gcc; ac_word=$2 -echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:737: checking for $ac_word" >&5 -if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then - echo $ac_n "(cached) $ac_c" 1>&6 -else - if test -n "$CC"; then - ac_cv_prog_CC="$CC" # Let the user override the test. -else - IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" - ac_dummy="$PATH" - for ac_dir in $ac_dummy; do - test -z "$ac_dir" && ac_dir=. - if test -f $ac_dir/$ac_word; then - ac_cv_prog_CC="gcc" - break - fi - done - IFS="$ac_save_ifs" -fi -fi -CC="$ac_cv_prog_CC" -if test -n "$CC"; then - echo "$ac_t""$CC" 1>&6 -else - echo "$ac_t""no" 1>&6 -fi -if test -z "$CC"; then - # Extract the first word of "cc", so it can be a program name with args. -set dummy cc; ac_word=$2 -echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:767: checking for $ac_word" >&5 -if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then - echo $ac_n "(cached) $ac_c" 1>&6 -else - if test -n "$CC"; then - ac_cv_prog_CC="$CC" # Let the user override the test. -else - IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" - ac_prog_rejected=no - ac_dummy="$PATH" - for ac_dir in $ac_dummy; do - test -z "$ac_dir" && ac_dir=. - if test -f $ac_dir/$ac_word; then - if test "$ac_dir/$ac_word" = "/usr/ucb/cc"; then - ac_prog_rejected=yes - continue - fi - ac_cv_prog_CC="cc" - break - fi - done - IFS="$ac_save_ifs" -if test $ac_prog_rejected = yes; then - # We found a bogon in the path, so make sure we never use it. - set dummy $ac_cv_prog_CC - shift - if test $# -gt 0; then - # We chose a different compiler from the bogus one. - # However, it has the same basename, so the bogon will be chosen - # first if we set CC to just the basename; use the full file name. - shift - set dummy "$ac_dir/$ac_word" "$@" - shift - ac_cv_prog_CC="$@" - fi -fi -fi -fi -CC="$ac_cv_prog_CC" -if test -n "$CC"; then - echo "$ac_t""$CC" 1>&6 -else - echo "$ac_t""no" 1>&6 -fi - - if test -z "$CC"; then - case "`uname -s`" in - *win32* | *WIN32*) - # Extract the first word of "cl", so it can be a program name with args. -set dummy cl; ac_word=$2 -echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:818: checking for $ac_word" >&5 -if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "checking for strerror in -lcposix""... $ac_c" 1>&6 +echo "configure:725: checking for strerror in -lcposix" >&5 +ac_lib_var=`echo cposix'_'strerror | sed 'y%./+-%__p_%'` +if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else - if test -n "$CC"; then - ac_cv_prog_CC="$CC" # Let the user override the test. -else - IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" - ac_dummy="$PATH" - for ac_dir in $ac_dummy; do - test -z "$ac_dir" && ac_dir=. - if test -f $ac_dir/$ac_word; then - ac_cv_prog_CC="cl" - break - fi - done - IFS="$ac_save_ifs" -fi -fi -CC="$ac_cv_prog_CC" -if test -n "$CC"; then - echo "$ac_t""$CC" 1>&6 -else - echo "$ac_t""no" 1>&6 -fi - ;; - esac - fi - test -z "$CC" && { echo "configure: error: no acceptable cc found in \$PATH" 1>&2; exit 1; } -fi - -echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6 -echo "configure:850: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 - -ac_ext=c -# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. -ac_cpp='$CPP $CPPFLAGS' -ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' -ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' -cross_compiling=$ac_cv_prog_cc_cross - -cat > conftest.$ac_ext << EOF - -#line 861 "configure" + ac_save_LIBS="$LIBS" +LIBS="-lcposix $LIBS" +cat > conftest.$ac_ext <<EOF +#line 733 "configure" #include "confdefs.h" +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char strerror(); -main(){return(0);} +int main() { +strerror() +; return 0; } EOF -if { (eval echo configure:866: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then - ac_cv_prog_cc_works=yes - # If we can't run a trivial program, we are probably using a cross compiler. - if (./conftest; exit) 2>/dev/null; then - ac_cv_prog_cc_cross=no - else - ac_cv_prog_cc_cross=yes - fi +if { (eval echo configure:744: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=yes" else echo "configure: failed program was:" >&5 cat conftest.$ac_ext >&5 - ac_cv_prog_cc_works=no -fi -rm -fr conftest* -ac_ext=c -# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. -ac_cpp='$CPP $CPPFLAGS' -ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' -ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' -cross_compiling=$ac_cv_prog_cc_cross - -echo "$ac_t""$ac_cv_prog_cc_works" 1>&6 -if test $ac_cv_prog_cc_works = no; then - { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; } -fi -echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6 -echo "configure:892: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 -echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6 -cross_compiling=$ac_cv_prog_cc_cross - -echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6 -echo "configure:897: checking whether we are using GNU C" >&5 -if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then - echo $ac_n "(cached) $ac_c" 1>&6 -else - cat > conftest.c <<EOF -#ifdef __GNUC__ - yes; -#endif -EOF -if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:906: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then - ac_cv_prog_gcc=yes -else - ac_cv_prog_gcc=no -fi -fi - -echo "$ac_t""$ac_cv_prog_gcc" 1>&6 - -if test $ac_cv_prog_gcc = yes; then - GCC=yes -else - GCC= -fi - -ac_test_CFLAGS="${CFLAGS+set}" -ac_save_CFLAGS="$CFLAGS" -CFLAGS= -echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6 -echo "configure:925: checking whether ${CC-cc} accepts -g" >&5 -if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then - echo $ac_n "(cached) $ac_c" 1>&6 -else - echo 'void f(){}' > conftest.c -if test -z "`${CC-cc} -g -c conftest.c 2>&1`"; then - ac_cv_prog_cc_g=yes -else - ac_cv_prog_cc_g=no + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=no" fi rm -f conftest* +LIBS="$ac_save_LIBS" fi - -echo "$ac_t""$ac_cv_prog_cc_g" 1>&6 -if test "$ac_test_CFLAGS" = set; then - CFLAGS="$ac_save_CFLAGS" -elif test $ac_cv_prog_cc_g = yes; then - if test "$GCC" = yes; then - CFLAGS="-g -O2" - else - CFLAGS="-g" - fi -else - if test "$GCC" = yes; then - CFLAGS="-O2" - else - CFLAGS= - fi -fi - -echo $ac_n "checking for POSIXized ISC""... $ac_c" 1>&6 -echo "configure:957: checking for POSIXized ISC" >&5 -if test -d /etc/conf/kconfig.d && - grep _POSIX_VERSION /usr/include/sys/unistd.h >/dev/null 2>&1 -then +if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then echo "$ac_t""yes" 1>&6 - ISC=yes # If later tests want to check for ISC. - cat >> confdefs.h <<\EOF -#define _POSIX_SOURCE 1 -EOF - - if test "$GCC" = yes; then - CC="$CC -posix" - else - CC="$CC -Xp" - fi + LIBS="$LIBS -lcposix" else echo "$ac_t""no" 1>&6 - ISC= fi + + # We currently only use the version number for the name of any shared # library. For user convenience, we always use the same version @@ -991,7 +780,7 @@ BFD_VERSION=`sed -n -e 's/^.._INIT_AUTOMAKE.*,[ ]*\([^ ]*\)[ ]*).*/\1/p' < ${ # SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" # ./install, which can be erroneously created by make from ./install.sh. echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6 -echo "configure:995: checking for a BSD compatible install" >&5 +echo "configure:784: checking for a BSD compatible install" >&5 if test -z "$INSTALL"; then if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -1044,7 +833,7 @@ test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL_PROGRAM}' test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' echo $ac_n "checking whether build environment is sane""... $ac_c" 1>&6 -echo "configure:1048: checking whether build environment is sane" >&5 +echo "configure:837: checking whether build environment is sane" >&5 # Just in case sleep 1 echo timestamp > conftestfile @@ -1101,7 +890,7 @@ test "$program_suffix" != NONE && test "$program_transform_name" = "" && program_transform_name="s,x,x," echo $ac_n "checking whether ${MAKE-make} sets \${MAKE}""... $ac_c" 1>&6 -echo "configure:1105: checking whether ${MAKE-make} sets \${MAKE}" >&5 +echo "configure:894: checking whether ${MAKE-make} sets \${MAKE}" >&5 set dummy ${MAKE-make}; ac_make=`echo "$2" | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_prog_make_${ac_make}_set'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -1147,7 +936,7 @@ EOF missing_dir=`cd $ac_aux_dir && pwd` echo $ac_n "checking for working aclocal""... $ac_c" 1>&6 -echo "configure:1151: checking for working aclocal" >&5 +echo "configure:940: checking for working aclocal" >&5 # Run test in a subshell; some versions of sh will print an error if # an executable is not found, even if stderr is redirected. # Redirect stdin to placate older versions of autoconf. Sigh. @@ -1160,7 +949,7 @@ else fi echo $ac_n "checking for working autoconf""... $ac_c" 1>&6 -echo "configure:1164: checking for working autoconf" >&5 +echo "configure:953: checking for working autoconf" >&5 # Run test in a subshell; some versions of sh will print an error if # an executable is not found, even if stderr is redirected. # Redirect stdin to placate older versions of autoconf. Sigh. @@ -1173,7 +962,7 @@ else fi echo $ac_n "checking for working automake""... $ac_c" 1>&6 -echo "configure:1177: checking for working automake" >&5 +echo "configure:966: checking for working automake" >&5 # Run test in a subshell; some versions of sh will print an error if # an executable is not found, even if stderr is redirected. # Redirect stdin to placate older versions of autoconf. Sigh. @@ -1186,7 +975,7 @@ else fi echo $ac_n "checking for working autoheader""... $ac_c" 1>&6 -echo "configure:1190: checking for working autoheader" >&5 +echo "configure:979: checking for working autoheader" >&5 # Run test in a subshell; some versions of sh will print an error if # an executable is not found, even if stderr is redirected. # Redirect stdin to placate older versions of autoconf. Sigh. @@ -1199,7 +988,7 @@ else fi echo $ac_n "checking for working makeinfo""... $ac_c" 1>&6 -echo "configure:1203: checking for working makeinfo" >&5 +echo "configure:992: checking for working makeinfo" >&5 # Run test in a subshell; some versions of sh will print an error if # an executable is not found, even if stderr is redirected. # Redirect stdin to placate older versions of autoconf. Sigh. @@ -1222,7 +1011,7 @@ fi # Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args. set dummy ${ac_tool_prefix}ar; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1226: checking for $ac_word" >&5 +echo "configure:1015: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_AR'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1254,7 +1043,7 @@ fi # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. set dummy ${ac_tool_prefix}ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1258: checking for $ac_word" >&5 +echo "configure:1047: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1286,7 +1075,7 @@ if test -n "$ac_tool_prefix"; then # Extract the first word of "ranlib", so it can be a program name with args. set dummy ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1290: checking for $ac_word" >&5 +echo "configure:1079: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1323,7 +1112,7 @@ fi if test "${enable_shared+set}" = set; then enableval="$enable_shared" p=${PACKAGE-default} -case "$enableval" in +case $enableval in yes) enable_shared=yes ;; no) enable_shared=no ;; *) @@ -1347,7 +1136,7 @@ fi if test "${enable_static+set}" = set; then enableval="$enable_static" p=${PACKAGE-default} -case "$enableval" in +case $enableval in yes) enable_static=yes ;; no) enable_static=no ;; *) @@ -1370,7 +1159,7 @@ fi if test "${enable_fast_install+set}" = set; then enableval="$enable_fast_install" p=${PACKAGE-default} -case "$enableval" in +case $enableval in yes) enable_fast_install=yes ;; no) enable_fast_install=no ;; *) @@ -1389,6 +1178,228 @@ else enable_fast_install=yes fi +# Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1185: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_CC="gcc" + break + fi + done + IFS="$ac_save_ifs" +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1215: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_prog_rejected=no + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test "$ac_dir/$ac_word" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + break + fi + done + IFS="$ac_save_ifs" +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# -gt 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + set dummy "$ac_dir/$ac_word" "$@" + shift + ac_cv_prog_CC="$@" + fi +fi +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + if test -z "$CC"; then + case "`uname -s`" in + *win32* | *WIN32*) + # Extract the first word of "cl", so it can be a program name with args. +set dummy cl; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1266: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_CC="cl" + break + fi + done + IFS="$ac_save_ifs" +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + ;; + esac + fi + test -z "$CC" && { echo "configure: error: no acceptable cc found in \$PATH" 1>&2; exit 1; } +fi + +echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6 +echo "configure:1298: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 + +ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross + +cat > conftest.$ac_ext << EOF + +#line 1309 "configure" +#include "confdefs.h" + +main(){return(0);} +EOF +if { (eval echo configure:1314: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + ac_cv_prog_cc_works=yes + # If we can't run a trivial program, we are probably using a cross compiler. + if (./conftest; exit) 2>/dev/null; then + ac_cv_prog_cc_cross=no + else + ac_cv_prog_cc_cross=yes + fi +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + ac_cv_prog_cc_works=no +fi +rm -fr conftest* +ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross + +echo "$ac_t""$ac_cv_prog_cc_works" 1>&6 +if test $ac_cv_prog_cc_works = no; then + { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; } +fi +echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6 +echo "configure:1340: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 +echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6 +cross_compiling=$ac_cv_prog_cc_cross + +echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6 +echo "configure:1345: checking whether we are using GNU C" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.c <<EOF +#ifdef __GNUC__ + yes; +#endif +EOF +if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:1354: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then + ac_cv_prog_gcc=yes +else + ac_cv_prog_gcc=no +fi +fi + +echo "$ac_t""$ac_cv_prog_gcc" 1>&6 + +if test $ac_cv_prog_gcc = yes; then + GCC=yes +else + GCC= +fi + +ac_test_CFLAGS="${CFLAGS+set}" +ac_save_CFLAGS="$CFLAGS" +CFLAGS= +echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6 +echo "configure:1373: checking whether ${CC-cc} accepts -g" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + echo 'void f(){}' > conftest.c +if test -z "`${CC-cc} -g -c conftest.c 2>&1`"; then + ac_cv_prog_cc_g=yes +else + ac_cv_prog_cc_g=no +fi +rm -f conftest* + +fi + +echo "$ac_t""$ac_cv_prog_cc_g" 1>&6 +if test "$ac_test_CFLAGS" = set; then + CFLAGS="$ac_save_CFLAGS" +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi + # Check whether --with-gnu-ld or --without-gnu-ld was given. if test "${with_gnu_ld+set}" = set; then withval="$with_gnu_ld" @@ -1398,10 +1409,10 @@ else fi ac_prog=ld -if test "$ac_cv_prog_gcc" = yes; then +if test "$GCC" = yes; then # Check if gcc -print-prog-name=ld gives a path. echo $ac_n "checking for ld used by GCC""... $ac_c" 1>&6 -echo "configure:1405: checking for ld used by GCC" >&5 +echo "configure:1416: checking for ld used by GCC" >&5 case $host in *-*-mingw*) # gcc leaves a trailing carriage return which upsets mingw @@ -1409,7 +1420,7 @@ echo "configure:1405: checking for ld used by GCC" >&5 *) ac_prog=`($CC -print-prog-name=ld) 2>&5` ;; esac - case "$ac_prog" in + case $ac_prog in # Accept absolute paths. [\\/]* | [A-Za-z]:[\\/]*) re_direlt='/[^/][^/]*/\.\./' @@ -1431,12 +1442,12 @@ echo "configure:1405: checking for ld used by GCC" >&5 esac elif test "$with_gnu_ld" = yes; then echo $ac_n "checking for GNU ld""... $ac_c" 1>&6 -echo "configure:1435: checking for GNU ld" >&5 +echo "configure:1446: checking for GNU ld" >&5 else echo $ac_n "checking for non-GNU ld""... $ac_c" 1>&6 -echo "configure:1438: checking for non-GNU ld" >&5 +echo "configure:1449: checking for non-GNU ld" >&5 fi -if eval "test \"`echo '$''{'ac_cv_path_LD'+set}'`\" = set"; then +if eval "test \"`echo '$''{'lt_cv_path_LD'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else if test -z "$LD"; then @@ -1444,11 +1455,11 @@ else for ac_dir in $PATH; do test -z "$ac_dir" && ac_dir=. if test -f "$ac_dir/$ac_prog" || test -f "$ac_dir/$ac_prog$ac_exeext"; then - ac_cv_path_LD="$ac_dir/$ac_prog" + lt_cv_path_LD="$ac_dir/$ac_prog" # Check to see if the program is GNU ld. I'd rather use --version, # but apparently some GNU ld's only accept -v. # Break only if it was the GNU/non-GNU ld that we prefer. - if "$ac_cv_path_LD" -v 2>&1 < /dev/null | egrep '(GNU|with BFD)' > /dev/null; then + if "$lt_cv_path_LD" -v 2>&1 < /dev/null | egrep '(GNU|with BFD)' > /dev/null; then test "$with_gnu_ld" != no && break else test "$with_gnu_ld" != yes && break @@ -1457,11 +1468,11 @@ else done IFS="$ac_save_ifs" else - ac_cv_path_LD="$LD" # Let the user override the test with a path. + lt_cv_path_LD="$LD" # Let the user override the test with a path. fi fi -LD="$ac_cv_path_LD" +LD="$lt_cv_path_LD" if test -n "$LD"; then echo "$ac_t""$LD" 1>&6 else @@ -1469,24 +1480,24 @@ else fi test -z "$LD" && { echo "configure: error: no acceptable ld found in \$PATH" 1>&2; exit 1; } echo $ac_n "checking if the linker ($LD) is GNU ld""... $ac_c" 1>&6 -echo "configure:1473: checking if the linker ($LD) is GNU ld" >&5 -if eval "test \"`echo '$''{'ac_cv_prog_gnu_ld'+set}'`\" = set"; then +echo "configure:1484: checking if the linker ($LD) is GNU ld" >&5 +if eval "test \"`echo '$''{'lt_cv_prog_gnu_ld'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else # I'd rather use --version here, but apparently some GNU ld's only accept -v. if $LD -v 2>&1 </dev/null | egrep '(GNU|with BFD)' 1>&5; then - ac_cv_prog_gnu_ld=yes + lt_cv_prog_gnu_ld=yes else - ac_cv_prog_gnu_ld=no + lt_cv_prog_gnu_ld=no fi fi -echo "$ac_t""$ac_cv_prog_gnu_ld" 1>&6 -with_gnu_ld=$ac_cv_prog_gnu_ld +echo "$ac_t""$lt_cv_prog_gnu_ld" 1>&6 +with_gnu_ld=$lt_cv_prog_gnu_ld echo $ac_n "checking for $LD option to reload object files""... $ac_c" 1>&6 -echo "configure:1490: checking for $LD option to reload object files" >&5 +echo "configure:1501: checking for $LD option to reload object files" >&5 if eval "test \"`echo '$''{'lt_cv_ld_reload_flag'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1498,13 +1509,13 @@ reload_flag=$lt_cv_ld_reload_flag test -n "$reload_flag" && reload_flag=" $reload_flag" echo $ac_n "checking for BSD-compatible nm""... $ac_c" 1>&6 -echo "configure:1502: checking for BSD-compatible nm" >&5 -if eval "test \"`echo '$''{'ac_cv_path_NM'+set}'`\" = set"; then +echo "configure:1513: checking for BSD-compatible nm" >&5 +if eval "test \"`echo '$''{'lt_cv_path_NM'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else if test -n "$NM"; then # Let the user override the test. - ac_cv_path_NM="$NM" + lt_cv_path_NM="$NM" else IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS="${IFS}${PATH_SEPARATOR-:}" for ac_dir in $PATH /usr/ccs/bin /usr/ucb /bin; do @@ -1516,27 +1527,27 @@ else # nm: unknown option "B" ignored # Tru64's nm complains that /dev/null is an invalid object file if ($tmp_nm -B /dev/null 2>&1 | sed '1q'; exit 0) | egrep '(/dev/null|Invalid file or object type)' >/dev/null; then - ac_cv_path_NM="$tmp_nm -B" + lt_cv_path_NM="$tmp_nm -B" break elif ($tmp_nm -p /dev/null 2>&1 | sed '1q'; exit 0) | egrep /dev/null >/dev/null; then - ac_cv_path_NM="$tmp_nm -p" + lt_cv_path_NM="$tmp_nm -p" break else - ac_cv_path_NM=${ac_cv_path_NM="$tmp_nm"} # keep the first match, but + lt_cv_path_NM=${lt_cv_path_NM="$tmp_nm"} # keep the first match, but continue # so that we can try to find one that supports BSD flags fi fi done IFS="$ac_save_ifs" - test -z "$ac_cv_path_NM" && ac_cv_path_NM=nm + test -z "$lt_cv_path_NM" && lt_cv_path_NM=nm fi fi -NM="$ac_cv_path_NM" +NM="$lt_cv_path_NM" echo "$ac_t""$NM" 1>&6 echo $ac_n "checking whether ln -s works""... $ac_c" 1>&6 -echo "configure:1540: checking whether ln -s works" >&5 +echo "configure:1551: checking whether ln -s works" >&5 if eval "test \"`echo '$''{'ac_cv_prog_LN_S'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1557,7 +1568,7 @@ else fi echo $ac_n "checking how to recognise dependant libraries""... $ac_c" 1>&6 -echo "configure:1561: checking how to recognise dependant libraries" >&5 +echo "configure:1572: checking how to recognise dependant libraries" >&5 if eval "test \"`echo '$''{'lt_cv_deplibs_check_method'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1575,8 +1586,8 @@ lt_cv_deplibs_check_method='unknown' # If you have `file' or equivalent on your system and you're not sure # whether `pass_all' will *always* work, you probably want this one. -case "$host_os" in -aix4*) +case $host_os in +aix*) lt_cv_deplibs_check_method=pass_all ;; @@ -1585,8 +1596,8 @@ beos*) ;; bsdi4*) - lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib)' - lt_cv_file_magic_cmd='/usr/bin/file -L' + lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib)' + lt_cv_file_magic_cmd='/usr/bin/file -L' lt_cv_file_magic_test_file=/shlib/libc.so ;; @@ -1595,14 +1606,27 @@ cygwin* | mingw* |pw32*) lt_cv_file_magic_cmd='$OBJDUMP -f' ;; +darwin* | rhapsody*) + lt_cv_deplibs_check_method='file_magic Mach-O dynamically linked shared library' + lt_cv_file_magic_cmd='/usr/bin/file -L' + case "$host_os" in + rhapsody* | darwin1.012) + lt_cv_file_magic_test_file='/System/Library/Frameworks/System.framework/System' + ;; + *) # Darwin 1.3 on + lt_cv_file_magic_test_file='/usr/lib/libSystem.dylib' + ;; + esac + ;; + freebsd* ) if echo __ELF__ | $CC -E - | grep __ELF__ > /dev/null; then - case "$host_cpu" in + case $host_cpu in i*86 ) # Not sure whether the presence of OpenBSD here was a mistake. # Let's accept both of them until this is cleared up. - lt_cv_deplibs_check_method='file_magic (FreeBSD|OpenBSD)/i[3-9]86 (compact )?demand paged shared library' - lt_cv_file_magic_cmd=/usr/bin/file + lt_cv_deplibs_check_method='file_magic (FreeBSD|OpenBSD)/i[3-9]86 (compact )?demand paged shared library' + lt_cv_file_magic_cmd=/usr/bin/file lt_cv_file_magic_test_file=`echo /usr/lib/libc.so.*` ;; esac @@ -1615,29 +1639,28 @@ gnu*) lt_cv_deplibs_check_method=pass_all ;; -hpux10.20*) - # TODO: Does this work for hpux-11 too? - lt_cv_deplibs_check_method='file_magic (s0-90-90-9|PA-RISC0-9.0-9) shared library' +hpux10.20*|hpux11*) + lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|PA-RISC[0-9].[0-9]) shared library' lt_cv_file_magic_cmd=/usr/bin/file lt_cv_file_magic_test_file=/usr/lib/libc.sl ;; irix5* | irix6*) - case "$host_os" in + case $host_os in irix5*) # this will be overridden with pass_all, but let us keep it just in case lt_cv_deplibs_check_method="file_magic ELF 32-bit MSB dynamic lib MIPS - version 1" ;; *) - case "$LD" in + case $LD in *-32|*"-32 ") libmagic=32-bit;; *-n32|*"-n32 ") libmagic=N32;; *-64|*"-64 ") libmagic=64-bit;; *) libmagic=never-match;; esac # this will be overridden with pass_all, but let us keep it just in case - lt_cv_deplibs_check_method="file_magic ELF ${libmagic} MSB mips-[1234] dynamic lib MIPS - version 1" - ;; + lt_cv_deplibs_check_method="file_magic ELF ${libmagic} MSB mips-[1234] dynamic lib MIPS - version 1" + ;; esac lt_cv_file_magic_test_file=`echo /lib${libsuff}/libc.so*` lt_cv_deplibs_check_method=pass_all @@ -1645,25 +1668,30 @@ irix5* | irix6*) # This must be Linux ELF. linux-gnu*) - case "$host_cpu" in - alpha* | i*86 | powerpc* | sparc* | ia64* ) + case $host_cpu in + alpha* | hppa* | i*86 | powerpc* | sparc* | ia64* ) lt_cv_deplibs_check_method=pass_all ;; *) # glibc up to 2.1.1 does not perform some relocations on ARM - lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [LM]SB (shared object|dynamic lib )' ;; - esac + lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [LM]SB (shared object|dynamic lib )' ;; + esac lt_cv_file_magic_test_file=`echo /lib/libc.so* /lib/libc-*.so` ;; netbsd*) - if echo __ELF__ | $CC -E - | grep __ELF__ > /dev/null; then : + if echo __ELF__ | $CC -E - | grep __ELF__ > /dev/null; then + lt_cv_deplibs_check_method='match_pattern /lib[^/\.]+\.so\.[0-9]+\.[0-9]+$' else - lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [LM]SB shared object' - lt_cv_file_magic_cmd='/usr/bin/file -L' - lt_cv_file_magic_test_file=`echo /usr/lib/libc.so*` + lt_cv_deplibs_check_method='match_pattern /lib[^/\.]+\.so$' fi ;; +newsos6) + lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (executable|dynamic lib)' + lt_cv_file_magic_cmd=/usr/bin/file + lt_cv_file_magic_test_file=/usr/lib/libnls.so + ;; + osf3* | osf4* | osf5*) # this will be overridden with pass_all, but let us keep it just in case lt_cv_deplibs_check_method='file_magic COFF format alpha shared library' @@ -1680,14 +1708,18 @@ solaris*) lt_cv_file_magic_test_file=/lib/libc.so ;; +sysv5uw[78]* | sysv4*uw2*) + lt_cv_deplibs_check_method=pass_all + ;; + sysv4 | sysv4.2uw2* | sysv4.3* | sysv5*) - case "$host_vendor" in + case $host_vendor in ncr) lt_cv_deplibs_check_method=pass_all ;; motorola) - lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib) M[0-9][0-9]* Version [0-9]' - lt_cv_file_magic_test_file=`echo /usr/lib/libc.so*` + lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib) M[0-9][0-9]* Version [0-9]' + lt_cv_file_magic_test_file=`echo /usr/lib/libc.so*` ;; esac ;; @@ -1700,13 +1732,13 @@ file_magic_cmd=$lt_cv_file_magic_cmd deplibs_check_method=$lt_cv_deplibs_check_method echo $ac_n "checking for object suffix""... $ac_c" 1>&6 -echo "configure:1704: checking for object suffix" >&5 +echo "configure:1736: checking for object suffix" >&5 if eval "test \"`echo '$''{'ac_cv_objext'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else rm -f conftest* echo 'int i = 1;' > conftest.$ac_ext -if { (eval echo configure:1710: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:1742: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then for ac_file in conftest.*; do case $ac_file in *.c) ;; @@ -1726,7 +1758,7 @@ ac_objext=$ac_cv_objext echo $ac_n "checking for executable suffix""... $ac_c" 1>&6 -echo "configure:1730: checking for executable suffix" >&5 +echo "configure:1762: checking for executable suffix" >&5 if eval "test \"`echo '$''{'ac_cv_exeext'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1736,10 +1768,10 @@ else rm -f conftest* echo 'int main () { return 0; }' > conftest.$ac_ext ac_cv_exeext= - if { (eval echo configure:1740: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then + if { (eval echo configure:1772: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then for file in conftest.*; do case $file in - *.c | *.o | *.obj | *.ilk | *.pdb) ;; + *.c | *.o | *.obj) ;; *) ac_cv_exeext=`echo $file | sed -e s/conftest//` ;; esac done @@ -1759,15 +1791,15 @@ ac_exeext=$EXEEXT # Autoconf 2.13's AC_OBJEXT and AC_EXEEXT macros only works for C compilers! # Only perform the check for file, if the check method requires it -case "$deplibs_check_method" in +case $deplibs_check_method in file_magic*) if test "$file_magic_cmd" = '$MAGIC_CMD'; then echo $ac_n "checking for ${ac_tool_prefix}file""... $ac_c" 1>&6 -echo "configure:1767: checking for ${ac_tool_prefix}file" >&5 +echo "configure:1799: checking for ${ac_tool_prefix}file" >&5 if eval "test \"`echo '$''{'lt_cv_path_MAGIC_CMD'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else - case "$MAGIC_CMD" in + case $MAGIC_CMD in /*) lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path. ;; @@ -1783,7 +1815,7 @@ else if test -f $ac_dir/${ac_tool_prefix}file; then lt_cv_path_MAGIC_CMD="$ac_dir/${ac_tool_prefix}file" if test -n "$file_magic_test_file"; then - case "$deplibs_check_method" in + case $deplibs_check_method in "file_magic "*) file_magic_regex="`expr \"$deplibs_check_method\" : \"file_magic \(.*\)\"`" MAGIC_CMD="$lt_cv_path_MAGIC_CMD" @@ -1825,11 +1857,11 @@ fi if test -z "$lt_cv_path_MAGIC_CMD"; then if test -n "$ac_tool_prefix"; then echo $ac_n "checking for file""... $ac_c" 1>&6 -echo "configure:1829: checking for file" >&5 +echo "configure:1861: checking for file" >&5 if eval "test \"`echo '$''{'lt_cv_path_MAGIC_CMD'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else - case "$MAGIC_CMD" in + case $MAGIC_CMD in /*) lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path. ;; @@ -1845,7 +1877,7 @@ else if test -f $ac_dir/file; then lt_cv_path_MAGIC_CMD="$ac_dir/file" if test -n "$file_magic_test_file"; then - case "$deplibs_check_method" in + case $deplibs_check_method in "file_magic "*) file_magic_regex="`expr \"$deplibs_check_method\" : \"file_magic \(.*\)\"`" MAGIC_CMD="$lt_cv_path_MAGIC_CMD" @@ -1896,7 +1928,7 @@ esac # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. set dummy ${ac_tool_prefix}ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1900: checking for $ac_word" >&5 +echo "configure:1932: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1928,7 +1960,7 @@ if test -n "$ac_tool_prefix"; then # Extract the first word of "ranlib", so it can be a program name with args. set dummy ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1932: checking for $ac_word" >&5 +echo "configure:1964: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1963,7 +1995,7 @@ fi # Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args. set dummy ${ac_tool_prefix}strip; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1967: checking for $ac_word" >&5 +echo "configure:1999: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_STRIP'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1995,7 +2027,7 @@ if test -n "$ac_tool_prefix"; then # Extract the first word of "strip", so it can be a program name with args. set dummy strip; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1999: checking for $ac_word" >&5 +echo "configure:2031: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_STRIP'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2033,8 +2065,8 @@ libtool_flags="--cache-file=$cache_file" test "$enable_shared" = no && libtool_flags="$libtool_flags --disable-shared" test "$enable_static" = no && libtool_flags="$libtool_flags --disable-static" test "$enable_fast_install" = no && libtool_flags="$libtool_flags --disable-fast-install" -test "$ac_cv_prog_gcc" = yes && libtool_flags="$libtool_flags --with-gcc" -test "$ac_cv_prog_gnu_ld" = yes && libtool_flags="$libtool_flags --with-gnu-ld" +test "$GCC" = yes && libtool_flags="$libtool_flags --with-gcc" +test "$lt_cv_prog_gnu_ld" = yes && libtool_flags="$libtool_flags --with-gnu-ld" # Check whether --enable-libtool-lock or --disable-libtool-lock was given. @@ -2059,12 +2091,12 @@ test x"$pic_mode" = xno && libtool_flags="$libtool_flags --prefer-non-pic" # Some flags need to be propagated to the compiler or linker for good # libtool support. -case "$host" in +case $host in *-*-irix6*) # Find out which ABI we are using. - echo '#line 2066 "configure"' > conftest.$ac_ext - if { (eval echo configure:2067: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then - case "`/usr/bin/file conftest.o`" in + echo '#line 2098 "configure"' > conftest.$ac_ext + if { (eval echo configure:2099: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then + case `/usr/bin/file conftest.$ac_objext` in *32-bit*) LD="${LD-ld} -32" ;; @@ -2084,7 +2116,7 @@ case "$host" in SAVE_CFLAGS="$CFLAGS" CFLAGS="$CFLAGS -belf" echo $ac_n "checking whether the C compiler needs -belf""... $ac_c" 1>&6 -echo "configure:2088: checking whether the C compiler needs -belf" >&5 +echo "configure:2120: checking whether the C compiler needs -belf" >&5 if eval "test \"`echo '$''{'lt_cv_cc_needs_belf'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2097,14 +2129,14 @@ ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$a cross_compiling=$ac_cv_prog_cc_cross cat > conftest.$ac_ext <<EOF -#line 2101 "configure" +#line 2133 "configure" #include "confdefs.h" int main() { ; return 0; } EOF -if { (eval echo configure:2108: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:2140: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* lt_cv_cc_needs_belf=yes else @@ -2214,7 +2246,6 @@ LIBTOOL='$(SHELL) $(top_builddir)/libtool' # clobbered by the next message. exec 5>>./config.log - @@ -2241,7 +2272,7 @@ if test "${enable_commonbfdlib+set}" = set; then esac fi -build_warnings="-W -Wall" +build_warnings="-W -Wall -Wstrict-prototypes -Wmissing-prototypes" # Check whether --enable-build-warnings or --disable-build-warnings was given. if test "${enable_build_warnings+set}" = set; then enableval="$enable_build_warnings" @@ -2271,28 +2302,9 @@ fi if test -z "$target" ; then { echo "configure: error: Unrecognized target system type; please check config.sub." 1>&2; exit 1; } fi -if test "$program_transform_name" = s,x,x,; then - program_transform_name= -else - # Double any \ or $. echo might interpret backslashes. - cat <<\EOF_SED > conftestsed -s,\\,\\\\,g; s,\$,$$,g -EOF_SED - program_transform_name="`echo $program_transform_name|sed -f conftestsed`" - rm -f conftestsed -fi -test "$program_prefix" != NONE && - program_transform_name="s,^,${program_prefix},; $program_transform_name" -# Use a double $ so make ignores it. -test "$program_suffix" != NONE && - program_transform_name="s,\$\$,${program_suffix},; $program_transform_name" - -# sed with no file args requires a program. -test "$program_transform_name" = "" && program_transform_name="s,x,x," - echo $ac_n "checking whether to enable maintainer-specific portions of Makefiles""... $ac_c" 1>&6 -echo "configure:2296: checking whether to enable maintainer-specific portions of Makefiles" >&5 +echo "configure:2308: checking whether to enable maintainer-specific portions of Makefiles" >&5 # Check whether --enable-maintainer-mode or --disable-maintainer-mode was given. if test "${enable_maintainer_mode+set}" = set; then enableval="$enable_maintainer_mode" @@ -2317,7 +2329,7 @@ fi echo $ac_n "checking for executable suffix""... $ac_c" 1>&6 -echo "configure:2321: checking for executable suffix" >&5 +echo "configure:2333: checking for executable suffix" >&5 if eval "test \"`echo '$''{'ac_cv_exeext'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2327,10 +2339,10 @@ else rm -f conftest* echo 'int main () { return 0; }' > conftest.$ac_ext ac_cv_exeext= - if { (eval echo configure:2331: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then + if { (eval echo configure:2343: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then for file in conftest.*; do case $file in - *.c | *.o | *.obj | *.ilk | *.pdb) ;; + *.c | *.o | *.obj) ;; *) ac_cv_exeext=`echo $file | sed -e s/conftest//` ;; esac done @@ -2353,7 +2365,7 @@ ac_exeext=$EXEEXT # Extract the first word of "gcc", so it can be a program name with args. set dummy gcc; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2357: checking for $ac_word" >&5 +echo "configure:2369: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2383,7 +2395,7 @@ if test -z "$CC"; then # Extract the first word of "cc", so it can be a program name with args. set dummy cc; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2387: checking for $ac_word" >&5 +echo "configure:2399: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2434,7 +2446,7 @@ fi # Extract the first word of "cl", so it can be a program name with args. set dummy cl; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2438: checking for $ac_word" >&5 +echo "configure:2450: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2466,7 +2478,7 @@ fi fi echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6 -echo "configure:2470: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 +echo "configure:2482: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 ac_ext=c # CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. @@ -2477,12 +2489,12 @@ cross_compiling=$ac_cv_prog_cc_cross cat > conftest.$ac_ext << EOF -#line 2481 "configure" +#line 2493 "configure" #include "confdefs.h" main(){return(0);} EOF -if { (eval echo configure:2486: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:2498: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then ac_cv_prog_cc_works=yes # If we can't run a trivial program, we are probably using a cross compiler. if (./conftest; exit) 2>/dev/null; then @@ -2508,12 +2520,12 @@ if test $ac_cv_prog_cc_works = no; then { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; } fi echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6 -echo "configure:2512: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 +echo "configure:2524: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6 cross_compiling=$ac_cv_prog_cc_cross echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6 -echo "configure:2517: checking whether we are using GNU C" >&5 +echo "configure:2529: checking whether we are using GNU C" >&5 if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2522,7 +2534,7 @@ else yes; #endif EOF -if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:2526: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then +if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:2538: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then ac_cv_prog_gcc=yes else ac_cv_prog_gcc=no @@ -2541,7 +2553,7 @@ ac_test_CFLAGS="${CFLAGS+set}" ac_save_CFLAGS="$CFLAGS" CFLAGS= echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6 -echo "configure:2545: checking whether ${CC-cc} accepts -g" >&5 +echo "configure:2557: checking whether ${CC-cc} accepts -g" >&5 if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2573,9 +2585,9 @@ else fi -ALL_LINGUAS= +ALL_LINGUAS="fr sv tr es da" echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6 -echo "configure:2579: checking how to run the C preprocessor" >&5 +echo "configure:2591: checking how to run the C preprocessor" >&5 # On Suns, sometimes $CPP names a directory. if test -n "$CPP" && test -d "$CPP"; then CPP= @@ -2590,13 +2602,13 @@ else # On the NeXT, cc -E runs the code through the compiler's parser, # not just through cpp. cat > conftest.$ac_ext <<EOF -#line 2594 "configure" +#line 2606 "configure" #include "confdefs.h" #include <assert.h> Syntax Error EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2600: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:2612: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then : @@ -2607,13 +2619,13 @@ else rm -rf conftest* CPP="${CC-cc} -E -traditional-cpp" cat > conftest.$ac_ext <<EOF -#line 2611 "configure" +#line 2623 "configure" #include "confdefs.h" #include <assert.h> Syntax Error EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2617: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:2629: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then : @@ -2624,13 +2636,13 @@ else rm -rf conftest* CPP="${CC-cc} -nologo -E" cat > conftest.$ac_ext <<EOF -#line 2628 "configure" +#line 2640 "configure" #include "confdefs.h" #include <assert.h> Syntax Error EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2634: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:2646: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then : @@ -2657,7 +2669,7 @@ echo "$ac_t""$CPP" 1>&6 # Extract the first word of "ranlib", so it can be a program name with args. set dummy ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2661: checking for $ac_word" >&5 +echo "configure:2673: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2685,12 +2697,12 @@ else fi echo $ac_n "checking for ANSI C header files""... $ac_c" 1>&6 -echo "configure:2689: checking for ANSI C header files" >&5 +echo "configure:2701: checking for ANSI C header files" >&5 if eval "test \"`echo '$''{'ac_cv_header_stdc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2694 "configure" +#line 2706 "configure" #include "confdefs.h" #include <stdlib.h> #include <stdarg.h> @@ -2698,7 +2710,7 @@ else #include <float.h> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2702: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:2714: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -2715,7 +2727,7 @@ rm -f conftest* if test $ac_cv_header_stdc = yes; then # SunOS 4.x string.h does not declare mem*, contrary to ANSI. cat > conftest.$ac_ext <<EOF -#line 2719 "configure" +#line 2731 "configure" #include "confdefs.h" #include <string.h> EOF @@ -2733,7 +2745,7 @@ fi if test $ac_cv_header_stdc = yes; then # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. cat > conftest.$ac_ext <<EOF -#line 2737 "configure" +#line 2749 "configure" #include "confdefs.h" #include <stdlib.h> EOF @@ -2754,7 +2766,7 @@ if test "$cross_compiling" = yes; then : else cat > conftest.$ac_ext <<EOF -#line 2758 "configure" +#line 2770 "configure" #include "confdefs.h" #include <ctype.h> #define ISLOWER(c) ('a' <= (c) && (c) <= 'z') @@ -2765,7 +2777,7 @@ if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) exit(2); exit (0); } EOF -if { (eval echo configure:2769: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +if { (eval echo configure:2781: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null then : else @@ -2789,12 +2801,12 @@ EOF fi echo $ac_n "checking for working const""... $ac_c" 1>&6 -echo "configure:2793: checking for working const" >&5 +echo "configure:2805: checking for working const" >&5 if eval "test \"`echo '$''{'ac_cv_c_const'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2798 "configure" +#line 2810 "configure" #include "confdefs.h" int main() { @@ -2843,7 +2855,7 @@ ccp = (char const *const *) p; ; return 0; } EOF -if { (eval echo configure:2847: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:2859: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* ac_cv_c_const=yes else @@ -2864,21 +2876,21 @@ EOF fi echo $ac_n "checking for inline""... $ac_c" 1>&6 -echo "configure:2868: checking for inline" >&5 +echo "configure:2880: checking for inline" >&5 if eval "test \"`echo '$''{'ac_cv_c_inline'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else ac_cv_c_inline=no for ac_kw in inline __inline__ __inline; do cat > conftest.$ac_ext <<EOF -#line 2875 "configure" +#line 2887 "configure" #include "confdefs.h" int main() { } $ac_kw foo() { ; return 0; } EOF -if { (eval echo configure:2882: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:2894: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* ac_cv_c_inline=$ac_kw; break else @@ -2904,12 +2916,12 @@ EOF esac echo $ac_n "checking for off_t""... $ac_c" 1>&6 -echo "configure:2908: checking for off_t" >&5 +echo "configure:2920: checking for off_t" >&5 if eval "test \"`echo '$''{'ac_cv_type_off_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2913 "configure" +#line 2925 "configure" #include "confdefs.h" #include <sys/types.h> #if STDC_HEADERS @@ -2937,12 +2949,12 @@ EOF fi echo $ac_n "checking for size_t""... $ac_c" 1>&6 -echo "configure:2941: checking for size_t" >&5 +echo "configure:2953: checking for size_t" >&5 if eval "test \"`echo '$''{'ac_cv_type_size_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2946 "configure" +#line 2958 "configure" #include "confdefs.h" #include <sys/types.h> #if STDC_HEADERS @@ -2972,19 +2984,19 @@ fi # The Ultrix 4.2 mips builtin alloca declared by alloca.h only works # for constant arguments. Useless! echo $ac_n "checking for working alloca.h""... $ac_c" 1>&6 -echo "configure:2976: checking for working alloca.h" >&5 +echo "configure:2988: checking for working alloca.h" >&5 if eval "test \"`echo '$''{'ac_cv_header_alloca_h'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2981 "configure" +#line 2993 "configure" #include "confdefs.h" #include <alloca.h> int main() { char *p = alloca(2 * sizeof(int)); ; return 0; } EOF -if { (eval echo configure:2988: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3000: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* ac_cv_header_alloca_h=yes else @@ -3005,12 +3017,12 @@ EOF fi echo $ac_n "checking for alloca""... $ac_c" 1>&6 -echo "configure:3009: checking for alloca" >&5 +echo "configure:3021: checking for alloca" >&5 if eval "test \"`echo '$''{'ac_cv_func_alloca_works'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3014 "configure" +#line 3026 "configure" #include "confdefs.h" #ifdef __GNUC__ @@ -3038,7 +3050,7 @@ int main() { char *p = (char *) alloca(1); ; return 0; } EOF -if { (eval echo configure:3042: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3054: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* ac_cv_func_alloca_works=yes else @@ -3070,12 +3082,12 @@ EOF echo $ac_n "checking whether alloca needs Cray hooks""... $ac_c" 1>&6 -echo "configure:3074: checking whether alloca needs Cray hooks" >&5 +echo "configure:3086: checking whether alloca needs Cray hooks" >&5 if eval "test \"`echo '$''{'ac_cv_os_cray'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3079 "configure" +#line 3091 "configure" #include "confdefs.h" #if defined(CRAY) && ! defined(CRAY2) webecray @@ -3100,12 +3112,12 @@ echo "$ac_t""$ac_cv_os_cray" 1>&6 if test $ac_cv_os_cray = yes; then for ac_func in _getb67 GETB67 getb67; do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:3104: checking for $ac_func" >&5 +echo "configure:3116: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3109 "configure" +#line 3121 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -3128,7 +3140,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:3132: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3144: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -3155,7 +3167,7 @@ done fi echo $ac_n "checking stack direction for C alloca""... $ac_c" 1>&6 -echo "configure:3159: checking stack direction for C alloca" >&5 +echo "configure:3171: checking stack direction for C alloca" >&5 if eval "test \"`echo '$''{'ac_cv_c_stack_direction'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3163,7 +3175,7 @@ else ac_cv_c_stack_direction=0 else cat > conftest.$ac_ext <<EOF -#line 3167 "configure" +#line 3179 "configure" #include "confdefs.h" find_stack_direction () { @@ -3182,7 +3194,7 @@ main () exit (find_stack_direction() < 0); } EOF -if { (eval echo configure:3186: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +if { (eval echo configure:3198: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null then ac_cv_c_stack_direction=1 else @@ -3203,21 +3215,21 @@ EOF fi -for ac_hdr in unistd.h +for ac_hdr in stdlib.h unistd.h sys/stat.h sys/types.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:3211: checking for $ac_hdr" >&5 +echo "configure:3223: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3216 "configure" +#line 3228 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:3221: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:3233: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -3246,12 +3258,12 @@ done for ac_func in getpagesize do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:3250: checking for $ac_func" >&5 +echo "configure:3262: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3255 "configure" +#line 3267 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -3274,7 +3286,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:3278: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3290: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -3299,7 +3311,7 @@ fi done echo $ac_n "checking for working mmap""... $ac_c" 1>&6 -echo "configure:3303: checking for working mmap" >&5 +echo "configure:3315: checking for working mmap" >&5 if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3307,7 +3319,7 @@ else ac_cv_func_mmap_fixed_mapped=no else cat > conftest.$ac_ext <<EOF -#line 3311 "configure" +#line 3323 "configure" #include "confdefs.h" /* Thanks to Mike Haertel and Jim Avera for this test. @@ -3335,11 +3347,24 @@ else #include <fcntl.h> #include <sys/mman.h> +#if HAVE_SYS_TYPES_H +# include <sys/types.h> +#endif + +#if HAVE_STDLIB_H +# include <stdlib.h> +#endif + +#if HAVE_SYS_STAT_H +# include <sys/stat.h> +#endif + +#if HAVE_UNISTD_H +# include <unistd.h> +#endif + /* This mess was copied from the GNU getpagesize.h. */ #ifndef HAVE_GETPAGESIZE -# ifdef HAVE_UNISTD_H -# include <unistd.h> -# endif /* Assume that all systems that can run configure have sys/param.h. */ # ifndef HAVE_SYS_PARAM_H @@ -3447,7 +3472,7 @@ main() } EOF -if { (eval echo configure:3451: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +if { (eval echo configure:3476: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null then ac_cv_func_mmap_fixed_mapped=yes else @@ -3475,17 +3500,17 @@ unistd.h values.h sys/param.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:3479: checking for $ac_hdr" >&5 +echo "configure:3504: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3484 "configure" +#line 3509 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:3489: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:3514: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -3515,12 +3540,12 @@ done __argz_count __argz_stringify __argz_next do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:3519: checking for $ac_func" >&5 +echo "configure:3544: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3524 "configure" +#line 3549 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -3543,7 +3568,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:3547: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3572: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -3572,12 +3597,12 @@ done for ac_func in stpcpy do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:3576: checking for $ac_func" >&5 +echo "configure:3601: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3581 "configure" +#line 3606 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -3600,7 +3625,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:3604: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3629: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -3634,19 +3659,19 @@ EOF if test $ac_cv_header_locale_h = yes; then echo $ac_n "checking for LC_MESSAGES""... $ac_c" 1>&6 -echo "configure:3638: checking for LC_MESSAGES" >&5 +echo "configure:3663: checking for LC_MESSAGES" >&5 if eval "test \"`echo '$''{'am_cv_val_LC_MESSAGES'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3643 "configure" +#line 3668 "configure" #include "confdefs.h" #include <locale.h> int main() { return LC_MESSAGES ; return 0; } EOF -if { (eval echo configure:3650: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3675: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* am_cv_val_LC_MESSAGES=yes else @@ -3667,7 +3692,7 @@ EOF fi fi echo $ac_n "checking whether NLS is requested""... $ac_c" 1>&6 -echo "configure:3671: checking whether NLS is requested" >&5 +echo "configure:3696: checking whether NLS is requested" >&5 # Check whether --enable-nls or --disable-nls was given. if test "${enable_nls+set}" = set; then enableval="$enable_nls" @@ -3687,7 +3712,7 @@ fi EOF echo $ac_n "checking whether included gettext is requested""... $ac_c" 1>&6 -echo "configure:3691: checking whether included gettext is requested" >&5 +echo "configure:3716: checking whether included gettext is requested" >&5 # Check whether --with-included-gettext or --without-included-gettext was given. if test "${with_included_gettext+set}" = set; then withval="$with_included_gettext" @@ -3706,17 +3731,17 @@ fi ac_safe=`echo "libintl.h" | sed 'y%./+-%__p_%'` echo $ac_n "checking for libintl.h""... $ac_c" 1>&6 -echo "configure:3710: checking for libintl.h" >&5 +echo "configure:3735: checking for libintl.h" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3715 "configure" +#line 3740 "configure" #include "confdefs.h" #include <libintl.h> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:3720: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:3745: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -3733,19 +3758,19 @@ fi if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then echo "$ac_t""yes" 1>&6 echo $ac_n "checking for gettext in libc""... $ac_c" 1>&6 -echo "configure:3737: checking for gettext in libc" >&5 +echo "configure:3762: checking for gettext in libc" >&5 if eval "test \"`echo '$''{'gt_cv_func_gettext_libc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3742 "configure" +#line 3767 "configure" #include "confdefs.h" #include <libintl.h> int main() { return (int) gettext ("") ; return 0; } EOF -if { (eval echo configure:3749: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3774: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* gt_cv_func_gettext_libc=yes else @@ -3761,7 +3786,7 @@ echo "$ac_t""$gt_cv_func_gettext_libc" 1>&6 if test "$gt_cv_func_gettext_libc" != "yes"; then echo $ac_n "checking for bindtextdomain in -lintl""... $ac_c" 1>&6 -echo "configure:3765: checking for bindtextdomain in -lintl" >&5 +echo "configure:3790: checking for bindtextdomain in -lintl" >&5 ac_lib_var=`echo intl'_'bindtextdomain | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -3769,7 +3794,7 @@ else ac_save_LIBS="$LIBS" LIBS="-lintl $LIBS" cat > conftest.$ac_ext <<EOF -#line 3773 "configure" +#line 3798 "configure" #include "confdefs.h" /* Override any gcc2 internal prototype to avoid an error. */ /* We use char because int might match the return type of a gcc2 @@ -3780,7 +3805,7 @@ int main() { bindtextdomain() ; return 0; } EOF -if { (eval echo configure:3784: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3809: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -3796,19 +3821,19 @@ fi if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then echo "$ac_t""yes" 1>&6 echo $ac_n "checking for gettext in libintl""... $ac_c" 1>&6 -echo "configure:3800: checking for gettext in libintl" >&5 +echo "configure:3825: checking for gettext in libintl" >&5 if eval "test \"`echo '$''{'gt_cv_func_gettext_libintl'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3805 "configure" +#line 3830 "configure" #include "confdefs.h" int main() { return (int) gettext ("") ; return 0; } EOF -if { (eval echo configure:3812: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3837: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* gt_cv_func_gettext_libintl=yes else @@ -3836,7 +3861,7 @@ EOF # Extract the first word of "msgfmt", so it can be a program name with args. set dummy msgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3840: checking for $ac_word" >&5 +echo "configure:3865: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3870,12 +3895,12 @@ fi for ac_func in dcgettext do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:3874: checking for $ac_func" >&5 +echo "configure:3899: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3879 "configure" +#line 3904 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -3898,7 +3923,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:3902: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3927: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -3925,7 +3950,7 @@ done # Extract the first word of "gmsgfmt", so it can be a program name with args. set dummy gmsgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3929: checking for $ac_word" >&5 +echo "configure:3954: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3961,7 +3986,7 @@ fi # Extract the first word of "xgettext", so it can be a program name with args. set dummy xgettext; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3965: checking for $ac_word" >&5 +echo "configure:3990: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3993,7 +4018,7 @@ else fi cat > conftest.$ac_ext <<EOF -#line 3997 "configure" +#line 4022 "configure" #include "confdefs.h" int main() { @@ -4001,7 +4026,7 @@ extern int _nl_msg_cat_cntr; return _nl_msg_cat_cntr ; return 0; } EOF -if { (eval echo configure:4005: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4030: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* CATOBJEXT=.gmo DATADIRNAME=share @@ -4033,7 +4058,7 @@ fi # Extract the first word of "msgfmt", so it can be a program name with args. set dummy msgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4037: checking for $ac_word" >&5 +echo "configure:4062: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4067,7 +4092,7 @@ fi # Extract the first word of "gmsgfmt", so it can be a program name with args. set dummy gmsgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4071: checking for $ac_word" >&5 +echo "configure:4096: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4103,7 +4128,7 @@ fi # Extract the first word of "xgettext", so it can be a program name with args. set dummy xgettext; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4107: checking for $ac_word" >&5 +echo "configure:4132: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4193,7 +4218,7 @@ fi LINGUAS= else echo $ac_n "checking for catalogs to be installed""... $ac_c" 1>&6 -echo "configure:4197: checking for catalogs to be installed" >&5 +echo "configure:4222: checking for catalogs to be installed" >&5 NEW_LINGUAS= for lang in ${LINGUAS=$ALL_LINGUAS}; do case "$ALL_LINGUAS" in @@ -4221,17 +4246,17 @@ echo "configure:4197: checking for catalogs to be installed" >&5 if test "$CATOBJEXT" = ".cat"; then ac_safe=`echo "linux/version.h" | sed 'y%./+-%__p_%'` echo $ac_n "checking for linux/version.h""... $ac_c" 1>&6 -echo "configure:4225: checking for linux/version.h" >&5 +echo "configure:4250: checking for linux/version.h" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 4230 "configure" +#line 4255 "configure" #include "confdefs.h" #include <linux/version.h> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:4235: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:4260: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -4276,7 +4301,7 @@ fi l= - if test -d $srcdir/po; then + if test -f $srcdir/po/POTFILES.in; then test -d po || mkdir po if test "x$srcdir" != "x."; then if test "x`echo $srcdir | sed 's@/.*@@'`" = "x"; then @@ -4295,6 +4320,44 @@ fi . ${srcdir}/../bfd/configure.host +# Put a plausible default for CC_FOR_BUILD in Makefile. +if test -z "$CC_FOR_BUILD"; then + if test "x$cross_compiling" = "xno"; then + CC_FOR_BUILD='$(CC)' + else + CC_FOR_BUILD=gcc + fi +fi + +# Also set EXEEXT_FOR_BUILD. +if test "x$cross_compiling" = "xno"; then + EXEEXT_FOR_BUILD='$(EXEEXT)' +else + echo $ac_n "checking for build system executable suffix""... $ac_c" 1>&6 +echo "configure:4338: checking for build system executable suffix" >&5 +if eval "test \"`echo '$''{'bfd_cv_build_exeext'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + rm -f conftest* + echo 'int main () { return 0; }' > conftest.c + bfd_cv_build_exeext= + ${CC_FOR_BUILD} -o conftest conftest.c 1>&5 2>&5 + for file in conftest.*; do + case $file in + *.c | *.o | *.obj | *.ilk | *.pdb) ;; + *) bfd_cv_build_exeext=`echo $file | sed -e s/conftest//` ;; + esac + done + rm -f conftest* + test x"${bfd_cv_build_exeext}" = x && bfd_cv_build_exeext=no +fi + +echo "$ac_t""$bfd_cv_build_exeext" 1>&6 + EXEEXT_FOR_BUILD="" + test x"${bfd_cv_build_exeext}" != xno && EXEEXT_FOR_BUILD=${bfd_cv_build_exeext} +fi + + # Find a good install program. We prefer a C program (faster), # so one script is as good as another. But avoid the broken or @@ -4308,7 +4371,7 @@ fi # SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" # ./install, which can be erroneously created by make from ./install.sh. echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6 -echo "configure:4312: checking for a BSD compatible install" >&5 +echo "configure:4375: checking for a BSD compatible install" >&5 if test -z "$INSTALL"; then if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -4365,17 +4428,17 @@ for ac_hdr in string.h strings.h stdlib.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:4369: checking for $ac_hdr" >&5 +echo "configure:4432: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 4374 "configure" +#line 4437 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:4379: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:4442: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -4517,15 +4580,19 @@ if test x${all_targets} = xfalse ; then bfd_m88k_arch) ta="$ta m88k-dis.lo" ;; bfd_mcore_arch) ta="$ta mcore-dis.lo" ;; bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;; + bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;; bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;; bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;; bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;; + bfd_openrisc_arch) ta="$ta openrisc-asm.lo openrisc-desc.lo openrisc-dis.lo openrisc-ibld.lo openrisc-opc.lo" using_cgen=yes ;; + bfd_pdp11_arch) ta="$ta pdp11-dis.lo pdp11-opc.lo" ;; bfd_pj_arch) ta="$ta pj-dis.lo pj-opc.lo" ;; bfd_powerpc_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; bfd_powerpc_64_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; bfd_pyramid_arch) ;; bfd_romp_arch) ;; bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; + bfd_s390_arch) ta="$ta s390-dis.lo s390-opc.lo" ;; bfd_sh_arch) ta="$ta sh-dis.lo" ;; bfd_sparc_arch) ta="$ta sparc-dis.lo sparc-opc.lo" ;; @@ -4539,6 +4606,7 @@ if test x${all_targets} = xfalse ; then bfd_vax_arch) ta="$ta vax-dis.lo" ;; bfd_w65_arch) ta="$ta w65-dis.lo" ;; bfd_we32k_arch) ;; + bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;; bfd_z8k_arch) ta="$ta z8k-dis.lo" ;; "") ;; @@ -4728,7 +4796,6 @@ s%@build_alias@%$build_alias%g s%@build_cpu@%$build_cpu%g s%@build_vendor@%$build_vendor%g s%@build_os@%$build_os%g -s%@CC@%$CC%g s%@INSTALL_PROGRAM@%$INSTALL_PROGRAM%g s%@INSTALL_SCRIPT@%$INSTALL_SCRIPT%g s%@INSTALL_DATA@%$INSTALL_DATA%g @@ -4742,6 +4809,7 @@ s%@MAKEINFO@%$MAKEINFO%g s%@SET_MAKE@%$SET_MAKE%g s%@AR@%$AR%g s%@RANLIB@%$RANLIB%g +s%@CC@%$CC%g s%@LN_S@%$LN_S%g s%@OBJEXT@%$OBJEXT%g s%@EXEEXT@%$EXEEXT%g @@ -4773,6 +4841,8 @@ s%@GT_NO@%$GT_NO%g s%@GT_YES@%$GT_YES%g s%@MKINSTALLDIRS@%$MKINSTALLDIRS%g s%@l@%$l%g +s%@CC_FOR_BUILD@%$CC_FOR_BUILD%g +s%@EXEEXT_FOR_BUILD@%$EXEEXT_FOR_BUILD%g s%@HDEFINES@%$HDEFINES%g s%@CGEN_MAINT_TRUE@%$CGEN_MAINT_TRUE%g s%@CGEN_MAINT_FALSE@%$CGEN_MAINT_FALSE%g diff --git a/contrib/binutils/opcodes/configure.in b/contrib/binutils/opcodes/configure.in index 28f12ed..302cd53 100644 --- a/contrib/binutils/opcodes/configure.in +++ b/contrib/binutils/opcodes/configure.in @@ -43,7 +43,7 @@ AC_ARG_ENABLE(commonbfdlib, *) AC_MSG_ERROR([bad value ${enableval} for opcodes commonbfdlib option]) ;; esac])dnl -build_warnings="-W -Wall" +build_warnings="-W -Wall -Wstrict-prototypes -Wmissing-prototypes" AC_ARG_ENABLE(build-warnings, [ --enable-build-warnings Enable build-time compiler warnings if gcc is used], [case "${enableval}" in @@ -69,7 +69,6 @@ AM_CONFIG_HEADER(config.h:config.in) if test -z "$target" ; then AC_MSG_ERROR(Unrecognized target system type; please check config.sub.) fi -AC_ARG_PROGRAM AM_MAINTAINER_MODE AC_EXEEXT @@ -78,11 +77,13 @@ AC_EXEEXT AC_PROG_CC -ALL_LINGUAS= +ALL_LINGUAS="fr sv tr es da" CY_GNU_GETTEXT . ${srcdir}/../bfd/configure.host +BFD_CC_FOR_BUILD + AC_SUBST(HDEFINES) AC_PROG_INSTALL @@ -193,15 +194,19 @@ if test x${all_targets} = xfalse ; then bfd_m88k_arch) ta="$ta m88k-dis.lo" ;; bfd_mcore_arch) ta="$ta mcore-dis.lo" ;; bfd_mips_arch) ta="$ta mips-dis.lo mips-opc.lo mips16-opc.lo" ;; + bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;; bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;; bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;; bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;; + bfd_openrisc_arch) ta="$ta openrisc-asm.lo openrisc-desc.lo openrisc-dis.lo openrisc-ibld.lo openrisc-opc.lo" using_cgen=yes ;; + bfd_pdp11_arch) ta="$ta pdp11-dis.lo pdp11-opc.lo" ;; bfd_pj_arch) ta="$ta pj-dis.lo pj-opc.lo" ;; bfd_powerpc_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; bfd_powerpc_64_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; bfd_pyramid_arch) ;; bfd_romp_arch) ;; bfd_rs6000_arch) ta="$ta ppc-dis.lo ppc-opc.lo" ;; + bfd_s390_arch) ta="$ta s390-dis.lo s390-opc.lo" ;; bfd_sh_arch) ta="$ta sh-dis.lo" ;; bfd_sparc_arch) ta="$ta sparc-dis.lo sparc-opc.lo" ;; @@ -215,6 +220,7 @@ if test x${all_targets} = xfalse ; then bfd_vax_arch) ta="$ta vax-dis.lo" ;; bfd_w65_arch) ta="$ta w65-dis.lo" ;; bfd_we32k_arch) ;; + bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;; bfd_z8k_arch) ta="$ta z8k-dis.lo" ;; "") ;; diff --git a/contrib/binutils/opcodes/dis-buf.c b/contrib/binutils/opcodes/dis-buf.c index 46ac2f7..8f846a9 100644 --- a/contrib/binutils/opcodes/dis-buf.c +++ b/contrib/binutils/opcodes/dis-buf.c @@ -80,10 +80,13 @@ generic_print_address (addr, info) (*info->fprintf_func) (info->stream, "0x%s", buf); } +#if 0 /* Just concatenate the address as hex. This is included for completeness even though both GDB and objdump provide their own (to print symbolic addresses). */ +void generic_strcat_address PARAMS ((bfd_vma, char *, int)); + void generic_strcat_address (addr, buf, len) bfd_vma addr; @@ -102,6 +105,7 @@ generic_strcat_address (addr, buf, len) } return; } +#endif /* Just return the given address. */ diff --git a/contrib/binutils/opcodes/disassemble.c b/contrib/binutils/opcodes/disassemble.c index 3a76d55..ab23635 100644 --- a/contrib/binutils/opcodes/disassemble.c +++ b/contrib/binutils/opcodes/disassemble.c @@ -44,12 +44,16 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define ARCH_m88k #define ARCH_mcore #define ARCH_mips +#define ARCH_mmix #define ARCH_mn10200 #define ARCH_mn10300 #define ARCH_ns32k +#define ARCH_openrisc +#define ARCH_pdp11 #define ARCH_pj #define ARCH_powerpc #define ARCH_rs6000 +#define ARCH_s390 #define ARCH_sh #define ARCH_sparc #define ARCH_tic30 @@ -58,6 +62,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define ARCH_v850 #define ARCH_vax #define ARCH_w65 +#define ARCH_xstormy16 #define ARCH_z8k #endif @@ -146,11 +151,7 @@ disassembler (abfd) #endif #ifdef ARCH_i386 case bfd_arch_i386: - if (bfd_get_mach (abfd) == bfd_mach_i386_i386_intel_syntax - || bfd_get_mach (abfd) == bfd_mach_x86_64_intel_syntax) - disassemble = print_insn_i386_intel; - else - disassemble = print_insn_i386_att; + disassemble = print_insn_i386; break; #endif #ifdef ARCH_i860 @@ -214,6 +215,11 @@ disassembler (abfd) disassemble = print_insn_little_mips; break; #endif +#ifdef ARCH_mmix + case bfd_arch_mmix: + disassemble = print_insn_mmix; + break; +#endif #ifdef ARCH_mn10200 case bfd_arch_mn10200: disassemble = print_insn_mn10200; @@ -224,6 +230,16 @@ disassembler (abfd) disassemble = print_insn_mn10300; break; #endif +#ifdef ARCH_openrisc + case bfd_arch_openrisc: + disassemble = print_insn_openrisc; + break; +#endif +#ifdef ARCH_pdp11 + case bfd_arch_pdp11: + disassemble = print_insn_pdp11; + break; +#endif #ifdef ARCH_pj case bfd_arch_pj: disassemble = print_insn_pj; @@ -245,6 +261,11 @@ disassembler (abfd) disassemble = print_insn_rs6000; break; #endif +#ifdef ARCH_s390 + case bfd_arch_s390: + disassemble = print_insn_s390; + break; +#endif #ifdef ARCH_sh case bfd_arch_sh: if (bfd_big_endian (abfd)) @@ -283,6 +304,11 @@ disassembler (abfd) disassemble = print_insn_w65; break; #endif +#ifdef ARCH_xstormy16 + case bfd_arch_xstormy16: + disassemble = print_insn_xstormy16; + break; +#endif #ifdef ARCH_z8k case bfd_arch_z8k: if (bfd_get_mach(abfd) == bfd_mach_z8001) diff --git a/contrib/binutils/opcodes/i386-dis.c b/contrib/binutils/opcodes/i386-dis.c index 3eb40c6..7b4b858 100644 --- a/contrib/binutils/opcodes/i386-dis.c +++ b/contrib/binutils/opcodes/i386-dis.c @@ -52,7 +52,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ static int fetch_data PARAMS ((struct disassemble_info *, bfd_byte *)); static void ckprefix PARAMS ((void)); static const char *prefix_name PARAMS ((int, int)); -static int print_insn_i386 PARAMS ((bfd_vma, disassemble_info *)); +static int print_insn PARAMS ((bfd_vma, disassemble_info *)); static void dofloat PARAMS ((int)); static void OP_ST PARAMS ((int, int)); static void OP_STi PARAMS ((int, int)); @@ -101,6 +101,7 @@ struct dis_private { bfd_byte *max_fetched; bfd_byte the_buffer[MAXLEN]; bfd_vma insn_start; + int orig_sizeflag; jmp_buf bailout; }; @@ -298,9 +299,7 @@ fetch_data (info, addr) #define loop_jcxz_flag NULL, loop_jcxz_mode /* bits in sizeflag */ -#if 0 /* Leave undefined until someone adds the extra flag to objdump. */ #define SUFFIX_ALWAYS 4 -#endif #define AFLAG 2 #define DFLAG 1 @@ -442,9 +441,9 @@ struct dis386 { 'N' => print 'n' if instruction has no wait "prefix" 'O' => print 'd', or 'o' 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, - or suffix_always is true - print 'q' if rex prefix is present. - 'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always is true + . or suffix_always is true. print 'q' if rex prefix is present. + 'Q' => print 'w', 'l' or 'q' if no register operands or suffix_always + . is true 'R' => print 'w', 'l' or 'q' ("wd" or "dq" in intel mode) 'S' => print 'w', 'l' or 'q' if suffix_always is true 'T' => print 'q' in 64bit mode and behave as 'P' otherwise @@ -1337,8 +1336,8 @@ static const struct dis386 grps[][8] = { }, /* GRP6 */ { - { "sldt", Ew, XX, XX }, - { "str", Ew, XX, XX }, + { "sldtQ", Ev, XX, XX }, + { "strQ", Ev, XX, XX }, { "lldt", Ew, XX, XX }, { "ltr", Ew, XX, XX }, { "verr", Ew, XX, XX }, @@ -1352,7 +1351,7 @@ static const struct dis386 grps[][8] = { { "sidtQ", M, XX, XX }, { "lgdtQ", M, XX, XX }, { "lidtQ", M, XX, XX }, - { "smsw", Ew, XX, XX }, + { "smswQ", Ev, XX, XX }, { "(bad)", XX, XX, XX }, { "lmsw", Ew, XX, XX }, { "invlpg", Ew, XX, XX }, @@ -1837,25 +1836,17 @@ static char close_char; static char separator_char; static char scale_char; +/* Here for backwards compatibility. When gdb stops using + print_insn_i386_att and print_insn_i386_intel these functions can + disappear, and print_insn_i386 be merged into print_insn. */ int print_insn_i386_att (pc, info) bfd_vma pc; disassemble_info *info; { intel_syntax = 0; - names64 = att_names64; - names32 = att_names32; - names16 = att_names16; - names8 = att_names8; - names8rex = att_names8rex; - names_seg = att_names_seg; - index16 = att_index16; - open_char = '('; - close_char = ')'; - separator_char = ','; - scale_char = ','; - - return print_insn_i386 (pc, info); + + return print_insn (pc, info); } int @@ -1864,51 +1855,127 @@ print_insn_i386_intel (pc, info) disassemble_info *info; { intel_syntax = 1; - names64 = intel_names64; - names32 = intel_names32; - names16 = intel_names16; - names8 = intel_names8; - names8rex = intel_names8rex; - names_seg = intel_names_seg; - index16 = intel_index16; - open_char = '['; - close_char = ']'; - separator_char = '+'; - scale_char = '*'; - - return print_insn_i386 (pc, info); + + return print_insn (pc, info); } -static int +int print_insn_i386 (pc, info) bfd_vma pc; disassemble_info *info; { + intel_syntax = -1; + + return print_insn (pc, info); +} + +static int +print_insn (pc, info) + bfd_vma pc; + disassemble_info *info; +{ const struct dis386 *dp; int i; int two_source_ops; char *first, *second, *third; int needcomma; unsigned char uses_SSE_prefix; - VOLATILE int sizeflag; - VOLATILE int orig_sizeflag; - + int sizeflag; + const char *p; struct dis_private priv; - bfd_byte *inbuf = priv.the_buffer; mode_64bit = (info->mach == bfd_mach_x86_64_intel_syntax || info->mach == bfd_mach_x86_64); + if (intel_syntax == -1) + intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax + || info->mach == bfd_mach_x86_64_intel_syntax); + if (info->mach == bfd_mach_i386_i386 || info->mach == bfd_mach_x86_64 || info->mach == bfd_mach_i386_i386_intel_syntax || info->mach == bfd_mach_x86_64_intel_syntax) - sizeflag = AFLAG | DFLAG; + priv.orig_sizeflag = AFLAG | DFLAG; else if (info->mach == bfd_mach_i386_i8086) - sizeflag = 0; + priv.orig_sizeflag = 0; else abort (); - orig_sizeflag = sizeflag; + + for (p = info->disassembler_options; p != NULL; ) + { + if (strncmp (p, "x86-64", 6) == 0) + { + mode_64bit = 1; + priv.orig_sizeflag = AFLAG | DFLAG; + } + else if (strncmp (p, "i386", 4) == 0) + { + mode_64bit = 0; + priv.orig_sizeflag = AFLAG | DFLAG; + } + else if (strncmp (p, "i8086", 5) == 0) + { + mode_64bit = 0; + priv.orig_sizeflag = 0; + } + else if (strncmp (p, "intel", 5) == 0) + { + intel_syntax = 1; + } + else if (strncmp (p, "att", 3) == 0) + { + intel_syntax = 0; + } + else if (strncmp (p, "addr", 4) == 0) + { + if (p[4] == '1' && p[5] == '6') + priv.orig_sizeflag &= ~AFLAG; + else if (p[4] == '3' && p[5] == '2') + priv.orig_sizeflag |= AFLAG; + } + else if (strncmp (p, "data", 4) == 0) + { + if (p[4] == '1' && p[5] == '6') + priv.orig_sizeflag &= ~DFLAG; + else if (p[4] == '3' && p[5] == '2') + priv.orig_sizeflag |= DFLAG; + } + else if (strncmp (p, "suffix", 6) == 0) + priv.orig_sizeflag |= SUFFIX_ALWAYS; + + p = strchr (p, ','); + if (p != NULL) + p++; + } + + if (intel_syntax) + { + names64 = intel_names64; + names32 = intel_names32; + names16 = intel_names16; + names8 = intel_names8; + names8rex = intel_names8rex; + names_seg = intel_names_seg; + index16 = intel_index16; + open_char = '['; + close_char = ']'; + separator_char = '+'; + scale_char = '*'; + } + else + { + names64 = att_names64; + names32 = att_names32; + names16 = att_names16; + names8 = att_names8; + names8rex = att_names8rex; + names_seg = att_names_seg; + index16 = att_index16; + open_char = '('; + close_char = ')'; + separator_char = ','; + scale_char = ','; + } /* The output looks better if we put 7 bytes on a line, since that puts most long word instructions on a single line. */ @@ -1927,26 +1994,26 @@ print_insn_i386 (pc, info) the_info = info; start_pc = pc; - start_codep = inbuf; - codep = inbuf; + start_codep = priv.the_buffer; + codep = priv.the_buffer; if (setjmp (priv.bailout) != 0) { const char *name; /* Getting here means we tried for data but didn't get it. That - means we have an incomplete instruction of some sort. Just - print the first byte as a prefix or a .byte pseudo-op. */ - if (codep > inbuf) + means we have an incomplete instruction of some sort. Just + print the first byte as a prefix or a .byte pseudo-op. */ + if (codep > priv.the_buffer) { - name = prefix_name (inbuf[0], orig_sizeflag); + name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); if (name != NULL) (*info->fprintf_func) (info->stream, "%s", name); else { /* Just print the first byte as a .byte instruction. */ (*info->fprintf_func) (info->stream, ".byte 0x%x", - (unsigned int) inbuf[0]); + (unsigned int) priv.the_buffer[0]); } return 1; @@ -1959,6 +2026,7 @@ print_insn_i386 (pc, info) ckprefix (); insn_codep = codep; + sizeflag = priv.orig_sizeflag; FETCH_DATA (info, codep + 1); two_source_ops = (*codep == 0x62) || (*codep == 0xc8); @@ -1970,7 +2038,7 @@ print_insn_i386 (pc, info) /* fwait not followed by floating point instruction. Print the first prefix, which is probably fwait itself. */ - name = prefix_name (inbuf[0], orig_sizeflag); + name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); if (name == NULL) name = INTERNAL_DISASSEMBLER_ERROR; (*info->fprintf_func) (info->stream, "%s", name); @@ -2116,7 +2184,7 @@ print_insn_i386 (pc, info) { const char *name; - name = prefix_name (inbuf[0], orig_sizeflag); + name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); if (name == NULL) name = INTERNAL_DISASSEMBLER_ERROR; (*info->fprintf_func) (info->stream, "%s", name); @@ -2125,7 +2193,7 @@ print_insn_i386 (pc, info) if (rex & ~rex_used) { const char *name; - name = prefix_name (rex | 0x40, orig_sizeflag); + name = prefix_name (rex | 0x40, priv.orig_sizeflag); if (name == NULL) name = INTERNAL_DISASSEMBLER_ERROR; (*info->fprintf_func) (info->stream, "%s ", name); @@ -2189,7 +2257,7 @@ print_insn_i386 (pc, info) (*info->print_address_func) ((bfd_vma) (start_pc + codep - start_codep + op_address[op_index[i]]), info); } - return codep - inbuf; + return codep - priv.the_buffer; } static const char *float_mem[] = { @@ -2548,20 +2616,14 @@ putop (template, sizeflag) case 'A': if (intel_syntax) break; - if (mod != 3 -#ifdef SUFFIX_ALWAYS - || (sizeflag & SUFFIX_ALWAYS) -#endif - ) + if (mod != 3 || (sizeflag & SUFFIX_ALWAYS)) *obufp++ = 'b'; break; case 'B': if (intel_syntax) break; -#ifdef SUFFIX_ALWAYS if (sizeflag & SUFFIX_ALWAYS) *obufp++ = 'b'; -#endif break; case 'E': /* For jcxz/jecxz */ if (sizeflag & AFLAG) @@ -2571,11 +2633,7 @@ putop (template, sizeflag) case 'F': if (intel_syntax) break; - if ((prefixes & PREFIX_ADDR) -#ifdef SUFFIX_ALWAYS - || (sizeflag & SUFFIX_ALWAYS) -#endif - ) + if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) { if (sizeflag & AFLAG) *obufp++ = 'l'; @@ -2602,10 +2660,8 @@ putop (template, sizeflag) case 'L': if (intel_syntax) break; -#ifdef SUFFIX_ALWAYS if (sizeflag & SUFFIX_ALWAYS) *obufp++ = 'l'; -#endif break; case 'N': if ((prefixes & PREFIX_FWAIT) == 0) @@ -2634,10 +2690,7 @@ putop (template, sizeflag) break; if ((prefixes & PREFIX_DATA) || (rex & REX_MODE64) -#ifdef SUFFIX_ALWAYS - || (sizeflag & SUFFIX_ALWAYS) -#endif - ) + || (sizeflag & SUFFIX_ALWAYS)) { USED_REX (REX_MODE64); if (rex & REX_MODE64) @@ -2665,11 +2718,7 @@ putop (template, sizeflag) if (intel_syntax) break; USED_REX (REX_MODE64); - if (mod != 3 -#ifdef SUFFIX_ALWAYS - || (sizeflag & SUFFIX_ALWAYS) -#endif - ) + if (mod != 3 || (sizeflag & SUFFIX_ALWAYS)) { if (rex & REX_MODE64) *obufp++ = 'q'; @@ -2718,7 +2767,6 @@ putop (template, sizeflag) case 'S': if (intel_syntax) break; -#ifdef SUFFIX_ALWAYS if (sizeflag & SUFFIX_ALWAYS) { if (rex & REX_MODE64) @@ -2732,7 +2780,6 @@ putop (template, sizeflag) used_prefixes |= (prefixes & PREFIX_DATA); } } -#endif break; case 'X': if (prefixes & PREFIX_DATA) diff --git a/contrib/binutils/opcodes/ia64-gen.c b/contrib/binutils/opcodes/ia64-gen.c index 4b4b197..6443c7c 100644 --- a/contrib/binutils/opcodes/ia64-gen.c +++ b/contrib/binutils/opcodes/ia64-gen.c @@ -1,5 +1,5 @@ /* ia64-gen.c -- Generate a shrunk set of opcode tables - Copyright 1999, 2000 Free Software Foundation, Inc. + Copyright 1999, 2000, 2001 Free Software Foundation, Inc. Written by Bob Manson, Cygnus Solutions, <manson@cygnus.com> This file is part of GDB, GAS, and the GNU binutils. @@ -35,10 +35,10 @@ */ #include <stdio.h> -#include <ctype.h> #include "ansidecl.h" #include "libiberty.h" +#include "safe-ctype.h" #include "sysdep.h" #include "ia64-opc.h" #include "ia64-opc-a.c" @@ -543,7 +543,7 @@ load_insn_classes() if (fgets (buf, sizeof(buf), fp) == NULL) break; - while (isspace(buf[strlen(buf)-1])) + while (ISSPACE (buf[strlen(buf)-1])) buf[strlen(buf)-1] = '\0'; name = tmp = buf; @@ -571,7 +571,7 @@ load_insn_classes() char *subname; int sub; - while (*tmp && isspace(*tmp)) + while (*tmp && ISSPACE (*tmp)) { ++tmp; if (tmp == buf + sizeof(buf)) @@ -633,7 +633,7 @@ parse_resource_users(ref, usersp, nusersp, notesp) int create = 0; char *name; - while (isspace(*tmp)) + while (ISSPACE (*tmp)) ++tmp; name = tmp; while (*tmp && *tmp != ',') @@ -754,7 +754,7 @@ load_depfile (const char *filename, enum ia64_dependency_mode mode) if (fgets (buf, sizeof(buf), fp) == NULL) break; - while (isspace(buf[strlen(buf)-1])) + while (ISSPACE (buf[strlen(buf)-1])) buf[strlen(buf)-1] = '\0'; name = tmp = buf; @@ -762,21 +762,21 @@ load_depfile (const char *filename, enum ia64_dependency_mode mode) ++tmp; *tmp++ = '\0'; - while (isspace (*tmp)) + while (ISSPACE (*tmp)) ++tmp; regp = tmp; tmp = strchr (tmp, ';'); if (!tmp) abort (); *tmp++ = 0; - while (isspace (*tmp)) + while (ISSPACE (*tmp)) ++tmp; chkp = tmp; tmp = strchr (tmp, ';'); if (!tmp) abort (); *tmp++ = 0; - while (isspace (*tmp)) + while (ISSPACE (*tmp)) ++tmp; semantics = parse_semantics (tmp); extra = semantics == IA64_DVS_OTHER ? xstrdup (tmp) : NULL; diff --git a/contrib/binutils/opcodes/ia64-opc.c b/contrib/binutils/opcodes/ia64-opc.c index 84e3837..9726381 100644 --- a/contrib/binutils/opcodes/ia64-opc.c +++ b/contrib/binutils/opcodes/ia64-opc.c @@ -25,6 +25,20 @@ #include "ia64-asmtab.h" #include "ia64-asmtab.c" +static void get_opc_prefix PARAMS ((const char **, char *)); +static short int find_string_ent PARAMS ((const char *)); +static short int find_main_ent PARAMS ((short int)); +static short int find_completer PARAMS ((short int, short int, const char *)); +static ia64_insn apply_completer PARAMS ((ia64_insn, int)); +static int extract_op_bits PARAMS ((int, int, int)); +static int extract_op PARAMS ((int, int *, unsigned int *)); +static int opcode_verify PARAMS ((ia64_insn, int, enum ia64_insn_type)); +static int locate_opcode_ent PARAMS ((ia64_insn, enum ia64_insn_type)); +static struct ia64_opcode *make_ia64_opcode + PARAMS ((ia64_insn, const char *, int, int)); +static struct ia64_opcode *ia64_find_matching_opcode + PARAMS ((const char *, short int)); + const struct ia64_templ_desc ia64_templ_desc[16] = { { 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" }, /* 0 */ @@ -149,7 +163,7 @@ find_main_ent (nameindex) MAIN_ENT (starting from PREV_COMPLETER) that matches NAME, or return -1 if one does not exist. */ -static short +static short find_completer (main_ent, prev_completer, name) short main_ent; short prev_completer; @@ -312,7 +326,7 @@ opcode_verify (opcode, place, type) { return 0; } - if (main_table[place].flags + if (main_table[place].flags & (IA64_OPCODE_F2_EQ_F3 | IA64_OPCODE_LEN_EQ_64MCNT)) { const struct ia64_operand *o1, *o2; @@ -481,7 +495,7 @@ locate_opcode_ent (opcode, type) priority = ia64_dis_names[disent].priority; - if (opcode_verify (opcode, place, type) + if (opcode_verify (opcode, place, type) && priority > found_priority) { break; @@ -610,7 +624,7 @@ ia64_dis_opcode (insn, type) { abort (); } - return make_ia64_opcode (insn, name, place, + return make_ia64_opcode (insn, name, place, completer_table[ci].dependencies); } } @@ -646,7 +660,7 @@ ia64_find_matching_opcode (name, place) short completer = -1; do { - if (suffix[0] == '\0') + if (suffix[0] == '\0') { completer = find_completer (place, completer, suffix); } diff --git a/contrib/binutils/opcodes/po/POTFILES.in b/contrib/binutils/opcodes/po/POTFILES.in index f27d27a..e8d2ba8 100644 --- a/contrib/binutils/opcodes/po/POTFILES.in +++ b/contrib/binutils/opcodes/po/POTFILES.in @@ -68,11 +68,25 @@ mcore-opc.h mips-dis.c mips-opc.c mips16-opc.c +mmix-dis.c +mmix-opc.c ns32k-dis.c +openrisc-asm.c +openrisc-desc.c +openrisc-desc.h +openrisc-dis.c +openrisc-ibld.c +openrisc-opc.c +openrisc-opc.h +pdp11-dis.c +pdp11-opc.c pj-dis.c pj-opc.c ppc-dis.c ppc-opc.c +s390-dis.c +s390-mkopc.c +s390-opc.c sh-dis.c sh-opc.h sparc-dis.c @@ -88,6 +102,13 @@ v850-opc.c vax-dis.c w65-dis.c w65-opc.h +xstormy16-asm.c +xstormy16-desc.c +xstormy16-desc.h +xstormy16-dis.c +xstormy16-ibld.c +xstormy16-opc.c +xstormy16-opc.h z8k-dis.c z8k-opc.h z8kgen.c diff --git a/contrib/binutils/opcodes/po/opcodes.pot b/contrib/binutils/opcodes/po/opcodes.pot index 3336bbd..4e079cd 100644 --- a/contrib/binutils/opcodes/po/opcodes.pot +++ b/contrib/binutils/opcodes/po/opcodes.pot @@ -6,13 +6,13 @@ msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" -"POT-Creation-Date: 2001-01-11 12:44-0800\n" +"POT-Creation-Date: 2002-01-17 13:58+0000\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n" "Language-Team: LANGUAGE <LL@li.org>\n" "MIME-Version: 1.0\n" "Content-Type: text/plain; charset=CHARSET\n" -"Content-Transfer-Encoding: ENCODING\n" +"Content-Transfer-Encoding: 8bit\n" #: alpha-opc.c:335 msgid "branch operand unaligned" @@ -26,21 +26,21 @@ msgstr "" msgid "Illegal limm reference in last instruction!\n" msgstr "" -#: arm-dis.c:489 +#: arm-dis.c:509 msgid "<illegal precision>" msgstr "" -#: arm-dis.c:904 +#: arm-dis.c:1019 #, c-format msgid "Unrecognised register name set: %s\n" msgstr "" -#: arm-dis.c:911 +#: arm-dis.c:1026 #, c-format msgid "Unrecognised disassembler option: %s\n" msgstr "" -#: arm-dis.c:1083 +#: arm-dis.c:1198 msgid "" "\n" "The following ARM specific disassembler options are supported for use with\n" @@ -60,133 +60,148 @@ msgstr "" msgid "unknown constraint `%c'" msgstr "" -#: cgen-asm.c:224 -msgid "unrecognized keyword/register name" -msgstr "" - -#: cgen-asm.c:332 fr30-ibld.c:232 m32r-ibld.c:232 +#: cgen-asm.c:346 fr30-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 #, c-format msgid "operand out of range (%ld not between %ld and %ld)" msgstr "" -#: cgen-asm.c:353 +#: cgen-asm.c:367 #, c-format msgid "operand out of range (%lu not between %lu and %lu)" msgstr "" -#: d30v-dis.c:306 +#: d30v-dis.c:312 #, c-format msgid "<unknown register %d>" msgstr "" #. Can't happen. -#: dis-buf.c:56 +#: dis-buf.c:57 #, c-format msgid "Unknown error %d\n" msgstr "" -#: dis-buf.c:61 +#: dis-buf.c:62 #, c-format msgid "Address 0x%x is out of bounds.\n" msgstr "" -#: fr30-asm.c:305 m32r-asm.c:313 +#: fr30-asm.c:324 m32r-asm.c:326 openrisc-asm.c:245 #, c-format msgid "Unrecognized field %d while parsing.\n" msgstr "" +#: fr30-asm.c:374 m32r-asm.c:376 openrisc-asm.c:295 +msgid "missing mnemonic in syntax string" +msgstr "" + #. We couldn't parse it. -#: fr30-asm.c:369 fr30-asm.c:373 fr30-asm.c:449 m32r-asm.c:377 m32r-asm.c:381 -#: m32r-asm.c:457 +#: fr30-asm.c:510 fr30-asm.c:514 fr30-asm.c:601 fr30-asm.c:703 m32r-asm.c:512 +#: m32r-asm.c:516 m32r-asm.c:603 m32r-asm.c:705 openrisc-asm.c:431 +#: openrisc-asm.c:435 openrisc-asm.c:522 openrisc-asm.c:624 msgid "unrecognized instruction" msgstr "" -#: fr30-asm.c:415 m32r-asm.c:423 +#: fr30-asm.c:557 m32r-asm.c:559 openrisc-asm.c:478 #, c-format msgid "syntax error (expected char `%c', found `%c')" msgstr "" -#: fr30-asm.c:443 m32r-asm.c:451 +#: fr30-asm.c:567 m32r-asm.c:569 openrisc-asm.c:488 +#, c-format +msgid "syntax error (expected char `%c', found end of instruction)" +msgstr "" + +#: fr30-asm.c:595 m32r-asm.c:597 openrisc-asm.c:516 msgid "junk at end of line" msgstr "" -#: fr30-asm.c:551 m32r-asm.c:559 +#: fr30-asm.c:702 m32r-asm.c:704 openrisc-asm.c:623 +msgid "unrecognized form of instruction" +msgstr "" + +#: fr30-asm.c:714 m32r-asm.c:716 openrisc-asm.c:635 #, c-format msgid "bad instruction `%.50s...'" msgstr "" -#: fr30-asm.c:554 m32r-asm.c:562 +#: fr30-asm.c:717 m32r-asm.c:719 openrisc-asm.c:638 #, c-format msgid "bad instruction `%.50s'" msgstr "" #. Default text to print if an instruction isn't recognized. -#: fr30-dis.c:39 m32r-dis.c:39 +#: fr30-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 msgid "*unknown*" msgstr "" -#: fr30-dis.c:300 m32r-dis.c:239 +#: fr30-dis.c:319 m32r-dis.c:250 openrisc-dis.c:137 #, c-format msgid "Unrecognized field %d while printing insn.\n" msgstr "" -#: fr30-ibld.c:216 m32r-ibld.c:216 +#: fr30-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 +#, c-format +msgid "operand out of range (%ld not between %ld and %lu)" +msgstr "" + +#: fr30-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 #, c-format msgid "operand out of range (%lu not between 0 and %lu)" msgstr "" -#: fr30-ibld.c:790 m32r-ibld.c:719 +#: fr30-ibld.c:731 m32r-ibld.c:660 openrisc-ibld.c:634 #, c-format msgid "Unrecognized field %d while building insn.\n" msgstr "" -#: fr30-ibld.c:994 m32r-ibld.c:849 +#: fr30-ibld.c:939 m32r-ibld.c:794 openrisc-ibld.c:737 #, c-format msgid "Unrecognized field %d while decoding insn.\n" msgstr "" -#: fr30-ibld.c:1138 m32r-ibld.c:954 +#: fr30-ibld.c:1088 m32r-ibld.c:904 openrisc-ibld.c:817 #, c-format msgid "Unrecognized field %d while getting int operand.\n" msgstr "" -#: fr30-ibld.c:1267 m32r-ibld.c:1044 +#: fr30-ibld.c:1217 m32r-ibld.c:994 openrisc-ibld.c:877 #, c-format msgid "Unrecognized field %d while getting vma operand.\n" msgstr "" -#: fr30-ibld.c:1396 m32r-ibld.c:1137 +#: fr30-ibld.c:1351 m32r-ibld.c:1092 openrisc-ibld.c:946 #, c-format msgid "Unrecognized field %d while setting int operand.\n" msgstr "" -#: fr30-ibld.c:1518 m32r-ibld.c:1223 +#: fr30-ibld.c:1473 m32r-ibld.c:1178 openrisc-ibld.c:1003 #, c-format msgid "Unrecognized field %d while setting vma operand.\n" msgstr "" -#: h8300-dis.c:380 +#: h8300-dis.c:384 #, c-format msgid "Hmmmm %x" msgstr "" -#: h8300-dis.c:391 +#: h8300-dis.c:395 #, c-format msgid "Don't understand %x \n" msgstr "" -#: h8500-dis.c:141 +#: h8500-dis.c:143 #, c-format msgid "can't cope with insert %d\n" msgstr "" #. Couldn't understand anything. -#: h8500-dis.c:348 +#: h8500-dis.c:350 #, c-format msgid "%02x\t\t*unknown*" msgstr "" -#: i386-dis.c:2740 +#: i386-dis.c:1649 msgid "<internal disassembler error>" msgstr "" @@ -205,90 +220,126 @@ msgstr "" msgid "unknown\t0x%04x" msgstr "" -#: m68k-dis.c:412 +#: m68k-dis.c:429 #, c-format msgid "<internal error in opcode table: %s %s>\n" msgstr "" -#: m68k-dis.c:990 +#: m68k-dis.c:1007 #, c-format msgid "<function code %d>" msgstr "" -#: m88k-dis.c:274 +#: m88k-dis.c:255 #, c-format msgid "# <dis error: %08x>" msgstr "" -#: mips-dis.c:273 +#: mips-dis.c:290 #, c-format msgid "# internal error, undefined modifier(%c)" msgstr "" +#: mips-dis.c:1154 +#, c-format +msgid "# internal disassembler error, unrecognised modifier (%c)" +msgstr "" + +#: mmix-dis.c:34 +#, c-format +msgid "Bad case %d (%s) in %s:%d\n" +msgstr "" + +#: mmix-dis.c:44 +#, c-format +msgid "Internal: Non-debugged code (test-case missing): %s:%d" +msgstr "" + +#: mmix-dis.c:53 +msgid "(unknown)" +msgstr "" + +#: mmix-dis.c:517 +#, c-format +msgid "*unknown operands type: %d*" +msgstr "" + #. I and Z are output operands and can`t be immediate #. * A is an address and we can`t have the address of #. * an immediate either. We don't know how much to increase #. * aoffsetp by since whatever generated this is broken #. * anyway! #. -#: ns32k-dis.c:618 +#: ns32k-dis.c:628 msgid "$<undefined>" msgstr "" -#: ppc-opc.c:619 ppc-opc.c:650 +#: ppc-opc.c:765 ppc-opc.c:798 msgid "invalid conditional option" msgstr "" -#: ppc-opc.c:652 +#: ppc-opc.c:800 msgid "attempt to set y bit when using + or - modifier" msgstr "" -#: ppc-opc.c:707 +#: ppc-opc.c:832 ppc-opc.c:884 +msgid "offset not a multiple of 4" +msgstr "" + +#: ppc-opc.c:857 +msgid "offset not between -2048 and 2047" +msgstr "" + +#: ppc-opc.c:882 +msgid "offset not between -8192 and 8191" +msgstr "" + +#: ppc-opc.c:910 msgid "ignoring least significant bits in branch offset" msgstr "" -#: ppc-opc.c:742 ppc-opc.c:779 +#: ppc-opc.c:944 ppc-opc.c:981 msgid "illegal bitmask" msgstr "" -#: ppc-opc.c:848 +#: ppc-opc.c:1054 msgid "value out of range" msgstr "" -#: ppc-opc.c:922 +#: ppc-opc.c:1130 msgid "index register in load range" msgstr "" -#: ppc-opc.c:937 +#: ppc-opc.c:1146 msgid "invalid register operand when updating" msgstr "" #. Mark as non-valid instruction -#: sparc-dis.c:748 +#: sparc-dis.c:749 msgid "unknown" msgstr "" -#: sparc-dis.c:823 +#: sparc-dis.c:824 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "" -#: sparc-dis.c:834 +#: sparc-dis.c:835 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "" -#: sparc-dis.c:883 +#: sparc-dis.c:884 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" msgstr "" -#: v850-dis.c:221 +#: v850-dis.c:224 #, c-format msgid "unknown operand shift: %x\n" msgstr "" -#: v850-dis.c:233 +#: v850-dis.c:236 #, c-format msgid "unknown pop reg: %d\n" msgstr "" @@ -298,46 +349,46 @@ msgstr "" #. v850_insert_operand() in gas/config/tc-v850.c. Error messages #. containing the string 'out of range' will be ignored unless a #. specific command line option is given to GAS. -#: v850-opc.c:46 +#: v850-opc.c:68 msgid "displacement value is not in range and is not aligned" msgstr "" -#: v850-opc.c:47 +#: v850-opc.c:69 msgid "displacement value is out of range" msgstr "" -#: v850-opc.c:48 +#: v850-opc.c:70 msgid "displacement value is not aligned" msgstr "" -#: v850-opc.c:50 +#: v850-opc.c:72 msgid "immediate value is out of range" msgstr "" -#: v850-opc.c:61 +#: v850-opc.c:83 msgid "branch value not in range and to odd offset" msgstr "" -#: v850-opc.c:63 v850-opc.c:95 +#: v850-opc.c:85 v850-opc.c:117 msgid "branch value out of range" msgstr "" -#: v850-opc.c:66 v850-opc.c:98 +#: v850-opc.c:88 v850-opc.c:120 msgid "branch to odd offset" msgstr "" -#: v850-opc.c:93 +#: v850-opc.c:115 msgid "branch value not in range and to an odd offset" msgstr "" -#: v850-opc.c:321 +#: v850-opc.c:346 msgid "invalid register for stack adjustment" msgstr "" -#: v850-opc.c:343 +#: v850-opc.c:370 msgid "immediate value not in range and not even" msgstr "" -#: v850-opc.c:348 +#: v850-opc.c:375 msgid "immediate value must be even" msgstr "" diff --git a/contrib/binutils/opcodes/ppc-dis.c b/contrib/binutils/opcodes/ppc-dis.c index c59a920..5d654c0 100644 --- a/contrib/binutils/opcodes/ppc-dis.c +++ b/contrib/binutils/opcodes/ppc-dis.c @@ -32,32 +32,58 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * static int print_insn_powerpc PARAMS ((bfd_vma, struct disassemble_info *, int bigendian, int dialect)); -/* Print a big endian PowerPC instruction. For convenience, also - disassemble instructions supported by the Motorola PowerPC 601 - and the Altivec vector unit. */ +static int powerpc_dialect PARAMS ((struct disassemble_info *)); + +/* Determine which set of machines to disassemble for. PPC403/601 or + Motorola BookE. For convenience, also disassemble instructions + supported by the AltiVec vector unit. */ + +int +powerpc_dialect(info) + struct disassemble_info *info; +{ + int dialect = PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC; + + if (BFD_DEFAULT_TARGET_SIZE == 64) + dialect |= PPC_OPCODE_64; + + if (info->disassembler_options + && (strcmp (info->disassembler_options, "booke") == 0 + || strcmp (info->disassembler_options, "booke32") == 0 + || strcmp (info->disassembler_options, "booke64") == 0)) + dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64; + else + dialect |= PPC_OPCODE_403 | PPC_OPCODE_601; + + if (info->disassembler_options) + { + if (strstr (info->disassembler_options, "32") != NULL) + dialect &= ~PPC_OPCODE_64; + else if (strstr (info->disassembler_options, "64") != NULL) + dialect |= PPC_OPCODE_64; + } + + return dialect; +} + +/* Print a big endian PowerPC instruction. */ int print_insn_big_powerpc (memaddr, info) bfd_vma memaddr; struct disassemble_info *info; { - return print_insn_powerpc (memaddr, info, 1, - PPC_OPCODE_PPC | PPC_OPCODE_601 | - PPC_OPCODE_ALTIVEC); + return print_insn_powerpc (memaddr, info, 1, powerpc_dialect(info)); } -/* Print a little endian PowerPC instruction. For convenience, also - disassemble instructions supported by the Motorola PowerPC 601 - and the Altivec vector unit. */ +/* Print a little endian PowerPC instruction. */ int print_insn_little_powerpc (memaddr, info) bfd_vma memaddr; struct disassemble_info *info; { - return print_insn_powerpc (memaddr, info, 0, - PPC_OPCODE_PPC | PPC_OPCODE_601 | - PPC_OPCODE_ALTIVEC); + return print_insn_powerpc (memaddr, info, 0, powerpc_dialect(info)); } /* Print a POWER (RS/6000) instruction. */ @@ -131,7 +157,7 @@ print_insn_powerpc (memaddr, info, bigendian, dialect) { operand = powerpc_operands + *opindex; if (operand->extract) - (*operand->extract) (insn, &invalid); + (*operand->extract) (insn, dialect, &invalid); } if (invalid) continue; @@ -158,7 +184,7 @@ print_insn_powerpc (memaddr, info, bigendian, dialect) /* Extract the value from the instruction. */ if (operand->extract) - value = (*operand->extract) (insn, (int *) NULL); + value = (*operand->extract) (insn, dialect, (int *) NULL); else { value = (insn >> operand->shift) & ((1 << operand->bits) - 1); diff --git a/contrib/binutils/opcodes/ppc-opc.c b/contrib/binutils/opcodes/ppc-opc.c index 311a5ba..0d96e03 100644 --- a/contrib/binutils/opcodes/ppc-opc.c +++ b/contrib/binutils/opcodes/ppc-opc.c @@ -1,5 +1,5 @@ /* ppc-opc.c -- PowerPC opcode list - Copyright 1994, 1995, 1996, 1997, 1998, 2000 + Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001 Free Software Foundation, Inc. Written by Ian Lance Taylor, Cygnus Support @@ -38,44 +38,90 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA /* Local insertion and extraction functions. */ -static unsigned long insert_bat PARAMS ((unsigned long, long, const char **)); -static long extract_bat PARAMS ((unsigned long, int *)); -static unsigned long insert_bba PARAMS ((unsigned long, long, const char **)); -static long extract_bba PARAMS ((unsigned long, int *)); -static unsigned long insert_bd PARAMS ((unsigned long, long, const char **)); -static long extract_bd PARAMS ((unsigned long, int *)); -static unsigned long insert_bdm PARAMS ((unsigned long, long, const char **)); -static long extract_bdm PARAMS ((unsigned long, int *)); -static unsigned long insert_bdp PARAMS ((unsigned long, long, const char **)); -static long extract_bdp PARAMS ((unsigned long, int *)); -static int valid_bo PARAMS ((long)); -static unsigned long insert_bo PARAMS ((unsigned long, long, const char **)); -static long extract_bo PARAMS ((unsigned long, int *)); -static unsigned long insert_boe PARAMS ((unsigned long, long, const char **)); -static long extract_boe PARAMS ((unsigned long, int *)); -static unsigned long insert_ds PARAMS ((unsigned long, long, const char **)); -static long extract_ds PARAMS ((unsigned long, int *)); -static unsigned long insert_li PARAMS ((unsigned long, long, const char **)); -static long extract_li PARAMS ((unsigned long, int *)); -static unsigned long insert_mbe PARAMS ((unsigned long, long, const char **)); -static long extract_mbe PARAMS ((unsigned long, int *)); -static unsigned long insert_mb6 PARAMS ((unsigned long, long, const char **)); -static long extract_mb6 PARAMS ((unsigned long, int *)); -static unsigned long insert_nb PARAMS ((unsigned long, long, const char **)); -static long extract_nb PARAMS ((unsigned long, int *)); -static unsigned long insert_nsi PARAMS ((unsigned long, long, const char **)); -static long extract_nsi PARAMS ((unsigned long, int *)); -static unsigned long insert_ral PARAMS ((unsigned long, long, const char **)); -static unsigned long insert_ram PARAMS ((unsigned long, long, const char **)); -static unsigned long insert_ras PARAMS ((unsigned long, long, const char **)); -static unsigned long insert_rbs PARAMS ((unsigned long, long, const char **)); -static long extract_rbs PARAMS ((unsigned long, int *)); -static unsigned long insert_sh6 PARAMS ((unsigned long, long, const char **)); -static long extract_sh6 PARAMS ((unsigned long, int *)); -static unsigned long insert_spr PARAMS ((unsigned long, long, const char **)); -static long extract_spr PARAMS ((unsigned long, int *)); -static unsigned long insert_tbr PARAMS ((unsigned long, long, const char **)); -static long extract_tbr PARAMS ((unsigned long, int *)); +static unsigned long insert_bat + PARAMS ((unsigned long, long, int, const char **)); +static long extract_bat + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_bba + PARAMS ((unsigned long, long, int, const char **)); +static long extract_bba + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_bd + PARAMS ((unsigned long, long, int, const char **)); +static long extract_bd + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_bdm + PARAMS ((unsigned long, long, int, const char **)); +static long extract_bdm + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_bdp + PARAMS ((unsigned long, long, int, const char **)); +static long extract_bdp + PARAMS ((unsigned long, int, int *)); +static int valid_bo + PARAMS ((long, int)); +static unsigned long insert_bo + PARAMS ((unsigned long, long, int, const char **)); +static long extract_bo + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_boe + PARAMS ((unsigned long, long, int, const char **)); +static long extract_boe + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_ds + PARAMS ((unsigned long, long, int, const char **)); +static long extract_ds + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_de + PARAMS ((unsigned long, long, int, const char **)); +static long extract_de + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_des + PARAMS ((unsigned long, long, int, const char **)); +static long extract_des + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_li + PARAMS ((unsigned long, long, int, const char **)); +static long extract_li + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_mbe + PARAMS ((unsigned long, long, int, const char **)); +static long extract_mbe + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_mb6 + PARAMS ((unsigned long, long, int, const char **)); +static long extract_mb6 + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_nb + PARAMS ((unsigned long, long, int, const char **)); +static long extract_nb + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_nsi + PARAMS ((unsigned long, long, int, const char **)); +static long extract_nsi + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_ral + PARAMS ((unsigned long, long, int, const char **)); +static unsigned long insert_ram + PARAMS ((unsigned long, long, int, const char **)); +static unsigned long insert_ras + PARAMS ((unsigned long, long, int, const char **)); +static unsigned long insert_rbs + PARAMS ((unsigned long, long, int, const char **)); +static long extract_rbs + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_sh6 + PARAMS ((unsigned long, long, int, const char **)); +static long extract_sh6 + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_spr + PARAMS ((unsigned long, long, int, const char **)); +static long extract_spr + PARAMS ((unsigned long, int, int *)); +static unsigned long insert_tbr + PARAMS ((unsigned long, long, int, const char **)); +static long extract_tbr + PARAMS ((unsigned long, int, int *)); /* The operands table. @@ -189,16 +235,31 @@ const struct powerpc_operand powerpc_operands[] = #define CR BT + 1 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, + /* The CT field in an X form instruction. */ +#define CT CR + 1 + { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL }, + /* The D field in a D form instruction. This is a displacement off a register, and implies that the next operand is a register in parentheses. */ -#define D CR + 1 +#define D CT + 1 { 16, 0, 0, 0, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, + /* The DE field in a DE form instruction. This is like D, but is 12 + bits only. */ +#define DE D + 1 + { 14, 0, insert_de, extract_de, PPC_OPERAND_PARENS }, + + /* The DES field in a DES form instruction. This is like DS, but is 14 + bits only (12 stored.) */ +#define DES DE + 1 + { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, + /* The DS field in a DS form instruction. This is like D, but the lower two bits are forced to zero. */ -#define DS D + 1 - { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, +#define DS DES + 1 + { 16, 0, insert_ds, extract_ds, + PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, /* The E field in a wrteei instruction. */ #define E DS + 1 @@ -260,8 +321,12 @@ const struct powerpc_operand powerpc_operands[] = #define LIA LI + 1 { 26, 0, insert_li, extract_li, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED }, + /* The LS field in an X (sync) form instruction. */ +#define LS LIA + 1 + { 2, 21, 0, 0, PPC_OPERAND_OPTIONAL }, + /* The MB field in an M form instruction. */ -#define MB LIA + 1 +#define MB LS + 1 #define MB_MASK (0x1f << 6) { 5, 6, 0, 0, 0 }, @@ -285,9 +350,13 @@ const struct powerpc_operand powerpc_operands[] = #define MB6_MASK (0x3f << 5) { 6, 5, insert_mb6, extract_mb6, 0 }, + /* The MO field in an mbar instruction. */ +#define MO MB6 + 1 + { 5, 21, 0, 0, 0 }, + /* The NB field in an X form instruction. The value 32 is stored as 0. */ -#define NB MB6 + 1 +#define NB MO + 1 { 6, 11, insert_nb, extract_nb, 0 }, /* The NSI field in a D form instruction. This is the same as the @@ -376,8 +445,13 @@ const struct powerpc_operand powerpc_operands[] = #define SR SPRG + 1 { 4, 16, 0, 0, 0 }, + /* The STRM field in an X AltiVec form instruction. */ +#define STRM SR + 1 +#define STRM_MASK (0x3 << 21) + { 2, 21, 0, 0, 0 }, + /* The SV field in a POWER SC form instruction. */ -#define SV SR + 1 +#define SV STRM + 1 { 14, 2, 0, 0, 0 }, /* The TBR field in an XFX form instruction. This is like the SPR @@ -401,23 +475,23 @@ const struct powerpc_operand powerpc_operands[] = /* The VA field in a VA, VX or VXR form instruction. */ #define VA UI + 1 #define VA_MASK (0x1f << 16) - {5, 16, 0, 0, PPC_OPERAND_VR}, + { 5, 16, 0, 0, PPC_OPERAND_VR }, /* The VB field in a VA, VX or VXR form instruction. */ #define VB VA + 1 #define VB_MASK (0x1f << 11) - {5, 11, 0, 0, PPC_OPERAND_VR}, + { 5, 11, 0, 0, PPC_OPERAND_VR }, /* The VC field in a VA form instruction. */ #define VC VB + 1 #define VC_MASK (0x1f << 6) - {5, 6, 0, 0, PPC_OPERAND_VR}, + { 5, 6, 0, 0, PPC_OPERAND_VR }, /* The VD or VS field in a VA, VX, VXR or X form instruction. */ #define VD VC + 1 #define VS VD #define VD_MASK (0x1f << 21) - {5, 21, 0, 0, PPC_OPERAND_VR}, + { 5, 21, 0, 0, PPC_OPERAND_VR }, /* The SIMM field in a VX form instruction. */ #define SIMM VD + 1 @@ -442,17 +516,19 @@ const struct powerpc_operand powerpc_operands[] = /*ARGSUSED*/ static unsigned long -insert_bat (insn, value, errmsg) +insert_bat (insn, value, dialect, errmsg) unsigned long insn; long value ATTRIBUTE_UNUSED; + int dialect ATTRIBUTE_UNUSED; const char **errmsg ATTRIBUTE_UNUSED; { return insn | (((insn >> 21) & 0x1f) << 16); } static long -extract_bat (insn, invalid) +extract_bat (insn, dialect, invalid) unsigned long insn; + int dialect ATTRIBUTE_UNUSED; int *invalid; { if (invalid != (int *) NULL @@ -469,17 +545,19 @@ extract_bat (insn, invalid) /*ARGSUSED*/ static unsigned long -insert_bba (insn, value, errmsg) +insert_bba (insn, value, dialect, errmsg) unsigned long insn; long value ATTRIBUTE_UNUSED; + int dialect ATTRIBUTE_UNUSED; const char **errmsg ATTRIBUTE_UNUSED; { return insn | (((insn >> 16) & 0x1f) << 11); } static long -extract_bba (insn, invalid) +extract_bba (insn, dialect, invalid) unsigned long insn; + int dialect ATTRIBUTE_UNUSED; int *invalid; { if (invalid != (int *) NULL @@ -493,9 +571,10 @@ extract_bba (insn, invalid) /*ARGSUSED*/ static unsigned long -insert_bd (insn, value, errmsg) +insert_bd (insn, value, dialect, errmsg) unsigned long insn; long value; + int dialect ATTRIBUTE_UNUSED; const char **errmsg ATTRIBUTE_UNUSED; { return insn | (value & 0xfffc); @@ -503,48 +582,69 @@ insert_bd (insn, value, errmsg) /*ARGSUSED*/ static long -extract_bd (insn, invalid) +extract_bd (insn, dialect, invalid) unsigned long insn; + int dialect ATTRIBUTE_UNUSED; int *invalid ATTRIBUTE_UNUSED; { - if ((insn & 0x8000) != 0) - return (insn & 0xfffc) - 0x10000; - else - return insn & 0xfffc; + return ((insn & 0xfffc) ^ 0x8000) - 0x8000; } /* The BD field in a B form instruction when the - modifier is used. This modifier means that the branch is not expected to be taken. - We must set the y bit of the BO field to 1 if the offset is - negative. When extracting, we require that the y bit be 1 and that - the offset be positive, since if the y bit is 0 we just want to - print the normal form of the instruction. */ + For 32 bit targets we set the y bit of the BO field to 1 if the + offset is negative. When extracting, we require that the y bit be + 1 and that the offset be positive, since if the y bit is 0 we just + want to print the normal form of the instruction. + 64 bit targets use two bits, "a", and "t", instead of the "y" bit. + at == 10 => not taken, at == 11 => taken. The t bit is 00001 in + BO field, the a bit is 00010 for branch on CR(BI) and 01000 for + branch on CTR. */ /*ARGSUSED*/ static unsigned long -insert_bdm (insn, value, errmsg) +insert_bdm (insn, value, dialect, errmsg) unsigned long insn; long value; + int dialect; const char **errmsg ATTRIBUTE_UNUSED; { - if ((value & 0x8000) != 0) - insn |= 1 << 21; + if ((dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_64)) != PPC_OPCODE_64) + { + if ((value & 0x8000) != 0) + insn |= 1 << 21; + } + else + { + if ((insn & (0x14 << 21)) == (0x04 << 21)) + insn |= 0x02 << 21; + else if ((insn & (0x14 << 21)) == (0x10 << 21)) + insn |= 0x08 << 21; + } return insn | (value & 0xfffc); } static long -extract_bdm (insn, invalid) +extract_bdm (insn, dialect, invalid) unsigned long insn; + int dialect; int *invalid; { - if (invalid != (int *) NULL - && ((insn & (1 << 21)) == 0 - || (insn & (1 << 15)) == 0)) - *invalid = 1; - if ((insn & 0x8000) != 0) - return (insn & 0xfffc) - 0x10000; - else - return insn & 0xfffc; + if (invalid != (int *) NULL) + { + if ((dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_64)) != PPC_OPCODE_64) + { + if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) + *invalid = 1; + } + else + { + if ((insn & (0x17 << 21)) != (0x06 << 21) + && (insn & (0x1d << 21)) != (0x18 << 21)) + *invalid = 1; + } + } + return ((insn & 0xfffc) ^ 0x8000) - 0x8000; } /* The BD field in a B form instruction when the + modifier is used. @@ -553,56 +653,100 @@ extract_bdm (insn, invalid) /*ARGSUSED*/ static unsigned long -insert_bdp (insn, value, errmsg) +insert_bdp (insn, value, dialect, errmsg) unsigned long insn; long value; + int dialect; const char **errmsg ATTRIBUTE_UNUSED; { - if ((value & 0x8000) == 0) - insn |= 1 << 21; + if ((dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_64)) != PPC_OPCODE_64) + { + if ((value & 0x8000) == 0) + insn |= 1 << 21; + } + else + { + if ((insn & (0x14 << 21)) == (0x04 << 21)) + insn |= 0x03 << 21; + else if ((insn & (0x14 << 21)) == (0x10 << 21)) + insn |= 0x09 << 21; + } return insn | (value & 0xfffc); } static long -extract_bdp (insn, invalid) +extract_bdp (insn, dialect, invalid) unsigned long insn; + int dialect; int *invalid; { - if (invalid != (int *) NULL - && ((insn & (1 << 21)) == 0 - || (insn & (1 << 15)) != 0)) - *invalid = 1; - if ((insn & 0x8000) != 0) - return (insn & 0xfffc) - 0x10000; - else - return insn & 0xfffc; + if (invalid != (int *) NULL) + { + if ((dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_64)) != PPC_OPCODE_64) + { + if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) + *invalid = 1; + } + else + { + if ((insn & (0x17 << 21)) != (0x07 << 21) + && (insn & (0x1d << 21)) != (0x19 << 21)) + *invalid = 1; + } + } + return ((insn & 0xfffc) ^ 0x8000) - 0x8000; } /* Check for legal values of a BO field. */ static int -valid_bo (value) +valid_bo (value, dialect) long value; + int dialect; { - /* Certain encodings have bits that are required to be zero. These - are (z must be zero, y may be anything): - 001zy - 011zy - 1z00y - 1z01y - 1z1zz - */ - switch (value & 0x14) + if ((dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_64)) != PPC_OPCODE_64) + { + /* Certain encodings have bits that are required to be zero. + These are (z must be zero, y may be anything): + 001zy + 011zy + 1z00y + 1z01y + 1z1zz + */ + switch (value & 0x14) + { + default: + case 0: + return 1; + case 0x4: + return (value & 0x2) == 0; + case 0x10: + return (value & 0x8) == 0; + case 0x14: + return value == 0x14; + } + } + else { - default: - case 0: - return 1; - case 0x4: - return (value & 0x2) == 0; - case 0x10: - return (value & 0x8) == 0; - case 0x14: - return value == 0x14; + /* Certain encodings have bits that are required to be zero. + These are (z must be zero, a & t may be anything): + 0000z + 0001z + 0100z + 0101z + 001at + 011at + 1a00t + 1a01t + 1z1zz + */ + if ((value & 0x14) == 0) + return (value & 0x1) == 0; + else if ((value & 0x14) == 0x14) + return value == 0x14; + else + return 1; } } @@ -610,27 +754,29 @@ valid_bo (value) the field to an illegal value. */ static unsigned long -insert_bo (insn, value, errmsg) +insert_bo (insn, value, dialect, errmsg) unsigned long insn; long value; + int dialect; const char **errmsg; { if (errmsg != (const char **) NULL - && ! valid_bo (value)) + && ! valid_bo (value, dialect)) *errmsg = _("invalid conditional option"); return insn | ((value & 0x1f) << 21); } static long -extract_bo (insn, invalid) +extract_bo (insn, dialect, invalid) unsigned long insn; + int dialect; int *invalid; { long value; value = (insn >> 21) & 0x1f; if (invalid != (int *) NULL - && ! valid_bo (value)) + && ! valid_bo (value, dialect)) *invalid = 1; return value; } @@ -640,14 +786,15 @@ extract_bo (insn, invalid) extracting it, we force it to be even. */ static unsigned long -insert_boe (insn, value, errmsg) +insert_boe (insn, value, dialect, errmsg) unsigned long insn; long value; + int dialect; const char **errmsg; { if (errmsg != (const char **) NULL) { - if (! valid_bo (value)) + if (! valid_bo (value, dialect)) *errmsg = _("invalid conditional option"); else if ((value & 1) != 0) *errmsg = _("attempt to set y bit when using + or - modifier"); @@ -656,15 +803,16 @@ insert_boe (insn, value, errmsg) } static long -extract_boe (insn, invalid) +extract_boe (insn, dialect, invalid) unsigned long insn; + int dialect; int *invalid; { long value; value = (insn >> 21) & 0x1f; if (invalid != (int *) NULL - && ! valid_bo (value)) + && ! valid_bo (value, dialect)) *invalid = 1; return value & 0x1e; } @@ -674,24 +822,77 @@ extract_boe (insn, invalid) /*ARGSUSED*/ static unsigned long -insert_ds (insn, value, errmsg) +insert_ds (insn, value, dialect, errmsg) unsigned long insn; long value; - const char **errmsg ATTRIBUTE_UNUSED; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg; { + if ((value & 3) != 0 && errmsg != NULL) + *errmsg = _("offset not a multiple of 4"); return insn | (value & 0xfffc); } /*ARGSUSED*/ static long -extract_ds (insn, invalid) +extract_ds (insn, dialect, invalid) unsigned long insn; + int dialect ATTRIBUTE_UNUSED; int *invalid ATTRIBUTE_UNUSED; { - if ((insn & 0x8000) != 0) - return (insn & 0xfffc) - 0x10000; - else - return insn & 0xfffc; + return ((insn & 0xfffc) ^ 0x8000) - 0x8000; +} + +/* The DE field in a DE form instruction. */ + +/*ARGSUSED*/ +static unsigned long +insert_de (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg; +{ + if ((value > 2047 || value < -2048) && errmsg != NULL) + *errmsg = _("offset not between -2048 and 2047"); + return insn | ((value << 4) & 0xfff0); +} + +/*ARGSUSED*/ +static long +extract_de (insn, dialect, invalid) + unsigned long insn; + int dialect ATTRIBUTE_UNUSED; + int *invalid ATTRIBUTE_UNUSED; +{ + return (insn & 0xfff0) >> 4; +} + +/* The DES field in a DES form instruction. */ + +/*ARGSUSED*/ +static unsigned long +insert_des (insn, value, dialect, errmsg) + unsigned long insn; + long value; + int dialect ATTRIBUTE_UNUSED; + const char **errmsg; +{ + if ((value > 8191 || value < -8192) && errmsg != NULL) + *errmsg = _("offset not between -8192 and 8191"); + else if ((value & 3) != 0 && errmsg != NULL) + *errmsg = _("offset not a multiple of 4"); + return insn | ((value << 2) & 0xfff0); +} + +/*ARGSUSED*/ +static long +extract_des (insn, dialect, invalid) + unsigned long insn; + int dialect ATTRIBUTE_UNUSED; + int *invalid ATTRIBUTE_UNUSED; +{ + return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000; } /* The LI field in an I form instruction. The lower two bits are @@ -699,9 +900,10 @@ extract_ds (insn, invalid) /*ARGSUSED*/ static unsigned long -insert_li (insn, value, errmsg) +insert_li (insn, value, dialect, errmsg) unsigned long insn; long value; + int dialect ATTRIBUTE_UNUSED; const char **errmsg; { if ((value & 3) != 0 && errmsg != (const char **) NULL) @@ -711,14 +913,12 @@ insert_li (insn, value, errmsg) /*ARGSUSED*/ static long -extract_li (insn, invalid) +extract_li (insn, dialect, invalid) unsigned long insn; + int dialect ATTRIBUTE_UNUSED; int *invalid ATTRIBUTE_UNUSED; { - if ((insn & 0x2000000) != 0) - return (insn & 0x3fffffc) - 0x4000000; - else - return insn & 0x3fffffc; + return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000; } /* The MB and ME fields in an M form instruction expressed as a single @@ -727,9 +927,10 @@ extract_li (insn, invalid) instruction which uses a field of this type. */ static unsigned long -insert_mbe (insn, value, errmsg) +insert_mbe (insn, value, dialect, errmsg) unsigned long insn; long value; + int dialect ATTRIBUTE_UNUSED; const char **errmsg; { unsigned long uval, mask; @@ -784,8 +985,9 @@ insert_mbe (insn, value, errmsg) } static long -extract_mbe (insn, invalid) +extract_mbe (insn, dialect, invalid) unsigned long insn; + int dialect ATTRIBUTE_UNUSED; int *invalid; { long ret; @@ -819,9 +1021,10 @@ extract_mbe (insn, invalid) /*ARGSUSED*/ static unsigned long -insert_mb6 (insn, value, errmsg) +insert_mb6 (insn, value, dialect, errmsg) unsigned long insn; long value; + int dialect ATTRIBUTE_UNUSED; const char **errmsg ATTRIBUTE_UNUSED; { return insn | ((value & 0x1f) << 6) | (value & 0x20); @@ -829,8 +1032,9 @@ insert_mb6 (insn, value, errmsg) /*ARGSUSED*/ static long -extract_mb6 (insn, invalid) +extract_mb6 (insn, dialect, invalid) unsigned long insn; + int dialect ATTRIBUTE_UNUSED; int *invalid ATTRIBUTE_UNUSED; { return ((insn >> 6) & 0x1f) | (insn & 0x20); @@ -840,9 +1044,10 @@ extract_mb6 (insn, invalid) 0. */ static unsigned long -insert_nb (insn, value, errmsg) +insert_nb (insn, value, dialect, errmsg) unsigned long insn; long value; + int dialect ATTRIBUTE_UNUSED; const char **errmsg; { if (value < 0 || value > 32) @@ -854,8 +1059,9 @@ insert_nb (insn, value, errmsg) /*ARGSUSED*/ static long -extract_nb (insn, invalid) +extract_nb (insn, dialect, invalid) unsigned long insn; + int dialect ATTRIBUTE_UNUSED; int *invalid ATTRIBUTE_UNUSED; { long ret; @@ -873,25 +1079,24 @@ extract_nb (insn, invalid) /*ARGSUSED*/ static unsigned long -insert_nsi (insn, value, errmsg) +insert_nsi (insn, value, dialect, errmsg) unsigned long insn; long value; + int dialect ATTRIBUTE_UNUSED; const char **errmsg ATTRIBUTE_UNUSED; { return insn | ((- value) & 0xffff); } static long -extract_nsi (insn, invalid) +extract_nsi (insn, dialect, invalid) unsigned long insn; + int dialect ATTRIBUTE_UNUSED; int *invalid; { if (invalid != (int *) NULL) *invalid = 1; - if ((insn & 0x8000) != 0) - return - ((long)(insn & 0xffff) - 0x10000); - else - return - (long)(insn & 0xffff); + return - (((insn & 0xffff) ^ 0x8000) - 0x8000); } /* The RA field in a D or X form instruction which is an updating @@ -899,9 +1104,10 @@ extract_nsi (insn, invalid) equal the RT field. */ static unsigned long -insert_ral (insn, value, errmsg) +insert_ral (insn, value, dialect, errmsg) unsigned long insn; long value; + int dialect ATTRIBUTE_UNUSED; const char **errmsg; { if (value == 0 @@ -914,9 +1120,10 @@ insert_ral (insn, value, errmsg) restrictions. */ static unsigned long -insert_ram (insn, value, errmsg) +insert_ram (insn, value, dialect, errmsg) unsigned long insn; long value; + int dialect ATTRIBUTE_UNUSED; const char **errmsg; { if ((unsigned long) value >= ((insn >> 21) & 0x1f)) @@ -929,9 +1136,10 @@ insert_ram (insn, value, errmsg) field may not be zero. */ static unsigned long -insert_ras (insn, value, errmsg) +insert_ras (insn, value, dialect, errmsg) unsigned long insn; long value; + int dialect ATTRIBUTE_UNUSED; const char **errmsg; { if (value == 0) @@ -947,17 +1155,19 @@ insert_ras (insn, value, errmsg) /*ARGSUSED*/ static unsigned long -insert_rbs (insn, value, errmsg) +insert_rbs (insn, value, dialect, errmsg) unsigned long insn; long value ATTRIBUTE_UNUSED; + int dialect ATTRIBUTE_UNUSED; const char **errmsg ATTRIBUTE_UNUSED; { return insn | (((insn >> 21) & 0x1f) << 11); } static long -extract_rbs (insn, invalid) +extract_rbs (insn, dialect, invalid) unsigned long insn; + int dialect ATTRIBUTE_UNUSED; int *invalid; { if (invalid != (int *) NULL @@ -970,9 +1180,10 @@ extract_rbs (insn, invalid) /*ARGSUSED*/ static unsigned long -insert_sh6 (insn, value, errmsg) +insert_sh6 (insn, value, dialect, errmsg) unsigned long insn; long value; + int dialect ATTRIBUTE_UNUSED; const char **errmsg ATTRIBUTE_UNUSED; { return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); @@ -980,8 +1191,9 @@ insert_sh6 (insn, value, errmsg) /*ARGSUSED*/ static long -extract_sh6 (insn, invalid) +extract_sh6 (insn, dialect, invalid) unsigned long insn; + int dialect ATTRIBUTE_UNUSED; int *invalid ATTRIBUTE_UNUSED; { return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); @@ -991,17 +1203,19 @@ extract_sh6 (insn, invalid) lower 5 bits are stored in the upper 5 and vice- versa. */ static unsigned long -insert_spr (insn, value, errmsg) +insert_spr (insn, value, dialect, errmsg) unsigned long insn; long value; + int dialect ATTRIBUTE_UNUSED; const char **errmsg ATTRIBUTE_UNUSED; { return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); } static long -extract_spr (insn, invalid) +extract_spr (insn, dialect, invalid) unsigned long insn; + int dialect ATTRIBUTE_UNUSED; int *invalid ATTRIBUTE_UNUSED; { return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); @@ -1018,9 +1232,10 @@ extract_spr (insn, invalid) #define TB (268) static unsigned long -insert_tbr (insn, value, errmsg) +insert_tbr (insn, value, dialect, errmsg) unsigned long insn; long value; + int dialect ATTRIBUTE_UNUSED; const char **errmsg ATTRIBUTE_UNUSED; { if (value == 0) @@ -1029,8 +1244,9 @@ insert_tbr (insn, value, errmsg) } static long -extract_tbr (insn, invalid) +extract_tbr (insn, dialect, invalid) unsigned long insn; + int dialect ATTRIBUTE_UNUSED; int *invalid ATTRIBUTE_UNUSED; { long ret; @@ -1082,9 +1298,12 @@ extract_tbr (insn, invalid) /* A BBO_MASK with the y bit of the BO field removed. This permits matching a conditional branch regardless of the setting of the y - bit. */ -#define Y_MASK (((unsigned long)1) << 21) -#define BBOY_MASK (BBO_MASK &~ Y_MASK) + bit. Similarly for the 'at' bits used for 64 bit branch hints. */ +#define Y_MASK (((unsigned long) 1) << 21) +#define AT1_MASK (((unsigned long) 3) << 21) +#define AT2_MASK (((unsigned long) 9) << 21) +#define BBOY_MASK (BBO_MASK &~ Y_MASK) +#define BBOAT_MASK (BBO_MASK &~ AT1_MASK) /* A B form instruction setting the BO field and the condition bits of the BI field. */ @@ -1094,9 +1313,12 @@ extract_tbr (insn, invalid) /* A BBOCB_MASK with the y bit of the BO field removed. */ #define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK) +#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK) +#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK) /* A BBOYCB_MASK in which the BI field is fixed. */ #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) +#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) /* The main opcode mask with the RA field clear. */ #define DRA_MASK (OP_MASK | RA_MASK) @@ -1105,6 +1327,10 @@ extract_tbr (insn, invalid) #define DSO(op, xop) (OP (op) | ((xop) & 0x3)) #define DS_MASK DSO (0x3f, 3) +/* A DE form instruction. */ +#define DEO(op, xop) (OP (op) | ((xop) & 0xf)) +#define DE_MASK DEO (0x3e, 0xf) + /* An M form instruction. */ #define M(op, rc) (OP (op) | ((rc) & 1)) #define M_MASK M (0x3f, 1) @@ -1146,10 +1372,10 @@ extract_tbr (insn, invalid) #define VX_MASK VX(0x3f, 0x7ff) /* An VA form instruction. */ -#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x07f)) +#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f)) /* The mask for an VA form instruction. */ -#define VXA_MASK VXA(0x3f, 0x7f) +#define VXA_MASK VXA(0x3f, 0x3f) /* An VXR form instruction. */ #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff)) @@ -1199,6 +1425,16 @@ extract_tbr (insn, invalid) #define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11)) #define XTLB_MASK (X_MASK | SH_MASK) +/* An X form sync instruction. */ +#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21)) + +/* An X form sync instruction with everything filled in except the LS field. */ +#define XSYNC_MASK (0xff9fffff) + +/* An X form AltiVec dss instruction. */ +#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25)) +#define XDSS_MASK XDSS(0x3f, 0x3ff, 1) + /* An XFL form instruction. */ #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16)) @@ -1279,18 +1515,29 @@ extract_tbr (insn, invalid) #define BODNZFP (0x1) #define BODZF (0x2) #define BODZFP (0x3) -#define BOF (0x4) -#define BOFP (0x5) #define BODNZT (0x8) #define BODNZTP (0x9) #define BODZT (0xa) #define BODZTP (0xb) + +#define BOF (0x4) +#define BOFP (0x5) +#define BOFM64 (0x6) +#define BOFP64 (0x7) #define BOT (0xc) #define BOTP (0xd) +#define BOTM64 (0xe) +#define BOTP64 (0xf) + #define BODNZ (0x10) #define BODNZP (0x11) #define BODZ (0x12) #define BODZP (0x13) +#define BODNZM64 (0x18) +#define BODNZP64 (0x19) +#define BODZM64 (0x1a) +#define BODZP64 (0x1b) + #define BOU (0x14) /* The BI condition bit encodings used in extended conditional branch @@ -1322,14 +1569,16 @@ extract_tbr (insn, invalid) #undef PPC #define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY #define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY -#define PPC32 PPC_OPCODE_PPC | PPC_OPCODE_32 | PPC_OPCODE_ANY -#define PPC64 PPC_OPCODE_PPC | PPC_OPCODE_64 | PPC_OPCODE_ANY +#define PPCCOM32 PPC_OPCODE_32 | PPCCOM +#define PPCCOM64 PPC_OPCODE_64 | PPCCOM +#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC | PPC_OPCODE_ANY +#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC | PPC_OPCODE_ANY #define PPCONLY PPC_OPCODE_PPC -#define PPC403 PPC +#define PPC403 PPC_OPCODE_403 #define PPC405 PPC403 #define PPC750 PPC #define PPC860 PPC -#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY +#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC #define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY #define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY #define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY @@ -1340,6 +1589,8 @@ extract_tbr (insn, invalid) #define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY #define MFDEC1 PPC_OPCODE_POWER #define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 +#define BOOKE PPC_OPCODE_BOOKE +#define BOOKE64 PPC_OPCODE_BOOKE64 /* The opcode table. @@ -1492,7 +1743,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } }, { "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } }, { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } }, -{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VD } }, +{ "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } }, { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } }, { "vaddfp", VX(4, 10), VX_MASK, PPCVEC, { VD, VA, VB } }, { "vaddsbs", VX(4, 768), VX_MASK, PPCVEC, { VD, VA, VB } }, @@ -1657,6 +1908,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "dozi", OP(9), OP_MASK, M601, { RT, RA, SI } }, +{ "bce", B(9,0,0), B_MASK, BOOKE64, { BO, BI, BD } }, +{ "bcel", B(9,0,1), B_MASK, BOOKE64, { BO, BI, BD } }, +{ "bcea", B(9,1,0), B_MASK, BOOKE64, { BO, BI, BDA } }, +{ "bcela", B(9,1,1), B_MASK, BOOKE64, { BO, BI, BDA } }, + { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, { "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } }, @@ -1688,257 +1944,257 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } }, { "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } }, -{ "bdnz-", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM, { BDM } }, -{ "bdnz+", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM, { BDP } }, -{ "bdnz", BBO(16,BODNZ,0,0), BBOYBI_MASK, PPCCOM, { BD } }, -{ "bdn", BBO(16,BODNZ,0,0), BBOYBI_MASK, PWRCOM, { BD } }, -{ "bdnzl-", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM, { BDM } }, -{ "bdnzl+", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM, { BDP } }, -{ "bdnzl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PPCCOM, { BD } }, -{ "bdnl", BBO(16,BODNZ,0,1), BBOYBI_MASK, PWRCOM, { BD } }, -{ "bdnza-", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM, { BDMA } }, -{ "bdnza+", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM, { BDPA } }, -{ "bdnza", BBO(16,BODNZ,1,0), BBOYBI_MASK, PPCCOM, { BDA } }, -{ "bdna", BBO(16,BODNZ,1,0), BBOYBI_MASK, PWRCOM, { BDA } }, -{ "bdnzla-", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM, { BDMA } }, -{ "bdnzla+", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM, { BDPA } }, -{ "bdnzla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PPCCOM, { BDA } }, -{ "bdnla", BBO(16,BODNZ,1,1), BBOYBI_MASK, PWRCOM, { BDA } }, -{ "bdz-", BBO(16,BODZ,0,0), BBOYBI_MASK, PPCCOM, { BDM } }, -{ "bdz+", BBO(16,BODZ,0,0), BBOYBI_MASK, PPCCOM, { BDP } }, -{ "bdz", BBO(16,BODZ,0,0), BBOYBI_MASK, COM, { BD } }, -{ "bdzl-", BBO(16,BODZ,0,1), BBOYBI_MASK, PPCCOM, { BDM } }, -{ "bdzl+", BBO(16,BODZ,0,1), BBOYBI_MASK, PPCCOM, { BDP } }, -{ "bdzl", BBO(16,BODZ,0,1), BBOYBI_MASK, COM, { BD } }, -{ "bdza-", BBO(16,BODZ,1,0), BBOYBI_MASK, PPCCOM, { BDMA } }, -{ "bdza+", BBO(16,BODZ,1,0), BBOYBI_MASK, PPCCOM, { BDPA } }, -{ "bdza", BBO(16,BODZ,1,0), BBOYBI_MASK, COM, { BDA } }, -{ "bdzla-", BBO(16,BODZ,1,1), BBOYBI_MASK, PPCCOM, { BDMA } }, -{ "bdzla+", BBO(16,BODZ,1,1), BBOYBI_MASK, PPCCOM, { BDPA } }, -{ "bdzla", BBO(16,BODZ,1,1), BBOYBI_MASK, COM, { BDA } }, -{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOYCB_MASK, COM, { CR, BD } }, -{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOYCB_MASK, COM, { CR, BD } }, -{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOYCB_MASK, COM, { CR, BD } }, -{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOYCB_MASK, COM, { CR, BD } }, -{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOYCB_MASK, COM, { CR, BDA } }, -{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOYCB_MASK, COM, { CR, BD } }, -{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOYCB_MASK, COM, { CR, BD } }, -{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOYCB_MASK, COM, { CR, BDA } }, -{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, COM, { CR, BD } }, -{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, COM, { CR, BD } }, -{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BD } }, -{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BD } }, -{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDA } }, -{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDA } }, -{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM, { CR, BD } }, -{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM, { CR, BD } }, -{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOYCB_MASK, COM, { CR, BD } }, -{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOYCB_MASK, COM, { CR, BD } }, -{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOYCB_MASK, COM, { CR, BDA } }, -{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM, { CR, BD } }, -{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM, { CR, BD } }, -{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM, { CR, BDA } }, -{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOYCB_MASK, COM, { CR, BD } }, -{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOYCB_MASK, COM, { CR, BD } }, -{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOYCB_MASK, COM, { CR, BD } }, -{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOYCB_MASK, COM, { CR, BD } }, -{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, COM, { CR, BD } }, -{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, COM, { CR, BD } }, -{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, COM, { CR, BDA } }, -{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOYCB_MASK, PPCCOM, { CR, BD } }, -{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDM } }, -{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BDP } }, -{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOYCB_MASK, PPCCOM, { CR, BD } }, -{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOYCB_MASK, PPCCOM, { CR, BDA } }, -{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDMA } }, -{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDPA } }, -{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOYCB_MASK, PPCCOM, { CR, BDA } }, -{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BDM } }, -{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BDP } }, +{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, +{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, +{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } }, +{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } }, +{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, +{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, +{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } }, +{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } }, +{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, +{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, +{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } }, +{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } }, +{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, +{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, +{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } }, +{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } }, +{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, +{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, +{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } }, +{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, +{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, +{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } }, +{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, +{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, +{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } }, +{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, +{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, +{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } }, +{ "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, +{ "bltl-", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bltl+", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bltl", BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, +{ "blta-", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "blta+", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "blta", BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bltla-", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bltla+", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bltla", BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bgt-", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bgt+", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bgt", BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, +{ "bgtl-", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bgtl+", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bgtl", BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, +{ "bgta-", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bgta+", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bgta", BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bgtla-", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bgtla+", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bgtla", BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, +{ "beq-", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "beq+", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "beq", BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, +{ "beql-", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "beql+", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "beql", BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, +{ "beqa-", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "beqa+", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "beqa", BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, +{ "beqla-", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "beqla+", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "beqla", BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bso-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bso+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bso", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, +{ "bsol-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bsol+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bsol", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, +{ "bsoa-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bsoa+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bsoa", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bsola-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bsola+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bsola", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bun-", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bun+", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bun", BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, +{ "bunl-", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bunl+", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bunl", BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, +{ "buna-", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "buna+", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "buna", BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, +{ "bunla-", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bunla+", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bunla", BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, +{ "bge-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bge+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bge", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, +{ "bgel-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bgel+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bgel", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, +{ "bgea-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bgea+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bgea", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bgela-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bgela+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bgela", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bnl-", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bnl+", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bnl", BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, +{ "bnll-", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bnll+", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bnll", BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM, { CR, BD } }, +{ "bnla-", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bnla+", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bnla", BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bnlla-", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bnlla+", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bnlla", BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, +{ "ble-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "ble+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "ble", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, +{ "blel-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "blel+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "blel", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, +{ "blea-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "blea+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "blea", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, +{ "blela-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "blela+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "blela", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bng-", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bng+", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bng", BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM, { CR, BD } }, +{ "bngl-", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bngl+", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bngl", BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM, { CR, BD } }, +{ "bnga-", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bnga+", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bnga", BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bngla-", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bngla+", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bngla", BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bne-", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bne+", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bne", BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM, { CR, BD } }, +{ "bnel-", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bnel+", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bnel", BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM, { CR, BD } }, +{ "bnea-", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bnea+", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bnea", BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bnela-", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bnela+", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bnela", BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bns-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bns+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bns", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM, { CR, BD } }, +{ "bnsl-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bnsl+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bnsl", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM, { CR, BD } }, +{ "bnsa-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bnsa+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bnsa", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bnsla-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bnsla+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bnsla", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM, { CR, BDA } }, +{ "bnu-", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bnu+", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bnu", BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM, { CR, BD } }, +{ "bnul-", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDM } }, +{ "bnul+", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BDP } }, +{ "bnul", BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM, { CR, BD } }, +{ "bnua-", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bnua+", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bnua", BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM, { CR, BDA } }, +{ "bnula-", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDMA } }, +{ "bnula+", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDPA } }, +{ "bnula", BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM, { CR, BDA } }, +{ "bdnzt-", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM32, { BI, BDM } }, +{ "bdnzt+", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM32, { BI, BDP } }, { "bdnzt", BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BDM } }, -{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BDP } }, +{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM32, { BI, BDM } }, +{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM32, { BI, BDP } }, { "bdnztl", BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } }, -{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } }, +{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM32, { BI, BDMA } }, +{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM32, { BI, BDPA } }, { "bdnzta", BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } }, -{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } }, +{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM32, { BI, BDMA } }, +{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM32, { BI, BDPA } }, { "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BDM } }, -{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BDP } }, +{ "bdnzf-", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM32, { BI, BDM } }, +{ "bdnzf+", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM32, { BI, BDP } }, { "bdnzf", BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BDM } }, -{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BDP } }, +{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM32, { BI, BDM } }, +{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM32, { BI, BDP } }, { "bdnzfl", BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } }, -{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } }, +{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM32, { BI, BDMA } }, +{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM32, { BI, BDPA } }, { "bdnzfa", BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } }, -{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } }, +{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM32, { BI, BDMA } }, +{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM32, { BI, BDPA } }, { "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bt-", BBO(16,BOT,0,0), BBOY_MASK, PPCCOM, { BI, BDM } }, -{ "bt+", BBO(16,BOT,0,0), BBOY_MASK, PPCCOM, { BI, BDP } }, -{ "bt", BBO(16,BOT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bbt", BBO(16,BOT,0,0), BBOY_MASK, PWRCOM, { BI, BD } }, -{ "btl-", BBO(16,BOT,0,1), BBOY_MASK, PPCCOM, { BI, BDM } }, -{ "btl+", BBO(16,BOT,0,1), BBOY_MASK, PPCCOM, { BI, BDP } }, -{ "btl", BBO(16,BOT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bbtl", BBO(16,BOT,0,1), BBOY_MASK, PWRCOM, { BI, BD } }, -{ "bta-", BBO(16,BOT,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } }, -{ "bta+", BBO(16,BOT,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } }, -{ "bta", BBO(16,BOT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bbta", BBO(16,BOT,1,0), BBOY_MASK, PWRCOM, { BI, BDA } }, -{ "btla-", BBO(16,BOT,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } }, -{ "btla+", BBO(16,BOT,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } }, -{ "btla", BBO(16,BOT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bbtla", BBO(16,BOT,1,1), BBOY_MASK, PWRCOM, { BI, BDA } }, -{ "bf-", BBO(16,BOF,0,0), BBOY_MASK, PPCCOM, { BI, BDM } }, -{ "bf+", BBO(16,BOF,0,0), BBOY_MASK, PPCCOM, { BI, BDP } }, -{ "bf", BBO(16,BOF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bbf", BBO(16,BOF,0,0), BBOY_MASK, PWRCOM, { BI, BD } }, -{ "bfl-", BBO(16,BOF,0,1), BBOY_MASK, PPCCOM, { BI, BDM } }, -{ "bfl+", BBO(16,BOF,0,1), BBOY_MASK, PPCCOM, { BI, BDP } }, -{ "bfl", BBO(16,BOF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bbfl", BBO(16,BOF,0,1), BBOY_MASK, PWRCOM, { BI, BD } }, -{ "bfa-", BBO(16,BOF,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } }, -{ "bfa+", BBO(16,BOF,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } }, -{ "bfa", BBO(16,BOF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bbfa", BBO(16,BOF,1,0), BBOY_MASK, PWRCOM, { BI, BDA } }, -{ "bfla-", BBO(16,BOF,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } }, -{ "bfla+", BBO(16,BOF,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } }, -{ "bfla", BBO(16,BOF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bbfla", BBO(16,BOF,1,1), BBOY_MASK, PWRCOM, { BI, BDA } }, -{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BDM } }, -{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BDP } }, +{ "bt-", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, +{ "bt+", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, +{ "bt", BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, +{ "bbt", BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM, { BI, BD } }, +{ "btl-", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, +{ "btl+", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, +{ "btl", BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, +{ "bbtl", BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM, { BI, BD } }, +{ "bta-", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, +{ "bta+", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, +{ "bta", BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, +{ "bbta", BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } }, +{ "btla-", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, +{ "btla+", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, +{ "btla", BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, +{ "bbtla", BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } }, +{ "bf-", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDM } }, +{ "bf+", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BDP } }, +{ "bf", BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM, { BI, BD } }, +{ "bbf", BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM, { BI, BD } }, +{ "bfl-", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDM } }, +{ "bfl+", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BDP } }, +{ "bfl", BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM, { BI, BD } }, +{ "bbfl", BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM, { BI, BD } }, +{ "bfa-", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDMA } }, +{ "bfa+", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDPA } }, +{ "bfa", BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM, { BI, BDA } }, +{ "bbfa", BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM, { BI, BDA } }, +{ "bfla-", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDMA } }, +{ "bfla+", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDPA } }, +{ "bfla", BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM, { BI, BDA } }, +{ "bbfla", BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM, { BI, BDA } }, +{ "bdzt-", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM32, { BI, BDM } }, +{ "bdzt+", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM32, { BI, BDP } }, { "bdzt", BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BDM } }, -{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BDP } }, +{ "bdztl-", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM32, { BI, BDM } }, +{ "bdztl+", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM32, { BI, BDP } }, { "bdztl", BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } }, -{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } }, +{ "bdzta-", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM32, { BI, BDMA } }, +{ "bdzta+", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM32, { BI, BDPA } }, { "bdzta", BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } }, -{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } }, +{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM32, { BI, BDMA } }, +{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM32, { BI, BDPA } }, { "bdztla", BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BDM } }, -{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BDP } }, +{ "bdzf-", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM32, { BI, BDM } }, +{ "bdzf+", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM32, { BI, BDP } }, { "bdzf", BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BDM } }, -{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BDP } }, +{ "bdzfl-", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM32, { BI, BDM } }, +{ "bdzfl+", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM32, { BI, BDP } }, { "bdzfl", BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM, { BI, BD } }, -{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDMA } }, -{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDPA } }, +{ "bdzfa-", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM32, { BI, BDMA } }, +{ "bdzfa+", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM32, { BI, BDPA } }, { "bdzfa", BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM, { BI, BDA } }, -{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDMA } }, -{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDPA } }, +{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM32, { BI, BDMA } }, +{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM32, { BI, BDPA } }, { "bdzfla", BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM, { BI, BDA } }, { "bc-", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDM } }, { "bc+", B(16,0,0), B_MASK, PPCCOM, { BOE, BI, BDP } }, @@ -1959,10 +2215,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "svca", SC(17,1,0), SC_MASK, PWRCOM, { SV } }, { "svcla", SC(17,1,1), SC_MASK, POWER, { SV } }, -{ "b", B(18,0,0), B_MASK, COM, { LI } }, -{ "bl", B(18,0,1), B_MASK, COM, { LI } }, -{ "ba", B(18,1,0), B_MASK, COM, { LIA } }, -{ "bla", B(18,1,1), B_MASK, COM, { LIA } }, +{ "b", B(18,0,0), B_MASK, COM, { LI } }, +{ "bl", B(18,0,1), B_MASK, COM, { LI } }, +{ "ba", B(18,1,0), B_MASK, COM, { LIA } }, +{ "bla", B(18,1,1), B_MASK, COM, { LIA } }, { "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } }, @@ -1971,149 +2227,213 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "blrl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } }, { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, +{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM32, { 0 } }, +{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, PPCCOM32, { 0 } }, +{ "bdnzlr-", XLO(19,BODNZM64,16,0), XLBOBIBB_MASK, PPCCOM64, { 0 } }, +{ "bdnzlr+", XLO(19,BODNZP64,16,0), XLBOBIBB_MASK, PPCCOM64, { 0 } }, { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, +{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM32, { 0 } }, +{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, PPCCOM32, { 0 } }, +{ "bdnzlrl-",XLO(19,BODNZM64,16,1), XLBOBIBB_MASK, PPCCOM64, { 0 } }, +{ "bdnzlrl+",XLO(19,BODNZP64,16,1), XLBOBIBB_MASK, PPCCOM64, { 0 } }, { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, +{ "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM32, { 0 } }, +{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, PPCCOM32, { 0 } }, +{ "bdzlr-", XLO(19,BODZM64,16,0), XLBOBIBB_MASK, PPCCOM64, { 0 } }, +{ "bdzlr+", XLO(19,BODZP64,16,0), XLBOBIBB_MASK, PPCCOM64, { 0 } }, { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, -{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, +{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM32, { 0 } }, +{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, PPCCOM32, { 0 } }, +{ "bdzlrl-", XLO(19,BODZM64,16,1), XLBOBIBB_MASK, PPCCOM64, { 0 } }, +{ "bdzlrl+", XLO(19,BODZP64,16,1), XLBOBIBB_MASK, PPCCOM64, { 0 } }, { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bltlr-", XLOCB(19,BOTM64,CBLT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bltlr+", XLOCB(19,BOTP64,CBLT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bltlrl-", XLOCB(19,BOTM64,CBLT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bltlrl+", XLOCB(19,BOTP64,CBLT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bgtlr-", XLOCB(19,BOTM64,CBGT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bgtlr+", XLOCB(19,BOTP64,CBGT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bgtlrl-", XLOCB(19,BOTM64,CBGT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bgtlrl+", XLOCB(19,BOTP64,CBGT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "beqlr-", XLOCB(19,BOTM64,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "beqlr+", XLOCB(19,BOTP64,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "beqlrl-", XLOCB(19,BOTM64,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "beqlrl+", XLOCB(19,BOTP64,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bsolr-", XLOCB(19,BOTM64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bsolr+", XLOCB(19,BOTP64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bsolrl-", XLOCB(19,BOTM64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bsolrl+", XLOCB(19,BOTP64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bunlr-", XLOCB(19,BOTM64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bunlr+", XLOCB(19,BOTP64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bunlrl-", XLOCB(19,BOTM64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bunlrl+", XLOCB(19,BOTP64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bgelr-", XLOCB(19,BOFM64,CBLT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bgelr+", XLOCB(19,BOFP64,CBLT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bgelrl-", XLOCB(19,BOFM64,CBLT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bgelrl+", XLOCB(19,BOFP64,CBLT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnllr-", XLOCB(19,BOFM64,CBLT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bnllr+", XLOCB(19,BOFP64,CBLT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnllrl-", XLOCB(19,BOFM64,CBLT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bnllrl+", XLOCB(19,BOFP64,CBLT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "blelr-", XLOCB(19,BOFM64,CBGT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "blelr+", XLOCB(19,BOFP64,CBGT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "blelrl-", XLOCB(19,BOFM64,CBGT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "blelrl+", XLOCB(19,BOFP64,CBGT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnglr-", XLOCB(19,BOFM64,CBGT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bnglr+", XLOCB(19,BOFP64,CBGT,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnglrl-", XLOCB(19,BOFM64,CBGT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bnglrl+", XLOCB(19,BOFP64,CBGT,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnelr-", XLOCB(19,BOFM64,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bnelr+", XLOCB(19,BOFP64,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnelrl-", XLOCB(19,BOFM64,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bnelrl+", XLOCB(19,BOFP64,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnslr-", XLOCB(19,BOFM64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bnslr+", XLOCB(19,BOFP64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnslrl-", XLOCB(19,BOFM64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bnslrl+", XLOCB(19,BOFP64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnulr-", XLOCB(19,BOFM64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bnulr+", XLOCB(19,BOFP64,CBSO,16,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnulrl-", XLOCB(19,BOFM64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bnulrl+", XLOCB(19,BOFP64,CBSO,16,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM, { BI } }, +{ "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "btlr-", XLO(19,BOTM64,16,0), XLBOBB_MASK, PPCCOM64, { BI } }, +{ "btlr+", XLO(19,BOTP64,16,0), XLBOBB_MASK, PPCCOM64, { BI } }, { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } }, { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM, { BI } }, +{ "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "btlrl-", XLO(19,BOTM64,16,1), XLBOBB_MASK, PPCCOM64, { BI } }, +{ "btlrl+", XLO(19,BOTP64,16,1), XLBOBB_MASK, PPCCOM64, { BI } }, { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } }, { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM, { BI } }, +{ "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "bflr-", XLO(19,BOFM64,16,0), XLBOBB_MASK, PPCCOM64, { BI } }, +{ "bflr+", XLO(19,BOFP64,16,0), XLBOBB_MASK, PPCCOM64, { BI } }, { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } }, { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM, { BI } }, +{ "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "bflrl-", XLO(19,BOFM64,16,1), XLBOBB_MASK, PPCCOM64, { BI } }, +{ "bflrl+", XLO(19,BOFP64,16,1), XLBOBB_MASK, PPCCOM64, { BI } }, { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } }, { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM, { BI } }, +{ "bdnztlr-",XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "bdnztlr+",XLO(19,BODNZTP,16,0), XLBOBB_MASK, PPCCOM32, { BI } }, { "bdnztlrl",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM,{ BI } }, +{ "bdnztlrl-",XLO(19,BODNZT,16,1), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "bdnztlrl+",XLO(19,BODNZTP,16,1), XLBOBB_MASK, PPCCOM32, { BI } }, { "bdnzflr", XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM, { BI } }, +{ "bdnzflr-",XLO(19,BODNZF,16,0), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "bdnzflr+",XLO(19,BODNZFP,16,0), XLBOBB_MASK, PPCCOM32, { BI } }, { "bdnzflrl",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM,{ BI } }, +{ "bdnzflrl-",XLO(19,BODNZF,16,1), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "bdnzflrl+",XLO(19,BODNZFP,16,1), XLBOBB_MASK, PPCCOM32, { BI } }, { "bdztlr", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM, { BI } }, +{ "bdztlr-", XLO(19,BODZT,16,0), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "bdztlr+", XLO(19,BODZTP,16,0), XLBOBB_MASK, PPCCOM32, { BI } }, { "bdztlrl", XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM, { BI } }, +{ "bdztlrl-",XLO(19,BODZT,16,1), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "bdztlrl+",XLO(19,BODZTP,16,1), XLBOBB_MASK, PPCCOM32, { BI } }, { "bdzflr", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM, { BI } }, +{ "bdzflr-", XLO(19,BODZF,16,0), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "bdzflr+", XLO(19,BODZFP,16,0), XLBOBB_MASK, PPCCOM32, { BI } }, { "bdzflrl", XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM, { BI } }, +{ "bdzflrl-",XLO(19,BODZF,16,1), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "bdzflrl+",XLO(19,BODZFP,16,1), XLBOBB_MASK, PPCCOM32, { BI } }, { "bclr", XLLK(19,16,0), XLYBB_MASK, PPCCOM, { BO, BI } }, { "bclrl", XLLK(19,16,1), XLYBB_MASK, PPCCOM, { BO, BI } }, { "bclr+", XLYLK(19,16,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, @@ -2122,6 +2442,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "bclrl-", XLYLK(19,16,0,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, { "bcr", XLLK(19,16,0), XLBB_MASK, PWRCOM, { BO, BI } }, { "bcrl", XLLK(19,16,1), XLBB_MASK, PWRCOM, { BO, BI } }, +{ "bclre", XLLK(19,17,0), XLBB_MASK, BOOKE64, { BO, BI } }, +{ "bclrel", XLLK(19,17,1), XLBB_MASK, BOOKE64, { BO, BI } }, { "rfid", XL(19,18), 0xffffffff, PPC64, { 0 } }, @@ -2130,6 +2452,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "rfi", XL(19,50), 0xffffffff, COM, { 0 } }, { "rfci", XL(19,51), 0xffffffff, PPC403, { 0 } }, +{ "rfci", XL(19,51), 0xffffffff, BOOKE, { 0 } }, { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } }, @@ -2156,89 +2479,145 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "bctr", XLO(19,BOU,528,0), XLBOBIBB_MASK, COM, { 0 } }, { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } }, { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bltctr-", XLOCB(19,BOTM64,CBLT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bltctr+", XLOCB(19,BOTP64,CBLT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bltctrl-",XLOCB(19,BOTM64,CBLT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bltctrl+",XLOCB(19,BOTP64,CBLT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bgtctr-", XLOCB(19,BOTM64,CBGT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bgtctr+", XLOCB(19,BOTP64,CBGT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bgtctrl-",XLOCB(19,BOTM64,CBGT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bgtctrl+",XLOCB(19,BOTP64,CBGT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "beqctr-", XLOCB(19,BOTM64,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "beqctr+", XLOCB(19,BOTP64,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "beqctrl-",XLOCB(19,BOTM64,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "beqctrl+",XLOCB(19,BOTP64,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bsoctr-", XLOCB(19,BOTM64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bsoctr+", XLOCB(19,BOTP64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bsoctrl-",XLOCB(19,BOTM64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bsoctrl+",XLOCB(19,BOTP64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bunctr-", XLOCB(19,BOTM64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bunctr+", XLOCB(19,BOTP64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bunctrl-",XLOCB(19,BOTM64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bunctrl+",XLOCB(19,BOTP64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bgectr-", XLOCB(19,BOFM64,CBLT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bgectr+", XLOCB(19,BOFP64,CBLT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bgectrl-",XLOCB(19,BOFM64,CBLT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bgectrl+",XLOCB(19,BOFP64,CBLT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnlctr-", XLOCB(19,BOFM64,CBLT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bnlctr+", XLOCB(19,BOFP64,CBLT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnlctrl-",XLOCB(19,BOFM64,CBLT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bnlctrl+",XLOCB(19,BOFP64,CBLT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "blectr-", XLOCB(19,BOFM64,CBGT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "blectr+", XLOCB(19,BOFP64,CBGT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "blectrl-",XLOCB(19,BOFM64,CBGT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "blectrl+",XLOCB(19,BOFP64,CBGT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bngctr-", XLOCB(19,BOFM64,CBGT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bngctr+", XLOCB(19,BOFP64,CBGT,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bngctrl-",XLOCB(19,BOFM64,CBGT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bngctrl+",XLOCB(19,BOFP64,CBGT,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnectr-", XLOCB(19,BOFM64,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bnectr+", XLOCB(19,BOFP64,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnectrl-",XLOCB(19,BOFM64,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bnectrl+",XLOCB(19,BOFP64,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnsctr-", XLOCB(19,BOFM64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bnsctr+", XLOCB(19,BOFP64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnsctrl-",XLOCB(19,BOFM64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bnsctrl+",XLOCB(19,BOFP64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnuctr-", XLOCB(19,BOFM64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bnuctr+", XLOCB(19,BOFP64,CBSO,528,0), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, -{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, +{ "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, PPCCOM32, { CR } }, +{ "bnuctrl-",XLOCB(19,BOFM64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, +{ "bnuctrl+",XLOCB(19,BOFP64,CBSO,528,1), XLBOCBBB_MASK, PPCCOM64, { CR } }, { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM, { BI } }, +{ "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "btctr-", XLO(19,BOTM64,528,0), XLBOBB_MASK, PPCCOM64, { BI } }, +{ "btctr+", XLO(19,BOTP64,528,0), XLBOBB_MASK, PPCCOM64, { BI } }, { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM, { BI } }, +{ "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "btctrl-", XLO(19,BOTM64,528,1), XLBOBB_MASK, PPCCOM64, { BI } }, +{ "btctrl+", XLO(19,BOTP64,528,1), XLBOBB_MASK, PPCCOM64, { BI } }, { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM, { BI } }, +{ "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "bfctr-", XLO(19,BOFM64,528,0), XLBOBB_MASK, PPCCOM64, { BI } }, +{ "bfctr+", XLO(19,BOFP64,528,0), XLBOBB_MASK, PPCCOM64, { BI } }, { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } }, -{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM, { BI } }, +{ "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, PPCCOM32, { BI } }, +{ "bfctrl-", XLO(19,BOFM64,528,1), XLBOBB_MASK, PPCCOM64, { BI } }, +{ "bfctrl+", XLO(19,BOFP64,528,1), XLBOBB_MASK, PPCCOM64, { BI } }, { "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } }, { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, { "bcctr+", XLYLK(19,528,1,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, @@ -2247,6 +2626,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "bcctrl+", XLYLK(19,528,1,1), XLYBB_MASK, PPCCOM, { BOE, BI } }, { "bcc", XLLK(19,528,0), XLBB_MASK, PWRCOM, { BO, BI } }, { "bccl", XLLK(19,528,1), XLBB_MASK, PWRCOM, { BO, BI } }, +{ "bcctre", XLLK(19,529,0), XLYBB_MASK, BOOKE64, { BO, BI } }, +{ "bcctrel", XLLK(19,529,1), XLYBB_MASK, BOOKE64, { BO, BI } }, { "rlwimi", M(20,0), M_MASK, PPCCOM, { RA,RS,SH,MBE,ME } }, { "rlimi", M(20,0), M_MASK, PWRCOM, { RA,RS,SH,MBE,ME } }, @@ -2266,6 +2647,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "rlmi", M(22,0), M_MASK, M601, { RA,RS,RB,MBE,ME } }, { "rlmi.", M(22,1), M_MASK, M601, { RA,RS,RB,MBE,ME } }, +{ "be", B(22,0,0), B_MASK, BOOKE64, { LI } }, +{ "bel", B(22,0,1), B_MASK, BOOKE64, { LI } }, +{ "bea", B(22,1,0), B_MASK, BOOKE64, { LIA } }, +{ "bela", B(22,1,1), B_MASK, BOOKE64, { LIA } }, + { "rotlw", MME(23,31,0), MMBME_MASK, PPCCOM, { RA, RS, RB } }, { "rlwnm", M(23,0), M_MASK, PPCCOM, { RA,RS,RB,MBE,ME } }, { "rlnm", M(23,0), M_MASK, PWRCOM, { RA,RS,RB,MBE,ME } }, @@ -2387,6 +2773,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } }, +{ "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } }, + { "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } }, { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } }, @@ -2409,6 +2797,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "maskg", XRC(31,29,0), X_MASK, M601, { RA, RS, RB } }, { "maskg.", XRC(31,29,1), X_MASK, M601, { RA, RS, RB } }, +{ "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } }, + +{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA, RB } }, + { "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, { "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, { "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB } }, @@ -2430,11 +2822,15 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "lwzux", X(31,55), X_MASK, PPCCOM, { RT, RAL, RB } }, { "lux", X(31,55), X_MASK, PWRCOM, { RT, RA, RB } }, +{ "dcbste", X(31,62), XRT_MASK, BOOKE64, { RA, RB } }, + +{ "lwzuxe", X(31,63), X_MASK, BOOKE64, { RT, RAL, RB } }, + { "cntlzd", XRC(31,58,0), XRB_MASK, PPC64, { RA, RS } }, { "cntlzd.", XRC(31,58,1), XRB_MASK, PPC64, { RA, RS } }, -{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } }, -{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } }, +{ "andc", XRC(31,60,0), X_MASK, COM, { RA, RS, RB } }, +{ "andc.", XRC(31,60,1), X_MASK, COM, { RA, RS, RB } }, { "tdlgt", XTO(31,68,TOLGT), XTO_MASK, PPC64, { RA, RB } }, { "tdllt", XTO(31,68,TOLLT), XTO_MASK, PPC64, { RA, RB } }, @@ -2468,6 +2864,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } }, +{ "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } }, + +{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA, RB } }, + { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } }, { "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } }, { "nego", XO(31,104,1,0), XORB_MASK, COM, { RT, RA } }, @@ -2489,7 +2889,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } }, { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } }, +{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA, RB } }, + +{ "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } }, + { "wrtee", X(31,131), XRARB_MASK, PPC403, { RS } }, +{ "wrtee", X(31,131), XRARB_MASK, BOOKE, { RS } }, { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, @@ -2521,6 +2926,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } }, { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } }, +{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA, RB } }, + +{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA, RB } }, + { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } }, { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } }, @@ -2528,6 +2937,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } }, { "wrteei", X(31,163), XE_MASK, PPC403, { E } }, +{ "wrteei", X(31,163), XE_MASK, BOOKE, { E } }, { "mtmsrd", X(31,178), XRARB_MASK, PPC64, { RS } }, @@ -2539,6 +2949,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } }, { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } }, +{ "stwuxe", X(31,191), X_MASK, BOOKE64, { RS, RAS, RB } }, + { "subfze", XO(31,200,0,0), XORB_MASK, PPCCOM, { RT, RA } }, { "sfze", XO(31,200,0,0), XORB_MASK, PWRCOM, { RT, RA } }, { "subfze.", XO(31,200,0,1), XORB_MASK, PPCCOM, { RT, RA } }, @@ -2561,7 +2973,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } }, -{ "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } }, +{ "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } }, { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } }, { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } }, @@ -2569,6 +2981,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } }, { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } }, +{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA, RB } }, + { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } }, { "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } }, { "subfme.", XO(31,232,0,1), XORB_MASK, PPCCOM, { RT, RA } }, @@ -2604,13 +3018,21 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } }, { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } }, -{ "dcbtst", X(31,246), XRT_MASK, PPC, { RA, RB } }, +{ "dcbtst", X(31,246), XRT_MASK, PPC, { CT, RA, RB } }, { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } }, { "slliq", XRC(31,248,0), X_MASK, M601, { RA, RS, SH } }, { "slliq.", XRC(31,248,1), X_MASK, M601, { RA, RS, SH } }, +{ "dcbtste", X(31,253), X_MASK, BOOKE64, { CT, RA, RB } }, + +{ "stbuxe", X(31,255), X_MASK, BOOKE64, { RS, RAS, RB } }, + +{ "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } }, + +{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } }, + { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } }, { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } }, { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } }, @@ -2625,18 +3047,22 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "addo.", XO(31,266,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, { "caxo.", XO(31,266,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "mfapidi", X(31,275), X_MASK, BOOKE, { RT, RA } }, + { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } }, { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } }, -{ "dcbt", X(31,278), XRT_MASK, PPC, { RA, RB } }, +{ "dcbt", X(31,278), XRT_MASK, PPC, { CT, RA, RB } }, { "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } }, -{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } }, - { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } }, { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } }, +{ "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } }, + +{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA, RB } }, + { "tlbie", X(31,306), XRTRA_MASK, PPC, { RB } }, { "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } }, @@ -2647,6 +3073,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "xor", XRC(31,316,0), X_MASK, COM, { RA, RS, RB } }, { "xor.", XRC(31,316,1), X_MASK, COM, { RA, RS, RB } }, +{ "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } }, + { "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } }, { "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } }, { "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } }, @@ -2682,6 +3110,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } }, { "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } }, { "mfdcr", X(31,323), X_MASK, PPC403, { RT, SPR } }, +{ "mfdcr", X(31,323), X_MASK, BOOKE, { RT, SPR } }, { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } }, { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } }, @@ -2719,6 +3148,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } }, { "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } }, { "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } }, +{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } }, { "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } }, { "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } }, { "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } }, @@ -2822,8 +3252,16 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } }, +{ "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, +{ "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, + { "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } }, +{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA, RB } }, + +{ "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, +{ "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, + { "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } }, { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } }, @@ -2846,6 +3284,18 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } }, +{ "lhauxe", X(31,383), X_MASK, BOOKE64, { RT, RAL, RB } }, + +{ "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } }, + +{ "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } }, +{ "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } }, + +{ "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } }, +{ "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } }, + +{ "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } }, + { "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } }, { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } }, @@ -2862,12 +3312,16 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } }, { "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } }, +{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA, RB } }, + { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } }, { "ecowx", X(31,438), X_MASK, PPC, { RT, RA, RB } }, { "sthux", X(31,439), X_MASK, COM, { RS, RAS, RB } }, +{ "sthuxe", X(31,447), X_MASK, BOOKE64, { RS, RAS, RB } }, + { "mr", XRC(31,444,0), X_MASK, COM, { RA, RS, RBS } }, { "or", XRC(31,444,0), X_MASK, COM, { RA, RS, RB } }, { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } }, @@ -2908,12 +3362,19 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RT } }, { "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RT } }, { "mtdcr", X(31,451), X_MASK, PPC403, { SPR, RS } }, +{ "mtdcr", X(31,451), X_MASK, BOOKE, { SPR, RS } }, + +{ "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } }, +{ "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } }, { "divdu", XO(31,457,0,0), XO_MASK, PPC64, { RT, RA, RB } }, { "divdu.", XO(31,457,0,1), XO_MASK, PPC64, { RT, RA, RB } }, { "divduo", XO(31,457,1,0), XO_MASK, PPC64, { RT, RA, RB } }, { "divduo.", XO(31,457,1,1), XO_MASK, PPC64, { RT, RA, RB } }, +{ "addze64", XO(31,458,0,0), XORB_MASK, BOOKE64, { RT, RA } }, +{ "addze64o",XO(31,458,1,0), XORB_MASK, BOOKE64, { RT, RA } }, + { "divwu", XO(31,459,0,0), XO_MASK, PPC, { RT, RA, RB } }, { "divwu.", XO(31,459,0,1), XO_MASK, PPC, { RT, RA, RB } }, { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } }, @@ -2949,6 +3410,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RT } }, { "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RT } }, { "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RT } }, +{ "mtvrsave",XSPR(31,467,256), XSPR_MASK, PPCVEC, { RT } }, { "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } }, { "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RT } }, { "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } }, @@ -3028,11 +3490,15 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "nand", XRC(31,476,0), X_MASK, COM, { RA, RS, RB } }, { "nand.", XRC(31,476,1), X_MASK, COM, { RA, RS, RB } }, +{ "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } }, + { "dcread", X(31,486), X_MASK, PPC403, { RT, RA, RB }}, { "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } }, +{ "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } }, { "nabs.", XO(31,488,0,1), XORB_MASK, M601, { RT, RA } }, { "nabso", XO(31,488,1,0), XORB_MASK, M601, { RT, RA } }, +{ "subfme64o",XO(31,488,1,0), XORB_MASK, BOOKE64, { RT, RA } }, { "nabso.", XO(31,488,1,1), XORB_MASK, M601, { RT, RA } }, { "divd", XO(31,489,0,0), XO_MASK, PPC64, { RT, RA, RB } }, @@ -3040,6 +3506,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "divdo", XO(31,489,1,0), XO_MASK, PPC64, { RT, RA, RB } }, { "divdo.", XO(31,489,1,1), XO_MASK, PPC64, { RT, RA, RB } }, +{ "addme64", XO(31,490,0,0), XORB_MASK, BOOKE64, { RT, RA } }, +{ "addme64o",XO(31,490,1,0), XORB_MASK, BOOKE64, { RT, RA } }, + { "divw", XO(31,491,0,0), XO_MASK, PPC, { RT, RA, RB } }, { "divw.", XO(31,491,0,1), XO_MASK, PPC, { RT, RA, RB } }, { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } }, @@ -3049,8 +3518,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } }, +{ "stdcxe.", XRC(31,511,1), X_MASK, BOOKE64, { RS, RA, RB } }, + { "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } }, +{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE, { BF } }, + { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } }, { "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } }, @@ -3075,26 +3548,39 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } }, { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } }, +{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA, RB } }, + +{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA, RB } }, + { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } }, { "lfsux", X(31,567), X_MASK, COM, { FRT, RAS, RB } }, +{ "lfsuxe", X(31,575), X_MASK, BOOKE64, { FRT, RAS, RB } }, + { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } }, { "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } }, { "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } }, -{ "sync", X(31,598), 0xffffffff, PPCCOM, { 0 } }, +{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPCONLY, { 0 } }, +{ "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } }, +{ "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } }, { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } }, +{ "msync", X(31,598), 0xf80007fe, BOOKE, { 0 } }, { "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } }, +{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA, RB } }, + { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } }, { "dclst", X(31,630), XRB_MASK, PWRCOM, { RS, RA } }, { "lfdux", X(31,631), X_MASK, COM, { FRT, RAS, RB } }, +{ "lfduxe", X(31,639), X_MASK, BOOKE64, { FRT, RAS, RB } }, + { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } }, { "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } }, @@ -3111,11 +3597,17 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } }, { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } }, +{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA, RB } }, + +{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA, RB } }, + { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } }, { "sriq", XRC(31,696,0), X_MASK, M601, { RA, RS, SH } }, { "sriq.", XRC(31,696,1), X_MASK, M601, { RA, RS, SH } }, +{ "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } }, + { "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } }, { "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB } }, @@ -3127,13 +3619,23 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } }, { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } }, +{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA, RB } }, + { "dcba", X(31,758), XRT_MASK, PPC405, { RA, RB } }, +{ "dcba", X(31,758), XRT_MASK, BOOKE, { RA, RB } }, { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } }, { "srliq", XRC(31,760,0), X_MASK, M601, { RA, RS, SH } }, { "srliq.", XRC(31,760,1), X_MASK, M601, { RA, RS, SH } }, +{ "dcbae", X(31,766), XRT_MASK, BOOKE64, { RA, RB } }, + +{ "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } }, + +{ "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } }, +{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE, { RA, RB } }, + { "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } }, { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } }, @@ -3144,17 +3646,33 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } }, { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } }, +{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA, RB } }, + +{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA, RB } }, +{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA, RB } }, + { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } }, +{ "dss", XDSS(31,822,0), XDSS_MASK, PPCVEC, { STRM } }, +{ "dssall", XDSS(31,822,1), XDSS_MASK, PPCVEC, { STRM } }, + { "srawi", XRC(31,824,0), X_MASK, PPCCOM, { RA, RS, SH } }, { "srai", XRC(31,824,0), X_MASK, PWRCOM, { RA, RS, SH } }, { "srawi.", XRC(31,824,1), X_MASK, PPCCOM, { RA, RS, SH } }, { "srai.", XRC(31,824,1), X_MASK, PWRCOM, { RA, RS, SH } }, +{ "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } }, + { "eieio", X(31,854), 0xffffffff, PPC, { 0 } }, +{ "mbar", X(31,854), 0xffffffff, BOOKE, { MO } }, + +{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } }, +{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } }, -{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } }, -{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } }, +{ "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } }, +{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE, { RA, RB } }, + +{ "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } }, { "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } }, @@ -3169,9 +3687,14 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } }, { "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } }, +{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA, RB } }, + +{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA, RB } }, + +{ "tlbre", X(31,946), X_MASK, BOOKE, { RT, RA, SH } }, + { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } }, { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } }, -{ "tlbre", X(31,946), X_MASK, PPC403, { RT, RA, SH } }, { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } }, { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } }, @@ -3179,6 +3702,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "extsb", XRC(31,954,0), XRB_MASK, PPC, { RA, RS} }, { "extsb.", XRC(31,954,1), XRB_MASK, PPC, { RA, RS} }, +{ "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } }, + { "iccci", X(31,966), XRT_MASK, PPC403, { RA, RB } }, { "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } }, @@ -3187,6 +3712,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } }, { "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } }, +{ "tlbwe", X(31,978), X_MASK, BOOKE, { RT, RA, SH } }, + { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } }, { "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } }, @@ -3196,11 +3723,16 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "icread", X(31,998), XRT_MASK, PPC403, { RA, RB } }, +{ "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } }, +{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA, RB } }, + { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } }, { "dcbz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, { "dclz", X(31,1014), XRT_MASK, PPC, { RA, RB } }, +{ "dcbze", X(31,1022), XRT_MASK, BOOKE64, { RA, RB } }, + { "lvebx", X(31, 7), X_MASK, PPCVEC, { VD, RA, RB } }, { "lvehx", X(31, 39), X_MASK, PPCVEC, { VD, RA, RB } }, { "lvewx", X(31, 71), X_MASK, PPCVEC, { VD, RA, RB } }, @@ -3272,6 +3804,21 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } }, +{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA } }, +{ "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } }, +{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA } }, +{ "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } }, +{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA } }, +{ "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } }, +{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA } }, +{ "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } }, +{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA } }, +{ "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } }, +{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA } }, +{ "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } }, +{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA } }, +{ "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } }, + { "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA } }, { "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } }, @@ -3312,6 +3859,19 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } }, +{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA } }, +{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA } }, +{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA } }, +{ "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } }, +{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA } }, +{ "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } }, +{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA } }, +{ "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } }, +{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA } }, +{ "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } }, +{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA } }, +{ "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } }, + { "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } }, { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } }, diff --git a/contrib/binutils/opcodes/sh-dis.c b/contrib/binutils/opcodes/sh-dis.c index 7091afc..ed472dc 100644 --- a/contrib/binutils/opcodes/sh-dis.c +++ b/contrib/binutils/opcodes/sh-dis.c @@ -1,5 +1,5 @@ /* Disassemble SH instructions. - Copyright 1993, 1994, 1995, 1997, 1998, 2000 + Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify @@ -26,6 +26,13 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define LITTLE_BIT 2 +static void print_movxy + PARAMS ((sh_opcode_info *, int, int, fprintf_ftype, void *)); +static void print_insn_ddt PARAMS ((int, struct disassemble_info *)); +static void print_dsp_reg PARAMS ((int, fprintf_ftype, void *)); +static void print_insn_ppi PARAMS ((int, struct disassemble_info *)); +static int print_insn_shx PARAMS ((bfd_vma, struct disassemble_info *)); + static void print_movxy (op, rn, rm, fprintf_fn, stream) sh_opcode_info *op; diff --git a/contrib/binutils/opcodes/sh-opc.h b/contrib/binutils/opcodes/sh-opc.h index 4128c08..38ba17d 100644 --- a/contrib/binutils/opcodes/sh-opc.h +++ b/contrib/binutils/opcodes/sh-opc.h @@ -835,7 +835,7 @@ sh_opcode_info sh_table[] = { /* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_NM,HEX_F,HEX_D}, arch_sh4_up}, -{ 0 } +{ 0, {0}, {0}, 0 } }; #endif |
