Import of Binutils from the FSF 2.12 branch.

(this fixes several linker problems and coredumps)
These bits are taken from the FSF anoncvs repo on 10-April-2002 13:24 Zulu

1 files changed, 21 insertions, 5 deletions

diff --git a/contrib/binutils/opcodes/ppc-opc.c b/contrib/binutils/opcodes/ppc-opc.c
index ebabb9a..c868ccc 100644
--- a/contrib/binutils/opcodes/ppc-opc.c
+++ b/contrib/binutils/opcodes/ppc-opc.c
@@ -504,6 +504,16 @@ const struct powerpc_operand powerpc_operands[] =
   /* The SHB field in a VA form instruction. */
 #define SHB UIMM + 1
   { 4, 6, 0, 0, 0 },
+
+  /* The WS field.  */
+#define WS SHB + 1
+#define WS_MASK (0x7 << 11)
+  { 3, 11, 0, 0, 0 },
+
+  /* The L field in an mtmsrd instruction */
+#define MTMSRD_L WS + 1
+  { 1, 16, 0, 0, PPC_OPERAND_OPTIONAL },
+
 };
 
 /* The functions used to insert and extract complicated operands.  */
@@ -1406,9 +1416,15 @@ extract_tbr (insn, dialect, invalid)
 /* An X_MASK with the RA and RB fields fixed.  */
 #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)
 
+/* An XRARB_MASK, but with the L bit clear. */
+#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))
+
 /* An X_MASK with the RT and RA fields fixed.  */
 #define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)
 
+/* An XRTRA_MASK, but with L bit clear.  */
+#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))
+
 /* An X form comparison instruction.  */
 #define XCMPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))
 
@@ -1797,7 +1813,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "vctuxs",    VX(4,  906), VX_MASK,	PPCVEC,		{ VD, VB, UIMM } },
 { "vexptefp",  VX(4,  394), VX_MASK,	PPCVEC,		{ VD, VB } },
 { "vlogefp",   VX(4,  458), VX_MASK,	PPCVEC,		{ VD, VB } },
-{ "vmaddfp",   VXA(4,  46), VXA_MASK,	PPCVEC,		{ VD, VA, VB, VC } },
+{ "vmaddfp",   VXA(4,  46), VXA_MASK,	PPCVEC,		{ VD, VA, VC, VB } },
 { "vmaxfp",    VX(4, 1034), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
 { "vmaxsb",    VX(4,  258), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
 { "vmaxsh",    VX(4,  322), VX_MASK,	PPCVEC,		{ VD, VA, VB } },
@@ -2941,7 +2957,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "wrteei",  X(31,163),	XE_MASK,	PPC403,		{ E } },
 { "wrteei",  X(31,163),	XE_MASK,	BOOKE,		{ E } },
 
-{ "mtmsrd",  X(31,178),	XRARB_MASK,	PPC64,		{ RS } },
+{ "mtmsrd",  X(31,178),	XRLARB_MASK,	PPC64,		{ RS, MTMSRD_L } },
 
 { "stdux",   X(31,181),	X_MASK,		PPC64,		{ RS, RAS, RB } },
 
@@ -3065,7 +3081,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "lhzxe",   X(31,287),	X_MASK,		BOOKE64,	{ RT, RA, RB } },
 
-{ "tlbie",   X(31,306),	XRTRA_MASK,	PPC,		{ RB } },
+{ "tlbie",   X(31,306),	XRTLRA_MASK,	PPC,		{ RB, L } },
 { "tlbi",    X(31,306),	XRT_MASK,	POWER,		{ RA, RB } },
 
 { "eciwx",   X(31,310), X_MASK,		PPC,		{ RT, RA, RB } },
@@ -3693,7 +3709,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 
 { "stdxe",   X(31,927), X_MASK,		BOOKE64,	{ RS, RA, RB } },
 
-{ "tlbre",   X(31,946),	X_MASK,		BOOKE,		{ RT, RA, SH } },
+{ "tlbre",   X(31,946),	X_MASK,		BOOKE,		{ RT, RA, WS } },
 
 { "tlbrehi", XTLB(31,946,0), XTLB_MASK,	PPC403,		{ RT, RA } },
 { "tlbrelo", XTLB(31,946,1), XTLB_MASK,	PPC403,		{ RT, RA } },
@@ -3714,7 +3730,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
 { "tlbwelo", XTLB(31,978,1), XTLB_MASK,	PPC403,		{ RT, RA } },
 { "tlbwe",   X(31,978),	X_MASK,		PPC403,		{ RS, RA, SH } },
 
-{ "tlbwe",   X(31,978),	X_MASK,		BOOKE,		{ RT, RA, SH } },
+{ "tlbwe",   X(31,978),	X_MASK,		BOOKE,		{ RT, RA, WS } },
 
 { "icbi",    X(31,982),	XRT_MASK,	PPC,		{ RA, RB } },