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| author | jhb <jhb@FreeBSD.org> | 2012-07-04 22:12:10 +0000 |
|---|---|---|
| committer | jhb <jhb@FreeBSD.org> | 2012-07-04 22:12:10 +0000 |
| commit | 2ce653dc23b0936cbde96f33f880475b25dbdaba (patch) | |
| tree | 8ee8e0ddd2e44400cf824846499bf22e3f69e664 /contrib/binutils/opcodes/i386-opc.tbl | |
| parent | 4f65fa236f2375697aae8a26e4208dd71aadf951 (diff) | |
| download | FreeBSD-src-2ce653dc23b0936cbde96f33f880475b25dbdaba.zip FreeBSD-src-2ce653dc23b0936cbde96f33f880475b25dbdaba.tar.gz | |
Add support for the 'xsave', 'xrstor', 'xsaveopt', 'xgetbv', and 'xsetbv'
instructions. I reimplemented this from scratch based on the Intel
manuals and the existing support for handling the fxsave and fxrstor
instructions. This will let us use these instructions natively with GCC
rather than hardcoding the opcodes in hex.
Reviewed by: kib
MFC after: 1 month
Diffstat (limited to 'contrib/binutils/opcodes/i386-opc.tbl')
| -rw-r--r-- | contrib/binutils/opcodes/i386-opc.tbl | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/contrib/binutils/opcodes/i386-opc.tbl b/contrib/binutils/opcodes/i386-opc.tbl index 5465608..bfe8d41 100644 --- a/contrib/binutils/opcodes/i386-opc.tbl +++ b/contrib/binutils/opcodes/i386-opc.tbl @@ -1487,3 +1487,10 @@ xcryptcfb, 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf xcryptofb, 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } // Alias for xstore-rng. xstore, 0, 0xfa7, 0xc0, Cpu686|CpuPadLock, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|IsString|ImmExt, { 0 } + +// XSAVE/XRSTOR related instructions +xgetbv, 0, 0xf01, 0xd0, CpuXSAVE, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } +xsetbv, 0, 0xf01, 0xd1, CpuXSAVE, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_xSuf|ImmExt, { 0 } +xsave, 1, 0xfae, 0x4, CpuXSAVE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +xsaveopt, 1, 0xfae, 0x6, CpuXSAVE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } +xrstor, 1, 0xfae, 0x5, CpuXSAVE, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf, { BaseIndex|Disp8|Disp16|Disp32|Disp32S } |
