diff options
| author | obrien <obrien@FreeBSD.org> | 2001-05-28 05:21:37 +0000 |
|---|---|---|
| committer | obrien <obrien@FreeBSD.org> | 2001-05-28 05:21:37 +0000 |
| commit | 328e45595b12375b6d16a846069507d25086abdb (patch) | |
| tree | ae2a6f4f4987889b7bd2af7bdf0b86fa580df011 /contrib/binutils/include | |
| parent | 7fbb72605a1c3bcb81f8b6bb6297ffef30f84335 (diff) | |
| download | FreeBSD-src-328e45595b12375b6d16a846069507d25086abdb.zip FreeBSD-src-328e45595b12375b6d16a846069507d25086abdb.tar.gz | |
Import of GNU Binutils version 2.11.0.
Believe it or not, this is heavily stripped down.
Diffstat (limited to 'contrib/binutils/include')
59 files changed, 4146 insertions, 1373 deletions
diff --git a/contrib/binutils/include/ChangeLog b/contrib/binutils/include/ChangeLog index a41d5b1..39085a1 100644 --- a/contrib/binutils/include/ChangeLog +++ b/contrib/binutils/include/ChangeLog @@ -1,6 +1,198 @@ -2000-10-23 Philip Blundell <pb@futuretv.com> +2001-01-11 Peter Targett <peter.targett@arccores.com> - * demangle.h, dyn-string.h: Update from trunk version. + * dis-asm.h (arc_get_disassembler): Correct declaration. + +2001-01-09 Philip Blundell <philb@gnu.org> + + * bin-bugs.h (REPORT_BUGS_TO): Set to `bug-binutils@gnu.org'. + +2000-12-18 Joseph S. Myers <jsm28@cam.ac.uk> + + * COPYING: Update to current + ftp://ftp.gnu.org/pub/gnu/Licenses/COPYING-2.0 (fixes references + to 19yy as example year in copyright notice). + +2000-12-19 Hans-Peter Nilsson <hp@bitrange.com> + + * dis-asm.h (struct disassemble_info): New member "section". + (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialize private_data member. + Initialize section member. + +2000-12-16 Herman A.J. ten Brugge <Haj.Ten.Brugge@net.HCC.nl> + + * safe-ctype.h: Make code work on all targets and not just on + targets where a char is 8 bits. + +2000-12-10 Fred Fish <fnf@be.com> + + * bfdlink.h (struct bfd_link_info): Add new allow_shlib_undefined + member to struct for systems where it is normal to have undefined + symbols in shared libraries at runtime and the runtime linker + takes care of redirecting them. + +2000-12-07 Zack Weinberg <zack@wolery.stanford.edu> + + * safe-ctype.h: New file. + +2000-12-06 Rodney Brown <RodneyBrown@mynd.com> + + * getopt.h obstack.h: Standarize copyright statement. + +2000-12-05 Richard Henderson <rth@redhat.com> + + * demangle.h: Change "new_abi" to "v3" everywhere. + +2000-11-29 Zack Weinberg <zack@wolery.stanford.edu> + + * libiberty.h: Move #includes to top. Prototype xmalloc_failed. + +2000-11-15 Kenneth Block <kenneth.block@compaq.com> + + * demangle.h: Add gnat and java demangle styles. + +2000-11-04 Hans-Peter Nilsson <hp@bitrange.com> + + * hashtab.h (struct htab): Add member return_allocation_failure. + (htab_try_create): New prototype. Mention which functions may + return NULL when this is used. + +2000-11-03 Hans-Peter Nilsson <hp@bitrange.com> + + * hashtab.h: Change void * to PTR where necessary. + +2000-10-11 Mark Mitchell <mark@codesourcery.com> + + * splay-tree.h (splay_tree_predecessor): Declare. + +2000-09-29 Hans-Peter Nilsson <hp@axis.com> + + * dis-asm.h: Declare cris_get_disassembler, not print_insn_cris. + Fix typo in comment. + +2000-09-28 John David Anglin <dave@hiauly1.hia.nrc.ca> + + * alloca-conf.h: New file (copied from libiberty). + +2000-09-05 John David Anglin <dave@hiauly1.hia.nrc.ca> + + * md5.h (md5_uint32): Choose via INT_MAX instead of UINT_MAX. + +2000-09-04 Alex Samuel <samuel@codesourcery.com> + + * dyn-string.h: Adjust formatting. + (dyn_string_insert_char): New macro. New declaration. + +2000-08-28 Jason Merrill <jason@redhat.com> + + * md5.h: New file. + +2000-08-24 Greg McGary <greg@mcgary.org> + + * libiberty.h (ARRAY_SIZE): New macro. + +2000-08-08 Jason Eckhardt <jle@cygnus.com> + + * opcode/i860.h: Small formatting adjustments. + +2000-07-29 Nick Clifton <nickc@cygnus.com> + + * os9k.h: Add copyright notice. + Fix formatting. + +2000-07-22 Jason Eckhardt <jle@cygnus.com> + + * opcode/i860.h (btne, bte, bla): Changed these opcodes + to use sbroff ('r') instead of split16 ('s'). + (J, K, L, M): New operand types for 16-bit aligned fields. + (ld.x, {p}fld.x, fst.x, pst.d): Changed these opcodes to + use I, J, K, L, M instead of just I. + (T, U): New operand types for split 16-bit aligned fields. + (st.x): Changed these opcodes to use S, T, U instead of just S. + (andh, andnoth, orh, xorh): Deleted 3-register forms as they do not + exist on the i860. + (pfgt.sd, pfle.sd): Deleted these as they do not exist on the i860. + (pfeq.ss, pfeq.dd): New opcodes. + (st.s): Fixed incorrect mask bits. + (fmlow): Fixed incorrect mask bits. + (fzchkl, pfzchkl): Fixed incorrect mask bits. + (faddz, pfaddz): Fixed incorrect mask bits. + (form, pform): Fixed incorrect mask bits. + (pfld.l): Fixed incorrect mask bits. + (fst.q): Fixed incorrect mask bits. + (all floating point opcodes): Fixed incorrect mask bits for + handling of dual bit. + + * elf/i860.h: New file. + (elf_i860_reloc_type): Defined ELF32 i860 relocations. + + * dis-asm.h (print_insn_i860): Add prototype. + +2000-07-20 H.J. Lu <hjl@gnu.org> + + * bfdlink.h (bfd_link_info): Add new_dtags. + +2000-07-20 Hans-Peter Nilsson <hp@axis.com> + + * dis-asm.h (print_insn_cris): Declare. + +2000-07-19 H.J. Lu (hjl@gnu.org) + + * bfdlink.h (bfd_link_info): Add flags and flags_1. + +2000-06-05 DJ Delorie <dj@redhat.com> + + * MAINTAINERS: new + +2000-06-30 DJ Delorie <dj@cygnus.com> + + * coff/pe.h: clarify a comment + +2000-06-21 Alex Samuel <samuel@codesourcery.com> + + * dyn-string.h (dyn_string_init, dyn_string_new, + dyn_string_delete, dyn_string_release, dyn_string_resize, + dyn_string_clear, dyn_string_copy, dyn_string_copy_cstr, + dyn_string_prepend, dyn_string_prepend_cstr, dyn_string_insert, + dyn_string_insert_cstr, dyn_string_append, dyn_string_append_cstr, + dyn_string_append_char, dyn_string_substring_dyn_string_eq): + Define as same name with __cxa_ prepended, if IN_LIBGCC2. + (dyn_string_init, dyn_string_copy, dyn_string_copy_cstr, + dyn_string_prepend, dyn_string_prepend_cstr, dyn_string_insert, + dyn_string_insert_cstr, dyn_string_append, dyn_string_append_cstr, + dyn_string_append_char, dyn_string_substring): Change return type + to int. + +2000-06-18 Stephane Carrez <stcarrez@worldnet.fr> + + * dis-asm.h (print_insn_m68hc12): Define. + (print_insn_m68hc11): Likewise. + +2000-06-18 Nick Clifton <nickc@redhat.com> + + * os9k.h: Change values of MODSYNC and CRCCON due to bug report + from Russ Magee <rmagee@home.com>. + +2000-06-07 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * demangle.h (demangling_styles): Remove trailing comma in enum. + + * dyn-string.h (dyn_string_append_char): Change parameter from + char to int. + +2000-06-04 Alex Samuel <samuel@codesourcery.com> + + * dyn-string.h: Move here from gcc/dyn-string.h. Add new functions. + + * demangle.h (DMGL_GNU_NEW_ABI): New macro. + (DMGL_STYLE_MASK): Or in DMGL_GNU_NEW_ABI. + (current_demangling_style): Add gnu_new_abi_demangling. + (GNU_NEW_ABI_DEMANGLING_STYLE_STRING): New macro. + (GNU_NEW_ABI_DEMANGLING): Likewise. + (cplus_demangle_new_abi): New declaration. + +Tue May 30 16:53:34 2000 Andrew Cagney <cagney@b1.cygnus.com> + + * floatformat.h (struct floatformat): Add field name. 2000-05-26 Eli Zaretskii <eliz@is.elta.co.il> @@ -8,6 +200,82 @@ (HAVE_DOS_BASED_FILE_SYSTEM, IS_DIR_SEPARATOR) (IS_ABSOLUTE_PATH, FILENAME_CMP): New macros. +2000-05-23 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * getopt.h (getopt): Also check HAVE_DECL_* when prototyping. + + * libiberty.h (basename): Likewise. + +2000-05-17 S. Bharadwaj Yadavalli <sby@scrugs.lkg.dec.com> + Rick Gorton <gorton@scrugs.lkg.dec.com> + + * bfdlink.h (struct bfd_link_info): Add emitrelocations flag. + +2000-05-08 Alan Modra <alan@linuxcare.com.au> + + * dis-asm.h (print_insn_tic54x): Declare. + +2000-05-06 Zack Weinberg <zack@wolery.cumb.org> + + * ansidecl.h: #define __extension__ to nothing if + GCC_VERSION < 2008. + +Fri May 5 16:51:03 2000 Clinton Popetz <cpopetz@cygnus.com> + + * coff/rs6k64.h (U802TOC64MAGIC): Change to U803XTOCMAGIC. + +2000-05-04 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * demangle.h (demangler_engine): Constify. + +Thu May 4 17:15:26 2000 Philippe De Muyter <phdm@macqel.be> + + * sort.h (sys/types.h): File included unconditionnaly. + (stddef.h): File include only #ifdef __STDC__. + +2000-05-03 Zack Weinberg <zack@wolery.cumb.org> + + * symcat.h: Remove #endif label. + +2000-04-28 Kenneth Block <block@zk3.dec.com> + Jason Merrill <jason@casey.cygnus.com> + + * demangle.h (libiberty_demanglers): new table for different styles. + (cplus_demangle_set_style): New function for setting style. + (cplus_demangle_name_to_style): New function to translate name. + +Mon Apr 24 15:20:51 2000 Clinton Popetz <cpopetz@cygnus.com> + + * include/coff/rs6k64.h: New file. + +2000-04-24 Mark Mitchell <mark@codesourcery.com> + + * hashtab.h (hash_pointer): Declare. + (eq_pointer): Likewise. + +2000-04-23 Mark Mitchell <mark@codesourcery.com> + + * sort.h: New file. + +Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com> + David Mosberger <davidm@hpl.hp.com> + + * dis-asm.h (print_insn_ia64): Declare. + +Tue Apr 18 16:22:30 2000 Richard Kenner <kenner@vlsi1.ultra.nyu.edu> + + * hashtab.h (enum insert_option): New type. + (htab_find_slot, htab_find_slot_with_hash): Use it. + +2000-04-17 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * symcat.h: Honor autoconf macro HAVE_STRINGIZE. Add + comments/caveats with regard to traditional C behavior. + +2000-04-05 Richard Henderson <rth@cygnus.com> + + * splay-tree.h (splay_tree_remove): Declare. + 2000-04-04 Alan Modra <alan@linuxcare.com.au> * bin-bugs.h (REPORT_BUGS_TO): Remove translated part. @@ -16,6 +284,12 @@ * bin-bugs.h: New file. +2000-03-30 Mark Mitchell <mark@codesourcery.com> + + * hashtab.h (hashval_t): New type. + (htab_find_with_hash): Use it as an argument. + (htab_find_slot_with_hash): Likewise. + 2000-03-27 Denis Chertykov <denisc@overta.ru> * dis-asm.h (print_insn_avr): Declare. @@ -258,7 +532,7 @@ Mon Feb 1 21:05:46 1999 Catherine Moore <clm@cygnus.com> * dis-asm.h (print_insn_i386_att): Declare. (print_insn_i386_intel): Declare. -998-12-30 Michael Meissner <meissner@cygnus.com> +1998-12-30 Michael Meissner <meissner@cygnus.com> * dis-asm.h (INIT_DISASSEMBLE_INFO_NO_ARCH): Cast STREAM and FPRINTF_FUNC to avoid compiler warnings. @@ -288,8 +562,7 @@ Tue Dec 8 00:30:31 1998 Elena Zannoni <ezannoni@kwikemart.cygnus.com> (demangling_styles): add new edg_demangling style (EDG_DEMANGLING_STYLE_STRING): new macro (EDG_DEMANGLING): new macro - - * demangle.h (DMGL_HP): new macro, for HP/aCC compiler. + (DMGL_HP): new macro, for HP/aCC compiler. (DMGL_STYLE_MASK): modify to include new HP's style. (demangling_styles): add new hp_demangling value. (HP_DEMANGLING_STYLE_STRING): new macro. diff --git a/contrib/binutils/include/MAINTAINERS b/contrib/binutils/include/MAINTAINERS new file mode 100644 index 0000000..d59a3bd --- /dev/null +++ b/contrib/binutils/include/MAINTAINERS @@ -0,0 +1 @@ +See ../binutils/MAINTAINERS diff --git a/contrib/binutils/include/alloca-conf.h b/contrib/binutils/include/alloca-conf.h new file mode 100644 index 0000000..9c3eea3 --- /dev/null +++ b/contrib/binutils/include/alloca-conf.h @@ -0,0 +1,24 @@ +#include "config.h" + +#if defined(__GNUC__) && !defined(C_ALLOCA) +# ifndef alloca +# define alloca __builtin_alloca +# endif +#else /* ! defined (__GNUC__) */ +# ifdef _AIX + #pragma alloca +# else +# if defined(HAVE_ALLOCA_H) && !defined(C_ALLOCA) +# include <alloca.h> +# else /* ! defined (HAVE_ALLOCA_H) */ +# ifdef __STDC__ +extern PTR alloca (size_t); +# else /* ! defined (__STDC__) */ +extern PTR alloca (); +# endif /* ! defined (__STDC__) */ +# endif /* ! defined (HAVE_ALLOCA_H) */ +# ifdef _WIN32 +# include <malloc.h> +# endif +# endif /* ! defined (_AIX) */ +#endif /* ! defined (__GNUC__) */ diff --git a/contrib/binutils/include/ansidecl.h b/contrib/binutils/include/ansidecl.h index 1030867..e7852c6 100644 --- a/contrib/binutils/include/ansidecl.h +++ b/contrib/binutils/include/ansidecl.h @@ -160,6 +160,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #endif /* ANSI C. */ + /* Using MACRO(x,y) in cpp #if conditionals does not work with some older preprocessors. Thus we can't define something like this: @@ -221,4 +222,11 @@ So instead we use the macro below and test it against specific values. */ #define ATTRIBUTE_PRINTF_5 ATTRIBUTE_PRINTF(5, 6) #endif /* ATTRIBUTE_PRINTF */ +/* We use __extension__ in some places to suppress -pedantic warnings + about GCC extensions. This feature didn't work properly before + gcc 2.8. */ +#if GCC_VERSION < 2008 +#define __extension__ +#endif + #endif /* ansidecl.h */ diff --git a/contrib/binutils/include/aout/ChangeLog b/contrib/binutils/include/aout/ChangeLog index 63f17ec..1645a5a 100644 --- a/contrib/binutils/include/aout/ChangeLog +++ b/contrib/binutils/include/aout/ChangeLog @@ -1,3 +1,12 @@ +Mon Apr 3 13:29:08 2000 Hans-Peter Nilsson <hp@axis.com> + + * aout64.h (RELOC_EXT_BITS_EXTERN_BIG): Wrap definition in #ifndef. + (RELOC_EXT_BITS_EXTERN_LITTLE): Ditto. + (RELOC_EXT_BITS_TYPE_BIG): Ditto. + (RELOC_EXT_BITS_TYPE_SH_BIG): Ditto. + (RELOC_EXT_BITS_TYPE_LITTLE): Ditto. + (RELOC_EXT_BITS_TYPE_SH_LITTLE): Ditto. + 1999-07-12 Ian Lance Taylor <ian@zembu.com> * aout64.h (N_SHARED_LIB): Define as 0 if TEXT_START_ADDR is diff --git a/contrib/binutils/include/aout/aout64.h b/contrib/binutils/include/aout/aout64.h index bf743c4..bec8440 100644 --- a/contrib/binutils/include/aout/aout64.h +++ b/contrib/binutils/include/aout/aout64.h @@ -388,13 +388,29 @@ struct reloc_ext_external { bfd_byte r_addend[BYTES_IN_WORD]; /* datum addend */ }; +#ifndef RELOC_EXT_BITS_EXTERN_BIG #define RELOC_EXT_BITS_EXTERN_BIG ((unsigned int) 0x80) +#endif + +#ifndef RELOC_EXT_BITS_EXTERN_LITTLE #define RELOC_EXT_BITS_EXTERN_LITTLE ((unsigned int) 0x01) +#endif +#ifndef RELOC_EXT_BITS_TYPE_BIG #define RELOC_EXT_BITS_TYPE_BIG ((unsigned int) 0x1F) +#endif + +#ifndef RELOC_EXT_BITS_TYPE_SH_BIG #define RELOC_EXT_BITS_TYPE_SH_BIG 0 +#endif + +#ifndef RELOC_EXT_BITS_TYPE_LITTLE #define RELOC_EXT_BITS_TYPE_LITTLE ((unsigned int) 0xF8) +#endif + +#ifndef RELOC_EXT_BITS_TYPE_SH_LITTLE #define RELOC_EXT_BITS_TYPE_SH_LITTLE 3 +#endif /* Bytes per relocation entry */ #define RELOC_EXT_SIZE (BYTES_IN_WORD + 3 + 1 + BYTES_IN_WORD) diff --git a/contrib/binutils/include/bfdlink.h b/contrib/binutils/include/bfdlink.h index bb827a3..ae96323 100644 --- a/contrib/binutils/include/bfdlink.h +++ b/contrib/binutils/include/bfdlink.h @@ -179,6 +179,8 @@ struct bfd_link_info const struct bfd_link_callbacks *callbacks; /* true if BFD should generate a relocateable object file. */ boolean relocateable; + /* true if BFD should generate relocation information in the final executable. */ + boolean emitrelocations; /* true if BFD should generate a "task linked" object file, similar to relocatable but also with globals converted to statics. */ boolean task_link; @@ -199,6 +201,19 @@ struct bfd_link_info /* true if BFD should generate errors for undefined symbols even if generating a shared object. */ boolean no_undefined; + /* true if BFD should allow undefined symbols in shared objects even + when no_undefined is set to disallow undefined symbols. The net + result will be that undefined symbols in regular objects will + still trigger an error, but undefined symbols in shared objects + will be ignored. The implementation of no_undefined makes the + assumption that the runtime linker will choke on undefined + symbols. However there is at least one system (BeOS) where + undefined symbols in shared libraries is normal since the kernel + patches them at load time to select which function is most + appropriate for the current architecture. I.E. dynamically + select an appropriate memset function. Apparently it is also + normal for HPPA shared libraries to have undefined symbols. */ + boolean allow_shlib_undefined; /* Which symbols to strip. */ enum bfd_link_strip strip; /* Which local symbols to discard. */ @@ -244,6 +259,15 @@ struct bfd_link_info /* The function to call when the executable or shared object is unloaded. */ const char *fini_function; + + /* true if the new ELF dynamic tags are enabled. */ + boolean new_dtags; + + /* May be used to set DT_FLAGS for ELF. */ + bfd_vma flags; + + /* May be used to set DT_FLAGS_1 for ELF. */ + bfd_vma flags_1; }; /* This structures holds a set of callback functions. These are diff --git a/contrib/binutils/include/bin-bugs.h b/contrib/binutils/include/bin-bugs.h index cb14a66..3c97715 100644 --- a/contrib/binutils/include/bin-bugs.h +++ b/contrib/binutils/include/bin-bugs.h @@ -1,3 +1,3 @@ #ifndef REPORT_BUGS_TO -#define REPORT_BUGS_TO "bug-gnu-utils@gnu.org" +#define REPORT_BUGS_TO "bug-binutils@gnu.org" #endif diff --git a/contrib/binutils/include/coff/ChangeLog b/contrib/binutils/include/coff/ChangeLog index 76b52c0..eb97871 100644 --- a/contrib/binutils/include/coff/ChangeLog +++ b/contrib/binutils/include/coff/ChangeLog @@ -1,3 +1,64 @@ +2001-02-17 Philip Blundell <philb@gnu.org> + + From 2001-01-23 H.J. Lu <hjl@gnu.org> + * pe.h (struct external_PEI_DOS_hdr): New. + (struct external_PEI_IMAGE_hdr): New. + +2000-12-11 Alan Modra <alan@linuxcare.com.au> + + * ti.h (OCTETS_PER_BYTE_POWER): Change #warning to #error. + +2000-12-08 Alan Modra <alan@linuxcare.com.au> + + * ti.h (OCTETS_PER_BYTE_POWER): Change #warn to #warning. + +2000-06-30 DJ Delorie <dj@cygnus.com> + + * pe.h: Clarify a comment. + +2000-04-17 Timothy Wall <twall@cygnus.com> + + * ti.h: Load page cleanup. + * intental.h: Add load page field. + +Mon Apr 17 16:44:01 2000 David Mosberger <davidm@hpl.hp.com> + + * pe.h (PEP64AOUTHDR): New header for PE+. + (PEP64AOUTSZ): New macro. + (IMAGE_SUBSYSTEM_UNKNOWN): New macro. + (IMAGE_SUBSYSTEM_NATIVE): Ditto. + (IMAGE_SUBSYSTEM_WINDOWS_GUI): Ditto. + (IMAGE_SUBSYSTEM_WINDOWS_CUI): Ditto. + (IMAGE_SUBSYSTEM_POSIX_CUI): Ditto. + (IMAGE_SUBSYSTEM_WINDOWS_CE_GUI): Ditto. + (IMAGE_SUBSYSTEM_EFI_APPLICATION): Ditto. + (IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER): Ditto. + (IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER): Ditto. + * internal.h (PE_DEF_FILE_ALIGNMENT): Define only if not defined + already. + * ia64.h: New file. + +2000-04-13 Alan Modra <alan@linuxcare.com.au> + + * ti.h (ADDR_MASK): Don't use ul suffix on constants. + (PG_MASK): Ditto. + +2000-04-11 Timothy Wall <twall@cygnus.com> + + * ti.h: Remove load page references until load pages are + reimplemented. + * tic54x.h: Ditto. + +2000-04-07 Timothy Wall <twall@cygnus.com> + + * internal.h: Fix some comments related to TI COFF (instead of tic80). + * ti.h: New. + * tic54x.h: New. + +Wed Apr 5 22:08:41 2000 J"orn Rennecke <amylaar@cygnus.co.uk> + + * sh.h (R_SH_LOOP_START, R_SH_LOOP_END): Define. + 2000-03-15 Kazu Hirata <kazu@hxi.com> * internal.h: Fix a typo in the comment for R_MOVL2. diff --git a/contrib/binutils/include/coff/internal.h b/contrib/binutils/include/coff/internal.h index e89b528..c6f2760 100644 --- a/contrib/binutils/include/coff/internal.h +++ b/contrib/binutils/include/coff/internal.h @@ -53,7 +53,7 @@ struct internal_filehdr long f_nsyms; /* number of symtab entries */ unsigned short f_opthdr; /* sizeof(optional hdr) */ unsigned short f_flags; /* flags */ - unsigned short f_target_id; /* (TIc80 specific) */ + unsigned short f_target_id; /* (TI COFF specific) */ }; @@ -100,7 +100,9 @@ typedef struct _IMAGE_DATA_DIRECTORY /* Extra stuff in a PE aouthdr */ #define PE_DEF_SECTION_ALIGNMENT 0x1000 -#define PE_DEF_FILE_ALIGNMENT 0x200 +#ifndef PE_DEF_FILE_ALIGNMENT +# define PE_DEF_FILE_ALIGNMENT 0x200 +#endif struct internal_extra_pe_aouthdr { @@ -222,7 +224,7 @@ struct internal_aouthdr #define C_WEAKEXT 127 /* weak symbol -- GNU extension */ -/* New storage classes for TIc80 */ +/* New storage classes for TI COFF */ #define C_UEXT 19 /* Tentative external definition */ #define C_STATLAB 20 /* Static load time label */ #define C_EXTLAB 21 /* External load time label */ @@ -301,6 +303,7 @@ struct internal_scnhdr unsigned long s_nlnno; /* number of line number entries*/ long s_flags; /* flags */ long s_align; /* used on I960 */ + unsigned char s_page; /* TI COFF load page */ }; /* diff --git a/contrib/binutils/include/coff/pe.h b/contrib/binutils/include/coff/pe.h index 6932ee8..0cf46d0 100644 --- a/contrib/binutils/include/coff/pe.h +++ b/contrib/binutils/include/coff/pe.h @@ -1,5 +1,22 @@ -/* PE COFF header information */ +/* pe.h - PE COFF header information + Copyright (C) 2000 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef _PE_H #define _PE_H @@ -89,50 +106,101 @@ #define IMAGE_FILE_MACHINE_SH4 0x1a6 #define IMAGE_FILE_MACHINE_THUMB 0x1c2 -/* Magic values that are true for all dos/nt implementations */ +#define IMAGE_SUBSYSTEM_UNKNOWN 0 +#define IMAGE_SUBSYSTEM_NATIVE 1 +#define IMAGE_SUBSYSTEM_WINDOWS_GUI 2 +#define IMAGE_SUBSYSTEM_WINDOWS_CUI 3 +#define IMAGE_SUBSYSTEM_POSIX_CUI 7 +#define IMAGE_SUBSYSTEM_WINDOWS_CE_GUI 9 +#define IMAGE_SUBSYSTEM_EFI_APPLICATION 10 +#define IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER 11 +#define IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER 12 + +/* Magic values that are true for all dos/nt implementations. */ #define DOSMAGIC 0x5a4d #define NT_SIGNATURE 0x00004550 - /* NT allows long filenames, we want to accommodate this. This may break - some of the bfd functions */ +/* NT allows long filenames, we want to accommodate this. + This may break some of the bfd functions. */ #undef FILNMLEN -#define FILNMLEN 18 /* # characters in a file name */ +#define FILNMLEN 18 /* # characters in a file name. */ -struct external_PEI_filehdr +struct external_PEI_DOS_hdr { - /* DOS header fields */ - char e_magic[2]; /* Magic number, 0x5a4d */ - char e_cblp[2]; /* Bytes on last page of file, 0x90 */ - char e_cp[2]; /* Pages in file, 0x3 */ - char e_crlc[2]; /* Relocations, 0x0 */ - char e_cparhdr[2]; /* Size of header in paragraphs, 0x4 */ - char e_minalloc[2]; /* Minimum extra paragraphs needed, 0x0 */ - char e_maxalloc[2]; /* Maximum extra paragraphs needed, 0xFFFF */ - char e_ss[2]; /* Initial (relative) SS value, 0x0 */ - char e_sp[2]; /* Initial SP value, 0xb8 */ - char e_csum[2]; /* Checksum, 0x0 */ - char e_ip[2]; /* Initial IP value, 0x0 */ - char e_cs[2]; /* Initial (relative) CS value, 0x0 */ - char e_lfarlc[2]; /* File address of relocation table, 0x40 */ - char e_ovno[2]; /* Overlay number, 0x0 */ - char e_res[4][2]; /* Reserved words, all 0x0 */ - char e_oemid[2]; /* OEM identifier (for e_oeminfo), 0x0 */ - char e_oeminfo[2]; /* OEM information; e_oemid specific, 0x0 */ - char e_res2[10][2]; /* Reserved words, all 0x0 */ - char e_lfanew[4]; /* File address of new exe header, 0x80 */ - char dos_message[16][4]; /* other stuff, always follow DOS header */ - char nt_signature[4]; /* required NT signature, 0x4550 */ - - /* From standard header */ - - char f_magic[2]; /* magic number */ - char f_nscns[2]; /* number of sections */ - char f_timdat[4]; /* time & date stamp */ - char f_symptr[4]; /* file pointer to symtab */ - char f_nsyms[4]; /* number of symtab entries */ - char f_opthdr[2]; /* sizeof(optional hdr) */ - char f_flags[2]; /* flags */ + /* DOS header fields - always at offset zero in the EXE file. */ + char e_magic[2]; /* Magic number, 0x5a4d. */ + char e_cblp[2]; /* Bytes on last page of file, 0x90. */ + char e_cp[2]; /* Pages in file, 0x3. */ + char e_crlc[2]; /* Relocations, 0x0. */ + char e_cparhdr[2]; /* Size of header in paragraphs, 0x4. */ + char e_minalloc[2]; /* Minimum extra paragraphs needed, 0x0. */ + char e_maxalloc[2]; /* Maximum extra paragraphs needed, 0xFFFF. */ + char e_ss[2]; /* Initial (relative) SS value, 0x0. */ + char e_sp[2]; /* Initial SP value, 0xb8. */ + char e_csum[2]; /* Checksum, 0x0. */ + char e_ip[2]; /* Initial IP value, 0x0. */ + char e_cs[2]; /* Initial (relative) CS value, 0x0. */ + char e_lfarlc[2]; /* File address of relocation table, 0x40. */ + char e_ovno[2]; /* Overlay number, 0x0. */ + char e_res[4][2]; /* Reserved words, all 0x0. */ + char e_oemid[2]; /* OEM identifier (for e_oeminfo), 0x0. */ + char e_oeminfo[2]; /* OEM information; e_oemid specific, 0x0. */ + char e_res2[10][2]; /* Reserved words, all 0x0. */ + char e_lfanew[4]; /* File address of new exe header, usually 0x80. */ + char dos_message[16][4]; /* Other stuff, always follow DOS header. */ +}; + +struct external_PEI_IMAGE_hdr +{ + char nt_signature[4]; /* required NT signature, 0x4550. */ + + /* From standard header. */ + char f_magic[2]; /* Magic number. */ + char f_nscns[2]; /* Number of sections. */ + char f_timdat[4]; /* Time & date stamp. */ + char f_symptr[4]; /* File pointer to symtab. */ + char f_nsyms[4]; /* Number of symtab entries. */ + char f_opthdr[2]; /* Sizeof(optional hdr). */ + char f_flags[2]; /* Flags. */ +}; +struct external_PEI_filehdr +{ + /* DOS header fields - always at offset zero in the EXE file. */ + char e_magic[2]; /* Magic number, 0x5a4d. */ + char e_cblp[2]; /* Bytes on last page of file, 0x90. */ + char e_cp[2]; /* Pages in file, 0x3. */ + char e_crlc[2]; /* Relocations, 0x0. */ + char e_cparhdr[2]; /* Size of header in paragraphs, 0x4. */ + char e_minalloc[2]; /* Minimum extra paragraphs needed, 0x0. */ + char e_maxalloc[2]; /* Maximum extra paragraphs needed, 0xFFFF. */ + char e_ss[2]; /* Initial (relative) SS value, 0x0. */ + char e_sp[2]; /* Initial SP value, 0xb8. */ + char e_csum[2]; /* Checksum, 0x0. */ + char e_ip[2]; /* Initial IP value, 0x0. */ + char e_cs[2]; /* Initial (relative) CS value, 0x0. */ + char e_lfarlc[2]; /* File address of relocation table, 0x40. */ + char e_ovno[2]; /* Overlay number, 0x0. */ + char e_res[4][2]; /* Reserved words, all 0x0. */ + char e_oemid[2]; /* OEM identifier (for e_oeminfo), 0x0. */ + char e_oeminfo[2]; /* OEM information; e_oemid specific, 0x0. */ + char e_res2[10][2]; /* Reserved words, all 0x0. */ + char e_lfanew[4]; /* File address of new exe header, usually 0x80. */ + char dos_message[16][4]; /* Other stuff, always follow DOS header. */ + + /* Note: additional bytes may be inserted before the signature. Use + the e_lfanew field to find the actual location of the NT signature. */ + + char nt_signature[4]; /* required NT signature, 0x4550. */ + + /* From standard header. */ + char f_magic[2]; /* Magic number. */ + char f_nscns[2]; /* Number of sections. */ + char f_timdat[4]; /* Time & date stamp. */ + char f_symptr[4]; /* File pointer to symtab. */ + char f_nsyms[4]; /* Number of symtab entries. */ + char f_opthdr[2]; /* Sizeof(optional hdr). */ + char f_flags[2]; /* Flags. */ }; #ifdef COFF_IMAGE_WITH_PE @@ -146,11 +214,13 @@ struct external_PEI_filehdr #endif /* COFF_IMAGE_WITH_PE */ +/* 32-bit PE a.out header: */ + typedef struct { AOUTHDR standard; - /* NT extra fields; see internal.h for descriptions */ + /* NT extra fields; see internal.h for descriptions. */ char ImageBase[4]; char SectionAlignment[4]; char FileAlignment[4]; @@ -172,17 +242,48 @@ typedef struct char SizeOfHeapCommit[4]; char LoaderFlags[4]; char NumberOfRvaAndSizes[4]; - /* IMAGE_DATA_DIRECTORY DataDirectory[IMAGE_NUMBEROF_DIRECTORY_ENTRIES]; */ - char DataDirectory[16][2][4]; /* 16 entries, 2 elements/entry, 4 chars */ - + /* IMAGE_DATA_DIRECTORY DataDirectory[IMAGE_NUMBEROF_DIRECTORY_ENTRIES]; */ + char DataDirectory[16][2][4]; /* 16 entries, 2 elements/entry, 4 chars. */ } PEAOUTHDR; - - #undef AOUTSZ #define AOUTSZ (AOUTHDRSZ + 196) +/* Like PEAOUTHDR, except that the "standard" member has no BaseOfData + (aka data_start) member and that some of the members are 8 instead + of just 4 bytes long. */ +typedef struct +{ + AOUTHDR standard; + + /* NT extra fields; see internal.h for descriptions. */ + char ImageBase[8]; + char SectionAlignment[4]; + char FileAlignment[4]; + char MajorOperatingSystemVersion[2]; + char MinorOperatingSystemVersion[2]; + char MajorImageVersion[2]; + char MinorImageVersion[2]; + char MajorSubsystemVersion[2]; + char MinorSubsystemVersion[2]; + char Reserved1[4]; + char SizeOfImage[4]; + char SizeOfHeaders[4]; + char CheckSum[4]; + char Subsystem[2]; + char DllCharacteristics[2]; + char SizeOfStackReserve[8]; + char SizeOfStackCommit[8]; + char SizeOfHeapReserve[8]; + char SizeOfHeapCommit[8]; + char LoaderFlags[4]; + char NumberOfRvaAndSizes[4]; + /* IMAGE_DATA_DIRECTORY DataDirectory[IMAGE_NUMBEROF_DIRECTORY_ENTRIES]; */ + char DataDirectory[16][2][4]; /* 16 entries, 2 elements/entry, 4 chars. */ +} PEP64AOUTHDR; +#define PEP64AOUTSZ 240 + #undef E_FILNMLEN -#define E_FILNMLEN 18 /* # characters in a file name */ +#define E_FILNMLEN 18 /* # characters in a file name. */ /* Import Tyoes fot ILF format object files.. */ #define IMPORT_CODE 0 diff --git a/contrib/binutils/include/coff/ti.h b/contrib/binutils/include/coff/ti.h new file mode 100644 index 0000000..445707c --- /dev/null +++ b/contrib/binutils/include/coff/ti.h @@ -0,0 +1,434 @@ +/* COFF information for TI COFF support. Definitions in this file should be + customized in a target-specific file, and then this file included (see + tic54x.h for an example). */ +#ifndef COFF_TI_H +#define COFF_TI_H + +/********************** FILE HEADER **********************/ + +struct external_filehdr { + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ + char f_target_id[2]; /* magic no. (TI COFF-specific) */ +}; + +/* COFF0 has magic number in f_magic, and omits f_target_id from the file + header; for later versions, f_magic is 0xC1 for COFF1 and 0xC2 for COFF2 + and the target-specific magic number is found in f_target_id */ + +#define TICOFF0MAGIC TI_TARGET_ID +#define TICOFF1MAGIC 0x00C1 +#define TICOFF2MAGIC 0x00C2 +#define TICOFF_AOUT_MAGIC 0x0108 /* magic number in optional header */ +#define TICOFF 1 /* customize coffcode.h */ + +/* The target_id field changes depending on the particular CPU target */ +/* for COFF0, the target id appeared in f_magic, where COFFX magic is now */ +#ifndef TI_TARGET_ID +#error "TI_TARGET_ID needs to be defined for your CPU" +#endif + +/* Which bfd_arch to use... */ +#ifndef TICOFF_TARGET_ARCH +#error "TICOFF_TARGET_ARCH needs to be defined for your CPU" +#endif + +/* Default to COFF2 for file output */ +#ifndef TICOFF_DEFAULT_MAGIC +#define TICOFF_DEFAULT_MAGIC TICOFF2MAGIC +#endif + +/* This value is made available in the rare case where a bfd is unavailable */ +#ifndef OCTETS_PER_BYTE_POWER +#error "OCTETS_PER_BYTE_POWER not defined for this CPU" +#else +#define OCTETS_PER_BYTE (1<<OCTETS_PER_BYTE_POWER) +#endif + +/* default alignment is on a byte (not octet!) boundary */ +#ifndef COFF_DEFAULT_SECTION_ALIGNMENT_POWER +#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 0 +#endif + +/* TI COFF encodes the section alignment in the section header flags */ +#define COFF_ALIGN_IN_SECTION_HEADER 1 +#define COFF_ALIGN_IN_S_FLAGS 1 +/* requires a power-of-two argument */ +#define COFF_ENCODE_ALIGNMENT(S,X) ((S).s_flags |= (((unsigned)(X)&0xF)<<8)) +/* result is a power of two */ +#define COFF_DECODE_ALIGNMENT(X) (((X)>>8)&0xF) + +#define COFF0_P(ABFD) (bfd_coff_filhsz(ABFD) == FILHSZ_V0) +#define COFF2_P(ABFD) (bfd_coff_scnhsz(ABFD) != SCNHSZ_V01) + +#define COFF0_BADMAG(x) ((x).f_magic != TICOFF0MAGIC) +#define COFF1_BADMAG(x) ((x).f_magic != TICOFF1MAGIC || (x).f_target_id != TI_TARGET_ID) +#define COFF2_BADMAG(x) ((x).f_magic != TICOFF2MAGIC || (x).f_target_id != TI_TARGET_ID) + +/* we need to read/write an extra field in the coff file header */ +#ifndef COFF_ADJUST_FILEHDR_IN_POST +#define COFF_ADJUST_FILEHDR_IN_POST(abfd,src,dst) \ +do { ((struct internal_filehdr *)(dst))->f_target_id = \ +bfd_h_get_16(abfd, (bfd_byte *)(((FILHDR *)(src))->f_target_id)); \ +} while(0) +#endif + +#ifndef COFF_ADJUST_FILEHDR_OUT_POST +#define COFF_ADJUST_FILEHDR_OUT_POST(abfd,src,dst) \ +do { bfd_h_put_16(abfd, ((struct internal_filehdr *)(src))->f_target_id, \ + (bfd_byte *)(((FILHDR *)(dst))->f_target_id)); \ +} while(0) +#endif + +#define FILHDR struct external_filehdr +#define FILHSZ 22 +#define FILHSZ_V0 20 /* COFF0 omits target_id field */ + +/* File header flags */ +#define F_RELFLG (0x0001) +#define F_EXEC (0x0002) +#define F_LNNO (0x0004) +/* F_LSYMS needs to be redefined in your source file */ +#define F_LSYMS_TICOFF (0x0010) /* normal COFF is 0x8 */ + +#define F_10 0x00 /* file built for TMS320C1x devices */ +#define F_20 0x10 /* file built for TMS320C2x devices */ +#define F_25 0x20 /* file built for TMS320C2x/C5x devices */ +#define F_LENDIAN 0x0100 /* 16 bits/word, LSB first */ +#define F_SYMMERGE 0x1000 /* duplicate symbols were removed */ + +/********************** OPTIONAL HEADER **********************/ + + +typedef struct +{ + char magic[2]; /* type of file (0x108) */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry*/ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ +} +AOUTHDR; + + +#define AOUTHDRSZ 28 +#define AOUTSZ 28 + + +/********************** SECTION HEADER **********************/ +/* COFF0, COFF1 */ +struct external_scnhdr_v01 { + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size (in WORDS) */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries*/ + char s_flags[2]; /* flags */ + char s_reserved[1]; /* reserved */ + char s_page[1]; /* section page number (LOAD) */ +}; + +/* COFF2 */ +struct external_scnhdr { + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size (in WORDS) */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[4]; /* number of relocation entries */ + char s_nlnno[4]; /* number of line number entries*/ + char s_flags[4]; /* flags */ + char s_reserved[2]; /* reserved */ + char s_page[2]; /* section page number (LOAD) */ +}; + +/* + * Special section flags + */ + +/* TI COFF defines these flags; + STYP_CLINK: the section should be excluded from the final + linker output if there are no references found to any symbol in the section + STYP_BLOCK: the section should be blocked, i.e. if the section would cross + a page boundary, it is started at a page boundary instead. + TI COFF puts the section alignment power of two in the section flags + e.g. 2**N is alignment, flags |= (N & 0xF) << 8 +*/ +#define STYP_CLINK (0x4000) +#define STYP_BLOCK (0x1000) +#define STYP_ALIGN (0x0F00) /* TI COFF stores section alignment here */ + +#define SCNHDR_V01 struct external_scnhdr_v01 +#define SCNHDR struct external_scnhdr +#define SCNHSZ_V01 40 /* for v0 and v1 */ +#define SCNHSZ 48 + +/* COFF2 changes the offsets and sizes of these fields + Assume we're dealing with the COFF2 scnhdr structure, and adjust + accordingly + */ +#define GET_SCNHDR_NRELOC(ABFD,PTR) \ +(COFF2_P(ABFD) ? bfd_h_get_32 (ABFD,PTR) : bfd_h_get_16 (ABFD, PTR)) +#define PUT_SCNHDR_NRELOC(ABFD,VAL,PTR) \ +(COFF2_P(ABFD) ? bfd_h_put_32 (ABFD,VAL,PTR) : bfd_h_put_16 (ABFD,VAL,PTR)) +#define GET_SCNHDR_NLNNO(ABFD,PTR) \ +(COFF2_P(ABFD) ? bfd_h_get_32 (ABFD,PTR) : bfd_h_get_16 (ABFD, (PTR)-2)) +#define PUT_SCNHDR_NLNNO(ABFD,VAL,PTR) \ +(COFF2_P(ABFD) ? bfd_h_put_32 (ABFD,VAL,PTR) : bfd_h_put_16 (ABFD,VAL,(PTR)-2)) +#define GET_SCNHDR_FLAGS(ABFD,PTR) \ +(COFF2_P(ABFD) ? bfd_h_get_32 (ABFD,PTR) : bfd_h_get_16 (ABFD, (PTR)-4)) +#define PUT_SCNHDR_FLAGS(ABFD,VAL,PTR) \ +(COFF2_P(ABFD) ? bfd_h_put_32 (ABFD,VAL,PTR) : bfd_h_put_16 (ABFD,VAL,(PTR)-4)) +#define GET_SCNHDR_PAGE(ABFD,PTR) \ +(COFF2_P(ABFD) ? bfd_h_get_16 (ABFD,PTR) : bfd_h_get_8 (ABFD, (PTR)-7)) +/* on output, make sure that the "reserved" field is zero */ +#define PUT_SCNHDR_PAGE(ABFD,VAL,PTR) \ +(COFF2_P(ABFD) ? bfd_h_put_16 (ABFD,VAL,PTR) : \ +bfd_h_put_8 (ABFD,VAL,(PTR)-7), bfd_h_put_8 (ABFD, 0, (PTR)-8)) + +/* TI COFF stores section size as number of bytes (address units, not octets), + so adjust to be number of octets, which is what BFD expects */ +#define GET_SCNHDR_SIZE(ABFD,SZP) \ +(bfd_h_get_32(ABFD,SZP)*bfd_octets_per_byte(ABFD)) +#define PUT_SCNHDR_SIZE(ABFD,SZ,SZP) \ +bfd_h_put_32(ABFD,(SZ)/bfd_octets_per_byte(ABFD),SZP) + +#define COFF_ADJUST_SCNHDR_IN_POST(ABFD,EXT,INT) \ +do { ((struct internal_scnhdr *)(INT))->s_page = \ +GET_SCNHDR_PAGE(ABFD,(bfd_byte *)((SCNHDR *)(EXT))->s_page); \ +} while(0) + +/* The line number and reloc overflow checking in coff_swap_scnhdr_out in + coffswap.h doesn't use PUT_X for s_nlnno and s_nreloc. + Due to different sized v0/v1/v2 section headers, we have to re-write these + fields. + */ +#define COFF_ADJUST_SCNHDR_OUT_POST(ABFD,INT,EXT) \ +do { \ +PUT_SCNHDR_NLNNO(ABFD,((struct internal_scnhdr *)(INT))->s_nlnno,\ + (bfd_byte *)((SCNHDR *)(EXT))->s_nlnno); \ +PUT_SCNHDR_NRELOC(ABFD,((struct internal_scnhdr *)(INT))->s_nreloc,\ + (bfd_byte *)((SCNHDR *)(EXT))->s_nreloc); \ +PUT_SCNHDR_FLAGS(ABFD,((struct internal_scnhdr *)(INT))->s_flags, \ + (bfd_byte *)((SCNHDR *)(EXT))->s_flags); \ +PUT_SCNHDR_PAGE(ABFD,((struct internal_scnhdr *)(INT))->s_page, \ + (bfd_byte *)((SCNHDR *)(EXT))->s_page); \ +} while(0) + +/* Page macros + + The first GDB port requires flags in its remote memory access commands to + distinguish between data/prog space. Hopefully we can make this go away + eventually. Stuff the page in the upper bits of a 32-bit address, since + the c5x family only uses 16 or 23 bits. + + c2x, c5x and most c54x devices have 16-bit addresses, but the c548 has + 23-bit program addresses. Make sure the page flags don't interfere. + These flags are used by GDB to identify the destination page for + addresses. +*/ + +/* recognized load pages */ +#define PG_PROG 0x0 /* PROG page */ +#define PG_DATA 0x1 /* DATA page */ + +#define ADDR_MASK 0x00FFFFFF +#define PG_TO_FLAG(p) (((unsigned long)(p) & 0xFF) << 24) +#define FLAG_TO_PG(f) (((f) >> 24) & 0xFF) + +/* + * names of "special" sections + */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" +#define _CINIT ".cinit" /* initialized C data */ +#define _SCONST ".const" /* constants */ +#define _SWITCH ".switch" /* switch tables */ +#define _STACK ".stack" /* C stack */ +#define _SYSMEM ".sysmem" /* used for malloc et al. syscalls */ + +/********************** LINE NUMBERS **********************/ + +/* 1 line number entry for every "breakpointable" source line in a section. + * Line numbers are grouped on a per function basis; first entry in a function + * grouping will have l_lnno = 0 and in place of physical address will be the + * symbol table index of the function name. + */ +struct external_lineno { + union { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[4]; /* (physical) address of line number */ + } l_addr; + char l_lnno[2]; /* line number */ +}; + +#define LINENO struct external_lineno +#define LINESZ 6 + + +/********************** SYMBOLS **********************/ + +/* NOTE: this is what a local label looks like in assembly source; what it + looks like in COFF output is undefined */ +#define TICOFF_LOCAL_LABEL_P(NAME) \ +((NAME[0] == '$' && NAME[1] >= '0' && NAME[1] <= '9' && NAME[2] == '\0') \ + || NAME[strlen(NAME)-1] == '?') + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union { + char e_name[E_SYMNMLEN]; + struct { + char e_zeroes[4]; + char e_offset[4]; + } e; + } e; + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; +}; + + +#define N_BTMASK (017) +#define N_TMASK (060) +#define N_BTSHFT (4) +#define N_TSHIFT (2) + + +union external_auxent { + struct { + char x_tagndx[4]; /* str, un, or enum tag indx */ + union { + struct { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + char x_fsize[4]; /* size of function */ + } x_misc; + union { + struct { /* if ISFCN, tag, or .bb */ + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + struct { /* if ISARY, up to 4 dimen. */ + char x_dimen[E_DIMNUM][2]; + } x_ary; + } x_fcnary; + char x_tvndx[2]; /* tv index */ + } x_sym; + + union { + char x_fname[E_FILNMLEN]; + struct { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + } x_file; + + struct { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + } x_scn; + + struct { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ + + +}; + +#define SYMENT struct external_syment +#define SYMESZ 18 +#define AUXENT union external_auxent +#define AUXESZ 18 + +/* section lengths are in target bytes (not host bytes) */ +#define GET_SCN_SCNLEN(ABFD,EXT) \ +(bfd_h_get_32(ABFD,(bfd_byte *)(EXT)->x_scn.x_scnlen)*bfd_octets_per_byte(ABFD)) +#define PUT_SCN_SCNLEN(ABFD,INT,EXT) \ +bfd_h_put_32(ABFD,(INT)/bfd_octets_per_byte(ABFD),\ + (bfd_byte *)(EXT)->x_scn.x_scnlen) + +/* lnsz size is in bits in COFF file, in bytes in BFD */ +#define GET_LNSZ_SIZE(abfd, ext) \ +(bfd_h_get_16(abfd, (bfd_byte *)ext->x_sym.x_misc.x_lnsz.x_size) / \ + (class != C_FIELD ? 8 : 1)) + +#define PUT_LNSZ_SIZE(abfd, in, ext) \ + bfd_h_put_16(abfd, ((class != C_FIELD) ? (in)*8 : (in)), \ + (bfd_byte*) ext->x_sym.x_misc.x_lnsz.x_size) + +/* TI COFF stores offsets for MOS and MOU in bits; BFD expects bytes */ +#define COFF_ADJUST_SYM_IN_POST(ABFD,EXT,INT) \ +do { struct internal_syment *dst = (struct internal_syment *)(INT); \ +if (dst->n_sclass == C_MOS || dst->n_sclass == C_MOU) dst->n_value /= 8; \ +} while (0) + +#define COFF_ADJUST_SYM_OUT_POST(ABFD,INT,EXT) \ +do { struct internal_syment *src = (struct internal_syment *)(INT); \ +SYMENT *dst = (SYMENT *)(EXT); \ +if(src->n_sclass == C_MOU || src->n_sclass == C_MOS) \ +bfd_h_put_32(abfd,src->n_value * 8,(bfd_byte *)dst->e_value); \ +} while (0) + +/* Detect section-relative absolute symbols so they get flagged with a sym + index of -1. +*/ +#define SECTION_RELATIVE_ABSOLUTE_SYMBOL_P(RELOC,SECT) \ +((*(RELOC)->sym_ptr_ptr)->section->output_section == (SECT) \ + && (RELOC)->howto->name[0] == 'A') + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc_v0 { + char r_vaddr[4]; + char r_symndx[2]; + char r_reserved[2]; + char r_type[2]; +}; + +struct external_reloc { + char r_vaddr[4]; + char r_symndx[4]; + char r_reserved[2]; /* extended pmad byte for COFF2 */ + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ_V0 10 /* FIXME -- coffcode.h needs fixing */ +#define RELSZ 12 /* for COFF1/2 */ + +/* various relocation types. */ +#define R_ABS 0x0000 /* no relocation */ +#define R_REL13 0x002A /* 13-bit direct reference (???) */ +#define R_PARTLS7 0x0028 /* 7 LSBs of an address */ +#define R_PARTMS9 0x0029 /* 9MSBs of an address */ +#define R_EXTWORD 0x002B /* 23-bit direct reference */ +#define R_EXTWORD16 0x002C /* 16-bit direct reference to 23-bit addr*/ +#define R_EXTWORDMS7 0x002D /* upper 7 bits of 23-bit address */ + +#endif /* COFF_TI_H */ diff --git a/contrib/binutils/include/demangle.h b/contrib/binutils/include/demangle.h index 61dd230..7fb6259 100644 --- a/contrib/binutils/include/demangle.h +++ b/contrib/binutils/include/demangle.h @@ -37,10 +37,11 @@ same as ARM except for template arguments, etc. */ #define DMGL_EDG (1 << 13) -#define DMGL_GNU_NEW_ABI (1 << 14) +#define DMGL_GNU_V3 (1 << 14) +#define DMGL_GNAT (1 << 15) /* If none of these are set, use 'current_demangling_style' as the default. */ -#define DMGL_STYLE_MASK (DMGL_AUTO|DMGL_GNU|DMGL_LUCID|DMGL_ARM|DMGL_HP|DMGL_EDG|DMGL_GNU_NEW_ABI) +#define DMGL_STYLE_MASK (DMGL_AUTO|DMGL_GNU|DMGL_LUCID|DMGL_ARM|DMGL_HP|DMGL_EDG|DMGL_GNU_V3|DMGL_JAVA|DMGL_GNAT) /* Enumeration of possible demangling styles. @@ -59,7 +60,9 @@ extern enum demangling_styles arm_demangling = DMGL_ARM, hp_demangling = DMGL_HP, edg_demangling = DMGL_EDG, - gnu_new_abi_demangling = DMGL_GNU_NEW_ABI + gnu_v3_demangling = DMGL_GNU_V3, + java_demangling = DMGL_JAVA, + gnat_demangling = DMGL_GNAT } current_demangling_style; /* Define string names for the various demangling styles. */ @@ -70,7 +73,9 @@ extern enum demangling_styles #define ARM_DEMANGLING_STYLE_STRING "arm" #define HP_DEMANGLING_STYLE_STRING "hp" #define EDG_DEMANGLING_STYLE_STRING "edg" -#define GNU_NEW_ABI_DEMANGLING_STYLE_STRING "gnu-new-abi" +#define GNU_V3_DEMANGLING_STYLE_STRING "gnu-v3" +#define JAVA_DEMANGLING_STYLE_STRING "java" +#define GNAT_DEMANGLING_STYLE_STRING "gnat" /* Some macros to test what demangling style is active. */ @@ -81,7 +86,9 @@ extern enum demangling_styles #define ARM_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_ARM) #define HP_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_HP) #define EDG_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_EDG) -#define GNU_NEW_ABI_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_GNU_NEW_ABI) +#define GNU_V3_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_GNU_V3) +#define JAVA_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_JAVA) +#define GNAT_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_GNAT) /* Provide information about the available demangle styles. This code is pulled from gdb into libiberty because it is useful to binutils also. */ @@ -113,8 +120,8 @@ cplus_demangle_set_style PARAMS ((enum demangling_styles style)); extern enum demangling_styles cplus_demangle_name_to_style PARAMS ((const char *name)); -/* New-ABI demangling entry point, defined in cp-demangle.c. */ +/* V3 ABI demangling entry point, defined in cp-demangle.c. */ extern char* -cplus_demangle_new_abi PARAMS ((const char* mangled)); +cplus_demangle_v3 PARAMS ((const char* mangled)); #endif /* DEMANGLE_H */ diff --git a/contrib/binutils/include/dis-asm.h b/contrib/binutils/include/dis-asm.h index 6e6c04b..5c9d8d8 100644 --- a/contrib/binutils/include/dis-asm.h +++ b/contrib/binutils/include/dis-asm.h @@ -56,6 +56,11 @@ typedef struct disassemble_info { /* Endianness (for bi-endian cpus). Mono-endian cpus can ignore this. */ enum bfd_endian endian; + /* Some targets need information about the current section to accurately + display insns. If this is NULL, the target disassembler function + will have to make its best guess. */ + asection *section; + /* An array of pointers to symbols either at the location being disassembled or at the start of the function being disassembled. The array is sorted so that the first symbol is intended to be the one used. The others are @@ -157,7 +162,10 @@ extern int print_insn_big_mips PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_little_mips PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_i386_att PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_i386_intel PARAMS ((bfd_vma, disassemble_info*)); +extern int print_insn_ia64 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_i370 PARAMS ((bfd_vma, disassemble_info*)); +extern int print_insn_m68hc11 PARAMS ((bfd_vma, disassemble_info*)); +extern int print_insn_m68hc12 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_m68k PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_z8001 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_z8002 PARAMS ((bfd_vma, disassemble_info*)); @@ -166,12 +174,13 @@ extern int print_insn_h8300h PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_h8300s PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_h8500 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_alpha PARAMS ((bfd_vma, disassemble_info*)); -extern disassembler_ftype arc_get_disassembler PARAMS ((int, int)); +extern disassembler_ftype arc_get_disassembler PARAMS ((void *)); extern int print_insn_big_arm PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_little_arm PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_sparc PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_big_a29k PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_little_a29k PARAMS ((bfd_vma, disassemble_info*)); +extern int print_insn_i860 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_i960 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_sh PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_shl PARAMS ((bfd_vma, disassemble_info*)); @@ -187,11 +196,13 @@ extern int print_insn_big_powerpc PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_little_powerpc PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_rs6000 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_w65 PARAMS ((bfd_vma, disassemble_info*)); +extern disassembler_ftype cris_get_disassembler PARAMS ((bfd *)); extern int print_insn_d10v PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_d30v PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_v850 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_tic30 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_vax PARAMS ((bfd_vma, disassemble_info*)); +extern int print_insn_tic54x PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_tic80 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_pj PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_avr PARAMS ((bfd_vma, disassemble_info*)); @@ -245,13 +256,15 @@ extern int generic_symbol_at_address /* Call this macro to initialize only the internal variables for the disassembler. Architecture dependent things such as byte order, or machine variant are not touched by this macro. This makes things much easier for - GDB which must initialize these things seperatly. */ + GDB which must initialize these things separately. */ #define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \ (INFO).fprintf_func = (fprintf_ftype)(FPRINTF_FUNC), \ (INFO).stream = (PTR)(STREAM), \ + (INFO).section = NULL, \ (INFO).symbols = NULL, \ (INFO).num_symbols = 0, \ + (INFO).private_data = NULL, \ (INFO).buffer = NULL, \ (INFO).buffer_vma = 0, \ (INFO).buffer_length = 0, \ diff --git a/contrib/binutils/include/elf/ChangeLog b/contrib/binutils/include/elf/ChangeLog index ba8bf9f..05e73b8 100644 --- a/contrib/binutils/include/elf/ChangeLog +++ b/contrib/binutils/include/elf/ChangeLog @@ -1,15 +1,130 @@ -2000-10-14 Philip Blundell <philb@gnu.org> +2001-01-11 Peter Targett <peter.targett@arccores.com> - From 2000-07-19 H.J. Lu <hjl@gnu.org> + * arc.h (E_ARC_MACH_ARC5, E_ARC_MACH_ARC6, E_ARC_MACH_ARC7, + E_ARC_MACH_ARC8): New definitions for cpu types. + + * common.h (EM_ARC): Change comment. + +2000-12-12 Nick Clifton <nickc@redhat.com> + + * mips.h: Fix formatting. + +2000-12-11 Jeffrey A Law (law@cygnus.com) + + * hppa.h (DT_HP_*): Define relative to OLD_DT_LOOS for hpux + compatibility. + +2000-10-16 Chris Demetriou <cgd@sibyte.com> + + * mips.h (E_MIPS_ARCH_32): New constant. + (E_MIPS_MACH_MIPS32, E_MIPS_MACH_MIPS32_4K): Replace the + former with the latter. + + * mips.h (E_MIPS_ARCH_5, E_MIPS_ARCH_64): New definitions. + + * mips.h (E_MIPS_MACH_SB1): New constant. + +2000-11-30 Jan Hubicka <jh@suse.cz> + + * common.h (EM_X86_64): New macro. + * x86-64.h: New file. + +2000-11-27 Hans-Peter Nilsson <hp@axis.com> + + * common.h (e_machine numbers): Clarify comments to describe how + EM_* constants are assigned. Move EM_PJ from official section to + ad-hoc section. + (EM_CRIS): Correct comment to match official description. + (EM_MMIX): Ditto. + +2000-11-22 Nick Clifton <nickc@redhat.com> + + * common.h (EM_JAVELIN): New machine number. + (EM_FIREPATH): New machine number. + (EM_ZSP): New machine number. + (EM_MMIX): New machine number. + (EM_HUANY): New machine number. + (EM_PRISM): New machine number. + (SHT_GROUP): New section type. + (SHT_SYMTAB_SHNDX): New section type. + (SHF_GROUP): New section flag. + (SHN_XINDEX): New section index. + (GRP_COMDAT): New section group flag. + +2000-11-20 H.J. Lu <hjl@gnu.org> + + * common.h (ELFOSABI_MONTEREY): Renamed to ... + (ELFOSABI_AIX): This. + +2000-11-16 Richard Henderson <rth@redhat.com> + + Update relocations per August psABI docs. + * ia64.h (R_IA64_SEGBASE): Remove. + (R_IA64_LTV*): Renumber to 0x74 to 0x77. + (R_IA64_EPLTMSB, R_IA64_EPLTLSB): Remove. + (R_IA64_TPREL14, R_IA64_TPREL64I): New. + (R_IA64_DTPMOD*): New. + (R_IA64_DTPREL*): New. + +2000-09-29 Hans-Peter Nilsson <hp@axis.com> + + * cris.h (EF_CRIS_UNDERSCORE): New. + +2000-09-27 Alan Modra <alan@linuxcare.com.au> + + * hppa.h (R_PARISC_DIR14F): Add. + +2000-09-14 Alexandre Oliva <aoliva@redhat.com> + + * sh.h (R_SH_GOT32, R_SH_PLT32, R_SH_COPY, R_SH_GLOB_DAT, + R_SH_JMP_SLOT, R_SH_RELATIVE, R_SH_GOTOFF, R_SH_GOTPC): Change + numbers to the range from 160 to 167. + (R_SH_FIRST_INVALID_RELOC): Adjust. + (R_SH_FIRST_INVALID_RELOC_2, R_SH_LAST_INVALID_RELOC_2): + New relocs to fill in the gap. + +2000-09-13 Anders Norlander <anorland@acc.umu.se> + + * mips.h (E_MIPS_MACH_4K): New define. + +2000-09-05 Alan Modra <alan@linuxcare.com.au> + + * hppa.h: Fix a comment. + (R_PARISC_PCREL12F): Define. + (R_PARISC_GNU_VTENTRY): Define. + (R_PARISC_GNU_VTINHERIT): Define. + +2000-09-01 Alexandre Oliva <aoliva@redhat.com> + + * sh.h (R_SH_GOT32, R_SH_PLT32, R_SH_COPY, R_SH_GLOB_DAT, + R_SH_JMP_SLOT, R_SH_RELATIVE, R_SH_GOTOFF, R_SH_GOTPC): New relocs. + (R_SH_FIRST_INVALID_RELOC): Adjust. + +2000-08-14 Jim Wilson <wilson@cygnus.com> + + * elf/ia64.h (EF_IA_64_REDUCEDFP, EF_IA_64_CONS_GP, + EF_IA_64_NOFUNCDESC_CONS_GP, EF_IA_64_ABSOLUTE): Define. + +2000-08-07 Nick Clifton <nickc@cygnus.com> + + * ppc.h: Remove spurious CYGNUS LOCAL comments. + * v850.h: Likewise. + +2000-07-20 Hans-Peter Nilsson <hp@axis.com> + + common.h (EM_CRIS): New machine number. + cris.h: New file. + +2000-07-19 H.J. Lu <hjl@gnu.org> * common.h (DF_1_NODEFLIB): Renamed from DF_1_NODEPLIB. - From 2000-07-19 H.J. Lu <hjl@gnu.org> +2000-07-19 H.J. Lu <hjl@gnu.org> * common.h (DT_CHECKSUM): Set to 0x6ffffdf8. (DTF_1_CONFEXP): It is 0x00000002 as suspected. - From 2000-07-19 H.J. Lu <hjl@gnu.org> +2000-07-19 H.J. Lu <hjl@gnu.org> * common.h (DT_FEATURE): Renamed from DT_FEATURE_1. (DT_CONFIG): New. From Solaris 8. @@ -23,16 +138,83 @@ (DT_CHECKSUM): Likewise. FIXME. Check the value on Solaris 8. (DTF_1_CONFEXP): Likewise. - From 2000-07-18 H.J. Lu <hjl@gnu.org> +2000-07-18 H.J. Lu <hjl@gnu.org> * common.h (DT_FLAGS_1): Renamed from DT_1_FLAGS. +2000-07-12 Alan Modra <alan@linuxcare.com.au> + + * internal.h (struct elf_internal_sym): Update comment for st_other. + +2000-07-10 Alan Modra <alan@linuxcare.com.au> + + * hppa.h: Add comments to all the relocs. + +2000-06-26 Marek Michalkiewicz <marekm@linux.org.pl> + + * avr.h (E_AVR_MACH_AVR5): Define. + +2000-06-18 Stephane Carrez <stcarrez@worldnet.fr> + + * m68hc11.h: New file, definitions for the Motorola 68hc11. + +2000-06-06 Alan Modra <alan@linuxcare.com.au> + + * reloc-macros.h (START_RELOC_NUMBERS): Don't define initial dummy + -1 valued enum. + (RELOC_NUMBER, FAKE_RELOC, EMPTY_RELOC): Append rather than + prepend comma. + (END_RELOC_NUMBERS): Give macro an arg to define as last enum. + + * alpha.h (R_ALPHA_max): Define via END_RELOC_NUMBERS rather than + with EMPTY_RELOC. + * arc.h (R_ARC_max): Likewise. + * avr.h (R_AVR_max): Likewise. + * fr30.h (R_FR30_max): Likewise. + * hppa.h (R_PARISC_UNIMPLEMENTED): Likewise. + * i960.h (R_960_max): Likewise. + * m32r.h (R_M32R_max): Likewise. + * m68k.h (R_68K_max): Likewise. + * mcore.h (R_MCORE_max): Likewise. + * mn10300.h (R_MN10300_MAX): Likewise. + * pj.h (R_PJ_max): Likewise. + * ppc.h (R_PPC_max): Likewise. + * sh.h (R_SH_max): Likewise. + * sparc.h (R_SPARC_max): Likewise. + * v850.h (R_V850_max): Likewise. + + * arm.h (R_ARM_max): Define via END_RELOC_NUMBERS. + * d10v.h (R_D10V_max): Likewise. + * d30v.h (R_D30V_max): Likewise. + * ia64.h (R_IA64_max): Likewise. + * mips.h (R_MIPS_maxext): Likewise. + * mn10200.h (R_MN10200_max): Likewise. + + * i386.h (R_386_max): Remove old RELOC_NUMBER definition, and + define via END_RELOC_NUMBERS. + +2000-06-03 Alan Modra <alan@linuxcare.com.au> + + * reloc-macros.h (START_RELOC_NUMBERS): Fix name clash for + !__STDC__ case. + (RELOC_NUMBER): Use ansi stringify if ALMOST_STDC defined. + +2000-05-22 Richard Henderson <rth@cygnus.com> + + * ia64.h (R_IA64_PCREL60B, R_IA64_PCREL21BI): New. + (R_IA64_PCREL22, R_IA64_PCREL64I): New. + 2000-05-02 H.J. Lu <hjl@gnu.org> * common.h (ELFOSABI_NONE): Renamed from ELFOSABI_SYSV. (ELFOSABI_MODESTO): Defined. (ELFOSABI_OPENBSD): Likewise. +Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com> + David Mosberger <davidm@hpl.hp.com> + + * ia64.h: New file. + 2000-04-14 H.J. Lu <hjl@gnu.org> * common.h (ELFOSABI_TRUE64): Renamed to ELFOSABI_TRU64. @@ -47,6 +229,26 @@ (ELFOSABI_FREEBSD): Likewise. (ELFOSABI_TRUE64): Likewise. +2000-04-07 Nick Clifton <nickc@cygnus.com> + + * arm-oabi.h: Delete. + * arm.h: Merge in definitions of old reloc numbers from + arm-oabi.h. + +2000-04-06 Nick Clifton <nickc@cygnus.com> + + * arm.h (EF_ARM_SYMSARESORTED): Define. + (EF_ARM_EABIMASK): Define. + (EF_ARM_EABI_VERSION): Define. + (EF_ARM_EABI_UNKNOWN): Define. + (EF_ARM_EABI_VER1): Define. + (PF_ARM_PI): Define. + (PF_ARM_ABS): Define. + +Wed Apr 5 22:08:59 2000 J"orn Rennecke <amylaar@cygnus.co.uk> + + * sh.h (R_SH_LOOP_START, R_SH_LOOP_END): New RELOC_NUMBERs. + 2000-03-27 Denis Chertykov <denisc@overta.ru> * avr.h: New file. AVR ELF support for BFD. @@ -55,8 +257,8 @@ 2000-03-10 Geoffrey Keating <geoffk@cygnus.com> * mips.h: Add R_MIPS_GNU_REL_HI16, R_MIPS_GNU_REL_LO16, - R_MIPS_GNU_REL16_S2, R_MIPS_PC64 and R_MIPS_PC32 relocation - numbers. + R_MIPS_GNU_REL16_S2, R_MIPS_PC64 and R_MIPS_PC32 relocation + numbers. 2000-02-23 Linas Vepstas <linas@linas.org> @@ -85,7 +287,7 @@ Thu Feb 17 00:18:33 2000 J"orn Rennecke <amylaar@cygnus.co.uk> 2000-01-27 Thomas de Lellis <tdel@windriver.com> - * arm.h (STT_ARM_TFUNC): Define in terms of STT_LOPROC. + * arm.h (STT_ARM_TFUNC): Define in terms of STT_LOPROC. (STT_ARM_16BIT): New flag. Denotes a label that was defined in Thumb block but was does not identify a function. @@ -112,12 +314,12 @@ Thu Feb 17 00:18:33 2000 J"orn Rennecke <amylaar@cygnus.co.uk> 2000-01-10 Egor Duda <deo@logos-m.ru> - * common.h (NT_WIN32PSTATUS): Define. (cygwin elf core dumps). + * common.h (NT_WIN32PSTATUS): Define. (cygwin elf core dumps). 1999-12-28 Nick Clifton <nickc@cygnus.com> * mips.h (STO_*): Redefine in terms of STV_* values now in - common.h. + common.h. 1999-12-27 Nick Clifton <nickc@cygnus.com> @@ -175,7 +377,7 @@ Thu Feb 17 00:18:33 2000 J"orn Rennecke <amylaar@cygnus.co.uk> * i960.h (reloc-macros.h): Include using relative dir elf/. * i386.h (reloc-macros.h): Include using relative dir elf/. * hppa.h (reloc-macros.h): Include using relative dir elf/. - + 1999-12-07 Jim Blandy <jimb@cygnus.com> * common.h (NT_PRXFPREG): New definition. @@ -284,9 +486,9 @@ Wed Jun 9 15:16:34 1999 Jeffrey A Law (law@cygnus.com) * mcore.h (R_MCORE_RELATIVE): Define. -999-05-05 Catherine Moore <clm@cygnus.com> +1999-05-05 Catherine Moore <clm@cygnus.com> - * m68k.h (EF_CPU32): Define. + * m68k.h (EF_CPU32): Define. 1999-04-21 Nick Clifton <nickc@cygnus.com> @@ -344,10 +546,10 @@ Thu Feb 18 18:58:26 1999 Ian Lance Taylor <ian@cygnus.com> Mon Feb 1 11:33:56 1999 Catherine Moore <clm@cygnus.com> - * arm.h: Renumber relocs to conform to standard. - (EF_NEW_ABI): Define. - (EF_OLD_ABI): Define. - * arm-oabi.h: New file. + * arm.h: Renumber relocs to conform to standard. + (EF_NEW_ABI): Define. + (EF_OLD_ABI): Define. + * arm-oabi.h: New file. 1999-01-28 Nick Clifton <nickc@cygnus.com> @@ -384,7 +586,7 @@ Tue Nov 10 15:12:28 1998 Nick Clifton <nickc@cygnus.com> Tue Nov 10 15:17:28 1998 Catherine Moore <clm@cygnus.com> - * d10v.h: Add vtable relocs. + * d10v.h: Add vtable relocs. Wed Nov 4 15:56:50 1998 Nick Clifton <nickc@cygnus.com> @@ -394,9 +596,9 @@ Wed Nov 4 15:56:50 1998 Nick Clifton <nickc@cygnus.com> Fri Oct 30 11:54:15 1998 Catherine Moore <clm@cygnus.com> - From Philip Blundell <pb@nexus.co.uk>: - * arm.h (R_ARM_COPY, et al.): New relocs, used by Linux for PIC. - (EF_ALIGN8): New flag. + From Philip Blundell <pb@nexus.co.uk>: + * arm.h (R_ARM_COPY, et al.): New relocs, used by Linux for PIC. + (EF_ALIGN8): New flag. Tue Oct 20 11:19:50 1998 Ian Lance Taylor <ian@cygnus.com> @@ -404,25 +606,25 @@ Tue Oct 20 11:19:50 1998 Ian Lance Taylor <ian@cygnus.com> Mon Oct 19 20:24:11 1998 Catherine Moore <clm@cygnus.com> - * sh.h: Add vtable relocs. + * sh.h: Add vtable relocs. Mon Oct 19 01:44:42 1998 Felix Lee <flee@cygnus.com> * common.h (NT_PSTATUS, NT_FPREGS, NT_PSINFO, - NT_LWPSTATUS,NT_LWPSINFO): added. + NT_LWPSTATUS,NT_LWPSINFO): added. * internal.h (Elf_Internal_Note): new structure members. Fri Oct 16 14:11:25 1998 Catherine Moore <clm@cygnus.com> - * m32r.h: Add vtable relocs. + * m32r.h: Add vtable relocs. Tue Oct 6 09:22:22 1998 Catherine Moore <clm@cygnus.com> - * sparc.h: Add vtable relocs. + * sparc.h: Add vtable relocs. Mon Oct 5 09:39:22 1998 Catherine Moore <clm@cygnus.com> - * v850.h: Add vtable relocs. + * v850.h: Add vtable relocs. Sun Oct 4 21:17:51 1998 Ian Lance Taylor <ian@cygnus.com> @@ -430,7 +632,7 @@ Sun Oct 4 21:17:51 1998 Ian Lance Taylor <ian@cygnus.com> Mon Sep 21 12:24:44 1998 Catherine Moore <clm@cygnus.com> - * i386.h: Change vtable reloc numbers. + * i386.h: Change vtable reloc numbers. Sun Sep 20 00:54:22 1998 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> @@ -438,12 +640,12 @@ Sun Sep 20 00:54:22 1998 Andreas Schwab <schwab@issan.informatik.uni-dortmund. Tue Sep 15 09:56:49 CDT 1998 Catherine Moore <clm@cygnus.com> - * arm.h: Add vtable relocs. + * arm.h: Add vtable relocs. Mon Aug 31 11:25:27 1998 Catherine Moore <clm@cygnus.com> - * arm.h: Define STT_ARM_TFUNC. Remove ST_THUMB_xxxx - definitions. + * arm.h: Define STT_ARM_TFUNC. Remove ST_THUMB_xxxx + definitions. Sat Aug 29 22:25:51 1998 Richard Henderson <rth@cygnus.com> @@ -460,7 +662,7 @@ Sat Aug 29 22:25:51 1998 Richard Henderson <rth@cygnus.com> Sun Aug 9 20:26:49 CDT 1998 Catherine Moore <clm@cygnus.com> - * arm.h: Add ST_THUMB definitions. + * arm.h: Add ST_THUMB definitions. Wed Aug 5 15:52:35 1998 Nick Clifton <nickc@cygnus.com> @@ -476,7 +678,7 @@ Wed Aug 5 15:52:35 1998 Nick Clifton <nickc@cygnus.com> Fri Jul 31 10:01:40 1998 Catherine Moore <clm@cygnus.com> - * arm.h: Add R_ARM_THM_PC9 relocation. + * arm.h: Add R_ARM_THM_PC9 relocation. 1998-07-30 16:25 Ulrich Drepper <drepper@cygnus.com> @@ -496,7 +698,7 @@ Fri Jul 24 11:22:06 1998 Jeffrey A Law (law@cygnus.com) Wed Jul 22 19:29:00 Catherine Moore <clm@cygnus.com> - * arm.h: Rename relocations. + * arm.h: Rename relocations. 1998-07-22 Ulrich Drepper <drepper@cygnus.com> diff --git a/contrib/binutils/include/elf/alpha.h b/contrib/binutils/include/elf/alpha.h index 1ae9d5e..d353434 100644 --- a/contrib/binutils/include/elf/alpha.h +++ b/contrib/binutils/include/elf/alpha.h @@ -1,5 +1,5 @@ /* ALPHA ELF support for BFD. - Copyright (C) 1996, 1998 Free Software Foundation, Inc. + Copyright (C) 1996, 98, 2000 Free Software Foundation, Inc. By Eric Youngdale, <eric@aib.com>. No processor supplement available for this platform. @@ -102,7 +102,6 @@ START_RELOC_NUMBERS (elf_alpha_reloc_type) RELOC_NUMBER (R_ALPHA_JMP_SLOT, 26) /* Create PLT entry */ RELOC_NUMBER (R_ALPHA_RELATIVE, 27) /* Adjust by program base */ - EMPTY_RELOC (R_ALPHA_max) -END_RELOC_NUMBERS +END_RELOC_NUMBERS (R_ALPHA_max) #endif /* _ELF_ALPHA_H */ diff --git a/contrib/binutils/include/elf/arc.h b/contrib/binutils/include/elf/arc.h index 334b55f..a8d0a74 100644 --- a/contrib/binutils/include/elf/arc.h +++ b/contrib/binutils/include/elf/arc.h @@ -1,5 +1,5 @@ /* ARC ELF support for BFD. - Copyright (C) 1995, 1997 Free Software Foundation, Inc. + Copyright (C) 1995, 97, 98, 2000 Free Software Foundation, Inc. Contributed by Doug Evans, (dje@cygnus.com) This file is part of BFD, the Binary File Descriptor library. @@ -26,29 +26,31 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "elf/reloc-macros.h" /* Relocations. */ + START_RELOC_NUMBERS (elf_arc_reloc_type) RELOC_NUMBER (R_ARC_NONE, 0) RELOC_NUMBER (R_ARC_32, 1) RELOC_NUMBER (R_ARC_B26, 2) RELOC_NUMBER (R_ARC_B22_PCREL, 3) - EMPTY_RELOC (R_ARC_max) -END_RELOC_NUMBERS +END_RELOC_NUMBERS (R_ARC_max) /* Processor specific flags for the ELF header e_flags field. */ /* Four bit ARC machine type field. */ -#define EF_ARC_MACH 0x0000000f + +#define EF_ARC_MACH 0x0000000f /* Various CPU types. */ -#define E_ARC_MACH_BASE 0x00000000 -#define E_ARC_MACH_UNUSED1 0x00000001 -#define E_ARC_MACH_UNUSED2 0x00000002 -#define E_ARC_MACH_UNUSED4 0x00000003 -/* Leave bits 0xf0 alone in case we ever have more than 16 cpu types. - Highly unlikely, but what the heck. */ +#define E_ARC_MACH_ARC5 0 +#define E_ARC_MACH_ARC6 1 +#define E_ARC_MACH_ARC7 2 +#define E_ARC_MACH_ARC8 3 + +/* Leave bits 0xf0 alone in case we ever have more than 16 cpu types. */ /* File contains position independent code. */ -#define EF_ARC_PIC 0x00000100 + +#define EF_ARC_PIC 0x00000100 #endif /* _ELF_ARC_H */ diff --git a/contrib/binutils/include/elf/arm.h b/contrib/binutils/include/elf/arm.h index 4d3405d..0499251 100644 --- a/contrib/binutils/include/elf/arm.h +++ b/contrib/binutils/include/elf/arm.h @@ -34,6 +34,14 @@ #define EF_OLD_ABI 0x100 #define EF_SOFT_FLOAT 0x200 +/* Other constants defined in the ARM ELF spec. version A-08. */ +#define EF_ARM_SYMSARESORTED 0x04 /* NB conflicts with EF_INTERWORK */ +#define EF_ARM_EABIMASK 0xFF000000 + +#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) +#define EF_ARM_EABI_UNKNOWN 0x00000000 +#define EF_ARM_EABI_VER1 0x01000000 + /* Local aliases for some flags to match names used by COFF port. */ #define F_INTERWORK EF_INTERWORK #define F_APCS26 EF_APCS_26 @@ -51,49 +59,71 @@ /* ARM-specific program header flags. */ #define PF_ARM_SB 0x10000000 /* Segment contains the location addressed by the static base. */ +#define PF_ARM_PI 0x20000000 /* Segment is position-independent. */ +#define PF_ARM_ABS 0x40000000 /* Segment must be loaded at its base address. */ /* Relocation types. */ + START_RELOC_NUMBERS (elf_arm_reloc_type) - RELOC_NUMBER (R_ARM_NONE, 0) - RELOC_NUMBER (R_ARM_PC24, 1) - RELOC_NUMBER (R_ARM_ABS32, 2) - RELOC_NUMBER (R_ARM_REL32, 3) - RELOC_NUMBER (R_ARM_PC13, 4) - RELOC_NUMBER (R_ARM_ABS16, 5) - RELOC_NUMBER (R_ARM_ABS12, 6) - RELOC_NUMBER (R_ARM_THM_ABS5, 7) - RELOC_NUMBER (R_ARM_ABS8, 8) - RELOC_NUMBER (R_ARM_SBREL32, 9) - RELOC_NUMBER (R_ARM_THM_PC22, 10) - RELOC_NUMBER (R_ARM_THM_PC8, 11) - RELOC_NUMBER (R_ARM_AMP_VCALL9, 12) - RELOC_NUMBER (R_ARM_SWI24, 13) - RELOC_NUMBER (R_ARM_THM_SWI8, 14) - RELOC_NUMBER (R_ARM_XPC25, 15) - RELOC_NUMBER (R_ARM_THM_XPC22, 16) - RELOC_NUMBER (R_ARM_COPY, 20) /* copy symbol at runtime */ - RELOC_NUMBER (R_ARM_GLOB_DAT, 21) /* create GOT entry */ - RELOC_NUMBER (R_ARM_JUMP_SLOT, 22) /* create PLT entry */ - RELOC_NUMBER (R_ARM_RELATIVE, 23) /* adjust by program base */ - RELOC_NUMBER (R_ARM_GOTOFF, 24) /* 32 bit offset to GOT */ - RELOC_NUMBER (R_ARM_GOTPC, 25) /* 32 bit PC relative offset to GOT */ - RELOC_NUMBER (R_ARM_GOT32, 26) /* 32 bit GOT entry */ - RELOC_NUMBER (R_ARM_PLT32, 27) /* 32 bit PLT address */ - FAKE_RELOC (FIRST_INVALID_RELOC1, 28) - FAKE_RELOC (LAST_INVALID_RELOC1, 99) - RELOC_NUMBER (R_ARM_GNU_VTENTRY, 100) - RELOC_NUMBER (R_ARM_GNU_VTINHERIT, 101) - RELOC_NUMBER (R_ARM_THM_PC11, 102) /* Cygnus extension to abi: Thumb unconditional branch */ - RELOC_NUMBER (R_ARM_THM_PC9, 103) /* Cygnus extension to abi: Thumb conditional branch */ + RELOC_NUMBER (R_ARM_NONE, 0) + RELOC_NUMBER (R_ARM_PC24, 1) + RELOC_NUMBER (R_ARM_ABS32, 2) + RELOC_NUMBER (R_ARM_REL32, 3) +#ifdef OLD_ARM_ABI + RELOC_NUMBER (R_ARM_ABS8, 4) + RELOC_NUMBER (R_ARM_ABS16, 5) + RELOC_NUMBER (R_ARM_ABS12, 6) + RELOC_NUMBER (R_ARM_THM_ABS5, 7) + RELOC_NUMBER (R_ARM_THM_PC22, 8) + RELOC_NUMBER (R_ARM_SBREL32, 9) + RELOC_NUMBER (R_ARM_AMP_VCALL9, 10) + RELOC_NUMBER (R_ARM_THM_PC11, 11) /* Cygnus extension to abi: Thumb unconditional branch. */ + RELOC_NUMBER (R_ARM_THM_PC9, 12) /* Cygnus extension to abi: Thumb conditional branch. */ + RELOC_NUMBER (R_ARM_GNU_VTINHERIT, 13) + RELOC_NUMBER (R_ARM_GNU_VTENTRY, 14) +#else /* not OLD_ARM_ABI */ + RELOC_NUMBER (R_ARM_PC13, 4) + RELOC_NUMBER (R_ARM_ABS16, 5) + RELOC_NUMBER (R_ARM_ABS12, 6) + RELOC_NUMBER (R_ARM_THM_ABS5, 7) + RELOC_NUMBER (R_ARM_ABS8, 8) + RELOC_NUMBER (R_ARM_SBREL32, 9) + RELOC_NUMBER (R_ARM_THM_PC22, 10) + RELOC_NUMBER (R_ARM_THM_PC8, 11) + RELOC_NUMBER (R_ARM_AMP_VCALL9, 12) + RELOC_NUMBER (R_ARM_SWI24, 13) + RELOC_NUMBER (R_ARM_THM_SWI8, 14) + RELOC_NUMBER (R_ARM_XPC25, 15) + RELOC_NUMBER (R_ARM_THM_XPC22, 16) +#endif /* not OLD_ARM_ABI */ + RELOC_NUMBER (R_ARM_COPY, 20) /* Copy symbol at runtime. */ + RELOC_NUMBER (R_ARM_GLOB_DAT, 21) /* Create GOT entry. */ + RELOC_NUMBER (R_ARM_JUMP_SLOT, 22) /* Create PLT entry. */ + RELOC_NUMBER (R_ARM_RELATIVE, 23) /* Adjust by program base. */ + RELOC_NUMBER (R_ARM_GOTOFF, 24) /* 32 bit offset to GOT. */ + RELOC_NUMBER (R_ARM_GOTPC, 25) /* 32 bit PC relative offset to GOT. */ + RELOC_NUMBER (R_ARM_GOT32, 26) /* 32 bit GOT entry. */ + RELOC_NUMBER (R_ARM_PLT32, 27) /* 32 bit PLT address. */ +#ifdef OLD_ARM_ABI + FAKE_RELOC (FIRST_INVALID_RELOC, 28) + FAKE_RELOC (LAST_INVALID_RELOC, 249) +#else /* not OLD_ARM_ABI */ + FAKE_RELOC (FIRST_INVALID_RELOC1, 28) + FAKE_RELOC (LAST_INVALID_RELOC1, 99) + RELOC_NUMBER (R_ARM_GNU_VTENTRY, 100) + RELOC_NUMBER (R_ARM_GNU_VTINHERIT, 101) + RELOC_NUMBER (R_ARM_THM_PC11, 102) /* Cygnus extension to abi: Thumb unconditional branch. */ + RELOC_NUMBER (R_ARM_THM_PC9, 103) /* Cygnus extension to abi: Thumb conditional branch. */ FAKE_RELOC (FIRST_INVALID_RELOC2, 104) FAKE_RELOC (LAST_INVALID_RELOC2, 248) - RELOC_NUMBER (R_ARM_RXPC25, 249) - RELOC_NUMBER (R_ARM_RSBREL32, 250) - RELOC_NUMBER (R_ARM_THM_RPC22, 251) - RELOC_NUMBER (R_ARM_RREL32, 252) - RELOC_NUMBER (R_ARM_RABS32, 253) - RELOC_NUMBER (R_ARM_RPC24, 254) - RELOC_NUMBER (R_ARM_RBASE, 255) -END_RELOC_NUMBERS - -#endif + RELOC_NUMBER (R_ARM_RXPC25, 249) +#endif /* not OLD_ARM_ABI */ + RELOC_NUMBER (R_ARM_RSBREL32, 250) + RELOC_NUMBER (R_ARM_THM_RPC22, 251) + RELOC_NUMBER (R_ARM_RREL32, 252) + RELOC_NUMBER (R_ARM_RABS32, 253) + RELOC_NUMBER (R_ARM_RPC24, 254) + RELOC_NUMBER (R_ARM_RBASE, 255) +END_RELOC_NUMBERS (R_ARM_max) + +#endif /* _ELF_ARM_H */ diff --git a/contrib/binutils/include/elf/avr.h b/contrib/binutils/include/elf/avr.h index 1527455..09cdf7b 100644 --- a/contrib/binutils/include/elf/avr.h +++ b/contrib/binutils/include/elf/avr.h @@ -30,6 +30,7 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define E_AVR_MACH_AVR2 2 #define E_AVR_MACH_AVR3 3 #define E_AVR_MACH_AVR4 4 +#define E_AVR_MACH_AVR5 5 /* Relocations. */ START_RELOC_NUMBERS (elf_avr_reloc_type) @@ -52,7 +53,6 @@ START_RELOC_NUMBERS (elf_avr_reloc_type) RELOC_NUMBER (R_AVR_HI8_LDI_PM_NEG, 16) RELOC_NUMBER (R_AVR_HH8_LDI_PM_NEG, 17) RELOC_NUMBER (R_AVR_CALL, 18) - EMPTY_RELOC (R_AVR_max) -END_RELOC_NUMBERS +END_RELOC_NUMBERS (R_AVR_max) #endif /* _ELF_AVR_H */ diff --git a/contrib/binutils/include/elf/common.h b/contrib/binutils/include/elf/common.h index b290853..d127b9c 100644 --- a/contrib/binutils/include/elf/common.h +++ b/contrib/binutils/include/elf/common.h @@ -64,21 +64,21 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define ELFOSABI_LINUX 3 /* GNU/Linux */ #define ELFOSABI_HURD 4 /* GNU/Hurd */ #define ELFOSABI_SOLARIS 6 /* Solaris */ -#define ELFOSABI_MONTEREY 7 /* Monterey */ +#define ELFOSABI_AIX 7 /* AIX */ #define ELFOSABI_IRIX 8 /* IRIX */ #define ELFOSABI_FREEBSD 9 /* FreeBSD */ #define ELFOSABI_TRU64 10 /* TRU64 UNIX */ #define ELFOSABI_MODESTO 11 /* Novell Modesto */ #define ELFOSABI_OPENBSD 12 /* OpenBSD */ #define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ -#define ELFOSABI_ARM 97 /* ARM */ +#define ELFOSABI_ARM 97 /* ARM */ #define EI_ABIVERSION 8 /* ABI version */ #define EI_PAD 9 /* Start of padding bytes */ -/* Values for e_type, which identifies the object file type */ +/* Values for e_type, which identifies the object file type. */ #define ET_NONE 0 /* No file type */ #define ET_REL 1 /* Relocatable file */ @@ -90,7 +90,9 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define ET_LOPROC 0xFF00 /* Processor-specific */ #define ET_HIPROC 0xFFFF /* Processor-specific */ -/* Values for e_machine, which identifies the architecture */ +/* Values for e_machine, which identifies the architecture. These numbers + are officially assigned by registry@sco.com. See below for a list of + ad-hoc numbers used during initial development. */ #define EM_NONE 0 /* No machine */ #define EM_M32 1 /* AT&T WE 32100 */ @@ -98,7 +100,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define EM_386 3 /* Intel 80386 */ #define EM_68K 4 /* Motorola m68k family */ #define EM_88K 5 /* Motorola m88k family */ -#define EM_486 6 /* Intel 80486 */ +#define EM_486 6 /* Intel 80486 *//* Reserved for future use */ #define EM_860 7 /* Intel 80860 */ #define EM_MIPS 8 /* MIPS R3000 (officially, big-endian only) */ #define EM_S370 9 /* IBM System/370 */ @@ -123,7 +125,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define EM_SH 42 /* Hitachi SH */ #define EM_SPARCV9 43 /* SPARC v9 64-bit */ #define EM_TRICORE 44 /* Siemens Tricore embedded processor */ -#define EM_ARC 45 /* Argonaut RISC Core, Argonaut Technologies Inc. */ +#define EM_ARC 45 /* ARC Cores */ #define EM_H8_300 46 /* Hitachi H8/300 */ #define EM_H8_300H 47 /* Hitachi H8/300H */ #define EM_H8S 48 /* Hitachi H8S */ @@ -140,6 +142,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define EM_ME16 59 /* Toyota ME16 processor */ #define EM_ST100 60 /* STMicroelectronics ST100 processor */ #define EM_TINYJ 61 /* Advanced Logic Corp. TinyJ embedded processor */ +#define EM_X86_64 62 /* Advanced Micro Devices X86-64 processor */ #define EM_FX66 66 /* Siemens FX66 microcontroller */ #define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 bit microcontroller */ @@ -149,10 +152,15 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define EM_68HC08 71 /* Motorola MC68HC08 Microcontroller */ #define EM_68HC05 72 /* Motorola MC68HC05 Microcontroller */ #define EM_SVX 73 /* Silicon Graphics SVx */ -#define EM_ST19 74 /* STMicroelectronics ST19 8-bit microcontroller */ +#define EM_ST19 74 /* STMicroelectronics ST19 8-bit cpu */ #define EM_VAX 75 /* Digital VAX */ - -#define EM_PJ 99 /* picoJava */ +#define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ +#define EM_JAVELIN 77 /* Infineon Technologies 32-bit embedded cpu */ +#define EM_FIREPATH 78 /* Element 14 64-bit DSP processor */ +#define EM_ZSP 79 /* LSI Logic's 16-bit DSP processor */ +#define EM_MMIX 80 /* Donald Knuth's educational 64-bit processor */ +#define EM_HUANY 81 /* Harvard's machine-independent format */ +#define EM_PRISM 82 /* SiTera Prism */ /* If it is necessary to assign new unofficial EM_* values, please pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision @@ -160,7 +168,13 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ NOTE: Do not just increment the most recent number by one. Somebody else somewhere will do exactly the same thing, and you - will have a collision. Instead, pick a random number. */ + will have a collision. Instead, pick a random number. + + Normally, each entity or maintainer responsible for a machine with an + unofficial e_machine number should eventually ask registry@sco.com for + an officially blessed number to be added to the list above. */ + +#define EM_PJ 99 /* picoJava */ /* Cygnus PowerPC ELF backend. Written in the absence of an ABI. */ #define EM_CYGNUS_POWERPC 0x9025 @@ -204,12 +218,12 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* See the above comment before you add a new EM_* value here. */ -/* Values for e_version */ +/* Values for e_version. */ #define EV_NONE 0 /* Invalid ELF version */ #define EV_CURRENT 1 /* Current version */ -/* Values for program header, p_type field */ +/* Values for program header, p_type field. */ #define PT_NULL 0 /* Program header table entry unused */ #define PT_LOAD 1 /* Loadable program segment */ @@ -223,7 +237,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define PT_LOPROC 0x70000000 /* Processor-specific */ #define PT_HIPROC 0x7FFFFFFF /* Processor-specific */ -/* Program segment permissions, in program header p_flags field */ +/* Program segment permissions, in program header p_flags field. */ #define PF_X (1 << 0) /* Segment is executable */ #define PF_W (1 << 1) /* Segment is writable */ @@ -232,7 +246,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define PF_MASKOS 0x0FF00000 /* New value, Oct 4, 1999 Draft */ #define PF_MASKPROC 0xF0000000 /* Processor-specific reserved bits */ -/* Values for section header, sh_type field */ +/* Values for section header, sh_type field. */ #define SHT_NULL 0 /* Section header table entry unused */ #define SHT_PROGBITS 1 /* Program specific (private) data */ @@ -247,12 +261,14 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define SHT_SHLIB 10 /* Reserved, unspecified semantics */ #define SHT_DYNSYM 11 /* Dynamic linking symbol table */ -#define SHT_INIT_ARRAY 14 /* Array of pointers to init functions */ -#define SHT_FINI_ARRAY 15 /* Array of pointers to finish functions */ -#define SHT_PREINIT_ARRAY 16 /* Array of pointers to pre-init functions */ +#define SHT_INIT_ARRAY 14 /* Array of ptrs to init functions */ +#define SHT_FINI_ARRAY 15 /* Array of ptrs to finish functions */ +#define SHT_PREINIT_ARRAY 16 /* Array of ptrs to pre-init funcs */ +#define SHT_GROUP 17 /* Section contains a section group */ +#define SHT_SYMTAB_SHNDX 18 /* Indicies for SHN_XINDEX entries */ -#define SHT_LOOS 0x60000000 /* Operating system specific semantics, lo */ -#define SHT_HIOS 0x6fffffff /* Operating system specific semantics, hi */ +#define SHT_LOOS 0x60000000 /* First of OS specific semantics */ +#define SHT_HIOS 0x6fffffff /* Last of OS specific semantics */ /* The next three section types are defined by Solaris, and are named SHT_SUNW*. We use them in GNU code, so we also define SHT_GNU* @@ -271,7 +287,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* #define SHT_HIUSER 0x8FFFFFFF *//* Application-specific semantics */ #define SHT_HIUSER 0xFFFFFFFF /* New value, defined in Oct 4, 1999 Draft */ -/* Values for section header, sh_flags field */ +/* Values for section header, sh_flags field. */ #define SHF_WRITE (1 << 0) /* Writable data during execution */ #define SHF_ALLOC (1 << 1) /* Occupies memory during execution */ @@ -280,13 +296,14 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define SHF_STRINGS (1 << 5) /* Contains null terminated character strings */ #define SHF_INFO_LINK (1 << 6) /* sh_info holds section header table index */ #define SHF_LINK_ORDER (1 << 7) /* Preserve section ordering when linking */ -#define SHF_OS_NONCONFORMING (1 << 8) /* OS specifci processing required */ +#define SHF_OS_NONCONFORMING (1 << 8) /* OS specific processing required */ +#define SHF_GROUP (1 << 9) /* Member of a section group */ /* #define SHF_MASKOS 0x0F000000 *//* OS-specific semantics */ #define SHF_MASKOS 0x0FF00000 /* New value, Oct 4, 1999 Draft */ #define SHF_MASKPROC 0xF0000000 /* Processor-specific semantics */ -/* Values of note segment descriptor types for core files. */ +/* Values of note segment descriptor types for core files. */ #define NT_PRSTATUS 1 /* Contains copy of prstatus struct */ #define NT_FPREGSET 2 /* Contains copy of fpregset struct */ @@ -295,7 +312,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define NT_PRXFPREG 0x46e62b7f /* Contains a user_xfpregs_struct; */ /* note name must be "LINUX". */ -/* Note segments for core files on dir-style procfs systems. */ +/* Note segments for core files on dir-style procfs systems. */ #define NT_PSTATUS 10 /* Has a struct pstatus */ #define NT_FPREGS 12 /* Has a struct fpregset */ @@ -311,7 +328,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* These three macros disassemble and assemble a symbol table st_info field, which contains the symbol binding and symbol type. The STB_ and STT_ - defines identify the binding and type. */ + defines identify the binding and type. */ #define ELF_ST_BIND(val) (((unsigned int)(val)) >> 4) #define ELF_ST_TYPE(val) ((val) & 0xF) @@ -337,7 +354,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define ELF64_ST_VISIBILITY ELF_ST_VISIBILITY -#define STN_UNDEF 0 /* undefined symbol index */ +#define STN_UNDEF 0 /* Undefined symbol index */ #define STB_LOCAL 0 /* Symbol not visible outside obj */ #define STB_GLOBAL 1 /* Symbol visible outside obj */ @@ -359,7 +376,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define STT_HIPROC 15 /* Application-specific semantics */ /* Special section indices, which may show up in st_shndx fields, among - other places. */ + other places. */ #define SHN_UNDEF 0 /* Undefined section reference */ #define SHN_LORESERVE 0xFF00 /* Begin range of reserved indices */ @@ -367,9 +384,10 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define SHN_HIPROC 0xFF1F /* End range of appl-specific */ #define SHN_LOOS 0xFF20 /* OS specific semantics, lo */ #define SHN_HIOS 0xFF3F /* OS specific semantics, hi */ -#define SHN_ABS 0xFFF1 /* Associated symbol is absolute */ -#define SHN_COMMON 0xFFF2 /* Associated symbol is in common */ -#define SHN_HIRESERVE 0xFFFF /* End range of reserved indices */ +#define SHN_ABS 0xFFF1 /* Associated symbol is absolute */ +#define SHN_COMMON 0xFFF2 /* Associated symbol is in common */ +#define SHN_XINDEX 0xFFFF /* Section index it held elsewhere */ +#define SHN_HIRESERVE 0xFFFF /* End range of reserved indices */ /* The following constants control how a symbol may be accessed once it has become part of an executable or shared library. */ @@ -378,9 +396,8 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define STV_INTERNAL 1 /* OS specific version of STV_HIDDEN */ #define STV_HIDDEN 2 /* Can only be seen inside currect component */ #define STV_PROTECTED 3 /* Treat as STB_LOCAL inside current component */ - -/* relocation info handling macros */ +/* Relocation info handling macros. */ #define ELF32_R_SYM(i) ((i) >> 8) #define ELF32_R_TYPE(i) ((i) & 0xff) @@ -390,7 +407,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define ELF64_R_TYPE(i) ((i) & 0xffffffff) #define ELF64_R_INFO(s,t) (((bfd_vma) (s) << 32) + (bfd_vma) (t)) -/* Dynamic section tags */ +/* Dynamic section tags. */ #define DT_NULL 0 #define DT_NEEDED 1 @@ -492,7 +509,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ http://docs.sun.com:80/ab2/coll.45.13/LLM/@Ab2PageView/21165?Ab2Lang=C&Ab2Enc=iso-8859-1 DTF_1_CONFEXP is the same as DTF_1_PARINIT. It is a typo. The value - defined here is the same as the one in <sys/link.h> on Solaris 8. */ + defined here is the same as the one in <sys/link.h> on Solaris 8. */ #define DTF_1_CONFEXP 0x00000002 /* Flag values used in the DT_POSFLAG_1 .dynamic entry. */ @@ -563,19 +580,26 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define ELF_VER_CHR '@' /* Possible values for si_boundto. */ + #define SYMINFO_BT_SELF 0xffff /* Symbol bound to self */ #define SYMINFO_BT_PARENT 0xfffe /* Symbol bound to parent */ #define SYMINFO_BT_LOWRESERVE 0xff00 /* Beginning of reserved entries */ /* Possible bitmasks for si_flags. */ + #define SYMINFO_FLG_DIRECT 0x0001 /* Direct bound symbol */ #define SYMINFO_FLG_PASSTHRU 0x0002 /* Pass-thru symbol for translator */ #define SYMINFO_FLG_COPY 0x0004 /* Symbol is a copy-reloc */ -#define SYMINFO_FLG_LAZYLOAD 0x0008 /* Symbol bound to object to be lazy - loaded */ +#define SYMINFO_FLG_LAZYLOAD 0x0008 /* Symbol bound to object to be lazy loaded */ + /* Syminfo version values. */ + #define SYMINFO_NONE 0 #define SYMINFO_CURRENT 1 #define SYMINFO_NUM 2 +/* Section Group Flags. */ + +#define GRP_COMDAT 0x1 /* A COMDAT group */ + #endif /* _ELF_COMMON_H */ diff --git a/contrib/binutils/include/elf/cris.h b/contrib/binutils/include/elf/cris.h new file mode 100644 index 0000000..957f194 --- /dev/null +++ b/contrib/binutils/include/elf/cris.h @@ -0,0 +1,47 @@ +/* CRIS ELF support for BFD. + Copyright (C) 2000 Free Software Foundation, Inc. + Contributed by Axis Communications AB, Lund, Sweden. + Written by Hans-Peter Nilsson. + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_CRIS_H +#define _ELF_CRIS_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_cris_reloc_type) + RELOC_NUMBER (R_CRIS_NONE, 0) + RELOC_NUMBER (R_CRIS_8, 1) + RELOC_NUMBER (R_CRIS_16, 2) + RELOC_NUMBER (R_CRIS_32, 3) + RELOC_NUMBER (R_CRIS_8_PCREL, 4) + RELOC_NUMBER (R_CRIS_16_PCREL, 5) + RELOC_NUMBER (R_CRIS_32_PCREL, 6) + + RELOC_NUMBER (R_CRIS_GNU_VTINHERIT, 7) + RELOC_NUMBER (R_CRIS_GNU_VTENTRY, 8) + + /* No other relocs must be visible outside the assembler. */ + +END_RELOC_NUMBERS (R_CRIS_max) + +/* User symbols in this file have a leading underscore. */ +#define EF_CRIS_UNDERSCORE 0x00000001 + +#endif /* _ELF_CRIS_H */ diff --git a/contrib/binutils/include/elf/d10v.h b/contrib/binutils/include/elf/d10v.h index 63b79c8..96bfaf2 100644 --- a/contrib/binutils/include/elf/d10v.h +++ b/contrib/binutils/include/elf/d10v.h @@ -1,5 +1,5 @@ /* d10v ELF support for BFD. - Copyright (C) 1998 Free Software Foundation, Inc. + Copyright (C) 1998, 2000 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -33,6 +33,6 @@ START_RELOC_NUMBERS (elf_d10v_reloc_type) RELOC_NUMBER (R_D10V_32, 6) RELOC_NUMBER (R_D10V_GNU_VTINHERIT, 7) RELOC_NUMBER (R_D10V_GNU_VTENTRY, 8) -END_RELOC_NUMBERS +END_RELOC_NUMBERS (R_D10V_max) #endif diff --git a/contrib/binutils/include/elf/d30v.h b/contrib/binutils/include/elf/d30v.h index adbad19..369aa4b 100644 --- a/contrib/binutils/include/elf/d30v.h +++ b/contrib/binutils/include/elf/d30v.h @@ -1,5 +1,5 @@ /* d30v ELF support for BFD. - Copyright (C) 1998 Free Software Foundation, Inc. + Copyright (C) 1998, 2000 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -37,6 +37,6 @@ START_RELOC_NUMBERS (elf_d30v_reloc_type) RELOC_NUMBER (R_D30V_32, 10) RELOC_NUMBER (R_D30V_32_PCREL, 11) RELOC_NUMBER (R_D30V_32_NORMAL, 12) -END_RELOC_NUMBERS +END_RELOC_NUMBERS (R_D30V_max) #endif diff --git a/contrib/binutils/include/elf/fr30.h b/contrib/binutils/include/elf/fr30.h index 223b052..54c1ae6 100644 --- a/contrib/binutils/include/elf/fr30.h +++ b/contrib/binutils/include/elf/fr30.h @@ -1,5 +1,5 @@ /* FR30 ELF support for BFD. - Copyright (C) 1998 Free Software Foundation, Inc. + Copyright (C) 1998, 99, 2000 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -37,7 +37,6 @@ START_RELOC_NUMBERS (elf_fr30_reloc_type) RELOC_NUMBER (R_FR30_12_PCREL, 10) RELOC_NUMBER (R_FR30_GNU_VTINHERIT, 11) RELOC_NUMBER (R_FR30_GNU_VTENTRY, 12) - EMPTY_RELOC (R_FR30_max) -END_RELOC_NUMBERS +END_RELOC_NUMBERS (R_FR30_max) #endif /* _ELF_FR30_H */ diff --git a/contrib/binutils/include/elf/hppa.h b/contrib/binutils/include/elf/hppa.h index 0e45d74..e9ec03a 100644 --- a/contrib/binutils/include/elf/hppa.h +++ b/contrib/binutils/include/elf/hppa.h @@ -1,5 +1,5 @@ /* HPPA ELF support for BFD. - Copyright (C) 1993, 1994, 1999 Free Software Foundation, Inc. + Copyright (C) 1993, 94, 95, 99, 2000 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -102,173 +102,385 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "elf/reloc-macros.h" START_RELOC_NUMBERS (elf_hppa_reloc_type) - RELOC_NUMBER (R_PARISC_NONE, 0) /* No reloc */ - - /* These relocation types do simple base + offset relocations. */ - - RELOC_NUMBER (R_PARISC_DIR32, 1) - RELOC_NUMBER (R_PARISC_DIR21L, 2) - RELOC_NUMBER (R_PARISC_DIR17R, 3) - RELOC_NUMBER (R_PARISC_DIR17F, 4) - RELOC_NUMBER (R_PARISC_DIR14R, 6) - - /* PC-relative relocation types - Typically used for calls. - Note PCREL17C and PCREL17F differ only in overflow handling. - PCREL17C never reports a relocation error. - - When supporting argument relocations, function calls must be - accompanied by parameter relocation information. This information is - carried in the ten high-order bits of the addend field. The remaining - 22 bits of of the addend field are sign-extended to form the Addend. - - Note the code to build argument relocations depends on the - addend being zero. A consequence of this limitation is GAS - can not perform relocation reductions for function symbols. */ - - RELOC_NUMBER (R_PARISC_PCREL32, 9) - RELOC_NUMBER (R_PARISC_PCREL21L, 10) - RELOC_NUMBER (R_PARISC_PCREL17R, 11) - RELOC_NUMBER (R_PARISC_PCREL17F, 12) - RELOC_NUMBER (R_PARISC_PCREL17C, 13) - RELOC_NUMBER (R_PARISC_PCREL14R, 14) - RELOC_NUMBER (R_PARISC_PCREL14F, 15) - - /* DP-relative relocation types. */ - RELOC_NUMBER (R_PARISC_DPREL21L, 18) - RELOC_NUMBER (R_PARISC_DPREL14WR, 19) - RELOC_NUMBER (R_PARISC_DPREL14DR, 20) - RELOC_NUMBER (R_PARISC_DPREL14R, 22) - RELOC_NUMBER (R_PARISC_DPREL14F, 23) - - /* Data linkage table (DLT) relocation types - - SOM DLT_REL fixup requests are used to for static data references - from position-independent code within shared libraries. They are - similar to the GOT relocation types in some SVR4 implementations. */ - - RELOC_NUMBER (R_PARISC_DLTREL21L, 26) - RELOC_NUMBER (R_PARISC_DLTREL14R, 30) - RELOC_NUMBER (R_PARISC_DLTREL14F, 31) - - /* DLT indirect relocation types */ - RELOC_NUMBER (R_PARISC_DLTIND21L, 34) - RELOC_NUMBER (R_PARISC_DLTIND14R, 38) - RELOC_NUMBER (R_PARISC_DLTIND14F, 39) - - /* Base relative relocation types. Ugh. These imply lots of state */ - RELOC_NUMBER (R_PARISC_SETBASE, 40) - RELOC_NUMBER (R_PARISC_SECREL32, 41) - RELOC_NUMBER (R_PARISC_BASEREL21L, 42) - RELOC_NUMBER (R_PARISC_BASEREL17R, 43) - RELOC_NUMBER (R_PARISC_BASEREL17F, 44) - RELOC_NUMBER (R_PARISC_BASEREL14R, 46) - RELOC_NUMBER (R_PARISC_BASEREL14F, 47) - - /* Segment relative relocation types. */ - RELOC_NUMBER (R_PARISC_SEGBASE, 48) - RELOC_NUMBER (R_PARISC_SEGREL32, 49) - - /* Offsets from the PLT. */ - RELOC_NUMBER (R_PARISC_PLTOFF21L, 50) - RELOC_NUMBER (R_PARISC_PLTOFF14R, 54) - RELOC_NUMBER (R_PARISC_PLTOFF14F, 55) - - RELOC_NUMBER (R_PARISC_LTOFF_FPTR32, 57) - RELOC_NUMBER (R_PARISC_LTOFF_FPTR21L, 58) - RELOC_NUMBER (R_PARISC_LTOFF_FPTR14R, 62) - - RELOC_NUMBER (R_PARISC_FPTR64, 64) - - /* Plabel relocation types. */ - RELOC_NUMBER (R_PARISC_PLABEL32, 65) - RELOC_NUMBER (R_PARISC_PLABEL21L, 66) - RELOC_NUMBER (R_PARISC_PLABEL14R, 70) - - /* PCREL relocations. */ - RELOC_NUMBER (R_PARISC_PCREL64, 72) - RELOC_NUMBER (R_PARISC_PCREL22C, 73) - RELOC_NUMBER (R_PARISC_PCREL22F, 74) - RELOC_NUMBER (R_PARISC_PCREL14WR, 75) - RELOC_NUMBER (R_PARISC_PCREL14DR, 76) - RELOC_NUMBER (R_PARISC_PCREL16F, 77) - RELOC_NUMBER (R_PARISC_PCREL16WF, 78) - RELOC_NUMBER (R_PARISC_PCREL16DF, 79) - - - RELOC_NUMBER (R_PARISC_DIR64, 80) - RELOC_NUMBER (R_PARISC_DIR64WR, 81) - RELOC_NUMBER (R_PARISC_DIR64DR, 82) - RELOC_NUMBER (R_PARISC_DIR14WR, 83) - RELOC_NUMBER (R_PARISC_DIR14DR, 84) - RELOC_NUMBER (R_PARISC_DIR16F, 85) - RELOC_NUMBER (R_PARISC_DIR16WF, 86) - RELOC_NUMBER (R_PARISC_DIR16DF, 87) - - RELOC_NUMBER (R_PARISC_GPREL64, 88) - - RELOC_NUMBER (R_PARISC_DLTREL14WR, 91) - RELOC_NUMBER (R_PARISC_DLTREL14DR, 92) - RELOC_NUMBER (R_PARISC_GPREL16F, 93) - RELOC_NUMBER (R_PARISC_GPREL16WF, 94) - RELOC_NUMBER (R_PARISC_GPREL16DF, 95) - - - RELOC_NUMBER (R_PARISC_LTOFF64, 96) - RELOC_NUMBER (R_PARISC_DLTIND14WR, 99) - RELOC_NUMBER (R_PARISC_DLTIND14DR, 100) - RELOC_NUMBER (R_PARISC_LTOFF16F, 101) - RELOC_NUMBER (R_PARISC_LTOFF16WF, 102) - RELOC_NUMBER (R_PARISC_LTOFF16DF, 103) - - RELOC_NUMBER (R_PARISC_SECREL64, 104) - - RELOC_NUMBER (R_PARISC_BASEREL14WR, 107) - RELOC_NUMBER (R_PARISC_BASEREL14DR, 108) - - RELOC_NUMBER (R_PARISC_SEGREL64, 112) - - RELOC_NUMBER (R_PARISC_PLTOFF14WR, 115) - RELOC_NUMBER (R_PARISC_PLTOFF14DR, 116) - RELOC_NUMBER (R_PARISC_PLTOFF16F, 117) - RELOC_NUMBER (R_PARISC_PLTOFF16WF, 118) - RELOC_NUMBER (R_PARISC_PLTOFF16DF, 119) - - RELOC_NUMBER (R_PARISC_LTOFF_FPTR64, 120) - RELOC_NUMBER (R_PARISC_LTOFF_FPTR14WR, 123) - RELOC_NUMBER (R_PARISC_LTOFF_FPTR14DR, 124) - RELOC_NUMBER (R_PARISC_LTOFF_FPTR16F, 125) - RELOC_NUMBER (R_PARISC_LTOFF_FPTR16WF, 126) - RELOC_NUMBER (R_PARISC_LTOFF_FPTR16DF, 127) - - - RELOC_NUMBER (R_PARISC_COPY, 128) - RELOC_NUMBER (R_PARISC_IPLT, 129) - RELOC_NUMBER (R_PARISC_EPLT, 130) - - RELOC_NUMBER (R_PARISC_TPREL32, 153) - RELOC_NUMBER (R_PARISC_TPREL21L, 154) - RELOC_NUMBER (R_PARISC_TPREL14R, 158) - - RELOC_NUMBER (R_PARISC_LTOFF_TP21L, 162) - RELOC_NUMBER (R_PARISC_LTOFF_TP14R, 166) - RELOC_NUMBER (R_PARISC_LTOFF_TP14F, 167) - - RELOC_NUMBER (R_PARISC_TPREL64, 216) - RELOC_NUMBER (R_PARISC_TPREL14WR, 219) - RELOC_NUMBER (R_PARISC_TPREL14DR, 220) - RELOC_NUMBER (R_PARISC_TPREL16F, 221) - RELOC_NUMBER (R_PARISC_TPREL16WF, 222) - RELOC_NUMBER (R_PARISC_TPREL16DF, 223) - - RELOC_NUMBER (R_PARISC_LTOFF_TP64, 224) - RELOC_NUMBER (R_PARISC_LTOFF_TP14WR, 227) - RELOC_NUMBER (R_PARISC_LTOFF_TP14DR, 228) - RELOC_NUMBER (R_PARISC_LTOFF_TP16F, 229) - RELOC_NUMBER (R_PARISC_LTOFF_TP16WF, 230) - RELOC_NUMBER (R_PARISC_LTOFF_TP16DF, 231) - EMPTY_RELOC (R_PARISC_UNIMPLEMENTED) -END_RELOC_NUMBERS +RELOC_NUMBER (R_PARISC_NONE, 0) /* No reloc */ + +/* Data / Inst. Format Relocation Expression */ + +RELOC_NUMBER (R_PARISC_DIR32, 1) +/* 32-bit word symbol + addend */ + +RELOC_NUMBER (R_PARISC_DIR21L, 2) +/* long immediate (7) LR(symbol, addend) */ + +RELOC_NUMBER (R_PARISC_DIR17R, 3) +/* branch external (19) RR(symbol, addend) */ + +RELOC_NUMBER (R_PARISC_DIR17F, 4) +/* branch external (19) symbol + addend */ + +RELOC_NUMBER (R_PARISC_DIR14R, 6) +/* load/store (1) RR(symbol, addend) */ + +RELOC_NUMBER (R_PARISC_DIR14F, 7) +/* load/store (1) symbol, addend */ + +/* PC-relative relocation types + Typically used for calls. + Note PCREL17C and PCREL17F differ only in overflow handling. + PCREL17C never reports a relocation error. + + When supporting argument relocations, function calls must be + accompanied by parameter relocation information. This information is + carried in the ten high-order bits of the addend field. The remaining + 22 bits of of the addend field are sign-extended to form the Addend. + + Note the code to build argument relocations depends on the + addend being zero. A consequence of this limitation is GAS + can not perform relocation reductions for function symbols. */ + +RELOC_NUMBER (R_PARISC_PCREL12F, 8) +/* op & branch (17) symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL32, 9) +/* 32-bit word symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL21L, 10) +/* long immediate (7) L(symbol - PC - 8 + addend) */ + +RELOC_NUMBER (R_PARISC_PCREL17R, 11) +/* branch external (19) R(symbol - PC - 8 + addend) */ + +RELOC_NUMBER (R_PARISC_PCREL17F, 12) +/* branch (20) symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL17C, 13) +/* branch (20) symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL14R, 14) +/* load/store (1) R(symbol - PC - 8 + addend) */ + +RELOC_NUMBER (R_PARISC_PCREL14F, 15) +/* load/store (1) symbol - PC - 8 + addend */ + + +/* DP-relative relocation types. */ +RELOC_NUMBER (R_PARISC_DPREL21L, 18) +/* long immediate (7) LR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_DPREL14WR, 19) +/* load/store mod. comp. (2) RR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_DPREL14DR, 20) +/* load/store doubleword (3) RR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_DPREL14R, 22) +/* load/store (1) RR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_DPREL14F, 23) +/* load/store (1) symbol - GP + addend */ + + +/* Data linkage table (DLT) relocation types + + SOM DLT_REL fixup requests are used to for static data references + from position-independent code within shared libraries. They are + similar to the GOT relocation types in some SVR4 implementations. */ + +RELOC_NUMBER (R_PARISC_DLTREL21L, 26) +/* long immediate (7) LR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_DLTREL14R, 30) +/* load/store (1) RR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_DLTREL14F, 31) +/* load/store (1) symbol - GP + addend */ + + +/* DLT indirect relocation types */ +RELOC_NUMBER (R_PARISC_DLTIND21L, 34) +/* long immediate (7) L(ltoff(symbol + addend)) */ + +RELOC_NUMBER (R_PARISC_DLTIND14R, 38) +/* load/store (1) R(ltoff(symbol + addend)) */ + +RELOC_NUMBER (R_PARISC_DLTIND14F, 39) +/* load/store (1) ltoff(symbol + addend) */ + + +/* Base relative relocation types. Ugh. These imply lots of state */ +RELOC_NUMBER (R_PARISC_SETBASE, 40) +/* none no reloc; base := sym */ + +RELOC_NUMBER (R_PARISC_SECREL32, 41) +/* 32-bit word symbol - SECT + addend */ + +RELOC_NUMBER (R_PARISC_BASEREL21L, 42) +/* long immediate (7) LR(symbol - base, addend) */ + +RELOC_NUMBER (R_PARISC_BASEREL17R, 43) +/* branch external (19) RR(symbol - base, addend) */ + +RELOC_NUMBER (R_PARISC_BASEREL17F, 44) +/* branch external (19) symbol - base + addend */ + +RELOC_NUMBER (R_PARISC_BASEREL14R, 46) +/* load/store (1) RR(symbol - base, addend) */ + +RELOC_NUMBER (R_PARISC_BASEREL14F, 47) +/* load/store (1) symbol - base, addend */ + + +/* Segment relative relocation types. */ +RELOC_NUMBER (R_PARISC_SEGBASE, 48) +/* none no relocation; SB := sym */ + +RELOC_NUMBER (R_PARISC_SEGREL32, 49) +/* 32-bit word symbol - SB + addend */ + + +/* Offsets from the PLT. */ +RELOC_NUMBER (R_PARISC_PLTOFF21L, 50) +/* long immediate (7) LR(pltoff(symbol), addend) */ + +RELOC_NUMBER (R_PARISC_PLTOFF14R, 54) +/* load/store (1) RR(pltoff(symbol), addend) */ + +RELOC_NUMBER (R_PARISC_PLTOFF14F, 55) +/* load/store (1) pltoff(symbol) + addend */ + + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR32, 57) +/* 32-bit word ltoff(fptr(symbol+addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR21L, 58) +/* long immediate (7) L(ltoff(fptr(symbol+addend))) */ + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR14R, 62) +/* load/store (1) R(ltoff(fptr(symbol+addend))) */ + + +RELOC_NUMBER (R_PARISC_FPTR64, 64) +/* 64-bit doubleword fptr(symbol+addend) */ + + +/* Plabel relocation types. */ +RELOC_NUMBER (R_PARISC_PLABEL32, 65) +/* 32-bit word fptr(symbol) */ + +RELOC_NUMBER (R_PARISC_PLABEL21L, 66) +/* long immediate (7) L(fptr(symbol)) */ + +RELOC_NUMBER (R_PARISC_PLABEL14R, 70) +/* load/store (1) R(fptr(symbol)) */ + + +/* PCREL relocations. */ +RELOC_NUMBER (R_PARISC_PCREL64, 72) +/* 64-bit doubleword symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL22C, 73) +/* branch & link (21) symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL22F, 74) +/* branch & link (21) symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL14WR, 75) +/* load/store mod. comp. (2) R(symbol - PC - 8 + addend) */ + +RELOC_NUMBER (R_PARISC_PCREL14DR, 76) +/* load/store doubleword (3) R(symbol - PC - 8 + addend) */ + +RELOC_NUMBER (R_PARISC_PCREL16F, 77) +/* load/store (1) symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL16WF, 78) +/* load/store mod. comp. (2) symbol - PC - 8 + addend */ + +RELOC_NUMBER (R_PARISC_PCREL16DF, 79) +/* load/store doubleword (3) symbol - PC - 8 + addend */ + + +RELOC_NUMBER (R_PARISC_DIR64, 80) +/* 64-bit doubleword symbol + addend */ + +RELOC_NUMBER (R_PARISC_DIR64WR, 81) +/* 64-bit doubleword RR(symbol, addend) */ + +RELOC_NUMBER (R_PARISC_DIR64DR, 82) +/* 64-bit doubleword RR(symbol, addend) */ + +RELOC_NUMBER (R_PARISC_DIR14WR, 83) +/* load/store mod. comp. (2) RR(symbol, addend) */ + +RELOC_NUMBER (R_PARISC_DIR14DR, 84) +/* load/store doubleword (3) RR(symbol, addend) */ + +RELOC_NUMBER (R_PARISC_DIR16F, 85) +/* load/store (1) symbol + addend */ + +RELOC_NUMBER (R_PARISC_DIR16WF, 86) +/* load/store mod. comp. (2) symbol + addend */ + +RELOC_NUMBER (R_PARISC_DIR16DF, 87) +/* load/store doubleword (3) symbol + addend */ + +RELOC_NUMBER (R_PARISC_GPREL64, 88) +/* 64-bit doubleword symbol - GP + addend */ + +RELOC_NUMBER (R_PARISC_DLTREL14WR, 91) +/* load/store mod. comp. (2) RR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_DLTREL14DR, 92) +/* load/store doubleword (3) RR(symbol - GP, addend) */ + +RELOC_NUMBER (R_PARISC_GPREL16F, 93) +/* load/store (1) symbol - GP + addend */ + +RELOC_NUMBER (R_PARISC_GPREL16WF, 94) +/* load/store mod. comp. (2) symbol - GP + addend */ + +RELOC_NUMBER (R_PARISC_GPREL16DF, 95) +/* load/store doubleword (3) symbol - GP + addend */ + + +RELOC_NUMBER (R_PARISC_LTOFF64, 96) +/* 64-bit doubleword ltoff(symbol + addend) */ + +RELOC_NUMBER (R_PARISC_DLTIND14WR, 99) +/* load/store mod. comp. (2) R(ltoff(symbol + addend)) */ + +RELOC_NUMBER (R_PARISC_DLTIND14DR, 100) +/* load/store doubleword (3) R(ltoff(symbol + addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF16F, 101) +/* load/store (1) ltoff(symbol + addend) */ + +RELOC_NUMBER (R_PARISC_LTOFF16WF, 102) +/* load/store mod. comp. (2) ltoff(symbol + addend) */ + +RELOC_NUMBER (R_PARISC_LTOFF16DF, 103) +/* load/store doubleword (3) ltoff(symbol + addend) */ + + +RELOC_NUMBER (R_PARISC_SECREL64, 104) +/* 64-bit doubleword symbol - SECT + addend */ + +RELOC_NUMBER (R_PARISC_BASEREL14WR, 107) +/* load/store mod. comp. (2) RR(symbol - base, addend) */ + +RELOC_NUMBER (R_PARISC_BASEREL14DR, 108) +/* load/store doubleword (3) RR(symbol - base, addend) */ + + +RELOC_NUMBER (R_PARISC_SEGREL64, 112) +/* 64-bit doubleword symbol - SB + addend */ + +RELOC_NUMBER (R_PARISC_PLTOFF14WR, 115) +/* load/store mod. comp. (2) RR(pltoff(symbol), addend) */ + +RELOC_NUMBER (R_PARISC_PLTOFF14DR, 116) +/* load/store doubleword (3) RR(pltoff(symbol), addend) */ + +RELOC_NUMBER (R_PARISC_PLTOFF16F, 117) +/* load/store (1) pltoff(symbol) + addend */ + +RELOC_NUMBER (R_PARISC_PLTOFF16WF, 118) +/* load/store mod. comp. (2) pltoff(symbol) + addend */ + +RELOC_NUMBER (R_PARISC_PLTOFF16DF, 119) +/* load/store doubleword (3) pltoff(symbol) + addend */ + + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR64, 120) +/* 64-bit doubleword ltoff(fptr(symbol+addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR14WR, 123) +/* load/store mod. comp. (2) R(ltoff(fptr(symbol+addend))) */ + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR14DR, 124) +/* load/store doubleword (3) R(ltoff(fptr(symbol+addend))) */ + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR16F, 125) +/* load/store (1) ltoff(fptr(symbol+addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR16WF, 126) +/* load/store mod. comp. (2) ltoff(fptr(symbol+addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_FPTR16DF, 127) +/* load/store doubleword (3) ltoff(fptr(symbol+addend)) */ + + +RELOC_NUMBER (R_PARISC_COPY, 128) +/* data Dynamic relocations only */ + +RELOC_NUMBER (R_PARISC_IPLT, 129) +/* plt */ + +RELOC_NUMBER (R_PARISC_EPLT, 130) +/* plt */ + + +RELOC_NUMBER (R_PARISC_TPREL32, 153) +/* 32-bit word symbol - TP + addend */ + +RELOC_NUMBER (R_PARISC_TPREL21L, 154) +/* long immediate (7) LR(symbol - TP, addend) */ + +RELOC_NUMBER (R_PARISC_TPREL14R, 158) +/* load/store (1) RR(symbol - TP, addend) */ + + +RELOC_NUMBER (R_PARISC_LTOFF_TP21L, 162) +/* long immediate (7) L(ltoff(symbol - TP + addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_TP14R, 166) +/* load/store (1) R(ltoff(symbol - TP + addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_TP14F, 167) +/* load/store (1) ltoff(symbol - TP + addend) */ + + +RELOC_NUMBER (R_PARISC_TPREL64, 216) +/* 64-bit word symbol - TP + addend */ + +RELOC_NUMBER (R_PARISC_TPREL14WR, 219) +/* load/store mod. comp. (2) RR(symbol - TP, addend) */ + +RELOC_NUMBER (R_PARISC_TPREL14DR, 220) +/* load/store doubleword (3) RR(symbol - TP, addend) */ + +RELOC_NUMBER (R_PARISC_TPREL16F, 221) +/* load/store (1) symbol - TP + addend */ + +RELOC_NUMBER (R_PARISC_TPREL16WF, 222) +/* load/store mod. comp. (2) symbol - TP + addend */ + +RELOC_NUMBER (R_PARISC_TPREL16DF, 223) +/* load/store doubleword (3) symbol - TP + addend */ + + +RELOC_NUMBER (R_PARISC_LTOFF_TP64, 224) +/* 64-bit doubleword ltoff(symbol - TP + addend) */ + +RELOC_NUMBER (R_PARISC_LTOFF_TP14WR, 227) +/* load/store mod. comp. (2) R(ltoff(symbol - TP + addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_TP14DR, 228) +/* load/store doubleword (3) R(ltoff(symbol - TP + addend)) */ + +RELOC_NUMBER (R_PARISC_LTOFF_TP16F, 229) +/* load/store (1) ltoff(symbol - TP + addend) */ + +RELOC_NUMBER (R_PARISC_LTOFF_TP16WF, 230) +/* load/store mod. comp. (2) ltoff(symbol - TP + addend) */ + +RELOC_NUMBER (R_PARISC_LTOFF_TP16DF, 231) +/* load/store doubleword (3) ltoff(symbol - TP + addend) */ + +RELOC_NUMBER (R_PARISC_GNU_VTENTRY, 232) +RELOC_NUMBER (R_PARISC_GNU_VTINHERIT, 233) + +END_RELOC_NUMBERS (R_PARISC_UNIMPLEMENTED) #ifndef RELOC_MACROS_GEN_FUNC typedef enum elf_hppa_reloc_type elf_hppa_reloc_type; @@ -288,19 +500,22 @@ typedef enum elf_hppa_reloc_type elf_hppa_reloc_type; /* Processor specific dynamic array tags. */ -#define DT_HP_LOAD_MAP (DT_LOOS + 0x0) -#define DT_HP_DLD_FLAGS (DT_LOOS + 0x1) -#define DT_HP_DLD_HOOK (DT_LOOS + 0x2) -#define DT_HP_UX10_INIT (DT_LOOS + 0x3) -#define DT_HP_UX10_INITSZ (DT_LOOS + 0x4) -#define DT_HP_PREINIT (DT_LOOS + 0x5) -#define DT_HP_PREINITSZ (DT_LOOS + 0x6) -#define DT_HP_NEEDED (DT_LOOS + 0x7) -#define DT_HP_TIME_STAMP (DT_LOOS + 0x8) -#define DT_HP_CHECKSUM (DT_LOOS + 0x9) -#define DT_HP_GST_SIZE (DT_LOOS + 0xa) -#define DT_HP_GST_VERSION (DT_LOOS + 0xb) -#define DT_HP_GST_HASHVAL (DT_LOOS + 0xc) +/* Arggh. HP's tools define these symbols based on the + old value of DT_LOOS. So we must do the same to be + compatible. */ +#define DT_HP_LOAD_MAP (OLD_DT_LOOS + 0x0) +#define DT_HP_DLD_FLAGS (OLD_DT_LOOS + 0x1) +#define DT_HP_DLD_HOOK (OLD_DT_LOOS + 0x2) +#define DT_HP_UX10_INIT (OLD_DT_LOOS + 0x3) +#define DT_HP_UX10_INITSZ (OLD_DT_LOOS + 0x4) +#define DT_HP_PREINIT (OLD_DT_LOOS + 0x5) +#define DT_HP_PREINITSZ (OLD_DT_LOOS + 0x6) +#define DT_HP_NEEDED (OLD_DT_LOOS + 0x7) +#define DT_HP_TIME_STAMP (OLD_DT_LOOS + 0x8) +#define DT_HP_CHECKSUM (OLD_DT_LOOS + 0x9) +#define DT_HP_GST_SIZE (OLD_DT_LOOS + 0xa) +#define DT_HP_GST_VERSION (OLD_DT_LOOS + 0xb) +#define DT_HP_GST_HASHVAL (OLD_DT_LOOS + 0xc) /* Values for DT_HP_DLD_FLAGS. */ #define DT_HP_DEBUG_PRIVATE 0x0001 /* Map text private */ diff --git a/contrib/binutils/include/elf/i370.h b/contrib/binutils/include/elf/i370.h index 9c021f0..b4e21aa 100644 --- a/contrib/binutils/include/elf/i370.h +++ b/contrib/binutils/include/elf/i370.h @@ -1,5 +1,5 @@ /* i370 ELF support for BFD. - Copyright (C) 1995, 2000 Free Software Foundation, Inc. + Copyright (C) 2000 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. diff --git a/contrib/binutils/include/elf/i386.h b/contrib/binutils/include/elf/i386.h index 0586661..c91f4be 100644 --- a/contrib/binutils/include/elf/i386.h +++ b/contrib/binutils/include/elf/i386.h @@ -1,5 +1,5 @@ /* ix86 ELF support for BFD. - Copyright (C) 1998 Free Software Foundation, Inc. + Copyright (C) 1998, 99, 2000 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -40,10 +40,9 @@ START_RELOC_NUMBERS (elf_i386_reloc_type) RELOC_NUMBER (R_386_PC16, 21) RELOC_NUMBER (R_386_8, 22) RELOC_NUMBER (R_386_PC8, 23) - RELOC_NUMBER (R_386_max, 24) /* These are GNU extensions to enable C++ vtable garbage collection. */ RELOC_NUMBER (R_386_GNU_VTINHERIT, 250) RELOC_NUMBER (R_386_GNU_VTENTRY, 251) -END_RELOC_NUMBERS +END_RELOC_NUMBERS (R_386_max) #endif diff --git a/contrib/binutils/include/elf/i860.h b/contrib/binutils/include/elf/i860.h new file mode 100644 index 0000000..08b2ff5 --- /dev/null +++ b/contrib/binutils/include/elf/i860.h @@ -0,0 +1,66 @@ +/* i860 ELF support for BFD. + Copyright (C) 2000 Free Software Foundation, Inc. + + Contributed by Jason Eckhardt <jle@cygnus.com>. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_I860_H +#define _ELF_I860_H + +/* Note: i860 ELF is defined to use only RELA relocations. */ + +#include "elf/reloc-macros.h" + +START_RELOC_NUMBERS (elf_i860_reloc_type) + RELOC_NUMBER (R_860_NONE, 0x00) /* No reloc */ + RELOC_NUMBER (R_860_32, 0x01) /* S+A */ + RELOC_NUMBER (R_860_COPY, 0x02) /* No calculation */ + RELOC_NUMBER (R_860_GLOB_DAT, 0x03) /* S, Create GOT entry */ + RELOC_NUMBER (R_860_JUMP_SLOT, 0x04) /* S+A, Create PLT entry */ + RELOC_NUMBER (R_860_RELATIVE, 0x05) /* B+A, Adj by program base */ + RELOC_NUMBER (R_860_PC26, 0x30) /* (S+A-P) >> 2 */ + RELOC_NUMBER (R_860_PLT26, 0x31) /* (L+A-P) >> 2 */ + RELOC_NUMBER (R_860_PC16, 0x32) /* (S+A-P) >> 2 */ + RELOC_NUMBER (R_860_LOW0, 0x40) /* S+A */ + RELOC_NUMBER (R_860_SPLIT0, 0x42) /* S+A */ + RELOC_NUMBER (R_860_LOW1, 0x44) /* S+A */ + RELOC_NUMBER (R_860_SPLIT1, 0x46) /* S+A */ + RELOC_NUMBER (R_860_LOW2, 0x48) /* S+A */ + RELOC_NUMBER (R_860_SPLIT2, 0x4A) /* S+A */ + RELOC_NUMBER (R_860_LOW3, 0x4C) /* S+A */ + RELOC_NUMBER (R_860_LOGOT0, 0x50) /* G */ + RELOC_NUMBER (R_860_SPGOT0, 0x52) /* G */ + RELOC_NUMBER (R_860_LOGOT1, 0x54) /* G */ + RELOC_NUMBER (R_860_SPGOT1, 0x56) /* G */ + RELOC_NUMBER (R_860_LOGOTOFF0, 0x60) /* O */ + RELOC_NUMBER (R_860_SPGOTOFF0, 0x62) /* O */ + RELOC_NUMBER (R_860_LOGOTOFF1, 0x64) /* O */ + RELOC_NUMBER (R_860_SPGOTOFF1, 0x66) /* O */ + RELOC_NUMBER (R_860_LOGOTOFF2, 0x68) /* O */ + RELOC_NUMBER (R_860_LOGOTOFF3, 0x6C) /* O */ + RELOC_NUMBER (R_860_LOPC, 0x70) /* (S+A-P) >> 2 */ + RELOC_NUMBER (R_860_HIGHADJ, 0x80) /* hiadj(S+A) */ + RELOC_NUMBER (R_860_HAGOT, 0x90) /* hiadj(G) */ + RELOC_NUMBER (R_860_HAGOTOFF, 0xA0) /* hiadj(O) */ + RELOC_NUMBER (R_860_HAPC, 0xB0) /* hiadj((S+A-P) >> 2) */ + RELOC_NUMBER (R_860_HIGH, 0xC0) /* (S+A) >> 16 */ + RELOC_NUMBER (R_860_HIGOT, 0xD0) /* G >> 16 */ + RELOC_NUMBER (R_860_HIGOTOFF, 0xE0) /* O */ +END_RELOC_NUMBERS (R_860_max) + +#endif diff --git a/contrib/binutils/include/elf/i960.h b/contrib/binutils/include/elf/i960.h index 3e60289..cbf67d7 100644 --- a/contrib/binutils/include/elf/i960.h +++ b/contrib/binutils/include/elf/i960.h @@ -1,5 +1,5 @@ /* Intel 960 ELF support for BFD. - Copyright (C) 1999 Free Software Foundation, Inc. + Copyright (C) 1999, 2000 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -32,7 +32,6 @@ START_RELOC_NUMBERS (elf_i960_reloc_type) RELOC_NUMBER (R_960_OPTCALL, 5) RELOC_NUMBER (R_960_OPTCALLX, 6) RELOC_NUMBER (R_960_OPTCALLXA, 7) - EMPTY_RELOC (R_960_max) -END_RELOC_NUMBERS +END_RELOC_NUMBERS (R_960_max) #endif /* _ELF_I960_H */ diff --git a/contrib/binutils/include/elf/ia64.h b/contrib/binutils/include/elf/ia64.h new file mode 100644 index 0000000..3b18288 --- /dev/null +++ b/contrib/binutils/include/elf/ia64.h @@ -0,0 +1,190 @@ +/* IA-64 ELF support for BFD. + Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang <davidm@hpl.hp.com> + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +#ifndef _ELF_IA64_H +#define _ELF_IA64_H + +/* Bits in the e_flags field of the Elf64_Ehdr: */ + +#define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */ +#define EF_IA_64_ARCH 0xff000000 /* arch. version mask */ + +/* ??? These four definitions are not part of the SVR4 ABI. + They were present in David's initial code drop, so it is probable + that they are used by HP/UX. */ +#define EF_IA_64_TRAPNIL (1 << 0) /* trap NIL pointer dereferences */ +#define EF_IA_64_EXT (1 << 2) /* program uses arch. extensions */ +#define EF_IA_64_BE (1 << 3) /* PSR BE bit set (big-endian) */ +#define EFA_IA_64_EAS2_3 0x23000000 /* ia64 EAS 2.3 */ + +#define EF_IA_64_ABI64 (1 << 4) /* 64-bit ABI */ +/* Not used yet. */ +#define EF_IA_64_REDUCEDFP (1 << 5) /* Only FP6-FP11 used. */ +#define EF_IA_64_CONS_GP (1 << 6) /* gp as program wide constant. */ +#define EF_IA_64_NOFUNCDESC_CONS_GP (1 << 7) /* And no function descriptors. */ +/* Not used yet. */ +#define EF_IA_64_ABSOLUTE (1 << 8) /* Load at absolute addresses. */ + +#define ELF_STRING_ia64_archext ".IA_64.archext" +#define ELF_STRING_ia64_pltoff ".IA_64.pltoff" +#define ELF_STRING_ia64_unwind ".IA_64.unwind" +#define ELF_STRING_ia64_unwind_info ".IA_64.unwind_info" + +/* Bits in the sh_flags field of Elf64_Shdr: */ + +#define SHF_IA_64_SHORT 0x10000000 /* section near gp */ +#define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */ + +/* Possible values for sh_type in Elf64_Shdr: */ + +#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */ +#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */ + +/* Bits in the p_flags field of Elf64_Phdr: */ + +#define PF_IA_64_NORECOV 0x80000000 + +/* Possible values for p_type in Elf64_Phdr: */ + +#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */ +#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */ + +/* Possible values for d_tag in Elf64_Dyn: */ + +#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) + +/* ia64-specific relocation types: */ + +/* Relocs apply to specific instructions within a bundle. The least + significant 2 bits of the address indicate which instruction in the + bundle the reloc refers to (0=first slot, 1=second slow, 2=third + slot, 3=undefined) and the remaining bits give the address of the + bundle (16 byte aligned). + + The top 5 bits of the reloc code specifies the expression type, the + low 3 bits the format of the data word being relocated. */ + +#include "elf/reloc-macros.h" + +START_RELOC_NUMBERS (elf_ia64_reloc_type) + RELOC_NUMBER (R_IA64_NONE, 0x00) /* none */ + + RELOC_NUMBER (R_IA64_IMM14, 0x21) /* symbol + addend, add imm14 */ + RELOC_NUMBER (R_IA64_IMM22, 0x22) /* symbol + addend, add imm22 */ + RELOC_NUMBER (R_IA64_IMM64, 0x23) /* symbol + addend, mov imm64 */ + RELOC_NUMBER (R_IA64_DIR32MSB, 0x24) /* symbol + addend, data4 MSB */ + RELOC_NUMBER (R_IA64_DIR32LSB, 0x25) /* symbol + addend, data4 LSB */ + RELOC_NUMBER (R_IA64_DIR64MSB, 0x26) /* symbol + addend, data8 MSB */ + RELOC_NUMBER (R_IA64_DIR64LSB, 0x27) /* symbol + addend, data8 LSB */ + + RELOC_NUMBER (R_IA64_GPREL22, 0x2a) /* @gprel(sym+add), add imm22 */ + RELOC_NUMBER (R_IA64_GPREL64I, 0x2b) /* @gprel(sym+add), mov imm64 */ + RELOC_NUMBER (R_IA64_GPREL32MSB, 0x2c) /* @gprel(sym+add), data4 MSB */ + RELOC_NUMBER (R_IA64_GPREL32LSB, 0x2d) /* @gprel(sym+add), data4 LSB */ + RELOC_NUMBER (R_IA64_GPREL64MSB, 0x2e) /* @gprel(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_GPREL64LSB, 0x2f) /* @gprel(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_LTOFF22, 0x32) /* @ltoff(sym+add), add imm22 */ + RELOC_NUMBER (R_IA64_LTOFF64I, 0x33) /* @ltoff(sym+add), mov imm64 */ + + RELOC_NUMBER (R_IA64_PLTOFF22, 0x3a) /* @pltoff(sym+add), add imm22 */ + RELOC_NUMBER (R_IA64_PLTOFF64I, 0x3b) /* @pltoff(sym+add), mov imm64 */ + RELOC_NUMBER (R_IA64_PLTOFF64MSB, 0x3e) /* @pltoff(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_PLTOFF64LSB, 0x3f) /* @pltoff(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_FPTR64I, 0x43) /* @fptr(sym+add), mov imm64 */ + RELOC_NUMBER (R_IA64_FPTR32MSB, 0x44) /* @fptr(sym+add), data4 MSB */ + RELOC_NUMBER (R_IA64_FPTR32LSB, 0x45) /* @fptr(sym+add), data4 LSB */ + RELOC_NUMBER (R_IA64_FPTR64MSB, 0x46) /* @fptr(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_FPTR64LSB, 0x47) /* @fptr(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_PCREL60B, 0x48) /* @pcrel(sym+add), brl */ + RELOC_NUMBER (R_IA64_PCREL21B, 0x49) /* @pcrel(sym+add), ptb, call */ + RELOC_NUMBER (R_IA64_PCREL21M, 0x4a) /* @pcrel(sym+add), chk.s */ + RELOC_NUMBER (R_IA64_PCREL21F, 0x4b) /* @pcrel(sym+add), fchkf */ + RELOC_NUMBER (R_IA64_PCREL32MSB, 0x4c) /* @pcrel(sym+add), data4 MSB */ + RELOC_NUMBER (R_IA64_PCREL32LSB, 0x4d) /* @pcrel(sym+add), data4 LSB */ + RELOC_NUMBER (R_IA64_PCREL64MSB, 0x4e) /* @pcrel(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_PCREL64LSB, 0x4f) /* @pcrel(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_LTOFF_FPTR22, 0x52) /* @ltoff(@fptr(s+a)), imm22 */ + RELOC_NUMBER (R_IA64_LTOFF_FPTR64I, 0x53) /* @ltoff(@fptr(s+a)), imm64 */ + RELOC_NUMBER (R_IA64_LTOFF_FPTR32MSB, 0x54) /* @ltoff(@fptr(s+a)), 4 MSB */ + RELOC_NUMBER (R_IA64_LTOFF_FPTR32LSB, 0x55) /* @ltoff(@fptr(s+a)), 4 LSB */ + RELOC_NUMBER (R_IA64_LTOFF_FPTR64MSB, 0x56) /* @ltoff(@fptr(s+a)), 8 MSB */ + RELOC_NUMBER (R_IA64_LTOFF_FPTR64LSB, 0x57) /* @ltoff(@fptr(s+a)), 8 LSB */ + + RELOC_NUMBER (R_IA64_SEGREL32MSB, 0x5c) /* @segrel(sym+add), data4 MSB */ + RELOC_NUMBER (R_IA64_SEGREL32LSB, 0x5d) /* @segrel(sym+add), data4 LSB */ + RELOC_NUMBER (R_IA64_SEGREL64MSB, 0x5e) /* @segrel(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_SEGREL64LSB, 0x5f) /* @segrel(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_SECREL32MSB, 0x64) /* @secrel(sym+add), data4 MSB */ + RELOC_NUMBER (R_IA64_SECREL32LSB, 0x65) /* @secrel(sym+add), data4 LSB */ + RELOC_NUMBER (R_IA64_SECREL64MSB, 0x66) /* @secrel(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_SECREL64LSB, 0x67) /* @secrel(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_REL32MSB, 0x6c) /* data 4 + REL */ + RELOC_NUMBER (R_IA64_REL32LSB, 0x6d) /* data 4 + REL */ + RELOC_NUMBER (R_IA64_REL64MSB, 0x6e) /* data 8 + REL */ + RELOC_NUMBER (R_IA64_REL64LSB, 0x6f) /* data 8 + REL */ + + RELOC_NUMBER (R_IA64_LTV32MSB, 0x74) /* symbol + addend, data4 MSB */ + RELOC_NUMBER (R_IA64_LTV32LSB, 0x75) /* symbol + addend, data4 LSB */ + RELOC_NUMBER (R_IA64_LTV64MSB, 0x76) /* symbol + addend, data8 MSB */ + RELOC_NUMBER (R_IA64_LTV64LSB, 0x77) /* symbol + addend, data8 LSB */ + + RELOC_NUMBER (R_IA64_PCREL21BI, 0x79) /* @pcrel(sym+add), ptb, call */ + RELOC_NUMBER (R_IA64_PCREL22, 0x7a) /* @pcrel(sym+add), imm22 */ + RELOC_NUMBER (R_IA64_PCREL64I, 0x7b) /* @pcrel(sym+add), imm64 */ + + RELOC_NUMBER (R_IA64_IPLTMSB, 0x80) /* dynamic reloc, imported PLT, MSB */ + RELOC_NUMBER (R_IA64_IPLTLSB, 0x81) /* dynamic reloc, imported PLT, LSB */ + RELOC_NUMBER (R_IA64_COPY, 0x84) /* dynamic reloc, data copy */ + RELOC_NUMBER (R_IA64_LTOFF22X, 0x86) /* LTOFF22, relaxable. */ + RELOC_NUMBER (R_IA64_LDXMOV, 0x87) /* Use of LTOFF22X. */ + + RELOC_NUMBER (R_IA64_TPREL14, 0x91) /* @tprel(sym+add), add imm14 */ + RELOC_NUMBER (R_IA64_TPREL22, 0x92) /* @tprel(sym+add), add imm22 */ + RELOC_NUMBER (R_IA64_TPREL64I, 0x93) /* @tprel(sym+add), add imm64 */ + RELOC_NUMBER (R_IA64_TPREL64MSB, 0x96) /* @tprel(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_TPREL64LSB, 0x97) /* @tprel(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_LTOFF_TP22, 0x9a) /* @ltoff(@tprel(s+a)), add imm22 */ + + RELOC_NUMBER (R_IA64_DTPMOD64MSB, 0xa6) /* @dtpmod(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_DTPMOD64LSB, 0xa7) /* @dtpmod(sym+add), data8 LSB */ + RELOC_NUMBER (R_IA64_LTOFF_DTPMOD22, 0xaa) /* @ltoff(@dtpmod(s+a)), imm22 */ + + RELOC_NUMBER (R_IA64_DTPREL14, 0xb1) /* @dtprel(sym+add), imm14 */ + RELOC_NUMBER (R_IA64_DTPREL22, 0xb2) /* @dtprel(sym+add), imm22 */ + RELOC_NUMBER (R_IA64_DTPREL64I, 0xb3) /* @dtprel(sym+add), imm64 */ + RELOC_NUMBER (R_IA64_DTPREL32MSB, 0xb4) /* @dtprel(sym+add), data4 MSB */ + RELOC_NUMBER (R_IA64_DTPREL32LSB, 0xb5) /* @dtprel(sym+add), data4 LSB */ + RELOC_NUMBER (R_IA64_DTPREL64MSB, 0xb6) /* @dtprel(sym+add), data8 MSB */ + RELOC_NUMBER (R_IA64_DTPREL64LSB, 0xb7) /* @dtprel(sym+add), data8 LSB */ + + RELOC_NUMBER (R_IA64_LTOFF_DTPREL22, 0xba) /* @ltoff(@dtprel(s+a)), imm22 */ + + FAKE_RELOC (R_IA64_MAX_RELOC_CODE, 0xba) +END_RELOC_NUMBERS (R_IA64_max) + +#endif /* _ELF_IA64_H */ diff --git a/contrib/binutils/include/elf/internal.h b/contrib/binutils/include/elf/internal.h index a9b81a07..6ca316b 100644 --- a/contrib/binutils/include/elf/internal.h +++ b/contrib/binutils/include/elf/internal.h @@ -1,5 +1,6 @@ /* ELF support for BFD. - Copyright (C) 1991, 92, 93, 94, 95, 97, 1998 Free Software Foundation, Inc. + Copyright (C) 1991, 92, 93, 94, 95, 97, 98, 2000 + Free Software Foundation, Inc. Written by Fred Fish @ Cygnus Support, from information published in "UNIX System V Release 4, Programmers Guide: ANSI C and @@ -112,7 +113,7 @@ struct elf_internal_sym { bfd_vma st_size; /* Associated symbol size */ unsigned long st_name; /* Symbol name, index in string tbl */ unsigned char st_info; /* Type and binding attributes */ - unsigned char st_other; /* No defined meaning, 0 */ + unsigned char st_other; /* Visibilty, and target specific */ unsigned short st_shndx; /* Associated section index */ }; diff --git a/contrib/binutils/include/elf/m32r.h b/contrib/binutils/include/elf/m32r.h index a12ae16..9b6c4e9 100644 --- a/contrib/binutils/include/elf/m32r.h +++ b/contrib/binutils/include/elf/m32r.h @@ -1,5 +1,5 @@ /* M32R ELF support for BFD. - Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. + Copyright (C) 1996, 97, 98, 99, 2000 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -37,8 +37,7 @@ START_RELOC_NUMBERS (elf_m32r_reloc_type) RELOC_NUMBER (R_M32R_SDA16, 10) RELOC_NUMBER (R_M32R_GNU_VTINHERIT, 11) RELOC_NUMBER (R_M32R_GNU_VTENTRY, 12) - EMPTY_RELOC (R_M32R_max) -END_RELOC_NUMBERS +END_RELOC_NUMBERS (R_M32R_max) /* Processor specific section indices. These sections do not actually exist. Symbols with a st_shndx field corresponding to one of these diff --git a/contrib/binutils/include/elf/m68hc11.h b/contrib/binutils/include/elf/m68hc11.h new file mode 100644 index 0000000..30e0556 --- /dev/null +++ b/contrib/binutils/include/elf/m68hc11.h @@ -0,0 +1,42 @@ +/* m68hc11 & m68hc12 ELF support for BFD. + Copyright (C) 1999, 2000 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_M68HC11_H +#define _ELF_M68HC11_H + +#include "elf/reloc-macros.h" + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_m68hc11_reloc_type) + RELOC_NUMBER (R_M68HC11_NONE, 0) + RELOC_NUMBER (R_M68HC11_8, 1) + RELOC_NUMBER (R_M68HC11_HI8, 2) + RELOC_NUMBER (R_M68HC11_LO8, 3) + RELOC_NUMBER (R_M68HC11_PCREL_8, 4) + RELOC_NUMBER (R_M68HC11_16, 5) + RELOC_NUMBER (R_M68HC11_32, 6) + RELOC_NUMBER (R_M68HC11_3B, 7) + RELOC_NUMBER (R_M68HC11_PCREL_16, 8) + + /* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_M68HC11_GNU_VTINHERIT, 9) + RELOC_NUMBER (R_M68HC11_GNU_VTENTRY, 10) +END_RELOC_NUMBERS (R_M68HC11_max) + +#endif diff --git a/contrib/binutils/include/elf/m68k.h b/contrib/binutils/include/elf/m68k.h index e2d51ef..a6aab10 100644 --- a/contrib/binutils/include/elf/m68k.h +++ b/contrib/binutils/include/elf/m68k.h @@ -1,5 +1,5 @@ /* MC68k ELF support for BFD. - Copyright (C) 1998 Free Software Foundation, Inc. + Copyright (C) 1998, 99, 2000 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -50,8 +50,7 @@ START_RELOC_NUMBERS (elf_m68k_reloc_type) /* These are GNU extensions to enable C++ vtable garbage collection. */ RELOC_NUMBER (R_68K_GNU_VTINHERIT, 23) RELOC_NUMBER (R_68K_GNU_VTENTRY, 24) - EMPTY_RELOC (R_68K_max) -END_RELOC_NUMBERS +END_RELOC_NUMBERS (R_68K_max) #define EF_CPU32 0x00810000 diff --git a/contrib/binutils/include/elf/mcore.h b/contrib/binutils/include/elf/mcore.h index 62a88c9..f97a682 100644 --- a/contrib/binutils/include/elf/mcore.h +++ b/contrib/binutils/include/elf/mcore.h @@ -1,5 +1,5 @@ /* Motorola MCore support for BFD. - Copyright (C) 1995, 1999 Free Software Foundation, Inc. + Copyright (C) 1995, 99, 2000 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -38,8 +38,7 @@ START_RELOC_NUMBERS (elf_mcore_reloc_type) RELOC_NUMBER (R_MCORE_COPY, 10) RELOC_NUMBER (R_MCORE_GLOB_DAT, 11) RELOC_NUMBER (R_MCORE_JUMP_SLOT, 12) - EMPTY_RELOC (R_MCORE_max) -END_RELOC_NUMBERS +END_RELOC_NUMBERS (R_MCORE_max) /* Section Attributes. */ #define SHF_MCORE_NOREAD 0x80000000 diff --git a/contrib/binutils/include/elf/mips.h b/contrib/binutils/include/elf/mips.h index 1e2a9f9..4446512 100644 --- a/contrib/binutils/include/elf/mips.h +++ b/contrib/binutils/include/elf/mips.h @@ -1,5 +1,6 @@ /* MIPS ELF support for BFD. - Copyright (C) 1993, 1994, 1995, 1996, 1998 Free Software Foundation, Inc. + Copyright (C) 1993, 94, 95, 96, 97, 98, 99, 2000 + Free Software Foundation, Inc. By Ian Lance Taylor, Cygnus Support, <ian@cygnus.com>, from information in the System V Application Binary Interface, MIPS @@ -84,7 +85,7 @@ START_RELOC_NUMBERS (elf_mips_reloc_type) /* These are GNU extensions to enable C++ vtable garbage collection. */ RELOC_NUMBER (R_MIPS_GNU_VTINHERIT, 253) RELOC_NUMBER (R_MIPS_GNU_VTENTRY, 254) -END_RELOC_NUMBERS +END_RELOC_NUMBERS (R_MIPS_maxext) /* Processor specific flags for the ELF header e_flags field. */ @@ -120,6 +121,15 @@ END_RELOC_NUMBERS /* -mips4 code. */ #define E_MIPS_ARCH_4 0x30000000 +/* -mips5 code. */ +#define E_MIPS_ARCH_5 0x40000000 + +/* -mips32 code. */ +#define E_MIPS_ARCH_32 0x50000000 + +/* -mips64 code. */ +#define E_MIPS_ARCH_64 0x60000000 + /* The ABI of the file. Also see EF_MIPS_ABI2 above. */ #define EF_MIPS_ABI 0x0000F000 @@ -152,7 +162,8 @@ END_RELOC_NUMBERS #define E_MIPS_MACH_4100 0x00830000 #define E_MIPS_MACH_4650 0x00850000 #define E_MIPS_MACH_4111 0x00880000 - +#define E_MIPS_MACH_MIPS32_4K 0x00890000 +#define E_MIPS_MACH_SB1 0x008a0000 /* Processor specific section indices. These sections do not actually exist. Symbols with a st_shndx field corresponding to one of these diff --git a/contrib/binutils/include/elf/mn10200.h b/contrib/binutils/include/elf/mn10200.h index 5e29e0a..1a14ee7 100644 --- a/contrib/binutils/include/elf/mn10200.h +++ b/contrib/binutils/include/elf/mn10200.h @@ -1,5 +1,5 @@ /* MN10200 ELF support for BFD. - Copyright (C) 1998 Free Software Foundation, Inc. + Copyright (C) 1998, 2000 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -34,6 +34,6 @@ START_RELOC_NUMBERS (elf_mn10200_reloc_type) RELOC_NUMBER (R_MN10200_PCREL8, 5) RELOC_NUMBER (R_MN10200_PCREL16, 6) RELOC_NUMBER (R_MN10200_PCREL24, 7) -END_RELOC_NUMBERS +END_RELOC_NUMBERS (R_MN10200_max) #endif /* _ELF_MN10200_H */ diff --git a/contrib/binutils/include/elf/mn10300.h b/contrib/binutils/include/elf/mn10300.h index 1b90a13..74f2da8 100644 --- a/contrib/binutils/include/elf/mn10300.h +++ b/contrib/binutils/include/elf/mn10300.h @@ -1,5 +1,5 @@ /* MN10300 ELF support for BFD. - Copyright (C) 1998 Free Software Foundation, Inc. + Copyright (C) 1998, 99, 2000 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -36,8 +36,7 @@ START_RELOC_NUMBERS (elf_mn10300_reloc_type) RELOC_NUMBER (R_MN10300_GNU_VTINHERIT, 7) RELOC_NUMBER (R_MN10300_GNU_VTENTRY, 8) RELOC_NUMBER (R_MN10300_24, 9) - EMPTY_RELOC (R_MN10300_MAX) -END_RELOC_NUMBERS +END_RELOC_NUMBERS (R_MN10300_MAX) /* Machine variant if we know it. This field was invented at Cygnus, but it is hoped that other vendors will adopt it. If some standard diff --git a/contrib/binutils/include/elf/pj.h b/contrib/binutils/include/elf/pj.h index 6bb8306..7690ea6 100644 --- a/contrib/binutils/include/elf/pj.h +++ b/contrib/binutils/include/elf/pj.h @@ -1,5 +1,5 @@ /* picoJava ELF support for BFD. - Copyright (C) 1999 Free Software Foundation, Inc. + Copyright (C) 1999, 2000 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -35,8 +35,7 @@ START_RELOC_NUMBERS (elf_pj_reloc_type) RELOC_NUMBER (R_PJ_CODE_HI16, 14) RELOC_NUMBER (R_PJ_GNU_VTINHERIT, 15) RELOC_NUMBER (R_PJ_GNU_VTENTRY, 16) - EMPTY_RELOC (R_PJ_max) -END_RELOC_NUMBERS +END_RELOC_NUMBERS (R_PJ_max) #define EF_PICOJAVA_ARCH 0x0000000f #define EF_PICOJAVA_NEWCALLS 0x00000010 diff --git a/contrib/binutils/include/elf/ppc.h b/contrib/binutils/include/elf/ppc.h index b3116d8..f53bacd 100644 --- a/contrib/binutils/include/elf/ppc.h +++ b/contrib/binutils/include/elf/ppc.h @@ -1,5 +1,5 @@ /* PPC ELF support for BFD. - Copyright (C) 1995, 1998 Free Software Foundation, Inc. + Copyright (C) 1995, 96, 98, 2000 Free Software Foundation, Inc. By Michael Meissner, Cygnus Support, <meissner@cygnus.com>, from information in the System V Application Binary Interface, PowerPC Processor Supplement @@ -96,19 +96,17 @@ START_RELOC_NUMBERS (elf_ppc_reloc_type) that may still be in object files. */ RELOC_NUMBER (R_PPC_TOC16, 255) - EMPTY_RELOC (R_PPC_max) -END_RELOC_NUMBERS +END_RELOC_NUMBERS (R_PPC_max) /* Processor specific flags for the ELF header e_flags field. */ -#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ +#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag. */ - /* CYGNUS local bits below */ -#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag */ -#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib flag */ +#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag. */ +#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib flag. */ -/* Processor specific section headers, sh_type field */ +/* Processor specific section headers, sh_type field. */ #define SHT_ORDERED SHT_HIPROC /* Link editor is to sort the \ entries in this section \ @@ -116,7 +114,7 @@ END_RELOC_NUMBERS specified in the associated \ symbol table entry. */ -/* Processor specific section flags, sh_flags field */ +/* Processor specific section flags, sh_flags field. */ #define SHF_EXCLUDE 0x80000000 /* Link editor is to exclude \ this section from executable \ diff --git a/contrib/binutils/include/elf/reloc-macros.h b/contrib/binutils/include/elf/reloc-macros.h index 42174ca..df5e0e3 100644 --- a/contrib/binutils/include/elf/reloc-macros.h +++ b/contrib/binutils/include/elf/reloc-macros.h @@ -1,5 +1,5 @@ /* Generic relocation support for BFD. - Copyright (C) 1998 Free Software Foundation, Inc. + Copyright (C) 1998, 99, 2000 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -27,20 +27,20 @@ START_RELOC_NUMBERS (foo) RELOC_NUMBER (R_foo_NONE, 0) RELOC_NUMBER (R_foo_32, 1) - FAKE_RELOC (R_foo_illegal, 2) - EMPTY_RELOC (R_foo_max) - END_RELOC_NUMBERS + EMPTY_RELOC (R_foo_good) + FAKE_RELOC (R_foo_illegal, 9) + END_RELOC_NUMBERS (R_foo_count) Then the following will be produced by default (ie if RELOC_MACROS_GEN_FUNC is *not* defined). enum foo { - foo = -1, R_foo_NONE = 0, R_foo_32 = 1, - R_foo_illegal = 2, - R_foo_max + R_foo_good, + R_foo_illegal = 9, + R_foo_count }; If RELOC_MACROS_GEN_FUNC *is* defined, then instead the @@ -59,7 +59,7 @@ } } */ - + #ifndef _RELOC_MACROS_H #define _RELOC_MACROS_H @@ -78,16 +78,16 @@ name (rtype) \ switch (rtype) \ { -#ifdef __STDC__ +#if defined (__STDC__) || defined (ALMOST_STDC) #define RELOC_NUMBER(name, number) case number : return #name ; #else #define RELOC_NUMBER(name, number) case number : return "name" ; #endif -#define FAKE_RELOC(name, number) +#define FAKE_RELOC(name, number) #define EMPTY_RELOC(name) - -#define END_RELOC_NUMBERS \ + +#define END_RELOC_NUMBERS(name) \ default: return NULL; \ } \ } @@ -95,21 +95,11 @@ name (rtype) \ #else /* Default to generating enum. */ -/* Some compilers cannot cope with an enum that ends with a trailing - comma, so START_RELOC_NUMBERS creates a fake reloc entry, (initialised - to -1 so that the first real entry will still default to 0). Further - entries then prepend a comma to their definitions, creating a list - of enumerator entries that will satisfy these compilers. */ -#ifdef __STDC__ -#define START_RELOC_NUMBERS(name) enum name { _##name = -1 -#else -#define START_RELOC_NUMBERS(name) enum name { name = -1 -#endif - -#define RELOC_NUMBER(name, number) , name = number -#define FAKE_RELOC(name, number) , name = number -#define EMPTY_RELOC(name) , name -#define END_RELOC_NUMBERS }; +#define START_RELOC_NUMBERS(name) enum name { +#define RELOC_NUMBER(name, number) name = number, +#define FAKE_RELOC(name, number) name = number, +#define EMPTY_RELOC(name) name, +#define END_RELOC_NUMBERS(name) name }; #endif diff --git a/contrib/binutils/include/elf/sh.h b/contrib/binutils/include/elf/sh.h index faee509..6a1e561 100644 --- a/contrib/binutils/include/elf/sh.h +++ b/contrib/binutils/include/elf/sh.h @@ -1,5 +1,5 @@ /* SH ELF support for BFD. - Copyright (C) 1998 Free Software Foundation, Inc. + Copyright (C) 1998, 2000 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -76,7 +76,18 @@ START_RELOC_NUMBERS (elf_sh_reloc_type) RELOC_NUMBER (R_SH_SWITCH8, 33) RELOC_NUMBER (R_SH_GNU_VTINHERIT, 34) RELOC_NUMBER (R_SH_GNU_VTENTRY, 35) - EMPTY_RELOC (R_SH_max) -END_RELOC_NUMBERS + RELOC_NUMBER (R_SH_LOOP_START, 36) + RELOC_NUMBER (R_SH_LOOP_END, 37) + FAKE_RELOC (R_SH_FIRST_INVALID_RELOC_2, 38) + FAKE_RELOC (R_SH_LAST_INVALID_RELOC_2, 159) + RELOC_NUMBER (R_SH_GOT32, 160) + RELOC_NUMBER (R_SH_PLT32, 161) + RELOC_NUMBER (R_SH_COPY, 162) + RELOC_NUMBER (R_SH_GLOB_DAT, 163) + RELOC_NUMBER (R_SH_JMP_SLOT, 164) + RELOC_NUMBER (R_SH_RELATIVE, 165) + RELOC_NUMBER (R_SH_GOTOFF, 166) + RELOC_NUMBER (R_SH_GOTPC, 167) +END_RELOC_NUMBERS (R_SH_max) #endif diff --git a/contrib/binutils/include/elf/sparc.h b/contrib/binutils/include/elf/sparc.h index 390e4a8..f4a199e 100644 --- a/contrib/binutils/include/elf/sparc.h +++ b/contrib/binutils/include/elf/sparc.h @@ -1,5 +1,5 @@ /* SPARC ELF support for BFD. - Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. + Copyright (C) 1996, 97, 98, 99, 2000 Free Software Foundation, Inc. By Doug Evans, Cygnus Support, <dje@cygnus.com>. This file is part of BFD, the Binary File Descriptor library. @@ -134,8 +134,7 @@ START_RELOC_NUMBERS (elf_sparc_reloc_type) RELOC_NUMBER (R_SPARC_GNU_VTINHERIT, 250) RELOC_NUMBER (R_SPARC_GNU_VTENTRY, 251) - EMPTY_RELOC (R_SPARC_max) -END_RELOC_NUMBERS +END_RELOC_NUMBERS (R_SPARC_max) /* Relocation macros. */ diff --git a/contrib/binutils/include/elf/v850.h b/contrib/binutils/include/elf/v850.h index d443b7f..7b22340 100644 --- a/contrib/binutils/include/elf/v850.h +++ b/contrib/binutils/include/elf/v850.h @@ -1,5 +1,5 @@ /* V850 ELF support for BFD. - Copyright (C) 1997 Free Software Foundation, Inc. + Copyright (C) 1997, 98, 2000 Free Software Foundation, Inc. Created by Michael Meissner, Cygnus Support <meissner@cygnus.com> This file is part of BFD, the Binary File Descriptor library. @@ -67,19 +67,15 @@ START_RELOC_NUMBERS (v850_reloc_type) RELOC_NUMBER( R_V850_TDA_7_8_OFFSET, 14) /* For sst.h, sld.h */ RELOC_NUMBER( R_V850_TDA_7_7_OFFSET, 15) /* For sst.b, sld.b */ RELOC_NUMBER( R_V850_TDA_16_16_OFFSET, 16) /* For set1, clr1, not1, tst1, movea, movhi */ -/* CYGNUS LOCAL v850e */ RELOC_NUMBER( R_V850_TDA_4_5_OFFSET, 17) /* For sld.hu */ RELOC_NUMBER( R_V850_TDA_4_4_OFFSET, 18) /* For sld.bu */ RELOC_NUMBER( R_V850_SDA_16_16_SPLIT_OFFSET, 19) /* For ld.bu */ RELOC_NUMBER( R_V850_ZDA_16_16_SPLIT_OFFSET, 20) /* For ld.bu */ RELOC_NUMBER( R_V850_CALLT_6_7_OFFSET, 21) /* For callt */ RELOC_NUMBER( R_V850_CALLT_16_16_OFFSET, 22) /* For callt */ -/* END CYGNUS LOCAL */ RELOC_NUMBER (R_V850_GNU_VTINHERIT, 23) RELOC_NUMBER (R_V850_GNU_VTENTRY, 24) - - EMPTY_RELOC (R_V850_max) -END_RELOC_NUMBERS +END_RELOC_NUMBERS (R_V850_max) /* Processor specific section indices. These sections do not actually diff --git a/contrib/binutils/include/elf/x86-64.h b/contrib/binutils/include/elf/x86-64.h new file mode 100644 index 0000000..a4da0a3 --- /dev/null +++ b/contrib/binutils/include/elf/x86-64.h @@ -0,0 +1,46 @@ +/* x86_64 ELF support for BFD. + Copyright (C) 2000 Free Software Foundation, Inc. + Contributed by Jan Hubicka <jh@suse.cz> + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_X86_64_H +#define _ELF_X86_64_H + +#include "elf/reloc-macros.h" + +START_RELOC_NUMBERS (elf_x86_64_reloc_type) + RELOC_NUMBER (R_X86_64_NONE, 0) /* No reloc */ + RELOC_NUMBER (R_X86_64_64, 1) /* Direct 64 bit */ + RELOC_NUMBER (R_X86_64_PC32, 2) /* PC relative 32 bit signed */ + RELOC_NUMBER (R_X86_64_GOT32, 3) /* 32 bit GOT entry */ + RELOC_NUMBER (R_X86_64_PLT32, 4) /* 32 bit PLT address */ + RELOC_NUMBER (R_X86_64_COPY, 5) /* Copy symbol at runtime */ + RELOC_NUMBER (R_X86_64_GLOB_DAT, 6) /* Create GOT entry */ + RELOC_NUMBER (R_X86_64_JUMP_SLOT, 7) /* Create PLT entry */ + RELOC_NUMBER (R_X86_64_RELATIVE, 8) /* Adjust by program base */ + RELOC_NUMBER (R_X86_64_GOTPCREL, 9) /* 32 bit signed pc relative + offset to GOT */ + RELOC_NUMBER (R_X86_64_32, 10) /* Direct 32 bit zero extended */ + RELOC_NUMBER (R_X86_64_32S, 11) /* Direct 32 bit sign extended */ + RELOC_NUMBER (R_X86_64_16, 12) /* Direct 16 bit zero extended */ + RELOC_NUMBER (R_X86_64_PC16, 13) /* 16 bit sign extended pc relative*/ + RELOC_NUMBER (R_X86_64_8, 14) /* Direct 8 bit sign extended */ + RELOC_NUMBER (R_X86_64_PC8, 15) /* 8 bit sign extended pc relative*/ +END_RELOC_NUMBERS (R_X86_64_max) + +#endif diff --git a/contrib/binutils/include/floatformat.h b/contrib/binutils/include/floatformat.h index 90daca2..e4d1d15 100644 --- a/contrib/binutils/include/floatformat.h +++ b/contrib/binutils/include/floatformat.h @@ -1,5 +1,5 @@ /* IEEE floating point support declarations, for GDB, the GNU Debugger. - Copyright (C) 1991 Free Software Foundation, Inc. + Copyright (C) 1991, 2000 Free Software Foundation, Inc. This file is part of GDB. @@ -73,6 +73,9 @@ struct floatformat /* Is the integer bit explicit or implicit? */ enum floatformat_intbit intbit; + + /* Internal name for debugging. */ + const char *name; }; /* floatformats for IEEE single and double, big and little endian. */ diff --git a/contrib/binutils/include/getopt.h b/contrib/binutils/include/getopt.h index fb30719..bf65c6e 100644 --- a/contrib/binutils/include/getopt.h +++ b/contrib/binutils/include/getopt.h @@ -1,5 +1,6 @@ /* Declarations for getopt. - Copyright (C) 1989,90,91,92,93,94,96,97 Free Software Foundation, Inc. + Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1996, 1997 + Free Software Foundation, Inc. NOTE: The canonical source of this file is maintained with the GNU C Library. Bugs can be reported to bug-glibc@gnu.org. @@ -99,13 +100,20 @@ struct option #define optional_argument 2 #if defined (__STDC__) && __STDC__ -#ifdef __GNU_LIBRARY__ +/* HAVE_DECL_* is a three-state macro: undefined, 0 or 1. If it is + undefined, we haven't run the autoconf check so provide the + declaration without arguments. If it is 0, we checked and failed + to find the declaration so provide a fully prototyped one. If it + is 1, we found it so don't provide any declaration at all. */ +#if defined (__GNU_LIBRARY__) || (defined (HAVE_DECL_GETOPT) && !HAVE_DECL_GETOPT) /* Many other libraries have conflicting prototypes for getopt, with differences in the consts, in stdlib.h. To avoid compilation errors, only prototype getopt for the GNU C library. */ extern int getopt (int argc, char *const *argv, const char *shortopts); #else /* not __GNU_LIBRARY__ */ +# if !defined (HAVE_DECL_GETOPT) extern int getopt (); +# endif #endif /* __GNU_LIBRARY__ */ extern int getopt_long (int argc, char *const *argv, const char *shortopts, const struct option *longopts, int *longind); diff --git a/contrib/binutils/include/hashtab.h b/contrib/binutils/include/hashtab.h index 5fe2393..a577c5e 100644 --- a/contrib/binutils/include/hashtab.h +++ b/contrib/binutils/include/hashtab.h @@ -1,5 +1,5 @@ /* An expandable hash tables datatype. - Copyright (C) 1999 Free Software Foundation, Inc. + Copyright (C) 1999, 2000 Free Software Foundation, Inc. Contributed by Vladimir Makarov (vmakarov@cygnus.com). This program is free software; you can redistribute it and/or modify @@ -38,10 +38,13 @@ extern "C" { #include <ansidecl.h> +/* The type for a hash code. */ +typedef unsigned int hashval_t; + /* Callback function pointer types. */ /* Calculate hash of a table entry. */ -typedef unsigned int (*htab_hash) PARAMS ((const void *)); +typedef hashval_t (*htab_hash) PARAMS ((const void *)); /* Compare a table entry with a possible entry. The entry already in the table always comes first, so the second element can be of a @@ -77,7 +80,7 @@ struct htab htab_del del_f; /* Table itself. */ - void **entries; + PTR *entries; /* Current size (in entries) of the hash table */ size_t size; @@ -95,23 +98,38 @@ struct htab /* The following member is used for debugging. Its value is number of collisions fixed for time of work with the hash table. */ unsigned int collisions; + + /* This is non-zero if we are allowed to return NULL for function calls + that allocate memory. */ + int return_allocation_failure; }; typedef struct htab *htab_t; +/* An enum saying whether we insert into the hash table or not. */ +enum insert_option {NO_INSERT, INSERT}; + /* The prototypes of the package functions. */ extern htab_t htab_create PARAMS ((size_t, htab_hash, htab_eq, htab_del)); + +/* This function is like htab_create, but may return NULL if memory + allocation fails, and also signals that htab_find_slot_with_hash and + htab_find_slot are allowed to return NULL when inserting. */ +extern htab_t htab_try_create PARAMS ((size_t, htab_hash, + htab_eq, htab_del)); extern void htab_delete PARAMS ((htab_t)); extern void htab_empty PARAMS ((htab_t)); -extern void *htab_find PARAMS ((htab_t, const void *)); -extern void **htab_find_slot PARAMS ((htab_t, const void *, int)); -extern void *htab_find_with_hash PARAMS ((htab_t, const void *, - unsigned int)); -extern void **htab_find_slot_with_hash PARAMS ((htab_t, const void *, - unsigned int, int)); +extern PTR htab_find PARAMS ((htab_t, const void *)); +extern PTR *htab_find_slot PARAMS ((htab_t, const void *, + enum insert_option)); +extern PTR htab_find_with_hash PARAMS ((htab_t, const void *, + hashval_t)); +extern PTR *htab_find_slot_with_hash PARAMS ((htab_t, const void *, + hashval_t, + enum insert_option)); extern void htab_clear_slot PARAMS ((htab_t, void **)); extern void htab_remove_elt PARAMS ((htab_t, void *)); @@ -121,6 +139,12 @@ extern size_t htab_size PARAMS ((htab_t)); extern size_t htab_elements PARAMS ((htab_t)); extern double htab_collisions PARAMS ((htab_t)); +/* A hash function for pointers. */ +extern htab_hash htab_hash_pointer; + +/* An equality function for pointers. */ +extern htab_eq htab_eq_pointer; + #ifdef __cplusplus } #endif /* __cplusplus */ diff --git a/contrib/binutils/include/libiberty.h b/contrib/binutils/include/libiberty.h index 9a536a4..64d072b 100644 --- a/contrib/binutils/include/libiberty.h +++ b/contrib/binutils/include/libiberty.h @@ -16,6 +16,13 @@ extern "C" { #include "ansidecl.h" +#ifdef ANSI_PROTOTYPES +/* Get a definition for size_t. */ +#include <stddef.h> +/* Get a definition for va_list. */ +#include <stdarg.h> +#endif + /* Build an argument vector from a string. Allocates memory using malloc. Use freeargv to free the vector. */ @@ -36,10 +43,17 @@ extern char **dupargv PARAMS ((char **)) ATTRIBUTE_MALLOC; across different systems, sometimes as "char *" and sometimes as "const char *" */ -#if defined (__GNU_LIBRARY__ ) || defined (__linux__) || defined (__FreeBSD__) || defined (__OpenBSD__) || defined (__CYGWIN__) || defined (__CYGWIN32__) +/* HAVE_DECL_* is a three-state macro: undefined, 0 or 1. If it is + undefined, we haven't run the autoconf check so provide the + declaration without arguments. If it is 0, we checked and failed + to find the declaration so provide a fully prototyped one. If it + is 1, we found it so don't provide any declaration at all. */ +#if defined (__GNU_LIBRARY__ ) || defined (__linux__) || defined (__FreeBSD__) || defined (__OpenBSD__) || defined (__CYGWIN__) || defined (__CYGWIN32__) || (defined (HAVE_DECL_BASENAME) && !HAVE_DECL_BASENAME) extern char *basename PARAMS ((const char *)); #else +# if !defined (HAVE_DECL_BASENAME) extern char *basename (); +# endif #endif /* Concatenate an arbitrary number of strings, up to (char *) NULL. @@ -123,16 +137,13 @@ extern void xexit PARAMS ((int status)) ATTRIBUTE_NORETURN; extern void xmalloc_set_program_name PARAMS ((const char *)); +/* Report an allocation failure. */ +extern void xmalloc_failed PARAMS ((size_t)) ATTRIBUTE_NORETURN; + /* Allocate memory without fail. If malloc fails, this will print a message to stderr (using the name set by xmalloc_set_program_name, if any) and then call xexit. */ -#ifdef ANSI_PROTOTYPES -/* Get a definition for size_t. */ -#include <stddef.h> -/* Get a definition for va_list. */ -#include <stdarg.h> -#endif extern PTR xmalloc PARAMS ((size_t)) ATTRIBUTE_MALLOC; /* Reallocate memory without fail. This works like xmalloc. Note, @@ -193,6 +204,8 @@ extern int asprintf PARAMS ((char **, const char *, ...)) ATTRIBUTE_PRINTF_2; extern int vasprintf PARAMS ((char **, const char *, va_list)) ATTRIBUTE_PRINTF(2,0); +#define ARRAY_SIZE(a) (sizeof (a) / sizeof ((a)[0])) + #ifdef __cplusplus } #endif diff --git a/contrib/binutils/include/md5.h b/contrib/binutils/include/md5.h new file mode 100644 index 0000000..0840b31 --- /dev/null +++ b/contrib/binutils/include/md5.h @@ -0,0 +1,142 @@ +/* md5.h - Declaration of functions and data types used for MD5 sum + computing library functions. + Copyright (C) 1995, 1996 Free Software Foundation, Inc. + NOTE: The canonical source of this file is maintained with the GNU C + Library. Bugs can be reported to bug-glibc@prep.ai.mit.edu. + + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _MD5_H +#define _MD5_H 1 + +#include <stdio.h> + +#if defined HAVE_LIMITS_H || _LIBC +# include <limits.h> +#endif + +/* The following contortions are an attempt to use the C preprocessor + to determine an unsigned integral type that is 32 bits wide. An + alternative approach is to use autoconf's AC_CHECK_SIZEOF macro, but + doing that would require that the configure script compile and *run* + the resulting executable. Locally running cross-compiled executables + is usually not possible. */ + +#ifdef _LIBC +# include <sys/types.h> +typedef u_int32_t md5_uint32; +#else +# define INT_MAX_32_BITS 2147483647 + +/* If UINT_MAX isn't defined, assume it's a 32-bit type. + This should be valid for all systems GNU cares about because + that doesn't include 16-bit systems, and only modern systems + (that certainly have <limits.h>) have 64+-bit integral types. */ + +# ifndef INT_MAX +# define INT_MAX INT_MAX_32_BITS +# endif + +# if INT_MAX == INT_MAX_32_BITS + typedef unsigned int md5_uint32; +# else +# if SHRT_MAX == INT_MAX_32_BITS + typedef unsigned short md5_uint32; +# else +# if LONG_MAX == INT_MAX_32_BITS + typedef unsigned long md5_uint32; +# else + /* The following line is intended to evoke an error. + Using #error is not portable enough. */ + "Cannot determine unsigned 32-bit data type." +# endif +# endif +# endif +#endif + +#undef __P +#if defined (__STDC__) && __STDC__ +#define __P(x) x +#else +#define __P(x) () +#endif + +/* Structure to save state of computation between the single steps. */ +struct md5_ctx +{ + md5_uint32 A; + md5_uint32 B; + md5_uint32 C; + md5_uint32 D; + + md5_uint32 total[2]; + md5_uint32 buflen; + char buffer[128]; +}; + +/* + * The following three functions are build up the low level used in + * the functions `md5_stream' and `md5_buffer'. + */ + +/* Initialize structure containing state of computation. + (RFC 1321, 3.3: Step 3) */ +extern void md5_init_ctx __P ((struct md5_ctx *ctx)); + +/* Starting with the result of former calls of this function (or the + initialization function update the context for the next LEN bytes + starting at BUFFER. + It is necessary that LEN is a multiple of 64!!! */ +extern void md5_process_block __P ((const void *buffer, size_t len, + struct md5_ctx *ctx)); + +/* Starting with the result of former calls of this function (or the + initialization function update the context for the next LEN bytes + starting at BUFFER. + It is NOT required that LEN is a multiple of 64. */ +extern void md5_process_bytes __P ((const void *buffer, size_t len, + struct md5_ctx *ctx)); + +/* Process the remaining bytes in the buffer and put result from CTX + in first 16 bytes following RESBUF. The result is always in little + endian byte order, so that a byte-wise output yields to the wanted + ASCII representation of the message digest. + + IMPORTANT: On some systems it is required that RESBUF is correctly + aligned for a 32 bits value. */ +extern void *md5_finish_ctx __P ((struct md5_ctx *ctx, void *resbuf)); + + +/* Put result from CTX in first 16 bytes following RESBUF. The result is + always in little endian byte order, so that a byte-wise output yields + to the wanted ASCII representation of the message digest. + + IMPORTANT: On some systems it is required that RESBUF is correctly + aligned for a 32 bits value. */ +extern void *md5_read_ctx __P ((const struct md5_ctx *ctx, void *resbuf)); + + +/* Compute MD5 message digest for bytes read from STREAM. The + resulting message digest number will be written into the 16 bytes + beginning at RESBLOCK. */ +extern int md5_stream __P ((FILE *stream, void *resblock)); + +/* Compute MD5 message digest for LEN bytes beginning at BUFFER. The + result is always in little endian byte order, so that a byte-wise + output yields to the wanted ASCII representation of the message + digest. */ +extern void *md5_buffer __P ((const char *buffer, size_t len, void *resblock)); + +#endif diff --git a/contrib/binutils/include/obstack.h b/contrib/binutils/include/obstack.h index a20ab55..314a27a 100644 --- a/contrib/binutils/include/obstack.h +++ b/contrib/binutils/include/obstack.h @@ -1,5 +1,6 @@ /* obstack.h - object stack macros - Copyright (C) 1988,89,90,91,92,93,94,96,97,98 Free Software Foundation, Inc. + Copyright (C) 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1996, 1997, 1998 + Free Software Foundation, Inc. NOTE: The canonical source of this file is maintained with the GNU C Library. diff --git a/contrib/binutils/include/opcode/ChangeLog b/contrib/binutils/include/opcode/ChangeLog index 4e8dbf1..6a5da3e 100644 --- a/contrib/binutils/include/opcode/ChangeLog +++ b/contrib/binutils/include/opcode/ChangeLog @@ -1,17 +1,258 @@ +2001-03-24 Alan Modra <alan@linuxcare.com.au> + + * i386.h (i386_optab): Correct entry for "movntdq". Add "punpcklqdq". + Add InvMem to first operand of "maskmovdqu". + +2001-03-22 Alan Modra <alan@linuxcare.com.au> + + * i386.h (i386_optab): Add paddq, psubq. + +2001-03-19 Alan Modra <alan@linuxcare.com.au> + + * i386.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Define. + +Mon Feb 12 17:39:31 CET 2001 Jan Hubicka <jh@suse.cz> + + * i386.h (i386_optab): SSE integer converison instructions have + 64bit versions on x86-64. + +2001-01-24 Karsten Keil <kkeil@suse.de> + + * i386.h (i386_optab): Fix swapgs + +2001-01-14 Alan Modra <alan@linuxcare.com.au> + + * hppa.h: Describe new '<' and '>' operand types, and tidy + existing comments. + (pa_opcodes): Add entries for missing wide mode ldi,ldo,ldw,stw. + Remove duplicate "ldw j(s,b),x". Sort some entries. + +Sat Jan 13 09:56:32 MET 2001 Jan Hubicka <jh@suse.cz> + + * i386.h (i386_optab): Fix pusha and ret templates. + +2001-01-11 Peter Targett <peter.targett@arccores.com> + + * arc.h (ARC_MACH_5, ARC_MACH_6, ARC_MACH_7, ARC_MACH_8): New + definitions for masking cpu type. + (arc_ext_operand_value) New structure for storing extended + operands. + (ARC_OPERAND_*) Flags for operand values. + +2001-01-10 Jan Hubicka <jh@suse.cz> + + * i386.h (pinsrw): Add. + (pshufw): Remove. + (cvttpd2dq): Fix operands. + (cvttps2dq): Likewise. + (movq2q): Rename to movdq2q. + +2001-01-10 Richard Schaal <richard.schaal@intel.com> + + * i386.h: Correct movnti instruction. + +2001-01-09 Jeff Johnston <jjohnstn@redhat.com> + + * cgen.h (CGEN_SYNTAX_CHAR_TYPE): New typedef based on max number + of operands (unsigned char or unsigned short). + (CGEN_SYNTAX): Changed to make array CGEN_SYNTAX_CHAR_TYPE. + (CGEN_SYNTAX_CHAR): Changed to cast to unsigned char. + +2001-01-05 Jan Hubicka <jh@suse.cz> + + * i386.h (i386_optab): Make [sml]fence template to use immext field. + +2001-01-03 Jan Hubicka <jh@suse.cz> + + * i386.h (i386_optab): Fix 64bit pushf template; Add instructions + introduced by Pentium4 + +2000-12-30 Jan Hubicka <jh@suse.cz> + + * i386.h (i386_optab): Add "rex*" instructions; + add swapgs; disable jmp/call far direct instructions for + 64bit mode; add syscall and sysret; disable registers for 0xc6 + template. Add 'q' suffixes to extendable instructions, disable + obsolete instructions, add new sign/zero extension ones. + (i386_regtab): Add extended registers. + (*Suf): Add No_qSuf. + (q_Suf, wlq_Suf, bwlq_Suf): New. + +2000-12-20 Jan Hubicka <jh@suse.cz> + + * i386.h (i386_optab): Replace "Imm" with "EncImm". + (i386_regtab): Add flags field. + +2000-12-12 Nick Clifton <nickc@redhat.com> + + * mips.h: Fix formatting. + +2000-12-01 Chris Demetriou <cgd@sibyte.com> + + mips.h (OP_MASK_SYSCALL, OP_SH_SYSCALL): Delete. + (OP_MASK_CODE20, OP_SH_CODE20): Define, with values of old + OP_*_SYSCALL definitions. + (OP_SH_CODE19, OP_MASK_CODE19): Define, for use as + 19 bit wait codes. + (MIPS operand specifier comments): Remove 'm', add 'U' and + 'J', and update the meaning of 'B' so that it's more general. + + * mips.h (INSN_ISA1, INSN_ISA2, INSN_ISA3, INSN_ISA4, + INSN_ISA5): Renumber, redefine to mean the ISA at which the + instruction was added. + (INSN_ISA32): New constant. + (INSN_4650, INSN_4010, INSN_4100, INSN_3900, INSN_GP32): + Renumber to avoid new and/or renumbered INSN_* constants. + (INSN_MIPS32): Delete. + (ISA_UNKNOWN): New constant to indicate unknown ISA. + (ISA_MIPS1, ISA_MIPS2, ISA_MIPS3, ISA_MIPS4, ISA_MIPS5, + ISA_MIPS32): New constants, defined to be the mask of INSN_* + constants available at that ISA level. + (CPU_UNKNOWN): New constant to indicate unknown CPU. + (CPU_4K, CPU_MIPS32_4K): Rename the former to the latter, + define it with a unique value. + (OPCODE_IS_MEMBER): Update for new ISA membership-related + constant meanings. + + * mips.h (INSN_ISA64, ISA_MIPS5, ISA_MIPS64): New + definitions. + + * mips.h (CPU_SB1): New constant. + +2000-10-20 Jakub Jelinek <jakub@redhat.com> + + * sparc.h (enum sparc_opcode_arch_val): Add SPARC_OPCODE_ARCH_V9B. + Note that '3' is used for siam operand. + +2000-09-22 Jim Wilson <wilson@cygnus.com> + + * ia64.h (enum ia64_dependency_semantics): Add IA64_DVS_STOP. + +2000-09-13 Anders Norlander <anorland@acc.umu.se> + + * mips.h: Use defines instead of hard-coded processor numbers. + (CPU_R2000, CPU_R3000, CPU_R3900, CPU_R4000, CPU_R4010, + CPU_VR4100, CPU_R4111, CPU_R4300, CPU_R4400, CPU_R4600, CPU_R4650, + CPU_R5000, CPU_R6000, CPU_R8000, CPU_R10000, CPU_MIPS32, CPU_4K, + CPU_4KC, CPU_4KM, CPU_4KP): Define.. + (OPCODE_IS_MEMBER): Use new defines. + (OP_MASK_SEL, OP_SH_SEL): Define. + (OP_MASK_CODE20, OP_SH_CODE20): Define. + Add 'P' to used characters. + Use 'H' for coprocessor select field. + Use 'm' for 20 bit breakpoint code. + Document new arg characters and add to used characters. + (INSN_MIPS32): New define for MIPS32 extensions. + (OPCODE_IS_MEMBER): Recognize MIPS32 instructions. + +2000-09-05 Alan Modra <alan@linuxcare.com.au> + + * hppa.h: Mention cz completer. + +2000-08-16 Jim Wilson <wilson@cygnus.com> + + * ia64.h (IA64_OPCODE_POSTINC): New. + +2000-08-15 H.J. Lu <hjl@gnu.org> + + * i386.h: Swap the Intel syntax "movsx"/"movzx" due to the + IgnoreSize change. + +2000-07-29 Marek Michalkiewicz <marekm@linux.org.pl> + + * avr.h (AVR_UNDEF_P, AVR_SKIP_P, AVR_DISP0_P): New macros. + Move related opcodes closer to each other. + Minor changes in comments, list undefined opcodes. + +2000-07-26 Dave Brolley <brolley@redhat.com> + + * cgen.h (cgen_hw_lookup_by_num): Second parameter is unsigned. + +2000-07-20 Hans-Peter Nilsson <hp@axis.com> + + cris.h: New file. + +2000-06-26 Marek Michalkiewicz <marekm@linux.org.pl> + + * avr.h (AVR_ISA_WRAP): Remove, now assumed if not AVR_ISA_MEGA. + (AVR_ISA_ESPM): Remove, because ESPM removed in databook update. + (AVR_ISA_85xx): Remove, all uses changed back to AVR_ISA_2xxx. + (AVR_ISA_M83): Define for ATmega83, ATmega85. + (espm): Remove, because ESPM removed in databook update. + (eicall, eijmp): Move to the end of opcode table. + +2000-06-18 Stephane Carrez <stcarrez@worldnet.fr> + + * m68hc11.h: New file for support of Motorola 68hc11. + +Fri Jun 9 21:51:50 2000 Denis Chertykov <denisc@overta.ru> + + * avr.h: clr,lsl,rol, ... moved after add,adc, ... + +Wed Jun 7 21:39:54 2000 Denis Chertykov <denisc@overta.ru> + + * avr.h: New file with AVR opcodes. + +Wed Apr 12 17:11:20 2000 Donald Lindsay <dlindsay@hound.cygnus.com> + + * d10v.h: added ALONE attribute for d10v_opcode.exec_type. + 2000-05-23 Maciej W. Rozycki <macro@ds2.pg.gda.pl> * i386.h: Allow d suffix on iret, and add DefaultSize modifier. -2000-05-23 Alan Modra <alan@linuxcare.com.au> +2000-05-17 Maciej W. Rozycki <macro@ds2.pg.gda.pl> + + * i386.h: Use sl_FP, not sl_Suf for fild. + +2000-05-16 Frank Ch. Eigler <fche@redhat.com> + + * cgen.h (CGEN_MAX_SYNTAX_BYTES): Increase to 32. Check that + it exceeds CGEN_ACTUAL_MAX_SYNTAX_BYTES, if set. + (CGEN_MAX_IFMT_OPERANDS): Increase to 16. Check that it exceeds + CGEN_ACTUAL_MAX_IFMT_OPERANDS, if set. + +2000-05-13 Alan Modra <alan@linuxcare.com.au>, + + * i386.h (i386_optab): Cpu686 for sysenter,sysexit,fxsave,fxrestore. + +2000-05-13 Alan Modra <alan@linuxcare.com.au>, + Alexander Sokolov <robocop@netlink.ru> + + * i386.h (i386_optab): Add cpu_flags for all instructions. - * i386.h: Delete redundant fp instruction comments. +2000-05-13 Alan Modra <alan@linuxcare.com.au> From Gavin Romig-Koch <gavin@cygnus.com> * i386.h (wld_Suf): Define. Use on pushf, popf, pusha, popa. -2000-05-17 Maciej W. Rozycki <macro@ds2.pg.gda.pl> +2000-05-04 Timothy Wall <twall@cygnus.com> - * i386.h: Use sl_FP, not sl_Suf for fild. + * tic54x.h: New. + +2000-05-03 J.T. Conklin <jtc@redback.com> + + * ppc.h (PPC_OPCODE_ALTIVEC): New opcode flag for vector unit. + (PPC_OPERAND_VR): New operand flag for vector registers. + +2000-05-01 Kazu Hirata <kazu@hxi.com> + + * h8300.h (EOP): Add missing initializer. + +Fri Apr 21 15:03:37 2000 Jason Eckhardt <jle@cygnus.com> + + * hppa.h (pa_opcodes): New opcodes for PA2.0 wide mode + forms of ld/st{b,h,w,d} and fld/fst{w,d} (16-bit displacements). + New operand types l,y,&,fe,fE,fx added to support above forms. + (pa_opcodes): Replaced usage of 'x' as source/target for + floating point double-word loads/stores with 'fx'. + +Fri Apr 21 13:20:53 2000 Richard Henderson <rth@cygnus.com> + David Mosberger <davidm@hpl.hp.com> + Timothy Wall <twall@cygnus.com> + Jim Wilson <wilson@cygnus.com> + + * ia64.h: New file. 2000-03-27 Nick Clifton <nickc@cygnus.com> diff --git a/contrib/binutils/include/opcode/i386.h b/contrib/binutils/include/opcode/i386.h index d00d331..9deffcc 100644 --- a/contrib/binutils/include/opcode/i386.h +++ b/contrib/binutils/include/opcode/i386.h @@ -1,6 +1,7 @@ /* opcode/i386.h -- Intel 80386 opcode table - Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 98, 99, 2000 - Free Software Foundation. + Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, + 2000, 2001 + Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. @@ -50,28 +51,25 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ static const template i386_optab[] = { #define X None -#define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf) -#define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf) -#define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf) -#define l_Suf (No_bSuf|No_wSuf|No_sSuf|No_dSuf|No_xSuf) -#define d_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_xSuf) -#define x_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_dSuf) -#define bw_Suf (No_lSuf|No_sSuf|No_dSuf|No_xSuf) -#define bl_Suf (No_wSuf|No_sSuf|No_dSuf|No_xSuf) -#define wl_Suf (No_bSuf|No_sSuf|No_dSuf|No_xSuf) -#define wld_Suf (No_bSuf|No_sSuf|No_xSuf) -#define sl_Suf (No_bSuf|No_wSuf|No_dSuf|No_xSuf) -#define sld_Suf (No_bSuf|No_wSuf|No_xSuf) -#define sldx_Suf (No_bSuf|No_wSuf) -#define bwl_Suf (No_sSuf|No_dSuf|No_xSuf) -#define bwld_Suf (No_sSuf|No_xSuf) +#define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) +#define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) +#define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) +#define l_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf|No_qSuf) +#define q_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_xSuf) +#define x_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_qSuf) +#define bw_Suf (No_lSuf|No_sSuf|No_xSuf|No_qSuf) +#define bl_Suf (No_wSuf|No_sSuf|No_xSuf|No_qSuf) +#define wl_Suf (No_bSuf|No_sSuf|No_xSuf|No_qSuf) +#define wlq_Suf (No_bSuf|No_sSuf|No_xSuf) +#define lq_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf) +#define sl_Suf (No_bSuf|No_wSuf|No_xSuf|No_qSuf) +#define sldx_Suf (No_bSuf|No_wSuf|No_qSuf) +#define bwl_Suf (No_sSuf|No_xSuf|No_qSuf) +#define bwlq_Suf (No_sSuf|No_xSuf) #define FP (NoSuf|IgnoreSize) #define l_FP (l_Suf|IgnoreSize) -#define d_FP (d_Suf|IgnoreSize) #define x_FP (x_Suf|IgnoreSize) #define sl_FP (sl_Suf|IgnoreSize) -#define sld_FP (sld_Suf|IgnoreSize) -#define sldx_FP (sldx_Suf|IgnoreSize) #if SYSV386_COMPAT /* Someone forgot that the FloatR bit reverses the operation when not equal to the FloatD bit. ie. Changing only FloatD results in the @@ -83,1013 +81,1260 @@ static const template i386_optab[] = { /* Move instructions. */ #define MOV_AX_DISP32 0xa0 -{ "mov", 2, 0xa0, X, bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } }, -{ "mov", 2, 0x88, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0 } }, -{ "mov", 2, 0xb0, X, bwl_Suf|W|ShortForm, { Imm, Reg, 0 } }, -{ "mov", 2, 0xc6, X, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0 } }, -/* The next two instructions accept WordReg so that a segment register +/* In the 64bit mode the short form mov immediate is redefined to have + 64bit displacement value. */ +{ "mov", 2, 0xa0, X, CpuNo64,bwlq_Suf|D|W, { Disp16|Disp32, Acc, 0 } }, +{ "mov", 2, 0x88, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +/* In the 64bit mode the short form mov immediate is redefined to have + 64bit displacement value. */ +{ "mov", 2, 0xb0, X, 0, bwl_Suf|W|ShortForm, { EncImm, Reg8|Reg16|Reg32, 0 } }, +{ "mov", 2, 0xc6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0 } }, +{ "mov", 2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } }, +/* The segment register moves accept WordReg so that a segment register can be copied to a 32 bit register, and vice versa, without using a size prefix. When moving to a 32 bit register, the upper 16 bits are set to an implementation defined value (on the Pentium Pro, the implementation defined value is zero). */ -{ "mov", 2, 0x8c, X, wl_Suf|Modrm, { SReg3|SReg2, WordReg|WordMem, 0 } }, -{ "mov", 2, 0x8e, X, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg3|SReg2, 0 } }, -/* Move to/from control debug registers. */ -{ "mov", 2, 0x0f20, X, l_Suf|D|Modrm|IgnoreSize, { Control, Reg32|InvMem, 0} }, -{ "mov", 2, 0x0f21, X, l_Suf|D|Modrm|IgnoreSize, { Debug, Reg32|InvMem, 0} }, -{ "mov", 2, 0x0f24, X, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} }, +{ "mov", 2, 0x8c, X, 0, wl_Suf|Modrm, { SReg2, WordReg|WordMem, 0 } }, +{ "mov", 2, 0x8c, X, Cpu386, wl_Suf|Modrm, { SReg3, WordReg|WordMem, 0 } }, +{ "mov", 2, 0x8e, X, 0, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg2, 0 } }, +{ "mov", 2, 0x8e, X, Cpu386, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg3, 0 } }, +/* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit + mode they are 64bit.*/ +{ "mov", 2, 0x0f20, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Control, Reg32|InvMem, 0} }, +{ "mov", 2, 0x0f20, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Control, Reg64|InvMem, 0} }, +{ "mov", 2, 0x0f21, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Debug, Reg32|InvMem, 0} }, +{ "mov", 2, 0x0f21, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Debug, Reg64|InvMem, 0} }, +{ "mov", 2, 0x0f24, X, Cpu386, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} }, +{ "movabs",2, 0xa0, X, Cpu64, bwlq_Suf|D|W, { Disp64, Acc, 0 } }, +{ "movabs",2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } }, /* Move with sign extend. */ /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid conflict with the "movs" string move instruction. */ -{"movsbl", 2, 0x0fbe, X, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} }, -{"movsbw", 2, 0x0fbe, X, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} }, -{"movswl", 2, 0x0fbf, X, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, -/* Intel Syntax next 2 insns */ -{"movsx", 2, 0x0fbf, X, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, -{"movsx", 2, 0x0fbe, X, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, +{"movsbl", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} }, +{"movsbw", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} }, +{"movswl", 2, 0x0fbf, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem,Reg32, 0} }, +{"movsbq", 2, 0x0fbe, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, +{"movswq", 2, 0x0fbf, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem,Reg64, 0} }, +{"movslq", 2, 0x63, X, Cpu64, NoSuf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} }, +/* Intel Syntax next 5 insns */ +{"movsx", 2, 0x0fbe, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, +{"movsx", 2, 0x0fbf, X, Cpu386, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, +{"movsx", 2, 0x0fbe, X, Cpu64, b_Suf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, +{"movsx", 2, 0x0fbf, X, Cpu64, w_Suf|Modrm|IgnoreSize|Rex64, { Reg16|ShortMem, Reg64, 0} }, +{"movsx", 2, 0x63, X, Cpu64, l_Suf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} }, /* Move with zero extend. */ -{"movzb", 2, 0x0fb6, X, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, -{"movzwl", 2, 0x0fb7, X, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, -/* Intel Syntax next 2 insns */ -{"movzx", 2, 0x0fb7, X, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, -{"movzx", 2, 0x0fb6, X, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, +{"movzb", 2, 0x0fb6, X, Cpu386, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, +{"movzwl", 2, 0x0fb7, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, +/* These instructions are not particulary usefull, since the zero extend + 32->64 is implicit, but we can encode them. */ +{"movzbq", 2, 0x0fb6, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, +{"movzwq", 2, 0x0fb7, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} }, +/* Intel Syntax next 4 insns */ +{"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, +{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, +/* These instructions are not particulary usefull, since the zero extend + 32->64 is implicit, but we can encode them. */ +{"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, +{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm|IgnoreSize|Rex64, { Reg16|ShortMem, Reg64, 0} }, /* Push instructions. */ -{"push", 1, 0x50, X, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, -{"push", 1, 0xff, 6, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, -{"push", 1, 0x6a, X, wl_Suf|DefaultSize, { Imm8S, 0, 0} }, -{"push", 1, 0x68, X, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} }, -{"push", 1, 0x06, X, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, -{"push", 1, 0x0fa0, X, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, -{"pusha", 0, 0x60, X, wld_Suf|DefaultSize, { 0, 0, 0 } }, +{"push", 1, 0x50, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, +{"push", 1, 0xff, 6, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, +{"push", 1, 0x6a, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm8S, 0, 0} }, +{"push", 1, 0x68, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} }, +{"push", 1, 0x06, X, 0|CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, +{"push", 1, 0x0fa0, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, +/* In 64bit mode, the operand size is implicitly 64bit. */ +{"push", 1, 0x50, X, Cpu64, q_Suf|ShortForm|DefaultSize|NoRex64, { Reg64, 0, 0 } }, +{"push", 1, 0xff, 6, Cpu64, q_Suf|Modrm|DefaultSize|NoRex64, { Reg64|WordMem, 0, 0 } }, +{"push", 1, 0x6a, X, Cpu186|Cpu64, q_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} }, +{"push", 1, 0x68, X, Cpu186|Cpu64, q_Suf|DefaultSize|NoRex64, { Imm32S, 0, 0} }, +{"push", 1, 0x06, X, Cpu64, q_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } }, +{"push", 1, 0x0fa0, X, Cpu386|Cpu64, q_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } }, + +{"pusha", 0, 0x60, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } }, /* Pop instructions. */ -{"pop", 1, 0x58, X, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, -{"pop", 1, 0x8f, 0, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, +{"pop", 1, 0x58, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, +{"pop", 1, 0x8f, 0, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, #define POP_SEG_SHORT 0x07 -{"pop", 1, 0x07, X, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, -{"pop", 1, 0x0fa1, X, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, -{"popa", 0, 0x61, X, wld_Suf|DefaultSize, { 0, 0, 0 } }, +{"pop", 1, 0x07, X, CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, +{"pop", 1, 0x0fa1, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, +/* In 64bit mode, the operand size is implicitly 64bit. */ +{"pop", 1, 0x58, X, Cpu64, q_Suf|ShortForm|DefaultSize|NoRex64, { Reg64, 0, 0 } }, +{"pop", 1, 0x8f, 0, Cpu64, q_Suf|Modrm|DefaultSize|NoRex64, { Reg64|WordMem, 0, 0 } }, +{"pop", 1, 0x07, X, Cpu64, q_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } }, +{"pop", 1, 0x0fa1, X, Cpu64, q_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } }, + +{"popa", 0, 0x61, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } }, /* Exchange instructions. - xchg commutes: we allow both operand orders. */ -{"xchg", 2, 0x90, X, wl_Suf|ShortForm, { WordReg, Acc, 0 } }, -{"xchg", 2, 0x90, X, wl_Suf|ShortForm, { Acc, WordReg, 0 } }, -{"xchg", 2, 0x86, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, -{"xchg", 2, 0x86, X, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } }, + xchg commutes: we allow both operand orders. + + In the 64bit code, xchg eax, eax is reused for new nop instruction. + */ +{"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { WordReg, Acc, 0 } }, +{"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { Acc, WordReg, 0 } }, +{"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, +{"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } }, /* In/out from ports. */ -{"in", 2, 0xe4, X, bwl_Suf|W, { Imm8, Acc, 0 } }, -{"in", 2, 0xec, X, bwl_Suf|W, { InOutPortReg, Acc, 0 } }, -{"in", 1, 0xe4, X, bwl_Suf|W, { Imm8, 0, 0 } }, -{"in", 1, 0xec, X, bwl_Suf|W, { InOutPortReg, 0, 0 } }, -{"out", 2, 0xe6, X, bwl_Suf|W, { Acc, Imm8, 0 } }, -{"out", 2, 0xee, X, bwl_Suf|W, { Acc, InOutPortReg, 0 } }, -{"out", 1, 0xe6, X, bwl_Suf|W, { Imm8, 0, 0 } }, -{"out", 1, 0xee, X, bwl_Suf|W, { InOutPortReg, 0, 0 } }, +{"in", 2, 0xe4, X, 0, bwlq_Suf|W, { Imm8, Acc, 0 } }, +{"in", 2, 0xec, X, 0, bwlq_Suf|W, { InOutPortReg, Acc, 0 } }, +{"in", 1, 0xe4, X, 0, bwlq_Suf|W, { Imm8, 0, 0 } }, +{"in", 1, 0xec, X, 0, bwlq_Suf|W, { InOutPortReg, 0, 0 } }, +{"out", 2, 0xe6, X, 0, bwlq_Suf|W, { Acc, Imm8, 0 } }, +{"out", 2, 0xee, X, 0, bwlq_Suf|W, { Acc, InOutPortReg, 0 } }, +{"out", 1, 0xe6, X, 0, bwlq_Suf|W, { Imm8, 0, 0 } }, +{"out", 1, 0xee, X, 0, bwlq_Suf|W, { InOutPortReg, 0, 0 } }, /* Load effective address. */ -{"lea", 2, 0x8d, X, wl_Suf|Modrm, { WordMem, WordReg, 0 } }, +{"lea", 2, 0x8d, X, 0, wlq_Suf|Modrm, { WordMem, WordReg, 0 } }, /* Load segment registers from memory. */ -{"lds", 2, 0xc5, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, -{"les", 2, 0xc4, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, -{"lfs", 2, 0x0fb4, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, -{"lgs", 2, 0x0fb5, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, -{"lss", 2, 0x0fb2, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, +{"lds", 2, 0xc5, X, CpuNo64, wlq_Suf|Modrm, { WordMem, WordReg, 0} }, +{"les", 2, 0xc4, X, CpuNo64, wlq_Suf|Modrm, { WordMem, WordReg, 0} }, +{"lfs", 2, 0x0fb4, X, Cpu386, wlq_Suf|Modrm, { WordMem, WordReg, 0} }, +{"lgs", 2, 0x0fb5, X, Cpu386, wlq_Suf|Modrm, { WordMem, WordReg, 0} }, +{"lss", 2, 0x0fb2, X, Cpu386, wlq_Suf|Modrm, { WordMem, WordReg, 0} }, /* Flags register instructions. */ -{"clc", 0, 0xf8, X, NoSuf, { 0, 0, 0} }, -{"cld", 0, 0xfc, X, NoSuf, { 0, 0, 0} }, -{"cli", 0, 0xfa, X, NoSuf, { 0, 0, 0} }, -{"clts", 0, 0x0f06, X, NoSuf, { 0, 0, 0} }, -{"cmc", 0, 0xf5, X, NoSuf, { 0, 0, 0} }, -{"lahf", 0, 0x9f, X, NoSuf, { 0, 0, 0} }, -{"sahf", 0, 0x9e, X, NoSuf, { 0, 0, 0} }, -{"pushf", 0, 0x9c, X, wld_Suf|DefaultSize, { 0, 0, 0} }, -{"popf", 0, 0x9d, X, wld_Suf|DefaultSize, { 0, 0, 0} }, -{"stc", 0, 0xf9, X, NoSuf, { 0, 0, 0} }, -{"std", 0, 0xfd, X, NoSuf, { 0, 0, 0} }, -{"sti", 0, 0xfb, X, NoSuf, { 0, 0, 0} }, +{"clc", 0, 0xf8, X, 0, NoSuf, { 0, 0, 0} }, +{"cld", 0, 0xfc, X, 0, NoSuf, { 0, 0, 0} }, +{"cli", 0, 0xfa, X, 0, NoSuf, { 0, 0, 0} }, +{"clts", 0, 0x0f06, X, Cpu286, NoSuf, { 0, 0, 0} }, +{"cmc", 0, 0xf5, X, 0, NoSuf, { 0, 0, 0} }, +{"lahf", 0, 0x9f, X, CpuNo64,NoSuf, { 0, 0, 0} }, +{"sahf", 0, 0x9e, X, CpuNo64,NoSuf, { 0, 0, 0} }, +{"pushf", 0, 0x9c, X, CpuNo64,wlq_Suf|DefaultSize, { 0, 0, 0} }, +{"pushf", 0, 0x9c, X, Cpu64, q_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, +{"popf", 0, 0x9d, X, CpuNo64,wlq_Suf|DefaultSize, { 0, 0, 0} }, +{"popf", 0, 0x9d, X, Cpu64, q_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, +{"stc", 0, 0xf9, X, 0, NoSuf, { 0, 0, 0} }, +{"std", 0, 0xfd, X, 0, NoSuf, { 0, 0, 0} }, +{"sti", 0, 0xfb, X, 0, NoSuf, { 0, 0, 0} }, /* Arithmetic. */ -{"add", 2, 0x00, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"add", 2, 0x83, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"add", 2, 0x04, X, bwl_Suf|W, { Imm, Acc, 0} }, -{"add", 2, 0x80, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, - -{"inc", 1, 0x40, X, wl_Suf|ShortForm, { WordReg, 0, 0} }, -{"inc", 1, 0xfe, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"sub", 2, 0x28, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"sub", 2, 0x83, 5, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"sub", 2, 0x2c, X, bwl_Suf|W, { Imm, Acc, 0} }, -{"sub", 2, 0x80, 5, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, - -{"dec", 1, 0x48, X, wl_Suf|ShortForm, { WordReg, 0, 0} }, -{"dec", 1, 0xfe, 1, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"sbb", 2, 0x18, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"sbb", 2, 0x83, 3, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"sbb", 2, 0x1c, X, bwl_Suf|W, { Imm, Acc, 0} }, -{"sbb", 2, 0x80, 3, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, - -{"cmp", 2, 0x38, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"cmp", 2, 0x83, 7, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"cmp", 2, 0x3c, X, bwl_Suf|W, { Imm, Acc, 0} }, -{"cmp", 2, 0x80, 7, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, - -{"test", 2, 0x84, X, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0} }, -{"test", 2, 0x84, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"test", 2, 0xa8, X, bwl_Suf|W, { Imm, Acc, 0} }, -{"test", 2, 0xf6, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, - -{"and", 2, 0x20, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"and", 2, 0x83, 4, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"and", 2, 0x24, X, bwl_Suf|W, { Imm, Acc, 0} }, -{"and", 2, 0x80, 4, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, - -{"or", 2, 0x08, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"or", 2, 0x83, 1, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"or", 2, 0x0c, X, bwl_Suf|W, { Imm, Acc, 0} }, -{"or", 2, 0x80, 1, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, - -{"xor", 2, 0x30, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"xor", 2, 0x83, 6, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"xor", 2, 0x34, X, bwl_Suf|W, { Imm, Acc, 0} }, -{"xor", 2, 0x80, 6, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, +{"add", 2, 0x00, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"add", 2, 0x83, 0, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"add", 2, 0x04, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, +{"add", 2, 0x80, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, + +{"inc", 1, 0x40, X, CpuNo64,wl_Suf|ShortForm, { WordReg, 0, 0} }, +{"inc", 1, 0xfe, 0, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"sub", 2, 0x28, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"sub", 2, 0x83, 5, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"sub", 2, 0x2c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, +{"sub", 2, 0x80, 5, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, + +{"dec", 1, 0x48, X, CpuNo64, wl_Suf|ShortForm, { WordReg, 0, 0} }, +{"dec", 1, 0xfe, 1, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"sbb", 2, 0x18, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"sbb", 2, 0x83, 3, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"sbb", 2, 0x1c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, +{"sbb", 2, 0x80, 3, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, + +{"cmp", 2, 0x38, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"cmp", 2, 0x83, 7, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"cmp", 2, 0x3c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, +{"cmp", 2, 0x80, 7, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, + +{"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0} }, +{"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"test", 2, 0xa8, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, +{"test", 2, 0xf6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, + +{"and", 2, 0x20, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"and", 2, 0x83, 4, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"and", 2, 0x24, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, +{"and", 2, 0x80, 4, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, + +{"or", 2, 0x08, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"or", 2, 0x83, 1, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"or", 2, 0x0c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, +{"or", 2, 0x80, 1, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, + +{"xor", 2, 0x30, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"xor", 2, 0x83, 6, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"xor", 2, 0x34, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, +{"xor", 2, 0x80, 6, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, /* clr with 1 operand is really xor with 2 operands. */ -{"clr", 1, 0x30, X, bwl_Suf|W|Modrm|regKludge, { Reg, 0, 0 } }, +{"clr", 1, 0x30, X, 0, bwlq_Suf|W|Modrm|regKludge, { Reg, 0, 0 } }, -{"adc", 2, 0x10, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"adc", 2, 0x83, 2, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"adc", 2, 0x14, X, bwl_Suf|W, { Imm, Acc, 0} }, -{"adc", 2, 0x80, 2, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, +{"adc", 2, 0x10, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"adc", 2, 0x83, 2, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"adc", 2, 0x14, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, +{"adc", 2, 0x80, 2, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, -{"neg", 1, 0xf6, 3, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"not", 1, 0xf6, 2, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, +{"neg", 1, 0xf6, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, +{"not", 1, 0xf6, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"aaa", 0, 0x37, X, NoSuf, { 0, 0, 0} }, -{"aas", 0, 0x3f, X, NoSuf, { 0, 0, 0} }, -{"daa", 0, 0x27, X, NoSuf, { 0, 0, 0} }, -{"das", 0, 0x2f, X, NoSuf, { 0, 0, 0} }, -{"aad", 0, 0xd50a, X, NoSuf, { 0, 0, 0} }, -{"aad", 1, 0xd5, X, NoSuf, { Imm8S, 0, 0} }, -{"aam", 0, 0xd40a, X, NoSuf, { 0, 0, 0} }, -{"aam", 1, 0xd4, X, NoSuf, { Imm8S, 0, 0} }, +{"aaa", 0, 0x37, X, 0, NoSuf, { 0, 0, 0} }, +{"aas", 0, 0x3f, X, 0, NoSuf, { 0, 0, 0} }, +{"daa", 0, 0x27, X, 0, NoSuf, { 0, 0, 0} }, +{"das", 0, 0x2f, X, 0, NoSuf, { 0, 0, 0} }, +{"aad", 0, 0xd50a, X, 0, NoSuf, { 0, 0, 0} }, +{"aad", 1, 0xd5, X, 0, NoSuf, { Imm8S, 0, 0} }, +{"aam", 0, 0xd40a, X, 0, NoSuf, { 0, 0, 0} }, +{"aam", 1, 0xd4, X, 0, NoSuf, { Imm8S, 0, 0} }, /* Conversion insns. */ /* Intel naming */ -{"cbw", 0, 0x98, X, NoSuf|Size16, { 0, 0, 0} }, -{"cwde", 0, 0x98, X, NoSuf|Size32, { 0, 0, 0} }, -{"cwd", 0, 0x99, X, NoSuf|Size16, { 0, 0, 0} }, -{"cdq", 0, 0x99, X, NoSuf|Size32, { 0, 0, 0} }, +{"cbw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} }, +{"cdqe", 0, 0x98, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, +{"cwde", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} }, +{"cwd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} }, +{"cdq", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} }, +{"cqo", 0, 0x99, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, /* AT&T naming */ -{"cbtw", 0, 0x98, X, NoSuf|Size16, { 0, 0, 0} }, -{"cwtl", 0, 0x98, X, NoSuf|Size32, { 0, 0, 0} }, -{"cwtd", 0, 0x99, X, NoSuf|Size16, { 0, 0, 0} }, -{"cltd", 0, 0x99, X, NoSuf|Size32, { 0, 0, 0} }, +{"cbtw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} }, +{"cltq", 0, 0x98, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, +{"cwtl", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} }, +{"cwtd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} }, +{"cltd", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} }, +{"cqto", 0, 0x99, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are expanding 64-bit multiplies, and *cannot* be selected to accomplish 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) These multiplies can only be selected with single operand forms. */ -{"mul", 1, 0xf6, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"imul", 1, 0xf6, 5, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"imul", 2, 0x0faf, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"imul", 3, 0x6b, X, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, WordReg} }, -{"imul", 3, 0x69, X, wl_Suf|Modrm, { Imm16|Imm32, WordReg|WordMem, WordReg} }, +{"mul", 1, 0xf6, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, +{"imul", 1, 0xf6, 5, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, +{"imul", 2, 0x0faf, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"imul", 3, 0x6b, X, Cpu186, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, WordReg} }, +{"imul", 3, 0x69, X, Cpu186, wlq_Suf|Modrm, { Imm16|Imm32S|Imm32, WordReg|WordMem, WordReg} }, /* imul with 2 operands mimics imul with 3 by putting the register in both i.rm.reg & i.rm.regmem fields. regKludge enables this transformation. */ -{"imul", 2, 0x6b, X, wl_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} }, -{"imul", 2, 0x69, X, wl_Suf|Modrm|regKludge,{ Imm16|Imm32, WordReg, 0} }, - -{"div", 1, 0xf6, 6, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"div", 2, 0xf6, 6, bwl_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, -{"idiv", 1, 0xf6, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"idiv", 2, 0xf6, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, - -{"rol", 2, 0xd0, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"rol", 2, 0xc0, 0, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"rol", 2, 0xd2, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"rol", 1, 0xd0, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"ror", 2, 0xd0, 1, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"ror", 2, 0xc0, 1, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"ror", 2, 0xd2, 1, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"ror", 1, 0xd0, 1, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"rcl", 2, 0xd0, 2, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"rcl", 2, 0xc0, 2, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"rcl", 2, 0xd2, 2, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"rcl", 1, 0xd0, 2, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"rcr", 2, 0xd0, 3, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"rcr", 2, 0xc0, 3, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"rcr", 2, 0xd2, 3, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"rcr", 1, 0xd0, 3, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"sal", 2, 0xd0, 4, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"sal", 2, 0xc0, 4, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"sal", 2, 0xd2, 4, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"sal", 1, 0xd0, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"shl", 2, 0xd0, 4, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"shl", 2, 0xc0, 4, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"shl", 2, 0xd2, 4, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"shl", 1, 0xd0, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"shr", 2, 0xd0, 5, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"shr", 2, 0xc0, 5, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"shr", 2, 0xd2, 5, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"shr", 1, 0xd0, 5, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"sar", 2, 0xd0, 7, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"sar", 2, 0xc0, 7, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"sar", 2, 0xd2, 7, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"sar", 1, 0xd0, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"shld", 3, 0x0fa4, X, wl_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, -{"shld", 3, 0x0fa5, X, wl_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, -{"shld", 2, 0x0fa5, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, - -{"shrd", 3, 0x0fac, X, wl_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, -{"shrd", 3, 0x0fad, X, wl_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, -{"shrd", 2, 0x0fad, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, +{"imul", 2, 0x6b, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} }, +{"imul", 2, 0x69, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm16|Imm32S|Imm32, WordReg, 0} }, + +{"div", 1, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, +{"div", 2, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, +{"idiv", 1, 0xf6, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, +{"idiv", 2, 0xf6, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, + +{"rol", 2, 0xd0, 0, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"rol", 2, 0xc0, 0, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"rol", 2, 0xd2, 0, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"rol", 1, 0xd0, 0, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"ror", 2, 0xd0, 1, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"ror", 2, 0xc0, 1, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"ror", 2, 0xd2, 1, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"ror", 1, 0xd0, 1, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"rcl", 2, 0xd0, 2, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"rcl", 2, 0xc0, 2, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"rcl", 2, 0xd2, 2, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"rcl", 1, 0xd0, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"rcr", 2, 0xd0, 3, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"rcr", 2, 0xc0, 3, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"rcr", 2, 0xd2, 3, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"rcr", 1, 0xd0, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"sal", 2, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"sal", 2, 0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"sal", 2, 0xd2, 4, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"sal", 1, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"shl", 2, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"shl", 2, 0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"shl", 2, 0xd2, 4, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"shl", 1, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"shr", 2, 0xd0, 5, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"shr", 2, 0xc0, 5, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"shr", 2, 0xd2, 5, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"shr", 1, 0xd0, 5, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"sar", 2, 0xd0, 7, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"sar", 2, 0xc0, 7, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"sar", 2, 0xd2, 7, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"sar", 1, 0xd0, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"shld", 3, 0x0fa4, X, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, +{"shld", 3, 0x0fa5, X, Cpu386, wlq_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, +{"shld", 2, 0x0fa5, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, + +{"shrd", 3, 0x0fac, X, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, +{"shrd", 3, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, +{"shrd", 2, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, /* Control transfer instructions. */ -{"call", 1, 0xe8, X, wl_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} }, -{"call", 1, 0xff, 2, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} }, +{"call", 1, 0xe8, X, 0, wlq_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} }, +{"call", 1, 0xff, 2, 0, wlq_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} }, /* Intel Syntax */ -{"call", 2, 0x9a, X, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, +{"call", 2, 0x9a, X, CpuNo64,wlq_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, /* Intel Syntax */ -{"call", 1, 0xff, 3, x_Suf|Modrm|DefaultSize, { WordMem, 0, 0} }, -{"lcall", 2, 0x9a, X, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, -{"lcall", 1, 0xff, 3, wl_Suf|Modrm|DefaultSize, { WordMem|JumpAbsolute, 0, 0} }, +{"call", 1, 0xff, 3, 0, x_Suf|Modrm|DefaultSize, { WordMem, 0, 0} }, +{"lcall", 2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, +{"lcall", 1, 0xff, 3, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordMem|JumpAbsolute, 0, 0} }, +{"lcall", 1, 0xff, 3, Cpu64, q_Suf|Modrm|DefaultSize|NoRex64,{ WordMem|JumpAbsolute, 0, 0} }, #define JUMP_PC_RELATIVE 0xeb -{"jmp", 1, 0xeb, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jmp", 1, 0xff, 4, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} }, +{"jmp", 1, 0xeb, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jmp", 1, 0xff, 4, 0, wlq_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} }, /* Intel Syntax */ -{"jmp", 2, 0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, +{"jmp", 2, 0xea, X, CpuNo64,wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, /* Intel Syntax */ -{"jmp", 1, 0xff, 5, x_Suf|Modrm, { WordMem, 0, 0} }, -{"ljmp", 2, 0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, -{"ljmp", 1, 0xff, 5, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} }, - -{"ret", 0, 0xc3, X, wl_Suf|DefaultSize, { 0, 0, 0} }, -{"ret", 1, 0xc2, X, wl_Suf|DefaultSize, { Imm16, 0, 0} }, -{"lret", 0, 0xcb, X, wl_Suf|DefaultSize, { 0, 0, 0} }, -{"lret", 1, 0xca, X, wl_Suf|DefaultSize, { Imm16, 0, 0} }, -{"enter", 2, 0xc8, X, wl_Suf|DefaultSize, { Imm16, Imm8, 0} }, -{"leave", 0, 0xc9, X, wl_Suf|DefaultSize, { 0, 0, 0} }, +{"jmp", 1, 0xff, 5, 0, x_Suf|Modrm, { WordMem, 0, 0} }, +{"ljmp", 2, 0xea, X, CpuNo64, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, +{"ljmp", 1, 0xff, 5, CpuNo64, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} }, +{"ljmp", 1, 0xff, 5, Cpu64, q_Suf|Modrm|NoRex64, { WordMem|JumpAbsolute, 0, 0} }, + +{"ret", 0, 0xc3, X, CpuNo64,wlq_Suf|DefaultSize, { 0, 0, 0} }, +{"ret", 1, 0xc2, X, CpuNo64,wlq_Suf|DefaultSize, { Imm16, 0, 0} }, +{"ret", 0, 0xc3, X, Cpu64, q_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, +{"ret", 1, 0xc2, X, Cpu64, q_Suf|DefaultSize|NoRex64,{ Imm16, 0, 0} }, +{"lret", 0, 0xcb, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} }, +{"lret", 1, 0xca, X, 0, wlq_Suf|DefaultSize, { Imm16, 0, 0} }, +{"enter", 2, 0xc8, X, Cpu186, wlq_Suf|DefaultSize, { Imm16, Imm8, 0} }, +{"leave", 0, 0xc9, X, Cpu186, wlq_Suf|DefaultSize, { 0, 0, 0} }, /* Conditional jumps. */ -{"jo", 1, 0x70, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jno", 1, 0x71, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jb", 1, 0x72, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jc", 1, 0x72, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jnae", 1, 0x72, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jnb", 1, 0x73, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jnc", 1, 0x73, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jae", 1, 0x73, X, NoSuf|Jump, { Disp, 0, 0} }, -{"je", 1, 0x74, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jz", 1, 0x74, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jne", 1, 0x75, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jnz", 1, 0x75, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jbe", 1, 0x76, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jna", 1, 0x76, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jnbe", 1, 0x77, X, NoSuf|Jump, { Disp, 0, 0} }, -{"ja", 1, 0x77, X, NoSuf|Jump, { Disp, 0, 0} }, -{"js", 1, 0x78, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jns", 1, 0x79, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jp", 1, 0x7a, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jpe", 1, 0x7a, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jnp", 1, 0x7b, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jpo", 1, 0x7b, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jl", 1, 0x7c, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jnge", 1, 0x7c, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jnl", 1, 0x7d, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jge", 1, 0x7d, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jle", 1, 0x7e, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jng", 1, 0x7e, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jnle", 1, 0x7f, X, NoSuf|Jump, { Disp, 0, 0} }, -{"jg", 1, 0x7f, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jo", 1, 0x70, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jno", 1, 0x71, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jb", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jc", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jnae", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jnb", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jnc", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jae", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"je", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jz", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jne", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jnz", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jbe", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jna", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jnbe", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"ja", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"js", 1, 0x78, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jns", 1, 0x79, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jp", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jpe", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jnp", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jpo", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jl", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jnge", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jnl", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jge", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jle", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jng", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jnle", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jg", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} }, /* jcxz vs. jecxz is chosen on the basis of the address size prefix. */ -{"jcxz", 1, 0xe3, X, NoSuf|JumpByte|Size16, { Disp, 0, 0} }, -{"jecxz", 1, 0xe3, X, NoSuf|JumpByte|Size32, { Disp, 0, 0} }, +{"jcxz", 1, 0xe3, X, 0, NoSuf|JumpByte|Size16, { Disp, 0, 0} }, +{"jecxz", 1, 0xe3, X, 0, NoSuf|JumpByte|Size32, { Disp, 0, 0} }, /* The loop instructions also use the address size prefix to select %cx rather than %ecx for the loop count, so the `w' form of these instructions emit an address size prefix rather than a data size prefix. */ -{"loop", 1, 0xe2, X, wl_Suf|JumpByte, { Disp, 0, 0} }, -{"loopz", 1, 0xe1, X, wl_Suf|JumpByte, { Disp, 0, 0} }, -{"loope", 1, 0xe1, X, wl_Suf|JumpByte, { Disp, 0, 0} }, -{"loopnz", 1, 0xe0, X, wl_Suf|JumpByte, { Disp, 0, 0} }, -{"loopne", 1, 0xe0, X, wl_Suf|JumpByte, { Disp, 0, 0} }, +{"loop", 1, 0xe2, X, 0, wlq_Suf|JumpByte, { Disp, 0, 0} }, +{"loopz", 1, 0xe1, X, 0, wlq_Suf|JumpByte, { Disp, 0, 0} }, +{"loope", 1, 0xe1, X, 0, wlq_Suf|JumpByte, { Disp, 0, 0} }, +{"loopnz", 1, 0xe0, X, 0, wlq_Suf|JumpByte, { Disp, 0, 0} }, +{"loopne", 1, 0xe0, X, 0, wlq_Suf|JumpByte, { Disp, 0, 0} }, /* Set byte on flag instructions. */ -{"seto", 1, 0x0f90, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setno", 1, 0x0f91, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setb", 1, 0x0f92, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setc", 1, 0x0f92, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnae", 1, 0x0f92, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnb", 1, 0x0f93, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnc", 1, 0x0f93, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setae", 1, 0x0f93, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"sete", 1, 0x0f94, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setz", 1, 0x0f94, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setne", 1, 0x0f95, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnz", 1, 0x0f95, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setbe", 1, 0x0f96, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setna", 1, 0x0f96, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnbe", 1, 0x0f97, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"seta", 1, 0x0f97, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"sets", 1, 0x0f98, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setns", 1, 0x0f99, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setp", 1, 0x0f9a, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setpe", 1, 0x0f9a, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnp", 1, 0x0f9b, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setpo", 1, 0x0f9b, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setl", 1, 0x0f9c, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnge", 1, 0x0f9c, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnl", 1, 0x0f9d, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setge", 1, 0x0f9d, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setle", 1, 0x0f9e, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setng", 1, 0x0f9e, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnle", 1, 0x0f9f, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setg", 1, 0x0f9f, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"seto", 1, 0x0f90, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setno", 1, 0x0f91, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setb", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setc", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnae", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnb", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnc", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setae", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"sete", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setz", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setne", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnz", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setbe", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setna", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnbe", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"seta", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"sets", 1, 0x0f98, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setns", 1, 0x0f99, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setp", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setpe", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnp", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setpo", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setl", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnge", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnl", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setge", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setle", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setng", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnle", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setg", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, /* String manipulation. */ -{"cmps", 0, 0xa6, X, bwld_Suf|W|IsString, { 0, 0, 0} }, -{"cmps", 2, 0xa6, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, -{"scmp", 0, 0xa6, X, bwld_Suf|W|IsString, { 0, 0, 0} }, -{"scmp", 2, 0xa6, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, -{"ins", 0, 0x6c, X, bwld_Suf|W|IsString, { 0, 0, 0} }, -{"ins", 2, 0x6c, X, bwld_Suf|W|IsString, { InOutPortReg, AnyMem|EsSeg, 0} }, -{"outs", 0, 0x6e, X, bwld_Suf|W|IsString, { 0, 0, 0} }, -{"outs", 2, 0x6e, X, bwld_Suf|W|IsString, { AnyMem, InOutPortReg, 0} }, -{"lods", 0, 0xac, X, bwld_Suf|W|IsString, { 0, 0, 0} }, -{"lods", 1, 0xac, X, bwld_Suf|W|IsString, { AnyMem, 0, 0} }, -{"lods", 2, 0xac, X, bwld_Suf|W|IsString, { AnyMem, Acc, 0} }, -{"slod", 0, 0xac, X, bwld_Suf|W|IsString, { 0, 0, 0} }, -{"slod", 1, 0xac, X, bwld_Suf|W|IsString, { AnyMem, 0, 0} }, -{"slod", 2, 0xac, X, bwld_Suf|W|IsString, { AnyMem, Acc, 0} }, -{"movs", 0, 0xa4, X, bwld_Suf|W|IsString, { 0, 0, 0} }, -{"movs", 2, 0xa4, X, bwld_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, -{"smov", 0, 0xa4, X, bwld_Suf|W|IsString, { 0, 0, 0} }, -{"smov", 2, 0xa4, X, bwld_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, -{"scas", 0, 0xae, X, bwld_Suf|W|IsString, { 0, 0, 0} }, -{"scas", 1, 0xae, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, -{"scas", 2, 0xae, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, -{"ssca", 0, 0xae, X, bwld_Suf|W|IsString, { 0, 0, 0} }, -{"ssca", 1, 0xae, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, -{"ssca", 2, 0xae, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, -{"stos", 0, 0xaa, X, bwld_Suf|W|IsString, { 0, 0, 0} }, -{"stos", 1, 0xaa, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, -{"stos", 2, 0xaa, X, bwld_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, -{"ssto", 0, 0xaa, X, bwld_Suf|W|IsString, { 0, 0, 0} }, -{"ssto", 1, 0xaa, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, -{"ssto", 2, 0xaa, X, bwld_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, -{"xlat", 0, 0xd7, X, b_Suf|IsString, { 0, 0, 0} }, -{"xlat", 1, 0xd7, X, b_Suf|IsString, { AnyMem, 0, 0} }, +{"cmps", 0, 0xa6, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, +{"cmps", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, +{"scmp", 0, 0xa6, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, +{"scmp", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, +{"ins", 0, 0x6c, X, Cpu186, bwlq_Suf|W|IsString, { 0, 0, 0} }, +{"ins", 2, 0x6c, X, Cpu186, bwlq_Suf|W|IsString, { InOutPortReg, AnyMem|EsSeg, 0} }, +{"outs", 0, 0x6e, X, Cpu186, bwlq_Suf|W|IsString, { 0, 0, 0} }, +{"outs", 2, 0x6e, X, Cpu186, bwlq_Suf|W|IsString, { AnyMem, InOutPortReg, 0} }, +{"lods", 0, 0xac, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, +{"lods", 1, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, 0, 0} }, +{"lods", 2, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, Acc, 0} }, +{"slod", 0, 0xac, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, +{"slod", 1, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, 0, 0} }, +{"slod", 2, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, Acc, 0} }, +{"movs", 0, 0xa4, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, +{"movs", 2, 0xa4, X, 0, bwlq_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, +{"smov", 0, 0xa4, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, +{"smov", 2, 0xa4, X, 0, bwlq_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, +{"scas", 0, 0xae, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, +{"scas", 1, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, +{"scas", 2, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, +{"ssca", 0, 0xae, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, +{"ssca", 1, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, +{"ssca", 2, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, +{"stos", 0, 0xaa, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, +{"stos", 1, 0xaa, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, +{"stos", 2, 0xaa, X, 0, bwlq_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, +{"ssto", 0, 0xaa, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, +{"ssto", 1, 0xaa, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, +{"ssto", 2, 0xaa, X, 0, bwlq_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, +{"xlat", 0, 0xd7, X, 0, b_Suf|IsString, { 0, 0, 0} }, +{"xlat", 1, 0xd7, X, 0, b_Suf|IsString, { AnyMem, 0, 0} }, /* Bit manipulation. */ -{"bsf", 2, 0x0fbc, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"bsr", 2, 0x0fbd, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"bt", 2, 0x0fa3, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, -{"bt", 2, 0x0fba, 4, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, -{"btc", 2, 0x0fbb, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, -{"btc", 2, 0x0fba, 7, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, -{"btr", 2, 0x0fb3, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, -{"btr", 2, 0x0fba, 6, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, -{"bts", 2, 0x0fab, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, -{"bts", 2, 0x0fba, 5, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, +{"bsf", 2, 0x0fbc, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"bsr", 2, 0x0fbd, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"bt", 2, 0x0fa3, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, +{"bt", 2, 0x0fba, 4, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, +{"btc", 2, 0x0fbb, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, +{"btc", 2, 0x0fba, 7, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, +{"btr", 2, 0x0fb3, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, +{"btr", 2, 0x0fba, 6, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, +{"bts", 2, 0x0fab, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, +{"bts", 2, 0x0fba, 5, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, /* Interrupts & op. sys insns. */ /* See gas/config/tc-i386.c for conversion of 'int $3' into the special int 3 insn. */ #define INT_OPCODE 0xcd #define INT3_OPCODE 0xcc -{"int", 1, 0xcd, X, NoSuf, { Imm8, 0, 0} }, -{"int3", 0, 0xcc, X, NoSuf, { 0, 0, 0} }, -{"into", 0, 0xce, X, NoSuf, { 0, 0, 0} }, -{"iret", 0, 0xcf, X, wld_Suf|DefaultSize, { 0, 0, 0} }, +{"int", 1, 0xcd, X, 0, NoSuf, { Imm8, 0, 0} }, +{"int3", 0, 0xcc, X, 0, NoSuf, { 0, 0, 0} }, +{"into", 0, 0xce, X, 0, NoSuf, { 0, 0, 0} }, +{"iret", 0, 0xcf, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} }, /* i386sl, i486sl, later 486, and Pentium. */ -{"rsm", 0, 0x0faa, X, NoSuf, { 0, 0, 0} }, +{"rsm", 0, 0x0faa, X, Cpu386, NoSuf, { 0, 0, 0} }, -{"bound", 2, 0x62, X, wl_Suf|Modrm, { WordReg, WordMem, 0} }, +{"bound", 2, 0x62, X, Cpu186, wlq_Suf|Modrm, { WordReg, WordMem, 0} }, -{"hlt", 0, 0xf4, X, NoSuf, { 0, 0, 0} }, +{"hlt", 0, 0xf4, X, 0, NoSuf, { 0, 0, 0} }, /* nop is actually 'xchgl %eax, %eax'. */ -{"nop", 0, 0x90, X, NoSuf, { 0, 0, 0} }, +{"nop", 0, 0x90, X, 0, NoSuf, { 0, 0, 0} }, /* Protection control. */ -{"arpl", 2, 0x63, X, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} }, -{"lar", 2, 0x0f02, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"lgdt", 1, 0x0f01, 2, wl_Suf|Modrm, { WordMem, 0, 0} }, -{"lidt", 1, 0x0f01, 3, wl_Suf|Modrm, { WordMem, 0, 0} }, -{"lldt", 1, 0x0f00, 2, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"lmsw", 1, 0x0f01, 6, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"lsl", 2, 0x0f03, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"ltr", 1, 0x0f00, 3, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, - -{"sgdt", 1, 0x0f01, 0, wl_Suf|Modrm, { WordMem, 0, 0} }, -{"sidt", 1, 0x0f01, 1, wl_Suf|Modrm, { WordMem, 0, 0} }, -{"sldt", 1, 0x0f00, 0, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} }, -{"smsw", 1, 0x0f01, 4, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} }, -{"str", 1, 0x0f00, 1, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, - -{"verr", 1, 0x0f00, 4, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"verw", 1, 0x0f00, 5, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"arpl", 2, 0x63, X, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} }, +{"lar", 2, 0x0f02, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"lgdt", 1, 0x0f01, 2, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} }, +{"lidt", 1, 0x0f01, 3, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} }, +{"lldt", 1, 0x0f00, 2, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"lmsw", 1, 0x0f01, 6, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"lsl", 2, 0x0f03, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"ltr", 1, 0x0f00, 3, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, + +{"sgdt", 1, 0x0f01, 0, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} }, +{"sidt", 1, 0x0f01, 1, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} }, +{"sldt", 1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, 0, 0} }, +{"smsw", 1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, 0, 0} }, +{"str", 1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, + +{"verr", 1, 0x0f00, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"verw", 1, 0x0f00, 5, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, /* Floating point instructions. */ /* load */ -{"fld", 1, 0xd9c0, X, FP|ShortForm, { FloatReg, 0, 0} }, -{"fld", 1, 0xd9, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fld", 1, 0xd9c0, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, +{"fld", 1, 0xd9c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fld", 1, 0xd9, 0, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fld", 1, 0xd9c0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, /* Intel Syntax */ -{"fld", 1, 0xdb, 5, x_FP|Modrm, { LLongMem, 0, 0} }, -{"fild", 1, 0xdf, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fld", 1, 0xdb, 5, 0, x_FP|Modrm, { LLongMem, 0, 0} }, +{"fild", 1, 0xdf, 0, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* Intel Syntax */ -{"fildd", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, -{"fildq", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, -{"fildll", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, -{"fldt", 1, 0xdb, 5, FP|Modrm, { LLongMem, 0, 0} }, -{"fbld", 1, 0xdf, 4, FP|Modrm, { LLongMem, 0, 0} }, +{"fildd", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, +{"fildq", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, +{"fildll", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, +{"fldt", 1, 0xdb, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, +{"fbld", 1, 0xdf, 4, 0, FP|Modrm, { LLongMem, 0, 0} }, /* store (no pop) */ -{"fst", 1, 0xddd0, X, FP|ShortForm, { FloatReg, 0, 0} }, -{"fst", 1, 0xd9, 2, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fst", 1, 0xddd0, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, -{"fist", 1, 0xdf, 2, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fst", 1, 0xddd0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fst", 1, 0xd9, 2, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fst", 1, 0xddd0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, +{"fist", 1, 0xdf, 2, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* store (with pop) */ -{"fstp", 1, 0xddd8, X, FP|ShortForm, { FloatReg, 0, 0} }, -{"fstp", 1, 0xd9, 3, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fstp", 1, 0xddd8, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, +{"fstp", 1, 0xddd8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fstp", 1, 0xd9, 3, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fstp", 1, 0xddd8, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, /* Intel Syntax */ -{"fstp", 1, 0xdb, 7, x_FP|Modrm, { LLongMem, 0, 0} }, -{"fistp", 1, 0xdf, 3, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fstp", 1, 0xdb, 7, 0, x_FP|Modrm, { LLongMem, 0, 0} }, +{"fistp", 1, 0xdf, 3, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* Intel Syntax */ -{"fistpd", 1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, -{"fistpq", 1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, -{"fistpll",1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, -{"fstpt", 1, 0xdb, 7, FP|Modrm, { LLongMem, 0, 0} }, -{"fbstp", 1, 0xdf, 6, FP|Modrm, { LLongMem, 0, 0} }, +{"fistpd", 1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, +{"fistpq", 1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, +{"fistpll",1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, +{"fstpt", 1, 0xdb, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, +{"fbstp", 1, 0xdf, 6, 0, FP|Modrm, { LLongMem, 0, 0} }, /* exchange %st<n> with %st0 */ -{"fxch", 1, 0xd9c8, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fxch", 1, 0xd9c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, /* alias for fxch %st(1) */ -{"fxch", 0, 0xd9c9, X, FP, { 0, 0, 0} }, +{"fxch", 0, 0xd9c9, X, 0, FP, { 0, 0, 0} }, /* comparison (without pop) */ -{"fcom", 1, 0xd8d0, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fcom", 1, 0xd8d0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, /* alias for fcom %st(1) */ -{"fcom", 0, 0xd8d1, X, FP, { 0, 0, 0} }, -{"fcom", 1, 0xd8, 2, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fcom", 1, 0xd8d0, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, -{"ficom", 1, 0xde, 2, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fcom", 0, 0xd8d1, X, 0, FP, { 0, 0, 0} }, +{"fcom", 1, 0xd8, 2, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fcom", 1, 0xd8d0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, +{"ficom", 1, 0xde, 2, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* comparison (with pop) */ -{"fcomp", 1, 0xd8d8, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fcomp", 1, 0xd8d8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, /* alias for fcomp %st(1) */ -{"fcomp", 0, 0xd8d9, X, FP, { 0, 0, 0} }, -{"fcomp", 1, 0xd8, 3, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fcomp", 1, 0xd8d8, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, -{"ficomp", 1, 0xde, 3, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, -{"fcompp", 0, 0xded9, X, FP, { 0, 0, 0} }, +{"fcomp", 0, 0xd8d9, X, 0, FP, { 0, 0, 0} }, +{"fcomp", 1, 0xd8, 3, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fcomp", 1, 0xd8d8, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, +{"ficomp", 1, 0xde, 3, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fcompp", 0, 0xded9, X, 0, FP, { 0, 0, 0} }, /* unordered comparison (with pop) */ -{"fucom", 1, 0xdde0, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fucom", 1, 0xdde0, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} }, /* alias for fucom %st(1) */ -{"fucom", 0, 0xdde1, X, FP, { 0, 0, 0} }, -{"fucomp", 1, 0xdde8, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fucom", 0, 0xdde1, X, Cpu286, FP, { 0, 0, 0} }, +{"fucomp", 1, 0xdde8, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} }, /* alias for fucomp %st(1) */ -{"fucomp", 0, 0xdde9, X, FP, { 0, 0, 0} }, -{"fucompp",0, 0xdae9, X, FP, { 0, 0, 0} }, +{"fucomp", 0, 0xdde9, X, Cpu286, FP, { 0, 0, 0} }, +{"fucompp",0, 0xdae9, X, Cpu286, FP, { 0, 0, 0} }, -{"ftst", 0, 0xd9e4, X, FP, { 0, 0, 0} }, -{"fxam", 0, 0xd9e5, X, FP, { 0, 0, 0} }, +{"ftst", 0, 0xd9e4, X, 0, FP, { 0, 0, 0} }, +{"fxam", 0, 0xd9e5, X, 0, FP, { 0, 0, 0} }, /* load constants into %st0 */ -{"fld1", 0, 0xd9e8, X, FP, { 0, 0, 0} }, -{"fldl2t", 0, 0xd9e9, X, FP, { 0, 0, 0} }, -{"fldl2e", 0, 0xd9ea, X, FP, { 0, 0, 0} }, -{"fldpi", 0, 0xd9eb, X, FP, { 0, 0, 0} }, -{"fldlg2", 0, 0xd9ec, X, FP, { 0, 0, 0} }, -{"fldln2", 0, 0xd9ed, X, FP, { 0, 0, 0} }, -{"fldz", 0, 0xd9ee, X, FP, { 0, 0, 0} }, +{"fld1", 0, 0xd9e8, X, 0, FP, { 0, 0, 0} }, +{"fldl2t", 0, 0xd9e9, X, 0, FP, { 0, 0, 0} }, +{"fldl2e", 0, 0xd9ea, X, 0, FP, { 0, 0, 0} }, +{"fldpi", 0, 0xd9eb, X, 0, FP, { 0, 0, 0} }, +{"fldlg2", 0, 0xd9ec, X, 0, FP, { 0, 0, 0} }, +{"fldln2", 0, 0xd9ed, X, 0, FP, { 0, 0, 0} }, +{"fldz", 0, 0xd9ee, X, 0, FP, { 0, 0, 0} }, /* arithmetic */ /* add */ -{"fadd", 2, 0xd8c0, X, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, +{"fadd", 2, 0xd8c0, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, /* alias for fadd %st(i), %st */ -{"fadd", 1, 0xd8c0, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fadd", 1, 0xd8c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, #if SYSV386_COMPAT /* alias for faddp */ -{"fadd", 0, 0xdec1, X, FP|Ugh, { 0, 0, 0} }, +{"fadd", 0, 0xdec1, X, 0, FP|Ugh, { 0, 0, 0} }, #endif -{"fadd", 1, 0xd8, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fiadd", 1, 0xde, 0, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fadd", 1, 0xd8, 0, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fiadd", 1, 0xde, 0, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, -{"faddp", 2, 0xdec0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"faddp", 1, 0xdec0, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"faddp", 2, 0xdec0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"faddp", 1, 0xdec0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, /* alias for faddp %st, %st(1) */ -{"faddp", 0, 0xdec1, X, FP, { 0, 0, 0} }, -{"faddp", 2, 0xdec0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, +{"faddp", 0, 0xdec1, X, 0, FP, { 0, 0, 0} }, +{"faddp", 2, 0xdec0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, /* subtract */ -{"fsub", 2, 0xd8e0, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, -{"fsub", 1, 0xd8e0, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fsub", 2, 0xd8e0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, +{"fsub", 1, 0xd8e0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, #if SYSV386_COMPAT /* alias for fsubp */ -{"fsub", 0, 0xdee1, X, FP|Ugh, { 0, 0, 0} }, +{"fsub", 0, 0xdee1, X, 0, FP|Ugh, { 0, 0, 0} }, #endif -{"fsub", 1, 0xd8, 4, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fisub", 1, 0xde, 4, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fsub", 1, 0xd8, 4, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fisub", 1, 0xde, 4, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, #if SYSV386_COMPAT -{"fsubp", 2, 0xdee0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fsubp", 1, 0xdee0, X, FP|ShortForm, { FloatReg, 0, 0} }, -{"fsubp", 0, 0xdee1, X, FP, { 0, 0, 0} }, +{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fsubp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fsubp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} }, #if OLDGCC_COMPAT -{"fsubp", 2, 0xdee0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, +{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, #endif #else -{"fsubp", 2, 0xdee8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fsubp", 1, 0xdee8, X, FP|ShortForm, { FloatReg, 0, 0} }, -{"fsubp", 0, 0xdee9, X, FP, { 0, 0, 0} }, +{"fsubp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fsubp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fsubp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} }, #endif /* subtract reverse */ -{"fsubr", 2, 0xd8e8, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, -{"fsubr", 1, 0xd8e8, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fsubr", 2, 0xd8e8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, +{"fsubr", 1, 0xd8e8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, #if SYSV386_COMPAT /* alias for fsubrp */ -{"fsubr", 0, 0xdee9, X, FP|Ugh, { 0, 0, 0} }, +{"fsubr", 0, 0xdee9, X, 0, FP|Ugh, { 0, 0, 0} }, #endif -{"fsubr", 1, 0xd8, 5, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fisubr", 1, 0xde, 5, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fsubr", 1, 0xd8, 5, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fisubr", 1, 0xde, 5, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, #if SYSV386_COMPAT -{"fsubrp", 2, 0xdee8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fsubrp", 1, 0xdee8, X, FP|ShortForm, { FloatReg, 0, 0} }, -{"fsubrp", 0, 0xdee9, X, FP, { 0, 0, 0} }, +{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fsubrp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fsubrp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} }, #if OLDGCC_COMPAT -{"fsubrp", 2, 0xdee8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, +{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, #endif #else -{"fsubrp", 2, 0xdee0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fsubrp", 1, 0xdee0, X, FP|ShortForm, { FloatReg, 0, 0} }, -{"fsubrp", 0, 0xdee1, X, FP, { 0, 0, 0} }, +{"fsubrp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fsubrp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fsubrp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} }, #endif /* multiply */ -{"fmul", 2, 0xd8c8, X, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, -{"fmul", 1, 0xd8c8, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fmul", 2, 0xd8c8, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, +{"fmul", 1, 0xd8c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, #if SYSV386_COMPAT /* alias for fmulp */ -{"fmul", 0, 0xdec9, X, FP|Ugh, { 0, 0, 0} }, +{"fmul", 0, 0xdec9, X, 0, FP|Ugh, { 0, 0, 0} }, #endif -{"fmul", 1, 0xd8, 1, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fimul", 1, 0xde, 1, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fmul", 1, 0xd8, 1, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fimul", 1, 0xde, 1, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, -{"fmulp", 2, 0xdec8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fmulp", 1, 0xdec8, X, FP|ShortForm, { FloatReg, 0, 0} }, -{"fmulp", 0, 0xdec9, X, FP, { 0, 0, 0} }, -{"fmulp", 2, 0xdec8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, +{"fmulp", 2, 0xdec8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fmulp", 1, 0xdec8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fmulp", 0, 0xdec9, X, 0, FP, { 0, 0, 0} }, +{"fmulp", 2, 0xdec8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, /* divide */ -{"fdiv", 2, 0xd8f0, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, -{"fdiv", 1, 0xd8f0, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fdiv", 2, 0xd8f0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, +{"fdiv", 1, 0xd8f0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, #if SYSV386_COMPAT /* alias for fdivp */ -{"fdiv", 0, 0xdef1, X, FP|Ugh, { 0, 0, 0} }, +{"fdiv", 0, 0xdef1, X, 0, FP|Ugh, { 0, 0, 0} }, #endif -{"fdiv", 1, 0xd8, 6, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fidiv", 1, 0xde, 6, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fdiv", 1, 0xd8, 6, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fidiv", 1, 0xde, 6, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, #if SYSV386_COMPAT -{"fdivp", 2, 0xdef0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fdivp", 1, 0xdef0, X, FP|ShortForm, { FloatReg, 0, 0} }, -{"fdivp", 0, 0xdef1, X, FP, { 0, 0, 0} }, +{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fdivp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fdivp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} }, #if OLDGCC_COMPAT -{"fdivp", 2, 0xdef0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, +{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, #endif #else -{"fdivp", 2, 0xdef8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fdivp", 1, 0xdef8, X, FP|ShortForm, { FloatReg, 0, 0} }, -{"fdivp", 0, 0xdef9, X, FP, { 0, 0, 0} }, +{"fdivp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fdivp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fdivp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} }, #endif /* divide reverse */ -{"fdivr", 2, 0xd8f8, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, -{"fdivr", 1, 0xd8f8, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fdivr", 2, 0xd8f8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, +{"fdivr", 1, 0xd8f8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, #if SYSV386_COMPAT /* alias for fdivrp */ -{"fdivr", 0, 0xdef9, X, FP|Ugh, { 0, 0, 0} }, +{"fdivr", 0, 0xdef9, X, 0, FP|Ugh, { 0, 0, 0} }, #endif -{"fdivr", 1, 0xd8, 7, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fidivr", 1, 0xde, 7, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fdivr", 1, 0xd8, 7, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fidivr", 1, 0xde, 7, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, #if SYSV386_COMPAT -{"fdivrp", 2, 0xdef8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fdivrp", 1, 0xdef8, X, FP|ShortForm, { FloatReg, 0, 0} }, -{"fdivrp", 0, 0xdef9, X, FP, { 0, 0, 0} }, +{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fdivrp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fdivrp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} }, #if OLDGCC_COMPAT -{"fdivrp", 2, 0xdef8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, +{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, #endif #else -{"fdivrp", 2, 0xdef0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fdivrp", 1, 0xdef0, X, FP|ShortForm, { FloatReg, 0, 0} }, -{"fdivrp", 0, 0xdef1, X, FP, { 0, 0, 0} }, +{"fdivrp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fdivrp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, +{"fdivrp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} }, #endif -{"f2xm1", 0, 0xd9f0, X, FP, { 0, 0, 0} }, -{"fyl2x", 0, 0xd9f1, X, FP, { 0, 0, 0} }, -{"fptan", 0, 0xd9f2, X, FP, { 0, 0, 0} }, -{"fpatan", 0, 0xd9f3, X, FP, { 0, 0, 0} }, -{"fxtract",0, 0xd9f4, X, FP, { 0, 0, 0} }, -{"fprem1", 0, 0xd9f5, X, FP, { 0, 0, 0} }, -{"fdecstp",0, 0xd9f6, X, FP, { 0, 0, 0} }, -{"fincstp",0, 0xd9f7, X, FP, { 0, 0, 0} }, -{"fprem", 0, 0xd9f8, X, FP, { 0, 0, 0} }, -{"fyl2xp1",0, 0xd9f9, X, FP, { 0, 0, 0} }, -{"fsqrt", 0, 0xd9fa, X, FP, { 0, 0, 0} }, -{"fsincos",0, 0xd9fb, X, FP, { 0, 0, 0} }, -{"frndint",0, 0xd9fc, X, FP, { 0, 0, 0} }, -{"fscale", 0, 0xd9fd, X, FP, { 0, 0, 0} }, -{"fsin", 0, 0xd9fe, X, FP, { 0, 0, 0} }, -{"fcos", 0, 0xd9ff, X, FP, { 0, 0, 0} }, -{"fchs", 0, 0xd9e0, X, FP, { 0, 0, 0} }, -{"fabs", 0, 0xd9e1, X, FP, { 0, 0, 0} }, +{"f2xm1", 0, 0xd9f0, X, 0, FP, { 0, 0, 0} }, +{"fyl2x", 0, 0xd9f1, X, 0, FP, { 0, 0, 0} }, +{"fptan", 0, 0xd9f2, X, 0, FP, { 0, 0, 0} }, +{"fpatan", 0, 0xd9f3, X, 0, FP, { 0, 0, 0} }, +{"fxtract",0, 0xd9f4, X, 0, FP, { 0, 0, 0} }, +{"fprem1", 0, 0xd9f5, X, Cpu286, FP, { 0, 0, 0} }, +{"fdecstp",0, 0xd9f6, X, 0, FP, { 0, 0, 0} }, +{"fincstp",0, 0xd9f7, X, 0, FP, { 0, 0, 0} }, +{"fprem", 0, 0xd9f8, X, 0, FP, { 0, 0, 0} }, +{"fyl2xp1",0, 0xd9f9, X, 0, FP, { 0, 0, 0} }, +{"fsqrt", 0, 0xd9fa, X, 0, FP, { 0, 0, 0} }, +{"fsincos",0, 0xd9fb, X, Cpu286, FP, { 0, 0, 0} }, +{"frndint",0, 0xd9fc, X, 0, FP, { 0, 0, 0} }, +{"fscale", 0, 0xd9fd, X, 0, FP, { 0, 0, 0} }, +{"fsin", 0, 0xd9fe, X, Cpu286, FP, { 0, 0, 0} }, +{"fcos", 0, 0xd9ff, X, Cpu286, FP, { 0, 0, 0} }, +{"fchs", 0, 0xd9e0, X, 0, FP, { 0, 0, 0} }, +{"fabs", 0, 0xd9e1, X, 0, FP, { 0, 0, 0} }, /* processor control */ -{"fninit", 0, 0xdbe3, X, FP, { 0, 0, 0} }, -{"finit", 0, 0xdbe3, X, FP|FWait, { 0, 0, 0} }, -{"fldcw", 1, 0xd9, 5, FP|Modrm, { ShortMem, 0, 0} }, -{"fnstcw", 1, 0xd9, 7, FP|Modrm, { ShortMem, 0, 0} }, -{"fstcw", 1, 0xd9, 7, FP|FWait|Modrm, { ShortMem, 0, 0} }, -{"fnstsw", 1, 0xdfe0, X, FP, { Acc, 0, 0} }, -{"fnstsw", 1, 0xdd, 7, FP|Modrm, { ShortMem, 0, 0} }, -{"fnstsw", 0, 0xdfe0, X, FP, { 0, 0, 0} }, -{"fstsw", 1, 0xdfe0, X, FP|FWait, { Acc, 0, 0} }, -{"fstsw", 1, 0xdd, 7, FP|FWait|Modrm, { ShortMem, 0, 0} }, -{"fstsw", 0, 0xdfe0, X, FP|FWait, { 0, 0, 0} }, -{"fnclex", 0, 0xdbe2, X, FP, { 0, 0, 0} }, -{"fclex", 0, 0xdbe2, X, FP|FWait, { 0, 0, 0} }, +{"fninit", 0, 0xdbe3, X, 0, FP, { 0, 0, 0} }, +{"finit", 0, 0xdbe3, X, 0, FP|FWait, { 0, 0, 0} }, +{"fldcw", 1, 0xd9, 5, 0, FP|Modrm, { ShortMem, 0, 0} }, +{"fnstcw", 1, 0xd9, 7, 0, FP|Modrm, { ShortMem, 0, 0} }, +{"fstcw", 1, 0xd9, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} }, +{"fnstsw", 1, 0xdfe0, X, 0, FP, { Acc, 0, 0} }, +{"fnstsw", 1, 0xdd, 7, 0, FP|Modrm, { ShortMem, 0, 0} }, +{"fnstsw", 0, 0xdfe0, X, 0, FP, { 0, 0, 0} }, +{"fstsw", 1, 0xdfe0, X, 0, FP|FWait, { Acc, 0, 0} }, +{"fstsw", 1, 0xdd, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} }, +{"fstsw", 0, 0xdfe0, X, 0, FP|FWait, { 0, 0, 0} }, +{"fnclex", 0, 0xdbe2, X, 0, FP, { 0, 0, 0} }, +{"fclex", 0, 0xdbe2, X, 0, FP|FWait, { 0, 0, 0} }, /* Short forms of fldenv, fstenv use data size prefix. */ -{"fnstenv",1, 0xd9, 6, sl_Suf|Modrm, { LLongMem, 0, 0} }, -{"fstenv", 1, 0xd9, 6, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} }, -{"fldenv", 1, 0xd9, 4, sl_Suf|Modrm, { LLongMem, 0, 0} }, -{"fnsave", 1, 0xdd, 6, sl_Suf|Modrm, { LLongMem, 0, 0} }, -{"fsave", 1, 0xdd, 6, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} }, -{"frstor", 1, 0xdd, 4, sl_Suf|Modrm, { LLongMem, 0, 0} }, - -{"ffree", 1, 0xddc0, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fnstenv",1, 0xd9, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, +{"fstenv", 1, 0xd9, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} }, +{"fldenv", 1, 0xd9, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, +{"fnsave", 1, 0xdd, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, +{"fsave", 1, 0xdd, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} }, +{"frstor", 1, 0xdd, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, + +{"ffree", 1, 0xddc0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, /* P6:free st(i), pop st */ -{"ffreep", 1, 0xdfc0, X, FP|ShortForm, { FloatReg, 0, 0} }, -{"fnop", 0, 0xd9d0, X, FP, { 0, 0, 0} }, +{"ffreep", 1, 0xdfc0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, +{"fnop", 0, 0xd9d0, X, 0, FP, { 0, 0, 0} }, #define FWAIT_OPCODE 0x9b -{"fwait", 0, 0x9b, X, FP, { 0, 0, 0} }, +{"fwait", 0, 0x9b, X, 0, FP, { 0, 0, 0} }, /* Opcode prefixes; we allow them as separate insns too. */ #define ADDR_PREFIX_OPCODE 0x67 -{"addr16", 0, 0x67, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, -{"addr32", 0, 0x67, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, -{"aword", 0, 0x67, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, -{"adword", 0, 0x67, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, +{"addr16", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, +{"addr32", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, +{"aword", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, +{"adword", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, #define DATA_PREFIX_OPCODE 0x66 -{"data16", 0, 0x66, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, -{"data32", 0, 0x66, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, -{"word", 0, 0x66, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, -{"dword", 0, 0x66, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, +{"data16", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, +{"data32", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, +{"word", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, +{"dword", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, #define LOCK_PREFIX_OPCODE 0xf0 -{"lock", 0, 0xf0, X, NoSuf|IsPrefix, { 0, 0, 0} }, -{"wait", 0, 0x9b, X, NoSuf|IsPrefix, { 0, 0, 0} }, +{"lock", 0, 0xf0, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, +{"wait", 0, 0x9b, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, #define CS_PREFIX_OPCODE 0x2e -{"cs", 0, 0x2e, X, NoSuf|IsPrefix, { 0, 0, 0} }, +{"cs", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, #define DS_PREFIX_OPCODE 0x3e -{"ds", 0, 0x3e, X, NoSuf|IsPrefix, { 0, 0, 0} }, +{"ds", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, #define ES_PREFIX_OPCODE 0x26 -{"es", 0, 0x26, X, NoSuf|IsPrefix, { 0, 0, 0} }, +{"es", 0, 0x26, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, #define FS_PREFIX_OPCODE 0x64 -{"fs", 0, 0x64, X, NoSuf|IsPrefix, { 0, 0, 0} }, +{"fs", 0, 0x64, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} }, #define GS_PREFIX_OPCODE 0x65 -{"gs", 0, 0x65, X, NoSuf|IsPrefix, { 0, 0, 0} }, +{"gs", 0, 0x65, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} }, #define SS_PREFIX_OPCODE 0x36 -{"ss", 0, 0x36, X, NoSuf|IsPrefix, { 0, 0, 0} }, +{"ss", 0, 0x36, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, #define REPNE_PREFIX_OPCODE 0xf2 #define REPE_PREFIX_OPCODE 0xf3 -{"rep", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} }, -{"repe", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} }, -{"repz", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} }, -{"repne", 0, 0xf2, X, NoSuf|IsPrefix, { 0, 0, 0} }, -{"repnz", 0, 0xf2, X, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rep", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, +{"repe", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, +{"repz", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, +{"repne", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, +{"repnz", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rex", 0, 0x40, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rexz", 0, 0x41, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rexy", 0, 0x42, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rexyz", 0, 0x43, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rexx", 0, 0x44, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rexxz", 0, 0x45, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rexxy", 0, 0x46, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rexxyz", 0, 0x47, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rex64", 0, 0x48, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rex64z", 0, 0x49, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rex64y", 0, 0x4a, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rex64yz",0, 0x4b, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rex64x", 0, 0x4c, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rex64xz",0, 0x4d, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rex64xy",0, 0x4e, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, +{"rex64xyz",0, 0x4f, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, /* 486 extensions. */ -{"bswap", 1, 0x0fc8, X, l_Suf|ShortForm, { Reg32, 0, 0 } }, -{"xadd", 2, 0x0fc0, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, -{"cmpxchg", 2, 0x0fb0, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, -{"invd", 0, 0x0f08, X, NoSuf, { 0, 0, 0} }, -{"wbinvd", 0, 0x0f09, X, NoSuf, { 0, 0, 0} }, -{"invlpg", 1, 0x0f01, 7, NoSuf|Modrm, { AnyMem, 0, 0} }, +{"bswap", 1, 0x0fc8, X, Cpu486, lq_Suf|ShortForm, { Reg32|Reg64, 0, 0 } }, +{"xadd", 2, 0x0fc0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, +{"cmpxchg", 2, 0x0fb0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, +{"invd", 0, 0x0f08, X, Cpu486, NoSuf, { 0, 0, 0} }, +{"wbinvd", 0, 0x0f09, X, Cpu486, NoSuf, { 0, 0, 0} }, +{"invlpg", 1, 0x0f01, 7, Cpu486, NoSuf|Modrm, { AnyMem, 0, 0} }, /* 586 and late 486 extensions. */ -{"cpuid", 0, 0x0fa2, X, NoSuf, { 0, 0, 0} }, +{"cpuid", 0, 0x0fa2, X, Cpu486, NoSuf, { 0, 0, 0} }, /* Pentium extensions. */ -{"wrmsr", 0, 0x0f30, X, NoSuf, { 0, 0, 0} }, -{"rdtsc", 0, 0x0f31, X, NoSuf, { 0, 0, 0} }, -{"rdmsr", 0, 0x0f32, X, NoSuf, { 0, 0, 0} }, -{"cmpxchg8b",1,0x0fc7, 1, NoSuf|Modrm, { LLongMem, 0, 0} }, +{"wrmsr", 0, 0x0f30, X, Cpu586, NoSuf, { 0, 0, 0} }, +{"rdtsc", 0, 0x0f31, X, Cpu586, NoSuf, { 0, 0, 0} }, +{"rdmsr", 0, 0x0f32, X, Cpu586, NoSuf, { 0, 0, 0} }, +{"cmpxchg8b",1,0x0fc7, 1, Cpu586, NoSuf|Modrm, { LLongMem, 0, 0} }, /* Pentium II/Pentium Pro extensions. */ -{"sysenter",0, 0x0f34, X, NoSuf, { 0, 0, 0} }, -{"sysexit", 0, 0x0f35, X, NoSuf, { 0, 0, 0} }, -{"fxsave", 1, 0x0fae, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fxrstor", 1, 0x0fae, 1, FP|Modrm, { LLongMem, 0, 0} }, -{"rdpmc", 0, 0x0f33, X, NoSuf, { 0, 0, 0} }, +{"sysenter",0, 0x0f34, X, Cpu686|CpuNo64, NoSuf, { 0, 0, 0} }, +{"sysexit", 0, 0x0f35, X, Cpu686|CpuNo64, NoSuf, { 0, 0, 0} }, +{"fxsave", 1, 0x0fae, 0, Cpu686, FP|Modrm, { LLongMem, 0, 0} }, +{"fxrstor", 1, 0x0fae, 1, Cpu686, FP|Modrm, { LLongMem, 0, 0} }, +{"rdpmc", 0, 0x0f33, X, Cpu686, NoSuf, { 0, 0, 0} }, /* official undefined instr. */ -{"ud2", 0, 0x0f0b, X, NoSuf, { 0, 0, 0} }, +{"ud2", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} }, /* alias for ud2 */ -{"ud2a", 0, 0x0f0b, X, NoSuf, { 0, 0, 0} }, +{"ud2a", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} }, /* 2nd. official undefined instr. */ -{"ud2b", 0, 0x0fb9, X, NoSuf, { 0, 0, 0} }, - -{"cmovo", 2, 0x0f40, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovno", 2, 0x0f41, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovb", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovc", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnae", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovae", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnc", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnb", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmove", 2, 0x0f44, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovz", 2, 0x0f44, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovne", 2, 0x0f45, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnz", 2, 0x0f45, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovbe", 2, 0x0f46, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovna", 2, 0x0f46, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmova", 2, 0x0f47, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnbe", 2, 0x0f47, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovs", 2, 0x0f48, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovns", 2, 0x0f49, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovp", 2, 0x0f4a, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnp", 2, 0x0f4b, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovl", 2, 0x0f4c, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnge", 2, 0x0f4c, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovge", 2, 0x0f4d, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnl", 2, 0x0f4d, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovle", 2, 0x0f4e, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovng", 2, 0x0f4e, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovg", 2, 0x0f4f, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnle", 2, 0x0f4f, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, - -{"fcmovb", 2, 0xdac0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnae",2, 0xdac0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmove", 2, 0xdac8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovbe", 2, 0xdad0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovna", 2, 0xdad0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovu", 2, 0xdad8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovae", 2, 0xdbc0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnb", 2, 0xdbc0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovne", 2, 0xdbc8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmova", 2, 0xdbd0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnbe",2, 0xdbd0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnu", 2, 0xdbd8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, - -{"fcomi", 2, 0xdbf0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcomi", 0, 0xdbf1, X, FP|ShortForm, { 0, 0, 0} }, -{"fcomi", 1, 0xdbf0, X, FP|ShortForm, { FloatReg, 0, 0} }, -{"fucomi", 2, 0xdbe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fucomi", 0, 0xdbe9, X, FP|ShortForm, { 0, 0, 0} }, -{"fucomi", 1, 0xdbe8, X, FP|ShortForm, { FloatReg, 0, 0} }, -{"fcomip", 2, 0xdff0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcompi", 2, 0xdff0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcompi", 0, 0xdff1, X, FP|ShortForm, { 0, 0, 0} }, -{"fcompi", 1, 0xdff0, X, FP|ShortForm, { FloatReg, 0, 0} }, -{"fucomip", 2, 0xdfe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fucompi", 2, 0xdfe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fucompi", 0, 0xdfe9, X, FP|ShortForm, { 0, 0, 0} }, -{"fucompi", 1, 0xdfe8, X, FP|ShortForm, { FloatReg, 0, 0} }, - -/* MMX instructions. */ - -{"emms", 0, 0x0f77, X, FP, { 0, 0, 0 } }, -{"movd", 2, 0x0f6e, X, FP|Modrm, { Reg32|LongMem, RegMMX, 0 } }, -{"movd", 2, 0x0f7e, X, FP|Modrm, { RegMMX, Reg32|LongMem, 0 } }, -{"movq", 2, 0x0f6f, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"movq", 2, 0x0f7f, X, FP|Modrm, { RegMMX, RegMMX|LongMem, 0 } }, -{"packssdw", 2, 0x0f6b, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"packsswb", 2, 0x0f63, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"packuswb", 2, 0x0f67, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddb", 2, 0x0ffc, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddw", 2, 0x0ffd, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddd", 2, 0x0ffe, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddsb", 2, 0x0fec, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddsw", 2, 0x0fed, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddusb", 2, 0x0fdc, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddusw", 2, 0x0fdd, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pand", 2, 0x0fdb, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pandn", 2, 0x0fdf, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqb", 2, 0x0f74, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqw", 2, 0x0f75, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqd", 2, 0x0f76, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtb", 2, 0x0f64, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtw", 2, 0x0f65, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtd", 2, 0x0f66, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmaddwd", 2, 0x0ff5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmulhw", 2, 0x0fe5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmullw", 2, 0x0fd5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"por", 2, 0x0feb, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psllw", 2, 0x0ff1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psllw", 2, 0x0f71, 6, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"pslld", 2, 0x0ff2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pslld", 2, 0x0f72, 6, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"psllq", 2, 0x0ff3, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psllq", 2, 0x0f73, 6, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"psraw", 2, 0x0fe1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psraw", 2, 0x0f71, 4, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"psrad", 2, 0x0fe2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrad", 2, 0x0f72, 4, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"psrlw", 2, 0x0fd1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrlw", 2, 0x0f71, 2, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"psrld", 2, 0x0fd2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrld", 2, 0x0f72, 2, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"psrlq", 2, 0x0fd3, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrlq", 2, 0x0f73, 2, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"psubb", 2, 0x0ff8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubw", 2, 0x0ff9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubd", 2, 0x0ffa, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubsb", 2, 0x0fe8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubsw", 2, 0x0fe9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubusb", 2, 0x0fd8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubusw", 2, 0x0fd9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhbw",2, 0x0f68, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhwd",2, 0x0f69, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhdq",2, 0x0f6a, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpcklbw",2, 0x0f60, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpcklwd",2, 0x0f61, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckldq",2, 0x0f62, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pxor", 2, 0x0fef, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, - +{"ud2b", 0, 0x0fb9, X, Cpu686, NoSuf, { 0, 0, 0} }, + +{"cmovo", 2, 0x0f40, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovno", 2, 0x0f41, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovb", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovc", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnae", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovae", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnc", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnb", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmove", 2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovz", 2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovne", 2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnz", 2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovbe", 2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovna", 2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmova", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnbe", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovs", 2, 0x0f48, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovns", 2, 0x0f49, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovp", 2, 0x0f4a, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnp", 2, 0x0f4b, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovl", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnge", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovge", 2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnl", 2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovle", 2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovng", 2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovg", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnle", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, + +{"fcmovb", 2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnae",2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmove", 2, 0xdac8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovbe", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovna", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovu", 2, 0xdad8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovae", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnb", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovne", 2, 0xdbc8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmova", 2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnbe",2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnu", 2, 0xdbd8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, + +{"fcomi", 2, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcomi", 0, 0xdbf1, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, +{"fcomi", 1, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, +{"fucomi", 2, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fucomi", 0, 0xdbe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, +{"fucomi", 1, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, +{"fcomip", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcompi", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcompi", 0, 0xdff1, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, +{"fcompi", 1, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, +{"fucomip", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fucompi", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fucompi", 0, 0xdfe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, +{"fucompi", 1, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, + +/* Pentium4 extensions. */ + +{"movnti", 2, 0x0fc3, X, CpuP4, FP|Modrm, { WordReg, WordMem, 0 } }, +{"clflush", 1, 0x0fae, 7, CpuP4, FP|Modrm, { ByteMem, 0, 0 } }, +{"lfence", 0, 0x0fae, 0xe8, CpuP4, FP|ImmExt, { 0, 0, 0 } }, +{"mfence", 0, 0x0fae, 0xf0, CpuP4, FP|ImmExt, { 0, 0, 0 } }, +{"pause", 0, 0xf390, X, CpuP4, FP, { 0, 0, 0 } }, + +/* MMX/SSE2 instructions. */ + +{"emms", 0, 0x0f77, X, CpuMMX, FP, { 0, 0, 0 } }, +{"movd", 2, 0x0f6e, X, CpuMMX, FP|Modrm, { Reg32|LongMem, RegMMX, 0 } }, +{"movd", 2, 0x0f7e, X, CpuMMX, FP|Modrm, { RegMMX, Reg32|LongMem, 0 } }, +{"movd", 2, 0x660f6e,X,CpuSSE2,FP|Modrm, { Reg32|LLongMem, RegXMM, 0 } }, +{"movd", 2, 0x660f7e,X,CpuSSE2,FP|Modrm, { RegXMM, Reg32|LLongMem, 0 } }, +/* Real MMX instructions. */ +{"movq", 2, 0x0f6f, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"movq", 2, 0x0f7f, X, CpuMMX, FP|Modrm, { RegMMX, RegMMX|LongMem, 0 } }, +{"movq", 2, 0xf30f7e,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movq", 2, 0x660fd6,X,CpuSSE2,FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +/* In the 64bit mode the short form mov immediate is redefined to have + 64bit displacement value. */ +{"movq", 2, 0x88, X, Cpu64, NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } }, +{"movq", 2, 0xc6, 0, Cpu64, NoSuf|W|Modrm|Size64, { Imm32S, Reg64|WordMem, 0 } }, +{"movq", 2, 0xb0, X, Cpu64, NoSuf|W|ShortForm|Size64,{ Imm64, Reg64, 0 } }, +/* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit + mode they are 64bit.*/ +{"movq", 2, 0x0f20, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Control, Reg64|InvMem, 0} }, +{"movq", 2, 0x0f21, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Debug, Reg64|InvMem, 0} }, +{"packssdw", 2, 0x0f6b, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"packssdw", 2, 0x660f6b,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"packsswb", 2, 0x0f63, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"packsswb", 2, 0x660f63,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"packuswb", 2, 0x0f67, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"packuswb", 2, 0x660f67,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddb", 2, 0x0ffc, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddb", 2, 0x660ffc,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddw", 2, 0x0ffd, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddw", 2, 0x660ffd,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddd", 2, 0x0ffe, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddd", 2, 0x660ffe,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddq", 2, 0x0fd4, X, CpuMMX, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"paddq", 2, 0x660fd4,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddsb", 2, 0x0fec, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddsb", 2, 0x660fec,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddsw", 2, 0x0fed, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddsw", 2, 0x660fed,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddusb", 2, 0x0fdc, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddusb", 2, 0x660fdc,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddusw", 2, 0x0fdd, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddusw", 2, 0x660fdd,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pand", 2, 0x0fdb, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pand", 2, 0x660fdb,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pandn", 2, 0x0fdf, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pandn", 2, 0x660fdf,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pcmpeqb", 2, 0x0f74, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpeqb", 2, 0x660f74,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pcmpeqw", 2, 0x0f75, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpeqw", 2, 0x660f75,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pcmpeqd", 2, 0x0f76, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpeqd", 2, 0x660f76,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pcmpgtb", 2, 0x0f64, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpgtb", 2, 0x660f64,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pcmpgtw", 2, 0x0f65, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpgtw", 2, 0x660f65,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pcmpgtd", 2, 0x0f66, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpgtd", 2, 0x660f66,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pmaddwd", 2, 0x0ff5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmaddwd", 2, 0x660ff5,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pmulhw", 2, 0x0fe5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmulhw", 2, 0x660fe5,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pmullw", 2, 0x0fd5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmullw", 2, 0x660fd5,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"por", 2, 0x0feb, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"por", 2, 0x660feb,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psllw", 2, 0x0ff1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psllw", 2, 0x660ff1,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psllw", 2, 0x0f71, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psllw", 2, 0x660f71,6,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, +{"pslld", 2, 0x0ff2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pslld", 2, 0x660ff2,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pslld", 2, 0x0f72, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"pslld", 2, 0x660f72,6,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, +{"psllq", 2, 0x0ff3, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psllq", 2, 0x660ff3,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psllq", 2, 0x0f73, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psllq", 2, 0x660f73,6,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, +{"psraw", 2, 0x0fe1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psraw", 2, 0x660fe1,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psraw", 2, 0x0f71, 4, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psraw", 2, 0x660f71,4,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, +{"psrad", 2, 0x0fe2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrad", 2, 0x660fe2,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psrad", 2, 0x0f72, 4, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrad", 2, 0x660f72,4,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, +{"psrlw", 2, 0x0fd1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrlw", 2, 0x660fd1,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psrlw", 2, 0x0f71, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrlw", 2, 0x660f71,2,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, +{"psrld", 2, 0x0fd2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrld", 2, 0x660fd2,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psrld", 2, 0x0f72, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrld", 2, 0x660f72,2,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, +{"psrlq", 2, 0x0fd3, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrlq", 2, 0x660fd3,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psrlq", 2, 0x0f73, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrlq", 2, 0x660f73,2,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, +{"psubb", 2, 0x0ff8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubb", 2, 0x660ff8,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psubw", 2, 0x0ff9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubw", 2, 0x660ff9,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psubd", 2, 0x0ffa, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubd", 2, 0x660ffa,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psubq", 2, 0x0ffb, X, CpuMMX, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"psubq", 2, 0x660ffb,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psubsb", 2, 0x0fe8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubsb", 2, 0x660fe8,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psubsw", 2, 0x0fe9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubsw", 2, 0x660fe9,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psubusb", 2, 0x0fd8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubusb", 2, 0x660fd8,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psubusw", 2, 0x0fd9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubusw", 2, 0x660fd9,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"punpckhbw",2, 0x0f68, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckhbw",2, 0x660f68,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"punpckhwd",2, 0x0f69, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckhwd",2, 0x660f69,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"punpckhdq",2, 0x0f6a, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckhdq",2, 0x660f6a,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"punpcklbw",2, 0x0f60, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpcklbw",2, 0x660f60,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"punpcklwd",2, 0x0f61, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpcklwd",2, 0x660f61,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"punpckldq",2, 0x0f62, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckldq",2, 0x660f62,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pxor", 2, 0x0fef, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pxor", 2, 0x660fef,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, /* PIII Katmai New Instructions / SIMD instructions. */ -{"addps", 2, 0x0f58, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"addss", 2, 0xf30f58, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"andnps", 2, 0x0f55, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"andps", 2, 0x0f54, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpeqps", 2, 0x0fc2, 0, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpeqss", 2, 0xf30fc2, 0, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpleps", 2, 0x0fc2, 2, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpless", 2, 0xf30fc2, 2, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpltps", 2, 0x0fc2, 1, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpltss", 2, 0xf30fc2, 1, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpneqps", 2, 0x0fc2, 4, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpneqss", 2, 0xf30fc2, 4, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpnleps", 2, 0x0fc2, 6, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpnless", 2, 0xf30fc2, 6, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpnltps", 2, 0x0fc2, 5, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpnltss", 2, 0xf30fc2, 5, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpordps", 2, 0x0fc2, 7, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpordss", 2, 0xf30fc2, 7, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpunordps",2, 0x0fc2, 3, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpunordss",2, 0xf30fc2, 3, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpps", 3, 0x0fc2, X, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"cmpss", 3, 0xf30fc2, X, FP|Modrm, { Imm8, RegXMM|WordMem, RegXMM } }, -{"comiss", 2, 0x0f2f, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"cvtpi2ps", 2, 0x0f2a, X, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, -{"cvtps2pi", 2, 0x0f2d, X, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, -{"cvtsi2ss", 2, 0xf30f2a, X, FP|Modrm, { Reg32|WordMem, RegXMM, 0 } }, -{"cvtss2si", 2, 0xf30f2d, X, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } }, -{"cvttps2pi", 2, 0x0f2c, X, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, -{"cvttss2si", 2, 0xf30f2c, X, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } }, -{"divps", 2, 0x0f5e, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"divss", 2, 0xf30f5e, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"ldmxcsr", 1, 0x0fae, 2, FP|Modrm, { WordMem, 0, 0 } }, -{"maskmovq", 2, 0x0ff7, X, FP|Modrm, { RegMMX|InvMem, RegMMX, 0 } }, -{"maxps", 2, 0x0f5f, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"maxss", 2, 0xf30f5f, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"minps", 2, 0x0f5d, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"minss", 2, 0xf30f5d, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"movaps", 2, 0x0f28, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movaps", 2, 0x0f29, X, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"movhlps", 2, 0x0f12, X, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, -{"movhps", 2, 0x0f16, X, FP|Modrm, { LLongMem, RegXMM, 0 } }, -{"movhps", 2, 0x0f17, X, FP|Modrm, { RegXMM, LLongMem, 0 } }, -{"movlhps", 2, 0x0f16, X, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, -{"movlps", 2, 0x0f12, X, FP|Modrm, { LLongMem, RegXMM, 0 } }, -{"movlps", 2, 0x0f13, X, FP|Modrm, { RegXMM, LLongMem, 0 } }, -{"movmskps", 2, 0x0f50, X, FP|Modrm, { RegXMM|InvMem, Reg32, 0 } }, -{"movntps", 2, 0x0f2b, X, FP|Modrm, { RegXMM, LLongMem, 0 } }, -{"movntq", 2, 0x0fe7, X, FP|Modrm, { RegMMX, LLongMem, 0 } }, -{"movss", 2, 0xf30f10, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"movss", 2, 0xf30f11, X, FP|Modrm, { RegXMM, RegXMM|WordMem, 0 } }, -{"movups", 2, 0x0f10, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movups", 2, 0x0f11, X, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"mulps", 2, 0x0f59, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"mulss", 2, 0xf30f59, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"orps", 2, 0x0f56, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pavgb", 2, 0x0fe0, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pavgw", 2, 0x0fe3, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pextrw", 3, 0x0fc5, X, FP|Modrm, { Imm8, RegMMX, Reg32|InvMem } }, -{"pinsrw", 3, 0x0fc4, X, FP|Modrm, { Imm8, Reg32|ShortMem, RegMMX } }, -{"pmaxsw", 2, 0x0fee, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pmaxub", 2, 0x0fde, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pminsw", 2, 0x0fea, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pminub", 2, 0x0fda, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pmovmskb", 2, 0x0fd7, X, FP|Modrm, { RegMMX, Reg32|InvMem, 0 } }, -{"pmulhuw", 2, 0x0fe4, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"prefetchnta", 1, 0x0f18, 0, FP|Modrm, { LLongMem, 0, 0 } }, -{"prefetcht0", 1, 0x0f18, 1, FP|Modrm, { LLongMem, 0, 0 } }, -{"prefetcht1", 1, 0x0f18, 2, FP|Modrm, { LLongMem, 0, 0 } }, -{"prefetcht2", 1, 0x0f18, 3, FP|Modrm, { LLongMem, 0, 0 } }, -{"psadbw", 2, 0x0ff6, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pshufw", 3, 0x0f70, X, FP|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } }, -{"rcpps", 2, 0x0f53, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"rcpss", 2, 0xf30f53, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"rsqrtps", 2, 0x0f52, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"rsqrtss", 2, 0xf30f52, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"sfence", 0, 0x0faef8, X, FP, { 0, 0, 0 } }, -{"shufps", 3, 0x0fc6, X, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"sqrtps", 2, 0x0f51, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"sqrtss", 2, 0xf30f51, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"stmxcsr", 1, 0x0fae, 3, FP|Modrm, { WordMem, 0, 0 } }, -{"subps", 2, 0x0f5c, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"subss", 2, 0xf30f5c, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"ucomiss", 2, 0x0f2e, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"unpckhps", 2, 0x0f15, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"unpcklps", 2, 0x0f14, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"xorps", 2, 0x0f57, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"addps", 2, 0x0f58, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"addss", 2, 0xf30f58, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"andnps", 2, 0x0f55, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"andps", 2, 0x0f54, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpeqps", 2, 0x0fc2, 0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpeqss", 2, 0xf30fc2, 0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpleps", 2, 0x0fc2, 2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpless", 2, 0xf30fc2, 2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpltps", 2, 0x0fc2, 1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpltss", 2, 0xf30fc2, 1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpneqps", 2, 0x0fc2, 4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpneqss", 2, 0xf30fc2, 4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpnleps", 2, 0x0fc2, 6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpnless", 2, 0xf30fc2, 6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpnltps", 2, 0x0fc2, 5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpnltss", 2, 0xf30fc2, 5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpordps", 2, 0x0fc2, 7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpordss", 2, 0xf30fc2, 7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpunordps",2, 0x0fc2, 3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpunordss",2, 0xf30fc2, 3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpps", 3, 0x0fc2, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"cmpss", 3, 0xf30fc2, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|WordMem, RegXMM } }, +{"comiss", 2, 0x0f2f, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"cvtpi2ps", 2, 0x0f2a, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, +{"cvtps2pi", 2, 0x0f2d, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, +{"cvtsi2ss", 2, 0xf30f2a, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } }, +{"cvtss2si", 2, 0xf30f2d, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } }, +{"cvttps2pi", 2, 0x0f2c, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, +{"cvttss2si", 2, 0xf30f2c, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|WordMem, Reg32|Reg64, 0 } }, +{"divps", 2, 0x0f5e, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"divss", 2, 0xf30f5e, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"ldmxcsr", 1, 0x0fae, 2, CpuSSE, FP|Modrm, { WordMem, 0, 0 } }, +{"maskmovq", 2, 0x0ff7, X, CpuSSE, FP|Modrm, { RegMMX|InvMem, RegMMX, 0 } }, +{"maxps", 2, 0x0f5f, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"maxss", 2, 0xf30f5f, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"minps", 2, 0x0f5d, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"minss", 2, 0xf30f5d, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"movaps", 2, 0x0f28, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movaps", 2, 0x0f29, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"movhlps", 2, 0x0f12, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, +{"movhps", 2, 0x0f16, X, CpuSSE, FP|Modrm, { LLongMem, RegXMM, 0 } }, +{"movhps", 2, 0x0f17, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movlhps", 2, 0x0f16, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, +{"movlps", 2, 0x0f12, X, CpuSSE, FP|Modrm, { LLongMem, RegXMM, 0 } }, +{"movlps", 2, 0x0f13, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movmskps", 2, 0x0f50, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, Reg32, 0 } }, +{"movntps", 2, 0x0f2b, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movntq", 2, 0x0fe7, X, CpuSSE, FP|Modrm, { RegMMX, LLongMem, 0 } }, +{"movntdq", 2, 0x660fe7, X, CpuSSE2,FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movss", 2, 0xf30f10, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"movss", 2, 0xf30f11, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|WordMem, 0 } }, +{"movups", 2, 0x0f10, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movups", 2, 0x0f11, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"mulps", 2, 0x0f59, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"mulss", 2, 0xf30f59, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"orps", 2, 0x0f56, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pavgb", 2, 0x0fe0, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pavgb", 2, 0x660fe0, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pavgw", 2, 0x0fe3, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pavgw", 2, 0x660fe3, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pextrw", 3, 0x0fc5, X, CpuSSE, FP|Modrm, { Imm8, RegMMX, Reg32|InvMem } }, +{"pextrw", 3, 0x660fc5, X, CpuSSE2,FP|Modrm, { Imm8, RegXMM, Reg32|InvMem } }, +{"pinsrw", 3, 0x0fc4, X, CpuSSE, FP|Modrm, { Imm8, Reg32|ShortMem, RegMMX } }, +{"pinsrw", 3, 0x660fc4, X, CpuSSE2, FP|Modrm, { Imm8, Reg32|ShortMem, RegXMM } }, +{"pmaxsw", 2, 0x0fee, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pmaxsw", 2, 0x660fee, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pmaxub", 2, 0x0fde, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pmaxub", 2, 0x660fde, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pminsw", 2, 0x0fea, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pminsw", 2, 0x660fea, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pminub", 2, 0x0fda, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pminub", 2, 0x660fda, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pmovmskb", 2, 0x0fd7, X, CpuSSE, FP|Modrm, { RegMMX, Reg32|InvMem, 0 } }, +{"pmovmskb", 2, 0x660fd7, X, CpuSSE2,FP|Modrm, { RegXMM, Reg32|InvMem, 0 } }, +{"pmulhuw", 2, 0x0fe4, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pmulhuw", 2, 0x660fe4, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"prefetchnta", 1, 0x0f18, 0, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, +{"prefetcht0", 1, 0x0f18, 1, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, +{"prefetcht1", 1, 0x0f18, 2, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, +{"prefetcht2", 1, 0x0f18, 3, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, +{"psadbw", 2, 0x0ff6, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"psadbw", 2, 0x660ff6, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pshufw", 3, 0x0f70, X, CpuSSE, FP|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } }, +{"rcpps", 2, 0x0f53, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"rcpss", 2, 0xf30f53, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"rsqrtps", 2, 0x0f52, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"rsqrtss", 2, 0xf30f52, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"sfence", 0, 0x0fae, 0xf8, CpuSSE, FP|ImmExt, { 0, 0, 0 } }, +{"shufps", 3, 0x0fc6, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"sqrtps", 2, 0x0f51, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"sqrtss", 2, 0xf30f51, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"stmxcsr", 1, 0x0fae, 3, CpuSSE, FP|Modrm, { WordMem, 0, 0 } }, +{"subps", 2, 0x0f5c, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"subss", 2, 0xf30f5c, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"ucomiss", 2, 0x0f2e, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"unpckhps", 2, 0x0f15, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"unpcklps", 2, 0x0f14, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"xorps", 2, 0x0f57, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, + +/* SSE-2 instructions. */ + +{"addpd", 2, 0x660f58, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"addsd", 2, 0xf20f58, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"andnpd", 2, 0x660f55, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"andpd", 2, 0x660f54, X, CpuSSE2, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpeqpd", 2, 0x660fc2, 0, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpeqsd", 2, 0xf20fc2, 0, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmplepd", 2, 0x660fc2, 2, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmplesd", 2, 0xf20fc2, 2, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmpltpd", 2, 0x660fc2, 1, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpltsd", 2, 0xf20fc2, 1, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmpneqpd", 2, 0x660fc2, 4, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpneqsd", 2, 0xf20fc2, 4, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmpnlepd", 2, 0x660fc2, 6, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpnlesd", 2, 0xf20fc2, 6, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmpnltpd", 2, 0x660fc2, 5, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpnltsd", 2, 0xf20fc2, 5, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmpordpd", 2, 0x660fc2, 7, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpordsd", 2, 0xf20fc2, 7, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmpunordpd",2, 0x660fc2, 3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpunordsd",2, 0xf20fc2, 3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmppd", 3, 0x660fc2, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"cmpsd", 3, 0xf20fc2, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LongMem, RegXMM } }, +{"comisd", 2, 0x660f2f, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"cvtpi2pd", 2, 0x660f2a, X, CpuSSE2, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, +{"cvtsi2sd", 2, 0xf20f2a, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } }, +{"divpd", 2, 0x660f5e, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"divsd", 2, 0xf20f5e, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"maxpd", 2, 0x660f5f, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"maxsd", 2, 0xf20f5f, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"minpd", 2, 0x660f5d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"minsd", 2, 0xf20f5d, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"movapd", 2, 0x660f28, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movapd", 2, 0x660f29, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"movhpd", 2, 0x660f16, X, CpuSSE2, FP|Modrm, { LLongMem, RegXMM, 0 } }, +{"movhpd", 2, 0x660f17, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movlpd", 2, 0x660f12, X, CpuSSE2, FP|Modrm, { LLongMem, RegXMM, 0 } }, +{"movlpd", 2, 0x660f13, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movmskpd", 2, 0x660f50, X, CpuSSE2, FP|Modrm, { RegXMM|InvMem, Reg32, 0 } }, +{"movntpd", 2, 0x660f2b, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movsd", 2, 0xf20f10, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"movsd", 2, 0xf20f11, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LongMem, 0 } }, +{"movupd", 2, 0x660f10, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movupd", 2, 0x660f11, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"mulpd", 2, 0x660f59, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"mulsd", 2, 0xf20f59, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"orpd", 2, 0x660f56, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"shufpd", 3, 0x660fc6, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"sqrtpd", 2, 0x660f51, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"sqrtsd", 2, 0xf20f51, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"subpd", 2, 0x660f5c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"subsd", 2, 0xf20f5c, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"ucomisd", 2, 0x660f2e, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"unpckhpd", 2, 0x660f15, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"unpcklpd", 2, 0x660f14, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"xorpd", 2, 0x660f57, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvtdq2pd", 2, 0xf30fe6, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvtpd2dq", 2, 0xf20fe6, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvtdq2ps", 2, 0x0f5b, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvtpd2pi", 2, 0x660f2d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, +{"cvtpd2ps", 2, 0x660f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvtps2pd", 2, 0x0f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvtps2dq", 2, 0x660f5b, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, +{"cvtsd2si", 2, 0xf20f2d, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|LLongMem, Reg32|Reg64, 0 } }, +{"cvtsd2ss", 2, 0xf20f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvtss2sd", 2, 0xf30f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvttpd2pi", 2, 0x660f2c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, +{"cvttsd2si", 2, 0xf20f2c, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } }, +{"cvttpd2dq", 2, 0x660fe6, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvttps2dq", 2, 0xf30f5b, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"maskmovdqu",2, 0x660ff7, X, CpuSSE2, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, +{"movdqa", 2, 0x660f6f, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movdqa", 2, 0x660f7f, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"movdqu", 2, 0xf30f6f, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movdqu", 2, 0xf30f7f, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"movdq2q", 2, 0xf20fd6, X, CpuSSE2, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, +{"movq2dq", 2, 0xf30fd6, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, +{"pmuludq", 2, 0x0ff4, X, CpuSSE2, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmuludq", 2, 0x660ff4, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"pshufd", 3, 0x660f70, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"pshufhw", 3, 0xf30f70, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"pshuflw", 3, 0xf20f70, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"pslldq", 2, 0x660f73, 7, CpuSSE2, FP|Modrm, { Imm8, RegXMM, 0 } }, +{"psrldq", 2, 0x660f73, 3, CpuSSE2, FP|Modrm, { Imm8, RegXMM, 0 } }, +{"punpckhqdq",2, 0x660f6d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"punpcklqdq",2, 0x660f6c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, /* AMD 3DNow! instructions. */ -{"prefetch", 1, 0x0f0d, 0, FP|Modrm, { ByteMem, 0, 0 } }, -{"prefetchw",1, 0x0f0d, 1, FP|Modrm, { ByteMem, 0, 0 } }, -{"femms", 0, 0x0f0e, X, FP, { 0, 0, 0 } }, -{"pavgusb", 2, 0x0f0f, 0xbf, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pf2id", 2, 0x0f0f, 0x1d, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pf2iw", 2, 0x0f0f, 0x1c, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ -{"pfacc", 2, 0x0f0f, 0xae, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfadd", 2, 0x0f0f, 0x9e, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpeq", 2, 0x0f0f, 0xb0, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpge", 2, 0x0f0f, 0x90, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpgt", 2, 0x0f0f, 0xa0, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmax", 2, 0x0f0f, 0xa4, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmin", 2, 0x0f0f, 0x94, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmul", 2, 0x0f0f, 0xb4, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfnacc", 2, 0x0f0f, 0x8a, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ -{"pfpnacc", 2, 0x0f0f, 0x8e, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ -{"pfrcp", 2, 0x0f0f, 0x96, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrcpit1", 2, 0x0f0f, 0xa6, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrcpit2", 2, 0x0f0f, 0xb6, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrsqit1", 2, 0x0f0f, 0xa7, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrsqrt", 2, 0x0f0f, 0x97, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfsub", 2, 0x0f0f, 0x9a, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfsubr", 2, 0x0f0f, 0xaa, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pi2fd", 2, 0x0f0f, 0x0d, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pi2fw", 2, 0x0f0f, 0x0c, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ -{"pmulhrw", 2, 0x0f0f, 0xb7, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pswapd", 2, 0x0f0f, 0xbb, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ +{"prefetch", 1, 0x0f0d, 0, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } }, +{"prefetchw",1, 0x0f0d, 1, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } }, +{"femms", 0, 0x0f0e, X, Cpu3dnow, FP, { 0, 0, 0 } }, +{"pavgusb", 2, 0x0f0f, 0xbf, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pf2id", 2, 0x0f0f, 0x1d, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pf2iw", 2, 0x0f0f, 0x1c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfacc", 2, 0x0f0f, 0xae, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfadd", 2, 0x0f0f, 0x9e, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfcmpeq", 2, 0x0f0f, 0xb0, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfcmpge", 2, 0x0f0f, 0x90, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfcmpgt", 2, 0x0f0f, 0xa0, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfmax", 2, 0x0f0f, 0xa4, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfmin", 2, 0x0f0f, 0x94, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfmul", 2, 0x0f0f, 0xb4, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfnacc", 2, 0x0f0f, 0x8a, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfpnacc", 2, 0x0f0f, 0x8e, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrcp", 2, 0x0f0f, 0x96, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrsqrt", 2, 0x0f0f, 0x97, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfsub", 2, 0x0f0f, 0x9a, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfsubr", 2, 0x0f0f, 0xaa, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pi2fd", 2, 0x0f0f, 0x0d, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pi2fw", 2, 0x0f0f, 0x0c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmulhrw", 2, 0x0f0f, 0xb7, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pswapd", 2, 0x0f0f, 0xbb, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, + +/* AMD extensions. */ +{"syscall", 0, 0x0f05, X, CpuK6, NoSuf, { 0, 0, 0} }, +{"sysret", 0, 0x0f07, X, CpuK6, lq_Suf|DefaultSize, { 0, 0, 0} }, +{"swapgs", 0, 0x0f01, 0xf8, Cpu64, NoSuf|ImmExt, { 0, 0, 0} }, /* sentinel */ -{NULL, 0, 0, 0, 0, { 0, 0, 0} } +{NULL, 0, 0, 0, 0, 0, { 0, 0, 0} } }; #undef X #undef NoSuf #undef b_Suf #undef w_Suf #undef l_Suf -#undef d_Suf +#undef q_Suf #undef x_Suf #undef bw_Suf #undef bl_Suf #undef wl_Suf -#undef wld_Suf +#undef wlq_Suf #undef sl_Suf -#undef sld_Suf -#undef sldx_Suf #undef bwl_Suf -#undef bwld_Suf +#undef bwlq_Suf #undef FP #undef l_FP -#undef d_FP #undef x_FP #undef sl_FP -#undef sld_FP -#undef sldx_FP #define MAX_MNEM_SIZE 16 /* for parsing insn mnemonics from input */ @@ -1098,104 +1343,190 @@ static const template i386_optab[] = { static const reg_entry i386_regtab[] = { /* make %st first as we test for it */ - {"st", FloatReg|FloatAcc, 0}, + {"st", FloatReg|FloatAcc, 0, 0}, /* 8 bit regs */ - {"al", Reg8|Acc, 0}, - {"cl", Reg8|ShiftCount, 1}, - {"dl", Reg8, 2}, - {"bl", Reg8, 3}, - {"ah", Reg8, 4}, - {"ch", Reg8, 5}, - {"dh", Reg8, 6}, - {"bh", Reg8, 7}, +#define REGNAM_AL 1 /* Entry in i386_regtab. */ + {"al", Reg8|Acc, 0, 0}, + {"cl", Reg8|ShiftCount, 0, 1}, + {"dl", Reg8, 0, 2}, + {"bl", Reg8, 0, 3}, + {"ah", Reg8, 0, 4}, + {"ch", Reg8, 0, 5}, + {"dh", Reg8, 0, 6}, + {"bh", Reg8, 0, 7}, + {"axl", Reg8|Acc, RegRex64, 0}, /* Must be in the "al + 8" slot. */ + {"cxl", Reg8, RegRex64, 1}, + {"dxl", Reg8, RegRex64, 2}, + {"bxl", Reg8, RegRex64, 3}, + {"spl", Reg8, RegRex64, 4}, + {"bpl", Reg8, RegRex64, 5}, + {"sil", Reg8, RegRex64, 6}, + {"dil", Reg8, RegRex64, 7}, + {"r8b", Reg8, RegRex64|RegRex, 0}, + {"r9b", Reg8, RegRex64|RegRex, 1}, + {"r10b", Reg8, RegRex64|RegRex, 2}, + {"r11b", Reg8, RegRex64|RegRex, 3}, + {"r12b", Reg8, RegRex64|RegRex, 4}, + {"r13b", Reg8, RegRex64|RegRex, 5}, + {"r14b", Reg8, RegRex64|RegRex, 6}, + {"r15b", Reg8, RegRex64|RegRex, 7}, /* 16 bit regs */ - {"ax", Reg16|Acc, 0}, - {"cx", Reg16, 1}, - {"dx", Reg16|InOutPortReg, 2}, - {"bx", Reg16|BaseIndex, 3}, - {"sp", Reg16, 4}, - {"bp", Reg16|BaseIndex, 5}, - {"si", Reg16|BaseIndex, 6}, - {"di", Reg16|BaseIndex, 7}, +#define REGNAM_AX 25 + {"ax", Reg16|Acc, 0, 0}, + {"cx", Reg16, 0, 1}, + {"dx", Reg16|InOutPortReg, 0, 2}, + {"bx", Reg16|BaseIndex, 0, 3}, + {"sp", Reg16, 0, 4}, + {"bp", Reg16|BaseIndex, 0, 5}, + {"si", Reg16|BaseIndex, 0, 6}, + {"di", Reg16|BaseIndex, 0, 7}, + {"r8w", Reg16, RegRex, 0}, + {"r9w", Reg16, RegRex, 1}, + {"r10w", Reg16, RegRex, 2}, + {"r11w", Reg16, RegRex, 3}, + {"r12w", Reg16, RegRex, 4}, + {"r13w", Reg16, RegRex, 5}, + {"r14w", Reg16, RegRex, 6}, + {"r15w", Reg16, RegRex, 7}, /* 32 bit regs */ - {"eax", Reg32|BaseIndex|Acc, 0}, - {"ecx", Reg32|BaseIndex, 1}, - {"edx", Reg32|BaseIndex, 2}, - {"ebx", Reg32|BaseIndex, 3}, - {"esp", Reg32, 4}, - {"ebp", Reg32|BaseIndex, 5}, - {"esi", Reg32|BaseIndex, 6}, - {"edi", Reg32|BaseIndex, 7}, +#define REGNAM_EAX 41 + {"eax", Reg32|BaseIndex|Acc, 0, 0}, /* Must be in ax + 16 slot */ + {"ecx", Reg32|BaseIndex, 0, 1}, + {"edx", Reg32|BaseIndex, 0, 2}, + {"ebx", Reg32|BaseIndex, 0, 3}, + {"esp", Reg32, 0, 4}, + {"ebp", Reg32|BaseIndex, 0, 5}, + {"esi", Reg32|BaseIndex, 0, 6}, + {"edi", Reg32|BaseIndex, 0, 7}, + {"r8d", Reg32|BaseIndex, RegRex, 0}, + {"r9d", Reg32|BaseIndex, RegRex, 1}, + {"r10d", Reg32|BaseIndex, RegRex, 2}, + {"r11d", Reg32|BaseIndex, RegRex, 3}, + {"r12d", Reg32|BaseIndex, RegRex, 4}, + {"r13d", Reg32|BaseIndex, RegRex, 5}, + {"r14d", Reg32|BaseIndex, RegRex, 6}, + {"r15d", Reg32|BaseIndex, RegRex, 7}, + {"rax", Reg64|BaseIndex|Acc, 0, 0}, + {"rcx", Reg64|BaseIndex, 0, 1}, + {"rdx", Reg64|BaseIndex, 0, 2}, + {"rbx", Reg64|BaseIndex, 0, 3}, + {"rsp", Reg64, 0, 4}, + {"rbp", Reg64|BaseIndex, 0, 5}, + {"rsi", Reg64|BaseIndex, 0, 6}, + {"rdi", Reg64|BaseIndex, 0, 7}, + {"r8", Reg64|BaseIndex, RegRex, 0}, + {"r9", Reg64|BaseIndex, RegRex, 1}, + {"r10", Reg64|BaseIndex, RegRex, 2}, + {"r11", Reg64|BaseIndex, RegRex, 3}, + {"r12", Reg64|BaseIndex, RegRex, 4}, + {"r13", Reg64|BaseIndex, RegRex, 5}, + {"r14", Reg64|BaseIndex, RegRex, 6}, + {"r15", Reg64|BaseIndex, RegRex, 7}, /* segment registers */ - {"es", SReg2, 0}, - {"cs", SReg2, 1}, - {"ss", SReg2, 2}, - {"ds", SReg2, 3}, - {"fs", SReg3, 4}, - {"gs", SReg3, 5}, + {"es", SReg2, 0, 0}, + {"cs", SReg2, 0, 1}, + {"ss", SReg2, 0, 2}, + {"ds", SReg2, 0, 3}, + {"fs", SReg3, 0, 4}, + {"gs", SReg3, 0, 5}, /* control registers */ - {"cr0", Control, 0}, - {"cr1", Control, 1}, - {"cr2", Control, 2}, - {"cr3", Control, 3}, - {"cr4", Control, 4}, - {"cr5", Control, 5}, - {"cr6", Control, 6}, - {"cr7", Control, 7}, + {"cr0", Control, 0, 0}, + {"cr1", Control, 0, 1}, + {"cr2", Control, 0, 2}, + {"cr3", Control, 0, 3}, + {"cr4", Control, 0, 4}, + {"cr5", Control, 0, 5}, + {"cr6", Control, 0, 6}, + {"cr7", Control, 0, 7}, + {"cr8", Control, RegRex, 0}, + {"cr9", Control, RegRex, 1}, + {"cr10", Control, RegRex, 2}, + {"cr11", Control, RegRex, 3}, + {"cr12", Control, RegRex, 4}, + {"cr13", Control, RegRex, 5}, + {"cr14", Control, RegRex, 6}, + {"cr15", Control, RegRex, 7}, /* debug registers */ - {"db0", Debug, 0}, - {"db1", Debug, 1}, - {"db2", Debug, 2}, - {"db3", Debug, 3}, - {"db4", Debug, 4}, - {"db5", Debug, 5}, - {"db6", Debug, 6}, - {"db7", Debug, 7}, - {"dr0", Debug, 0}, - {"dr1", Debug, 1}, - {"dr2", Debug, 2}, - {"dr3", Debug, 3}, - {"dr4", Debug, 4}, - {"dr5", Debug, 5}, - {"dr6", Debug, 6}, - {"dr7", Debug, 7}, + {"db0", Debug, 0, 0}, + {"db1", Debug, 0, 1}, + {"db2", Debug, 0, 2}, + {"db3", Debug, 0, 3}, + {"db4", Debug, 0, 4}, + {"db5", Debug, 0, 5}, + {"db6", Debug, 0, 6}, + {"db7", Debug, 0, 7}, + {"db8", Debug, RegRex, 0}, + {"db9", Debug, RegRex, 1}, + {"db10", Debug, RegRex, 2}, + {"db11", Debug, RegRex, 3}, + {"db12", Debug, RegRex, 4}, + {"db13", Debug, RegRex, 5}, + {"db14", Debug, RegRex, 6}, + {"db15", Debug, RegRex, 7}, + {"dr0", Debug, 0, 0}, + {"dr1", Debug, 0, 1}, + {"dr2", Debug, 0, 2}, + {"dr3", Debug, 0, 3}, + {"dr4", Debug, 0, 4}, + {"dr5", Debug, 0, 5}, + {"dr6", Debug, 0, 6}, + {"dr7", Debug, 0, 7}, + {"dr8", Debug, RegRex, 0}, + {"dr9", Debug, RegRex, 1}, + {"dr10", Debug, RegRex, 2}, + {"dr11", Debug, RegRex, 3}, + {"dr12", Debug, RegRex, 4}, + {"dr13", Debug, RegRex, 5}, + {"dr14", Debug, RegRex, 6}, + {"dr15", Debug, RegRex, 7}, /* test registers */ - {"tr0", Test, 0}, - {"tr1", Test, 1}, - {"tr2", Test, 2}, - {"tr3", Test, 3}, - {"tr4", Test, 4}, - {"tr5", Test, 5}, - {"tr6", Test, 6}, - {"tr7", Test, 7}, + {"tr0", Test, 0, 0}, + {"tr1", Test, 0, 1}, + {"tr2", Test, 0, 2}, + {"tr3", Test, 0, 3}, + {"tr4", Test, 0, 4}, + {"tr5", Test, 0, 5}, + {"tr6", Test, 0, 6}, + {"tr7", Test, 0, 7}, /* mmx and simd registers */ - {"mm0", RegMMX, 0}, - {"mm1", RegMMX, 1}, - {"mm2", RegMMX, 2}, - {"mm3", RegMMX, 3}, - {"mm4", RegMMX, 4}, - {"mm5", RegMMX, 5}, - {"mm6", RegMMX, 6}, - {"mm7", RegMMX, 7}, - {"xmm0", RegXMM, 0}, - {"xmm1", RegXMM, 1}, - {"xmm2", RegXMM, 2}, - {"xmm3", RegXMM, 3}, - {"xmm4", RegXMM, 4}, - {"xmm5", RegXMM, 5}, - {"xmm6", RegXMM, 6}, - {"xmm7", RegXMM, 7} + {"mm0", RegMMX, 0, 0}, + {"mm1", RegMMX, 0, 1}, + {"mm2", RegMMX, 0, 2}, + {"mm3", RegMMX, 0, 3}, + {"mm4", RegMMX, 0, 4}, + {"mm5", RegMMX, 0, 5}, + {"mm6", RegMMX, 0, 6}, + {"mm7", RegMMX, 0, 7}, + {"xmm0", RegXMM, 0, 0}, + {"xmm1", RegXMM, 0, 1}, + {"xmm2", RegXMM, 0, 2}, + {"xmm3", RegXMM, 0, 3}, + {"xmm4", RegXMM, 0, 4}, + {"xmm5", RegXMM, 0, 5}, + {"xmm6", RegXMM, 0, 6}, + {"xmm7", RegXMM, 0, 7}, + {"xmm8", RegXMM, RegRex, 0}, + {"xmm9", RegXMM, RegRex, 1}, + {"xmm10", RegXMM, RegRex, 2}, + {"xmm11", RegXMM, RegRex, 3}, + {"xmm12", RegXMM, RegRex, 4}, + {"xmm13", RegXMM, RegRex, 5}, + {"xmm14", RegXMM, RegRex, 6}, + {"xmm15", RegXMM, RegRex, 7}, + /* no type will make this register rejected for all purposes except + for addressing. This saves creating one extra type for RIP. */ + {"rip", BaseIndex, 0, 0} }; static const reg_entry i386_float_regtab[] = { - {"st(0)", FloatReg|FloatAcc, 0}, - {"st(1)", FloatReg, 1}, - {"st(2)", FloatReg, 2}, - {"st(3)", FloatReg, 3}, - {"st(4)", FloatReg, 4}, - {"st(5)", FloatReg, 5}, - {"st(6)", FloatReg, 6}, - {"st(7)", FloatReg, 7} + {"st(0)", FloatReg|FloatAcc, 0, 0}, + {"st(1)", FloatReg, 0, 1}, + {"st(2)", FloatReg, 0, 2}, + {"st(3)", FloatReg, 0, 3}, + {"st(4)", FloatReg, 0, 4}, + {"st(5)", FloatReg, 0, 5}, + {"st(6)", FloatReg, 0, 6}, + {"st(7)", FloatReg, 0, 7} }; #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */ diff --git a/contrib/binutils/include/opcode/ppc.h b/contrib/binutils/include/opcode/ppc.h index 974f0dfa..246e3c7 100644 --- a/contrib/binutils/include/opcode/ppc.h +++ b/contrib/binutils/include/opcode/ppc.h @@ -88,6 +88,9 @@ extern const int powerpc_num_opcodes; /* Opcode is supported as part of the 64-bit bridge. */ #define PPC_OPCODE_64_BRIDGE (0400) +/* Opcode is supported by Altivec Vector Unit */ +#define PPC_OPCODE_ALTIVEC (01000) + /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) @@ -221,6 +224,11 @@ extern const struct powerpc_operand powerpc_operands[]; number is allowed). This flag will only be set for a signed operand. */ #define PPC_OPERAND_NEGATIVE (04000) + +/* This operand names a vector unit register. The disassembler + prints these with a leading 'v'. */ +#define PPC_OPERAND_VR (010000) + /* The POWER and PowerPC assemblers use a few macros. We keep them with the operands table for simplicity. The macro table is an diff --git a/contrib/binutils/include/opcode/sparc.h b/contrib/binutils/include/opcode/sparc.h index 4f159bd..423cea7 100644 --- a/contrib/binutils/include/opcode/sparc.h +++ b/contrib/binutils/include/opcode/sparc.h @@ -1,5 +1,5 @@ /* Definitions for opcode table for the sparc. - Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 1997 + Copyright (C) 1989, 91, 92, 93, 94, 95, 96, 97, 2000 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and @@ -46,6 +46,7 @@ enum sparc_opcode_arch_val { /* v9 variants must appear last */ SPARC_OPCODE_ARCH_V9, SPARC_OPCODE_ARCH_V9A, /* v9 with ultrasparc additions */ + SPARC_OPCODE_ARCH_V9B, /* v9 with ultrasparc and cheetah additions */ SPARC_OPCODE_ARCH_BAD /* error return from sparc_opcode_lookup_arch */ }; @@ -141,6 +142,7 @@ Kinds of operands: h 22 high bits. X 5 bit unsigned immediate Y 6 bit unsigned immediate + 3 SIAM mode (3 bits). (v9b) K MEMBAR mask (7 bits). (v9) j 10 bit Immediate. (v9) I 11 bit Immediate. (v9) @@ -187,7 +189,7 @@ Kinds of operands: / Ancillary state register in rs1 (v9a) The following chars are unused: (note: ,[] are used as punctuation) -[345] +[45] */ diff --git a/contrib/binutils/include/safe-ctype.h b/contrib/binutils/include/safe-ctype.h new file mode 100644 index 0000000..d5fc649 --- /dev/null +++ b/contrib/binutils/include/safe-ctype.h @@ -0,0 +1,100 @@ +/* <ctype.h> replacement macros. + + Copyright (C) 2000 Free Software Foundation, Inc. + Contributed by Zack Weinberg <zackw@stanford.edu>. + +This file is part of the libiberty library. +Libiberty is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public +License as published by the Free Software Foundation; either +version 2 of the License, or (at your option) any later version. + +Libiberty is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +Library General Public License for more details. + +You should have received a copy of the GNU Library General Public +License along with libiberty; see the file COPYING.LIB. If +not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* This is a compatible replacement of the standard C library's <ctype.h> + with the following properties: + + - Implements all isxxx() macros required by C99. + - Also implements some character classes useful when + parsing C-like languages. + - Does not change behavior depending on the current locale. + - Behaves properly for all values in the range of a signed or + unsigned char. + + To avoid conflicts, this header defines the isxxx functions in upper + case, e.g. ISALPHA not isalpha. */ + +#ifndef SAFE_CTYPE_H +#define SAFE_CTYPE_H + +#ifdef isalpha + #error "safe-ctype.h and ctype.h may not be used simultaneously" +#else + +/* Categories. */ + +enum { + /* In C99 */ + _sch_isblank = 0x0001, /* space \t */ + _sch_iscntrl = 0x0002, /* nonprinting characters */ + _sch_isdigit = 0x0004, /* 0-9 */ + _sch_islower = 0x0008, /* a-z */ + _sch_isprint = 0x0010, /* any printing character including ' ' */ + _sch_ispunct = 0x0020, /* all punctuation */ + _sch_isspace = 0x0040, /* space \t \n \r \f \v */ + _sch_isupper = 0x0080, /* A-Z */ + _sch_isxdigit = 0x0100, /* 0-9A-Fa-f */ + + /* Extra categories useful to cpplib. */ + _sch_isidst = 0x0200, /* A-Za-z_ */ + _sch_isvsp = 0x0400, /* \n \r */ + _sch_isnvsp = 0x0800, /* space \t \f \v \0 */ + + /* Combinations of the above. */ + _sch_isalpha = _sch_isupper|_sch_islower, /* A-Za-z */ + _sch_isalnum = _sch_isalpha|_sch_isdigit, /* A-Za-z0-9 */ + _sch_isidnum = _sch_isidst|_sch_isdigit, /* A-Za-z0-9_ */ + _sch_isgraph = _sch_isalnum|_sch_ispunct, /* isprint and not space */ + _sch_iscppsp = _sch_isvsp|_sch_isnvsp /* isspace + \0 */ +}; + +/* Character classification. */ +extern const unsigned short _sch_istable[256]; + +#define _sch_test(c, bit) (_sch_istable[(c) & 0xff] & (bit)) + +#define ISALPHA(c) _sch_test(c, _sch_isalpha) +#define ISALNUM(c) _sch_test(c, _sch_isalnum) +#define ISBLANK(c) _sch_test(c, _sch_isblank) +#define ISCNTRL(c) _sch_test(c, _sch_iscntrl) +#define ISDIGIT(c) _sch_test(c, _sch_isdigit) +#define ISGRAPH(c) _sch_test(c, _sch_isgraph) +#define ISLOWER(c) _sch_test(c, _sch_islower) +#define ISPRINT(c) _sch_test(c, _sch_isprint) +#define ISPUNCT(c) _sch_test(c, _sch_ispunct) +#define ISSPACE(c) _sch_test(c, _sch_isspace) +#define ISUPPER(c) _sch_test(c, _sch_isupper) +#define ISXDIGIT(c) _sch_test(c, _sch_isxdigit) + +#define ISIDNUM(c) _sch_test(c, _sch_isidnum) +#define ISIDST(c) _sch_test(c, _sch_isidst) +#define IS_VSPACE(c) _sch_test(c, _sch_isvsp) +#define IS_NVSPACE(c) _sch_test(c, _sch_isnvsp) +#define IS_SPACE_OR_NUL(c) _sch_test(c, _sch_iscppsp) + +/* Character transformation. */ +extern const unsigned char _sch_toupper[256]; +extern const unsigned char _sch_tolower[256]; +#define TOUPPER(c) _sch_toupper[(c) & 0xff] +#define TOLOWER(c) _sch_tolower[(c) & 0xff] + +#endif /* no ctype.h */ +#endif /* SAFE_CTYPE_H */ diff --git a/contrib/binutils/include/sort.h b/contrib/binutils/include/sort.h new file mode 100644 index 0000000..c8e1d55 --- /dev/null +++ b/contrib/binutils/include/sort.h @@ -0,0 +1,48 @@ +/* Sorting algorithms. + Copyright (C) 2000 Free Software Foundation, Inc. + Contributed by Mark Mitchell <mark@codesourcery.com>. + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +#ifndef SORT_H +#define SORT_H + +#include <sys/types.h> /* For size_t */ +#ifdef __STDC__ +#include <stddef.h> +#endif /* __STDC__ */ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include <ansidecl.h> + +/* Sort an array of pointers. */ + +extern void sort_pointers PARAMS ((size_t, void **, void **)); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* SORT_H */ + + + + diff --git a/contrib/binutils/include/splay-tree.h b/contrib/binutils/include/splay-tree.h index 6d70c8d..f53f855 100644 --- a/contrib/binutils/include/splay-tree.h +++ b/contrib/binutils/include/splay-tree.h @@ -1,5 +1,5 @@ /* A splay-tree datatype. - Copyright (C) 1998 Free Software Foundation, Inc. + Copyright (C) 1998, 2000 Free Software Foundation, Inc. Contributed by Mark Mitchell (mark@markmitchell.com). This file is part of GNU CC. @@ -99,9 +99,17 @@ extern splay_tree_node splay_tree_insert PARAMS((splay_tree, splay_tree_key, splay_tree_value)); +extern void splay_tree_remove PARAMS((splay_tree, + splay_tree_key)); extern splay_tree_node splay_tree_lookup PARAMS((splay_tree, splay_tree_key)); +extern splay_tree_node splay_tree_predecessor + PARAMS((splay_tree, + splay_tree_key)); +extern splay_tree_node splay_tree_successor + PARAMS((splay_tree, + splay_tree_key)); extern int splay_tree_foreach PARAMS((splay_tree, splay_tree_foreach_fn, void*)); diff --git a/contrib/binutils/include/symcat.h b/contrib/binutils/include/symcat.h index 3e27162..61ce1e9 100644 --- a/contrib/binutils/include/symcat.h +++ b/contrib/binutils/include/symcat.h @@ -19,12 +19,16 @@ #ifndef SYM_CAT_H #define SYM_CAT_H -#if defined (__STDC__) || defined (ALMOST_STDC) +#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) #define CONCAT2(a,b) a##b #define CONCAT3(a,b,c) a##b##c #define CONCAT4(a,b,c,d) a##b##c##d #define STRINGX(s) #s #else +/* Note one should never pass extra whitespace to the CONCATn macros, + e.g. CONCAT2(foo, bar) because traditonal C will keep the space between + the two labels instead of concatenating them. Instead, make sure to + write CONCAT2(foo,bar). */ #define CONCAT2(a,b) a/**/b #define CONCAT3(a,b,c) a/**/b/**/c #define CONCAT4(a,b,c,d) a/**/b/**/c/**/d @@ -35,6 +39,11 @@ #define XCONCAT3(a,b,c) CONCAT3(a,b,c) #define XCONCAT4(a,b,c,d) CONCAT4(a,b,c,d) +/* Note the layer of indirection here is typically used to allow + stringification of the expansion of macros. I.e. "#define foo + bar", "XSTRING(foo)", to yield "bar". Be aware that this only + works for __STDC__, not for traditional C which will still resolve + to "foo". */ #define XSTRING(s) STRINGX(s) -#endif SYM_CAT_H +#endif /* SYM_CAT_H */ |
