Import GNU binutils-2.9.1. This will break things for a few minutes

until I've made the commits to resolve the conflicts.

Submitted by:	Doug Rabson <dfr>

28 files changed, 3142 insertions, 399 deletions

diff --git a/contrib/binutils/include/ChangeLog b/contrib/binutils/include/ChangeLog
index c4657ee..985d9f1 100644
--- a/contrib/binutils/include/ChangeLog
+++ b/contrib/binutils/include/ChangeLog
@@ -1,3 +1,212 @@
+Tue Feb 24 13:05:02 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* dis-asm.h (disassemble_info): Member `symbol' renamed to `symbols'
+	and made an "asymbol **".  New member num_symbols.
+	(INIT_DISASSEMBLE_INFO_NO_ARCH): Update.
+
+Tue Feb 17 12:32:18 1998  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h (sim_fetch_register, sim_store_register): Add
+ 	register length parameter.  Functions return actual length of
+ 	register.
+
+Thu Feb 12 16:29:01 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* getopt.h: Update to latest FSF version.
+
+Wed Feb 11 16:56:06 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* symcat.h: New file.
+
+Mon Feb  2 17:13:31 1998  Steve Haworth  <steve@pm.cse.rmit.EDU.AU>
+
+	* dis-asm.h (print_insn_tic30): Declare.
+
+Thu Jan 22 16:23:59 1998  Fred Fish <fnf@cygnus.com>
+
+	* dis-asm.h: Add flag INSN_HAS_RELOC to tell disassembly 
+	function there is a reloc on this line.
+
+Mon Dec  8 11:22:23 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* dis-asm.h: Remove prototype of disasm_symaddr() as this function
+	no longer exists.
+
+Tue Dec  2 10:20:53 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* dis-asm.h (disasm_symaddr): New prototype.
+
+Mon Dec  1 20:24:18 1997  J"orn Rennecke <amylaar@cygnus.co.uk>
+
+	* coff/sh.h (R_SH_SWITCH8): New.
+
+Mon Dec  1 11:29:35 1997  Doug Evans  <devans@canuck.cygnus.com>
+
+	* callback.h (CB_SYSCALL): Comment out arg names in prototypes.
+
+Wed Nov 26 16:47:58 1997  Michael Meissner  <meissner@cygnus.com>
+
+	* callback.h (CB_SYSCALL): Consistantly use names for prototype
+	arguments.
+
+Wed Nov 26 11:39:30 1997  Doug Evans  <devans@canuck.cygnus.com>
+
+	* callback.h (CB_SYSCALL): Change byte count arguments to
+	{read,write}_mem to `int'.  New member `magic'.
+	(CB_SYSCALL_MAGIC,CB_SYSCALL_INIT): New macros.
+
+Tue Nov 25 01:35:52 1997  Doug Evans  <devans@seba.cygnus.com>
+
+	* callback.h (struct stat): Move forward decl up.
+	(host_callback): Pass stat struct pointer to stat,fstat.
+	(CB_SYS_nnn): Reorganize.
+	(CB_SYSCALL): New members p1,p2.
+	(cb_host_to_target_stat): Delete fourth arg.
+
+Sat Nov 22 23:34:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h (sim_stop_reason): Clarify sim_signalled SIGRC
+ 	argument.
+
+Mon Nov 17 14:00:51 1997  Doug Evans  <devans@seba.cygnus.com>
+
+	* callback.h (CB_TARGET_DEFS_MAP): Renamed from target_defs_map.
+	(host_callback): Add stat, fstat, syscall_map, errno_map, open_map,
+	signal_map, stat_map.
+	(errn_map,open_map): Renamed to cb_init_foo_map.
+	(cb_host_to_target_errno,cb_target_to_host_open): Renamed from
+	host_to_target_errno,target_to_host_open.
+	(cb_read_target_syscall_maps): Add prototype.
+	(cb_target_to_host_syscall): Likewise.
+	(cb_host_to_target_stat): Likewise.
+	(cb_syscall): Likewise.
+	(CB_SYS_{exit,open,close,read,write,lseek,unlink,getpid,kill,fstat,
+	argvlen,argv,chdir,stat,chmod,utime,time}): Define.
+	(CB_SYSCALL): New type.
+	(CB_RC): New enum.
+
+Fri Nov  7 10:34:09 1997  Rob Savoye  <rob@darkstar.cygnus.com>
+
+	* libiberty.h: Add extern "C" { so it can be used with C++
+	programs.
+	* remote-sim.h:  Add extern "C" { so it can be used with C++
+	programs.
+
+Tue Oct 14 16:07:51 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* dis-asm.h (struct disassemble_info): New field
+	'symbol_at_address_func'.
+	(INIT_DISASSEMBLE_INFO_NO_ARCH): Initialise new field with
+	generic_symbol_at_address. 
+
+Mon Oct 13 10:17:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h: Clarify sim_read, sim_write MEM argument.
+
+Wed Sep 24 18:03:10 1997  Stu Grossman  <grossman@babylon-5.cygnus.com>
+
+	* remote-sim.h (SIM_RC):  Add a bunch of new return codes for
+	breakpoint stuff.
+	* Add functions to tell the simulator to set/clear/enable/disable
+	intrinsic breakpoints.
+
+Thu Aug 28 19:41:42 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* libiberty.h (dupargv): Add prototype.
+
+Tue Aug 26 12:25:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h (sim_create_inferior): Add ABFD arg. Document.
+
+Mon Aug 25 10:50:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h (sim_open): Add ABFD arg. Document.
+
+Fri Aug  8 16:43:56 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* dis-asm.h (arc_get_disassembler): Declare.
+
+Wed Jul 30 11:39:50 1997  Per Bothner  <bothner@deneb.cygnus.com>
+
+	* demangle.h (DMGL_JAVA):  New option to request Java demangling.
+
+Tue Jul 22 17:59:54 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* libiberty.h (PEXECUTE_*): Define.
+	(pexecute, pwait): Declare.
+
+Fri Jun  6 13:02:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h (sim_kill): Mark as depreciated.
+
+Fri May 23 13:43:41 1997  Fred Fish  <fnf@cygnus.com>
+
+	* bfdlink.h (struct bfd_link_info): Add task_link member.
+
+Thu May 22 11:32:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h: Review documentation.  Clarify restrictions on
+ 	when functions can be called.
+
+Wed May 21 16:47:53 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h (sim_set_profile_size): Add prototype, document as
+ 	depreciated.
+
+Tue May 20 09:32:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h (sim_open): Add callback struct.
+	(sim_set_callbacks): Drop SIM_DESC argument. Document.
+	(sim_size): Remove recently added SIM_DESC argument. Document.
+
+Mon May 19 19:14:44 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h: Pass SD into sim_size.
+
+Thu May 15 01:24:16 1997  Mark Alexander  <marka@cygnus.com>
+
+	* obstack.h (obstack_specify_allocation_with_arg, obstack_chunkfun,
+	obstack_freefun): Eliminate compile warnings in gdb.
+
+Tue May 13 10:21:14 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* coff/arm.h (constants):   Added new flag bits F_APCS_26 and
+	F_APCS_SET for the f_flags field of the filehdr structure.  Added new
+	flags: F_APCS26, F_ARM_2, F_ARM_3, F_ARM_7, F_ARM_7T to store
+	information in the flags field of the internal_f structure used by BFD
+	routines.
+
+Tue Apr 22 10:24:34 1997  Fred Fish  <fnf@cygnus.com>
+
+	* floatformat.h (floatformat_byteorders): Add comments for previous
+	formats and add floatformat_littlebyte_bigword, primarily for ARM.
+	Add declaration for floatformat_ieee_double_littlebyte_bigword.
+
+Fri Apr 18 13:04:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* remote-sim.h (sim_stop): New interface - asynchronous
+ 	notification of a request to stop / suspend the running
+ 	simulation.
+
+	* remote-sim.h (enum sim_stop): Add sim_running and sim_polling as
+ 	states for use internal to simulators.
+	
+	* callback.h (struct host_callback_strut): Put a magic number at
+ 	the end of the struct to allow basic checking.
+	(struct host_callback_struct ): Add poll_quit - so
+ 	that the console etc can be polled at regular intervals.
+	
+Thu Apr 17 02:17:12 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* remote-sim.h (struct _bfd): Declare.
+	(sim_load): Return SIM_RC.  New arg `abfd'.
+	(sim_create_inferior): Return SIM_RC.  Delete arg `start_address'.
+
+Wed Apr  2 17:09:12 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
+
+	* remote-sim.h (sim_trace, sim_size): Make these global.  They
+ 	will go away shortly.
+
 Wed Apr  2 15:23:49 1997  Doug Evans  <dje@canuck.cygnus.com>
 
 	* remote-sim.h (SIM_OPEN_KIND, SIM_RC): New enums.
@@ -121,6 +330,10 @@ Mon Sep 30 13:56:11 1996  Fred Fish  <fnf@cygnus.com>
 
 	* libiberty.h: Remove #ifndef PRIVATE_XMALLOC.
 
+Sat Aug 31 13:27:06 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* dis-asm.h (print_insn_v850): Declare.
+
 Tue Aug 13 16:10:30 1996  Stu Grossman  (grossman@critters.cygnus.com)
 
 	* obstack.h:  Change bcopy to memcpy.  Works better on Posix
@@ -319,13 +532,11 @@ Thu May  4 14:36:42 1995  Jason Merrill  <jason@phydeaux.cygnus.com>
 
 	* demangle.h: Don't include ansidecl.h if IN_GCC.
 
-
 Tue Feb 21 00:37:28 1995  Jeff Law  (law@snake.cs.utah.edu)
 
 	* hp-symtab.h: Don't use bitfield enumerations, the HP C compiler
 	does not handle them correctly.
 
-
 Thu Feb  9 14:20:27 1995  Ian Lance Taylor  <ian@cygnus.com>
 
 	* libiberty.h (basename): Don't declare parameter type; some
@@ -368,7 +579,6 @@ Wed Dec 14 13:08:43 1994  Stan Shebs  <shebs@andros.cygnus.com>
 
 	* progress.h: New file, empty definitions for progress macros.
 
-
 Fri Nov 25 00:14:05 1994  Jeff Law  (law@snake.cs.utah.edu)
 
 	* hp-symtab.h: New file describing the debug symbols emitted
diff --git a/contrib/binutils/include/bfdlink.h b/contrib/binutils/include/bfdlink.h
index 6bc4d47..f4acf2f 100644
--- a/contrib/binutils/include/bfdlink.h
+++ b/contrib/binutils/include/bfdlink.h
@@ -179,6 +179,9 @@ struct bfd_link_info
   const struct bfd_link_callbacks *callbacks;
   /* true if BFD should generate a relocateable object file.  */
   boolean relocateable;
+  /* true if BFD should generate a "task linked" object file,
+     similar to relocatable but also with globals converted to statics. */
+  boolean task_link;
   /* true if BFD should generate a shared object.  */
   boolean shared;
   /* true if BFD should pre-bind symbols in a shared object.  */
diff --git a/contrib/binutils/include/callback.h b/contrib/binutils/include/callback.h
index b2a7fe2..3075284 100644
--- a/contrib/binutils/include/callback.h
+++ b/contrib/binutils/include/callback.h
@@ -1,5 +1,6 @@
 /* Remote target system call callback support.
    Copyright 1997 Free Software Foundation, Inc.
+   Contributed by Cygnus Solutions.
 
 This file is part of GDB.
 
@@ -17,9 +18,36 @@ You should have received a copy of the GNU General Public License
 along with this program; if not, write to the Free Software
 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
+/* This interface isn't intended to be specific to any particular kind
+   of remote (hardware, simulator, whatever).  As such, support for it
+   (e.g. sim/common/callback.c) should *not* live in the simulator source
+   tree, nor should it live in the gdb source tree.  */
+
+/* There are various ways to handle system calls:
+
+   1) Have a simulator intercept the appropriate trap instruction and
+   directly perform the system call on behalf of the target program.
+   This is the typical way of handling system calls for embedded targets.
+   [Handling system calls for embedded targets isn't that much of an
+   oxymoron as running compiler testsuites make use of the capability.]
+
+   This method of system call handling is done when STATE_ENVIRONMENT
+   is ENVIRONMENT_USER.
+
+   2) Have a simulator emulate the hardware as much as possible.
+   If the program running on the real hardware communicates with some sort
+   of target manager, one would want to be able to run this program on the
+   simulator as well.
+
+   This method of system call handling is done when STATE_ENVIRONMENT
+   is ENVIRONMENT_OPERATING.
+*/
+
 #ifndef CALLBACK_H
 #define CALLBACK_H
 
+/* ??? The reason why we check for va_start here should be documented.  */
+
 #ifndef va_start
 #include <ansidecl.h>
 #ifdef ANSI_PROTOTYPES
@@ -28,11 +56,23 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 #include <varargs.h>
 #endif
 #endif
+
+/* Mapping of host/target values.  */
+/* ??? For debugging purposes, one might want to add a string of the
+   name of the symbol.  */
 
-typedef struct host_callback_struct host_callback;
+typedef struct {
+  int host_val;
+  int target_val;
+} CB_TARGET_DEFS_MAP;
 
 #define MAX_CALLBACK_FDS 10
 
+/* Forward decl for stat/fstat.  */
+struct stat;
+
+typedef struct host_callback_struct host_callback;
+
 struct host_callback_struct 
 {
   int (*close) PARAMS ((host_callback *,int));
@@ -51,6 +91,13 @@ struct host_callback_struct
   void (*flush_stdout) PARAMS ((host_callback *));
   int (*write_stderr) PARAMS ((host_callback *, const char *, int));
   void (*flush_stderr) PARAMS ((host_callback *));
+  int (*stat) PARAMS ((host_callback *, const char *, struct stat *));
+  int (*fstat) PARAMS ((host_callback *, int, struct stat *));
+
+  /* When present, call to the client to give it the oportunity to
+     poll any io devices for a request to quit (indicated by a nonzero
+     return value). */
+  int (*poll_quit) PARAMS ((host_callback *));
 
   /* Used when the target has gone away, so we can close open
      handles and free memory etc etc.  */
@@ -60,8 +107,7 @@ struct host_callback_struct
   /* depreciated, use vprintf_filtered - Talk to the user on a console.  */
   void (*printf_filtered) PARAMS ((host_callback *, const char *, ...));
 
-  /* Talk to the user on a console.
-     The `void *' is actually `va_list *'.  */
+  /* Talk to the user on a console.  */
   void (*vprintf_filtered) PARAMS ((host_callback *, const char *, va_list));
 
   /* Same as vprintf_filtered but to stderr.  */
@@ -77,23 +123,148 @@ struct host_callback_struct
   int fdmap[MAX_CALLBACK_FDS];
   char fdopen[MAX_CALLBACK_FDS];
   char alwaysopen[MAX_CALLBACK_FDS];
+
+  /* System call numbers.  */
+  CB_TARGET_DEFS_MAP *syscall_map;
+  /* Errno values.  */
+  CB_TARGET_DEFS_MAP *errno_map;
+  /* Flags to the open system call.  */
+  CB_TARGET_DEFS_MAP *open_map;
+  /* Signal numbers.  */
+  CB_TARGET_DEFS_MAP *signal_map;
+  /* Layout of `stat' struct.
+     The format is a series of "name,length" pairs separated by colons.
+     Empty space is indicated with a `name' of "space".
+     All padding must be explicitly mentioned.
+     Lengths are in bytes.  If this needs to be extended to bits,
+     use "name.bits".
+     Example: "st_dev,4:st_ino,4:st_mode,4:..."  */
+  const char *stat_map;
+
+  /* Marker for those wanting to do sanity checks.
+     This should remain the last member of this struct to help catch
+     miscompilation errors. */
+#define HOST_CALLBACK_MAGIC 4705 /* teds constant */
+  int magic;
 };
 
 extern host_callback default_callback;
+
+/* Canonical versions of system call numbers.
+   It's not intended to willy-nilly throw every system call ever heard
+   of in here.  Only include those that have an important use.
+   ??? One can certainly start a discussion over the ones that are currently
+   here, but that will always be true.  */
 
-/* Mapping of host/target values.  */
-/* ??? For debugging purposes, one might want to add a string of the
-   name of the symbol.  */
+/* These are used by the ANSI C support of libc.  */
+#define	CB_SYS_exit	1
+#define	CB_SYS_open	2
+#define	CB_SYS_close	3
+#define	CB_SYS_read	4
+#define	CB_SYS_write	5
+#define	CB_SYS_lseek	6
+#define	CB_SYS_unlink	7
+#define	CB_SYS_getpid	8
+#define	CB_SYS_kill	9
+#define CB_SYS_fstat    10
+/*#define CB_SYS_sbrk	11 - not currently a system call, but reserved.  */
 
-typedef struct {
-  int host_val;
-  int target_val;
-} target_defs_map;
+/* ARGV support.  */
+#define CB_SYS_argvlen	12
+#define CB_SYS_argv	13
+
+/* These are extras added for one reason or another.  */
+#define CB_SYS_chdir	14
+#define CB_SYS_stat	15
+#define CB_SYS_chmod 	16
+#define CB_SYS_utime 	17
+#define CB_SYS_time 	18
+
+/* Struct use to pass and return information necessary to perform a
+   system call.  */
+/* FIXME: Need to consider target word size.  */
+
+typedef struct cb_syscall {
+  /* The target's value of what system call to perform.  */
+  int func;
+  /* The arguments to the syscall.  */
+  long arg1, arg2, arg3, arg4;
+
+  /* The result.  */
+  long result;
+  /* Some system calls have two results.  */
+  long result2;
+  /* The target's errno value, or 0 if success.
+     This is converted to the target's value with host_to_target_errno.  */
+  int errcode;
+
+  /* Working space to be used by memory read/write callbacks.  */
+  PTR p1;
+  PTR p2;
+  long x1,x2;
+
+  /* Callbacks for reading/writing memory (e.g. for read/write syscalls).
+     ??? long or unsigned long might be better to use for the `count'
+     argument here.  We mimic sim_{read,write} for now.  Be careful to
+     test any changes with -Wall -Werror, mixed signed comparisons
+     will get you.  */
+  int (*read_mem) PARAMS ((host_callback * /*cb*/, struct cb_syscall * /*sc*/,
+			   unsigned long /*taddr*/, char * /*buf*/,
+			   int /*bytes*/));
+  int (*write_mem) PARAMS ((host_callback * /*cb*/, struct cb_syscall * /*sc*/,
+			    unsigned long /*taddr*/, const char * /*buf*/,
+			    int /*bytes*/));
+
+  /* For sanity checking, should be last entry.  */
+  int magic;
+} CB_SYSCALL;
+
+/* Magic number sanity checker.  */
+#define CB_SYSCALL_MAGIC 0x12344321
+
+/* Macro to initialize CB_SYSCALL.  Called first, before filling in
+   any fields.  */
+#define CB_SYSCALL_INIT(sc) \
+do { \
+  memset ((sc), 0, sizeof (*(sc))); \
+  (sc)->magic = CB_SYSCALL_MAGIC; \
+} while (0)
+
+/* Return codes for various interface routines.  */
+
+typedef enum {
+  CB_RC_OK = 0,
+  /* generic error */
+  CB_RC_ERR,
+  /* either file not found or no read access */
+  CB_RC_ACCESS,
+  CB_RC_NO_MEM
+} CB_RC;
+
+/* Read in target values for system call numbers, errno values, signals.  */
+CB_RC cb_read_target_syscall_maps PARAMS ((host_callback *, const char *));
+
+/* Translate target to host syscall function numbers.  */
+int cb_target_to_host_syscall PARAMS ((host_callback *, int));
+
+/* Translate host to target errno value.  */
+int cb_host_to_target_errno PARAMS ((host_callback *, int));
+
+/* Translate target to host open flags.  */
+int cb_target_to_host_open PARAMS ((host_callback *, int));
+
+/* Translate target signal number to host.  */
+int cb_target_to_host_signal PARAMS ((host_callback *, int));
+
+/* Translate host signal number to target.  */
+int cb_host_to_target_signal PARAMS ((host_callback *, int));
 
-extern target_defs_map errno_map[];
-extern target_defs_map open_map[];
+/* Translate host stat struct to target.
+   If stat struct ptr is NULL, just compute target stat struct size.
+   Result is size of target stat struct or 0 if error.  */
+int cb_host_to_target_stat PARAMS ((host_callback *, const struct stat *, PTR));
 
-extern int host_to_target_errno PARAMS ((int));
-extern int target_to_host_open PARAMS ((int));
+/* Perform a system call.  */
+CB_RC cb_syscall PARAMS ((host_callback *, CB_SYSCALL *));
 
 #endif
diff --git a/contrib/binutils/include/coff/ChangeLog b/contrib/binutils/include/coff/ChangeLog
index 07b8217..21ef0bc 100644
--- a/contrib/binutils/include/coff/ChangeLog
+++ b/contrib/binutils/include/coff/ChangeLog
@@ -1,3 +1,31 @@
+Fri Mar 27 17:16:57 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* internal.h (ISPTR, ISFCN, ISARY): Add casts to unsigned long.
+
+Mon Feb  2 17:10:38 1998  Steve Haworth  <steve@pm.cse.rmit.EDU.AU>
+
+	* tic30.h: New file.
+
+Tue Dec  2 10:21:40 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* arm.h (COFFARM): New define.
+
+Sat Nov 22 15:10:14 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* internal.h (C_THUMBEXTFUNC, C_THUMBSTATFUNC): Constants to
+	define static and external functions.
+
+	* arm.h: Add bits to support PIC and APCS-FLOAT type binaries,
+	when implemented.
+
+Tue Jul 22 18:18:58 1997  Robert Hoehne <robert.hoehne@Mathematik.TU-Chemnitz.DE>
+
+	* go32exe.h: New file.
+
+Tue Jun  3 16:44:18 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* internal.h: Add storage classes for Thumb symbols
+
 Fri Apr 18 11:52:55 1997  Niklas Hallqvist  <niklas@appli.se>
 
 	* alpha.h (ALPHA_ECOFF_BADMAG): Recognize *BSD/alpha magic too.
diff --git a/contrib/binutils/include/coff/internal.h b/contrib/binutils/include/coff/internal.h
index d37f7ca..d873f28 100644
--- a/contrib/binutils/include/coff/internal.h
+++ b/contrib/binutils/include/coff/internal.h
@@ -215,6 +215,7 @@ struct internal_aouthdr
 #define C_ALIAS	 	105	/* duplicate tag		*/
 #define C_HIDDEN	106	/* ext symbol in dmert public lib */
 
+
 /* New storage classes for WINDOWS_NT   */
 #define C_SECTION       104     /* section name */
 #define C_NT_WEAK	105	/* weak external */
@@ -258,6 +259,13 @@ struct internal_aouthdr
 #define C_BSTAT         (0x8f)
 #define C_ESTAT         (0x90)
 
+/* Storage classes for Thumb symbols */
+#define C_THUMBEXT      (128 + C_EXT)
+#define C_THUMBSTAT     (128 + C_STAT)
+#define C_THUMBLABEL    (128 + C_LABEL)
+#define C_THUMBEXTFUNC  (C_THUMBEXT  + 20)
+#define C_THUMBSTATFUNC (C_THUMBSTAT + 20)
+
 /********************** SECTION HEADER **********************/
 
 #define SCNNMLEN (8)
@@ -402,12 +410,16 @@ struct internal_syment
 
 #define BTYPE(x)	((x) & N_BTMASK)
 
-#define ISPTR(x)	(((x) & N_TMASK) == (DT_PTR << N_BTSHFT))
-#define ISFCN(x)	(((x) & N_TMASK) == (DT_FCN << N_BTSHFT))
-#define ISARY(x)	(((x) & N_TMASK) == (DT_ARY << N_BTSHFT))
-#define ISTAG(x)	((x)==C_STRTAG||(x)==C_UNTAG||(x)==C_ENTAG)
-#define DECREF(x) ((((x)>>N_TSHIFT)&~N_BTMASK)|((x)&N_BTMASK))
-
+#define ISPTR(x) \
+  (((unsigned long) (x) & N_TMASK) == ((unsigned long) DT_PTR << N_BTSHFT))
+#define ISFCN(x) \
+  (((unsigned long) (x) & N_TMASK) == ((unsigned long) DT_FCN << N_BTSHFT))
+#define ISARY(x) \
+  (((unsigned long) (x) & N_TMASK) == ((unsigned long) DT_ARY << N_BTSHFT))
+#define ISTAG(x) \
+  ((x) == C_STRTAG || (x) == C_UNTAG || (x) == C_ENTAG)
+#define DECREF(x) \
+  ((((x) >> N_TSHIFT) & ~ N_BTMASK) | ((x) & N_BTMASK))
 
 union internal_auxent
 {
diff --git a/contrib/binutils/include/coff/sh.h b/contrib/binutils/include/coff/sh.h
index 65ed478..41957df 100644
--- a/contrib/binutils/include/coff/sh.h
+++ b/contrib/binutils/include/coff/sh.h
@@ -227,6 +227,7 @@ struct external_reloc {
      .word L1 - L2
    The r_offset field holds the difference between the reloc address
    and L2.  */
+#define R_SH_SWITCH8	33		/* 8 bit switch table entry */
 #define R_SH_SWITCH16	25		/* 16 bit switch table entry */
 #define R_SH_SWITCH32	26		/* 32 bit switch table entry */
 
@@ -264,3 +265,5 @@ struct external_reloc {
    label within a block of instructions.  This permits the linker to
    avoid swapping instructions which are the targets of branches.  */
 #define R_SH_LABEL	32		/* label */
+
+/* NB: R_SH_SWITCH8 is 33 */
diff --git a/contrib/binutils/include/coff/tic30.h b/contrib/binutils/include/coff/tic30.h
new file mode 100644
index 0000000..10b026c
--- /dev/null
+++ b/contrib/binutils/include/coff/tic30.h
@@ -0,0 +1,203 @@
+/*** coff information for Texas Instruments TMS320C3X */
+
+/********************** FILE HEADER **********************/
+
+struct external_filehdr {
+	char f_magic[2];	/* magic number			*/
+	char f_nscns[2];	/* number of sections		*/
+	char f_timdat[4];	/* time & date stamp		*/
+	char f_symptr[4];	/* file pointer to symtab	*/
+	char f_nsyms[4];	/* number of symtab entries	*/
+	char f_opthdr[2];	/* sizeof(optional hdr)		*/
+	char f_flags[2];	/* flags			*/
+};
+
+
+#define	TIC30MAGIC	0xC000
+
+#define TIC30BADMAG(x) (((x).f_magic!=TIC30MAGIC))
+
+#define	FILHDR	struct external_filehdr
+#define	FILHSZ	20
+
+
+/********************** AOUT "OPTIONAL HEADER" **********************/
+
+
+typedef struct 
+{
+  char 	magic[2];		/* type of file				*/
+  char	vstamp[2];		/* version stamp			*/
+  char	tsize[4];		/* text size in bytes, padded to FW bdry*/
+  char	dsize[4];		/* initialized data "  "		*/
+  char	bsize[4];		/* uninitialized data "   "		*/
+  char	entry[4];		/* entry pt.				*/
+  char 	text_start[4];		/* base of text used for this file */
+  char 	data_start[4];		/* base of data used for this file */
+}
+AOUTHDR;
+
+
+#define AOUTHDRSZ 28
+#define AOUTSZ 28
+
+
+
+
+/********************** SECTION HEADER **********************/
+
+
+struct external_scnhdr {
+	char		s_name[8];	/* section name			*/
+	char		s_paddr[4];	/* physical address, aliased s_nlib */
+	char		s_vaddr[4];	/* virtual address		*/
+	char		s_size[4];	/* section size			*/
+	char		s_scnptr[4];	/* file ptr to raw data for section */
+	char		s_relptr[4];	/* file ptr to relocation	*/
+	char		s_lnnoptr[4];	/* file ptr to line numbers	*/
+	char		s_nreloc[2];	/* number of relocation entries	*/
+	char		s_nlnno[2];	/* number of line number entries*/
+	char		s_flags[4];	/* flags			*/
+};
+
+/*
+ * names of "special" sections
+ */
+#define _TEXT	".text"
+#define _DATA	".data"
+#define _BSS	".bss"
+
+
+#define	SCNHDR	struct external_scnhdr
+#define	SCNHSZ	40
+
+
+/********************** LINE NUMBERS **********************/
+
+/* 1 line number entry for every "breakpointable" source line in a section.
+ * Line numbers are grouped on a per function basis; first entry in a function
+ * grouping will have l_lnno = 0 and in place of physical address will be the
+ * symbol table index of the function name.
+ */
+struct external_lineno {
+	union {
+		char l_symndx[4];	/* function name symbol index, iff l_lnno == 0*/
+		char l_paddr[4];	/* (physical) address of line number	*/
+	} l_addr;
+	char l_lnno[4];	/* line number		*/
+};
+
+#define GET_LINENO_LNNO(abfd, ext) bfd_h_get_32(abfd, (bfd_byte *) (ext->l_lnno));
+#define PUT_LINENO_LNNO(abfd,val, ext) bfd_h_put_32(abfd,val,  (bfd_byte *) (ext->l_lnno));
+
+#define	LINENO	struct external_lineno
+#define	LINESZ	8
+
+
+/********************** SYMBOLS **********************/
+
+#define E_SYMNMLEN	8	/* # characters in a symbol name	*/
+#define E_FILNMLEN	14	/* # characters in a file name		*/
+#define E_DIMNUM	4	/* # array dimensions in auxiliary entry */
+
+struct external_syment 
+{
+  union {
+    char e_name[E_SYMNMLEN];
+    struct {
+      char e_zeroes[4];
+      char e_offset[4];
+    } e;
+  } e;
+  char e_value[4];
+  char e_scnum[2];
+  char e_type[2];
+  char e_sclass[1];
+  char e_numaux[1];
+};
+
+
+
+#define N_BTMASK	(017)
+#define N_TMASK		(060)
+#define N_BTSHFT	(4)
+#define N_TSHIFT	(2)
+  
+
+union external_auxent {
+  struct {
+	char x_tagndx[4];	/* str, un, or enum tag indx */
+	union {
+	  struct {
+		char  x_lnno[2]; /* declaration line number */
+		char  x_size[2]; /* str/union/array size */
+	  } x_lnsz;
+	  char x_fsize[4];	/* size of function */
+	} x_misc;
+	union {
+	  struct {		/* if ISFCN, tag, or .bb */
+		char x_lnnoptr[4];	/* ptr to fcn line # */
+		char x_endndx[4];	/* entry ndx past block end */
+	  } x_fcn;
+	  struct {		/* if ISARY, up to 4 dimen. */
+		char x_dimen[E_DIMNUM][2];
+	  } x_ary;
+	} x_fcnary;
+	char x_tvndx[2];		/* tv index */
+  } x_sym;
+  
+  union {
+	char x_fname[E_FILNMLEN];
+	struct {
+	  char x_zeroes[4];
+	  char x_offset[4];
+	} x_n;
+  } x_file;
+  
+  struct {
+	char x_scnlen[4];			/* section length */
+	char x_nreloc[2];	/* # relocation entries */
+	char x_nlinno[2];	/* # line numbers */
+  } x_scn;
+  
+  struct {
+	char x_tvfill[4];	/* tv fill value */
+	char x_tvlen[2];	/* length of .tv */
+	char x_tvran[2][2];	/* tv range */
+  } x_tv;		/* info about .tv section (in auxent of symbol .tv)) */
+  
+
+};
+
+#define	SYMENT	struct external_syment
+#define	SYMESZ	18	
+#define	AUXENT	union external_auxent
+#define	AUXESZ	18
+
+
+
+/********************** RELOCATION DIRECTIVES **********************/
+
+/* The external reloc has an offset field, because some of the reloc
+   types on the z8k don't have room in the instruction for the entire
+   offset - eg with segments */
+
+struct external_reloc {
+  char r_vaddr[4];
+  char r_symndx[4];
+  char r_offset[4];
+  char r_type[2];
+  char r_stuff[2];
+};
+
+
+#define RELOC struct external_reloc
+#define RELSZ 16
+
+/* TMS320C30 relocation types.  */
+
+#define R_TIC30_ABS16 0x100  /* 16 bit absolute. */
+#define R_TIC30_ABS24 0x101  /* 24 bit absolute. */
+#define R_TIC30_ABS32 0x102  /* 32 bit absolute. */
+#define R_TIC30_LDP   0x103  /* LDP bits 23-16 to 7-0. */
+#define R_TIC30_PC16  0x104  /* 16 bit pc relative. */
diff --git a/contrib/binutils/include/demangle.h b/contrib/binutils/include/demangle.h
index b0254af..00f6a0c 100644
--- a/contrib/binutils/include/demangle.h
+++ b/contrib/binutils/include/demangle.h
@@ -32,6 +32,7 @@
 #define DMGL_NO_OPTS	0		/* For readability... */
 #define DMGL_PARAMS	(1 << 0)	/* Include function args */
 #define DMGL_ANSI	(1 << 1)	/* Include const, volatile, etc */
+#define DMGL_JAVA	(1 << 2)	/* Demangle as Java rather than C++. */
 
 #define DMGL_AUTO	(1 << 8)
 #define DMGL_GNU	(1 << 9)
diff --git a/contrib/binutils/include/dis-asm.h b/contrib/binutils/include/dis-asm.h
index 80739ac..bd7e478 100644
--- a/contrib/binutils/include/dis-asm.h
+++ b/contrib/binutils/include/dis-asm.h
@@ -51,14 +51,21 @@ typedef struct disassemble_info {
   unsigned long mach;
   /* Endianness (for bi-endian cpus).  Mono-endian cpus can ignore this.  */
   enum bfd_endian endian;
-  /* The symbol at the start of the function being disassembled.  This
-     is not set reliably, but if it is not NULL, it is correct.  */
-  asymbol *symbol;
+
+  /* An array of pointers to symbols either at the location being disassembled
+     or at the start of the function being disassembled.  The array is sorted
+     so that the first symbol is intended to be the one used.  The others are
+     present for any misc. purposes.  This is not set reliably, but if it is
+     not NULL, it is correct.  */
+  asymbol **symbols;
+  /* Number of symbols in array.  */
+  int num_symbols;
 
   /* For use by the disassembler.
      The top 16 bits are reserved for public use (and are documented here).
      The bottom 16 bits are for the internal use of the disassembler.  */
   unsigned long flags;
+#define INSN_HAS_RELOC	0x80000000
   PTR private_data;
 
   /* Function used to get bytes to disassemble.  MEMADDR is the
@@ -81,6 +88,16 @@ typedef struct disassemble_info {
   void (*print_address_func)
     PARAMS ((bfd_vma addr, struct disassemble_info *info));
 
+  /* Function called to determine if there is a symbol at the given ADDR.
+     If there is, the function returns 1, otherwise it returns 0.
+     This is used by ports which support an overlay manager where
+     the overlay number is held in the top part of an address.  In
+     some circumstances we want to include the overlay number in the
+     address, (normally because there is a symbol associated with
+     that address), but sometimes we want to mask out the overlay bits.  */
+  int (* symbol_at_address_func)
+    PARAMS ((bfd_vma addr, struct disassemble_info * info));
+
   /* These are for buffer_read_memory.  */
   bfd_byte *buffer;
   bfd_vma buffer_vma;
@@ -135,6 +152,7 @@ extern int print_insn_h8300h		PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_h8300s		PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_h8500		PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_alpha		PARAMS ((bfd_vma, disassemble_info*));
+extern disassembler_ftype arc_get_disassembler PARAMS ((int, int));
 extern int print_insn_big_arm		PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_little_arm	PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_sparc		PARAMS ((bfd_vma, disassemble_info*));
@@ -154,6 +172,8 @@ extern int print_insn_little_powerpc	PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_rs6000		PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_w65		PARAMS ((bfd_vma, disassemble_info*));
 extern int print_insn_d10v		PARAMS ((bfd_vma, disassemble_info*));
+extern int print_insn_v850		PARAMS ((bfd_vma, disassemble_info*));
+extern int print_insn_tic30		PARAMS ((bfd_vma, disassemble_info*));
 
 /* Fetch the disassembler for a given BFD, if that support is available.  */
 extern disassembler_ftype disassembler	PARAMS ((bfd *));
@@ -178,6 +198,10 @@ extern void perror_memory PARAMS ((int, bfd_vma, struct disassemble_info *));
 extern void generic_print_address
   PARAMS ((bfd_vma, struct disassemble_info *));
 
+/* Always true.  */
+extern int generic_symbol_at_address
+  PARAMS ((bfd_vma, struct disassemble_info *));
+
 /* Macro to initialize a disassemble_info struct.  This should be called
    by all applications creating such a struct.  */
 #define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC) \
@@ -195,13 +219,15 @@ extern void generic_print_address
 #define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \
   (INFO).fprintf_func = (FPRINTF_FUNC), \
   (INFO).stream = (STREAM), \
-  (INFO).symbol = NULL, \
+  (INFO).symbols = NULL, \
+  (INFO).num_symbols = 0, \
   (INFO).buffer = NULL, \
   (INFO).buffer_vma = 0, \
   (INFO).buffer_length = 0, \
   (INFO).read_memory_func = buffer_read_memory, \
   (INFO).memory_error_func = perror_memory, \
   (INFO).print_address_func = generic_print_address, \
+  (INFO).symbol_at_address_func = generic_symbol_at_address, \
   (INFO).flags = 0, \
   (INFO).bytes_per_line = 0, \
   (INFO).bytes_per_chunk = 0, \
diff --git a/contrib/binutils/include/elf/ChangeLog b/contrib/binutils/include/elf/ChangeLog
index ac5e824..aed10aa 100644
--- a/contrib/binutils/include/elf/ChangeLog
+++ b/contrib/binutils/include/elf/ChangeLog
@@ -1,3 +1,78 @@
+Sat Feb 28 17:04:41 1998  Richard Henderson  <rth@cygnus.com>
+
+	* alpha.h (EF_ALPHA_32BIT, EF_ALPHA_CANRELAX): New.
+
+Mon Dec 15 15:07:49 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* m32r.h (EF_M32R_ARCH, E_M32R_ARCH): New flags to
+	specify machine architecture.
+	
+Fri Dec  5 11:20:08 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h: New constants: SHN_V850_SCOMMON, SHN_V850_TCOMMON,
+	SHN_V850_ZCOMMON, SHT_V850_SCOMMON, SHT_V850_TCOMMON,
+	SHT_V850_ZCOMMON to handle v850 common sections.
+	enum reloc_type renamed to v850_reloc_type to avoid name
+	conflict. 
+	
+Thu Oct 23 13:55:24 1997  Richard Henderson  <rth@cygnus.com>
+
+	* sparc.h (enum elf_sparc_reloc_type): Add UA64 & UA16.
+
+Thu Oct 23 00:42:04 1997  Richard Henderson  <rth@dot.cygnus.com>
+
+	* sparc.h (DT_SPARC_REGISTER): New macro.
+	(DT_SPARC_PLTFMT): In support of old sparc64-linux .plts; will
+	go away soon.
+
+Tue Sep 30 13:26:58 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* sparc.h (EF_SPARC_HAL_R1, EF_SPARC_EXT_MASK): New macros.
+	(EF_SPARCV9_{MM,TSO,PSO,RMO}): New macros.
+	(SHN_BEFORE,SHN_AFTER): New macros.
+	(SHF_EXCLUDE,SHF_ORDERED): New macros.
+	(STT_REGISTER): New macro.
+	(R_SPARC_GLOB_JMP): Deleted, but slot reserved.
+	(R_SPARC_{DISP64,PLT64,HIX22,LOX10}): New relocations.
+	(R_SPARC_{H44,M44,L44,REGISTER}): New relocations.
+	(ELF64_R_TYPE_{DATA,ID,INFO}): New macros.
+
+Tue Sep 16 14:16:17 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h (reloc_type): Add R_V850_TDA_16_16_OFFSET.
+
+Wed Sep  3 15:11:14 1997  Richard Henderson  <rth@cygnus.com>
+
+	* mips.h: Correct typo in comment.
+
+Wed Sep  3 11:25:57 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h (reloc_type): Remove R_V850_16_PCREL.
+
+Tue Sep  2 17:41:05 1997  Nick Clifton  <nickc@cygnus.com>
+
+
+	* v850.h: Add new flags for e_flags field in elf header.
+
+
+Mon Aug 18 11:05:23 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h (reloc_type): Add 16 bit PC relative relocation.
+
+Fri Aug 15 05:10:09 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* arc.h (enum reloc): Move here from elf32-arc.c.
+
+Fri Aug  8 17:05:29 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* arc.h: New file.
+	* common.h (EM_CYGNUS_ARC): Define.
+
+Mon Jun 16 14:46:12 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* internal.h (Elf_Internal_Ehdr): Change e_phoff and e_shoff from
+	bfd_signed_vma to bfd_size_type, as they are not signed.
+
 Wed Mar  5 15:35:26 1997  Doug Evans  <dje@seba.cygnus.com>
 
 	* m32r.h (SHF_M32R_CAN_RELAX): Define.
@@ -24,6 +99,19 @@ Mon Jan 27 11:54:44 1997  Doug Evans  <dje@seba.cygnus.com>
 
 	* m32r.h (enum reloc_type): Add R_M32R_HI16_[SU]LO,R_M32R_LO16.
 
+Fri Jan  3 11:32:51 1997  Michael Meissner  <meissner@tiktok.cygnus.com>
+
+	* v850.h (V850_OTHER_{TDA_BYTE,ERROR}): New bits for the st_other
+	field.
+	(SHN_V850_*): Remove v850 specific section indexes, which are not
+	needed.
+	(enum reloc_type): Move the v850 relocations here from
+	elf32-v850.c
+
+Thu Jan  2 19:30:23 1997  Michael Meissner  <meissner@tiktok.cygnus.com>
+
+	* v850.h: New file, provide V850 specific definitions. 
+
 Tue Dec 31 14:44:32 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 	* common.h (DT_AUXILIARY): Define.
@@ -61,6 +149,10 @@ Fri Aug 30 17:06:21 1996  Ian Lance Taylor  <ian@cygnus.com>
 
 	* common.h (EM_SH): Define.
 
+Tue Aug 20 14:47:54 1996  J.T. Conklin  <jtc@hippo.cygnus.com>
+
+	* common.h (EM_CYGNUS_V850): Define.
+
 Mon Aug 19 10:59:10 1996  Doug Evans  <dje@canuck.cygnus.com>
 
 	* common.h (EM_CYGNUS_M32R): Define.
@@ -165,7 +257,6 @@ Tue Feb 14 13:59:13 1995  Michael Meissner  <meissner@tiktok.cygnus.com>
 	* common.h (EM_PPC): Use offical value of 20, not 17.
 	(EM_PPC_OLD): Define this to be the old value of EM_PPC.
 
-
 Tue Jan 24 09:40:59 1995  Michael Meissner  <meissner@tiktok.cygnus.com>
 
 	* common.h (EM_PPC): New macro, PowerPC machine id.
@@ -174,7 +265,6 @@ Tue Jan 17 10:51:38 1995  Ian Lance Taylor  <ian@sanguine.cygnus.com>
 
 	* mips.h (SHT_MIPS_MSYM, SHT_MIPS_DWARF, SHT_MIPS_EVENTS): Define.
 
-
 Mon Oct 17 13:43:59 1994  Ian Lance Taylor  <ian@sanguine.cygnus.com>
 
 	* internal.h (Elf_Internal_Shdr): Remove rawdata and size fields.
diff --git a/contrib/binutils/include/elf/alpha.h b/contrib/binutils/include/elf/alpha.h
index 8e12dd9..28b9fe3 100644
--- a/contrib/binutils/include/elf/alpha.h
+++ b/contrib/binutils/include/elf/alpha.h
@@ -26,6 +26,14 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 #ifndef _ELF_ALPHA_H
 #define _ELF_ALPHA_H
 
+/* Processor specific flags for the ELF header e_flags field.  */
+
+/* All addresses must be below 2GB.  */
+#define EF_ALPHA_32BIT		0x00000001
+
+/* All relocations needed for relaxation with code movement are present.  */
+#define EF_ALPHA_CANRELAX	0x00000002
+
 /* Processor specific section flags.  */
 
 /* This section must be in the global data area.  */
diff --git a/contrib/binutils/include/elf/arc.h b/contrib/binutils/include/elf/arc.h
new file mode 100644
index 0000000..25ba97a
--- /dev/null
+++ b/contrib/binutils/include/elf/arc.h
@@ -0,0 +1,52 @@
+/* ARC ELF support for BFD.
+   Copyright (C) 1995, 1997 Free Software Foundation, Inc.
+   Contributed by Doug Evans, (dje@cygnus.com)
+
+This file is part of BFD, the Binary File Descriptor library.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+/* This file holds definitions specific to the ARC ELF ABI.  */
+
+#ifndef _ELF_ARC_H
+#define _ELF_ARC_H
+
+enum reloc_type
+{
+  R_ARC_NONE = 0,
+  R_ARC_32,
+  R_ARC_B26,
+  R_ARC_B22_PCREL,
+  R_ARC_max
+};
+
+/* Processor specific flags for the ELF header e_flags field.  */
+
+/* Four bit ARC machine type field.  */
+#define EF_ARC_MACH		0x0000000f
+
+/* Various CPU types.  */
+#define E_ARC_MACH_BASE		0x00000000
+#define E_ARC_MACH_UNUSED1	0x00000001
+#define E_ARC_MACH_UNUSED2	0x00000002
+#define E_ARC_MACH_UNUSED4	0x00000003
+
+/* Leave bits 0xf0 alone in case we ever have more than 16 cpu types.
+   Highly unlikely, but what the heck.  */
+
+/* File contains position independent code.  */
+#define EF_ARC_PIC		0x00000100
+
+#endif /* _ELF_ARC_H */
diff --git a/contrib/binutils/include/elf/common.h b/contrib/binutils/include/elf/common.h
index d555c59..dd0d4d5 100644
--- a/contrib/binutils/include/elf/common.h
+++ b/contrib/binutils/include/elf/common.h
@@ -106,6 +106,8 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 /* Old version of PowerPC, this should be removed shortly. */
 #define EM_PPC_OLD	17
 
+/* Cygnus ARC ELF backend.  Written in the absence of an ABI.  */
+#define EM_CYGNUS_ARC 0x9040
 
 /* Cygnus M32R ELF backend.  Written in the absence of an ABI.  */
 #define EM_CYGNUS_M32R 0x9041
@@ -117,6 +119,8 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 #define EM_CYGNUS_D10V	0x7650
 
 
+/* V850 backend magic number.  Written in the absense of an ABI.  */
+#define EM_CYGNUS_V850	0x9080
 
 /* mn10200 and mn10300 backend magic numbers.
    Written in the absense of an ABI.  */
diff --git a/contrib/binutils/include/elf/internal.h b/contrib/binutils/include/elf/internal.h
index bb849d6..6540310 100644
--- a/contrib/binutils/include/elf/internal.h
+++ b/contrib/binutils/include/elf/internal.h
@@ -43,8 +43,8 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 typedef struct elf_internal_ehdr {
   unsigned char		e_ident[EI_NIDENT];	/* ELF "magic number" */
   bfd_vma		e_entry;		/* Entry point virtual address */
-  bfd_signed_vma	e_phoff;		/* Program header table file offset */
-  bfd_signed_vma	e_shoff;		/* Section header table file offset */
+  bfd_size_type		e_phoff;		/* Program header table file offset */
+  bfd_size_type		e_shoff;		/* Section header table file offset */
   unsigned long		e_version;		/* Identifies object file version */
   unsigned long		e_flags;		/* Processor-specific flags */
   unsigned short	e_type;			/* Identifies object file type */
diff --git a/contrib/binutils/include/elf/v850.h b/contrib/binutils/include/elf/v850.h
new file mode 100644
index 0000000..cc815c5
--- /dev/null
+++ b/contrib/binutils/include/elf/v850.h
@@ -0,0 +1,94 @@
+/* V850 ELF support for BFD.
+   Copyright (C) 1997 Free Software Foundation, Inc.
+   Created by Michael Meissner, Cygnus Support <meissner@cygnus.com>
+
+This file is part of BFD, the Binary File Descriptor library.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+/* This file holds definitions specific to the MIPS ELF ABI.  Note
+   that most of this is not actually implemented by BFD.  */
+
+#ifndef _ELF_V850_H
+#define _ELF_V850_H
+
+/* Processor specific flags for the ELF header e_flags field.  */
+
+/* Four bit V850 architecture field.  */
+#define EF_V850_ARCH		0xf0000000
+
+/* v850 code.  */
+#define E_V850_ARCH		0x00000000
+
+
+
+/* Flags for the st_other field */
+#define V850_OTHER_SDA		0x01	/* symbol had SDA relocations */
+#define V850_OTHER_ZDA		0x02	/* symbol had ZDA relocations */
+#define V850_OTHER_TDA		0x04	/* symbol had TDA relocations */
+#define V850_OTHER_TDA_BYTE	0x08	/* symbol had TDA byte relocations */
+#define V850_OTHER_ERROR	0x80	/* symbol had an error reported */
+
+/* V850 relocations */
+enum v850_reloc_type
+{
+  R_V850_NONE = 0,
+  R_V850_9_PCREL,
+  R_V850_22_PCREL,
+  R_V850_HI16_S,
+  R_V850_HI16,
+  R_V850_LO16,
+  R_V850_32,
+  R_V850_16,
+  R_V850_8,
+  R_V850_SDA_16_16_OFFSET,		/* For ld.b, st.b, set1, clr1, not1, tst1, movea, movhi */
+  R_V850_SDA_15_16_OFFSET,		/* For ld.w, ld.h, ld.hu, st.w, st.h */
+  R_V850_ZDA_16_16_OFFSET,		/* For ld.b, st.b, set1, clr1, not1, tst1, movea, movhi */
+  R_V850_ZDA_15_16_OFFSET,		/* For ld.w, ld.h, ld.hu, st.w, st.h */
+  R_V850_TDA_6_8_OFFSET,		/* For sst.w, sld.w */
+  R_V850_TDA_7_8_OFFSET,		/* For sst.h, sld.h */
+  R_V850_TDA_7_7_OFFSET,		/* For sst.b, sld.b */
+  R_V850_TDA_16_16_OFFSET,		/* For set1, clr1, not1, tst1, movea, movhi */
+  R_V850_max
+};
+
+
+/* Processor specific section indices.  These sections do not actually
+   exist.  Symbols with a st_shndx field corresponding to one of these
+   values have a special meaning.  */
+
+/* Small data area common symbol.  */
+#define SHN_V850_SCOMMON	0xff00
+
+/* Tiny data area common symbol.  */
+#define SHN_V850_TCOMMON	0xff01
+
+/* Zero data area common symbol.  */
+#define SHN_V850_ZCOMMON	0xff02
+
+
+/* Processor specific section types.  */
+
+/* Section contains the .scommon data.  */
+#define SHT_V850_SCOMMON	0x70000000
+
+/* Section contains the .scommon data.  */
+#define SHT_V850_TCOMMON	0x70000001
+
+/* Section contains the .scommon data.  */
+#define SHT_V850_ZCOMMON	0x70000002
+
+
+#endif /* _ELF_V850_H */
diff --git a/contrib/binutils/include/floatformat.h b/contrib/binutils/include/floatformat.h
index 01e3dcb..90daca2 100644
--- a/contrib/binutils/include/floatformat.h
+++ b/contrib/binutils/include/floatformat.h
@@ -28,7 +28,26 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
    (i.e. BITS_BIG_ENDIAN type numbering), and specify which bits each field
    contains with the *_start and *_len fields.  */
 
-enum floatformat_byteorders { floatformat_little, floatformat_big };
+/* What is the order of the bytes. */
+
+enum floatformat_byteorders {
+
+  /* Standard little endian byte order.
+     EX: 1.2345678e10 => 00 00 80 c5 e0 fe 06 42 */
+
+  floatformat_little,
+
+  /* Standard big endian byte order.
+     EX: 1.2345678e10 => 42 06 fe e0 c5 80 00 00 */
+
+  floatformat_big,
+
+  /* Little endian byte order but big endian word order.
+     EX: 1.2345678e10 => e0 fe 06 42 00 00 80 c5 */
+
+  floatformat_littlebyte_bigword
+
+};
 
 enum floatformat_intbit { floatformat_intbit_yes, floatformat_intbit_no };
 
@@ -63,6 +82,10 @@ extern const struct floatformat floatformat_ieee_single_little;
 extern const struct floatformat floatformat_ieee_double_big;
 extern const struct floatformat floatformat_ieee_double_little;
 
+/* floatformat for ARM IEEE double, little endian bytes and big endian words */
+
+extern const struct floatformat floatformat_ieee_double_littlebyte_bigword;
+
 /* floatformats for various extendeds.  */
 
 extern const struct floatformat floatformat_i387_ext;
diff --git a/contrib/binutils/include/getopt.h b/contrib/binutils/include/getopt.h
index abf9153..c4adc30 100644
--- a/contrib/binutils/include/getopt.h
+++ b/contrib/binutils/include/getopt.h
@@ -1,19 +1,23 @@
 /* Declarations for getopt.
-   Copyright (C) 1989, 1990, 1991, 1992, 1993 Free Software Foundation, Inc.
+   Copyright (C) 1989,90,91,92,93,94,96,97 Free Software Foundation, Inc.
 
-   This program is free software; you can redistribute it and/or
-   modify it under the terms of the GNU Library General Public License
-   as published by the Free Software Foundation; either version 2, or
-   (at your option) any later version.
+   NOTE: The canonical source of this file is maintained with the GNU C Library.
+   Bugs can be reported to bug-glibc@prep.ai.mit.edu.
+
+   This program is free software; you can redistribute it and/or modify it
+   under the terms of the GNU General Public License as published by the
+   Free Software Foundation; either version 2, or (at your option) any
+   later version.
 
    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU Library General Public License for more details.
+   GNU General Public License for more details.
 
-   You should have received a copy of the GNU Library General Public License
+   You should have received a copy of the GNU General Public License
    along with this program; if not, write to the Free Software
-   Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307,
+   USA.  */
 
 #ifndef _GETOPT_H
 #define _GETOPT_H 1
@@ -36,7 +40,7 @@ extern char *optarg;
 
    On entry to `getopt', zero means this is the first call; initialize.
 
-   When `getopt' returns EOF, this is the index of the first of the
+   When `getopt' returns -1, this is the index of the first of the
    non-option elements that the caller should itself scan.
 
    Otherwise, `optind' communicates from one call to the next
@@ -76,7 +80,7 @@ extern int optopt;
 
 struct option
 {
-#if	__STDC__
+#if defined (__STDC__) && __STDC__
   const char *name;
 #else
   char *name;
@@ -94,15 +98,15 @@ struct option
 #define required_argument	1
 #define optional_argument	2
 
-#if __STDC__
-#if defined(__GNU_LIBRARY__)
+#if defined (__STDC__) && __STDC__
+#ifdef __GNU_LIBRARY__
 /* Many other libraries have conflicting prototypes for getopt, with
    differences in the consts, in stdlib.h.  To avoid compilation
    errors, only prototype getopt for the GNU C library.  */
 extern int getopt (int argc, char *const *argv, const char *shortopts);
 #else /* not __GNU_LIBRARY__ */
 extern int getopt ();
-#endif /* not __GNU_LIBRARY__ */
+#endif /* __GNU_LIBRARY__ */
 extern int getopt_long (int argc, char *const *argv, const char *shortopts,
 		        const struct option *longopts, int *longind);
 extern int getopt_long_only (int argc, char *const *argv,
@@ -120,10 +124,10 @@ extern int getopt_long ();
 extern int getopt_long_only ();
 
 extern int _getopt_internal ();
-#endif /* not __STDC__ */
+#endif /* __STDC__ */
 
 #ifdef	__cplusplus
 }
 #endif
 
-#endif /* _GETOPT_H */
+#endif /* getopt.h */
diff --git a/contrib/binutils/include/libiberty.h b/contrib/binutils/include/libiberty.h
index d15a98d..951e156 100644
--- a/contrib/binutils/include/libiberty.h
+++ b/contrib/binutils/include/libiberty.h
@@ -10,6 +10,10 @@
 #ifndef LIBIBERTY_H
 #define LIBIBERTY_H
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 #include "ansidecl.h"
 
 /* Build an argument vector from a string.  Allocates memory using
@@ -21,6 +25,12 @@ extern char **buildargv PARAMS ((char *));
 
 extern void freeargv PARAMS ((char **));
 
+/* Duplicate an argument vector. Allocates memory using malloc.  Use
+   freeargv to free the vector.  */
+
+extern char **dupargv PARAMS ((char **));
+
+
 /* Return the last component of a path name.  Note that we can't use a
    prototype here because the parameter is declared inconsistently
    across different systems, sometimes as "char *" and sometimes as
@@ -141,4 +151,26 @@ extern void hex_init PARAMS ((void));
    the argument being performed exactly once.  */
 #define hex_value(c)	(_hex_value[(unsigned char) (c)])
 
+/* Definitions used by the pexecute routine.  */
+
+#define PEXECUTE_FIRST   1
+#define PEXECUTE_LAST    2
+#define PEXECUTE_ONE     (PEXECUTE_FIRST + PEXECUTE_LAST)
+#define PEXECUTE_SEARCH  4
+#define PEXECUTE_VERBOSE 8
+
+/* Execute a program.  */
+
+extern int pexecute PARAMS ((const char *, char * const *, const char *,
+			    const char *, char **, char **, int));
+
+/* Wait for pexecute to finish.  */
+
+extern int pwait PARAMS ((int, int *, int));
+
+#ifdef __cplusplus
+}
+#endif
+
+
 #endif /* ! defined (LIBIBERTY_H) */
diff --git a/contrib/binutils/include/obstack.h b/contrib/binutils/include/obstack.h
index 807259c..ffc6b9e 100644
--- a/contrib/binutils/include/obstack.h
+++ b/contrib/binutils/include/obstack.h
@@ -279,13 +279,14 @@ int obstack_memory_used (struct obstack *obstack);
 
 #define obstack_specify_allocation_with_arg(h, size, alignment, chunkfun, freefun, arg) \
   _obstack_begin_1 ((h), (size), (alignment), \
-		    (void *(*) (long)) (chunkfun), (void (*) (void *)) (freefun), (arg))
+		    (void *(*) (void *, long)) (chunkfun), \
+		    (void (*) (void *, void *)) (freefun), (arg))
 
 #define obstack_chunkfun(h, newchunkfun) \
-  ((h) -> chunkfun = (struct _obstack_chunk *(*)(long)) (newchunkfun))
+  ((h) -> chunkfun = (struct _obstack_chunk *(*)(void *, long)) (newchunkfun))
 
 #define obstack_freefun(h, newfreefun) \
-  ((h) -> freefun = (void (*)(void *)) (newfreefun))
+  ((h) -> freefun = (void (*)(void *, struct _obstack_chunk *)) (newfreefun))
 
 #else
 
diff --git a/contrib/binutils/include/opcode/ChangeLog b/contrib/binutils/include/opcode/ChangeLog
index 8a1b7d7..40ea655 100644
--- a/contrib/binutils/include/opcode/ChangeLog
+++ b/contrib/binutils/include/opcode/ChangeLog
@@ -1,3 +1,218 @@
+Mon Mar 30 21:31:56 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h: Revert March 24 patch; no more LinearAddress.
+
+Mon Mar 30 10:25:54 1998  Alan Modra  <alan@spri.levels.unisa.edu.au>
+
+	* i386.h (i386_optab): Remove fwait (9b) from all floating point
+	instructions, and instead add FWait opcode modifier.  Add short
+	form of fldenv and fstenv.
+	(FWAIT_OPCODE): Define.
+
+	* i386.h (i386_optab): Change second operand constraint of `mov
+	sreg,reg|mem' instruction from Reg16|Mem to WordReg|WordMem to
+	allow legal instructions such as `movl %gs,%esi'
+
+Fri Mar 27 18:30:52 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* h8300.h: Various changes to fully bracket initializers.
+
+Tue Mar 24 18:32:47 1998  H.J. Lu  <hjl@gnu.org>
+
+	* i386.h: Set LinearAddress for lidt and lgdt.
+
+Mon Mar  2 10:44:07 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (CGEN_BOOL_ATTR): New macro.
+
+Mon Feb 23 10:38:21 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (CGEN_CAT3): Delete.  Use CONCAT3 now.
+	(cgen_insn): Record syntax and format entries here, rather than
+	separately.
+
+Tue Feb 17 21:42:56 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* cgen.h (CGEN_SYNTAX_MAKE_FIELD): New macro.
+
+Tue Feb 17 16:00:56 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (cgen_insert_fn): Change type of result to const char *.
+	(cgen_parse_{signed,unsigned}_integer): Delete min,max arguments.
+	(CGEN_{INSN,KEYWORD,OPERAND}_NBOOL_ATTRS): Renamed from ..._MAX_ATTRS.
+
+Thu Feb 12 18:30:41 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* cgen.h (lookup_insn): New argument alias_p.
+
+Thu Feb 12 03:41:00 1998  J"orn Rennecke  <amylaar@cygnus.co.uk>
+
+Fix rac to accept only a0:
+	* d10v.h (OPERAND_ACC): Split into:
+	(OPERAND_ACC0, OPERAND_ACC1) .
+	(OPERAND_GPR): Define.
+
+Wed Feb 11 17:31:53 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (CGEN_FIELDS): Define here.
+	(CGEN_HW_ENTRY): New member `type'.
+	(hw_list): Delete decl.
+	(enum cgen_mode): Declare.
+	(CGEN_OPERAND): New member `hw'.
+	(enum cgen_operand_instance_type): Declare.
+	(CGEN_OPERAND_INSTANCE): New type.
+	(CGEN_INSN): New member `operands'.
+	(CGEN_OPCODE_DATA): Make hw_list const.
+	(get_insn_operands,lookup_insn): Add prototypes for.
+
+Tue Feb  3 17:11:23 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (CGEN_INSN_MAX_ATTRS): Renamed from CGEN_MAX_INSN_ATTRS.
+	(CGEN_HW_ENTRY): Move `next' entry to end of struct.
+	(CGEN_KEYWORD_MAX_ATTRS): Renamed from CGEN_MAX_KEYWORD_ATTRS.
+	(CGEN_OPERAND_MAX_ATTRS): Renamed from CGEN_MAX_OPERAND_ATTRS.
+
+Mon Feb  2 19:19:15 1998  Ian Lance Taylor  <ian@cygnus.com>
+
+	* cgen.h: Correct typo in comment end marker.
+
+Mon Feb  2 17:10:38 1998  Steve Haworth  <steve@pm.cse.rmit.EDU.AU>
+
+	* tic30.h: New file.
+
+Thu Jan 22 17:54:56 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* cgen.h: Add prototypes for cgen_save_fixups(),
+	cgen_restore_fixups(), and cgen_swap_fixups().  Change prototype
+	of cgen_asm_finish_insn() to return a char *.
+
+Wed Jan 14 17:21:43 1998  Nick Clifton  <nickc@cygnus.com>
+
+	* cgen.h: Formatting changes to improve readability. 
+
+Mon Jan 12 11:37:36 1998  Doug Evans  <devans@seba.cygnus.com>
+
+	* cgen.h (*): Clean up pass over `struct foo' usage.
+	(CGEN_ATTR): Make unsigned char.
+	(CGEN_ATTR_TYPE): Update.
+	(CGEN_ATTR_{ENTRY,TABLE}): New types.
+	(cgen_base): Move member `attrs' to cgen_insn.
+	(CGEN_KEYWORD): New member `null_entry'.
+	(CGEN_{SYNTAX,FORMAT}): New types.
+	(cgen_insn): Format and syntax separated from each other.
+
+Mon Dec  1 12:24:44 1997  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
+
+	* m68k.h: Fix comment describing operand types.
+
+Tue Nov 18 18:45:14 1997  J"orn Rennecke  <amylaar@cygnus.co.uk>
+
+	* d10v.h (OPERAND_FLAG): Split into:
+	(OPERAND_FFLAG, OPERAND_CFLAG) .
+
+Thu Nov 13 11:04:24 1997  Gavin Koch  <gavin@cygnus.com>
+
+	* mips.h (struct mips_opcode): Changed comments to reflect new
+	field usage.
+
+Fri Oct 24 22:36:20 1997  Ken Raeburn  <raeburn@cygnus.com>
+
+	* mips.h: Added to comments a quick-ref list of all assigned
+	operand type characters.
+	(OP_{MASK,SH}_PERFREG): New macros.
+
+Wed Oct 22 17:28:33 1997  Richard Henderson  <rth@cygnus.com>
+
+	* sparc.h: Add '_' and '/' for v9a asr's.
+	Patch from David Miller <davem@vger.rutgers.edu>
+
+Tue Oct 14 13:22:29 1997  Jeffrey A Law  (law@cygnus.com)
+
+	* h8300.h: Bit ops with absolute addresses not in the 8 bit
+	area are not available in the base model (H8/300).
+
+Thu Sep 25 13:03:41 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* m68k.h: Remove documentation of ` operand specifier.
+
+Wed Sep 24 19:00:34 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* m68k.h: Document q and v operand specifiers.
+
+Mon Sep 15 18:28:37 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h (struct v850_opcode): Add processors field.
+	(PROCESSOR_V850, PROCESSOR_ALL): New bit constants.
+
+Mon Sep  8 14:05:45 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* cgen.h: Move assembler interface section
+	up so cgen_parse_operand_result is defined for cgen_parse_address.
+	(cgen_parse_address): Update prototype.
+
+Tue Sep  2 15:32:32 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h (V850_OPREAND_ADJUST_SHORT_MEMORY): Removed. 
+
+Tue Aug 26 12:21:52 1997  Ian Lance Taylor  <ian@cygnus.com>
+
+	* i386.h (two_byte_segment_defaults): Correct base register 5 in
+	modes 1 and 2 to be ss rather than ds.  From Gabriel Paubert
+	<paubert@iram.es>.
+
+	* i386.h: Set ud2 to 0x0f0b.  From Gabriel Paubert
+	<paubert@iram.es>.
+
+	* i386.h: Comment fixes for ficom[p]?{s,l} from Gabriel Paubert
+	<paubert@iram.es>.
+
+	* i386.h (JUMP_ON_CX_ZERO): Uncomment (define again).
+	(JUMP_ON_ECX_ZERO): Remove commented out macro.
+
+Fri Aug 22 10:38:29 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h (V850_NOT_R0): New flag.
+
+Mon Aug 18 11:05:58 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h (struct v850_opcode): Remove flags field. 
+
+Wed Aug 13 18:45:48 1997  Nick Clifton  <nickc@cygnus.com>
+
+	* v850.h (struct v850_opcode): Add flags field.
+	(struct v850_operand): Extend meaning of 'bits' and 'shift'
+	fields. 
+
+
+Fri Aug  8 16:58:42 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* arc.h: New file.
+
+Thu Jul 24 21:16:58 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+	* sparc.h (sparc_opcodes): Declare as const.
+
+Thu Jul 10 12:53:25 1997  Jeffrey A Law  (law@cygnus.com)
+
+	* mips.h (FP_S, FP_D): Define.  Bitmasks indicating if an insn
+	uses single or double precision floating point resources.
+	(INSN_NO_ISA, INSN_ISA1): Define.
+	(cpu specific INSN macros): Tweak into bitmasks outside the range
+	of INSN_ISA field.
+
+Mon Jun 16 14:10:00 1997  H.J. Lu  <hjl@gnu.ai.mit.edu>
+
+	* i386.h: Fix pand opcode.
+
+Mon Jun  2 11:35:09 1997  Gavin Koch  <gavin@cygnus.com>
+
+	* mips.h: Widen INSN_ISA and move it to a more convenient
+	bit position.  Add INSN_3900.
+
+Tue May 20 11:25:29 1997  Gavin Koch  <gavin@cygnus.com>
+
+	* mips.h (struct mips_opcode): added new field membership.
+
 Mon May 12 16:26:50 1997  H.J. Lu  <hjl@gnu.ai.mit.edu>
 
 	* i386.h (movd): only Reg32 is allowed.
@@ -42,6 +257,10 @@ Fri Apr  4 14:02:32 1997  Ian Lance Taylor  <ian@cygnus.com>
 	* i386.h: Correct opcode values for fsubp, fsubrp, fdivp, and
 	fdivrp.
 
+Tue Mar 25 22:57:26 1997  Stu Grossman  (grossman@critters.cygnus.com)
+
+	* v850.h (extract):  Make unsigned.
+
 Mon Mar 24 14:38:15 1997  Ian Lance Taylor  <ian@cygnus.com>
 
 	* i386.h: Add iclr.
@@ -81,6 +300,11 @@ Wed Jan 29 09:37:25 1997  Jeffrey A Law  (law@cygnus.com)
 
 	* mn10200.h (MN10200_OPERAND_RELAX): Define.
 
+Tue Dec 31 15:05:41 1996  Michael Meissner  <meissner@tiktok.cygnus.com>
+
+	* v850.h (V850_OPERAND_ADJUST_SHORT_MEMORY): New flag to adjust
+	type IV instruction offsets.
+
 Wed Dec 18 10:06:31 1996  Jeffrey A Law  (law@cygnus.com)
 
 	* mn10200.h (MN10200_OPERAND_NOCHECK): Define.
@@ -89,6 +313,7 @@ Sat Dec 14 10:48:31 1996  Fred Fish  <fnf@ninemoons.com>
 
 	* mn10200.h: Fix comment, mn10200_operand not powerpc_operand.
 	* mn10300.h: Fix comment, mn10300_operand not powerpc_operand.
+	* v850.h: Fix comment, v850_operand not powerpc_operand.
 	
 Mon Dec  9 16:45:39 1996  Jeffrey A Law  (law@cygnus.com)
 
@@ -132,6 +357,10 @@ Fri Nov  1 10:31:02 1996  Richard Henderson  <rth@tamu.edu>
  	implementation.
 	(struct alpha_operand): Move flags slot for better packing.
 
+Tue Oct 29 12:19:10 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* v850.h (V850_OPERAND_RELAX): New operand flag.
+
 Thu Oct 10 14:29:11 1996  Jeffrey A Law  (law@cygnus.com)
 
 	* mn10300.h (FMT_*): Move operand format definitions
@@ -155,10 +384,42 @@ Wed Oct  2 21:31:26 1996  Jeffrey A Law  (law@cygnus.com)
 
 	* mn10x00.h: New file.
 
+Fri Sep 27 18:26:46 1996  Stu Grossman  (grossman@critters.cygnus.com)
+
+	* v850.h:  Add new flag to indicate this instruction uses a PC
+	displacement.
+
 Fri Sep 13 14:58:13 1996  Jeffrey A Law  (law@cygnus.com)
 
 	* h8300.h (stmac): Add missing instruction.
 
+Sat Aug 31 16:02:03 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* v850.h (v850_opcode): Remove "size" field.  Add "memop"
+	field.
+
+Fri Aug 23 10:39:08 1996  Jeffrey A Law  (law@cygnus.com)
+
+	* v850.h (V850_OPERAND_EP): Define.
+
+	* v850.h (v850_opcode): Add size field.
+
+Thu Aug 22 16:51:25 1996  J.T. Conklin  <jtc@rtl.cygnus.com>
+
+	* v850.h (v850_operands): Add insert and extract fields, pointers
+ 	to functions used to handle unusual operand encoding.
+	(V850_OPERAND_REG, V850_OPERAND_SRG, V850_OPERAND_CC,
+ 	V850_OPERAND_SIGNED): Defined.
+
+Wed Aug 21 17:45:10 1996  J.T. Conklin  <jtc@rtl.cygnus.com>
+
+	* v850.h (v850_operands): Add flags field.
+	(OPERAND_REG, OPERAND_NUM): Defined.
+
+Tue Aug 20 14:52:02 1996  J.T. Conklin  <jtc@rtl.cygnus.com>
+
+	* v850.h: New file.
+
 Fri Aug 16 14:44:15 1996  James G. Smith  <jsmith@cygnus.co.uk>
 
 	* mips.h (OP_SH_LOCC, OP_SH_HICC, OP_MASK_CC, OP_SH_COP1NORM,
@@ -419,14 +680,12 @@ Wed Jun 21 18:49:51 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
 	[!NO_DEFAULT_SIZES]: An omitted size defaults to `w'.
 	(m68k_opcode_aliases): Add more aliases.
 
-
 Fri Apr 14 22:15:34 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
 
 	* m68k.h: Added explcitly short-sized conditional branches, and a
 	bunch of aliases (fmov*, ftest*, tdivul) to support gcc's
 	svr4-based configurations.
 
-
 Mon Mar 13 21:30:01 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
 
 	Mon Feb 27 08:36:39 1995  Bryan Ford  <baford@cs.utah.edu>
@@ -455,7 +714,6 @@ Wed Mar  8 03:13:23 1995  Ken Raeburn  <raeburn@cujo.cygnus.com>
 	[DONT_DEFINE_TABLE]: Declare numopcodes, numaliases, and
 	m68k_opcode_aliases; update declaration of m68k_opcodes.
 
-
 Mon Mar  6 10:02:00 1995  Jeff Law  (law@snake.cs.utah.edu)
 
 	* hppa.h (delay_type): Delete unused enumeration.
@@ -479,7 +737,6 @@ Wed Feb 15 12:19:52 1995  Ian Lance Taylor  <ian@cygnus.com>
 
 	* mips.h (M_ULD, M_ULD_A, M_USD, M_USD_A): Define.
 
-
 Mon Feb  6 10:35:23 1995  J.T. Conklin  <jtc@rtl.cygnus.com>
 
 	* i386.h: added cpuid instruction , and dr[0-7] aliases for the
@@ -510,8 +767,6 @@ Tue Jan 17 10:55:30 1995  Ian Lance Taylor  <ian@sanguine.cygnus.com>
 
 	* mips.h (INSN_ISA, INSN_4650): Define.
 
-
-
 Wed Oct 19 13:34:17 1994  Ian Lance Taylor  <ian@sanguine.cygnus.com>
 
 	* a29k.h: Add operand type 'I' for `inv' and `iretinv'.  On
diff --git a/contrib/binutils/include/opcode/arc.h b/contrib/binutils/include/opcode/arc.h
new file mode 100644
index 0000000..a1e0ca1
--- /dev/null
+++ b/contrib/binutils/include/opcode/arc.h
@@ -0,0 +1,274 @@
+/* Opcode table for the ARC.
+   Copyright 1994, 1995, 1997 Free Software Foundation, Inc.
+   Contributed by Doug Evans (dje@cygnus.com).
+
+This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
+the GNU Binutils.
+
+GAS/GDB is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GAS/GDB is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GAS or GDB; see the file COPYING.	If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* List of the various cpu types.
+   The tables currently use bit masks to say whether the instruction or
+   whatever is supported by a particular cpu.  This lets us have one entry
+   apply to several cpus.
+
+   This duplicates bfd_mach_arc_xxx.  For now I wish to isolate this from bfd
+   and bfd from this.  Also note that these numbers are bit values as we want
+   to allow for things available on more than one ARC (but not necessarily all
+   ARCs).  */
+
+/* The `base' cpu must be 0 (table entries are omitted for the base cpu).
+   The cpu type is treated independently of endianness.
+   The complete `mach' number includes endianness.
+   These values are internal to opcodes/bfd/binutils/gas.  */
+#define ARC_MACH_BASE 0
+#define ARC_MACH_UNUSED1 1
+#define ARC_MACH_UNUSED2 2
+#define ARC_MACH_UNUSED4 4
+/* Additional cpu values can be inserted here and ARC_MACH_BIG moved down.  */
+#define ARC_MACH_BIG 8
+
+/* Mask of number of bits necessary to record cpu type.  */
+#define ARC_MACH_CPU_MASK 7
+/* Mask of number of bits necessary to record cpu type + endianness.  */
+#define ARC_MACH_MASK 15
+
+/* Type to denote an ARC instruction (at least a 32 bit unsigned int).  */
+typedef unsigned int arc_insn;
+
+struct arc_opcode {
+  char *syntax;			/* syntax of insn */
+  unsigned long mask, value;	/* recognize insn if (op&mask)==value */
+  int flags;			/* various flag bits */
+
+/* Values for `flags'.  */
+
+/* Return CPU number, given flag bits.  */
+#define ARC_OPCODE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
+/* Return MACH number, given flag bits.  */
+#define ARC_OPCODE_MACH(bits) ((bits) & ARC_MACH_MASK)
+/* First opcode flag bit available after machine mask.  */
+#define ARC_OPCODE_FLAG_START ((ARC_MACH_MASK + 1) << 0)
+/* This insn is a conditional branch.  */
+#define ARC_OPCODE_COND_BRANCH (ARC_OPCODE_FLAG_START)
+
+  /* These values are used to optimize assembly and disassembly.  Each insn is
+     on a list of related insns (same first letter for assembly, same insn code
+     for disassembly).  */
+  struct arc_opcode *next_asm;	/* Next instruction to try during assembly.  */
+  struct arc_opcode *next_dis;	/* Next instruction to try during disassembly.  */
+
+  /* Macros to create the hash values for the lists.  */
+#define ARC_HASH_OPCODE(string) \
+  ((string)[0] >= 'a' && (string)[0] <= 'z' ? (string)[0] - 'a' : 26)
+#define ARC_HASH_ICODE(insn) \
+  ((unsigned int) (insn) >> 27)
+
+  /* Macros to access `next_asm', `next_dis' so users needn't care about the
+     underlying mechanism.  */
+#define ARC_OPCODE_NEXT_ASM(op) ((op)->next_asm)
+#define ARC_OPCODE_NEXT_DIS(op) ((op)->next_dis)
+};
+
+struct arc_operand_value {
+  char *name;			/* eg: "eq" */
+  short value;			/* eg: 1 */
+  unsigned char type;		/* index into `arc_operands' */
+  unsigned char flags;		/* various flag bits */
+
+/* Values for `flags'.  */
+
+/* Return CPU number, given flag bits.  */
+#define ARC_OPVAL_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
+/* Return MACH number, given flag bits.  */
+#define ARC_OPVAL_MACH(bits) ((bits) & ARC_MACH_MASK)
+};
+
+struct arc_operand {
+  /* One of the insn format chars.  */
+  unsigned char fmt;
+
+  /* The number of bits in the operand (may be unused for a modifier).  */
+  unsigned char bits;
+
+  /* How far the operand is left shifted in the instruction, or
+     the modifier's flag bit (may be unused for a modifier.  */
+  unsigned char shift;
+
+  /* Various flag bits.  */
+  int flags;
+
+/* Values for `flags'.  */
+
+/* This operand is a suffix to the opcode.  */
+#define ARC_OPERAND_SUFFIX 1
+
+/* This operand is a relative branch displacement.  The disassembler
+   prints these symbolically if possible.  */
+#define ARC_OPERAND_RELATIVE_BRANCH 2
+
+/* This operand is an absolute branch address.  The disassembler
+   prints these symbolically if possible.  */
+#define ARC_OPERAND_ABSOLUTE_BRANCH 4
+
+/* This operand is an address.  The disassembler
+   prints these symbolically if possible.  */
+#define ARC_OPERAND_ADDRESS 8
+
+/* This operand is a long immediate value.  */
+#define ARC_OPERAND_LIMM 0x10
+
+/* This operand takes signed values.  */
+#define ARC_OPERAND_SIGNED 0x20
+
+/* This operand takes signed values, but also accepts a full positive
+   range of values.  That is, if bits is 16, it takes any value from
+   -0x8000 to 0xffff.  */
+#define ARC_OPERAND_SIGNOPT 0x40
+
+/* This operand should be regarded as a negative number for the
+   purposes of overflow checking (i.e., the normal most negative
+   number is disallowed and one more than the normal most positive
+   number is allowed).  This flag will only be set for a signed
+   operand.  */
+#define ARC_OPERAND_NEGATIVE 0x80
+
+/* This operand doesn't really exist.  The program uses these operands
+   in special ways.  */
+#define ARC_OPERAND_FAKE 0x100
+
+/* Modifier values.  */
+/* A dot is required before a suffix.  Eg: .le  */
+#define ARC_MOD_DOT 0x1000
+
+/* A normal register is allowed (not used, but here for completeness).  */
+#define ARC_MOD_REG 0x2000
+
+/* An auxiliary register name is expected.  */
+#define ARC_MOD_AUXREG 0x4000
+
+/* Sum of all ARC_MOD_XXX bits.  */
+#define ARC_MOD_BITS 0x7000
+
+/* Non-zero if the operand type is really a modifier.  */
+#define ARC_MOD_P(X) ((X) & ARC_MOD_BITS)
+
+  /* Insertion function.  This is used by the assembler.  To insert an
+     operand value into an instruction, check this field.
+
+     If it is NULL, execute
+         i |= (p & ((1 << o->bits) - 1)) << o->shift;
+     (I is the instruction which we are filling in, O is a pointer to
+     this structure, and OP is the opcode value; this assumes twos
+     complement arithmetic).
+
+     If this field is not NULL, then simply call it with the
+     instruction and the operand value.  It will return the new value
+     of the instruction.  If the ERRMSG argument is not NULL, then if
+     the operand value is illegal, *ERRMSG will be set to a warning
+     string (the operand will be inserted in any case).  If the
+     operand value is legal, *ERRMSG will be unchanged.
+
+     REG is non-NULL when inserting a register value.  */
+
+  arc_insn (*insert) PARAMS ((arc_insn insn,
+			      const struct arc_operand *operand, int mods,
+			      const struct arc_operand_value *reg, long value,
+			      const char **errmsg));
+
+  /* Extraction function.  This is used by the disassembler.  To
+     extract this operand type from an instruction, check this field.
+
+     If it is NULL, compute
+         op = ((i) >> o->shift) & ((1 << o->bits) - 1);
+	 if ((o->flags & ARC_OPERAND_SIGNED) != 0
+	     && (op & (1 << (o->bits - 1))) != 0)
+	   op -= 1 << o->bits;
+     (I is the instruction, O is a pointer to this structure, and OP
+     is the result; this assumes twos complement arithmetic).
+
+     If this field is not NULL, then simply call it with the
+     instruction value.  It will return the value of the operand.  If
+     the INVALID argument is not NULL, *INVALID will be set to
+     non-zero if this operand type can not actually be extracted from
+     this operand (i.e., the instruction does not match).  If the
+     operand is valid, *INVALID will not be changed.
+
+     INSN is a pointer to an array of two `arc_insn's.  The first element is
+     the insn, the second is the limm if present.
+
+     Operands that have a printable form like registers and suffixes have
+     their struct arc_operand_value pointer stored in OPVAL.  */
+
+  long (*extract) PARAMS ((arc_insn *insn,
+			   const struct arc_operand *operand,
+			   int mods, const struct arc_operand_value **opval,
+			   int *invalid));
+};
+
+/* Bits that say what version of cpu we have.
+   These should be passed to arc_init_opcode_tables.
+   At present, all there is is the cpu type.  */
+
+/* CPU number, given value passed to `arc_init_opcode_tables'.  */
+#define ARC_HAVE_CPU(bits) ((bits) & ARC_MACH_CPU_MASK)
+/* MACH number, given value passed to `arc_init_opcode_tables'.  */
+#define ARC_HAVE_MACH(bits) ((bits) & ARC_MACH_MASK)
+
+/* Special register values:  */
+#define ARC_REG_SHIMM_UPDATE 61
+#define ARC_REG_SHIMM 63
+#define ARC_REG_LIMM 62
+
+/* Non-zero if REG is a constant marker.  */
+#define ARC_REG_CONSTANT_P(REG) ((REG) >= 61)
+
+/* Positions and masks of various fields:  */
+#define ARC_SHIFT_REGA 21
+#define ARC_SHIFT_REGB 15
+#define ARC_SHIFT_REGC 9
+#define ARC_MASK_REG 63
+
+/* Delay slot types.  */
+#define ARC_DELAY_NONE 0	/* no delay slot */
+#define ARC_DELAY_NORMAL 1	/* delay slot in both cases */
+#define ARC_DELAY_JUMP 2	/* delay slot only if branch taken */
+
+/* Non-zero if X will fit in a signed 9 bit field.  */
+#define ARC_SHIMM_CONST_P(x) ((long) (x) >= -256 && (long) (x) <= 255)
+
+extern const struct arc_operand arc_operands[];
+extern const int arc_operand_count;
+extern /*const*/ struct arc_opcode arc_opcodes[];
+extern const int arc_opcodes_count;
+extern const struct arc_operand_value arc_suffixes[];
+extern const int arc_suffixes_count;
+extern const struct arc_operand_value arc_reg_names[];
+extern const int arc_reg_names_count;
+extern unsigned char arc_operand_map[];
+
+/* Utility fns in arc-opc.c.  */
+int arc_get_opcode_mach PARAMS ((int, int));
+/* `arc_opcode_init_tables' must be called before `arc_xxx_supported'.  */
+void arc_opcode_init_tables PARAMS ((int));
+void arc_opcode_init_insert PARAMS ((void));
+void arc_opcode_init_extract PARAMS ((void));
+const struct arc_opcode *arc_opcode_lookup_asm PARAMS ((const char *));
+const struct arc_opcode *arc_opcode_lookup_dis PARAMS ((unsigned int));
+int arc_opcode_limm_p PARAMS ((long *));
+const struct arc_operand_value *arc_opcode_lookup_suffix PARAMS ((const struct arc_operand *type, int value));
+int arc_opcode_supported PARAMS ((const struct arc_opcode *));
+int arc_opval_supported PARAMS ((const struct arc_operand_value *));
diff --git a/contrib/binutils/include/opcode/cgen.h b/contrib/binutils/include/opcode/cgen.h
index cda3373..ab59f24 100644
--- a/contrib/binutils/include/opcode/cgen.h
+++ b/contrib/binutils/include/opcode/cgen.h
@@ -1,6 +1,6 @@
 /* Header file for targets using CGEN: Cpu tools GENerator.
 
-Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
 
 This file is part of GDB, the GNU debugger, and the GNU Binutils.
 
@@ -14,22 +14,13 @@ but WITHOUT ANY WARRANTY; without even the implied warranty of
 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 GNU General Public License for more details.
 
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 
 #ifndef CGEN_H
 #define CGEN_H
 
-#ifndef CGEN_CAT3
-#if defined(__STDC__) || defined(ALMOST_STDC)
-#define CGEN_XCAT3(a,b,c) a ## b ## c
-#define CGEN_CAT3(a,b,c) CGEN_XCAT3 (a, b, c)
-#else
-#define CGEN_CAT3(a,b,c) a/**/b/**/c
-#endif
-#endif
-
 /* Prepend the cpu name, defined in cpu-opc.h, and _cgen_ to symbol S.
    The lack of spaces in the arg list is important for non-stdc systems.
    This file is included by <cpu>-opc.h.
@@ -37,7 +28,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
    dependent portions will be declared as "unknown_cgen_foo".  */
 
 #ifndef CGEN_SYM
-#define CGEN_SYM(s) CGEN_CAT3 (unknown,_cgen_,s)
+#define CGEN_SYM(s) CONCAT3 (unknown,_cgen_,s)
 #endif
 
 /* This file contains the static (unchanging) pieces and as much other stuff
@@ -60,7 +51,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 #ifdef CGEN_INT_INSN
 typedef unsigned int cgen_insn_t;
 #else
-typedef char *cgen_insn_t;
+typedef char * cgen_insn_t;
 #endif
 
 #ifdef __GNUC__
@@ -71,7 +62,8 @@ typedef char *cgen_insn_t;
 
 /* Perhaps we should just use bfd.h, but it's not clear
    one would want to require that yet.  */
-enum cgen_endian {
+enum cgen_endian
+{
   CGEN_ENDIAN_UNKNOWN,
   CGEN_ENDIAN_LITTLE,
   CGEN_ENDIAN_BIG
@@ -81,8 +73,9 @@ enum cgen_endian {
    Attributes are used to describe various random things.  */
 
 /* Struct to record attribute information.  */
-typedef struct {
-  unsigned int num_nonbools;
+typedef struct
+{
+  unsigned char num_nonbools;
   unsigned int bool;
   unsigned int nonbool[1];
 } CGEN_ATTR;
@@ -94,13 +87,17 @@ typedef struct {
    nonbool: values of non-boolean attributes
    There is a maximum of 32 attributes total.  */
 #define CGEN_ATTR_TYPE(n) \
-const struct { unsigned int num_nonbools; \
+const struct { unsigned char num_nonbools; \
 	       unsigned int bool; \
 	       unsigned int nonbool[(n) ? (n) : 1]; }
 
 /* Given an attribute number, return its mask.  */
 #define CGEN_ATTR_MASK(attr) (1 << (attr))
 
+/* Return the value of boolean attribute ATTR in ATTRS.  */
+#define CGEN_BOOL_ATTR(attrs, attr) \
+((CGEN_ATTR_MASK (attr) & (attrs)) != 0)
+
 /* Return value of attribute ATTR in ATTR_TABLE for OBJ.
    OBJ is a pointer to the entity that has the attributes.
    It's not used at present but is reserved for future purposes.  */
@@ -108,6 +105,24 @@ const struct { unsigned int num_nonbools; \
 ((unsigned int) (attr) < (attr_table)->num_nonbools \
  ? ((attr_table)->nonbool[attr]) \
  : (((attr_table)->bool & (1 << (attr))) != 0))
+
+/* Attribute name/value tables.
+   These are used to assist parsing of descriptions at runtime.  */
+
+typedef struct
+{
+  const char * name;
+  int          value;
+} CGEN_ATTR_ENTRY;
+
+/* For each domain (fld,operand,insn), list of attributes.  */
+
+typedef struct
+{
+  const char *            name;
+  /* NULL for boolean attributes.  */
+  const CGEN_ATTR_ENTRY * vals;
+} CGEN_ATTR_TABLE;
 
 /* Parse result (also extraction result).
 
@@ -125,7 +140,7 @@ const struct { unsigned int num_nonbools; \
    where it varies.
 */
 
-struct cgen_fields;
+typedef struct cgen_fields CGEN_FIELDS;
 
 /* Total length of the insn, as recorded in the `fields' struct.  */
 /* ??? The field insert handler has lots of opportunities for optimization
@@ -151,7 +166,7 @@ typedef struct cgen_insn CGEN_INSN;
    The result is NULL if success or an error message.  */
 typedef const char * (cgen_parse_fn) PARAMS ((const struct cgen_insn *,
 					      const char **,
-					      struct cgen_fields *));
+					      CGEN_FIELDS *));
 
 /* Print handler.
    The first argument is a pointer to the disassembly info.
@@ -165,7 +180,7 @@ typedef const char * (cgen_parse_fn) PARAMS ((const struct cgen_insn *,
 /* Don't require bfd.h unnecessarily.  */
 #ifdef BFD_VERSION
 typedef void (cgen_print_fn) PARAMS ((PTR, const struct cgen_insn *,
-				      struct cgen_fields *, bfd_vma, int));
+				      CGEN_FIELDS *, bfd_vma, int));
 #else
 typedef void (cgen_print_fn) ();
 #endif
@@ -175,9 +190,10 @@ typedef void (cgen_print_fn) ();
    parsed.
    The second argument is a pointer to a cgen_fields struct
    from which the values are fetched.
-   The third argument is a pointer to a buffer in which to place the insn.  */
-typedef void (cgen_insert_fn) PARAMS ((const struct cgen_insn *,
-				       struct cgen_fields *, cgen_insn_t *));
+   The third argument is a pointer to a buffer in which to place the insn.
+   The result is an error message or NULL if success.  */
+typedef const char * (cgen_insert_fn) PARAMS ((const struct cgen_insn *,
+					       CGEN_FIELDS *, cgen_insn_t *));
 
 /* Extract handler.
    The first argument is a pointer to a struct describing the insn being
@@ -190,7 +206,7 @@ typedef void (cgen_insert_fn) PARAMS ((const struct cgen_insn *,
    The result is the length of the insn or zero if not recognized.  */
 typedef int (cgen_extract_fn) PARAMS ((const struct cgen_insn *,
 				       void *, cgen_insn_t,
-				       struct cgen_fields *));
+				       CGEN_FIELDS *));
 
 /* The `parse' and `insert' fields are indices into these tables.
    The elements are pointer to specialized handler functions.
@@ -207,127 +223,155 @@ extern cgen_print_fn * CGEN_SYM (print_handlers) [];
 #define CGEN_PRINT_FN(x) (CGEN_SYM (print_handlers)[(x)->base.print])
 
 /* Base class of parser/printer.
-   (Don't read too much into the use of the phrase "base class").
+   (Don't read too much into the use of the phrase "base class".
+   It's a name I'm using to organize my thoughts.)
 
    Instructions and expressions all share this data in common.
-   It's a collection of the common elements needed to parse and print
-   each of them.  */
+   It's a collection of the common elements needed to parse, insert, extract,
+   and print each of them.  */
 
-#ifndef CGEN_MAX_INSN_ATTRS
-#define CGEN_MAX_INSN_ATTRS 1
-#endif
-
-struct cgen_base {
+struct cgen_base
+{
   /* Indices into the handler tables.
      We could use pointers here instead, but in the case of the insn table,
      90% of them would be identical and that's a lot of redundant data.
      0 means use the default (what the default is is up to the code).  */
   unsigned char parse, insert, extract, print;
-
-  /* Attributes.  */
-  CGEN_ATTR_TYPE (CGEN_MAX_INSN_ATTRS) attrs;
 };
 
-/* Syntax table.
+/* Assembler interface.
 
-   Each insn and subexpression has one of these.
+   The interface to the assembler is intended to be clean in the sense that
+   libopcodes.a is a standalone entity and could be used with any assembler.
+   Not that one would necessarily want to do that but rather that it helps
+   keep a clean interface.  The interface will obviously be slanted towards
+   GAS, but at least it's a start.
 
-   The syntax "string" consists of characters (n > 0 && n < 128), and operand
-   values (n >= 128), and is terminated by 0.  Operand values are 128 + index
-   into the operand table.  The operand table doesn't exist in C, per se, as
-   the data is recorded in the parse/insert/extract/print switch statements.
+   Parsing is controlled by the assembler which calls
+   CGEN_SYM (assemble_insn).  If it can parse and build the entire insn
+   it doesn't call back to the assembler.  If it needs/wants to call back
+   to the assembler, (*cgen_parse_operand_fn) is called which can either
 
-   ??? Whether we want to use yacc instead is unclear, but we do make an
-   effort to not make doing that difficult.  At least that's the intent.
-*/
+   - return a number to be inserted in the insn
+   - return a "register" value to be inserted
+     (the register might not be a register per pe)
+   - queue the argument and return a marker saying the expression has been
+     queued (eg: a fix-up)
+   - return an error message indicating the expression wasn't recognizable
 
-struct cgen_syntax {
-  /* Original syntax string, for debugging purposes.  */
-  char *orig;
+   The result is an error message or NULL for success.
+   The parsed value is stored in the bfd_vma *.  */
 
-  /* Name of entry (that distinguishes it from all other entries).
-     This is used, for example, in simulator profiling results.  */
-  char *name;
+/* Values for indicating what the caller wants.  */
+enum cgen_parse_operand_type
+{
+  CGEN_PARSE_OPERAND_INIT,
+  CGEN_PARSE_OPERAND_INTEGER,
+  CGEN_PARSE_OPERAND_ADDRESS
+};
+
+/* Values for indicating what was parsed.
+   ??? Not too useful at present but in time.  */
+enum cgen_parse_operand_result
+{
+  CGEN_PARSE_OPERAND_RESULT_NUMBER,
+  CGEN_PARSE_OPERAND_RESULT_REGISTER,
+  CGEN_PARSE_OPERAND_RESULT_QUEUED,
+  CGEN_PARSE_OPERAND_RESULT_ERROR
+};
 
-#if 0 /* not needed yet */
-  /* Format of this insn.
-     This doesn't closely follow the notion of instruction formats for more
-     complex instruction sets.  This is the value computed at runtime.  */
-  enum cgen_fmt_type fmt;
+/* Don't require bfd.h unnecessarily.  */
+#ifdef BFD_VERSION
+extern const char * (*cgen_parse_operand_fn)
+     PARAMS ((enum cgen_parse_operand_type, const char **, int, int,
+	      enum cgen_parse_operand_result *, bfd_vma *));
 #endif
 
-  /* Mnemonic (or name if expression).  */
-  char *mnemonic;
+/* Called before trying to match a table entry with the insn.  */
+void cgen_init_parse_operand PARAMS ((void));
 
-  /* Syntax string.  */
-  /* FIXME: If each insn's mnemonic is constant, do we want to record just
-     the arguments here?  */
-#ifndef CGEN_MAX_SYNTAX_BYTES
-#define CGEN_MAX_SYNTAX_BYTES 16
-#endif
-  unsigned char syntax[CGEN_MAX_SYNTAX_BYTES];
+/* Called from <cpu>-asm.c to initialize operand parsing.  */
 
-#define CGEN_SYNTAX_CHAR_P(c) ((c) < 128)
-#define CGEN_SYNTAX_CHAR(c) (c)
-#define CGEN_SYNTAX_FIELD(c) ((c) - 128)
+/* These are GAS specific.  They're not here as part of the interface,
+   but rather that we need to put them somewhere.  */
 
-  /* recognize insn if (op & mask) == value
-     For architectures with variable length insns, this is just a preliminary
-     test.  */
-  /* FIXME: Might want a selectable type (rather than always
-     unsigned long).  */
-  unsigned long mask, value;
+/* Call this from md_assemble to initialize the assembler callback.  */
+void cgen_asm_init_parse PARAMS ((void));
 
-  /* length, in bits
-     This is the size that `mask' and `value' have been calculated to.
-     Normally it is CGEN_BASE_INSN_BITSIZE.  On vliw architectures where
-     the base insn size may be larger than the size of an insn, this field is
-     less than CGEN_BASE_INSN_BITSIZE.
-     On architectures like the 386 and m68k the real size of the insn may
-     be computed while parsing.  */
-  /* FIXME: wip, of course */
-  int length;
-};
+/* Don't require bfd.h unnecessarily.  */
+#ifdef BFD_VERSION
+/* The result is an error message or NULL for success.
+   The parsed value is stored in the bfd_vma *.  */
+const char * cgen_parse_operand PARAMS ((enum cgen_parse_operand_type,
+					 const char **, int, int,
+					 enum cgen_parse_operand_result *,
+					 bfd_vma *));
+#endif
+
+void cgen_save_fixups PARAMS ((void));
+void cgen_restore_fixups PARAMS ((void));
+void cgen_swap_fixups PARAMS ((void));
+     
+/* Add a register to the assembler's hash table.
+   This makes lets GAS parse registers for us.
+   ??? This isn't currently used, but it could be in the future.  */
+void cgen_asm_record_register PARAMS ((char *, int));
+
+/* After CGEN_SYM (assemble_insn) is done, this is called to
+   output the insn and record any fixups.  The address of the
+   assembled instruction is returned in case it is needed by
+   the caller.  */
+char * cgen_asm_finish_insn PARAMS ((const struct cgen_insn *, cgen_insn_t *,
+				   unsigned int));
 
 /* Operand values (keywords, integers, symbols, etc.)  */
 
 /* Types of assembler elements.  */
 
-enum cgen_asm_type {
+enum cgen_asm_type
+{
   CGEN_ASM_KEYWORD, CGEN_ASM_MAX
 };
 
 /* List of hardware elements.  */
 
-typedef struct cgen_hw_entry {
-  struct cgen_hw_entry *next;
-  char *name;
-  enum cgen_asm_type asm_type;
-  PTR asm_data;
+typedef struct cgen_hw_entry
+{
+  /* The type of this entry, one of `enum hw_type'.
+     This is an int and not the enum as the latter may not be declared yet.  */
+  int                          type;
+  const struct cgen_hw_entry * next;
+  char *                       name;
+  enum cgen_asm_type           asm_type;
+  PTR                          asm_data;
 } CGEN_HW_ENTRY;
 
-extern CGEN_HW_ENTRY *CGEN_SYM (hw_list);
-
-CGEN_HW_ENTRY *cgen_hw_lookup PARAMS ((const char *));
-
-#ifndef CGEN_MAX_KEYWORD_ATTRS
-#define CGEN_MAX_KEYWORD_ATTRS 1
-#endif
+const CGEN_HW_ENTRY * cgen_hw_lookup PARAMS ((const char *));
 
 /* This struct is used to describe things like register names, etc.  */
 
-typedef struct cgen_keyword_entry {
+typedef struct cgen_keyword_entry
+{
   /* Name (as in register name).  */
-  char *name;
+  char * name;
 
   /* Value (as in register number).
      The value cannot be -1 as that is used to indicate "not found".
      IDEA: Have "FUNCTION" attribute? [function is called to fetch value].  */
   int value;
 
-  /* Attributes.  */
+  /* Attributes.
+     This should, but technically needn't, appear last.  It is a variable sized
+     array in that one architecture may have 1 nonbool attribute and another
+     may have more.  Having this last means the non-architecture specific code
+     needn't care.  */
+  /* ??? Moving this last should be done by treating keywords like insn lists
+     and moving the `next' fields into a CGEN_KEYWORD_LIST struct.  */
   /* FIXME: Not used yet.  */
-  CGEN_ATTR_TYPE (CGEN_MAX_KEYWORD_ATTRS) attrs;
+#ifndef CGEN_KEYWORD_NBOOL_ATTRS
+#define CGEN_KEYWORD_NBOOL_ATTRS 1
+#endif
+  CGEN_ATTR_TYPE (CGEN_KEYWORD_NBOOL_ATTRS) attrs;
 
   /* Next name hash table entry.  */
   struct cgen_keyword_entry *next_name;
@@ -340,93 +384,138 @@ typedef struct cgen_keyword_entry {
 
    This struct supports runtime entry of new values, and hashed lookups.  */
 
-typedef struct cgen_keyword {
+typedef struct cgen_keyword
+{
   /* Pointer to initial [compiled in] values.  */
-  struct cgen_keyword_entry *init_entries;
+  CGEN_KEYWORD_ENTRY * init_entries;
+  
   /* Number of entries in `init_entries'.  */
   unsigned int num_init_entries;
+  
   /* Hash table used for name lookup.  */
-  struct cgen_keyword_entry **name_hash_table;
+  CGEN_KEYWORD_ENTRY ** name_hash_table;
+  
   /* Hash table used for value lookup.  */
-  struct cgen_keyword_entry **value_hash_table;
+  CGEN_KEYWORD_ENTRY ** value_hash_table;
+  
   /* Number of entries in the hash_tables.  */
   unsigned int hash_table_size;
+  
+  /* Pointer to null keyword "" entry if present.  */
+  const CGEN_KEYWORD_ENTRY * null_entry;
 } CGEN_KEYWORD;
 
 /* Structure used for searching.  */
 
-typedef struct cgen_keyword_search {
+typedef struct
+{
   /* Table being searched.  */
-  const struct cgen_keyword *table;
+  const CGEN_KEYWORD * table;
+  
   /* Specification of what is being searched for.  */
-  const char *spec;
+  const char * spec;
+  
   /* Current index in hash table.  */
   unsigned int current_hash;
+  
   /* Current element in current hash chain.  */
-  struct cgen_keyword_entry *current_entry;
+  CGEN_KEYWORD_ENTRY * current_entry;
 } CGEN_KEYWORD_SEARCH;
 
 /* Lookup a keyword from its name.  */
-const struct cgen_keyword_entry * cgen_keyword_lookup_name
-  PARAMS ((struct cgen_keyword *, const char *));
+const CGEN_KEYWORD_ENTRY * cgen_keyword_lookup_name
+  PARAMS ((CGEN_KEYWORD *, const char *));
 /* Lookup a keyword from its value.  */
-const struct cgen_keyword_entry * cgen_keyword_lookup_value
-  PARAMS ((struct cgen_keyword *, int));
+const CGEN_KEYWORD_ENTRY * cgen_keyword_lookup_value
+  PARAMS ((CGEN_KEYWORD *, int));
 /* Add a keyword.  */
-void cgen_keyword_add PARAMS ((struct cgen_keyword *,
-			       struct cgen_keyword_entry *));
+void cgen_keyword_add PARAMS ((CGEN_KEYWORD *, CGEN_KEYWORD_ENTRY *));
 /* Keyword searching.
    This can be used to retrieve every keyword, or a subset.  */
-struct cgen_keyword_search cgen_keyword_search_init
-  PARAMS ((struct cgen_keyword *, const char *));
-const struct cgen_keyword_entry *cgen_keyword_search_next
-  PARAMS ((struct cgen_keyword_search *));
+CGEN_KEYWORD_SEARCH cgen_keyword_search_init
+  PARAMS ((CGEN_KEYWORD *, const char *));
+const CGEN_KEYWORD_ENTRY *cgen_keyword_search_next
+  PARAMS ((CGEN_KEYWORD_SEARCH *));
 
 /* Operand value support routines.  */
 /* FIXME: some of the long's here will need to be bfd_vma or some such.  */
 
 const char * cgen_parse_keyword PARAMS ((const char **,
-					 struct cgen_keyword *,
+					 CGEN_KEYWORD *,
 					 long *));
-const char * cgen_parse_signed_integer PARAMS ((const char **, int,
-						long, long, long *));
+const char * cgen_parse_signed_integer PARAMS ((const char **, int, long *));
 const char * cgen_parse_unsigned_integer PARAMS ((const char **, int,
-						  unsigned long, unsigned long,
 						  unsigned long *));
-const char * cgen_parse_address PARAMS ((const char **, int,
-					 int, long *));
+const char * cgen_parse_address PARAMS ((const char **, int, int,
+					 enum cgen_parse_operand_result *,
+					 long *));
 const char * cgen_validate_signed_integer PARAMS ((long, long, long));
 const char * cgen_validate_unsigned_integer PARAMS ((unsigned long,
 						     unsigned long,
 						     unsigned long));
 
+/* Operand modes.  */
+
+/* ??? This duplicates the values in arch.h.  Revisit.
+   These however need the CGEN_ prefix [as does everything in this file].  */
+/* ??? Targets may need to add their own modes so we may wish to move this
+   to <arch>-opc.h, or add a hook.  */
+
+enum cgen_mode {
+  CGEN_MODE_VOID, /* FIXME: rename simulator's VM to VOID */
+  CGEN_MODE_BI, CGEN_MODE_QI, CGEN_MODE_HI, CGEN_MODE_SI, CGEN_MODE_DI,
+  CGEN_MODE_UBI, CGEN_MODE_UQI, CGEN_MODE_UHI, CGEN_MODE_USI, CGEN_MODE_UDI,
+  CGEN_MODE_SF, CGEN_MODE_DF, CGEN_MODE_XF, CGEN_MODE_TF,
+  CGEN_MODE_MAX
+};
+
+/* FIXME: Until simulator is updated.  */
+#define CGEN_MODE_VM CGEN_MODE_VOID
+
 /* This struct defines each entry in the operand table.  */
 
-#ifndef CGEN_MAX_OPERAND_ATTRS
-#define CGEN_MAX_OPERAND_ATTRS 1
-#endif
+typedef struct cgen_operand
+{
+  /* Name as it appears in the syntax string.  */
+  char * name;
 
-typedef struct cgen_operand {
-  /* For debugging.  */
-  char *name;
+  /* The hardware element associated with this operand.  */
+  const CGEN_HW_ENTRY *hw;
+
+  /* FIXME: We don't yet record ifield definitions, which we should.
+     When we do it might make sense to delete start/length (since they will
+     be duplicated in the ifield's definition) and replace them with a
+     pointer to the ifield entry.  Note that as more complicated situations
+     need to be handled, going more and more with an OOP paradigm will help
+     keep the complication under control.  Of course, this was the goal from
+     the start, but getting there in one step was too much too soon.  */
 
   /* Bit position (msb of first byte = bit 0).
+     This is just a hint, and may be unused in more complex operands.
      May be unused for a modifier.  */
   unsigned char start;
 
   /* The number of bits in the operand.
+     This is just a hint, and may be unused in more complex operands.
      May be unused for a modifier.  */
   unsigned char length;
 
-  /* Attributes.  */
-  CGEN_ATTR_TYPE (CGEN_MAX_OPERAND_ATTRS) attrs;
-#define CGEN_OPERAND_ATTRS(operand) (&(operand)->attrs)
-
-#if 0 /* ??? Interesting idea but relocs tend to get too complicated for
-	 simple table lookups to work.  */
+#if 0 /* ??? Interesting idea but relocs tend to get too complicated,
+	 and ABI dependent, for simple table lookups to work.  */
   /* Ideally this would be the internal (external?) reloc type.  */
   int reloc_type;
 #endif
+
+  /* Attributes.
+     This should, but technically needn't, appear last.  It is a variable sized
+     array in that one architecture may have 1 nonbool attribute and another
+     may have more.  Having this last means the non-architecture specific code
+     needn't care, now or tomorrow.  */
+#ifndef CGEN_OPERAND_NBOOL_ATTRS
+#define CGEN_OPERAND_NBOOL_ATTRS 1
+#endif
+  CGEN_ATTR_TYPE (CGEN_OPERAND_NBOOL_ATTRS) attrs;
+#define CGEN_OPERAND_ATTRS(operand) (&(operand)->attrs)
 } CGEN_OPERAND;
 
 /* Return value of attribute ATTR in OPERAND.  */
@@ -442,48 +531,207 @@ enum cgen_operand_type;
 /* FIXME: Rename, cpu-opc.h defines this as the typedef of the enum.  */
 #define CGEN_OPERAND_TYPE(operand) ((enum cgen_operand_type) CGEN_OPERAND_INDEX (operand))
 #define CGEN_OPERAND_ENTRY(n) (& CGEN_SYM (operand_table) [n])
+
+/* Types of parse/insert/extract/print cover-fn handlers.  */
+/* FIXME: move opindex first to match caller.  */
+/* FIXME: also need types of insert/extract/print fns.  */
+/* FIXME: not currently used as type of 3rd arg varies.  */
+typedef const char * (CGEN_PARSE_OPERAND_FN) PARAMS ((const char **, int,
+						      long *));
+
+/* Instruction operand instances.
+
+   For each instruction, a list of the hardware elements that are read and
+   written are recorded.  */
+
+/* The type of the instance.  */
+enum cgen_operand_instance_type {
+  /* End of table marker.  */
+  CGEN_OPERAND_INSTANCE_END = 0,
+  CGEN_OPERAND_INSTANCE_INPUT, CGEN_OPERAND_INSTANCE_OUTPUT
+};
+
+typedef struct
+{
+  /* The type of this operand.  */
+  enum cgen_operand_instance_type type;
+#define CGEN_OPERAND_INSTANCE_TYPE(opinst) ((opinst)->type)
+
+  /* The hardware element referenced.  */
+  const CGEN_HW_ENTRY *hw;
+#define CGEN_OPERAND_INSTANCE_HW(opinst) ((opinst)->hw)
+
+  /* The mode in which the operand is being used.  */
+  enum cgen_mode mode;
+#define CGEN_OPERAND_INSTANCE_MODE(opinst) ((opinst)->mode)
+
+  /* The operand table entry or NULL if there is none (i.e. an explicit
+     hardware reference).  */
+  const CGEN_OPERAND *operand;
+#define CGEN_OPERAND_INSTANCE_OPERAND(opinst) ((opinst)->operand)
+
+  /* If `operand' is NULL, the index (e.g. into array of registers).  */
+  int index;
+#define CGEN_OPERAND_INSTANCE_INDEX(opinst) ((opinst)->index)
+} CGEN_OPERAND_INSTANCE;
+
+/* Syntax string.
+
+   Each insn format and subexpression has one of these.
+
+   The syntax "string" consists of characters (n > 0 && n < 128), and operand
+   values (n >= 128), and is terminated by 0.  Operand values are 128 + index
+   into the operand table.  The operand table doesn't exist in C, per se, as
+   the data is recorded in the parse/insert/extract/print switch statements. */
+
+#ifndef CGEN_MAX_SYNTAX_BYTES
+#define CGEN_MAX_SYNTAX_BYTES 16
+#endif
+
+typedef struct
+{
+  unsigned char syntax[CGEN_MAX_SYNTAX_BYTES];
+} CGEN_SYNTAX;
+
+#define CGEN_SYNTAX_STRING(syn) (syn->syntax)
+#define CGEN_SYNTAX_CHAR_P(c) ((c) < 128)
+#define CGEN_SYNTAX_CHAR(c) (c)
+#define CGEN_SYNTAX_FIELD(c) ((c) - 128)
+#define CGEN_SYNTAX_MAKE_FIELD(c) ((c) + 128)
+
+/* ??? I can't currently think of any case where the mnemonic doesn't come
+   first [and if one ever doesn't building the hash tables will be tricky].
+   However, we treat mnemonics as just another operand of the instruction.
+   A value of 1 means "this is where the mnemonic appears".  1 isn't
+   special other than it's a non-printable ASCII char.  */
+#define CGEN_SYNTAX_MNEMONIC       1
+#define CGEN_SYNTAX_MNEMONIC_P(ch) ((ch) == CGEN_SYNTAX_MNEMONIC)
+
+/* Instruction formats.
+
+   Instructions are grouped by format.  Associated with an instruction is its
+   format.  Each opcode table entry contains a format table entry.
+   ??? There is usually very few formats compared with the number of insns,
+   so one can reduce the size of the opcode table by recording the format table
+   as a separate entity.  Given that we currently don't, format table entries
+   are also distinguished by their operands.  This increases the size of the
+   table, but reduces the number of tables.  It's all minutiae anyway so it
+   doesn't really matter [at this point in time].
+
+   ??? Support for variable length ISA's is wip.  */
+
+typedef struct
+{
+  /* Length that MASK and VALUE have been calculated to
+     [VALUE is recorded elsewhere].
+     Normally it is CGEN_BASE_INSN_BITSIZE.  On [V]LIW architectures where
+     the base insn size may be larger than the size of an insn, this field is
+     less than CGEN_BASE_INSN_BITSIZE.  */
+  unsigned char mask_length;
+
+  /* Total length of instruction, in bits.  */
+  unsigned char length;
+
+  /* Mask to apply to the first MASK_LENGTH bits.
+     Each insn's value is stored with the insn.
+     The first step in recognizing an insn for disassembly is
+     (opcode & mask) == value.  */
+  unsigned int mask;
+} CGEN_FORMAT;
 
 /* This struct defines each entry in the instruction table.  */
 
-struct cgen_insn {
+struct cgen_insn
+{
+  /* ??? Further table size reductions can be had by moving this element
+     either to the format table or to a separate table of its own.  Not
+     sure this is desirable yet.  */
   struct cgen_base base;
+  
 /* Given a pointer to a cgen_insn struct, return a pointer to `base'.  */
 #define CGEN_INSN_BASE(insn) (&(insn)->base)
-#define CGEN_INSN_ATTRS(insn) (&(insn)->base.attrs)
 
-  struct cgen_syntax syntax;
-#define CGEN_INSN_SYNTAX(insn) (&(insn)->syntax)
-#define CGEN_INSN_FMT(insn) ((insn)->syntax.fmt)
-#define CGEN_INSN_BITSIZE(insn) ((insn)->syntax.length)
-};
+  /* Name of entry (that distinguishes it from all other entries).
+     This is used, for example, in simulator profiling results.  */
+  /* ??? If mnemonics have operands, try to print full mnemonic.  */
+  const char * name;
+#define CGEN_INSN_NAME(insn) ((insn)->name)
 
+  /* Mnemonic.  This is used when parsing and printing the insn.
+     In the case of insns that have operands on the mnemonics, this is
+     only the constant part.  E.g. for conditional execution of an `add' insn,
+     where the full mnemonic is addeq, addne, etc., this is only "add".  */
+  const char * mnemonic;
+#define CGEN_INSN_MNEMONIC(insn) ((insn)->mnemonic)
+
+  /* Syntax string.  */
+  const CGEN_SYNTAX syntax;
+#define CGEN_INSN_SYNTAX(insn) (& (insn)->syntax)
+
+  /* Format entry.  */
+  const CGEN_FORMAT format;
+#define CGEN_INSN_MASK_BITSIZE(insn) ((insn)->format.mask_length)
+#define CGEN_INSN_BITSIZE(insn) ((insn)->format.length)
+
+  /* Instruction opcode value.  */
+  unsigned int value;
+#define CGEN_INSN_VALUE(insn) ((insn)->value)
+#define CGEN_INSN_MASK(insn) ((insn)->format.mask)
+
+  /* Pointer to NULL entry terminated table of operands used,
+     or NULL if none.  */
+  const CGEN_OPERAND_INSTANCE *operands;
+#define CGEN_INSN_OPERANDS(insn) ((insn)->operands)
+
+  /* Attributes.
+     This must appear last.  It is a variable sized array in that one
+     architecture may have 1 nonbool attribute and another may have more.
+     Having this last means the non-architecture specific code needn't
+     care.  */
+#ifndef CGEN_INSN_NBOOL_ATTRS
+#define CGEN_INSN_NBOOL_ATTRS 1
+#endif
+  CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) attrs;
+#define CGEN_INSN_ATTRS(insn) (&(insn)->attrs)
 /* Return value of attribute ATTR in INSN.  */
 #define CGEN_INSN_ATTR(insn, attr) \
 CGEN_ATTR_VALUE (insn, CGEN_INSN_ATTRS (insn), attr)
+};
 
 /* Instruction lists.
    This is used for adding new entries and for creating the hash lists.  */
 
-typedef struct cgen_insn_list {
-  struct cgen_insn_list *next;
-  const struct cgen_insn *insn;
+typedef struct cgen_insn_list
+{
+  struct cgen_insn_list * next;
+  const CGEN_INSN * insn;
 } CGEN_INSN_LIST;
 
 /* The table of instructions.  */
 
-typedef struct cgen_insn_table {
+typedef struct
+{
   /* Pointer to initial [compiled in] entries.  */
-  const struct cgen_insn *init_entries;
+  const CGEN_INSN * init_entries;
+  
+  /* Size of an entry (since the attribute member is variable sized).  */
+  unsigned int entry_size;
+  
   /* Number of entries in `init_entries', including trailing NULL entry.  */
   unsigned int num_init_entries;
+  
   /* Values added at runtime.  */
-  struct cgen_insn_list *new_entries;
+  CGEN_INSN_LIST * new_entries;
+  
   /* Assembler hash function.  */
-  unsigned int (*asm_hash) PARAMS ((const char *));
+  unsigned int (* asm_hash) PARAMS ((const char *));
+  
   /* Number of entries in assembler hash table.  */
   unsigned int asm_hash_table_size;
+  
   /* Disassembler hash function.  */
-  unsigned int (*dis_hash) PARAMS ((const char *, unsigned long));
+  unsigned int (* dis_hash) PARAMS ((const char *, unsigned long));
+  
   /* Number of entries in disassembler hash table.  */
   unsigned int dis_hash_table_size;
 } CGEN_INSN_TABLE;
@@ -498,7 +746,7 @@ extern const CGEN_INSN CGEN_SYM (insn_table_entries)[];
 
 /* Return number of instructions.  This includes any added at runtime.  */
 
-int cgen_insn_count PARAMS (());
+int cgen_insn_count PARAMS ((void));
 
 /* The assembler insn table is hashed based on some function of the mnemonic
    (the actually hashing done is up to the target, but we provide a few
@@ -541,10 +789,11 @@ CGEN_INSN_LIST * cgen_dis_lookup_insn PARAMS ((const char *, unsigned long));
 
 /* Top level structures and functions.  */
 
-typedef struct cgen_opcode_data {
-  CGEN_HW_ENTRY *hw_list;
-  /*CGEN_OPERAND_TABLE *operand_table; - FIXME:wip */
-  CGEN_INSN_TABLE *insn_table;
+typedef struct
+{
+  const CGEN_HW_ENTRY *  hw_list;
+  /*CGEN_OPERAND_TABLE * operand_table; - FIXME:wip */
+  CGEN_INSN_TABLE *      insn_table;
 } CGEN_OPCODE_DATA;
 
 /* Each CPU has one of these.  */
@@ -562,7 +811,7 @@ extern enum cgen_endian cgen_current_endian;
 
 /* Prototypes of major functions.  */
 
-/* Set the current cpu (+ mach number, endian, etc.).  *?
+/* Set the current cpu (+ mach number, endian, etc.).  */
 void cgen_set_cpu PARAMS ((CGEN_OPCODE_DATA *, int, enum cgen_endian));
 
 /* Initialize the assembler, disassembler.  */
@@ -577,28 +826,40 @@ void CGEN_SYM (init_parse) PARAMS ((void));
 void CGEN_SYM (init_print) PARAMS ((void));
 void CGEN_SYM (init_insert) PARAMS ((void));
 void CGEN_SYM (init_extract) PARAMS ((void));
+
+/* FIXME: This prototype is wrong ifndef CGEN_INT_INSN.
+   Furthermore, ifdef CGEN_INT_INSN, the insn is created in
+   target byte order (in which case why use int's at all).
+   Perhaps replace cgen_insn_t * with char *?  */
 const struct cgen_insn *
-CGEN_SYM (assemble_insn) PARAMS ((const char *, struct cgen_fields *,
+CGEN_SYM (assemble_insn) PARAMS ((const char *, CGEN_FIELDS *,
 				  cgen_insn_t *, char **));
-int CGEN_SYM (insn_supported) PARAMS ((const struct cgen_syntax *));
 #if 0 /* old */
+int CGEN_SYM (insn_supported) PARAMS ((const struct cgen_insn *));
 int CGEN_SYM (opval_supported) PARAMS ((const struct cgen_opval *));
 #endif
 
-extern const struct cgen_keyword  CGEN_SYM (operand_mach);
+extern const CGEN_KEYWORD  CGEN_SYM (operand_mach);
 int CGEN_SYM (get_mach) PARAMS ((const char *));
 
+const CGEN_INSN *
+CGEN_SYM (get_insn_operands) PARAMS ((const CGEN_INSN *, cgen_insn_t,
+				      int, int *));
+const CGEN_INSN *
+CGEN_SYM (lookup_insn) PARAMS ((const CGEN_INSN *, cgen_insn_t,
+				int, CGEN_FIELDS *, int));
+
 CGEN_INLINE void
 CGEN_SYM (put_operand) PARAMS ((int, const long *,
-				struct cgen_fields *));
+				CGEN_FIELDS *));
 CGEN_INLINE long
-CGEN_SYM (get_operand) PARAMS ((int, const struct cgen_fields *));
+CGEN_SYM (get_operand) PARAMS ((int, const CGEN_FIELDS *));
 
-CGEN_INLINE const char *
-CGEN_SYM (parse_operand) PARAMS ((int, const char **, struct cgen_fields *));
+const char *
+CGEN_SYM (parse_operand) PARAMS ((int, const char **, CGEN_FIELDS *));
 
-CGEN_INLINE const char *
-CGEN_SYM (validate_operand) PARAMS ((int, const struct cgen_fields *));
+const char *
+CGEN_SYM (insert_operand) PARAMS ((int, CGEN_FIELDS *, char *));
 
 /* Default insn parser, printer.  */
 extern cgen_parse_fn CGEN_SYM (parse_insn);
@@ -608,79 +869,5 @@ extern cgen_print_fn CGEN_SYM (print_insn);
 
 /* Read in a cpu description file.  */
 const char * cgen_read_cpu_file PARAMS ((const char *));
-
-/* Assembler interface.
-
-   The interface to the assembler is intended to be clean in the sense that
-   libopcodes.a is a standalone entity and could be used with any assembler.
-   Not that one would necessarily want to do that but rather that it helps
-   keep a clean interface.  The interface will obviously be slanted towards
-   GAS, but at least it's a start.
-
-   Parsing is controlled by the assembler which calls
-   CGEN_SYM (assemble_insn).  If it can parse and build the entire insn
-   it doesn't call back to the assembler.  If it needs/wants to call back
-   to the assembler, (*cgen_parse_operand_fn) is called which can either
-
-   - return a number to be inserted in the insn
-   - return a "register" value to be inserted
-     (the register might not be a register per pe)
-   - queue the argument and return a marker saying the expression has been
-     queued (eg: a fix-up)
-   - return an error message indicating the expression wasn't recognizable
-
-   The result is an error message or NULL for success.
-   The parsed value is stored in the bfd_vma *.  */
-
-/* Values for indicating what the caller wants.  */
-enum cgen_parse_operand_type {
-  CGEN_PARSE_OPERAND_INIT, CGEN_PARSE_OPERAND_INTEGER,
-  CGEN_PARSE_OPERAND_ADDRESS
-};
-
-/* Values for indicating what was parsed.
-   ??? Not too useful at present but in time.  */
-enum cgen_parse_operand_result {
-  CGEN_PARSE_OPERAND_RESULT_NUMBER, CGEN_PARSE_OPERAND_RESULT_REGISTER,
-  CGEN_PARSE_OPERAND_RESULT_QUEUED, CGEN_PARSE_OPERAND_RESULT_ERROR
-};
-
-/* Don't require bfd.h unnecessarily.  */
-#ifdef BFD_VERSION
-extern const char * (*cgen_parse_operand_fn)
-     PARAMS ((enum cgen_parse_operand_type, const char **, int, int,
-	      enum cgen_parse_operand_result *, bfd_vma *));
-#endif
-
-/* Called before trying to match a table entry with the insn.  */
-void cgen_init_parse_operand PARAMS ((void));
-
-/* Called from <cpu>-asm.c to initialize operand parsing.  */
-
-/* These are GAS specific.  They're not here as part of the interface,
-   but rather that we need to put them somewhere.  */
-
-/* Call this from md_assemble to initialize the assembler callback.  */
-void cgen_asm_init_parse PARAMS ((void));
-
-/* Don't require bfd.h unnecessarily.  */
-#ifdef BFD_VERSION
-/* The result is an error message or NULL for success.
-   The parsed value is stored in the bfd_vma *.  */
-const char *cgen_parse_operand PARAMS ((enum cgen_parse_operand_type,
-					const char **, int, int,
-					enum cgen_parse_operand_result *,
-					bfd_vma *));
-#endif
-
-/* Add a register to the assembler's hash table.
-   This makes lets GAS parse registers for us.
-   ??? This isn't currently used, but it could be in the future.  */
-void cgen_asm_record_register PARAMS ((char *, int));
-
-/* After CGEN_SYM (assemble_insn) is done, this is called to
-   output the insn and record any fixups.  */
-void cgen_asm_finish_insn PARAMS ((const struct cgen_insn *, cgen_insn_t *,
-				   unsigned int));
 
 #endif /* CGEN_H */
diff --git a/contrib/binutils/include/opcode/i386.h b/contrib/binutils/include/opcode/i386.h
index c74d2d6..da238c9 100644
--- a/contrib/binutils/include/opcode/i386.h
+++ b/contrib/binutils/include/opcode/i386.h
@@ -1,5 +1,5 @@
 /* i386-opcode.h -- Intel 80386 opcode table
-   Copyright 1989, 91, 92, 93, 94, 95, 96, 1997 Free Software Foundation.
+   Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation.
 
 This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger.
 
@@ -32,7 +32,12 @@ static const template i386_optab[] = {
 { "mov", 2, 0x88, _, DW|Modrm, { Reg, Reg|Mem, 0 } },
 { "mov", 2, 0xb0, _, ShortFormW, { Imm, Reg, 0 } },
 { "mov", 2, 0xc6, _,  W|Modrm,  { Imm, Reg|Mem, 0 } },
-{ "mov", 2, 0x8c, _, D|Modrm,  { SReg3|SReg2, Reg16|Mem, 0 } },
+/* The next instruction accepts WordReg so that `movl %gs,%esi' can be
+   used to move a segment register to a 32 bit register without using
+   a size prefix.  This will set the upper 16 bits of the 32 bit
+   register to an implementation defined value (on the Pentium Pro,
+   the implementation defined value is zero).  */
+{ "mov", 2, 0x8c, _, D|Modrm,  { SReg3|SReg2, WordReg|WordMem, 0 } },
 /* move to/from control debug registers */
 { "mov", 2, 0x0f20, _, D|Modrm, { Control, Reg32, 0} },
 { "mov", 2, 0x0f21, _, D|Modrm, { Debug, Reg32, 0} },
@@ -343,17 +348,10 @@ static const template i386_optab[] = {
 {"jnle", 1, 0x7f, _, Jump, { Disp, 0, 0} },
 {"jg", 1, 0x7f, _, Jump, { Disp, 0, 0} },
 
-#if 0  /* XXX where are these macros used?
-	  To get them working again, they need to take
-	  an entire template as the parameter,
-	  and check for Data16/Data32 flags.  */
-/* these turn into pseudo operations when disp is larger than 8 bits */
 #define IS_JUMP_ON_CX_ZERO(o) \
-  (o == 0x66e3)
-#define IS_JUMP_ON_ECX_ZERO(o) \
   (o == 0xe3)
-#endif
 
+/* jcxz vs. jecxz is chosen on the basis of the address size prefix.  */
 {"jcxz", 1, 0xe3, _, JumpByte|Data16, { Disp, 0, 0} },
 {"jecxz", 1, 0xe3, _, JumpByte|Data32, { Disp, 0, 0} },
 
@@ -528,19 +526,19 @@ static const template i386_optab[] = {
 /* comparison (without pop) */
 {"fcom", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} },
 {"fcoms", 1, 0xd8, 2, Modrm, { Mem, 0, 0} },	/* compare %st0, mem float  */
-{"ficoml", 1, 0xda, 2, Modrm, { Mem, 0, 0} },	/* compare %st0, mem word  */
+{"ficoml", 1, 0xda, 2, Modrm, { Mem, 0, 0} },	/* compare %st0, mem dword  */
 {"fcoml", 1, 0xdc, 2, Modrm, { Mem, 0, 0} },	/* compare %st0, mem double  */
 {"fcoml", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} },
-{"ficoms", 1, 0xde, 2, Modrm, { Mem, 0, 0} },	/* compare %st0, mem dword */
+{"ficoms", 1, 0xde, 2, Modrm, { Mem, 0, 0} },	/* compare %st0, mem word */
 
 /* comparison (with pop) */
 {"fcomp", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} },
 {"fcomp", 0, 0xd8d9, _, NoModrm, {0, 0, 0} },   /* fcomp %st, %st(1) */
 {"fcomps", 1, 0xd8, 3, Modrm, { Mem, 0, 0} },	/* compare %st0, mem float  */
-{"ficompl", 1, 0xda, 3, Modrm, { Mem, 0, 0} },	/* compare %st0, mem word  */
+{"ficompl", 1, 0xda, 3, Modrm, { Mem, 0, 0} },	/* compare %st0, mem dword  */
 {"fcompl", 1, 0xdc, 3, Modrm, { Mem, 0, 0} },	/* compare %st0, mem double  */
 {"fcompl", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} },
-{"ficomps", 1, 0xde, 3, Modrm, { Mem, 0, 0} },	/* compare %st0, mem dword */
+{"ficomps", 1, 0xde, 3, Modrm, { Mem, 0, 0} },	/* compare %st0, mem word */
 {"fcompp", 0, 0xded9, _, NoModrm, { 0, 0, 0} },	/* compare %st0, %st1 & pop 2 */
 
 /* unordered comparison (with pop) */
@@ -705,36 +703,38 @@ static const template i386_optab[] = {
 {"fabs", 0, 0xd9e1, _, NoModrm, { 0, 0, 0} },
 
 /* processor control */
-{"fninit", 0, 0xdbe3, _, NoModrm, { 0, 0, 0} },
-{"finit", 0, 0x9bdbe3, _, NoModrm, { 0, 0, 0} },
-{"fldcw", 1, 0xd9, 5, Modrm, { Mem, 0, 0} },
-{"fnstcw", 1, 0xd9, 7, Modrm, { Mem, 0, 0} },
-{"fstcw", 1, 0x9bd9, 7, Modrm, { Mem, 0, 0} },
-{"fnstsw", 1, 0xdfe0, _, NoModrm, { Acc, 0, 0} },
-{"fnstsw", 1, 0xdd, 7, Modrm, { Mem, 0, 0} },
-{"fnstsw", 0, 0xdfe0, _, NoModrm, { 0, 0, 0} },
-{"fstsw", 1, 0x9bdfe0, _, NoModrm, { Acc, 0, 0} },
-{"fstsw", 1, 0x9bdd, 7, Modrm, { Mem, 0, 0} },
-{"fstsw", 0, 0x9bdfe0, _, NoModrm, { 0, 0, 0} },
-{"fnclex", 0, 0xdbe2, _, NoModrm, { 0, 0, 0} },
-{"fclex", 0, 0x9bdbe2, _, NoModrm, { 0, 0, 0} },
-/*
- We ignore the short format (287) versions of fstenv/fldenv & fsave/frstor
- instructions;  i'm not sure how to add them or how they are different.
- My 386/387 book offers no details about this.
-*/
-{"fnstenv", 1, 0xd9, 6, Modrm, { Mem, 0, 0} },
-{"fstenv", 1, 0x9bd9, 6, Modrm, { Mem, 0, 0} },
-{"fldenv", 1, 0xd9, 4, Modrm, { Mem, 0, 0} },
-{"fnsave", 1, 0xdd, 6, Modrm, { Mem, 0, 0} },
-{"fsave", 1, 0x9bdd, 6, Modrm, { Mem, 0, 0} },
-{"frstor", 1, 0xdd, 4, Modrm, { Mem, 0, 0} },
-
-{"ffree", 1, 0xddc0, _, ShortForm, { FloatReg, 0, 0} },
+{"fninit", 0, 0xdbe3, _, NoModrm,	{ 0, 0, 0} },
+{"finit",  0, 0xdbe3, _, FWait|NoModrm, { 0, 0, 0} },
+{"fldcw",  1,	0xd9, 5, Modrm,		{ Mem, 0, 0} },
+{"fnstcw", 1,	0xd9, 7, Modrm,		{ Mem, 0, 0} },
+{"fstcw",  1,	0xd9, 7, FWait|Modrm,	{ Mem, 0, 0} },
+{"fnstsw", 1, 0xdfe0, _, NoModrm,	{ Acc, 0, 0} },
+{"fnstsw", 1,	0xdd, 7, Modrm,		{ Mem, 0, 0} },
+{"fnstsw", 0, 0xdfe0, _, NoModrm,	{ 0, 0, 0} },
+{"fstsw",  1, 0xdfe0, _, FWait|NoModrm,	{ Acc, 0, 0} },
+{"fstsw",  1,	0xdd, 7, FWait|Modrm,	{ Mem, 0, 0} },
+{"fstsw",  0, 0xdfe0, _, FWait|NoModrm,	{ 0, 0, 0} },
+{"fnclex", 0, 0xdbe2, _, NoModrm,	{ 0, 0, 0} },
+{"fclex",  0, 0xdbe2, _, FWait|NoModrm,	{ 0, 0, 0} },
+{"fnstenv",1,	0xd9, 6, Modrm,		{ Mem, 0, 0} },
+{"fstenv", 1,	0xd9, 6, FWait|Modrm,	{ Mem, 0, 0} },
+{"fldenv", 1,	0xd9, 4, Modrm,		{ Mem, 0, 0} },
+{"fnsave", 1,	0xdd, 6, Modrm,		{ Mem, 0, 0} },
+{"fsave",  1,	0xdd, 6, FWait|Modrm,	{ Mem, 0, 0} },
+{"frstor", 1,	0xdd, 4, Modrm,		{ Mem, 0, 0} },
+/* Short forms of fldenv, fstenv use data size prefix. (At least I
+   think so.  The PentPro prog ref I have says address size in one
+   place, operand size elsewhere).  FIXME: Are these the right names?  */
+{"fnstenvs",1,	0xd9, 6, Modrm|Data16,	{ Mem, 0, 0} },
+{"fstenvs", 1,	0xd9, 6, FWait|Modrm|Data16, { Mem, 0, 0} },
+{"fldenvs", 1,	0xd9, 4, Modrm|Data16,	{ Mem, 0, 0} },
+
+{"ffree",  1, 0xddc0, _, ShortForm,	{ FloatReg, 0, 0} },
 /* P6:free st(i), pop st */
-{"ffreep", 1, 0xdfc0, _, ShortForm, { FloatReg, 0, 0} },
-{"fnop", 0, 0xd9d0, _, NoModrm, { 0, 0, 0} },
-{"fwait", 0, 0x9b, _, NoModrm, { 0, 0, 0} },
+{"ffreep", 1, 0xdfc0, _, ShortForm,	{ FloatReg, 0, 0} },
+{"fnop",   0, 0xd9d0, _, NoModrm,	{ 0, 0, 0} },
+#define FWAIT_OPCODE 0x9b
+{"fwait",  0,	0x9b, _, NoModrm,	{ 0, 0, 0} },
 
 /*
   opcode prefixes; we allow them as seperate insns too
@@ -778,7 +778,7 @@ static const template i386_optab[] = {
 /* Pentium Pro extensions */
 {"rdpmc", 0, 0x0f33, _, NoModrm, { 0, 0, 0} },
 
-{"ud2", 0, 0x0fff, _, NoModrm, {0, 0, 0} }, /* official undefined instr. */
+{"ud2", 0, 0x0f0b, _, NoModrm, {0, 0, 0} }, /* official undefined instr. */
 
 {"cmovo",  2, 0x0f40, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
 {"cmovno", 2, 0x0f41, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} },
@@ -828,7 +828,7 @@ static const template i386_optab[] = {
 {"paddsw",    2, 0x0fed, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
 {"paddusb",   2, 0x0fdc, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
 {"paddusw",   2, 0x0fdd, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
-{"pand",      2, 0x0fda, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
+{"pand",      2, 0x0fdb, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
 {"pandn",     2, 0x0fdf, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
 {"pcmpeqb",   2, 0x0f74, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
 {"pcmpeqw",   2, 0x0f75, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } },
@@ -950,9 +950,9 @@ static const seg_entry *const two_byte_segment_defaults[] = {
   /* mode 0 */
   &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
   /* mode 1 */
-  &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
+  &ds, &ds, &ds, &ds, &ss, &ss, &ds, &ds,
   /* mode 2 */
-  &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds,
+  &ds, &ds, &ds, &ds, &ss, &ss, &ds, &ds,
   /* mode 3 --- not a memory reference; never referenced */
 };
 
diff --git a/contrib/binutils/include/opcode/tic30.h b/contrib/binutils/include/opcode/tic30.h
new file mode 100644
index 0000000..a700275
--- /dev/null
+++ b/contrib/binutils/include/opcode/tic30.h
@@ -0,0 +1,691 @@
+/* tic30.h -- Header file for TI TMS320C30 opcode table
+   Copyright 1998 Free Software Foundation, Inc.
+   Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
+
+This file is part of GDB, GAS, and the GNU binutils.
+
+GDB, GAS, and the GNU binutils are free software; you can redistribute
+them and/or modify them under the terms of the GNU General Public
+License as published by the Free Software Foundation; either version
+1, or (at your option) any later version.
+
+GDB, GAS, and the GNU binutils are distributed in the hope that they
+will be useful, but WITHOUT ANY WARRANTY; without even the implied
+warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+the GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this file; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA
+02111-1307, USA.  */
+
+/* FIXME: The opcode table should be in opcodes/tic30-opc.c, not in a
+   header file.  */
+
+#ifndef _TMS320_H_
+#define _TMS320_H_
+
+struct _register
+{
+  char *name;
+  unsigned char opcode;
+  unsigned char regtype;
+};
+
+typedef struct _register reg;
+
+#define REG_Rn    0x01
+#define REG_ARn   0x02
+#define REG_DP    0x03
+#define REG_OTHER 0x04
+
+static const reg tic30_regtab[] = {
+  { "r0", 0x00, REG_Rn },
+  { "r1", 0x01, REG_Rn },
+  { "r2", 0x02, REG_Rn },
+  { "r3", 0x03, REG_Rn },
+  { "r4", 0x04, REG_Rn },
+  { "r5", 0x05, REG_Rn },
+  { "r6", 0x06, REG_Rn },
+  { "r7", 0x07, REG_Rn },
+  { "ar0",0x08, REG_ARn },
+  { "ar1",0x09, REG_ARn },
+  { "ar2",0x0A, REG_ARn },
+  { "ar3",0x0B, REG_ARn },
+  { "ar4",0x0C, REG_ARn },
+  { "ar5",0x0D, REG_ARn },
+  { "ar6",0x0E, REG_ARn },
+  { "ar7",0x0F, REG_ARn },
+  { "dp", 0x10, REG_DP },
+  { "ir0",0x11, REG_OTHER },
+  { "ir1",0x12, REG_OTHER },
+  { "bk", 0x13, REG_OTHER },
+  { "sp", 0x14, REG_OTHER },
+  { "st", 0x15, REG_OTHER },
+  { "ie", 0x16, REG_OTHER },
+  { "if", 0x17, REG_OTHER },
+  { "iof",0x18, REG_OTHER },
+  { "rs", 0x19, REG_OTHER },
+  { "re", 0x1A, REG_OTHER },
+  { "rc", 0x1B, REG_OTHER },
+  { "R0", 0x00, REG_Rn },
+  { "R1", 0x01, REG_Rn },
+  { "R2", 0x02, REG_Rn },
+  { "R3", 0x03, REG_Rn },
+  { "R4", 0x04, REG_Rn },
+  { "R5", 0x05, REG_Rn },
+  { "R6", 0x06, REG_Rn },
+  { "R7", 0x07, REG_Rn },
+  { "AR0",0x08, REG_ARn },
+  { "AR1",0x09, REG_ARn },
+  { "AR2",0x0A, REG_ARn },
+  { "AR3",0x0B, REG_ARn },
+  { "AR4",0x0C, REG_ARn },
+  { "AR5",0x0D, REG_ARn },
+  { "AR6",0x0E, REG_ARn },
+  { "AR7",0x0F, REG_ARn },
+  { "DP", 0x10, REG_DP },
+  { "IR0",0x11, REG_OTHER },
+  { "IR1",0x12, REG_OTHER },
+  { "BK", 0x13, REG_OTHER },
+  { "SP", 0x14, REG_OTHER },
+  { "ST", 0x15, REG_OTHER },
+  { "IE", 0x16, REG_OTHER },
+  { "IF", 0x17, REG_OTHER },
+  { "IOF",0x18, REG_OTHER },
+  { "RS", 0x19, REG_OTHER },
+  { "RE", 0x1A, REG_OTHER },
+  { "RC", 0x1B, REG_OTHER },
+  { "",   0, 0 }
+};
+
+static const reg *const tic30_regtab_end
+  = tic30_regtab + sizeof(tic30_regtab)/sizeof(tic30_regtab[0]);
+
+/* Indirect Addressing Modes Modification Fields */
+/* Indirect Addressing with Displacement */
+#define PreDisp_Add        0x00
+#define PreDisp_Sub        0x01
+#define PreDisp_Add_Mod    0x02
+#define PreDisp_Sub_Mod    0x03
+#define PostDisp_Add_Mod   0x04
+#define PostDisp_Sub_Mod   0x05
+#define PostDisp_Add_Circ  0x06
+#define PostDisp_Sub_Circ  0x07
+/* Indirect Addressing with Index Register IR0 */
+#define PreIR0_Add         0x08
+#define PreIR0_Sub         0x09
+#define PreIR0_Add_Mod     0x0A
+#define PreIR0_Sub_Mod     0x0B
+#define PostIR0_Add_Mod    0x0C
+#define PostIR0_Sub_Mod    0x0D
+#define PostIR0_Add_Circ   0x0E
+#define PostIR0_Sub_Circ   0x0F
+/* Indirect Addressing with Index Register IR1 */
+#define PreIR1_Add         0x10
+#define PreIR1_Sub         0x11
+#define PreIR1_Add_Mod     0x12
+#define PreIR1_Sub_Mod     0x13
+#define PostIR1_Add_Mod    0x14
+#define PostIR1_Sub_Mod    0x15
+#define PostIR1_Add_Circ   0x16
+#define PostIR1_Sub_Circ   0x17
+/* Indirect Addressing (Special Cases) */
+#define IndirectOnly       0x18
+#define PostIR0_Add_BitRev 0x19
+
+typedef struct {
+  char *syntax;
+  unsigned char modfield;
+  unsigned char displacement;
+} ind_addr_type;
+
+#define IMPLIED_DISP  0x01
+#define DISP_REQUIRED 0x02
+#define NO_DISP       0x03
+
+static const ind_addr_type tic30_indaddr_tab[] = {
+  { "*+ar",       PreDisp_Add,        IMPLIED_DISP },
+  { "*-ar",       PreDisp_Sub,        IMPLIED_DISP },
+  { "*++ar",      PreDisp_Add_Mod,    IMPLIED_DISP },
+  { "*--ar",      PreDisp_Sub_Mod,    IMPLIED_DISP },
+  { "*ar++",      PostDisp_Add_Mod,   IMPLIED_DISP },
+  { "*ar--",      PostDisp_Sub_Mod,   IMPLIED_DISP },
+  { "*ar++%",     PostDisp_Add_Circ,  IMPLIED_DISP },
+  { "*ar--%",     PostDisp_Sub_Circ,  IMPLIED_DISP },
+  { "*+ar()",     PreDisp_Add,        DISP_REQUIRED },
+  { "*-ar()",     PreDisp_Sub,        DISP_REQUIRED },
+  { "*++ar()",    PreDisp_Add_Mod,    DISP_REQUIRED },
+  { "*--ar()",    PreDisp_Sub_Mod,    DISP_REQUIRED },
+  { "*ar++()",    PostDisp_Add_Mod,   DISP_REQUIRED },
+  { "*ar--()",    PostDisp_Sub_Mod,   DISP_REQUIRED },
+  { "*ar++()%",   PostDisp_Add_Circ,  DISP_REQUIRED },
+  { "*ar--()%",   PostDisp_Sub_Circ,  DISP_REQUIRED },
+  { "*+ar(ir0)",  PreIR0_Add,         NO_DISP },
+  { "*-ar(ir0)",  PreIR0_Sub,         NO_DISP },
+  { "*++ar(ir0)", PreIR0_Add_Mod,     NO_DISP },
+  { "*--ar(ir0)", PreIR0_Sub_Mod,     NO_DISP },
+  { "*ar++(ir0)", PostIR0_Add_Mod,    NO_DISP },
+  { "*ar--(ir0)", PostIR0_Sub_Mod,    NO_DISP },
+  { "*ar++(ir0)%",PostIR0_Add_Circ,   NO_DISP },
+  { "*ar--(ir0)%",PostIR0_Sub_Circ,   NO_DISP },
+  { "*+ar(ir1)",  PreIR1_Add,         NO_DISP },
+  { "*-ar(ir1)",  PreIR1_Sub,         NO_DISP },
+  { "*++ar(ir1)", PreIR1_Add_Mod,     NO_DISP },
+  { "*--ar(ir1)", PreIR1_Sub_Mod,     NO_DISP },
+  { "*ar++(ir1)", PostIR1_Add_Mod,    NO_DISP },
+  { "*ar--(ir1)", PostIR1_Sub_Mod,    NO_DISP },
+  { "*ar++(ir1)%",PostIR1_Add_Circ,   NO_DISP },
+  { "*ar--(ir1)%",PostIR1_Sub_Circ,   NO_DISP },
+  { "*ar",        IndirectOnly,       NO_DISP },
+  { "*ar++(ir0)b",PostIR0_Add_BitRev, NO_DISP },
+  { "",           0,0 }
+};
+
+static const ind_addr_type *const tic30_indaddrtab_end
+  = tic30_indaddr_tab + sizeof(tic30_indaddr_tab)/sizeof(tic30_indaddr_tab[0]);
+
+/* Possible operand types */
+/* Register types */
+#define Rn       0x0001
+#define ARn      0x0002
+#define DPReg    0x0004
+#define OtherReg 0x0008
+/* Addressing mode types */
+#define Direct   0x0010
+#define Indirect 0x0020
+#define Imm16    0x0040
+#define Disp     0x0080
+#define Imm24    0x0100
+#define Abs24    0x0200
+/* 3 operand addressing mode types */
+#define op3T1    0x0400
+#define op3T2    0x0800
+/* Interrupt vector */
+#define IVector  0x1000
+/* Not required */
+#define NotReq   0x2000
+
+#define GAddr1   Rn | Direct | Indirect | Imm16
+#define GAddr2   GAddr1 | AllReg
+#define TAddr1   op3T1 | Rn | Indirect
+#define TAddr2   op3T2 | Rn | Indirect
+#define Reg      Rn | ARn
+#define AllReg   Reg | DPReg | OtherReg
+
+typedef struct _template
+{
+  char *name;
+  unsigned int operands; /* how many operands */
+  unsigned int base_opcode; /* base_opcode is the fundamental opcode byte */
+  /* the bits in opcode_modifier are used to generate the final opcode from
+     the base_opcode.  These bits also are used to detect alternate forms of
+     the same instruction */
+  unsigned int opcode_modifier;
+
+  /* opcode_modifier bits: */
+#define AddressMode 0x00600000
+#define PCRel       0x02000000
+#define StackOp     0x001F0000
+#define Rotate      StackOp
+  
+  /* operand_types[i] describes the type of operand i.  This is made
+     by OR'ing together all of the possible type masks.  (e.g.
+     'operand_types[i] = Reg|Imm' specifies that operand i can be
+     either a register or an immediate operand */
+  unsigned int operand_types[3];
+  /* This defines the number type of an immediate argument to an instruction. */
+  int imm_arg_type;
+#define Imm_None  0
+#define Imm_Float 1
+#define Imm_SInt  2
+#define Imm_UInt  3
+}
+template;
+
+static const template tic30_optab[] = {
+  { "absf"   ,2,0x00000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "absi"   ,2,0x00800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "addc"   ,2,0x01000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "addc3"  ,3,0x20000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
+  { "addf"   ,2,0x01800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "addf3"  ,3,0x20800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
+  { "addi"   ,2,0x02000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "addi3"  ,3,0x21000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
+  { "and"    ,2,0x02800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
+  { "and3"   ,3,0x21800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
+  { "andn"   ,2,0x03000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
+  { "andn3"  ,3,0x22000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
+  { "ash"    ,2,0x03800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ash3"   ,3,0x22800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
+  { "b"      ,1,0x68000000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bu"     ,1,0x68000000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "blo"    ,1,0x68010000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bls"    ,1,0x68020000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bhi"    ,1,0x68030000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bhs"    ,1,0x68040000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "beq"    ,1,0x68050000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bne"    ,1,0x68060000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "blt"    ,1,0x68070000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "ble"    ,1,0x68080000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bgt"    ,1,0x68090000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bge"    ,1,0x680A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bz"     ,1,0x68050000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnz"    ,1,0x68060000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bp"     ,1,0x68090000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bn"     ,1,0x68070000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnn"    ,1,0x680A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnv"    ,1,0x680C0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bv"     ,1,0x680D0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnuf"   ,1,0x680E0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "buf"    ,1,0x680F0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnc"    ,1,0x68040000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bc"     ,1,0x68010000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnlv"   ,1,0x68100000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "blv"    ,1,0x68110000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnluf"  ,1,0x68120000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bluf"   ,1,0x68130000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bzuf"   ,1,0x68140000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bd"     ,1,0x68200000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bud"    ,1,0x68200000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "blod"   ,1,0x68210000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "blsd"   ,1,0x68220000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bhid"   ,1,0x68230000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bhsd"   ,1,0x68240000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "beqd"   ,1,0x68250000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bned"   ,1,0x68260000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bltd"   ,1,0x68270000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bled"   ,1,0x68280000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bgtd"   ,1,0x68290000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bged"   ,1,0x682A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bzd"    ,1,0x68250000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnzd"   ,1,0x68260000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bpd"    ,1,0x68290000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnd"    ,1,0x68270000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnnd"   ,1,0x682A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnvd"   ,1,0x682C0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bvd"    ,1,0x682D0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnufd"  ,1,0x682E0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bufd"   ,1,0x682F0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bncd"   ,1,0x68240000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bcd"    ,1,0x68210000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnlvd"  ,1,0x68300000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "blvd"   ,1,0x68310000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bnlufd" ,1,0x68320000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "blufd"  ,1,0x68330000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "bzufd"  ,1,0x68340000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_None },
+  { "br"     ,1,0x60000000,0,           { Imm24, 0, 0 }, Imm_UInt },
+  { "brd"    ,1,0x61000000,0,           { Imm24, 0, 0 }, Imm_UInt },
+  { "call"   ,1,0x62000000,0,           { Imm24, 0, 0 }, Imm_UInt },
+  { "callu"  ,1,0x70000000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "calllo" ,1,0x70010000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callls" ,1,0x70020000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callhi" ,1,0x70030000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callhs" ,1,0x70040000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "calleq" ,1,0x70050000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callne" ,1,0x70060000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "calllt" ,1,0x70070000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callle" ,1,0x70080000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callgt" ,1,0x70090000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callge" ,1,0x700A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callz"  ,1,0x70050000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callnz" ,1,0x70060000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callp"  ,1,0x70090000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "calln"  ,1,0x70070000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callnn" ,1,0x700A0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callnv" ,1,0x700C0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callv"  ,1,0x700D0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callnuf",1,0x700E0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "calluf" ,1,0x700F0000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callnc" ,1,0x70040000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callc"  ,1,0x70010000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callnlv",1,0x70100000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "calllv" ,1,0x70110000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callnluf",1,0x70120000,PCRel,      { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callluf",1,0x70130000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "callzuf",1,0x70140000,PCRel,       { AllReg|Disp, 0, 0 }, Imm_UInt },
+  { "cmpf"   ,2,0x04000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "cmpf3"  ,2,0x23000000,AddressMode, { TAddr1, TAddr2, 0 }, Imm_None },
+  { "cmpi"   ,2,0x04800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "cmpi3"  ,2,0x23800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None },
+  { "db"     ,2,0x6C000000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbu"    ,2,0x6C000000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dblo"   ,2,0x6C010000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbls"   ,2,0x6C020000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbhi"   ,2,0x6C030000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbhs"   ,2,0x6C040000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbeq"   ,2,0x6C050000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbne"   ,2,0x6C060000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dblt"   ,2,0x6C070000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dble"   ,2,0x6C080000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbgt"   ,2,0x6C090000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbge"   ,2,0x6C0A0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbz"    ,2,0x6C050000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnz"   ,2,0x6C060000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbp"    ,2,0x6C090000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbn"    ,2,0x6C070000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnn"   ,2,0x6C0A0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnv"   ,2,0x6C0C0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbv"    ,2,0x6C0D0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnuf"  ,2,0x6C0E0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbuf"   ,2,0x6C0F0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnc"   ,2,0x6C040000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbc"    ,2,0x6C010000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnlv"  ,2,0x6C100000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dblv"   ,2,0x6C110000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnluf" ,2,0x6C120000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbluf"  ,2,0x6C130000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbzuf"  ,2,0x6C140000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbd"    ,2,0x6C200000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbud"   ,2,0x6C200000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dblod"  ,2,0x6C210000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dblsd"  ,2,0x6C220000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbhid"  ,2,0x6C230000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbhsd"  ,2,0x6C240000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbeqd"  ,2,0x6C250000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbned"  ,2,0x6C260000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbltd"  ,2,0x6C270000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbled"  ,2,0x6C280000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbgtd"  ,2,0x6C290000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbged"  ,2,0x6C2A0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbzd"   ,2,0x6C250000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnzd"  ,2,0x6C260000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbpd"   ,2,0x6C290000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnd"   ,2,0x6C270000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnnd"  ,2,0x6C2A0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnvd"  ,2,0x6C2C0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbvd"   ,2,0x6C2D0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnufd" ,2,0x6C2E0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbufd"  ,2,0x6C2F0000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbncd"  ,2,0x6C240000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbcd"   ,2,0x6C210000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnlvd" ,2,0x6C300000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dblvd"  ,2,0x6C310000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbnlufd",2,0x6C320000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dblufd" ,2,0x6C330000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "dbzufd" ,2,0x6C340000,PCRel,       { ARn, AllReg|Disp, 0 }, Imm_None },
+  { "fix"    ,2,0x05000000,AddressMode, { GAddr1, AllReg, 0 }, Imm_Float },
+  { "float"  ,2,0x05800000,AddressMode, { GAddr2, Rn, 0 }, Imm_SInt },
+  { "iack"   ,1,0x1B000000,AddressMode, { Direct|Indirect, 0, 0 }, Imm_None },
+  { "idle"   ,0,0x06000000,0,           { 0, 0, 0 }, Imm_None },
+  { "idle2"  ,0,0x06000001,0,           { 0, 0, 0 }, Imm_None }, /* LC31 Only */
+  { "lde"    ,2,0x06800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldf"    ,2,0x07000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfu"   ,2,0x40000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldflo"  ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfls"  ,2,0x41000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfhi"  ,2,0x41800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfhs"  ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfeq"  ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfne"  ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldflt"  ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfle"  ,2,0x44000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfgt"  ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfge"  ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfz"   ,2,0x42800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfnz"  ,2,0x43000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfp"   ,2,0x44800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfn"   ,2,0x43800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfnn"  ,2,0x45000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfnv"  ,2,0x46000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfv"   ,2,0x46800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfnuf" ,2,0x47000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfuf"  ,2,0x47800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfnc"  ,2,0x42000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfc"   ,2,0x40800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfnlv" ,2,0x48000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldflv"  ,2,0x48800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfnluf",2,0x49000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfluf" ,2,0x49800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfzuf" ,2,0x4A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldfi"   ,2,0x07800000,AddressMode, { Direct|Indirect, Rn, 0 }, Imm_None },
+  { "ldi"    ,2,0x08000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldiu"   ,2,0x50000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldilo"  ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldils"  ,2,0x51000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldihi"  ,2,0x51800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldihs"  ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldieq"  ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldine"  ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldilt"  ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldile"  ,2,0x54000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldigt"  ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldige"  ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldiz"   ,2,0x52800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldinz"  ,2,0x53000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldip"   ,2,0x54800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldin"   ,2,0x53800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldinn"  ,2,0x55000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldinv"  ,2,0x56000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldiv"   ,2,0x56800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldinuf" ,2,0x57000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldiuf"  ,2,0x57800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldinc"  ,2,0x52000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldic"   ,2,0x50800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldinlv" ,2,0x58000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldilv"  ,2,0x58800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldinluf",2,0x59000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldiluf" ,2,0x59800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldizuf" ,2,0x5A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "ldii"   ,2,0x08800000,AddressMode, { Direct|Indirect, AllReg, 0 }, Imm_None },
+  { "ldm"    ,2,0x09000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "ldp"    ,2,0x08700000,0,           { Abs24|Direct, DPReg|NotReq, 0 }, Imm_UInt },
+  { "lopower",0,0x10800001,0,           { 0, 0, 0 }, Imm_None }, /* LC31 Only */
+  { "lsh"    ,2,0x09800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
+  { "lsh3"   ,3,0x24000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
+  { "maxspeed",0,0x10800000,0,          { 0, 0, 0 }, Imm_None }, /* LC31 Only */
+  { "mpyf"   ,2,0x0A000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "mpyf3"  ,3,0x24800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
+  { "mpyi"   ,2,0x0A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "mpyi3"  ,3,0x25000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
+  { "negb"   ,2,0x0B000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "negf"   ,2,0x0B800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "negi"   ,2,0x0C000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "nop"    ,1,0x0C800000,AddressMode, { AllReg|Indirect|NotReq, 0, 0 }, Imm_None },
+  { "norm"   ,2,0x0D000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float }, /*Check another source*/
+  { "not"    ,2,0x0D800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
+  { "or"     ,2,0x10000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
+  { "or3"    ,3,0x25800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
+  { "pop"    ,1,0x0E200000,StackOp,     { AllReg, 0, 0 }, Imm_None },
+  { "popf"   ,1,0x0EA00000,StackOp,     { Rn, 0, 0 }, Imm_None },
+  { "push"   ,1,0x0F200000,StackOp,     { AllReg, 0, 0 }, Imm_None },
+  { "pushf"  ,1,0x0FA00000,StackOp,     { Rn, 0, 0 }, Imm_None },
+  { "reti"   ,0,0x78000000,0,           { 0, 0, 0 }, Imm_None },
+  { "retiu"  ,0,0x78000000,0,           { 0, 0, 0 }, Imm_None },
+  { "retilo" ,0,0x78010000,0,           { 0, 0, 0 }, Imm_None },
+  { "retils" ,0,0x78020000,0,           { 0, 0, 0 }, Imm_None },
+  { "retihi" ,0,0x78030000,0,           { 0, 0, 0 }, Imm_None },
+  { "retihs" ,0,0x78040000,0,           { 0, 0, 0 }, Imm_None },
+  { "retieq" ,0,0x78050000,0,           { 0, 0, 0 }, Imm_None },
+  { "retine" ,0,0x78060000,0,           { 0, 0, 0 }, Imm_None },
+  { "retilt" ,0,0x78070000,0,           { 0, 0, 0 }, Imm_None },
+  { "retile" ,0,0x78080000,0,           { 0, 0, 0 }, Imm_None },
+  { "retigt" ,0,0x78090000,0,           { 0, 0, 0 }, Imm_None },
+  { "retige" ,0,0x780A0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retiz"  ,0,0x78050000,0,           { 0, 0, 0 }, Imm_None },
+  { "retinz" ,0,0x78060000,0,           { 0, 0, 0 }, Imm_None },
+  { "retip"  ,0,0x78090000,0,           { 0, 0, 0 }, Imm_None },
+  { "retin"  ,0,0x78070000,0,           { 0, 0, 0 }, Imm_None },
+  { "retinn" ,0,0x780A0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retinv" ,0,0x780C0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retiv"  ,0,0x780D0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retinuf",0,0x780E0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retiuf" ,0,0x780F0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retinc" ,0,0x78040000,0,           { 0, 0, 0 }, Imm_None },
+  { "retic"  ,0,0x78010000,0,           { 0, 0, 0 }, Imm_None },
+  { "retinlv",0,0x78100000,0,           { 0, 0, 0 }, Imm_None },
+  { "retilv" ,0,0x78110000,0,           { 0, 0, 0 }, Imm_None },
+  { "retinluf",0,0x78120000,0,          { 0, 0, 0 }, Imm_None },
+  { "retiluf",0,0x78130000,0,           { 0, 0, 0 }, Imm_None },
+  { "retizuf",0,0x78140000,0,           { 0, 0, 0 }, Imm_None },
+  { "rets"   ,0,0x78800000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsu"  ,0,0x78800000,0,           { 0, 0, 0 }, Imm_None },
+  { "retslo" ,0,0x78810000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsls" ,0,0x78820000,0,           { 0, 0, 0 }, Imm_None },
+  { "retshi" ,0,0x78830000,0,           { 0, 0, 0 }, Imm_None },
+  { "retshs" ,0,0x78840000,0,           { 0, 0, 0 }, Imm_None },
+  { "retseq" ,0,0x78850000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsne" ,0,0x78860000,0,           { 0, 0, 0 }, Imm_None },
+  { "retslt" ,0,0x78870000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsle" ,0,0x78880000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsgt" ,0,0x78890000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsge" ,0,0x788A0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsz"  ,0,0x78850000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsnz" ,0,0x78860000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsp"  ,0,0x78890000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsn"  ,0,0x78870000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsnn" ,0,0x788A0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsnv" ,0,0x788C0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsv"  ,0,0x788D0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsnuf",0,0x788E0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsuf" ,0,0x788F0000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsnc" ,0,0x78840000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsc"  ,0,0x78810000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsnlv",0,0x78900000,0,           { 0, 0, 0 }, Imm_None },
+  { "retslv" ,0,0x78910000,0,           { 0, 0, 0 }, Imm_None },
+  { "retsnluf",0,0x78920000,0,          { 0, 0, 0 }, Imm_None },
+  { "retsluf",0,0x78930000,0,           { 0, 0, 0 }, Imm_None },
+  { "retszuf",0,0x78940000,0,           { 0, 0, 0 }, Imm_None },
+  { "rnd"    ,2,0x11000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "rol"    ,1,0x11E00001,Rotate,      { AllReg, 0, 0 }, Imm_None },
+  { "rolc"   ,1,0x12600001,Rotate,      { AllReg, 0, 0 }, Imm_None },
+  { "ror"    ,1,0x12E0FFFF,Rotate,      { AllReg, 0, 0 }, Imm_None },
+  { "rorc"   ,1,0x1360FFFF,Rotate,      { AllReg, 0, 0 }, Imm_None },
+  { "rptb"   ,1,0x64000000,0,           { Imm24, 0, 0 }, Imm_UInt },
+  { "rpts"   ,1,0x139B0000,AddressMode, { GAddr2, 0, 0 }, Imm_UInt },
+  { "sigi"   ,0,0x16000000,0,           { 0, 0, 0 }, Imm_None },
+  { "stf"    ,2,0x14000000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float },
+  { "stfi"   ,2,0x14800000,AddressMode, { Rn, Direct|Indirect, 0 }, Imm_Float },
+  { "sti"    ,2,0x15000000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt },
+  { "stii"   ,2,0x15800000,AddressMode, { AllReg, Direct|Indirect, 0 }, Imm_SInt },
+  { "subb"   ,2,0x16800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "subb3"  ,3,0x26000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
+  { "subc"   ,2,0x17000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
+  { "subf"   ,2,0x17800000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "subf3"  ,3,0x26800000,AddressMode, { TAddr1, TAddr2, Rn }, Imm_None },
+  { "subi"   ,2,0x18000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "subi3"  ,3,0x27000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
+  { "subrb"  ,2,0x18800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "subrf"  ,2,0x19000000,AddressMode, { GAddr1, Rn, 0 }, Imm_Float },
+  { "subri"  ,2,0x19800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_SInt },
+  { "swi"    ,0,0x66000000,0,           { 0, 0, 0 }, Imm_None },
+  { "trap"   ,1,0x74800020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapu"  ,1,0x74800020,0,           { IVector, 0, 0 }, Imm_None },
+  { "traplo" ,1,0x74810020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapls" ,1,0x74820020,0,           { IVector, 0, 0 }, Imm_None },
+  { "traphi" ,1,0x74830020,0,           { IVector, 0, 0 }, Imm_None },
+  { "traphs" ,1,0x74840020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapeq" ,1,0x74850020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapne" ,1,0x74860020,0,           { IVector, 0, 0 }, Imm_None },
+  { "traplt" ,1,0x74870020,0,           { IVector, 0, 0 }, Imm_None },
+  { "traple" ,1,0x74880020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapgt" ,1,0x74890020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapge" ,1,0x748A0020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapz"  ,1,0x74850020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapnz" ,1,0x74860020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapp"  ,1,0x74890020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapn"  ,1,0x74870020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapnn" ,1,0x748A0020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapnv" ,1,0x748C0020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapv"  ,1,0x748D0020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapnuf",1,0x748E0020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapuf" ,1,0x748F0020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapnc" ,1,0x74840020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapc"  ,1,0x74810020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapnlv",1,0x74900020,0,           { IVector, 0, 0 }, Imm_None },
+  { "traplv" ,1,0x74910020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapnluf",1,0x74920020,0,          { IVector, 0, 0 }, Imm_None },
+  { "trapluf",1,0x74930020,0,           { IVector, 0, 0 }, Imm_None },
+  { "trapzuf",1,0x74940020,0,           { IVector, 0, 0 }, Imm_None },
+  { "tstb"   ,2,0x1A000000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
+  { "tstb3"  ,2,0x27800000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, 0 }, Imm_None },
+  { "xor"    ,2,0x1A800000,AddressMode, { GAddr2, AllReg, 0 }, Imm_UInt },
+  { "xor3"   ,3,0x28000000,AddressMode, { TAddr1|AllReg, TAddr2|AllReg, AllReg }, Imm_None },
+  { ""       ,0,0x00000000,0,           { 0, 0, 0 }, 0 }
+};
+
+static const template *const tic30_optab_end =
+  tic30_optab + sizeof(tic30_optab)/sizeof(tic30_optab[0]);
+
+typedef struct {
+  char *name;
+  unsigned int operands_1;
+  unsigned int operands_2;
+  unsigned int base_opcode;
+  unsigned int operand_types[2][3];
+  /* Which operand fits into which part of the final opcode word. */
+  int oporder;
+} partemplate;
+
+/* oporder defines - not very descriptive. */
+#define OO_4op1   0
+#define OO_4op2   1
+#define OO_4op3   2
+#define OO_5op1   3
+#define OO_5op2   4
+#define OO_PField 5
+
+static const partemplate tic30_paroptab[] = {
+  { "q_absf_stf",   2,2,0xC8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
+	OO_4op1 },
+  { "q_absi_sti",   2,2,0xCA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
+	OO_4op1 },
+  { "q_addf3_stf",  3,2,0xCC000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
+	OO_5op1 },
+  { "q_addi3_sti",  3,2,0xCE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
+	OO_5op1 },
+  { "q_and3_sti",   3,2,0xD0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
+	OO_5op1 },
+  { "q_ash3_sti",   3,2,0xD2000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
+	OO_5op2 },
+  { "q_fix_sti",    2,2,0xD4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
+	OO_4op1 },
+  { "q_float_stf",  2,2,0xD6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
+	OO_4op1 },
+  { "q_ldf_ldf",    2,2,0xC4000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } },
+	OO_4op2 },
+  { "q_ldf_stf",    2,2,0xD8000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
+	OO_4op1 },
+  { "q_ldi_ldi",    2,2,0xC6000000, { { Indirect, Rn, 0 }, { Indirect, Rn, 0 } },
+	OO_4op2 },
+  { "q_ldi_sti",    2,2,0xDA000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
+	OO_4op1 },
+  { "q_lsh3_sti",   3,2,0xDC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
+	OO_5op2 },
+  { "q_mpyf3_addf3",3,3,0x80000000, { { Rn | Indirect, Rn | Indirect, Rn },
+ 	                              { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
+  { "q_mpyf3_stf",  3,2,0xDE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
+	OO_5op1 },
+  { "q_mpyf3_subf3",3,3,0x84000000, { { Rn | Indirect, Rn | Indirect, Rn },
+	                              { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
+  { "q_mpyi3_addi3",3,3,0x88000000, { { Rn | Indirect, Rn | Indirect, Rn },
+	                              { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
+  { "q_mpyi3_sti",  3,2,0xE0000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
+	OO_5op1 },
+  { "q_mpyi3_subi3",3,3,0x8C000000, { { Rn | Indirect, Rn | Indirect, Rn },
+	                              { Rn | Indirect, Rn | Indirect, Rn } }, OO_PField },
+  { "q_negf_stf",   2,2,0xE2000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
+	OO_4op1 },
+  { "q_negi_sti",   2,2,0xE4000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
+	OO_4op1 },
+  { "q_not_sti",    2,2,0xE6000000, { { Indirect, Rn, 0 }, { Rn, Indirect, 0 } },
+	OO_4op1 },
+  { "q_or3_sti",    3,2,0xE8000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
+	OO_5op1 },
+  { "q_stf_stf",    2,2,0xC0000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } },
+	OO_4op3 },
+  { "q_sti_sti",    2,2,0xC2000000, { { Rn, Indirect, 0 }, { Rn, Indirect, 0 } },
+	OO_4op3 },
+  { "q_subf3_stf",  3,2,0xEA000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
+	OO_5op2 },
+  { "q_subi3_sti",  3,2,0xEC000000, { { Rn, Indirect, Rn }, { Rn, Indirect, 0 } },
+	OO_5op2 },
+  { "q_xor3_sti",   3,2,0xEE000000, { { Indirect, Rn, Rn }, { Rn, Indirect, 0 } },
+	OO_5op1 },
+  { "",             0,0,0x00000000, { { 0, 0, 0 }, { 0, 0, 0 } }, 0 }
+};
+
+static const partemplate *const tic30_paroptab_end =
+  tic30_paroptab + sizeof(tic30_paroptab)/sizeof(tic30_paroptab[0]);
+
+#endif
diff --git a/contrib/binutils/include/opcode/v850.h b/contrib/binutils/include/opcode/v850.h
new file mode 100644
index 0000000..0c10ade
--- /dev/null
+++ b/contrib/binutils/include/opcode/v850.h
@@ -0,0 +1,154 @@
+/* v850.h -- Header file for NEC V850 opcode table
+   Copyright 1996 Free Software Foundation, Inc.
+   Written by J.T. Conklin, Cygnus Support
+
+This file is part of GDB, GAS, and the GNU binutils.
+
+GDB, GAS, and the GNU binutils are free software; you can redistribute
+them and/or modify them under the terms of the GNU General Public
+License as published by the Free Software Foundation; either version
+1, or (at your option) any later version.
+
+GDB, GAS, and the GNU binutils are distributed in the hope that they
+will be useful, but WITHOUT ANY WARRANTY; without even the implied
+warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
+the GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this file; see the file COPYING.  If not, write to the Free
+Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef V850_H
+#define V850_H
+
+/* The opcode table is an array of struct v850_opcode.  */
+
+struct v850_opcode
+{
+  /* The opcode name.  */
+  const char *name;
+
+  /* The opcode itself.  Those bits which will be filled in with
+     operands are zeroes.  */
+  unsigned long opcode;
+
+  /* The opcode mask.  This is used by the disassembler.  This is a
+     mask containing ones indicating those bits which must match the
+     opcode field, and zeroes indicating those bits which need not
+     match (and are presumably filled in by operands).  */
+  unsigned long mask;
+
+  /* An array of operand codes.  Each code is an index into the
+     operand table.  They appear in the order which the operands must
+     appear in assembly code, and are terminated by a zero.  */
+  unsigned char operands[8];
+
+  /* Which (if any) operand is a memory operand.  */
+  unsigned int memop;
+
+  /* Target processor(s).  A bit field of processors which support
+     this instruction.  Note a bit field is used as some instructions
+     are available on multiple, different processor types, whereas
+     other instructions are only available on one specific type.  */
+  unsigned int processors;
+};
+
+/* Values for the processors field in the v850_opcode structure.  */
+#define PROCESSOR_V850		(1 << 0)		/* Just the V850.  */
+#define PROCESSOR_ALL		-1			/* Any processor.  */
+
+/* The table itself is sorted by major opcode number, and is otherwise
+   in the order in which the disassembler should consider
+   instructions.  */
+extern const struct v850_opcode v850_opcodes[];
+extern const int v850_num_opcodes;
+
+
+/* The operands table is an array of struct v850_operand.  */
+
+struct v850_operand
+{
+  /* The number of bits in the operand.  */
+  /* If this value is -1 then the operand's bits are in a discontinous distribution in the instruction. */
+  int bits;
+
+  /* (bits >= 0):  How far the operand is left shifted in the instruction.  */
+  /* (bits == -1): Bit mask of the bits in the operand.  */
+  int shift;
+
+  /* Insertion function.  This is used by the assembler.  To insert an
+     operand value into an instruction, check this field.
+
+     If it is NULL, execute
+         i |= (op & ((1 << o->bits) - 1)) << o->shift;
+     (i is the instruction which we are filling in, o is a pointer to
+     this structure, and op is the opcode value; this assumes twos
+     complement arithmetic).
+
+     If this field is not NULL, then simply call it with the
+     instruction and the operand value.  It will return the new value
+     of the instruction.  If the ERRMSG argument is not NULL, then if
+     the operand value is illegal, *ERRMSG will be set to a warning
+     string (the operand will be inserted in any case).  If the
+     operand value is legal, *ERRMSG will be unchanged (most operands
+     can accept any value).  */
+  unsigned long (* insert) PARAMS ((unsigned long instruction, long op,
+				   const char ** errmsg));
+
+  /* Extraction function.  This is used by the disassembler.  To
+     extract this operand type from an instruction, check this field.
+
+     If it is NULL, compute
+         op = o->bits == -1 ? ((i) & o->shift) : ((i) >> o->shift) & ((1 << o->bits) - 1);
+	 if (o->flags & V850_OPERAND_SIGNED)
+	     op = (op << (32 - o->bits)) >> (32 - o->bits);
+     (i is the instruction, o is a pointer to this structure, and op
+     is the result; this assumes twos complement arithmetic).
+
+     If this field is not NULL, then simply call it with the
+     instruction value.  It will return the value of the operand.  If
+     the INVALID argument is not NULL, *INVALID will be set to
+     non-zero if this operand type can not actually be extracted from
+     this operand (i.e., the instruction does not match).  If the
+     operand is valid, *INVALID will not be changed.  */
+  unsigned long (* extract) PARAMS ((unsigned long instruction, int * invalid));
+
+  /* One bit syntax flags.  */
+  int flags;
+};
+
+/* Elements in the table are retrieved by indexing with values from
+   the operands field of the v850_opcodes table.  */
+
+extern const struct v850_operand v850_operands[];
+
+/* Values defined for the flags field of a struct v850_operand.  */
+
+/* This operand names a general purpose register */
+#define V850_OPERAND_REG	0x01
+
+/* This operand names a system register */
+#define V850_OPERAND_SRG	0x02
+
+/* This operand names a condition code used in the setf instruction */
+#define V850_OPERAND_CC		0x04
+
+/* This operand takes signed values */
+#define V850_OPERAND_SIGNED	0x08
+
+/* This operand is the ep register.  */
+#define V850_OPERAND_EP		0x10
+
+/* This operand is a PC displacement */
+#define V850_OPERAND_DISP	0x20
+
+/* This is a relaxable operand.   Only used for D9->D22 branch relaxing
+   right now.  We may need others in the future (or maybe handle them like
+   promoted operands on the mn10300?)  */
+#define V850_OPERAND_RELAX	0x40
+
+/* The register specified must not be r0 */
+#define V850_NOT_R0	        0x80
+
+
+#endif /* V850_H */
diff --git a/contrib/binutils/include/regs/ChangeLog b/contrib/binutils/include/regs/ChangeLog
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/contrib/binutils/include/regs/ChangeLog
diff --git a/contrib/binutils/include/remote-sim.h b/contrib/binutils/include/remote-sim.h
index 77685d5..a4480b4 100644
--- a/contrib/binutils/include/remote-sim.h
+++ b/contrib/binutils/include/remote-sim.h
@@ -20,6 +20,10 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
 #if !defined (REMOTE_SIM_H)
 #define REMOTE_SIM_H 1
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /* This file is used when building stand-alone simulators, so isolate this
    file from gdb.  */
 
@@ -32,113 +36,286 @@ typedef unsigned int SIM_ADDR;
 typedef CORE_ADDR_TYPE SIM_ADDR;
 #endif
 
+
 /* Semi-opaque type used as result of sim_open and passed back to all
    other routines.  "desc" is short for "descriptor".
    It is up to each simulator to define `sim_state'.  */
 
 typedef struct sim_state *SIM_DESC;
 
+
 /* Values for `kind' arg to sim_open.  */
+
 typedef enum {
   SIM_OPEN_STANDALONE, /* simulator used standalone (run.c) */
   SIM_OPEN_DEBUG       /* simulator used by debugger (gdb) */
 } SIM_OPEN_KIND;
 
+
 /* Return codes from various functions.  */
+
 typedef enum {
   SIM_RC_FAIL = 0,
-  SIM_RC_OK = 1
+  SIM_RC_OK = 1,
+  SIM_RC_UNKNOWN_BREAKPOINT = 2,
+  SIM_RC_INSUFFICIENT_RESOURCES = 3,
+  SIM_RC_DUPLICATE_BREAKPOINT = 4
 } SIM_RC;
 
+
+/* The bfd struct, as an opaque type.  */
+
+struct _bfd;
+
+
 /* Main simulator entry points.  */
 
-/* Initialize the simulator.  This function is called when the simulator
-   is selected from the gdb command line.
-   KIND specifies how the simulator will be used.  Currently there are only
-   two kinds: standalone and debug.
-   ARGV is passed from the command line and can be used to select whatever
-   run time options the simulator provides.
-   ARGV is the standard NULL terminated array of pointers, with argv[0]
-   being the program name.
-   The result is a descriptor that must be passed back to the other sim_foo
-   functions.  */
 
-SIM_DESC sim_open PARAMS ((SIM_OPEN_KIND kind, char **argv));
+/* Create a fully initialized simulator instance.
+
+   (This function is called when the simulator is selected from the
+   gdb command line.)
+
+   KIND specifies how the simulator shall be used.  Currently there
+   are only two kinds: stand-alone and debug.
+
+   CALLBACK specifies a standard host callback (defined in callback.h).
+
+   ABFD, when non NULL, designates a target program.  The program is
+   not loaded.
+
+   ARGV is a standard ARGV pointer such as that passed from the
+   command line.  The syntax of the argument list is is assumed to be
+   ``SIM-PROG { SIM-OPTION } [ TARGET-PROGRAM { TARGET-OPTION } ]''.
+   The trailing TARGET-PROGRAM and args are only valid for a
+   stand-alone simulator.
+
+   On success, the result is a non NULL descriptor that shall be
+   passed to the other sim_foo functions.  While the simulator
+   configuration can be parameterized by (in decreasing precedence)
+   ARGV's SIM-OPTION, ARGV's TARGET-PROGRAM and the ABFD argument, the
+   successful creation of the simulator shall not dependent on the
+   presence of any of these arguments/options.
+
+   Hardware simulator: The created simulator shall be sufficiently
+   initialized to handle, with out restrictions any client requests
+   (including memory reads/writes, register fetch/stores and a
+   resume).
+
+   Process simulator: that process is not created until a call to
+   sim_create_inferior.  FIXME: What should the state of the simulator
+   be? */
+
+SIM_DESC sim_open PARAMS ((SIM_OPEN_KIND kind, struct host_callback_struct *callback, struct _bfd *abfd, char **argv));
 
-/* Terminate usage of the simulator.  This may involve freeing target memory
-   and closing any open files and mmap'd areas.  You cannot assume sim_kill
-   has already been called.
-   QUITTING is non-zero if we cannot hang on errors.  */
+
+/* Destory a simulator instance.
+
+   QUITTING is non-zero if we cannot hang on errors.
+
+   This may involve freeing target memory and closing any open files
+   and mmap'd areas.  You cannot assume sim_kill has already been
+   called. */
 
 void sim_close PARAMS ((SIM_DESC sd, int quitting));
 
-/* Load program PROG into the simulator.
-   Return non-zero if you wish the caller to handle it
-   (it is done this way because most simulators can use gr_load_image,
-   but defining it as a callback seems awkward).  */
 
-int sim_load PARAMS ((SIM_DESC sd, char *prog, int from_tty));
+/* Load program PROG into the simulators memory.
+
+   If ABFD is non-NULL, the bfd for the file has already been opened.
+   The result is a return code indicating success.
+
+   Hardware simulator: Normally, each program section is written into
+   memory according to that sections LMA using physical (direct)
+   addressing.  The exception being systems, such as PPC/CHRP, which
+   support more complicated program loaders.  A call to this function
+   should not effect the state of the processor registers.  Multiple
+   calls to this function are permitted and have an accumulative
+   effect.
+
+   Process simulator: Calls to this function may be ignored.
+
+   FIXME: Most hardware simulators load the image at the VMA using
+   virtual addressing.
+
+   FIXME: For some hardware targets, before a loaded program can be
+   executed, it requires the manipulation of VM registers and tables.
+   Such manipulation should probably (?) occure in
+   sim_create_inferior. */
+
+SIM_RC sim_load PARAMS ((SIM_DESC sd, char *prog, struct _bfd *abfd, int from_tty));
+
 
 /* Prepare to run the simulated program.
-   START_ADDRESS is, yes, you guessed it, the start address of the program.
-   ARGV and ENV are NULL terminated lists of pointers.
-   Gdb will set the start address via sim_store_register as well, but
-   standalone versions of existing simulators are not set up to cleanly call
-   sim_store_register, so the START_ADDRESS argument is there as a
-   workaround.  */
 
-void sim_create_inferior PARAMS ((SIM_DESC sd, SIM_ADDR start_address,
-				  char **argv, char **env));
+   ABFD, if not NULL, provides initial processor state information.
+   ARGV and ENV, if non NULL, are NULL terminated lists of pointers.
 
-/* Kill the running program.
-   This may involve closing any open files and deleting any mmap'd areas.  */
+   Hardware simulator: This function shall initialize the processor
+   registers to a known value.  The program counter and possibly stack
+   pointer shall be set using information obtained from ABFD (or
+   hardware reset defaults).  ARGV and ENV, dependant on the target
+   ABI, may be written to memory.
 
-void sim_kill PARAMS ((SIM_DESC sd));
+   Process simulator: After a call to this function, a new process
+   instance shall exist. The TEXT, DATA, BSS and stack regions shall
+   all be initialized, ARGV and ENV shall be written to process
+   address space (according to the applicable ABI) and the program
+   counter and stack pointer set accordingly. */
+
+SIM_RC sim_create_inferior PARAMS ((SIM_DESC sd, struct _bfd *abfd, char **argv, char **env));
 
-/* Read LENGTH bytes of the simulated program's memory and store in BUF.
-   Result is number of bytes read, or zero if error.  */
+
+/* Fetch LENGTH bytes of the simulated program's memory.  Start fetch
+   at virtual address MEM and store in BUF.  Result is number of bytes
+   read, or zero if error.  */
 
 int sim_read PARAMS ((SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length));
 
-/* Store LENGTH bytes from BUF in the simulated program's memory.
-   Result is number of bytes write, or zero if error.  */
+
+/* Store LENGTH bytes from BUF into the simulated program's
+   memory. Store bytes starting at virtual address MEM. Result is
+   number of bytes write, or zero if error.  */
 
 int sim_write PARAMS ((SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length));
 
-/* Fetch register REGNO and store the raw value in BUF.  */
 
-void sim_fetch_register PARAMS ((SIM_DESC sd, int regno, unsigned char *buf));
+/* Fetch register REGNO storing its raw (target endian) value in the
+   LENGTH byte buffer BUF.  Return the actual size of the register or
+   zero if REGNO is not applicable.
 
-/* Store register REGNO from BUF (in raw format).  */
+   Legacy implementations ignore LENGTH and always return -1.
 
-void sim_store_register PARAMS ((SIM_DESC sd, int regno, unsigned char *buf));
+   If LENGTH does not match the size of REGNO no data is transfered
+   (the actual register size is still returned). */
 
-/* Print some interesting information about the simulator.
-   VERBOSE is non-zero for the wordy version.  */
+int sim_fetch_register PARAMS ((SIM_DESC sd, int regno, unsigned char *buf, int length));
 
-void sim_info PARAMS ((SIM_DESC sd, int verbose));
 
-/* Fetch why the program stopped.
-   SIGRC will contain either the argument to exit() or the signal number.  */
+/* Store register REGNO from the raw (target endian) value in BUF.
+   Return the actual size of the register or zero if REGNO is not
+   applicable.
 
-enum sim_stop { sim_exited, sim_stopped, sim_signalled };
+   Legacy implementations ignore LENGTH and always return -1.
+
+   If LENGTH does not match the size of REGNO no data is transfered
+   (the actual register size is still returned). */
+
+int sim_store_register PARAMS ((SIM_DESC sd, int regno, unsigned char *buf, int length));
 
-void sim_stop_reason PARAMS ((SIM_DESC sd, enum sim_stop *reason, int *sigrc));
 
-/* Run (or resume) the program.  */
+/* Print whatever statistics the simulator has collected.
+
+   VERBOSE is currently unused and must always be zero.  */
+
+void sim_info PARAMS ((SIM_DESC sd, int verbose));
+
+
+/* Run (or resume) the simulated program.  */
 
 void sim_resume PARAMS ((SIM_DESC sd, int step, int siggnal));
 
+
+/* Asynchronous request to stop the simulation.
+   A nonzero return indicates that the simulator is able to handle
+   the request */
+
+int sim_stop PARAMS ((SIM_DESC sd));
+
+
+/* Fetch the REASON why the program stopped.
+
+   SIM_EXITED: The program has terminated. SIGRC indicates the target
+   dependant exit status.
+
+   SIM_STOPPED: The program has stopped.  SIGRC uses the host's signal
+   numbering as a way of identifying the reaon: program interrupted by
+   user via a sim_stop request (SIGINT); a breakpoint instruction
+   (SIGTRAP); a completed single step (SIGTRAP); an internal error
+   condition (SIGABRT); an illegal instruction (SIGILL); Access to an
+   undefined memory region (SIGSEGV); Mis-aligned memory access
+   (SIGBUS).
+
+   SIM_SIGNALLED: The program has stopped. The simulator has
+   encountered target code that requires the (HOST) signal SIGRC to be
+   delivered to the simulated program.  Ex: `kill (getpid (),
+   TARGET_SIGxxx)'.  Where TARGET_SIGxxx has been translated into a
+   host signal.  FIXME: This is not always possible..
+
+   SIM_RUNNING, SIM_POLLING: The return of one of these values
+   indicates a problem internal to the simulator. */
+
+enum sim_stop { sim_running, sim_polling, sim_exited, sim_stopped, sim_signalled };
+
+void sim_stop_reason PARAMS ((SIM_DESC sd, enum sim_stop *reason, int *sigrc));
+
+
 /* Passthru for other commands that the simulator might support.
-   If SD is NULL, the command is to be interpreted as refering to
-   the global state, however the simulator defines that.  */
+   Simulators should be prepared to deal with any combination of NULL
+   or empty CMD. */
 
 void sim_do_command PARAMS ((SIM_DESC sd, char *cmd));
 
-/* Provide simulator with a standard host_callback_struct.
-   If SD is NULL, the command is to be interpreted as refering to
-   the global state, however the simulator defines that.  */
+/* Call these functions to set and clear breakpoints at ADDR. */
+
+SIM_RC sim_set_breakpoint PARAMS ((SIM_DESC sd, SIM_ADDR addr));
+SIM_RC sim_clear_breakpoint PARAMS ((SIM_DESC sd, SIM_ADDR addr));
+SIM_RC sim_clear_all_breakpoints PARAMS ((SIM_DESC sd));
 
-void sim_set_callbacks PARAMS ((SIM_DESC sd, struct host_callback_struct *));
+/* These functions are used to enable and disable breakpoints. */
+
+SIM_RC sim_enable_breakpoint PARAMS ((SIM_DESC sd, SIM_ADDR addr));
+SIM_RC sim_disable_breakpoint PARAMS ((SIM_DESC sd, SIM_ADDR addr));
+SIM_RC sim_enable_all_breakpoints PARAMS ((SIM_DESC sd));
+SIM_RC sim_disable_all_breakpoints PARAMS ((SIM_DESC sd));
+
+
+/* Provide simulator with a default (global) host_callback_struct.
+   THIS PROCEDURE IS DEPRECIATED.
+   GDB and NRUN do not use this interface.
+   This procedure does not take a SIM_DESC argument as it is
+   used before sim_open. */
+
+void sim_set_callbacks PARAMS ((struct host_callback_struct *));
+
+
+/* Set the size of the simulator memory array.
+   THIS PROCEDURE IS DEPRECIATED.
+   GDB and NRUN do not use this interface.
+   This procedure does not take a SIM_DESC argument as it is
+   used before sim_open. */
+
+void sim_size PARAMS ((int i));
+
+
+/* Run a simulation with tracing enabled.
+   THIS PROCEDURE IS DEPRECIATED.
+   GDB and NRUN do not use this interface.
+   This procedure does not take a SIM_DESC argument as it is
+   used before sim_open. */
+
+int sim_trace PARAMS ((SIM_DESC sd));
+
+
+/* Configure the size of the profile buffer.
+   THIS PROCEDURE IS DEPRECIATED.
+   GDB and NRUN do not use this interface.
+   This procedure does not take a SIM_DESC argument as it is
+   used before sim_open. */
+
+void sim_set_profile_size PARAMS ((int n));
+
+
+/* Kill the running program.
+   THIS PROCEDURE IS DEPRECIATED.
+   GDB and NRUN do not use this interface.
+   This procedure will be replaced as part of the introduction of
+   multi-cpu simulators. */
+
+void sim_kill PARAMS ((SIM_DESC sd));
+
+#ifdef __cplusplus
+}
+#endif
 
 #endif /* !defined (REMOTE_SIM_H) */
diff --git a/contrib/binutils/include/symcat.h b/contrib/binutils/include/symcat.h
new file mode 100644
index 0000000..01efada
--- /dev/null
+++ b/contrib/binutils/include/symcat.h
@@ -0,0 +1,40 @@
+/* Symbol concatenation utilities.
+
+   Copyright (C) 1998, Free Software Foundation, Inc.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+ 
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef SYM_CAT_H
+#define SYM_CAT_H
+
+#if defined (__STDC__) || defined (ALMOST_STDC)
+#define CONCAT2(a,b)	 a##b
+#define CONCAT3(a,b,c)	 a##b##c
+#define CONCAT4(a,b,c,d) a##b##c##d
+#define STRINGX(s) #s
+#else
+#define CONCAT2(a,b)	 a/**/b
+#define CONCAT3(a,b,c)	 a/**/b/**/c
+#define CONCAT4(a,b,c,d) a/**/b/**/c/**/d
+#define STRINGX(s) "?"
+#endif
+
+#define XCONCAT2(a,b)     CONCAT2(a,b)
+#define XCONCAT3(a,b,c)   CONCAT3(a,b,c)
+#define XCONCAT4(a,b,c,d) CONCAT4(a,b,c,d)
+
+#define XSTRING(s) STRINGX(s) 
+
+#endif SYM_CAT_H