diff options
| author | obrien <obrien@FreeBSD.org> | 2000-05-12 23:15:20 +0000 |
|---|---|---|
| committer | obrien <obrien@FreeBSD.org> | 2000-05-12 23:15:20 +0000 |
| commit | 2a9ea95d682586d2b0c31da28d82a73d786c7c0a (patch) | |
| tree | 9d4ce42d357c391a11d77254b770908c02ecf672 /contrib/binutils/include | |
| parent | bffe850874e72664f78cf171ab1c4339b9b63cab (diff) | |
| download | FreeBSD-src-2a9ea95d682586d2b0c31da28d82a73d786c7c0a.zip FreeBSD-src-2a9ea95d682586d2b0c31da28d82a73d786c7c0a.tar.gz | |
Import of Binutils 2.10 snapshot.
Diffstat (limited to 'contrib/binutils/include')
51 files changed, 7408 insertions, 1737 deletions
diff --git a/contrib/binutils/include/ChangeLog b/contrib/binutils/include/ChangeLog index 985d9f1..0dda323 100644 --- a/contrib/binutils/include/ChangeLog +++ b/contrib/binutils/include/ChangeLog @@ -1,3 +1,360 @@ +2000-04-04 Alan Modra <alan@linuxcare.com.au> + + * bin-bugs.h (REPORT_BUGS_TO): Remove translated part. + +2000-04-03 Alan Modra <alan@linuxcare.com.au> + + * bin-bugs.h: New file. + +2000-03-27 Denis Chertykov <denisc@overta.ru> + + * dis-asm.h (print_insn_avr): Declare. + +2000-03-14 Bernd Schmidt <bernds@cygnus.co.uk> + + * hashtab.h (htab_trav): Modify type so that first arg is of type + void **. + (htab_find_with_hash, htab_find_slot_with_hash): Declare new + functions. + +2000-03-09 Alex Samuel <samuel@codesourcery.com> + + * partition.h: New file. + +2000-03-09 Zack Weinberg <zack@wolery.cumb.org> + + * hashtab.h (struct htab): Add del_f. + (htab_del): New type. + (htab_create): Add fourth argument. + +2000-03-08 Zack Weinberg <zack@wolery.cumb.org> + + * hashtab.h (hash_table_t): Rename to htab_t. + (struct hash_table): Rename to struct htab. Shorten element + names. Reorder elements by size. + (htab_hash, htab_eq, htab_trav): New typedefs for the callback + function pointers. + (hash_table_entry_t): Discard; just use void * for element + type. + +2000-03-01 H.J. Lu <hjl@gnu.org> + + * bfdlink.h (bfd_link_callbacks): Add a boolean arg to + the undefined_symbol callback. + +2000-02-23 Linas Vepstas <linas@linas.org> + + * dis-asm.h (print_insn_i370): Declare. + +2000-02-22 Chandra Chavva <cchavva@cygnus.com> + + * opcode/d30v.h (FLAG_NOT_WITH_ADDSUBppp): Redefined as operation + cannot be combined in parallel with ADD/SUBppp. + +Tue Feb 22 15:19:54 2000 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_trace): Document return values. + (sim_set_trace): Declare. Deprecate. + +2000-02-21 Alan Modra <alan@spri.levels.unisa.edu.au> + + * dis-asm.h (struct disassemble_info): Change `length' param of + read_memory_func to unsigned. Change type of `buffer_length' and + `octets_per_byte' to unsigned. + (buffer_read_memory): Change `length' param to unsigned. + +2000-02-16 Nick Clifton <nickc@cygnus.com> + + * dis-asm.h: Add prototypes for ARM register name functions. + +Wed Feb 9 18:45:49 2000 Andrew Cagney <cagney@b1.cygnus.com> + + * wait.h: Delete. No longer used by GDB. + +Tue Feb 8 17:01:13 2000 Andrew Cagney <cagney@b1.cygnus.com> + + * remote-sim.h (sim_resume): Clarify use of SIGGNAL. + (sim_stop_reason): Clarify meaning of sim_signalled. + +2000-02-03 Timothy Wall <twall@redhat.com> + + * dis-asm.h (struct disassemble_info): Added octets_per_byte + field and initialize it to one (1). + +2000-01-27 Nick Clifton <nickc@redhat.com> + + * dis-asm.h: Add prototype for disassembler_usage(). + Add prototype for arm_disassembler_options(). + Remove prototype for arm_toggle_regnames(). + Add prototype for parse_arm_disassembler_option(). + +Sat Jan 1 19:06:52 2000 Hans-Peter Nilsson <hp@bitrange.com> + + * symcat.h (STRINGX) [!__STDC__ || ALMOST_STDC]: Change "?" to "s" + to stringify argument s. + +Wed Dec 15 11:22:56 1999 Jeffrey A Law (law@cygnus.com) + + * hp-symtab.h (HP_LANGUAGE_FORTRAN): New enumeration constant. + (HP_LANGUAGE_F77): Define using HP_LANGUAGE_FORTRAN. + +1999-12-15 Doug Evans <dje@transmeta.com> + + * dis-asm.h: Enclose in extern "C" ifdef __cplusplus. + +1999-12-05 Mark Mitchell <mark@codesourcery.com> + + * splay-tree.h (struct splay_tree_node): Rename to ... + (struct splay_tree_node_s): ... this. + (struct splay_tree): Rename to ... + (struct splay_tree_s): ... this. + +1999-11-30 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * ansidecl.h (ATTRIBUTE_MALLOC): New macro. + + * libiberty.h (buildargv, dupargv, concat, choose_temp_base, + make_temp_file, xmalloc, xcalloc, xstrdup, xmemdup): Add + ATTRIBUTE_MALLOC. + (xatexit): Remove __GNUC__ check, add ATTRIBUTE_NORETURN. + +1999-11-28 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h: Include stdarg.h when ANSI_PROTOTYPES is defined. + (asprintf, vasprintf): Provide declarations. + +Wed Nov 10 12:43:21 1999 Philippe De Muyter <phdm@macqel.be> + Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * ansidecl.h: Define and test `GCC_VERSION', not `HAVE_GCC_VERSION'. + +1999-11-04 Jimmy Guo <guo@cup.hp.com> + + * hp-symtab.h (dntt_type_fparam): Add doc_ranges, misc_kind + fields, change location type to CORE_ADDR from int. + (dntt_type_const): Name the 5th field location_type. + +Sun Oct 24 19:11:32 1999 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-d10v.h (SIM_D10V_TS2_DMAP_REGNUM): Define. + +1999-10-23 08:51 -0700 Zack Weinberg <zack@bitmover.com> + + * hashtab.h: Give hash_table_t a struct tag. Add prototypes + for clear_hash_table_slot and traverse_hash_table. Correct + prototype of all_hash_table_collisions. + +Sat Oct 23 19:00:13 1999 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-d10v.h: New file. + +Fri Oct 15 01:47:51 1999 Vladimir Makarov <vmakarov@loony.cygnus.com> + + * hashtab.h: New file. + +1999-10-10 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * ansidecl.h (HAVE_GCC_VERSION): New macro. Use it instead of + explicitly testing __GNUC__ and __GNUC_MINOR__. + + (ATTRIBUTE_PRINTF): Use `__format__', not `format'. + +1999-09-25 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h (make_temp_file): Add a prototype. + +Tue Sep 14 00:35:02 1999 Marc Espie <espie@cvs.openbsd.org> + + * libiberty.h (basename): OpenBSD has a correct prototype. + (xrealloc): Remove outdated comment. + +1999-09-07 Jeff Garzik <jgarzik@pobox.com> + + * libiberty.h (xmemdup): Add prototype for new function. + +1999-09-04 Steve Chamberlain <sac@pobox.com> + + * dis-asm.h (print_insn_pj): Declare. + +1999-09-01 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * obstack.h (obstack_grow, obstack_grow0): Move (char*) casts + in calls to `_obstack_memcpy' from here ... + + (_obstack_memcpy): ... to here, except in the __STDC__ case which + doesn't need it. + +1999-08-30 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h (getpwd): Prototype. + +1999-08-01 Mark Mitchell <mark@codesourcery.com> + + * splay-tree.h (splay_tree_insert): Return the new node. + +1999-07-11 Ian Lance Taylor <ian@zembu.com> + + * ansidecl.h: Copy attribute support macros from egcs. + +1999-06-22 Mark Mitchell <mark@codesourcery.com> + + * bfdlink.h (struct bfd_link_hash_entry): Add init_function and + fini_function. + +1999-06-20 Mark Mitchell <mark@codesourcery.com> + + * mips.h (Elf32_Internal_Msym): New structure. + (Elf32_External_Msym): Likewise. + (ELF32_MS_REL_INDEX): New macro. + (ELF32_MS_FLAGS): Likewise. + (ELF32_MS_INFO): Likewise. + +1999-06-14 Nick Clifton <nickc@cygnus.com> + + * dis-asm.h (arm_toggle_regnames): New prototype. + (struct diassemble_info): New field: disassembler_options. + +1999-04-11 Richard Henderson <rth@cygnus.com> + + * bfdlink.h (bfd_elf_version_expr): Rename `match' to `pattern'. + Add `match' callback function. + +1999-04-10 Richard Henderson <rth@cygnus.com> + + * bfdlink.h (bfd_link_info): Add no_undefined. + +1999-04-08 Nick Clifton <nickc@cygnus.com> + + * dis-asm.h: Add prototype for print_insn_mcore. + +1999-04-02 Mark Mitchell <mark@codesourcery.com> + + * splay-tree.h (splay_tree_compare_pointers): Declare. + +1999-03-30 Mark Mitchell <mark@codesourcery.com> + + * splay-tree.h (splay_tree_compare_ints): Declare. + +Wed Mar 24 12:46:29 1999 Andrew Cagney <cagney@amy.cygnus.com> + + * libiberty.h (basename): Cygwin{,32} should have the prototype. + +1999-02-22 Jim Lemke <jlemke@cygnus.com> + + * bfdlink.h (bfd_link_info): add field "mpc860c0". + +Mon Feb 1 21:05:46 1999 Catherine Moore <clm@cygnus.com> + + * dis-asm.h (print_insn_i386_att): Declare. + (print_insn_i386_intel): Declare. + +998-12-30 Michael Meissner <meissner@cygnus.com> + + * dis-asm.h (INIT_DISASSEMBLE_INFO_NO_ARCH): Cast STREAM and + FPRINTF_FUNC to avoid compiler warnings. + +Wed Dec 30 16:07:14 1998 David Taylor <taylor@texas.cygnus.com> + + * dis-asm.h: change void * to PTR (two places). + +Mon Dec 14 09:53:31 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * demangle.h: Don't check IN_GCC anymore. + * splay-tree.h: Likewise. + +Tue Dec 8 00:30:31 1998 Elena Zannoni <ezannoni@kwikemart.cygnus.com> + + The following changes were made by Elena Zannoni + <ezannoni@kwikemart.cygnus.com> and Edith Epstein + <eepstein@sophia.cygnus.com> as part of a project to merge in + changes made by HP; HP did not create ChangeLog entries. + + * dis-asm.h (struct disassemble_info): change the type of stream + from FILE* to void*, for use with gdb's new type GDB_FILE. + (fprintf_ftype): change FILE* parameter type to void*. + + * demangle.h: (DMGL_EDG): new macro for Kuck and Associates + (DMGL_STYLE_MASK): modify to include Kuck and Assoc style + (demangling_styles): add new edg_demangling style + (EDG_DEMANGLING_STYLE_STRING): new macro + (EDG_DEMANGLING): new macro + + * demangle.h (DMGL_HP): new macro, for HP/aCC compiler. + (DMGL_STYLE_MASK): modify to include new HP's style. + (demangling_styles): add new hp_demangling value. + (HP_DEMANGLING_STYLE_STRING): new macro. + (ARM_DEMANGLING): coerce to int. + (HP_DEMANGLING): new macro. + + * hp-symtab.h: rewritten, from HP. + (quick_procedure): change type of language field to unsigned int + (quick_module): change type of language field to unsigned int + (struct dntt_type_svar): add field thread_specific. + (hp_language): add languages modcal and dmpascal. + +Mon Nov 30 15:25:58 1998 J"orn Rennecke <amylaar@cygnus.co.uk> + + * elf/sh.h (elf_sh_reloc_type): Add R_SH_FIRST_INVALID_RELOC, + R_SH_LAST_INVALID_RELOC, R_SH_SWITCH8 and R_SH_max. + +Fri Nov 20 13:14:00 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * libiberty.h (basename): Add prototype for FreeBSD. + +Fri Nov 13 19:19:11 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * libiberty.h: Prototype xcalloc. + +Sun Nov 8 17:42:25 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * ansidecl.h: Wrap problematic macros with !IN_GCC. + + * demangle.h: Never define PARAMS(). + * splay-tree.h: Likewise. + +Sat Nov 7 18:30:20 1998 Peter Schauer <peter.schauer@regent.e-technik.tu-muenchen.de> + + * dis-asm.h (print_insn_vax): Declare. + +Sat Nov 7 16:04:03 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * demangle.h: Don't include gansidecl.h. + * splay-tree.h: Likewise. + +1998-10-26 16:03 Ulrich Drepper <drepper@cygnus.com> + + * bfdlink.h (struct bfd_link_info): Add new field optimize. + +Thu Oct 22 19:58:00 1998 Kaveh R. Ghazi <ghazi@caip.rutgers.edu> + + * splay-tree.h: Wrap function pointer parameter declarations in + PARAMS() macro. + +1998-10-21 Mark Mitchell <mark@markmitchell.com> + + * splay-tree.h: New file. + +Fri Oct 9 00:02:03 1998 Jeffrey A Law (law@cygnus.com) + + * Merge devo and egcs include directories. + +Sat Sep 5 12:16:33 1998 Jeffrey A Law (law@cygnus.com) + + * getopt.h, obstack.h: Updated from gcc. + +1998-08-03 Jason Molenda (jsm@bugshack.cygnus.com) + + * libiberty.h (xexit): Change decl to use modern GCC attribute + to indicate exit does not return. + +Mon Jun 1 13:48:32 1998 Jason Molenda (crash@bugshack.cygnus.com) + + * obstack.h: Update to latest FSF version. + +Tue May 26 20:57:43 1998 Stan Cox <scox@equinox.cygnus.com> + + * elf/sparc.h (EF_SPARC_LEDATA, R_SPARC_32LE): Added. + Tue Feb 24 13:05:02 1998 Doug Evans <devans@canuck.cygnus.com> * dis-asm.h (disassemble_info): Member `symbol' renamed to `symbols' @@ -24,7 +381,7 @@ Mon Feb 2 17:13:31 1998 Steve Haworth <steve@pm.cse.rmit.EDU.AU> Thu Jan 22 16:23:59 1998 Fred Fish <fnf@cygnus.com> - * dis-asm.h: Add flag INSN_HAS_RELOC to tell disassembly + * dis-asm.h: Add flag INSN_HAS_RELOC to tell disassembly function there is a reloc on this line. Mon Dec 8 11:22:23 1997 Nick Clifton <nickc@cygnus.com> @@ -97,7 +454,7 @@ Tue Oct 14 16:07:51 1997 Nick Clifton <nickc@cygnus.com> * dis-asm.h (struct disassemble_info): New field 'symbol_at_address_func'. (INIT_DISASSEMBLE_INFO_NO_ARCH): Initialise new field with - generic_symbol_at_address. + generic_symbol_at_address. Mon Oct 13 10:17:15 1997 Andrew Cagney <cagney@b1.cygnus.com> @@ -190,12 +547,12 @@ Fri Apr 18 13:04:49 1997 Andrew Cagney <cagney@b1.cygnus.com> * remote-sim.h (enum sim_stop): Add sim_running and sim_polling as states for use internal to simulators. - + * callback.h (struct host_callback_strut): Put a magic number at the end of the struct to allow basic checking. (struct host_callback_struct ): Add poll_quit - so that the console etc can be polled at regular intervals. - + Thu Apr 17 02:17:12 1997 Doug Evans <dje@canuck.cygnus.com> * remote-sim.h (struct _bfd): Declare. @@ -270,6 +627,10 @@ Thu Feb 6 14:20:01 1997 Martin M. Hunt <hunt@pizza.cygnus.com> bytes_per_chunk and display_endian to control the display of raw instructions. +Fri Dec 27 22:17:37 1996 Fred Fish <fnf@cygnus.com> + + * dis-asm.h (print_insn_tic80): Declare. + Sun Dec 8 17:11:12 1996 Doug Evans <dje@canuck.cygnus.com> * callback.h (host_callback): New member `error'. @@ -284,7 +645,7 @@ Mon Nov 18 16:34:00 1996 Dawn Perchik <dawn@critters.cygnus.com> Wed Nov 13 08:22:00 1996 Dawn Perchik <dawn@critters.cygnus.com> - * libiberty.h: Revert last commit due to conflicts with hpux + * libiberty.h: Revert last commit due to conflicts with hpux system headers. Tue Nov 12 16:31:00 1996 Dawn Perchik <dawn@critters.cygnus.com> @@ -453,7 +814,7 @@ Wed Jan 3 13:12:09 1996 Fred Fish <fnf@cygnus.com> * obstack.h: Update copyright to 1996. (_obstack_memory_used): Declare. (obstack_memory_used): Define macro. - + Thu Dec 28 11:42:12 1995 Ian Lance Taylor <ian@cygnus.com> * libiberty.h (xstrdup): Declare. @@ -582,7 +943,7 @@ Wed Dec 14 13:08:43 1994 Stan Shebs <shebs@andros.cygnus.com> Fri Nov 25 00:14:05 1994 Jeff Law (law@snake.cs.utah.edu) * hp-symtab.h: New file describing the debug symbols emitted - by the HP C compilers. + by the HP C compilers. Fri Nov 11 15:48:37 1994 Ian Lance Taylor <ian@sanguine.cygnus.com> @@ -647,8 +1008,8 @@ Thu Apr 28 19:06:50 1994 Ken Raeburn (raeburn@cujo.cygnus.com) Fri Apr 1 00:38:17 1994 Jim Wilson (wilson@mole.gnu.ai.mit.edu) - * obstack.h: Delete use of IN_GCC to control whether - stddef.h or gstddef.h is included. + * obstack.h: Delete use of IN_GCC to control whether + stddef.h or gstddef.h is included. Tue Mar 22 13:06:02 1994 Ian Lance Taylor (ian@tweedledumb.cygnus.com) @@ -706,7 +1067,7 @@ Tue Feb 8 05:19:52 1994 David J. Mackenzie (djm@thepub.cygnus.com) * obstack.h (struct obstack): Add alloc_failed flag. _obstack_begin, _obstack_begin_1): Declare to return int, not void. (obstack_finish): If alloc_failed, return NULL. - (obstack_base, obstack_next_free, objstack_object_size): + (obstack_base, obstack_next_free, objstack_object_size): If alloc_failed, return 0. (obstack_grow, obstack_grow0, obstack_1grow, obstack_ptr_grow, obstack_int_grow, obstack_blank): If alloc_failed, do nothing that @@ -764,7 +1125,7 @@ Mon Aug 2 08:49:30 1993 Stu Grossman (grossman at cygnus.com) Fri Jul 30 18:38:02 1993 John Gilmore (gnu@cygnus.com) - * dis-asm.h: Add new fields insn_info_valid, branch_delay_insns, + * dis-asm.h: Add new fields insn_info_valid, branch_delay_insns, data_size, insn_type, target, target2. These are used to return information from the instruction decoders back to the calling program. Add comments, make more readable. @@ -1032,7 +1393,7 @@ Sat Jul 4 03:22:23 1992 John Gilmore (gnu at cygnus.com) Mon Jun 29 14:18:36 1992 Fred Fish (fnf at sunfish) - * obstack.h: Convert bcopy() use to memcpy(), which is more + * obstack.h: Convert bcopy() use to memcpy(), which is more portable, more standard, and can take advantage of gcc's builtin functions for increased performance. @@ -1086,7 +1447,7 @@ Thu Jan 30 01:18:42 1992 John Gilmore (gnu at cygnus.com) Mon Jan 27 22:01:13 1992 Steve Chamberlain (sac at cygnus.com) - * bfd.h : new target entr, bfd_relax_section + * bfd.h : new target entr, bfd_relax_section Wed Dec 18 17:19:44 1991 Stu Grossman (grossman at cygnus.com) @@ -1153,7 +1514,7 @@ Wed Nov 27 10:38:31 1991 Steve Chamberlain (sac at rtl.cygnus.com) * internalcoff.h: (internal_scnhdr) took out #def dependency, now s_nreloc and s_nlnno are always long. (internal_reloc): allways - has an offset field now. + has an offset field now. Fri Nov 22 08:12:58 1991 John Gilmore (gnu at cygnus.com) @@ -1291,7 +1652,7 @@ Fri Oct 4 01:25:59 1991 John Gilmore (gnu at cygnus.com) Tue Oct 1 04:58:42 1991 John Gilmore (gnu at cygnus.com) - * bfd.h, elf-common.h, elf-external.h, elf-internal.h: + * bfd.h, elf-common.h, elf-external.h, elf-internal.h: Add preliminary ELF support, sufficient for GDB, from Fred Fish. * sysdep.h, sys/h-amix.h: Support Amiga SVR4. diff --git a/contrib/binutils/include/ansidecl.h b/contrib/binutils/include/ansidecl.h index abe87a9..1030867 100644 --- a/contrib/binutils/include/ansidecl.h +++ b/contrib/binutils/include/ansidecl.h @@ -1,5 +1,5 @@ /* ANSI and traditional C compatability macros - Copyright 1991, 1992, 1996 Free Software Foundation, Inc. + Copyright 1991, 1992, 1996, 1999 Free Software Foundation, Inc. This file is part of the GNU C Library. This program is free software; you can redistribute it and/or modify @@ -103,10 +103,12 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define PTRCONST void *CONST #define LONG_DOUBLE long double +#ifndef IN_GCC #define AND , #define NOARGS void #define VOLATILE volatile #define SIGNED signed +#endif /* ! IN_GCC */ #define PARAMS(paramlist) paramlist #define ANSI_PROTOTYPES 1 @@ -115,12 +117,14 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define VA_START(va_list,var) va_start(va_list,var) /* These are obsolete. Do not use. */ +#ifndef IN_GCC #define CONST const #define DOTS , ... #define PROTO(type, name, arglist) type name arglist #define EXFUN(name, proto) name proto #define DEFUN(name, arglist, args) name(args) #define DEFUN_VOID(name) name(void) +#endif /* ! IN_GCC */ #else /* Not ANSI C. */ @@ -128,13 +132,16 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define PTRCONST PTR #define LONG_DOUBLE double +#ifndef IN_GCC #define AND ; #define NOARGS +#define VOLATILE +#define SIGNED +#endif /* !IN_GCC */ + #ifndef const /* some systems define it in header files for non-ansi mode */ #define const #endif -#define VOLATILE -#define SIGNED #define PARAMS(paramlist) () @@ -142,13 +149,76 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define VA_START(va_list,var) va_start(va_list) /* These are obsolete. Do not use. */ +#ifndef IN_GCC #define CONST #define DOTS #define PROTO(type, name, arglist) type name () #define EXFUN(name, proto) name() #define DEFUN(name, arglist, args) name arglist args; #define DEFUN_VOID(name) name() +#endif /* ! IN_GCC */ #endif /* ANSI C. */ +/* Using MACRO(x,y) in cpp #if conditionals does not work with some + older preprocessors. Thus we can't define something like this: + +#define HAVE_GCC_VERSION(MAJOR, MINOR) \ + (__GNUC__ > (MAJOR) || (__GNUC__ == (MAJOR) && __GNUC_MINOR__ >= (MINOR))) + +and then test "#if HAVE_GCC_VERSION(2,7)". + +So instead we use the macro below and test it against specific values. */ + +/* This macro simplifies testing whether we are using gcc, and if it + is of a particular minimum version. (Both major & minor numbers are + significant.) This macro will evaluate to 0 if we are not using + gcc at all. */ +#ifndef GCC_VERSION +#define GCC_VERSION (__GNUC__ * 1000 + __GNUC_MINOR__) +#endif /* GCC_VERSION */ + +/* Define macros for some gcc attributes. This permits us to use the + macros freely, and know that they will come into play for the + version of gcc in which they are supported. */ + +#if (GCC_VERSION < 2007) +# define __attribute__(x) +#endif + +/* Attribute __malloc__ on functions was valid as of gcc 2.96. */ +#ifndef ATTRIBUTE_MALLOC +# if (GCC_VERSION >= 2096) +# define ATTRIBUTE_MALLOC __attribute__ ((__malloc__)) +# else +# define ATTRIBUTE_MALLOC +# endif /* GNUC >= 2.96 */ +#endif /* ATTRIBUTE_MALLOC */ + +/* Attributes on labels were valid as of gcc 2.93. */ +#ifndef ATTRIBUTE_UNUSED_LABEL +# if (GCC_VERSION >= 2093) +# define ATTRIBUTE_UNUSED_LABEL ATTRIBUTE_UNUSED +# else +# define ATTRIBUTE_UNUSED_LABEL +# endif /* GNUC >= 2.93 */ +#endif /* ATTRIBUTE_UNUSED_LABEL */ + +#ifndef ATTRIBUTE_UNUSED +#define ATTRIBUTE_UNUSED __attribute__ ((__unused__)) +#endif /* ATTRIBUTE_UNUSED */ + +#ifndef ATTRIBUTE_NORETURN +#define ATTRIBUTE_NORETURN __attribute__ ((__noreturn__)) +#endif /* ATTRIBUTE_NORETURN */ + +#ifndef ATTRIBUTE_PRINTF +#define ATTRIBUTE_PRINTF(m, n) __attribute__ ((__format__ (__printf__, m, n))) +#define ATTRIBUTE_PRINTF_1 ATTRIBUTE_PRINTF(1, 2) +#define ATTRIBUTE_PRINTF_2 ATTRIBUTE_PRINTF(2, 3) +#define ATTRIBUTE_PRINTF_3 ATTRIBUTE_PRINTF(3, 4) +#define ATTRIBUTE_PRINTF_4 ATTRIBUTE_PRINTF(4, 5) +#define ATTRIBUTE_PRINTF_5 ATTRIBUTE_PRINTF(5, 6) +#endif /* ATTRIBUTE_PRINTF */ + #endif /* ansidecl.h */ diff --git a/contrib/binutils/include/aout/ChangeLog b/contrib/binutils/include/aout/ChangeLog index 307448b..63f17ec 100644 --- a/contrib/binutils/include/aout/ChangeLog +++ b/contrib/binutils/include/aout/ChangeLog @@ -1,3 +1,12 @@ +1999-07-12 Ian Lance Taylor <ian@zembu.com> + + * aout64.h (N_SHARED_LIB): Define as 0 if TEXT_START_ADDR is + defined as 0. + +Sun Jun 28 11:33:48 1998 Peter Schauer <pes@regent.e-technik.tu-muenchen.de> + + * stab.def: Add N_ALIAS from SunPro F77. + Mon Mar 11 12:15:52 1996 Ian Lance Taylor <ian@cygnus.com> * stab.def: Use __define_stab_duplicate rather than __define_stab diff --git a/contrib/binutils/include/aout/aout64.h b/contrib/binutils/include/aout/aout64.h index 76f1140..bf743c4 100644 --- a/contrib/binutils/include/aout/aout64.h +++ b/contrib/binutils/include/aout/aout64.h @@ -121,8 +121,12 @@ struct external_exec /* Sun shared libraries, not linux. This macro is only relevant for ZMAGIC files. */ #ifndef N_SHARED_LIB +#if defined (TEXT_START_ADDR) && TEXT_START_ADDR == 0 +#define N_SHARED_LIB(x) (0) +#else #define N_SHARED_LIB(x) ((x).a_entry < TEXT_START_ADDR) #endif +#endif /* Returning 0 not TEXT_START_ADDR for OMAGIC and NMAGIC is based on the assumption that we are dealing with a .o file, not an diff --git a/contrib/binutils/include/aout/stab.def b/contrib/binutils/include/aout/stab.def index 3c6b456..9c2d2dd 100644 --- a/contrib/binutils/include/aout/stab.def +++ b/contrib/binutils/include/aout/stab.def @@ -1,5 +1,6 @@ /* Table of DBX symbol codes for the GNU system. - Copyright (C) 1988, 91, 92, 93, 94, 95, 1996 Free Software Foundation, Inc. + Copyright (C) 1988, 91, 92, 93, 94, 95, 96, 1998 + Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -135,6 +136,9 @@ __define_stab (N_ENDM, 0x62, "ENDM") __define_stab (N_SO, 0x64, "SO") +/* SunPro F77: Name of alias. */ +__define_stab (N_ALIAS, 0x6c, "ALIAS") + /* Automatic variable in the stack. Value is offset from frame pointer. Also used for type descriptions. */ __define_stab (N_LSYM, 0x80, "LSYM") @@ -239,7 +243,7 @@ __define_stab (N_LENG, 0xfe, "LENG") | 50 EHDECL*| 52 | 54 CATCH | 56 | | 58 | 5A | 5C | 5E | | 60 SSYM | 62 ENDM | 64 SO | 66 | - | 68 | 6A | 6C | 6E | + | 68 | 6A | 6C ALIAS | 6E | | 70 | 72 | 74 | 76 | | 78 | 7A | 7C | 7E | | 80 LSYM | 82 BINCL | 84 SOL | 86 | diff --git a/contrib/binutils/include/bfdlink.h b/contrib/binutils/include/bfdlink.h index f4acf2f..bb827a3 100644 --- a/contrib/binutils/include/bfdlink.h +++ b/contrib/binutils/include/bfdlink.h @@ -1,5 +1,5 @@ /* bfdlink.h -- header file for BFD link routines - Copyright 1993, 94, 95, 96, 1997 Free Software Foundation, Inc. + Copyright 1993, 94, 95, 96, 97, 1999 Free Software Foundation, Inc. Written by Steve Chamberlain and Ian Lance Taylor, Cygnus Support. This file is part of BFD, the Binary File Descriptor library. @@ -193,6 +193,12 @@ struct bfd_link_info on the output file, but may be checked when reading the input files. */ boolean traditional_format; + /* true if we want to produced optimized output files. This might + need much more time and therefore must be explicitly selected. */ + boolean optimize; + /* true if BFD should generate errors for undefined symbols + even if generating a shared object. */ + boolean no_undefined; /* Which symbols to strip. */ enum bfd_link_strip strip; /* Which local symbols to discard. */ @@ -226,6 +232,18 @@ struct bfd_link_info struct bfd_hash_table *wrap_hash; /* If a base output file is wanted, then this points to it */ PTR base_file; + + /* If non-zero, specifies that branches which are problematic for the + MPC860 C0 (or earlier) should be checked for and modified. It gives the + number of bytes that should be checked at the end of each text page. */ + int mpc860c0; + + /* The function to call when the executable or shared object is + loaded. */ + const char *init_function; + /* The function to call when the executable or shared object is + unloaded. */ + const char *fini_function; }; /* This structures holds a set of callback functions. These are @@ -311,10 +329,13 @@ struct bfd_link_callbacks /* A function which is called when a relocation is attempted against an undefined symbol. NAME is the symbol which is undefined. ABFD, SECTION and ADDRESS identify the location from which the - reference is made. In some cases SECTION may be NULL. */ + reference is made. FATAL indicates whether an undefined symbol is + a fatal error or not. In some cases SECTION may be NULL. */ boolean (*undefined_symbol) PARAMS ((struct bfd_link_info *, const char *name, bfd *abfd, - asection *section, bfd_vma address)); + asection *section, + bfd_vma address, + boolean fatal)); /* A function which is called when a reloc overflow occurs. NAME is the name of the symbol or section the reloc is against, RELOC_NAME is the name of the relocation, and ADDEND is any @@ -469,7 +490,9 @@ struct bfd_elf_version_expr /* Next regular expression for this version. */ struct bfd_elf_version_expr *next; /* Regular expression. */ - const char *match; + const char *pattern; + /* Matching function. */ + int (*match) PARAMS((struct bfd_elf_version_expr *, const char *)); }; /* Version dependencies. */ diff --git a/contrib/binutils/include/bin-bugs.h b/contrib/binutils/include/bin-bugs.h new file mode 100644 index 0000000..cb14a66 --- /dev/null +++ b/contrib/binutils/include/bin-bugs.h @@ -0,0 +1,3 @@ +#ifndef REPORT_BUGS_TO +#define REPORT_BUGS_TO "bug-gnu-utils@gnu.org" +#endif diff --git a/contrib/binutils/include/coff/ChangeLog b/contrib/binutils/include/coff/ChangeLog index 21ef0bc..76b52c0 100644 --- a/contrib/binutils/include/coff/ChangeLog +++ b/contrib/binutils/include/coff/ChangeLog @@ -1,3 +1,107 @@ +2000-03-15 Kazu Hirata <kazu@hxi.com> + + * internal.h: Fix a typo in the comment for R_MOVL2. + +2000-02-28 Nick Clifton <nickc@cygnus.com> + + * mipspe.h (MIPS_PE_MAGIC): Define. + * sh.h (SH_PE_MAGIC): Define. + +2000-02-22 Nick Clifton <nickc@cygnus.com> DJ Delorie <dj@cygnus.com> + + * sh.h: Add Windows CE definitions. + * arm.h: Add Windows CE definitions. + * mipspe.h: New file: Windows CE definitions for MIPS. + * pe.h: Add constants for ILF support. + +2000-01-05 Nick Clifton <nickc@cygnus.com> + + * pe.h: Fix formatting of comments. + (IMAGE_FILE_AGGRESSIVE_WS_TRIM): Define. + (IMAGE_FILE_LARGE_ADDRESS_AWARE): Define. + (IMAGE_FILE_16BIT_MACHINE): Define. + (IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP): Define. + (IMAGE_FILE_UP_SYSTEM_ONLY): Define. + (IMAGE_FILE_MACHINE_UNKNOWN): Define. + (IMAGE_FILE_MACHINE_ALPHA): Define. + (IMAGE_FILE_MACHINE_ALPHA64): Define. + (IMAGE_FILE_MACHINE_I386): Define. + (IMAGE_FILE_MACHINE_IA64): Define. + (IMAGE_FILE_MACHINE_M68K): Define. + (IMAGE_FILE_MACHINE_MIPS16): Define. + (IMAGE_FILE_MACHINE_MIPSFPU): Define. + (IMAGE_FILE_MACHINE_MIPSFPU16): Define. + (IMAGE_FILE_MACHINE_POWERPC): Define. + (IMAGE_FILE_MACHINE_R3000): Define. + (IMAGE_FILE_MACHINE_R4000): Define. + (IMAGE_FILE_MACHINE_R10000): Define. + (IMAGE_FILE_MACHINE_SH3): Define. + (IMAGE_FILE_MACHINE_SH4): Define. + (IMAGE_FILE_MACHINE_THUMB): Define. + +1999-09-20 Alan Modra <alan@spri.levels.unisa.edu.au> + + * internal.h: Delete bogus R_PCLONG, duplicate R_RELBYTE and + R_RELWORD, and rewrite some R_* as decimal. + +1999-09-06 Donn Terry <donn@interix.com> + + * internal.h (DTYPE): Define. + * pe.h (struct external_PEI_filehdr): Rename from + external_PE_filehdr. Define even if COFF_IMAGE_WITH_PE is not + defined. + +1999-07-17 Nick Clifton <nickc@cygnus.com> + + * arm.h (F_SOFT_FLOAT): Rename from F_SOFTFLOAT. + +1999-06-21 Philip Blundell <pb@nexus.co.uk> + + * arm.h (F_SOFTFLOAT): Define. + +1999-07-05 Nick Clifton <nickc@cygnus.com> + + * arm.h (F_ARM_5): Define. + +Wed Jun 2 18:08:18 1999 Richard Henderson <rth@cygnus.com> + + * internal.h (BEOS_EXE_IMAGE_BASE, BEOS_DLL_IMAGE_BASE): New. + +Mon May 17 13:35:35 1999 Stan Cox <scox@cygnus.com> + + * coff/arm.h (F_PIC, F_ARM_2, F_ARM_2a, F_ARM_3, F_ARM_3M, + F_ARM_4, F_ARM_4T, F_APCS26): Changed values to distinguish + F_ARM_2a, F_ARM_3M, F_ARM_4T. + +1999-05-15 Nick Clifton <nickc@cygnus.com> + + * mcore.h (IMAGE_REL_MCORE_RVA): Define. + +1999-04-21 Nick Clifton <nickc@cygnus.com> + + * mcore.h (GET_LINENO_LNNO): New macro. + (PUT_LINENO_LNNO): New macro. + +1999-04-08 Nick Clifton <nickc@cygnus.com> + + * mcore.h: New header file. Defines for Motorola's MCore + processor. + +Sun Dec 6 21:36:37 1998 Mark Elbrecht <snowball3@usa.net> + + * internal.h (C_WEAKEXT): Define. + +Wed Jan 27 13:35:35 1999 Stan Cox <scox@cygnus.com> + + * coff/arm.h (F_PIC_INT, F_ARM_2, F_ARM_3, F_ARM_4, F_APCS26): + Changed values to avoid clashing with IMAGE_FILE_* coff header + flag values. + +Wed Apr 1 16:06:15 1998 Nick Clifton <nickc@cygnus.com> + + * internal.h: Document numbers associated with Thumb symbol + types. + Fri Mar 27 17:16:57 1998 Ian Lance Taylor <ian@cygnus.com> * internal.h (ISPTR, ISFCN, ISARY): Add casts to unsigned long. @@ -6,6 +110,11 @@ Mon Feb 2 17:10:38 1998 Steve Haworth <steve@pm.cse.rmit.EDU.AU> * tic30.h: New file. +Fri Dec 12 11:49:07 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (R_MPPCR15W): New relocation type, for 15 bit PC relative + offsets. + Tue Dec 2 10:21:40 1997 Nick Clifton <nickc@cygnus.com> * arm.h (COFFARM): New define. @@ -18,14 +127,32 @@ Sat Nov 22 15:10:14 1997 Nick Clifton <nickc@cygnus.com> * arm.h: Add bits to support PIC and APCS-FLOAT type binaries, when implemented. +Fri Oct 3 14:25:17 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (R_PPL16B): Make constant uppercase for consistency. + Tue Jul 22 18:18:58 1997 Robert Hoehne <robert.hoehne@Mathematik.TU-Chemnitz.DE> * go32exe.h: New file. +Tue Jul 8 12:23:55 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (TIC80_TARGET_ID): Add define. + * internal.h (struct internal_filehdr): Add f_target_id field. + Tue Jun 3 16:44:18 1997 Nick Clifton <nickc@cygnus.com> * internal.h: Add storage classes for Thumb symbols +Mon May 26 14:07:55 1997 Ian Lance Taylor <ian@cygnus.com> + + * tic80.h (R_PPL16B): Correct value. + +Sat May 3 08:24:59 1997 Fred Fish <fnf@cygnus.com> + + * internal.h (C_UEXT, C_STATLAB, C_EXTLAB, C_SYSTEM): + New storage classes for TIc80. + Fri Apr 18 11:52:55 1997 Niklas Hallqvist <niklas@appli.se> * alpha.h (ALPHA_ECOFF_BADMAG): Recognize *BSD/alpha magic too. @@ -42,6 +169,14 @@ Mon Jan 27 13:34:30 1997 Ian Lance Taylor <ian@cygnus.com> from here... * i960.h (R_IPRMED, R_OPTCALL, R_OPTCALLX): ...to here. +Wed Jan 22 20:10:47 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (TIC80MAGIC): Renamed to TIC80_AOUTHDR_MAGIC. + +Fri Dec 27 22:05:45 1996 Fred Fish <fnf@cygnus.com> + + * tic80.h: New file for TIc80 support. + Thu Dec 19 16:18:11 1996 Ian Lance Taylor <ian@cygnus.com> * arm.h (_LIT): Define. diff --git a/contrib/binutils/include/coff/arm.h b/contrib/binutils/include/coff/arm.h new file mode 100644 index 0000000..7ca9329 --- /dev/null +++ b/contrib/binutils/include/coff/arm.h @@ -0,0 +1,303 @@ +/* ARM COFF support for BFD. + Copyright (C) 1998, 1999 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#define COFFARM 1 + +/********************** FILE HEADER **********************/ + +struct external_filehdr +{ + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ +}; + +/* Bits for f_flags: + * F_RELFLG relocation info stripped from file + * F_EXEC file is executable (no unresolved external references) + * F_LNNO line numbers stripped from file + * F_LSYMS local symbols stripped from file + * F_INTERWORK file supports switching between ARM and Thumb instruction sets + * F_INTERWORK_SET the F_INTERWORK bit is valid + * F_APCS_FLOAT code passes float arguments in float registers + * F_PIC code is reentrant/position-independent + * F_AR32WR file has byte ordering of an AR32WR machine (e.g. vax) + * F_APCS_26 file uses 26 bit ARM Procedure Calling Standard + * F_APCS_SET the F_APCS_26, F_APCS_FLOAT and F_PIC bits have been initialised + * F_SOFT_FLOAT code does not use floating point instructions + */ + +#define F_RELFLG (0x0001) +#define F_EXEC (0x0002) +#define F_LNNO (0x0004) +#define F_LSYMS (0x0008) +#define F_INTERWORK (0x0010) +#define F_INTERWORK_SET (0x0020) +#define F_APCS_FLOAT (0x0040) +#undef F_AR16WR +#define F_PIC (0x0080) +#define F_AR32WR (0x0100) +#define F_APCS_26 (0x0400) +#define F_APCS_SET (0x0800) +#define F_SOFT_FLOAT (0x2000) + +/* Bits stored in flags field of the internal_f structure */ + +#define F_INTERWORK (0x0010) +#define F_APCS_FLOAT (0x0040) +#define F_PIC (0x0080) +#define F_APCS26 (0x1000) +#define F_ARM_ARCHITECTURE_MASK (0x4000+0x0800+0x0400) +#define F_ARM_2 (0x0400) +#define F_ARM_2a (0x0800) +#define F_ARM_3 (0x0c00) +#define F_ARM_3M (0x4000) +#define F_ARM_4 (0x4400) +#define F_ARM_4T (0x4800) +#define F_ARM_5 (0x4c00) + +/* + * ARMMAGIC ought to encoded the procesor type, + * but it is too late to change it now, instead + * the flags field of the internal_f structure + * is used as shown above. + * + * XXX - NC 5/6/97 + */ + +#define ARMMAGIC 0xa00 /* I just made this up */ + +#define ARMBADMAG(x) (((x).f_magic != ARMMAGIC)) + +#define ARMPEMAGIC 0x1c0 +#define THUMBPEMAGIC 0x1c2 + +#undef ARMBADMAG +#define ARMBADMAG(x) (((x).f_magic != ARMMAGIC) && ((x).f_magic != ARMPEMAGIC) && ((x).f_magic != THUMBPEMAGIC)) + +#define FILHDR struct external_filehdr +#define FILHSZ 20 + + +/********************** AOUT "OPTIONAL HEADER" **********************/ + + +typedef struct +{ + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry*/ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ +} +AOUTHDR; + + +#define AOUTSZ 28 +#define AOUTHDRSZ 28 + +#define OMAGIC 0404 /* object files, eg as output */ +#define ZMAGIC 0413 /* demand load format, eg normal ld output */ +#define STMAGIC 0401 /* target shlib */ +#define SHMAGIC 0443 /* host shlib */ + + +/* define some NT default values */ +/* #define NT_IMAGE_BASE 0x400000 moved to internal.h */ +#define NT_SECTION_ALIGNMENT 0x1000 +#define NT_FILE_ALIGNMENT 0x200 +#define NT_DEF_RESERVE 0x100000 +#define NT_DEF_COMMIT 0x1000 + +/********************** SECTION HEADER **********************/ +struct external_scnhdr +{ + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries*/ + char s_flags[4]; /* flags */ +}; + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 40 + +/* + * names of "special" sections + */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" +#define _COMMENT ".comment" +#define _LIB ".lib" + +/* We use the .rdata section to hold read only data. */ +#define _LIT ".rdata" + +/********************** LINE NUMBERS **********************/ + +/* 1 line number entry for every "breakpointable" source line in a section. + * Line numbers are grouped on a per function basis; first entry in a function + * grouping will have l_lnno = 0 and in place of physical address will be the + * symbol table index of the function name. + */ +struct external_lineno +{ + union + { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ + char l_paddr[4]; /* (physical) address of line number */ + } l_addr; + char l_lnno[2]; /* line number */ +}; + + +#define LINENO struct external_lineno +#define LINESZ 6 + + +/********************** SYMBOLS **********************/ + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ +#define E_FILNMLEN 14 /* # characters in a file name */ +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union + { + char e_name[E_SYMNMLEN]; + struct + { + char e_zeroes[4]; + char e_offset[4]; + } e; + } e; + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; +}; + +#define N_BTMASK (0xf) +#define N_TMASK (0x30) +#define N_BTSHFT (4) +#define N_TSHIFT (2) + +union external_auxent +{ + struct + { + char x_tagndx[4]; /* str, un, or enum tag indx */ + union + { + struct + { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + char x_fsize[4]; /* size of function */ + } x_misc; + union + { + struct /* if ISFCN, tag, or .bb */ + { + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + struct /* if ISARY, up to 4 dimen. */ + { + char x_dimen[E_DIMNUM][2]; + } x_ary; + } x_fcnary; + char x_tvndx[2]; /* tv index */ + } x_sym; + + union + { + char x_fname[E_FILNMLEN]; + struct + { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + } x_file; + + struct + { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + char x_checksum[4]; /* section COMDAT checksum */ + char x_associated[2]; /* COMDAT associated section index */ + char x_comdat[1]; /* COMDAT selection number */ + } x_scn; + + struct + { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ +}; + +#define SYMENT struct external_syment +#define SYMESZ 18 +#define AUXENT union external_auxent +#define AUXESZ 18 + +#define _ETEXT "etext" + +/********************** RELOCATION DIRECTIVES **********************/ +#ifdef ARM_WINCE +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 10 + +#else +struct external_reloc +{ + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; + char r_offset[4]; +}; + +#define RELOC struct external_reloc +#define RELSZ 14 +#endif diff --git a/contrib/binutils/include/coff/internal.h b/contrib/binutils/include/coff/internal.h index d873f28..e89b528 100644 --- a/contrib/binutils/include/coff/internal.h +++ b/contrib/binutils/include/coff/internal.h @@ -53,6 +53,7 @@ struct internal_filehdr long f_nsyms; /* number of symtab entries */ unsigned short f_opthdr; /* sizeof(optional hdr) */ unsigned short f_flags; /* flags */ + unsigned short f_target_id; /* (TIc80 specific) */ }; @@ -88,10 +89,14 @@ typedef struct _IMAGE_DATA_DIRECTORY } IMAGE_DATA_DIRECTORY; #define IMAGE_NUMBEROF_DIRECTORY_ENTRIES 16 -/* default image base for NT */ +/* Default image base for NT. */ #define NT_EXE_IMAGE_BASE 0x400000 #define NT_DLL_IMAGE_BASE 0x10000000 +/* Default image base for BeOS. */ +#define BEOS_EXE_IMAGE_BASE 0x80000000 +#define BEOS_DLL_IMAGE_BASE 0x10000000 + /* Extra stuff in a PE aouthdr */ #define PE_DEF_SECTION_ALIGNMENT 0x1000 @@ -215,6 +220,13 @@ struct internal_aouthdr #define C_ALIAS 105 /* duplicate tag */ #define C_HIDDEN 106 /* ext symbol in dmert public lib */ +#define C_WEAKEXT 127 /* weak symbol -- GNU extension */ + +/* New storage classes for TIc80 */ +#define C_UEXT 19 /* Tentative external definition */ +#define C_STATLAB 20 /* Static load time label */ +#define C_EXTLAB 21 /* External load time label */ +#define C_SYSTEM 23 /* System Wide variable */ /* New storage classes for WINDOWS_NT */ #define C_SECTION 104 /* section name */ @@ -260,11 +272,11 @@ struct internal_aouthdr #define C_ESTAT (0x90) /* Storage classes for Thumb symbols */ -#define C_THUMBEXT (128 + C_EXT) -#define C_THUMBSTAT (128 + C_STAT) -#define C_THUMBLABEL (128 + C_LABEL) -#define C_THUMBEXTFUNC (C_THUMBEXT + 20) -#define C_THUMBSTATFUNC (C_THUMBSTAT + 20) +#define C_THUMBEXT (128 + C_EXT) /* 130 */ +#define C_THUMBSTAT (128 + C_STAT) /* 131 */ +#define C_THUMBLABEL (128 + C_LABEL) /* 134 */ +#define C_THUMBEXTFUNC (C_THUMBEXT + 20) /* 150 */ +#define C_THUMBSTATFUNC (C_THUMBSTAT + 20) /* 151 */ /********************** SECTION HEADER **********************/ @@ -409,6 +421,7 @@ struct internal_syment #define DT_ARY (3) /* array */ #define BTYPE(x) ((x) & N_BTMASK) +#define DTYPE(x) (((x) & N_TMASK) >> N_BTSHFT) #define ISPTR(x) \ (((unsigned long) (x) & N_TMASK) == ((unsigned long) DT_PTR << N_BTSHFT)) @@ -577,33 +590,28 @@ struct internal_reloc unsigned long r_offset; /* Used by Alpha ECOFF, SPARC, others */ }; -#define R_RELBYTE 017 -#define R_RELWORD 020 -#define R_PCRBYTE 022 -#define R_PCRWORD 023 -#define R_PCRLONG 024 - -#define R_DIR16 01 -#define R_DIR32 06 -#define R_PCLONG 020 -#define R_RELBYTE 017 -#define R_RELWORD 020 -#define R_IMAGEBASE 07 - - -#define R_PCR16L 128 -#define R_PCR26L 129 -#define R_VRT16 130 -#define R_HVRT16 131 -#define R_LVRT16 132 -#define R_VRT32 133 -#define R_RELLONG (0x11) /* Direct 32-bit relocation */ -#define R_IPRSHORT (0x18) -#define R_IPRLONG (0x1a) -#define R_GETSEG (0x1d) -#define R_GETPA (0x1e) -#define R_TAGWORD (0x1f) -#define R_JUMPTARG 0x20 /* strange 29k 00xx00xx reloc */ +#define R_DIR16 1 +#define R_DIR32 6 +#define R_IMAGEBASE 7 +#define R_RELBYTE 15 +#define R_RELWORD 16 +#define R_RELLONG 17 +#define R_PCRBYTE 18 +#define R_PCRWORD 19 +#define R_PCRLONG 20 +#define R_IPRSHORT 24 +#define R_IPRLONG 26 +#define R_GETSEG 29 +#define R_GETPA 30 +#define R_TAGWORD 31 +#define R_JUMPTARG 32 /* strange 29k 00xx00xx reloc */ + +#define R_PCR16L 128 +#define R_PCR26L 129 +#define R_VRT16 130 +#define R_HVRT16 131 +#define R_LVRT16 132 +#define R_VRT32 133 /* This reloc identifies mov.b instructions with a 16bit absolute @@ -663,7 +671,7 @@ struct internal_reloc #define R_MOVL1 0x4c /* This reloc identifies mov.[wl] insns which formerlly had - a 32/24bit absolute address and how have a 16bit absolute address. */ + a 32/24bit absolute address and now have a 16bit absolute address. */ #define R_MOVL2 0x4d /* This reloc identifies a bCC:8 which will have it's condition diff --git a/contrib/binutils/include/coff/pe.h b/contrib/binutils/include/coff/pe.h index 7e676a5..6932ee8 100644 --- a/contrib/binutils/include/coff/pe.h +++ b/contrib/binutils/include/coff/pe.h @@ -3,29 +3,32 @@ #ifndef _PE_H #define _PE_H -/* NT specific file attributes */ +/* NT specific file attributes. */ #define IMAGE_FILE_RELOCS_STRIPPED 0x0001 #define IMAGE_FILE_EXECUTABLE_IMAGE 0x0002 #define IMAGE_FILE_LINE_NUMS_STRIPPED 0x0004 #define IMAGE_FILE_LOCAL_SYMS_STRIPPED 0x0008 +#define IMAGE_FILE_AGGRESSIVE_WS_TRIM 0x0010 +#define IMAGE_FILE_LARGE_ADDRESS_AWARE 0x0020 +#define IMAGE_FILE_16BIT_MACHINE 0x0040 #define IMAGE_FILE_BYTES_REVERSED_LO 0x0080 #define IMAGE_FILE_32BIT_MACHINE 0x0100 #define IMAGE_FILE_DEBUG_STRIPPED 0x0200 +#define IMAGE_FILE_REMOVABLE_RUN_FROM_SWAP 0x0400 #define IMAGE_FILE_SYSTEM 0x1000 #define IMAGE_FILE_DLL 0x2000 +#define IMAGE_FILE_UP_SYSTEM_ONLY 0x4000 #define IMAGE_FILE_BYTES_REVERSED_HI 0x8000 -/* additional flags to be set for section headers to allow the NT loader to +/* Additional flags to be set for section headers to allow the NT loader to read and write to the section data (to replace the addresses of data in - dlls for one thing); also to execute the section in .text's case */ + dlls for one thing); also to execute the section in .text's case. */ #define IMAGE_SCN_MEM_DISCARDABLE 0x02000000 #define IMAGE_SCN_MEM_EXECUTE 0x20000000 #define IMAGE_SCN_MEM_READ 0x40000000 #define IMAGE_SCN_MEM_WRITE 0x80000000 -/* - * Section characteristics added for ppc-nt - */ +/* Section characteristics added for ppc-nt. */ #define IMAGE_SCN_TYPE_NO_PAD 0x00000008 /* Reserved. */ @@ -53,7 +56,6 @@ #define IMAGE_SCN_ALIGN_32BYTES 0x00600000 #define IMAGE_SCN_ALIGN_64BYTES 0x00700000 - #define IMAGE_SCN_LNK_NRELOC_OVFL 0x01000000 /* Section contains extended relocations. */ #define IMAGE_SCN_MEM_NOT_CACHED 0x04000000 /* Section is not cachable. */ #define IMAGE_SCN_MEM_NOT_PAGED 0x08000000 /* Section is not pageable. */ @@ -67,6 +69,26 @@ #define IMAGE_COMDAT_SELECT_EXACT_MATCH (4) /* Warn if different. */ #define IMAGE_COMDAT_SELECT_ASSOCIATIVE (5) /* Base on other section. */ +/* Machine numbers. */ + +#define IMAGE_FILE_MACHINE_UNKNOWN 0x0 +#define IMAGE_FILE_MACHINE_ALPHA 0x184 +#define IMAGE_FILE_MACHINE_ARM 0x1c0 +#define IMAGE_FILE_MACHINE_ALPHA64 0x284 +#define IMAGE_FILE_MACHINE_I386 0x14c +#define IMAGE_FILE_MACHINE_IA64 0x200 +#define IMAGE_FILE_MACHINE_M68K 0x268 +#define IMAGE_FILE_MACHINE_MIPS16 0x266 +#define IMAGE_FILE_MACHINE_MIPSFPU 0x366 +#define IMAGE_FILE_MACHINE_MIPSFPU16 0x466 +#define IMAGE_FILE_MACHINE_POWERPC 0x1f0 +#define IMAGE_FILE_MACHINE_R3000 0x162 +#define IMAGE_FILE_MACHINE_R4000 0x166 +#define IMAGE_FILE_MACHINE_R10000 0x168 +#define IMAGE_FILE_MACHINE_SH3 0x1a2 +#define IMAGE_FILE_MACHINE_SH4 0x1a6 +#define IMAGE_FILE_MACHINE_THUMB 0x1c2 + /* Magic values that are true for all dos/nt implementations */ #define DOSMAGIC 0x5a4d #define NT_SIGNATURE 0x00004550 @@ -76,12 +98,7 @@ #undef FILNMLEN #define FILNMLEN 18 /* # characters in a file name */ - -#ifdef COFF_IMAGE_WITH_PE -/* The filehdr is only weired in images */ - -#undef FILHDR -struct external_PE_filehdr +struct external_PEI_filehdr { /* DOS header fields */ char e_magic[2]; /* Magic number, 0x5a4d */ @@ -108,7 +125,6 @@ struct external_PE_filehdr /* From standard header */ - char f_magic[2]; /* magic number */ char f_nscns[2]; /* number of sections */ char f_timdat[4]; /* time & date stamp */ @@ -119,12 +135,16 @@ struct external_PE_filehdr }; +#ifdef COFF_IMAGE_WITH_PE + +/* The filehdr is only weird in images. */ -#define FILHDR struct external_PE_filehdr -#undef FILHSZ +#undef FILHDR +#define FILHDR struct external_PEI_filehdr +#undef FILHSZ #define FILHSZ 152 -#endif +#endif /* COFF_IMAGE_WITH_PE */ typedef struct { @@ -163,7 +183,16 @@ typedef struct #undef E_FILNMLEN #define E_FILNMLEN 18 /* # characters in a file name */ -#endif +/* Import Tyoes fot ILF format object files.. */ +#define IMPORT_CODE 0 +#define IMPORT_DATA 1 +#define IMPORT_CONST 2 +/* Import Name Tyoes for ILF format object files. */ +#define IMPORT_ORDINAL 0 +#define IMPORT_NAME 1 +#define IMPORT_NAME_NOPREFIX 2 +#define IMPORT_NAME_UNDECORATE 3 +#endif /* _PE_H */ diff --git a/contrib/binutils/include/coff/powerpc.h b/contrib/binutils/include/coff/powerpc.h new file mode 100644 index 0000000..9552cf9 --- /dev/null +++ b/contrib/binutils/include/coff/powerpc.h @@ -0,0 +1,199 @@ +/* Basic coff information for the PowerPC + * + * Based on coff/rs6000.h, coff/i386.h and others. + * + * Initial release: Kim Knuttila (krk@cygnus.com) + */ + +/********************** FILE HEADER **********************/ + +struct external_filehdr { + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ +}; + +#define FILHDR struct external_filehdr +#define FILHSZ 20 + +/* Bits for f_flags: + * F_RELFLG relocation info stripped from file + * F_EXEC file is executable (no unresolved external references) + * F_LNNO line numbers stripped from file + * F_LSYMS local symbols stripped from file + * F_AR32WR file has byte ordering of an AR32WR machine (e.g. vax) + */ + +#define F_RELFLG (0x0001) +#define F_EXEC (0x0002) +#define F_LNNO (0x0004) +#define F_LSYMS (0x0008) + +/* extra NT defines */ +#define PPCMAGIC 0760 /* peeked on aa PowerPC Windows NT box */ +#define DOSMAGIC 0x5a4d /* from arm.h, i386.h */ +#define NT_SIGNATURE 0x00004550 /* from arm.h, i386.h */ + +/* from winnt.h */ +#define IMAGE_NT_OPTIONAL_HDR_MAGIC 0x10b + +#define PPCBADMAG(x) ((x).f_magic != PPCMAGIC) + +/********************** AOUT "OPTIONAL HEADER" **********************/ + +typedef struct +{ + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry*/ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ +} +AOUTHDR; + +#define AOUTSZ 28 +#define AOUTHDRSZ 28 + +/********************** SECTION HEADER **********************/ + +struct external_scnhdr { + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries */ + char s_flags[4]; /* flags */ +}; + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 40 + +/* + * names of "special" sections + */ +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" +#define _COMMENT ".comment" +#define _LIB ".lib" + +/********************** LINE NUMBERS **********************/ + +/* 1 line number entry for every "breakpointable" source line in a section. + * Line numbers are grouped on a per function basis; first entry in a function + * grouping will have l_lnno = 0 and in place of physical address will be the + * symbol table index of the function name. + */ +struct external_lineno { + union { + char l_symndx[4]; /* function name symbol index, iff l_lnno == 0 */ + char l_paddr[4]; /* (physical) address of line number */ + } l_addr; + char l_lnno[2]; /* line number */ +}; + +#define LINENO struct external_lineno +#define LINESZ 6 + +/********************** SYMBOLS **********************/ + +#define E_SYMNMLEN 8 /* # characters in a symbol name */ + +/* Allow the file name length to be overridden in the including file */ +#ifndef E_FILNMLEN +#define E_FILNMLEN 14 +#endif + +#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union { + char e_name[E_SYMNMLEN]; + struct { + char e_zeroes[4]; + char e_offset[4]; + } e; + } e; + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; +}; + +#define SYMENT struct external_syment +#define SYMESZ 18 + +#define N_BTMASK (0xf) +#define N_TMASK (0x30) +#define N_BTSHFT (4) +#define N_TSHIFT (2) + +union external_auxent { + struct { + char x_tagndx[4]; /* str, un, or enum tag indx */ + union { + struct { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + char x_fsize[4]; /* size of function */ + } x_misc; + union { + struct { /* if ISFCN, tag, or .bb */ + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + struct { /* if ISARY, up to 4 dimen. */ + char x_dimen[E_DIMNUM][2]; + } x_ary; + } x_fcnary; + char x_tvndx[2]; /* tv index */ + } x_sym; + + union { + char x_fname[E_FILNMLEN]; + struct { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + } x_file; + + struct { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + char x_checksum[4]; /* section COMDAT checksum */ + char x_associated[2]; /* COMDAT associated section index */ + char x_comdat[1]; /* COMDAT selection number */ + } x_scn; +}; + +#define AUXENT union external_auxent +#define AUXESZ 18 + +#define _ETEXT "etext" + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc { + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; + +#define RELOC struct external_reloc +#define RELSZ 10 + diff --git a/contrib/binutils/include/coff/sh.h b/contrib/binutils/include/coff/sh.h index 41957df..f7271f2 100644 --- a/contrib/binutils/include/coff/sh.h +++ b/contrib/binutils/include/coff/sh.h @@ -16,10 +16,13 @@ struct external_filehdr { #define SH_ARCH_MAGIC_BIG 0x0500 #define SH_ARCH_MAGIC_LITTLE 0x0550 /* Little endian SH */ +#define SH_ARCH_MAGIC_WINCE 0x01a2 /* Windows CE - little endian */ +#define SH_PE_MAGIC 0x010b #define SHBADMAG(x) \ (((x).f_magic!=SH_ARCH_MAGIC_BIG) && \ + ((x).f_magic!=SH_ARCH_MAGIC_WINCE) && \ ((x).f_magic!=SH_ARCH_MAGIC_LITTLE)) #define FILHDR struct external_filehdr @@ -48,6 +51,12 @@ AOUTHDR; +/* Define some NT default values. */ +/* #define NT_IMAGE_BASE 0x400000 moved to internal.h */ +#define NT_SECTION_ALIGNMENT 0x1000 +#define NT_FILE_ALIGNMENT 0x200 +#define NT_DEF_RESERVE 0x100000 +#define NT_DEF_COMMIT 0x1000 /********************** SECTION HEADER **********************/ @@ -89,14 +98,26 @@ struct external_lineno { char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/ char l_paddr[4]; /* (physical) address of line number */ } l_addr; +#ifdef COFF_WITH_PE + char l_lnno[2]; /* line number */ +#else char l_lnno[4]; /* line number */ +#endif }; #define GET_LINENO_LNNO(abfd, ext) bfd_h_get_32(abfd, (bfd_byte *) (ext->l_lnno)); #define PUT_LINENO_LNNO(abfd,val, ext) bfd_h_put_32(abfd,val, (bfd_byte *) (ext->l_lnno)); #define LINENO struct external_lineno +#ifdef COFF_WITH_PE +#define LINESZ 6 +#undef GET_LINENO_LNNO +#define GET_LINENO_LNNO(abfd, ext) bfd_h_get_16(abfd, (bfd_byte *) (ext->l_lnno)); +#undef PUT_LINENO_LNNO +#define PUT_LINENO_LNNO(abfd,val, ext) bfd_h_put_16(abfd,val, (bfd_byte *) (ext->l_lnno)); +#else #define LINESZ 8 +#endif /********************** SYMBOLS **********************/ @@ -163,6 +184,9 @@ union external_auxent { char x_scnlen[4]; /* section length */ char x_nreloc[2]; /* # relocation entries */ char x_nlinno[2]; /* # line numbers */ + char x_checksum[4]; /* section COMDAT checksum */ + char x_associated[2]; /* COMDAT associated section index */ + char x_comdat[1]; /* COMDAT selection number */ } x_scn; struct { @@ -187,6 +211,7 @@ union external_auxent { types on the h8 don't have room in the instruction for the entire offset - eg the strange jump and high page addressing modes */ +#ifndef COFF_WITH_PE struct external_reloc { char r_vaddr[4]; char r_symndx[4]; @@ -194,14 +219,26 @@ struct external_reloc { char r_type[2]; char r_stuff[2]; }; +#else +struct external_reloc { + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; +}; +#endif #define RELOC struct external_reloc +#ifdef COFF_WITH_PE +#define RELSZ 10 +#else #define RELSZ 16 +#endif /* SH relocation types. Not all of these are actually used. */ #define R_SH_UNUSED 0 /* only used internally */ +#define R_SH_IMM32CE 2 /* 32 bit immediate for WinCE */ #define R_SH_PCREL8 3 /* 8 bit pcrel */ #define R_SH_PCREL16 4 /* 16 bit pcrel */ #define R_SH_HIGH8 5 /* high 8 bits of 24 bit address */ @@ -213,6 +250,7 @@ struct external_reloc { #define R_SH_PCDISP 12 /* 12 bit branch */ #define R_SH_IMM32 14 /* 32 bit immediate */ #define R_SH_IMM8 16 /* 8 bit immediate */ +#define R_SH_IMAGEBASE 16 /* Windows CE */ #define R_SH_IMM8BY2 17 /* 8 bit immediate *2 */ #define R_SH_IMM8BY4 18 /* 8 bit immediate *4 */ #define R_SH_IMM4 19 /* 4 bit immediate */ diff --git a/contrib/binutils/include/coff/sparc.h b/contrib/binutils/include/coff/sparc.h new file mode 100644 index 0000000..82a24f0 --- /dev/null +++ b/contrib/binutils/include/coff/sparc.h @@ -0,0 +1,210 @@ +/*** coff information for Sparc. */ + +/* This file is an amalgamation of several standard include files that + define coff format, such as filehdr.h, aouthdr.h, and so forth. In + addition, all datatypes have been translated into character arrays of + (presumed) equivalent size. This is necessary so that this file can + be used with different systems while still yielding the same results. */ + +/********************** FILE HEADER **********************/ + +struct external_filehdr +{ + char f_magic[2]; /* magic number */ + char f_nscns[2]; /* number of sections */ + char f_timdat[4]; /* time & date stamp */ + char f_symptr[4]; /* file pointer to symtab */ + char f_nsyms[4]; /* number of symtab entries */ + char f_opthdr[2]; /* sizeof(optional hdr) */ + char f_flags[2]; /* flags */ +}; + +#define F_RELFLG (0x0001) /* relocation info stripped */ +#define F_EXEC (0x0002) /* file is executable */ +#define F_LNNO (0x0004) /* line numbers stripped */ +#define F_LSYMS (0x0008) /* local symbols stripped */ + +#define SPARCMAGIC (0540) + +/* This is Lynx's all-platform magic number for executables. */ + +#define LYNXCOFFMAGIC (0415) + +#define FILHDR struct external_filehdr +#define FILHSZ 20 + +/********************** AOUT "OPTIONAL HEADER" **********************/ + +typedef struct +{ + char magic[2]; /* type of file */ + char vstamp[2]; /* version stamp */ + char tsize[4]; /* text size in bytes, padded to FW bdry*/ + char dsize[4]; /* initialized data " " */ + char bsize[4]; /* uninitialized data " " */ + char entry[4]; /* entry pt. */ + char text_start[4]; /* base of text used for this file */ + char data_start[4]; /* base of data used for this file */ +} +AOUTHDR; + +#define AOUTSZ 28 +#define AOUTHDRSZ 28 + +#define OMAGIC 0404 /* object files, eg as output */ +#define ZMAGIC 0413 /* demand load format, eg normal ld output */ +#define STMAGIC 0401 /* target shlib */ +#define SHMAGIC 0443 /* host shlib */ + +/********************** SECTION HEADER **********************/ + +struct external_scnhdr +{ + char s_name[8]; /* section name */ + char s_paddr[4]; /* physical address, aliased s_nlib */ + char s_vaddr[4]; /* virtual address */ + char s_size[4]; /* section size */ + char s_scnptr[4]; /* file ptr to raw data for section */ + char s_relptr[4]; /* file ptr to relocation */ + char s_lnnoptr[4]; /* file ptr to line numbers */ + char s_nreloc[2]; /* number of relocation entries */ + char s_nlnno[2]; /* number of line number entries*/ + char s_flags[4]; /* flags */ +}; + +#define SCNHDR struct external_scnhdr +#define SCNHSZ 40 + +/* Names of "special" sections. */ + +#define _TEXT ".text" +#define _DATA ".data" +#define _BSS ".bss" +#define _TV ".tv" +#define _INIT ".init" +#define _FINI ".fini" +#define _COMMENT ".comment" +#define _LIB ".lib" + +/********************** LINE NUMBERS **********************/ + +/* 1 line number entry for every "breakpointable" source line in a section. + Line numbers are grouped on a per function basis; first entry in a function + grouping will have l_lnno = 0 and in place of physical address will be the + symbol table index of the function name. */ + +struct external_lineno +{ + union { + char l_symndx[4]; /* fn name symbol index, iff l_lnno == 0 */ + char l_paddr[4]; /* (physical) address of line number */ + } l_addr; + char l_lnno[2]; /* line number */ +}; + +#define LINENO struct external_lineno +#define LINESZ (6) + +/********************** SYMBOLS **********************/ + +#define E_SYMNMLEN (8) /* # characters in a symbol name */ +#define E_FILNMLEN (14) /* # characters in a file name */ +#define E_DIMNUM (4) /* # array dimensions in auxiliary entry */ + +struct external_syment +{ + union { + char e_name[E_SYMNMLEN]; + struct { + char e_zeroes[4]; + char e_offset[4]; + } e; +#if 0 /* of doubtful value */ + char e_nptr[2][4]; + struct { + char e_leading_zero[1]; + char e_dbx_type[1]; + char e_dbx_desc[2]; + } e_dbx; +#endif + } e; + + char e_value[4]; + char e_scnum[2]; + char e_type[2]; + char e_sclass[1]; + char e_numaux[1]; + char padding[2]; +}; + +#define N_BTMASK (0xf) +#define N_TMASK (0x30) +#define N_BTSHFT (4) +#define N_TSHIFT (2) + +union external_auxent +{ + struct { + char x_tagndx[4]; /* str, un, or enum tag indx */ + union { + struct { + char x_lnno[2]; /* declaration line number */ + char x_size[2]; /* str/union/array size */ + } x_lnsz; + char x_fsize[4]; /* size of function */ + } x_misc; + union { + struct { /* if ISFCN, tag, or .bb */ + char x_lnnoptr[4]; /* ptr to fcn line # */ + char x_endndx[4]; /* entry ndx past block end */ + } x_fcn; + struct { /* if ISARY, up to 4 dimen. */ + char x_dimen[E_DIMNUM][2]; + } x_ary; + } x_fcnary; + char x_tvndx[2]; /* tv index */ + } x_sym; + + union { + char x_fname[E_FILNMLEN]; + struct { + char x_zeroes[4]; + char x_offset[4]; + } x_n; + } x_file; + + struct { + char x_scnlen[4]; /* section length */ + char x_nreloc[2]; /* # relocation entries */ + char x_nlinno[2]; /* # line numbers */ + } x_scn; + + struct { + char x_tvfill[4]; /* tv fill value */ + char x_tvlen[2]; /* length of .tv */ + char x_tvran[2][2]; /* tv range */ + } x_tv; /* .tv section info (in auxent of sym .tv)) */ + + char x_fill[20]; /* forces to 20-byte size */ +}; + +#define SYMENT struct external_syment +#define SYMESZ 20 +#define AUXENT union external_auxent +#define AUXESZ 20 + +#define _ETEXT "etext" + +/********************** RELOCATION DIRECTIVES **********************/ + +struct external_reloc { + char r_vaddr[4]; + char r_symndx[4]; + char r_type[2]; + char r_spare[2]; + char r_offset[4]; +}; + +#define RELOC struct external_reloc +#define RELSZ 16 + diff --git a/contrib/binutils/include/demangle.h b/contrib/binutils/include/demangle.h index 00f6a0c..63fe5e2 100644 --- a/contrib/binutils/include/demangle.h +++ b/contrib/binutils/include/demangle.h @@ -20,12 +20,7 @@ #if !defined (DEMANGLE_H) #define DEMANGLE_H -#ifdef IN_GCC -#include "gansidecl.h" -#define PARAMS(ARGS) PROTO(ARGS) -#else /* ! IN_GCC */ #include <ansidecl.h> -#endif /* IN_GCC */ /* Options passed to cplus_demangle (in 2nd parameter). */ @@ -38,8 +33,12 @@ #define DMGL_GNU (1 << 9) #define DMGL_LUCID (1 << 10) #define DMGL_ARM (1 << 11) +#define DMGL_HP (1 << 12) /* For the HP aCC compiler; same as ARM + except for template arguments, etc. */ +#define DMGL_EDG (1 << 13) + /* If none of these are set, use 'current_demangling_style' as the default. */ -#define DMGL_STYLE_MASK (DMGL_AUTO|DMGL_GNU|DMGL_LUCID|DMGL_ARM) +#define DMGL_STYLE_MASK (DMGL_AUTO|DMGL_GNU|DMGL_LUCID|DMGL_ARM|DMGL_HP|DMGL_EDG) /* Enumeration of possible demangling styles. @@ -55,7 +54,9 @@ extern enum demangling_styles auto_demangling = DMGL_AUTO, gnu_demangling = DMGL_GNU, lucid_demangling = DMGL_LUCID, - arm_demangling = DMGL_ARM + arm_demangling = DMGL_ARM, + hp_demangling = DMGL_HP, + edg_demangling = DMGL_EDG } current_demangling_style; /* Define string names for the various demangling styles. */ @@ -64,6 +65,8 @@ extern enum demangling_styles #define GNU_DEMANGLING_STYLE_STRING "gnu" #define LUCID_DEMANGLING_STYLE_STRING "lucid" #define ARM_DEMANGLING_STYLE_STRING "arm" +#define HP_DEMANGLING_STYLE_STRING "hp" +#define EDG_DEMANGLING_STYLE_STRING "edg" /* Some macros to test what demangling style is active. */ @@ -71,7 +74,9 @@ extern enum demangling_styles #define AUTO_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_AUTO) #define GNU_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_GNU) #define LUCID_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_LUCID) -#define ARM_DEMANGLING (CURRENT_DEMANGLING_STYLE & DMGL_ARM) +#define ARM_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_ARM) +#define HP_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_HP) +#define EDG_DEMANGLING (((int) CURRENT_DEMANGLING_STYLE) & DMGL_EDG) extern char * cplus_demangle PARAMS ((const char *mangled, int options)); diff --git a/contrib/binutils/include/dis-asm.h b/contrib/binutils/include/dis-asm.h index bd7e478..6e6c04b 100644 --- a/contrib/binutils/include/dis-asm.h +++ b/contrib/binutils/include/dis-asm.h @@ -9,10 +9,14 @@ #ifndef DIS_ASM_H #define DIS_ASM_H +#ifdef __cplusplus +extern "C" { +#endif + #include <stdio.h> #include "bfd.h" -typedef int (*fprintf_ftype) PARAMS((FILE*, const char*, ...)); +typedef int (*fprintf_ftype) PARAMS((PTR, const char*, ...)); enum dis_insn_type { dis_noninsn, /* Not a valid instruction */ @@ -37,7 +41,7 @@ enum dis_insn_type { typedef struct disassemble_info { fprintf_ftype fprintf_func; - FILE *stream; + PTR stream; PTR application_data; /* Target description. We could replace this with a pointer to the bfd, @@ -74,7 +78,7 @@ typedef struct disassemble_info { INFO is a pointer to this struct. Returns an errno value or 0 for success. */ int (*read_memory_func) - PARAMS ((bfd_vma memaddr, bfd_byte *myaddr, int length, + PARAMS ((bfd_vma memaddr, bfd_byte *myaddr, unsigned int length, struct disassemble_info *info)); /* Function which should be called if we get an error that we can't @@ -101,7 +105,7 @@ typedef struct disassemble_info { /* These are for buffer_read_memory. */ bfd_byte *buffer; bfd_vma buffer_vma; - int buffer_length; + unsigned int buffer_length; /* This variable may be set by the instruction decoder. It suggests the number of bytes objdump should display on a single line. If @@ -117,6 +121,11 @@ typedef struct disassemble_info { int bytes_per_chunk; enum bfd_endian display_endian; + /* Number of octets per incremented target address + Normally one, but some DSPs have byte sizes of 16 or 32 bits + */ + unsigned int octets_per_byte; + /* Results from instruction decoders. Not all decoders yet support this information. This info is set each time an instruction is decoded, and is only valid for the last such instruction. @@ -133,6 +142,9 @@ typedef struct disassemble_info { zero if unknown. */ bfd_vma target2; /* Second target address for dref2 */ + /* Command line options specific to the target disassembler. */ + char * disassembler_options; + } disassemble_info; @@ -143,7 +155,9 @@ typedef int (*disassembler_ftype) extern int print_insn_big_mips PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_little_mips PARAMS ((bfd_vma, disassemble_info*)); -extern int print_insn_i386 PARAMS ((bfd_vma, disassemble_info*)); +extern int print_insn_i386_att PARAMS ((bfd_vma, disassemble_info*)); +extern int print_insn_i386_intel PARAMS ((bfd_vma, disassemble_info*)); +extern int print_insn_i370 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_m68k PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_z8001 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_z8002 PARAMS ((bfd_vma, disassemble_info*)); @@ -162,8 +176,10 @@ extern int print_insn_i960 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_sh PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_shl PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_hppa PARAMS ((bfd_vma, disassemble_info*)); +extern int print_insn_fr30 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_m32r PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_m88k PARAMS ((bfd_vma, disassemble_info*)); +extern int print_insn_mcore PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_mn10200 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_mn10300 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_ns32k PARAMS ((bfd_vma, disassemble_info*)); @@ -172,12 +188,26 @@ extern int print_insn_little_powerpc PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_rs6000 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_w65 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_d10v PARAMS ((bfd_vma, disassemble_info*)); +extern int print_insn_d30v PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_v850 PARAMS ((bfd_vma, disassemble_info*)); extern int print_insn_tic30 PARAMS ((bfd_vma, disassemble_info*)); +extern int print_insn_vax PARAMS ((bfd_vma, disassemble_info*)); +extern int print_insn_tic80 PARAMS ((bfd_vma, disassemble_info*)); +extern int print_insn_pj PARAMS ((bfd_vma, disassemble_info*)); +extern int print_insn_avr PARAMS ((bfd_vma, disassemble_info*)); + +extern void print_arm_disassembler_options PARAMS ((FILE *)); +extern void parse_arm_disassembler_option PARAMS ((char *)); +extern int get_arm_regname_num_options PARAMS ((void)); +extern int set_arm_regname_option PARAMS ((int)); +extern int get_arm_regnames PARAMS ((int, const char **, const char **, const char ***)); /* Fetch the disassembler for a given BFD, if that support is available. */ extern disassembler_ftype disassembler PARAMS ((bfd *)); +/* Document any target specific options available from the disassembler. */ +extern void disassembler_usage PARAMS ((FILE *)); + /* This block of definitions is for particular callers who read instructions into a buffer before calling the instruction decoder. */ @@ -185,7 +215,7 @@ extern disassembler_ftype disassembler PARAMS ((bfd *)); /* Here is a function which callers may wish to use for read_memory_func. It gets bytes from a buffer. */ extern int buffer_read_memory - PARAMS ((bfd_vma, bfd_byte *, int, struct disassemble_info *)); + PARAMS ((bfd_vma, bfd_byte *, unsigned int, struct disassemble_info *)); /* This function goes with buffer_read_memory. It prints a message using info->fprintf_func and info->stream. */ @@ -209,6 +239,7 @@ extern int generic_symbol_at_address (INFO).arch = bfd_arch_unknown, \ (INFO).mach = 0, \ (INFO).endian = BFD_ENDIAN_UNKNOWN, \ + (INFO).octets_per_byte = 1, \ INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) /* Call this macro to initialize only the internal variables for the @@ -217,8 +248,8 @@ extern int generic_symbol_at_address GDB which must initialize these things seperatly. */ #define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \ - (INFO).fprintf_func = (FPRINTF_FUNC), \ - (INFO).stream = (STREAM), \ + (INFO).fprintf_func = (fprintf_ftype)(FPRINTF_FUNC), \ + (INFO).stream = (PTR)(STREAM), \ (INFO).symbols = NULL, \ (INFO).num_symbols = 0, \ (INFO).buffer = NULL, \ @@ -234,4 +265,8 @@ extern int generic_symbol_at_address (INFO).display_endian = BFD_ENDIAN_UNKNOWN, \ (INFO).insn_info_valid = 0 +#ifdef __cplusplus +}; +#endif + #endif /* ! defined (DIS_ASM_H) */ diff --git a/contrib/binutils/include/elf/ChangeLog b/contrib/binutils/include/elf/ChangeLog index aed10aa..e1f68c3 100644 --- a/contrib/binutils/include/elf/ChangeLog +++ b/contrib/binutils/include/elf/ChangeLog @@ -1,3 +1,552 @@ +2000-03-27 Denis Chertykov <denisc@overta.ru> + + * avr.h: New file. AVR ELF support for BFD. + * common.h: Add AVR magic number. + +2000-03-10 Geoffrey Keating <geoffk@cygnus.com> + + * mips.h: Add R_MIPS_GNU_REL_HI16, R_MIPS_GNU_REL_LO16, + R_MIPS_GNU_REL16_S2, R_MIPS_PC64 and R_MIPS_PC32 relocation + numbers. + +2000-02-23 Linas Vepstas <linas@linas.org> + + * i370.h: New file. + +2000-02-22 Nick Clifton <nickc@cygnus.com> + + * common.h (ELF_ST_OTHER): Remove definition. + (ELF32_ST_OTHER): Remove definition. + (ELF64_ST_OTHER): Remove definition. + +2000-02-22 H.J. Lu <hjl@gnu.org> + + * common.h (ELFOSABI_LINUX): Define. + +Thu Feb 17 00:18:33 2000 J"orn Rennecke <amylaar@cygnus.co.uk> + + * sh.h: (EF_SH_MACH_MASK, EF_SH_UNKNOWN, EF_SH1, EF_SH2): New macros. + (EF_SH3, EF_SH_HAS_DSP, EF_SH_DSP, EF_SH3_DSP): Likewise. + (EF_SH_HAS_FP, EF_SH3E, EF_SH4, EF_SH_MERGE_MACH): Likewise. + +2000-02-03 H.J. Lu <hjl@gnu.org> + + * arm-oabi.h: Duplicate changes made to arm.h on Jan. 27, + 2000 by Thomas de Lellis <tdel@windriver.com>. + +2000-01-27 Thomas de Lellis <tdel@windriver.com> + + * arm.h (STT_ARM_TFUNC): Define in terms of STT_LOPROC. + (STT_ARM_16BIT): New flag. Denotes a label that was defined in + Thumb block but was does not identify a function. + +2000-01-20 Nick Clifton <nickc@cygnus.com> + + * common.h (EM_MCORE): Fix spelling of Motorola. + * mcore.h (EM_MCORE): Fix spelling of Motorola. + +2000-01-13 Nick Clifton <nickc@cygnus.com> + + * common.h (EM_S370): Change comment - this is now the IBM + System/370. + (EM_IA_64): Change comment - this is now the IA-64. + +2000-01-11 Nick Clifton <nickc@cygnus.com> + + * common.h (DT_ENCODING): Fix definition of this value. + (DT_LOOS): Fix definition of this value. + (DT_HIOS): Fix definition of this value. + (OLD_DT_LOOS): Value of DT_LOOS before Oct 4, 1999 draft + of ELF spec changed it. + (OLD_DT_HIOS): Value of DT_HIOS before Oct 4, 1999 draft + of ELF spec changed it. + +2000-01-10 Egor Duda <deo@logos-m.ru> + + * common.h (NT_WIN32PSTATUS): Define. (cygwin elf core dumps). + +1999-12-28 Nick Clifton <nickc@cygnus.com> + + * mips.h (STO_*): Redefine in terms of STV_* values now in + common.h. + +1999-12-27 Nick Clifton <nickc@cygnus.com> + + * common.h: Upgrade to match Oct4, 1999 Draft ELF ABI Spec. + (EM_MIPS_RS3_LE): New machine number. + (EM_RCE): New machine number. + (EM_MMA): New machine number. + (EM_PCP): New machine number. + (EM_NCPU): New machine number. + (EM_NDR1): New machine number. + (EM_STARCORE): New machine number. + (EM_ME16): New machine number. + (EM_ST100): New machine number. + (EM_TINYJ): New machine number. + (EM_FX66): New machine number. + (EM_ST9PLUS): New machine number. + (EM_ST7): New machine number. + (EM_68HC16): New machine number. + (EM_68HC11): New machine number. + (EM_68HC08): New machine number. + (EM_68HC05): New machine number. + (EM_SVX): New machine number. + (EM_VAX): New machine number. + (PF_MASKOS): Change value. + (SHT_INIT_ARRAY): New value for sh_type field. + (SHT_FINI_ARRAY): New value for sh_type field. + (SHT_PREINIT_ARRAY): New value for sh_type field. + (SHT_HIUSER): Change value. + (SHF_MERGE): New valye for sh_flags field. + (SHF_STRINGS): New valye for sh_flags field. + (SHF_INFO_LINK): New valye for sh_flags field. + (SHF_OS_NONCONFORMING): New valye for sh_flags field. + (SHF_MASKOS): Change value. + (ELF_ST_VISIBILITY): New macro. + (ELF_ST_OTHER): New macro. + (STT_COMMON): New symbol type. + (STV_DEFAULT): Value for symbol visibility. + (STV_INTERNAL): Value for symbol visibility. + (STV_HIDDEN): Value for symbol visibility. + (STV_PROTECTED): Value for symbol visibility. + (DT_RUNPATH): New dynamic section tag. + (DT_FLAGS): New dynamic section tag. + (DT_ENCODING): New dynamic section tag. + (DT_PREINIT_ARRAY): New dynamic section tag. + (DT_PREINIT_ARRAYSZ): New dynamic section tag. + (DT_LOPROC): New dynamic section tag index. + (DT_HIPROC): New dynamic section tag index. + (DF_ORIGIN): Value for dynamic section flag. + (DF_SYMBOLIC): Value for dynamic section flag. + (DF_TEXTREL): Value for dynamic section flag. + (DF_BIND_NOW): Value for dynamic section flag. + +1999-12-09 Fred Fish <fnf@cygnus.com> + + * i960.h (reloc-macros.h): Include using relative dir elf/. + * i386.h (reloc-macros.h): Include using relative dir elf/. + * hppa.h (reloc-macros.h): Include using relative dir elf/. + +1999-12-07 Jim Blandy <jimb@cygnus.com> + + * common.h (NT_PRXFPREG): New definition. + +Wed Dec 1 03:02:15 1999 Jeffrey A Law (law@cygnus.com) + + * mn10300.h (E_MN10300_MACH_AM33): Define. + +Mon Oct 11 22:42:37 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (PF_HP_PAGE_SIZE): Define. + (PF_HP_FAR_SHARED, PF_HP_NEAR_SHARED, PF_HP_CODE): Likewise. + (PF_HP_MODIFY, PF_HP_LAZYSWAP, PF_HP_SBP): Likewise. + +Mon Oct 4 17:42:38 1999 Doug Evans <devans@canuck.cygnus.com> + + * m32r.h (E_M32RX_ARCH): Define. + +1999-09-15 Ulrich Drepper <drepper@cygnus.com> + + * hppa.h: Add DT_HP_GST_SIZE, DT_HP_GST_VERSION, and DT_HP_GST_HASHVAL. + +1999-09-04 Steve Chamberlain <sac@pobox.com> + + * pj.h: New file. + * common.h (EM_PJ): Define. + +1999-09-02 Ulrich Drepper <drepper@cygnus.com> + + * hppa.h: Add HPUX specific symbol type definitions. + + * hppa.h: Add HPUX specific dynamic and program header table + specific definitions. + +1999-08-31 Scott Bambrough <scottb@netwinder.org> + + * common.h (NT_TASKSTRUCT): Define. + +1999-07-16 Jakub Jelinek <jj@ultra.linux.cz> + + * sparc.h (EF_SPARC_SUN_US3): Define in Cheetah extensions + flag (as per SCD2.4.1). + +1999-07-16 Jakub Jelinek <jj@ultra.linux.cz> + + * sparc.h (ELF64_R_TYPE_DATA): Only use ELF64_R_TYPE bits, not + ELF64_R_SYM bits. + +1999-06-21 Philip Blundell <pb@nexus.co.uk> + + * arm.h (EF_SOFT_FLOAT, F_SOFT_FLOAT): Define. + +1999-07-13 Andreas Schwab <schwab@suse.de> + + * m68k.h (EF_CPU32): Move definition inside multiple inclusion + guard. + +1999-07-08 Richard Henderson <rth@cygnus.com> + + * sparc.h (ELF64_R_TYPE_DATA): Sign extend the value. + (ELF64_R_TYPE_INFO): Mask out all but low 24 bits of data. + (DT_SPARC_PLTFMT): Delete. + Based on a patch from Jakub Jelinek. + +Mon Jun 21 16:36:02 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (elf_hppa_reloc_type): Renamed from elf32_hppa_reloc_type. + +1999-06-10 Jakub Jelinek <jj@ultra.linux.cz> + + * sparc.h (R_SPARC_max_std): Define. + +Wed Jun 9 15:16:34 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h: Update with various changes from newest PA ELF + specifications. + +1999-06-03 Ian Lance Taylor <ian@zembu.com> + + * common.h (EM_PPC64): Define. + +1999-06-02 Stu Grossman <grossman@babylon-5.cygnus.com> + + * dwarf.h: Add LANG_JAVA. + * dwarf2.h: Add DW_LANG_Java. + +1999-05-29 Nick Clifton <nickc@cygnus.com> + + * common.h (ELFOSABI_ARM): Define. + +1999-05-28 Nick Clifton <nickc@cygnus.com> + + * reloc-macros.h: Update comment. + +1999-05-28 Ian Lance Taylor <ian@zembu.com> + + * i960.h: New file. + +1999-05-16 Nick Clifton <nickc@cygnus.com> + + * mcore.h (R_MCORE_COPY): Define. + (R_MCORE_GLOB_DAT): Define. + (R_MCORE_JUMP_SLOT): Define. + +1999-05-15 Nick Clifton <nickc@cygnus.com> + + * mcore.h (R_MCORE_RELATIVE): Define. + +999-05-05 Catherine Moore <clm@cygnus.com> + + * m68k.h (EF_CPU32): Define. + +1999-04-21 Nick Clifton <nickc@cygnus.com> + + * reloc-macros.h (START_RELOC_NUMBERS): Prepend an underscore to + fake reloc entry name (if possible), in order to avoid conflicts + with typedefs of the same name. + +1999-04-16 Gavin Romig-Koch <gavin@cygnus.com> + + * mips.h (EF_MIPS_32BITMODE): New. + +1999-04-08 Nick Clifton <nickc@cygnus.com> + + * mcore.h: New header file. Defines for Motorola's MCore + processor. + +1999-04-08 Nick Clifton <nickc@cygnus.com> + + * common.h: Add new constants defined in: "System V Application + Binary Interface - DRAFT - April 29, 1998" found at the web site: + http://www.sco.com/developer/gabi/contents.html + + (EM_MMA): Removed. Replaced with EM_MCORE as Motorolla own this + value. + +1999-03-31 Nick Clifton <nickc@cygnus.com> + + * reloc-macros.h: Fixed to not generate an enum with a trailing + comma. + +1999-03-16 Gavin Romig-Koch <gavin@cygnus.com> + + * mips.h (E_MIPS_MACH_5000): New. + +1999-03-10 Ulrich Drepper <drepper@cygnus.com> + + * common.h: Add definitions for a few more Solaris ELF extensions. + +Thu Feb 18 18:58:26 1999 Ian Lance Taylor <ian@cygnus.com> + + * external.h: Only use attribute if __GNUC__ is defined. + +1999-02-17 Nick Clifton <nickc@cygnus.com> + + Patch submitted by: Scott Bambrough <scottb@corelcomputer.com> + + * elf/external.h: struct Elf_External_Versym must be packed on + ARM. Code uses sizeof(Elf_External_Versym) and assumes it is + equal to sizeof(char[2]). Reported by Jim Pick <jim@jimpick.com> + +1999-02-02 Nick Clifton <nickc@cygnus.com> + + * dwarf2.h (DWARF2_External_ARange): New structure. + (DWARF2_Internal_ARange): New structure. + +Mon Feb 1 11:33:56 1999 Catherine Moore <clm@cygnus.com> + + * arm.h: Renumber relocs to conform to standard. + (EF_NEW_ABI): Define. + (EF_OLD_ABI): Define. + * arm-oabi.h: New file. + +1999-01-28 Nick Clifton <nickc@cygnus.com> + + * fr30.h: Add R_FR30_GNU_VT{INHERIT,ENTRY} relocs. + +1999-01-27 Nick Clifton <nickc@cygnus.com> + + * dwarf2.h: Add typedefs for structures found in dwarf2 sections. + +1998-12-16 Gavin Romig-Koch <gavin@cygnus.com> + + * mips.h (E_MIPS_MACH_4111): New. + +1998-12-15 Gavin Romig-Koch <gavin@cygnus.com> + + * mips.h (EF_MIPS_ABI,E_MIPS_ABI_O32,E_MIPS_ABI_O64, + E_MIPS_ABI_EABI32,E_MIPS_ABI_EABI64): + +1998-12-03 Nick Clifton <nickc@cygnus.com> + + * fr30.h: Add R_FR30_48 reloc. + +1998-12-02 Ulrich Drepper <drepper@cygnus.com> + + * mips.h: Add external data type for conflict section. + + * mips.h: Add more LL_* options from Irix 6.5. + + * mips.h: Add R_MIPS_JALR and adjust R_MIPS_max appropriately. + +Tue Nov 10 15:12:28 1998 Nick Clifton <nickc@cygnus.com> + + * common.h (EM_CYGNUS_FR30): Reduce to a 16 bit value. + +Tue Nov 10 15:17:28 1998 Catherine Moore <clm@cygnus.com> + + * d10v.h: Add vtable relocs. + +Wed Nov 4 15:56:50 1998 Nick Clifton <nickc@cygnus.com> + + * common.h (EM_CYGNUS_FR30): New machine number. + + * fr30.h: New file: Definitions for the FR30. + +Fri Oct 30 11:54:15 1998 Catherine Moore <clm@cygnus.com> + + From Philip Blundell <pb@nexus.co.uk>: + * arm.h (R_ARM_COPY, et al.): New relocs, used by Linux for PIC. + (EF_ALIGN8): New flag. + +Tue Oct 20 11:19:50 1998 Ian Lance Taylor <ian@cygnus.com> + + * common.h (NT_LWPSTATUS): Close comment accidentally left open. + +Mon Oct 19 20:24:11 1998 Catherine Moore <clm@cygnus.com> + + * sh.h: Add vtable relocs. + +Mon Oct 19 01:44:42 1998 Felix Lee <flee@cygnus.com> + + * common.h (NT_PSTATUS, NT_FPREGS, NT_PSINFO, + NT_LWPSTATUS,NT_LWPSINFO): added. + * internal.h (Elf_Internal_Note): new structure members. + +Fri Oct 16 14:11:25 1998 Catherine Moore <clm@cygnus.com> + + * m32r.h: Add vtable relocs. + +Tue Oct 6 09:22:22 1998 Catherine Moore <clm@cygnus.com> + + * sparc.h: Add vtable relocs. + +Mon Oct 5 09:39:22 1998 Catherine Moore <clm@cygnus.com> + + * v850.h: Add vtable relocs. + +Sun Oct 4 21:17:51 1998 Ian Lance Taylor <ian@cygnus.com> + + * i386.h (R_386_max): Change from 252 to 24. + +Mon Sep 21 12:24:44 1998 Catherine Moore <clm@cygnus.com> + + * i386.h: Change vtable reloc numbers. + +Sun Sep 20 00:54:22 1998 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> + + * m68k.h: Add vtable relocs and R_68K_max. + +Tue Sep 15 09:56:49 CDT 1998 Catherine Moore <clm@cygnus.com> + + * arm.h: Add vtable relocs. + +Mon Aug 31 11:25:27 1998 Catherine Moore <clm@cygnus.com> + + * arm.h: Define STT_ARM_TFUNC. Remove ST_THUMB_xxxx + definitions. + +Sat Aug 29 22:25:51 1998 Richard Henderson <rth@cygnus.com> + + * i386.h: Add vtable relocs. + +1998-08-25 16:42 Ulrich Drepper <drepper@cygnus.com> + + * common.h: Add SYMINFO_* macros to access Elf*_Syminfo information. + + * external.h: Add Elf_External_Syminfo definition. + + * internal.h: Add Elf_Internal_Syminfo, Elf32_Internal_Syminfo, + and Elf64_Syminfo definitions. + +Sun Aug 9 20:26:49 CDT 1998 Catherine Moore <clm@cygnus.com> + + * arm.h: Add ST_THUMB definitions. + +Wed Aug 5 15:52:35 1998 Nick Clifton <nickc@cygnus.com> + + * arm.h: Add ELF header flags to specify compile time optins: + EF_INTERWORK: New flag. + EF_APCS_26: New flag. + EF_APCS_FLOAT: New flag. + EF_PIC: New flag. + +1998-07-31 21:28 Ulrich Drepper <drepper@cygnus.com> + + * mips.h: Add missing RHF_* constants. + +Fri Jul 31 10:01:40 1998 Catherine Moore <clm@cygnus.com> + + * arm.h: Add R_ARM_THM_PC9 relocation. + +1998-07-30 16:25 Ulrich Drepper <drepper@cygnus.com> + + * common.h: Add new DT_* entries and there flag macros from Solaris. + +Tue Jul 28 18:14:07 1998 Stan Cox <scox@equinox.cygnus.com> + + * sparc.h: (R_SPARC_REV32): Added for little endian data e.g. sparc 86x. + +Fri Jul 24 11:22:06 1998 Jeffrey A Law (law@cygnus.com) + + * mn10300.h: Add R_MN10300_24 relocation. + +1998-07-24 Ulrich Drepper <drepper@cygnus.com> + + * mips.h: Add MIPS64 relocation names and values. + +Wed Jul 22 19:29:00 Catherine Moore <clm@cygnus.com> + + * arm.h: Rename relocations. + +1998-07-22 Ulrich Drepper <drepper@cygnus.com> + + * ppc.h: Define enum as elf_ppc_reloc_type. + +Wed Jul 22 16:22:11 1998 Nick Clifton <nickc@cygnus.com> + + * reloc-macros.h: New file. Provides relocation macros: + START_RELOC_NUMBERS, RELOC_NUMBER, FAKE_RELOC, EMPTY_RELOC and + END_RELOC_NUMBERS used by other elf header files. + + * alpha.h: Use reloc-macros.h. + * arc.h: Use reloc-macros.h. + * arm.h: Use reloc-macros.h. + * d10v.h: Use reloc-macros.h. + * d30v.h: Use reloc-macros.h. + * hppa.h: Use reloc-macros.h. + * i386.h: Use reloc-macros.h. + * m32r.h: Use reloc-macros.h. + * m68k.h: Use reloc-macros.h. + * mips.h: Use reloc-macros.h. + * mn10200.h: Use reloc-macros.h. + * mn10300.h: Use reloc-macros.h. + * ppc.h: Use reloc-macros.h. + * sh.h: Use reloc-macros.h. + * sparc.h: Use reloc-macros.h. + * v850.h: Use reloc-macros.h. + +1998-07-22 13:07 Ulrich Drepper <drepper@cygnus.com> + + * mn10300.h: Rewrite relocation definition using macros. + * mips.h: Likewise. + * ppc.h: Likewise. + * alpha.h: Likewise. + * arm.h: Likewise. + * d10v.h: Likewise. + * d30v.h: Likewise. + * m32r.h: Likewise. + * m68k.h: Likewise. + * mn10200.h: Likewise. + * sh.h: Likewise. + * sparc.h: Likewise. + +1998-07-21 13:07 Ulrich Drepper <drepper@cygnus.com> + + * arm.h: New file. + * d10v.h: New file. + * d30v.h: New file. + * i386.h: New file. + * m68k.h: New file. + * mn10200.h: New file. + * sh.h: New file. + + * mips.h: Add R_MIPS_* and SHT_MIPS_* entries. + + * mn10300.h: Add R_MN10300_* entries. + + * ppc.h: Add R_PPC_* entries. + +1998-07-20 07:11 Ulrich Drepper <drepper@cygnus.com> + + * mips.h: Add ODK_*, OEX_*, OPAD_*, OHW_*, and OGP_* constants. + Define Elf32_External_Lib. + +1998-07-19 15:24 Ulrich Drepper <drepper@cygnus.com> + + * mips.h (PT_MIPS_OPTIONS): New symbol. + Add lots of DT_MIPS_* symbols. + +Fri Jun 26 10:46:35 1998 Jeffrey A Law (law@cygnus.com) + + * mn10300.h: New file. + +Thu Jun 18 19:27:56 1998 Nick Clifton <nickc@cygnus.com> + + * common.h (EM_960, EM_V800, EM_FR20, EM_RH32, EM_MMA, + EM_OLD_ALPHA): Add these constants. + +Thu Jun 11 17:59:01 1998 Nick Clifton <nickc@cygnus.com> + + * common.h (EM_486, EM_S370): Add these constants. + +Tue Jun 9 09:35:29 1998 Nick Clifton <nickc@cygnus.com> + + * common.h (EM_ARM): Add this constant. + +Wed May 6 09:45:30 1998 Gavin Koch <gavin@cygnus.com> + + * mips.h (EF_MIPS_MACH,E_MIPS_MACH_*): Added. + +Sat Apr 25 18:35:06 1998 Richard Henderson <rth@cygnus.com> + + * alpha.h (STO_ALPHA_NOPV, STO_ALPHA_STD_GPLOAD): New. + +Wed Apr 15 15:42:45 1998 Richard Henderson <rth@cygnus.com> + + * common.h (EM_SPARC64): Move and rename to EM_OLD_SPARCV9. + (EM_SPARCV9): New. This is the official ABI name and number. + Sat Feb 28 17:04:41 1998 Richard Henderson <rth@cygnus.com> * alpha.h (EF_ALPHA_32BIT, EF_ALPHA_CANRELAX): New. @@ -6,15 +555,15 @@ Mon Dec 15 15:07:49 1997 Nick Clifton <nickc@cygnus.com> * m32r.h (EF_M32R_ARCH, E_M32R_ARCH): New flags to specify machine architecture. - + Fri Dec 5 11:20:08 1997 Nick Clifton <nickc@cygnus.com> * v850.h: New constants: SHN_V850_SCOMMON, SHN_V850_TCOMMON, SHN_V850_ZCOMMON, SHT_V850_SCOMMON, SHT_V850_TCOMMON, SHT_V850_ZCOMMON to handle v850 common sections. enum reloc_type renamed to v850_reloc_type to avoid name - conflict. - + conflict. + Thu Oct 23 13:55:24 1997 Richard Henderson <rth@cygnus.com> * sparc.h (enum elf_sparc_reloc_type): Add UA64 & UA16. @@ -37,6 +586,10 @@ Tue Sep 30 13:26:58 1997 Doug Evans <dje@canuck.cygnus.com> (R_SPARC_{H44,M44,L44,REGISTER}): New relocations. (ELF64_R_TYPE_{DATA,ID,INFO}): New macros. +Wed Sep 17 16:41:42 1997 Nick Clifton <nickc@cygnus.com> + + * v850.h: Add R_V850_CALLT_6_7_OFFSET and R_V850_CALLT_16_16_OFFSET. + Tue Sep 16 14:16:17 1997 Nick Clifton <nickc@cygnus.com> * v850.h (reloc_type): Add R_V850_TDA_16_16_OFFSET. @@ -51,9 +604,14 @@ Wed Sep 3 11:25:57 1997 Nick Clifton <nickc@cygnus.com> Tue Sep 2 17:41:05 1997 Nick Clifton <nickc@cygnus.com> - + * common.h: Remove magic number for V850E. + * common.h: Remove magic number for V850EA. * v850.h: Add new flags for e_flags field in elf header. +Mon Aug 25 16:06:47 1997 Nick Clifton <nickc@cygnus.com> + + * common.h (EM_CYGNUS_V850E): backend magic number for v850e. + * common.h (EM_CYGNUS_V850EA): backend magic number for v850ea. Mon Aug 18 11:05:23 1997 Nick Clifton <nickc@cygnus.com> @@ -95,6 +653,10 @@ Wed Feb 19 15:35:31 1997 Ian Lance Taylor <ian@cygnus.com> * external.h, internal.h, common.h: Added new structures and definitions for ELF versions. +Tue Feb 18 17:40:36 1997 Martin M. Hunt <hunt@pizza.cygnus.com> + + * common.h (EM_CYGNUS_D30V): Define. + Mon Jan 27 11:54:44 1997 Doug Evans <dje@seba.cygnus.com> * m32r.h (enum reloc_type): Add R_M32R_HI16_[SU]LO,R_M32R_LO16. @@ -110,7 +672,7 @@ Fri Jan 3 11:32:51 1997 Michael Meissner <meissner@tiktok.cygnus.com> Thu Jan 2 19:30:23 1997 Michael Meissner <meissner@tiktok.cygnus.com> - * v850.h: New file, provide V850 specific definitions. + * v850.h: New file, provide V850 specific definitions. Tue Dec 31 14:44:32 1996 Ian Lance Taylor <ian@cygnus.com> @@ -156,7 +718,7 @@ Tue Aug 20 14:47:54 1996 J.T. Conklin <jtc@hippo.cygnus.com> Mon Aug 19 10:59:10 1996 Doug Evans <dje@canuck.cygnus.com> * common.h (EM_CYGNUS_M32R): Define. - + Mon Jul 22 18:59:55 1996 Ian Lance Taylor <ian@cygnus.com> * mips.h (SHT_MIPS_IFACE, SHT_MIPS_CONTENT): Define. @@ -170,7 +732,7 @@ Thu Jul 18 19:12:15 1996 Stan Shebs <shebs@andros.cygnus.com> Jul 18 13:20:39 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - * common.h (EM_CYGNUS_D10V): Define. + * common.h (EM_CYGNUS_D10V): Define. * d10v.h: New file. Fri Jun 21 12:33:24 1996 Richard Henderson <rth@tamu.edu> @@ -380,7 +942,7 @@ Fri Apr 3 20:58:58 1992 Mark Eichin (eichin at cygnus.com) * common.h: added ELF_R_{SYM,TYPE,INFO} for handling relocation info added EM_MIPS, and corrected value of EM_860 based on System V ABI - manual. + manual. * external.h: added Elf_External_{Rel,Rela}. diff --git a/contrib/binutils/include/elf/alpha.h b/contrib/binutils/include/elf/alpha.h index 28b9fe3..1ae9d5e 100644 --- a/contrib/binutils/include/elf/alpha.h +++ b/contrib/binutils/include/elf/alpha.h @@ -1,5 +1,5 @@ /* ALPHA ELF support for BFD. - Copyright (C) 1996 Free Software Foundation, Inc. + Copyright (C) 1996, 1998 Free Software Foundation, Inc. By Eric Youngdale, <eric@aib.com>. No processor supplement available for this platform. @@ -58,43 +58,51 @@ typedef struct long ri_gp_value; } Elf64_RegInfo; -/* Alpha relocs. */ +/* Special values for the st_other field in the symbol table. */ + +#define STO_ALPHA_NOPV 0x80 +#define STO_ALPHA_STD_GPLOAD 0x88 -#define R_ALPHA_NONE 0 /* No reloc */ -#define R_ALPHA_REFLONG 1 /* Direct 32 bit */ -#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ -#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ -#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ -#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ -#define R_ALPHA_GPDISP 6 /* Add displacement to GP */ -#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ -#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ -#define R_ALPHA_SREL16 9 /* PC relative 16 bit */ -#define R_ALPHA_SREL32 10 /* PC relative 32 bit */ -#define R_ALPHA_SREL64 11 /* PC relative 64 bit */ +#include "elf/reloc-macros.h" + +/* Alpha relocs. */ +START_RELOC_NUMBERS (elf_alpha_reloc_type) + RELOC_NUMBER (R_ALPHA_NONE, 0) /* No reloc */ + RELOC_NUMBER (R_ALPHA_REFLONG, 1) /* Direct 32 bit */ + RELOC_NUMBER (R_ALPHA_REFQUAD, 2) /* Direct 64 bit */ + RELOC_NUMBER (R_ALPHA_GPREL32, 3) /* GP relative 32 bit */ + RELOC_NUMBER (R_ALPHA_LITERAL, 4) /* GP relative 16 bit w/optimization */ + RELOC_NUMBER (R_ALPHA_LITUSE, 5) /* Optimization hint for LITERAL */ + RELOC_NUMBER (R_ALPHA_GPDISP, 6) /* Add displacement to GP */ + RELOC_NUMBER (R_ALPHA_BRADDR, 7) /* PC+4 relative 23 bit shifted */ + RELOC_NUMBER (R_ALPHA_HINT, 8) /* PC+4 relative 16 bit shifted */ + RELOC_NUMBER (R_ALPHA_SREL16, 9) /* PC relative 16 bit */ + RELOC_NUMBER (R_ALPHA_SREL32, 10) /* PC relative 32 bit */ + RELOC_NUMBER (R_ALPHA_SREL64, 11) /* PC relative 64 bit */ /* Inherited these from ECOFF, but they are not particularly useful and are depreciated. And not implemented in the BFD, btw. */ -#define R_ALPHA_OP_PUSH 12 /* OP stack push */ -#define R_ALPHA_OP_STORE 13 /* OP stack pop and store */ -#define R_ALPHA_OP_PSUB 14 /* OP stack subtract */ -#define R_ALPHA_OP_PRSHIFT 15 /* OP stack right shift */ - -#define R_ALPHA_GPVALUE 16 -#define R_ALPHA_GPRELHIGH 17 -#define R_ALPHA_GPRELLOW 18 -#define R_ALPHA_IMMED_GP_16 19 -#define R_ALPHA_IMMED_GP_HI32 20 -#define R_ALPHA_IMMED_SCN_HI32 21 -#define R_ALPHA_IMMED_BR_HI32 22 -#define R_ALPHA_IMMED_LO32 23 + RELOC_NUMBER (R_ALPHA_OP_PUSH, 12) /* OP stack push */ + RELOC_NUMBER (R_ALPHA_OP_STORE, 13) /* OP stack pop and store */ + RELOC_NUMBER (R_ALPHA_OP_PSUB, 14) /* OP stack subtract */ + RELOC_NUMBER (R_ALPHA_OP_PRSHIFT, 15) /* OP stack right shift */ + + RELOC_NUMBER (R_ALPHA_GPVALUE, 16) + RELOC_NUMBER (R_ALPHA_GPRELHIGH, 17) + RELOC_NUMBER (R_ALPHA_GPRELLOW, 18) + RELOC_NUMBER (R_ALPHA_IMMED_GP_16, 19) + RELOC_NUMBER (R_ALPHA_IMMED_GP_HI32, 20) + RELOC_NUMBER (R_ALPHA_IMMED_SCN_HI32, 21) + RELOC_NUMBER (R_ALPHA_IMMED_BR_HI32, 22) + RELOC_NUMBER (R_ALPHA_IMMED_LO32, 23) /* These relocations are specific to shared libraries. */ -#define R_ALPHA_COPY 24 /* Copy symbol at runtime */ -#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ -#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ -#define R_ALPHA_RELATIVE 27 /* Adjust by program base */ + RELOC_NUMBER (R_ALPHA_COPY, 24) /* Copy symbol at runtime */ + RELOC_NUMBER (R_ALPHA_GLOB_DAT, 25) /* Create GOT entry */ + RELOC_NUMBER (R_ALPHA_JMP_SLOT, 26) /* Create PLT entry */ + RELOC_NUMBER (R_ALPHA_RELATIVE, 27) /* Adjust by program base */ -#define R_ALPHA_max 28 + EMPTY_RELOC (R_ALPHA_max) +END_RELOC_NUMBERS #endif /* _ELF_ALPHA_H */ diff --git a/contrib/binutils/include/elf/arc.h b/contrib/binutils/include/elf/arc.h index 25ba97a..334b55f 100644 --- a/contrib/binutils/include/elf/arc.h +++ b/contrib/binutils/include/elf/arc.h @@ -23,14 +23,16 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef _ELF_ARC_H #define _ELF_ARC_H -enum reloc_type -{ - R_ARC_NONE = 0, - R_ARC_32, - R_ARC_B26, - R_ARC_B22_PCREL, - R_ARC_max -}; +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_arc_reloc_type) + RELOC_NUMBER (R_ARC_NONE, 0) + RELOC_NUMBER (R_ARC_32, 1) + RELOC_NUMBER (R_ARC_B26, 2) + RELOC_NUMBER (R_ARC_B22_PCREL, 3) + EMPTY_RELOC (R_ARC_max) +END_RELOC_NUMBERS /* Processor specific flags for the ELF header e_flags field. */ diff --git a/contrib/binutils/include/elf/arm-oabi.h b/contrib/binutils/include/elf/arm-oabi.h new file mode 100644 index 0000000..da5e731 --- /dev/null +++ b/contrib/binutils/include/elf/arm-oabi.h @@ -0,0 +1,88 @@ +/* ARM ELF support for BFD. + Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_ARM_H +#define _ELF_ARM_H + +#include "elf/reloc-macros.h" + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_ARM_RELEXEC 0x01 +#define EF_ARM_HASENTRY 0x02 +#define EF_INTERWORK 0x04 +#define EF_APCS_26 0x08 +#define EF_APCS_FLOAT 0x10 +#define EF_PIC 0x20 +#define EF_ALIGN8 0x40 /* 8-bit structure alignment is in use. */ +#define EF_NEW_ABI 0x80 +#define EF_OLD_ABI 0x100 + +/* Local aliases for some flags to match names used by COFF port. */ +#define F_INTERWORK EF_INTERWORK +#define F_APCS26 EF_APCS_26 +#define F_APCS_FLOAT EF_APCS_FLOAT +#define F_PIC EF_PIC + +/* Additional symbol types for Thumb. */ +#define STT_ARM_TFUNC STT_LOPROC /* A Thumb function. */ +#define STT_ARM_16BIT STT_HIPROC /* A Thumb label. */ + +/* ARM-specific values for sh_flags. */ +#define SHF_ENTRYSECT 0x10000000 /* Section contains an entry point. */ +#define SHF_COMDEF 0x80000000 /* Section may be multiply defined in the input to a link step. */ + +/* ARM-specific program header flags. */ +#define PF_ARM_SB 0x10000000 /* Segment contains the location addressed by the static base. */ + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_arm_reloc_type) + RELOC_NUMBER (R_ARM_NONE, 0) + RELOC_NUMBER (R_ARM_PC24, 1) + RELOC_NUMBER (R_ARM_ABS32, 2) + RELOC_NUMBER (R_ARM_REL32, 3) + RELOC_NUMBER (R_ARM_ABS8, 4) + RELOC_NUMBER (R_ARM_ABS16, 5) + RELOC_NUMBER (R_ARM_ABS12, 6) + RELOC_NUMBER (R_ARM_THM_ABS5, 7) + RELOC_NUMBER (R_ARM_THM_PC22, 8) + RELOC_NUMBER (R_ARM_SBREL32, 9) + RELOC_NUMBER (R_ARM_AMP_VCALL9, 10) + RELOC_NUMBER (R_ARM_THM_PC11, 11) /* Cygnus extension to abi: Thumb unconditional branch. */ + RELOC_NUMBER (R_ARM_THM_PC9, 12) /* Cygnus extension to abi: Thumb conditional branch. */ + RELOC_NUMBER (R_ARM_GNU_VTINHERIT, 13) + RELOC_NUMBER (R_ARM_GNU_VTENTRY, 14) + RELOC_NUMBER (R_ARM_COPY, 20) /* Copy symbol at runtime. */ + RELOC_NUMBER (R_ARM_GLOB_DAT, 21) /* Create GOT entry. */ + RELOC_NUMBER (R_ARM_JUMP_SLOT, 22) /* Create PLT entry. */ + RELOC_NUMBER (R_ARM_RELATIVE, 23) /* Adjust by program base. */ + RELOC_NUMBER (R_ARM_GOTOFF, 24) /* 32 bit offset to GOT. */ + RELOC_NUMBER (R_ARM_GOTPC, 25) /* 32 bit PC relative offset to GOT. */ + RELOC_NUMBER (R_ARM_GOT32, 26) /* 32 bit GOT entry. */ + RELOC_NUMBER (R_ARM_PLT32, 27) /* 32 bit PLT address. */ + FAKE_RELOC (FIRST_INVALID_RELOC, 28) + FAKE_RELOC (LAST_INVALID_RELOC, 249) + RELOC_NUMBER (R_ARM_RSBREL32, 250) + RELOC_NUMBER (R_ARM_THM_RPC22, 251) + RELOC_NUMBER (R_ARM_RREL32, 252) + RELOC_NUMBER (R_ARM_RABS32, 253) + RELOC_NUMBER (R_ARM_RPC24, 254) + RELOC_NUMBER (R_ARM_RBASE, 255) +END_RELOC_NUMBERS + +#endif diff --git a/contrib/binutils/include/elf/arm.h b/contrib/binutils/include/elf/arm.h new file mode 100644 index 0000000..4d3405d --- /dev/null +++ b/contrib/binutils/include/elf/arm.h @@ -0,0 +1,99 @@ +/* ARM ELF support for BFD. + Copyright (C) 1998, 1999, 2000 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_ARM_H +#define _ELF_ARM_H + +#include "elf/reloc-macros.h" + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_ARM_RELEXEC 0x01 +#define EF_ARM_HASENTRY 0x02 +#define EF_INTERWORK 0x04 +#define EF_APCS_26 0x08 +#define EF_APCS_FLOAT 0x10 +#define EF_PIC 0x20 +#define EF_ALIGN8 0x40 /* 8-bit structure alignment is in use. */ +#define EF_NEW_ABI 0x80 +#define EF_OLD_ABI 0x100 +#define EF_SOFT_FLOAT 0x200 + +/* Local aliases for some flags to match names used by COFF port. */ +#define F_INTERWORK EF_INTERWORK +#define F_APCS26 EF_APCS_26 +#define F_APCS_FLOAT EF_APCS_FLOAT +#define F_PIC EF_PIC +#define F_SOFT_FLOAT EF_SOFT_FLOAT + +/* Additional symbol types for Thumb. */ +#define STT_ARM_TFUNC STT_LOPROC /* A Thumb function. */ +#define STT_ARM_16BIT STT_HIPROC /* A Thumb label. */ + +/* ARM-specific values for sh_flags. */ +#define SHF_ENTRYSECT 0x10000000 /* Section contains an entry point. */ +#define SHF_COMDEF 0x80000000 /* Section may be multiply defined in the input to a link step. */ + +/* ARM-specific program header flags. */ +#define PF_ARM_SB 0x10000000 /* Segment contains the location addressed by the static base. */ + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_arm_reloc_type) + RELOC_NUMBER (R_ARM_NONE, 0) + RELOC_NUMBER (R_ARM_PC24, 1) + RELOC_NUMBER (R_ARM_ABS32, 2) + RELOC_NUMBER (R_ARM_REL32, 3) + RELOC_NUMBER (R_ARM_PC13, 4) + RELOC_NUMBER (R_ARM_ABS16, 5) + RELOC_NUMBER (R_ARM_ABS12, 6) + RELOC_NUMBER (R_ARM_THM_ABS5, 7) + RELOC_NUMBER (R_ARM_ABS8, 8) + RELOC_NUMBER (R_ARM_SBREL32, 9) + RELOC_NUMBER (R_ARM_THM_PC22, 10) + RELOC_NUMBER (R_ARM_THM_PC8, 11) + RELOC_NUMBER (R_ARM_AMP_VCALL9, 12) + RELOC_NUMBER (R_ARM_SWI24, 13) + RELOC_NUMBER (R_ARM_THM_SWI8, 14) + RELOC_NUMBER (R_ARM_XPC25, 15) + RELOC_NUMBER (R_ARM_THM_XPC22, 16) + RELOC_NUMBER (R_ARM_COPY, 20) /* copy symbol at runtime */ + RELOC_NUMBER (R_ARM_GLOB_DAT, 21) /* create GOT entry */ + RELOC_NUMBER (R_ARM_JUMP_SLOT, 22) /* create PLT entry */ + RELOC_NUMBER (R_ARM_RELATIVE, 23) /* adjust by program base */ + RELOC_NUMBER (R_ARM_GOTOFF, 24) /* 32 bit offset to GOT */ + RELOC_NUMBER (R_ARM_GOTPC, 25) /* 32 bit PC relative offset to GOT */ + RELOC_NUMBER (R_ARM_GOT32, 26) /* 32 bit GOT entry */ + RELOC_NUMBER (R_ARM_PLT32, 27) /* 32 bit PLT address */ + FAKE_RELOC (FIRST_INVALID_RELOC1, 28) + FAKE_RELOC (LAST_INVALID_RELOC1, 99) + RELOC_NUMBER (R_ARM_GNU_VTENTRY, 100) + RELOC_NUMBER (R_ARM_GNU_VTINHERIT, 101) + RELOC_NUMBER (R_ARM_THM_PC11, 102) /* Cygnus extension to abi: Thumb unconditional branch */ + RELOC_NUMBER (R_ARM_THM_PC9, 103) /* Cygnus extension to abi: Thumb conditional branch */ + FAKE_RELOC (FIRST_INVALID_RELOC2, 104) + FAKE_RELOC (LAST_INVALID_RELOC2, 248) + RELOC_NUMBER (R_ARM_RXPC25, 249) + RELOC_NUMBER (R_ARM_RSBREL32, 250) + RELOC_NUMBER (R_ARM_THM_RPC22, 251) + RELOC_NUMBER (R_ARM_RREL32, 252) + RELOC_NUMBER (R_ARM_RABS32, 253) + RELOC_NUMBER (R_ARM_RPC24, 254) + RELOC_NUMBER (R_ARM_RBASE, 255) +END_RELOC_NUMBERS + +#endif diff --git a/contrib/binutils/include/elf/common.h b/contrib/binutils/include/elf/common.h index febda9c..fe8c216 100644 --- a/contrib/binutils/include/elf/common.h +++ b/contrib/binutils/include/elf/common.h @@ -60,14 +60,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define EI_OSABI 7 /* Operating System/ABI indication */ #define ELFOSABI_SYSV 0 /* UNIX System V ABI */ #define ELFOSABI_HPUX 1 /* HP-UX operating system */ -#define ELFOSABI_NETBSD 2 /* NetBSD */ #define ELFOSABI_LINUX 3 /* GNU/Linux */ -#define ELFOSABI_HURD 4 /* GNU/Hurd */ -#define ELFOSABI_SOLARIS 6 /* Solaris */ -#define ELFOSABI_MONTEREY 7 /* Monterey */ -#define ELFOSABI_IRIX 8 /* IRIX */ -#define ELFOSABI_FREEBSD 9 /* FreeBSD */ -#define ELFOSABI_TRU64 10 /* TRU64 UNIX */ #define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ #define ELFOSABI_ARM 97 /* ARM */ diff --git a/contrib/binutils/include/elf/dwarf.h b/contrib/binutils/include/elf/dwarf.h index 4333d5e..1e72cd7 100644 --- a/contrib/binutils/include/elf/dwarf.h +++ b/contrib/binutils/include/elf/dwarf.h @@ -3,7 +3,7 @@ Written by Ron Guilmette (rfg@ncd.com) -Copyright (C) 1992 Free Software Foundation, Inc. +Copyright (C) 1992, 1999 Free Software Foundation, Inc. This file is part of GNU CC. @@ -301,7 +301,8 @@ enum dwarf_source_language { /* GNU extensions */ - LANG_CHILL = 0x00009af3 /* random value for GNU Chill */ + LANG_CHILL = 0x00009af3, /* random value for GNU Chill */ + LANG_JAVA = 0x00009af4 /* random value + 1 for GNU Java */ }; #define LANG_lo_user 0x00008000 /* implementation-defined range start */ diff --git a/contrib/binutils/include/elf/dwarf2.h b/contrib/binutils/include/elf/dwarf2.h index f2b2510..1bd4fa6 100644 --- a/contrib/binutils/include/elf/dwarf2.h +++ b/contrib/binutils/include/elf/dwarf2.h @@ -1,6 +1,6 @@ /* Declarations and definitions of codes relating to the DWARF symbolic debugging information format. - Copyright (C) 1992, 1993, 1995, 1996 Free Software Foundation, Inc. + Copyright (C) 1992, 1993, 1995, 1996, 1999 Free Software Foundation, Inc. Written by Gary Funck (gary@intrepid.com) The Ada Joint Program Office (AJPO), Florida State Unviversity and Silicon Graphics Inc. @@ -34,6 +34,92 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * #ifndef _ELF_DWARF2_H #define _ELF_DWARF2_H +/* Structure found in the .debug_line section. */ +typedef struct +{ + unsigned char li_length [4]; + unsigned char li_version [2]; + unsigned char li_prologue_length [4]; + unsigned char li_min_insn_length [1]; + unsigned char li_default_is_stmt [1]; + unsigned char li_line_base [1]; + unsigned char li_line_range [1]; + unsigned char li_opcode_base [1]; +} +DWARF2_External_LineInfo; + +typedef struct +{ + unsigned long li_length; + unsigned short li_version; + unsigned int li_prologue_length; + unsigned char li_min_insn_length; + unsigned char li_default_is_stmt; + int li_line_base; + unsigned char li_line_range; + unsigned char li_opcode_base; +} +DWARF2_Internal_LineInfo; + +/* Structure found in .debug_pubnames section. */ +typedef struct +{ + unsigned char pn_length [4]; + unsigned char pn_version [2]; + unsigned char pn_offset [4]; + unsigned char pn_size [4]; +} +DWARF2_External_PubNames; + +typedef struct +{ + unsigned long pn_length; + unsigned short pn_version; + unsigned long pn_offset; + unsigned long pn_size; +} +DWARF2_Internal_PubNames; + +/* Strcuture found in .debug_info section. */ +typedef struct +{ + unsigned char cu_length [4]; + unsigned char cu_version [2]; + unsigned char cu_abbrev_offset [4]; + unsigned char cu_pointer_size [1]; +} +DWARF2_External_CompUnit; + +typedef struct +{ + unsigned long cu_length; + unsigned short cu_version; + unsigned long cu_abbrev_offset; + unsigned char cu_pointer_size; +} +DWARF2_Internal_CompUnit; + +typedef struct +{ + unsigned char ar_length [4]; + unsigned char ar_version [2]; + unsigned char ar_info_offset [4]; + unsigned char ar_pointer_size [1]; + unsigned char ar_segment_size [1]; +} +DWARF2_External_ARange; + +typedef struct +{ + unsigned long ar_length; + unsigned short ar_version; + unsigned long ar_info_offset; + unsigned char ar_pointer_size; + unsigned char ar_segment_size; +} +DWARF2_Internal_ARange; + + /* Tag names and codes. */ enum dwarf_tag @@ -530,6 +616,7 @@ enum dwarf_source_language DW_LANG_Fortran90 = 0x0008, DW_LANG_Pascal83 = 0x0009, DW_LANG_Modula2 = 0x000a, + DW_LANG_Java = 0x9af4, DW_LANG_Mips_Assembler = 0x8001 }; diff --git a/contrib/binutils/include/elf/external.h b/contrib/binutils/include/elf/external.h index 4399085..5cab77e 100644 --- a/contrib/binutils/include/elf/external.h +++ b/contrib/binutils/include/elf/external.h @@ -1,5 +1,5 @@ /* ELF support for BFD. - Copyright (C) 1991, 92, 93, 95, 1997 Free Software Foundation, Inc. + Copyright (C) 1991, 92, 93, 95, 97, 98, 1999 Free Software Foundation, Inc. Written by Fred Fish @ Cygnus Support, from information published in "UNIX System V Release 4, Programmers Guide: ANSI C and @@ -27,7 +27,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ I.E. it describes the in-file representation of ELF. It requires the elf-common.h file which contains the portions that are common to both the internal and external representations. */ - + /* The 64-bit stuff is kind of random. Perhaps someone will publish a spec someday. */ @@ -240,6 +240,17 @@ typedef struct { typedef struct { unsigned char vs_vers[2]; -} Elf_External_Versym; +} +#ifdef __GNUC__ + __attribute__ ((packed)) +#endif + Elf_External_Versym; + +/* Structure for syminfo section. */ +typedef struct +{ + unsigned char si_boundto[2]; + unsigned char si_flags[2]; +} Elf_External_Syminfo; #endif /* _ELF_EXTERNAL_H */ diff --git a/contrib/binutils/include/elf/i386.h b/contrib/binutils/include/elf/i386.h new file mode 100644 index 0000000..0586661 --- /dev/null +++ b/contrib/binutils/include/elf/i386.h @@ -0,0 +1,49 @@ +/* ix86 ELF support for BFD. + Copyright (C) 1998 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_I386_H +#define _ELF_I386_H + +#include "elf/reloc-macros.h" + +START_RELOC_NUMBERS (elf_i386_reloc_type) + RELOC_NUMBER (R_386_NONE, 0) /* No reloc */ + RELOC_NUMBER (R_386_32, 1) /* Direct 32 bit */ + RELOC_NUMBER (R_386_PC32, 2) /* PC relative 32 bit */ + RELOC_NUMBER (R_386_GOT32, 3) /* 32 bit GOT entry */ + RELOC_NUMBER (R_386_PLT32, 4) /* 32 bit PLT address */ + RELOC_NUMBER (R_386_COPY, 5) /* Copy symbol at runtime */ + RELOC_NUMBER (R_386_GLOB_DAT, 6) /* Create GOT entry */ + RELOC_NUMBER (R_386_JUMP_SLOT, 7) /* Create PLT entry */ + RELOC_NUMBER (R_386_RELATIVE, 8) /* Adjust by program base */ + RELOC_NUMBER (R_386_GOTOFF, 9) /* 32 bit offset to GOT */ + RELOC_NUMBER (R_386_GOTPC, 10) /* 32 bit PC relative offset to GOT */ + FAKE_RELOC (FIRST_INVALID_RELOC, 11) + FAKE_RELOC (LAST_INVALID_RELOC, 19) + RELOC_NUMBER (R_386_16, 20) + RELOC_NUMBER (R_386_PC16, 21) + RELOC_NUMBER (R_386_8, 22) + RELOC_NUMBER (R_386_PC8, 23) + RELOC_NUMBER (R_386_max, 24) + /* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_386_GNU_VTINHERIT, 250) + RELOC_NUMBER (R_386_GNU_VTENTRY, 251) +END_RELOC_NUMBERS + +#endif diff --git a/contrib/binutils/include/elf/internal.h b/contrib/binutils/include/elf/internal.h index 6540310..a9b81a07 100644 --- a/contrib/binutils/include/elf/internal.h +++ b/contrib/binutils/include/elf/internal.h @@ -1,5 +1,5 @@ /* ELF support for BFD. - Copyright (C) 1991, 92, 93, 94, 95, 1997 Free Software Foundation, Inc. + Copyright (C) 1991, 92, 93, 94, 95, 97, 1998 Free Software Foundation, Inc. Written by Fred Fish @ Cygnus Support, from information published in "UNIX System V Release 4, Programmers Guide: ANSI C and @@ -27,7 +27,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ I.E. it describes the in-memory representation of ELF. It requires the elf-common.h file which contains the portions that are common to both the internal and external representations. */ - + /* NOTE that these structures are not kept in the same order as they appear in the object file. In some cases they've been reordered for more optimal @@ -129,7 +129,9 @@ typedef struct elf_internal_note { unsigned long namesz; /* Size of entry's owner string */ unsigned long descsz; /* Size of the note descriptor */ unsigned long type; /* Interpretation of the descriptor */ - char name[1]; /* Start of the name+desc data */ + char * namedata; /* Start of the name+desc data */ + char * descdata; /* Start of the desc data */ + bfd_vma descpos; /* File offset of the descdata */ } Elf_Internal_Note; #define Elf32_Internal_Note Elf_Internal_Note #define elf32_internal_note elf_internal_note @@ -206,7 +208,7 @@ typedef struct elf_internal_verdaux { const char *vda_nodename; /* vda_name as pointer. */ struct elf_internal_verdaux *vda_nextptr; /* vda_next as pointer. */ } Elf_Internal_Verdaux; - + /* This structure appears in a SHT_GNU_verneed section. */ typedef struct elf_internal_verneed { @@ -246,6 +248,14 @@ typedef struct elf_internal_versym { unsigned short vs_vers; } Elf_Internal_Versym; +/* Structure for syminfo section. */ +typedef struct +{ + unsigned short int si_boundto; + unsigned short int si_flags; +} Elf_Internal_Syminfo; + + #define elf32_internal_verdef elf_internal_verdef #define elf64_internal_verdef elf_internal_verdef #define elf32_internal_verdaux elf_internal_verdaux @@ -267,6 +277,8 @@ typedef struct elf_internal_versym { #define Elf64_Internal_Vernaux Elf_Internal_Vernaux #define Elf32_Internal_Versym Elf_Internal_Versym #define Elf64_Internal_Versym Elf_Internal_Versym +#define Elf32_Internal_Syminfo Elf_Internal_Syminfo +#define Elf64_Internal_Syminfo Elf_Internal_Syminfo /* This structure is used to describe how sections should be assigned to program segments. */ diff --git a/contrib/binutils/include/elf/mips.h b/contrib/binutils/include/elf/mips.h index f6efad3..1e2a9f9 100644 --- a/contrib/binutils/include/elf/mips.h +++ b/contrib/binutils/include/elf/mips.h @@ -1,5 +1,5 @@ /* MIPS ELF support for BFD. - Copyright (C) 1993, 1994, 1995, 1996 Free Software Foundation, Inc. + Copyright (C) 1993, 1994, 1995, 1996, 1998 Free Software Foundation, Inc. By Ian Lance Taylor, Cygnus Support, <ian@cygnus.com>, from information in the System V Application Binary Interface, MIPS @@ -27,6 +27,65 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #ifndef _ELF_MIPS_H #define _ELF_MIPS_H +#include "elf/reloc-macros.h" + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_mips_reloc_type) + RELOC_NUMBER (R_MIPS_NONE, 0) + RELOC_NUMBER (R_MIPS_16, 1) + RELOC_NUMBER (R_MIPS_32, 2) + RELOC_NUMBER (R_MIPS_REL32, 3) + RELOC_NUMBER (R_MIPS_26, 4) + RELOC_NUMBER (R_MIPS_HI16, 5) + RELOC_NUMBER (R_MIPS_LO16, 6) + RELOC_NUMBER (R_MIPS_GPREL16, 7) + RELOC_NUMBER (R_MIPS_LITERAL, 8) + RELOC_NUMBER (R_MIPS_GOT16, 9) + RELOC_NUMBER (R_MIPS_PC16, 10) + RELOC_NUMBER (R_MIPS_CALL16, 11) + RELOC_NUMBER (R_MIPS_GPREL32, 12) + /* The remaining relocs are defined on Irix, although they are not + in the MIPS ELF ABI. */ + RELOC_NUMBER (R_MIPS_UNUSED1, 13) + RELOC_NUMBER (R_MIPS_UNUSED2, 14) + RELOC_NUMBER (R_MIPS_UNUSED3, 15) + RELOC_NUMBER (R_MIPS_SHIFT5, 16) + RELOC_NUMBER (R_MIPS_SHIFT6, 17) + RELOC_NUMBER (R_MIPS_64, 18) + RELOC_NUMBER (R_MIPS_GOT_DISP, 19) + RELOC_NUMBER (R_MIPS_GOT_PAGE, 20) + RELOC_NUMBER (R_MIPS_GOT_OFST, 21) + RELOC_NUMBER (R_MIPS_GOT_HI16, 22) + RELOC_NUMBER (R_MIPS_GOT_LO16, 23) + RELOC_NUMBER (R_MIPS_SUB, 24) + RELOC_NUMBER (R_MIPS_INSERT_A, 25) + RELOC_NUMBER (R_MIPS_INSERT_B, 26) + RELOC_NUMBER (R_MIPS_DELETE, 27) + RELOC_NUMBER (R_MIPS_HIGHER, 28) + RELOC_NUMBER (R_MIPS_HIGHEST, 29) + RELOC_NUMBER (R_MIPS_CALL_HI16, 30) + RELOC_NUMBER (R_MIPS_CALL_LO16, 31) + RELOC_NUMBER (R_MIPS_SCN_DISP, 32) + RELOC_NUMBER (R_MIPS_REL16, 33) + RELOC_NUMBER (R_MIPS_ADD_IMMEDIATE, 34) + RELOC_NUMBER (R_MIPS_PJUMP, 35) + RELOC_NUMBER (R_MIPS_RELGOT, 36) + RELOC_NUMBER (R_MIPS_JALR, 37) + RELOC_NUMBER (R_MIPS_max, 38) + /* These relocs are used for the mips16. */ + RELOC_NUMBER (R_MIPS16_26, 100) + RELOC_NUMBER (R_MIPS16_GPREL, 101) + /* These are GNU extensions to handle embedded-pic. */ + RELOC_NUMBER (R_MIPS_PC32, 248) + RELOC_NUMBER (R_MIPS_PC64, 249) + RELOC_NUMBER (R_MIPS_GNU_REL16_S2, 250) + RELOC_NUMBER (R_MIPS_GNU_REL_LO16, 251) + RELOC_NUMBER (R_MIPS_GNU_REL_HI16, 252) + /* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_MIPS_GNU_VTINHERIT, 253) + RELOC_NUMBER (R_MIPS_GNU_VTENTRY, 254) +END_RELOC_NUMBERS + /* Processor specific flags for the ELF header e_flags field. */ /* At least one .noreorder directive appears in the source. */ @@ -42,6 +101,10 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* Code in file uses new ABI (-n32 on Irix 6). */ #define EF_MIPS_ABI2 0x00000020 +/* Indicates code compiled for a 64-bit machine in 32-bit mode. + (regs are 32-bits wide.) */ +#define EF_MIPS_32BITMODE 0x00000100 + /* Four bit MIPS architecture field. */ #define EF_MIPS_ARCH 0xf0000000 @@ -56,6 +119,40 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* -mips4 code. */ #define E_MIPS_ARCH_4 0x30000000 + +/* The ABI of the file. Also see EF_MIPS_ABI2 above. */ +#define EF_MIPS_ABI 0x0000F000 + +/* The original o32 abi. */ +#define E_MIPS_ABI_O32 0x00001000 + +/* O32 extended to work on 64 bit architectures */ +#define E_MIPS_ABI_O64 0x00002000 + +/* EABI in 32 bit mode */ +#define E_MIPS_ABI_EABI32 0x00003000 + +/* EABI in 64 bit mode */ +#define E_MIPS_ABI_EABI64 0x00004000 + + +/* Machine variant if we know it. This field was invented at Cygnus, + but it is hoped that other vendors will adopt it. If some standard + is developed, this code should be changed to follow it. */ + +#define EF_MIPS_MACH 0x00FF0000 + +/* Cygnus is choosing values between 80 and 9F; + 00 - 7F should be left for a future standard; + the rest are open. */ + +#define E_MIPS_MACH_3900 0x00810000 + +#define E_MIPS_MACH_4010 0x00820000 +#define E_MIPS_MACH_4100 0x00830000 +#define E_MIPS_MACH_4650 0x00850000 +#define E_MIPS_MACH_4111 0x00880000 + /* Processor specific section indices. These sections do not actually exist. Symbols with a st_shndx field corresponding to one of these @@ -106,6 +203,15 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* Section contains register usage information. */ #define SHT_MIPS_REGINFO 0x70000006 +/* ??? */ +#define SHT_MIPS_PACKAGE 0x70000007 + +/* ??? */ +#define SHT_MIPS_PACKSYM 0x70000008 + +/* ??? */ +#define SHT_MIPS_RELD 0x70000009 + /* Section contains interface information. */ #define SHT_MIPS_IFACE 0x7000000b @@ -115,15 +221,86 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* Section contains miscellaneous options. */ #define SHT_MIPS_OPTIONS 0x7000000d +/* ??? */ +#define SHT_MIPS_SHDR 0x70000010 + +/* ??? */ +#define SHT_MIPS_FDESC 0x70000011 + +/* ??? */ +#define SHT_MIPS_EXTSYM 0x70000012 + +/* ??? */ +#define SHT_MIPS_DENSE 0x70000013 + +/* ??? */ +#define SHT_MIPS_PDESC 0x70000014 + +/* ??? */ +#define SHT_MIPS_LOCSYM 0x70000015 + +/* ??? */ +#define SHT_MIPS_AUXSYM 0x70000016 + +/* ??? */ +#define SHT_MIPS_OPTSYM 0x70000017 + +/* ??? */ +#define SHT_MIPS_LOCSTR 0x70000018 + +/* ??? */ +#define SHT_MIPS_LINE 0x70000019 + +/* ??? */ +#define SHT_MIPS_RFDESC 0x7000001a + +/* ??? */ +#define SHT_MIPS_DELTASYM 0x7000001b + +/* ??? */ +#define SHT_MIPS_DELTAINST 0x7000001c + +/* ??? */ +#define SHT_MIPS_DELTACLASS 0x7000001d + /* DWARF debugging section. */ #define SHT_MIPS_DWARF 0x7000001e -/* I'm not sure what this is, but it appears on Irix 6. */ +/* ??? */ +#define SHT_MIPS_DELTADECL 0x7000001f + +/* List of libraries the binary depends on. Includes a time stamp, version + number. */ #define SHT_MIPS_SYMBOL_LIB 0x70000020 /* Events section. */ #define SHT_MIPS_EVENTS 0x70000021 +/* ??? */ +#define SHT_MIPS_TRANSLATE 0x70000022 + +/* ??? */ +#define SHT_MIPS_PIXIE 0x70000023 + +/* ??? */ +#define SHT_MIPS_XLATE 0x70000024 + +/* ??? */ +#define SHT_MIPS_XLATE_DEBUG 0x70000025 + +/* ??? */ +#define SHT_MIPS_WHIRL 0x70000026 + +/* ??? */ +#define SHT_MIPS_EH_REGION 0x70000027 + +/* ??? */ +#define SHT_MIPS_XLATE_OLD 0x70000028 + +/* ??? */ +#define SHT_MIPS_PDR_EXCEPTION 0x70000029 + + /* A section of type SHT_MIPS_LIBLIST contains an array of the following structure. The sh_link field is the section index of the string table. The sh_info field is the number of entries in the @@ -142,6 +319,16 @@ typedef struct unsigned long l_flags; } Elf32_Lib; +/* The external version of Elf32_Lib. */ +typedef struct +{ + unsigned char l_name[4]; + unsigned char l_time_stamp[4]; + unsigned char l_checksum[4]; + unsigned char l_version[4]; + unsigned char l_flags[4]; +} Elf32_External_Lib; + /* The l_flags field of an Elf32_Lib structure may contain the following flags. */ @@ -151,9 +338,26 @@ typedef struct /* Ignore version incompatibilities at runtime. */ #define LL_IGNORE_INT_VER 0x00000002 +/* Require matching minor version number. */ +#define LL_REQUIRE_MINOR 0x00000004 + +/* ??? */ +#define LL_EXPORTS 0x00000008 + +/* Delay loading of this library until really needed. */ +#define LL_DELAY_LOAD 0x00000010 + +/* ??? Delta C++ stuff ??? */ +#define LL_DELTA 0x00000020 + + /* A section of type SHT_MIPS_CONFLICT is an array of indices into the .dynsym section. Each element has the following type. */ typedef unsigned long Elf32_Conflict; +typedef unsigned char Elf32_External_Conflict[4]; + +typedef unsigned long Elf64_Conflict; +typedef unsigned char Elf64_External_Conflict[8]; /* A section of type SHT_MIPS_GPTAB contains information about how much GP space would be required for different -G arguments. This @@ -253,6 +457,9 @@ extern void bfd_mips_elf32_swap_reginfo_out /* Runtime procedure table. */ #define PT_MIPS_RTPROC 0x70000001 + +/* Options (for what ???). */ +#define PT_MIPS_OPTIONS 0x70000002 /* Processor specific dynamic array tags. */ @@ -274,6 +481,9 @@ extern void bfd_mips_elf32_swap_reginfo_out /* Base address of the segment. */ #define DT_MIPS_BASE_ADDRESS 0x70000006 +/* ??? */ +#define DT_MIPS_MSYM 0x70000007 + /* Address of .conflict section. */ #define DT_MIPS_CONFLICT 0x70000008 @@ -303,6 +513,84 @@ extern void bfd_mips_elf32_swap_reginfo_out /* Address of run time loader map, used for debugging. */ #define DT_MIPS_RLD_MAP 0x70000016 + +/* Delta C++ class definition. */ +#define DT_MIPS_DELTA_CLASS 0x70000017 + +/* Number of entries in DT_MIPS_DELTA_CLASS. */ +#define DT_MIPS_DELTA_CLASS_NO 0x70000018 + +/* Delta C++ class instances. */ +#define DT_MIPS_DELTA_INSTANCE 0x70000019 + +/* Number of entries in DT_MIPS_DELTA_INSTANCE. */ +#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a + +/* Delta relocations. */ +#define DT_MIPS_DELTA_RELOC 0x7000001b + +/* Number of entries in DT_MIPS_DELTA_RELOC. */ +#define DT_MIPS_DELTA_RELOC_NO 0x7000001c + +/* Delta symbols that Delta relocations refer to. */ +#define DT_MIPS_DELTA_SYM 0x7000001d + +/* Number of entries in DT_MIPS_DELTA_SYM. */ +#define DT_MIPS_DELTA_SYM_NO 0x7000001e + +/* Delta symbols that hold class declarations. */ +#define DT_MIPS_DELTA_CLASSSYM 0x70000020 + +/* Number of entries in DT_MIPS_DELTA_CLASSSYM. */ +#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 + +/* Flags indicating information about C++ flavor. */ +#define DT_MIPS_CXX_FLAGS 0x70000022 + +/* Pixie information (???). */ +#define DT_MIPS_PIXIE_INIT 0x70000023 + +/* ??? */ +#define DT_MIPS_SYMBOL_LIB 0x70000024 + +/* ??? */ +#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 + +/* ??? */ +#define DT_MIPS_LOCAL_GOTIDX 0x70000026 + +/* ??? */ +#define DT_MIPS_HIDDEN_GOTIDX 0x70000027 + +/* ??? */ +#define DT_MIPS_PROTECTED_GOTIDX 0x70000028 + +/* Address of `.MIPS.options'. */ +#define DT_MIPS_OPTIONS 0x70000029 + +/* Address of `.interface'. */ +#define DT_MIPS_INTERFACE 0x7000002a + +/* ??? */ +#define DT_MIPS_DYNSTR_ALIGN 0x7000002b + +/* Size of the .interface section. */ +#define DT_MIPS_INTERFACE_SIZE 0x7000002c + +/* Size of rld_text_resolve function stored in the GOT. */ +#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d + +/* Default suffix of DSO to be added by rld on dlopen() calls. */ +#define DT_MIPS_PERF_SUFFIX 0x7000002e + +/* Size of compact relocation section (O32). */ +#define DT_MIPS_COMPACT_SIZE 0x7000002f + +/* GP value for auxiliary GOTs. */ +#define DT_MIPS_GP_VALUE 0x70000030 + +/* Address of auxiliary .dynamic. */ +#define DT_MIPS_AUX_DYNAMIC 0x70000031 /* Flags which may appear in a DT_MIPS_FLAGS entry. */ @@ -318,14 +606,27 @@ extern void bfd_mips_elf32_swap_reginfo_out /* Ignore LD_LIBRARY_PATH. */ #define RHS_NO_LIBRARY_REPLACEMENT \ 0x00000004 + +#define RHF_NO_MOVE 0x00000008 +#define RHF_SGI_ONLY 0x00000010 +#define RHF_GUARANTEE_INIT 0x00000020 +#define RHF_DELTA_C_PLUS_PLUS 0x00000040 +#define RHF_GUARANTEE_START_INIT 0x00000080 +#define RHF_PIXIE 0x00000100 +#define RHF_DEFAULT_DELAY_LOAD 0x00000200 +#define RHF_REQUICKSTART 0x00000400 +#define RHF_REQUICKSTARTED 0x00000800 +#define RHF_CORD 0x00001000 +#define RHF_NO_UNRES_UNDEF 0x00002000 +#define RHF_RLD_ORDER_SAFE 0x00004000 /* Special values for the st_other field in the symbol table. These are used in an Irix 5 dynamic symbol table. */ -#define STO_DEFAULT 0x00 -#define STO_INTERNAL 0x01 -#define STO_HIDDEN 0x02 -#define STO_PROTECTED 0x03 +#define STO_DEFAULT STV_DEFAULT +#define STO_INTERNAL STV_INTERNAL +#define STO_HIDDEN STV_HIDDEN +#define STO_PROTECTED STV_PROTECTED /* This value is used for a mips16 .text symbol. */ #define STO_MIPS16 0xf0 @@ -472,7 +773,28 @@ extern void bfd_mips_elf_swap_options_out /* Section padding information. */ #define ODK_PAD 3 -/* In the 32 bit ABI, an ODK_REGINFO option is just a Elf32_Reginfo +/* Hardware workarounds performed. */ +#define ODK_HWPATCH 4 + +/* Fill value used by the linker. */ +#define ODK_FILL 5 + +/* Reserved space for desktop tools. */ +#define ODK_TAGS 6 + +/* Hardware workarounds, AND bits when merging. */ +#define ODK_HWAND 7 + +/* Hardware workarounds, OR bits when merging. */ +#define ODK_HWOR 8 + +/* GP group to use for text/data sections. */ +#define ODK_GP_GROUP 9 + +/* ID information. */ +#define ODK_IDENT 10 + +/* In the 32 bit ABI, an ODK_REGINFO option is just a Elf32_RegInfo structure. In the 64 bit ABI, it is the following structure. The info field of the options header is not used. */ @@ -500,10 +822,79 @@ typedef struct bfd_vma ri_gp_value; } Elf64_Internal_RegInfo; +typedef struct +{ + /* The hash value computed from the name of the corresponding + dynamic symbol. */ + unsigned char ms_hash_value[4]; + /* Contains both the dynamic relocation index and the symbol flags + field. The macros ELF32_MS_REL_INDEX and ELF32_MS_FLAGS are used + to access the individual values. The dynamic relocation index + identifies the first entry in the .rel.dyn section that + references the dynamic symbol corresponding to this msym entry. + If the index is 0, no dynamic relocations are associated with the + symbol. The symbol flags field is reserved for future use. */ + unsigned char ms_info[4]; +} Elf32_External_Msym; + +typedef struct +{ + /* The hash value computed from the name of the corresponding + dynamic symbol. */ + unsigned long ms_hash_value; + /* Contains both the dynamic relocation index and the symbol flags + field. The macros ELF32_MS_REL_INDEX and ELF32_MS_FLAGS are used + to access the individual values. The dynamic relocation index + identifies the first entry in the .rel.dyn section that + references the dynamic symbol corresponding to this msym entry. + If the index is 0, no dynamic relocations are associated with the + symbol. The symbol flags field is reserved for future use. */ + unsigned long ms_info; +} Elf32_Internal_Msym; + +#define ELF32_MS_REL_INDEX(i) ((i) >> 8) +#define ELF32_MS_FLAGS(i) (i) & 0xff) +#define ELF32_MS_INFO(r, f) (((r) << 8) + ((f) & 0xff)) + /* MIPS ELF reginfo swapping routines. */ extern void bfd_mips_elf64_swap_reginfo_in PARAMS ((bfd *, const Elf64_External_RegInfo *, Elf64_Internal_RegInfo *)); extern void bfd_mips_elf64_swap_reginfo_out PARAMS ((bfd *, const Elf64_Internal_RegInfo *, Elf64_External_RegInfo *)); +/* Masks for the info work of an ODK_EXCEPTIONS descriptor. */ +#define OEX_FPU_MIN 0x1f /* FPEs which must be enabled. */ +#define OEX_FPU_MAX 0x1f00 /* FPEs which may be enabled. */ +#define OEX_PAGE0 0x10000 /* Page zero must be mapped. */ +#define OEX_SMM 0x20000 /* Force sequential memory mode. */ +#define OEX_FPDBUG 0x40000 /* Force floating-point debug mode. */ +#define OEX_DISMISS 0x80000 /* Dismiss invalid address faults. */ + +/* Masks of the FP exceptions for OEX_FPU_MIN and OEX_FPU_MAX. */ +#define OEX_FPU_INVAL 0x10 /* Invalid operation exception. */ +#define OEX_FPU_DIV0 0x08 /* Division by zero exception. */ +#define OEX_FPU_OFLO 0x04 /* Overflow exception. */ +#define OEX_FPU_UFLO 0x02 /* Underflow exception. */ +#define OEX_FPU_INEX 0x01 /* Inexact exception. */ + +/* Masks for the info word of an ODK_PAD descriptor. */ +#define OPAD_PREFIX 0x01 +#define OPAD_POSTFIX 0x02 +#define OPAD_SYMBOL 0x04 + +/* Masks for the info word of an ODK_HWPATCH descriptor. */ +#define OHW_R4KEOP 0x01 /* R4000 end-of-page patch. */ +#define OHW_R8KPFETCH 0x02 /* May need R8000 prefetch patch. */ +#define OHW_R5KEOP 0x04 /* R5000 end-of-page patch. */ +#define OHW_R5KCVTL 0x08 /* R5000 cvt.[ds].l bug (clean == 1). */ + +/* Masks for the info word of an ODK_IDENT/ODK_GP_GROUP descriptor. */ +#define OGP_GROUP 0x0000ffff /* GP group number. */ +#define OGP_SELF 0xffff0000 /* Self-contained GP groups. */ + +/* Masks for the info word of an ODK_HWAND/ODK_HWOR descriptor. */ +#define OHWA0_R4KEOP_CHECKED 0x00000001 +#define OHWA0_R4KEOP_CLEAN 0x00000002 + + #endif /* _ELF_MIPS_H */ diff --git a/contrib/binutils/include/elf/ppc.h b/contrib/binutils/include/elf/ppc.h new file mode 100644 index 0000000..b3116d8 --- /dev/null +++ b/contrib/binutils/include/elf/ppc.h @@ -0,0 +1,127 @@ +/* PPC ELF support for BFD. + Copyright (C) 1995, 1998 Free Software Foundation, Inc. + + By Michael Meissner, Cygnus Support, <meissner@cygnus.com>, from information + in the System V Application Binary Interface, PowerPC Processor Supplement + and the PowerPC Embedded Application Binary Interface (eabi). + +This file is part of BFD, the Binary File Descriptor library. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This file holds definitions specific to the PPC ELF ABI. Note + that most of this is not actually implemented by BFD. */ + +#ifndef _ELF_PPC_H +#define _ELF_PPC_H + +#include "elf/reloc-macros.h" + +/* Relocations. */ +START_RELOC_NUMBERS (elf_ppc_reloc_type) + RELOC_NUMBER (R_PPC_NONE, 0) + RELOC_NUMBER (R_PPC_ADDR32, 1) + RELOC_NUMBER (R_PPC_ADDR24, 2) + RELOC_NUMBER (R_PPC_ADDR16, 3) + RELOC_NUMBER (R_PPC_ADDR16_LO, 4) + RELOC_NUMBER (R_PPC_ADDR16_HI, 5) + RELOC_NUMBER (R_PPC_ADDR16_HA, 6) + RELOC_NUMBER (R_PPC_ADDR14, 7) + RELOC_NUMBER (R_PPC_ADDR14_BRTAKEN, 8) + RELOC_NUMBER (R_PPC_ADDR14_BRNTAKEN, 9) + RELOC_NUMBER (R_PPC_REL24, 10) + RELOC_NUMBER (R_PPC_REL14, 11) + RELOC_NUMBER (R_PPC_REL14_BRTAKEN, 12) + RELOC_NUMBER (R_PPC_REL14_BRNTAKEN, 13) + RELOC_NUMBER (R_PPC_GOT16, 14) + RELOC_NUMBER (R_PPC_GOT16_LO, 15) + RELOC_NUMBER (R_PPC_GOT16_HI, 16) + RELOC_NUMBER (R_PPC_GOT16_HA, 17) + RELOC_NUMBER (R_PPC_PLTREL24, 18) + RELOC_NUMBER (R_PPC_COPY, 19) + RELOC_NUMBER (R_PPC_GLOB_DAT, 20) + RELOC_NUMBER (R_PPC_JMP_SLOT, 21) + RELOC_NUMBER (R_PPC_RELATIVE, 22) + RELOC_NUMBER (R_PPC_LOCAL24PC, 23) + RELOC_NUMBER (R_PPC_UADDR32, 24) + RELOC_NUMBER (R_PPC_UADDR16, 25) + RELOC_NUMBER (R_PPC_REL32, 26) + RELOC_NUMBER (R_PPC_PLT32, 27) + RELOC_NUMBER (R_PPC_PLTREL32, 28) + RELOC_NUMBER (R_PPC_PLT16_LO, 29) + RELOC_NUMBER (R_PPC_PLT16_HI, 30) + RELOC_NUMBER (R_PPC_PLT16_HA, 31) + RELOC_NUMBER (R_PPC_SDAREL16, 32) + RELOC_NUMBER (R_PPC_SECTOFF, 33) + RELOC_NUMBER (R_PPC_SECTOFF_LO, 34) + RELOC_NUMBER (R_PPC_SECTOFF_HI, 35) + RELOC_NUMBER (R_PPC_SECTOFF_HA, 36) + +/* The remaining relocs are from the Embedded ELF ABI, and are not + in the SVR4 ELF ABI. */ + RELOC_NUMBER (R_PPC_EMB_NADDR32, 101) + RELOC_NUMBER (R_PPC_EMB_NADDR16, 102) + RELOC_NUMBER (R_PPC_EMB_NADDR16_LO, 103) + RELOC_NUMBER (R_PPC_EMB_NADDR16_HI, 104) + RELOC_NUMBER (R_PPC_EMB_NADDR16_HA, 105) + RELOC_NUMBER (R_PPC_EMB_SDAI16, 106) + RELOC_NUMBER (R_PPC_EMB_SDA2I16, 107) + RELOC_NUMBER (R_PPC_EMB_SDA2REL, 108) + RELOC_NUMBER (R_PPC_EMB_SDA21, 109) + RELOC_NUMBER (R_PPC_EMB_MRKREF, 110) + RELOC_NUMBER (R_PPC_EMB_RELSEC16, 111) + RELOC_NUMBER (R_PPC_EMB_RELST_LO, 112) + RELOC_NUMBER (R_PPC_EMB_RELST_HI, 113) + RELOC_NUMBER (R_PPC_EMB_RELST_HA, 114) + RELOC_NUMBER (R_PPC_EMB_BIT_FLD, 115) + RELOC_NUMBER (R_PPC_EMB_RELSDA, 116) + + /* These are GNU extensions to enable C++ vtable garbage collection. */ + RELOC_NUMBER (R_PPC_GNU_VTINHERIT, 253) + RELOC_NUMBER (R_PPC_GNU_VTENTRY, 254) + +/* This is a phony reloc to handle any old fashioned TOC16 references + that may still be in object files. */ + RELOC_NUMBER (R_PPC_TOC16, 255) + + EMPTY_RELOC (R_PPC_max) +END_RELOC_NUMBERS + + +/* Processor specific flags for the ELF header e_flags field. */ + +#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ + + /* CYGNUS local bits below */ +#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag */ +#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib flag */ + +/* Processor specific section headers, sh_type field */ + +#define SHT_ORDERED SHT_HIPROC /* Link editor is to sort the \ + entries in this section \ + based on the address \ + specified in the associated \ + symbol table entry. */ + +/* Processor specific section flags, sh_flags field */ + +#define SHF_EXCLUDE 0x80000000 /* Link editor is to exclude \ + this section from executable \ + and shared objects that it \ + builds when those objects \ + are not to be furhter \ + relocated. */ +#endif /* _ELF_PPC_H */ diff --git a/contrib/binutils/include/elf/reloc-macros.h b/contrib/binutils/include/elf/reloc-macros.h new file mode 100644 index 0000000..42174ca --- /dev/null +++ b/contrib/binutils/include/elf/reloc-macros.h @@ -0,0 +1,116 @@ +/* Generic relocation support for BFD. + Copyright (C) 1998 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* These macros are used by the various *.h target specific header + files to either generate an enum containing all the known relocations + for that target, or if RELOC_MACROS_GEN_FUNC is defined, a recognition + function is generated instead. (This is used by binutils/readelf.c) + + Given a header file like this: + + START_RELOC_NUMBERS (foo) + RELOC_NUMBER (R_foo_NONE, 0) + RELOC_NUMBER (R_foo_32, 1) + FAKE_RELOC (R_foo_illegal, 2) + EMPTY_RELOC (R_foo_max) + END_RELOC_NUMBERS + + Then the following will be produced by default (ie if + RELOC_MACROS_GEN_FUNC is *not* defined). + + enum foo + { + foo = -1, + R_foo_NONE = 0, + R_foo_32 = 1, + R_foo_illegal = 2, + R_foo_max + }; + + If RELOC_MACROS_GEN_FUNC *is* defined, then instead the + following function will be generated: + + static const char * foo PARAMS ((unsigned long rtype)); + static const char * + foo (rtype) + unsigned long rtype; + { + switch (rtype) + { + case 0: return "R_foo_NONE"; + case 1: return "R_foo_32"; + default: return NULL; + } + } + */ + +#ifndef _RELOC_MACROS_H +#define _RELOC_MACROS_H + +#ifdef RELOC_MACROS_GEN_FUNC + +/* This function takes the relocation number and returns the + string version name of the name of that relocation. If + the relocation is not recognised, NULL is returned. */ + +#define START_RELOC_NUMBERS(name) \ +static const char * name PARAMS ((unsigned long rtype)); \ +static const char * \ +name (rtype) \ + unsigned long rtype; \ +{ \ + switch (rtype) \ + { + +#ifdef __STDC__ +#define RELOC_NUMBER(name, number) case number : return #name ; +#else +#define RELOC_NUMBER(name, number) case number : return "name" ; +#endif + +#define FAKE_RELOC(name, number) +#define EMPTY_RELOC(name) + +#define END_RELOC_NUMBERS \ + default: return NULL; \ + } \ +} + + +#else /* Default to generating enum. */ + +/* Some compilers cannot cope with an enum that ends with a trailing + comma, so START_RELOC_NUMBERS creates a fake reloc entry, (initialised + to -1 so that the first real entry will still default to 0). Further + entries then prepend a comma to their definitions, creating a list + of enumerator entries that will satisfy these compilers. */ +#ifdef __STDC__ +#define START_RELOC_NUMBERS(name) enum name { _##name = -1 +#else +#define START_RELOC_NUMBERS(name) enum name { name = -1 +#endif + +#define RELOC_NUMBER(name, number) , name = number +#define FAKE_RELOC(name, number) , name = number +#define EMPTY_RELOC(name) , name +#define END_RELOC_NUMBERS }; + +#endif + +#endif /* RELOC_MACROS_H */ diff --git a/contrib/binutils/include/elf/sh.h b/contrib/binutils/include/elf/sh.h new file mode 100644 index 0000000..faee509 --- /dev/null +++ b/contrib/binutils/include/elf/sh.h @@ -0,0 +1,82 @@ +/* SH ELF support for BFD. + Copyright (C) 1998 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_SH_H +#define _ELF_SH_H + +/* Processor specific flags for the ELF header e_flags field. */ + +#define EF_SH_MACH_MASK 0x1f +#define EF_SH_UNKNOWN 0 /* For backwards compatibility. */ +#define EF_SH1 1 +#define EF_SH2 2 +#define EF_SH3 3 +#define EF_SH_HAS_DSP(flags) ((flags) & 4) +#define EF_SH_DSP 4 +#define EF_SH3_DSP 5 +#define EF_SH_HAS_FP(flags) ((flags) & 8) +#define EF_SH3E 8 +#define EF_SH4 9 + +#define EF_SH_MERGE_MACH(mach1, mach2) \ + (((((mach1) == EF_SH3 || (mach1) == EF_SH_UNKNOWN) && (mach2) == EF_SH_DSP) \ + || ((mach1) == EF_SH_DSP \ + && ((mach2) == EF_SH3 || (mach2) == EF_SH_UNKNOWN))) \ + ? EF_SH3_DSP \ + : (((mach1) < EF_SH3 && (mach2) == EF_SH_UNKNOWN) \ + || ((mach2) < EF_SH3 && (mach1) == EF_SH_UNKNOWN)) \ + ? EF_SH3 \ + : (((mach1) == EF_SH3E && (mach2) == EF_SH_UNKNOWN) \ + || ((mach2) == EF_SH3E && (mach1) == EF_SH_UNKNOWN)) \ + ? EF_SH4 \ + : ((mach1) > (mach2) ? (mach1) : (mach2))) + +#include "elf/reloc-macros.h" + +/* Relocations. */ +/* Relocations 25ff are GNU extensions. + 25..33 are used for relaxation and use the same constants as COFF uses. */ +START_RELOC_NUMBERS (elf_sh_reloc_type) + RELOC_NUMBER (R_SH_NONE, 0) + RELOC_NUMBER (R_SH_DIR32, 1) + RELOC_NUMBER (R_SH_REL32, 2) + RELOC_NUMBER (R_SH_DIR8WPN, 3) + RELOC_NUMBER (R_SH_IND12W, 4) + RELOC_NUMBER (R_SH_DIR8WPL, 5) + RELOC_NUMBER (R_SH_DIR8WPZ, 6) + RELOC_NUMBER (R_SH_DIR8BP, 7) + RELOC_NUMBER (R_SH_DIR8W, 8) + RELOC_NUMBER (R_SH_DIR8L, 9) + FAKE_RELOC (R_SH_FIRST_INVALID_RELOC, 10) + FAKE_RELOC (R_SH_LAST_INVALID_RELOC, 24) + RELOC_NUMBER (R_SH_SWITCH16, 25) + RELOC_NUMBER (R_SH_SWITCH32, 26) + RELOC_NUMBER (R_SH_USES, 27) + RELOC_NUMBER (R_SH_COUNT, 28) + RELOC_NUMBER (R_SH_ALIGN, 29) + RELOC_NUMBER (R_SH_CODE, 30) + RELOC_NUMBER (R_SH_DATA, 31) + RELOC_NUMBER (R_SH_LABEL, 32) + RELOC_NUMBER (R_SH_SWITCH8, 33) + RELOC_NUMBER (R_SH_GNU_VTINHERIT, 34) + RELOC_NUMBER (R_SH_GNU_VTENTRY, 35) + EMPTY_RELOC (R_SH_max) +END_RELOC_NUMBERS + +#endif diff --git a/contrib/binutils/include/elf/sparc.h b/contrib/binutils/include/elf/sparc.h index d9aed21..390e4a8 100644 --- a/contrib/binutils/include/elf/sparc.h +++ b/contrib/binutils/include/elf/sparc.h @@ -1,5 +1,5 @@ /* SPARC ELF support for BFD. - Copyright (C) 1996, 1997 Free Software Foundation, Inc. + Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. By Doug Evans, Cygnus Support, <dje@cygnus.com>. This file is part of BFD, the Binary File Descriptor library. @@ -29,6 +29,9 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */ #define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */ #define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */ +#define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */ + +#define EF_SPARC_LEDATA 0x800000 /* little endian data */ /* This name is used in the V9 ABI. */ #define EF_SPARC_EXT_MASK 0xffff00 /* reserved for vendor extensions */ @@ -53,65 +56,98 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define STT_REGISTER 13 /* global reg reserved to app. */ -/* Relocation types. */ +#include "elf/reloc-macros.h" -enum elf_sparc_reloc_type { - R_SPARC_NONE = 0, - R_SPARC_8, R_SPARC_16, R_SPARC_32, - R_SPARC_DISP8, R_SPARC_DISP16, R_SPARC_DISP32, - R_SPARC_WDISP30, R_SPARC_WDISP22, - R_SPARC_HI22, R_SPARC_22, - R_SPARC_13, R_SPARC_LO10, - R_SPARC_GOT10, R_SPARC_GOT13, R_SPARC_GOT22, - R_SPARC_PC10, R_SPARC_PC22, - R_SPARC_WPLT30, - R_SPARC_COPY, - R_SPARC_GLOB_DAT, R_SPARC_JMP_SLOT, - R_SPARC_RELATIVE, - R_SPARC_UA32, - - /* ??? These 6 relocs are new but not currently used. For binary - compatility in the sparc64-elf toolchain, we leave them out. - A non-binary upward compatible change is expected for sparc64-elf. */ +/* Relocation types. */ +START_RELOC_NUMBERS (elf_sparc_reloc_type) + RELOC_NUMBER (R_SPARC_NONE, 0) + RELOC_NUMBER (R_SPARC_8, 1) + RELOC_NUMBER (R_SPARC_16, 2) + RELOC_NUMBER (R_SPARC_32, 3) + RELOC_NUMBER (R_SPARC_DISP8, 4) + RELOC_NUMBER (R_SPARC_DISP16, 5) + RELOC_NUMBER (R_SPARC_DISP32, 6) + RELOC_NUMBER (R_SPARC_WDISP30, 7) + RELOC_NUMBER (R_SPARC_WDISP22, 8) + RELOC_NUMBER (R_SPARC_HI22, 9) + RELOC_NUMBER (R_SPARC_22, 10) + RELOC_NUMBER (R_SPARC_13, 11) + RELOC_NUMBER (R_SPARC_LO10, 12) + RELOC_NUMBER (R_SPARC_GOT10, 13) + RELOC_NUMBER (R_SPARC_GOT13, 14) + RELOC_NUMBER (R_SPARC_GOT22, 15) + RELOC_NUMBER (R_SPARC_PC10, 16) + RELOC_NUMBER (R_SPARC_PC22, 17) + RELOC_NUMBER (R_SPARC_WPLT30, 18) + RELOC_NUMBER (R_SPARC_COPY, 19) + RELOC_NUMBER (R_SPARC_GLOB_DAT, 20) + RELOC_NUMBER (R_SPARC_JMP_SLOT, 21) + RELOC_NUMBER (R_SPARC_RELATIVE, 22) + RELOC_NUMBER (R_SPARC_UA32, 23) + + /* ??? These 6 relocs are new but not currently used. For binary + compatility in the sparc64-elf toolchain, we leave them out. + A non-binary upward compatible change is expected for sparc64-elf. */ #ifndef SPARC64_OLD_RELOCS - /* ??? New relocs on the UltraSPARC. Not sure what they're for yet. */ - R_SPARC_PLT32, R_SPARC_HIPLT22, R_SPARC_LOPLT10, - R_SPARC_PCPLT32, R_SPARC_PCPLT22, R_SPARC_PCPLT10, + /* ??? New relocs on the UltraSPARC. Not sure what they're for yet. */ + RELOC_NUMBER (R_SPARC_PLT32, 24) + RELOC_NUMBER (R_SPARC_HIPLT22, 25) + RELOC_NUMBER (R_SPARC_LOPLT10, 26) + RELOC_NUMBER (R_SPARC_PCPLT32, 27) + RELOC_NUMBER (R_SPARC_PCPLT22, 28) + RELOC_NUMBER (R_SPARC_PCPLT10, 29) #endif - /* v9 relocs */ - R_SPARC_10, R_SPARC_11, R_SPARC_64, - R_SPARC_OLO10, R_SPARC_HH22, R_SPARC_HM10, R_SPARC_LM22, - R_SPARC_PC_HH22, R_SPARC_PC_HM10, R_SPARC_PC_LM22, - R_SPARC_WDISP16, R_SPARC_WDISP19, - R_SPARC_UNUSED_42, - R_SPARC_7, R_SPARC_5, R_SPARC_6, - R_SPARC_DISP64, R_SPARC_PLT64, - R_SPARC_HIX22, R_SPARC_LOX10, - R_SPARC_H44, R_SPARC_M44, R_SPARC_L44, - R_SPARC_REGISTER, - R_SPARC_UA64, R_SPARC_UA16, - - R_SPARC_max -}; + /* v9 relocs */ + RELOC_NUMBER (R_SPARC_10, 30) + RELOC_NUMBER (R_SPARC_11, 31) + RELOC_NUMBER (R_SPARC_64, 32) + RELOC_NUMBER (R_SPARC_OLO10, 33) + RELOC_NUMBER (R_SPARC_HH22, 34) + RELOC_NUMBER (R_SPARC_HM10, 35) + RELOC_NUMBER (R_SPARC_LM22, 36) + RELOC_NUMBER (R_SPARC_PC_HH22, 37) + RELOC_NUMBER (R_SPARC_PC_HM10, 38) + RELOC_NUMBER (R_SPARC_PC_LM22, 39) + RELOC_NUMBER (R_SPARC_WDISP16, 40) + RELOC_NUMBER (R_SPARC_WDISP19, 41) + RELOC_NUMBER (R_SPARC_UNUSED_42, 42) + RELOC_NUMBER (R_SPARC_7, 43) + RELOC_NUMBER (R_SPARC_5, 44) + RELOC_NUMBER (R_SPARC_6, 45) + RELOC_NUMBER (R_SPARC_DISP64, 46) + RELOC_NUMBER (R_SPARC_PLT64, 47) + RELOC_NUMBER (R_SPARC_HIX22, 48) + RELOC_NUMBER (R_SPARC_LOX10, 49) + RELOC_NUMBER (R_SPARC_H44, 50) + RELOC_NUMBER (R_SPARC_M44, 51) + RELOC_NUMBER (R_SPARC_L44, 52) + RELOC_NUMBER (R_SPARC_REGISTER, 53) + RELOC_NUMBER (R_SPARC_UA64, 54) + RELOC_NUMBER (R_SPARC_UA16, 55) + + /* little endian data relocs */ + RELOC_NUMBER (R_SPARC_REV32, 56) + + EMPTY_RELOC (R_SPARC_max_std) + + RELOC_NUMBER (R_SPARC_GNU_VTINHERIT, 250) + RELOC_NUMBER (R_SPARC_GNU_VTENTRY, 251) + + EMPTY_RELOC (R_SPARC_max) +END_RELOC_NUMBERS /* Relocation macros. */ -#define ELF64_R_TYPE_DATA(info) (((bfd_vma) (info) << 32) >> 40) -#define ELF64_R_TYPE_ID(info) (((bfd_vma) (info) << 56) >> 56) -#define ELF64_R_TYPE_INFO(data, type) (((bfd_vma) (data) << 8) \ - + (bfd_vma) (type)) +#define ELF64_R_TYPE_DATA(info) \ + (((bfd_signed_vma)(ELF64_R_TYPE(info) >> 8) ^ 0x800000) - 0x800000) +#define ELF64_R_TYPE_ID(info) \ + ((info) & 0xff) +#define ELF64_R_TYPE_INFO(data, type) \ + (((bfd_vma) ((data) & 0xffffff) << 8) | (bfd_vma) (type)) -#define DT_SPARC_REGISTER 0x70000001 - -/* - * FIXME: NOT ABI -- GET RID OF THIS - * Defines the format used by the .plt. Currently defined values are - * 0 -- reserved to SI - * 1 -- absolute address in .got.plt - * 2 -- got-relative address in .got.plt - */ +/* Values for Elf64_Dyn.d_tag. */ -#define DT_SPARC_PLTFMT 0x70000001 +#define DT_SPARC_REGISTER 0x70000001 #endif /* _ELF_SPARC_H */ diff --git a/contrib/binutils/include/elf/v850.h b/contrib/binutils/include/elf/v850.h index cc815c5..d443b7f 100644 --- a/contrib/binutils/include/elf/v850.h +++ b/contrib/binutils/include/elf/v850.h @@ -32,6 +32,11 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* v850 code. */ #define E_V850_ARCH 0x00000000 +/* v850e code. */ +#define E_V850E_ARCH 0x10000000 + +/* v850ea code. */ +#define E_V850EA_ARCH 0x20000000 /* Flags for the st_other field */ @@ -42,27 +47,39 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define V850_OTHER_ERROR 0x80 /* symbol had an error reported */ /* V850 relocations */ -enum v850_reloc_type -{ - R_V850_NONE = 0, - R_V850_9_PCREL, - R_V850_22_PCREL, - R_V850_HI16_S, - R_V850_HI16, - R_V850_LO16, - R_V850_32, - R_V850_16, - R_V850_8, - R_V850_SDA_16_16_OFFSET, /* For ld.b, st.b, set1, clr1, not1, tst1, movea, movhi */ - R_V850_SDA_15_16_OFFSET, /* For ld.w, ld.h, ld.hu, st.w, st.h */ - R_V850_ZDA_16_16_OFFSET, /* For ld.b, st.b, set1, clr1, not1, tst1, movea, movhi */ - R_V850_ZDA_15_16_OFFSET, /* For ld.w, ld.h, ld.hu, st.w, st.h */ - R_V850_TDA_6_8_OFFSET, /* For sst.w, sld.w */ - R_V850_TDA_7_8_OFFSET, /* For sst.h, sld.h */ - R_V850_TDA_7_7_OFFSET, /* For sst.b, sld.b */ - R_V850_TDA_16_16_OFFSET, /* For set1, clr1, not1, tst1, movea, movhi */ - R_V850_max -}; +#include "elf/reloc-macros.h" + +START_RELOC_NUMBERS (v850_reloc_type) + RELOC_NUMBER (R_V850_NONE, 0) + RELOC_NUMBER (R_V850_9_PCREL, 1) + RELOC_NUMBER (R_V850_22_PCREL, 2) + RELOC_NUMBER (R_V850_HI16_S, 3) + RELOC_NUMBER (R_V850_HI16, 4) + RELOC_NUMBER (R_V850_LO16, 5) + RELOC_NUMBER (R_V850_32, 6) + RELOC_NUMBER (R_V850_16, 7) + RELOC_NUMBER (R_V850_8, 8) + RELOC_NUMBER( R_V850_SDA_16_16_OFFSET, 9) /* For ld.b, st.b, set1, clr1, not1, tst1, movea, movhi */ + RELOC_NUMBER( R_V850_SDA_15_16_OFFSET, 10) /* For ld.w, ld.h, ld.hu, st.w, st.h */ + RELOC_NUMBER( R_V850_ZDA_16_16_OFFSET, 11) /* For ld.b, st.b, set1, clr1, not1, tst1, movea, movhi */ + RELOC_NUMBER( R_V850_ZDA_15_16_OFFSET, 12) /* For ld.w, ld.h, ld.hu, st.w, st.h */ + RELOC_NUMBER( R_V850_TDA_6_8_OFFSET, 13) /* For sst.w, sld.w */ + RELOC_NUMBER( R_V850_TDA_7_8_OFFSET, 14) /* For sst.h, sld.h */ + RELOC_NUMBER( R_V850_TDA_7_7_OFFSET, 15) /* For sst.b, sld.b */ + RELOC_NUMBER( R_V850_TDA_16_16_OFFSET, 16) /* For set1, clr1, not1, tst1, movea, movhi */ +/* CYGNUS LOCAL v850e */ + RELOC_NUMBER( R_V850_TDA_4_5_OFFSET, 17) /* For sld.hu */ + RELOC_NUMBER( R_V850_TDA_4_4_OFFSET, 18) /* For sld.bu */ + RELOC_NUMBER( R_V850_SDA_16_16_SPLIT_OFFSET, 19) /* For ld.bu */ + RELOC_NUMBER( R_V850_ZDA_16_16_SPLIT_OFFSET, 20) /* For ld.bu */ + RELOC_NUMBER( R_V850_CALLT_6_7_OFFSET, 21) /* For callt */ + RELOC_NUMBER( R_V850_CALLT_16_16_OFFSET, 22) /* For callt */ +/* END CYGNUS LOCAL */ + RELOC_NUMBER (R_V850_GNU_VTINHERIT, 23) + RELOC_NUMBER (R_V850_GNU_VTENTRY, 24) + + EMPTY_RELOC (R_V850_max) +END_RELOC_NUMBERS /* Processor specific section indices. These sections do not actually diff --git a/contrib/binutils/include/fnmatch.h b/contrib/binutils/include/fnmatch.h index 1a653ab..d5eb700 100644 --- a/contrib/binutils/include/fnmatch.h +++ b/contrib/binutils/include/fnmatch.h @@ -15,7 +15,8 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software -Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ +Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ #ifndef _FNMATCH_H diff --git a/contrib/binutils/include/getopt.h b/contrib/binutils/include/getopt.h index c4adc30..fb30719 100644 --- a/contrib/binutils/include/getopt.h +++ b/contrib/binutils/include/getopt.h @@ -2,7 +2,7 @@ Copyright (C) 1989,90,91,92,93,94,96,97 Free Software Foundation, Inc. NOTE: The canonical source of this file is maintained with the GNU C Library. - Bugs can be reported to bug-glibc@prep.ai.mit.edu. + Bugs can be reported to bug-glibc@gnu.org. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the diff --git a/contrib/binutils/include/hashtab.h b/contrib/binutils/include/hashtab.h new file mode 100644 index 0000000..5fe2393 --- /dev/null +++ b/contrib/binutils/include/hashtab.h @@ -0,0 +1,128 @@ +/* An expandable hash tables datatype. + Copyright (C) 1999 Free Software Foundation, Inc. + Contributed by Vladimir Makarov (vmakarov@cygnus.com). + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, write to the Free Software +Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* This package implements basic hash table functionality. It is possible + to search for an entry, create an entry and destroy an entry. + + Elements in the table are generic pointers. + + The size of the table is not fixed; if the occupancy of the table + grows too high the hash table will be expanded. + + The abstract data implementation is based on generalized Algorithm D + from Knuth's book "The art of computer programming". Hash table is + expanded by creation of new hash table and transferring elements from + the old table to the new table. */ + +#ifndef __HASHTAB_H__ +#define __HASHTAB_H__ + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include <ansidecl.h> + +/* Callback function pointer types. */ + +/* Calculate hash of a table entry. */ +typedef unsigned int (*htab_hash) PARAMS ((const void *)); + +/* Compare a table entry with a possible entry. The entry already in + the table always comes first, so the second element can be of a + different type (but in this case htab_find and htab_find_slot + cannot be used; instead the variants that accept a hash value + must be used). */ +typedef int (*htab_eq) PARAMS ((const void *, const void *)); + +/* Cleanup function called whenever a live element is removed from + the hash table. */ +typedef void (*htab_del) PARAMS ((void *)); + +/* Function called by htab_traverse for each live element. The first + arg is the slot of the element (which can be passed to htab_clear_slot + if desired), the second arg is the auxiliary pointer handed to + htab_traverse. Return 1 to continue scan, 0 to stop. */ +typedef int (*htab_trav) PARAMS ((void **, void *)); + +/* Hash tables are of the following type. The structure + (implementation) of this type is not needed for using the hash + tables. All work with hash table should be executed only through + functions mentioned below. */ + +struct htab +{ + /* Pointer to hash function. */ + htab_hash hash_f; + + /* Pointer to comparison function. */ + htab_eq eq_f; + + /* Pointer to cleanup function. */ + htab_del del_f; + + /* Table itself. */ + void **entries; + + /* Current size (in entries) of the hash table */ + size_t size; + + /* Current number of elements including also deleted elements */ + size_t n_elements; + + /* Current number of deleted elements in the table */ + size_t n_deleted; + + /* The following member is used for debugging. Its value is number + of all calls of `htab_find_slot' for the hash table. */ + unsigned int searches; + + /* The following member is used for debugging. Its value is number + of collisions fixed for time of work with the hash table. */ + unsigned int collisions; +}; + +typedef struct htab *htab_t; + +/* The prototypes of the package functions. */ + +extern htab_t htab_create PARAMS ((size_t, htab_hash, + htab_eq, htab_del)); +extern void htab_delete PARAMS ((htab_t)); +extern void htab_empty PARAMS ((htab_t)); + +extern void *htab_find PARAMS ((htab_t, const void *)); +extern void **htab_find_slot PARAMS ((htab_t, const void *, int)); +extern void *htab_find_with_hash PARAMS ((htab_t, const void *, + unsigned int)); +extern void **htab_find_slot_with_hash PARAMS ((htab_t, const void *, + unsigned int, int)); +extern void htab_clear_slot PARAMS ((htab_t, void **)); +extern void htab_remove_elt PARAMS ((htab_t, void *)); + +extern void htab_traverse PARAMS ((htab_t, htab_trav, void *)); + +extern size_t htab_size PARAMS ((htab_t)); +extern size_t htab_elements PARAMS ((htab_t)); +extern double htab_collisions PARAMS ((htab_t)); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* __HASHTAB_H */ diff --git a/contrib/binutils/include/libiberty.h b/contrib/binutils/include/libiberty.h index 951e156..9a536a4 100644 --- a/contrib/binutils/include/libiberty.h +++ b/contrib/binutils/include/libiberty.h @@ -19,7 +19,7 @@ extern "C" { /* Build an argument vector from a string. Allocates memory using malloc. Use freeargv to free the vector. */ -extern char **buildargv PARAMS ((char *)); +extern char **buildargv PARAMS ((char *)) ATTRIBUTE_MALLOC; /* Free a vector returned by buildargv. */ @@ -28,7 +28,7 @@ extern void freeargv PARAMS ((char **)); /* Duplicate an argument vector. Allocates memory using malloc. Use freeargv to free the vector. */ -extern char **dupargv PARAMS ((char **)); +extern char **dupargv PARAMS ((char **)) ATTRIBUTE_MALLOC; /* Return the last component of a path name. Note that we can't use a @@ -36,7 +36,7 @@ extern char **dupargv PARAMS ((char **)); across different systems, sometimes as "char *" and sometimes as "const char *" */ -#if defined(__GNU_LIBRARY__ ) || defined (__linux__) +#if defined (__GNU_LIBRARY__ ) || defined (__linux__) || defined (__FreeBSD__) || defined (__OpenBSD__) || defined (__CYGWIN__) || defined (__CYGWIN32__) extern char *basename PARAMS ((const char *)); #else extern char *basename (); @@ -45,19 +45,28 @@ extern char *basename (); /* Concatenate an arbitrary number of strings, up to (char *) NULL. Allocates memory using xmalloc. */ -extern char *concat PARAMS ((const char *, ...)); +extern char *concat PARAMS ((const char *, ...)) ATTRIBUTE_MALLOC; /* Check whether two file descriptors refer to the same file. */ extern int fdmatch PARAMS ((int fd1, int fd2)); +/* Get the working directory. The result is cached, so don't call + chdir() between calls to getpwd(). */ + +extern char * getpwd PARAMS ((void)); + /* Get the amount of time the process has run, in microseconds. */ extern long get_run_time PARAMS ((void)); /* Choose a temporary directory to use for scratch files. */ -extern char *choose_temp_base PARAMS ((void)); +extern char *choose_temp_base PARAMS ((void)) ATTRIBUTE_MALLOC; + +/* Return a temporary file name or NULL if unable to create one. */ + +extern char *make_temp_file PARAMS ((const char *)) ATTRIBUTE_MALLOC; /* Allocate memory filled with spaces. Allocates using malloc. */ @@ -108,12 +117,7 @@ extern int xatexit PARAMS ((void (*fn) (void))); /* Exit, calling all the functions registered with xatexit. */ -#ifndef __GNUC__ -extern void xexit PARAMS ((int status)); -#else -typedef void libiberty_voidfn PARAMS ((int status)); -__volatile__ libiberty_voidfn xexit; -#endif +extern void xexit PARAMS ((int status)) ATTRIBUTE_NORETURN; /* Set the program name used by xmalloc. */ @@ -126,19 +130,29 @@ extern void xmalloc_set_program_name PARAMS ((const char *)); #ifdef ANSI_PROTOTYPES /* Get a definition for size_t. */ #include <stddef.h> +/* Get a definition for va_list. */ +#include <stdarg.h> #endif -extern PTR xmalloc PARAMS ((size_t)); +extern PTR xmalloc PARAMS ((size_t)) ATTRIBUTE_MALLOC; -/* Reallocate memory without fail. This works like xmalloc. +/* Reallocate memory without fail. This works like xmalloc. Note, + realloc type functions are not suitable for attribute malloc since + they may return the same address across multiple calls. */ + +extern PTR xrealloc PARAMS ((PTR, size_t)); - FIXME: We do not declare the parameter types for the same reason as +/* Allocate memory without fail and set it to zero. This works like xmalloc. */ -extern PTR xrealloc PARAMS ((PTR, size_t)); +extern PTR xcalloc PARAMS ((size_t, size_t)) ATTRIBUTE_MALLOC; /* Copy a string into a memory buffer without fail. */ -extern char *xstrdup PARAMS ((const char *)); +extern char *xstrdup PARAMS ((const char *)) ATTRIBUTE_MALLOC; + +/* Copy an existing memory buffer to a new memory buffer without fail. */ + +extern PTR xmemdup PARAMS ((const PTR, size_t, size_t)) ATTRIBUTE_MALLOC; /* hex character manipulation routines */ @@ -168,6 +182,17 @@ extern int pexecute PARAMS ((const char *, char * const *, const char *, extern int pwait PARAMS ((int, int *, int)); +/* Like sprintf but provides a pointer to malloc'd storage, which must + be freed by the caller. */ + +extern int asprintf PARAMS ((char **, const char *, ...)) ATTRIBUTE_PRINTF_2; + +/* Like vsprintf but provides a pointer to malloc'd storage, which + must be freed by the caller. */ + +extern int vasprintf PARAMS ((char **, const char *, va_list)) + ATTRIBUTE_PRINTF(2,0); + #ifdef __cplusplus } #endif diff --git a/contrib/binutils/include/objalloc.h b/contrib/binutils/include/objalloc.h index 24f87f8..0b451cd 100644 --- a/contrib/binutils/include/objalloc.h +++ b/contrib/binutils/include/objalloc.h @@ -14,7 +14,8 @@ GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software -Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ +Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ #ifndef OBJALLOC_H #define OBJALLOC_H diff --git a/contrib/binutils/include/obstack.h b/contrib/binutils/include/obstack.h index ffc6b9e..a20ab55 100644 --- a/contrib/binutils/include/obstack.h +++ b/contrib/binutils/include/obstack.h @@ -1,19 +1,24 @@ /* obstack.h - object stack macros - Copyright (C) 1988,89,90,91,92,93,94,96 Free Software Foundation, Inc. + Copyright (C) 1988,89,90,91,92,93,94,96,97,98 Free Software Foundation, Inc. -This program is free software; you can redistribute it and/or modify it -under the terms of the GNU General Public License as published by the -Free Software Foundation; either version 2, or (at your option) any -later version. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + NOTE: The canonical source of this file is maintained with the GNU C Library. + Bugs can be reported to bug-glibc@gnu.org. -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ + This program is free software; you can redistribute it and/or modify it + under the terms of the GNU General Public License as published by the + Free Software Foundation; either version 2, or (at your option) any + later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, + USA. */ /* Summary: @@ -100,42 +105,55 @@ Summary: /* Don't do the contents of this file more than once. */ -#ifndef __OBSTACK_H__ -#define __OBSTACK_H__ +#ifndef _OBSTACK_H +#define _OBSTACK_H 1 + +#ifdef __cplusplus +extern "C" { +#endif /* We use subtraction of (char *) 0 instead of casting to int because on word-addressable machines a simple cast to int may ignore the byte-within-word field of the pointer. */ #ifndef __PTR_TO_INT -#define __PTR_TO_INT(P) ((P) - (char *) 0) +# define __PTR_TO_INT(P) ((P) - (char *) 0) #endif #ifndef __INT_TO_PTR -#define __INT_TO_PTR(P) ((P) + (char *) 0) +# define __INT_TO_PTR(P) ((P) + (char *) 0) #endif -/* We need the type of the resulting object. In ANSI C it is ptrdiff_t - but in traditional C it is usually long. If we are in ANSI C and - don't already have ptrdiff_t get it. */ - -#if defined (__STDC__) && __STDC__ && ! defined (offsetof) -#if defined (__GNUC__) && defined (IN_GCC) -/* On Next machine, the system's stddef.h screws up if included - after we have defined just ptrdiff_t, so include all of stddef.h. - Otherwise, define just ptrdiff_t, which is all we need. */ -#ifndef __NeXT__ -#define __need_ptrdiff_t -#endif -#endif +/* We need the type of the resulting object. If __PTRDIFF_TYPE__ is + defined, as with GNU C, use that; that way we don't pollute the + namespace with <stddef.h>'s symbols. Otherwise, if <stddef.h> is + available, include it and use ptrdiff_t. In traditional C, long is + the best that we can do. */ -#include <stddef.h> +#ifdef __PTRDIFF_TYPE__ +# define PTR_INT_TYPE __PTRDIFF_TYPE__ +#else +# ifdef HAVE_STDDEF_H +# include <stddef.h> +# define PTR_INT_TYPE ptrdiff_t +# else +# define PTR_INT_TYPE long +# endif #endif -#if defined (__STDC__) && __STDC__ -#define PTR_INT_TYPE ptrdiff_t +#if defined _LIBC || defined HAVE_STRING_H +# include <string.h> +# if defined __STDC__ && __STDC__ +# define _obstack_memcpy(To, From, N) memcpy ((To), (From), (N)) +# else +# define _obstack_memcpy(To, From, N) memcpy ((To), (char *)(From), (N)) +# endif #else -#define PTR_INT_TYPE long +# ifdef memcpy +# define _obstack_memcpy(To, From, N) memcpy ((To), (char *)(From), (N)) +# else +# define _obstack_memcpy(To, From, N) bcopy ((char *)(From), (To), (N)) +# endif #endif struct _obstack_chunk /* Lives at front of each chunk. */ @@ -154,7 +172,7 @@ struct obstack /* control current object in current chunk */ char *chunk_limit; /* address of char after current chunk */ PTR_INT_TYPE temp; /* Temporary for some macros. */ int alignment_mask; /* Mask of alignment for each object. */ -#if defined (__STDC__) && __STDC__ +#if defined __STDC__ && __STDC__ /* These prototypes vary based on `use_extra_arg', and we use casts to the prototypeless function type in all assignments, but having prototypes here quiets -Wstrict-prototypes. */ @@ -171,12 +189,14 @@ struct obstack /* control current object in current chunk */ chunk contains a zero-length object. This prevents freeing the chunk if we allocate a bigger chunk to replace it. */ - unsigned alloc_failed:1; /* chunk alloc func returned 0 */ + unsigned alloc_failed:1; /* No longer used, as we now call the failed + handler on error, but retained for binary + compatibility. */ }; /* Declare the external functions we use; they are in obstack.c. */ -#if defined (__STDC__) && __STDC__ +#if defined __STDC__ && __STDC__ extern void _obstack_newchunk (struct obstack *, int); extern void _obstack_free (struct obstack *, void *); extern int _obstack_begin (struct obstack *, int, int, @@ -184,20 +204,16 @@ extern int _obstack_begin (struct obstack *, int, int, extern int _obstack_begin_1 (struct obstack *, int, int, void *(*) (void *, long), void (*) (void *, void *), void *); -/* CYGNUS LOCAL */ extern int _obstack_memory_used (struct obstack *); -/* END CYGNUS LOCAL */ #else extern void _obstack_newchunk (); extern void _obstack_free (); extern int _obstack_begin (); extern int _obstack_begin_1 (); -/* CYGNUS LOCAL */ extern int _obstack_memory_used (); -/* END CYGNUS LOCAL */ #endif -#if defined (__STDC__) && __STDC__ +#if defined __STDC__ && __STDC__ /* Do the function-declarations after the structs but before defining the macros. */ @@ -225,6 +241,7 @@ void * obstack_finish (struct obstack *obstack); int obstack_object_size (struct obstack *obstack); int obstack_room (struct obstack *obstack); +void obstack_make_room (struct obstack *obstack, int size); void obstack_1grow_fast (struct obstack *obstack, int data_char); void obstack_ptr_grow_fast (struct obstack *obstack, void *data); void obstack_int_grow_fast (struct obstack *obstack, int data); @@ -234,20 +251,30 @@ void * obstack_base (struct obstack *obstack); void * obstack_next_free (struct obstack *obstack); int obstack_alignment_mask (struct obstack *obstack); int obstack_chunk_size (struct obstack *obstack); -/* CYGNUS LOCAL */ int obstack_memory_used (struct obstack *obstack); -/* END CYGNUS LOCAL */ #endif /* __STDC__ */ /* Non-ANSI C cannot really support alternative functions for these macros, so we do not declare them. */ + +/* Error handler called when `obstack_chunk_alloc' failed to allocate + more memory. This can be set to a user defined function. The + default action is to print a message and abort. */ +#if defined __STDC__ && __STDC__ +extern void (*obstack_alloc_failed_handler) (void); +#else +extern void (*obstack_alloc_failed_handler) (); +#endif + +/* Exit value used when `print_and_abort' is used. */ +extern int obstack_exit_failure; /* Pointer to beginning of object being allocated or to be allocated next. Note that this might not be the final address of the object because a new chunk might be needed to hold the final size. */ -#define obstack_base(h) ((h)->alloc_failed ? 0 : (h)->object_base) +#define obstack_base(h) ((h)->object_base) /* Size for allocating ordinary chunks. */ @@ -255,7 +282,7 @@ int obstack_memory_used (struct obstack *obstack); /* Pointer to next byte not yet allocated in current chunk. */ -#define obstack_next_free(h) ((h)->alloc_failed ? 0 : (h)->next_free) +#define obstack_next_free(h) ((h)->next_free) /* Mask specifying low bits that should be clear in address of an object. */ @@ -263,53 +290,53 @@ int obstack_memory_used (struct obstack *obstack); /* To prevent prototype warnings provide complete argument list in standard C version. */ -#if defined (__STDC__) && __STDC__ +#if defined __STDC__ && __STDC__ -#define obstack_init(h) \ +# define obstack_init(h) \ _obstack_begin ((h), 0, 0, \ (void *(*) (long)) obstack_chunk_alloc, (void (*) (void *)) obstack_chunk_free) -#define obstack_begin(h, size) \ +# define obstack_begin(h, size) \ _obstack_begin ((h), (size), 0, \ (void *(*) (long)) obstack_chunk_alloc, (void (*) (void *)) obstack_chunk_free) -#define obstack_specify_allocation(h, size, alignment, chunkfun, freefun) \ +# define obstack_specify_allocation(h, size, alignment, chunkfun, freefun) \ _obstack_begin ((h), (size), (alignment), \ (void *(*) (long)) (chunkfun), (void (*) (void *)) (freefun)) -#define obstack_specify_allocation_with_arg(h, size, alignment, chunkfun, freefun, arg) \ +# define obstack_specify_allocation_with_arg(h, size, alignment, chunkfun, freefun, arg) \ _obstack_begin_1 ((h), (size), (alignment), \ (void *(*) (void *, long)) (chunkfun), \ (void (*) (void *, void *)) (freefun), (arg)) -#define obstack_chunkfun(h, newchunkfun) \ +# define obstack_chunkfun(h, newchunkfun) \ ((h) -> chunkfun = (struct _obstack_chunk *(*)(void *, long)) (newchunkfun)) -#define obstack_freefun(h, newfreefun) \ +# define obstack_freefun(h, newfreefun) \ ((h) -> freefun = (void (*)(void *, struct _obstack_chunk *)) (newfreefun)) #else -#define obstack_init(h) \ +# define obstack_init(h) \ _obstack_begin ((h), 0, 0, \ (void *(*) ()) obstack_chunk_alloc, (void (*) ()) obstack_chunk_free) -#define obstack_begin(h, size) \ +# define obstack_begin(h, size) \ _obstack_begin ((h), (size), 0, \ (void *(*) ()) obstack_chunk_alloc, (void (*) ()) obstack_chunk_free) -#define obstack_specify_allocation(h, size, alignment, chunkfun, freefun) \ +# define obstack_specify_allocation(h, size, alignment, chunkfun, freefun) \ _obstack_begin ((h), (size), (alignment), \ (void *(*) ()) (chunkfun), (void (*) ()) (freefun)) -#define obstack_specify_allocation_with_arg(h, size, alignment, chunkfun, freefun, arg) \ +# define obstack_specify_allocation_with_arg(h, size, alignment, chunkfun, freefun, arg) \ _obstack_begin_1 ((h), (size), (alignment), \ (void *(*) ()) (chunkfun), (void (*) ()) (freefun), (arg)) -#define obstack_chunkfun(h, newchunkfun) \ +# define obstack_chunkfun(h, newchunkfun) \ ((h) -> chunkfun = (struct _obstack_chunk *(*)()) (newchunkfun)) -#define obstack_freefun(h, newfreefun) \ +# define obstack_freefun(h, newfreefun) \ ((h) -> freefun = (void (*)()) (newfreefun)) #endif @@ -318,118 +345,118 @@ int obstack_memory_used (struct obstack *obstack); #define obstack_blank_fast(h,n) ((h)->next_free += (n)) -/* CYGNUS LOCAL */ #define obstack_memory_used(h) _obstack_memory_used (h) -/* END CYGNUS LOCAL */ -#if defined (__GNUC__) && defined (__STDC__) && __STDC__ +#if defined __GNUC__ && defined __STDC__ && __STDC__ /* NextStep 2.0 cc is really gcc 1.93 but it defines __GNUC__ = 2 and does not implement __extension__. But that compiler doesn't define __GNUC_MINOR__. */ -#if __GNUC__ < 2 || (__NeXT__ && !__GNUC_MINOR__) -#define __extension__ -#endif +# if __GNUC__ < 2 || (__NeXT__ && !__GNUC_MINOR__) +# define __extension__ +# endif /* For GNU C, if not -traditional, we can define these macros to compute all args only once without using a global variable. Also, we can avoid using the `temp' slot, to make faster code. */ -#define obstack_object_size(OBSTACK) \ +# define obstack_object_size(OBSTACK) \ __extension__ \ ({ struct obstack *__o = (OBSTACK); \ - __o->alloc_failed ? 0 : \ (unsigned) (__o->next_free - __o->object_base); }) -#define obstack_room(OBSTACK) \ +# define obstack_room(OBSTACK) \ __extension__ \ ({ struct obstack *__o = (OBSTACK); \ (unsigned) (__o->chunk_limit - __o->next_free); }) -#define obstack_grow(OBSTACK,where,length) \ +# define obstack_make_room(OBSTACK,length) \ +__extension__ \ +({ struct obstack *__o = (OBSTACK); \ + int __len = (length); \ + if (__o->chunk_limit - __o->next_free < __len) \ + _obstack_newchunk (__o, __len); \ + (void) 0; }) + +# define obstack_empty_p(OBSTACK) \ + __extension__ \ + ({ struct obstack *__o = (OBSTACK); \ + (__o->chunk->prev == 0 && __o->next_free - __o->chunk->contents == 0); }) + +# define obstack_grow(OBSTACK,where,length) \ __extension__ \ ({ struct obstack *__o = (OBSTACK); \ int __len = (length); \ if (__o->next_free + __len > __o->chunk_limit) \ _obstack_newchunk (__o, __len); \ - if (!__o->alloc_failed) \ - { \ - memcpy (__o->next_free, (char *) (where), __len); \ - __o->next_free += __len; \ - } \ + _obstack_memcpy (__o->next_free, (where), __len); \ + __o->next_free += __len; \ (void) 0; }) -#define obstack_grow0(OBSTACK,where,length) \ +# define obstack_grow0(OBSTACK,where,length) \ __extension__ \ ({ struct obstack *__o = (OBSTACK); \ int __len = (length); \ if (__o->next_free + __len + 1 > __o->chunk_limit) \ _obstack_newchunk (__o, __len + 1); \ - if (!__o->alloc_failed) \ - { \ - memcpy (__o->next_free, (char *) (where), __len); \ - __o->next_free += __len; \ - *(__o->next_free)++ = 0; \ - } \ + _obstack_memcpy (__o->next_free, (where), __len); \ + __o->next_free += __len; \ + *(__o->next_free)++ = 0; \ (void) 0; }) -#define obstack_1grow(OBSTACK,datum) \ +# define obstack_1grow(OBSTACK,datum) \ __extension__ \ ({ struct obstack *__o = (OBSTACK); \ if (__o->next_free + 1 > __o->chunk_limit) \ _obstack_newchunk (__o, 1); \ - if (!__o->alloc_failed) \ - *(__o->next_free)++ = (datum); \ + *(__o->next_free)++ = (datum); \ (void) 0; }) /* These assume that the obstack alignment is good enough for pointers or ints, and that the data added so far to the current object shares that much alignment. */ -#define obstack_ptr_grow(OBSTACK,datum) \ +# define obstack_ptr_grow(OBSTACK,datum) \ __extension__ \ ({ struct obstack *__o = (OBSTACK); \ if (__o->next_free + sizeof (void *) > __o->chunk_limit) \ _obstack_newchunk (__o, sizeof (void *)); \ - if (!__o->alloc_failed) \ - *((void **)__o->next_free)++ = ((void *)datum); \ + *((void **)__o->next_free)++ = ((void *)datum); \ (void) 0; }) -#define obstack_int_grow(OBSTACK,datum) \ +# define obstack_int_grow(OBSTACK,datum) \ __extension__ \ ({ struct obstack *__o = (OBSTACK); \ if (__o->next_free + sizeof (int) > __o->chunk_limit) \ _obstack_newchunk (__o, sizeof (int)); \ - if (!__o->alloc_failed) \ - *((int *)__o->next_free)++ = ((int)datum); \ + *((int *)__o->next_free)++ = ((int)datum); \ (void) 0; }) -#define obstack_ptr_grow_fast(h,aptr) (*((void **) (h)->next_free)++ = (void *)aptr) -#define obstack_int_grow_fast(h,aint) (*((int *) (h)->next_free)++ = (int) aint) +# define obstack_ptr_grow_fast(h,aptr) (*((void **) (h)->next_free)++ = (void *)aptr) +# define obstack_int_grow_fast(h,aint) (*((int *) (h)->next_free)++ = (int) aint) -#define obstack_blank(OBSTACK,length) \ +# define obstack_blank(OBSTACK,length) \ __extension__ \ ({ struct obstack *__o = (OBSTACK); \ int __len = (length); \ if (__o->chunk_limit - __o->next_free < __len) \ _obstack_newchunk (__o, __len); \ - if (!__o->alloc_failed) \ - __o->next_free += __len; \ + __o->next_free += __len; \ (void) 0; }) -#define obstack_alloc(OBSTACK,length) \ +# define obstack_alloc(OBSTACK,length) \ __extension__ \ ({ struct obstack *__h = (OBSTACK); \ obstack_blank (__h, (length)); \ obstack_finish (__h); }) -#define obstack_copy(OBSTACK,where,length) \ +# define obstack_copy(OBSTACK,where,length) \ __extension__ \ ({ struct obstack *__h = (OBSTACK); \ obstack_grow (__h, (where), (length)); \ obstack_finish (__h); }) -#define obstack_copy0(OBSTACK,where,length) \ +# define obstack_copy0(OBSTACK,where,length) \ __extension__ \ ({ struct obstack *__h = (OBSTACK); \ obstack_grow0 (__h, (where), (length)); \ @@ -437,28 +464,23 @@ __extension__ \ /* The local variable is named __o1 to avoid a name conflict when obstack_blank is called. */ -#define obstack_finish(OBSTACK) \ +# define obstack_finish(OBSTACK) \ __extension__ \ ({ struct obstack *__o1 = (OBSTACK); \ void *value; \ - if (__o1->alloc_failed) \ - value = 0; \ - else \ - { \ - value = (void *) __o1->object_base; \ - if (__o1->next_free == value) \ - __o1->maybe_empty_object = 1; \ - __o1->next_free \ - = __INT_TO_PTR ((__PTR_TO_INT (__o1->next_free)+__o1->alignment_mask)\ - & ~ (__o1->alignment_mask)); \ - if (__o1->next_free - (char *)__o1->chunk \ - > __o1->chunk_limit - (char *)__o1->chunk) \ - __o1->next_free = __o1->chunk_limit; \ - __o1->object_base = __o1->next_free; \ - } \ + value = (void *) __o1->object_base; \ + if (__o1->next_free == value) \ + __o1->maybe_empty_object = 1; \ + __o1->next_free \ + = __INT_TO_PTR ((__PTR_TO_INT (__o1->next_free)+__o1->alignment_mask)\ + & ~ (__o1->alignment_mask)); \ + if (__o1->next_free - (char *)__o1->chunk \ + > __o1->chunk_limit - (char *)__o1->chunk) \ + __o1->next_free = __o1->chunk_limit; \ + __o1->object_base = __o1->next_free; \ value; }) -#define obstack_free(OBSTACK, OBJ) \ +# define obstack_free(OBSTACK, OBJ) \ __extension__ \ ({ struct obstack *__o = (OBSTACK); \ void *__obj = (OBJ); \ @@ -468,103 +490,108 @@ __extension__ \ #else /* not __GNUC__ or not __STDC__ */ -#define obstack_object_size(h) \ - (unsigned) ((h)->alloc_failed ? 0 : (h)->next_free - (h)->object_base) +# define obstack_object_size(h) \ + (unsigned) ((h)->next_free - (h)->object_base) -#define obstack_room(h) \ +# define obstack_room(h) \ (unsigned) ((h)->chunk_limit - (h)->next_free) +# define obstack_empty_p(h) \ + ((h)->chunk->prev == 0 && (h)->next_free - (h)->chunk->contents == 0) + /* Note that the call to _obstack_newchunk is enclosed in (..., 0) so that we can avoid having void expressions in the arms of the conditional expression. Casting the third operand to void was tried before, but some compilers won't accept it. */ -#define obstack_grow(h,where,length) \ +# define obstack_make_room(h,length) \ +( (h)->temp = (length), \ + (((h)->next_free + (h)->temp > (h)->chunk_limit) \ + ? (_obstack_newchunk ((h), (h)->temp), 0) : 0)) + +# define obstack_grow(h,where,length) \ ( (h)->temp = (length), \ (((h)->next_free + (h)->temp > (h)->chunk_limit) \ ? (_obstack_newchunk ((h), (h)->temp), 0) : 0), \ - ((h)->alloc_failed ? 0 : \ - (memcpy ((h)->next_free, (char *) (where), (h)->temp), \ - (h)->next_free += (h)->temp))) + _obstack_memcpy ((h)->next_free, (where), (h)->temp), \ + (h)->next_free += (h)->temp) -#define obstack_grow0(h,where,length) \ +# define obstack_grow0(h,where,length) \ ( (h)->temp = (length), \ (((h)->next_free + (h)->temp + 1 > (h)->chunk_limit) \ ? (_obstack_newchunk ((h), (h)->temp + 1), 0) : 0), \ - ((h)->alloc_failed ? 0 : \ - (memcpy ((h)->next_free, (char *) (where), (h)->temp), \ + _obstack_memcpy ((h)->next_free, (where), (h)->temp), \ (h)->next_free += (h)->temp, \ - *((h)->next_free)++ = 0))) + *((h)->next_free)++ = 0) -#define obstack_1grow(h,datum) \ +# define obstack_1grow(h,datum) \ ( (((h)->next_free + 1 > (h)->chunk_limit) \ ? (_obstack_newchunk ((h), 1), 0) : 0), \ - ((h)->alloc_failed ? 0 : \ - (*((h)->next_free)++ = (datum)))) + (*((h)->next_free)++ = (datum))) -#define obstack_ptr_grow(h,datum) \ +# define obstack_ptr_grow(h,datum) \ ( (((h)->next_free + sizeof (char *) > (h)->chunk_limit) \ ? (_obstack_newchunk ((h), sizeof (char *)), 0) : 0), \ - ((h)->alloc_failed ? 0 : \ - (*((char **) (((h)->next_free+=sizeof(char *))-sizeof(char *))) = ((char *) datum)))) + (*((char **) (((h)->next_free+=sizeof(char *))-sizeof(char *))) = ((char *) datum))) -#define obstack_int_grow(h,datum) \ +# define obstack_int_grow(h,datum) \ ( (((h)->next_free + sizeof (int) > (h)->chunk_limit) \ ? (_obstack_newchunk ((h), sizeof (int)), 0) : 0), \ - ((h)->alloc_failed ? 0 : \ - (*((int *) (((h)->next_free+=sizeof(int))-sizeof(int))) = ((int) datum)))) + (*((int *) (((h)->next_free+=sizeof(int))-sizeof(int))) = ((int) datum))) -#define obstack_ptr_grow_fast(h,aptr) (*((char **) (h)->next_free)++ = (char *) aptr) -#define obstack_int_grow_fast(h,aint) (*((int *) (h)->next_free)++ = (int) aint) +# define obstack_ptr_grow_fast(h,aptr) (*((char **) (h)->next_free)++ = (char *) aptr) +# define obstack_int_grow_fast(h,aint) (*((int *) (h)->next_free)++ = (int) aint) -#define obstack_blank(h,length) \ +# define obstack_blank(h,length) \ ( (h)->temp = (length), \ (((h)->chunk_limit - (h)->next_free < (h)->temp) \ ? (_obstack_newchunk ((h), (h)->temp), 0) : 0), \ - ((h)->alloc_failed ? 0 : \ - ((h)->next_free += (h)->temp))) + ((h)->next_free += (h)->temp)) -#define obstack_alloc(h,length) \ +# define obstack_alloc(h,length) \ (obstack_blank ((h), (length)), obstack_finish ((h))) -#define obstack_copy(h,where,length) \ +# define obstack_copy(h,where,length) \ (obstack_grow ((h), (where), (length)), obstack_finish ((h))) -#define obstack_copy0(h,where,length) \ +# define obstack_copy0(h,where,length) \ (obstack_grow0 ((h), (where), (length)), obstack_finish ((h))) -#define obstack_finish(h) \ -( (h)->alloc_failed ? 0 : \ - (((h)->next_free == (h)->object_base \ +# define obstack_finish(h) \ +( ((h)->next_free == (h)->object_base \ ? (((h)->maybe_empty_object = 1), 0) \ : 0), \ (h)->temp = __PTR_TO_INT ((h)->object_base), \ (h)->next_free \ = __INT_TO_PTR ((__PTR_TO_INT ((h)->next_free)+(h)->alignment_mask) \ & ~ ((h)->alignment_mask)), \ - (((h)->next_free - (char *) (h)->chunk \ + (((h)->next_free - (char *) (h)->chunk \ > (h)->chunk_limit - (char *) (h)->chunk) \ ? ((h)->next_free = (h)->chunk_limit) : 0), \ (h)->object_base = (h)->next_free, \ - __INT_TO_PTR ((h)->temp))) + __INT_TO_PTR ((h)->temp)) -#if defined (__STDC__) && __STDC__ -#define obstack_free(h,obj) \ +# if defined __STDC__ && __STDC__ +# define obstack_free(h,obj) \ ( (h)->temp = (char *) (obj) - (char *) (h)->chunk, \ (((h)->temp > 0 && (h)->temp < (h)->chunk_limit - (char *) (h)->chunk)\ ? (int) ((h)->next_free = (h)->object_base \ = (h)->temp + (char *) (h)->chunk) \ : (((obstack_free) ((h), (h)->temp + (char *) (h)->chunk), 0), 0))) -#else -#define obstack_free(h,obj) \ +# else +# define obstack_free(h,obj) \ ( (h)->temp = (char *) (obj) - (char *) (h)->chunk, \ (((h)->temp > 0 && (h)->temp < (h)->chunk_limit - (char *) (h)->chunk)\ ? (int) ((h)->next_free = (h)->object_base \ = (h)->temp + (char *) (h)->chunk) \ : (_obstack_free ((h), (h)->temp + (char *) (h)->chunk), 0))) -#endif +# endif #endif /* not __GNUC__ or not __STDC__ */ -#endif /* not __OBSTACK_H__ */ +#ifdef __cplusplus +} /* C++ */ +#endif + +#endif /* obstack.h */ diff --git a/contrib/binutils/include/opcode/ChangeLog b/contrib/binutils/include/opcode/ChangeLog index 40ea655..7452c2b 100644 --- a/contrib/binutils/include/opcode/ChangeLog +++ b/contrib/binutils/include/opcode/ChangeLog @@ -1,3 +1,688 @@ +2000-03-27 Nick Clifton <nickc@cygnus.com> + + * d30v.h (SHORT_A1): Fix value. + (SHORT_AR): Renumber so that it is at the end of the list of short + instructions, not the end of the list of long instructions. + +2000-03-26 Alan Modra <alan@linuxcare.com> + + * i386.h: (UNIXWARE_COMPAT): Rename to SYSV386_COMPAT as the + problem isn't really specific to Unixware. + (OLDGCC_COMPAT): Define. + (i386_optab): If !OLDGCC_COMPAT, don't handle fsubp etc. with + destination %st(0). + Fix lots of comments. + +2000-03-02 J"orn Rennecke <amylaar@cygnus.co.uk> + + * d30v.h: + (SHORT_B2r, SHORT_B3, SHORT_B3r, SHORT_B3b, SHORT_B3br): Updated. + (SHORT_D1r, SHORT_D2, SHORT_D2r, SHORT_D2Br, SHORT_U): Updated. + (SHORT_F, SHORT_AF, SHORT_T, SHORT_A5, SHORT_CMP, SHORT_CMPU): Updated. + (SHORT_A1, SHORT_AA, SHORT_RA, SHORT_MODINC, SHORT_MODDEC): Updated. + (SHORT_C1, SHORT_C2, SHORT_UF, SHORT_A2, SHORT_NONE, LONG): Updated. + (LONG_U, LONG_Ur, LONG_CMP, LONG_M, LONG_M2, LONG_2, LONG_2r): Updated. + (LONG_2b, LONG_2br, LONG_D, LONG_Dr, LONG_Dbr): Updated. + +2000-02-25 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (fild, fistp): Change intel d_Suf form to fildd and + fistpd without suffix. + +2000-02-24 Nick Clifton <nickc@cygnus.com> + + * cgen.h (cgen_cpu_desc): Rename field 'flags' to + 'signed_overflow_ok_p'. + Delete prototypes for cgen_set_flags() and cgen_get_flags(). + +2000-02-24 Andrew Haley <aph@cygnus.com> + + * cgen.h (CGEN_INSN_MACH_HAS_P): New macro. + (CGEN_CPU_TABLE): flags: new field. + Add prototypes for new functions. + +2000-02-24 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Add some more UNIXWARE_COMPAT comments. + +2000-02-23 Linas Vepstas <linas@linas.org> + + * i370.h: New file. + +2000-02-22 Andrew Haley <aph@cygnus.com> + + * mips.h: (OPCODE_IS_MEMBER): Add comment. + +1999-12-30 Andrew Haley <aph@cygnus.com> + + * mips.h (OPCODE_IS_MEMBER): Add gp32 arg, which determines + whether synthetic opcodes (e.g. move) generate 32-bit or 64-bit + insns. + +2000-01-15 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Qualify intel mode far call and jmp with x_Suf. + +1999-12-27 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Add JumpAbsolute qualifier to all non-intel mode + indirect jumps and calls. Add FF/3 call for intel mode. + +Wed Dec 1 03:05:25 1999 Jeffrey A Law (law@cygnus.com) + + * mn10300.h: Add new operand types. Add new instruction formats. + +Wed Nov 24 20:28:58 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Correctly handle immediate for PA2.0 "bb" + instruction. + +1999-11-18 Gavin Romig-Koch <gavin@cygnus.com> + + * mips.h (INSN_ISA5): New. + +1999-11-01 Gavin Romig-Koch <gavin@cygnus.com> + + * mips.h (OPCODE_IS_MEMBER): New. + +1999-10-29 Nick Clifton <nickc@cygnus.com> + + * d30v.h (SHORT_AR): Define. + +1999-10-18 Michael Meissner <meissner@cygnus.com> + + * alpha.h (alpha_num_opcodes): Convert to unsigned. + (alpha_num_operands): Ditto. + +Sun Oct 10 01:46:56 1999 Jerry Quinn <jerry.quinn.adv91@alum.dartmouth.org> + + * hppa.h (pa_opcodes): Add load and store cache control to + instructions. Add ordered access load and store. + + * hppa.h (pa_opcode): Add new entries for addb and addib. + + * hppa.h (pa_opcodes): Fix cmpb and cmpib entries. + + * hppa.h (pa_opcodes): Add entries for cmpb and cmpib. + +Thu Oct 7 00:12:25 MDT 1999 Diego Novillo <dnovillo@cygnus.com> + + * d10v.h: Add flag RESTRICTED_NUM3 for imm3 operands. + +Thu Sep 23 07:08:38 1999 Jerry Quinn <jquinn@nortelnetworks.com> + + * hppa.h (pa_opcodes): Add "call" and "ret". Clean up "b", "bve" + and "be" using completer prefixes. + + * hppa.h (pa_opcodes): Add initializers to silence compiler. + + * hppa.h: Update comments about character usage. + +Mon Sep 20 03:55:31 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Fix minor thinkos introduced while cleaning + up the new fstw & bve instructions. + +Sun Sep 19 10:40:59 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Add remaining PA2.0 integer load/store + instructions. + + * hppa.h (pa_opcodes): Add remaining PA2.0 FP load/store instructions. + + * hppa.h (pa_opcodes): Add long offset double word load/store + instructions. + + * hppa.h (pa_opcodes): Add FLAG_STRICT variants of FP loads and + stores. + + * hppa.h (pa_opcodes): Handle PA2.0 fcnv, fcmp and ftest insns. + + * hppa.h (pa_opcodes): Finish support for PA2.0 "b" instructions. + + * hppa.h (pa_opcodes): Handle PA2.0 "bve" instructions. + + * hppa.h (pa_opcodes): Add new syntax "be" instructions. + + * hppa.h (pa_opcodes): Note use of 'M' and 'L'. + + * hppa.h (pa_opcodes): Add support for "b,l". + + * hppa.h (pa_opcodes): Add support for "b,gate". + +Sat Sep 18 11:41:16 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Use 'fX' for first register operand + in xmpyu. + + * hppa.h (pa_opcodes): Fix mask for probe and probei. + + * hppa.h (pa_opcodes): Fix mask for depwi. + +Tue Sep 7 13:44:25 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Add "addil" variant which has the %r1 as + an explicit output argument. + +Mon Sep 6 04:41:42 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h: Add strict variants of PA1.0/PA1.1 loads and stores. + Add a few PA2.0 loads and store variants. + +1999-09-04 Steve Chamberlain <sac@pobox.com> + + * pj.h: New file. + +1999-08-29 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (i386_regtab): Move %st to top of table, and split off + other fp reg entries. + (i386_float_regtab): To here. + +Sat Aug 28 00:25:25 1999 Jerry Quinn <jquinn@nortelnetworks.com> + + * hppa.h (pa_opcodes): Replace 'f' by 'v'. Prefix float register args + by 'f'. + + * hppa.h (pa_opcodes): Add extrd, extrw, depd, depdi, depw, depwi. + Add supporting args. + + * hppa.h: Document new completers and args. + * hppa.h (pa_opcodes): Add 64 bit patterns and pa2.0 syntax for uxor, + uaddcm, dcor, addi, add, sub, subi, shladd, rfi, and probe. Add pa2.0 + extensions for ssm, rsm, pdtlb, pitlb. Add performance instructions + pmenb and pmdis. + + * hppa.h (pa_opcodes): Add pa2.0 instructions hadd, hshl, + hshr, hsub, mixh, mixw, permh. + + * hppa.h (pa_opcodes): Change completers in instructions to + use 'c' prefix. + + * hppa.h (pa_opcodes): Add popbts, new forms of bb, havg, + hshladd, hshradd, shrpd, and shrpw instructions. Update arg comments. + + * hppa.h (pa_opcodes): Change fmpyfadd, fmpynfadd, fneg, + fnegabs to use 'I' instead of 'F'. + +1999-08-21 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Add AMD athlon instructions, pfnacc, pfpnacc, pswapd. + Document pf2iw and pi2fw as athlon insns. Remove pswapw. + Alphabetically sort PIII insns. + +Wed Aug 18 18:14:40 1999 Doug Evans <devans@canuck.cygnus.com> + + * cgen.h (CGEN_INSN_MACH_HAS_P): New macro. + +Fri Aug 6 09:46:35 1999 Jerry Quinn <jquinn@nortelnetworks.com> + + * hppa.h (pa_opcodes): Add 64 bit versions of or, xor, and, + and andcm. Add 32 and 64 bit version of cmpclr, cmpiclr. + + * hppa.h: Document 64 bit condition completers. + +Thu Aug 5 16:56:07 1999 Jerry Quinn <jquinn@nortelnetworks.com> + + * hppa.h (pa_opcodes): Change condition args to use '?' prefix. + +1999-08-04 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (i386_optab): Add DefaultSize modifier to all insns + that implicitly modify %esp. #undef d_Suf, x_suf, sld_suf, + sldx_suf, bwld_Suf, d_FP, x_FP, sld_FP, sldx_FP at end of table. + +Wed Jul 28 02:04:24 1999 Jerry Quinn <jquinn@nortelnetworks.com> + Jeff Law <law@cygnus.com> + + * hppa.h (pa_opcodes): Add "pushnom" and "pushbts". + + * hppa.h (pa_opcodes): Mark all PA2.0 opcodes with FLAG_STRICT. + + * hppa.h (pa_opcodes): Change xmpyu, fmpyfadd, + and fmpynfadd to use 'J' and 'K' instead of 'E' and 'X'. + +1999-07-13 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Add "undocumented" AMD 3DNow! pf2iw, pi2fw, pswapw insns. + +Thu Jul 1 00:17:24 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (struct pa_opcode): Add new field "flags". + (FLAGS_STRICT): Define. + +Fri Jun 25 04:22:04 1999 Jerry Quinn <jquinn@nortelnetworks.com> + Jeff Law <law@cygnus.com> + + * hppa.h (pa_opcodes): Add pa2.0 clrbts instruction. + + * hppa.h (pa_opcodes): Add entries for mfia and mtsarcm instructions. + +1999-06-23 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Allow `l' suffix on bswap. Allow `w' suffix on arpl, + lldt, lmsw, ltr, str, verr, verw. Add FP flag to fcmov*. Add FP + flag to fcomi and friends. + +Fri May 28 15:26:11 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Move integer arithmetic instructions after + integer logical instructions. + +1999-05-28 Linus Nordberg <linus.nordberg@canit.se> + + * m68k.h: Document new formats `E', `G', `H' and new places `N', + `n', `o'. + + * m68k.h: Define mcf5206e, mcf5307, mcf. Document new format `u' + and new places `m', `M', `h'. + +Thu May 27 04:13:54 1999 Joel Sherrill (joel@OARcorp.com + + * hppa.h (pa_opcodes): Add several processor specific system + instructions. + +Wed May 26 16:57:44 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (pa_opcodes): Add second entry for "comb", "comib", + "addb", and "addib" to be used by the disassembler. + +1999-05-12 Alan Modra <alan@apri.levels.unisa.edu.au> + + * i386.h (ReverseModrm): Remove all occurences. + (InvMem): Add to control/debug/test mov insns, movhlps, movlhps, + movmskps, pextrw, pmovmskb, maskmovq. + Change NoSuf to FP on all MMX, XMM and AMD insns as these all + ignore the data size prefix. + + * i386.h (i386_optab, i386_regtab): Add support for PIII SIMD. + Mostly stolen from Doug Ledford <dledford@redhat.com> + +Sat May 8 23:27:35 1999 Richard Henderson <rth@cygnus.com> + + * ppc.h (PPC_OPCODE_64_BRIDGE): New. + +1999-04-14 Doug Evans <devans@casey.cygnus.com> + + * cgen.h (CGEN_ATTR): Delete member num_nonbools. + (CGEN_ATTR_TYPE): Update. + (CGEN_ATTR_MASK): Number booleans starting at 0. + (CGEN_ATTR_VALUE): Update. + (CGEN_INSN_ATTR): Update. + +Mon Apr 12 23:43:27 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (fmpyfadd, fmpynfadd, fneg, fnegabs): New PA2.0 + instructions. + +Tue Mar 23 11:24:38 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (bb, bvb): Tweak opcode/mask. + + +1999-03-22 Doug Evans <devans@casey.cygnus.com> + + * cgen.h (CGEN_ISA,CGEN_MACH): New typedefs. + (struct cgen_cpu_desc): Rename member mach to machs. New member isas. + New members word_bitsize,default_insn_bitsize,base_insn-bitsize, + min_insn_bitsize,max_insn_bitsize,isa_table,mach_table,rebuild_tables. + Delete member max_insn_size. + (enum cgen_cpu_open_arg): New enum. + (cpu_open): Update prototype. + (cpu_open_1): Declare. + (cgen_set_cpu): Delete. + +1999-03-11 Doug Evans <devans@casey.cygnus.com> + + * cgen.h (CGEN_HW_TABLE): Delete `num_init_entries' member. + (CGEN_OPERAND_NIL): New macro. + (CGEN_OPERAND): New member `type'. + (@arch@_cgen_operand_table): Delete decl. + (CGEN_OPERAND_INDEX,CGEN_OPERAND_TYPE,CGEN_OPERAND_ENTRY): Delete. + (CGEN_OPERAND_TABLE): New struct. + (cgen_operand_lookup_by_name,cgen_operand_lookup_by_num): Declare. + (CGEN_OPINST): Pointer to operand table entry replaced with enum. + (CGEN_CPU_TABLE): New member `isa'. Change member `operand_table', + now a CGEN_OPERAND_TABLE. Add CGEN_CPU_DESC arg to + {get,set}_{int,vma}_operand. + (@arch@_cgen_cpu_open): New arg `isa'. + (cgen_set_cpu): Ditto. + +Fri Feb 26 02:36:45 1999 Richard Henderson <rth@cygnus.com> + + * i386.h: Fill in cmov and fcmov alternates. Add fcomi short forms. + +1999-02-25 Doug Evans <devans@casey.cygnus.com> + + * cgen.h (enum cgen_asm_type): Add CGEN_ASM_NONE. + (CGEN_HW_ENTRY): Delete member `next'. Change type of `type' to + enum cgen_hw_type. + (CGEN_HW_TABLE): New struct. + (hw_table): Delete declaration. + (CGEN_OPERAND): Change member hw to hw_type, change type from pointer + to table entry to enum. + (CGEN_OPINST): Ditto. + (CGEN_CPU_TABLE): Change member hw_list to hw_table. + +Sat Feb 13 14:13:44 1999 Richard Henderson <rth@cygnus.com> + + * alpha.h (AXP_OPCODE_EV6): New. + (AXP_OPCODE_NOPAL): Include it. + +1999-02-09 Doug Evans <devans@casey.cygnus.com> + + * cgen.h (CGEN_CPU_DESC): Renamed from CGEN_OPCODE_DESC. + All uses updated. New members int_insn_p, max_insn_size, + parse_operand,insert_operand,extract_operand,print_operand, + sizeof_fields,set_fields_bitsize,get_int_operand,set_int_operand, + get_vma_operand,set_vma_operand,parse_handlers,insert_handlers, + extract_handlers,print_handlers. + (CGEN_ATTR): Change type of num_nonbools to unsigned int. + (CGEN_ATTR_BOOL_OFFSET): New macro. + (CGEN_ATTR_MASK): Subtract it to compute bit number. + (CGEN_ATTR_VALUE): Redo bool/nonbool attr calculation. + (cgen_opcode_handler): Renamed from cgen_base. + (CGEN_HW_ATTR_VALUE): Renamed from CGEN_HW_ATTR, all uses updated. + (CGEN_OPERAND_ATTR_VALUE): Renamed from CGEN_OPERAND_ATTR, + all uses updated. + (CGEN_OPERAND_INDEX): Rewrite to use table entry, not global. + (enum cgen_opinst_type): Renamed from cgen_operand_instance_type. + (CGEN_IFLD_ATTR_VALUE): Renamed from CGEN_IFLD_ATTR, all uses updated. + (CGEN_OPCODE,CGEN_IBASE): New types. + (CGEN_INSN): Rewrite. + (CGEN_{ASM,DIS}_HASH*): Delete. + (init_opcode_table,init_ibld_table): Declare. + (CGEN_INSN_ATTR): New type. + +Mon Feb 1 21:09:14 1999 Catherine Moore <clm@cygnus.com> + + * i386.h (d_Suf, x_Suf, sld_Suf, sldx_Suf, bwld_Suf): Define. + (x_FP, d_FP, dls_FP, sldx_FP): Define. + Change *Suf definitions to include x and d suffixes. + (movsx): Use w_Suf and b_Suf. + (movzx): Likewise. + (movs): Use bwld_Suf. + (fld): Change ordering. Use sld_FP. + (fild): Add Intel Syntax equivalent of fildq. + (fst): Use sld_FP. + (fist): Use sld_FP. + (fstp): Use sld_FP. Add x_FP version. + (fistp): LLongMem version for Intel Syntax. + (fcom, fcomp): Use sld_FP. + (fadd, fiadd, fsub): Use sld_FP. + (fsubr): Use sld_FP. + (fmul, fimul, fdvi, fidiv, fdivr): Use sld_FP. + +1999-01-27 Doug Evans <devans@casey.cygnus.com> + + * cgen.h (enum cgen_mode): Add CGEN_MODE_TARGET_MAX, CGEN_MODE_INT, + CGEN_MODE_UINT. + +Sat Jan 16 01:29:25 1999 Jeffrey A Law (law@cygnus.com) + + * hppa.h (bv): Fix mask. + +1999-01-05 Doug Evans <devans@casey.cygnus.com> + + * cgen.h (CGEN_ATTR_VALUE_TYPE): New typedef. + (CGEN_ATTR): Use it. + (CGEN_ATTR_TYPE,CGEN_ATTR_ENTRY): Ditto. + (CGEN_ATTR_TABLE): New member dfault. + +1998-12-30 Gavin Romig-Koch <gavin@cygnus.com> + + * mips.h (MIPS16_INSN_BRANCH): New. + +Wed Dec 9 10:38:48 1998 David Taylor <taylor@texas.cygnus.com> + + The following is part of a change made by Edith Epstein + <eepstein@sophia.cygnus.com> as part of a project to merge in + changes by HP; HP did not create ChangeLog entries. + + * hppa.h (completer_chars): list of chars to not put a space + after. + +Sun Dec 6 13:21:34 1998 Ian Lance Taylor <ian@cygnus.com> + + * i386.h (i386_optab): Permit w suffix on processor control and + status word instructions. + +1998-11-30 Doug Evans <devans@casey.cygnus.com> + + * cgen.h (struct cgen_hw_entry): Delete const on attrs member. + (struct cgen_keyword_entry): Ditto. + (struct cgen_operand): Ditto. + (CGEN_IFLD): New typedef, with associated access macros. + (CGEN_IFMT): New typedef, with associated access macros. + (CGEN_IFMT): Renamed from CGEN_FORMAT. New member `iflds'. + (CGEN_IVALUE): New typedef. + (struct cgen_insn): Delete const on syntax,attrs members. + `format' now points to format data. Type of `value' is now + CGEN_IVALUE. + (struct cgen_opcode_table): New member ifld_table. + +1998-11-18 Doug Evans <devans@casey.cygnus.com> + + * cgen.h (cgen_extract_fn): Update type of `base_insn' arg. + (CGEN_OPERAND_INSTANCE): New member `attrs'. + (CGEN_OPERAND_INSTANCE_{ATTRS,ATTR}): New macros. + (cgen_dis_lookup_insn): Update type of `base_insn' arg. + (cgen_opcode_table): Update type of dis_hash fn. + (extract_operand): Update type of `insn_value' arg. + +Thu Oct 29 11:38:36 1998 Doug Evans <devans@canuck.cygnus.com> + + * cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Delete. + +Tue Oct 27 08:57:59 1998 Gavin Romig-Koch <gavin@cygnus.com> + + * mips.h (INSN_MULT): Added. + +Tue Oct 20 11:31:34 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (MAX_MNEM_SIZE): Rename from MAX_OPCODE_SIZE. + +Mon Oct 19 12:50:00 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen.h (CGEN_INSN_INT): New typedef. + (CGEN_INT_INSN_P): Renamed from CGEN_INT_INSN. + (CGEN_INSN_BYTES): Renamed from cgen_insn_t. + (CGEN_INSN_BYTES_PTR): New typedef. + (CGEN_EXTRACT_INFO): New typedef. + (cgen_insert_fn,cgen_extract_fn): Update. + (cgen_opcode_table): New member `insn_endian'. + (assemble_insn,lookup_insn,lookup_get_insn_operands): Update. + (insert_operand,extract_operand): Update. + (cgen_get_insn_value,cgen_put_insn_value): Add prototypes. + +Fri Oct 9 13:38:13 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen.h (CGEN_ATTR_BOOLS): New macro. + (struct CGEN_HW_ENTRY): New member `attrs'. + (CGEN_HW_ATTR): New macro. + (struct CGEN_OPERAND_INSTANCE): New member `name'. + (CGEN_INSN_INVALID_P): New macro. + +Mon Oct 5 00:21:07 1998 Jeffrey A Law (law@cygnus.com) + + * hppa.h: Add "fid". + +Sun Oct 4 21:00:00 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + From Robert Andrew Dale <rob@nb.net> + * i386.h (i386_optab): Add AMD 3DNow! instructions. + (AMD_3DNOW_OPCODE): Define. + +Tue Sep 22 17:53:47 1998 Nick Clifton <nickc@cygnus.com> + + * d30v.h (EITHER_BUT_PREFER_MU): Define. + +Mon Aug 10 14:09:38 1998 Doug Evans <devans@canuck.cygnus.com> + + * cgen.h (cgen_insn): #if 0 out element `cdx'. + +Mon Aug 3 12:21:57 1998 Doug Evans <devans@seba.cygnus.com> + + Move all global state data into opcode table struct, and treat + opcode table as something that is "opened/closed". + * cgen.h (CGEN_OPCODE_DESC): New type. + (all fns): New first arg of opcode table descriptor. + (cgen_set_parse_operand_fn): Add prototype. + (cgen_current_machine,cgen_current_endian): Delete. + (CGEN_OPCODE_TABLE): New members mach,endian,operand_table, + parse_operand_fn,asm_hash_table,asm_hash_table_entries, + dis_hash_table,dis_hash_table_entries. + (opcode_open,opcode_close): Add prototypes. + + * cgen.h (cgen_insn): New element `cdx'. + +Thu Jul 30 21:44:25 1998 Frank Ch. Eigler <fche@cygnus.com> + + * d30v.h (FLAG_LKR): New flag for "left-kills-right" instructions. + +Tue Jul 28 10:59:07 1998 Jeffrey A Law (law@cygnus.com) + + * mn10300.h: Add "no_match_operands" field for instructions. + (MN10300_MAX_OPERANDS): Define. + +Fri Jul 24 11:44:24 1998 Doug Evans <devans@canuck.cygnus.com> + + * cgen.h (cgen_macro_insn_count): Declare. + +Tue Jul 21 13:12:13 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen.h (CGEN_VERSION_{MAJOR,MINOR,FIXLEVEL}): Define. + (cgen_insert_fn,cgen_extract_fn): New arg `pc'. + (get_operand,put_operand): Replaced with get_{int,vma}_operand, + set_{int,vma}_operand. + +Fri Jun 26 11:09:06 1998 Jeffrey A Law (law@cygnus.com) + + * mn10300.h: Add "machine" field for instructions. + (MN103, AM30): Define machine types. + +Fri Jun 19 16:09:09 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Use FP, not sl_Suf, for fxsave and fxrstor. + +1998-06-18 Ulrich Drepper <drepper@cygnus.com> + + * i386.h: Add support for fxsave, fxrstor, sysenter and sysexit. + +Sat Jun 13 11:31:35 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (i386_optab): Add general form of aad and aam. Add ud2a + and ud2b. + (i386_regtab): Allow cr0..7, db0..7, dr0..7, tr0..7, not just + those that happen to be implemented on pentiums. + +Tue Jun 9 12:16:01 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Change occurences of Data16 to Size16, Data32 to Size32, + IgnoreDataSize to IgnoreSize. Flag address and data size prefixes + with Size16|IgnoreSize or Size32|IgnoreSize. + +Mon Jun 8 12:15:52 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (REPNE): Rename to REPNE_PREFIX_OPCODE. + (REPE): Rename to REPE_PREFIX_OPCODE. + (i386_regtab_end): Remove. + (i386_prefixtab, i386_prefixtab_end): Remove. + (i386_optab): Use NULL as sentinel rather than "" to suit rewrite + of md_begin. + (MAX_OPCODE_SIZE): Define. + (i386_optab_end): Remove. + (sl_Suf): Define. + (sl_FP): Use sl_Suf. + + * i386.h (i386_optab): Allow 16 bit displacement for `mov + mem,acc'. Combine 16 and 32 bit forms of various insns. Allow 16 + bit form of ljmp. Add IsPrefix modifier to prefixes. Add addr32, + data32, dword, and adword prefixes. + (i386_regtab): Add BaseIndex modifier to valid 16 bit base/index + regs. + +Fri Jun 5 23:42:43 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (i386_regtab): Remove BaseIndex modifier from esp. + + * i386.h: Allow `l' suffix on fld, fst, fstp, fcom, fcomp with + register operands, because this is a common idiom. Flag them with + a warning. Allow illegal faddp, fsubp, fsubrp, fmulp, fdivp, + fdivrp because gcc erroneously generates them. Also flag with a + warning. + + * i386.h: Add suffix modifiers to most insns, and tighter operand + checks in some cases. Fix a number of UnixWare compatibility + issues with float insns. Merge some floating point opcodes, using + new FloatMF modifier. + (WORD_PREFIX_OPCODE): Rename to DATA_PREFIX_OPCODE for + consistency. + + * i386.h: Change occurence of ShortformW to W|ShortForm. Add + IgnoreDataSize where appropriate. + +Wed Jun 3 18:28:45 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: (one_byte_segment_defaults): Remove. + (two_byte_segment_defaults): Remove. + (i386_regtab): Add BaseIndex to 32 bit regs reg_type. + +Fri May 15 15:59:04 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen.h (cgen_hw_lookup_by_name): Renamed from cgen_hw_lookup. + (cgen_hw_lookup_by_num): Declare. + +Thu May 7 09:27:58 1998 Frank Ch. Eigler <fche@cygnus.com> + + * mips.h (OP_{SH,MASK}_CODE2): Added "q" operand format for lower + ten bits of MIPS ISA1 "break" instruction, and for "sdbbp" + +Thu May 7 02:14:08 1998 Doug Evans <devans@charmed.cygnus.com> + + * cgen.h (cgen_asm_init_parse): Delete. + (cgen_save_fixups,cgen_restore_fixups,cgen_swap_fixups): Delete. + (cgen_asm_record_register,cgen_asm_finish_insn): Delete. + +Mon Apr 27 10:13:11 1998 Doug Evans <devans@seba.cygnus.com> + + * cgen.h (CGEN_ATTR_TYPE): Delete `const', moved to uses. + (cgen_asm_finish_insn): Update prototype. + (cgen_insn): New members num, data. + (CGEN_INSN_TABLE): Members asm_hash, asm_hash_table_size, + dis_hash, dis_hash_table_size moved to ... + (CGEN_OPCODE_TABLE). Here. Renamed from CGEN_OPCODE_DATA. + All uses updated. New members asm_hash_p, dis_hash_p. + (CGEN_MINSN_EXPANSION): New struct. + (cgen_expand_macro_insn): Declare. + (cgen_macro_insn_count): Declare. + (get_insn_operands): Update prototype. + (lookup_get_insn_operands): Declare. + +Tue Apr 21 17:11:32 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h (i386_optab): Change iclrKludge and imulKludge to + regKludge. Add operands types for string instructions. + +Mon Apr 20 14:40:29 1998 Tom Tromey <tromey@cygnus.com> + + * i386.h (X): Renamed from `Z_' to preserve formatting of opcode + table. + +Sun Apr 19 13:54:06 1998 Tom Tromey <tromey@cygnus.com> + + * i386.h (Z_): Renamed from `_' to avoid clash with common alias + for `gettext'. + +Fri Apr 3 12:04:48 1998 Alan Modra <alan@spri.levels.unisa.edu.au> + + * i386.h: Remove NoModrm flag from all insns: it's never checked. + Add IsString flag to string instructions. + (IS_STRING): Don't define. + (LOCK_PREFIX_OPCODE, CS_PREFIX_OPCODE, DS_PREFIX_OPCODE): Define. + (ES_PREFIX_OPCODE, FS_PREFIX_OPCODE, GS_PREFIX_OPCODE): Define. + (SS_PREFIX_OPCODE): Define. + Mon Mar 30 21:31:56 1998 Ian Lance Taylor <ian@cygnus.com> * i386.h: Revert March 24 patch; no more LinearAddress. @@ -25,6 +710,10 @@ Mon Mar 2 10:44:07 1998 Doug Evans <devans@seba.cygnus.com> * cgen.h (CGEN_BOOL_ATTR): New macro. +Thu Feb 26 15:54:31 1998 Michael Meissner <meissner@cygnus.com> + + * d30v.h (FLAG_DELAY): New flag for delayed branches/jumps. + Mon Feb 23 10:38:21 1998 Doug Evans <devans@seba.cygnus.com> * cgen.h (CGEN_CAT3): Delete. Use CONCAT3 now. @@ -88,7 +777,7 @@ Thu Jan 22 17:54:56 1998 Nick Clifton <nickc@cygnus.com> Wed Jan 14 17:21:43 1998 Nick Clifton <nickc@cygnus.com> - * cgen.h: Formatting changes to improve readability. + * cgen.h: Formatting changes to improve readability. Mon Jan 12 11:37:36 1998 Doug Evans <devans@seba.cygnus.com> @@ -101,10 +790,22 @@ Mon Jan 12 11:37:36 1998 Doug Evans <devans@seba.cygnus.com> (CGEN_{SYNTAX,FORMAT}): New types. (cgen_insn): Format and syntax separated from each other. +Tue Dec 16 15:15:52 1997 Michael Meissner <meissner@cygnus.com> + + * d30v.h (d30v_opcode): Reorder flags somewhat, add new flags for + 2 word load/store, ADDppp/SUBppp, 16/32 bit multiply. Make + flags_{used,set} long. + (d30v_operand): Make flags field long. + Mon Dec 1 12:24:44 1997 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> * m68k.h: Fix comment describing operand types. +Sun Nov 23 22:31:27 1997 Michael Meissner <meissner@cygnus.com> + + * d30v.h (SHORT_CMPU): Add case for cmpu instruction, and move + everything else after down. + Tue Nov 18 18:45:14 1997 J"orn Rennecke <amylaar@cygnus.co.uk> * d10v.h (OPERAND_FLAG): Split into: @@ -143,6 +844,26 @@ Mon Sep 15 18:28:37 1997 Nick Clifton <nickc@cygnus.com> * v850.h (struct v850_opcode): Add processors field. (PROCESSOR_V850, PROCESSOR_ALL): New bit constants. + (PROCESSOR_V850E, PROCESSOR_NOT_V850): New bit constants. + (PROCESSOR_V850EA): New bit constants. + +Mon Sep 15 11:29:43 1997 Ken Raeburn <raeburn@cygnus.com> + + Merge changes from Martin Hunt: + + * d30v.h: Allow up to 64 control registers. Add + SHORT_A5S format. + + * d30v.h (LONG_Db): New form for delayed branches. + + * d30v.h: (LONG_Db): New form for repeati. + + * d30v.h (SHORT_D2B): New form. + + * d30v.h (SHORT_A2): New form. + + * d30v.h (OPERAND_2REG): Add new operand to indicate 2 + registers are used. Needed for VLIW optimization. Mon Sep 8 14:05:45 1997 Doug Evans <dje@canuck.cygnus.com> @@ -152,7 +873,7 @@ Mon Sep 8 14:05:45 1997 Doug Evans <dje@canuck.cygnus.com> Tue Sep 2 15:32:32 1997 Nick Clifton <nickc@cygnus.com> - * v850.h (V850_OPREAND_ADJUST_SHORT_MEMORY): Removed. + * v850.h (V850_OPREAND_ADJUST_SHORT_MEMORY): Removed. Tue Aug 26 12:21:52 1997 Ian Lance Taylor <ian@cygnus.com> @@ -175,14 +896,15 @@ Fri Aug 22 10:38:29 1997 Nick Clifton <nickc@cygnus.com> Mon Aug 18 11:05:58 1997 Nick Clifton <nickc@cygnus.com> - * v850.h (struct v850_opcode): Remove flags field. + * v850.h (struct v850_opcode): Remove flags field. Wed Aug 13 18:45:48 1997 Nick Clifton <nickc@cygnus.com> * v850.h (struct v850_opcode): Add flags field. (struct v850_operand): Extend meaning of 'bits' and 'shift' - fields. - + fields. + (V850E_INSTRUCTION, V850EA_INSTRUCTION): New flags. + (V850E_PUSH_POP, V850E_IMMEDIATE16, V850E_IMMEDIATE32): New flags. Fri Aug 8 16:58:42 1997 Doug Evans <dje@canuck.cygnus.com> @@ -285,26 +1007,117 @@ Thu Mar 6 14:18:30 1997 Jeffrey A Law (law@cygnus.com) Mon Feb 24 15:15:56 1997 Martin M. Hunt <hunt@pizza.cygnus.com> - * d10v.h: Change pre_defined_registers to + * d10v.h: Change pre_defined_registers to d10v_predefined_registers and reg_name_cnt to d10v_reg_name_cnt. Sat Feb 22 21:25:00 1997 Dawn Perchik <dawn@cygnus.com> * mips.h: Add macros for cop0, cop1 cop2 and cop3. - Change mips_opcodes from const array to a pointer, + Change mips_opcodes from const array to a pointer, and change bfd_mips_num_opcodes from const int to int, - so that we can increase the size of the mips opcodes table + so that we can increase the size of the mips opcodes table dynamically. - + +Fri Feb 21 16:34:18 1997 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d30v.h (FLAG_X): Remove unused flag. + +Tue Feb 18 17:37:20 1997 Martin M. Hunt <hunt@pizza.cygnus.com> + + * d30v.h: New file. + +Fri Feb 14 13:16:15 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (PDS_NAME): Macro to access name field of predefined symbols. + (PDS_VALUE): Macro to access value field of predefined symbols. + (tic80_next_predefined_symbol): Add prototype. + +Mon Feb 10 10:32:17 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (tic80_symbol_to_value): Change prototype to match + change in function, added class parameter. + +Thu Feb 6 17:30:15 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (TIC80_OPERAND_ENDMASK): Add for flagging TIc80 + endmask fields, which are somewhat weird in that 0 and 32 are + treated exactly the same. + +Thu Jan 30 13:46:18 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h: Change all the OPERAND defines to use the form (1 << X) + rather than a constant that is 2**X. Reorder them to put bits for + operands that have symbolic names in the upper bits, so they can + be packed into an int where the lower bits contain the value that + corresponds to that symbolic name. + (predefined_symbo): Add struct. + (tic80_predefined_symbols): Declare array of translations. + (tic80_num_predefined_symbols): Declare size of that array. + (tic80_value_to_symbol): Declare function. + (tic80_symbol_to_value): Declare function. + Wed Jan 29 09:37:25 1997 Jeffrey A Law (law@cygnus.com) * mn10200.h (MN10200_OPERAND_RELAX): Define. +Sat Jan 18 15:18:59 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (TIC80_NO_R0_DEST): Add for opcodes where r0 cannot + be the destination register. + +Thu Jan 16 20:48:55 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (struct tic80_opcode): Change "format" field to "flags". + (FMT_UNUSED, FMT_SI, FMT_LI, FMT_REG): Delete. + (TIC80_VECTOR): Define a flag bit for the flags. This one means + that the opcode can have two vector instructions in a single + 32 bit word and we have to encode/decode both. + +Tue Jan 14 19:37:09 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (TIC80_OPERAND_PCREL): Renamed from + TIC80_OPERAND_RELATIVE for PC relative. + (TIC80_OPERAND_BASEREL): New flag bit for register + base relative. + +Mon Jan 13 15:56:38 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (TIC80_OPERAND_FLOAT): Add for floating point operands. + +Mon Jan 6 10:51:15 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (TIC80_OPERAND_SCALED): Operand may have optional + ":s" modifier for scaling. + +Sun Jan 5 12:12:19 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (TIC80_OPERAND_M_SI): Add operand modifier for ":m". + (TIC80_OPERAND_M_LI): Ditto + +Sat Jan 4 19:02:44 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (TIC80_OPERAND_BITNUM): Renamed from TIC80_OPERAND_CC_SZ. + (TIC80_OPERAND_CC): New define for condition code operand. + (TIC80_OPERAND_CR): New define for control register operand. + +Fri Jan 3 16:22:23 1997 Fred Fish <fnf@cygnus.com> + + * tic80.h (struct tic80_opcode): Name changed. + (struct tic80_opcode): Remove format field. + (struct tic80_operand): Add insertion and extraction functions. + (TIC80_OPERAND_*): Remove old bogus values, start adding new + correct ones. + (FMT_*): Ditto. + Tue Dec 31 15:05:41 1996 Michael Meissner <meissner@tiktok.cygnus.com> * v850.h (V850_OPERAND_ADJUST_SHORT_MEMORY): New flag to adjust type IV instruction offsets. +Fri Dec 27 22:23:10 1996 Fred Fish <fnf@cygnus.com> + + * tic80.h: New file. + Wed Dec 18 10:06:31 1996 Jeffrey A Law (law@cygnus.com) * mn10200.h (MN10200_OPERAND_NOCHECK): Define. @@ -314,7 +1127,7 @@ Sat Dec 14 10:48:31 1996 Fred Fish <fnf@ninemoons.com> * mn10200.h: Fix comment, mn10200_operand not powerpc_operand. * mn10300.h: Fix comment, mn10300_operand not powerpc_operand. * v850.h: Fix comment, v850_operand not powerpc_operand. - + Mon Dec 9 16:45:39 1996 Jeffrey A Law (law@cygnus.com) * mn10200.h: Flesh out structures and definitions needed by @@ -467,7 +1280,7 @@ Mon Jul 22 12:15:25 1996 Ian Lance Taylor <ian@cygnus.com> Wed Jul 17 14:46:38 1996 Martin M. Hunt <hunt@pizza.cygnus.com> - * d10v.h: New file. + * d10v.h: New file. Thu Jul 11 12:09:15 1996 Jeffrey A Law (law@cygnus.com) @@ -509,7 +1322,7 @@ Tue Jun 18 16:06:00 1996 Jeffrey A. Law <law@rtl.cygnus.com> (EBITOP): Likewise. (O_LAST): Bump. (ldc, stc, movb, movw, movl): Use 32bit offsets and absolutes. - + * h8300.h (EXR, SHIFT_2, MACREG, SHIFT_IMM, RDINC): Define. (O_TAS, O_CLRMAC, O_LDMAC, O_MAC, O_LDM, O_STM): Define. (BITOP, EBITOP): Handle new H8/S addressing modes for @@ -517,7 +1330,7 @@ Tue Jun 18 16:06:00 1996 Jeffrey A. Law <law@rtl.cygnus.com> (UNOP3): Handle new shift/rotate insns on the H8/S. (insns using exr): New instructions. (tas, mac, ldmac, clrmac, ldm, stm): New instructions. - + Thu May 23 16:56:48 1996 Jeffrey A Law (law@cygnus.com) * h8300.h (add.l): Undo Apr 5th change. The manual I had @@ -805,7 +1618,7 @@ Sun Jul 10 11:01:09 1994 Ian Dall (dall@hfrd.dsto.gov.au) Thu Jul 7 12:34:48 1994 Steve Chamberlain (sac@jonny.cygnus.com) - * h8300.h (xor.l) :fix bit pattern. + * h8300.h (xor.l) :fix bit pattern. (L_2): New size of operand. (trapa): Use it. @@ -906,7 +1719,7 @@ Sat Dec 11 16:14:06 1993 Steve Chamberlain (sac@thepub.cygnus.com) Wed Dec 1 12:15:32 1993 Jeffrey A. Law (law@snake.cs.utah.edu) - * From Hisashi MINAMINO <minamino@sramhc.sra.co.jp> + * From Hisashi MINAMINO <minamino@sramhc.sra.co.jp> * hppa.h: #undef NONE to avoid conflict with hiux include files. Sun Nov 21 22:06:57 1993 Jeffrey A. Law (law@snake.cs.utah.edu) @@ -1059,11 +1872,11 @@ Fri Jun 11 18:38:44 1993 Ken Raeburn (raeburn@cygnus.com) Patches from Jeff Law, law@cs.utah.edu: * hppa.h: Clean up some of the OLD_TABLE, non-OLD_TABLE braindamage. Make the tables be the same for the following instructions: - "bb", "addb[tf]", "addib[tf]", "add", "add[loc]", "addco", + "bb", "addb[tf]", "addib[tf]", "add", "add[loc]", "addco", "sh[123]add", "sh[123]add[lo]", "sub", "sub[obt]", "sub[bt]o", - "ds", "comclr", "addi", "addi[ot]", "addito", "subi", "subio", - "comiclr", "fadd", "fsub", "fmpy", "fdiv", "fsqrt", "fabs", - "frnd", "fcpy", "fcnvff", "fcnvxf", "fcnvfx", "fcnvfxt", + "ds", "comclr", "addi", "addi[ot]", "addito", "subi", "subio", + "comiclr", "fadd", "fsub", "fmpy", "fdiv", "fsqrt", "fabs", + "frnd", "fcpy", "fcnvff", "fcnvxf", "fcnvfx", "fcnvfxt", "fcmp", and "ftest". * hppa.h: Make new and old tables the same for "break", "mtctl", @@ -1084,7 +1897,7 @@ Fri Jun 4 15:41:37 1993 Steve Chamberlain (sac@phydeaux.cygnus.com) Thu Jun 3 15:42:59 1993 Stu Grossman (grossman@cygnus.com) * Patches from Jeffrey Law <law@cs.utah.edu>. - * hppa.h: Rework single precision FP + * hppa.h: Rework single precision FP instructions so that they correctly disassemble code PA1.1 code. @@ -1131,7 +1944,7 @@ Thu Feb 18 02:03:14 1993 John Gilmore (gnu@cygnus.com) * m68k.h (BREAK_UP_BIG_DECL, AND_OTHER_PART): Add kludge which allows callers to break up the large initialized struct full of - opcodes into two half-sized ones. This permits GCC to compile + opcodes into two half-sized ones. This permits GCC to compile this module, since it takes exponential space for initializers. (numopcodes, endop): Revise to use AND_OTHER_PART in size calcs. @@ -1354,7 +2167,7 @@ Tue Dec 10 00:22:20 1991 K. Richard Pixley (rich at rtl.cygnus.com) Sat Nov 30 20:40:51 1991 Steve Chamberlain (sac at rtl.cygnus.com) - * a29k.h, arm.h, h8300.h, i386.h, i860.h, i960.h , m68k.h, + * a29k.h, arm.h, h8300.h, i386.h, i860.h, i960.h , m68k.h, m88k.h, mips.h , np1.h, ns32k.h, pn.h, pyr.h, sparc.h, tahoe.h, vax.h, ChangeLog: renamed from ../<foo>-opcode.h diff --git a/contrib/binutils/include/opcode/alpha.h b/contrib/binutils/include/opcode/alpha.h index c3babc9..6f31e9a 100644 --- a/contrib/binutils/include/opcode/alpha.h +++ b/contrib/binutils/include/opcode/alpha.h @@ -1,5 +1,5 @@ /* alpha.h -- Header file for Alpha opcode table - Copyright 1996 Free Software Foundation, Inc. + Copyright 1996, 1999 Free Software Foundation, Inc. Contributed by Richard Henderson <rth@tamu.edu>, patterned after the PPC opcode table written by Ian Lance Taylor. @@ -54,7 +54,7 @@ struct alpha_opcode in the order in which the disassembler should consider instructions. */ extern const struct alpha_opcode alpha_opcodes[]; -extern const int alpha_num_opcodes; +extern const unsigned alpha_num_opcodes; /* Values defined for the flags field of a struct alpha_opcode. */ @@ -62,11 +62,12 @@ extern const int alpha_num_opcodes; #define AXP_OPCODE_BASE 0x0001 /* Base architecture -- all cpus. */ #define AXP_OPCODE_EV4 0x0002 /* EV4 specific PALcode insns. */ #define AXP_OPCODE_EV5 0x0004 /* EV5 specific PALcode insns. */ +#define AXP_OPCODE_EV6 0x0008 /* EV6 specific PALcode insns. */ #define AXP_OPCODE_BWX 0x0100 /* Byte/word extension (amask bit 0). */ #define AXP_OPCODE_CIX 0x0200 /* "Count" extension (amask bit 1). */ #define AXP_OPCODE_MAX 0x0400 /* Multimedia extension (amask bit 8). */ -#define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5)) +#define AXP_OPCODE_NOPAL (~(AXP_OPCODE_EV4|AXP_OPCODE_EV5|AXP_OPCODE_EV6)) /* A macro to extract the major opcode from an instruction. */ #define AXP_OP(i) (((i) >> 26) & 0x3F) @@ -134,7 +135,7 @@ struct alpha_operand the operands field of the alpha_opcodes table. */ extern const struct alpha_operand alpha_operands[]; -extern const int alpha_num_operands; +extern const unsigned alpha_num_operands; /* Values defined for the flags field of a struct alpha_operand. */ diff --git a/contrib/binutils/include/opcode/arm.h b/contrib/binutils/include/opcode/arm.h new file mode 100644 index 0000000..c7087eb --- /dev/null +++ b/contrib/binutils/include/opcode/arm.h @@ -0,0 +1,294 @@ +/* ARM opcode list. + Copyright (C) 1989, Free Software Foundation, Inc. + +This file is part of GDB and GAS. + +GDB and GAS are free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 1, or (at your option) +any later version. + +GDB and GAS are distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GDB or GAS; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +/* types of instruction (encoded in bits 26 and 27 of the instruction) */ + +#define TYPE_ARITHMETIC 0 +#define TYPE_LDR_STR 1 +#define TYPE_BLOCK_BRANCH 2 +#define TYPE_SWI 3 + +/* bit 25 decides whether an instruction is a block move or a branch */ +#define SUBTYPE_BLOCK 0 +#define SUBTYPE_BRANCH 1 + +/* codes to distinguish the arithmetic instructions */ + +#define OPCODE_AND 0 +#define OPCODE_EOR 1 +#define OPCODE_SUB 2 +#define OPCODE_RSB 3 +#define OPCODE_ADD 4 +#define OPCODE_ADC 5 +#define OPCODE_SBC 6 +#define OPCODE_RSC 7 +#define OPCODE_TST 8 +#define OPCODE_TEQ 9 +#define OPCODE_CMP 10 +#define OPCODE_CMN 11 +#define OPCODE_ORR 12 +#define OPCODE_MOV 13 +#define OPCODE_BIC 14 +#define OPCODE_MVN 15 + +/* condition codes */ + +#define COND_EQ 0 +#define COND_NE 1 +#define COND_CS 2 +#define COND_CC 3 +#define COND_MI 4 +#define COND_PL 5 +#define COND_VS 6 +#define COND_VC 7 +#define COND_HI 8 +#define COND_LS 9 +#define COND_GE 10 +#define COND_LT 11 +#define COND_GT 12 +#define COND_LE 13 +#define COND_AL 14 +#define COND_NV 15 + +/* Describes the format of an ARM machine instruction */ + +struct generic_fmt { + unsigned rest :25; /* the rest of the instruction */ + unsigned subtype :1; /* used to decide between block and branch */ + unsigned type :2; /* one of TYPE_* */ + unsigned cond :4; /* one of COND_* defined above */ +}; + +struct arith_fmt { + unsigned operand2 :12; /* #nn or rn or rn shift #m or rn shift rm */ + unsigned dest :4; /* place where the answer goes */ + unsigned operand1 :4; /* first operand to instruction */ + unsigned set :1; /* == 1 means set processor flags */ + unsigned opcode :4; /* one of OPCODE_* defined above */ + unsigned immed :1; /* operand2 is an immediate value */ + unsigned type :2; /* == TYPE_ARITHMETIC */ + unsigned cond :4; /* one of COND_* defined above */ +}; + +struct ldr_str_fmt { + unsigned offset :12; /* #nn or rn or rn shift #m */ + unsigned reg :4; /* destination for LDR, source for STR */ + unsigned base :4; /* base register */ + unsigned is_load :1; /* == 1 for LDR */ + unsigned writeback :1; /* == 1 means write back (base+offset) into base */ + unsigned byte :1; /* == 1 means byte access else word */ + unsigned up :1; /* == 1 means add offset else subtract it */ + unsigned pre_index :1; /* == 1 means [a,b] form else [a],b form */ + unsigned immed :1; /* == 0 means immediate offset */ + unsigned type :2; /* == TYPE_LDR_STR */ + unsigned cond :4; /* one of COND_* defined above */ +}; + +struct block_fmt { + unsigned mask :16; /* register mask */ + unsigned base :4; /* register used as base of move */ + unsigned is_load :1; /* == 1 for LDM */ + unsigned writeback :1; /* == 1 means update base after move */ + unsigned set :1; /* == 1 means set flags in pc if included in mask */ + unsigned increment :1; /* == 1 means increment base register */ + unsigned before :1; /* == 1 means inc/dec before each move */ + unsigned is_block :1; /* == SUBTYPE_BLOCK */ + unsigned type :2; /* == TYPE_BLOCK_BRANCH */ + unsigned cond :4; /* one of COND_* defined above */ +}; + +struct branch_fmt { + unsigned dest :24; /* destination of the branch */ + unsigned link :1; /* branch with link (function call) */ + unsigned is_branch :1; /* == SUBTYPE_BRANCH */ + unsigned type :2; /* == TYPE_BLOCK_BRANCH */ + unsigned cond :4; /* one of COND_* defined above */ +}; + +#define ROUND_N 0 +#define ROUND_P 1 +#define ROUND_M 2 +#define ROUND_Z 3 + +#define FLOAT2_MVF 0 +#define FLOAT2_MNF 1 +#define FLOAT2_ABS 2 +#define FLOAT2_RND 3 +#define FLOAT2_SQT 4 +#define FLOAT2_LOG 5 +#define FLOAT2_LGN 6 +#define FLOAT2_EXP 7 +#define FLOAT2_SIN 8 +#define FLOAT2_COS 9 +#define FLOAT2_TAN 10 +#define FLOAT2_ASN 11 +#define FLOAT2_ACS 12 +#define FLOAT2_ATN 13 + +#define FLOAT3_ADF 0 +#define FLOAT3_MUF 1 +#define FLOAT3_SUF 2 +#define FLOAT3_RSF 3 +#define FLOAT3_DVF 4 +#define FLOAT3_RDF 5 +#define FLOAT3_POW 6 +#define FLOAT3_RPW 7 +#define FLOAT3_RMF 8 +#define FLOAT3_FML 9 +#define FLOAT3_FDV 10 +#define FLOAT3_FRD 11 +#define FLOAT3_POL 12 + +struct float2_fmt { + unsigned operand2 :3; /* second operand */ + unsigned immed :1; /* == 1 if second operand is a constant */ + unsigned pad1 :1; /* == 0 */ + unsigned rounding :2; /* ROUND_* */ + unsigned is_double :1; /* == 1 if precision is double (only if not extended) */ + unsigned pad2 :4; /* == 1 */ + unsigned dest :3; /* destination */ + unsigned is_2_op :1; /* == 1 if 2 operand ins */ + unsigned operand1 :3; /* first operand (only of is_2_op == 0) */ + unsigned is_extended :1; /* == 1 if precision is extended */ + unsigned opcode :4; /* FLOAT2_* or FLOAT3_* depending on is_2_op */ + unsigned must_be_2 :2; /* == 2 */ + unsigned type :2; /* == TYPE_SWI */ + unsigned cond :4; /* COND_* */ +}; + +struct swi_fmt { + unsigned argument :24; /* argument to SWI (syscall number) */ + unsigned must_be_3 :2; /* == 3 */ + unsigned type :2; /* == TYPE_SWI */ + unsigned cond :4; /* one of COND_* defined above */ +}; + +union insn_fmt { + struct generic_fmt generic; + struct arith_fmt arith; + struct ldr_str_fmt ldr_str; + struct block_fmt block; + struct branch_fmt branch; + struct swi_fmt swi; + unsigned long ins; +}; + +struct opcode { + unsigned long value, mask; /* recognise instruction if (op&mask)==value */ + char *assembler; /* how to disassemble this instruction */ +}; + +/* format of the assembler string : + + %% % + %<bitfield>d print the bitfield in decimal + %<bitfield>x print the bitfield in hex + %<bitfield>r print as an ARM register + %<bitfield>f print a floating point constant if >7 else an fp register + %c print condition code (always bits 28-31) + %P print floating point precision in arithmetic insn + %Q print floating point precision in ldf/stf insn + %R print floating point rounding mode + %<bitnum>'c print specified char iff bit is one + %<bitnum>`c print specified char iff bit is zero + %<bitnum>?ab print a if bit is one else print b + %p print 'p' iff bits 12-15 are 15 + %o print operand2 (immediate or register + shift) + %a print address for ldr/str instruction + %b print branch destination + %A print address for ldc/stc/ldf/stf instruction + %m print register mask for ldm/stm instruction +*/ + +static struct opcode opcodes[] = { + /* ARM instructions */ + 0x00000090, 0x0fe000f0, "mul%20's %12-15r, %16-19r, %0-3r", + 0x00200090, 0x0fe000f0, "mla%20's %12-15r, %16-19r, %0-3r, %8-11r", + 0x00000000, 0x0de00000, "and%c%20's %12-15r, %16-19r, %o", + 0x00200000, 0x0de00000, "eor%c%20's %12-15r, %16-19r, %o", + 0x00400000, 0x0de00000, "sub%c%20's %12-15r, %16-19r, %o", + 0x00600000, 0x0de00000, "rsb%c%20's %12-15r, %16-19r, %o", + 0x00800000, 0x0de00000, "add%c%20's %12-15r, %16-19r, %o", + 0x00a00000, 0x0de00000, "adc%c%20's %12-15r, %16-19r, %o", + 0x00c00000, 0x0de00000, "sbc%c%20's %12-15r, %16-19r, %o", + 0x00e00000, 0x0de00000, "rsc%c%20's %12-15r, %16-19r, %o", + 0x01000000, 0x0de00000, "tst%c%p %16-19r, %o", + 0x01200000, 0x0de00000, "teq%c%p %16-19r, %o", + 0x01400000, 0x0de00000, "cmp%c%p %16-19r, %o", + 0x01600000, 0x0de00000, "cmn%c%p %16-19r, %o", + 0x01800000, 0x0de00000, "orr%c%20's %12-15r, %16-19r, %o", + 0x01a00000, 0x0de00000, "mov%c%20's %12-15r, %o", + 0x01c00000, 0x0de00000, "bic%c%20's %12-15r, %16-19r, %o", + 0x01e00000, 0x0de00000, "mvn%c%20's %12-15r, %o", + 0x04000000, 0x0c100000, "str%c%22'b %12-15r, %a", + 0x04100000, 0x0c100000, "ldr%c%22'b %12-15r, %a", + 0x08000000, 0x0e100000, "stm%c%23?id%24?ba %16-19r%22`!, %m", + 0x08100000, 0x0e100000, "ldm%c%23?id%24?ba %16-19r%22`!, %m%22'^", + 0x0a000000, 0x0e000000, "b%c%24'l %b", + 0x0f000000, 0x0f000000, "swi%c %0-23x", + /* Floating point coprocessor instructions */ + 0x0e000100, 0x0ff08f10, "adf%c%P%R %12-14f, %16-18f, %0-3f", + 0x0e100100, 0x0ff08f10, "muf%c%P%R %12-14f, %16-18f, %0-3f", + 0x0e200100, 0x0ff08f10, "suf%c%P%R %12-14f, %16-18f, %0-3f", + 0x0e300100, 0x0ff08f10, "rsf%c%P%R %12-14f, %16-18f, %0-3f", + 0x0e400100, 0x0ff08f10, "dvf%c%P%R %12-14f, %16-18f, %0-3f", + 0x0e500100, 0x0ff08f10, "rdf%c%P%R %12-14f, %16-18f, %0-3f", + 0x0e600100, 0x0ff08f10, "pow%c%P%R %12-14f, %16-18f, %0-3f", + 0x0e700100, 0x0ff08f10, "rpw%c%P%R %12-14f, %16-18f, %0-3f", + 0x0e800100, 0x0ff08f10, "rmf%c%P%R %12-14f, %16-18f, %0-3f", + 0x0e900100, 0x0ff08f10, "fml%c%P%R %12-14f, %16-18f, %0-3f", + 0x0ea00100, 0x0ff08f10, "fdv%c%P%R %12-14f, %16-18f, %0-3f", + 0x0eb00100, 0x0ff08f10, "frd%c%P%R %12-14f, %16-18f, %0-3f", + 0x0ec00100, 0x0ff08f10, "pol%c%P%R %12-14f, %16-18f, %0-3f", + 0x0e008100, 0x0ff08f10, "mvf%c%P%R %12-14f, %0-3f", + 0x0e108100, 0x0ff08f10, "mnf%c%P%R %12-14f, %0-3f", + 0x0e208100, 0x0ff08f10, "abs%c%P%R %12-14f, %0-3f", + 0x0e308100, 0x0ff08f10, "rnd%c%P%R %12-14f, %0-3f", + 0x0e408100, 0x0ff08f10, "sqt%c%P%R %12-14f, %0-3f", + 0x0e508100, 0x0ff08f10, "log%c%P%R %12-14f, %0-3f", + 0x0e608100, 0x0ff08f10, "lgn%c%P%R %12-14f, %0-3f", + 0x0e708100, 0x0ff08f10, "exp%c%P%R %12-14f, %0-3f", + 0x0e808100, 0x0ff08f10, "sin%c%P%R %12-14f, %0-3f", + 0x0e908100, 0x0ff08f10, "cos%c%P%R %12-14f, %0-3f", + 0x0ea08100, 0x0ff08f10, "tan%c%P%R %12-14f, %0-3f", + 0x0eb08100, 0x0ff08f10, "asn%c%P%R %12-14f, %0-3f", + 0x0ec08100, 0x0ff08f10, "acs%c%P%R %12-14f, %0-3f", + 0x0ed08100, 0x0ff08f10, "atn%c%P%R %12-14f, %0-3f", + 0x0e000110, 0x0ff00f1f, "flt%c%P%R %16-18f, %12-15r", + 0x0e100110, 0x0fff0f98, "fix%c%R %12-15r, %0-2f", + 0x0e200110, 0x0fff0fff, "wfs%c %12-15r", + 0x0e300110, 0x0fff0fff, "rfs%c %12-15r", + 0x0e400110, 0x0fff0fff, "wfc%c %12-15r", + 0x0e500110, 0x0fff0fff, "rfc%c %12-15r", + 0x0e90f110, 0x0ff8fff0, "cmf%c %16-18f, %0-3f", + 0x0eb0f110, 0x0ff8fff0, "cnf%c %16-18f, %0-3f", + 0x0ed0f110, 0x0ff8fff0, "cmfe%c %16-18f, %0-3f", + 0x0ef0f110, 0x0ff8fff0, "cnfe%c %16-18f, %0-3f", + 0x0c000100, 0x0e100f00, "stf%c%Q %12-14f, %A", + 0x0c100100, 0x0e100f00, "ldf%c%Q %12-14f, %A", + /* Generic coprocessor instructions */ + 0x0e000000, 0x0f000010, "cdp%c %8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}", + 0x0e000010, 0x0f100010, "mrc%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}", + 0x0e100010, 0x0f100010, "mcr%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}", + 0x0c000000, 0x0e100000, "stc%c%22`l %8-11d, cr%12-15d, %A", + 0x0c100000, 0x0e100000, "ldc%c%22`l %8-11d, cr%12-15d, %A", + /* the rest */ + 0x00000000, 0x00000000, "undefined instruction %0-31x", +}; +#define N_OPCODES (sizeof opcodes / sizeof opcodes[0]) diff --git a/contrib/binutils/include/opcode/cgen.h b/contrib/binutils/include/opcode/cgen.h index ab59f24..0cff7c8 100644 --- a/contrib/binutils/include/opcode/cgen.h +++ b/contrib/binutils/include/opcode/cgen.h @@ -1,6 +1,6 @@ /* Header file for targets using CGEN: Cpu tools GENerator. -Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. +Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. This file is part of GDB, the GNU debugger, and the GNU Binutils. @@ -21,10 +21,23 @@ with this program; if not, write to the Free Software Foundation, Inc., #ifndef CGEN_H #define CGEN_H -/* Prepend the cpu name, defined in cpu-opc.h, and _cgen_ to symbol S. +/* ??? This file requires bfd.h but only to get bfd_vma. + Seems like an awful lot to require just to get such a fundamental type. + Perhaps the definition of bfd_vma can be moved outside of bfd.h. + Or perhaps one could duplicate its definition in another file. + Until such time, this file conditionally compiles definitions that require + bfd_vma using BFD_VERSION. */ + +/* Enums must be defined before they can be used. + Allow them to be used in struct definitions, even though the enum must + be defined elsewhere. + If CGEN_ARCH isn't defined, this file is being included by something other + than <arch>-desc.h. */ + +/* Prepend the arch name, defined in <arch>-desc.h, and _cgen_ to symbol S. The lack of spaces in the arg list is important for non-stdc systems. - This file is included by <cpu>-opc.h. - It can be included independently of cpu-opc.h, in which case the cpu + This file is included by <arch>-desc.h. + It can be included independently of <arch>-desc.h, in which case the arch dependent portions will be declared as "unknown_cgen_foo". */ #ifndef CGEN_SYM @@ -38,92 +51,156 @@ with this program; if not, write to the Free Software Foundation, Inc., /* The assembler syntax is made up of expressions (duh...). At the lowest level the values are mnemonics, register names, numbers, etc. Above that are subexpressions, if any (an example might be the - "effective address" in m68k cpus). At the second highest level are the - insns themselves. Above that are pseudo-insns, synthetic insns, and macros, - if any. -*/ + "effective address" in m68k cpus). Subexpressions are wip. + At the second highest level are the insns themselves. Above that are + pseudo-insns, synthetic insns, and macros, if any. */ /* Lots of cpu's have a fixed insn size, or one which rarely changes, and it's generally easier to handle these by treating the insn as an integer type, rather than an array of characters. So we allow targets - to control this. */ + to control this. When an integer type the value is in host byte order, + when an array of characters the value is in target byte order. */ -#ifdef CGEN_INT_INSN -typedef unsigned int cgen_insn_t; +typedef unsigned int CGEN_INSN_INT; +#if CGEN_INT_INSN_P +typedef CGEN_INSN_INT CGEN_INSN_BYTES; +typedef CGEN_INSN_INT *CGEN_INSN_BYTES_PTR; #else -typedef char * cgen_insn_t; +typedef unsigned char *CGEN_INSN_BYTES; +typedef unsigned char *CGEN_INSN_BYTES_PTR; #endif #ifdef __GNUC__ -#define CGEN_INLINE inline +#define CGEN_INLINE __inline__ #else #define CGEN_INLINE #endif -/* Perhaps we should just use bfd.h, but it's not clear - one would want to require that yet. */ enum cgen_endian { CGEN_ENDIAN_UNKNOWN, CGEN_ENDIAN_LITTLE, CGEN_ENDIAN_BIG }; + +/* Forward decl. */ + +typedef struct cgen_insn CGEN_INSN; + +/* Opaque pointer version for use by external world. */ + +typedef struct cgen_cpu_desc *CGEN_CPU_DESC; /* Attributes. - Attributes are used to describe various random things. */ + Attributes are used to describe various random things associated with + an object (ifield, hardware, operand, insn, whatever) and are specified + as name/value pairs. + Integer attributes computed at compile time are currently all that's + supported, though adding string attributes and run-time computation is + straightforward. Integer attribute values are always host int's + (signed or unsigned). For portability, this means 32 bits. + Integer attributes are further categorized as boolean, bitset, integer, + and enum types. Boolean attributes appear frequently enough that they're + recorded in one host int. This limits the maximum number of boolean + attributes to 32, though that's a *lot* of attributes. */ + +/* Type of attribute values. */ + +typedef int CGEN_ATTR_VALUE_TYPE; /* Struct to record attribute information. */ + typedef struct { - unsigned char num_nonbools; + /* Boolean attributes. */ unsigned int bool; - unsigned int nonbool[1]; + /* Non-boolean integer attributes. */ + CGEN_ATTR_VALUE_TYPE nonbool[1]; } CGEN_ATTR; /* Define a structure member for attributes with N non-boolean entries. - The attributes are sorted so that the non-boolean ones come first. - num_nonbools: count of nonboolean attributes - bool: values of boolean attributes - nonbool: values of non-boolean attributes - There is a maximum of 32 attributes total. */ + There is no maximum number of non-boolean attributes. + There is a maximum of 32 boolean attributes (since they are all recorded + in one host int). */ + #define CGEN_ATTR_TYPE(n) \ -const struct { unsigned char num_nonbools; \ - unsigned int bool; \ - unsigned int nonbool[(n) ? (n) : 1]; } +struct { unsigned int bool; \ + CGEN_ATTR_VALUE_TYPE nonbool[(n) ? (n) : 1]; } + +/* Return the boolean attributes. */ + +#define CGEN_ATTR_BOOLS(a) ((a)->bool) + +/* Non-boolean attribute numbers are offset by this much. */ + +#define CGEN_ATTR_NBOOL_OFFSET 32 + +/* Given a boolean attribute number, return its mask. */ -/* Given an attribute number, return its mask. */ #define CGEN_ATTR_MASK(attr) (1 << (attr)) /* Return the value of boolean attribute ATTR in ATTRS. */ -#define CGEN_BOOL_ATTR(attrs, attr) \ -((CGEN_ATTR_MASK (attr) & (attrs)) != 0) + +#define CGEN_BOOL_ATTR(attrs, attr) ((CGEN_ATTR_MASK (attr) & (attrs)) != 0) /* Return value of attribute ATTR in ATTR_TABLE for OBJ. - OBJ is a pointer to the entity that has the attributes. - It's not used at present but is reserved for future purposes. */ + OBJ is a pointer to the entity that has the attributes + (??? not used at present but is reserved for future purposes - eventually + the goal is to allow recording attributes in source form and computing + them lazily at runtime, not sure of the details yet). */ + #define CGEN_ATTR_VALUE(obj, attr_table, attr) \ -((unsigned int) (attr) < (attr_table)->num_nonbools \ - ? ((attr_table)->nonbool[attr]) \ - : (((attr_table)->bool & (1 << (attr))) != 0)) +((unsigned int) (attr) < CGEN_ATTR_NBOOL_OFFSET \ + ? ((CGEN_ATTR_BOOLS (attr_table) & CGEN_ATTR_MASK (attr)) != 0) \ + : ((attr_table)->nonbool[(attr) - CGEN_ATTR_NBOOL_OFFSET])) /* Attribute name/value tables. - These are used to assist parsing of descriptions at runtime. */ + These are used to assist parsing of descriptions at run-time. */ typedef struct { const char * name; - int value; + CGEN_ATTR_VALUE_TYPE value; } CGEN_ATTR_ENTRY; -/* For each domain (fld,operand,insn), list of attributes. */ +/* For each domain (ifld,hw,operand,insn), list of attributes. */ typedef struct { - const char * name; - /* NULL for boolean attributes. */ + const char * name; + const CGEN_ATTR_ENTRY * dfault; const CGEN_ATTR_ENTRY * vals; } CGEN_ATTR_TABLE; +/* Instruction set variants. */ + +typedef struct { + const char *name; + + /* Default instruction size (in bits). + This is used by the assembler when it encounters an unknown insn. */ + unsigned int default_insn_bitsize; + + /* Base instruction size (in bits). + For non-LIW cpus this is generally the length of the smallest insn. + For LIW cpus its wip (work-in-progress). For the m32r its 32. */ + unsigned int base_insn_bitsize; + + /* Minimum/maximum instruction size (in bits). */ + unsigned int min_insn_bitsize; + unsigned int max_insn_bitsize; +} CGEN_ISA; + +/* Machine variants. */ + +typedef struct { + const char *name; + /* The argument to bfd_arch_info->scan. */ + const char *bfd_name; + /* one of enum mach_attr */ + int num; +} CGEN_MACH; + /* Parse result (also extraction result). The result of parsing an insn is stored here. @@ -147,95 +224,115 @@ typedef struct cgen_fields CGEN_FIELDS; if it ever gets inlined. On architectures where insns all have the same size, may wish to detect that and make this macro a constant - to allow further optimizations. */ + #define CGEN_FIELDS_BITSIZE(fields) ((fields)->length) +/* Extraction support for variable length insn sets. */ + +/* When disassembling we don't know the number of bytes to read at the start. + So the first CGEN_BASE_INSN_SIZE bytes are read at the start and the rest + are read when needed. This struct controls this. It is basically the + disassemble_info stuff, except that we provide a cache for values already + read (since bytes can typically be read several times to fetch multiple + operands that may be in them), and that extraction of fields is needed + in contexts other than disassembly. */ + +typedef struct { + /* A pointer to the disassemble_info struct. + We don't require dis-asm.h so we use PTR for the type here. + If NULL, BYTES is full of valid data (VALID == -1). */ + PTR dis_info; + /* Points to a working buffer of sufficient size. */ + unsigned char *insn_bytes; + /* Mask of bytes that are valid in INSN_BYTES. */ + unsigned int valid; +} CGEN_EXTRACT_INFO; + /* Associated with each insn or expression is a set of "handlers" for - performing operations like parsing, printing, etc. */ - -/* Forward decl. */ -typedef struct cgen_insn CGEN_INSN; + performing operations like parsing, printing, etc. These require a bfd_vma + value to be passed around but we don't want all applications to need bfd.h. + So this stuff is only provided if bfd.h has been included. */ /* Parse handler. - The first argument is a pointer to a struct describing the insn being - parsed. - The second argument is a pointer to a pointer to the text being parsed. - The third argument is a pointer to a cgen_fields struct - in which the results are placed. - If the expression is successfully parsed, the pointer to the text is - updated. If not it is left alone. + CD is a cpu table descriptor. + INSN is a pointer to a struct describing the insn being parsed. + STRP is a pointer to a pointer to the text being parsed. + FIELDS is a pointer to a cgen_fields struct in which the results are placed. + If the expression is successfully parsed, *STRP is updated. + If not it is left alone. The result is NULL if success or an error message. */ -typedef const char * (cgen_parse_fn) PARAMS ((const struct cgen_insn *, - const char **, - CGEN_FIELDS *)); +typedef const char * (cgen_parse_fn) + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *insn_, + const char **strp_, CGEN_FIELDS *fields_)); + +/* Insert handler. + CD is a cpu table descriptor. + INSN is a pointer to a struct describing the insn being parsed. + FIELDS is a pointer to a cgen_fields struct from which the values + are fetched. + INSNP is a pointer to a buffer in which to place the insn. + PC is the pc value of the insn. + The result is an error message or NULL if success. */ + +#ifdef BFD_VERSION +typedef const char * (cgen_insert_fn) + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *insn_, + CGEN_FIELDS *fields_, CGEN_INSN_BYTES_PTR insnp_, + bfd_vma pc_)); +#else +typedef const char * (cgen_insert_fn) (); +#endif + +/* Extract handler. + CD is a cpu table descriptor. + INSN is a pointer to a struct describing the insn being parsed. + The second argument is a pointer to a struct controlling extraction + (only used for variable length insns). + EX_INFO is a pointer to a struct for controlling reading of further + bytes for the insn. + BASE_INSN is the first CGEN_BASE_INSN_SIZE bytes (host order). + FIELDS is a pointer to a cgen_fields struct in which the results are placed. + PC is the pc value of the insn. + The result is the length of the insn in bits or zero if not recognized. */ + +#ifdef BFD_VERSION +typedef int (cgen_extract_fn) + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *insn_, + CGEN_EXTRACT_INFO *ex_info_, CGEN_INSN_INT base_insn_, + CGEN_FIELDS *fields_, bfd_vma pc_)); +#else +typedef int (cgen_extract_fn) (); +#endif /* Print handler. - The first argument is a pointer to the disassembly info. + CD is a cpu table descriptor. + INFO is a pointer to the disassembly info. Eg: disassemble_info. It's defined as `PTR' so this file can be included without dis-asm.h. - The second argument is a pointer to a struct describing the insn being - printed. - The third argument is a pointer to a cgen_fields struct. - The fourth argument is the pc value of the insn. - The fifth argument is the length of the insn, in bytes. */ -/* Don't require bfd.h unnecessarily. */ + INSN is a pointer to a struct describing the insn being printed. + FIELDS is a pointer to a cgen_fields struct. + PC is the pc value of the insn. + LEN is the length of the insn, in bits. */ + #ifdef BFD_VERSION -typedef void (cgen_print_fn) PARAMS ((PTR, const struct cgen_insn *, - CGEN_FIELDS *, bfd_vma, int)); +typedef void (cgen_print_fn) + PARAMS ((CGEN_CPU_DESC, PTR info_, const CGEN_INSN *insn_, + CGEN_FIELDS *fields_, bfd_vma pc_, int len_)); #else typedef void (cgen_print_fn) (); #endif -/* Insert handler. - The first argument is a pointer to a struct describing the insn being - parsed. - The second argument is a pointer to a cgen_fields struct - from which the values are fetched. - The third argument is a pointer to a buffer in which to place the insn. - The result is an error message or NULL if success. */ -typedef const char * (cgen_insert_fn) PARAMS ((const struct cgen_insn *, - CGEN_FIELDS *, cgen_insn_t *)); +/* Parse/insert/extract/print handlers. -/* Extract handler. - The first argument is a pointer to a struct describing the insn being - parsed. - The second argument is a pointer to a struct controlling extraction - (only used for variable length insns). - The third argument is the first CGEN_BASE_INSN_SIZE bytes. - The fourth argument is a pointer to a cgen_fields struct - in which the results are placed. - The result is the length of the insn or zero if not recognized. */ -typedef int (cgen_extract_fn) PARAMS ((const struct cgen_insn *, - void *, cgen_insn_t, - CGEN_FIELDS *)); - -/* The `parse' and `insert' fields are indices into these tables. - The elements are pointer to specialized handler functions. - Element 0 is special, it means use the default handler. */ -extern cgen_parse_fn * CGEN_SYM (parse_handlers) []; -#define CGEN_PARSE_FN(x) (CGEN_SYM (parse_handlers)[(x)->base.parse]) -extern cgen_insert_fn * CGEN_SYM (insert_handlers) []; -#define CGEN_INSERT_FN(x) (CGEN_SYM (insert_handlers)[(x)->base.insert]) - -/* Likewise for the `extract' and `print' fields. */ -extern cgen_extract_fn * CGEN_SYM (extract_handlers) []; -#define CGEN_EXTRACT_FN(x) (CGEN_SYM (extract_handlers)[(x)->base.extract]) -extern cgen_print_fn * CGEN_SYM (print_handlers) []; -#define CGEN_PRINT_FN(x) (CGEN_SYM (print_handlers)[(x)->base.print]) - -/* Base class of parser/printer. - (Don't read too much into the use of the phrase "base class". - It's a name I'm using to organize my thoughts.) + Indices into the handler tables. + We could use pointers here instead, but 90% of them are generally identical + and that's a lot of redundant data. Making these unsigned char indices + into tables of pointers saves a bit of space. + Using indices also keeps assembler code out of the disassembler and + vice versa. */ - Instructions and expressions all share this data in common. - It's a collection of the common elements needed to parse, insert, extract, - and print each of them. */ - -struct cgen_base +struct cgen_opcode_handler { - /* Indices into the handler tables. - We could use pointers here instead, but in the case of the insn table, - 90% of them would be identical and that's a lot of redundant data. - 0 means use the default (what the default is is up to the code). */ unsigned char parse, insert, extract, print; }; @@ -246,11 +343,12 @@ struct cgen_base Not that one would necessarily want to do that but rather that it helps keep a clean interface. The interface will obviously be slanted towards GAS, but at least it's a start. + ??? Note that one possible user of the assembler besides GAS is GDB. Parsing is controlled by the assembler which calls CGEN_SYM (assemble_insn). If it can parse and build the entire insn it doesn't call back to the assembler. If it needs/wants to call back - to the assembler, (*cgen_parse_operand_fn) is called which can either + to the assembler, cgen_parse_operand_fn is called which can either - return a number to be inserted in the insn - return a "register" value to be inserted @@ -263,6 +361,7 @@ struct cgen_base The parsed value is stored in the bfd_vma *. */ /* Values for indicating what the caller wants. */ + enum cgen_parse_operand_type { CGEN_PARSE_OPERAND_INIT, @@ -270,8 +369,8 @@ enum cgen_parse_operand_type CGEN_PARSE_OPERAND_ADDRESS }; -/* Values for indicating what was parsed. - ??? Not too useful at present but in time. */ +/* Values for indicating what was parsed. */ + enum cgen_parse_operand_result { CGEN_PARSE_OPERAND_RESULT_NUMBER, @@ -280,49 +379,23 @@ enum cgen_parse_operand_result CGEN_PARSE_OPERAND_RESULT_ERROR }; -/* Don't require bfd.h unnecessarily. */ -#ifdef BFD_VERSION -extern const char * (*cgen_parse_operand_fn) - PARAMS ((enum cgen_parse_operand_type, const char **, int, int, +#ifdef BFD_VERSION /* Don't require bfd.h unnecessarily. */ +typedef const char * (cgen_parse_operand_fn) + PARAMS ((CGEN_CPU_DESC, + enum cgen_parse_operand_type, const char **, int, int, enum cgen_parse_operand_result *, bfd_vma *)); +#else +typedef const char * (cgen_parse_operand_fn) (); #endif -/* Called before trying to match a table entry with the insn. */ -void cgen_init_parse_operand PARAMS ((void)); - -/* Called from <cpu>-asm.c to initialize operand parsing. */ +/* Set the cgen_parse_operand_fn callback. */ -/* These are GAS specific. They're not here as part of the interface, - but rather that we need to put them somewhere. */ +extern void cgen_set_parse_operand_fn + PARAMS ((CGEN_CPU_DESC, cgen_parse_operand_fn)); -/* Call this from md_assemble to initialize the assembler callback. */ -void cgen_asm_init_parse PARAMS ((void)); - -/* Don't require bfd.h unnecessarily. */ -#ifdef BFD_VERSION -/* The result is an error message or NULL for success. - The parsed value is stored in the bfd_vma *. */ -const char * cgen_parse_operand PARAMS ((enum cgen_parse_operand_type, - const char **, int, int, - enum cgen_parse_operand_result *, - bfd_vma *)); -#endif +/* Called before trying to match a table entry with the insn. */ -void cgen_save_fixups PARAMS ((void)); -void cgen_restore_fixups PARAMS ((void)); -void cgen_swap_fixups PARAMS ((void)); - -/* Add a register to the assembler's hash table. - This makes lets GAS parse registers for us. - ??? This isn't currently used, but it could be in the future. */ -void cgen_asm_record_register PARAMS ((char *, int)); - -/* After CGEN_SYM (assemble_insn) is done, this is called to - output the insn and record any fixups. The address of the - assembled instruction is returned in case it is needed by - the caller. */ -char * cgen_asm_finish_insn PARAMS ((const struct cgen_insn *, cgen_insn_t *, - unsigned int)); +extern void cgen_init_parse_operand PARAMS ((CGEN_CPU_DESC)); /* Operand values (keywords, integers, symbols, etc.) */ @@ -330,23 +403,56 @@ char * cgen_asm_finish_insn PARAMS ((const struct cgen_insn *, cgen_insn_t *, enum cgen_asm_type { - CGEN_ASM_KEYWORD, CGEN_ASM_MAX + CGEN_ASM_NONE, CGEN_ASM_KEYWORD, CGEN_ASM_MAX }; +#ifndef CGEN_ARCH +enum cgen_hw_type { CGEN_HW_MAX }; +#endif + /* List of hardware elements. */ -typedef struct cgen_hw_entry +typedef struct { - /* The type of this entry, one of `enum hw_type'. - This is an int and not the enum as the latter may not be declared yet. */ - int type; - const struct cgen_hw_entry * next; - char * name; - enum cgen_asm_type asm_type; - PTR asm_data; + char *name; + enum cgen_hw_type type; + /* There is currently no example where both index specs and value specs + are required, so for now both are clumped under "asm_data". */ + enum cgen_asm_type asm_type; + PTR asm_data; +#ifndef CGEN_HW_NBOOL_ATTRS +#define CGEN_HW_NBOOL_ATTRS 1 +#endif + CGEN_ATTR_TYPE (CGEN_HW_NBOOL_ATTRS) attrs; +#define CGEN_HW_ATTRS(hw) (&(hw)->attrs) } CGEN_HW_ENTRY; -const CGEN_HW_ENTRY * cgen_hw_lookup PARAMS ((const char *)); +/* Return value of attribute ATTR in HW. */ + +#define CGEN_HW_ATTR_VALUE(hw, attr) \ +CGEN_ATTR_VALUE ((hw), CGEN_HW_ATTRS (hw), (attr)) + +/* Table of hardware elements for selected mach, computed at runtime. + enum cgen_hw_type is an index into this table (specifically `entries'). */ + +typedef struct { + /* Pointer to null terminated table of all compiled in entries. */ + const CGEN_HW_ENTRY *init_entries; + unsigned int entry_size; /* since the attribute member is variable sized */ + /* Array of all entries, initial and run-time added. */ + const CGEN_HW_ENTRY **entries; + /* Number of elements in `entries'. */ + unsigned int num_entries; + /* For now, xrealloc is called each time a new entry is added at runtime. + ??? May wish to keep track of some slop to reduce the number of calls to + xrealloc, except that there's unlikely to be many and not expected to be + in speed critical code. */ +} CGEN_HW_TABLE; + +extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_name + PARAMS ((CGEN_CPU_DESC, const char *)); +extern const CGEN_HW_ENTRY * cgen_hw_lookup_by_num + PARAMS ((CGEN_CPU_DESC, int)); /* This struct is used to describe things like register names, etc. */ @@ -364,7 +470,9 @@ typedef struct cgen_keyword_entry This should, but technically needn't, appear last. It is a variable sized array in that one architecture may have 1 nonbool attribute and another may have more. Having this last means the non-architecture specific code - needn't care. */ + needn't care. The goal is to eventually record + attributes in their raw form, evaluate them at run-time, and cache the + values, so this worry will go away anyway. */ /* ??? Moving this last should be done by treating keywords like insn lists and moving the `next' fields into a CGEN_KEYWORD_LIST struct. */ /* FIXME: Not used yet. */ @@ -373,6 +481,8 @@ typedef struct cgen_keyword_entry #endif CGEN_ATTR_TYPE (CGEN_KEYWORD_NBOOL_ATTRS) attrs; + /* ??? Putting these here means compiled in entries can't be const. + Not a really big deal, but something to consider. */ /* Next name hash table entry. */ struct cgen_keyword_entry *next_name; /* Next value hash table entry. */ @@ -382,27 +492,27 @@ typedef struct cgen_keyword_entry /* Top level struct for describing a set of related keywords (e.g. register names). - This struct supports runtime entry of new values, and hashed lookups. */ + This struct supports run-time entry of new values, and hashed lookups. */ typedef struct cgen_keyword { /* Pointer to initial [compiled in] values. */ - CGEN_KEYWORD_ENTRY * init_entries; + CGEN_KEYWORD_ENTRY *init_entries; /* Number of entries in `init_entries'. */ unsigned int num_init_entries; /* Hash table used for name lookup. */ - CGEN_KEYWORD_ENTRY ** name_hash_table; + CGEN_KEYWORD_ENTRY **name_hash_table; /* Hash table used for value lookup. */ - CGEN_KEYWORD_ENTRY ** value_hash_table; + CGEN_KEYWORD_ENTRY **value_hash_table; /* Number of entries in the hash_tables. */ unsigned int hash_table_size; /* Pointer to null keyword "" entry if present. */ - const CGEN_KEYWORD_ENTRY * null_entry; + const CGEN_KEYWORD_ENTRY *null_entry; } CGEN_KEYWORD; /* Structure used for searching. */ @@ -410,49 +520,57 @@ typedef struct cgen_keyword typedef struct { /* Table being searched. */ - const CGEN_KEYWORD * table; + const CGEN_KEYWORD *table; /* Specification of what is being searched for. */ - const char * spec; + const char *spec; /* Current index in hash table. */ unsigned int current_hash; /* Current element in current hash chain. */ - CGEN_KEYWORD_ENTRY * current_entry; + CGEN_KEYWORD_ENTRY *current_entry; } CGEN_KEYWORD_SEARCH; /* Lookup a keyword from its name. */ -const CGEN_KEYWORD_ENTRY * cgen_keyword_lookup_name + +const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_name PARAMS ((CGEN_KEYWORD *, const char *)); + /* Lookup a keyword from its value. */ -const CGEN_KEYWORD_ENTRY * cgen_keyword_lookup_value + +const CGEN_KEYWORD_ENTRY *cgen_keyword_lookup_value PARAMS ((CGEN_KEYWORD *, int)); + /* Add a keyword. */ + void cgen_keyword_add PARAMS ((CGEN_KEYWORD *, CGEN_KEYWORD_ENTRY *)); + /* Keyword searching. This can be used to retrieve every keyword, or a subset. */ + CGEN_KEYWORD_SEARCH cgen_keyword_search_init PARAMS ((CGEN_KEYWORD *, const char *)); const CGEN_KEYWORD_ENTRY *cgen_keyword_search_next PARAMS ((CGEN_KEYWORD_SEARCH *)); /* Operand value support routines. */ -/* FIXME: some of the long's here will need to be bfd_vma or some such. */ - -const char * cgen_parse_keyword PARAMS ((const char **, - CGEN_KEYWORD *, - long *)); -const char * cgen_parse_signed_integer PARAMS ((const char **, int, long *)); -const char * cgen_parse_unsigned_integer PARAMS ((const char **, int, - unsigned long *)); -const char * cgen_parse_address PARAMS ((const char **, int, int, - enum cgen_parse_operand_result *, - long *)); -const char * cgen_validate_signed_integer PARAMS ((long, long, long)); -const char * cgen_validate_unsigned_integer PARAMS ((unsigned long, - unsigned long, - unsigned long)); + +extern const char *cgen_parse_keyword + PARAMS ((CGEN_CPU_DESC, const char **, CGEN_KEYWORD *, long *)); +#ifdef BFD_VERSION /* Don't require bfd.h unnecessarily. */ +extern const char *cgen_parse_signed_integer + PARAMS ((CGEN_CPU_DESC, const char **, int, long *)); +extern const char *cgen_parse_unsigned_integer + PARAMS ((CGEN_CPU_DESC, const char **, int, unsigned long *)); +extern const char *cgen_parse_address + PARAMS ((CGEN_CPU_DESC, const char **, int, int, + enum cgen_parse_operand_result *, bfd_vma *)); +extern const char *cgen_validate_signed_integer + PARAMS ((long, long, long)); +extern const char *cgen_validate_unsigned_integer + PARAMS ((unsigned long, unsigned long, unsigned long)); +#endif /* Operand modes. */ @@ -462,35 +580,47 @@ const char * cgen_validate_unsigned_integer PARAMS ((unsigned long, to <arch>-opc.h, or add a hook. */ enum cgen_mode { - CGEN_MODE_VOID, /* FIXME: rename simulator's VM to VOID */ + CGEN_MODE_VOID, /* ??? rename simulator's VM to VOID? */ CGEN_MODE_BI, CGEN_MODE_QI, CGEN_MODE_HI, CGEN_MODE_SI, CGEN_MODE_DI, CGEN_MODE_UBI, CGEN_MODE_UQI, CGEN_MODE_UHI, CGEN_MODE_USI, CGEN_MODE_UDI, CGEN_MODE_SF, CGEN_MODE_DF, CGEN_MODE_XF, CGEN_MODE_TF, + CGEN_MODE_TARGET_MAX, + CGEN_MODE_INT, CGEN_MODE_UINT, CGEN_MODE_MAX }; /* FIXME: Until simulator is updated. */ + #define CGEN_MODE_VM CGEN_MODE_VOID +/* Operands. */ + +#ifndef CGEN_ARCH +enum cgen_operand_type { CGEN_OPERAND_MAX }; +#endif + +/* "nil" indicator for the operand instance table */ +#define CGEN_OPERAND_NIL CGEN_OPERAND_MAX + /* This struct defines each entry in the operand table. */ -typedef struct cgen_operand +typedef struct { /* Name as it appears in the syntax string. */ - char * name; + char *name; + + /* Operand type. */ + enum cgen_operand_type type; /* The hardware element associated with this operand. */ - const CGEN_HW_ENTRY *hw; + enum cgen_hw_type hw_type; /* FIXME: We don't yet record ifield definitions, which we should. When we do it might make sense to delete start/length (since they will be duplicated in the ifield's definition) and replace them with a - pointer to the ifield entry. Note that as more complicated situations - need to be handled, going more and more with an OOP paradigm will help - keep the complication under control. Of course, this was the goal from - the start, but getting there in one step was too much too soon. */ + pointer to the ifield entry. */ - /* Bit position (msb of first byte = bit 0). + /* Bit position. This is just a hint, and may be unused in more complex operands. May be unused for a modifier. */ unsigned char start; @@ -510,7 +640,9 @@ typedef struct cgen_operand This should, but technically needn't, appear last. It is a variable sized array in that one architecture may have 1 nonbool attribute and another may have more. Having this last means the non-architecture specific code - needn't care, now or tomorrow. */ + needn't care, now or tomorrow. The goal is to eventually record + attributes in their raw form, evaluate them at run-time, and cache the + values, so this worry will go away anyway. */ #ifndef CGEN_OPERAND_NBOOL_ATTRS #define CGEN_OPERAND_NBOOL_ATTRS 1 #endif @@ -519,25 +651,32 @@ typedef struct cgen_operand } CGEN_OPERAND; /* Return value of attribute ATTR in OPERAND. */ -#define CGEN_OPERAND_ATTR(operand, attr) \ -CGEN_ATTR_VALUE (operand, CGEN_OPERAND_ATTRS (operand), attr) - -/* The operand table is currently a very static entity. */ -extern const CGEN_OPERAND CGEN_SYM (operand_table)[]; -enum cgen_operand_type; - -#define CGEN_OPERAND_INDEX(operand) ((int) ((operand) - CGEN_SYM (operand_table))) -/* FIXME: Rename, cpu-opc.h defines this as the typedef of the enum. */ -#define CGEN_OPERAND_TYPE(operand) ((enum cgen_operand_type) CGEN_OPERAND_INDEX (operand)) -#define CGEN_OPERAND_ENTRY(n) (& CGEN_SYM (operand_table) [n]) - -/* Types of parse/insert/extract/print cover-fn handlers. */ -/* FIXME: move opindex first to match caller. */ -/* FIXME: also need types of insert/extract/print fns. */ -/* FIXME: not currently used as type of 3rd arg varies. */ -typedef const char * (CGEN_PARSE_OPERAND_FN) PARAMS ((const char **, int, - long *)); +#define CGEN_OPERAND_ATTR_VALUE(operand, attr) \ +CGEN_ATTR_VALUE ((operand), CGEN_OPERAND_ATTRS (operand), (attr)) + +/* Table of operands for selected mach/isa, computed at runtime. + enum cgen_operand_type is an index into this table (specifically + `entries'). */ + +typedef struct { + /* Pointer to null terminated table of all compiled in entries. */ + const CGEN_OPERAND *init_entries; + unsigned int entry_size; /* since the attribute member is variable sized */ + /* Array of all entries, initial and run-time added. */ + const CGEN_OPERAND **entries; + /* Number of elements in `entries'. */ + unsigned int num_entries; + /* For now, xrealloc is called each time a new entry is added at runtime. + ??? May wish to keep track of some slop to reduce the number of calls to + xrealloc, except that there's unlikely to be many and not expected to be + in speed critical code. */ +} CGEN_OPERAND_TABLE; + +extern const CGEN_OPERAND * cgen_operand_lookup_by_name + PARAMS ((CGEN_CPU_DESC, const char *)); +extern const CGEN_OPERAND * cgen_operand_lookup_by_num + PARAMS ((CGEN_CPU_DESC, int)); /* Instruction operand instances. @@ -545,35 +684,47 @@ typedef const char * (CGEN_PARSE_OPERAND_FN) PARAMS ((const char **, int, written are recorded. */ /* The type of the instance. */ -enum cgen_operand_instance_type { + +enum cgen_opinst_type { /* End of table marker. */ - CGEN_OPERAND_INSTANCE_END = 0, - CGEN_OPERAND_INSTANCE_INPUT, CGEN_OPERAND_INSTANCE_OUTPUT + CGEN_OPINST_END = 0, + CGEN_OPINST_INPUT, CGEN_OPINST_OUTPUT }; typedef struct { - /* The type of this operand. */ - enum cgen_operand_instance_type type; -#define CGEN_OPERAND_INSTANCE_TYPE(opinst) ((opinst)->type) + /* Input or output indicator. */ + enum cgen_opinst_type type; + + /* Name of operand. */ + const char *name; /* The hardware element referenced. */ - const CGEN_HW_ENTRY *hw; -#define CGEN_OPERAND_INSTANCE_HW(opinst) ((opinst)->hw) + enum cgen_hw_type hw_type; /* The mode in which the operand is being used. */ enum cgen_mode mode; -#define CGEN_OPERAND_INSTANCE_MODE(opinst) ((opinst)->mode) - /* The operand table entry or NULL if there is none (i.e. an explicit - hardware reference). */ - const CGEN_OPERAND *operand; -#define CGEN_OPERAND_INSTANCE_OPERAND(opinst) ((opinst)->operand) + /* The operand table entry CGEN_OPERAND_NIL if there is none + (i.e. an explicit hardware reference). */ + enum cgen_operand_type op_type; - /* If `operand' is NULL, the index (e.g. into array of registers). */ + /* If `operand' is "nil", the index (e.g. into array of registers). */ int index; -#define CGEN_OPERAND_INSTANCE_INDEX(opinst) ((opinst)->index) -} CGEN_OPERAND_INSTANCE; + + /* Attributes. + ??? This perhaps should be a real attribute struct but there's + no current need, so we save a bit of space and just have a set of + flags. The interface is such that this can easily be made attributes + should it prove useful. */ + unsigned int attrs; +#define CGEN_OPINST_ATTRS(opinst) ((opinst)->attrs) +/* Return value of attribute ATTR in OPINST. */ +#define CGEN_OPINST_ATTR(opinst, attr) \ +((CGEN_OPINST_ATTRS (opinst) & (attr)) != 0) +/* Operand is conditionally referenced (read/written). */ +#define CGEN_OPINST_COND_REF 1 +} CGEN_OPINST; /* Syntax string. @@ -604,13 +755,59 @@ typedef struct However, we treat mnemonics as just another operand of the instruction. A value of 1 means "this is where the mnemonic appears". 1 isn't special other than it's a non-printable ASCII char. */ + #define CGEN_SYNTAX_MNEMONIC 1 #define CGEN_SYNTAX_MNEMONIC_P(ch) ((ch) == CGEN_SYNTAX_MNEMONIC) +/* Instruction fields. + + ??? We currently don't allow adding fields at run-time. + Easy to fix when needed. */ + +typedef struct cgen_ifld { + /* Enum of ifield. */ + int num; +#define CGEN_IFLD_NUM(f) ((f)->num) + + /* Name of the field, distinguishes it from all other fields. */ + const char *name; +#define CGEN_IFLD_NAME(f) ((f)->name) + + /* Default offset, in bits, from the start of the insn to the word + containing the field. */ + int word_offset; +#define CGEN_IFLD_WORD_OFFSET(f) ((f)->word_offset) + + /* Default length of the word containing the field. */ + int word_size; +#define CGEN_IFLD_WORD_SIZE(f) ((f)->word_size) + + /* Default starting bit number. + Whether lsb=0 or msb=0 is determined by CGEN_INSN_LSB0_P. */ + int start; +#define CGEN_IFLD_START(f) ((f)->start) + + /* Length of the field, in bits. */ + int length; +#define CGEN_IFLD_LENGTH(f) ((f)->length) + +#ifndef CGEN_IFLD_NBOOL_ATTRS +#define CGEN_IFLD_NBOOL_ATTRS 1 +#endif + CGEN_ATTR_TYPE (CGEN_IFLD_NBOOL_ATTRS) attrs; +#define CGEN_IFLD_ATTRS(f) (&(f)->attrs) +} CGEN_IFLD; + +/* Return value of attribute ATTR in IFLD. */ +#define CGEN_IFLD_ATTR_VALUE(ifld, attr) \ +CGEN_ATTR_VALUE ((ifld), CGEN_IFLD_ATTRS (ifld), (attr)) + +/* Instruction data. */ + /* Instruction formats. Instructions are grouped by format. Associated with an instruction is its - format. Each opcode table entry contains a format table entry. + format. Each insn's opcode table entry contains a format table entry. ??? There is usually very few formats compared with the number of insns, so one can reduce the size of the opcode table by recording the format table as a separate entity. Given that we currently don't, format table entries @@ -620,82 +817,174 @@ typedef struct ??? Support for variable length ISA's is wip. */ +/* Accompanying each iformat description is a list of its fields. */ + +typedef struct { + const CGEN_IFLD *ifld; +#define CGEN_IFMT_IFLD_IFLD(ii) ((ii)->ifld) +} CGEN_IFMT_IFLD; + +#ifndef CGEN_MAX_IFMT_OPERANDS +#define CGEN_MAX_IFMT_OPERANDS 1 +#endif + typedef struct { /* Length that MASK and VALUE have been calculated to [VALUE is recorded elsewhere]. - Normally it is CGEN_BASE_INSN_BITSIZE. On [V]LIW architectures where - the base insn size may be larger than the size of an insn, this field is - less than CGEN_BASE_INSN_BITSIZE. */ + Normally it is base_insn_bitsize. On [V]LIW architectures where the base + insn size may be larger than the size of an insn, this field is less than + base_insn_bitsize. */ unsigned char mask_length; +#define CGEN_IFMT_MASK_LENGTH(ifmt) ((ifmt)->mask_length) /* Total length of instruction, in bits. */ unsigned char length; +#define CGEN_IFMT_LENGTH(ifmt) ((ifmt)->length) /* Mask to apply to the first MASK_LENGTH bits. Each insn's value is stored with the insn. The first step in recognizing an insn for disassembly is (opcode & mask) == value. */ - unsigned int mask; -} CGEN_FORMAT; - -/* This struct defines each entry in the instruction table. */ + CGEN_INSN_INT mask; +#define CGEN_IFMT_MASK(ifmt) ((ifmt)->mask) -struct cgen_insn + /* Instruction fields. + +1 for trailing NULL. */ + CGEN_IFMT_IFLD iflds[CGEN_MAX_IFMT_OPERANDS + 1]; +#define CGEN_IFMT_IFLDS(ifmt) ((ifmt)->iflds) +} CGEN_IFMT; + +/* Instruction values. */ + +typedef struct { - /* ??? Further table size reductions can be had by moving this element - either to the format table or to a separate table of its own. Not - sure this is desirable yet. */ - struct cgen_base base; - -/* Given a pointer to a cgen_insn struct, return a pointer to `base'. */ -#define CGEN_INSN_BASE(insn) (&(insn)->base) + /* The opcode portion of the base insn. */ + CGEN_INSN_INT base_value; - /* Name of entry (that distinguishes it from all other entries). - This is used, for example, in simulator profiling results. */ - /* ??? If mnemonics have operands, try to print full mnemonic. */ - const char * name; -#define CGEN_INSN_NAME(insn) ((insn)->name) +#ifdef CGEN_MAX_EXTRA_OPCODE_OPERANDS + /* Extra opcode values beyond base_value. */ + unsigned long ifield_values[CGEN_MAX_EXTRA_OPCODE_OPERANDS]; +#endif +} CGEN_IVALUE; - /* Mnemonic. This is used when parsing and printing the insn. - In the case of insns that have operands on the mnemonics, this is - only the constant part. E.g. for conditional execution of an `add' insn, - where the full mnemonic is addeq, addne, etc., this is only "add". */ - const char * mnemonic; -#define CGEN_INSN_MNEMONIC(insn) ((insn)->mnemonic) +/* Instruction opcode table. + This contains the syntax and format data of an instruction. */ + +/* ??? Some ports already have an opcode table yet still need to use the rest + of what cgen_insn has. Plus keeping the opcode data with the operand + instance data can create a pretty big file. So we keep them separately. + Not sure this is a good idea in the long run. */ + +typedef struct +{ + /* Indices into parse/insert/extract/print handler tables. */ + struct cgen_opcode_handler handlers; +#define CGEN_OPCODE_HANDLERS(opc) (& (opc)->handlers) /* Syntax string. */ - const CGEN_SYNTAX syntax; -#define CGEN_INSN_SYNTAX(insn) (& (insn)->syntax) + CGEN_SYNTAX syntax; +#define CGEN_OPCODE_SYNTAX(opc) (& (opc)->syntax) /* Format entry. */ - const CGEN_FORMAT format; -#define CGEN_INSN_MASK_BITSIZE(insn) ((insn)->format.mask_length) -#define CGEN_INSN_BITSIZE(insn) ((insn)->format.length) + const CGEN_IFMT *format; +#define CGEN_OPCODE_FORMAT(opc) ((opc)->format) +#define CGEN_OPCODE_MASK_BITSIZE(opc) CGEN_IFMT_MASK_LENGTH (CGEN_OPCODE_FORMAT (opc)) +#define CGEN_OPCODE_BITSIZE(opc) CGEN_IFMT_LENGTH (CGEN_OPCODE_FORMAT (opc)) +#define CGEN_OPCODE_IFLDS(opc) CGEN_IFMT_IFLDS (CGEN_OPCODE_FORMAT (opc)) /* Instruction opcode value. */ - unsigned int value; -#define CGEN_INSN_VALUE(insn) ((insn)->value) -#define CGEN_INSN_MASK(insn) ((insn)->format.mask) + CGEN_IVALUE value; +#define CGEN_OPCODE_VALUE(opc) (& (opc)->value) +#define CGEN_OPCODE_BASE_VALUE(opc) (CGEN_OPCODE_VALUE (opc)->base_value) +#define CGEN_OPCODE_BASE_MASK(opc) CGEN_IFMT_MASK (CGEN_OPCODE_FORMAT (opc)) +} CGEN_OPCODE; + +/* Instruction attributes. + This is made a published type as applications can cache a pointer to + the attributes for speed. */ + +#ifndef CGEN_INSN_NBOOL_ATTRS +#define CGEN_INSN_NBOOL_ATTRS 1 +#endif +typedef CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) CGEN_INSN_ATTR_TYPE; + +/* Enum of architecture independent attributes. */ + +#ifndef CGEN_ARCH +/* ??? Numbers here are recorded in two places. */ +typedef enum cgen_insn_attr { + CGEN_INSN_ALIAS = 0 +} CGEN_INSN_ATTR; +#endif + +/* This struct defines each entry in the instruction table. */ + +typedef struct +{ + /* Each real instruction is enumerated. */ + /* ??? This may go away in time. */ + int num; +#define CGEN_INSN_NUM(insn) ((insn)->base->num) + + /* Name of entry (that distinguishes it from all other entries). */ + /* ??? If mnemonics have operands, try to print full mnemonic. */ + const char *name; +#define CGEN_INSN_NAME(insn) ((insn)->base->name) - /* Pointer to NULL entry terminated table of operands used, - or NULL if none. */ - const CGEN_OPERAND_INSTANCE *operands; -#define CGEN_INSN_OPERANDS(insn) ((insn)->operands) + /* Mnemonic. This is used when parsing and printing the insn. + In the case of insns that have operands on the mnemonics, this is + only the constant part. E.g. for conditional execution of an `add' insn, + where the full mnemonic is addeq, addne, etc., and the condition is + treated as an operand, this is only "add". */ + const char *mnemonic; +#define CGEN_INSN_MNEMONIC(insn) ((insn)->base->mnemonic) + + /* Total length of instruction, in bits. */ + int bitsize; +#define CGEN_INSN_BITSIZE(insn) ((insn)->base->bitsize) + +#if 0 /* ??? Disabled for now as there is a problem with embedded newlines + and the table is already pretty big. Should perhaps be moved + to a file of its own. */ + /* Semantics, as RTL. */ + /* ??? Plain text or bytecodes? */ + /* ??? Note that the operand instance table could be computed at run-time + if we parse this and cache the results. Something to eventually do. */ + const char *rtx; +#define CGEN_INSN_RTX(insn) ((insn)->base->rtx) +#endif /* Attributes. This must appear last. It is a variable sized array in that one architecture may have 1 nonbool attribute and another may have more. Having this last means the non-architecture specific code needn't - care. */ -#ifndef CGEN_INSN_NBOOL_ATTRS -#define CGEN_INSN_NBOOL_ATTRS 1 -#endif - CGEN_ATTR_TYPE (CGEN_INSN_NBOOL_ATTRS) attrs; -#define CGEN_INSN_ATTRS(insn) (&(insn)->attrs) + care. The goal is to eventually record attributes in their raw form, + evaluate them at run-time, and cache the values, so this worry will go + away anyway. */ + CGEN_INSN_ATTR_TYPE attrs; +#define CGEN_INSN_ATTRS(insn) (&(insn)->base->attrs) /* Return value of attribute ATTR in INSN. */ -#define CGEN_INSN_ATTR(insn, attr) \ -CGEN_ATTR_VALUE (insn, CGEN_INSN_ATTRS (insn), attr) +#define CGEN_INSN_ATTR_VALUE(insn, attr) \ +CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr)) +} CGEN_IBASE; + +/* Return non-zero if INSN is the "invalid" insn marker. */ + +#define CGEN_INSN_INVALID_P(insn) (CGEN_INSN_MNEMONIC (insn) == 0) + +/* Main struct contain instruction information. + BASE is always present, the rest is present only if asked for. */ + +struct cgen_insn +{ + /* ??? May be of use to put a type indicator here. + Then this struct could different info for different classes of insns. */ + /* ??? A speedup can be had by moving `base' into this struct. + Maybe later. */ + const CGEN_IBASE *base; + const CGEN_OPCODE *opcode; + const CGEN_OPINST *opinst; }; /* Instruction lists. @@ -703,171 +992,408 @@ CGEN_ATTR_VALUE (insn, CGEN_INSN_ATTRS (insn), attr) typedef struct cgen_insn_list { - struct cgen_insn_list * next; - const CGEN_INSN * insn; + struct cgen_insn_list *next; + const CGEN_INSN *insn; } CGEN_INSN_LIST; -/* The table of instructions. */ +/* Table of instructions. */ typedef struct { - /* Pointer to initial [compiled in] entries. */ - const CGEN_INSN * init_entries; - - /* Size of an entry (since the attribute member is variable sized). */ - unsigned int entry_size; - - /* Number of entries in `init_entries', including trailing NULL entry. */ + const CGEN_INSN *init_entries; + unsigned int entry_size; /* since the attribute member is variable sized */ unsigned int num_init_entries; - - /* Values added at runtime. */ - CGEN_INSN_LIST * new_entries; - - /* Assembler hash function. */ - unsigned int (* asm_hash) PARAMS ((const char *)); - - /* Number of entries in assembler hash table. */ - unsigned int asm_hash_table_size; - - /* Disassembler hash function. */ - unsigned int (* dis_hash) PARAMS ((const char *, unsigned long)); - - /* Number of entries in disassembler hash table. */ - unsigned int dis_hash_table_size; + CGEN_INSN_LIST *new_entries; } CGEN_INSN_TABLE; -/* ??? This is currently used by the simulator. - We want this to be fast and the simulator currently doesn't handle - runtime added instructions so this is ok. An alternative would be to - store the index in the table. */ -extern const CGEN_INSN CGEN_SYM (insn_table_entries)[]; -#define CGEN_INSN_INDEX(insn) ((int) ((insn) - CGEN_SYM (insn_table_entries))) -#define CGEN_INSN_ENTRY(n) (& CGEN_SYM (insn_table_entries) [n]) +/* Return number of instructions. This includes any added at run-time. */ + +extern int cgen_insn_count PARAMS ((CGEN_CPU_DESC)); +extern int cgen_macro_insn_count PARAMS ((CGEN_CPU_DESC)); + +/* Macros to access the other insn elements not recorded in CGEN_IBASE. */ + +/* Fetch INSN's operand instance table. */ +/* ??? Doesn't handle insns added at runtime. */ +#define CGEN_INSN_OPERANDS(insn) ((insn)->opinst) + +/* Return INSN's opcode table entry. */ +#define CGEN_INSN_OPCODE(insn) ((insn)->opcode) + +/* Return INSN's handler data. */ +#define CGEN_INSN_HANDLERS(insn) CGEN_OPCODE_HANDLERS (CGEN_INSN_OPCODE (insn)) + +/* Return INSN's syntax. */ +#define CGEN_INSN_SYNTAX(insn) CGEN_OPCODE_SYNTAX (CGEN_INSN_OPCODE (insn)) -/* Return number of instructions. This includes any added at runtime. */ +/* Return size of base mask in bits. */ +#define CGEN_INSN_MASK_BITSIZE(insn) \ + CGEN_OPCODE_MASK_BITSIZE (CGEN_INSN_OPCODE (insn)) -int cgen_insn_count PARAMS ((void)); +/* Return mask of base part of INSN. */ +#define CGEN_INSN_BASE_MASK(insn) \ + CGEN_OPCODE_BASE_MASK (CGEN_INSN_OPCODE (insn)) +/* Return value of base part of INSN. */ +#define CGEN_INSN_BASE_VALUE(insn) \ + CGEN_OPCODE_BASE_VALUE (CGEN_INSN_OPCODE (insn)) + +/* Standard way to test whether INSN is supported by MACH. + MACH is one of enum mach_attr. + The "|1" is because the base mach is always selected. */ +#define CGEN_INSN_MACH_HAS_P(insn, mach) \ +((CGEN_INSN_ATTR_VALUE ((insn), CGEN_INSN_MACH) & ((1 << (mach)) | 1)) != 0) + +/* Macro instructions. + Macro insns aren't real insns, they map to one or more real insns. + E.g. An architecture's "nop" insn may actually be an "mv r0,r0" or + some such. + + Macro insns can expand to nothing (e.g. a nop that is optimized away). + This is useful in multi-insn macros that build a constant in a register. + Of course this isn't the default behaviour and must be explicitly enabled. + + Assembly of macro-insns is relatively straightforward. Disassembly isn't. + However, disassembly of at least some kinds of macro insns is important + in order that the disassembled code preserve the readability of the original + insn. What is attempted here is to disassemble all "simple" macro-insns, + where "simple" is currently defined to mean "expands to one real insn". + + Simple macro-insns are handled specially. They are emitted as ALIAS's + of real insns. This simplifies their handling since there's usually more + of them than any other kind of macro-insn, and proper disassembly of them + falls out for free. */ + +/* For each macro-insn there may be multiple expansion possibilities, + depending on the arguments. This structure is accessed via the `data' + member of CGEN_INSN. */ + +typedef struct cgen_minsn_expansion { + /* Function to do the expansion. + If the expansion fails (e.g. "no match") NULL is returned. + Space for the expansion is obtained with malloc. + It is up to the caller to free it. */ + const char * (* fn) PARAMS ((const struct cgen_minsn_expansion *, + const char *, const char **, int *, + CGEN_OPERAND **)); +#define CGEN_MIEXPN_FN(ex) ((ex)->fn) + + /* Instruction(s) the macro expands to. + The format of STR is defined by FN. + It is typically the assembly code of the real insn, but it could also be + the original Scheme expression or a tokenized form of it (with FN being + an appropriate interpreter). */ + const char * str; +#define CGEN_MIEXPN_STR(ex) ((ex)->str) +} CGEN_MINSN_EXPANSION; + +/* Normal expander. + When supported, this function will convert the input string to another + string and the parser will be invoked recursively. The output string + may contain further macro invocations. */ + +extern const char * cgen_expand_macro_insn + PARAMS ((CGEN_CPU_DESC, const struct cgen_minsn_expansion *, + const char *, const char **, int *, CGEN_OPERAND **)); + /* The assembler insn table is hashed based on some function of the mnemonic (the actually hashing done is up to the target, but we provide a few - examples like the first letter or a function of the entire mnemonic). - The index of each entry is the index of the corresponding table entry. - The value of each entry is the index of the next entry, with a 0 - terminating (thus the first entry is reserved). */ - -#ifndef CGEN_ASM_HASH -#ifdef CGEN_MNEMONIC_OPERANDS -#define CGEN_ASM_HASH_SIZE 127 -#define CGEN_ASM_HASH(string) (*(unsigned char *) (string) % CGEN_ASM_HASH_SIZE) -#else -#define CGEN_ASM_HASH_SIZE 128 -#define CGEN_ASM_HASH(string) (*(unsigned char *) (string) % CGEN_ASM_HASH_SIZE) /*FIXME*/ -#endif -#endif + examples like the first letter or a function of the entire mnemonic). */ -unsigned int CGEN_SYM (asm_hash_insn) PARAMS ((const char *)); -CGEN_INSN_LIST * cgen_asm_lookup_insn PARAMS ((const char *)); -#define CGEN_ASM_LOOKUP_INSN(insn) cgen_asm_lookup_insn (insn) +extern CGEN_INSN_LIST * cgen_asm_lookup_insn + PARAMS ((CGEN_CPU_DESC, const char *)); +#define CGEN_ASM_LOOKUP_INSN(cd, string) cgen_asm_lookup_insn ((cd), (string)) #define CGEN_ASM_NEXT_INSN(insn) ((insn)->next) /* The disassembler insn table is hashed based on some function of machine instruction (the actually hashing done is up to the target). */ -/* It doesn't make much sense to provide a default here, - but while this is under development we do. - BUFFER is a pointer to the bytes of the insn. - INSN is the first CGEN_BASE_INSN_SIZE bytes as an int in host order. */ -#ifndef CGEN_DIS_HASH -#define CGEN_DIS_HASH_SIZE 256 -#define CGEN_DIS_HASH(buffer, insn) (*(unsigned char *) (buffer)) -#endif - -unsigned int CGEN_SYM (dis_hash_insn) PARAMS ((const char *, unsigned long)); -CGEN_INSN_LIST * cgen_dis_lookup_insn PARAMS ((const char *, unsigned long)); -#define CGEN_DIS_LOOKUP_INSN(buf, insn) cgen_dis_lookup_insn (buf, insn) +extern CGEN_INSN_LIST * cgen_dis_lookup_insn + PARAMS ((CGEN_CPU_DESC, const char *, CGEN_INSN_INT)); +/* FIXME: delete these two */ +#define CGEN_DIS_LOOKUP_INSN(cd, buf, value) cgen_dis_lookup_insn ((cd), (buf), (value)) #define CGEN_DIS_NEXT_INSN(insn) ((insn)->next) -/* Top level structures and functions. */ +/* The CPU description. + A copy of this is created when the cpu table is "opened". + All global state information is recorded here. + Access macros are provided for "public" members. */ -typedef struct +typedef struct cgen_cpu_desc { - const CGEN_HW_ENTRY * hw_list; - /*CGEN_OPERAND_TABLE * operand_table; - FIXME:wip */ - CGEN_INSN_TABLE * insn_table; -} CGEN_OPCODE_DATA; + /* Bitmap of selected machine(s) (a la BFD machine number). */ + int machs; -/* Each CPU has one of these. */ -extern CGEN_OPCODE_DATA CGEN_SYM (opcode_data); + /* Bitmap of selected isa(s). + ??? Simultaneous multiple isas might not make sense, but it's not (yet) + precluded. */ + int isas; -/* Global state access macros. - Some of these are tucked away and accessed with cover fns. - Simpler things like the current machine and endian are not. */ + /* Current endian. */ + enum cgen_endian endian; +#define CGEN_CPU_ENDIAN(cd) ((cd)->endian) -extern int cgen_current_machine; -#define CGEN_CURRENT_MACHINE cgen_current_machine + /* Current insn endian. */ + enum cgen_endian insn_endian; +#define CGEN_CPU_INSN_ENDIAN(cd) ((cd)->insn_endian) -extern enum cgen_endian cgen_current_endian; -#define CGEN_CURRENT_ENDIAN cgen_current_endian + /* Word size (in bits). */ + /* ??? Or maybe maximum word size - might we ever need to allow a cpu table + to be opened for both sparc32/sparc64? + ??? Another alternative is to create a table of selected machs and + lazily fetch the data from there. */ + unsigned int word_bitsize; -/* Prototypes of major functions. */ + /* Indicator if sizes are unknown. + This is used by default_insn_bitsize,base_insn_bitsize if there is a + difference between the selected isa's. */ +#define CGEN_SIZE_UNKNOWN 65535 + + /* Default instruction size (in bits). + This is used by the assembler when it encounters an unknown insn. */ + unsigned int default_insn_bitsize; + + /* Base instruction size (in bits). + For non-LIW cpus this is generally the length of the smallest insn. + For LIW cpus its wip (work-in-progress). For the m32r its 32. */ + unsigned int base_insn_bitsize; + + /* Minimum/maximum instruction size (in bits). */ + unsigned int min_insn_bitsize; + unsigned int max_insn_bitsize; + + /* Instruction set variants. */ + const CGEN_ISA *isa_table; + + /* Machine variants. */ + const CGEN_MACH *mach_table; + + /* Hardware elements. */ + CGEN_HW_TABLE hw_table; + + /* Instruction fields. */ + const CGEN_IFLD *ifld_table; + + /* Operands. */ + CGEN_OPERAND_TABLE operand_table; + + /* Main instruction table. */ + CGEN_INSN_TABLE insn_table; +#define CGEN_CPU_INSN_TABLE(cd) (& (cd)->insn_table) + + /* Macro instructions are defined separately and are combined with real + insns during hash table computation. */ + CGEN_INSN_TABLE macro_insn_table; + + /* Copy of CGEN_INT_INSN_P. */ + int int_insn_p; + + /* Called to rebuild the tables after something has changed. */ + void (*rebuild_tables) PARAMS ((CGEN_CPU_DESC)); + + /* Operand parser callback. */ + cgen_parse_operand_fn * parse_operand_fn; + + /* Parse/insert/extract/print cover fns for operands. */ + const char * (*parse_operand) + PARAMS ((CGEN_CPU_DESC, int opindex_, const char **, + CGEN_FIELDS *fields_)); +#ifdef BFD_VERSION + const char * (*insert_operand) + PARAMS ((CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, + CGEN_INSN_BYTES_PTR, bfd_vma pc_)); + int (*extract_operand) + PARAMS ((CGEN_CPU_DESC, int opindex_, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + CGEN_FIELDS *fields_, bfd_vma pc_)); + void (*print_operand) + PARAMS ((CGEN_CPU_DESC, int opindex_, PTR info_, CGEN_FIELDS * fields_, + void const *attrs_, bfd_vma pc_, int length_)); +#else + const char * (*insert_operand) (); + int (*extract_operand) (); + void (*print_operand) (); +#endif +#define CGEN_CPU_PARSE_OPERAND(cd) ((cd)->parse_operand) +#define CGEN_CPU_INSERT_OPERAND(cd) ((cd)->insert_operand) +#define CGEN_CPU_EXTRACT_OPERAND(cd) ((cd)->extract_operand) +#define CGEN_CPU_PRINT_OPERAND(cd) ((cd)->print_operand) + + /* Size of CGEN_FIELDS struct. */ + unsigned int sizeof_fields; +#define CGEN_CPU_SIZEOF_FIELDS(cd) ((cd)->sizeof_fields) + + /* Set the bitsize field. */ + void (*set_fields_bitsize) PARAMS ((CGEN_FIELDS *fields_, int size_)); +#define CGEN_CPU_SET_FIELDS_BITSIZE(cd) ((cd)->set_fields_bitsize) + + /* CGEN_FIELDS accessors. */ + int (*get_int_operand) + PARAMS ((CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_)); + void (*set_int_operand) + PARAMS ((CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, int value_)); +#ifdef BFD_VERSION + bfd_vma (*get_vma_operand) + PARAMS ((CGEN_CPU_DESC, int opindex_, const CGEN_FIELDS *fields_)); + void (*set_vma_operand) + PARAMS ((CGEN_CPU_DESC, int opindex_, CGEN_FIELDS *fields_, bfd_vma value_)); +#else + long (*get_vma_operand) (); + void (*set_vma_operand) (); +#endif +#define CGEN_CPU_GET_INT_OPERAND(cd) ((cd)->get_int_operand) +#define CGEN_CPU_SET_INT_OPERAND(cd) ((cd)->set_int_operand) +#define CGEN_CPU_GET_VMA_OPERAND(cd) ((cd)->get_vma_operand) +#define CGEN_CPU_SET_VMA_OPERAND(cd) ((cd)->set_vma_operand) + + /* Instruction parse/insert/extract/print handlers. */ + /* FIXME: make these types uppercase. */ + cgen_parse_fn * const *parse_handlers; + cgen_insert_fn * const *insert_handlers; + cgen_extract_fn * const *extract_handlers; + cgen_print_fn * const *print_handlers; +#define CGEN_PARSE_FN(cd, insn) (cd->parse_handlers[(insn)->opcode->handlers.parse]) +#define CGEN_INSERT_FN(cd, insn) (cd->insert_handlers[(insn)->opcode->handlers.insert]) +#define CGEN_EXTRACT_FN(cd, insn) (cd->extract_handlers[(insn)->opcode->handlers.extract]) +#define CGEN_PRINT_FN(cd, insn) (cd->print_handlers[(insn)->opcode->handlers.print]) + + /* Return non-zero if insn should be added to hash table. */ + int (* asm_hash_p) PARAMS ((const CGEN_INSN *)); + + /* Assembler hash function. */ + unsigned int (* asm_hash) PARAMS ((const char *)); + + /* Number of entries in assembler hash table. */ + unsigned int asm_hash_size; + + /* Return non-zero if insn should be added to hash table. */ + int (* dis_hash_p) PARAMS ((const CGEN_INSN *)); -/* Set the current cpu (+ mach number, endian, etc.). */ -void cgen_set_cpu PARAMS ((CGEN_OPCODE_DATA *, int, enum cgen_endian)); - -/* Initialize the assembler, disassembler. */ -void cgen_asm_init PARAMS ((void)); -void cgen_dis_init PARAMS ((void)); - -/* `init_tables' must be called before `xxx_supported'. */ -void CGEN_SYM (init_tables) PARAMS ((int)); -void CGEN_SYM (init_asm) PARAMS ((int, enum cgen_endian)); -void CGEN_SYM (init_dis) PARAMS ((int, enum cgen_endian)); -void CGEN_SYM (init_parse) PARAMS ((void)); -void CGEN_SYM (init_print) PARAMS ((void)); -void CGEN_SYM (init_insert) PARAMS ((void)); -void CGEN_SYM (init_extract) PARAMS ((void)); - -/* FIXME: This prototype is wrong ifndef CGEN_INT_INSN. - Furthermore, ifdef CGEN_INT_INSN, the insn is created in - target byte order (in which case why use int's at all). - Perhaps replace cgen_insn_t * with char *? */ -const struct cgen_insn * -CGEN_SYM (assemble_insn) PARAMS ((const char *, CGEN_FIELDS *, - cgen_insn_t *, char **)); -#if 0 /* old */ -int CGEN_SYM (insn_supported) PARAMS ((const struct cgen_insn *)); -int CGEN_SYM (opval_supported) PARAMS ((const struct cgen_opval *)); + /* Disassembler hash function. */ + unsigned int (* dis_hash) PARAMS ((const char *, CGEN_INSN_INT)); + + /* Number of entries in disassembler hash table. */ + unsigned int dis_hash_size; + + /* Assembler instruction hash table. */ + CGEN_INSN_LIST **asm_hash_table; + CGEN_INSN_LIST *asm_hash_table_entries; + + /* Disassembler instruction hash table. */ + CGEN_INSN_LIST **dis_hash_table; + CGEN_INSN_LIST *dis_hash_table_entries; + + /* This field could be turned into a bitfield if room for other flags is needed. */ + unsigned int signed_overflow_ok_p; + +} CGEN_CPU_TABLE; + +/* wip */ +#ifndef CGEN_WORD_ENDIAN +#define CGEN_WORD_ENDIAN(cd) CGEN_CPU_ENDIAN (cd) +#endif +#ifndef CGEN_INSN_WORD_ENDIAN +#define CGEN_INSN_WORD_ENDIAN(cd) CGEN_CPU_INSN_ENDIAN (cd) #endif + +/* Prototypes of major functions. */ +/* FIXME: Move more CGEN_SYM-defined functions into CGEN_CPU_DESC. + Not the init fns though, as that would drag in things that mightn't be + used and might not even exist. */ + +/* Argument types to cpu_open. */ + +enum cgen_cpu_open_arg { + CGEN_CPU_OPEN_END, + /* Select instruction set(s), arg is bitmap or 0 meaning "unspecified". */ + CGEN_CPU_OPEN_ISAS, + /* Select machine(s), arg is bitmap or 0 meaning "unspecified". */ + CGEN_CPU_OPEN_MACHS, + /* Select machine, arg is mach's bfd name. + Multiple machines can be specified by repeated use. */ + CGEN_CPU_OPEN_BFDMACH, + /* Select endian, arg is CGEN_ENDIAN_*. */ + CGEN_CPU_OPEN_ENDIAN +}; + +/* Open a cpu descriptor table for use. + ??? We only support ISO C stdargs here, not K&R. + Laziness, plus experiment to see if anything requires K&R - eventually + K&R will no longer be supported - e.g. GDB is currently trying this. */ + +extern CGEN_CPU_DESC CGEN_SYM (cpu_open) (enum cgen_cpu_open_arg, ...); + +/* Cover fn to handle simple case. */ + +extern CGEN_CPU_DESC CGEN_SYM (cpu_open_1) PARAMS ((const char *mach_name_, + enum cgen_endian endian_)); + +/* Close it. */ + +extern void CGEN_SYM (cpu_close) PARAMS ((CGEN_CPU_DESC)); + +/* Initialize the opcode table for use. + Called by init_asm/init_dis. */ + +extern void CGEN_SYM (init_opcode_table) PARAMS ((CGEN_CPU_DESC cd_)); + +/* Initialize the ibld table for use. + Called by init_asm/init_dis. */ + +extern void CGEN_SYM (init_ibld_table) PARAMS ((CGEN_CPU_DESC cd_)); + +/* Initialize an cpu table for assembler or disassembler use. + These must be called immediately after cpu_open. */ + +extern void CGEN_SYM (init_asm) PARAMS ((CGEN_CPU_DESC)); +extern void CGEN_SYM (init_dis) PARAMS ((CGEN_CPU_DESC)); + +/* Initialize the operand instance table for use. */ + +extern void CGEN_SYM (init_opinst_table) PARAMS ((CGEN_CPU_DESC cd_)); + +/* Assemble an instruction. */ + +extern const CGEN_INSN * CGEN_SYM (assemble_insn) + PARAMS ((CGEN_CPU_DESC, const char *, CGEN_FIELDS *, + CGEN_INSN_BYTES_PTR, char **)); + +extern const CGEN_KEYWORD CGEN_SYM (operand_mach); +extern int CGEN_SYM (get_mach) PARAMS ((const char *)); + +/* Operand index computation. */ +extern const CGEN_INSN * cgen_lookup_insn + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN * insn_, + CGEN_INSN_INT int_value_, unsigned char *bytes_value_, + int length_, CGEN_FIELDS *fields_, int alias_p_)); +extern void cgen_get_insn_operands + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN * insn_, + const CGEN_FIELDS *fields_, int *indices_)); +extern const CGEN_INSN * cgen_lookup_get_insn_operands + PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *insn_, + CGEN_INSN_INT int_value_, unsigned char *bytes_value_, + int length_, int *indices_, CGEN_FIELDS *fields_)); -extern const CGEN_KEYWORD CGEN_SYM (operand_mach); -int CGEN_SYM (get_mach) PARAMS ((const char *)); +/* Cover fns to bfd_get/set. */ -const CGEN_INSN * -CGEN_SYM (get_insn_operands) PARAMS ((const CGEN_INSN *, cgen_insn_t, - int, int *)); -const CGEN_INSN * -CGEN_SYM (lookup_insn) PARAMS ((const CGEN_INSN *, cgen_insn_t, - int, CGEN_FIELDS *, int)); +extern CGEN_INSN_INT cgen_get_insn_value + PARAMS ((CGEN_CPU_DESC, unsigned char *, int)); +extern void cgen_put_insn_value + PARAMS ((CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT)); -CGEN_INLINE void -CGEN_SYM (put_operand) PARAMS ((int, const long *, - CGEN_FIELDS *)); -CGEN_INLINE long -CGEN_SYM (get_operand) PARAMS ((int, const CGEN_FIELDS *)); +/* Read in a cpu description file. + ??? For future concerns, including adding instructions to the assembler/ + disassembler at run-time. */ -const char * -CGEN_SYM (parse_operand) PARAMS ((int, const char **, CGEN_FIELDS *)); +extern const char * cgen_read_cpu_file + PARAMS ((CGEN_CPU_DESC, const char * filename_)); -const char * -CGEN_SYM (insert_operand) PARAMS ((int, CGEN_FIELDS *, char *)); +/* Allow signed overflow of instruction fields. */ +extern void cgen_set_signed_overflow_ok PARAMS ((CGEN_CPU_DESC)); -/* Default insn parser, printer. */ -extern cgen_parse_fn CGEN_SYM (parse_insn); -extern cgen_insert_fn CGEN_SYM (insert_insn); -extern cgen_extract_fn CGEN_SYM (extract_insn); -extern cgen_print_fn CGEN_SYM (print_insn); +/* Generate an error message if a signed field in an instruction overflows. */ +extern void cgen_clear_signed_overflow_ok PARAMS ((CGEN_CPU_DESC)); -/* Read in a cpu description file. */ -const char * cgen_read_cpu_file PARAMS ((const char *)); +/* Will an error message be generated if a signed field in an instruction overflows ? */ +extern unsigned int cgen_signed_overflow_ok_p PARAMS ((CGEN_CPU_DESC)); #endif /* CGEN_H */ diff --git a/contrib/binutils/include/opcode/i386.h b/contrib/binutils/include/opcode/i386.h index da238c9..d399f4eb 100644 --- a/contrib/binutils/include/opcode/i386.h +++ b/contrib/binutils/include/opcode/i386.h @@ -1,5 +1,5 @@ -/* i386-opcode.h -- Intel 80386 opcode table - Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 1998 Free Software Foundation. +/* opcode/i386.h -- Intel 80386 opcode table + Copyright 1989, 91, 92, 93, 94, 95, 96, 97, 98, 1999 Free Software Foundation. This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. @@ -17,910 +17,1170 @@ You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -/* The NON_BROKEN_OPCODES cases use the operands in the reverse order - from that documented in the Intel manuals. The opcode values are - such that they actually generate different instructions. These - values must not be changed, as they are the values generated by the - UnixWare assembler, and possibly other ix86 assemblers. */ +/* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived + ix86 Unix assemblers, generate floating point instructions with + reversed source and destination registers in certain cases. + Unfortunately, gcc and possibly many other programs use this + reversed syntax, so we're stuck with it. + + eg. `fsub %st(3),%st' results in st = st - st(3) as expected, but + `fsub %st,%st(3)' results in st(3) = st - st(3), rather than + the expected st(3) = st(3) - st + + This happens with all the non-commutative arithmetic floating point + operations with two register operands, where the source register is + %st, and destination register is %st(i). See FloatDR below. + + The affected opcode map is dceX, dcfX, deeX, defX. */ + +#ifndef SYSV386_COMPAT +/* Set non-zero for broken, compatible instructions. Set to zero for + non-broken opcodes at your peril. gcc generates SystemV/386 + compatible instructions. */ +#define SYSV386_COMPAT 1 +#endif +#ifndef OLDGCC_COMPAT +/* Set non-zero to cater for old (<= 2.8.1) versions of gcc that could + generate nonsense fsubp, fsubrp, fdivp and fdivrp with operands + reversed. */ +#define OLDGCC_COMPAT SYSV386_COMPAT +#endif static const template i386_optab[] = { -#define _ None -/* move instructions */ +#define X None +#define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf) +#define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf) +#define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_dSuf|No_xSuf) +#define l_Suf (No_bSuf|No_wSuf|No_sSuf|No_dSuf|No_xSuf) +#define d_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_xSuf) +#define x_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_dSuf) +#define bw_Suf (No_lSuf|No_sSuf|No_dSuf|No_xSuf) +#define bl_Suf (No_wSuf|No_sSuf|No_dSuf|No_xSuf) +#define wl_Suf (No_bSuf|No_sSuf|No_dSuf|No_xSuf) +#define sl_Suf (No_bSuf|No_wSuf|No_dSuf|No_xSuf) +#define sld_Suf (No_bSuf|No_wSuf|No_xSuf) +#define sldx_Suf (No_bSuf|No_wSuf) +#define bwl_Suf (No_sSuf|No_dSuf|No_xSuf) +#define bwld_Suf (No_sSuf|No_xSuf) +#define FP (NoSuf|IgnoreSize) +#define l_FP (l_Suf|IgnoreSize) +#define d_FP (d_Suf|IgnoreSize) +#define x_FP (x_Suf|IgnoreSize) +#define sl_FP (sl_Suf|IgnoreSize) +#define sld_FP (sld_Suf|IgnoreSize) +#define sldx_FP (sldx_Suf|IgnoreSize) +#if SYSV386_COMPAT +/* Someone forgot that the FloatR bit reverses the operation when not + equal to the FloatD bit. ie. Changing only FloatD results in the + destination being swapped *and* the direction being reversed. */ +#define FloatDR FloatD +#else +#define FloatDR (FloatD|FloatR) +#endif + +/* Move instructions. */ #define MOV_AX_DISP32 0xa0 -{ "mov", 2, 0xa0, _, DW|NoModrm, { Disp32, Acc, 0 } }, -{ "mov", 2, 0x88, _, DW|Modrm, { Reg, Reg|Mem, 0 } }, -{ "mov", 2, 0xb0, _, ShortFormW, { Imm, Reg, 0 } }, -{ "mov", 2, 0xc6, _, W|Modrm, { Imm, Reg|Mem, 0 } }, -/* The next instruction accepts WordReg so that `movl %gs,%esi' can be - used to move a segment register to a 32 bit register without using - a size prefix. This will set the upper 16 bits of the 32 bit - register to an implementation defined value (on the Pentium Pro, +{ "mov", 2, 0xa0, X, bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } }, +{ "mov", 2, 0x88, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0 } }, +{ "mov", 2, 0xb0, X, bwl_Suf|W|ShortForm, { Imm, Reg, 0 } }, +{ "mov", 2, 0xc6, X, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0 } }, +/* The next two instructions accept WordReg so that a segment register + can be copied to a 32 bit register, and vice versa, without using a + size prefix. When moving to a 32 bit register, the upper 16 bits + are set to an implementation defined value (on the Pentium Pro, the implementation defined value is zero). */ -{ "mov", 2, 0x8c, _, D|Modrm, { SReg3|SReg2, WordReg|WordMem, 0 } }, -/* move to/from control debug registers */ -{ "mov", 2, 0x0f20, _, D|Modrm, { Control, Reg32, 0} }, -{ "mov", 2, 0x0f21, _, D|Modrm, { Debug, Reg32, 0} }, -{ "mov", 2, 0x0f24, _, D|Modrm, { Test, Reg32, 0} }, - -/* move with sign extend */ +{ "mov", 2, 0x8c, X, wl_Suf|Modrm, { SReg3|SReg2, WordReg|WordMem, 0 } }, +{ "mov", 2, 0x8e, X, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg3|SReg2, 0 } }, +/* Move to/from control debug registers. */ +{ "mov", 2, 0x0f20, X, l_Suf|D|Modrm|IgnoreSize, { Control, Reg32|InvMem, 0} }, +{ "mov", 2, 0x0f21, X, l_Suf|D|Modrm|IgnoreSize, { Debug, Reg32|InvMem, 0} }, +{ "mov", 2, 0x0f24, X, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} }, + +/* Move with sign extend. */ /* "movsbl" & "movsbw" must not be unified into "movsb" to avoid - conflict with the "movs" string move instruction. Thus, - {"movsb", 2, 0x0fbe, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} }, - is not kosher; we must seperate the two instructions. */ -{"movsbl", 2, 0x0fbe, _, ReverseRegRegmem|Modrm|Data32, { Reg8|Mem, Reg32, 0} }, -{"movsbw", 2, 0x0fbe, _, ReverseRegRegmem|Modrm|Data16, { Reg8|Mem, Reg16, 0} }, -{"movswl", 2, 0x0fbf, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} }, - -/* move with zero extend */ -{"movzb", 2, 0x0fb6, _, ReverseRegRegmem|Modrm, { Reg8|Mem, Reg16|Reg32, 0} }, -{"movzwl", 2, 0x0fb7, _, ReverseRegRegmem|Modrm, { Reg16|Mem, Reg32, 0} }, - -/* push instructions */ -{"push", 1, 0x50, _, ShortForm, { WordReg,0,0 } }, -{"push", 1, 0xff, 0x6, Modrm, { WordReg|WordMem, 0, 0 } }, -{"push", 1, 0x6a, _, NoModrm, { Imm8S, 0, 0} }, -{"push", 1, 0x68, _, NoModrm, { Imm16|Imm32, 0, 0} }, -{"push", 1, 0x06, _, Seg2ShortForm, { SReg2,0,0 } }, -{"push", 1, 0x0fa0, _, Seg3ShortForm, { SReg3,0,0 } }, -/* push all */ -{"pusha", 0, 0x60, _, NoModrm, { 0, 0, 0 } }, - -/* pop instructions */ -{"pop", 1, 0x58, _, ShortForm, { WordReg,0,0 } }, -{"pop", 1, 0x8f, 0x0, Modrm, { WordReg|WordMem, 0, 0 } }, -#define POP_SEG_SHORT 0x7 -{"pop", 1, 0x07, _, Seg2ShortForm, { SReg2,0,0 } }, -{"pop", 1, 0x0fa1, _, Seg3ShortForm, { SReg3,0,0 } }, -/* pop all */ -{"popa", 0, 0x61, _, NoModrm, { 0, 0, 0 } }, - -/* xchg exchange instructions - xchg commutes: we allow both operand orders */ -{"xchg", 2, 0x90, _, ShortForm, { WordReg, Acc, 0 } }, -{"xchg", 2, 0x90, _, ShortForm, { Acc, WordReg, 0 } }, -{"xchg", 2, 0x86, _, W|Modrm, { Reg, Reg|Mem, 0 } }, -{"xchg", 2, 0x86, _, W|Modrm, { Reg|Mem, Reg, 0 } }, - -/* in/out from ports */ -{"in", 2, 0xe4, _, W|NoModrm, { Imm8, Acc, 0 } }, -{"in", 2, 0xec, _, W|NoModrm, { InOutPortReg, Acc, 0 } }, -{"in", 1, 0xe4, _, W|NoModrm, { Imm8, 0, 0 } }, -{"in", 1, 0xec, _, W|NoModrm, { InOutPortReg, 0, 0 } }, -{"out", 2, 0xe6, _, W|NoModrm, { Acc, Imm8, 0 } }, -{"out", 2, 0xee, _, W|NoModrm, { Acc, InOutPortReg, 0 } }, -{"out", 1, 0xe6, _, W|NoModrm, { Imm8, 0, 0 } }, -{"out", 1, 0xee, _, W|NoModrm, { InOutPortReg, 0, 0 } }, - -/* load effective address */ -{"lea", 2, 0x8d, _, Modrm, { WordMem, WordReg, 0 } }, - -/* load segment registers from memory */ -{"lds", 2, 0xc5, _, Modrm, { Mem, Reg32, 0} }, -{"les", 2, 0xc4, _, Modrm, { Mem, Reg32, 0} }, -{"lfs", 2, 0x0fb4, _, Modrm, { Mem, Reg32, 0} }, -{"lgs", 2, 0x0fb5, _, Modrm, { Mem, Reg32, 0} }, -{"lss", 2, 0x0fb2, _, Modrm, { Mem, Reg32, 0} }, - -/* flags register instructions */ -{"clc", 0, 0xf8, _, NoModrm, { 0, 0, 0} }, -{"cld", 0, 0xfc, _, NoModrm, { 0, 0, 0} }, -{"cli", 0, 0xfa, _, NoModrm, { 0, 0, 0} }, -{"clts", 0, 0x0f06, _, NoModrm, { 0, 0, 0} }, -{"cmc", 0, 0xf5, _, NoModrm, { 0, 0, 0} }, -{"lahf", 0, 0x9f, _, NoModrm, { 0, 0, 0} }, -{"sahf", 0, 0x9e, _, NoModrm, { 0, 0, 0} }, -{"pushfl", 0, 0x9c, _, NoModrm|Data32, { 0, 0, 0} }, -{"popfl", 0, 0x9d, _, NoModrm|Data32, { 0, 0, 0} }, -{"pushfw", 0, 0x9c, _, NoModrm|Data16, { 0, 0, 0} }, -{"popfw", 0, 0x9d, _, NoModrm|Data16, { 0, 0, 0} }, -{"pushf", 0, 0x9c, _, NoModrm, { 0, 0, 0} }, -{"popf", 0, 0x9d, _, NoModrm, { 0, 0, 0} }, -{"stc", 0, 0xf9, _, NoModrm, { 0, 0, 0} }, -{"std", 0, 0xfd, _, NoModrm, { 0, 0, 0} }, -{"sti", 0, 0xfb, _, NoModrm, { 0, 0, 0} }, - -{"add", 2, 0x0, _, DW|Modrm, { Reg, Reg|Mem, 0} }, -{"add", 2, 0x83, 0, Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"add", 2, 0x4, _, W|NoModrm, { Imm, Acc, 0} }, -{"add", 2, 0x80, 0, W|Modrm, { Imm, Reg|Mem, 0} }, - -{"inc", 1, 0x40, _, ShortForm, { WordReg, 0, 0} }, -{"inc", 1, 0xfe, 0, W|Modrm, { Reg|Mem, 0, 0} }, - -{"sub", 2, 0x28, _, DW|Modrm, { Reg, Reg|Mem, 0} }, -{"sub", 2, 0x83, 5, Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"sub", 2, 0x2c, _, W|NoModrm, { Imm, Acc, 0} }, -{"sub", 2, 0x80, 5, W|Modrm, { Imm, Reg|Mem, 0} }, - -{"dec", 1, 0x48, _, ShortForm, { WordReg, 0, 0} }, -{"dec", 1, 0xfe, 1, W|Modrm, { Reg|Mem, 0, 0} }, - -{"sbb", 2, 0x18, _, DW|Modrm, { Reg, Reg|Mem, 0} }, -{"sbb", 2, 0x83, 3, Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"sbb", 2, 0x1c, _, W|NoModrm, { Imm, Acc, 0} }, -{"sbb", 2, 0x80, 3, W|Modrm, { Imm, Reg|Mem, 0} }, - -{"cmp", 2, 0x38, _, DW|Modrm, { Reg, Reg|Mem, 0} }, -{"cmp", 2, 0x83, 7, Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"cmp", 2, 0x3c, _, W|NoModrm, { Imm, Acc, 0} }, -{"cmp", 2, 0x80, 7, W|Modrm, { Imm, Reg|Mem, 0} }, - -{"test", 2, 0x84, _, W|Modrm, { Reg|Mem, Reg, 0} }, -{"test", 2, 0x84, _, W|Modrm, { Reg, Reg|Mem, 0} }, -{"test", 2, 0xa8, _, W|NoModrm, { Imm, Acc, 0} }, -{"test", 2, 0xf6, 0, W|Modrm, { Imm, Reg|Mem, 0} }, - -{"and", 2, 0x20, _, DW|Modrm, { Reg, Reg|Mem, 0} }, -{"and", 2, 0x83, 4, Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"and", 2, 0x24, _, W|NoModrm, { Imm, Acc, 0} }, -{"and", 2, 0x80, 4, W|Modrm, { Imm, Reg|Mem, 0} }, - -{"or", 2, 0x08, _, DW|Modrm, { Reg, Reg|Mem, 0} }, -{"or", 2, 0x83, 1, Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"or", 2, 0x0c, _, W|NoModrm, { Imm, Acc, 0} }, -{"or", 2, 0x80, 1, W|Modrm, { Imm, Reg|Mem, 0} }, - -{"xor", 2, 0x30, _, DW|Modrm, { Reg, Reg|Mem, 0} }, -{"xor", 2, 0x83, 6, Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"xor", 2, 0x34, _, W|NoModrm, { Imm, Acc, 0} }, -{"xor", 2, 0x80, 6, W|Modrm, { Imm, Reg|Mem, 0} }, + conflict with the "movs" string move instruction. */ +{"movsbl", 2, 0x0fbe, X, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} }, +{"movsbw", 2, 0x0fbe, X, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} }, +{"movswl", 2, 0x0fbf, X, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, +/* Intel Syntax */ +{"movsx", 2, 0x0fbf, X, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, +{"movsx", 2, 0x0fbe, X, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, + +/* Move with zero extend. */ +{"movzb", 2, 0x0fb6, X, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, +{"movzwl", 2, 0x0fb7, X, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, +/* Intel Syntax */ +{"movzx", 2, 0x0fb7, X, w_Suf|Modrm|IgnoreSize, { Reg16|ShortMem, Reg32, 0} }, +{"movzx", 2, 0x0fb6, X, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, + +/* Push instructions. */ +{"push", 1, 0x50, X, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, +{"push", 1, 0xff, 6, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, +{"push", 1, 0x6a, X, wl_Suf|DefaultSize, { Imm8S, 0, 0} }, +{"push", 1, 0x68, X, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} }, +{"push", 1, 0x06, X, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, +{"push", 1, 0x0fa0, X, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, +{"pusha", 0, 0x60, X, wl_Suf|DefaultSize, { 0, 0, 0 } }, + +/* Pop instructions. */ +{"pop", 1, 0x58, X, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, +{"pop", 1, 0x8f, 0, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, +#define POP_SEG_SHORT 0x07 +{"pop", 1, 0x07, X, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, +{"pop", 1, 0x0fa1, X, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, +{"popa", 0, 0x61, X, wl_Suf|DefaultSize, { 0, 0, 0 } }, + +/* Exchange instructions. + xchg commutes: we allow both operand orders. */ +{"xchg", 2, 0x90, X, wl_Suf|ShortForm, { WordReg, Acc, 0 } }, +{"xchg", 2, 0x90, X, wl_Suf|ShortForm, { Acc, WordReg, 0 } }, +{"xchg", 2, 0x86, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, +{"xchg", 2, 0x86, X, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } }, + +/* In/out from ports. */ +{"in", 2, 0xe4, X, bwl_Suf|W, { Imm8, Acc, 0 } }, +{"in", 2, 0xec, X, bwl_Suf|W, { InOutPortReg, Acc, 0 } }, +{"in", 1, 0xe4, X, bwl_Suf|W, { Imm8, 0, 0 } }, +{"in", 1, 0xec, X, bwl_Suf|W, { InOutPortReg, 0, 0 } }, +{"out", 2, 0xe6, X, bwl_Suf|W, { Acc, Imm8, 0 } }, +{"out", 2, 0xee, X, bwl_Suf|W, { Acc, InOutPortReg, 0 } }, +{"out", 1, 0xe6, X, bwl_Suf|W, { Imm8, 0, 0 } }, +{"out", 1, 0xee, X, bwl_Suf|W, { InOutPortReg, 0, 0 } }, + +/* Load effective address. */ +{"lea", 2, 0x8d, X, wl_Suf|Modrm, { WordMem, WordReg, 0 } }, + +/* Load segment registers from memory. */ +{"lds", 2, 0xc5, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, +{"les", 2, 0xc4, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, +{"lfs", 2, 0x0fb4, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, +{"lgs", 2, 0x0fb5, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, +{"lss", 2, 0x0fb2, X, wl_Suf|Modrm, { WordMem, WordReg, 0} }, + +/* Flags register instructions. */ +{"clc", 0, 0xf8, X, NoSuf, { 0, 0, 0} }, +{"cld", 0, 0xfc, X, NoSuf, { 0, 0, 0} }, +{"cli", 0, 0xfa, X, NoSuf, { 0, 0, 0} }, +{"clts", 0, 0x0f06, X, NoSuf, { 0, 0, 0} }, +{"cmc", 0, 0xf5, X, NoSuf, { 0, 0, 0} }, +{"lahf", 0, 0x9f, X, NoSuf, { 0, 0, 0} }, +{"sahf", 0, 0x9e, X, NoSuf, { 0, 0, 0} }, +{"pushf", 0, 0x9c, X, wl_Suf|DefaultSize, { 0, 0, 0} }, +{"popf", 0, 0x9d, X, wl_Suf|DefaultSize, { 0, 0, 0} }, +{"stc", 0, 0xf9, X, NoSuf, { 0, 0, 0} }, +{"std", 0, 0xfd, X, NoSuf, { 0, 0, 0} }, +{"sti", 0, 0xfb, X, NoSuf, { 0, 0, 0} }, + +/* Arithmetic. */ +{"add", 2, 0x00, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"add", 2, 0x83, 0, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"add", 2, 0x04, X, bwl_Suf|W, { Imm, Acc, 0} }, +{"add", 2, 0x80, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, + +{"inc", 1, 0x40, X, wl_Suf|ShortForm, { WordReg, 0, 0} }, +{"inc", 1, 0xfe, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"sub", 2, 0x28, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"sub", 2, 0x83, 5, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"sub", 2, 0x2c, X, bwl_Suf|W, { Imm, Acc, 0} }, +{"sub", 2, 0x80, 5, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, + +{"dec", 1, 0x48, X, wl_Suf|ShortForm, { WordReg, 0, 0} }, +{"dec", 1, 0xfe, 1, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"sbb", 2, 0x18, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"sbb", 2, 0x83, 3, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"sbb", 2, 0x1c, X, bwl_Suf|W, { Imm, Acc, 0} }, +{"sbb", 2, 0x80, 3, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, + +{"cmp", 2, 0x38, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"cmp", 2, 0x83, 7, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"cmp", 2, 0x3c, X, bwl_Suf|W, { Imm, Acc, 0} }, +{"cmp", 2, 0x80, 7, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, + +{"test", 2, 0x84, X, bwl_Suf|W|Modrm, { Reg|AnyMem, Reg, 0} }, +{"test", 2, 0x84, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"test", 2, 0xa8, X, bwl_Suf|W, { Imm, Acc, 0} }, +{"test", 2, 0xf6, 0, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, + +{"and", 2, 0x20, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"and", 2, 0x83, 4, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"and", 2, 0x24, X, bwl_Suf|W, { Imm, Acc, 0} }, +{"and", 2, 0x80, 4, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, + +{"or", 2, 0x08, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"or", 2, 0x83, 1, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"or", 2, 0x0c, X, bwl_Suf|W, { Imm, Acc, 0} }, +{"or", 2, 0x80, 1, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, + +{"xor", 2, 0x30, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"xor", 2, 0x83, 6, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"xor", 2, 0x34, X, bwl_Suf|W, { Imm, Acc, 0} }, +{"xor", 2, 0x80, 6, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, /* iclr with 1 operand is really xor with 2 operands. */ -{"clr", 1, 0x30, _, W|Modrm|iclrKludge, { Reg } }, - -{"adc", 2, 0x10, _, DW|Modrm, { Reg, Reg|Mem, 0} }, -{"adc", 2, 0x83, 2, Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"adc", 2, 0x14, _, W|NoModrm, { Imm, Acc, 0} }, -{"adc", 2, 0x80, 2, W|Modrm, { Imm, Reg|Mem, 0} }, - -{"neg", 1, 0xf6, 3, W|Modrm, { Reg|Mem, 0, 0} }, -{"not", 1, 0xf6, 2, W|Modrm, { Reg|Mem, 0, 0} }, - -{"aaa", 0, 0x37, _, NoModrm, { 0, 0, 0} }, -{"aas", 0, 0x3f, _, NoModrm, { 0, 0, 0} }, -{"daa", 0, 0x27, _, NoModrm, { 0, 0, 0} }, -{"das", 0, 0x2f, _, NoModrm, { 0, 0, 0} }, -{"aad", 0, 0xd50a, _, NoModrm, { 0, 0, 0} }, -{"aam", 0, 0xd40a, _, NoModrm, { 0, 0, 0} }, - -/* conversion insns */ -/* conversion: intel naming */ -{"cbw", 0, 0x98, _, NoModrm|Data16, { 0, 0, 0} }, -{"cwd", 0, 0x99, _, NoModrm|Data16, { 0, 0, 0} }, -{"cwde", 0, 0x98, _, NoModrm|Data32, { 0, 0, 0} }, -{"cdq", 0, 0x99, _, NoModrm|Data32, { 0, 0, 0} }, -/* att naming */ -{"cbtw", 0, 0x98, _, NoModrm|Data16, { 0, 0, 0} }, -{"cwtl", 0, 0x98, _, NoModrm|Data32, { 0, 0, 0} }, -{"cwtd", 0, 0x99, _, NoModrm|Data16, { 0, 0, 0} }, -{"cltd", 0, 0x99, _, NoModrm|Data32, { 0, 0, 0} }, +{"clr", 1, 0x30, X, bwl_Suf|W|Modrm|regKludge, { Reg, 0, 0 } }, + +{"adc", 2, 0x10, X, bwl_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, +{"adc", 2, 0x83, 2, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, +{"adc", 2, 0x14, X, bwl_Suf|W, { Imm, Acc, 0} }, +{"adc", 2, 0x80, 2, bwl_Suf|W|Modrm, { Imm, Reg|AnyMem, 0} }, + +{"neg", 1, 0xf6, 3, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, +{"not", 1, 0xf6, 2, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"aaa", 0, 0x37, X, NoSuf, { 0, 0, 0} }, +{"aas", 0, 0x3f, X, NoSuf, { 0, 0, 0} }, +{"daa", 0, 0x27, X, NoSuf, { 0, 0, 0} }, +{"das", 0, 0x2f, X, NoSuf, { 0, 0, 0} }, +{"aad", 0, 0xd50a, X, NoSuf, { 0, 0, 0} }, +{"aad", 1, 0xd5, X, NoSuf, { Imm8S, 0, 0} }, +{"aam", 0, 0xd40a, X, NoSuf, { 0, 0, 0} }, +{"aam", 1, 0xd4, X, NoSuf, { Imm8S, 0, 0} }, + +/* Conversion insns. */ +/* Intel naming */ +{"cbw", 0, 0x98, X, NoSuf|Size16, { 0, 0, 0} }, +{"cwde", 0, 0x98, X, NoSuf|Size32, { 0, 0, 0} }, +{"cwd", 0, 0x99, X, NoSuf|Size16, { 0, 0, 0} }, +{"cdq", 0, 0x99, X, NoSuf|Size32, { 0, 0, 0} }, +/* AT&T naming */ +{"cbtw", 0, 0x98, X, NoSuf|Size16, { 0, 0, 0} }, +{"cwtl", 0, 0x98, X, NoSuf|Size32, { 0, 0, 0} }, +{"cwtd", 0, 0x99, X, NoSuf|Size16, { 0, 0, 0} }, +{"cltd", 0, 0x99, X, NoSuf|Size32, { 0, 0, 0} }, /* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are expanding 64-bit multiplies, and *cannot* be selected to accomplish 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) - These multiplies can only be selected with single operand forms. */ -{"mul", 1, 0xf6, 4, W|Modrm, { Reg|Mem, 0, 0} }, -{"imul", 1, 0xf6, 5, W|Modrm, { Reg|Mem, 0, 0} }, - - - - -/* imulKludge here is needed to reverse the i.rm.reg & i.rm.regmem fields. - These instructions are exceptions: 'imul $2, %eax, %ecx' would put - '%eax' in the reg field and '%ecx' in the regmem field if we did not - switch them. */ -{"imul", 2, 0x0faf, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} }, -{"imul", 3, 0x6b, _, Modrm|ReverseRegRegmem, { Imm8S, WordReg|Mem, WordReg} }, -{"imul", 3, 0x69, _, Modrm|ReverseRegRegmem, { Imm16|Imm32, WordReg|Mem, WordReg} }, -/* - imul with 2 operands mimicks imul with 3 by puting register both - in i.rm.reg & i.rm.regmem fields -*/ -{"imul", 2, 0x6b, _, Modrm|imulKludge, { Imm8S, WordReg, 0} }, -{"imul", 2, 0x69, _, Modrm|imulKludge, { Imm16|Imm32, WordReg, 0} }, -{"div", 1, 0xf6, 6, W|Modrm, { Reg|Mem, 0, 0} }, -{"div", 2, 0xf6, 6, W|Modrm, { Reg|Mem, Acc, 0} }, -{"idiv", 1, 0xf6, 7, W|Modrm, { Reg|Mem, 0, 0} }, -{"idiv", 2, 0xf6, 7, W|Modrm, { Reg|Mem, Acc, 0} }, - -{"rol", 2, 0xd0, 0, W|Modrm, { Imm1, Reg|Mem, 0} }, -{"rol", 2, 0xc0, 0, W|Modrm, { Imm8, Reg|Mem, 0} }, -{"rol", 2, 0xd2, 0, W|Modrm, { ShiftCount, Reg|Mem, 0} }, -{"rol", 1, 0xd0, 0, W|Modrm, { Reg|Mem, 0, 0} }, - -{"ror", 2, 0xd0, 1, W|Modrm, { Imm1, Reg|Mem, 0} }, -{"ror", 2, 0xc0, 1, W|Modrm, { Imm8, Reg|Mem, 0} }, -{"ror", 2, 0xd2, 1, W|Modrm, { ShiftCount, Reg|Mem, 0} }, -{"ror", 1, 0xd0, 1, W|Modrm, { Reg|Mem, 0, 0} }, - -{"rcl", 2, 0xd0, 2, W|Modrm, { Imm1, Reg|Mem, 0} }, -{"rcl", 2, 0xc0, 2, W|Modrm, { Imm8, Reg|Mem, 0} }, -{"rcl", 2, 0xd2, 2, W|Modrm, { ShiftCount, Reg|Mem, 0} }, -{"rcl", 1, 0xd0, 2, W|Modrm, { Reg|Mem, 0, 0} }, - -{"rcr", 2, 0xd0, 3, W|Modrm, { Imm1, Reg|Mem, 0} }, -{"rcr", 2, 0xc0, 3, W|Modrm, { Imm8, Reg|Mem, 0} }, -{"rcr", 2, 0xd2, 3, W|Modrm, { ShiftCount, Reg|Mem, 0} }, -{"rcr", 1, 0xd0, 3, W|Modrm, { Reg|Mem, 0, 0} }, - -{"sal", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} }, -{"sal", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} }, -{"sal", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} }, -{"sal", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} }, -{"shl", 2, 0xd0, 4, W|Modrm, { Imm1, Reg|Mem, 0} }, -{"shl", 2, 0xc0, 4, W|Modrm, { Imm8, Reg|Mem, 0} }, -{"shl", 2, 0xd2, 4, W|Modrm, { ShiftCount, Reg|Mem, 0} }, -{"shl", 1, 0xd0, 4, W|Modrm, { Reg|Mem, 0, 0} }, - -{"shld", 3, 0x0fa4, _, Modrm, { Imm8, WordReg, WordReg|Mem} }, -{"shld", 3, 0x0fa5, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} }, -{"shld", 2, 0x0fa5, _, Modrm, { WordReg, WordReg|Mem, 0} }, - -{"shr", 2, 0xd0, 5, W|Modrm, { Imm1, Reg|Mem, 0} }, -{"shr", 2, 0xc0, 5, W|Modrm, { Imm8, Reg|Mem, 0} }, -{"shr", 2, 0xd2, 5, W|Modrm, { ShiftCount, Reg|Mem, 0} }, -{"shr", 1, 0xd0, 5, W|Modrm, { Reg|Mem, 0, 0} }, - -{"shrd", 3, 0x0fac, _, Modrm, { Imm8, WordReg, WordReg|Mem} }, -{"shrd", 3, 0x0fad, _, Modrm, { ShiftCount, WordReg, WordReg|Mem} }, -{"shrd", 2, 0x0fad, _, Modrm, { WordReg, WordReg|Mem, 0} }, - -{"sar", 2, 0xd0, 7, W|Modrm, { Imm1, Reg|Mem, 0} }, -{"sar", 2, 0xc0, 7, W|Modrm, { Imm8, Reg|Mem, 0} }, -{"sar", 2, 0xd2, 7, W|Modrm, { ShiftCount, Reg|Mem, 0} }, -{"sar", 1, 0xd0, 7, W|Modrm, { Reg|Mem, 0, 0} }, - -/* control transfer instructions */ -#define CALL_PC_RELATIVE 0xe8 -{"call", 1, 0xe8, _, JumpDword, { Disp32, 0, 0} }, -{"call", 1, 0xff, 2, Modrm|Data32, { Reg|Mem|JumpAbsolute, 0, 0} }, -{"callw", 1, 0xff, 2, Modrm|Data16, { Reg|Mem|JumpAbsolute, 0, 0} }, -#define CALL_FAR_IMMEDIATE 0x9a -{"lcall", 2, 0x9a, _, JumpInterSegment, { Imm16, Imm32, 0} }, -{"lcall", 1, 0xff, 3, Modrm|Data32, { Mem, 0, 0} }, -{"lcallw", 1, 0xff, 3, Modrm|Data16, { Mem, 0, 0} }, + These multiplies can only be selected with single operand forms. */ +{"mul", 1, 0xf6, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, +{"imul", 1, 0xf6, 5, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, +{"imul", 2, 0x0faf, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"imul", 3, 0x6b, X, wl_Suf|Modrm, { Imm8S, WordReg|WordMem, WordReg} }, +{"imul", 3, 0x69, X, wl_Suf|Modrm, { Imm16|Imm32, WordReg|WordMem, WordReg} }, +/* imul with 2 operands mimics imul with 3 by putting the register in + both i.rm.reg & i.rm.regmem fields. regKludge enables this + transformation. */ +{"imul", 2, 0x6b, X, wl_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} }, +{"imul", 2, 0x69, X, wl_Suf|Modrm|regKludge,{ Imm16|Imm32, WordReg, 0} }, + +{"div", 1, 0xf6, 6, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, +{"div", 2, 0xf6, 6, bwl_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, +{"idiv", 1, 0xf6, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, +{"idiv", 2, 0xf6, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, + +{"rol", 2, 0xd0, 0, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"rol", 2, 0xc0, 0, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"rol", 2, 0xd2, 0, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"rol", 1, 0xd0, 0, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"ror", 2, 0xd0, 1, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"ror", 2, 0xc0, 1, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"ror", 2, 0xd2, 1, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"ror", 1, 0xd0, 1, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"rcl", 2, 0xd0, 2, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"rcl", 2, 0xc0, 2, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"rcl", 2, 0xd2, 2, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"rcl", 1, 0xd0, 2, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"rcr", 2, 0xd0, 3, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"rcr", 2, 0xc0, 3, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"rcr", 2, 0xd2, 3, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"rcr", 1, 0xd0, 3, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"sal", 2, 0xd0, 4, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"sal", 2, 0xc0, 4, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"sal", 2, 0xd2, 4, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"sal", 1, 0xd0, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, +{"shl", 2, 0xd0, 4, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"shl", 2, 0xc0, 4, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"shl", 2, 0xd2, 4, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"shl", 1, 0xd0, 4, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"shld", 3, 0x0fa4, X, wl_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, +{"shld", 3, 0x0fa5, X, wl_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, +{"shld", 2, 0x0fa5, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, + +{"shr", 2, 0xd0, 5, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"shr", 2, 0xc0, 5, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"shr", 2, 0xd2, 5, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"shr", 1, 0xd0, 5, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +{"shrd", 3, 0x0fac, X, wl_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, +{"shrd", 3, 0x0fad, X, wl_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, +{"shrd", 2, 0x0fad, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, + +{"sar", 2, 0xd0, 7, bwl_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, +{"sar", 2, 0xc0, 7, bwl_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, +{"sar", 2, 0xd2, 7, bwl_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, +{"sar", 1, 0xd0, 7, bwl_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, + +/* Control transfer instructions. */ +{"call", 1, 0xe8, X, wl_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} }, +{"call", 1, 0xff, 2, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} }, +/* Intel Syntax */ +{"call", 2, 0x9a, X, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, +/* Intel Syntax */ +{"call", 1, 0xff, 3, x_Suf|Modrm|DefaultSize, { WordMem, 0, 0} }, +{"lcall", 2, 0x9a, X, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, +{"lcall", 1, 0xff, 3, wl_Suf|Modrm|DefaultSize, { WordMem|JumpAbsolute, 0, 0} }, #define JUMP_PC_RELATIVE 0xeb -{"jmp", 1, 0xeb, _, Jump, { Disp, 0, 0} }, -{"jmp", 1, 0xff, 4, Modrm, { Reg32|Mem|JumpAbsolute, 0, 0} }, -#define JUMP_FAR_IMMEDIATE 0xea -{"ljmp", 2, 0xea, _, JumpInterSegment, { Imm16, Imm32, 0} }, -{"ljmp", 1, 0xff, 5, Modrm|Data32, { Mem, 0, 0} }, - -{"ret", 0, 0xc3, _, NoModrm|Data32, { 0, 0, 0} }, -{"ret", 1, 0xc2, _, NoModrm|Data32, { Imm16, 0, 0} }, -{"retw", 0, 0xc3, _, NoModrm|Data16, { 0, 0, 0} }, -{"retw", 1, 0xc2, _, NoModrm|Data16, { Imm16, 0, 0} }, -{"lret", 0, 0xcb, _, NoModrm|Data32, { 0, 0, 0} }, -{"lret", 1, 0xca, _, NoModrm|Data32, { Imm16, 0, 0} }, -{"lretw", 0, 0xcb, _, NoModrm|Data16, { 0, 0, 0} }, -{"lretw", 1, 0xca, _, NoModrm|Data16, { Imm16, 0, 0} }, -{"enter", 2, 0xc8, _, NoModrm|Data32, { Imm16, Imm8, 0} }, -{"leave", 0, 0xc9, _, NoModrm|Data32, { 0, 0, 0} }, -{"enterw", 2, 0xc8, _, NoModrm|Data16, { Imm16, Imm8, 0} }, -{"leavew", 0, 0xc9, _, NoModrm|Data16, { 0, 0, 0} }, - -/* conditional jumps */ -{"jo", 1, 0x70, _, Jump, { Disp, 0, 0} }, - -{"jno", 1, 0x71, _, Jump, { Disp, 0, 0} }, - -{"jb", 1, 0x72, _, Jump, { Disp, 0, 0} }, -{"jc", 1, 0x72, _, Jump, { Disp, 0, 0} }, -{"jnae", 1, 0x72, _, Jump, { Disp, 0, 0} }, - -{"jnb", 1, 0x73, _, Jump, { Disp, 0, 0} }, -{"jnc", 1, 0x73, _, Jump, { Disp, 0, 0} }, -{"jae", 1, 0x73, _, Jump, { Disp, 0, 0} }, - -{"je", 1, 0x74, _, Jump, { Disp, 0, 0} }, -{"jz", 1, 0x74, _, Jump, { Disp, 0, 0} }, - -{"jne", 1, 0x75, _, Jump, { Disp, 0, 0} }, -{"jnz", 1, 0x75, _, Jump, { Disp, 0, 0} }, - -{"jbe", 1, 0x76, _, Jump, { Disp, 0, 0} }, -{"jna", 1, 0x76, _, Jump, { Disp, 0, 0} }, - -{"jnbe", 1, 0x77, _, Jump, { Disp, 0, 0} }, -{"ja", 1, 0x77, _, Jump, { Disp, 0, 0} }, - -{"js", 1, 0x78, _, Jump, { Disp, 0, 0} }, - -{"jns", 1, 0x79, _, Jump, { Disp, 0, 0} }, - -{"jp", 1, 0x7a, _, Jump, { Disp, 0, 0} }, -{"jpe", 1, 0x7a, _, Jump, { Disp, 0, 0} }, - -{"jnp", 1, 0x7b, _, Jump, { Disp, 0, 0} }, -{"jpo", 1, 0x7b, _, Jump, { Disp, 0, 0} }, - -{"jl", 1, 0x7c, _, Jump, { Disp, 0, 0} }, -{"jnge", 1, 0x7c, _, Jump, { Disp, 0, 0} }, - -{"jnl", 1, 0x7d, _, Jump, { Disp, 0, 0} }, -{"jge", 1, 0x7d, _, Jump, { Disp, 0, 0} }, - -{"jle", 1, 0x7e, _, Jump, { Disp, 0, 0} }, -{"jng", 1, 0x7e, _, Jump, { Disp, 0, 0} }, - -{"jnle", 1, 0x7f, _, Jump, { Disp, 0, 0} }, -{"jg", 1, 0x7f, _, Jump, { Disp, 0, 0} }, - -#define IS_JUMP_ON_CX_ZERO(o) \ - (o == 0xe3) +{"jmp", 1, 0xeb, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jmp", 1, 0xff, 4, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} }, +/* Intel Syntax */ +{"jmp", 2, 0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, +/* Intel Syntax */ +{"jmp", 1, 0xff, 5, x_Suf|Modrm, { WordMem, 0, 0} }, +{"ljmp", 2, 0xea, X, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, +{"ljmp", 1, 0xff, 5, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} }, + +{"ret", 0, 0xc3, X, wl_Suf|DefaultSize, { 0, 0, 0} }, +{"ret", 1, 0xc2, X, wl_Suf|DefaultSize, { Imm16, 0, 0} }, +{"lret", 0, 0xcb, X, wl_Suf|DefaultSize, { 0, 0, 0} }, +{"lret", 1, 0xca, X, wl_Suf|DefaultSize, { Imm16, 0, 0} }, +{"enter", 2, 0xc8, X, wl_Suf|DefaultSize, { Imm16, Imm8, 0} }, +{"leave", 0, 0xc9, X, wl_Suf|DefaultSize, { 0, 0, 0} }, + +/* Conditional jumps. */ +{"jo", 1, 0x70, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jno", 1, 0x71, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jb", 1, 0x72, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jc", 1, 0x72, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jnae", 1, 0x72, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jnb", 1, 0x73, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jnc", 1, 0x73, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jae", 1, 0x73, X, NoSuf|Jump, { Disp, 0, 0} }, +{"je", 1, 0x74, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jz", 1, 0x74, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jne", 1, 0x75, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jnz", 1, 0x75, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jbe", 1, 0x76, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jna", 1, 0x76, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jnbe", 1, 0x77, X, NoSuf|Jump, { Disp, 0, 0} }, +{"ja", 1, 0x77, X, NoSuf|Jump, { Disp, 0, 0} }, +{"js", 1, 0x78, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jns", 1, 0x79, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jp", 1, 0x7a, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jpe", 1, 0x7a, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jnp", 1, 0x7b, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jpo", 1, 0x7b, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jl", 1, 0x7c, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jnge", 1, 0x7c, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jnl", 1, 0x7d, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jge", 1, 0x7d, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jle", 1, 0x7e, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jng", 1, 0x7e, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jnle", 1, 0x7f, X, NoSuf|Jump, { Disp, 0, 0} }, +{"jg", 1, 0x7f, X, NoSuf|Jump, { Disp, 0, 0} }, /* jcxz vs. jecxz is chosen on the basis of the address size prefix. */ -{"jcxz", 1, 0xe3, _, JumpByte|Data16, { Disp, 0, 0} }, -{"jecxz", 1, 0xe3, _, JumpByte|Data32, { Disp, 0, 0} }, - -#define IS_LOOP_ECX_TIMES(o) \ - (o == 0xe2 || o == 0xe1 || o == 0xe0) - -{"loop", 1, 0xe2, _, JumpByte, { Disp, 0, 0} }, - -{"loopz", 1, 0xe1, _, JumpByte, { Disp, 0, 0} }, -{"loope", 1, 0xe1, _, JumpByte, { Disp, 0, 0} }, - -{"loopnz", 1, 0xe0, _, JumpByte, { Disp, 0, 0} }, -{"loopne", 1, 0xe0, _, JumpByte, { Disp, 0, 0} }, - -/* set byte on flag instructions */ -{"seto", 1, 0x0f90, 0, Modrm, { Reg8|Mem, 0, 0} }, - -{"setno", 1, 0x0f91, 0, Modrm, { Reg8|Mem, 0, 0} }, - -{"setb", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} }, -{"setc", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} }, -{"setnae", 1, 0x0f92, 0, Modrm, { Reg8|Mem, 0, 0} }, - -{"setnb", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} }, -{"setnc", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} }, -{"setae", 1, 0x0f93, 0, Modrm, { Reg8|Mem, 0, 0} }, - -{"sete", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} }, -{"setz", 1, 0x0f94, 0, Modrm, { Reg8|Mem, 0, 0} }, - -{"setne", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} }, -{"setnz", 1, 0x0f95, 0, Modrm, { Reg8|Mem, 0, 0} }, - -{"setbe", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} }, -{"setna", 1, 0x0f96, 0, Modrm, { Reg8|Mem, 0, 0} }, - -{"setnbe", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} }, -{"seta", 1, 0x0f97, 0, Modrm, { Reg8|Mem, 0, 0} }, - -{"sets", 1, 0x0f98, 0, Modrm, { Reg8|Mem, 0, 0} }, - -{"setns", 1, 0x0f99, 0, Modrm, { Reg8|Mem, 0, 0} }, - -{"setp", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} }, -{"setpe", 1, 0x0f9a, 0, Modrm, { Reg8|Mem, 0, 0} }, - -{"setnp", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} }, -{"setpo", 1, 0x0f9b, 0, Modrm, { Reg8|Mem, 0, 0} }, - -{"setl", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} }, -{"setnge", 1, 0x0f9c, 0, Modrm, { Reg8|Mem, 0, 0} }, - -{"setnl", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} }, -{"setge", 1, 0x0f9d, 0, Modrm, { Reg8|Mem, 0, 0} }, - -{"setle", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} }, -{"setng", 1, 0x0f9e, 0, Modrm, { Reg8|Mem, 0, 0} }, - -{"setnle", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} }, -{"setg", 1, 0x0f9f, 0, Modrm, { Reg8|Mem, 0, 0} }, - -#define IS_STRING_INSTRUCTION(o) \ - ((o) == 0xa6 || (o) == 0x6c || (o) == 0x6e || (o) == 0x6e || \ - (o) == 0xac || (o) == 0xa4 || (o) == 0xae || (o) == 0xaa || \ - (o) == 0xd7) - -/* string manipulation */ -{"cmps", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} }, -{"scmp", 0, 0xa6, _, W|NoModrm, { 0, 0, 0} }, -{"ins", 0, 0x6c, _, W|NoModrm, { 0, 0, 0} }, -{"outs", 0, 0x6e, _, W|NoModrm, { 0, 0, 0} }, -{"lods", 0, 0xac, _, W|NoModrm, { 0, 0, 0} }, -{"slod", 0, 0xac, _, W|NoModrm, { 0, 0, 0} }, -{"movs", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} }, -{"smov", 0, 0xa4, _, W|NoModrm, { 0, 0, 0} }, -{"scas", 0, 0xae, _, W|NoModrm, { 0, 0, 0} }, -{"ssca", 0, 0xae, _, W|NoModrm, { 0, 0, 0} }, -{"stos", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} }, -{"ssto", 0, 0xaa, _, W|NoModrm, { 0, 0, 0} }, -{"xlat", 0, 0xd7, _, NoModrm, { 0, 0, 0} }, - -/* bit manipulation */ -{"bsf", 2, 0x0fbc, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} }, -{"bsr", 2, 0x0fbd, _, Modrm|ReverseRegRegmem, { Reg|Mem, Reg, 0} }, -{"bt", 2, 0x0fa3, _, Modrm, { Reg, Reg|Mem, 0} }, -{"bt", 2, 0x0fba, 4, Modrm, { Imm8, Reg|Mem, 0} }, -{"btc", 2, 0x0fbb, _, Modrm, { Reg, Reg|Mem, 0} }, -{"btc", 2, 0x0fba, 7, Modrm, { Imm8, Reg|Mem, 0} }, -{"btr", 2, 0x0fb3, _, Modrm, { Reg, Reg|Mem, 0} }, -{"btr", 2, 0x0fba, 6, Modrm, { Imm8, Reg|Mem, 0} }, -{"bts", 2, 0x0fab, _, Modrm, { Reg, Reg|Mem, 0} }, -{"bts", 2, 0x0fba, 5, Modrm, { Imm8, Reg|Mem, 0} }, - -/* interrupts & op. sys insns */ +{"jcxz", 1, 0xe3, X, NoSuf|JumpByte|Size16, { Disp, 0, 0} }, +{"jecxz", 1, 0xe3, X, NoSuf|JumpByte|Size32, { Disp, 0, 0} }, + +/* The loop instructions also use the address size prefix to select + %cx rather than %ecx for the loop count, so the `w' form of these + instructions emit an address size prefix rather than a data size + prefix. */ +{"loop", 1, 0xe2, X, wl_Suf|JumpByte, { Disp, 0, 0} }, +{"loopz", 1, 0xe1, X, wl_Suf|JumpByte, { Disp, 0, 0} }, +{"loope", 1, 0xe1, X, wl_Suf|JumpByte, { Disp, 0, 0} }, +{"loopnz", 1, 0xe0, X, wl_Suf|JumpByte, { Disp, 0, 0} }, +{"loopne", 1, 0xe0, X, wl_Suf|JumpByte, { Disp, 0, 0} }, + +/* Set byte on flag instructions. */ +{"seto", 1, 0x0f90, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setno", 1, 0x0f91, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setb", 1, 0x0f92, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setc", 1, 0x0f92, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnae", 1, 0x0f92, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnb", 1, 0x0f93, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnc", 1, 0x0f93, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setae", 1, 0x0f93, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"sete", 1, 0x0f94, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setz", 1, 0x0f94, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setne", 1, 0x0f95, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnz", 1, 0x0f95, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setbe", 1, 0x0f96, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setna", 1, 0x0f96, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnbe", 1, 0x0f97, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"seta", 1, 0x0f97, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"sets", 1, 0x0f98, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setns", 1, 0x0f99, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setp", 1, 0x0f9a, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setpe", 1, 0x0f9a, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnp", 1, 0x0f9b, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setpo", 1, 0x0f9b, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setl", 1, 0x0f9c, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnge", 1, 0x0f9c, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnl", 1, 0x0f9d, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setge", 1, 0x0f9d, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setle", 1, 0x0f9e, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setng", 1, 0x0f9e, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setnle", 1, 0x0f9f, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, +{"setg", 1, 0x0f9f, 0, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, + +/* String manipulation. */ +{"cmps", 0, 0xa6, X, bwld_Suf|W|IsString, { 0, 0, 0} }, +{"cmps", 2, 0xa6, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, +{"scmp", 0, 0xa6, X, bwld_Suf|W|IsString, { 0, 0, 0} }, +{"scmp", 2, 0xa6, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, +{"ins", 0, 0x6c, X, bwld_Suf|W|IsString, { 0, 0, 0} }, +{"ins", 2, 0x6c, X, bwld_Suf|W|IsString, { InOutPortReg, AnyMem|EsSeg, 0} }, +{"outs", 0, 0x6e, X, bwld_Suf|W|IsString, { 0, 0, 0} }, +{"outs", 2, 0x6e, X, bwld_Suf|W|IsString, { AnyMem, InOutPortReg, 0} }, +{"lods", 0, 0xac, X, bwld_Suf|W|IsString, { 0, 0, 0} }, +{"lods", 1, 0xac, X, bwld_Suf|W|IsString, { AnyMem, 0, 0} }, +{"lods", 2, 0xac, X, bwld_Suf|W|IsString, { AnyMem, Acc, 0} }, +{"slod", 0, 0xac, X, bwld_Suf|W|IsString, { 0, 0, 0} }, +{"slod", 1, 0xac, X, bwld_Suf|W|IsString, { AnyMem, 0, 0} }, +{"slod", 2, 0xac, X, bwld_Suf|W|IsString, { AnyMem, Acc, 0} }, +{"movs", 0, 0xa4, X, bwld_Suf|W|IsString, { 0, 0, 0} }, +{"movs", 2, 0xa4, X, bwld_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, +{"smov", 0, 0xa4, X, bwld_Suf|W|IsString, { 0, 0, 0} }, +{"smov", 2, 0xa4, X, bwld_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, +{"scas", 0, 0xae, X, bwld_Suf|W|IsString, { 0, 0, 0} }, +{"scas", 1, 0xae, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, +{"scas", 2, 0xae, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, +{"ssca", 0, 0xae, X, bwld_Suf|W|IsString, { 0, 0, 0} }, +{"ssca", 1, 0xae, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, +{"ssca", 2, 0xae, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, +{"stos", 0, 0xaa, X, bwld_Suf|W|IsString, { 0, 0, 0} }, +{"stos", 1, 0xaa, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, +{"stos", 2, 0xaa, X, bwld_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, +{"ssto", 0, 0xaa, X, bwld_Suf|W|IsString, { 0, 0, 0} }, +{"ssto", 1, 0xaa, X, bwld_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, +{"ssto", 2, 0xaa, X, bwld_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, +{"xlat", 0, 0xd7, X, b_Suf|IsString, { 0, 0, 0} }, +{"xlat", 1, 0xd7, X, b_Suf|IsString, { AnyMem, 0, 0} }, + +/* Bit manipulation. */ +{"bsf", 2, 0x0fbc, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"bsr", 2, 0x0fbd, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"bt", 2, 0x0fa3, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, +{"bt", 2, 0x0fba, 4, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, +{"btc", 2, 0x0fbb, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, +{"btc", 2, 0x0fba, 7, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, +{"btr", 2, 0x0fb3, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, +{"btr", 2, 0x0fba, 6, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, +{"bts", 2, 0x0fab, X, wl_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, +{"bts", 2, 0x0fba, 5, wl_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, + +/* Interrupts & op. sys insns. */ /* See gas/config/tc-i386.c for conversion of 'int $3' into the special - int 3 insn. */ + int 3 insn. */ #define INT_OPCODE 0xcd #define INT3_OPCODE 0xcc -{"int", 1, 0xcd, _, NoModrm, { Imm8, 0, 0} }, -{"int3", 0, 0xcc, _, NoModrm, { 0, 0, 0} }, -{"into", 0, 0xce, _, NoModrm, { 0, 0, 0} }, -{"iret", 0, 0xcf, _, NoModrm|Data32, { 0, 0, 0} }, -{"iretw", 0, 0xcf, _, NoModrm|Data16, { 0, 0, 0} }, -/* i386sl, i486sl, later 486, and Pentium */ -{"rsm", 0, 0x0faa, _, NoModrm,{ 0, 0, 0} }, - -{"boundl", 2, 0x62, _, Modrm|Data32, { Reg32, Mem, 0} }, -{"boundw", 2, 0x62, _, Modrm|Data16, { Reg16, Mem, 0} }, - -{"hlt", 0, 0xf4, _, NoModrm, { 0, 0, 0} }, -{"wait", 0, 0x9b, _, NoModrm, { 0, 0, 0} }, -/* nop is actually 'xchgl %eax, %eax' */ -{"nop", 0, 0x90, _, NoModrm, { 0, 0, 0} }, - -/* protection control */ -{"arpl", 2, 0x63, _, Modrm, { Reg16, Reg16|Mem, 0} }, -{"lar", 2, 0x0f02, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} }, -{"lgdt", 1, 0x0f01, 2, Modrm, { Mem, 0, 0} }, -{"lidt", 1, 0x0f01, 3, Modrm, { Mem, 0, 0} }, -{"lldt", 1, 0x0f00, 2, Modrm, { WordReg|Mem, 0, 0} }, -{"lmsw", 1, 0x0f01, 6, Modrm, { WordReg|Mem, 0, 0} }, -{"lsl", 2, 0x0f03, _, Modrm|ReverseRegRegmem, { WordReg|Mem, WordReg, 0} }, -{"ltr", 1, 0x0f00, 3, Modrm, { WordReg|Mem, 0, 0} }, - -{"sgdt", 1, 0x0f01, 0, Modrm, { Mem, 0, 0} }, -{"sidt", 1, 0x0f01, 1, Modrm, { Mem, 0, 0} }, -{"sldt", 1, 0x0f00, 0, Modrm, { WordReg|Mem, 0, 0} }, -{"smsw", 1, 0x0f01, 4, Modrm, { WordReg|Mem, 0, 0} }, -{"str", 1, 0x0f00, 1, Modrm, { Reg16|Mem, 0, 0} }, - -{"verr", 1, 0x0f00, 4, Modrm, { WordReg|Mem, 0, 0} }, -{"verw", 1, 0x0f00, 5, Modrm, { WordReg|Mem, 0, 0} }, - -/* floating point instructions */ +{"int", 1, 0xcd, X, NoSuf, { Imm8, 0, 0} }, +{"int3", 0, 0xcc, X, NoSuf, { 0, 0, 0} }, +{"into", 0, 0xce, X, NoSuf, { 0, 0, 0} }, +{"iret", 0, 0xcf, X, wl_Suf, { 0, 0, 0} }, +/* i386sl, i486sl, later 486, and Pentium. */ +{"rsm", 0, 0x0faa, X, NoSuf, { 0, 0, 0} }, + +{"bound", 2, 0x62, X, wl_Suf|Modrm, { WordReg, WordMem, 0} }, + +{"hlt", 0, 0xf4, X, NoSuf, { 0, 0, 0} }, +/* nop is actually 'xchgl %eax, %eax'. */ +{"nop", 0, 0x90, X, NoSuf, { 0, 0, 0} }, + +/* Protection control. */ +{"arpl", 2, 0x63, X, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} }, +{"lar", 2, 0x0f02, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"lgdt", 1, 0x0f01, 2, wl_Suf|Modrm, { WordMem, 0, 0} }, +{"lidt", 1, 0x0f01, 3, wl_Suf|Modrm, { WordMem, 0, 0} }, +{"lldt", 1, 0x0f00, 2, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"lmsw", 1, 0x0f01, 6, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"lsl", 2, 0x0f03, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"ltr", 1, 0x0f00, 3, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, + +{"sgdt", 1, 0x0f01, 0, wl_Suf|Modrm, { WordMem, 0, 0} }, +{"sidt", 1, 0x0f01, 1, wl_Suf|Modrm, { WordMem, 0, 0} }, +{"sldt", 1, 0x0f00, 0, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} }, +{"smsw", 1, 0x0f01, 4, wl_Suf|Modrm, { WordReg|WordMem, 0, 0} }, +{"str", 1, 0x0f00, 1, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, + +{"verr", 1, 0x0f00, 4, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, +{"verw", 1, 0x0f00, 5, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, + +/* Floating point instructions. */ /* load */ -{"fld", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ -{"flds", 1, 0xd9, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem float */ -{"fldl", 1, 0xdd, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem double */ -{"fldl", 1, 0xd9c0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ -{"fild", 1, 0xdf, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem word (16) */ -{"fildl", 1, 0xdb, 0, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem dword (32) */ -{"fildq",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword (64) */ -{"fildll",1, 0xdf, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem qword (64) */ -{"fldt", 1, 0xdb, 5, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem efloat */ -{"fbld", 1, 0xdf, 4, Modrm, { Mem, 0, 0} }, /* %st0 <-- mem bcd */ +{"fld", 1, 0xd9c0, X, FP|ShortForm, { FloatReg, 0, 0} }, /* register */ +{"fld", 1, 0xd9, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* %st0 <-- mem float/double */ +{"fld", 1, 0xd9c0, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, +/* Intel Syntax */ +{"fld", 1, 0xdb, 5, x_FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem efloat */ +{"fild", 1, 0xdf, 0, sl_Suf|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* %st0 <-- mem word(16)/dword(32) */ +/* Intel Syntax */ +{"fildd", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */ +{"fildq", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */ +{"fildll", 1, 0xdf, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem qword (64) */ +{"fldt", 1, 0xdb, 5, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem efloat */ +{"fbld", 1, 0xdf, 4, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 <-- mem bcd */ /* store (no pop) */ -{"fst", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ -{"fsts", 1, 0xd9, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */ -{"fstl", 1, 0xdd, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double */ -{"fstl", 1, 0xddd0, _, ShortForm, { FloatReg, 0, 0} }, /* register */ -{"fist", 1, 0xdf, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word (16) */ -{"fistl", 1, 0xdb, 2, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */ +{"fst", 1, 0xddd0, X, FP|ShortForm, { FloatReg, 0, 0} }, /* register */ +{"fst", 1, 0xd9, 2, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* %st0 --> mem float/double */ +{"fst", 1, 0xddd0, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, +{"fist", 1, 0xdf, 2, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* %st0 --> mem word(16)/dword(32) */ /* store (with pop) */ -{"fstp", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */ -{"fstps", 1, 0xd9, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem float */ -{"fstpl", 1, 0xdd, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem double */ -{"fstpl", 1, 0xddd8, _, ShortForm, { FloatReg, 0, 0} }, /* register */ -{"fistp", 1, 0xdf, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem word (16) */ -{"fistpl",1, 0xdb, 3, Modrm, { Mem, 0, 0} }, /* %st0 --> mem dword (32) */ -{"fistpq",1, 0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */ -{"fistpll",1,0xdf, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem qword (64) */ -{"fstpt", 1, 0xdb, 7, Modrm, { Mem, 0, 0} }, /* %st0 --> mem efloat */ -{"fbstp", 1, 0xdf, 6, Modrm, { Mem, 0, 0} }, /* %st0 --> mem bcd */ +{"fstp", 1, 0xddd8, X, FP|ShortForm, { FloatReg, 0, 0} }, /* register */ +{"fstp", 1, 0xd9, 3, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* %st0 --> mem float/double */ +{"fstp", 1, 0xddd8, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, +/* Intel Syntax */ +{"fstp", 1, 0xdb, 7, x_FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem efloat */ +{"fistp", 1, 0xdf, 3, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* %st0 --> mem word(16)/dword(32) */ +/* Intel Syntax */ +{"fistpd", 1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */ +{"fistpq", 1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */ +{"fistpll",1, 0xdf, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem qword (64) */ +{"fstpt", 1, 0xdb, 7, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem efloat */ +{"fbstp", 1, 0xdf, 6, FP|Modrm, { LLongMem, 0, 0} }, /* %st0 --> mem bcd */ /* exchange %st<n> with %st0 */ -{"fxch", 1, 0xd9c8, _, ShortForm, { FloatReg, 0, 0} }, -{"fxch", 0, 0xd9c9, _, NoModrm, { 0, 0, 0} }, /* alias for fxch %st, %st(1) */ +{"fxch", 1, 0xd9c8, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fxch", 0, 0xd9c9, X, FP, { 0, 0, 0} }, /* alias for fxch %st(1) */ /* comparison (without pop) */ -{"fcom", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} }, -{"fcoms", 1, 0xd8, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem float */ -{"ficoml", 1, 0xda, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem dword */ -{"fcoml", 1, 0xdc, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem double */ -{"fcoml", 1, 0xd8d0, _, ShortForm, { FloatReg, 0, 0} }, -{"ficoms", 1, 0xde, 2, Modrm, { Mem, 0, 0} }, /* compare %st0, mem word */ +{"fcom", 1, 0xd8d0, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fcom", 0, 0xd8d1, X, FP, { 0, 0, 0} }, /* alias for fcom %st(1) */ +{"fcom", 1, 0xd8, 2, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* compare %st0, mem float/double */ +{"fcom", 1, 0xd8d0, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, +{"ficom", 1, 0xde, 2, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* compare %st0, mem word/dword */ /* comparison (with pop) */ -{"fcomp", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} }, -{"fcomp", 0, 0xd8d9, _, NoModrm, {0, 0, 0} }, /* fcomp %st, %st(1) */ -{"fcomps", 1, 0xd8, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem float */ -{"ficompl", 1, 0xda, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem dword */ -{"fcompl", 1, 0xdc, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem double */ -{"fcompl", 1, 0xd8d8, _, ShortForm, { FloatReg, 0, 0} }, -{"ficomps", 1, 0xde, 3, Modrm, { Mem, 0, 0} }, /* compare %st0, mem word */ -{"fcompp", 0, 0xded9, _, NoModrm, { 0, 0, 0} }, /* compare %st0, %st1 & pop 2 */ +{"fcomp", 1, 0xd8d8, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fcomp", 0, 0xd8d9, X, FP, { 0, 0, 0} }, /* alias for fcomp %st(1) */ +{"fcomp", 1, 0xd8, 3, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, /* compare %st0, mem float/double */ +{"fcomp", 1, 0xd8d8, X, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, +{"ficomp", 1, 0xde, 3, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, /* compare %st0, mem word/dword */ +{"fcompp", 0, 0xded9, X, FP, { 0, 0, 0} }, /* compare %st0, %st1 & pop 2 */ /* unordered comparison (with pop) */ -{"fucom", 1, 0xdde0, _, ShortForm, { FloatReg, 0, 0} }, -{"fucomp", 1, 0xdde8, _, ShortForm, { FloatReg, 0, 0} }, -{"fucompp", 0, 0xdae9, _, NoModrm, { 0, 0, 0} }, /* ucompare %st0, %st1 & pop twice */ +{"fucom", 1, 0xdde0, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fucom", 0, 0xdde1, X, FP, { 0, 0, 0} }, /* alias for fucom %st(1) */ +{"fucomp", 1, 0xdde8, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fucomp", 0, 0xdde9, X, FP, { 0, 0, 0} }, /* alias for fucomp %st(1) */ +{"fucompp",0, 0xdae9, X, FP, { 0, 0, 0} }, /* ucompare %st0, %st1 & pop twice */ -{"ftst", 0, 0xd9e4, _, NoModrm, { 0, 0, 0} }, /* test %st0 */ -{"fxam", 0, 0xd9e5, _, NoModrm, { 0, 0, 0} }, /* examine %st0 */ +{"ftst", 0, 0xd9e4, X, FP, { 0, 0, 0} }, /* test %st0 */ +{"fxam", 0, 0xd9e5, X, FP, { 0, 0, 0} }, /* examine %st0 */ /* load constants into %st0 */ -{"fld1", 0, 0xd9e8, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- 1.0 */ -{"fldl2t", 0, 0xd9e9, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log2(10) */ -{"fldl2e", 0, 0xd9ea, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log2(e) */ -{"fldpi", 0, 0xd9eb, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- pi */ -{"fldlg2", 0, 0xd9ec, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- log10(2) */ -{"fldln2", 0, 0xd9ed, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- ln(2) */ -{"fldz", 0, 0xd9ee, _, NoModrm, { 0, 0, 0} }, /* %st0 <-- 0.0 */ +{"fld1", 0, 0xd9e8, X, FP, { 0, 0, 0} }, /* %st0 <-- 1.0 */ +{"fldl2t", 0, 0xd9e9, X, FP, { 0, 0, 0} }, /* %st0 <-- log2(10) */ +{"fldl2e", 0, 0xd9ea, X, FP, { 0, 0, 0} }, /* %st0 <-- log2(e) */ +{"fldpi", 0, 0xd9eb, X, FP, { 0, 0, 0} }, /* %st0 <-- pi */ +{"fldlg2", 0, 0xd9ec, X, FP, { 0, 0, 0} }, /* %st0 <-- log10(2) */ +{"fldln2", 0, 0xd9ed, X, FP, { 0, 0, 0} }, /* %st0 <-- ln(2) */ +{"fldz", 0, 0xd9ee, X, FP, { 0, 0, 0} }, /* %st0 <-- 0.0 */ /* arithmetic */ /* add */ -{"fadd", 1, 0xd8c0, _, ShortForm, { FloatReg, 0, 0} }, -{"fadd", 2, 0xd8c0, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, -{"fadd", 0, 0xdcc1, _, NoModrm, { 0, 0, 0} }, /* alias for fadd %st, %st(1) */ -{"faddp", 1, 0xdec0, _, ShortForm, { FloatReg, 0, 0} }, -{"faddp", 2, 0xdec0, _, ShortForm, { FloatReg, FloatAcc, 0} }, -{"faddp", 2, 0xdec0, _, ShortForm, { FloatAcc, FloatReg, 0} }, -{"faddp", 0, 0xdec1, _, NoModrm, { 0, 0, 0} }, /* alias for faddp %st, %st(1) */ -{"fadds", 1, 0xd8, 0, Modrm, { Mem, 0, 0} }, -{"fiaddl", 1, 0xda, 0, Modrm, { Mem, 0, 0} }, -{"faddl", 1, 0xdc, 0, Modrm, { Mem, 0, 0} }, -{"fiadds", 1, 0xde, 0, Modrm, { Mem, 0, 0} }, - -/* sub */ -/* Note: intel has decided that certain of these operations are reversed - in assembler syntax. */ -{"fsub", 1, 0xd8e0, _, ShortForm, { FloatReg, 0, 0} }, -{"fsub", 2, 0xd8e0, _, ShortForm, { FloatReg, FloatAcc, 0} }, -#ifdef NON_BROKEN_OPCODES -{"fsub", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} }, -#else -{"fsub", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} }, +{"fadd", 2, 0xd8c0, X, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, +{"fadd", 1, 0xd8c0, X, FP|ShortForm, { FloatReg, 0, 0} }, /* alias for fadd %st(i), %st */ +#if SYSV386_COMPAT +{"fadd", 0, 0xdec1, X, FP|Ugh, { 0, 0, 0} }, /* alias for faddp */ #endif -{"fsub", 0, 0xdce1, _, NoModrm, { 0, 0, 0} }, -{"fsubp", 1, 0xdee8, _, ShortForm, { FloatReg, 0, 0} }, -{"fsubp", 2, 0xdee8, _, ShortForm, { FloatReg, FloatAcc, 0} }, -#ifdef NON_BROKEN_OPCODES -{"fsubp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} }, -{"fsubp", 0, 0xdee9, _, NoModrm, { 0, 0, 0} }, -#else -{"fsubp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} }, -{"fsubp", 0, 0xdee1, _, NoModrm, { 0, 0, 0} }, +{"fadd", 1, 0xd8, 0, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fiadd", 1, 0xde, 0, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, + +{"faddp", 2, 0xdec0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"faddp", 1, 0xdec0, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"faddp", 0, 0xdec1, X, FP, { 0, 0, 0} }, /* alias for faddp %st, %st(1) */ +{"faddp", 2, 0xdec0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, + +/* subtract */ +{"fsub", 2, 0xd8e0, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, +{"fsub", 1, 0xd8e0, X, FP|ShortForm, { FloatReg, 0, 0} }, +#if SYSV386_COMPAT +{"fsub", 0, 0xdee1, X, FP|Ugh, { 0, 0, 0} }, /* alias for fsubp */ #endif -{"fsubs", 1, 0xd8, 4, Modrm, { Mem, 0, 0} }, -{"fisubl", 1, 0xda, 4, Modrm, { Mem, 0, 0} }, -{"fsubl", 1, 0xdc, 4, Modrm, { Mem, 0, 0} }, -{"fisubs", 1, 0xde, 4, Modrm, { Mem, 0, 0} }, - -/* sub reverse */ -{"fsubr", 1, 0xd8e8, _, ShortForm, { FloatReg, 0, 0} }, -{"fsubr", 2, 0xd8e8, _, ShortForm, { FloatReg, FloatAcc, 0} }, -#ifdef NON_BROKEN_OPCODES -{"fsubr", 2, 0xdce0, _, ShortForm, { FloatAcc, FloatReg, 0} }, -#else -{"fsubr", 2, 0xdce8, _, ShortForm, { FloatAcc, FloatReg, 0} }, +{"fsub", 1, 0xd8, 4, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fisub", 1, 0xde, 4, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, + +#if SYSV386_COMPAT +{"fsubp", 2, 0xdee0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fsubp", 1, 0xdee0, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fsubp", 0, 0xdee1, X, FP, { 0, 0, 0} }, +#if OLDGCC_COMPAT +{"fsubp", 2, 0xdee0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, #endif -{"fsubr", 0, 0xdce9, _, NoModrm, { 0, 0, 0} }, -{"fsubrp", 1, 0xdee0, _, ShortForm, { FloatReg, 0, 0} }, -{"fsubrp", 2, 0xdee0, _, ShortForm, { FloatReg, FloatAcc, 0} }, -#ifdef NON_BROKEN_OPCODES -{"fsubrp", 2, 0xdee0, _, ShortForm, { FloatAcc, FloatReg, 0} }, -{"fsubrp", 0, 0xdee1, _, NoModrm, { 0, 0, 0} }, #else -{"fsubrp", 2, 0xdee8, _, ShortForm, { FloatAcc, FloatReg, 0} }, -{"fsubrp", 0, 0xdee9, _, NoModrm, { 0, 0, 0} }, +{"fsubp", 2, 0xdee8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fsubp", 1, 0xdee8, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fsubp", 0, 0xdee9, X, FP, { 0, 0, 0} }, #endif -{"fsubrs", 1, 0xd8, 5, Modrm, { Mem, 0, 0} }, -{"fisubrl", 1, 0xda, 5, Modrm, { Mem, 0, 0} }, -{"fsubrl", 1, 0xdc, 5, Modrm, { Mem, 0, 0} }, -{"fisubrs", 1, 0xde, 5, Modrm, { Mem, 0, 0} }, - -/* mul */ -{"fmul", 1, 0xd8c8, _, ShortForm, { FloatReg, 0, 0} }, -{"fmul", 2, 0xd8c8, _, ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, -{"fmul", 0, 0xdcc9, _, NoModrm, { 0, 0, 0} }, -{"fmulp", 1, 0xdec8, _, ShortForm, { FloatReg, 0, 0} }, -{"fmulp", 2, 0xdec8, _, ShortForm, { FloatReg, FloatAcc, 0} }, -{"fmulp", 2, 0xdec8, _, ShortForm, { FloatAcc, FloatReg, 0} }, -{"fmulp", 0, 0xdec9, _, NoModrm, { 0, 0, 0} }, -{"fmuls", 1, 0xd8, 1, Modrm, { Mem, 0, 0} }, -{"fimull", 1, 0xda, 1, Modrm, { Mem, 0, 0} }, -{"fmull", 1, 0xdc, 1, Modrm, { Mem, 0, 0} }, -{"fimuls", 1, 0xde, 1, Modrm, { Mem, 0, 0} }, - -/* div */ -/* Note: intel has decided that certain of these operations are reversed - in assembler syntax. */ -{"fdiv", 1, 0xd8f0, _, ShortForm, { FloatReg, 0, 0} }, -{"fdiv", 2, 0xd8f0, _, ShortForm, { FloatReg, FloatAcc, 0} }, -#ifdef NON_BROKEN_OPCODES -{"fdiv", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} }, -#else -{"fdiv", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} }, + +/* subtract reverse */ +{"fsubr", 2, 0xd8e8, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, +{"fsubr", 1, 0xd8e8, X, FP|ShortForm, { FloatReg, 0, 0} }, +#if SYSV386_COMPAT +{"fsubr", 0, 0xdee9, X, FP|Ugh, { 0, 0, 0} }, /* alias for fsubrp */ +#endif +{"fsubr", 1, 0xd8, 5, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fisubr", 1, 0xde, 5, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, + +#if SYSV386_COMPAT +{"fsubrp", 2, 0xdee8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fsubrp", 1, 0xdee8, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fsubrp", 0, 0xdee9, X, FP, { 0, 0, 0} }, +#if OLDGCC_COMPAT +{"fsubrp", 2, 0xdee8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, #endif -{"fdiv", 0, 0xdcf1, _, NoModrm, { 0, 0, 0} }, -{"fdivp", 1, 0xdef8, _, ShortForm, { FloatReg, 0, 0} }, -{"fdivp", 2, 0xdef8, _, ShortForm, { FloatReg, FloatAcc, 0} }, -#ifdef NON_BROKEN_OPCODES -{"fdivp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} }, -{"fdivp", 0, 0xdef9, _, NoModrm, { 0, 0, 0} }, #else -{"fdivp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} }, -{"fdivp", 0, 0xdef1, _, NoModrm, { 0, 0, 0} }, +{"fsubrp", 2, 0xdee0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fsubrp", 1, 0xdee0, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fsubrp", 0, 0xdee1, X, FP, { 0, 0, 0} }, +#endif + +/* multiply */ +{"fmul", 2, 0xd8c8, X, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, +{"fmul", 1, 0xd8c8, X, FP|ShortForm, { FloatReg, 0, 0} }, +#if SYSV386_COMPAT +{"fmul", 0, 0xdec9, X, FP|Ugh, { 0, 0, 0} }, /* alias for fmulp */ +#endif +{"fmul", 1, 0xd8, 1, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fimul", 1, 0xde, 1, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, + +{"fmulp", 2, 0xdec8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fmulp", 1, 0xdec8, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fmulp", 0, 0xdec9, X, FP, { 0, 0, 0} }, +{"fmulp", 2, 0xdec8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, + +/* divide */ +{"fdiv", 2, 0xd8f0, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, +{"fdiv", 1, 0xd8f0, X, FP|ShortForm, { FloatReg, 0, 0} }, +#if SYSV386_COMPAT +{"fdiv", 0, 0xdef1, X, FP|Ugh, { 0, 0, 0} }, /* alias for fdivp */ +#endif +{"fdiv", 1, 0xd8, 6, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fidiv", 1, 0xde, 6, sld_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, + +#if SYSV386_COMPAT +{"fdivp", 2, 0xdef0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fdivp", 1, 0xdef0, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fdivp", 0, 0xdef1, X, FP, { 0, 0, 0} }, +#if OLDGCC_COMPAT +{"fdivp", 2, 0xdef0, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, #endif -{"fdivs", 1, 0xd8, 6, Modrm, { Mem, 0, 0} }, -{"fidivl", 1, 0xda, 6, Modrm, { Mem, 0, 0} }, -{"fdivl", 1, 0xdc, 6, Modrm, { Mem, 0, 0} }, -{"fidivs", 1, 0xde, 6, Modrm, { Mem, 0, 0} }, - -/* div reverse */ -{"fdivr", 1, 0xd8f8, _, ShortForm, { FloatReg, 0, 0} }, -{"fdivr", 2, 0xd8f8, _, ShortForm, { FloatReg, FloatAcc, 0} }, -#ifdef NON_BROKEN_OPCODES -{"fdivr", 2, 0xdcf0, _, ShortForm, { FloatAcc, FloatReg, 0} }, #else -{"fdivr", 2, 0xdcf8, _, ShortForm, { FloatAcc, FloatReg, 0} }, +{"fdivp", 2, 0xdef8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fdivp", 1, 0xdef8, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fdivp", 0, 0xdef9, X, FP, { 0, 0, 0} }, +#endif + +/* divide reverse */ +{"fdivr", 2, 0xd8f8, X, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, +{"fdivr", 1, 0xd8f8, X, FP|ShortForm, { FloatReg, 0, 0} }, +#if SYSV386_COMPAT +{"fdivr", 0, 0xdef9, X, FP|Ugh, { 0, 0, 0} }, /* alias for fdivrp */ +#endif +{"fdivr", 1, 0xd8, 7, sld_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fidivr", 1, 0xde, 7, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, + +#if SYSV386_COMPAT +{"fdivrp", 2, 0xdef8, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fdivrp", 1, 0xdef8, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fdivrp", 0, 0xdef9, X, FP, { 0, 0, 0} }, +#if OLDGCC_COMPAT +{"fdivrp", 2, 0xdef8, X, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, #endif -{"fdivr", 0, 0xdcf9, _, NoModrm, { 0, 0, 0} }, -{"fdivrp", 1, 0xdef0, _, ShortForm, { FloatReg, 0, 0} }, -{"fdivrp", 2, 0xdef0, _, ShortForm, { FloatReg, FloatAcc, 0} }, -#ifdef NON_BROKEN_OPCODES -{"fdivrp", 2, 0xdef0, _, ShortForm, { FloatAcc, FloatReg, 0} }, -{"fdivrp", 0, 0xdef1, _, NoModrm, { 0, 0, 0} }, #else -{"fdivrp", 2, 0xdef8, _, ShortForm, { FloatAcc, FloatReg, 0} }, -{"fdivrp", 0, 0xdef9, _, NoModrm, { 0, 0, 0} }, +{"fdivrp", 2, 0xdef0, X, FP|ShortForm, { FloatAcc, FloatReg, 0} }, +{"fdivrp", 1, 0xdef0, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fdivrp", 0, 0xdef1, X, FP, { 0, 0, 0} }, #endif -{"fdivrs", 1, 0xd8, 7, Modrm, { Mem, 0, 0} }, -{"fidivrl", 1, 0xda, 7, Modrm, { Mem, 0, 0} }, -{"fdivrl", 1, 0xdc, 7, Modrm, { Mem, 0, 0} }, -{"fidivrs", 1, 0xde, 7, Modrm, { Mem, 0, 0} }, - -{"f2xm1", 0, 0xd9f0, _, NoModrm, { 0, 0, 0} }, -{"fyl2x", 0, 0xd9f1, _, NoModrm, { 0, 0, 0} }, -{"fptan", 0, 0xd9f2, _, NoModrm, { 0, 0, 0} }, -{"fpatan", 0, 0xd9f3, _, NoModrm, { 0, 0, 0} }, -{"fxtract", 0, 0xd9f4, _, NoModrm, { 0, 0, 0} }, -{"fprem1", 0, 0xd9f5, _, NoModrm, { 0, 0, 0} }, -{"fdecstp", 0, 0xd9f6, _, NoModrm, { 0, 0, 0} }, -{"fincstp", 0, 0xd9f7, _, NoModrm, { 0, 0, 0} }, -{"fprem", 0, 0xd9f8, _, NoModrm, { 0, 0, 0} }, -{"fyl2xp1", 0, 0xd9f9, _, NoModrm, { 0, 0, 0} }, -{"fsqrt", 0, 0xd9fa, _, NoModrm, { 0, 0, 0} }, -{"fsincos", 0, 0xd9fb, _, NoModrm, { 0, 0, 0} }, -{"frndint", 0, 0xd9fc, _, NoModrm, { 0, 0, 0} }, -{"fscale", 0, 0xd9fd, _, NoModrm, { 0, 0, 0} }, -{"fsin", 0, 0xd9fe, _, NoModrm, { 0, 0, 0} }, -{"fcos", 0, 0xd9ff, _, NoModrm, { 0, 0, 0} }, - -{"fchs", 0, 0xd9e0, _, NoModrm, { 0, 0, 0} }, -{"fabs", 0, 0xd9e1, _, NoModrm, { 0, 0, 0} }, + +{"f2xm1", 0, 0xd9f0, X, FP, { 0, 0, 0} }, +{"fyl2x", 0, 0xd9f1, X, FP, { 0, 0, 0} }, +{"fptan", 0, 0xd9f2, X, FP, { 0, 0, 0} }, +{"fpatan", 0, 0xd9f3, X, FP, { 0, 0, 0} }, +{"fxtract",0, 0xd9f4, X, FP, { 0, 0, 0} }, +{"fprem1", 0, 0xd9f5, X, FP, { 0, 0, 0} }, +{"fdecstp",0, 0xd9f6, X, FP, { 0, 0, 0} }, +{"fincstp",0, 0xd9f7, X, FP, { 0, 0, 0} }, +{"fprem", 0, 0xd9f8, X, FP, { 0, 0, 0} }, +{"fyl2xp1",0, 0xd9f9, X, FP, { 0, 0, 0} }, +{"fsqrt", 0, 0xd9fa, X, FP, { 0, 0, 0} }, +{"fsincos",0, 0xd9fb, X, FP, { 0, 0, 0} }, +{"frndint",0, 0xd9fc, X, FP, { 0, 0, 0} }, +{"fscale", 0, 0xd9fd, X, FP, { 0, 0, 0} }, +{"fsin", 0, 0xd9fe, X, FP, { 0, 0, 0} }, +{"fcos", 0, 0xd9ff, X, FP, { 0, 0, 0} }, +{"fchs", 0, 0xd9e0, X, FP, { 0, 0, 0} }, +{"fabs", 0, 0xd9e1, X, FP, { 0, 0, 0} }, /* processor control */ -{"fninit", 0, 0xdbe3, _, NoModrm, { 0, 0, 0} }, -{"finit", 0, 0xdbe3, _, FWait|NoModrm, { 0, 0, 0} }, -{"fldcw", 1, 0xd9, 5, Modrm, { Mem, 0, 0} }, -{"fnstcw", 1, 0xd9, 7, Modrm, { Mem, 0, 0} }, -{"fstcw", 1, 0xd9, 7, FWait|Modrm, { Mem, 0, 0} }, -{"fnstsw", 1, 0xdfe0, _, NoModrm, { Acc, 0, 0} }, -{"fnstsw", 1, 0xdd, 7, Modrm, { Mem, 0, 0} }, -{"fnstsw", 0, 0xdfe0, _, NoModrm, { 0, 0, 0} }, -{"fstsw", 1, 0xdfe0, _, FWait|NoModrm, { Acc, 0, 0} }, -{"fstsw", 1, 0xdd, 7, FWait|Modrm, { Mem, 0, 0} }, -{"fstsw", 0, 0xdfe0, _, FWait|NoModrm, { 0, 0, 0} }, -{"fnclex", 0, 0xdbe2, _, NoModrm, { 0, 0, 0} }, -{"fclex", 0, 0xdbe2, _, FWait|NoModrm, { 0, 0, 0} }, -{"fnstenv",1, 0xd9, 6, Modrm, { Mem, 0, 0} }, -{"fstenv", 1, 0xd9, 6, FWait|Modrm, { Mem, 0, 0} }, -{"fldenv", 1, 0xd9, 4, Modrm, { Mem, 0, 0} }, -{"fnsave", 1, 0xdd, 6, Modrm, { Mem, 0, 0} }, -{"fsave", 1, 0xdd, 6, FWait|Modrm, { Mem, 0, 0} }, -{"frstor", 1, 0xdd, 4, Modrm, { Mem, 0, 0} }, -/* Short forms of fldenv, fstenv use data size prefix. (At least I - think so. The PentPro prog ref I have says address size in one - place, operand size elsewhere). FIXME: Are these the right names? */ -{"fnstenvs",1, 0xd9, 6, Modrm|Data16, { Mem, 0, 0} }, -{"fstenvs", 1, 0xd9, 6, FWait|Modrm|Data16, { Mem, 0, 0} }, -{"fldenvs", 1, 0xd9, 4, Modrm|Data16, { Mem, 0, 0} }, - -{"ffree", 1, 0xddc0, _, ShortForm, { FloatReg, 0, 0} }, +{"fninit", 0, 0xdbe3, X, FP, { 0, 0, 0} }, +{"finit", 0, 0xdbe3, X, FP|FWait, { 0, 0, 0} }, +{"fldcw", 1, 0xd9, 5, FP|Modrm, { ShortMem, 0, 0} }, +{"fnstcw", 1, 0xd9, 7, FP|Modrm, { ShortMem, 0, 0} }, +{"fstcw", 1, 0xd9, 7, FP|FWait|Modrm, { ShortMem, 0, 0} }, +{"fnstsw", 1, 0xdfe0, X, FP, { Acc, 0, 0} }, +{"fnstsw", 1, 0xdd, 7, FP|Modrm, { ShortMem, 0, 0} }, +{"fnstsw", 0, 0xdfe0, X, FP, { 0, 0, 0} }, +{"fstsw", 1, 0xdfe0, X, FP|FWait, { Acc, 0, 0} }, +{"fstsw", 1, 0xdd, 7, FP|FWait|Modrm, { ShortMem, 0, 0} }, +{"fstsw", 0, 0xdfe0, X, FP|FWait, { 0, 0, 0} }, +{"fnclex", 0, 0xdbe2, X, FP, { 0, 0, 0} }, +{"fclex", 0, 0xdbe2, X, FP|FWait, { 0, 0, 0} }, +/* Short forms of fldenv, fstenv use data size prefix. */ +{"fnstenv",1, 0xd9, 6, sl_Suf|Modrm, { LLongMem, 0, 0} }, +{"fstenv", 1, 0xd9, 6, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} }, +{"fldenv", 1, 0xd9, 4, sl_Suf|Modrm, { LLongMem, 0, 0} }, +{"fnsave", 1, 0xdd, 6, sl_Suf|Modrm, { LLongMem, 0, 0} }, +{"fsave", 1, 0xdd, 6, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} }, +{"frstor", 1, 0xdd, 4, sl_Suf|Modrm, { LLongMem, 0, 0} }, + +{"ffree", 1, 0xddc0, X, FP|ShortForm, { FloatReg, 0, 0} }, /* P6:free st(i), pop st */ -{"ffreep", 1, 0xdfc0, _, ShortForm, { FloatReg, 0, 0} }, -{"fnop", 0, 0xd9d0, _, NoModrm, { 0, 0, 0} }, +{"ffreep", 1, 0xdfc0, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fnop", 0, 0xd9d0, X, FP, { 0, 0, 0} }, #define FWAIT_OPCODE 0x9b -{"fwait", 0, 0x9b, _, NoModrm, { 0, 0, 0} }, - -/* - opcode prefixes; we allow them as seperate insns too - (see prefix table below) -*/ -{"aword", 0, 0x67, _, NoModrm, { 0, 0, 0} }, -{"addr16", 0, 0x67, _, NoModrm, { 0, 0, 0} }, -{"word", 0, 0x66, _, NoModrm, { 0, 0, 0} }, -{"data16", 0, 0x66, _, NoModrm, { 0, 0, 0} }, -{"lock", 0, 0xf0, _, NoModrm, { 0, 0, 0} }, -{"cs", 0, 0x2e, _, NoModrm, { 0, 0, 0} }, -{"ds", 0, 0x3e, _, NoModrm, { 0, 0, 0} }, -{"es", 0, 0x26, _, NoModrm, { 0, 0, 0} }, -{"fs", 0, 0x64, _, NoModrm, { 0, 0, 0} }, -{"gs", 0, 0x65, _, NoModrm, { 0, 0, 0} }, -{"ss", 0, 0x36, _, NoModrm, { 0, 0, 0} }, -{"rep", 0, 0xf3, _, NoModrm, { 0, 0, 0} }, -{"repe", 0, 0xf3, _, NoModrm, { 0, 0, 0} }, -{"repz", 0, 0xf3, _, NoModrm, { 0, 0, 0} }, -{"repne", 0, 0xf2, _, NoModrm, { 0, 0, 0} }, -{"repnz", 0, 0xf2, _, NoModrm, { 0, 0, 0} }, - -/* 486 extensions */ - -{"bswap", 1, 0x0fc8, _, ShortForm, { Reg32,0,0 } }, -{"xadd", 2, 0x0fc0, _, W|Modrm, { Reg, Reg|Mem, 0 } }, -{"cmpxchg", 2, 0x0fb0, _, W|Modrm, { Reg, Reg|Mem, 0 } }, -{"invd", 0, 0x0f08, _, NoModrm, { 0, 0, 0} }, -{"wbinvd", 0, 0x0f09, _, NoModrm, { 0, 0, 0} }, -{"invlpg", 1, 0x0f01, 7, Modrm, { Mem, 0, 0} }, - -/* 586 and late 486 extensions */ -{"cpuid", 0, 0x0fa2, _, NoModrm, { 0, 0, 0} }, - -/* Pentium extensions */ -{"wrmsr", 0, 0x0f30, _, NoModrm, { 0, 0, 0} }, -{"rdtsc", 0, 0x0f31, _, NoModrm, { 0, 0, 0} }, -{"rdmsr", 0, 0x0f32, _, NoModrm, { 0, 0, 0} }, -{"cmpxchg8b", 1, 0x0fc7, 1, Modrm, { Mem, 0, 0} }, - -/* Pentium Pro extensions */ -{"rdpmc", 0, 0x0f33, _, NoModrm, { 0, 0, 0} }, - -{"ud2", 0, 0x0f0b, _, NoModrm, {0, 0, 0} }, /* official undefined instr. */ - -{"cmovo", 2, 0x0f40, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, -{"cmovno", 2, 0x0f41, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, -{"cmovb", 2, 0x0f42, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, -{"cmovae", 2, 0x0f43, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, -{"cmove", 2, 0x0f44, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, -{"cmovne", 2, 0x0f45, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, -{"cmovbe", 2, 0x0f46, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, -{"cmova", 2, 0x0f47, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, -{"cmovs", 2, 0x0f48, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, -{"cmovns", 2, 0x0f49, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, -{"cmovp", 2, 0x0f4a, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, -{"cmovnp", 2, 0x0f4b, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, -{"cmovl", 2, 0x0f4c, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, -{"cmovge", 2, 0x0f4d, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, -{"cmovle", 2, 0x0f4e, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, -{"cmovg", 2, 0x0f4f, _, Modrm|ReverseRegRegmem, { WordReg|WordMem, WordReg, 0} }, - -{"fcmovb", 2, 0xdac0, _, ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmove", 2, 0xdac8, _, ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovbe",2, 0xdad0, _, ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovu", 2, 0xdad8, _, ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnb", 2, 0xdbc0, _, ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovne", 2, 0xdbc8, _, ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnbe",2, 0xdbd0, _, ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnu", 2, 0xdbd8, _, ShortForm, { FloatReg, FloatAcc, 0} }, - -{"fcomi", 2, 0xdbf0, _, ShortForm, { FloatReg, FloatAcc, 0} }, -{"fucomi", 2, 0xdbe8, _, ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcomip", 2, 0xdff0, _, ShortForm, { FloatReg, FloatAcc, 0} }, -{"fucomip",2, 0xdfe8, _, ShortForm, { FloatReg, FloatAcc, 0} }, +{"fwait", 0, 0x9b, X, FP, { 0, 0, 0} }, -/* MMX instructions. */ +/* Opcode prefixes; we allow them as separate insns too. */ -{"emms", 0, 0x0f77, _, NoModrm, { 0, 0, 0 } }, -{"movd", 2, 0x0f6e, _, Modrm, { Reg32|WordMem, RegMMX, 0 } }, -{"movd", 2, 0x0f7e, _, Modrm, { RegMMX, Reg32|WordMem, 0 } }, -{"movq", 2, 0x0f6f, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"movq", 2, 0x0f7f, _, Modrm, { RegMMX, RegMMX|WordMem, 0 } }, -{"packssdw", 2, 0x0f6b, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"packsswb", 2, 0x0f63, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"packuswb", 2, 0x0f67, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"paddb", 2, 0x0ffc, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"paddw", 2, 0x0ffd, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"paddd", 2, 0x0ffe, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"paddsb", 2, 0x0fec, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"paddsw", 2, 0x0fed, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"paddusb", 2, 0x0fdc, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"paddusw", 2, 0x0fdd, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"pand", 2, 0x0fdb, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"pandn", 2, 0x0fdf, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"pcmpeqb", 2, 0x0f74, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"pcmpeqw", 2, 0x0f75, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"pcmpeqd", 2, 0x0f76, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"pcmpgtb", 2, 0x0f64, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"pcmpgtw", 2, 0x0f65, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"pcmpgtd", 2, 0x0f66, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"pmaddwd", 2, 0x0ff5, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"pmulhw", 2, 0x0fe5, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"pmullw", 2, 0x0fd5, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"por", 2, 0x0feb, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"psllw", 2, 0x0ff1, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"psllw", 2, 0x0f71, 6, Modrm, { Imm8, RegMMX, 0 } }, -{"pslld", 2, 0x0ff2, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"pslld", 2, 0x0f72, 6, Modrm, { Imm8, RegMMX, 0 } }, -{"psllq", 2, 0x0ff3, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"psllq", 2, 0x0f73, 6, Modrm, { Imm8, RegMMX, 0 } }, -{"psraw", 2, 0x0fe1, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"psraw", 2, 0x0f71, 4, Modrm, { Imm8, RegMMX, 0 } }, -{"psrad", 2, 0x0fe2, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"psrad", 2, 0x0f72, 4, Modrm, { Imm8, RegMMX, 0 } }, -{"psrlw", 2, 0x0fd1, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"psrlw", 2, 0x0f71, 2, Modrm, { Imm8, RegMMX, 0 } }, -{"psrld", 2, 0x0fd2, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"psrld", 2, 0x0f72, 2, Modrm, { Imm8, RegMMX, 0 } }, -{"psrlq", 2, 0x0fd3, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"psrlq", 2, 0x0f73, 2, Modrm, { Imm8, RegMMX, 0 } }, -{"psubb", 2, 0x0ff8, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"psubw", 2, 0x0ff9, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"psubd", 2, 0x0ffa, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"psubsb", 2, 0x0fe8, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"psubsw", 2, 0x0fe9, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"psubusb", 2, 0x0fd8, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"psubusw", 2, 0x0fd9, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"punpckhbw", 2, 0x0f68, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"punpckhwd", 2, 0x0f69, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"punpckhdq", 2, 0x0f6a, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"punpcklbw", 2, 0x0f60, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"punpcklwd", 2, 0x0f61, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"punpckldq", 2, 0x0f62, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, -{"pxor", 2, 0x0fef, _, Modrm, { RegMMX|WordMem, RegMMX, 0 } }, - -{"", 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */ -}; -#undef _ +#define ADDR_PREFIX_OPCODE 0x67 +{"addr16", 0, 0x67, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, +{"addr32", 0, 0x67, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, +{"aword", 0, 0x67, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, +{"adword", 0, 0x67, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, +#define DATA_PREFIX_OPCODE 0x66 +{"data16", 0, 0x66, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, +{"data32", 0, 0x66, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, +{"word", 0, 0x66, X, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, +{"dword", 0, 0x66, X, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, +#define LOCK_PREFIX_OPCODE 0xf0 +{"lock", 0, 0xf0, X, NoSuf|IsPrefix, { 0, 0, 0} }, +{"wait", 0, 0x9b, X, NoSuf|IsPrefix, { 0, 0, 0} }, +#define CS_PREFIX_OPCODE 0x2e +{"cs", 0, 0x2e, X, NoSuf|IsPrefix, { 0, 0, 0} }, +#define DS_PREFIX_OPCODE 0x3e +{"ds", 0, 0x3e, X, NoSuf|IsPrefix, { 0, 0, 0} }, +#define ES_PREFIX_OPCODE 0x26 +{"es", 0, 0x26, X, NoSuf|IsPrefix, { 0, 0, 0} }, +#define FS_PREFIX_OPCODE 0x64 +{"fs", 0, 0x64, X, NoSuf|IsPrefix, { 0, 0, 0} }, +#define GS_PREFIX_OPCODE 0x65 +{"gs", 0, 0x65, X, NoSuf|IsPrefix, { 0, 0, 0} }, +#define SS_PREFIX_OPCODE 0x36 +{"ss", 0, 0x36, X, NoSuf|IsPrefix, { 0, 0, 0} }, +#define REPNE_PREFIX_OPCODE 0xf2 +#define REPE_PREFIX_OPCODE 0xf3 +{"rep", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} }, +{"repe", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} }, +{"repz", 0, 0xf3, X, NoSuf|IsPrefix, { 0, 0, 0} }, +{"repne", 0, 0xf2, X, NoSuf|IsPrefix, { 0, 0, 0} }, +{"repnz", 0, 0xf2, X, NoSuf|IsPrefix, { 0, 0, 0} }, + +/* 486 extensions. */ + +{"bswap", 1, 0x0fc8, X, l_Suf|ShortForm, { Reg32, 0, 0 } }, +{"xadd", 2, 0x0fc0, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, +{"cmpxchg", 2, 0x0fb0, X, bwl_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, +{"invd", 0, 0x0f08, X, NoSuf, { 0, 0, 0} }, +{"wbinvd", 0, 0x0f09, X, NoSuf, { 0, 0, 0} }, +{"invlpg", 1, 0x0f01, 7, NoSuf|Modrm, { AnyMem, 0, 0} }, + +/* 586 and late 486 extensions. */ +{"cpuid", 0, 0x0fa2, X, NoSuf, { 0, 0, 0} }, + +/* Pentium extensions. */ +{"wrmsr", 0, 0x0f30, X, NoSuf, { 0, 0, 0} }, +{"rdtsc", 0, 0x0f31, X, NoSuf, { 0, 0, 0} }, +{"rdmsr", 0, 0x0f32, X, NoSuf, { 0, 0, 0} }, +{"cmpxchg8b",1,0x0fc7, 1, NoSuf|Modrm, { LLongMem, 0, 0} }, +{"sysenter",0, 0x0f34, X, NoSuf, { 0, 0, 0} }, +{"sysexit", 0, 0x0f35, X, NoSuf, { 0, 0, 0} }, +{"fxsave", 1, 0x0fae, 0, FP|Modrm, { LLongMem, 0, 0} }, +{"fxrstor", 1, 0x0fae, 1, FP|Modrm, { LLongMem, 0, 0} }, + +/* Pentium Pro extensions. */ +{"rdpmc", 0, 0x0f33, X, NoSuf, { 0, 0, 0} }, + +{"ud2", 0, 0x0f0b, X, NoSuf, { 0, 0, 0} }, /* official undefined instr. */ +{"ud2a", 0, 0x0f0b, X, NoSuf, { 0, 0, 0} }, /* alias for ud2 */ +{"ud2b", 0, 0x0fb9, X, NoSuf, { 0, 0, 0} }, /* 2nd. official undefined instr. */ + +{"cmovo", 2, 0x0f40, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovno", 2, 0x0f41, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovb", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovc", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnae", 2, 0x0f42, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovae", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnc", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnb", 2, 0x0f43, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmove", 2, 0x0f44, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovz", 2, 0x0f44, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovne", 2, 0x0f45, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnz", 2, 0x0f45, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovbe", 2, 0x0f46, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovna", 2, 0x0f46, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmova", 2, 0x0f47, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnbe", 2, 0x0f47, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovs", 2, 0x0f48, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovns", 2, 0x0f49, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovp", 2, 0x0f4a, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnp", 2, 0x0f4b, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovl", 2, 0x0f4c, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnge", 2, 0x0f4c, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovge", 2, 0x0f4d, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnl", 2, 0x0f4d, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovle", 2, 0x0f4e, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovng", 2, 0x0f4e, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovg", 2, 0x0f4f, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, +{"cmovnle", 2, 0x0f4f, X, wl_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, + +{"fcmovb", 2, 0xdac0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnae",2, 0xdac0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmove", 2, 0xdac8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovbe", 2, 0xdad0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovna", 2, 0xdad0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovu", 2, 0xdad8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovae", 2, 0xdbc0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnb", 2, 0xdbc0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovne", 2, 0xdbc8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmova", 2, 0xdbd0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnbe",2, 0xdbd0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcmovnu", 2, 0xdbd8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, + +{"fcomi", 2, 0xdbf0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcomi", 0, 0xdbf1, X, FP|ShortForm, { 0, 0, 0} }, +{"fcomi", 1, 0xdbf0, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fucomi", 2, 0xdbe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fucomi", 0, 0xdbe9, X, FP|ShortForm, { 0, 0, 0} }, +{"fucomi", 1, 0xdbe8, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fcomip", 2, 0xdff0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcompi", 2, 0xdff0, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fcompi", 0, 0xdff1, X, FP|ShortForm, { 0, 0, 0} }, +{"fcompi", 1, 0xdff0, X, FP|ShortForm, { FloatReg, 0, 0} }, +{"fucomip", 2, 0xdfe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fucompi", 2, 0xdfe8, X, FP|ShortForm, { FloatReg, FloatAcc, 0} }, +{"fucompi", 0, 0xdfe9, X, FP|ShortForm, { 0, 0, 0} }, +{"fucompi", 1, 0xdfe8, X, FP|ShortForm, { FloatReg, 0, 0} }, -static const template *const i386_optab_end - = i386_optab + sizeof (i386_optab)/sizeof(i386_optab[0]); +/* MMX instructions. */ -/* 386 register table */ +{"emms", 0, 0x0f77, X, FP, { 0, 0, 0 } }, +{"movd", 2, 0x0f6e, X, FP|Modrm, { Reg32|LongMem, RegMMX, 0 } }, +{"movd", 2, 0x0f7e, X, FP|Modrm, { RegMMX, Reg32|LongMem, 0 } }, +{"movq", 2, 0x0f6f, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"movq", 2, 0x0f7f, X, FP|Modrm, { RegMMX, RegMMX|LongMem, 0 } }, +{"packssdw", 2, 0x0f6b, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"packsswb", 2, 0x0f63, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"packuswb", 2, 0x0f67, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddb", 2, 0x0ffc, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddw", 2, 0x0ffd, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddd", 2, 0x0ffe, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddsb", 2, 0x0fec, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddsw", 2, 0x0fed, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddusb", 2, 0x0fdc, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddusw", 2, 0x0fdd, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pand", 2, 0x0fdb, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pandn", 2, 0x0fdf, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpeqb", 2, 0x0f74, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpeqw", 2, 0x0f75, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpeqd", 2, 0x0f76, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpgtb", 2, 0x0f64, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpgtw", 2, 0x0f65, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpgtd", 2, 0x0f66, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmaddwd", 2, 0x0ff5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmulhw", 2, 0x0fe5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmullw", 2, 0x0fd5, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"por", 2, 0x0feb, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psllw", 2, 0x0ff1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psllw", 2, 0x0f71, 6, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"pslld", 2, 0x0ff2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pslld", 2, 0x0f72, 6, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psllq", 2, 0x0ff3, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psllq", 2, 0x0f73, 6, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psraw", 2, 0x0fe1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psraw", 2, 0x0f71, 4, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrad", 2, 0x0fe2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrad", 2, 0x0f72, 4, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrlw", 2, 0x0fd1, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrlw", 2, 0x0f71, 2, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrld", 2, 0x0fd2, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrld", 2, 0x0f72, 2, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psrlq", 2, 0x0fd3, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrlq", 2, 0x0f73, 2, FP|Modrm, { Imm8, RegMMX, 0 } }, +{"psubb", 2, 0x0ff8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubw", 2, 0x0ff9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubd", 2, 0x0ffa, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubsb", 2, 0x0fe8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubsw", 2, 0x0fe9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubusb", 2, 0x0fd8, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubusw", 2, 0x0fd9, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckhbw",2, 0x0f68, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckhwd",2, 0x0f69, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckhdq",2, 0x0f6a, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpcklbw",2, 0x0f60, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpcklwd",2, 0x0f61, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckldq",2, 0x0f62, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pxor", 2, 0x0fef, X, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, + + +/* PIII Katmai New Instructions / SIMD instructions. */ + +{"addps", 2, 0x0f58, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"addss", 2, 0xf30f58, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"andnps", 2, 0x0f55, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"andps", 2, 0x0f54, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpeqps", 2, 0x0fc2, 0, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpeqss", 2, 0xf30fc2, 0, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpleps", 2, 0x0fc2, 2, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpless", 2, 0xf30fc2, 2, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpltps", 2, 0x0fc2, 1, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpltss", 2, 0xf30fc2, 1, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpneqps", 2, 0x0fc2, 4, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpneqss", 2, 0xf30fc2, 4, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpnleps", 2, 0x0fc2, 6, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpnless", 2, 0xf30fc2, 6, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpnltps", 2, 0x0fc2, 5, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpnltss", 2, 0xf30fc2, 5, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpordps", 2, 0x0fc2, 7, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpordss", 2, 0xf30fc2, 7, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpunordps",2, 0x0fc2, 3, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpunordss",2, 0xf30fc2, 3, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpps", 3, 0x0fc2, X, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"cmpss", 3, 0xf30fc2, X, FP|Modrm, { Imm8, RegXMM|WordMem, RegXMM } }, +{"comiss", 2, 0x0f2f, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"cvtpi2ps", 2, 0x0f2a, X, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, +{"cvtps2pi", 2, 0x0f2d, X, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, +{"cvtsi2ss", 2, 0xf30f2a, X, FP|Modrm, { Reg32|WordMem, RegXMM, 0 } }, +{"cvtss2si", 2, 0xf30f2d, X, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } }, +{"cvttps2pi", 2, 0x0f2c, X, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, +{"cvttss2si", 2, 0xf30f2c, X, FP|Modrm, { RegXMM|WordMem, Reg32, 0 } }, +{"divps", 2, 0x0f5e, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"divss", 2, 0xf30f5e, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"ldmxcsr", 1, 0x0fae, 2, FP|Modrm, { WordMem, 0, 0 } }, +{"maskmovq", 2, 0x0ff7, X, FP|Modrm, { RegMMX|InvMem, RegMMX, 0 } }, +{"maxps", 2, 0x0f5f, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"maxss", 2, 0xf30f5f, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"minps", 2, 0x0f5d, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"minss", 2, 0xf30f5d, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"movaps", 2, 0x0f28, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movaps", 2, 0x0f29, X, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"movhlps", 2, 0x0f12, X, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, +{"movhps", 2, 0x0f16, X, FP|Modrm, { LLongMem, RegXMM, 0 } }, +{"movhps", 2, 0x0f17, X, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movlhps", 2, 0x0f16, X, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, +{"movlps", 2, 0x0f12, X, FP|Modrm, { LLongMem, RegXMM, 0 } }, +{"movlps", 2, 0x0f13, X, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movmskps", 2, 0x0f50, X, FP|Modrm, { RegXMM|InvMem, Reg32, 0 } }, +{"movntps", 2, 0x0f2b, X, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movntq", 2, 0x0fe7, X, FP|Modrm, { RegMMX, LLongMem, 0 } }, +{"movss", 2, 0xf30f10, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"movss", 2, 0xf30f11, X, FP|Modrm, { RegXMM, RegXMM|WordMem, 0 } }, +{"movups", 2, 0x0f10, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movups", 2, 0x0f11, X, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"mulps", 2, 0x0f59, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"mulss", 2, 0xf30f59, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"orps", 2, 0x0f56, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pavgb", 2, 0x0fe0, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pavgw", 2, 0x0fe3, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pextrw", 3, 0x0fc5, X, FP|Modrm, { Imm8, RegMMX, Reg32|InvMem } }, +{"pinsrw", 3, 0x0fc4, X, FP|Modrm, { Imm8, Reg32|ShortMem, RegMMX } }, +{"pmaxsw", 2, 0x0fee, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pmaxub", 2, 0x0fde, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pminsw", 2, 0x0fea, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pminub", 2, 0x0fda, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pmovmskb", 2, 0x0fd7, X, FP|Modrm, { RegMMX, Reg32|InvMem, 0 } }, +{"pmulhuw", 2, 0x0fe4, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"prefetchnta", 1, 0x0f18, 0, FP|Modrm, { LLongMem, 0, 0 } }, +{"prefetcht0", 1, 0x0f18, 1, FP|Modrm, { LLongMem, 0, 0 } }, +{"prefetcht1", 1, 0x0f18, 2, FP|Modrm, { LLongMem, 0, 0 } }, +{"prefetcht2", 1, 0x0f18, 3, FP|Modrm, { LLongMem, 0, 0 } }, +{"psadbw", 2, 0x0ff6, X, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pshufw", 3, 0x0f70, X, FP|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } }, +{"rcpps", 2, 0x0f53, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"rcpss", 2, 0xf30f53, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"rsqrtps", 2, 0x0f52, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"rsqrtss", 2, 0xf30f52, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"sfence", 0, 0x0faef8, X, FP, { 0, 0, 0 } }, +{"shufps", 3, 0x0fc6, X, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"sqrtps", 2, 0x0f51, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"sqrtss", 2, 0xf30f51, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"stmxcsr", 1, 0x0fae, 3, FP|Modrm, { WordMem, 0, 0 } }, +{"subps", 2, 0x0f5c, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"subss", 2, 0xf30f5c, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"ucomiss", 2, 0x0f2e, X, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"unpckhps", 2, 0x0f15, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"unpcklps", 2, 0x0f14, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"xorps", 2, 0x0f57, X, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, + +/* AMD 3DNow! instructions. */ + +{"prefetch", 1, 0x0f0d, 0, FP|Modrm, { ByteMem, 0, 0 } }, +{"prefetchw",1, 0x0f0d, 1, FP|Modrm, { ByteMem, 0, 0 } }, +{"femms", 0, 0x0f0e, X, FP, { 0, 0, 0 } }, +{"pavgusb", 2, 0x0f0f, 0xbf, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pf2id", 2, 0x0f0f, 0x1d, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pf2iw", 2, 0x0f0f, 0x1c, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ +{"pfacc", 2, 0x0f0f, 0xae, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfadd", 2, 0x0f0f, 0x9e, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfcmpeq", 2, 0x0f0f, 0xb0, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfcmpge", 2, 0x0f0f, 0x90, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfcmpgt", 2, 0x0f0f, 0xa0, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfmax", 2, 0x0f0f, 0xa4, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfmin", 2, 0x0f0f, 0x94, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfmul", 2, 0x0f0f, 0xb4, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfnacc", 2, 0x0f0f, 0x8a, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ +{"pfpnacc", 2, 0x0f0f, 0x8e, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ +{"pfrcp", 2, 0x0f0f, 0x96, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrcpit1", 2, 0x0f0f, 0xa6, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrcpit2", 2, 0x0f0f, 0xb6, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrsqit1", 2, 0x0f0f, 0xa7, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrsqrt", 2, 0x0f0f, 0x97, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfsub", 2, 0x0f0f, 0x9a, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfsubr", 2, 0x0f0f, 0xaa, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pi2fd", 2, 0x0f0f, 0x0d, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pi2fw", 2, 0x0f0f, 0x0c, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ +{"pmulhrw", 2, 0x0f0f, 0xb7, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pswapd", 2, 0x0f0f, 0xbb, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* Athlon */ + +{NULL, 0, 0, 0, 0, { 0, 0, 0} } /* sentinel */ +}; +#undef X +#undef NoSuf +#undef b_Suf +#undef w_Suf +#undef l_Suf +#undef d_Suf +#undef x_Suf +#undef bw_Suf +#undef bl_Suf +#undef wl_Suf +#undef sl_Suf +#undef sld_Suf +#undef sldx_Suf +#undef bwl_Suf +#undef bwld_Suf +#undef FP +#undef l_FP +#undef d_FP +#undef x_FP +#undef sl_FP +#undef sld_FP +#undef sldx_FP + +#define MAX_MNEM_SIZE 16 /* for parsing insn mnemonics from input */ + + +/* 386 register table. */ static const reg_entry i386_regtab[] = { + /* make %st first as we test for it */ + {"st", FloatReg|FloatAcc, 0}, /* 8 bit regs */ - {"al", Reg8|Acc, 0}, {"cl", Reg8|ShiftCount, 1}, {"dl", Reg8, 2}, + {"al", Reg8|Acc, 0}, + {"cl", Reg8|ShiftCount, 1}, + {"dl", Reg8, 2}, {"bl", Reg8, 3}, - {"ah", Reg8, 4}, {"ch", Reg8, 5}, {"dh", Reg8, 6}, {"bh", Reg8, 7}, + {"ah", Reg8, 4}, + {"ch", Reg8, 5}, + {"dh", Reg8, 6}, + {"bh", Reg8, 7}, /* 16 bit regs */ - {"ax", Reg16|Acc, 0}, {"cx", Reg16, 1}, {"dx", Reg16|InOutPortReg, 2}, {"bx", Reg16, 3}, - {"sp", Reg16, 4}, {"bp", Reg16, 5}, {"si", Reg16, 6}, {"di", Reg16, 7}, + {"ax", Reg16|Acc, 0}, + {"cx", Reg16, 1}, + {"dx", Reg16|InOutPortReg, 2}, + {"bx", Reg16|BaseIndex, 3}, + {"sp", Reg16, 4}, + {"bp", Reg16|BaseIndex, 5}, + {"si", Reg16|BaseIndex, 6}, + {"di", Reg16|BaseIndex, 7}, /* 32 bit regs */ - {"eax", Reg32|Acc, 0}, {"ecx", Reg32, 1}, {"edx", Reg32, 2}, {"ebx", Reg32, 3}, - {"esp", Reg32, 4}, {"ebp", Reg32, 5}, {"esi", Reg32, 6}, {"edi", Reg32, 7}, + {"eax", Reg32|BaseIndex|Acc, 0}, + {"ecx", Reg32|BaseIndex, 1}, + {"edx", Reg32|BaseIndex, 2}, + {"ebx", Reg32|BaseIndex, 3}, + {"esp", Reg32, 4}, + {"ebp", Reg32|BaseIndex, 5}, + {"esi", Reg32|BaseIndex, 6}, + {"edi", Reg32|BaseIndex, 7}, /* segment registers */ - {"es", SReg2, 0}, {"cs", SReg2, 1}, {"ss", SReg2, 2}, - {"ds", SReg2, 3}, {"fs", SReg3, 4}, {"gs", SReg3, 5}, + {"es", SReg2, 0}, + {"cs", SReg2, 1}, + {"ss", SReg2, 2}, + {"ds", SReg2, 3}, + {"fs", SReg3, 4}, + {"gs", SReg3, 5}, /* control registers */ - {"cr0", Control, 0}, {"cr2", Control, 2}, {"cr3", Control, 3}, + {"cr0", Control, 0}, + {"cr1", Control, 1}, + {"cr2", Control, 2}, + {"cr3", Control, 3}, {"cr4", Control, 4}, + {"cr5", Control, 5}, + {"cr6", Control, 6}, + {"cr7", Control, 7}, /* debug registers */ - {"db0", Debug, 0}, {"db1", Debug, 1}, {"db2", Debug, 2}, - {"db3", Debug, 3}, {"db6", Debug, 6}, {"db7", Debug, 7}, - {"dr0", Debug, 0}, {"dr1", Debug, 1}, {"dr2", Debug, 2}, - {"dr3", Debug, 3}, {"dr6", Debug, 6}, {"dr7", Debug, 7}, + {"db0", Debug, 0}, + {"db1", Debug, 1}, + {"db2", Debug, 2}, + {"db3", Debug, 3}, + {"db4", Debug, 4}, + {"db5", Debug, 5}, + {"db6", Debug, 6}, + {"db7", Debug, 7}, + {"dr0", Debug, 0}, + {"dr1", Debug, 1}, + {"dr2", Debug, 2}, + {"dr3", Debug, 3}, + {"dr4", Debug, 4}, + {"dr5", Debug, 5}, + {"dr6", Debug, 6}, + {"dr7", Debug, 7}, /* test registers */ - {"tr3", Test, 3}, {"tr4", Test, 4}, {"tr5", Test, 5}, - {"tr6", Test, 6}, {"tr7", Test, 7}, - /* float registers */ + {"tr0", Test, 0}, + {"tr1", Test, 1}, + {"tr2", Test, 2}, + {"tr3", Test, 3}, + {"tr4", Test, 4}, + {"tr5", Test, 5}, + {"tr6", Test, 6}, + {"tr7", Test, 7}, + /* mmx and simd registers */ + {"mm0", RegMMX, 0}, + {"mm1", RegMMX, 1}, + {"mm2", RegMMX, 2}, + {"mm3", RegMMX, 3}, + {"mm4", RegMMX, 4}, + {"mm5", RegMMX, 5}, + {"mm6", RegMMX, 6}, + {"mm7", RegMMX, 7}, + {"xmm0", RegXMM, 0}, + {"xmm1", RegXMM, 1}, + {"xmm2", RegXMM, 2}, + {"xmm3", RegXMM, 3}, + {"xmm4", RegXMM, 4}, + {"xmm5", RegXMM, 5}, + {"xmm6", RegXMM, 6}, + {"xmm7", RegXMM, 7} +}; + +static const reg_entry i386_float_regtab[] = { {"st(0)", FloatReg|FloatAcc, 0}, - {"st", FloatReg|FloatAcc, 0}, - {"st(1)", FloatReg, 1}, {"st(2)", FloatReg, 2}, - {"st(3)", FloatReg, 3}, {"st(4)", FloatReg, 4}, {"st(5)", FloatReg, 5}, - {"st(6)", FloatReg, 6}, {"st(7)", FloatReg, 7}, - {"mm0", RegMMX, 0}, {"mm1", RegMMX, 1}, {"mm2", RegMMX, 2}, - {"mm3", RegMMX, 3}, {"mm4", RegMMX, 4}, {"mm5", RegMMX, 5}, - {"mm6", RegMMX, 6}, {"mm7", RegMMX, 7} + {"st(1)", FloatReg, 1}, + {"st(2)", FloatReg, 2}, + {"st(3)", FloatReg, 3}, + {"st(4)", FloatReg, 4}, + {"st(5)", FloatReg, 5}, + {"st(6)", FloatReg, 6}, + {"st(7)", FloatReg, 7} }; #define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */ -static const reg_entry *const i386_regtab_end - = i386_regtab + sizeof(i386_regtab)/sizeof(i386_regtab[0]); - /* segment stuff */ static const seg_entry cs = { "cs", 0x2e }; static const seg_entry ds = { "ds", 0x3e }; @@ -928,54 +1188,5 @@ static const seg_entry ss = { "ss", 0x36 }; static const seg_entry es = { "es", 0x26 }; static const seg_entry fs = { "fs", 0x64 }; static const seg_entry gs = { "gs", 0x65 }; -static const seg_entry null = { "", 0x0 }; - -/* - This table is used to store the default segment register implied by all - possible memory addressing modes. - It is indexed by the mode & modrm entries of the modrm byte as follows: - index = (mode<<3) | modrm; -*/ -static const seg_entry *const one_byte_segment_defaults[] = { - /* mode 0 */ - &ds, &ds, &ds, &ds, &null, &ds, &ds, &ds, - /* mode 1 */ - &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds, - /* mode 2 */ - &ds, &ds, &ds, &ds, &null, &ss, &ds, &ds, - /* mode 3 --- not a memory reference; never referenced */ -}; - -static const seg_entry *const two_byte_segment_defaults[] = { - /* mode 0 */ - &ds, &ds, &ds, &ds, &ss, &ds, &ds, &ds, - /* mode 1 */ - &ds, &ds, &ds, &ds, &ss, &ss, &ds, &ds, - /* mode 2 */ - &ds, &ds, &ds, &ds, &ss, &ss, &ds, &ds, - /* mode 3 --- not a memory reference; never referenced */ -}; - -static const prefix_entry i386_prefixtab[] = { -#define ADDR_PREFIX_OPCODE 0x67 - { "addr16", 0x67 }, /* address size prefix ==> 16bit addressing - * (How is this useful?) */ -#define WORD_PREFIX_OPCODE 0x66 - { "data16", 0x66 }, /* operand size prefix */ - { "lock", 0xf0 }, /* bus lock prefix */ - { "wait", 0x9b }, /* wait for coprocessor */ - { "cs", 0x2e }, { "ds", 0x3e }, /* segment overrides ... */ - { "es", 0x26 }, { "fs", 0x64 }, - { "gs", 0x65 }, { "ss", 0x36 }, -/* REPE & REPNE used to detect rep/repne with a non-string instruction */ -#define REPNE 0xf2 -#define REPE 0xf3 - { "rep", 0xf3 }, /* repeat string instructions */ - { "repe", 0xf3 }, { "repz", 0xf3 }, - { "repne", 0xf2 }, { "repnz", 0xf2 } -}; - -static const prefix_entry *const i386_prefixtab_end - = i386_prefixtab + sizeof(i386_prefixtab)/sizeof(i386_prefixtab[0]); -/* end of i386-opcode.h */ +/* end of opcode/i386.h */ diff --git a/contrib/binutils/include/opcode/mips.h b/contrib/binutils/include/opcode/mips.h index ee5ee82..68fe57a 100644 --- a/contrib/binutils/include/opcode/mips.h +++ b/contrib/binutils/include/opcode/mips.h @@ -47,7 +47,8 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * A breakpoint instruction uses OP, CODE and SPEC (10 bits of the breakpoint instruction are not defined; Kane says the breakpoint code field in BREAK is 20 bits; yet MIPS assemblers and debuggers - only use ten bits). + only use ten bits). An optional two-operand form of break/sdbbp + allows the lower ten bits to be set too. The syscall instruction uses SYSCALL. @@ -65,6 +66,8 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * #define OP_SH_BCC 18 #define OP_MASK_CODE 0x3ff #define OP_SH_CODE 16 +#define OP_MASK_CODE2 0x3ff +#define OP_SH_CODE2 6 #define OP_MASK_RT 0x1f #define OP_SH_RT 16 #define OP_MASK_FT 0x1f @@ -171,6 +174,7 @@ struct mips_opcode "k" 5 bit cache opcode in target register position (OP_*_CACHE) "o" 16 bit signed offset (OP_*_DELTA) "p" 16 bit PC relative branch target address (OP_*_DELTA) + "q" 10 bit extra breakpoint code (OP_*_CODE2) "r" 5 bit same register used as both source and target (OP_*_RS) "s" 5 bit source register specifier (OP_*_RS) "t" 5 bit target register (OP_*_RT) @@ -212,7 +216,7 @@ struct mips_opcode Characters used so far, for quick reference when adding more: "<>()," "ABCDEFGILMNSTRVW" - "abcdfhijkloprstuvwxz" + "abcdfhijklopqrstuvwxz" */ /* These are the bits which may be set in the pinfo field of an @@ -278,8 +282,10 @@ struct mips_opcode #define FP_S 0x10000000 /* Instruction uses double precision floating point. */ #define FP_D 0x20000000 - -/* As yet unused bits: 0x40000000 */ +/* Instruction is part of the tx39's integer multiply family. */ +#define INSN_MULT 0x40000000 +/* Instruction synchronize shared memory. */ +#define INSN_SYNC 0x80000000 /* Instruction is actually a macro. It should be ignored by the disassembler, and requires special treatment by the assembler. */ @@ -302,6 +308,7 @@ struct mips_opcode #define INSN_ISA3 0x00000003 /* MIPS ISA 4 instruction (R8000). */ #define INSN_ISA4 0x00000004 +#define INSN_ISA5 0x00000005 /* Chip specific instructions. These are bitmasks. */ /* MIPS R4650 instruction. */ @@ -313,6 +320,31 @@ struct mips_opcode /* Toshiba R3900 instruction. */ #define INSN_3900 0x00000080 +/* 32-bit code running on a ISA3+ CPU. */ +#define INSN_GP32 0x00001000 + +/* Test for membership in an ISA including chip specific ISAs. + INSN is pointer to an element of the opcode table; ISA is the + specified ISA to test against; and CPU is the CPU specific ISA + to test, or zero if no CPU specific ISA test is desired. + The gp32 arg is set when you need to force 32-bit register usage on + a machine with 64-bit registers; see the documentation under -mgp32 + in the MIPS gas docs. */ + +#define OPCODE_IS_MEMBER(insn,isa,cpu,gp32) \ + ((((insn)->membership & INSN_ISA) != 0 \ + && ((insn)->membership & INSN_ISA) <= isa \ + && ((insn)->membership & INSN_GP32 ? gp32 : 1)) \ + || (cpu == 4650 \ + && ((insn)->membership & INSN_4650) != 0) \ + || (cpu == 4010 \ + && ((insn)->membership & INSN_4010) != 0) \ + || ((cpu == 4100 \ + || cpu == 4111 \ + ) \ + && ((insn)->membership & INSN_4100) != 0) \ + || (cpu == 3900 \ + && ((insn)->membership & INSN_3900) != 0)) /* This is a list of macro expanded instructions. * @@ -695,6 +727,8 @@ extern int bfd_mips_num_opcodes; #define MIPS16_INSN_READ_PC 0x00002000 /* Reads the general purpose register in MIPS16OP_*_REGR32. */ #define MIPS16_INSN_READ_GPR_X 0x00004000 +/* Is a branch insn. */ +#define MIPS16_INSN_BRANCH 0x00010000 /* The following flags have the same value for the mips16 opcode table: diff --git a/contrib/binutils/include/opcode/ppc.h b/contrib/binutils/include/opcode/ppc.h new file mode 100644 index 0000000..974f0dfa --- /dev/null +++ b/contrib/binutils/include/opcode/ppc.h @@ -0,0 +1,251 @@ +/* ppc.h -- Header file for PowerPC opcode table + Copyright 1994, 1995 Free Software Foundation, Inc. + Written by Ian Lance Taylor, Cygnus Support + +This file is part of GDB, GAS, and the GNU binutils. + +GDB, GAS, and the GNU binutils are free software; you can redistribute +them and/or modify them under the terms of the GNU General Public +License as published by the Free Software Foundation; either version +1, or (at your option) any later version. + +GDB, GAS, and the GNU binutils are distributed in the hope that they +will be useful, but WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See +the GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this file; see the file COPYING. If not, write to the Free +Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef PPC_H +#define PPC_H + +/* The opcode table is an array of struct powerpc_opcode. */ + +struct powerpc_opcode +{ + /* The opcode name. */ + const char *name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + unsigned long opcode; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + unsigned long mask; + + /* One bit flags for the opcode. These are used to indicate which + specific processors support the instructions. The defined values + are listed below. */ + unsigned long flags; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[8]; +}; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct powerpc_opcode powerpc_opcodes[]; +extern const int powerpc_num_opcodes; + +/* Values defined for the flags field of a struct powerpc_opcode. */ + +/* Opcode is defined for the PowerPC architecture. */ +#define PPC_OPCODE_PPC (01) + +/* Opcode is defined for the POWER (RS/6000) architecture. */ +#define PPC_OPCODE_POWER (02) + +/* Opcode is defined for the POWER2 (Rios 2) architecture. */ +#define PPC_OPCODE_POWER2 (04) + +/* Opcode is only defined on 32 bit architectures. */ +#define PPC_OPCODE_32 (010) + +/* Opcode is only defined on 64 bit architectures. */ +#define PPC_OPCODE_64 (020) + +/* Opcode is supported by the Motorola PowerPC 601 processor. The 601 + is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, + but it also supports many additional POWER instructions. */ +#define PPC_OPCODE_601 (040) + +/* Opcode is supported in both the Power and PowerPC architectures + (ie, compiler's -mcpu=common or assembler's -mcom). */ +#define PPC_OPCODE_COMMON (0100) + +/* Opcode is supported for any Power or PowerPC platform (this is + for the assembler's -many option, and it eliminates duplicates). */ +#define PPC_OPCODE_ANY (0200) + +/* Opcode is supported as part of the 64-bit bridge. */ +#define PPC_OPCODE_64_BRIDGE (0400) + +/* A macro to extract the major opcode from an instruction. */ +#define PPC_OP(i) (((i) >> 26) & 0x3f) + +/* The operands table is an array of struct powerpc_operand. */ + +struct powerpc_operand +{ + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + + /* Insertion function. This is used by the assembler. To insert an + operand value into an instruction, check this field. + + If it is NULL, execute + i |= (op & ((1 << o->bits) - 1)) << o->shift; + (i is the instruction which we are filling in, o is a pointer to + this structure, and op is the opcode value; this assumes twos + complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction and the operand value. It will return the new value + of the instruction. If the ERRMSG argument is not NULL, then if + the operand value is illegal, *ERRMSG will be set to a warning + string (the operand will be inserted in any case). If the + operand value is legal, *ERRMSG will be unchanged (most operands + can accept any value). */ + unsigned long (*insert) PARAMS ((unsigned long instruction, long op, + const char **errmsg)); + + /* Extraction function. This is used by the disassembler. To + extract this operand type from an instruction, check this field. + + If it is NULL, compute + op = ((i) >> o->shift) & ((1 << o->bits) - 1); + if ((o->flags & PPC_OPERAND_SIGNED) != 0 + && (op & (1 << (o->bits - 1))) != 0) + op -= 1 << o->bits; + (i is the instruction, o is a pointer to this structure, and op + is the result; this assumes twos complement arithmetic). + + If this field is not NULL, then simply call it with the + instruction value. It will return the value of the operand. If + the INVALID argument is not NULL, *INVALID will be set to + non-zero if this operand type can not actually be extracted from + this operand (i.e., the instruction does not match). If the + operand is valid, *INVALID will not be changed. */ + long (*extract) PARAMS ((unsigned long instruction, int *invalid)); + + /* One bit syntax flags. */ + unsigned long flags; +}; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the powerpc_opcodes table. */ + +extern const struct powerpc_operand powerpc_operands[]; + +/* Values defined for the flags field of a struct powerpc_operand. */ + +/* This operand takes signed values. */ +#define PPC_OPERAND_SIGNED (01) + +/* This operand takes signed values, but also accepts a full positive + range of values when running in 32 bit mode. That is, if bits is + 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, + this flag is ignored. */ +#define PPC_OPERAND_SIGNOPT (02) + +/* This operand does not actually exist in the assembler input. This + is used to support extended mnemonics such as mr, for which two + operands fields are identical. The assembler should call the + insert function with any op value. The disassembler should call + the extract function, ignore the return value, and check the value + placed in the valid argument. */ +#define PPC_OPERAND_FAKE (04) + +/* The next operand should be wrapped in parentheses rather than + separated from this one by a comma. This is used for the load and + store instructions which want their operands to look like + reg,displacement(reg) + */ +#define PPC_OPERAND_PARENS (010) + +/* This operand may use the symbolic names for the CR fields, which + are + lt 0 gt 1 eq 2 so 3 un 3 + cr0 0 cr1 1 cr2 2 cr3 3 + cr4 4 cr5 5 cr6 6 cr7 7 + These may be combined arithmetically, as in cr2*4+gt. These are + only supported on the PowerPC, not the POWER. */ +#define PPC_OPERAND_CR (020) + +/* This operand names a register. The disassembler uses this to print + register names with a leading 'r'. */ +#define PPC_OPERAND_GPR (040) + +/* This operand names a floating point register. The disassembler + prints these with a leading 'f'. */ +#define PPC_OPERAND_FPR (0100) + +/* This operand is a relative branch displacement. The disassembler + prints these symbolically if possible. */ +#define PPC_OPERAND_RELATIVE (0200) + +/* This operand is an absolute branch address. The disassembler + prints these symbolically if possible. */ +#define PPC_OPERAND_ABSOLUTE (0400) + +/* This operand is optional, and is zero if omitted. This is used for + the optional BF and L fields in the comparison instructions. The + assembler must count the number of operands remaining on the line, + and the number of operands remaining for the opcode, and decide + whether this operand is present or not. The disassembler should + print this operand out only if it is not zero. */ +#define PPC_OPERAND_OPTIONAL (01000) + +/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand + is omitted, then for the next operand use this operand value plus + 1, ignoring the next operand field for the opcode. This wretched + hack is needed because the Power rotate instructions can take + either 4 or 5 operands. The disassembler should print this operand + out regardless of the PPC_OPERAND_OPTIONAL field. */ +#define PPC_OPERAND_NEXT (02000) + +/* This operand should be regarded as a negative number for the + purposes of overflow checking (i.e., the normal most negative + number is disallowed and one more than the normal most positive + number is allowed). This flag will only be set for a signed + operand. */ +#define PPC_OPERAND_NEGATIVE (04000) + +/* The POWER and PowerPC assemblers use a few macros. We keep them + with the operands table for simplicity. The macro table is an + array of struct powerpc_macro. */ + +struct powerpc_macro +{ + /* The macro name. */ + const char *name; + + /* The number of operands the macro takes. */ + unsigned int operands; + + /* One bit flags for the opcode. These are used to indicate which + specific processors support the instructions. The values are the + same as those for the struct powerpc_opcode flags field. */ + unsigned long flags; + + /* A format string to turn the macro into a normal instruction. + Each %N in the string is replaced with operand number N (zero + based). */ + const char *format; +}; + +extern const struct powerpc_macro powerpc_macros[]; +extern const int powerpc_num_macros; + +#endif /* PPC_H */ diff --git a/contrib/binutils/include/opcode/v850.h b/contrib/binutils/include/opcode/v850.h index 0c10ade..88916f1 100644 --- a/contrib/binutils/include/opcode/v850.h +++ b/contrib/binutils/include/opcode/v850.h @@ -56,6 +56,9 @@ struct v850_opcode /* Values for the processors field in the v850_opcode structure. */ #define PROCESSOR_V850 (1 << 0) /* Just the V850. */ #define PROCESSOR_ALL -1 /* Any processor. */ +#define PROCESSOR_V850E (1 << 1) /* Just the V850E. */ +#define PROCESSOR_NOT_V850 (~ PROCESSOR_V850) /* Any processor except the V850. */ +#define PROCESSOR_V850EA (1 << 2) /* Just the V850EA. */ /* The table itself is sorted by major opcode number, and is otherwise in the order in which the disassembler should consider @@ -150,5 +153,14 @@ extern const struct v850_operand v850_operands[]; /* The register specified must not be r0 */ #define V850_NOT_R0 0x80 +/* CYGNUS LOCAL v850e */ +/* push/pop type instruction, V850E specific. */ +#define V850E_PUSH_POP 0x100 + +/* 16 bit immediate follows instruction, V850E specific. */ +#define V850E_IMMEDIATE16 0x200 + +/* 32 bit immediate follows instruction, V850E specific. */ +#define V850E_IMMEDIATE32 0x400 #endif /* V850_H */ diff --git a/contrib/binutils/include/partition.h b/contrib/binutils/include/partition.h new file mode 100644 index 0000000..f49d67a --- /dev/null +++ b/contrib/binutils/include/partition.h @@ -0,0 +1,81 @@ +/* List implentation of a partition of consecutive integers. + Copyright (C) 2000 Free Software Foundation, Inc. + Contributed by CodeSourcery, LLC. + + This file is part of GNU CC. + + GNU CC is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GNU CC is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GNU CC; see the file COPYING. If not, write to + the Free Software Foundation, 59 Temple Place - Suite 330, + Boston, MA 02111-1307, USA. */ + +/* This package implements a partition of consecutive integers. The + elements are partitioned into classes. Each class is represented + by one of its elements, the canonical element, which is chosen + arbitrarily from elements in the class. The principal operations + on a partition are FIND, which takes an element, determines its + class, and returns the canonical element for that class, and UNION, + which unites the two classes that contain two given elements into a + single class. + + The list implementation used here provides constant-time finds. By + storing the size of each class with the class's canonical element, + it is able to perform unions over all the classes in the partition + in O (N log N) time. */ + +#ifndef _PARTITION_H +#define _PARTITION_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include <ansidecl.h> +#include <stdio.h> + +struct partition_elem +{ + /* The canonical element that represents the class containing this + element. */ + int class_element; + /* The next element in this class. Elements in each class form a + circular list. */ + struct partition_elem* next; + /* The number of elements in this class. Valid only if this is the + canonical element for its class. */ + unsigned class_count; +}; + +typedef struct partition_def +{ + /* The number of elements in this partition. */ + int num_elements; + /* The elements in the partition. */ + struct partition_elem elements[1]; +} *partition; + +extern partition partition_new PARAMS((int)); +extern void partition_delete PARAMS((partition)); +extern int partition_union PARAMS((partition, + int, + int)); +extern void partition_print PARAMS((partition, + FILE*)); + +/* Returns the canonical element corresponding to the class containing + ELEMENT__ in PARTITION__. */ + +#define partition_find(partition__, element__) \ + ((partition__)->elements[(element__)].class_element) + +#endif /* _PARTITION_H */ diff --git a/contrib/binutils/include/remote-sim.h b/contrib/binutils/include/remote-sim.h index a4480b4..b32f93f 100644 --- a/contrib/binutils/include/remote-sim.h +++ b/contrib/binutils/include/remote-sim.h @@ -211,7 +211,27 @@ int sim_store_register PARAMS ((SIM_DESC sd, int regno, unsigned char *buf, int void sim_info PARAMS ((SIM_DESC sd, int verbose)); -/* Run (or resume) the simulated program. */ +/* Run (or resume) the simulated program. + + STEP, when non-zero indicates that only a single simulator cycle + should be emulated. + + SIGGNAL, if non-zero is a (HOST) SIGRC value indicating the type of + event (hardware interrupt, signal) to be delivered to the simulated + program. + + Hardware simulator: If the SIGRC value returned by + sim_stop_reason() is passed back to the simulator via SIGGNAL then + the hardware simulator shall correctly deliver the hardware event + indicated by that signal. If a value of zero is passed in then the + simulation will continue as if there were no outstanding signal. + The effect of any other SIGGNAL value is is implementation + dependant. + + Process simulator: If SIGRC is non-zero then the corresponding + signal is delivered to the simulated program and execution is then + continued. A zero SIGRC value indicates that the program should + continue as normal. */ void sim_resume PARAMS ((SIM_DESC sd, int step, int siggnal)); @@ -234,13 +254,13 @@ int sim_stop PARAMS ((SIM_DESC sd)); (SIGTRAP); a completed single step (SIGTRAP); an internal error condition (SIGABRT); an illegal instruction (SIGILL); Access to an undefined memory region (SIGSEGV); Mis-aligned memory access - (SIGBUS). + (SIGBUS). For some signals information in addition to the signal + number may be retained by the simulator (e.g. offending address), + that information is not directly accessable via this interface. - SIM_SIGNALLED: The program has stopped. The simulator has - encountered target code that requires the (HOST) signal SIGRC to be - delivered to the simulated program. Ex: `kill (getpid (), - TARGET_SIGxxx)'. Where TARGET_SIGxxx has been translated into a - host signal. FIXME: This is not always possible.. + SIM_SIGNALLED: The program has been terminated by a signal. The + simulator has encountered target code that causes the the program + to exit with signal SIGRC. SIM_RUNNING, SIM_POLLING: The return of one of these values indicates a problem internal to the simulator. */ @@ -288,15 +308,27 @@ void sim_set_callbacks PARAMS ((struct host_callback_struct *)); void sim_size PARAMS ((int i)); -/* Run a simulation with tracing enabled. +/* Single-step simulator with tracing enabled. THIS PROCEDURE IS DEPRECIATED. + THIS PROCEDURE IS EVEN MORE DEPRECATED THAN SIM_SET_TRACE GDB and NRUN do not use this interface. - This procedure does not take a SIM_DESC argument as it is - used before sim_open. */ + This procedure returns: ``0'' indicating that the simulator should + be continued using sim_trace() calls; ``1'' indicating that the + simulation has finished. */ int sim_trace PARAMS ((SIM_DESC sd)); +/* Enable tracing. + THIS PROCEDURE IS DEPRECIATED. + GDB and NRUN do not use this interface. + This procedure returns: ``0'' indicating that the simulator should + be continued using sim_trace() calls; ``1'' indicating that the + simulation has finished. */ + +void sim_set_trace PARAMS ((void)); + + /* Configure the size of the profile buffer. THIS PROCEDURE IS DEPRECIATED. GDB and NRUN do not use this interface. diff --git a/contrib/binutils/include/splay-tree.h b/contrib/binutils/include/splay-tree.h new file mode 100644 index 0000000..6d70c8d --- /dev/null +++ b/contrib/binutils/include/splay-tree.h @@ -0,0 +1,117 @@ +/* A splay-tree datatype. + Copyright (C) 1998 Free Software Foundation, Inc. + Contributed by Mark Mitchell (mark@markmitchell.com). + +This file is part of GNU CC. + +GNU CC is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +GNU CC is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GNU CC; see the file COPYING. If not, write to +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ + +/* For an easily readable description of splay-trees, see: + + Lewis, Harry R. and Denenberg, Larry. Data Structures and Their + Algorithms. Harper-Collins, Inc. 1991. + + The major feature of splay trees is that all basic tree operations + are amortized O(log n) time for a tree with n nodes. */ + +#ifndef _SPLAY_TREE_H +#define _SPLAY_TREE_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +#include <ansidecl.h> + +/* Use typedefs for the key and data types to facilitate changing + these types, if necessary. These types should be sufficiently wide + that any pointer or scalar can be cast to these types, and then + cast back, without loss of precision. */ +typedef unsigned long int splay_tree_key; +typedef unsigned long int splay_tree_value; + +/* Forward declaration for a node in the tree. */ +typedef struct splay_tree_node_s *splay_tree_node; + +/* The type of a function which compares two splay-tree keys. The + function should return values as for qsort. */ +typedef int (*splay_tree_compare_fn) PARAMS((splay_tree_key, splay_tree_key)); + +/* The type of a function used to deallocate any resources associated + with the key. */ +typedef void (*splay_tree_delete_key_fn) PARAMS((splay_tree_key)); + +/* The type of a function used to deallocate any resources associated + with the value. */ +typedef void (*splay_tree_delete_value_fn) PARAMS((splay_tree_value)); + +/* The type of a function used to iterate over the tree. */ +typedef int (*splay_tree_foreach_fn) PARAMS((splay_tree_node, void*)); + +/* The nodes in the splay tree. */ +struct splay_tree_node_s +{ + /* The key. */ + splay_tree_key key; + + /* The value. */ + splay_tree_value value; + + /* The left and right children, respectively. */ + splay_tree_node left; + splay_tree_node right; +}; + +/* The splay tree itself. */ +typedef struct splay_tree_s +{ + /* The root of the tree. */ + splay_tree_node root; + + /* The comparision function. */ + splay_tree_compare_fn comp; + + /* The deallocate-key function. NULL if no cleanup is necessary. */ + splay_tree_delete_key_fn delete_key; + + /* The deallocate-value function. NULL if no cleanup is necessary. */ + splay_tree_delete_value_fn delete_value; +} *splay_tree; + +extern splay_tree splay_tree_new PARAMS((splay_tree_compare_fn, + splay_tree_delete_key_fn, + splay_tree_delete_value_fn)); +extern void splay_tree_delete PARAMS((splay_tree)); +extern splay_tree_node splay_tree_insert + PARAMS((splay_tree, + splay_tree_key, + splay_tree_value)); +extern splay_tree_node splay_tree_lookup + PARAMS((splay_tree, + splay_tree_key)); +extern int splay_tree_foreach PARAMS((splay_tree, + splay_tree_foreach_fn, + void*)); +extern int splay_tree_compare_ints PARAMS((splay_tree_key, + splay_tree_key)); +extern int splay_tree_compare_pointers PARAMS((splay_tree_key, + splay_tree_key)); + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* _SPLAY_TREE_H */ diff --git a/contrib/binutils/include/symcat.h b/contrib/binutils/include/symcat.h index 01efada..3e27162 100644 --- a/contrib/binutils/include/symcat.h +++ b/contrib/binutils/include/symcat.h @@ -1,6 +1,6 @@ /* Symbol concatenation utilities. - Copyright (C) 1998, Free Software Foundation, Inc. + Copyright (C) 1998, 2000 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -28,7 +28,7 @@ #define CONCAT2(a,b) a/**/b #define CONCAT3(a,b,c) a/**/b/**/c #define CONCAT4(a,b,c,d) a/**/b/**/c/**/d -#define STRINGX(s) "?" +#define STRINGX(s) "s" #endif #define XCONCAT2(a,b) CONCAT2(a,b) |
