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| author | andrew <andrew@FreeBSD.org> | 2014-12-14 17:38:43 +0000 |
|---|---|---|
| committer | andrew <andrew@FreeBSD.org> | 2014-12-14 17:38:43 +0000 |
| commit | ab2a78a144f1c58eacc3f606f74e76ab9d0db633 (patch) | |
| tree | ecb91e1c4b2e28226a3efe10183836cf0663eb09 /contrib/binutils/gas | |
| parent | 23e47daf2840506187dd274d897a76d9d91cfdc0 (diff) | |
| download | FreeBSD-src-ab2a78a144f1c58eacc3f606f74e76ab9d0db633.zip FreeBSD-src-ab2a78a144f1c58eacc3f606f74e76ab9d0db633.tar.gz | |
MFC 275415:
Allow the UAL APSR_nzcv format for the mrc and mrc2 instructions. The clang
integrated assembler only allows these forms so binutils will need to
support them.
Sponsored by: ABT Systems Ltd
MFC 275584:
Fix mrc and mrc2 with APSR_nzcv. Binutils encodes it internally as 0 where
we need it to be set to 15 for it to be equivalent to r15.
Sponsored by: ABT Systems Ltd
Diffstat (limited to 'contrib/binutils/gas')
| -rw-r--r-- | contrib/binutils/gas/config/tc-arm.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/contrib/binutils/gas/config/tc-arm.c b/contrib/binutils/gas/config/tc-arm.c index 14c81a9..239d753 100644 --- a/contrib/binutils/gas/config/tc-arm.c +++ b/contrib/binutils/gas/config/tc-arm.c @@ -6771,7 +6771,11 @@ do_co_reg (void) { inst.instruction |= inst.operands[0].reg << 8; inst.instruction |= inst.operands[1].imm << 21; - inst.instruction |= inst.operands[2].reg << 12; + /* If this is a vector we are using the APSR_nzcv syntax, encode as r15 */ + if (inst.operands[2].isvec != 0) + inst.instruction |= 15 << 12; + else + inst.instruction |= inst.operands[2].reg << 12; inst.instruction |= inst.operands[3].reg << 16; inst.instruction |= inst.operands[4].reg; inst.instruction |= inst.operands[5].imm << 5; @@ -15029,7 +15033,7 @@ static const struct asm_opcode insns[] = TCE(stc, c000000, ec000000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), TC3(stcl, c400000, ec400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), TCE(mcr, e000010, ee000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), - TCE(mrc, e100010, ee100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), + TCE(mrc, e100010, ee100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), #undef ARM_VARIANT #define ARM_VARIANT &arm_ext_v2s /* ARM 3 - swp instructions. */ @@ -15088,7 +15092,7 @@ static const struct asm_opcode insns[] = TUF(stc2l, c400000, fc400000, 3, (RCP, RCN, ADDRGLDC), lstc, lstc), TUF(cdp2, e000000, fe000000, 6, (RCP, I15b, RCN, RCN, RCN, oI7b), cdp, cdp), TUF(mcr2, e000010, fe000010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), - TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, RR, RCN, RCN, oI7b), co_reg, co_reg), + TUF(mrc2, e100010, fe100010, 6, (RCP, I7b, APSR_RR, RCN, RCN, oI7b), co_reg, co_reg), #undef ARM_VARIANT #define ARM_VARIANT &arm_ext_v5exp /* ARM Architecture 5TExP. */ |
