- Read ASI_{D,I}TLB_DATA_ACCESS_REG twice in order to work around

  errata of USIII and beyond (USIII erratum #19, USIII+ erratum #1,
  USIIIi erratum #1).
- Use the cheetah PA mask in {d,i}tlb_va_to_pa_sun4u() for USIII
  and beyond. This is done so that these functions will still mask
  the debug bits of spitfire-class CPUs once we increase TD_PA_BITS
  to match the number of bits used for the PA by cheetah-class CPUs.
- Change {d,i}tlb_enter_sun4u() to also set TLB_CTX_KERNEL as the
  context of the mappings entered. This is more or less cosmetic as
  TLB_CTX_KERNEL is 0.
- Now that we have to distinguish between different sun4u CPUs in
  the loader anyway, no longer do trial and error when reading the
  portid property.

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