- Sort the prototypes.

- Add macros to ease the access of device configuration space in
  ofw_pcibus_setup_device().

1 files changed, 23 insertions, 24 deletions

diff --git a/sys/sparc64/pci/ofw_pcibus.c b/sys/sparc64/pci/ofw_pcibus.c
index 571b6ac..ae1cc37 100644
--- a/sys/sparc64/pci/ofw_pcibus.c
+++ b/sys/sparc64/pci/ofw_pcibus.c
@@ -64,11 +64,11 @@ static void ofw_pcibus_setup_device(device_t bridge, uint32_t clock,
     u_int busno, u_int slot, u_int func);
 
 /* Methods */
-static device_probe_t ofw_pcibus_probe;
+static bus_child_pnpinfo_str_t ofw_pcibus_pnpinfo_str;
 static device_attach_t ofw_pcibus_attach;
-static pci_assign_interrupt_t ofw_pcibus_assign_interrupt;
+static device_probe_t ofw_pcibus_probe;
 static ofw_bus_get_devinfo_t ofw_pcibus_get_devinfo;
-static bus_child_pnpinfo_str_t ofw_pcibus_pnpinfo_str;
+static pci_assign_interrupt_t ofw_pcibus_assign_interrupt;
 
 static device_method_t ofw_pcibus_methods[] = {
 	/* Device interface */
@@ -124,6 +124,11 @@ static void
 ofw_pcibus_setup_device(device_t bridge, uint32_t clock, u_int busno,
     u_int slot, u_int func)
 {
+#define	CS_READ(n, w)							\
+	PCIB_READ_CONFIG(bridge, busno, slot, func, (n), (w))
+#define	CS_WRITE(n, v, w)						\
+	PCIB_WRITE_CONFIG(bridge, busno, slot, func, (n), (v), (w))
+
 #ifndef SUN4V
 	uint32_t reg;
 
@@ -138,33 +143,27 @@ ofw_pcibus_setup_device(device_t bridge, uint32_t clock, u_int busno,
 	 * For bridges, we additionally set up the bridge control and the
 	 * secondary latency registers.
 	 */
-	if ((PCIB_READ_CONFIG(bridge, busno, slot, func, PCIR_HDRTYPE, 1) &
-	    PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) {
-		reg = PCIB_READ_CONFIG(bridge, busno, slot, func,
-		    PCIR_BRIDGECTL_1, 1);
+	if ((CS_READ(PCIR_HDRTYPE, 1) & PCIM_HDRTYPE) ==
+	    PCIM_HDRTYPE_BRIDGE) {
+		reg = CS_READ(PCIR_BRIDGECTL_1, 1);
 		reg |= PCIB_BCR_MASTER_ABORT_MODE | PCIB_BCR_SERR_ENABLE |
 		    PCIB_BCR_PERR_ENABLE;
 #ifdef OFW_PCI_DEBUG
 		device_printf(bridge,
 		    "bridge %d/%d/%d: control 0x%x -> 0x%x\n",
-		    busno, slot, func, PCIB_READ_CONFIG(bridge, busno, slot,
-		    func, PCIR_BRIDGECTL_1, 1), reg);
+		    busno, slot, func, CS_READ(PCIR_BRIDGECTL_1, 1), reg);
 #endif /* OFW_PCI_DEBUG */
-		PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_BRIDGECTL_1,
-		    reg, 1);
+		CS_WRITE(PCIR_BRIDGECTL_1, reg, 1);
 
 		reg = OFW_PCI_LATENCY;
 #ifdef OFW_PCI_DEBUG
 		device_printf(bridge,
 		    "bridge %d/%d/%d: latency timer %d -> %d\n",
-		    busno, slot, func, PCIB_READ_CONFIG(bridge, busno, slot,
-		    func, PCIR_SECLAT_1, 1), reg);
+		    busno, slot, func, CS_READ(PCIR_SECLAT_1, 1), reg);
 #endif /* OFW_PCI_DEBUG */
-		PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_SECLAT_1,
-		    reg, 1);
+		CS_WRITE(PCIR_SECLAT_1, reg, 1);
 	} else {
-		reg = PCIB_READ_CONFIG(bridge, busno, slot, func,
-		    PCIR_MINGNT, 1);
+		reg = CS_READ(PCIR_MINGNT, 1);
 		if (reg != 0) {
 			switch (clock) {
 			case 33000000:
@@ -180,10 +179,9 @@ ofw_pcibus_setup_device(device_t bridge, uint32_t clock, u_int busno,
 	}
 #ifdef OFW_PCI_DEBUG
 	device_printf(bridge, "device %d/%d/%d: latency timer %d -> %d\n",
-	    busno, slot, func, PCIB_READ_CONFIG(bridge, busno, slot, func,
-	    PCIR_LATTIMER, 1), reg);
+	    busno, slot, func, CS_READ(PCIR_LATTIMER, 1), reg);
 #endif /* OFW_PCI_DEBUG */
-	PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_LATTIMER, reg, 1);
+	CS_WRITE(PCIR_LATTIMER, reg, 1);
 
 	/*
 	 * Compute a value to write into the cache line size register.
@@ -192,8 +190,7 @@ ofw_pcibus_setup_device(device_t bridge, uint32_t clock, u_int busno,
 	 * reached.  Generally, the cache line size is fixed at 64 bytes
 	 * by Fireplane/Safari, JBus and UPA.
 	 */
-	PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_CACHELNSZ,
-	    STRBUF_LINESZ / sizeof(uint32_t), 1);
+	CS_WRITE(PCIR_CACHELNSZ, STRBUF_LINESZ / sizeof(uint32_t), 1);
 #endif
 
 	/*
@@ -201,8 +198,10 @@ ofw_pcibus_setup_device(device_t bridge, uint32_t clock, u_int busno,
 	 * it to 255, so that the PCI code will reroute the interrupt if
 	 * needed.
 	 */
-	PCIB_WRITE_CONFIG(bridge, busno, slot, func, PCIR_INTLINE,
-	    PCI_INVALID_IRQ, 1);
+	CS_WRITE(PCIR_INTLINE, PCI_INVALID_IRQ, 1);
+
+#undef CS_READ
+#undef CS_WRITE
 }
 
 static int