Add a public routine to set the L2 cache ram latencies. This can be

called by platform init routines to fine-tune cache performance.

2 files changed, 42 insertions, 0 deletions

diff --git a/sys/arm/arm/pl310.c b/sys/arm/arm/pl310.c
index a5eca1a..83e6907 100644
--- a/sys/arm/arm/pl310.c
+++ b/sys/arm/arm/pl310.c
@@ -125,6 +125,35 @@ pl310_print_config(struct pl310_softc *sc)
 		(prefetch & PREFETCH_CTRL_OFFSET_MASK));
 }
 
+void
+pl310_set_ram_latency(struct pl310_softc *sc, uint32_t which_reg,
+   uint32_t read, uint32_t write, uint32_t setup)
+{
+	uint32_t v;
+
+	KASSERT(which_reg == PL310_TAG_RAM_CTRL || 
+	    which_reg == PL310_DATA_RAM_CTRL,
+	    ("bad pl310 ram latency register address"));
+
+	v = pl310_read4(sc, which_reg);
+	if (setup != 0) {
+		KASSERT(setup <= 8, ("bad pl310 setup latency: %d", setup));
+		v &= ~RAM_CTRL_SETUP_MASK;
+		v |= (setup - 1) << RAM_CTRL_SETUP_SHIFT;
+	}
+	if (read != 0) {
+		KASSERT(read <= 8, ("bad pl310 read latency: %d", read));
+		v &= ~RAM_CTRL_READ_MASK;
+		v |= (read - 1) << RAM_CTRL_READ_SHIFT;
+	}
+	if (write != 0) {
+		KASSERT(write <= 8, ("bad pl310 write latency: %d", write));
+		v &= ~RAM_CTRL_WRITE_MASK;
+		v |= (write - 1) << RAM_CTRL_WRITE_SHIFT;
+	}
+	pl310_write4(sc, which_reg, v);
+}
+
 static int
 pl310_filter(void *arg)
 {
diff --git a/sys/arm/include/pl310.h b/sys/arm/include/pl310.h
index b88d84e..8730877 100644
--- a/sys/arm/include/pl310.h
+++ b/sys/arm/include/pl310.h
@@ -62,6 +62,14 @@
 #define 	AUX_CTRL_DATA_PREFETCH		(1 << 28)
 #define 	AUX_CTRL_INSTR_PREFETCH		(1 << 29)
 #define 	AUX_CTRL_EARLY_BRESP		(1 << 30)
+#define PL310_TAG_RAM_CTRL			0x108
+#define PL310_DATA_RAM_CTRL			0x10C
+#define		RAM_CTRL_WRITE_SHIFT		8
+#define		RAM_CTRL_WRITE_MASK		(0x7 << 8)
+#define		RAM_CTRL_READ_SHIFT		4
+#define		RAM_CTRL_READ_MASK		(0x7 << 4)
+#define		RAM_CTRL_SETUP_SHIFT		0
+#define		RAM_CTRL_SETUP_MASK		(0x7 << 0)
 #define PL310_EVENT_COUNTER_CTRL	0x200
 #define		EVENT_COUNTER_CTRL_ENABLED	(1 << 0)
 #define		EVENT_COUNTER_CTRL_C0_RESET	(1 << 1)
@@ -115,6 +123,7 @@
 #define PL310_DEBUG_CTRL		0xF40
 #define		DEBUG_CTRL_DISABLE_LINEFILL	(1 << 0)
 #define		DEBUG_CTRL_DISABLE_WRITEBACK	(1 << 1)
+#define		DEBUG_CTRL_SPNIDEN		(1 << 2)
 #define PL310_PREFETCH_CTRL		0xF60
 #define		PREFETCH_CTRL_OFFSET_MASK	(0x1f)
 #define		PREFETCH_CTRL_NOTSAMEID		(1 << 21)
@@ -125,6 +134,8 @@
 #define		PREFETCH_CTRL_INSTR_PREFETCH	(1 << 29)
 #define		PREFETCH_CTRL_DL		(1 << 30)
 #define PL310_POWER_CTRL		0xF60
+#define		POWER_CTRL_ENABLE_GATING	(1 << 0)
+#define		POWER_CTRL_ENABLE_STANDBY	(1 << 1)
 
 struct pl310_softc {
 	device_t	sc_dev;
@@ -164,6 +175,8 @@ pl310_write4(struct pl310_softc *sc, bus_size_t off, uint32_t val)
 }
 
 void pl310_print_config(struct pl310_softc *sc);
+void pl310_set_ram_latency(struct pl310_softc *sc, uint32_t which_reg,
+    uint32_t read, uint32_t write, uint32_t setup);
 
 void platform_pl310_init(struct pl310_softc *);
 void platform_pl310_write_ctrl(struct pl310_softc *, uint32_t);