MFC r261175:

binutils: add support for Intel SMAP-related instructions

Add support for stac/clac instructions to manipulate the flag
that controls the behaviour of Intel's Supervisor Mode Access
Prevention (SMAP) feature.

Tested by:	dim
Obtained from:	OpenBSD

4 files changed, 19 insertions, 2 deletions

diff --git a/contrib/binutils/gas/config/tc-i386.c b/contrib/binutils/gas/config/tc-i386.c
index 6eb51aa..5c8e6b1 100644
--- a/contrib/binutils/gas/config/tc-i386.c
+++ b/contrib/binutils/gas/config/tc-i386.c
@@ -1827,7 +1827,7 @@ md_assemble (line)
     {
       expressionS *exp;
 
-      if ((i.tm.cpu_flags & CpuSSE3) && i.operands > 0)
+      if ((i.tm.cpu_flags & (CpuSSE3|CpuSMAP)) && i.operands > 0)
 	{
 	  /* Streaming SIMD extensions 3 Instructions have the fixed
 	     operands with an opcode suffix which is coded in the same
diff --git a/contrib/binutils/opcodes/i386-dis.c b/contrib/binutils/opcodes/i386-dis.c
index a134213..460c04e 100644
--- a/contrib/binutils/opcodes/i386-dis.c
+++ b/contrib/binutils/opcodes/i386-dis.c
@@ -6257,6 +6257,16 @@ PNI_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag)
 
       codep++;
     }
+  else if (modrm.mod == 3 && modrm.reg == 1 && modrm.rm <= 3)
+    {
+      size_t olen = strlen (obuf);
+      char *p = obuf + olen - 4;
+      if (*codep == 0xca)
+        strcpy (p, "clac");
+      else if (*codep == 0xcb)
+        strcpy (p, "stac");
+      codep++;
+    }
   else
     OP_M (0, sizeflag);
 }
diff --git a/contrib/binutils/opcodes/i386-opc.h b/contrib/binutils/opcodes/i386-opc.h
index 8d6fd8a..ec80196 100644
--- a/contrib/binutils/opcodes/i386-opc.h
+++ b/contrib/binutils/opcodes/i386-opc.h
@@ -80,6 +80,7 @@ typedef struct template
 
 #define CpuPCLMUL   0x10000000	/* Carry-less Multiplication extensions */
 #define CpuRdRnd    0x20000000	/* Intel Random Number Generator extensions */
+#define CpuSMAP     0x40000000	/* Intel Supervisor Mode Access Prevention */
 
 /* SSE4.1/4.2 Instructions required */
 #define CpuSSE4	     (CpuSSE4_1|CpuSSE4_2)
@@ -88,7 +89,7 @@ typedef struct template
 #define CpuUnknownFlags (Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686 \
 	|CpuP4|CpuSledgehammer|CpuMMX|CpuMMX2|CpuSSE|CpuSSE2|CpuSSE3|CpuVMX \
 	|Cpu3dnow|Cpu3dnowA|CpuK6|CpuPadLock|CpuSVME|CpuSSSE3|CpuSSE4_1 \
-	|CpuSSE4_2|CpuABM|CpuSSE4a|CpuXSAVE|CpuAES|CpuPCLMUL|CpuRdRnd)
+	|CpuSSE4_2|CpuABM|CpuSSE4a|CpuXSAVE|CpuAES|CpuPCLMUL|CpuRdRnd|CpuSMAP)
 
   /* the bits in opcode_modifier are used to generate the final opcode from
      the base_opcode.  These bits also are used to detect alternate forms of
diff --git a/contrib/binutils/opcodes/i386-tbl.h b/contrib/binutils/opcodes/i386-tbl.h
index ec19f10..17553dc 100644
--- a/contrib/binutils/opcodes/i386-tbl.h
+++ b/contrib/binutils/opcodes/i386-tbl.h
@@ -4379,6 +4379,12 @@ const template i386_optab[] =
   {"rdrand", 1, 0x0fc7, 0x6, CpuRdRnd,
     Modrm|NoSuf,
     { Reg16|Reg32|Reg64 } },
+
+  /* Intel Supervisor Mode Access Prevention extensions */
+  {"clac", 0, 0x0f01, 0xca, CpuSMAP,
+    NoSuf|ImmExt, { 0, 0, 0 } },
+  {"stac", 0, 0x0f01, 0xcb, CpuSMAP,
+    NoSuf|ImmExt, { 0, 0, 0 } },
   
   { NULL, 0, 0, 0, 0, 0, { 0 } }
 };