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authorkato <kato@FreeBSD.org>1999-09-04 01:39:52 +0000
committerkato <kato@FreeBSD.org>1999-09-04 01:39:52 +0000
commitb0c80ddb8948dcf0b1afa8e6cccd6959083a19b7 (patch)
tree32a7f123ab10a63d5fb8151098fa84d25ad5574c
parent76a0e25b9235936c351df3cd9fab1a2808eac97f (diff)
downloadFreeBSD-src-b0c80ddb8948dcf0b1afa8e6cccd6959083a19b7.zip
FreeBSD-src-b0c80ddb8948dcf0b1afa8e6cccd6959083a19b7.tar.gz
Merge from sys/i386/isa/clock.c revision 1.145.
-rw-r--r--sys/pc98/cbus/clock.c10
-rw-r--r--sys/pc98/cbus/pcrtc.c10
-rw-r--r--sys/pc98/pc98/clock.c10
3 files changed, 30 insertions, 0 deletions
diff --git a/sys/pc98/cbus/clock.c b/sys/pc98/cbus/clock.c
index ba64484..56a92bc 100644
--- a/sys/pc98/cbus/clock.c
+++ b/sys/pc98/cbus/clock.c
@@ -95,6 +95,11 @@
#include <i386/isa/intr_machdep.h>
+#include "mca.h"
+#if NMCA > 0
+#include <i386/isa/mca_machdep.h>
+#endif
+
#ifdef SMP
#define disable_intr() CLOCK_DISABLE_INTR()
#define enable_intr() CLOCK_ENABLE_INTR()
@@ -283,6 +288,11 @@ clkintr(struct clockframe frame)
}
break;
}
+#if NMCA > 0
+ /* Reset clock interrupt by asserting bit 7 of port 0x61 */
+ if (MCA_system)
+ outb(0x61, inb(0x61) | 0x80);
+#endif
}
/*
diff --git a/sys/pc98/cbus/pcrtc.c b/sys/pc98/cbus/pcrtc.c
index ba64484..56a92bc 100644
--- a/sys/pc98/cbus/pcrtc.c
+++ b/sys/pc98/cbus/pcrtc.c
@@ -95,6 +95,11 @@
#include <i386/isa/intr_machdep.h>
+#include "mca.h"
+#if NMCA > 0
+#include <i386/isa/mca_machdep.h>
+#endif
+
#ifdef SMP
#define disable_intr() CLOCK_DISABLE_INTR()
#define enable_intr() CLOCK_ENABLE_INTR()
@@ -283,6 +288,11 @@ clkintr(struct clockframe frame)
}
break;
}
+#if NMCA > 0
+ /* Reset clock interrupt by asserting bit 7 of port 0x61 */
+ if (MCA_system)
+ outb(0x61, inb(0x61) | 0x80);
+#endif
}
/*
diff --git a/sys/pc98/pc98/clock.c b/sys/pc98/pc98/clock.c
index ba64484..56a92bc 100644
--- a/sys/pc98/pc98/clock.c
+++ b/sys/pc98/pc98/clock.c
@@ -95,6 +95,11 @@
#include <i386/isa/intr_machdep.h>
+#include "mca.h"
+#if NMCA > 0
+#include <i386/isa/mca_machdep.h>
+#endif
+
#ifdef SMP
#define disable_intr() CLOCK_DISABLE_INTR()
#define enable_intr() CLOCK_ENABLE_INTR()
@@ -283,6 +288,11 @@ clkintr(struct clockframe frame)
}
break;
}
+#if NMCA > 0
+ /* Reset clock interrupt by asserting bit 7 of port 0x61 */
+ if (MCA_system)
+ outb(0x61, inb(0x61) | 0x80);
+#endif
}
/*
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