Remove unused code in sys/mips/rmi :

 - ehcireg.h,ehcivar.h : USB related files from old merge
 - pcibus.c : was merged into xlr_pci.c earlier
 - xlr_boot1_console.c : obsolete console code using bootloader hooks
 - sys/mips/rmi/perfmon* : obsolete custom performance monitoring code

Approved by:	rrs (mentor)

9 files changed, 0 insertions, 1930 deletions

diff --git a/sys/mips/rmi/ehcireg.h b/sys/mips/rmi/ehcireg.h
deleted file mode 100644
index f54528b..0000000
--- a/sys/mips/rmi/ehcireg.h
+++ /dev/null
@@ -1,302 +0,0 @@
-/*	$NetBSD: ehcireg.h,v 1.18 2004/10/22 10:38:17 augustss Exp $	*/
-/*	$FreeBSD$	*/
-
-/*-
- * Copyright (c) 2001 The NetBSD Foundation, Inc.
- * All rights reserved.
- *
- * This code is derived from software contributed to The NetBSD Foundation
- * by Lennart Augustsson (lennart@augustsson.net).
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * The EHCI 0.96 spec can be found at
- * http://developer.intel.com/technology/usb/download/ehci-r096.pdf
- * and the USB 2.0 spec at
- * http://www.usb.org/developers/data/usb_20.zip
- */
-
-#ifndef _DEV_PCI_EHCIREG_H_
-#define _DEV_PCI_EHCIREG_H_
-
-/*** PCI config registers ***/
-
-#define PCI_CBMEM		0x10	/* configuration base MEM */
-
-#define PCI_INTERFACE_EHCI	0x20
-
-#define PCI_USBREV		0x60	/* RO USB protocol revision */
-#define  PCI_USBREV_MASK	0xff
-#define  PCI_USBREV_PRE_1_0	0x00
-#define  PCI_USBREV_1_0		0x10
-#define  PCI_USBREV_1_1		0x11
-#define  PCI_USBREV_2_0		0x20
-
-#define PCI_EHCI_FLADJ		0x61	/* RW Frame len adj, SOF=59488+6*fladj */
-
-#define PCI_EHCI_PORTWAKECAP	0x62	/* RW Port wake caps (opt)  */
-
-/* EHCI Extended Capabilities */
-#define EHCI_EC_LEGSUP		0x01
-
-#define EHCI_EECP_NEXT(x)	(((x) >> 8) & 0xff)
-#define EHCI_EECP_ID(x)		((x) & 0xff)
-
-/* Legacy support extended capability */
-#define	EHCI_LEGSUP_OS_SEM	0x03	/* OS owned semaphore */
-#define	EHCI_LEGSUP_BIOS_SEM	0x02	/* BIOS owned semaphore */
-#define EHCI_LEGSUP_USBLEGCTLSTS 0x04
-
-/*** EHCI capability registers ***/
-
-#define EHCI_CAPLENGTH		0x00	/* RO Capability register length field */
-/* reserved			0x01 */
-#define EHCI_HCIVERSION		0x02	/* RO Interface version number */
-
-#define EHCI_HCSPARAMS		0x04	/* RO Structural parameters */
-#define  EHCI_HCS_DEBUGPORT(x)	(((x) >> 20) & 0xf)
-#define  EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000)
-#define  EHCI_HCS_N_CC(x)	(((x) >> 12) & 0xf)	/* # of companion ctlrs */
-#define  EHCI_HCS_N_PCC(x)	(((x) >> 8) & 0xf)	/* # of ports per comp. */
-#define  EHCI_HCS_PPC(x)	((x) & 0x10)	/* port power control */
-#define  EHCI_HCS_N_PORTS(x)	((x) & 0xf)	/* # of ports */
-
-#define EHCI_HCCPARAMS		0x08	/* RO Capability parameters */
-#define  EHCI_HCC_EECP(x)	(((x) >> 8) & 0xff)	/* extended ports caps */
-#define  EHCI_HCC_IST(x)	(((x) >> 4) & 0xf)	/* isoc sched threshold */
-#define  EHCI_HCC_ASPC(x)	((x) & 0x4)	/* async sched park cap */
-#define  EHCI_HCC_PFLF(x)	((x) & 0x2)	/* prog frame list flag */
-#define  EHCI_HCC_64BIT(x)	((x) & 0x1)	/* 64 bit address cap */
-
-#define EHCI_HCSP_PORTROUTE	0x0c	/* RO Companion port route description */
-
-/* EHCI operational registers.  Offset given by EHCI_CAPLENGTH register */
-#define EHCI_USBCMD		0x00	/* RO, RW, WO Command register */
-#define  EHCI_CMD_ITC_M		0x00ff0000	/* RW interrupt threshold ctrl */
-#define   EHCI_CMD_ITC_1	0x00010000
-#define   EHCI_CMD_ITC_2	0x00020000
-#define   EHCI_CMD_ITC_4	0x00040000
-#define   EHCI_CMD_ITC_8	0x00080000
-#define   EHCI_CMD_ITC_16	0x00100000
-#define   EHCI_CMD_ITC_32	0x00200000
-#define   EHCI_CMD_ITC_64	0x00400000
-#define  EHCI_CMD_ASPME		0x00000800	/* RW/RO async park enable */
-#define  EHCI_CMD_ASPMC		0x00000300	/* RW/RO async park count */
-#define  EHCI_CMD_LHCR		0x00000080	/* RW light host ctrl reset */
-#define  EHCI_CMD_IAAD		0x00000040	/* RW intr on async adv door
-						 * bell */
-#define  EHCI_CMD_ASE		0x00000020	/* RW async sched enable */
-#define  EHCI_CMD_PSE		0x00000010	/* RW periodic sched enable */
-#define  EHCI_CMD_FLS_M		0x0000000c	/* RW/RO frame list size */
-#define  EHCI_CMD_FLS(x)	(((x) >> 2) & 3)	/* RW/RO frame list size */
-#define  EHCI_CMD_HCRESET	0x00000002	/* RW reset */
-#define  EHCI_CMD_RS		0x00000001	/* RW run/stop */
-
-#define EHCI_USBSTS		0x04	/* RO, RW, RWC Status register */
-#define  EHCI_STS_ASS		0x00008000	/* RO async sched status */
-#define  EHCI_STS_PSS		0x00004000	/* RO periodic sched status */
-#define  EHCI_STS_REC		0x00002000	/* RO reclamation */
-#define  EHCI_STS_HCH		0x00001000	/* RO host controller halted */
-#define  EHCI_STS_IAA		0x00000020	/* RWC interrupt on async adv */
-#define  EHCI_STS_HSE		0x00000010	/* RWC host system error */
-#define  EHCI_STS_FLR		0x00000008	/* RWC frame list rollover */
-#define  EHCI_STS_PCD		0x00000004	/* RWC port change detect */
-#define  EHCI_STS_ERRINT	0x00000002	/* RWC error interrupt */
-#define  EHCI_STS_INT		0x00000001	/* RWC interrupt */
-#define  EHCI_STS_INTRS(x)	((x) & 0x3f)
-
-#define EHCI_NORMAL_INTRS (EHCI_STS_IAA | EHCI_STS_HSE | EHCI_STS_PCD | EHCI_STS_ERRINT | EHCI_STS_INT)
-
-#define EHCI_USBINTR		0x08	/* RW Interrupt register */
-#define EHCI_INTR_IAAE		0x00000020	/* interrupt on async advance
-						 * ena */
-#define EHCI_INTR_HSEE		0x00000010	/* host system error ena */
-#define EHCI_INTR_FLRE		0x00000008	/* frame list rollover ena */
-#define EHCI_INTR_PCIE		0x00000004	/* port change ena */
-#define EHCI_INTR_UEIE		0x00000002	/* USB error intr ena */
-#define EHCI_INTR_UIE		0x00000001	/* USB intr ena */
-
-#define EHCI_FRINDEX		0x0c	/* RW Frame Index register */
-
-#define EHCI_CTRLDSSEGMENT	0x10	/* RW Control Data Structure Segment */
-
-#define EHCI_PERIODICLISTBASE	0x14	/* RW Periodic List Base */
-#define EHCI_ASYNCLISTADDR	0x18	/* RW Async List Base */
-
-#define EHCI_CONFIGFLAG		0x40	/* RW Configure Flag register */
-#define  EHCI_CONF_CF		0x00000001	/* RW configure flag */
-
-#define EHCI_PORTSC(n)		(0x40+4*(n))	/* RO, RW, RWC Port Status reg */
-#define  EHCI_PS_WKOC_E		0x00400000	/* RW wake on over current ena */
-#define  EHCI_PS_WKDSCNNT_E	0x00200000	/* RW wake on disconnect ena */
-#define  EHCI_PS_WKCNNT_E	0x00100000	/* RW wake on connect ena */
-#define  EHCI_PS_PTC		0x000f0000	/* RW port test control */
-#define  EHCI_PS_PIC		0x0000c000	/* RW port indicator control */
-#define  EHCI_PS_PO		0x00002000	/* RW port owner */
-#define  EHCI_PS_PP		0x00001000	/* RW,RO port power */
-#define  EHCI_PS_LS		0x00000c00	/* RO line status */
-#define  EHCI_PS_IS_LOWSPEED(x)	(((x) & EHCI_PS_LS) == 0x00000400)
-#define  EHCI_PS_PR		0x00000100	/* RW port reset */
-#define  EHCI_PS_SUSP		0x00000080	/* RW suspend */
-#define  EHCI_PS_FPR		0x00000040	/* RW force port resume */
-#define  EHCI_PS_OCC		0x00000020	/* RWC over current change */
-#define  EHCI_PS_OCA		0x00000010	/* RO over current active */
-#define  EHCI_PS_PEC		0x00000008	/* RWC port enable change */
-#define  EHCI_PS_PE		0x00000004	/* RW port enable */
-#define  EHCI_PS_CSC		0x00000002	/* RWC connect status change */
-#define  EHCI_PS_CS		0x00000001	/* RO connect status */
-#define  EHCI_PS_CLEAR		(EHCI_PS_OCC|EHCI_PS_PEC|EHCI_PS_CSC)
-
-#define EHCI_PORT_RESET_COMPLETE 2	/* ms */
-
-#define EHCI_FLALIGN_ALIGN	0x1000
-
-/* No data structure may cross a page boundary. */
-#define EHCI_PAGE_SIZE 0x1000
-#define EHCI_PAGE(x) ((x) &~ 0xfff)
-#define EHCI_PAGE_OFFSET(x) ((x) & 0xfff)
-#if defined(__FreeBSD__)
-#define EHCI_PAGE_MASK(x) ((x) & 0xfff)
-#endif
-
-typedef u_int32_t ehci_link_t;
-
-#define EHCI_LINK_TERMINATE	0x00000001
-#define EHCI_LINK_TYPE(x)	((x) & 0x00000006)
-#define  EHCI_LINK_ITD		0x0
-#define  EHCI_LINK_QH		0x2
-#define  EHCI_LINK_SITD		0x4
-#define  EHCI_LINK_FSTN		0x6
-#define EHCI_LINK_ADDR(x)	((x) &~ 0x1f)
-
-typedef u_int32_t ehci_physaddr_t;
-
-/* Isochronous Transfer Descriptor */
-typedef struct {
-	ehci_link_t itd_next;
-	/* XXX many more */
-}      ehci_itd_t;
-
-#define EHCI_ITD_ALIGN 32
-
-/* Split Transaction Isochronous Transfer Descriptor */
-typedef struct {
-	ehci_link_t sitd_next;
-	/* XXX many more */
-}      ehci_sitd_t;
-
-#define EHCI_SITD_ALIGN 32
-
-/* Queue Element Transfer Descriptor */
-#define EHCI_QTD_NBUFFERS 5
-typedef struct {
-	ehci_link_t qtd_next;
-	ehci_link_t qtd_altnext;
-	u_int32_t qtd_status;
-#define EHCI_QTD_GET_STATUS(x)	(((x) >>  0) & 0xff)
-#define EHCI_QTD_SET_STATUS(x) ((x) <<  0)
-#define  EHCI_QTD_ACTIVE	0x80
-#define  EHCI_QTD_HALTED	0x40
-#define  EHCI_QTD_BUFERR	0x20
-#define  EHCI_QTD_BABBLE	0x10
-#define  EHCI_QTD_XACTERR	0x08
-#define  EHCI_QTD_MISSEDMICRO	0x04
-#define  EHCI_QTD_SPLITXSTATE	0x02
-#define  EHCI_QTD_PINGSTATE	0x01
-#define  EHCI_QTD_STATERRS	0x7c
-#define EHCI_QTD_GET_PID(x)	(((x) >>  8) & 0x3)
-#define EHCI_QTD_SET_PID(x)	((x) <<  8)
-#define  EHCI_QTD_PID_OUT	0x0
-#define  EHCI_QTD_PID_IN	0x1
-#define  EHCI_QTD_PID_SETUP	0x2
-#define EHCI_QTD_GET_CERR(x)	(((x) >> 10) &  0x3)
-#define EHCI_QTD_SET_CERR(x)	((x) << 10)
-#define EHCI_QTD_GET_C_PAGE(x)	(((x) >> 12) &  0x7)
-#define EHCI_QTD_SET_C_PAGE(x)	((x) << 12)
-#define EHCI_QTD_GET_IOC(x)	(((x) >> 15) &  0x1)
-#define EHCI_QTD_IOC		0x00008000
-#define EHCI_QTD_GET_BYTES(x)	(((x) >> 16) &  0x7fff)
-#define EHCI_QTD_SET_BYTES(x)	((x) << 16)
-#define EHCI_QTD_GET_TOGGLE(x)	(((x) >> 31) &  0x1)
-#define	EHCI_QTD_SET_TOGGLE(x)	((x) << 31)
-#define EHCI_QTD_TOGGLE_MASK	0x80000000
-	ehci_physaddr_t qtd_buffer[EHCI_QTD_NBUFFERS];
-	ehci_physaddr_t qtd_buffer_hi[EHCI_QTD_NBUFFERS];
-}      ehci_qtd_t;
-
-#define EHCI_QTD_ALIGN 32
-
-/* Queue Head */
-typedef struct {
-	ehci_link_t qh_link;
-	u_int32_t qh_endp;
-#define EHCI_QH_GET_ADDR(x)	(((x) >>  0) & 0x7f)	/* endpoint addr */
-#define EHCI_QH_SET_ADDR(x)	(x)
-#define EHCI_QH_ADDRMASK	0x0000007f
-#define EHCI_QH_GET_INACT(x)	(((x) >>  7) & 0x01)	/* inactivate on next */
-#define EHCI_QH_INACT		0x00000080
-#define EHCI_QH_GET_ENDPT(x)	(((x) >>  8) & 0x0f)	/* endpoint no */
-#define EHCI_QH_SET_ENDPT(x)	((x) <<  8)
-#define EHCI_QH_GET_EPS(x)	(((x) >> 12) & 0x03)	/* endpoint speed */
-#define EHCI_QH_SET_EPS(x)	((x) << 12)
-#define  EHCI_QH_SPEED_FULL	0x0
-#define  EHCI_QH_SPEED_LOW	0x1
-#define  EHCI_QH_SPEED_HIGH	0x2
-#define EHCI_QH_GET_DTC(x)	(((x) >> 14) & 0x01)	/* data toggle control */
-#define EHCI_QH_DTC		0x00004000
-#define EHCI_QH_GET_HRECL(x)	(((x) >> 15) & 0x01)	/* head of reclamation */
-#define EHCI_QH_HRECL		0x00008000
-#define EHCI_QH_GET_MPL(x)	(((x) >> 16) & 0x7ff)	/* max packet len */
-#define EHCI_QH_SET_MPL(x)	((x) << 16)
-#define EHCI_QH_MPLMASK		0x07ff0000
-#define EHCI_QH_GET_CTL(x)	(((x) >> 27) & 0x01)	/* control endpoint */
-#define EHCI_QH_CTL		0x08000000
-#define EHCI_QH_GET_NRL(x)	(((x) >> 28) & 0x0f)	/* NAK reload */
-#define EHCI_QH_SET_NRL(x)	((x) << 28)
-	u_int32_t qh_endphub;
-#define EHCI_QH_GET_SMASK(x)	(((x) >>  0) & 0xff)	/* intr sched mask */
-#define EHCI_QH_SET_SMASK(x)	((x) <<  0)
-#define EHCI_QH_GET_CMASK(x)	(((x) >>  8) & 0xff)	/* split completion mask */
-#define EHCI_QH_SET_CMASK(x)	((x) <<  8)
-#define EHCI_QH_GET_HUBA(x)	(((x) >> 16) & 0x7f)	/* hub address */
-#define EHCI_QH_SET_HUBA(x)	((x) << 16)
-#define EHCI_QH_GET_PORT(x)	(((x) >> 23) & 0x7f)	/* hub port */
-#define EHCI_QH_SET_PORT(x)	((x) << 23)
-#define EHCI_QH_GET_MULT(x)	(((x) >> 30) & 0x03)	/* pipe multiplier */
-#define EHCI_QH_SET_MULT(x)	((x) << 30)
-	ehci_link_t qh_curqtd;
-	ehci_qtd_t qh_qtd;
-}      ehci_qh_t;
-
-#define EHCI_QH_ALIGN 32
-
-/* Periodic Frame Span Traversal Node */
-typedef struct {
-	ehci_link_t fstn_link;
-	ehci_link_t fstn_back;
-}      ehci_fstn_t;
-
-#define EHCI_FSTN_ALIGN 32
-
-#endif				/* _DEV_PCI_EHCIREG_H_ */
diff --git a/sys/mips/rmi/ehcivar.h b/sys/mips/rmi/ehcivar.h
deleted file mode 100644
index 72a12f1..0000000
--- a/sys/mips/rmi/ehcivar.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/*	$NetBSD: ehcivar.h,v 1.19 2005/04/29 15:04:29 augustss Exp $	*/
-/*	$FreeBSD$	*/
-
-/*-
- * Copyright (c) 2001 The NetBSD Foundation, Inc.
- * All rights reserved.
- *
- * This code is derived from software contributed to The NetBSD Foundation
- * by Lennart Augustsson (lennart@augustsson.net).
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
- * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-typedef struct ehci_soft_qtd {
-	ehci_qtd_t qtd;
-	struct ehci_soft_qtd *nextqtd;	/* mirrors nextqtd in TD */
-	ehci_physaddr_t physaddr;
-	usbd_xfer_handle xfer;
-	                 LIST_ENTRY(ehci_soft_qtd) hnext;
-	u_int16_t len;
-}             ehci_soft_qtd_t;
-
-#define EHCI_SQTD_SIZE ((sizeof (struct ehci_soft_qtd) + EHCI_QTD_ALIGN - 1) / EHCI_QTD_ALIGN * EHCI_QTD_ALIGN)
-#define EHCI_SQTD_CHUNK (EHCI_PAGE_SIZE / EHCI_SQTD_SIZE)
-
-typedef struct ehci_soft_qh {
-	ehci_qh_t qh;
-	struct ehci_soft_qh *next;
-	struct ehci_soft_qh *prev;
-	struct ehci_soft_qtd *sqtd;
-	ehci_physaddr_t physaddr;
-	int islot;		/* Interrupt list slot. */
-}            ehci_soft_qh_t;
-
-#define EHCI_SQH_SIZE ((sizeof (struct ehci_soft_qh) + EHCI_QH_ALIGN - 1) / EHCI_QH_ALIGN * EHCI_QH_ALIGN)
-#define EHCI_SQH_CHUNK (EHCI_PAGE_SIZE / EHCI_SQH_SIZE)
-
-struct ehci_xfer {
-	struct usbd_xfer xfer;
-	struct usb_task abort_task;
-	         LIST_ENTRY(ehci_xfer) inext;	/* list of active xfers */
-	ehci_soft_qtd_t *sqtdstart;
-	ehci_soft_qtd_t *sqtdend;
-	u_int32_t ehci_xfer_flags;
-#ifdef DIAGNOSTIC
-	int isdone;
-#endif
-};
-
-#define EHCI_XFER_ABORTING	0x0001	/* xfer is aborting. */
-#define EHCI_XFER_ABORTWAIT	0x0002	/* abort completion is being awaited. */
-
-#define EXFER(xfer) ((struct ehci_xfer *)(xfer))
-
-/*
- * Information about an entry in the interrupt list.
- */
-struct ehci_soft_islot {
-	ehci_soft_qh_t *sqh;	/* Queue Head. */
-};
-
-#define EHCI_FRAMELIST_MAXCOUNT	1024
-#define EHCI_IPOLLRATES		8	/* Poll rates (1ms, 2, 4, 8 ... 128) */
-#define EHCI_INTRQHS		((1 << EHCI_IPOLLRATES) - 1)
-#define EHCI_MAX_POLLRATE	(1 << (EHCI_IPOLLRATES - 1))
-#define EHCI_IQHIDX(lev, pos)	\
-    ((((pos) & ((1 << (lev)) - 1)) | (1 << (lev))) - 1)
-#define EHCI_ILEV_IVAL(lev)	(1 << (lev))
-
-#define EHCI_HASH_SIZE 128
-#define EHCI_COMPANION_MAX 8
-
-#define EHCI_SCFLG_DONEINIT	0x0001	/* ehci_init() has been called. */
-#define EHCI_SCFLG_LOSTINTRBUG	0x0002	/* workaround for VIA / ATI chipsets */
-
-typedef struct ehci_softc {
-	struct usbd_bus sc_bus;	/* base device */
-	int sc_flags;
-	bus_space_tag_t iot;
-	bus_space_handle_t ioh;
-	bus_size_t sc_size;
-#if defined(__FreeBSD__)
-	void *ih;
-
-	struct resource *io_res;
-	struct resource *irq_res;
-#endif
-	u_int sc_offs;		/* offset to operational regs */
-
-	char sc_vendor[32];	/* vendor string for root hub */
-	int sc_id_vendor;	/* vendor ID for root hub */
-
-	u_int32_t sc_cmd;	/* shadow of cmd reg during suspend */
-#if defined(__NetBSD__) || defined(__OpenBSD__)
-	void *sc_powerhook;	/* cookie from power hook */
-	void *sc_shutdownhook;	/* cookie from shutdown hook */
-#endif
-
-	u_int sc_ncomp;
-	u_int sc_npcomp;
-	struct usbd_bus *sc_comps[EHCI_COMPANION_MAX];
-
-	usb_dma_t sc_fldma;
-	ehci_link_t *sc_flist;
-	u_int sc_flsize;
-#ifndef __FreeBSD__
-	u_int sc_rand;		/* XXX need proper intr scheduling */
-#endif
-
-	struct ehci_soft_islot sc_islots[EHCI_INTRQHS];
-
-	                LIST_HEAD(, ehci_xfer) sc_intrhead;
-
-	ehci_soft_qh_t *sc_freeqhs;
-	ehci_soft_qtd_t *sc_freeqtds;
-
-	int sc_noport;
-	u_int8_t sc_addr;	/* device address */
-	u_int8_t sc_conf;	/* device configuration */
-	usbd_xfer_handle sc_intrxfer;
-	char sc_isreset;
-#ifdef USB_USE_SOFTINTR
-	char sc_softwake;
-#endif				/* USB_USE_SOFTINTR */
-
-	u_int32_t sc_eintrs;
-	ehci_soft_qh_t *sc_async_head;
-
-	               SIMPLEQ_HEAD(, usbd_xfer) sc_free_xfers;	/* free xfers */
-
-	struct lock sc_doorbell_lock;
-
-	usb_callout_t sc_tmo_pcd;
-	usb_callout_t sc_tmo_intrlist;
-
-#if defined(__NetBSD__) || defined(__OpenBSD__)
-	device_ptr_t sc_child;	/* /dev/usb# device */
-#endif
-	char sc_dying;
-#if defined(__NetBSD__)
-	struct usb_dma_reserve sc_dma_reserve;
-#endif
-}          ehci_softc_t;
-
-#define EREAD1(sc, a) bus_space_read_1((sc)->iot, (sc)->ioh, (a))
-#define EREAD2(sc, a) bus_space_read_2((sc)->iot, (sc)->ioh, (a))
-#define EREAD4(sc, a) bus_space_read_4((sc)->iot, (sc)->ioh, (a))
-#define EWRITE1(sc, a, x) bus_space_write_1((sc)->iot, (sc)->ioh, (a), (x))
-#define EWRITE2(sc, a, x) bus_space_write_2((sc)->iot, (sc)->ioh, (a), (x))
-#define EWRITE4(sc, a, x) bus_space_write_4((sc)->iot, (sc)->ioh, (a), (x))
-#define EOREAD1(sc, a) bus_space_read_1((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a))
-#define EOREAD2(sc, a) bus_space_read_2((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a))
-#define EOREAD4(sc, a) bus_space_read_4((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a))
-#define EOWRITE1(sc, a, x) bus_space_write_1((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a), (x))
-#define EOWRITE2(sc, a, x) bus_space_write_2((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a), (x))
-#define EOWRITE4(sc, a, x) bus_space_write_4((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a), (x))
-
-usbd_status ehci_init(ehci_softc_t *);
-int ehci_intr(void *);
-int ehci_detach(ehci_softc_t *, int);
-
-#if defined(__NetBSD__) || defined(__OpenBSD__)
-int ehci_activate(device_ptr_t, enum devact);
-
-#endif
-void ehci_power(int state, void *priv);
-void ehci_shutdown(void *v);
-
-#define MS_TO_TICKS(ms) ((ms) * hz / 1000)
diff --git a/sys/mips/rmi/pcibus.c b/sys/mips/rmi/pcibus.c
deleted file mode 100644
index c683d47..0000000
--- a/sys/mips/rmi/pcibus.c
+++ /dev/null
@@ -1,357 +0,0 @@
-/*-
- * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice unmodified, this list of conditions, and the following
- *    disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
- * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
- * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include "opt_isa.h"
-
-#define __RMAN_RESOURCE_VISIBLE
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/lock.h>
-#include <sys/mutex.h>
-#include <sys/module.h>
-#include <sys/proc.h>
-#include <sys/bus.h>
-
-#include <vm/vm.h>
-#include <vm/vm_param.h>
-#include <vm/pmap.h>
-
-#include <machine/bus.h>
-#include <machine/pmap.h>
-#include <sys/interrupt.h>
-#include <sys/sysctl.h>
-#include <mips/rmi/iomap.h>
-#include <mips/rmi/pic.h>
-#include <mips/rmi/shared_structs.h>
-#include <mips/rmi/board.h>
-#include <sys/rman.h>
-
-#include <dev/pci/pcivar.h>
-#include <machine/resource.h>
-#include <machine/md_var.h>
-#include <machine/intr_machdep.h>
-#include <mips/rmi/pcibus.h>
-/*
-static void bridge_pcix_ack(void *);
-static void bridge_pcie_ack(void *);
-static void pic_pcix_ack(void *);
-static void pic_pcie_ack(void *);
-*/
-
-extern vm_map_t kernel_map;
-vm_offset_t kmem_alloc_nofault(vm_map_t map, vm_size_t size);
-
-
-int
-mips_pci_route_interrupt(device_t bus, device_t dev, int pin)
-{
-	/*
-	 * Validate requested pin number.
-	 */
-	if ((pin < 1) || (pin > 4))
-		return (255);
-
-	if (xlr_board_info.is_xls) {
-		switch (pin) {
-		case 1:
-			return PIC_PCIE_LINK0_IRQ;
-		case 2:
-			return PIC_PCIE_LINK1_IRQ;
-		case 3:
-			return PIC_PCIE_LINK2_IRQ;
-		case 4:
-			return PIC_PCIE_LINK3_IRQ;
-		}
-	} else {
-		if (pin == 1) {
-			return (16);
-		}
-	}
-
-	return (255);
-}
-
-static struct rman irq_rman, port_rman, mem_rman;
-
-/*
-static void bridge_pcix_ack(void *arg)
-{
-	xlr_read_reg(xlr_io_mmio(XLR_IO_PCIX_OFFSET), 0x140 >> 2);
-	}
-*/
-/*
-static void bridge_pcie_ack(void *arg)
-{
-	int irq = (int)arg;
-	uint32_t reg;
-	xlr_reg_t *pcie_mmio_le = xlr_io_mmio(XLR_IO_PCIE_1_OFFSET);
-
-	switch (irq) {
-	case PIC_PCIE_LINK0_IRQ : reg = PCIE_LINK0_MSI_STATUS; break;
-	case PIC_PCIE_LINK1_IRQ : reg = PCIE_LINK1_MSI_STATUS; break;
-	case PIC_PCIE_LINK2_IRQ : reg = PCIE_LINK2_MSI_STATUS; break;
-	case PIC_PCIE_LINK3_IRQ : reg = PCIE_LINK3_MSI_STATUS; break;
-	default:
-		return;
-	}
-
-	xlr_write_reg(pcie_mmio_le, reg>>2, 0xffffffff);
-}
-*/
-/*
-static void pic_pcix_ack(void *none)
-{
-	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
-	
-	mtx_lock_spin(&xlr_pic_lock);
-	xlr_write_reg(mmio, PIC_INT_ACK, (1 << PIC_IRT_PCIX_INDEX));
-	mtx_unlock_spin(&xlr_pic_lock);
-}
-*/
-/*
-static void pic_pcie_ack(void *arg)
-{
-	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
-	int irq = (int) arg;
-
-	mtx_lock_spin(&xlr_pic_lock);
-	xlr_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
-	mtx_unlock_spin(&xlr_pic_lock);
-}
-
-*/
-
-int
-mips_platform_pci_setup_intr(device_t dev, device_t child,
-    struct resource *irq, int flags,
-    driver_filter_t * filt,
-    driver_intr_t * intr, void *arg,
-    void **cookiep)
-{
-	int level;
-	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
-	int error = 0;
-	int xlrirq;
-
-	error = rman_activate_resource(irq);
-	if (error)
-		return error;
-	if (rman_get_start(irq) != rman_get_end(irq)) {
-		device_printf(dev, "Interrupt allocation %lu != %lu\n",
-		    rman_get_start(irq), rman_get_end(irq));
-		return EINVAL;
-	}
-	xlrirq = rman_get_start(irq);
-	if (strcmp(device_get_name(dev), "pcib") != 0)
-		return 0;
-
-	if (xlr_board_info.is_xls == 0) {
-	
-		if (rmi_spin_mutex_safe) mtx_lock_spin(&xlr_pic_lock);
-		level = PIC_IRQ_IS_EDGE_TRIGGERED(PIC_IRT_PCIX_INDEX);
-		xlr_write_reg(mmio, PIC_IRT_0_PCIX, 0x01);
-		xlr_write_reg(mmio, PIC_IRT_1_PCIX, ((1 << 31) | (level << 30) |
-		    (1 << 6) | (PIC_PCIX_IRQ)));
-		if (rmi_spin_mutex_safe) mtx_unlock_spin(&xlr_pic_lock);
-		cpu_establish_hardintr(device_get_name(child), filt,
-		    (driver_intr_t *) intr, (void *)arg, PIC_PCIX_IRQ, flags, cookiep);
-
-	} else {
-		if (rmi_spin_mutex_safe) mtx_lock_spin(&xlr_pic_lock);
-		xlr_write_reg(mmio, PIC_IRT_0_BASE + xlrirq - PIC_IRQ_BASE, 0x01);
-		xlr_write_reg(mmio, PIC_IRT_1_BASE + xlrirq - PIC_IRQ_BASE,
-		    ((1 << 31) | (1 << 30) | (1 << 6) | xlrirq));
-		if (rmi_spin_mutex_safe) mtx_unlock_spin(&xlr_pic_lock);
-
-		if (flags & INTR_FAST)
-			cpu_establish_hardintr(device_get_name(child), filt,
-			    (driver_intr_t *) intr, (void *)arg, xlrirq, flags, cookiep);
-		else
-			cpu_establish_hardintr(device_get_name(child), filt,
-			    (driver_intr_t *) intr, (void *)arg, xlrirq, flags, cookiep);
-
-
-	}
-	return bus_generic_setup_intr(dev, child, irq, flags, filt, intr,
-	    arg, cookiep);
-}
-
-
-int
-mips_platform_pci_teardown_intr(device_t dev, device_t child,
-    struct resource *irq, void *cookie);
-int
-mips_platform_pci_teardown_intr(device_t dev, device_t child,
-    struct resource *irq, void *cookie)
-{
-	if (strcmp(device_get_name(child), "pci") == 0) {
-		/* if needed reprogram the pic to clear pcix related entry */
-	}
-	return bus_generic_teardown_intr(dev, child, irq, cookie);
-}
-
-void
-pci_init_resources(void)
-{
-	irq_rman.rm_start = 0;
-	irq_rman.rm_end = 255;
-	irq_rman.rm_type = RMAN_ARRAY;
-	irq_rman.rm_descr = "PCI Mapped Interrupts";
-	if (rman_init(&irq_rman)
-	    || rman_manage_region(&irq_rman, 0, 255))
-		panic("pci_init_resources irq_rman");
-
-	port_rman.rm_start = 0;
-	port_rman.rm_end = ~0u;
-	port_rman.rm_type = RMAN_ARRAY;
-	port_rman.rm_descr = "I/O ports";
-	if (rman_init(&port_rman)
-	    || rman_manage_region(&port_rman, 0x10000000, 0x1fffffff))
-		panic("pci_init_resources port_rman");
-
-	mem_rman.rm_start = 0;
-	mem_rman.rm_end = ~0u;
-	mem_rman.rm_type = RMAN_ARRAY;
-	mem_rman.rm_descr = "I/O memory";
-	if (rman_init(&mem_rman)
-	    || rman_manage_region(&mem_rman, 0xd0000000, 0xdfffffff))
-		panic("pci_init_resources mem_rman");
-}
-
-/* hack from bus.h in mips/include/bus.h */
-#ifndef MIPS_BUS_SPACE_PCI
-#define MIPS_BUS_SPACE_PCI 10
-#endif
-
-struct resource *
-xlr_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
-    u_long start, u_long end, u_long count, u_int flags)
-{
-	struct rman *rm;
-	struct resource *rv;
-	vm_offset_t va;
-	int needactivate = flags & RF_ACTIVE;
-
-#if 0
-	device_printf(bus, "xlr_pci_alloc_resource : child %s, type %d, start %lx end %lx, count %lx, flags %x\n",
-	    device_get_nameunit(child), type, start, end, count, flags);
-#endif
-
-	switch (type) {
-	case SYS_RES_IRQ:
-		rm = &irq_rman;
-		break;
-
-	case SYS_RES_IOPORT:
-		rm = &port_rman;
-		break;
-
-	case SYS_RES_MEMORY:
-		rm = &mem_rman;
-		break;
-
-	default:
-		return 0;
-	}
-
-	rv = rman_reserve_resource(rm, start, end, count, flags, child);
-	if (rv == 0)
-		return 0;
-
-	rman_set_bustag(rv, (bus_space_tag_t) MIPS_BUS_SPACE_PCI);
-	rman_set_rid(rv, *rid);
-
-	if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
-		/*
-		 * if ((start + count) > (2 << 28)) { va_start =
-		 * kmem_alloc_nofault(kernel_map, count); }
-		 */
-		/*
-		 * This called for pmap_map_uncached, but the pmap_map calls
-		 * pmap_kenter which does a is_cacheable_mem() check and
-		 * thus sets the PTE_UNCACHED bit. Hopefully this will work
-		 * for this guy... RRS
-		 */
-		/* va = pmap_map(&va_start, start, start + count, 0); */
-		va = (vm_offset_t)pmap_mapdev(start, start + count);
-		rman_set_bushandle(rv, va);
-		/* bushandle is same as virtual addr */
-		rman_set_virtual(rv, (void *)va);
-		rman_set_bustag(rv, (bus_space_tag_t) MIPS_BUS_SPACE_PCI);
-	}
-	if (needactivate) {
-		if (bus_activate_resource(child, type, *rid, rv)) {
-			rman_release_resource(rv);
-			return (NULL);
-		}
-	}
-	return rv;
-}
-
-
-int
-pci_deactivate_resource(device_t bus, device_t child, int type, int rid,
-    struct resource *r)
-{
-	return (rman_deactivate_resource(r));
-}
-
-/* now in pci.c
-int
-pci_activate_resource(device_t bus, device_t child, int type, int rid,
-		      struct resource *r)
-{
-	return (rman_activate_resource(r));
-}
-
-int
-pci_release_resource(device_t bus, device_t child, int type, int rid,
-		       struct resource *r)
-{
-	return (rman_release_resource(r));
-}
-*/
-
-struct rman *
-pci_get_rman(device_t dev, int type)
-{
-	switch (type) {
-		case SYS_RES_IOPORT:
-		return &port_rman;
-
-	case SYS_RES_MEMORY:
-		return &mem_rman;
-
-	case SYS_RES_IRQ:
-		return &irq_rman;
-	}
-
-	return 0;
-}
diff --git a/sys/mips/rmi/perfmon.h b/sys/mips/rmi/perfmon.h
deleted file mode 100644
index 555b181..0000000
--- a/sys/mips/rmi/perfmon.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/*-
- * Copyright (c) 2003-2009 RMI Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of RMI Corporation, nor the names of its contributors,
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * RMI_BSD */
-
-#ifndef PERFMON_H
-#define PERFMON_H
-
-#include <mips/rmi/perfmon_xlrconfig.h>
-
-/*
- * category events reported by the perfmon library
- */
-enum event_category_t {
-	PERF_CP0_COUNTER = 1, PERF_CP2_CREDITS, PERF_L2_COUNTER,
-	PERF_SBC_COUNTER, PERF_SBC_CREDITS, PERF_GMAC0_COUNTER, PERF_GMAC1_COUNTER,
-	PERF_GMAC2_COUNTER, PERF_GMAC_STAT_COM, PERF_GMAC_STAT_TX,
-PERF_GMAC_STAT_RX, PERF_DRAM_COUNTER, PERF_PARAMETER_CONF = 127};
-
-
-enum perf_param_t {
-	PERF_CPU_SAMPLING_INTERVAL, PERF_SYS_SAMPLING_INTERVAL, PERF_CC_SAMPLE_RATE, PERF_CP0_FLAGS
-};
-
-#define CPO_EVENTS_TEMPLATE  0x06	/* enable kernel and user events */
-
-#define PERFMON_ACTIVE_MAGIC 0xc001
-#define PERFMON_ENABLED_MAGIC 0xb007
-#define PERFMON_INITIAL_GENERATION 0x0101
-
-#define PERFMON_SERVER_PORT 7007
-
-enum system_bridge_credits_t {
-	PCIX_CREDITS, HT_CREDITS, GIO_CREDITS, OTHER_CREDITS
-};
-
-struct perf_config_data {
-	uint16_t magic;		/* monitor start when this is initialized */
-	uint16_t generation;	/* incremented when the config changes */
-	uint16_t flags;
-	uint16_t cc_sample_rate;/* rate at which credit counters are sampled
-				 * relative to sampling_rate */
-	uint32_t sampling_rate;	/* rate at which events are sampled */
-	uint32_t cc_register_mask;	/* credit counters registers to be
-					 * sampled */
-	uint64_t events[NTHREADS];	/* events bitmap for each thread */
-};
-
-struct perf_sample {
-	uint32_t counter;
-	uint32_t timestamp;
-	uint32_t sample_tag;
-	uint32_t duration;
-};
-
-struct sample_q {
-	int32_t head, tail;
-	struct perf_sample samples[PERF_SAMPLE_BUFSZ];
-	uint32_t overflows;
-};
-
-struct perf_area {
-	struct perf_config_data perf_config;
-	struct sample_q sample_fifo;
-};
-
-/*
- * We have a shared location to keep a global tick counter for all the
- * CPUS  - TODO is this optimal? effect on cache?
- */
-extern uint32_t *xlr_perfmon_timer_loc;
-
-#define PERFMON_TIMESTAMP_LOC (xlr_perfmon_timer_loc)
-
-static __inline__ uint32_t 
-perfmon_timestamp_get(void)
-{
-	return *PERFMON_TIMESTAMP_LOC;
-}
-
-static __inline__ void 
-perfmon_timestamp_set(uint32_t val)
-{
-	*PERFMON_TIMESTAMP_LOC = val;
-}
-
-static __inline__ void 
-perfmon_timestamp_incr(int val)
-{
-	(*PERFMON_TIMESTAMP_LOC) += val;
-}
-
-static __inline__ void 
-send_sample_gts(uint32_t tag, uint32_t value, uint32_t td)
-{
-	xlr_send_sample(tag, value, perfmon_timestamp_get(), td);
-}
-
-/*
- * Simple FIFO, one producer - one consumer - circlar queue - no locking
- */
-
-static __inline__ void 
-init_fifo(struct sample_q *q)
-{
-	q->head = q->tail = 0;
-}
-
-static __inline__ void 
-put_sample(struct sample_q *q, uint32_t sample_tag, uint32_t counter,
-    uint32_t duration)
-{
-	uint32_t timestamp = perfmon_timestamp_get();
-	int new_tail = (q->tail + 1) % PERF_SAMPLE_BUFSZ;
-
-	if (q->head == new_tail) {
-		q->overflows++;
-		return;
-	}
-	q->samples[new_tail].sample_tag = sample_tag;
-	q->samples[new_tail].counter = counter;
-	q->samples[new_tail].timestamp = timestamp;
-	q->samples[new_tail].duration = duration;
-
-	q->tail = new_tail;
-}
-
-static __inline__ int 
-get_sample(struct sample_q *q, uint32_t * sample_tag, uint32_t * counter,
-    uint32_t * timestamp, uint32_t * duration)
-{
-	int head = q->head;
-
-	if (head == q->tail)
-		return 0;
-	*sample_tag = q->samples[head].sample_tag;
-	*counter = q->samples[head].counter;
-	*timestamp = q->samples[head].timestamp;
-	*duration = q->samples[head].duration;
-
-	q->head = (head + 1) % PERF_SAMPLE_BUFSZ;
-	return 1;
-}
-
-static __inline__ void 
-clear_queue(struct sample_q *q)
-{
-	q->head = q->tail;
-}
-void xlr_perfmon_init_cpu(void *);
-void xlr_perfmon_sampler(void *);
-void log_active_core(int core);
-int get_start_generation(void);
-
-void xlr_perfmon_clockhandler(void);
-extern int xlr_perfmon_started;
-
-#endif				/* PERFMON_H */
diff --git a/sys/mips/rmi/perfmon_kern.c b/sys/mips/rmi/perfmon_kern.c
deleted file mode 100644
index 363bbb2..0000000
--- a/sys/mips/rmi/perfmon_kern.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/*-
- * Copyright (c) 2003-2009 RMI Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of RMI Corporation, nor the names of its contributors,
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * RMI_BSD */
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/malloc.h>
-#include <sys/pcpu.h>
-#include <sys/proc.h>
-#include <sys/smp.h>
-#include <sys/sysctl.h>
-#include <machine/smp.h>
-#include <mips/rmi/perfmon.h>
-#include <mips/rmi/pic.h>
-#include <sys/mutex.h>
-#include <mips/rmi/clock.h>
-
-
-int xlr_perfmon_started = 0;
-struct perf_area *xlr_shared_config_area = NULL;
-uint32_t *xlr_perfmon_timer_loc;
-uint32_t *xlr_cpu_sampling_interval;
-uint32_t xlr_perfmon_kernel_version = 1;	/* Future use */
-uint32_t xlr_perfmon_ticks;
-extern int mips_cpu_online_mask;
-extern uint32_t cpu_ltop_map[MAXCPU];
-
-#ifdef SMP
-static __inline__ void 
-pic_send_perfmon_ipi(int cpu)
-{
-	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
-	int tid, pid;
-	uint32_t ipi;
-
-	tid = cpu & 0x3;
-	pid = (cpu >> 2) & 0x7;
-	ipi = (pid << 20) | (tid << 16) | IPI_PERFMON;
-
-	mtx_lock_spin(&xlr_pic_lock);
-	xlr_write_reg(mmio, PIC_IPI, ipi);
-	mtx_unlock_spin(&xlr_pic_lock);
-}
-
-#endif
-
-
-void
-xlr_perfmon_clockhandler(void)
-{
-#ifdef SMP
-	int cpu;
-	int i;
-
-#endif
-
-	if (xlr_perfmon_ticks++ >= (*xlr_cpu_sampling_interval) / (XLR_PIC_HZ / (hz * 1024))) {
-
-		/* update timer */
-		*xlr_perfmon_timer_loc += *xlr_cpu_sampling_interval;
-		xlr_perfmon_ticks = 0;
-		xlr_perfmon_sampler(NULL);
-#ifdef SMP
-		for (i = 0; i < NCPUS; i = i + NTHREADS) {	/* oly thread 0 */
-			cpu = cpu_ltop_map[i];
-			if ((mips_cpu_online_mask & (1 << i)) &&
-			    xlr_shared_config_area[cpu / NTHREADS].perf_config.magic ==
-			    PERFMON_ACTIVE_MAGIC)
-				pic_send_perfmon_ipi(cpu);
-		}
-
-#endif
-
-	}
-}
-
-static void
-xlr_perfmon_start(void)
-{
-	size_t size;
-
-	size = (NCORES * sizeof(*xlr_shared_config_area)) +
-	    sizeof(*xlr_perfmon_timer_loc) +
-	    sizeof(*xlr_cpu_sampling_interval);
-
-	xlr_shared_config_area = malloc(size, M_TEMP, M_WAITOK);
-	if (!xlr_shared_config_area) {
-		/* ERROR */
-		return;
-	}
-	xlr_perfmon_timer_loc = (uint32_t *) (xlr_shared_config_area + NCORES);
-	xlr_cpu_sampling_interval = (uint32_t *) (xlr_perfmon_timer_loc + 1);
-
-	*xlr_cpu_sampling_interval = DEFAULT_CPU_SAMPLING_INTERVAL;
-	*xlr_perfmon_timer_loc = 0;
-	xlr_perfmon_ticks = 0;
-
-	xlr_perfmon_init_cpu(NULL);
-#ifdef SMP
-	smp_call_function(xlr_perfmon_init_cpu, NULL,
-	    PCPU_GET(other_cpus) & 0x11111111);
-#endif
-	xlr_perfmon_started = 1;
-
-}
-
-static void
-xlr_perfmon_stop(void)
-{
-	xlr_perfmon_started = 0;
-	free(xlr_shared_config_area, M_TEMP);
-	xlr_shared_config_area = NULL;
-}
-
-static int
-sysctl_xlr_perfmon_start_stop(SYSCTL_HANDLER_ARGS)
-{
-	int error, val = xlr_perfmon_started;
-
-	error = sysctl_handle_int(oidp, &val, 0, req);
-	if (error != 0 || req->newptr == NULL)
-		return (error);
-
-	if (!xlr_perfmon_started && val != 0)
-		xlr_perfmon_start();
-	else if (xlr_perfmon_started && val == 0)
-		xlr_perfmon_stop();
-
-	return (0);
-}
-
-
-SYSCTL_NODE(_debug, OID_AUTO, xlrperf, CTLFLAG_RW, NULL, "XLR PERF Nodes");
-SYSCTL_PROC(_debug_xlrperf, OID_AUTO, start, CTLTYPE_INT | CTLFLAG_RW,
-    &xlr_perfmon_started, 0, sysctl_xlr_perfmon_start_stop, "I", "set/unset to start/stop "
-    "performance monitoring");
diff --git a/sys/mips/rmi/perfmon_percpu.c b/sys/mips/rmi/perfmon_percpu.c
deleted file mode 100644
index fc0f062..0000000
--- a/sys/mips/rmi/perfmon_percpu.c
+++ /dev/null
@@ -1,342 +0,0 @@
-/*-
- * Copyright (c) 2003-2009 RMI Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of RMI Corporation, nor the names of its contributors,
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * RMI_BSD */
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/kernel.h>
-#include <sys/smp.h>
-#include <sys/pcpu.h>
-#include <mips/rmi/xlrconfig.h>
-#include <mips/rmi/perfmon_xlrconfig.h>
-#include <mips/rmi/perfmon.h>
-#include <mips/rmi/perfmon_utils.h>
-#include <mips/rmi/pic.h>
-#include <mips/rmi/msgring.h>
-
-#define CC_SAMPLE   (PERF_CP2_CREDITS <<24)
-
-#define CC_REG0 16
-#define CC_REG1 17
-#define CC_REG2 18
-#define CC_REG3 19
-#define CC_REG4 20
-#define CC_REG5 21
-#define CC_REG6 22
-#define CC_REG7 23
-#define CC_REG8 24
-#define CC_REG9 25
-#define CC_REG10 26
-#define CC_REG11 27
-#define CC_REG12 28
-#define CC_REG13 29
-#define CC_REG14 30
-#define CC_REG15 31
-
-extern uint32_t cpu_ltop_map[MAXCPU];
-extern struct perf_area *xlr_shared_config_area;
-
-static __inline__ uint32_t 
-make_cpu_tag(uint32_t val)
-{
-	return PERF_CP0_COUNTER << 24 | (val & 0xffff);
-}
-
-static __inline__ uint32_t 
-make_cp0_perf_control(uint32_t flags, uint32_t thread, uint32_t event)
-{
-	return (flags & 0x1f) | (thread & 0x03) << 11 | (event & 0x3f) << 5 | 0x01;
-}
-
-static __inline__ uint32_t 
-cp0_perf_control_get_thread(uint32_t control_word)
-{
-	return (control_word & 0x1800) >> 11;
-}
-
-static __inline__ uint32_t 
-cp0_perf_control_get_event(uint32_t control_word)
-{
-	return (control_word & 0x7e0) >> 5;
-}
-
-static __inline__ uint32_t 
-read_pic_6_timer_count(void)
-{
-	xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
-
-	/* PIC counts down, convert it to count up */
-	return 0xffffffffU - xlr_read_reg(mmio, PIC_TIMER_6_COUNTER_0);
-}
-
-
-static uint32_t 
-get_num_events(const uint64_t * events)
-{
-	int total = 0;
-	int thread;
-
-	for (thread = 0; thread < NTHREADS; thread++) {
-		if (events[thread] == 0)
-			continue;
-		total += get_set_bit_count64(events[thread]);
-	}
-	return total;
-}
-
-static uint32_t 
-get_first_control_word(uint32_t flags, const uint64_t * events)
-{
-	int thread, event;
-
-	for (thread = 0; thread < NTHREADS; thread++) {
-		if (events[thread] != 0)
-			break;
-	}
-	if (thread == NTHREADS)
-		return -1;
-
-	event = find_first_set_bit64(events[thread]);
-	return make_cp0_perf_control(flags, thread, event);
-}
-
-static uint32_t 
-get_next_control_word(uint32_t current_control_word, const uint64_t * events)
-{
-	int thread = cp0_perf_control_get_thread(current_control_word);
-	int event = cp0_perf_control_get_event(current_control_word);
-	int i;
-
-	event = find_next_set_bit64(events[thread], event);
-	for (i = 0; event == -1 && i < NTHREADS; i++) {
-		thread = (thread + 1) % NTHREADS;
-		if (events[thread] == 0)
-			continue;
-		event = find_first_set_bit64(events[thread]);
-	}
-
-	ASSERT(event != -1);
-	return make_cp0_perf_control(current_control_word, thread, event);
-}
-
-/* Global state per core */
-#define MY_CORE_NUM (cpu_ltop_map[PCPU_GET(cpuid)]/NTHREADS)
-#define my_perf_area (&(xlr_shared_config_area[MY_CORE_NUM]))
-
-static int num_events_array[NCORES];
-static uint32_t saved_timestamp_array[NCORES];
-static struct perf_config_data saved_config_array[NCORES];
-static int cc_sample_array[NCORES];
-
-#define num_events (num_events_array[MY_CORE_NUM])
-#define	saved_timestamp (saved_timestamp_array[MY_CORE_NUM])
-#define saved_config (saved_config_array[MY_CORE_NUM])
-#define cc_sample (cc_sample_array[MY_CORE_NUM])
-
-static void 
-do_sample_cc_registers(struct sample_q *q, uint32_t mask)
-{
-	unsigned long flags;
-
-	DPRINT("Sample CC registers %x", mask);
-	msgrng_flags_save(flags);
-	if (mask & 0x00000001)
-		put_sample(q, CC_SAMPLE + 0, read_cc_registers_0123(CC_REG0), 0);
-	if (mask & 0x00000002)
-		put_sample(q, CC_SAMPLE + 1, read_cc_registers_4567(CC_REG0), 0);
-	if (mask & 0x00000004)
-		put_sample(q, CC_SAMPLE + 2, read_cc_registers_0123(CC_REG1), 0);
-	if (mask & 0x00000008)
-		put_sample(q, CC_SAMPLE + 3, read_cc_registers_4567(CC_REG1), 0);
-	if (mask & 0x00000010)
-		put_sample(q, CC_SAMPLE + 4, read_cc_registers_0123(CC_REG2), 0);
-	if (mask & 0x00000020)
-		put_sample(q, CC_SAMPLE + 5, read_cc_registers_4567(CC_REG2), 0);
-	if (mask & 0x00000040)
-		put_sample(q, CC_SAMPLE + 6, read_cc_registers_0123(CC_REG3), 0);
-	if (mask & 0x00000080)
-		put_sample(q, CC_SAMPLE + 7, read_cc_registers_4567(CC_REG3), 0);
-	if (mask & 0x00000100)
-		put_sample(q, CC_SAMPLE + 8, read_cc_registers_0123(CC_REG4), 0);
-	if (mask & 0x00000200)
-		put_sample(q, CC_SAMPLE + 9, read_cc_registers_4567(CC_REG4), 0);
-	if (mask & 0x00000400)
-		put_sample(q, CC_SAMPLE + 10, read_cc_registers_0123(CC_REG5), 0);
-	if (mask & 0x00000800)
-		put_sample(q, CC_SAMPLE + 11, read_cc_registers_4567(CC_REG5), 0);
-	if (mask & 0x00001000)
-		put_sample(q, CC_SAMPLE + 12, read_cc_registers_0123(CC_REG6), 0);
-	if (mask & 0x00002000)
-		put_sample(q, CC_SAMPLE + 13, read_cc_registers_4567(CC_REG6), 0);
-	if (mask & 0x00004000)
-		put_sample(q, CC_SAMPLE + 14, read_cc_registers_0123(CC_REG7), 0);
-	if (mask & 0x00008000)
-		put_sample(q, CC_SAMPLE + 15, read_cc_registers_4567(CC_REG7), 0);
-	if (mask & 0x00010000)
-		put_sample(q, CC_SAMPLE + 16, read_cc_registers_0123(CC_REG8), 0);
-	if (mask & 0x00020000)
-		put_sample(q, CC_SAMPLE + 17, read_cc_registers_4567(CC_REG8), 0);
-	if (mask & 0x00040000)
-		put_sample(q, CC_SAMPLE + 18, read_cc_registers_0123(CC_REG9), 0);
-	if (mask & 0x00080000)
-		put_sample(q, CC_SAMPLE + 19, read_cc_registers_4567(CC_REG9), 0);
-	if (mask & 0x00100000)
-		put_sample(q, CC_SAMPLE + 20, read_cc_registers_0123(CC_REG10), 0);
-	if (mask & 0x00200000)
-		put_sample(q, CC_SAMPLE + 21, read_cc_registers_4567(CC_REG10), 0);
-	if (mask & 0x00400000)
-		put_sample(q, CC_SAMPLE + 22, read_cc_registers_0123(CC_REG11), 0);
-	if (mask & 0x00800000)
-		put_sample(q, CC_SAMPLE + 23, read_cc_registers_4567(CC_REG11), 0);
-	if (mask & 0x01000000)
-		put_sample(q, CC_SAMPLE + 24, read_cc_registers_0123(CC_REG12), 0);
-	if (mask & 0x02000000)
-		put_sample(q, CC_SAMPLE + 24, read_cc_registers_4567(CC_REG12), 0);
-	if (mask & 0x04000000)
-		put_sample(q, CC_SAMPLE + 26, read_cc_registers_0123(CC_REG13), 0);
-	if (mask & 0x08000000)
-		put_sample(q, CC_SAMPLE + 27, read_cc_registers_4567(CC_REG13), 0);
-	if (mask & 0x10000000)
-		put_sample(q, CC_SAMPLE + 28, read_cc_registers_0123(CC_REG14), 0);
-	if (mask & 0x20000000)
-		put_sample(q, CC_SAMPLE + 29, read_cc_registers_4567(CC_REG14), 0);
-	if (mask & 0x40000000)
-		put_sample(q, CC_SAMPLE + 30, read_cc_registers_0123(CC_REG15), 0);
-	if (mask & 0x80000000)
-		put_sample(q, CC_SAMPLE + 31, read_cc_registers_4567(CC_REG15), 0);
-	msgrng_flags_restore(flags);
-}
-
-static void 
-reconfigure(void)
-{
-	uint32_t cntr_cntrl;
-
-	saved_config = my_perf_area->perf_config;
-	num_events = get_num_events(saved_config.events);
-	cc_sample = saved_config.cc_sample_rate;
-
-	DPRINT("%d - reconfigure num_events = %d, events = %llx,%llx,%llx,%llx\n",
-	    processor_id(), num_events, saved_config.events[0],
-	    saved_config.events[1], saved_config.events[2], saved_config.events[3]);
-
-	if (num_events == 0)
-		return;
-
-	cntr_cntrl = get_first_control_word(saved_config.flags, saved_config.events);
-	write_c0_register(CP0_PERF_COUNTER, PERFCNTRCTL0, cntr_cntrl);
-	write_c0_register(CP0_PERF_COUNTER, PERFCNTR0, 0);	/* reset count */
-	if (num_events > 1) {
-		cntr_cntrl = get_next_control_word(cntr_cntrl, saved_config.events);
-		write_c0_register(CP0_PERF_COUNTER, PERFCNTRCTL1, cntr_cntrl);
-		write_c0_register(CP0_PERF_COUNTER, PERFCNTR1, 0);	/* reset count */
-	}
-	saved_timestamp = read_pic_6_timer_count();
-}
-
-int xlr_perfmon_no_event_count = 0;
-int xlr_perfmon_sample_count;
-
-/* timer callback routine */
-void 
-xlr_perfmon_sampler(void *dummy)
-{
-	uint32_t current_ts;
-	uint32_t cntr_cntrl = 0;
-
-	/* xlr_ack_interrupt(XLR_PERFMON_IPI_VECTOR); */
-
-	if (my_perf_area->perf_config.magic != PERFMON_ACTIVE_MAGIC)
-		return;
-	/*
-	 * If there has been a change in configuation, update the
-	 * configuration
-	 */
-	if (saved_config.generation != my_perf_area->perf_config.generation) {
-		reconfigure();
-		return;
-	}
-	/* credit counter samples if reqd */
-	if (saved_config.cc_register_mask && --cc_sample == 0) {
-		cc_sample = saved_config.cc_sample_rate;
-		do_sample_cc_registers(&my_perf_area->sample_fifo,
-		    my_perf_area->perf_config.cc_register_mask);
-	}
-	if (num_events == 0) {
-		xlr_perfmon_no_event_count++;
-		return;
-	}
-	/* put samples in the queue */
-	current_ts = read_pic_6_timer_count();
-	cntr_cntrl = read_c0_register(CP0_PERF_COUNTER, PERFCNTRCTL0);
-	put_sample(&my_perf_area->sample_fifo, make_cpu_tag(cntr_cntrl),
-	    read_c0_register(CP0_PERF_COUNTER, PERFCNTR0), current_ts - saved_timestamp);
-	xlr_perfmon_sample_count++;
-	write_c0_register(CP0_PERF_COUNTER, PERFCNTR0, 0);	/* reset count */
-
-	if (num_events > 1) {
-		cntr_cntrl = read_c0_register(CP0_PERF_COUNTER, PERFCNTRCTL1);
-		put_sample(&my_perf_area->sample_fifo, make_cpu_tag(cntr_cntrl),
-		    read_c0_register(CP0_PERF_COUNTER, PERFCNTR1), current_ts - saved_timestamp);
-		xlr_perfmon_sample_count++;
-		write_c0_register(CP0_PERF_COUNTER, PERFCNTR1, 0);	/* reset count */
-
-		if (num_events > 2) {
-			/* multiplex events */
-			cntr_cntrl = get_next_control_word(cntr_cntrl, saved_config.events);
-			write_c0_register(CP0_PERF_COUNTER, PERFCNTRCTL0, cntr_cntrl);
-
-			cntr_cntrl = get_next_control_word(cntr_cntrl, saved_config.events);
-			write_c0_register(CP0_PERF_COUNTER, PERFCNTRCTL1, cntr_cntrl);
-		}
-	}
-	saved_timestamp = read_pic_6_timer_count();
-}
-
-/*
- * Initializes time to gather CPU performance counters and credit counters
- */
-void 
-xlr_perfmon_init_cpu(void *dummy)
-{
-	int processor = cpu_ltop_map[PCPU_GET(cpuid)];
-
-	/* run on just one thread per core */
-	if (processor % 4)
-		return;
-
-	DPRINT("%d : configure with %p", processor, my_perf_area);
-	memset(my_perf_area, 0, sizeof(*my_perf_area));
-	init_fifo(&my_perf_area->sample_fifo);
-	my_perf_area->perf_config.magic = PERFMON_ENABLED_MAGIC;
-	my_perf_area->perf_config.generation = PERFMON_INITIAL_GENERATION;
-	DPRINT("%d : Initialize", processor);
-
-	return;
-}
diff --git a/sys/mips/rmi/perfmon_utils.h b/sys/mips/rmi/perfmon_utils.h
deleted file mode 100644
index bafcb54..0000000
--- a/sys/mips/rmi/perfmon_utils.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*-
- * Copyright (c) 2003-2009 RMI Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of RMI Corporation, nor the names of its contributors,
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * RMI_BSD */
-
-#ifndef UTILS_H
-#define UTILS_H
-
-#include <machine/stdarg.h>	/* variable args */
-
-/* TODO optimize of mips, even i & (i-1) is better */
-
-static int __inline__ 
-get_set_bit_count64(uint64_t value)
-{
-	int i, result = 0;
-
-	for (i = 0; i < sizeof(value) * 8; i++)
-		if (value & (1ULL << i))
-			result++;
-
-	return result;
-}
-
-static int __inline__ 
-find_first_set_bit64(uint64_t value)
-{
-	int i;
-
-	for (i = 0; i < sizeof(value) * 8; i++)
-		if (value & (1ULL << i))
-			return i;
-
-	return -1;
-}
-
-static int __inline__ 
-find_next_set_bit64(uint64_t value, int pos)
-{
-	int i;
-
-	for (i = pos + 1; i < sizeof(value) * 8; i++)
-		if (value & (1ULL << i))
-			return i;
-
-	return -1;
-}
-
-/** ---  **/
-
-static int __inline__ 
-get_set_bit_count(uint32_t value)
-{
-	int i, result = 0;
-
-	for (i = 0; i < sizeof(value) * 8; i++)
-		if (value & (1U << i))
-			result++;
-
-	return result;
-}
-
-static int __inline__ 
-find_first_set_bit(uint32_t value)
-{
-	int i;
-
-	for (i = 0; i < sizeof(value) * 8; i++)
-		if (value & (1U << i))
-			return i;
-
-	return -1;
-}
-
-static int __inline__ 
-find_next_set_bit(uint32_t value, int pos)
-{
-	int i;
-
-	for (i = pos + 1; i < sizeof(value) * 8; i++)
-		if (value & (1U << i))
-			return i;
-
-	return -1;
-}
-
-#ifdef DEBUG
-void abort();
-
-#define DPUTC(c)         (putchar(c) && fflush(stdout))
-#define DPRINT(fmt, ...) printf(fmt "\n", __VA_ARGS__)
-#define ASSERT(x)   ((x) || ({ printf("%s failed at (%s:%d)", #x, __FILE__, __LINE__) ; abort(); 0; }) )
-#else
-#define DPUTC(c)
-#define DPRINT(fmt, ...)
-#define ASSERT(x)
-#endif
-
-void xlr_send_sample(uint32_t tag, uint32_t value, uint32_t ts, uint32_t td);
-
-#endif
diff --git a/sys/mips/rmi/perfmon_xlrconfig.h b/sys/mips/rmi/perfmon_xlrconfig.h
deleted file mode 100644
index e3966ae..0000000
--- a/sys/mips/rmi/perfmon_xlrconfig.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/*-
- * Copyright (c) 2003-2009 RMI Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- * 3. Neither the name of RMI Corporation, nor the names of its contributors,
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * RMI_BSD */
-
-#ifdef XLR_PERFMON
-
-#ifndef XLRCONFIG_PERFMON_H
-#define XLRCONFIG_PERFMON_H
-
-#include <mips/rmi/perfmon_utils.h>	/* for DPRINT */
-
-#define NCPUS    32
-#define NCORES   8
-#define NTHREADS 4
-#define PERF_SAMPLE_BUFSZ 32
-/*select timeout is 512*1024 microsecs */
-#define DEFAULT_SYS_SAMPLING_INTERVAL (512*1024)
-/* default timer value programmed to PIC is 10*1024*1024 */
-#define DEFAULT_CPU_SAMPLING_INTERVAL (10*1024)
-#define DEFAULT_CC_SAMPLE_RATE 16
-#define DEFAULT_CP0_FLAGS 0x0A
-#define NUM_L2_BANKS 8
-#define NUM_DRAM_BANKS 4
-
-/* CP0 register for timestamp */
-#define CP0_COUNT              9
-#define CP0_EIRR_REG           9
-#define CP0_EIRR_SEL           6
-#define CP0_EIMR_REG           9
-#define CP0_EIMR_SEL           7
-
-/* CP0 register for perf counters */
-#define CP0_PERF_COUNTER       25
-/* selector values */
-#define PERFCNTRCTL0       0
-#define PERFCNTR0          1
-#define PERFCNTRCTL1       2
-#define PERFCNTR1          3
-
-#define XLR_IO_PIC_OFFSET   0x08000
-#define PIC_SYS_TIMER_0_BASE 0x120
-#define PIC_SYS_TIMER_NUM_6 6
-
-/* CP2 registers for reading credit counters */
-#define CC_REG0  16
-
-#define read_c0_register(reg, sel)                              \
-({ unsigned int __rv;                                           \
-        __asm__ __volatile__(                                   \
-	".set\tpush\n\t"					\
-        ".set mips32\n\t"                                       \
-        "mfc0\t%0,$%1,%2\n\t"                                   \
-	".set\tpop"						\
-        : "=r" (__rv) : "i" (reg), "i" (sel) );                 \
-        __rv;})
-
-#define write_c0_register(reg,  sel, value)                     \
-        __asm__ __volatile__(                                   \
-	".set\tpush\n\t"					\
-        ".set mips32\n\t"                                       \
-        "mtc0\t%0,$%1,%2\n\t"                                   \
-	".set\tpop"						\
-        : : "r" (value), "i" (reg), "i" (sel) );
-
-#define read_c2_register(reg, sel)                              \
-({ unsigned int __rv;                                           \
-        __asm__ __volatile__(                                   \
-	".set\tpush\n\t"					\
-        ".set mips32\n\t"                                       \
-        "mfc0\t%0,$%1,%2\n\t"                                   \
-	".set\tpop"					 	\
-        : "=r" (__rv) : "i"(reg), "i" (sel) );                  \
-        __rv;})
-
-/*
- * We have 128 registers in C2 credit counters, reading them one at
- * a time using bitmap will take a lot of code, so we have two functions
- * to read registers sel0-3 and sel 4-7 into one 32 bit word.
- */
-
-#define read_cc_registers_0123(reg)                            \
-({     	      						       \
-	unsigned int __rv;				       \
-							       \
-        __asm__ __volatile__(				       \
-		".set	push\n\t"			       \
-		".set	mips32\n\t"			       \
-		".set	noreorder\n\t"			       \
-		"mfc2	%0, $%1, 0\n\t"	                       \
-		"mfc2	$8, $%1, 1\n\t"	                       \
-		"sll    %0, %0, 8\n\t"			       \
-		"or     %0, %0, $8\n\t"			       \
-		"mfc2	$8, $%1, 2\n\t"	                       \
-		"sll    %0, %0, 8\n\t"			       \
-		"or     %0, %0, $8\n\t"			       \
-		"mfc2	$8, $%1, 3\n\t"	                       \
-		"sll    %0, %0, 8\n\t"			       \
-		"or     %0, %0, $8\n\t"			       \
-		".set	pop"				       \
-		: "=r" (__rv) : "i"(reg) : "$8");	       \
-							       \
-       __rv;						       \
-})
-
-#define read_cc_registers_4567(reg)                            \
-({     	      						       \
-	unsigned int __rv;				       \
-							       \
-        __asm__ __volatile__(				       \
-		".set	push\n\t"			       \
-		".set	mips32\n\t"			       \
-		".set	noreorder\n\t"			       \
-		"mfc2	%0, $%1, 4\n\t"	                       \
-		"mfc2	$8, $%1, 5\n\t"	                       \
-		"sll    %0, %0, 8\n\t"			       \
-		"or     %0, %0, $8\n\t"			       \
-		"mfc2	$8, $%1, 6\n\t"	                       \
-		"sll    %0, %0, 8\n\t"			       \
-		"or     %0, %0, $8\n\t"			       \
-		"mfc2	$8, $%1, 7\n\t"	                       \
-		"sll    %0, %0, 8\n\t"			       \
-		"or     %0, %0, $8\n\t"			       \
-		".set	pop"				       \
-		: "=r" (__rv) :"i"(reg) : "$8");	       \
-							       \
-       __rv;						       \
-})
-
-#endif
-#endif
diff --git a/sys/mips/rmi/xlr_boot1_console.c b/sys/mips/rmi/xlr_boot1_console.c
deleted file mode 100644
index 88cefcf..0000000
--- a/sys/mips/rmi/xlr_boot1_console.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*-
- * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in the
- *    documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
- * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
- * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
- * SUCH DAMAGE.
- *
- * $Id: xlr_boot1_console.c,v 1.6 2008-07-16 20:22:49 jayachandranc Exp $
- */
-/*
- *  Adapted for XLR bootloader
- *  RMi
- */
-
-#include <sys/cdefs.h>
-__FBSDID("$FreeBSD$");
-
-#include "opt_comconsole.h"
-
-#include <sys/param.h>
-#include <sys/kdb.h>
-#include <sys/kernel.h>
-#include <sys/systm.h>
-#include <sys/types.h>
-#include <sys/conf.h>
-#include <sys/cons.h>
-#include <sys/consio.h>
-#include <sys/tty.h>
-
-#include <mips/rmi/xlrconfig.h>
-#include <mips/rmi/shared_structs.h>
-#include <mips/rmi/shared_structs_func.h>
-
-#include <ddb/ddb.h>
-
-#if 0
-static cn_probe_t xlr_boot1_cnprobe;
-static cn_init_t xlr_boot1_cninit;
-static cn_term_t xlr_boot1_cnterm;
-static cn_getc_t xlr_boot1_cngetc;
-static cn_checkc_t xlr_boot1_cncheckc;
-static cn_putc_t xlr_boot1_cnputc;
-
-CONS_DRIVER(xlrboot, xlr_boot1_cnprobe, xlr_boot1_cninit, xlr_boot1_cnterm, xlr_boot1_cngetc,
-    xlr_boot1_cncheckc, xlr_boot1_cnputc, NULL);
-
-/*
- * Device gets probed. Firmwire should be checked here probably.
- */
-static void
-xlr_boot1_cnprobe(struct consdev *cp)
-{
-	cp->cn_pri = CN_NORMAL;
-	cp->cn_tp = NULL;
-	cp->cn_arg = NULL;	/* softc */
-	cp->cn_unit = -1;	/* ? */
-	cp->cn_flags = 0;
-}
-
-/*
- * Initialization.
- */
-static void
-xlr_boot1_cninit(struct consdev *cp)
-{
-	sprintf(cp->cn_name, "boot1");
-}
-
-static void
-xlr_boot1_cnterm(struct consdev *cp)
-{
-	cp->cn_pri = CN_DEAD;
-	cp->cn_flags = 0;
-	return;
-}
-
-static int
-xlr_boot1_cngetc(struct consdev *cp)
-{
-	return boot1_info_uart_getchar_func(&xlr_boot1_info);
-}
-
-static void
-xlr_boot1_cnputc(struct consdev *cp, int c)
-{
-	boot1_info_uart_putchar_func(&xlr_boot1_info, c);
-}
-
-static int
-xlr_boot1_cncheckc(struct consdev *cp)
-{
-	return 0;
-}
-
-#endif